1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c
);
150 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
152 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS
*);
157 static int i386_intel_parse_name (const char *, expressionS
*);
158 static const reg_entry
*parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template
*match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry
*build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS
*, offsetT
);
177 static void output_disp (fragS
*, offsetT
);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static const char *default_arch
= DEFAULT_ARCH
;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes
[3];
193 /* Destination or source register specifier. */
194 const reg_entry
*register_specifier
;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry
*regs
;
209 /* TM holds the template for the insn were currently assembling. */
212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
216 /* OPERANDS gives the number of given operands. */
217 unsigned int operands
;
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
222 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
224 /* TYPES [i] is the type (see above #defines) which tells us how to
225 use OP[i] for the corresponding operand. */
226 i386_operand_type types
[MAX_OPERANDS
];
228 /* Displacement expression, immediate expression, or register for each
230 union i386_op op
[MAX_OPERANDS
];
232 /* Flags for operands. */
233 unsigned int flags
[MAX_OPERANDS
];
234 #define Operand_PCrel 1
236 /* Relocation type for operand */
237 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry
*base_reg
;
242 const reg_entry
*index_reg
;
243 unsigned int log2_scale_factor
;
245 /* SEG gives the seg_entries of this insn. They are zero unless
246 explicit segment overrides are given. */
247 const seg_entry
*seg
[2];
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes
;
252 unsigned char prefix
[MAX_PREFIXES
];
254 /* RM and SIB are the modrm byte and the sib byte where the
255 addressing modes of this insn are encoded. */
261 /* Swap operand in encoding. */
262 unsigned int swap_operand
;
265 typedef struct _i386_insn i386_insn
;
267 /* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
269 const char extra_symbol_chars
[] = "*%-(["
278 #if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
280 && !defined (TE_GNU) \
281 && !defined (TE_LINUX) \
282 && !defined (TE_NETWARE) \
283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
285 /* This array holds the chars that always start a comment. If the
286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288 const char *i386_comment_chars
= "#/";
289 #define SVR4_COMMENT_CHARS 1
290 #define PREFIX_SEPARATOR '\\'
293 const char *i386_comment_chars
= "#";
294 #define PREFIX_SEPARATOR '/'
297 /* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
301 first line of the input file. This is because the compiler outputs
302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
304 '/' isn't otherwise defined. */
305 const char line_comment_chars
[] = "#/";
307 const char line_separator_chars
[] = ";";
309 /* Chars that can be used to separate mant from exp in floating point
311 const char EXP_CHARS
[] = "eE";
313 /* Chars that mean this number is a floating point constant
316 const char FLT_CHARS
[] = "fFdDxX";
318 /* Tables for lexical analysis. */
319 static char mnemonic_chars
[256];
320 static char register_chars
[256];
321 static char operand_chars
[256];
322 static char identifier_chars
[256];
323 static char digit_chars
[256];
325 /* Lexical macros. */
326 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327 #define is_operand_char(x) (operand_chars[(unsigned char) x])
328 #define is_register_char(x) (register_chars[(unsigned char) x])
329 #define is_space_char(x) ((x) == ' ')
330 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331 #define is_digit_char(x) (digit_chars[(unsigned char) x])
333 /* All non-digit non-letter characters that may occur in an operand. */
334 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
336 /* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
339 assembler instruction). */
340 static char save_stack
[32];
341 static char *save_stack_p
;
342 #define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344 #define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
347 /* The instruction we're assembling. */
350 /* Possible templates for current insn. */
351 static const templates
*current_templates
;
353 /* Per instruction expressionS buffers: max displacements & immediates. */
354 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
355 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
357 /* Current operand we are working on. */
358 static int this_operand
= -1;
360 /* We support four different modes. FLAG_CODE variable is used to distinguish
368 static enum flag_code flag_code
;
369 static unsigned int object_64bit
;
370 static int use_rela_relocations
= 0;
372 /* The names used to print error messages. */
373 static const char *flag_code_names
[] =
380 /* 1 for intel syntax,
382 static int intel_syntax
= 0;
384 /* 1 for intel mnemonic,
385 0 if att mnemonic. */
386 static int intel_mnemonic
= !SYSV386_COMPAT
;
388 /* 1 if support old (<= 2.8.1) versions of gcc. */
389 static int old_gcc
= OLDGCC_COMPAT
;
391 /* 1 if pseudo registers are permitted. */
392 static int allow_pseudo_reg
= 0;
394 /* 1 if register prefix % not required. */
395 static int allow_naked_reg
= 0;
397 /* 1 if pseudo index register, eiz/riz, is allowed . */
398 static int allow_index_reg
= 0;
408 /* Register prefix used for error message. */
409 static const char *register_prefix
= "%";
411 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414 static char stackop_size
= '\0';
416 /* Non-zero to optimize code alignment. */
417 int optimize_align_code
= 1;
419 /* Non-zero to quieten some warnings. */
420 static int quiet_warnings
= 0;
423 static const char *cpu_arch_name
= NULL
;
424 static char *cpu_sub_arch_name
= NULL
;
426 /* CPU feature flags. */
427 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
429 /* If we have selected a cpu we are generating instructions for. */
430 static int cpu_arch_tune_set
= 0;
432 /* Cpu we are generating instructions for. */
433 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
435 /* CPU feature flags of cpu we are generating instructions for. */
436 static i386_cpu_flags cpu_arch_tune_flags
;
438 /* CPU instruction set architecture used. */
439 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
441 /* CPU feature flags of instruction set architecture used. */
442 i386_cpu_flags cpu_arch_isa_flags
;
444 /* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446 static unsigned int no_cond_jump_promotion
= 0;
448 /* Encode SSE instructions with VEX prefix. */
449 static unsigned int sse2avx
;
451 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
452 static symbolS
*GOT_symbol
;
454 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
455 unsigned int x86_dwarf2_return_column
;
457 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458 int x86_cie_data_alignment
;
460 /* Interface to relax_segment.
461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
466 #define UNCOND_JUMP 0
468 #define COND_JUMP86 2
473 #define SMALL16 (SMALL | CODE16)
475 #define BIG16 (BIG | CODE16)
479 #define INLINE __inline__
485 #define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487 #define TYPE_FROM_RELAX_STATE(s) \
489 #define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
492 /* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
500 const relax_typeS md_relax_table
[] =
503 1) most positive reach of this state,
504 2) most negative reach of this state,
505 3) how many bytes this mode will have in the variable part of the frag
506 4) which index into the table to try if we can't fit into this one. */
508 /* UNCOND_JUMP states. */
509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
524 /* word conditionals add 3 bytes to frag:
525 1 extra opcode byte, 2 displacement bytes. */
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
539 static const arch_entry cpu_arch
[] =
541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
542 CPU_GENERIC32_FLAGS
, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
544 CPU_GENERIC64_FLAGS
, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
572 CPU_NOCONA_FLAGS
, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
578 CPU_CORE2_FLAGS
, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
580 CPU_CORE2_FLAGS
, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
582 CPU_COREI7_FLAGS
, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
590 CPU_ATHLON_FLAGS
, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
598 CPU_AMDFAM10_FLAGS
, 0 },
599 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
601 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
603 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
605 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
606 CPU_ANY87_FLAGS
, 0 },
607 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
609 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
610 CPU_3DNOWA_FLAGS
, 0 },
611 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
613 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
615 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
617 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
618 CPU_SSSE3_FLAGS
, 0 },
619 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
620 CPU_SSE4_1_FLAGS
, 0 },
621 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
622 CPU_SSE4_2_FLAGS
, 0 },
623 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
624 CPU_SSE4_2_FLAGS
, 0 },
625 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
626 CPU_ANY_SSE_FLAGS
, 0 },
627 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
629 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
630 CPU_ANY_AVX_FLAGS
, 0 },
631 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
633 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
635 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
636 CPU_XSAVE_FLAGS
, 0 },
637 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
639 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
640 CPU_PCLMUL_FLAGS
, 0 },
641 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
642 CPU_PCLMUL_FLAGS
, 1 },
643 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
645 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
647 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
649 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
651 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
652 CPU_MOVBE_FLAGS
, 0 },
653 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
655 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
656 CPU_CLFLUSH_FLAGS
, 0 },
657 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
658 CPU_SYSCALL_FLAGS
, 0 },
659 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
660 CPU_RDTSCP_FLAGS
, 0 },
661 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
662 CPU_3DNOW_FLAGS
, 0 },
663 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
664 CPU_3DNOWA_FLAGS
, 0 },
665 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
666 CPU_PADLOCK_FLAGS
, 0 },
667 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
669 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
671 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
672 CPU_SSE4A_FLAGS
, 0 },
673 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
678 /* Like s_lcomm_internal in gas/read.c but the alignment string
679 is allowed to be optional. */
682 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
689 && *input_line_pointer
== ',')
691 align
= parse_align (needs_align
- 1);
693 if (align
== (addressT
) -1)
708 bss_alloc (symbolP
, size
, align
);
713 pe_lcomm (int needs_align
)
715 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
719 const pseudo_typeS md_pseudo_table
[] =
721 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
722 {"align", s_align_bytes
, 0},
724 {"align", s_align_ptwo
, 0},
726 {"arch", set_cpu_arch
, 0},
730 {"lcomm", pe_lcomm
, 1},
732 {"ffloat", float_cons
, 'f'},
733 {"dfloat", float_cons
, 'd'},
734 {"tfloat", float_cons
, 'x'},
736 {"slong", signed_cons
, 4},
737 {"noopt", s_ignore
, 0},
738 {"optim", s_ignore
, 0},
739 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
740 {"code16", set_code_flag
, CODE_16BIT
},
741 {"code32", set_code_flag
, CODE_32BIT
},
742 {"code64", set_code_flag
, CODE_64BIT
},
743 {"intel_syntax", set_intel_syntax
, 1},
744 {"att_syntax", set_intel_syntax
, 0},
745 {"intel_mnemonic", set_intel_mnemonic
, 1},
746 {"att_mnemonic", set_intel_mnemonic
, 0},
747 {"allow_index_reg", set_allow_index_reg
, 1},
748 {"disallow_index_reg", set_allow_index_reg
, 0},
749 {"sse_check", set_sse_check
, 0},
750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
751 {"largecomm", handle_large_common
, 0},
753 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
754 {"loc", dwarf2_directive_loc
, 0},
755 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
758 {"secrel32", pe_directive_secrel
, 0},
763 /* For interface with expression (). */
764 extern char *input_line_pointer
;
766 /* Hash table for instruction mnemonic lookup. */
767 static struct hash_control
*op_hash
;
769 /* Hash table for register lookup. */
770 static struct hash_control
*reg_hash
;
773 i386_align_code (fragS
*fragP
, int count
)
775 /* Various efficient no-op patterns for aligning code labels.
776 Note: Don't try to assemble the instructions in the comments.
777 0L and 0w are not legal. */
778 static const char f32_1
[] =
780 static const char f32_2
[] =
781 {0x66,0x90}; /* xchg %ax,%ax */
782 static const char f32_3
[] =
783 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
784 static const char f32_4
[] =
785 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
786 static const char f32_5
[] =
788 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
789 static const char f32_6
[] =
790 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
791 static const char f32_7
[] =
792 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
793 static const char f32_8
[] =
795 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
796 static const char f32_9
[] =
797 {0x89,0xf6, /* movl %esi,%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_10
[] =
800 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_11
[] =
803 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_12
[] =
806 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
807 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
808 static const char f32_13
[] =
809 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_14
[] =
812 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
814 static const char f16_3
[] =
815 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
816 static const char f16_4
[] =
817 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
818 static const char f16_5
[] =
820 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
821 static const char f16_6
[] =
822 {0x89,0xf6, /* mov %si,%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char f16_7
[] =
825 {0x8d,0x74,0x00, /* lea 0(%si),%si */
826 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
827 static const char f16_8
[] =
828 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
829 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
830 static const char jump_31
[] =
831 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
833 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
835 static const char *const f32_patt
[] = {
836 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
837 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
839 static const char *const f16_patt
[] = {
840 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
843 static const char alt_3
[] =
845 /* nopl 0(%[re]ax) */
846 static const char alt_4
[] =
847 {0x0f,0x1f,0x40,0x00};
848 /* nopl 0(%[re]ax,%[re]ax,1) */
849 static const char alt_5
[] =
850 {0x0f,0x1f,0x44,0x00,0x00};
851 /* nopw 0(%[re]ax,%[re]ax,1) */
852 static const char alt_6
[] =
853 {0x66,0x0f,0x1f,0x44,0x00,0x00};
854 /* nopl 0L(%[re]ax) */
855 static const char alt_7
[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
857 /* nopl 0L(%[re]ax,%[re]ax,1) */
858 static const char alt_8
[] =
859 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* nopw 0L(%[re]ax,%[re]ax,1) */
861 static const char alt_9
[] =
862 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_10
[] =
865 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_11
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 nopw %cs:0L(%[re]ax,%[re]ax,1) */
874 static const char alt_long_12
[] =
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_13
[] =
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
891 nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_long_14
[] =
897 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_15
[] =
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* nopl 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_11
[] =
914 {0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_short_12
[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x66,0x0f,0x1f,0x44,0x00,0x00};
921 /* nopw 0(%[re]ax,%[re]ax,1)
923 static const char alt_short_13
[] =
924 {0x66,0x0f,0x1f,0x44,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 static const char alt_short_14
[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
932 nopl 0L(%[re]ax,%[re]ax,1) */
933 static const char alt_short_15
[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
935 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
936 static const char *const alt_short_patt
[] = {
937 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
938 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
939 alt_short_14
, alt_short_15
941 static const char *const alt_long_patt
[] = {
942 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
943 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
944 alt_long_14
, alt_long_15
947 /* Only align for at least a positive non-zero boundary. */
948 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
951 /* We need to decide which NOP sequence to use for 32bit and
952 64bit. When -mtune= is used:
954 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
955 PROCESSOR_GENERIC32, f32_patt will be used.
956 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
957 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
958 PROCESSOR_GENERIC64, alt_long_patt will be used.
959 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
960 PROCESSOR_AMDFAM10, alt_short_patt will be used.
962 When -mtune= isn't used, alt_long_patt will be used if
963 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 When -march= or .arch is used, we can't use anything beyond
967 cpu_arch_isa_flags. */
969 if (flag_code
== CODE_16BIT
)
973 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
975 /* Adjust jump offset. */
976 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
979 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
980 f16_patt
[count
- 1], count
);
984 const char *const *patt
= NULL
;
986 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
988 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
989 switch (cpu_arch_tune
)
991 case PROCESSOR_UNKNOWN
:
992 /* We use cpu_arch_isa_flags to check if we SHOULD
993 optimize for Cpu686. */
994 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
995 patt
= alt_long_patt
;
999 case PROCESSOR_PENTIUMPRO
:
1000 case PROCESSOR_PENTIUM4
:
1001 case PROCESSOR_NOCONA
:
1002 case PROCESSOR_CORE
:
1003 case PROCESSOR_CORE2
:
1004 case PROCESSOR_COREI7
:
1005 case PROCESSOR_L1OM
:
1006 case PROCESSOR_GENERIC64
:
1007 patt
= alt_long_patt
;
1010 case PROCESSOR_ATHLON
:
1012 case PROCESSOR_AMDFAM10
:
1013 patt
= alt_short_patt
;
1015 case PROCESSOR_I386
:
1016 case PROCESSOR_I486
:
1017 case PROCESSOR_PENTIUM
:
1018 case PROCESSOR_GENERIC32
:
1025 switch (fragP
->tc_frag_data
.tune
)
1027 case PROCESSOR_UNKNOWN
:
1028 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1029 PROCESSOR_UNKNOWN. */
1033 case PROCESSOR_I386
:
1034 case PROCESSOR_I486
:
1035 case PROCESSOR_PENTIUM
:
1037 case PROCESSOR_ATHLON
:
1039 case PROCESSOR_AMDFAM10
:
1040 case PROCESSOR_GENERIC32
:
1041 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1044 patt
= alt_short_patt
;
1048 case PROCESSOR_PENTIUMPRO
:
1049 case PROCESSOR_PENTIUM4
:
1050 case PROCESSOR_NOCONA
:
1051 case PROCESSOR_CORE
:
1052 case PROCESSOR_CORE2
:
1053 case PROCESSOR_COREI7
:
1054 case PROCESSOR_L1OM
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1073 /* For 64bit, the limit is 3 bytes. */
1074 if (flag_code
== CODE_64BIT
1075 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1080 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1081 patt
[count
- 1], count
);
1084 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1086 /* Adjust jump offset. */
1087 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1092 /* Maximum length of an instruction is 15 byte. If the
1093 padding is greater than 15 bytes and we don't use jump,
1094 we have to break it into smaller pieces. */
1095 int padding
= count
;
1096 while (padding
> 15)
1099 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1104 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1105 patt
[padding
- 1], padding
);
1108 fragP
->fr_var
= count
;
1112 operand_type_all_zero (const union i386_operand_type
*x
)
1114 switch (ARRAY_SIZE(x
->array
))
1123 return !x
->array
[0];
1130 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1132 switch (ARRAY_SIZE(x
->array
))
1147 operand_type_equal (const union i386_operand_type
*x
,
1148 const union i386_operand_type
*y
)
1150 switch (ARRAY_SIZE(x
->array
))
1153 if (x
->array
[2] != y
->array
[2])
1156 if (x
->array
[1] != y
->array
[1])
1159 return x
->array
[0] == y
->array
[0];
1167 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1169 switch (ARRAY_SIZE(x
->array
))
1178 return !x
->array
[0];
1185 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1187 switch (ARRAY_SIZE(x
->array
))
1202 cpu_flags_equal (const union i386_cpu_flags
*x
,
1203 const union i386_cpu_flags
*y
)
1205 switch (ARRAY_SIZE(x
->array
))
1208 if (x
->array
[2] != y
->array
[2])
1211 if (x
->array
[1] != y
->array
[1])
1214 return x
->array
[0] == y
->array
[0];
1222 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1224 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1225 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1228 static INLINE i386_cpu_flags
1229 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1231 switch (ARRAY_SIZE (x
.array
))
1234 x
.array
[2] &= y
.array
[2];
1236 x
.array
[1] &= y
.array
[1];
1238 x
.array
[0] &= y
.array
[0];
1246 static INLINE i386_cpu_flags
1247 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1249 switch (ARRAY_SIZE (x
.array
))
1252 x
.array
[2] |= y
.array
[2];
1254 x
.array
[1] |= y
.array
[1];
1256 x
.array
[0] |= y
.array
[0];
1264 static INLINE i386_cpu_flags
1265 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1267 switch (ARRAY_SIZE (x
.array
))
1270 x
.array
[2] &= ~y
.array
[2];
1272 x
.array
[1] &= ~y
.array
[1];
1274 x
.array
[0] &= ~y
.array
[0];
1282 #define CPU_FLAGS_ARCH_MATCH 0x1
1283 #define CPU_FLAGS_64BIT_MATCH 0x2
1284 #define CPU_FLAGS_AES_MATCH 0x4
1285 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1286 #define CPU_FLAGS_AVX_MATCH 0x10
1288 #define CPU_FLAGS_32BIT_MATCH \
1289 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1290 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1291 #define CPU_FLAGS_PERFECT_MATCH \
1292 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1294 /* Return CPU flags match bits. */
1297 cpu_flags_match (const insn_template
*t
)
1299 i386_cpu_flags x
= t
->cpu_flags
;
1300 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1302 x
.bitfield
.cpu64
= 0;
1303 x
.bitfield
.cpuno64
= 0;
1305 if (cpu_flags_all_zero (&x
))
1307 /* This instruction is available on all archs. */
1308 match
|= CPU_FLAGS_32BIT_MATCH
;
1312 /* This instruction is available only on some archs. */
1313 i386_cpu_flags cpu
= cpu_arch_flags
;
1315 cpu
.bitfield
.cpu64
= 0;
1316 cpu
.bitfield
.cpuno64
= 0;
1317 cpu
= cpu_flags_and (x
, cpu
);
1318 if (!cpu_flags_all_zero (&cpu
))
1320 if (x
.bitfield
.cpuavx
)
1322 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1323 if (cpu
.bitfield
.cpuavx
)
1325 /* Check SSE2AVX. */
1326 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1328 match
|= (CPU_FLAGS_ARCH_MATCH
1329 | CPU_FLAGS_AVX_MATCH
);
1331 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1332 match
|= CPU_FLAGS_AES_MATCH
;
1334 if (!x
.bitfield
.cpupclmul
1335 || cpu
.bitfield
.cpupclmul
)
1336 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1340 match
|= CPU_FLAGS_ARCH_MATCH
;
1343 match
|= CPU_FLAGS_32BIT_MATCH
;
1349 static INLINE i386_operand_type
1350 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1352 switch (ARRAY_SIZE (x
.array
))
1355 x
.array
[2] &= y
.array
[2];
1357 x
.array
[1] &= y
.array
[1];
1359 x
.array
[0] &= y
.array
[0];
1367 static INLINE i386_operand_type
1368 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1370 switch (ARRAY_SIZE (x
.array
))
1373 x
.array
[2] |= y
.array
[2];
1375 x
.array
[1] |= y
.array
[1];
1377 x
.array
[0] |= y
.array
[0];
1385 static INLINE i386_operand_type
1386 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1388 switch (ARRAY_SIZE (x
.array
))
1391 x
.array
[2] ^= y
.array
[2];
1393 x
.array
[1] ^= y
.array
[1];
1395 x
.array
[0] ^= y
.array
[0];
1403 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1404 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1405 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1406 static const i386_operand_type inoutportreg
1407 = OPERAND_TYPE_INOUTPORTREG
;
1408 static const i386_operand_type reg16_inoutportreg
1409 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1410 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1411 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1412 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1413 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1414 static const i386_operand_type anydisp
1415 = OPERAND_TYPE_ANYDISP
;
1416 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1417 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1418 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1419 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1420 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1421 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1422 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1423 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1424 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1425 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1426 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1437 operand_type_check (i386_operand_type t
, enum operand_type c
)
1442 return (t
.bitfield
.reg8
1445 || t
.bitfield
.reg64
);
1448 return (t
.bitfield
.imm8
1452 || t
.bitfield
.imm32s
1453 || t
.bitfield
.imm64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
);
1463 return (t
.bitfield
.disp8
1464 || t
.bitfield
.disp16
1465 || t
.bitfield
.disp32
1466 || t
.bitfield
.disp32s
1467 || t
.bitfield
.disp64
1468 || t
.bitfield
.baseindex
);
1477 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1478 operand J for instruction template T. */
1481 match_reg_size (const insn_template
*t
, unsigned int j
)
1483 return !((i
.types
[j
].bitfield
.byte
1484 && !t
->operand_types
[j
].bitfield
.byte
)
1485 || (i
.types
[j
].bitfield
.word
1486 && !t
->operand_types
[j
].bitfield
.word
)
1487 || (i
.types
[j
].bitfield
.dword
1488 && !t
->operand_types
[j
].bitfield
.dword
)
1489 || (i
.types
[j
].bitfield
.qword
1490 && !t
->operand_types
[j
].bitfield
.qword
));
1493 /* Return 1 if there is no conflict in any size on operand J for
1494 instruction template T. */
1497 match_mem_size (const insn_template
*t
, unsigned int j
)
1499 return (match_reg_size (t
, j
)
1500 && !((i
.types
[j
].bitfield
.unspecified
1501 && !t
->operand_types
[j
].bitfield
.unspecified
)
1502 || (i
.types
[j
].bitfield
.fword
1503 && !t
->operand_types
[j
].bitfield
.fword
)
1504 || (i
.types
[j
].bitfield
.tbyte
1505 && !t
->operand_types
[j
].bitfield
.tbyte
)
1506 || (i
.types
[j
].bitfield
.xmmword
1507 && !t
->operand_types
[j
].bitfield
.xmmword
)
1508 || (i
.types
[j
].bitfield
.ymmword
1509 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1512 /* Return 1 if there is no size conflict on any operands for
1513 instruction template T. */
1516 operand_size_match (const insn_template
*t
)
1521 /* Don't check jump instructions. */
1522 if (t
->opcode_modifier
.jump
1523 || t
->opcode_modifier
.jumpbyte
1524 || t
->opcode_modifier
.jumpdword
1525 || t
->opcode_modifier
.jumpintersegment
)
1528 /* Check memory and accumulator operand size. */
1529 for (j
= 0; j
< i
.operands
; j
++)
1531 if (t
->operand_types
[j
].bitfield
.anysize
)
1534 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1540 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1548 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1551 /* Check reverse. */
1552 gas_assert (i
.operands
== 2);
1555 for (j
= 0; j
< 2; j
++)
1557 if (t
->operand_types
[j
].bitfield
.acc
1558 && !match_reg_size (t
, j
? 0 : 1))
1564 if (i
.types
[j
].bitfield
.mem
1565 && !match_mem_size (t
, j
? 0 : 1))
1576 operand_type_match (i386_operand_type overlap
,
1577 i386_operand_type given
)
1579 i386_operand_type temp
= overlap
;
1581 temp
.bitfield
.jumpabsolute
= 0;
1582 temp
.bitfield
.unspecified
= 0;
1583 temp
.bitfield
.byte
= 0;
1584 temp
.bitfield
.word
= 0;
1585 temp
.bitfield
.dword
= 0;
1586 temp
.bitfield
.fword
= 0;
1587 temp
.bitfield
.qword
= 0;
1588 temp
.bitfield
.tbyte
= 0;
1589 temp
.bitfield
.xmmword
= 0;
1590 temp
.bitfield
.ymmword
= 0;
1591 if (operand_type_all_zero (&temp
))
1594 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1595 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1598 /* If given types g0 and g1 are registers they must be of the same type
1599 unless the expected operand type register overlap is null.
1600 Note that Acc in a template matches every size of reg. */
1603 operand_type_register_match (i386_operand_type m0
,
1604 i386_operand_type g0
,
1605 i386_operand_type t0
,
1606 i386_operand_type m1
,
1607 i386_operand_type g1
,
1608 i386_operand_type t1
)
1610 if (!operand_type_check (g0
, reg
))
1613 if (!operand_type_check (g1
, reg
))
1616 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1617 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1618 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1619 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1622 if (m0
.bitfield
.acc
)
1624 t0
.bitfield
.reg8
= 1;
1625 t0
.bitfield
.reg16
= 1;
1626 t0
.bitfield
.reg32
= 1;
1627 t0
.bitfield
.reg64
= 1;
1630 if (m1
.bitfield
.acc
)
1632 t1
.bitfield
.reg8
= 1;
1633 t1
.bitfield
.reg16
= 1;
1634 t1
.bitfield
.reg32
= 1;
1635 t1
.bitfield
.reg64
= 1;
1638 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1639 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1640 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1641 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1644 static INLINE
unsigned int
1645 mode_from_disp_size (i386_operand_type t
)
1647 if (t
.bitfield
.disp8
)
1649 else if (t
.bitfield
.disp16
1650 || t
.bitfield
.disp32
1651 || t
.bitfield
.disp32s
)
1658 fits_in_signed_byte (offsetT num
)
1660 return (num
>= -128) && (num
<= 127);
1664 fits_in_unsigned_byte (offsetT num
)
1666 return (num
& 0xff) == num
;
1670 fits_in_unsigned_word (offsetT num
)
1672 return (num
& 0xffff) == num
;
1676 fits_in_signed_word (offsetT num
)
1678 return (-32768 <= num
) && (num
<= 32767);
1682 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1687 return (!(((offsetT
) -1 << 31) & num
)
1688 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1690 } /* fits_in_signed_long() */
1693 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1698 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1700 } /* fits_in_unsigned_long() */
1702 static i386_operand_type
1703 smallest_imm_type (offsetT num
)
1705 i386_operand_type t
;
1707 operand_type_set (&t
, 0);
1708 t
.bitfield
.imm64
= 1;
1710 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1712 /* This code is disabled on the 486 because all the Imm1 forms
1713 in the opcode table are slower on the i486. They're the
1714 versions with the implicitly specified single-position
1715 displacement, which has another syntax if you really want to
1717 t
.bitfield
.imm1
= 1;
1718 t
.bitfield
.imm8
= 1;
1719 t
.bitfield
.imm8s
= 1;
1720 t
.bitfield
.imm16
= 1;
1721 t
.bitfield
.imm32
= 1;
1722 t
.bitfield
.imm32s
= 1;
1724 else if (fits_in_signed_byte (num
))
1726 t
.bitfield
.imm8
= 1;
1727 t
.bitfield
.imm8s
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_unsigned_byte (num
))
1734 t
.bitfield
.imm8
= 1;
1735 t
.bitfield
.imm16
= 1;
1736 t
.bitfield
.imm32
= 1;
1737 t
.bitfield
.imm32s
= 1;
1739 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1741 t
.bitfield
.imm16
= 1;
1742 t
.bitfield
.imm32
= 1;
1743 t
.bitfield
.imm32s
= 1;
1745 else if (fits_in_signed_long (num
))
1747 t
.bitfield
.imm32
= 1;
1748 t
.bitfield
.imm32s
= 1;
1750 else if (fits_in_unsigned_long (num
))
1751 t
.bitfield
.imm32
= 1;
1757 offset_in_range (offsetT val
, int size
)
1763 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1764 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1765 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1767 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1773 /* If BFD64, sign extend val for 32bit address mode. */
1774 if (flag_code
!= CODE_64BIT
1775 || i
.prefix
[ADDR_PREFIX
])
1776 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1777 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1780 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1782 char buf1
[40], buf2
[40];
1784 sprint_value (buf1
, val
);
1785 sprint_value (buf2
, val
& mask
);
1786 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1800 a. PREFIX_EXIST if attempting to add a prefix where one from the
1801 same class already exists.
1802 b. PREFIX_LOCK if lock prefix is added.
1803 c. PREFIX_REP if rep/repne prefix is added.
1804 d. PREFIX_OTHER if other prefix is added.
1807 static enum PREFIX_GROUP
1808 add_prefix (unsigned int prefix
)
1810 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1813 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1814 && flag_code
== CODE_64BIT
)
1816 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1817 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1818 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1829 case CS_PREFIX_OPCODE
:
1830 case DS_PREFIX_OPCODE
:
1831 case ES_PREFIX_OPCODE
:
1832 case FS_PREFIX_OPCODE
:
1833 case GS_PREFIX_OPCODE
:
1834 case SS_PREFIX_OPCODE
:
1838 case REPNE_PREFIX_OPCODE
:
1839 case REPE_PREFIX_OPCODE
:
1844 case LOCK_PREFIX_OPCODE
:
1853 case ADDR_PREFIX_OPCODE
:
1857 case DATA_PREFIX_OPCODE
:
1861 if (i
.prefix
[q
] != 0)
1869 i
.prefix
[q
] |= prefix
;
1872 as_bad (_("same type of prefix used twice"));
1878 set_code_flag (int value
)
1880 flag_code
= (enum flag_code
) value
;
1881 if (flag_code
== CODE_64BIT
)
1883 cpu_arch_flags
.bitfield
.cpu64
= 1;
1884 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1888 cpu_arch_flags
.bitfield
.cpu64
= 0;
1889 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1891 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1893 as_bad (_("64bit mode not supported on this CPU."));
1895 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1897 as_bad (_("32bit mode not supported on this CPU."));
1899 stackop_size
= '\0';
1903 set_16bit_gcc_code_flag (int new_code_flag
)
1905 flag_code
= (enum flag_code
) new_code_flag
;
1906 if (flag_code
!= CODE_16BIT
)
1908 cpu_arch_flags
.bitfield
.cpu64
= 0;
1909 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1910 stackop_size
= LONG_MNEM_SUFFIX
;
1914 set_intel_syntax (int syntax_flag
)
1916 /* Find out if register prefixing is specified. */
1917 int ask_naked_reg
= 0;
1920 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1922 char *string
= input_line_pointer
;
1923 int e
= get_symbol_end ();
1925 if (strcmp (string
, "prefix") == 0)
1927 else if (strcmp (string
, "noprefix") == 0)
1930 as_bad (_("bad argument to syntax directive."));
1931 *input_line_pointer
= e
;
1933 demand_empty_rest_of_line ();
1935 intel_syntax
= syntax_flag
;
1937 if (ask_naked_reg
== 0)
1938 allow_naked_reg
= (intel_syntax
1939 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1941 allow_naked_reg
= (ask_naked_reg
< 0);
1943 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1945 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1946 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1947 register_prefix
= allow_naked_reg
? "" : "%";
1951 set_intel_mnemonic (int mnemonic_flag
)
1953 intel_mnemonic
= mnemonic_flag
;
1957 set_allow_index_reg (int flag
)
1959 allow_index_reg
= flag
;
1963 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1967 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1969 char *string
= input_line_pointer
;
1970 int e
= get_symbol_end ();
1972 if (strcmp (string
, "none") == 0)
1973 sse_check
= sse_check_none
;
1974 else if (strcmp (string
, "warning") == 0)
1975 sse_check
= sse_check_warning
;
1976 else if (strcmp (string
, "error") == 0)
1977 sse_check
= sse_check_error
;
1979 as_bad (_("bad argument to sse_check directive."));
1980 *input_line_pointer
= e
;
1983 as_bad (_("missing argument for sse_check directive"));
1985 demand_empty_rest_of_line ();
1989 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1990 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1993 static const char *arch
;
1995 /* Intel LIOM is only supported on ELF. */
2001 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2002 use default_arch. */
2003 arch
= cpu_arch_name
;
2005 arch
= default_arch
;
2008 /* If we are targeting Intel L1OM, we must enable it. */
2009 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2010 || new_flag
.bitfield
.cpul1om
)
2013 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2018 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2022 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2024 char *string
= input_line_pointer
;
2025 int e
= get_symbol_end ();
2027 i386_cpu_flags flags
;
2029 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2031 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2033 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2037 cpu_arch_name
= cpu_arch
[j
].name
;
2038 cpu_sub_arch_name
= NULL
;
2039 cpu_arch_flags
= cpu_arch
[j
].flags
;
2040 if (flag_code
== CODE_64BIT
)
2042 cpu_arch_flags
.bitfield
.cpu64
= 1;
2043 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2047 cpu_arch_flags
.bitfield
.cpu64
= 0;
2048 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2050 cpu_arch_isa
= cpu_arch
[j
].type
;
2051 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2052 if (!cpu_arch_tune_set
)
2054 cpu_arch_tune
= cpu_arch_isa
;
2055 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2060 if (strncmp (string
+ 1, "no", 2))
2061 flags
= cpu_flags_or (cpu_arch_flags
,
2064 flags
= cpu_flags_and_not (cpu_arch_flags
,
2066 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2068 if (cpu_sub_arch_name
)
2070 char *name
= cpu_sub_arch_name
;
2071 cpu_sub_arch_name
= concat (name
,
2073 (const char *) NULL
);
2077 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2078 cpu_arch_flags
= flags
;
2080 *input_line_pointer
= e
;
2081 demand_empty_rest_of_line ();
2085 if (j
>= ARRAY_SIZE (cpu_arch
))
2086 as_bad (_("no such architecture: `%s'"), string
);
2088 *input_line_pointer
= e
;
2091 as_bad (_("missing cpu architecture"));
2093 no_cond_jump_promotion
= 0;
2094 if (*input_line_pointer
== ','
2095 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2097 char *string
= ++input_line_pointer
;
2098 int e
= get_symbol_end ();
2100 if (strcmp (string
, "nojumps") == 0)
2101 no_cond_jump_promotion
= 1;
2102 else if (strcmp (string
, "jumps") == 0)
2105 as_bad (_("no such architecture modifier: `%s'"), string
);
2107 *input_line_pointer
= e
;
2110 demand_empty_rest_of_line ();
2113 enum bfd_architecture
2116 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2118 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2119 || flag_code
!= CODE_64BIT
)
2120 as_fatal (_("Intel L1OM is 64bit ELF only"));
2121 return bfd_arch_l1om
;
2124 return bfd_arch_i386
;
2130 if (!strcmp (default_arch
, "x86_64"))
2132 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2134 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2135 as_fatal (_("Intel L1OM is 64bit ELF only"));
2136 return bfd_mach_l1om
;
2139 return bfd_mach_x86_64
;
2141 else if (!strcmp (default_arch
, "i386"))
2142 return bfd_mach_i386_i386
;
2144 as_fatal (_("Unknown architecture"));
2150 const char *hash_err
;
2152 /* Initialize op_hash hash table. */
2153 op_hash
= hash_new ();
2156 const insn_template
*optab
;
2157 templates
*core_optab
;
2159 /* Setup for loop. */
2161 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2162 core_optab
->start
= optab
;
2167 if (optab
->name
== NULL
2168 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2170 /* different name --> ship out current template list;
2171 add to hash table; & begin anew. */
2172 core_optab
->end
= optab
;
2173 hash_err
= hash_insert (op_hash
,
2175 (void *) core_optab
);
2178 as_fatal (_("Internal Error: Can't hash %s: %s"),
2182 if (optab
->name
== NULL
)
2184 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2185 core_optab
->start
= optab
;
2190 /* Initialize reg_hash hash table. */
2191 reg_hash
= hash_new ();
2193 const reg_entry
*regtab
;
2194 unsigned int regtab_size
= i386_regtab_size
;
2196 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2198 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2200 as_fatal (_("Internal Error: Can't hash %s: %s"),
2206 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2211 for (c
= 0; c
< 256; c
++)
2216 mnemonic_chars
[c
] = c
;
2217 register_chars
[c
] = c
;
2218 operand_chars
[c
] = c
;
2220 else if (ISLOWER (c
))
2222 mnemonic_chars
[c
] = c
;
2223 register_chars
[c
] = c
;
2224 operand_chars
[c
] = c
;
2226 else if (ISUPPER (c
))
2228 mnemonic_chars
[c
] = TOLOWER (c
);
2229 register_chars
[c
] = mnemonic_chars
[c
];
2230 operand_chars
[c
] = c
;
2233 if (ISALPHA (c
) || ISDIGIT (c
))
2234 identifier_chars
[c
] = c
;
2237 identifier_chars
[c
] = c
;
2238 operand_chars
[c
] = c
;
2243 identifier_chars
['@'] = '@';
2246 identifier_chars
['?'] = '?';
2247 operand_chars
['?'] = '?';
2249 digit_chars
['-'] = '-';
2250 mnemonic_chars
['_'] = '_';
2251 mnemonic_chars
['-'] = '-';
2252 mnemonic_chars
['.'] = '.';
2253 identifier_chars
['_'] = '_';
2254 identifier_chars
['.'] = '.';
2256 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2257 operand_chars
[(unsigned char) *p
] = *p
;
2260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2263 record_alignment (text_section
, 2);
2264 record_alignment (data_section
, 2);
2265 record_alignment (bss_section
, 2);
2269 if (flag_code
== CODE_64BIT
)
2271 x86_dwarf2_return_column
= 16;
2272 x86_cie_data_alignment
= -8;
2276 x86_dwarf2_return_column
= 8;
2277 x86_cie_data_alignment
= -4;
2282 i386_print_statistics (FILE *file
)
2284 hash_print_statistics (file
, "i386 opcode", op_hash
);
2285 hash_print_statistics (file
, "i386 register", reg_hash
);
2290 /* Debugging routines for md_assemble. */
2291 static void pte (insn_template
*);
2292 static void pt (i386_operand_type
);
2293 static void pe (expressionS
*);
2294 static void ps (symbolS
*);
2297 pi (char *line
, i386_insn
*x
)
2301 fprintf (stdout
, "%s: template ", line
);
2303 fprintf (stdout
, " address: base %s index %s scale %x\n",
2304 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2305 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2306 x
->log2_scale_factor
);
2307 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2308 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2309 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2310 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2311 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2312 (x
->rex
& REX_W
) != 0,
2313 (x
->rex
& REX_R
) != 0,
2314 (x
->rex
& REX_X
) != 0,
2315 (x
->rex
& REX_B
) != 0);
2316 for (i
= 0; i
< x
->operands
; i
++)
2318 fprintf (stdout
, " #%d: ", i
+ 1);
2320 fprintf (stdout
, "\n");
2321 if (x
->types
[i
].bitfield
.reg8
2322 || x
->types
[i
].bitfield
.reg16
2323 || x
->types
[i
].bitfield
.reg32
2324 || x
->types
[i
].bitfield
.reg64
2325 || x
->types
[i
].bitfield
.regmmx
2326 || x
->types
[i
].bitfield
.regxmm
2327 || x
->types
[i
].bitfield
.regymm
2328 || x
->types
[i
].bitfield
.sreg2
2329 || x
->types
[i
].bitfield
.sreg3
2330 || x
->types
[i
].bitfield
.control
2331 || x
->types
[i
].bitfield
.debug
2332 || x
->types
[i
].bitfield
.test
)
2333 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2334 if (operand_type_check (x
->types
[i
], imm
))
2336 if (operand_type_check (x
->types
[i
], disp
))
2337 pe (x
->op
[i
].disps
);
2342 pte (insn_template
*t
)
2345 fprintf (stdout
, " %d operands ", t
->operands
);
2346 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2347 if (t
->extension_opcode
!= None
)
2348 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2349 if (t
->opcode_modifier
.d
)
2350 fprintf (stdout
, "D");
2351 if (t
->opcode_modifier
.w
)
2352 fprintf (stdout
, "W");
2353 fprintf (stdout
, "\n");
2354 for (i
= 0; i
< t
->operands
; i
++)
2356 fprintf (stdout
, " #%d type ", i
+ 1);
2357 pt (t
->operand_types
[i
]);
2358 fprintf (stdout
, "\n");
2365 fprintf (stdout
, " operation %d\n", e
->X_op
);
2366 fprintf (stdout
, " add_number %ld (%lx)\n",
2367 (long) e
->X_add_number
, (long) e
->X_add_number
);
2368 if (e
->X_add_symbol
)
2370 fprintf (stdout
, " add_symbol ");
2371 ps (e
->X_add_symbol
);
2372 fprintf (stdout
, "\n");
2376 fprintf (stdout
, " op_symbol ");
2377 ps (e
->X_op_symbol
);
2378 fprintf (stdout
, "\n");
2385 fprintf (stdout
, "%s type %s%s",
2387 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2388 segment_name (S_GET_SEGMENT (s
)));
2391 static struct type_name
2393 i386_operand_type mask
;
2396 const type_names
[] =
2398 { OPERAND_TYPE_REG8
, "r8" },
2399 { OPERAND_TYPE_REG16
, "r16" },
2400 { OPERAND_TYPE_REG32
, "r32" },
2401 { OPERAND_TYPE_REG64
, "r64" },
2402 { OPERAND_TYPE_IMM8
, "i8" },
2403 { OPERAND_TYPE_IMM8
, "i8s" },
2404 { OPERAND_TYPE_IMM16
, "i16" },
2405 { OPERAND_TYPE_IMM32
, "i32" },
2406 { OPERAND_TYPE_IMM32S
, "i32s" },
2407 { OPERAND_TYPE_IMM64
, "i64" },
2408 { OPERAND_TYPE_IMM1
, "i1" },
2409 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2410 { OPERAND_TYPE_DISP8
, "d8" },
2411 { OPERAND_TYPE_DISP16
, "d16" },
2412 { OPERAND_TYPE_DISP32
, "d32" },
2413 { OPERAND_TYPE_DISP32S
, "d32s" },
2414 { OPERAND_TYPE_DISP64
, "d64" },
2415 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2416 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2417 { OPERAND_TYPE_CONTROL
, "control reg" },
2418 { OPERAND_TYPE_TEST
, "test reg" },
2419 { OPERAND_TYPE_DEBUG
, "debug reg" },
2420 { OPERAND_TYPE_FLOATREG
, "FReg" },
2421 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2422 { OPERAND_TYPE_SREG2
, "SReg2" },
2423 { OPERAND_TYPE_SREG3
, "SReg3" },
2424 { OPERAND_TYPE_ACC
, "Acc" },
2425 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2426 { OPERAND_TYPE_REGMMX
, "rMMX" },
2427 { OPERAND_TYPE_REGXMM
, "rXMM" },
2428 { OPERAND_TYPE_REGYMM
, "rYMM" },
2429 { OPERAND_TYPE_ESSEG
, "es" },
2433 pt (i386_operand_type t
)
2436 i386_operand_type a
;
2438 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2440 a
= operand_type_and (t
, type_names
[j
].mask
);
2441 if (!operand_type_all_zero (&a
))
2442 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2447 #endif /* DEBUG386 */
2449 static bfd_reloc_code_real_type
2450 reloc (unsigned int size
,
2453 bfd_reloc_code_real_type other
)
2455 if (other
!= NO_RELOC
)
2457 reloc_howto_type
*rel
;
2462 case BFD_RELOC_X86_64_GOT32
:
2463 return BFD_RELOC_X86_64_GOT64
;
2465 case BFD_RELOC_X86_64_PLTOFF64
:
2466 return BFD_RELOC_X86_64_PLTOFF64
;
2468 case BFD_RELOC_X86_64_GOTPC32
:
2469 other
= BFD_RELOC_X86_64_GOTPC64
;
2471 case BFD_RELOC_X86_64_GOTPCREL
:
2472 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2474 case BFD_RELOC_X86_64_TPOFF32
:
2475 other
= BFD_RELOC_X86_64_TPOFF64
;
2477 case BFD_RELOC_X86_64_DTPOFF32
:
2478 other
= BFD_RELOC_X86_64_DTPOFF64
;
2484 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2485 if (size
== 4 && flag_code
!= CODE_64BIT
)
2488 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2490 as_bad (_("unknown relocation (%u)"), other
);
2491 else if (size
!= bfd_get_reloc_size (rel
))
2492 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2493 bfd_get_reloc_size (rel
),
2495 else if (pcrel
&& !rel
->pc_relative
)
2496 as_bad (_("non-pc-relative relocation for pc-relative field"));
2497 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2499 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2501 as_bad (_("relocated field and relocation type differ in signedness"));
2510 as_bad (_("there are no unsigned pc-relative relocations"));
2513 case 1: return BFD_RELOC_8_PCREL
;
2514 case 2: return BFD_RELOC_16_PCREL
;
2515 case 4: return BFD_RELOC_32_PCREL
;
2516 case 8: return BFD_RELOC_64_PCREL
;
2518 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2525 case 4: return BFD_RELOC_X86_64_32S
;
2530 case 1: return BFD_RELOC_8
;
2531 case 2: return BFD_RELOC_16
;
2532 case 4: return BFD_RELOC_32
;
2533 case 8: return BFD_RELOC_64
;
2535 as_bad (_("cannot do %s %u byte relocation"),
2536 sign
> 0 ? "signed" : "unsigned", size
);
2542 /* Here we decide which fixups can be adjusted to make them relative to
2543 the beginning of the section instead of the symbol. Basically we need
2544 to make sure that the dynamic relocations are done correctly, so in
2545 some cases we force the original symbol to be used. */
2548 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2554 /* Don't adjust pc-relative references to merge sections in 64-bit
2556 if (use_rela_relocations
2557 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2561 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2562 and changed later by validate_fix. */
2563 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2564 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2567 /* adjust_reloc_syms doesn't know about the GOT. */
2568 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2569 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2570 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2577 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2579 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2580 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2594 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2595 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2602 intel_float_operand (const char *mnemonic
)
2604 /* Note that the value returned is meaningful only for opcodes with (memory)
2605 operands, hence the code here is free to improperly handle opcodes that
2606 have no operands (for better performance and smaller code). */
2608 if (mnemonic
[0] != 'f')
2609 return 0; /* non-math */
2611 switch (mnemonic
[1])
2613 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2614 the fs segment override prefix not currently handled because no
2615 call path can make opcodes without operands get here */
2617 return 2 /* integer op */;
2619 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2620 return 3; /* fldcw/fldenv */
2623 if (mnemonic
[2] != 'o' /* fnop */)
2624 return 3; /* non-waiting control op */
2627 if (mnemonic
[2] == 's')
2628 return 3; /* frstor/frstpm */
2631 if (mnemonic
[2] == 'a')
2632 return 3; /* fsave */
2633 if (mnemonic
[2] == 't')
2635 switch (mnemonic
[3])
2637 case 'c': /* fstcw */
2638 case 'd': /* fstdw */
2639 case 'e': /* fstenv */
2640 case 's': /* fsts[gw] */
2646 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2647 return 0; /* fxsave/fxrstor are not really math ops */
2654 /* Build the VEX prefix. */
2657 build_vex_prefix (const insn_template
*t
)
2659 unsigned int register_specifier
;
2660 unsigned int implied_prefix
;
2661 unsigned int vector_length
;
2663 /* Check register specifier. */
2664 if (i
.vex
.register_specifier
)
2666 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2667 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2668 register_specifier
+= 8;
2669 register_specifier
= ~register_specifier
& 0xf;
2672 register_specifier
= 0xf;
2674 /* Use 2-byte VEX prefix by swappping destination and source
2677 && i
.operands
== i
.reg_operands
2678 && i
.tm
.opcode_modifier
.vex0f
2679 && i
.tm
.opcode_modifier
.s
2682 unsigned int xchg
= i
.operands
- 1;
2683 union i386_op temp_op
;
2684 i386_operand_type temp_type
;
2686 temp_type
= i
.types
[xchg
];
2687 i
.types
[xchg
] = i
.types
[0];
2688 i
.types
[0] = temp_type
;
2689 temp_op
= i
.op
[xchg
];
2690 i
.op
[xchg
] = i
.op
[0];
2693 gas_assert (i
.rm
.mode
== 3);
2697 i
.rm
.regmem
= i
.rm
.reg
;
2700 /* Use the next insn. */
2704 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2706 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2711 case DATA_PREFIX_OPCODE
:
2714 case REPE_PREFIX_OPCODE
:
2717 case REPNE_PREFIX_OPCODE
:
2724 /* Use 2-byte VEX prefix if possible. */
2725 if (i
.tm
.opcode_modifier
.vex0f
2726 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2728 /* 2-byte VEX prefix. */
2732 i
.vex
.bytes
[0] = 0xc5;
2734 /* Check the REX.R bit. */
2735 r
= (i
.rex
& REX_R
) ? 0 : 1;
2736 i
.vex
.bytes
[1] = (r
<< 7
2737 | register_specifier
<< 3
2738 | vector_length
<< 2
2743 /* 3-byte VEX prefix. */
2747 i
.vex
.bytes
[0] = 0xc4;
2749 if (i
.tm
.opcode_modifier
.vex0f
)
2751 else if (i
.tm
.opcode_modifier
.vex0f38
)
2753 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2755 else if (i
.tm
.opcode_modifier
.xop08
)
2758 i
.vex
.bytes
[0] = 0x8f;
2760 else if (i
.tm
.opcode_modifier
.xop09
)
2763 i
.vex
.bytes
[0] = 0x8f;
2765 else if (i
.tm
.opcode_modifier
.xop0a
)
2768 i
.vex
.bytes
[0] = 0x8f;
2773 /* The high 3 bits of the second VEX byte are 1's compliment
2774 of RXB bits from REX. */
2775 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2777 /* Check the REX.W bit. */
2778 w
= (i
.rex
& REX_W
) ? 1 : 0;
2779 if (i
.tm
.opcode_modifier
.vexw
)
2784 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2788 i
.vex
.bytes
[2] = (w
<< 7
2789 | register_specifier
<< 3
2790 | vector_length
<< 2
2796 process_immext (void)
2800 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2802 /* SSE3 Instructions have the fixed operands with an opcode
2803 suffix which is coded in the same place as an 8-bit immediate
2804 field would be. Here we check those operands and remove them
2808 for (x
= 0; x
< i
.operands
; x
++)
2809 if (i
.op
[x
].regs
->reg_num
!= x
)
2810 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2811 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2818 which is coded in the same place as an 8-bit immediate field
2819 would be. Here we fake an 8-bit immediate operand from the
2820 opcode suffix stored in tm.extension_opcode.
2822 AVX instructions also use this encoding, for some of
2823 3 argument instructions. */
2825 gas_assert (i
.imm_operands
== 0
2827 || (i
.tm
.opcode_modifier
.vex
2828 && i
.operands
<= 4)));
2830 exp
= &im_expressions
[i
.imm_operands
++];
2831 i
.op
[i
.operands
].imms
= exp
;
2832 i
.types
[i
.operands
] = imm8
;
2834 exp
->X_op
= O_constant
;
2835 exp
->X_add_number
= i
.tm
.extension_opcode
;
2836 i
.tm
.extension_opcode
= None
;
2839 /* This is the guts of the machine-dependent assembler. LINE points to a
2840 machine dependent instruction. This function is supposed to emit
2841 the frags/bytes it assembles to. */
2844 md_assemble (char *line
)
2847 char mnemonic
[MAX_MNEM_SIZE
];
2848 const insn_template
*t
;
2850 /* Initialize globals. */
2851 memset (&i
, '\0', sizeof (i
));
2852 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2853 i
.reloc
[j
] = NO_RELOC
;
2854 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2855 memset (im_expressions
, '\0', sizeof (im_expressions
));
2856 save_stack_p
= save_stack
;
2858 /* First parse an instruction mnemonic & call i386_operand for the operands.
2859 We assume that the scrubber has arranged it so that line[0] is the valid
2860 start of a (possibly prefixed) mnemonic. */
2862 line
= parse_insn (line
, mnemonic
);
2866 line
= parse_operands (line
, mnemonic
);
2871 /* Now we've parsed the mnemonic into a set of templates, and have the
2872 operands at hand. */
2874 /* All intel opcodes have reversed operands except for "bound" and
2875 "enter". We also don't reverse intersegment "jmp" and "call"
2876 instructions with 2 immediate operands so that the immediate segment
2877 precedes the offset, as it does when in AT&T mode. */
2880 && (strcmp (mnemonic
, "bound") != 0)
2881 && (strcmp (mnemonic
, "invlpga") != 0)
2882 && !(operand_type_check (i
.types
[0], imm
)
2883 && operand_type_check (i
.types
[1], imm
)))
2886 /* The order of the immediates should be reversed
2887 for 2 immediates extrq and insertq instructions */
2888 if (i
.imm_operands
== 2
2889 && (strcmp (mnemonic
, "extrq") == 0
2890 || strcmp (mnemonic
, "insertq") == 0))
2891 swap_2_operands (0, 1);
2896 /* Don't optimize displacement for movabs since it only takes 64bit
2899 && (flag_code
!= CODE_64BIT
2900 || strcmp (mnemonic
, "movabs") != 0))
2903 /* Next, we find a template that matches the given insn,
2904 making sure the overlap of the given operands types is consistent
2905 with the template operand types. */
2907 if (!(t
= match_template ()))
2910 if (sse_check
!= sse_check_none
2911 && !i
.tm
.opcode_modifier
.noavx
2912 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2913 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2914 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2915 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2916 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2917 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2919 (sse_check
== sse_check_warning
2921 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2924 /* Zap movzx and movsx suffix. The suffix has been set from
2925 "word ptr" or "byte ptr" on the source operand in Intel syntax
2926 or extracted from mnemonic in AT&T syntax. But we'll use
2927 the destination register to choose the suffix for encoding. */
2928 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2930 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2931 there is no suffix, the default will be byte extension. */
2932 if (i
.reg_operands
!= 2
2935 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2940 if (i
.tm
.opcode_modifier
.fwait
)
2941 if (!add_prefix (FWAIT_OPCODE
))
2944 /* Check for lock without a lockable instruction. Destination operand
2945 must be memory unless it is xchg (0x86). */
2946 if (i
.prefix
[LOCK_PREFIX
]
2947 && (!i
.tm
.opcode_modifier
.islockable
2948 || i
.mem_operands
== 0
2949 || (i
.tm
.base_opcode
!= 0x86
2950 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2952 as_bad (_("expecting lockable instruction after `lock'"));
2956 /* Check string instruction segment overrides. */
2957 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2959 if (!check_string ())
2961 i
.disp_operands
= 0;
2964 if (!process_suffix ())
2967 /* Update operand types. */
2968 for (j
= 0; j
< i
.operands
; j
++)
2969 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2971 /* Make still unresolved immediate matches conform to size of immediate
2972 given in i.suffix. */
2973 if (!finalize_imm ())
2976 if (i
.types
[0].bitfield
.imm1
)
2977 i
.imm_operands
= 0; /* kludge for shift insns. */
2979 /* We only need to check those implicit registers for instructions
2980 with 3 operands or less. */
2981 if (i
.operands
<= 3)
2982 for (j
= 0; j
< i
.operands
; j
++)
2983 if (i
.types
[j
].bitfield
.inoutportreg
2984 || i
.types
[j
].bitfield
.shiftcount
2985 || i
.types
[j
].bitfield
.acc
2986 || i
.types
[j
].bitfield
.floatacc
)
2989 /* ImmExt should be processed after SSE2AVX. */
2990 if (!i
.tm
.opcode_modifier
.sse2avx
2991 && i
.tm
.opcode_modifier
.immext
)
2994 /* For insns with operands there are more diddles to do to the opcode. */
2997 if (!process_operands ())
3000 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3002 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3003 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3006 if (i
.tm
.opcode_modifier
.vex
)
3007 build_vex_prefix (t
);
3009 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3010 instructions may define INT_OPCODE as well, so avoid this corner
3011 case for those instructions that use MODRM. */
3012 if (i
.tm
.base_opcode
== INT_OPCODE
3013 && i
.op
[0].imms
->X_add_number
== 3
3014 && !i
.tm
.opcode_modifier
.modrm
)
3016 i
.tm
.base_opcode
= INT3_OPCODE
;
3020 if ((i
.tm
.opcode_modifier
.jump
3021 || i
.tm
.opcode_modifier
.jumpbyte
3022 || i
.tm
.opcode_modifier
.jumpdword
)
3023 && i
.op
[0].disps
->X_op
== O_constant
)
3025 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3026 the absolute address given by the constant. Since ix86 jumps and
3027 calls are pc relative, we need to generate a reloc. */
3028 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3029 i
.op
[0].disps
->X_op
= O_symbol
;
3032 if (i
.tm
.opcode_modifier
.rex64
)
3035 /* For 8 bit registers we need an empty rex prefix. Also if the
3036 instruction already has a prefix, we need to convert old
3037 registers to new ones. */
3039 if ((i
.types
[0].bitfield
.reg8
3040 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3041 || (i
.types
[1].bitfield
.reg8
3042 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3043 || ((i
.types
[0].bitfield
.reg8
3044 || i
.types
[1].bitfield
.reg8
)
3049 i
.rex
|= REX_OPCODE
;
3050 for (x
= 0; x
< 2; x
++)
3052 /* Look for 8 bit operand that uses old registers. */
3053 if (i
.types
[x
].bitfield
.reg8
3054 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3056 /* In case it is "hi" register, give up. */
3057 if (i
.op
[x
].regs
->reg_num
> 3)
3058 as_bad (_("can't encode register '%s%s' in an "
3059 "instruction requiring REX prefix."),
3060 register_prefix
, i
.op
[x
].regs
->reg_name
);
3062 /* Otherwise it is equivalent to the extended register.
3063 Since the encoding doesn't change this is merely
3064 cosmetic cleanup for debug output. */
3066 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3072 add_prefix (REX_OPCODE
| i
.rex
);
3074 /* We are ready to output the insn. */
3079 parse_insn (char *line
, char *mnemonic
)
3082 char *token_start
= l
;
3085 const insn_template
*t
;
3088 /* Non-zero if we found a prefix only acceptable with string insns. */
3089 const char *expecting_string_instruction
= NULL
;
3094 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3099 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3101 as_bad (_("no such instruction: `%s'"), token_start
);
3106 if (!is_space_char (*l
)
3107 && *l
!= END_OF_INSN
3109 || (*l
!= PREFIX_SEPARATOR
3112 as_bad (_("invalid character %s in mnemonic"),
3113 output_invalid (*l
));
3116 if (token_start
== l
)
3118 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3119 as_bad (_("expecting prefix; got nothing"));
3121 as_bad (_("expecting mnemonic; got nothing"));
3125 /* Look up instruction (or prefix) via hash table. */
3126 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3128 if (*l
!= END_OF_INSN
3129 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3130 && current_templates
3131 && current_templates
->start
->opcode_modifier
.isprefix
)
3133 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3135 as_bad ((flag_code
!= CODE_64BIT
3136 ? _("`%s' is only supported in 64-bit mode")
3137 : _("`%s' is not supported in 64-bit mode")),
3138 current_templates
->start
->name
);
3141 /* If we are in 16-bit mode, do not allow addr16 or data16.
3142 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3143 if ((current_templates
->start
->opcode_modifier
.size16
3144 || current_templates
->start
->opcode_modifier
.size32
)
3145 && flag_code
!= CODE_64BIT
3146 && (current_templates
->start
->opcode_modifier
.size32
3147 ^ (flag_code
== CODE_16BIT
)))
3149 as_bad (_("redundant %s prefix"),
3150 current_templates
->start
->name
);
3153 /* Add prefix, checking for repeated prefixes. */
3154 switch (add_prefix (current_templates
->start
->base_opcode
))
3159 expecting_string_instruction
= current_templates
->start
->name
;
3164 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3171 if (!current_templates
)
3173 /* Check if we should swap operand in encoding. */
3174 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3180 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3183 if (!current_templates
)
3186 /* See if we can get a match by trimming off a suffix. */
3189 case WORD_MNEM_SUFFIX
:
3190 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3191 i
.suffix
= SHORT_MNEM_SUFFIX
;
3193 case BYTE_MNEM_SUFFIX
:
3194 case QWORD_MNEM_SUFFIX
:
3195 i
.suffix
= mnem_p
[-1];
3197 current_templates
= (const templates
*) hash_find (op_hash
,
3200 case SHORT_MNEM_SUFFIX
:
3201 case LONG_MNEM_SUFFIX
:
3204 i
.suffix
= mnem_p
[-1];
3206 current_templates
= (const templates
*) hash_find (op_hash
,
3215 if (intel_float_operand (mnemonic
) == 1)
3216 i
.suffix
= SHORT_MNEM_SUFFIX
;
3218 i
.suffix
= LONG_MNEM_SUFFIX
;
3220 current_templates
= (const templates
*) hash_find (op_hash
,
3225 if (!current_templates
)
3227 as_bad (_("no such instruction: `%s'"), token_start
);
3232 if (current_templates
->start
->opcode_modifier
.jump
3233 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3235 /* Check for a branch hint. We allow ",pt" and ",pn" for
3236 predict taken and predict not taken respectively.
3237 I'm not sure that branch hints actually do anything on loop
3238 and jcxz insns (JumpByte) for current Pentium4 chips. They
3239 may work in the future and it doesn't hurt to accept them
3241 if (l
[0] == ',' && l
[1] == 'p')
3245 if (!add_prefix (DS_PREFIX_OPCODE
))
3249 else if (l
[2] == 'n')
3251 if (!add_prefix (CS_PREFIX_OPCODE
))
3257 /* Any other comma loses. */
3260 as_bad (_("invalid character %s in mnemonic"),
3261 output_invalid (*l
));
3265 /* Check if instruction is supported on specified architecture. */
3267 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3269 supported
|= cpu_flags_match (t
);
3270 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3274 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3276 as_bad (flag_code
== CODE_64BIT
3277 ? _("`%s' is not supported in 64-bit mode")
3278 : _("`%s' is only supported in 64-bit mode"),
3279 current_templates
->start
->name
);
3282 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3284 as_bad (_("`%s' is not supported on `%s%s'"),
3285 current_templates
->start
->name
,
3286 cpu_arch_name
? cpu_arch_name
: default_arch
,
3287 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3292 if (!cpu_arch_flags
.bitfield
.cpui386
3293 && (flag_code
!= CODE_16BIT
))
3295 as_warn (_("use .code16 to ensure correct addressing mode"));
3298 /* Check for rep/repne without a string instruction. */
3299 if (expecting_string_instruction
)
3301 static templates override
;
3303 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3304 if (t
->opcode_modifier
.isstring
)
3306 if (t
>= current_templates
->end
)
3308 as_bad (_("expecting string instruction after `%s'"),
3309 expecting_string_instruction
);
3312 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3313 if (!t
->opcode_modifier
.isstring
)
3316 current_templates
= &override
;
3323 parse_operands (char *l
, const char *mnemonic
)
3327 /* 1 if operand is pending after ','. */
3328 unsigned int expecting_operand
= 0;
3330 /* Non-zero if operand parens not balanced. */
3331 unsigned int paren_not_balanced
;
3333 while (*l
!= END_OF_INSN
)
3335 /* Skip optional white space before operand. */
3336 if (is_space_char (*l
))
3338 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3340 as_bad (_("invalid character %s before operand %d"),
3341 output_invalid (*l
),
3345 token_start
= l
; /* after white space */
3346 paren_not_balanced
= 0;
3347 while (paren_not_balanced
|| *l
!= ',')
3349 if (*l
== END_OF_INSN
)
3351 if (paren_not_balanced
)
3354 as_bad (_("unbalanced parenthesis in operand %d."),
3357 as_bad (_("unbalanced brackets in operand %d."),
3362 break; /* we are done */
3364 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3366 as_bad (_("invalid character %s in operand %d"),
3367 output_invalid (*l
),
3374 ++paren_not_balanced
;
3376 --paren_not_balanced
;
3381 ++paren_not_balanced
;
3383 --paren_not_balanced
;
3387 if (l
!= token_start
)
3388 { /* Yes, we've read in another operand. */
3389 unsigned int operand_ok
;
3390 this_operand
= i
.operands
++;
3391 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3392 if (i
.operands
> MAX_OPERANDS
)
3394 as_bad (_("spurious operands; (%d operands/instruction max)"),
3398 /* Now parse operand adding info to 'i' as we go along. */
3399 END_STRING_AND_SAVE (l
);
3403 i386_intel_operand (token_start
,
3404 intel_float_operand (mnemonic
));
3406 operand_ok
= i386_att_operand (token_start
);
3408 RESTORE_END_STRING (l
);
3414 if (expecting_operand
)
3416 expecting_operand_after_comma
:
3417 as_bad (_("expecting operand after ','; got nothing"));
3422 as_bad (_("expecting operand before ','; got nothing"));
3427 /* Now *l must be either ',' or END_OF_INSN. */
3430 if (*++l
== END_OF_INSN
)
3432 /* Just skip it, if it's \n complain. */
3433 goto expecting_operand_after_comma
;
3435 expecting_operand
= 1;
3442 swap_2_operands (int xchg1
, int xchg2
)
3444 union i386_op temp_op
;
3445 i386_operand_type temp_type
;
3446 enum bfd_reloc_code_real temp_reloc
;
3448 temp_type
= i
.types
[xchg2
];
3449 i
.types
[xchg2
] = i
.types
[xchg1
];
3450 i
.types
[xchg1
] = temp_type
;
3451 temp_op
= i
.op
[xchg2
];
3452 i
.op
[xchg2
] = i
.op
[xchg1
];
3453 i
.op
[xchg1
] = temp_op
;
3454 temp_reloc
= i
.reloc
[xchg2
];
3455 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3456 i
.reloc
[xchg1
] = temp_reloc
;
3460 swap_operands (void)
3466 swap_2_operands (1, i
.operands
- 2);
3469 swap_2_operands (0, i
.operands
- 1);
3475 if (i
.mem_operands
== 2)
3477 const seg_entry
*temp_seg
;
3478 temp_seg
= i
.seg
[0];
3479 i
.seg
[0] = i
.seg
[1];
3480 i
.seg
[1] = temp_seg
;
3484 /* Try to ensure constant immediates are represented in the smallest
3489 char guess_suffix
= 0;
3493 guess_suffix
= i
.suffix
;
3494 else if (i
.reg_operands
)
3496 /* Figure out a suffix from the last register operand specified.
3497 We can't do this properly yet, ie. excluding InOutPortReg,
3498 but the following works for instructions with immediates.
3499 In any case, we can't set i.suffix yet. */
3500 for (op
= i
.operands
; --op
>= 0;)
3501 if (i
.types
[op
].bitfield
.reg8
)
3503 guess_suffix
= BYTE_MNEM_SUFFIX
;
3506 else if (i
.types
[op
].bitfield
.reg16
)
3508 guess_suffix
= WORD_MNEM_SUFFIX
;
3511 else if (i
.types
[op
].bitfield
.reg32
)
3513 guess_suffix
= LONG_MNEM_SUFFIX
;
3516 else if (i
.types
[op
].bitfield
.reg64
)
3518 guess_suffix
= QWORD_MNEM_SUFFIX
;
3522 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3523 guess_suffix
= WORD_MNEM_SUFFIX
;
3525 for (op
= i
.operands
; --op
>= 0;)
3526 if (operand_type_check (i
.types
[op
], imm
))
3528 switch (i
.op
[op
].imms
->X_op
)
3531 /* If a suffix is given, this operand may be shortened. */
3532 switch (guess_suffix
)
3534 case LONG_MNEM_SUFFIX
:
3535 i
.types
[op
].bitfield
.imm32
= 1;
3536 i
.types
[op
].bitfield
.imm64
= 1;
3538 case WORD_MNEM_SUFFIX
:
3539 i
.types
[op
].bitfield
.imm16
= 1;
3540 i
.types
[op
].bitfield
.imm32
= 1;
3541 i
.types
[op
].bitfield
.imm32s
= 1;
3542 i
.types
[op
].bitfield
.imm64
= 1;
3544 case BYTE_MNEM_SUFFIX
:
3545 i
.types
[op
].bitfield
.imm8
= 1;
3546 i
.types
[op
].bitfield
.imm8s
= 1;
3547 i
.types
[op
].bitfield
.imm16
= 1;
3548 i
.types
[op
].bitfield
.imm32
= 1;
3549 i
.types
[op
].bitfield
.imm32s
= 1;
3550 i
.types
[op
].bitfield
.imm64
= 1;
3554 /* If this operand is at most 16 bits, convert it
3555 to a signed 16 bit number before trying to see
3556 whether it will fit in an even smaller size.
3557 This allows a 16-bit operand such as $0xffe0 to
3558 be recognised as within Imm8S range. */
3559 if ((i
.types
[op
].bitfield
.imm16
)
3560 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3562 i
.op
[op
].imms
->X_add_number
=
3563 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3565 if ((i
.types
[op
].bitfield
.imm32
)
3566 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3569 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3570 ^ ((offsetT
) 1 << 31))
3571 - ((offsetT
) 1 << 31));
3574 = operand_type_or (i
.types
[op
],
3575 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3577 /* We must avoid matching of Imm32 templates when 64bit
3578 only immediate is available. */
3579 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3580 i
.types
[op
].bitfield
.imm32
= 0;
3587 /* Symbols and expressions. */
3589 /* Convert symbolic operand to proper sizes for matching, but don't
3590 prevent matching a set of insns that only supports sizes other
3591 than those matching the insn suffix. */
3593 i386_operand_type mask
, allowed
;
3594 const insn_template
*t
;
3596 operand_type_set (&mask
, 0);
3597 operand_type_set (&allowed
, 0);
3599 for (t
= current_templates
->start
;
3600 t
< current_templates
->end
;
3602 allowed
= operand_type_or (allowed
,
3603 t
->operand_types
[op
]);
3604 switch (guess_suffix
)
3606 case QWORD_MNEM_SUFFIX
:
3607 mask
.bitfield
.imm64
= 1;
3608 mask
.bitfield
.imm32s
= 1;
3610 case LONG_MNEM_SUFFIX
:
3611 mask
.bitfield
.imm32
= 1;
3613 case WORD_MNEM_SUFFIX
:
3614 mask
.bitfield
.imm16
= 1;
3616 case BYTE_MNEM_SUFFIX
:
3617 mask
.bitfield
.imm8
= 1;
3622 allowed
= operand_type_and (mask
, allowed
);
3623 if (!operand_type_all_zero (&allowed
))
3624 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3631 /* Try to use the smallest displacement type too. */
3633 optimize_disp (void)
3637 for (op
= i
.operands
; --op
>= 0;)
3638 if (operand_type_check (i
.types
[op
], disp
))
3640 if (i
.op
[op
].disps
->X_op
== O_constant
)
3642 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3644 if (i
.types
[op
].bitfield
.disp16
3645 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3647 /* If this operand is at most 16 bits, convert
3648 to a signed 16 bit number and don't use 64bit
3650 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3651 i
.types
[op
].bitfield
.disp64
= 0;
3653 if (i
.types
[op
].bitfield
.disp32
3654 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3656 /* If this operand is at most 32 bits, convert
3657 to a signed 32 bit number and don't use 64bit
3659 op_disp
&= (((offsetT
) 2 << 31) - 1);
3660 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3661 i
.types
[op
].bitfield
.disp64
= 0;
3663 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3665 i
.types
[op
].bitfield
.disp8
= 0;
3666 i
.types
[op
].bitfield
.disp16
= 0;
3667 i
.types
[op
].bitfield
.disp32
= 0;
3668 i
.types
[op
].bitfield
.disp32s
= 0;
3669 i
.types
[op
].bitfield
.disp64
= 0;
3673 else if (flag_code
== CODE_64BIT
)
3675 if (fits_in_signed_long (op_disp
))
3677 i
.types
[op
].bitfield
.disp64
= 0;
3678 i
.types
[op
].bitfield
.disp32s
= 1;
3680 if (i
.prefix
[ADDR_PREFIX
]
3681 && fits_in_unsigned_long (op_disp
))
3682 i
.types
[op
].bitfield
.disp32
= 1;
3684 if ((i
.types
[op
].bitfield
.disp32
3685 || i
.types
[op
].bitfield
.disp32s
3686 || i
.types
[op
].bitfield
.disp16
)
3687 && fits_in_signed_byte (op_disp
))
3688 i
.types
[op
].bitfield
.disp8
= 1;
3690 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3691 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3693 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3694 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3695 i
.types
[op
].bitfield
.disp8
= 0;
3696 i
.types
[op
].bitfield
.disp16
= 0;
3697 i
.types
[op
].bitfield
.disp32
= 0;
3698 i
.types
[op
].bitfield
.disp32s
= 0;
3699 i
.types
[op
].bitfield
.disp64
= 0;
3702 /* We only support 64bit displacement on constants. */
3703 i
.types
[op
].bitfield
.disp64
= 0;
3707 static const insn_template
*
3708 match_template (void)
3710 /* Points to template once we've found it. */
3711 const insn_template
*t
;
3712 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3713 i386_operand_type overlap4
;
3714 unsigned int found_reverse_match
;
3715 i386_opcode_modifier suffix_check
;
3716 i386_operand_type operand_types
[MAX_OPERANDS
];
3717 int addr_prefix_disp
;
3719 unsigned int found_cpu_match
;
3720 unsigned int check_register
;
3722 #if MAX_OPERANDS != 5
3723 # error "MAX_OPERANDS must be 5."
3726 found_reverse_match
= 0;
3727 addr_prefix_disp
= -1;
3729 memset (&suffix_check
, 0, sizeof (suffix_check
));
3730 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3731 suffix_check
.no_bsuf
= 1;
3732 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3733 suffix_check
.no_wsuf
= 1;
3734 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3735 suffix_check
.no_ssuf
= 1;
3736 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3737 suffix_check
.no_lsuf
= 1;
3738 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3739 suffix_check
.no_qsuf
= 1;
3740 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3741 suffix_check
.no_ldsuf
= 1;
3743 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3745 addr_prefix_disp
= -1;
3747 /* Must have right number of operands. */
3748 if (i
.operands
!= t
->operands
)
3751 /* Check processor support. */
3752 found_cpu_match
= (cpu_flags_match (t
)
3753 == CPU_FLAGS_PERFECT_MATCH
);
3754 if (!found_cpu_match
)
3757 /* Check old gcc support. */
3758 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3761 /* Check AT&T mnemonic. */
3762 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3765 /* Check AT&T syntax Intel syntax. */
3766 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3767 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3770 /* Check the suffix, except for some instructions in intel mode. */
3771 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3772 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3773 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3774 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3775 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3776 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3777 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3780 if (!operand_size_match (t
))
3783 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3784 operand_types
[j
] = t
->operand_types
[j
];
3786 /* In general, don't allow 64-bit operands in 32-bit mode. */
3787 if (i
.suffix
== QWORD_MNEM_SUFFIX
3788 && flag_code
!= CODE_64BIT
3790 ? (!t
->opcode_modifier
.ignoresize
3791 && !intel_float_operand (t
->name
))
3792 : intel_float_operand (t
->name
) != 2)
3793 && ((!operand_types
[0].bitfield
.regmmx
3794 && !operand_types
[0].bitfield
.regxmm
3795 && !operand_types
[0].bitfield
.regymm
)
3796 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3797 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3798 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3799 && (t
->base_opcode
!= 0x0fc7
3800 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3803 /* In general, don't allow 32-bit operands on pre-386. */
3804 else if (i
.suffix
== LONG_MNEM_SUFFIX
3805 && !cpu_arch_flags
.bitfield
.cpui386
3807 ? (!t
->opcode_modifier
.ignoresize
3808 && !intel_float_operand (t
->name
))
3809 : intel_float_operand (t
->name
) != 2)
3810 && ((!operand_types
[0].bitfield
.regmmx
3811 && !operand_types
[0].bitfield
.regxmm
)
3812 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3813 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3816 /* Do not verify operands when there are none. */
3820 /* We've found a match; break out of loop. */
3824 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3825 into Disp32/Disp16/Disp32 operand. */
3826 if (i
.prefix
[ADDR_PREFIX
] != 0)
3828 /* There should be only one Disp operand. */
3832 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3834 if (operand_types
[j
].bitfield
.disp16
)
3836 addr_prefix_disp
= j
;
3837 operand_types
[j
].bitfield
.disp32
= 1;
3838 operand_types
[j
].bitfield
.disp16
= 0;
3844 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3846 if (operand_types
[j
].bitfield
.disp32
)
3848 addr_prefix_disp
= j
;
3849 operand_types
[j
].bitfield
.disp32
= 0;
3850 operand_types
[j
].bitfield
.disp16
= 1;
3856 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3858 if (operand_types
[j
].bitfield
.disp64
)
3860 addr_prefix_disp
= j
;
3861 operand_types
[j
].bitfield
.disp64
= 0;
3862 operand_types
[j
].bitfield
.disp32
= 1;
3870 /* We check register size only if size of operands can be
3871 encoded the canonical way. */
3872 check_register
= t
->opcode_modifier
.w
;
3873 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3874 switch (t
->operands
)
3877 if (!operand_type_match (overlap0
, i
.types
[0]))
3881 /* xchg %eax, %eax is a special case. It is an aliase for nop
3882 only in 32bit mode and we can use opcode 0x90. In 64bit
3883 mode, we can't use 0x90 for xchg %eax, %eax since it should
3884 zero-extend %eax to %rax. */
3885 if (flag_code
== CODE_64BIT
3886 && t
->base_opcode
== 0x90
3887 && operand_type_equal (&i
.types
[0], &acc32
)
3888 && operand_type_equal (&i
.types
[1], &acc32
))
3892 /* If we swap operand in encoding, we either match
3893 the next one or reverse direction of operands. */
3894 if (t
->opcode_modifier
.s
)
3896 else if (t
->opcode_modifier
.d
)
3901 /* If we swap operand in encoding, we match the next one. */
3902 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3906 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3907 if (!operand_type_match (overlap0
, i
.types
[0])
3908 || !operand_type_match (overlap1
, i
.types
[1])
3910 && !operand_type_register_match (overlap0
, i
.types
[0],
3912 overlap1
, i
.types
[1],
3915 /* Check if other direction is valid ... */
3916 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3920 /* Try reversing direction of operands. */
3921 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3922 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3923 if (!operand_type_match (overlap0
, i
.types
[0])
3924 || !operand_type_match (overlap1
, i
.types
[1])
3926 && !operand_type_register_match (overlap0
,
3933 /* Does not match either direction. */
3936 /* found_reverse_match holds which of D or FloatDR
3938 if (t
->opcode_modifier
.d
)
3939 found_reverse_match
= Opcode_D
;
3940 else if (t
->opcode_modifier
.floatd
)
3941 found_reverse_match
= Opcode_FloatD
;
3943 found_reverse_match
= 0;
3944 if (t
->opcode_modifier
.floatr
)
3945 found_reverse_match
|= Opcode_FloatR
;
3949 /* Found a forward 2 operand match here. */
3950 switch (t
->operands
)
3953 overlap4
= operand_type_and (i
.types
[4],
3956 overlap3
= operand_type_and (i
.types
[3],
3959 overlap2
= operand_type_and (i
.types
[2],
3964 switch (t
->operands
)
3967 if (!operand_type_match (overlap4
, i
.types
[4])
3968 || !operand_type_register_match (overlap3
,
3976 if (!operand_type_match (overlap3
, i
.types
[3])
3978 && !operand_type_register_match (overlap2
,
3986 /* Here we make use of the fact that there are no
3987 reverse match 3 operand instructions, and all 3
3988 operand instructions only need to be checked for
3989 register consistency between operands 2 and 3. */
3990 if (!operand_type_match (overlap2
, i
.types
[2])
3992 && !operand_type_register_match (overlap1
,
4002 /* Found either forward/reverse 2, 3 or 4 operand match here:
4003 slip through to break. */
4005 if (!found_cpu_match
)
4007 found_reverse_match
= 0;
4011 /* We've found a match; break out of loop. */
4015 if (t
== current_templates
->end
)
4017 /* We found no match. */
4019 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4020 current_templates
->start
->name
);
4022 as_bad (_("suffix or operands invalid for `%s'"),
4023 current_templates
->start
->name
);
4027 if (!quiet_warnings
)
4030 && (i
.types
[0].bitfield
.jumpabsolute
4031 != operand_types
[0].bitfield
.jumpabsolute
))
4033 as_warn (_("indirect %s without `*'"), t
->name
);
4036 if (t
->opcode_modifier
.isprefix
4037 && t
->opcode_modifier
.ignoresize
)
4039 /* Warn them that a data or address size prefix doesn't
4040 affect assembly of the next line of code. */
4041 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4045 /* Copy the template we found. */
4048 if (addr_prefix_disp
!= -1)
4049 i
.tm
.operand_types
[addr_prefix_disp
]
4050 = operand_types
[addr_prefix_disp
];
4052 if (found_reverse_match
)
4054 /* If we found a reverse match we must alter the opcode
4055 direction bit. found_reverse_match holds bits to change
4056 (different for int & float insns). */
4058 i
.tm
.base_opcode
^= found_reverse_match
;
4060 i
.tm
.operand_types
[0] = operand_types
[1];
4061 i
.tm
.operand_types
[1] = operand_types
[0];
4070 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4071 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4073 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4075 as_bad (_("`%s' operand %d must use `%ses' segment"),
4081 /* There's only ever one segment override allowed per instruction.
4082 This instruction possibly has a legal segment override on the
4083 second operand, so copy the segment to where non-string
4084 instructions store it, allowing common code. */
4085 i
.seg
[0] = i
.seg
[1];
4087 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4089 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4091 as_bad (_("`%s' operand %d must use `%ses' segment"),
4102 process_suffix (void)
4104 /* If matched instruction specifies an explicit instruction mnemonic
4106 if (i
.tm
.opcode_modifier
.size16
)
4107 i
.suffix
= WORD_MNEM_SUFFIX
;
4108 else if (i
.tm
.opcode_modifier
.size32
)
4109 i
.suffix
= LONG_MNEM_SUFFIX
;
4110 else if (i
.tm
.opcode_modifier
.size64
)
4111 i
.suffix
= QWORD_MNEM_SUFFIX
;
4112 else if (i
.reg_operands
)
4114 /* If there's no instruction mnemonic suffix we try to invent one
4115 based on register operands. */
4118 /* We take i.suffix from the last register operand specified,
4119 Destination register type is more significant than source
4120 register type. crc32 in SSE4.2 prefers source register
4122 if (i
.tm
.base_opcode
== 0xf20f38f1)
4124 if (i
.types
[0].bitfield
.reg16
)
4125 i
.suffix
= WORD_MNEM_SUFFIX
;
4126 else if (i
.types
[0].bitfield
.reg32
)
4127 i
.suffix
= LONG_MNEM_SUFFIX
;
4128 else if (i
.types
[0].bitfield
.reg64
)
4129 i
.suffix
= QWORD_MNEM_SUFFIX
;
4131 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4133 if (i
.types
[0].bitfield
.reg8
)
4134 i
.suffix
= BYTE_MNEM_SUFFIX
;
4141 if (i
.tm
.base_opcode
== 0xf20f38f1
4142 || i
.tm
.base_opcode
== 0xf20f38f0)
4144 /* We have to know the operand size for crc32. */
4145 as_bad (_("ambiguous memory operand size for `%s`"),
4150 for (op
= i
.operands
; --op
>= 0;)
4151 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4153 if (i
.types
[op
].bitfield
.reg8
)
4155 i
.suffix
= BYTE_MNEM_SUFFIX
;
4158 else if (i
.types
[op
].bitfield
.reg16
)
4160 i
.suffix
= WORD_MNEM_SUFFIX
;
4163 else if (i
.types
[op
].bitfield
.reg32
)
4165 i
.suffix
= LONG_MNEM_SUFFIX
;
4168 else if (i
.types
[op
].bitfield
.reg64
)
4170 i
.suffix
= QWORD_MNEM_SUFFIX
;
4176 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4178 if (!check_byte_reg ())
4181 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4183 if (!check_long_reg ())
4186 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4189 && i
.tm
.opcode_modifier
.ignoresize
4190 && i
.tm
.opcode_modifier
.no_qsuf
)
4192 else if (!check_qword_reg ())
4195 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4197 if (!check_word_reg ())
4200 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4201 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4203 /* Skip if the instruction has x/y suffix. match_template
4204 should check if it is a valid suffix. */
4206 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4207 /* Do nothing if the instruction is going to ignore the prefix. */
4212 else if (i
.tm
.opcode_modifier
.defaultsize
4214 /* exclude fldenv/frstor/fsave/fstenv */
4215 && i
.tm
.opcode_modifier
.no_ssuf
)
4217 i
.suffix
= stackop_size
;
4219 else if (intel_syntax
4221 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4222 || i
.tm
.opcode_modifier
.jumpbyte
4223 || i
.tm
.opcode_modifier
.jumpintersegment
4224 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4225 && i
.tm
.extension_opcode
<= 3)))
4230 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4232 i
.suffix
= QWORD_MNEM_SUFFIX
;
4236 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4237 i
.suffix
= LONG_MNEM_SUFFIX
;
4240 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4241 i
.suffix
= WORD_MNEM_SUFFIX
;
4250 if (i
.tm
.opcode_modifier
.w
)
4252 as_bad (_("no instruction mnemonic suffix given and "
4253 "no register operands; can't size instruction"));
4259 unsigned int suffixes
;
4261 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4262 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4264 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4266 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4268 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4270 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4273 /* There are more than suffix matches. */
4274 if (i
.tm
.opcode_modifier
.w
4275 || ((suffixes
& (suffixes
- 1))
4276 && !i
.tm
.opcode_modifier
.defaultsize
4277 && !i
.tm
.opcode_modifier
.ignoresize
))
4279 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4285 /* Change the opcode based on the operand size given by i.suffix;
4286 We don't need to change things for byte insns. */
4289 && i
.suffix
!= BYTE_MNEM_SUFFIX
4290 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4291 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4293 /* It's not a byte, select word/dword operation. */
4294 if (i
.tm
.opcode_modifier
.w
)
4296 if (i
.tm
.opcode_modifier
.shortform
)
4297 i
.tm
.base_opcode
|= 8;
4299 i
.tm
.base_opcode
|= 1;
4302 /* Now select between word & dword operations via the operand
4303 size prefix, except for instructions that will ignore this
4305 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4307 /* The address size override prefix changes the size of the
4309 if ((flag_code
== CODE_32BIT
4310 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4311 || (flag_code
!= CODE_32BIT
4312 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4313 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4316 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4317 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4318 && !i
.tm
.opcode_modifier
.ignoresize
4319 && !i
.tm
.opcode_modifier
.floatmf
4320 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4321 || (flag_code
== CODE_64BIT
4322 && i
.tm
.opcode_modifier
.jumpbyte
)))
4324 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4326 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4327 prefix
= ADDR_PREFIX_OPCODE
;
4329 if (!add_prefix (prefix
))
4333 /* Set mode64 for an operand. */
4334 if (i
.suffix
== QWORD_MNEM_SUFFIX
4335 && flag_code
== CODE_64BIT
4336 && !i
.tm
.opcode_modifier
.norex64
)
4338 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4339 need rex64. cmpxchg8b is also a special case. */
4340 if (! (i
.operands
== 2
4341 && i
.tm
.base_opcode
== 0x90
4342 && i
.tm
.extension_opcode
== None
4343 && operand_type_equal (&i
.types
[0], &acc64
)
4344 && operand_type_equal (&i
.types
[1], &acc64
))
4345 && ! (i
.operands
== 1
4346 && i
.tm
.base_opcode
== 0xfc7
4347 && i
.tm
.extension_opcode
== 1
4348 && !operand_type_check (i
.types
[0], reg
)
4349 && operand_type_check (i
.types
[0], anymem
)))
4353 /* Size floating point instruction. */
4354 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4355 if (i
.tm
.opcode_modifier
.floatmf
)
4356 i
.tm
.base_opcode
^= 4;
4363 check_byte_reg (void)
4367 for (op
= i
.operands
; --op
>= 0;)
4369 /* If this is an eight bit register, it's OK. If it's the 16 or
4370 32 bit version of an eight bit register, we will just use the
4371 low portion, and that's OK too. */
4372 if (i
.types
[op
].bitfield
.reg8
)
4375 /* Don't generate this warning if not needed. */
4376 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4379 /* crc32 doesn't generate this warning. */
4380 if (i
.tm
.base_opcode
== 0xf20f38f0)
4383 if ((i
.types
[op
].bitfield
.reg16
4384 || i
.types
[op
].bitfield
.reg32
4385 || i
.types
[op
].bitfield
.reg64
)
4386 && i
.op
[op
].regs
->reg_num
< 4)
4388 /* Prohibit these changes in the 64bit mode, since the
4389 lowering is more complicated. */
4390 if (flag_code
== CODE_64BIT
4391 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4393 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4394 register_prefix
, i
.op
[op
].regs
->reg_name
,
4398 #if REGISTER_WARNINGS
4400 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4401 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4403 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4404 ? REGNAM_AL
- REGNAM_AX
4405 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4407 i
.op
[op
].regs
->reg_name
,
4412 /* Any other register is bad. */
4413 if (i
.types
[op
].bitfield
.reg16
4414 || i
.types
[op
].bitfield
.reg32
4415 || i
.types
[op
].bitfield
.reg64
4416 || i
.types
[op
].bitfield
.regmmx
4417 || i
.types
[op
].bitfield
.regxmm
4418 || i
.types
[op
].bitfield
.regymm
4419 || i
.types
[op
].bitfield
.sreg2
4420 || i
.types
[op
].bitfield
.sreg3
4421 || i
.types
[op
].bitfield
.control
4422 || i
.types
[op
].bitfield
.debug
4423 || i
.types
[op
].bitfield
.test
4424 || i
.types
[op
].bitfield
.floatreg
4425 || i
.types
[op
].bitfield
.floatacc
)
4427 as_bad (_("`%s%s' not allowed with `%s%c'"),
4429 i
.op
[op
].regs
->reg_name
,
4439 check_long_reg (void)
4443 for (op
= i
.operands
; --op
>= 0;)
4444 /* Reject eight bit registers, except where the template requires
4445 them. (eg. movzb) */
4446 if (i
.types
[op
].bitfield
.reg8
4447 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4448 || i
.tm
.operand_types
[op
].bitfield
.reg32
4449 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4451 as_bad (_("`%s%s' not allowed with `%s%c'"),
4453 i
.op
[op
].regs
->reg_name
,
4458 /* Warn if the e prefix on a general reg is missing. */
4459 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4460 && i
.types
[op
].bitfield
.reg16
4461 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4462 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4464 /* Prohibit these changes in the 64bit mode, since the
4465 lowering is more complicated. */
4466 if (flag_code
== CODE_64BIT
)
4468 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4469 register_prefix
, i
.op
[op
].regs
->reg_name
,
4473 #if REGISTER_WARNINGS
4475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4477 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4479 i
.op
[op
].regs
->reg_name
,
4483 /* Warn if the r prefix on a general reg is missing. */
4484 else if (i
.types
[op
].bitfield
.reg64
4485 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4486 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4489 && i
.tm
.opcode_modifier
.toqword
4490 && !i
.types
[0].bitfield
.regxmm
)
4492 /* Convert to QWORD. We want REX byte. */
4493 i
.suffix
= QWORD_MNEM_SUFFIX
;
4497 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4498 register_prefix
, i
.op
[op
].regs
->reg_name
,
4507 check_qword_reg (void)
4511 for (op
= i
.operands
; --op
>= 0; )
4512 /* Reject eight bit registers, except where the template requires
4513 them. (eg. movzb) */
4514 if (i
.types
[op
].bitfield
.reg8
4515 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4516 || i
.tm
.operand_types
[op
].bitfield
.reg32
4517 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4519 as_bad (_("`%s%s' not allowed with `%s%c'"),
4521 i
.op
[op
].regs
->reg_name
,
4526 /* Warn if the e prefix on a general reg is missing. */
4527 else if ((i
.types
[op
].bitfield
.reg16
4528 || i
.types
[op
].bitfield
.reg32
)
4529 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4530 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4532 /* Prohibit these changes in the 64bit mode, since the
4533 lowering is more complicated. */
4535 && i
.tm
.opcode_modifier
.todword
4536 && !i
.types
[0].bitfield
.regxmm
)
4538 /* Convert to DWORD. We don't want REX byte. */
4539 i
.suffix
= LONG_MNEM_SUFFIX
;
4543 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4544 register_prefix
, i
.op
[op
].regs
->reg_name
,
4553 check_word_reg (void)
4556 for (op
= i
.operands
; --op
>= 0;)
4557 /* Reject eight bit registers, except where the template requires
4558 them. (eg. movzb) */
4559 if (i
.types
[op
].bitfield
.reg8
4560 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4561 || i
.tm
.operand_types
[op
].bitfield
.reg32
4562 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4564 as_bad (_("`%s%s' not allowed with `%s%c'"),
4566 i
.op
[op
].regs
->reg_name
,
4571 /* Warn if the e prefix on a general reg is present. */
4572 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4573 && i
.types
[op
].bitfield
.reg32
4574 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4575 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4577 /* Prohibit these changes in the 64bit mode, since the
4578 lowering is more complicated. */
4579 if (flag_code
== CODE_64BIT
)
4581 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4582 register_prefix
, i
.op
[op
].regs
->reg_name
,
4587 #if REGISTER_WARNINGS
4588 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4590 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4592 i
.op
[op
].regs
->reg_name
,
4600 update_imm (unsigned int j
)
4602 i386_operand_type overlap
= i
.types
[j
];
4603 if ((overlap
.bitfield
.imm8
4604 || overlap
.bitfield
.imm8s
4605 || overlap
.bitfield
.imm16
4606 || overlap
.bitfield
.imm32
4607 || overlap
.bitfield
.imm32s
4608 || overlap
.bitfield
.imm64
)
4609 && !operand_type_equal (&overlap
, &imm8
)
4610 && !operand_type_equal (&overlap
, &imm8s
)
4611 && !operand_type_equal (&overlap
, &imm16
)
4612 && !operand_type_equal (&overlap
, &imm32
)
4613 && !operand_type_equal (&overlap
, &imm32s
)
4614 && !operand_type_equal (&overlap
, &imm64
))
4618 i386_operand_type temp
;
4620 operand_type_set (&temp
, 0);
4621 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4623 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4624 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4626 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4627 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4628 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4630 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4631 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4634 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4637 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4638 || operand_type_equal (&overlap
, &imm16_32
)
4639 || operand_type_equal (&overlap
, &imm16_32s
))
4641 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4646 if (!operand_type_equal (&overlap
, &imm8
)
4647 && !operand_type_equal (&overlap
, &imm8s
)
4648 && !operand_type_equal (&overlap
, &imm16
)
4649 && !operand_type_equal (&overlap
, &imm32
)
4650 && !operand_type_equal (&overlap
, &imm32s
)
4651 && !operand_type_equal (&overlap
, &imm64
))
4653 as_bad (_("no instruction mnemonic suffix given; "
4654 "can't determine immediate size"));
4658 i
.types
[j
] = overlap
;
4668 /* Update the first 2 immediate operands. */
4669 n
= i
.operands
> 2 ? 2 : i
.operands
;
4672 for (j
= 0; j
< n
; j
++)
4673 if (update_imm (j
) == 0)
4676 /* The 3rd operand can't be immediate operand. */
4677 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4684 bad_implicit_operand (int xmm
)
4686 const char *ireg
= xmm
? "xmm0" : "ymm0";
4689 as_bad (_("the last operand of `%s' must be `%s%s'"),
4690 i
.tm
.name
, register_prefix
, ireg
);
4692 as_bad (_("the first operand of `%s' must be `%s%s'"),
4693 i
.tm
.name
, register_prefix
, ireg
);
4698 process_operands (void)
4700 /* Default segment register this instruction will use for memory
4701 accesses. 0 means unknown. This is only for optimizing out
4702 unnecessary segment overrides. */
4703 const seg_entry
*default_seg
= 0;
4705 if (i
.tm
.opcode_modifier
.sse2avx
4706 && (i
.tm
.opcode_modifier
.vexnds
4707 || i
.tm
.opcode_modifier
.vexndd
))
4709 unsigned int dupl
= i
.operands
;
4710 unsigned int dest
= dupl
- 1;
4713 /* The destination must be an xmm register. */
4714 gas_assert (i
.reg_operands
4715 && MAX_OPERANDS
> dupl
4716 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4718 if (i
.tm
.opcode_modifier
.firstxmm0
)
4720 /* The first operand is implicit and must be xmm0. */
4721 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4722 if (i
.op
[0].regs
->reg_num
!= 0)
4723 return bad_implicit_operand (1);
4725 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4727 /* Keep xmm0 for instructions with VEX prefix and 3
4733 /* We remove the first xmm0 and keep the number of
4734 operands unchanged, which in fact duplicates the
4736 for (j
= 1; j
< i
.operands
; j
++)
4738 i
.op
[j
- 1] = i
.op
[j
];
4739 i
.types
[j
- 1] = i
.types
[j
];
4740 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4744 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4746 gas_assert ((MAX_OPERANDS
- 1) > dupl
4747 && (i
.tm
.opcode_modifier
.vexsources
4750 /* Add the implicit xmm0 for instructions with VEX prefix
4752 for (j
= i
.operands
; j
> 0; j
--)
4754 i
.op
[j
] = i
.op
[j
- 1];
4755 i
.types
[j
] = i
.types
[j
- 1];
4756 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4759 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4760 i
.types
[0] = regxmm
;
4761 i
.tm
.operand_types
[0] = regxmm
;
4764 i
.reg_operands
+= 2;
4769 i
.op
[dupl
] = i
.op
[dest
];
4770 i
.types
[dupl
] = i
.types
[dest
];
4771 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4780 i
.op
[dupl
] = i
.op
[dest
];
4781 i
.types
[dupl
] = i
.types
[dest
];
4782 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4785 if (i
.tm
.opcode_modifier
.immext
)
4788 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4792 /* The first operand is implicit and must be xmm0/ymm0. */
4793 gas_assert (i
.reg_operands
4794 && (operand_type_equal (&i
.types
[0], ®xmm
)
4795 || operand_type_equal (&i
.types
[0], ®ymm
)));
4796 if (i
.op
[0].regs
->reg_num
!= 0)
4797 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4799 for (j
= 1; j
< i
.operands
; j
++)
4801 i
.op
[j
- 1] = i
.op
[j
];
4802 i
.types
[j
- 1] = i
.types
[j
];
4804 /* We need to adjust fields in i.tm since they are used by
4805 build_modrm_byte. */
4806 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4813 else if (i
.tm
.opcode_modifier
.regkludge
)
4815 /* The imul $imm, %reg instruction is converted into
4816 imul $imm, %reg, %reg, and the clr %reg instruction
4817 is converted into xor %reg, %reg. */
4819 unsigned int first_reg_op
;
4821 if (operand_type_check (i
.types
[0], reg
))
4825 /* Pretend we saw the extra register operand. */
4826 gas_assert (i
.reg_operands
== 1
4827 && i
.op
[first_reg_op
+ 1].regs
== 0);
4828 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4829 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4834 if (i
.tm
.opcode_modifier
.shortform
)
4836 if (i
.types
[0].bitfield
.sreg2
4837 || i
.types
[0].bitfield
.sreg3
)
4839 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4840 && i
.op
[0].regs
->reg_num
== 1)
4842 as_bad (_("you can't `pop %scs'"), register_prefix
);
4845 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4846 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4851 /* The register or float register operand is in operand
4855 if (i
.types
[0].bitfield
.floatreg
4856 || operand_type_check (i
.types
[0], reg
))
4860 /* Register goes in low 3 bits of opcode. */
4861 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4862 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4864 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4866 /* Warn about some common errors, but press on regardless.
4867 The first case can be generated by gcc (<= 2.8.1). */
4868 if (i
.operands
== 2)
4870 /* Reversed arguments on faddp, fsubp, etc. */
4871 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4872 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4873 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4877 /* Extraneous `l' suffix on fp insn. */
4878 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4879 register_prefix
, i
.op
[0].regs
->reg_name
);
4884 else if (i
.tm
.opcode_modifier
.modrm
)
4886 /* The opcode is completed (modulo i.tm.extension_opcode which
4887 must be put into the modrm byte). Now, we make the modrm and
4888 index base bytes based on all the info we've collected. */
4890 default_seg
= build_modrm_byte ();
4892 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4896 else if (i
.tm
.opcode_modifier
.isstring
)
4898 /* For the string instructions that allow a segment override
4899 on one of their operands, the default segment is ds. */
4903 if (i
.tm
.base_opcode
== 0x8d /* lea */
4906 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4908 /* If a segment was explicitly specified, and the specified segment
4909 is not the default, use an opcode prefix to select it. If we
4910 never figured out what the default segment is, then default_seg
4911 will be zero at this point, and the specified segment prefix will
4913 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4915 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4921 static const seg_entry
*
4922 build_modrm_byte (void)
4924 const seg_entry
*default_seg
= 0;
4925 unsigned int source
, dest
;
4928 /* The first operand of instructions with VEX prefix and 3 sources
4929 must be VEX_Imm4. */
4930 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
4933 unsigned int nds
, reg_slot
;
4936 if (i
.tm
.opcode_modifier
.veximmext
4937 && i
.tm
.opcode_modifier
.immext
)
4939 dest
= i
.operands
- 2;
4940 gas_assert (dest
== 3);
4943 dest
= i
.operands
- 1;
4946 /* This instruction must have 4 register operands
4947 or 3 register operands plus 1 memory operand.
4948 It must have VexNDS and VexImmExt. */
4949 gas_assert ((i
.reg_operands
== 4
4950 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4951 && i
.tm
.opcode_modifier
.vexnds
4952 && i
.tm
.opcode_modifier
.veximmext
4953 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4954 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4956 /* Generate an 8bit immediate operand to encode the register
4958 exp
= &im_expressions
[i
.imm_operands
++];
4959 i
.op
[i
.operands
].imms
= exp
;
4960 i
.types
[i
.operands
] = imm8
;
4962 /* If VexW1 is set, the first operand is the source and
4963 the second operand is encoded in the immediate operand. */
4964 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
4974 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg_slot
], ®xmm
)
4975 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
4977 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4978 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4980 exp
->X_op
= O_constant
;
4982 = ((i
.op
[reg_slot
].regs
->reg_num
4983 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4984 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4989 /* i.reg_operands MUST be the number of real register operands;
4990 implicit registers do not count. If there are 3 register
4991 operands, it must be a instruction with VexNDS. For a
4992 instruction with VexNDD, the destination register is encoded
4993 in VEX prefix. If there are 4 register operands, it must be
4994 a instruction with VEX prefix and 3 sources. */
4995 if (i
.mem_operands
== 0
4996 && ((i
.reg_operands
== 2
4997 && !i
.tm
.opcode_modifier
.vexndd
4998 && !i
.tm
.opcode_modifier
.vexlwp
)
4999 || (i
.reg_operands
== 3
5000 && i
.tm
.opcode_modifier
.vexnds
)
5001 || (i
.reg_operands
== 4 && vex_3_sources
)))
5009 /* When there are 3 operands, one of them may be immediate,
5010 which may be the first or the last operand. Otherwise,
5011 the first operand must be shift count register (cl) or it
5012 is an instruction with VexNDS. */
5013 gas_assert (i
.imm_operands
== 1
5014 || (i
.imm_operands
== 0
5015 && (i
.tm
.opcode_modifier
.vexnds
5016 || i
.types
[0].bitfield
.shiftcount
)));
5017 if (operand_type_check (i
.types
[0], imm
)
5018 || i
.types
[0].bitfield
.shiftcount
)
5024 /* When there are 4 operands, the first two must be 8bit
5025 immediate operands. The source operand will be the 3rd
5028 For instructions with VexNDS, if the first operand
5029 an imm8, the source operand is the 2nd one. If the last
5030 operand is imm8, the source operand is the first one. */
5031 gas_assert ((i
.imm_operands
== 2
5032 && i
.types
[0].bitfield
.imm8
5033 && i
.types
[1].bitfield
.imm8
)
5034 || (i
.tm
.opcode_modifier
.vexnds
5035 && i
.imm_operands
== 1
5036 && (i
.types
[0].bitfield
.imm8
5037 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5038 if (i
.tm
.opcode_modifier
.vexnds
)
5040 if (i
.types
[0].bitfield
.imm8
)
5058 if (i
.tm
.opcode_modifier
.vexnds
)
5060 /* For instructions with VexNDS, the register-only
5061 source operand must be XMM or YMM register. It is
5062 encoded in VEX prefix. We need to clear RegMem bit
5063 before calling operand_type_equal. */
5064 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5065 op
.bitfield
.regmem
= 0;
5066 if ((dest
+ 1) >= i
.operands
5067 || (!operand_type_equal (&op
, ®xmm
)
5068 && !operand_type_equal (&op
, ®ymm
)))
5070 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5076 /* One of the register operands will be encoded in the i.tm.reg
5077 field, the other in the combined i.tm.mode and i.tm.regmem
5078 fields. If no form of this instruction supports a memory
5079 destination operand, then we assume the source operand may
5080 sometimes be a memory operand and so we need to store the
5081 destination in the i.rm.reg field. */
5082 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5083 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5085 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5086 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5087 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5089 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5094 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5095 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5096 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5098 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5101 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5103 if (!i
.types
[0].bitfield
.control
5104 && !i
.types
[1].bitfield
.control
)
5106 i
.rex
&= ~(REX_R
| REX_B
);
5107 add_prefix (LOCK_PREFIX_OPCODE
);
5111 { /* If it's not 2 reg operands... */
5116 unsigned int fake_zero_displacement
= 0;
5119 for (op
= 0; op
< i
.operands
; op
++)
5120 if (operand_type_check (i
.types
[op
], anymem
))
5122 gas_assert (op
< i
.operands
);
5126 if (i
.base_reg
== 0)
5129 if (!i
.disp_operands
)
5130 fake_zero_displacement
= 1;
5131 if (i
.index_reg
== 0)
5133 /* Operand is just <disp> */
5134 if (flag_code
== CODE_64BIT
)
5136 /* 64bit mode overwrites the 32bit absolute
5137 addressing by RIP relative addressing and
5138 absolute addressing is encoded by one of the
5139 redundant SIB forms. */
5140 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5141 i
.sib
.base
= NO_BASE_REGISTER
;
5142 i
.sib
.index
= NO_INDEX_REGISTER
;
5143 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5144 ? disp32s
: disp32
);
5146 else if ((flag_code
== CODE_16BIT
)
5147 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5149 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5150 i
.types
[op
] = disp16
;
5154 i
.rm
.regmem
= NO_BASE_REGISTER
;
5155 i
.types
[op
] = disp32
;
5158 else /* !i.base_reg && i.index_reg */
5160 if (i
.index_reg
->reg_num
== RegEiz
5161 || i
.index_reg
->reg_num
== RegRiz
)
5162 i
.sib
.index
= NO_INDEX_REGISTER
;
5164 i
.sib
.index
= i
.index_reg
->reg_num
;
5165 i
.sib
.base
= NO_BASE_REGISTER
;
5166 i
.sib
.scale
= i
.log2_scale_factor
;
5167 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5168 i
.types
[op
].bitfield
.disp8
= 0;
5169 i
.types
[op
].bitfield
.disp16
= 0;
5170 i
.types
[op
].bitfield
.disp64
= 0;
5171 if (flag_code
!= CODE_64BIT
)
5173 /* Must be 32 bit */
5174 i
.types
[op
].bitfield
.disp32
= 1;
5175 i
.types
[op
].bitfield
.disp32s
= 0;
5179 i
.types
[op
].bitfield
.disp32
= 0;
5180 i
.types
[op
].bitfield
.disp32s
= 1;
5182 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5186 /* RIP addressing for 64bit mode. */
5187 else if (i
.base_reg
->reg_num
== RegRip
||
5188 i
.base_reg
->reg_num
== RegEip
)
5190 i
.rm
.regmem
= NO_BASE_REGISTER
;
5191 i
.types
[op
].bitfield
.disp8
= 0;
5192 i
.types
[op
].bitfield
.disp16
= 0;
5193 i
.types
[op
].bitfield
.disp32
= 0;
5194 i
.types
[op
].bitfield
.disp32s
= 1;
5195 i
.types
[op
].bitfield
.disp64
= 0;
5196 i
.flags
[op
] |= Operand_PCrel
;
5197 if (! i
.disp_operands
)
5198 fake_zero_displacement
= 1;
5200 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5202 switch (i
.base_reg
->reg_num
)
5205 if (i
.index_reg
== 0)
5207 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5208 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5212 if (i
.index_reg
== 0)
5215 if (operand_type_check (i
.types
[op
], disp
) == 0)
5217 /* fake (%bp) into 0(%bp) */
5218 i
.types
[op
].bitfield
.disp8
= 1;
5219 fake_zero_displacement
= 1;
5222 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5223 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5225 default: /* (%si) -> 4 or (%di) -> 5 */
5226 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5228 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5230 else /* i.base_reg and 32/64 bit mode */
5232 if (flag_code
== CODE_64BIT
5233 && operand_type_check (i
.types
[op
], disp
))
5235 i386_operand_type temp
;
5236 operand_type_set (&temp
, 0);
5237 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5239 if (i
.prefix
[ADDR_PREFIX
] == 0)
5240 i
.types
[op
].bitfield
.disp32s
= 1;
5242 i
.types
[op
].bitfield
.disp32
= 1;
5245 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5246 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5248 i
.sib
.base
= i
.base_reg
->reg_num
;
5249 /* x86-64 ignores REX prefix bit here to avoid decoder
5251 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5254 if (i
.disp_operands
== 0)
5256 fake_zero_displacement
= 1;
5257 i
.types
[op
].bitfield
.disp8
= 1;
5260 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5264 i
.sib
.scale
= i
.log2_scale_factor
;
5265 if (i
.index_reg
== 0)
5267 /* <disp>(%esp) becomes two byte modrm with no index
5268 register. We've already stored the code for esp
5269 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5270 Any base register besides %esp will not use the
5271 extra modrm byte. */
5272 i
.sib
.index
= NO_INDEX_REGISTER
;
5276 if (i
.index_reg
->reg_num
== RegEiz
5277 || i
.index_reg
->reg_num
== RegRiz
)
5278 i
.sib
.index
= NO_INDEX_REGISTER
;
5280 i
.sib
.index
= i
.index_reg
->reg_num
;
5281 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5282 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5287 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5288 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5291 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5294 if (fake_zero_displacement
)
5296 /* Fakes a zero displacement assuming that i.types[op]
5297 holds the correct displacement size. */
5300 gas_assert (i
.op
[op
].disps
== 0);
5301 exp
= &disp_expressions
[i
.disp_operands
++];
5302 i
.op
[op
].disps
= exp
;
5303 exp
->X_op
= O_constant
;
5304 exp
->X_add_number
= 0;
5305 exp
->X_add_symbol
= (symbolS
*) 0;
5306 exp
->X_op_symbol
= (symbolS
*) 0;
5314 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5316 if (operand_type_check (i
.types
[0], imm
))
5317 i
.vex
.register_specifier
= NULL
;
5320 /* VEX.vvvv encodes one of the sources when the first
5321 operand is not an immediate. */
5322 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5323 i
.vex
.register_specifier
= i
.op
[0].regs
;
5325 i
.vex
.register_specifier
= i
.op
[1].regs
;
5328 /* Destination is a XMM register encoded in the ModRM.reg
5330 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5331 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5334 /* ModRM.rm and VEX.B encodes the other source. */
5335 if (!i
.mem_operands
)
5339 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5340 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5342 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5344 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5348 else if (i
.tm
.opcode_modifier
.vexlwp
)
5350 i
.vex
.register_specifier
= i
.op
[2].regs
;
5351 if (!i
.mem_operands
)
5354 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5355 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5359 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5360 (if any) based on i.tm.extension_opcode. Again, we must be
5361 careful to make sure that segment/control/debug/test/MMX
5362 registers are coded into the i.rm.reg field. */
5363 else if (i
.reg_operands
)
5366 unsigned int vex_reg
= ~0;
5368 for (op
= 0; op
< i
.operands
; op
++)
5369 if (i
.types
[op
].bitfield
.reg8
5370 || i
.types
[op
].bitfield
.reg16
5371 || i
.types
[op
].bitfield
.reg32
5372 || i
.types
[op
].bitfield
.reg64
5373 || i
.types
[op
].bitfield
.regmmx
5374 || i
.types
[op
].bitfield
.regxmm
5375 || i
.types
[op
].bitfield
.regymm
5376 || i
.types
[op
].bitfield
.sreg2
5377 || i
.types
[op
].bitfield
.sreg3
5378 || i
.types
[op
].bitfield
.control
5379 || i
.types
[op
].bitfield
.debug
5380 || i
.types
[op
].bitfield
.test
)
5385 else if (i
.tm
.opcode_modifier
.vexnds
)
5387 /* For instructions with VexNDS, the register-only
5388 source operand is encoded in VEX prefix. */
5389 gas_assert (mem
!= (unsigned int) ~0);
5394 gas_assert (op
< i
.operands
);
5399 gas_assert (vex_reg
< i
.operands
);
5402 else if (i
.tm
.opcode_modifier
.vexndd
)
5404 /* For instructions with VexNDD, there should be
5405 no memory operand and the register destination
5406 is encoded in VEX prefix. */
5407 gas_assert (i
.mem_operands
== 0
5408 && (op
+ 2) == i
.operands
);
5412 gas_assert (op
< i
.operands
);
5414 if (vex_reg
!= (unsigned int) ~0)
5416 gas_assert (i
.reg_operands
== 2);
5418 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5420 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5424 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5427 /* Don't set OP operand twice. */
5430 /* If there is an extension opcode to put here, the
5431 register number must be put into the regmem field. */
5432 if (i
.tm
.extension_opcode
!= None
)
5434 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5435 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5440 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5441 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5446 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5447 must set it to 3 to indicate this is a register operand
5448 in the regmem field. */
5449 if (!i
.mem_operands
)
5453 /* Fill in i.rm.reg field with extension opcode (if any). */
5454 if (i
.tm
.extension_opcode
!= None
)
5455 i
.rm
.reg
= i
.tm
.extension_opcode
;
5461 output_branch (void)
5466 relax_substateT subtype
;
5471 if (flag_code
== CODE_16BIT
)
5475 if (i
.prefix
[DATA_PREFIX
] != 0)
5481 /* Pentium4 branch hints. */
5482 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5483 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5488 if (i
.prefix
[REX_PREFIX
] != 0)
5494 if (i
.prefixes
!= 0 && !intel_syntax
)
5495 as_warn (_("skipping prefixes on this instruction"));
5497 /* It's always a symbol; End frag & setup for relax.
5498 Make sure there is enough room in this frag for the largest
5499 instruction we may generate in md_convert_frag. This is 2
5500 bytes for the opcode and room for the prefix and largest
5502 frag_grow (prefix
+ 2 + 4);
5503 /* Prefix and 1 opcode byte go in fr_fix. */
5504 p
= frag_more (prefix
+ 1);
5505 if (i
.prefix
[DATA_PREFIX
] != 0)
5506 *p
++ = DATA_PREFIX_OPCODE
;
5507 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5508 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5509 *p
++ = i
.prefix
[SEG_PREFIX
];
5510 if (i
.prefix
[REX_PREFIX
] != 0)
5511 *p
++ = i
.prefix
[REX_PREFIX
];
5512 *p
= i
.tm
.base_opcode
;
5514 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5515 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5516 else if (cpu_arch_flags
.bitfield
.cpui386
)
5517 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5519 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5522 sym
= i
.op
[0].disps
->X_add_symbol
;
5523 off
= i
.op
[0].disps
->X_add_number
;
5525 if (i
.op
[0].disps
->X_op
!= O_constant
5526 && i
.op
[0].disps
->X_op
!= O_symbol
)
5528 /* Handle complex expressions. */
5529 sym
= make_expr_symbol (i
.op
[0].disps
);
5533 /* 1 possible extra opcode + 4 byte displacement go in var part.
5534 Pass reloc in fr_var. */
5535 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5545 if (i
.tm
.opcode_modifier
.jumpbyte
)
5547 /* This is a loop or jecxz type instruction. */
5549 if (i
.prefix
[ADDR_PREFIX
] != 0)
5551 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5554 /* Pentium4 branch hints. */
5555 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5556 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5558 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5567 if (flag_code
== CODE_16BIT
)
5570 if (i
.prefix
[DATA_PREFIX
] != 0)
5572 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5582 if (i
.prefix
[REX_PREFIX
] != 0)
5584 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5588 if (i
.prefixes
!= 0 && !intel_syntax
)
5589 as_warn (_("skipping prefixes on this instruction"));
5591 p
= frag_more (1 + size
);
5592 *p
++ = i
.tm
.base_opcode
;
5594 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5595 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5597 /* All jumps handled here are signed, but don't use a signed limit
5598 check for 32 and 16 bit jumps as we want to allow wrap around at
5599 4G and 64k respectively. */
5601 fixP
->fx_signed
= 1;
5605 output_interseg_jump (void)
5613 if (flag_code
== CODE_16BIT
)
5617 if (i
.prefix
[DATA_PREFIX
] != 0)
5623 if (i
.prefix
[REX_PREFIX
] != 0)
5633 if (i
.prefixes
!= 0 && !intel_syntax
)
5634 as_warn (_("skipping prefixes on this instruction"));
5636 /* 1 opcode; 2 segment; offset */
5637 p
= frag_more (prefix
+ 1 + 2 + size
);
5639 if (i
.prefix
[DATA_PREFIX
] != 0)
5640 *p
++ = DATA_PREFIX_OPCODE
;
5642 if (i
.prefix
[REX_PREFIX
] != 0)
5643 *p
++ = i
.prefix
[REX_PREFIX
];
5645 *p
++ = i
.tm
.base_opcode
;
5646 if (i
.op
[1].imms
->X_op
== O_constant
)
5648 offsetT n
= i
.op
[1].imms
->X_add_number
;
5651 && !fits_in_unsigned_word (n
)
5652 && !fits_in_signed_word (n
))
5654 as_bad (_("16-bit jump out of range"));
5657 md_number_to_chars (p
, n
, size
);
5660 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5661 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5662 if (i
.op
[0].imms
->X_op
!= O_constant
)
5663 as_bad (_("can't handle non absolute segment in `%s'"),
5665 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5671 fragS
*insn_start_frag
;
5672 offsetT insn_start_off
;
5674 /* Tie dwarf2 debug info to the address at the start of the insn.
5675 We can't do this after the insn has been output as the current
5676 frag may have been closed off. eg. by frag_var. */
5677 dwarf2_emit_insn (0);
5679 insn_start_frag
= frag_now
;
5680 insn_start_off
= frag_now_fix ();
5683 if (i
.tm
.opcode_modifier
.jump
)
5685 else if (i
.tm
.opcode_modifier
.jumpbyte
5686 || i
.tm
.opcode_modifier
.jumpdword
)
5688 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5689 output_interseg_jump ();
5692 /* Output normal instructions here. */
5696 unsigned int prefix
;
5698 /* Since the VEX prefix contains the implicit prefix, we don't
5699 need the explicit prefix. */
5700 if (!i
.tm
.opcode_modifier
.vex
)
5702 switch (i
.tm
.opcode_length
)
5705 if (i
.tm
.base_opcode
& 0xff000000)
5707 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5712 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5714 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5715 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5718 if (prefix
!= REPE_PREFIX_OPCODE
5719 || (i
.prefix
[REP_PREFIX
]
5720 != REPE_PREFIX_OPCODE
))
5721 add_prefix (prefix
);
5724 add_prefix (prefix
);
5733 /* The prefix bytes. */
5734 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5736 FRAG_APPEND_1_CHAR (*q
);
5739 if (i
.tm
.opcode_modifier
.vex
)
5741 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5746 /* REX byte is encoded in VEX prefix. */
5750 FRAG_APPEND_1_CHAR (*q
);
5753 /* There should be no other prefixes for instructions
5758 /* Now the VEX prefix. */
5759 p
= frag_more (i
.vex
.length
);
5760 for (j
= 0; j
< i
.vex
.length
; j
++)
5761 p
[j
] = i
.vex
.bytes
[j
];
5764 /* Now the opcode; be careful about word order here! */
5765 if (i
.tm
.opcode_length
== 1)
5767 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5771 switch (i
.tm
.opcode_length
)
5775 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5785 /* Put out high byte first: can't use md_number_to_chars! */
5786 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5787 *p
= i
.tm
.base_opcode
& 0xff;
5790 /* Now the modrm byte and sib byte (if present). */
5791 if (i
.tm
.opcode_modifier
.modrm
)
5793 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5796 /* If i.rm.regmem == ESP (4)
5797 && i.rm.mode != (Register mode)
5799 ==> need second modrm byte. */
5800 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5802 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5803 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5805 | i
.sib
.scale
<< 6));
5808 if (i
.disp_operands
)
5809 output_disp (insn_start_frag
, insn_start_off
);
5812 output_imm (insn_start_frag
, insn_start_off
);
5818 pi ("" /*line*/, &i
);
5820 #endif /* DEBUG386 */
5823 /* Return the size of the displacement operand N. */
5826 disp_size (unsigned int n
)
5829 if (i
.types
[n
].bitfield
.disp64
)
5831 else if (i
.types
[n
].bitfield
.disp8
)
5833 else if (i
.types
[n
].bitfield
.disp16
)
5838 /* Return the size of the immediate operand N. */
5841 imm_size (unsigned int n
)
5844 if (i
.types
[n
].bitfield
.imm64
)
5846 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5848 else if (i
.types
[n
].bitfield
.imm16
)
5854 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5859 for (n
= 0; n
< i
.operands
; n
++)
5861 if (operand_type_check (i
.types
[n
], disp
))
5863 if (i
.op
[n
].disps
->X_op
== O_constant
)
5865 int size
= disp_size (n
);
5868 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5870 p
= frag_more (size
);
5871 md_number_to_chars (p
, val
, size
);
5875 enum bfd_reloc_code_real reloc_type
;
5876 int size
= disp_size (n
);
5877 int sign
= i
.types
[n
].bitfield
.disp32s
;
5878 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5880 /* We can't have 8 bit displacement here. */
5881 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5883 /* The PC relative address is computed relative
5884 to the instruction boundary, so in case immediate
5885 fields follows, we need to adjust the value. */
5886 if (pcrel
&& i
.imm_operands
)
5891 for (n1
= 0; n1
< i
.operands
; n1
++)
5892 if (operand_type_check (i
.types
[n1
], imm
))
5894 /* Only one immediate is allowed for PC
5895 relative address. */
5896 gas_assert (sz
== 0);
5898 i
.op
[n
].disps
->X_add_number
-= sz
;
5900 /* We should find the immediate. */
5901 gas_assert (sz
!= 0);
5904 p
= frag_more (size
);
5905 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5907 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5908 && (((reloc_type
== BFD_RELOC_32
5909 || reloc_type
== BFD_RELOC_X86_64_32S
5910 || (reloc_type
== BFD_RELOC_64
5912 && (i
.op
[n
].disps
->X_op
== O_symbol
5913 || (i
.op
[n
].disps
->X_op
== O_add
5914 && ((symbol_get_value_expression
5915 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5917 || reloc_type
== BFD_RELOC_32_PCREL
))
5921 if (insn_start_frag
== frag_now
)
5922 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5927 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5928 for (fr
= insn_start_frag
->fr_next
;
5929 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5931 add
+= p
- frag_now
->fr_literal
;
5936 reloc_type
= BFD_RELOC_386_GOTPC
;
5937 i
.op
[n
].imms
->X_add_number
+= add
;
5939 else if (reloc_type
== BFD_RELOC_64
)
5940 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5942 /* Don't do the adjustment for x86-64, as there
5943 the pcrel addressing is relative to the _next_
5944 insn, and that is taken care of in other code. */
5945 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5947 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5948 i
.op
[n
].disps
, pcrel
, reloc_type
);
5955 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5960 for (n
= 0; n
< i
.operands
; n
++)
5962 if (operand_type_check (i
.types
[n
], imm
))
5964 if (i
.op
[n
].imms
->X_op
== O_constant
)
5966 int size
= imm_size (n
);
5969 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5971 p
= frag_more (size
);
5972 md_number_to_chars (p
, val
, size
);
5976 /* Not absolute_section.
5977 Need a 32-bit fixup (don't support 8bit
5978 non-absolute imms). Try to support other
5980 enum bfd_reloc_code_real reloc_type
;
5981 int size
= imm_size (n
);
5984 if (i
.types
[n
].bitfield
.imm32s
5985 && (i
.suffix
== QWORD_MNEM_SUFFIX
5986 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5991 p
= frag_more (size
);
5992 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5994 /* This is tough to explain. We end up with this one if we
5995 * have operands that look like
5996 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5997 * obtain the absolute address of the GOT, and it is strongly
5998 * preferable from a performance point of view to avoid using
5999 * a runtime relocation for this. The actual sequence of
6000 * instructions often look something like:
6005 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6007 * The call and pop essentially return the absolute address
6008 * of the label .L66 and store it in %ebx. The linker itself
6009 * will ultimately change the first operand of the addl so
6010 * that %ebx points to the GOT, but to keep things simple, the
6011 * .o file must have this operand set so that it generates not
6012 * the absolute address of .L66, but the absolute address of
6013 * itself. This allows the linker itself simply treat a GOTPC
6014 * relocation as asking for a pcrel offset to the GOT to be
6015 * added in, and the addend of the relocation is stored in the
6016 * operand field for the instruction itself.
6018 * Our job here is to fix the operand so that it would add
6019 * the correct offset so that %ebx would point to itself. The
6020 * thing that is tricky is that .-.L66 will point to the
6021 * beginning of the instruction, so we need to further modify
6022 * the operand so that it will point to itself. There are
6023 * other cases where you have something like:
6025 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6027 * and here no correction would be required. Internally in
6028 * the assembler we treat operands of this form as not being
6029 * pcrel since the '.' is explicitly mentioned, and I wonder
6030 * whether it would simplify matters to do it this way. Who
6031 * knows. In earlier versions of the PIC patches, the
6032 * pcrel_adjust field was used to store the correction, but
6033 * since the expression is not pcrel, I felt it would be
6034 * confusing to do it this way. */
6036 if ((reloc_type
== BFD_RELOC_32
6037 || reloc_type
== BFD_RELOC_X86_64_32S
6038 || reloc_type
== BFD_RELOC_64
)
6040 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6041 && (i
.op
[n
].imms
->X_op
== O_symbol
6042 || (i
.op
[n
].imms
->X_op
== O_add
6043 && ((symbol_get_value_expression
6044 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6049 if (insn_start_frag
== frag_now
)
6050 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6055 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6056 for (fr
= insn_start_frag
->fr_next
;
6057 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6059 add
+= p
- frag_now
->fr_literal
;
6063 reloc_type
= BFD_RELOC_386_GOTPC
;
6065 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6067 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6068 i
.op
[n
].imms
->X_add_number
+= add
;
6070 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6071 i
.op
[n
].imms
, 0, reloc_type
);
6077 /* x86_cons_fix_new is called via the expression parsing code when a
6078 reloc is needed. We use this hook to get the correct .got reloc. */
6079 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6080 static int cons_sign
= -1;
6083 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6086 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6088 got_reloc
= NO_RELOC
;
6091 if (exp
->X_op
== O_secrel
)
6093 exp
->X_op
= O_symbol
;
6094 r
= BFD_RELOC_32_SECREL
;
6098 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6101 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6102 # define lex_got(reloc, adjust, types) NULL
6104 /* Parse operands of the form
6105 <symbol>@GOTOFF+<nnn>
6106 and similar .plt or .got references.
6108 If we find one, set up the correct relocation in RELOC and copy the
6109 input string, minus the `@GOTOFF' into a malloc'd buffer for
6110 parsing by the calling routine. Return this buffer, and if ADJUST
6111 is non-null set it to the length of the string we removed from the
6112 input line. Otherwise return NULL. */
6114 lex_got (enum bfd_reloc_code_real
*rel
,
6116 i386_operand_type
*types
)
6118 /* Some of the relocations depend on the size of what field is to
6119 be relocated. But in our callers i386_immediate and i386_displacement
6120 we don't yet know the operand size (this will be set by insn
6121 matching). Hence we record the word32 relocation here,
6122 and adjust the reloc according to the real size in reloc(). */
6123 static const struct {
6125 const enum bfd_reloc_code_real rel
[2];
6126 const i386_operand_type types64
;
6128 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6129 BFD_RELOC_X86_64_PLTOFF64
},
6130 OPERAND_TYPE_IMM64
},
6131 { "PLT", { BFD_RELOC_386_PLT32
,
6132 BFD_RELOC_X86_64_PLT32
},
6133 OPERAND_TYPE_IMM32_32S_DISP32
},
6134 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6135 BFD_RELOC_X86_64_GOTPLT64
},
6136 OPERAND_TYPE_IMM64_DISP64
},
6137 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6138 BFD_RELOC_X86_64_GOTOFF64
},
6139 OPERAND_TYPE_IMM64_DISP64
},
6140 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6141 BFD_RELOC_X86_64_GOTPCREL
},
6142 OPERAND_TYPE_IMM32_32S_DISP32
},
6143 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6144 BFD_RELOC_X86_64_TLSGD
},
6145 OPERAND_TYPE_IMM32_32S_DISP32
},
6146 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6147 _dummy_first_bfd_reloc_code_real
},
6148 OPERAND_TYPE_NONE
},
6149 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6150 BFD_RELOC_X86_64_TLSLD
},
6151 OPERAND_TYPE_IMM32_32S_DISP32
},
6152 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6153 BFD_RELOC_X86_64_GOTTPOFF
},
6154 OPERAND_TYPE_IMM32_32S_DISP32
},
6155 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6156 BFD_RELOC_X86_64_TPOFF32
},
6157 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6158 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6159 _dummy_first_bfd_reloc_code_real
},
6160 OPERAND_TYPE_NONE
},
6161 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6162 BFD_RELOC_X86_64_DTPOFF32
},
6164 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6165 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6166 _dummy_first_bfd_reloc_code_real
},
6167 OPERAND_TYPE_NONE
},
6168 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6169 _dummy_first_bfd_reloc_code_real
},
6170 OPERAND_TYPE_NONE
},
6171 { "GOT", { BFD_RELOC_386_GOT32
,
6172 BFD_RELOC_X86_64_GOT32
},
6173 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6174 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6175 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6176 OPERAND_TYPE_IMM32_32S_DISP32
},
6177 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6178 BFD_RELOC_X86_64_TLSDESC_CALL
},
6179 OPERAND_TYPE_IMM32_32S_DISP32
},
6187 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6188 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6191 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6195 len
= strlen (gotrel
[j
].str
);
6196 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6198 if (gotrel
[j
].rel
[object_64bit
] != 0)
6201 char *tmpbuf
, *past_reloc
;
6203 *rel
= gotrel
[j
].rel
[object_64bit
];
6209 if (flag_code
!= CODE_64BIT
)
6211 types
->bitfield
.imm32
= 1;
6212 types
->bitfield
.disp32
= 1;
6215 *types
= gotrel
[j
].types64
;
6218 if (GOT_symbol
== NULL
)
6219 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6221 /* The length of the first part of our input line. */
6222 first
= cp
- input_line_pointer
;
6224 /* The second part goes from after the reloc token until
6225 (and including) an end_of_line char or comma. */
6226 past_reloc
= cp
+ 1 + len
;
6228 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6230 second
= cp
+ 1 - past_reloc
;
6232 /* Allocate and copy string. The trailing NUL shouldn't
6233 be necessary, but be safe. */
6234 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6235 memcpy (tmpbuf
, input_line_pointer
, first
);
6236 if (second
!= 0 && *past_reloc
!= ' ')
6237 /* Replace the relocation token with ' ', so that
6238 errors like foo@GOTOFF1 will be detected. */
6239 tmpbuf
[first
++] = ' ';
6240 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6241 tmpbuf
[first
+ second
] = '\0';
6245 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6246 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6251 /* Might be a symbol version string. Don't as_bad here. */
6256 x86_cons (expressionS
*exp
, int size
)
6258 intel_syntax
= -intel_syntax
;
6260 if (size
== 4 || (object_64bit
&& size
== 8))
6262 /* Handle @GOTOFF and the like in an expression. */
6264 char *gotfree_input_line
;
6267 save
= input_line_pointer
;
6268 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6269 if (gotfree_input_line
)
6270 input_line_pointer
= gotfree_input_line
;
6274 if (gotfree_input_line
)
6276 /* expression () has merrily parsed up to the end of line,
6277 or a comma - in the wrong buffer. Transfer how far
6278 input_line_pointer has moved to the right buffer. */
6279 input_line_pointer
= (save
6280 + (input_line_pointer
- gotfree_input_line
)
6282 free (gotfree_input_line
);
6283 if (exp
->X_op
== O_constant
6284 || exp
->X_op
== O_absent
6285 || exp
->X_op
== O_illegal
6286 || exp
->X_op
== O_register
6287 || exp
->X_op
== O_big
)
6289 char c
= *input_line_pointer
;
6290 *input_line_pointer
= 0;
6291 as_bad (_("missing or invalid expression `%s'"), save
);
6292 *input_line_pointer
= c
;
6299 intel_syntax
= -intel_syntax
;
6302 i386_intel_simplify (exp
);
6307 signed_cons (int size
)
6309 if (flag_code
== CODE_64BIT
)
6317 pe_directive_secrel (dummy
)
6318 int dummy ATTRIBUTE_UNUSED
;
6325 if (exp
.X_op
== O_symbol
)
6326 exp
.X_op
= O_secrel
;
6328 emit_expr (&exp
, 4);
6330 while (*input_line_pointer
++ == ',');
6332 input_line_pointer
--;
6333 demand_empty_rest_of_line ();
6338 i386_immediate (char *imm_start
)
6340 char *save_input_line_pointer
;
6341 char *gotfree_input_line
;
6344 i386_operand_type types
;
6346 operand_type_set (&types
, ~0);
6348 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6350 as_bad (_("at most %d immediate operands are allowed"),
6351 MAX_IMMEDIATE_OPERANDS
);
6355 exp
= &im_expressions
[i
.imm_operands
++];
6356 i
.op
[this_operand
].imms
= exp
;
6358 if (is_space_char (*imm_start
))
6361 save_input_line_pointer
= input_line_pointer
;
6362 input_line_pointer
= imm_start
;
6364 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6365 if (gotfree_input_line
)
6366 input_line_pointer
= gotfree_input_line
;
6368 exp_seg
= expression (exp
);
6371 if (*input_line_pointer
)
6372 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6374 input_line_pointer
= save_input_line_pointer
;
6375 if (gotfree_input_line
)
6377 free (gotfree_input_line
);
6379 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6380 exp
->X_op
= O_illegal
;
6383 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6387 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6388 i386_operand_type types
, const char *imm_start
)
6390 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6393 as_bad (_("missing or invalid immediate expression `%s'"),
6397 else if (exp
->X_op
== O_constant
)
6399 /* Size it properly later. */
6400 i
.types
[this_operand
].bitfield
.imm64
= 1;
6401 /* If BFD64, sign extend val. */
6402 if (!use_rela_relocations
6403 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6405 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6407 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6408 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6409 && exp_seg
!= absolute_section
6410 && exp_seg
!= text_section
6411 && exp_seg
!= data_section
6412 && exp_seg
!= bss_section
6413 && exp_seg
!= undefined_section
6414 && !bfd_is_com_section (exp_seg
))
6416 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6420 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6423 as_bad (_("illegal immediate register operand %s"), imm_start
);
6428 /* This is an address. The size of the address will be
6429 determined later, depending on destination register,
6430 suffix, or the default for the section. */
6431 i
.types
[this_operand
].bitfield
.imm8
= 1;
6432 i
.types
[this_operand
].bitfield
.imm16
= 1;
6433 i
.types
[this_operand
].bitfield
.imm32
= 1;
6434 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6435 i
.types
[this_operand
].bitfield
.imm64
= 1;
6436 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6444 i386_scale (char *scale
)
6447 char *save
= input_line_pointer
;
6449 input_line_pointer
= scale
;
6450 val
= get_absolute_expression ();
6455 i
.log2_scale_factor
= 0;
6458 i
.log2_scale_factor
= 1;
6461 i
.log2_scale_factor
= 2;
6464 i
.log2_scale_factor
= 3;
6468 char sep
= *input_line_pointer
;
6470 *input_line_pointer
= '\0';
6471 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6473 *input_line_pointer
= sep
;
6474 input_line_pointer
= save
;
6478 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6480 as_warn (_("scale factor of %d without an index register"),
6481 1 << i
.log2_scale_factor
);
6482 i
.log2_scale_factor
= 0;
6484 scale
= input_line_pointer
;
6485 input_line_pointer
= save
;
6490 i386_displacement (char *disp_start
, char *disp_end
)
6494 char *save_input_line_pointer
;
6495 char *gotfree_input_line
;
6497 i386_operand_type bigdisp
, types
= anydisp
;
6500 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6502 as_bad (_("at most %d displacement operands are allowed"),
6503 MAX_MEMORY_OPERANDS
);
6507 operand_type_set (&bigdisp
, 0);
6508 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6509 || (!current_templates
->start
->opcode_modifier
.jump
6510 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6512 bigdisp
.bitfield
.disp32
= 1;
6513 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6514 if (flag_code
== CODE_64BIT
)
6518 bigdisp
.bitfield
.disp32s
= 1;
6519 bigdisp
.bitfield
.disp64
= 1;
6522 else if ((flag_code
== CODE_16BIT
) ^ override
)
6524 bigdisp
.bitfield
.disp32
= 0;
6525 bigdisp
.bitfield
.disp16
= 1;
6530 /* For PC-relative branches, the width of the displacement
6531 is dependent upon data size, not address size. */
6532 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6533 if (flag_code
== CODE_64BIT
)
6535 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6536 bigdisp
.bitfield
.disp16
= 1;
6539 bigdisp
.bitfield
.disp32
= 1;
6540 bigdisp
.bitfield
.disp32s
= 1;
6546 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6548 : LONG_MNEM_SUFFIX
));
6549 bigdisp
.bitfield
.disp32
= 1;
6550 if ((flag_code
== CODE_16BIT
) ^ override
)
6552 bigdisp
.bitfield
.disp32
= 0;
6553 bigdisp
.bitfield
.disp16
= 1;
6557 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6560 exp
= &disp_expressions
[i
.disp_operands
];
6561 i
.op
[this_operand
].disps
= exp
;
6563 save_input_line_pointer
= input_line_pointer
;
6564 input_line_pointer
= disp_start
;
6565 END_STRING_AND_SAVE (disp_end
);
6567 #ifndef GCC_ASM_O_HACK
6568 #define GCC_ASM_O_HACK 0
6571 END_STRING_AND_SAVE (disp_end
+ 1);
6572 if (i
.types
[this_operand
].bitfield
.baseIndex
6573 && displacement_string_end
[-1] == '+')
6575 /* This hack is to avoid a warning when using the "o"
6576 constraint within gcc asm statements.
6579 #define _set_tssldt_desc(n,addr,limit,type) \
6580 __asm__ __volatile__ ( \
6582 "movw %w1,2+%0\n\t" \
6584 "movb %b1,4+%0\n\t" \
6585 "movb %4,5+%0\n\t" \
6586 "movb $0,6+%0\n\t" \
6587 "movb %h1,7+%0\n\t" \
6589 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6591 This works great except that the output assembler ends
6592 up looking a bit weird if it turns out that there is
6593 no offset. You end up producing code that looks like:
6606 So here we provide the missing zero. */
6608 *displacement_string_end
= '0';
6611 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6612 if (gotfree_input_line
)
6613 input_line_pointer
= gotfree_input_line
;
6615 exp_seg
= expression (exp
);
6618 if (*input_line_pointer
)
6619 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6621 RESTORE_END_STRING (disp_end
+ 1);
6623 input_line_pointer
= save_input_line_pointer
;
6624 if (gotfree_input_line
)
6626 free (gotfree_input_line
);
6628 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6629 exp
->X_op
= O_illegal
;
6632 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6634 RESTORE_END_STRING (disp_end
);
6640 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6641 i386_operand_type types
, const char *disp_start
)
6643 i386_operand_type bigdisp
;
6646 /* We do this to make sure that the section symbol is in
6647 the symbol table. We will ultimately change the relocation
6648 to be relative to the beginning of the section. */
6649 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6650 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6651 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6653 if (exp
->X_op
!= O_symbol
)
6656 if (S_IS_LOCAL (exp
->X_add_symbol
)
6657 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6658 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6659 exp
->X_op
= O_subtract
;
6660 exp
->X_op_symbol
= GOT_symbol
;
6661 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6662 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6663 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6664 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6666 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6669 else if (exp
->X_op
== O_absent
6670 || exp
->X_op
== O_illegal
6671 || exp
->X_op
== O_big
)
6674 as_bad (_("missing or invalid displacement expression `%s'"),
6679 else if (flag_code
== CODE_64BIT
6680 && !i
.prefix
[ADDR_PREFIX
]
6681 && exp
->X_op
== O_constant
)
6683 /* Since displacement is signed extended to 64bit, don't allow
6684 disp32 and turn off disp32s if they are out of range. */
6685 i
.types
[this_operand
].bitfield
.disp32
= 0;
6686 if (!fits_in_signed_long (exp
->X_add_number
))
6688 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6689 if (i
.types
[this_operand
].bitfield
.baseindex
)
6691 as_bad (_("0x%lx out range of signed 32bit displacement"),
6692 (long) exp
->X_add_number
);
6698 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6699 else if (exp
->X_op
!= O_constant
6700 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6701 && exp_seg
!= absolute_section
6702 && exp_seg
!= text_section
6703 && exp_seg
!= data_section
6704 && exp_seg
!= bss_section
6705 && exp_seg
!= undefined_section
6706 && !bfd_is_com_section (exp_seg
))
6708 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6713 /* Check if this is a displacement only operand. */
6714 bigdisp
= i
.types
[this_operand
];
6715 bigdisp
.bitfield
.disp8
= 0;
6716 bigdisp
.bitfield
.disp16
= 0;
6717 bigdisp
.bitfield
.disp32
= 0;
6718 bigdisp
.bitfield
.disp32s
= 0;
6719 bigdisp
.bitfield
.disp64
= 0;
6720 if (operand_type_all_zero (&bigdisp
))
6721 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6727 /* Make sure the memory operand we've been dealt is valid.
6728 Return 1 on success, 0 on a failure. */
6731 i386_index_check (const char *operand_string
)
6734 const char *kind
= "base/index";
6735 #if INFER_ADDR_PREFIX
6741 if (current_templates
->start
->opcode_modifier
.isstring
6742 && !current_templates
->start
->opcode_modifier
.immext
6743 && (current_templates
->end
[-1].opcode_modifier
.isstring
6746 /* Memory operands of string insns are special in that they only allow
6747 a single register (rDI, rSI, or rBX) as their memory address. */
6748 unsigned int expected
;
6750 kind
= "string address";
6752 if (current_templates
->start
->opcode_modifier
.w
)
6754 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6756 if (!type
.bitfield
.baseindex
6757 || ((!i
.mem_operands
!= !intel_syntax
)
6758 && current_templates
->end
[-1].operand_types
[1]
6759 .bitfield
.baseindex
))
6760 type
= current_templates
->end
[-1].operand_types
[1];
6761 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6764 expected
= 3 /* rBX */;
6766 if (!i
.base_reg
|| i
.index_reg
6767 || operand_type_check (i
.types
[this_operand
], disp
))
6769 else if (!(flag_code
== CODE_64BIT
6770 ? i
.prefix
[ADDR_PREFIX
]
6771 ? i
.base_reg
->reg_type
.bitfield
.reg32
6772 : i
.base_reg
->reg_type
.bitfield
.reg64
6773 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6774 ? i
.base_reg
->reg_type
.bitfield
.reg32
6775 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6777 else if (i
.base_reg
->reg_num
!= expected
)
6784 for (j
= 0; j
< i386_regtab_size
; ++j
)
6785 if ((flag_code
== CODE_64BIT
6786 ? i
.prefix
[ADDR_PREFIX
]
6787 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6788 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6789 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6790 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6791 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6792 && i386_regtab
[j
].reg_num
== expected
)
6794 gas_assert (j
< i386_regtab_size
);
6795 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6797 intel_syntax
? '[' : '(',
6799 i386_regtab
[j
].reg_name
,
6800 intel_syntax
? ']' : ')');
6804 else if (flag_code
== CODE_64BIT
)
6807 && ((i
.prefix
[ADDR_PREFIX
] == 0
6808 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6809 || (i
.prefix
[ADDR_PREFIX
]
6810 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6812 || i
.base_reg
->reg_num
!=
6813 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6815 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6816 || (i
.prefix
[ADDR_PREFIX
] == 0
6817 && i
.index_reg
->reg_num
!= RegRiz
6818 && !i
.index_reg
->reg_type
.bitfield
.reg64
6820 || (i
.prefix
[ADDR_PREFIX
]
6821 && i
.index_reg
->reg_num
!= RegEiz
6822 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6827 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6831 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6832 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6834 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6835 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6837 && i
.base_reg
->reg_num
< 6
6838 && i
.index_reg
->reg_num
>= 6
6839 && i
.log2_scale_factor
== 0))))
6846 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6848 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6849 && i
.index_reg
->reg_num
!= RegEiz
)
6850 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6856 #if INFER_ADDR_PREFIX
6857 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6859 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6861 /* Change the size of any displacement too. At most one of
6862 Disp16 or Disp32 is set.
6863 FIXME. There doesn't seem to be any real need for separate
6864 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6865 Removing them would probably clean up the code quite a lot. */
6866 if (flag_code
!= CODE_64BIT
6867 && (i
.types
[this_operand
].bitfield
.disp16
6868 || i
.types
[this_operand
].bitfield
.disp32
))
6869 i
.types
[this_operand
]
6870 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6875 as_bad (_("`%s' is not a valid %s expression"),
6880 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6882 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6883 ? flag_code
== CODE_32BIT
6892 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6896 i386_att_operand (char *operand_string
)
6900 char *op_string
= operand_string
;
6902 if (is_space_char (*op_string
))
6905 /* We check for an absolute prefix (differentiating,
6906 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6907 if (*op_string
== ABSOLUTE_PREFIX
)
6910 if (is_space_char (*op_string
))
6912 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6915 /* Check if operand is a register. */
6916 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6918 i386_operand_type temp
;
6920 /* Check for a segment override by searching for ':' after a
6921 segment register. */
6923 if (is_space_char (*op_string
))
6925 if (*op_string
== ':'
6926 && (r
->reg_type
.bitfield
.sreg2
6927 || r
->reg_type
.bitfield
.sreg3
))
6932 i
.seg
[i
.mem_operands
] = &es
;
6935 i
.seg
[i
.mem_operands
] = &cs
;
6938 i
.seg
[i
.mem_operands
] = &ss
;
6941 i
.seg
[i
.mem_operands
] = &ds
;
6944 i
.seg
[i
.mem_operands
] = &fs
;
6947 i
.seg
[i
.mem_operands
] = &gs
;
6951 /* Skip the ':' and whitespace. */
6953 if (is_space_char (*op_string
))
6956 if (!is_digit_char (*op_string
)
6957 && !is_identifier_char (*op_string
)
6958 && *op_string
!= '('
6959 && *op_string
!= ABSOLUTE_PREFIX
)
6961 as_bad (_("bad memory operand `%s'"), op_string
);
6964 /* Handle case of %es:*foo. */
6965 if (*op_string
== ABSOLUTE_PREFIX
)
6968 if (is_space_char (*op_string
))
6970 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6972 goto do_memory_reference
;
6976 as_bad (_("junk `%s' after register"), op_string
);
6980 temp
.bitfield
.baseindex
= 0;
6981 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6983 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6984 i
.op
[this_operand
].regs
= r
;
6987 else if (*op_string
== REGISTER_PREFIX
)
6989 as_bad (_("bad register name `%s'"), op_string
);
6992 else if (*op_string
== IMMEDIATE_PREFIX
)
6995 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6997 as_bad (_("immediate operand illegal with absolute jump"));
7000 if (!i386_immediate (op_string
))
7003 else if (is_digit_char (*op_string
)
7004 || is_identifier_char (*op_string
)
7005 || *op_string
== '(')
7007 /* This is a memory reference of some sort. */
7010 /* Start and end of displacement string expression (if found). */
7011 char *displacement_string_start
;
7012 char *displacement_string_end
;
7014 do_memory_reference
:
7015 if ((i
.mem_operands
== 1
7016 && !current_templates
->start
->opcode_modifier
.isstring
)
7017 || i
.mem_operands
== 2)
7019 as_bad (_("too many memory references for `%s'"),
7020 current_templates
->start
->name
);
7024 /* Check for base index form. We detect the base index form by
7025 looking for an ')' at the end of the operand, searching
7026 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7028 base_string
= op_string
+ strlen (op_string
);
7031 if (is_space_char (*base_string
))
7034 /* If we only have a displacement, set-up for it to be parsed later. */
7035 displacement_string_start
= op_string
;
7036 displacement_string_end
= base_string
+ 1;
7038 if (*base_string
== ')')
7041 unsigned int parens_balanced
= 1;
7042 /* We've already checked that the number of left & right ()'s are
7043 equal, so this loop will not be infinite. */
7047 if (*base_string
== ')')
7049 if (*base_string
== '(')
7052 while (parens_balanced
);
7054 temp_string
= base_string
;
7056 /* Skip past '(' and whitespace. */
7058 if (is_space_char (*base_string
))
7061 if (*base_string
== ','
7062 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7065 displacement_string_end
= temp_string
;
7067 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7071 base_string
= end_op
;
7072 if (is_space_char (*base_string
))
7076 /* There may be an index reg or scale factor here. */
7077 if (*base_string
== ',')
7080 if (is_space_char (*base_string
))
7083 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7086 base_string
= end_op
;
7087 if (is_space_char (*base_string
))
7089 if (*base_string
== ',')
7092 if (is_space_char (*base_string
))
7095 else if (*base_string
!= ')')
7097 as_bad (_("expecting `,' or `)' "
7098 "after index register in `%s'"),
7103 else if (*base_string
== REGISTER_PREFIX
)
7105 as_bad (_("bad register name `%s'"), base_string
);
7109 /* Check for scale factor. */
7110 if (*base_string
!= ')')
7112 char *end_scale
= i386_scale (base_string
);
7117 base_string
= end_scale
;
7118 if (is_space_char (*base_string
))
7120 if (*base_string
!= ')')
7122 as_bad (_("expecting `)' "
7123 "after scale factor in `%s'"),
7128 else if (!i
.index_reg
)
7130 as_bad (_("expecting index register or scale factor "
7131 "after `,'; got '%c'"),
7136 else if (*base_string
!= ')')
7138 as_bad (_("expecting `,' or `)' "
7139 "after base register in `%s'"),
7144 else if (*base_string
== REGISTER_PREFIX
)
7146 as_bad (_("bad register name `%s'"), base_string
);
7151 /* If there's an expression beginning the operand, parse it,
7152 assuming displacement_string_start and
7153 displacement_string_end are meaningful. */
7154 if (displacement_string_start
!= displacement_string_end
)
7156 if (!i386_displacement (displacement_string_start
,
7157 displacement_string_end
))
7161 /* Special case for (%dx) while doing input/output op. */
7163 && operand_type_equal (&i
.base_reg
->reg_type
,
7164 ®16_inoutportreg
)
7166 && i
.log2_scale_factor
== 0
7167 && i
.seg
[i
.mem_operands
] == 0
7168 && !operand_type_check (i
.types
[this_operand
], disp
))
7170 i
.types
[this_operand
] = inoutportreg
;
7174 if (i386_index_check (operand_string
) == 0)
7176 i
.types
[this_operand
].bitfield
.mem
= 1;
7181 /* It's not a memory operand; argh! */
7182 as_bad (_("invalid char %s beginning operand %d `%s'"),
7183 output_invalid (*op_string
),
7188 return 1; /* Normal return. */
7191 /* md_estimate_size_before_relax()
7193 Called just before relax() for rs_machine_dependent frags. The x86
7194 assembler uses these frags to handle variable size jump
7197 Any symbol that is now undefined will not become defined.
7198 Return the correct fr_subtype in the frag.
7199 Return the initial "guess for variable size of frag" to caller.
7200 The guess is actually the growth beyond the fixed part. Whatever
7201 we do to grow the fixed or variable part contributes to our
7205 md_estimate_size_before_relax (fragP
, segment
)
7209 /* We've already got fragP->fr_subtype right; all we have to do is
7210 check for un-relaxable symbols. On an ELF system, we can't relax
7211 an externally visible symbol, because it may be overridden by a
7213 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7216 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7217 || S_IS_WEAK (fragP
->fr_symbol
)
7218 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7219 & BSF_GNU_INDIRECT_FUNCTION
))))
7221 #if defined (OBJ_COFF) && defined (TE_PE)
7222 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7223 && S_IS_WEAK (fragP
->fr_symbol
))
7227 /* Symbol is undefined in this segment, or we need to keep a
7228 reloc so that weak symbols can be overridden. */
7229 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7230 enum bfd_reloc_code_real reloc_type
;
7231 unsigned char *opcode
;
7234 if (fragP
->fr_var
!= NO_RELOC
)
7235 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7237 reloc_type
= BFD_RELOC_16_PCREL
;
7239 reloc_type
= BFD_RELOC_32_PCREL
;
7241 old_fr_fix
= fragP
->fr_fix
;
7242 opcode
= (unsigned char *) fragP
->fr_opcode
;
7244 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7247 /* Make jmp (0xeb) a (d)word displacement jump. */
7249 fragP
->fr_fix
+= size
;
7250 fix_new (fragP
, old_fr_fix
, size
,
7252 fragP
->fr_offset
, 1,
7258 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7260 /* Negate the condition, and branch past an
7261 unconditional jump. */
7264 /* Insert an unconditional jump. */
7266 /* We added two extra opcode bytes, and have a two byte
7268 fragP
->fr_fix
+= 2 + 2;
7269 fix_new (fragP
, old_fr_fix
+ 2, 2,
7271 fragP
->fr_offset
, 1,
7278 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7283 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7285 fragP
->fr_offset
, 1,
7287 fixP
->fx_signed
= 1;
7291 /* This changes the byte-displacement jump 0x7N
7292 to the (d)word-displacement jump 0x0f,0x8N. */
7293 opcode
[1] = opcode
[0] + 0x10;
7294 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7295 /* We've added an opcode byte. */
7296 fragP
->fr_fix
+= 1 + size
;
7297 fix_new (fragP
, old_fr_fix
+ 1, size
,
7299 fragP
->fr_offset
, 1,
7304 BAD_CASE (fragP
->fr_subtype
);
7308 return fragP
->fr_fix
- old_fr_fix
;
7311 /* Guess size depending on current relax state. Initially the relax
7312 state will correspond to a short jump and we return 1, because
7313 the variable part of the frag (the branch offset) is one byte
7314 long. However, we can relax a section more than once and in that
7315 case we must either set fr_subtype back to the unrelaxed state,
7316 or return the value for the appropriate branch. */
7317 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7320 /* Called after relax() is finished.
7322 In: Address of frag.
7323 fr_type == rs_machine_dependent.
7324 fr_subtype is what the address relaxed to.
7326 Out: Any fixSs and constants are set up.
7327 Caller will turn frag into a ".space 0". */
7330 md_convert_frag (abfd
, sec
, fragP
)
7331 bfd
*abfd ATTRIBUTE_UNUSED
;
7332 segT sec ATTRIBUTE_UNUSED
;
7335 unsigned char *opcode
;
7336 unsigned char *where_to_put_displacement
= NULL
;
7337 offsetT target_address
;
7338 offsetT opcode_address
;
7339 unsigned int extension
= 0;
7340 offsetT displacement_from_opcode_start
;
7342 opcode
= (unsigned char *) fragP
->fr_opcode
;
7344 /* Address we want to reach in file space. */
7345 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7347 /* Address opcode resides at in file space. */
7348 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7350 /* Displacement from opcode start to fill into instruction. */
7351 displacement_from_opcode_start
= target_address
- opcode_address
;
7353 if ((fragP
->fr_subtype
& BIG
) == 0)
7355 /* Don't have to change opcode. */
7356 extension
= 1; /* 1 opcode + 1 displacement */
7357 where_to_put_displacement
= &opcode
[1];
7361 if (no_cond_jump_promotion
7362 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7363 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7364 _("long jump required"));
7366 switch (fragP
->fr_subtype
)
7368 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7369 extension
= 4; /* 1 opcode + 4 displacement */
7371 where_to_put_displacement
= &opcode
[1];
7374 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7375 extension
= 2; /* 1 opcode + 2 displacement */
7377 where_to_put_displacement
= &opcode
[1];
7380 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7381 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7382 extension
= 5; /* 2 opcode + 4 displacement */
7383 opcode
[1] = opcode
[0] + 0x10;
7384 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7385 where_to_put_displacement
= &opcode
[2];
7388 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7389 extension
= 3; /* 2 opcode + 2 displacement */
7390 opcode
[1] = opcode
[0] + 0x10;
7391 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7392 where_to_put_displacement
= &opcode
[2];
7395 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7400 where_to_put_displacement
= &opcode
[3];
7404 BAD_CASE (fragP
->fr_subtype
);
7409 /* If size if less then four we are sure that the operand fits,
7410 but if it's 4, then it could be that the displacement is larger
7412 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7414 && ((addressT
) (displacement_from_opcode_start
- extension
7415 + ((addressT
) 1 << 31))
7416 > (((addressT
) 2 << 31) - 1)))
7418 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7419 _("jump target out of range"));
7420 /* Make us emit 0. */
7421 displacement_from_opcode_start
= extension
;
7423 /* Now put displacement after opcode. */
7424 md_number_to_chars ((char *) where_to_put_displacement
,
7425 (valueT
) (displacement_from_opcode_start
- extension
),
7426 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7427 fragP
->fr_fix
+= extension
;
7430 /* Apply a fixup (fixS) to segment data, once it has been determined
7431 by our caller that we have all the info we need to fix it up.
7433 On the 386, immediates, displacements, and data pointers are all in
7434 the same (little-endian) format, so we don't need to care about which
7438 md_apply_fix (fixP
, valP
, seg
)
7439 /* The fix we're to put in. */
7441 /* Pointer to the value of the bits. */
7443 /* Segment fix is from. */
7444 segT seg ATTRIBUTE_UNUSED
;
7446 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7447 valueT value
= *valP
;
7449 #if !defined (TE_Mach)
7452 switch (fixP
->fx_r_type
)
7458 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7461 case BFD_RELOC_X86_64_32S
:
7462 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7465 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7468 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7473 if (fixP
->fx_addsy
!= NULL
7474 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7475 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7476 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7477 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7478 && !use_rela_relocations
)
7480 /* This is a hack. There should be a better way to handle this.
7481 This covers for the fact that bfd_install_relocation will
7482 subtract the current location (for partial_inplace, PC relative
7483 relocations); see more below. */
7487 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7490 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7492 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7495 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7498 || (symbol_section_p (fixP
->fx_addsy
)
7499 && sym_seg
!= absolute_section
))
7500 && !generic_force_reloc (fixP
))
7502 /* Yes, we add the values in twice. This is because
7503 bfd_install_relocation subtracts them out again. I think
7504 bfd_install_relocation is broken, but I don't dare change
7506 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7510 #if defined (OBJ_COFF) && defined (TE_PE)
7511 /* For some reason, the PE format does not store a
7512 section address offset for a PC relative symbol. */
7513 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7514 || S_IS_WEAK (fixP
->fx_addsy
))
7515 value
+= md_pcrel_from (fixP
);
7518 #if defined (OBJ_COFF) && defined (TE_PE)
7519 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7521 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7525 /* Fix a few things - the dynamic linker expects certain values here,
7526 and we must not disappoint it. */
7527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7528 if (IS_ELF
&& fixP
->fx_addsy
)
7529 switch (fixP
->fx_r_type
)
7531 case BFD_RELOC_386_PLT32
:
7532 case BFD_RELOC_X86_64_PLT32
:
7533 /* Make the jump instruction point to the address of the operand. At
7534 runtime we merely add the offset to the actual PLT entry. */
7538 case BFD_RELOC_386_TLS_GD
:
7539 case BFD_RELOC_386_TLS_LDM
:
7540 case BFD_RELOC_386_TLS_IE_32
:
7541 case BFD_RELOC_386_TLS_IE
:
7542 case BFD_RELOC_386_TLS_GOTIE
:
7543 case BFD_RELOC_386_TLS_GOTDESC
:
7544 case BFD_RELOC_X86_64_TLSGD
:
7545 case BFD_RELOC_X86_64_TLSLD
:
7546 case BFD_RELOC_X86_64_GOTTPOFF
:
7547 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7548 value
= 0; /* Fully resolved at runtime. No addend. */
7550 case BFD_RELOC_386_TLS_LE
:
7551 case BFD_RELOC_386_TLS_LDO_32
:
7552 case BFD_RELOC_386_TLS_LE_32
:
7553 case BFD_RELOC_X86_64_DTPOFF32
:
7554 case BFD_RELOC_X86_64_DTPOFF64
:
7555 case BFD_RELOC_X86_64_TPOFF32
:
7556 case BFD_RELOC_X86_64_TPOFF64
:
7557 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7560 case BFD_RELOC_386_TLS_DESC_CALL
:
7561 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7562 value
= 0; /* Fully resolved at runtime. No addend. */
7563 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7567 case BFD_RELOC_386_GOT32
:
7568 case BFD_RELOC_X86_64_GOT32
:
7569 value
= 0; /* Fully resolved at runtime. No addend. */
7572 case BFD_RELOC_VTABLE_INHERIT
:
7573 case BFD_RELOC_VTABLE_ENTRY
:
7580 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7582 #endif /* !defined (TE_Mach) */
7584 /* Are we finished with this relocation now? */
7585 if (fixP
->fx_addsy
== NULL
)
7587 #if defined (OBJ_COFF) && defined (TE_PE)
7588 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7591 /* Remember value for tc_gen_reloc. */
7592 fixP
->fx_addnumber
= value
;
7593 /* Clear out the frag for now. */
7597 else if (use_rela_relocations
)
7599 fixP
->fx_no_overflow
= 1;
7600 /* Remember value for tc_gen_reloc. */
7601 fixP
->fx_addnumber
= value
;
7605 md_number_to_chars (p
, value
, fixP
->fx_size
);
7609 md_atof (int type
, char *litP
, int *sizeP
)
7611 /* This outputs the LITTLENUMs in REVERSE order;
7612 in accord with the bigendian 386. */
7613 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7616 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7619 output_invalid (int c
)
7622 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7625 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7626 "(0x%x)", (unsigned char) c
);
7627 return output_invalid_buf
;
7630 /* REG_STRING starts *before* REGISTER_PREFIX. */
7632 static const reg_entry
*
7633 parse_real_register (char *reg_string
, char **end_op
)
7635 char *s
= reg_string
;
7637 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7640 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7641 if (*s
== REGISTER_PREFIX
)
7644 if (is_space_char (*s
))
7648 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7650 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7651 return (const reg_entry
*) NULL
;
7655 /* For naked regs, make sure that we are not dealing with an identifier.
7656 This prevents confusing an identifier like `eax_var' with register
7658 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7659 return (const reg_entry
*) NULL
;
7663 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7665 /* Handle floating point regs, allowing spaces in the (i) part. */
7666 if (r
== i386_regtab
/* %st is first entry of table */)
7668 if (is_space_char (*s
))
7673 if (is_space_char (*s
))
7675 if (*s
>= '0' && *s
<= '7')
7679 if (is_space_char (*s
))
7684 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7689 /* We have "%st(" then garbage. */
7690 return (const reg_entry
*) NULL
;
7694 if (r
== NULL
|| allow_pseudo_reg
)
7697 if (operand_type_all_zero (&r
->reg_type
))
7698 return (const reg_entry
*) NULL
;
7700 if ((r
->reg_type
.bitfield
.reg32
7701 || r
->reg_type
.bitfield
.sreg3
7702 || r
->reg_type
.bitfield
.control
7703 || r
->reg_type
.bitfield
.debug
7704 || r
->reg_type
.bitfield
.test
)
7705 && !cpu_arch_flags
.bitfield
.cpui386
)
7706 return (const reg_entry
*) NULL
;
7708 if (r
->reg_type
.bitfield
.floatreg
7709 && !cpu_arch_flags
.bitfield
.cpu8087
7710 && !cpu_arch_flags
.bitfield
.cpu287
7711 && !cpu_arch_flags
.bitfield
.cpu387
)
7712 return (const reg_entry
*) NULL
;
7714 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7715 return (const reg_entry
*) NULL
;
7717 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7718 return (const reg_entry
*) NULL
;
7720 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7721 return (const reg_entry
*) NULL
;
7723 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7724 if (!allow_index_reg
7725 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7726 return (const reg_entry
*) NULL
;
7728 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7729 || r
->reg_type
.bitfield
.reg64
)
7730 && (!cpu_arch_flags
.bitfield
.cpulm
7731 || !operand_type_equal (&r
->reg_type
, &control
))
7732 && flag_code
!= CODE_64BIT
)
7733 return (const reg_entry
*) NULL
;
7735 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7736 return (const reg_entry
*) NULL
;
7741 /* REG_STRING starts *before* REGISTER_PREFIX. */
7743 static const reg_entry
*
7744 parse_register (char *reg_string
, char **end_op
)
7748 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7749 r
= parse_real_register (reg_string
, end_op
);
7754 char *save
= input_line_pointer
;
7758 input_line_pointer
= reg_string
;
7759 c
= get_symbol_end ();
7760 symbolP
= symbol_find (reg_string
);
7761 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7763 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7765 know (e
->X_op
== O_register
);
7766 know (e
->X_add_number
>= 0
7767 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7768 r
= i386_regtab
+ e
->X_add_number
;
7769 *end_op
= input_line_pointer
;
7771 *input_line_pointer
= c
;
7772 input_line_pointer
= save
;
7778 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7781 char *end
= input_line_pointer
;
7784 r
= parse_register (name
, &input_line_pointer
);
7785 if (r
&& end
<= input_line_pointer
)
7787 *nextcharP
= *input_line_pointer
;
7788 *input_line_pointer
= 0;
7789 e
->X_op
= O_register
;
7790 e
->X_add_number
= r
- i386_regtab
;
7793 input_line_pointer
= end
;
7795 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7799 md_operand (expressionS
*e
)
7804 switch (*input_line_pointer
)
7806 case REGISTER_PREFIX
:
7807 r
= parse_real_register (input_line_pointer
, &end
);
7810 e
->X_op
= O_register
;
7811 e
->X_add_number
= r
- i386_regtab
;
7812 input_line_pointer
= end
;
7817 gas_assert (intel_syntax
);
7818 end
= input_line_pointer
++;
7820 if (*input_line_pointer
== ']')
7822 ++input_line_pointer
;
7823 e
->X_op_symbol
= make_expr_symbol (e
);
7824 e
->X_add_symbol
= NULL
;
7825 e
->X_add_number
= 0;
7831 input_line_pointer
= end
;
7838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7839 const char *md_shortopts
= "kVQ:sqn";
7841 const char *md_shortopts
= "qn";
7844 #define OPTION_32 (OPTION_MD_BASE + 0)
7845 #define OPTION_64 (OPTION_MD_BASE + 1)
7846 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7847 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7848 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7849 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7850 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7851 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7852 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7853 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7854 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7855 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7857 struct option md_longopts
[] =
7859 {"32", no_argument
, NULL
, OPTION_32
},
7860 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7861 || defined (TE_PE) || defined (TE_PEP))
7862 {"64", no_argument
, NULL
, OPTION_64
},
7864 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7865 {"march", required_argument
, NULL
, OPTION_MARCH
},
7866 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7867 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7868 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7869 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7870 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7871 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7872 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7873 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7874 {NULL
, no_argument
, NULL
, 0}
7876 size_t md_longopts_size
= sizeof (md_longopts
);
7879 md_parse_option (int c
, char *arg
)
7887 optimize_align_code
= 0;
7894 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7895 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7896 should be emitted or not. FIXME: Not implemented. */
7900 /* -V: SVR4 argument to print version ID. */
7902 print_version_id ();
7905 /* -k: Ignore for FreeBSD compatibility. */
7910 /* -s: On i386 Solaris, this tells the native assembler to use
7911 .stab instead of .stab.excl. We always use .stab anyhow. */
7914 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7915 || defined (TE_PE) || defined (TE_PEP))
7918 const char **list
, **l
;
7920 list
= bfd_target_list ();
7921 for (l
= list
; *l
!= NULL
; l
++)
7922 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7923 || strcmp (*l
, "coff-x86-64") == 0
7924 || strcmp (*l
, "pe-x86-64") == 0
7925 || strcmp (*l
, "pei-x86-64") == 0)
7927 default_arch
= "x86_64";
7931 as_fatal (_("No compiled in support for x86_64"));
7938 default_arch
= "i386";
7942 #ifdef SVR4_COMMENT_CHARS
7947 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7949 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7953 i386_comment_chars
= n
;
7959 arch
= xstrdup (arg
);
7963 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7964 next
= strchr (arch
, '+');
7967 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
7969 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
7972 cpu_arch_name
= cpu_arch
[j
].name
;
7973 cpu_sub_arch_name
= NULL
;
7974 cpu_arch_flags
= cpu_arch
[j
].flags
;
7975 cpu_arch_isa
= cpu_arch
[j
].type
;
7976 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
7977 if (!cpu_arch_tune_set
)
7979 cpu_arch_tune
= cpu_arch_isa
;
7980 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7984 else if (*cpu_arch
[j
].name
== '.'
7985 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
7987 /* ISA entension. */
7988 i386_cpu_flags flags
;
7990 if (strncmp (arch
, "no", 2))
7991 flags
= cpu_flags_or (cpu_arch_flags
,
7994 flags
= cpu_flags_and_not (cpu_arch_flags
,
7996 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7998 if (cpu_sub_arch_name
)
8000 char *name
= cpu_sub_arch_name
;
8001 cpu_sub_arch_name
= concat (name
,
8003 (const char *) NULL
);
8007 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8008 cpu_arch_flags
= flags
;
8014 if (j
>= ARRAY_SIZE (cpu_arch
))
8015 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8019 while (next
!= NULL
);
8024 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8025 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8027 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8029 cpu_arch_tune_set
= 1;
8030 cpu_arch_tune
= cpu_arch
[j
].type
;
8031 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8035 if (j
>= ARRAY_SIZE (cpu_arch
))
8036 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8039 case OPTION_MMNEMONIC
:
8040 if (strcasecmp (arg
, "att") == 0)
8042 else if (strcasecmp (arg
, "intel") == 0)
8045 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8048 case OPTION_MSYNTAX
:
8049 if (strcasecmp (arg
, "att") == 0)
8051 else if (strcasecmp (arg
, "intel") == 0)
8054 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8057 case OPTION_MINDEX_REG
:
8058 allow_index_reg
= 1;
8061 case OPTION_MNAKED_REG
:
8062 allow_naked_reg
= 1;
8065 case OPTION_MOLD_GCC
:
8069 case OPTION_MSSE2AVX
:
8073 case OPTION_MSSE_CHECK
:
8074 if (strcasecmp (arg
, "error") == 0)
8075 sse_check
= sse_check_error
;
8076 else if (strcasecmp (arg
, "warning") == 0)
8077 sse_check
= sse_check_warning
;
8078 else if (strcasecmp (arg
, "none") == 0)
8079 sse_check
= sse_check_none
;
8081 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8090 #define MESSAGE_TEMPLATE \
8094 show_arch (FILE *stream
, int ext
)
8096 static char message
[] = MESSAGE_TEMPLATE
;
8097 char *start
= message
+ 27;
8099 int size
= sizeof (MESSAGE_TEMPLATE
);
8106 left
= size
- (start
- message
);
8107 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8109 /* Should it be skipped? */
8110 if (cpu_arch
[j
].skip
)
8113 name
= cpu_arch
[j
].name
;
8114 len
= cpu_arch
[j
].len
;
8117 /* It is an extension. Skip if we aren't asked to show it. */
8128 /* It is an processor. Skip if we show only extension. */
8132 /* Reserve 2 spaces for ", " or ",\0" */
8135 /* Check if there is any room. */
8143 p
= mempcpy (p
, name
, len
);
8147 /* Output the current message now and start a new one. */
8150 fprintf (stream
, "%s\n", message
);
8152 left
= size
- (start
- message
) - len
- 2;
8154 gas_assert (left
>= 0);
8156 p
= mempcpy (p
, name
, len
);
8161 fprintf (stream
, "%s\n", message
);
8165 md_show_usage (FILE *stream
)
8167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8168 fprintf (stream
, _("\
8170 -V print assembler version number\n\
8173 fprintf (stream
, _("\
8174 -n Do not optimize code alignment\n\
8175 -q quieten some warnings\n"));
8176 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8177 fprintf (stream
, _("\
8180 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8181 || defined (TE_PE) || defined (TE_PEP))
8182 fprintf (stream
, _("\
8183 --32/--64 generate 32bit/64bit code\n"));
8185 #ifdef SVR4_COMMENT_CHARS
8186 fprintf (stream
, _("\
8187 --divide do not treat `/' as a comment character\n"));
8189 fprintf (stream
, _("\
8190 --divide ignored\n"));
8192 fprintf (stream
, _("\
8193 -march=CPU[,+EXTENSION...]\n\
8194 generate code for CPU and EXTENSION, CPU is one of:\n"));
8195 show_arch (stream
, 0);
8196 fprintf (stream
, _("\
8197 EXTENSION is combination of:\n"));
8198 show_arch (stream
, 1);
8199 fprintf (stream
, _("\
8200 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8201 show_arch (stream
, 0);
8202 fprintf (stream
, _("\
8203 -msse2avx encode SSE instructions with VEX prefix\n"));
8204 fprintf (stream
, _("\
8205 -msse-check=[none|error|warning]\n\
8206 check SSE instructions\n"));
8207 fprintf (stream
, _("\
8208 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8209 fprintf (stream
, _("\
8210 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8211 fprintf (stream
, _("\
8212 -mindex-reg support pseudo index registers\n"));
8213 fprintf (stream
, _("\
8214 -mnaked-reg don't require `%%' prefix for registers\n"));
8215 fprintf (stream
, _("\
8216 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8219 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8220 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8221 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8223 /* Pick the target format to use. */
8226 i386_target_format (void)
8228 if (!strcmp (default_arch
, "x86_64"))
8230 set_code_flag (CODE_64BIT
);
8231 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8233 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8234 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8235 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8236 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8237 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8238 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8239 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8240 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8241 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8242 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8243 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8245 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8247 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8248 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8249 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8250 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8251 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8252 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8253 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8254 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8255 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8256 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8259 else if (!strcmp (default_arch
, "i386"))
8261 set_code_flag (CODE_32BIT
);
8262 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8264 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8265 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8266 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8268 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8270 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8271 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8272 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8276 as_fatal (_("Unknown architecture"));
8277 switch (OUTPUT_FLAVOR
)
8279 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8280 case bfd_target_aout_flavour
:
8281 return AOUT_TARGET_FORMAT
;
8283 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8284 # if defined (TE_PE) || defined (TE_PEP)
8285 case bfd_target_coff_flavour
:
8286 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8287 # elif defined (TE_GO32)
8288 case bfd_target_coff_flavour
:
8291 case bfd_target_coff_flavour
:
8295 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8296 case bfd_target_elf_flavour
:
8298 if (flag_code
== CODE_64BIT
)
8301 use_rela_relocations
= 1;
8303 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8305 if (flag_code
!= CODE_64BIT
)
8306 as_fatal (_("Intel L1OM is 64bit only"));
8307 return ELF_TARGET_L1OM_FORMAT
;
8310 return (flag_code
== CODE_64BIT
8311 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8314 #if defined (OBJ_MACH_O)
8315 case bfd_target_mach_o_flavour
:
8316 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8324 #endif /* OBJ_MAYBE_ more than one */
8326 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8328 i386_elf_emit_arch_note (void)
8330 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8333 asection
*seg
= now_seg
;
8334 subsegT subseg
= now_subseg
;
8335 Elf_Internal_Note i_note
;
8336 Elf_External_Note e_note
;
8337 asection
*note_secp
;
8340 /* Create the .note section. */
8341 note_secp
= subseg_new (".note", 0);
8342 bfd_set_section_flags (stdoutput
,
8344 SEC_HAS_CONTENTS
| SEC_READONLY
);
8346 /* Process the arch string. */
8347 len
= strlen (cpu_arch_name
);
8349 i_note
.namesz
= len
+ 1;
8351 i_note
.type
= NT_ARCH
;
8352 p
= frag_more (sizeof (e_note
.namesz
));
8353 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8354 p
= frag_more (sizeof (e_note
.descsz
));
8355 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8356 p
= frag_more (sizeof (e_note
.type
));
8357 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8358 p
= frag_more (len
+ 1);
8359 strcpy (p
, cpu_arch_name
);
8361 frag_align (2, 0, 0);
8363 subseg_set (seg
, subseg
);
8369 md_undefined_symbol (name
)
8372 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8373 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8374 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8375 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8379 if (symbol_find (name
))
8380 as_bad (_("GOT already in symbol table"));
8381 GOT_symbol
= symbol_new (name
, undefined_section
,
8382 (valueT
) 0, &zero_address_frag
);
8389 /* Round up a section size to the appropriate boundary. */
8392 md_section_align (segment
, size
)
8393 segT segment ATTRIBUTE_UNUSED
;
8396 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8397 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8399 /* For a.out, force the section size to be aligned. If we don't do
8400 this, BFD will align it for us, but it will not write out the
8401 final bytes of the section. This may be a bug in BFD, but it is
8402 easier to fix it here since that is how the other a.out targets
8406 align
= bfd_get_section_alignment (stdoutput
, segment
);
8407 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8414 /* On the i386, PC-relative offsets are relative to the start of the
8415 next instruction. That is, the address of the offset, plus its
8416 size, since the offset is always the last part of the insn. */
8419 md_pcrel_from (fixS
*fixP
)
8421 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8427 s_bss (int ignore ATTRIBUTE_UNUSED
)
8431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8433 obj_elf_section_change_hook ();
8435 temp
= get_absolute_expression ();
8436 subseg_set (bss_section
, (subsegT
) temp
);
8437 demand_empty_rest_of_line ();
8443 i386_validate_fix (fixS
*fixp
)
8445 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8447 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8451 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8456 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8458 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8465 tc_gen_reloc (section
, fixp
)
8466 asection
*section ATTRIBUTE_UNUSED
;
8470 bfd_reloc_code_real_type code
;
8472 switch (fixp
->fx_r_type
)
8474 case BFD_RELOC_X86_64_PLT32
:
8475 case BFD_RELOC_X86_64_GOT32
:
8476 case BFD_RELOC_X86_64_GOTPCREL
:
8477 case BFD_RELOC_386_PLT32
:
8478 case BFD_RELOC_386_GOT32
:
8479 case BFD_RELOC_386_GOTOFF
:
8480 case BFD_RELOC_386_GOTPC
:
8481 case BFD_RELOC_386_TLS_GD
:
8482 case BFD_RELOC_386_TLS_LDM
:
8483 case BFD_RELOC_386_TLS_LDO_32
:
8484 case BFD_RELOC_386_TLS_IE_32
:
8485 case BFD_RELOC_386_TLS_IE
:
8486 case BFD_RELOC_386_TLS_GOTIE
:
8487 case BFD_RELOC_386_TLS_LE_32
:
8488 case BFD_RELOC_386_TLS_LE
:
8489 case BFD_RELOC_386_TLS_GOTDESC
:
8490 case BFD_RELOC_386_TLS_DESC_CALL
:
8491 case BFD_RELOC_X86_64_TLSGD
:
8492 case BFD_RELOC_X86_64_TLSLD
:
8493 case BFD_RELOC_X86_64_DTPOFF32
:
8494 case BFD_RELOC_X86_64_DTPOFF64
:
8495 case BFD_RELOC_X86_64_GOTTPOFF
:
8496 case BFD_RELOC_X86_64_TPOFF32
:
8497 case BFD_RELOC_X86_64_TPOFF64
:
8498 case BFD_RELOC_X86_64_GOTOFF64
:
8499 case BFD_RELOC_X86_64_GOTPC32
:
8500 case BFD_RELOC_X86_64_GOT64
:
8501 case BFD_RELOC_X86_64_GOTPCREL64
:
8502 case BFD_RELOC_X86_64_GOTPC64
:
8503 case BFD_RELOC_X86_64_GOTPLT64
:
8504 case BFD_RELOC_X86_64_PLTOFF64
:
8505 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8506 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8508 case BFD_RELOC_VTABLE_ENTRY
:
8509 case BFD_RELOC_VTABLE_INHERIT
:
8511 case BFD_RELOC_32_SECREL
:
8513 code
= fixp
->fx_r_type
;
8515 case BFD_RELOC_X86_64_32S
:
8516 if (!fixp
->fx_pcrel
)
8518 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8519 code
= fixp
->fx_r_type
;
8525 switch (fixp
->fx_size
)
8528 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8529 _("can not do %d byte pc-relative relocation"),
8531 code
= BFD_RELOC_32_PCREL
;
8533 case 1: code
= BFD_RELOC_8_PCREL
; break;
8534 case 2: code
= BFD_RELOC_16_PCREL
; break;
8535 case 4: code
= BFD_RELOC_32_PCREL
; break;
8537 case 8: code
= BFD_RELOC_64_PCREL
; break;
8543 switch (fixp
->fx_size
)
8546 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8547 _("can not do %d byte relocation"),
8549 code
= BFD_RELOC_32
;
8551 case 1: code
= BFD_RELOC_8
; break;
8552 case 2: code
= BFD_RELOC_16
; break;
8553 case 4: code
= BFD_RELOC_32
; break;
8555 case 8: code
= BFD_RELOC_64
; break;
8562 if ((code
== BFD_RELOC_32
8563 || code
== BFD_RELOC_32_PCREL
8564 || code
== BFD_RELOC_X86_64_32S
)
8566 && fixp
->fx_addsy
== GOT_symbol
)
8569 code
= BFD_RELOC_386_GOTPC
;
8571 code
= BFD_RELOC_X86_64_GOTPC32
;
8573 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8575 && fixp
->fx_addsy
== GOT_symbol
)
8577 code
= BFD_RELOC_X86_64_GOTPC64
;
8580 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8581 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8582 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8584 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8586 if (!use_rela_relocations
)
8588 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8589 vtable entry to be used in the relocation's section offset. */
8590 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8591 rel
->address
= fixp
->fx_offset
;
8592 #if defined (OBJ_COFF) && defined (TE_PE)
8593 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8594 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8599 /* Use the rela in 64bit mode. */
8602 if (!fixp
->fx_pcrel
)
8603 rel
->addend
= fixp
->fx_offset
;
8607 case BFD_RELOC_X86_64_PLT32
:
8608 case BFD_RELOC_X86_64_GOT32
:
8609 case BFD_RELOC_X86_64_GOTPCREL
:
8610 case BFD_RELOC_X86_64_TLSGD
:
8611 case BFD_RELOC_X86_64_TLSLD
:
8612 case BFD_RELOC_X86_64_GOTTPOFF
:
8613 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8614 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8615 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8618 rel
->addend
= (section
->vma
8620 + fixp
->fx_addnumber
8621 + md_pcrel_from (fixp
));
8626 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8627 if (rel
->howto
== NULL
)
8629 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8630 _("cannot represent relocation type %s"),
8631 bfd_get_reloc_code_name (code
));
8632 /* Set howto to a garbage value so that we can keep going. */
8633 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8634 gas_assert (rel
->howto
!= NULL
);
8640 #include "tc-i386-intel.c"
8643 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8645 int saved_naked_reg
;
8646 char saved_register_dot
;
8648 saved_naked_reg
= allow_naked_reg
;
8649 allow_naked_reg
= 1;
8650 saved_register_dot
= register_chars
['.'];
8651 register_chars
['.'] = '.';
8652 allow_pseudo_reg
= 1;
8653 expression_and_evaluate (exp
);
8654 allow_pseudo_reg
= 0;
8655 register_chars
['.'] = saved_register_dot
;
8656 allow_naked_reg
= saved_naked_reg
;
8658 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8660 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8662 exp
->X_op
= O_constant
;
8663 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8664 .dw2_regnum
[flag_code
>> 1];
8667 exp
->X_op
= O_illegal
;
8672 tc_x86_frame_initial_instructions (void)
8674 static unsigned int sp_regno
[2];
8676 if (!sp_regno
[flag_code
>> 1])
8678 char *saved_input
= input_line_pointer
;
8679 char sp
[][4] = {"esp", "rsp"};
8682 input_line_pointer
= sp
[flag_code
>> 1];
8683 tc_x86_parse_to_dw2regnum (&exp
);
8684 gas_assert (exp
.X_op
== O_constant
);
8685 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8686 input_line_pointer
= saved_input
;
8689 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8690 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8694 i386_elf_section_type (const char *str
, size_t len
)
8696 if (flag_code
== CODE_64BIT
8697 && len
== sizeof ("unwind") - 1
8698 && strncmp (str
, "unwind", 6) == 0)
8699 return SHT_X86_64_UNWIND
;
8706 i386_solaris_fix_up_eh_frame (segT sec
)
8708 if (flag_code
== CODE_64BIT
)
8709 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8715 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8719 exp
.X_op
= O_secrel
;
8720 exp
.X_add_symbol
= symbol
;
8721 exp
.X_add_number
= 0;
8722 emit_expr (&exp
, size
);
8726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8727 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8730 x86_64_section_letter (int letter
, char **ptr_msg
)
8732 if (flag_code
== CODE_64BIT
)
8735 return SHF_X86_64_LARGE
;
8737 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8740 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8745 x86_64_section_word (char *str
, size_t len
)
8747 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8748 return SHF_X86_64_LARGE
;
8754 handle_large_common (int small ATTRIBUTE_UNUSED
)
8756 if (flag_code
!= CODE_64BIT
)
8758 s_comm_internal (0, elf_common_parse
);
8759 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8763 static segT lbss_section
;
8764 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8765 asection
*saved_bss_section
= bss_section
;
8767 if (lbss_section
== NULL
)
8769 flagword applicable
;
8771 subsegT subseg
= now_subseg
;
8773 /* The .lbss section is for local .largecomm symbols. */
8774 lbss_section
= subseg_new (".lbss", 0);
8775 applicable
= bfd_applicable_section_flags (stdoutput
);
8776 bfd_set_section_flags (stdoutput
, lbss_section
,
8777 applicable
& SEC_ALLOC
);
8778 seg_info (lbss_section
)->bss
= 1;
8780 subseg_set (seg
, subseg
);
8783 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8784 bss_section
= lbss_section
;
8786 s_comm_internal (0, elf_common_parse
);
8788 elf_com_section_ptr
= saved_com_section_ptr
;
8789 bss_section
= saved_bss_section
;
8792 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */