1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
71 #define REX_PREFIX 6 /* must come last. */
72 #define MAX_PREFIXES 7 /* max prefixes per opcode */
74 /* we define the syntax here (modulo base,index,scale syntax) */
75 #define REGISTER_PREFIX '%'
76 #define IMMEDIATE_PREFIX '$'
77 #define ABSOLUTE_PREFIX '*'
79 /* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81 #define WORD_MNEM_SUFFIX 'w'
82 #define BYTE_MNEM_SUFFIX 'b'
83 #define SHORT_MNEM_SUFFIX 's'
84 #define LONG_MNEM_SUFFIX 'l'
85 #define QWORD_MNEM_SUFFIX 'q'
86 #define XMMWORD_MNEM_SUFFIX 'x'
87 #define YMMWORD_MNEM_SUFFIX 'y'
88 /* Intel Syntax. Use a non-ascii letter since since it never appears
90 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
92 #define END_OF_INSN '\0'
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
103 const insn_template
*start
;
104 const insn_template
*end
;
108 /* 386 operand encoding bytes: see 386 book for details of this. */
111 unsigned int regmem
; /* codes register or memory operand */
112 unsigned int reg
; /* codes register operand (or extended opcode) */
113 unsigned int mode
; /* how to interpret regmem & reg */
117 /* x86-64 extension prefix. */
118 typedef int rex_byte
;
120 /* 386 opcode byte to code indirect addressing. */
129 /* x86 arch names, types and features */
132 const char *name
; /* arch name */
133 unsigned int len
; /* arch string length */
134 enum processor_type type
; /* arch type */
135 i386_cpu_flags flags
; /* cpu feature flags */
136 unsigned int skip
; /* show_arch should skip this. */
137 unsigned int negated
; /* turn off indicated flags. */
141 static void update_code_flag (int, int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (char *, char **);
163 static char *parse_insn (char *, char *);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (int, int);
167 static void optimize_imm (void);
168 static void optimize_disp (void);
169 static const insn_template
*match_template (void);
170 static int check_string (void);
171 static int process_suffix (void);
172 static int check_byte_reg (void);
173 static int check_long_reg (void);
174 static int check_qword_reg (void);
175 static int check_word_reg (void);
176 static int finalize_imm (void);
177 static int process_operands (void);
178 static const seg_entry
*build_modrm_byte (void);
179 static void output_insn (void);
180 static void output_imm (fragS
*, offsetT
);
181 static void output_disp (fragS
*, offsetT
);
183 static void s_bss (int);
185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 static const char *default_arch
= DEFAULT_ARCH
;
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes
[3];
197 /* Destination or source register specifier. */
198 const reg_entry
*register_specifier
;
201 /* 'md_assemble ()' gathers together information and puts it into a
208 const reg_entry
*regs
;
213 operand_size_mismatch
,
214 operand_type_mismatch
,
215 register_type_mismatch
,
216 number_of_operands_mismatch
,
217 invalid_instruction_suffix
,
220 unsupported_with_intel_mnemonic
,
223 invalid_vsib_address
,
224 invalid_vector_register_set
,
225 unsupported_vector_index_register
230 /* TM holds the template for the insn were currently assembling. */
233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
237 /* OPERANDS gives the number of given operands. */
238 unsigned int operands
;
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
243 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
245 /* TYPES [i] is the type (see above #defines) which tells us how to
246 use OP[i] for the corresponding operand. */
247 i386_operand_type types
[MAX_OPERANDS
];
249 /* Displacement expression, immediate expression, or register for each
251 union i386_op op
[MAX_OPERANDS
];
253 /* Flags for operands. */
254 unsigned int flags
[MAX_OPERANDS
];
255 #define Operand_PCrel 1
257 /* Relocation type for operand */
258 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry
*base_reg
;
263 const reg_entry
*index_reg
;
264 unsigned int log2_scale_factor
;
266 /* SEG gives the seg_entries of this insn. They are zero unless
267 explicit segment overrides are given. */
268 const seg_entry
*seg
[2];
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes
;
273 unsigned char prefix
[MAX_PREFIXES
];
275 /* RM and SIB are the modrm byte and the sib byte where the
276 addressing modes of this insn are encoded. */
282 /* Swap operand in encoding. */
283 unsigned int swap_operand
;
285 /* Prefer 8bit or 32bit displacement in encoding. */
288 disp_encoding_default
= 0,
293 /* Have HLE prefix. */
294 unsigned int have_hle
;
297 enum i386_error error
;
300 typedef struct _i386_insn i386_insn
;
302 /* List of chars besides those in app.c:symbol_chars that can start an
303 operand. Used to prevent the scrubber eating vital white-space. */
304 const char extra_symbol_chars
[] = "*%-(["
313 #if (defined (TE_I386AIX) \
314 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
315 && !defined (TE_GNU) \
316 && !defined (TE_LINUX) \
317 && !defined (TE_NACL) \
318 && !defined (TE_NETWARE) \
319 && !defined (TE_FreeBSD) \
320 && !defined (TE_DragonFly) \
321 && !defined (TE_NetBSD)))
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325 const char *i386_comment_chars
= "#/";
326 #define SVR4_COMMENT_CHARS 1
327 #define PREFIX_SEPARATOR '\\'
330 const char *i386_comment_chars
= "#";
331 #define PREFIX_SEPARATOR '/'
334 /* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
338 first line of the input file. This is because the compiler outputs
339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
341 '/' isn't otherwise defined. */
342 const char line_comment_chars
[] = "#/";
344 const char line_separator_chars
[] = ";";
346 /* Chars that can be used to separate mant from exp in floating point
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant
353 const char FLT_CHARS
[] = "fFdDxX";
355 /* Tables for lexical analysis. */
356 static char mnemonic_chars
[256];
357 static char register_chars
[256];
358 static char operand_chars
[256];
359 static char identifier_chars
[256];
360 static char digit_chars
[256];
362 /* Lexical macros. */
363 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364 #define is_operand_char(x) (operand_chars[(unsigned char) x])
365 #define is_register_char(x) (register_chars[(unsigned char) x])
366 #define is_space_char(x) ((x) == ' ')
367 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368 #define is_digit_char(x) (digit_chars[(unsigned char) x])
370 /* All non-digit non-letter characters that may occur in an operand. */
371 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
373 /* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
376 assembler instruction). */
377 static char save_stack
[32];
378 static char *save_stack_p
;
379 #define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381 #define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
384 /* The instruction we're assembling. */
387 /* Possible templates for current insn. */
388 static const templates
*current_templates
;
390 /* Per instruction expressionS buffers: max displacements & immediates. */
391 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
392 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
394 /* Current operand we are working on. */
395 static int this_operand
= -1;
397 /* We support four different modes. FLAG_CODE variable is used to distinguish
405 static enum flag_code flag_code
;
406 static unsigned int object_64bit
;
407 static unsigned int disallow_64bit_reloc
;
408 static int use_rela_relocations
= 0;
410 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
411 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
412 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
414 /* The ELF ABI to use. */
422 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
425 /* The names used to print error messages. */
426 static const char *flag_code_names
[] =
433 /* 1 for intel syntax,
435 static int intel_syntax
= 0;
437 /* 1 for intel mnemonic,
438 0 if att mnemonic. */
439 static int intel_mnemonic
= !SYSV386_COMPAT
;
441 /* 1 if support old (<= 2.8.1) versions of gcc. */
442 static int old_gcc
= OLDGCC_COMPAT
;
444 /* 1 if pseudo registers are permitted. */
445 static int allow_pseudo_reg
= 0;
447 /* 1 if register prefix % not required. */
448 static int allow_naked_reg
= 0;
450 /* 1 if pseudo index register, eiz/riz, is allowed . */
451 static int allow_index_reg
= 0;
453 static enum check_kind
459 sse_check
, operand_check
= check_warning
;
461 /* Register prefix used for error message. */
462 static const char *register_prefix
= "%";
464 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
465 leave, push, and pop instructions so that gcc has the same stack
466 frame as in 32 bit mode. */
467 static char stackop_size
= '\0';
469 /* Non-zero to optimize code alignment. */
470 int optimize_align_code
= 1;
472 /* Non-zero to quieten some warnings. */
473 static int quiet_warnings
= 0;
476 static const char *cpu_arch_name
= NULL
;
477 static char *cpu_sub_arch_name
= NULL
;
479 /* CPU feature flags. */
480 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
482 /* If we have selected a cpu we are generating instructions for. */
483 static int cpu_arch_tune_set
= 0;
485 /* Cpu we are generating instructions for. */
486 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
488 /* CPU feature flags of cpu we are generating instructions for. */
489 static i386_cpu_flags cpu_arch_tune_flags
;
491 /* CPU instruction set architecture used. */
492 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
494 /* CPU feature flags of instruction set architecture used. */
495 i386_cpu_flags cpu_arch_isa_flags
;
497 /* If set, conditional jumps are not automatically promoted to handle
498 larger than a byte offset. */
499 static unsigned int no_cond_jump_promotion
= 0;
501 /* Encode SSE instructions with VEX prefix. */
502 static unsigned int sse2avx
;
504 /* Encode scalar AVX instructions with specific vector length. */
511 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
512 static symbolS
*GOT_symbol
;
514 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
515 unsigned int x86_dwarf2_return_column
;
517 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
518 int x86_cie_data_alignment
;
520 /* Interface to relax_segment.
521 There are 3 major relax states for 386 jump insns because the
522 different types of jumps add different sizes to frags when we're
523 figuring out what sort of jump to choose to reach a given label. */
526 #define UNCOND_JUMP 0
528 #define COND_JUMP86 2
533 #define SMALL16 (SMALL | CODE16)
535 #define BIG16 (BIG | CODE16)
539 #define INLINE __inline__
545 #define ENCODE_RELAX_STATE(type, size) \
546 ((relax_substateT) (((type) << 2) | (size)))
547 #define TYPE_FROM_RELAX_STATE(s) \
549 #define DISP_SIZE_FROM_RELAX_STATE(s) \
550 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
552 /* This table is used by relax_frag to promote short jumps to long
553 ones where necessary. SMALL (short) jumps may be promoted to BIG
554 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
555 don't allow a short jump in a 32 bit code segment to be promoted to
556 a 16 bit offset jump because it's slower (requires data size
557 prefix), and doesn't work, unless the destination is in the bottom
558 64k of the code segment (The top 16 bits of eip are zeroed). */
560 const relax_typeS md_relax_table
[] =
563 1) most positive reach of this state,
564 2) most negative reach of this state,
565 3) how many bytes this mode will have in the variable part of the frag
566 4) which index into the table to try if we can't fit into this one. */
568 /* UNCOND_JUMP states. */
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
570 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
571 /* dword jmp adds 4 bytes to frag:
572 0 extra opcode bytes, 4 displacement bytes. */
574 /* word jmp adds 2 byte2 to frag:
575 0 extra opcode bytes, 2 displacement bytes. */
578 /* COND_JUMP states. */
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
580 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
581 /* dword conditionals adds 5 bytes to frag:
582 1 extra opcode byte, 4 displacement bytes. */
584 /* word conditionals add 3 bytes to frag:
585 1 extra opcode byte, 2 displacement bytes. */
588 /* COND_JUMP86 states. */
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
590 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
591 /* dword conditionals adds 5 bytes to frag:
592 1 extra opcode byte, 4 displacement bytes. */
594 /* word conditionals add 4 bytes to frag:
595 1 displacement byte and a 3 byte long branch insn. */
599 static const arch_entry cpu_arch
[] =
601 /* Do not replace the first two entries - i386_target_format()
602 relies on them being there in this order. */
603 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
604 CPU_GENERIC32_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
606 CPU_GENERIC64_FLAGS
, 0, 0 },
607 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
608 CPU_NONE_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
610 CPU_I186_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
612 CPU_I286_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
614 CPU_I386_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
616 CPU_I486_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
618 CPU_I586_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
620 CPU_I686_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
622 CPU_I586_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
624 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
626 CPU_P2_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
628 CPU_P3_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
630 CPU_P4_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
632 CPU_CORE_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
634 CPU_NOCONA_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
636 CPU_CORE_FLAGS
, 1, 0 },
637 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
638 CPU_CORE_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
640 CPU_CORE2_FLAGS
, 1, 0 },
641 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
642 CPU_CORE2_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
644 CPU_COREI7_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
646 CPU_L1OM_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
648 CPU_K1OM_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
650 CPU_K6_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
652 CPU_K6_2_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
654 CPU_ATHLON_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
656 CPU_K8_FLAGS
, 1, 0 },
657 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
658 CPU_K8_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
660 CPU_K8_FLAGS
, 0, 0 },
661 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
662 CPU_AMDFAM10_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
664 CPU_BDVER1_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
666 CPU_BDVER2_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
668 CPU_BDVER3_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
670 CPU_BTVER1_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
672 CPU_BTVER2_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
674 CPU_8087_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
676 CPU_287_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
678 CPU_387_FLAGS
, 0, 0 },
679 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
680 CPU_ANY87_FLAGS
, 0, 1 },
681 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
682 CPU_MMX_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
684 CPU_3DNOWA_FLAGS
, 0, 1 },
685 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
686 CPU_SSE_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
688 CPU_SSE2_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
690 CPU_SSE3_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
692 CPU_SSSE3_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
694 CPU_SSE4_1_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
696 CPU_SSE4_2_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
698 CPU_SSE4_2_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
700 CPU_ANY_SSE_FLAGS
, 0, 1 },
701 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
702 CPU_AVX_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
704 CPU_AVX2_FLAGS
, 0, 0 },
705 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
706 CPU_ANY_AVX_FLAGS
, 0, 1 },
707 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
708 CPU_VMX_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
710 CPU_VMFUNC_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
712 CPU_SMX_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
714 CPU_XSAVE_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
716 CPU_XSAVEOPT_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
718 CPU_AES_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
720 CPU_PCLMUL_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
722 CPU_PCLMUL_FLAGS
, 1, 0 },
723 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
724 CPU_FSGSBASE_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
726 CPU_RDRND_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
728 CPU_F16C_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
730 CPU_BMI2_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
732 CPU_FMA_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
734 CPU_FMA4_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
736 CPU_XOP_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
738 CPU_LWP_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
740 CPU_MOVBE_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
742 CPU_CX16_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
744 CPU_EPT_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
746 CPU_LZCNT_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
748 CPU_HLE_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
750 CPU_RTM_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
752 CPU_INVPCID_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
754 CPU_CLFLUSH_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
756 CPU_NOP_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
758 CPU_SYSCALL_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
760 CPU_RDTSCP_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
762 CPU_3DNOW_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
764 CPU_3DNOWA_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
766 CPU_PADLOCK_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
768 CPU_SVME_FLAGS
, 1, 0 },
769 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
770 CPU_SVME_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
772 CPU_SSE4A_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
774 CPU_ABM_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
776 CPU_BMI_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
778 CPU_TBM_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
780 CPU_ADX_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
782 CPU_RDSEED_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
784 CPU_PRFCHW_FLAGS
, 0, 0 },
788 /* Like s_lcomm_internal in gas/read.c but the alignment string
789 is allowed to be optional. */
792 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
799 && *input_line_pointer
== ',')
801 align
= parse_align (needs_align
- 1);
803 if (align
== (addressT
) -1)
818 bss_alloc (symbolP
, size
, align
);
823 pe_lcomm (int needs_align
)
825 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
829 const pseudo_typeS md_pseudo_table
[] =
831 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
832 {"align", s_align_bytes
, 0},
834 {"align", s_align_ptwo
, 0},
836 {"arch", set_cpu_arch
, 0},
840 {"lcomm", pe_lcomm
, 1},
842 {"ffloat", float_cons
, 'f'},
843 {"dfloat", float_cons
, 'd'},
844 {"tfloat", float_cons
, 'x'},
846 {"slong", signed_cons
, 4},
847 {"noopt", s_ignore
, 0},
848 {"optim", s_ignore
, 0},
849 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
850 {"code16", set_code_flag
, CODE_16BIT
},
851 {"code32", set_code_flag
, CODE_32BIT
},
852 {"code64", set_code_flag
, CODE_64BIT
},
853 {"intel_syntax", set_intel_syntax
, 1},
854 {"att_syntax", set_intel_syntax
, 0},
855 {"intel_mnemonic", set_intel_mnemonic
, 1},
856 {"att_mnemonic", set_intel_mnemonic
, 0},
857 {"allow_index_reg", set_allow_index_reg
, 1},
858 {"disallow_index_reg", set_allow_index_reg
, 0},
859 {"sse_check", set_check
, 0},
860 {"operand_check", set_check
, 1},
861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
862 {"largecomm", handle_large_common
, 0},
864 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
865 {"loc", dwarf2_directive_loc
, 0},
866 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
869 {"secrel32", pe_directive_secrel
, 0},
874 /* For interface with expression (). */
875 extern char *input_line_pointer
;
877 /* Hash table for instruction mnemonic lookup. */
878 static struct hash_control
*op_hash
;
880 /* Hash table for register lookup. */
881 static struct hash_control
*reg_hash
;
884 i386_align_code (fragS
*fragP
, int count
)
886 /* Various efficient no-op patterns for aligning code labels.
887 Note: Don't try to assemble the instructions in the comments.
888 0L and 0w are not legal. */
889 static const char f32_1
[] =
891 static const char f32_2
[] =
892 {0x66,0x90}; /* xchg %ax,%ax */
893 static const char f32_3
[] =
894 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
895 static const char f32_4
[] =
896 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
897 static const char f32_5
[] =
899 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
900 static const char f32_6
[] =
901 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
902 static const char f32_7
[] =
903 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
904 static const char f32_8
[] =
906 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
907 static const char f32_9
[] =
908 {0x89,0xf6, /* movl %esi,%esi */
909 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
910 static const char f32_10
[] =
911 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
912 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
913 static const char f32_11
[] =
914 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
915 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
916 static const char f32_12
[] =
917 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
918 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
919 static const char f32_13
[] =
920 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
921 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
922 static const char f32_14
[] =
923 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
924 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
925 static const char f16_3
[] =
926 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
927 static const char f16_4
[] =
928 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
929 static const char f16_5
[] =
931 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
932 static const char f16_6
[] =
933 {0x89,0xf6, /* mov %si,%si */
934 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
935 static const char f16_7
[] =
936 {0x8d,0x74,0x00, /* lea 0(%si),%si */
937 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
938 static const char f16_8
[] =
939 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
940 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
941 static const char jump_31
[] =
942 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
943 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
944 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
945 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
946 static const char *const f32_patt
[] = {
947 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
948 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
950 static const char *const f16_patt
[] = {
951 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
954 static const char alt_3
[] =
956 /* nopl 0(%[re]ax) */
957 static const char alt_4
[] =
958 {0x0f,0x1f,0x40,0x00};
959 /* nopl 0(%[re]ax,%[re]ax,1) */
960 static const char alt_5
[] =
961 {0x0f,0x1f,0x44,0x00,0x00};
962 /* nopw 0(%[re]ax,%[re]ax,1) */
963 static const char alt_6
[] =
964 {0x66,0x0f,0x1f,0x44,0x00,0x00};
965 /* nopl 0L(%[re]ax) */
966 static const char alt_7
[] =
967 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
968 /* nopl 0L(%[re]ax,%[re]ax,1) */
969 static const char alt_8
[] =
970 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopw 0L(%[re]ax,%[re]ax,1) */
972 static const char alt_9
[] =
973 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
974 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
975 static const char alt_10
[] =
976 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
978 nopw %cs:0L(%[re]ax,%[re]ax,1) */
979 static const char alt_long_11
[] =
981 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
984 nopw %cs:0L(%[re]ax,%[re]ax,1) */
985 static const char alt_long_12
[] =
988 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
992 nopw %cs:0L(%[re]ax,%[re]ax,1) */
993 static const char alt_long_13
[] =
997 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1002 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1003 static const char alt_long_14
[] =
1008 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1014 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1015 static const char alt_long_15
[] =
1021 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1022 /* nopl 0(%[re]ax,%[re]ax,1)
1023 nopw 0(%[re]ax,%[re]ax,1) */
1024 static const char alt_short_11
[] =
1025 {0x0f,0x1f,0x44,0x00,0x00,
1026 0x66,0x0f,0x1f,0x44,0x00,0x00};
1027 /* nopw 0(%[re]ax,%[re]ax,1)
1028 nopw 0(%[re]ax,%[re]ax,1) */
1029 static const char alt_short_12
[] =
1030 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1031 0x66,0x0f,0x1f,0x44,0x00,0x00};
1032 /* nopw 0(%[re]ax,%[re]ax,1)
1034 static const char alt_short_13
[] =
1035 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1036 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1039 static const char alt_short_14
[] =
1040 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1041 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1043 nopl 0L(%[re]ax,%[re]ax,1) */
1044 static const char alt_short_15
[] =
1045 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1046 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1047 static const char *const alt_short_patt
[] = {
1048 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1049 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1050 alt_short_14
, alt_short_15
1052 static const char *const alt_long_patt
[] = {
1053 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1054 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1055 alt_long_14
, alt_long_15
1058 /* Only align for at least a positive non-zero boundary. */
1059 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1062 /* We need to decide which NOP sequence to use for 32bit and
1063 64bit. When -mtune= is used:
1065 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1066 PROCESSOR_GENERIC32, f32_patt will be used.
1067 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1068 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1069 PROCESSOR_GENERIC64, alt_long_patt will be used.
1070 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1071 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1074 When -mtune= isn't used, alt_long_patt will be used if
1075 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1078 When -march= or .arch is used, we can't use anything beyond
1079 cpu_arch_isa_flags. */
1081 if (flag_code
== CODE_16BIT
)
1085 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1087 /* Adjust jump offset. */
1088 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1091 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1092 f16_patt
[count
- 1], count
);
1096 const char *const *patt
= NULL
;
1098 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1100 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1101 switch (cpu_arch_tune
)
1103 case PROCESSOR_UNKNOWN
:
1104 /* We use cpu_arch_isa_flags to check if we SHOULD
1105 optimize with nops. */
1106 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1107 patt
= alt_long_patt
;
1111 case PROCESSOR_PENTIUM4
:
1112 case PROCESSOR_NOCONA
:
1113 case PROCESSOR_CORE
:
1114 case PROCESSOR_CORE2
:
1115 case PROCESSOR_COREI7
:
1116 case PROCESSOR_L1OM
:
1117 case PROCESSOR_K1OM
:
1118 case PROCESSOR_GENERIC64
:
1119 patt
= alt_long_patt
;
1122 case PROCESSOR_ATHLON
:
1124 case PROCESSOR_AMDFAM10
:
1127 patt
= alt_short_patt
;
1129 case PROCESSOR_I386
:
1130 case PROCESSOR_I486
:
1131 case PROCESSOR_PENTIUM
:
1132 case PROCESSOR_PENTIUMPRO
:
1133 case PROCESSOR_GENERIC32
:
1140 switch (fragP
->tc_frag_data
.tune
)
1142 case PROCESSOR_UNKNOWN
:
1143 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1144 PROCESSOR_UNKNOWN. */
1148 case PROCESSOR_I386
:
1149 case PROCESSOR_I486
:
1150 case PROCESSOR_PENTIUM
:
1152 case PROCESSOR_ATHLON
:
1154 case PROCESSOR_AMDFAM10
:
1157 case PROCESSOR_GENERIC32
:
1158 /* We use cpu_arch_isa_flags to check if we CAN optimize
1160 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1161 patt
= alt_short_patt
;
1165 case PROCESSOR_PENTIUMPRO
:
1166 case PROCESSOR_PENTIUM4
:
1167 case PROCESSOR_NOCONA
:
1168 case PROCESSOR_CORE
:
1169 case PROCESSOR_CORE2
:
1170 case PROCESSOR_COREI7
:
1171 case PROCESSOR_L1OM
:
1172 case PROCESSOR_K1OM
:
1173 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1174 patt
= alt_long_patt
;
1178 case PROCESSOR_GENERIC64
:
1179 patt
= alt_long_patt
;
1184 if (patt
== f32_patt
)
1186 /* If the padding is less than 15 bytes, we use the normal
1187 ones. Otherwise, we use a jump instruction and adjust
1191 /* For 64bit, the limit is 3 bytes. */
1192 if (flag_code
== CODE_64BIT
1193 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1198 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1199 patt
[count
- 1], count
);
1202 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1204 /* Adjust jump offset. */
1205 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1210 /* Maximum length of an instruction is 15 byte. If the
1211 padding is greater than 15 bytes and we don't use jump,
1212 we have to break it into smaller pieces. */
1213 int padding
= count
;
1214 while (padding
> 15)
1217 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1222 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1223 patt
[padding
- 1], padding
);
1226 fragP
->fr_var
= count
;
1230 operand_type_all_zero (const union i386_operand_type
*x
)
1232 switch (ARRAY_SIZE(x
->array
))
1241 return !x
->array
[0];
1248 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1250 switch (ARRAY_SIZE(x
->array
))
1265 operand_type_equal (const union i386_operand_type
*x
,
1266 const union i386_operand_type
*y
)
1268 switch (ARRAY_SIZE(x
->array
))
1271 if (x
->array
[2] != y
->array
[2])
1274 if (x
->array
[1] != y
->array
[1])
1277 return x
->array
[0] == y
->array
[0];
1285 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1287 switch (ARRAY_SIZE(x
->array
))
1296 return !x
->array
[0];
1303 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1305 switch (ARRAY_SIZE(x
->array
))
1320 cpu_flags_equal (const union i386_cpu_flags
*x
,
1321 const union i386_cpu_flags
*y
)
1323 switch (ARRAY_SIZE(x
->array
))
1326 if (x
->array
[2] != y
->array
[2])
1329 if (x
->array
[1] != y
->array
[1])
1332 return x
->array
[0] == y
->array
[0];
1340 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1342 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1343 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1346 static INLINE i386_cpu_flags
1347 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1349 switch (ARRAY_SIZE (x
.array
))
1352 x
.array
[2] &= y
.array
[2];
1354 x
.array
[1] &= y
.array
[1];
1356 x
.array
[0] &= y
.array
[0];
1364 static INLINE i386_cpu_flags
1365 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1367 switch (ARRAY_SIZE (x
.array
))
1370 x
.array
[2] |= y
.array
[2];
1372 x
.array
[1] |= y
.array
[1];
1374 x
.array
[0] |= y
.array
[0];
1382 static INLINE i386_cpu_flags
1383 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1385 switch (ARRAY_SIZE (x
.array
))
1388 x
.array
[2] &= ~y
.array
[2];
1390 x
.array
[1] &= ~y
.array
[1];
1392 x
.array
[0] &= ~y
.array
[0];
1400 #define CPU_FLAGS_ARCH_MATCH 0x1
1401 #define CPU_FLAGS_64BIT_MATCH 0x2
1402 #define CPU_FLAGS_AES_MATCH 0x4
1403 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1404 #define CPU_FLAGS_AVX_MATCH 0x10
1406 #define CPU_FLAGS_32BIT_MATCH \
1407 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1408 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1409 #define CPU_FLAGS_PERFECT_MATCH \
1410 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1412 /* Return CPU flags match bits. */
1415 cpu_flags_match (const insn_template
*t
)
1417 i386_cpu_flags x
= t
->cpu_flags
;
1418 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1420 x
.bitfield
.cpu64
= 0;
1421 x
.bitfield
.cpuno64
= 0;
1423 if (cpu_flags_all_zero (&x
))
1425 /* This instruction is available on all archs. */
1426 match
|= CPU_FLAGS_32BIT_MATCH
;
1430 /* This instruction is available only on some archs. */
1431 i386_cpu_flags cpu
= cpu_arch_flags
;
1433 cpu
.bitfield
.cpu64
= 0;
1434 cpu
.bitfield
.cpuno64
= 0;
1435 cpu
= cpu_flags_and (x
, cpu
);
1436 if (!cpu_flags_all_zero (&cpu
))
1438 if (x
.bitfield
.cpuavx
)
1440 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1441 if (cpu
.bitfield
.cpuavx
)
1443 /* Check SSE2AVX. */
1444 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1446 match
|= (CPU_FLAGS_ARCH_MATCH
1447 | CPU_FLAGS_AVX_MATCH
);
1449 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1450 match
|= CPU_FLAGS_AES_MATCH
;
1452 if (!x
.bitfield
.cpupclmul
1453 || cpu
.bitfield
.cpupclmul
)
1454 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1458 match
|= CPU_FLAGS_ARCH_MATCH
;
1461 match
|= CPU_FLAGS_32BIT_MATCH
;
1467 static INLINE i386_operand_type
1468 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1470 switch (ARRAY_SIZE (x
.array
))
1473 x
.array
[2] &= y
.array
[2];
1475 x
.array
[1] &= y
.array
[1];
1477 x
.array
[0] &= y
.array
[0];
1485 static INLINE i386_operand_type
1486 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1488 switch (ARRAY_SIZE (x
.array
))
1491 x
.array
[2] |= y
.array
[2];
1493 x
.array
[1] |= y
.array
[1];
1495 x
.array
[0] |= y
.array
[0];
1503 static INLINE i386_operand_type
1504 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1506 switch (ARRAY_SIZE (x
.array
))
1509 x
.array
[2] ^= y
.array
[2];
1511 x
.array
[1] ^= y
.array
[1];
1513 x
.array
[0] ^= y
.array
[0];
1521 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1522 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1523 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1524 static const i386_operand_type inoutportreg
1525 = OPERAND_TYPE_INOUTPORTREG
;
1526 static const i386_operand_type reg16_inoutportreg
1527 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1528 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1529 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1530 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1531 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1532 static const i386_operand_type anydisp
1533 = OPERAND_TYPE_ANYDISP
;
1534 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1535 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1536 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1537 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1538 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1539 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1540 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1541 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1542 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1543 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1544 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1545 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1556 operand_type_check (i386_operand_type t
, enum operand_type c
)
1561 return (t
.bitfield
.reg8
1564 || t
.bitfield
.reg64
);
1567 return (t
.bitfield
.imm8
1571 || t
.bitfield
.imm32s
1572 || t
.bitfield
.imm64
);
1575 return (t
.bitfield
.disp8
1576 || t
.bitfield
.disp16
1577 || t
.bitfield
.disp32
1578 || t
.bitfield
.disp32s
1579 || t
.bitfield
.disp64
);
1582 return (t
.bitfield
.disp8
1583 || t
.bitfield
.disp16
1584 || t
.bitfield
.disp32
1585 || t
.bitfield
.disp32s
1586 || t
.bitfield
.disp64
1587 || t
.bitfield
.baseindex
);
1596 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1597 operand J for instruction template T. */
1600 match_reg_size (const insn_template
*t
, unsigned int j
)
1602 return !((i
.types
[j
].bitfield
.byte
1603 && !t
->operand_types
[j
].bitfield
.byte
)
1604 || (i
.types
[j
].bitfield
.word
1605 && !t
->operand_types
[j
].bitfield
.word
)
1606 || (i
.types
[j
].bitfield
.dword
1607 && !t
->operand_types
[j
].bitfield
.dword
)
1608 || (i
.types
[j
].bitfield
.qword
1609 && !t
->operand_types
[j
].bitfield
.qword
));
1612 /* Return 1 if there is no conflict in any size on operand J for
1613 instruction template T. */
1616 match_mem_size (const insn_template
*t
, unsigned int j
)
1618 return (match_reg_size (t
, j
)
1619 && !((i
.types
[j
].bitfield
.unspecified
1620 && !t
->operand_types
[j
].bitfield
.unspecified
)
1621 || (i
.types
[j
].bitfield
.fword
1622 && !t
->operand_types
[j
].bitfield
.fword
)
1623 || (i
.types
[j
].bitfield
.tbyte
1624 && !t
->operand_types
[j
].bitfield
.tbyte
)
1625 || (i
.types
[j
].bitfield
.xmmword
1626 && !t
->operand_types
[j
].bitfield
.xmmword
)
1627 || (i
.types
[j
].bitfield
.ymmword
1628 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1631 /* Return 1 if there is no size conflict on any operands for
1632 instruction template T. */
1635 operand_size_match (const insn_template
*t
)
1640 /* Don't check jump instructions. */
1641 if (t
->opcode_modifier
.jump
1642 || t
->opcode_modifier
.jumpbyte
1643 || t
->opcode_modifier
.jumpdword
1644 || t
->opcode_modifier
.jumpintersegment
)
1647 /* Check memory and accumulator operand size. */
1648 for (j
= 0; j
< i
.operands
; j
++)
1650 if (t
->operand_types
[j
].bitfield
.anysize
)
1653 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1659 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1668 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1671 i
.error
= operand_size_mismatch
;
1675 /* Check reverse. */
1676 gas_assert (i
.operands
== 2);
1679 for (j
= 0; j
< 2; j
++)
1681 if (t
->operand_types
[j
].bitfield
.acc
1682 && !match_reg_size (t
, j
? 0 : 1))
1685 if (i
.types
[j
].bitfield
.mem
1686 && !match_mem_size (t
, j
? 0 : 1))
1694 operand_type_match (i386_operand_type overlap
,
1695 i386_operand_type given
)
1697 i386_operand_type temp
= overlap
;
1699 temp
.bitfield
.jumpabsolute
= 0;
1700 temp
.bitfield
.unspecified
= 0;
1701 temp
.bitfield
.byte
= 0;
1702 temp
.bitfield
.word
= 0;
1703 temp
.bitfield
.dword
= 0;
1704 temp
.bitfield
.fword
= 0;
1705 temp
.bitfield
.qword
= 0;
1706 temp
.bitfield
.tbyte
= 0;
1707 temp
.bitfield
.xmmword
= 0;
1708 temp
.bitfield
.ymmword
= 0;
1709 if (operand_type_all_zero (&temp
))
1712 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1713 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1717 i
.error
= operand_type_mismatch
;
1721 /* If given types g0 and g1 are registers they must be of the same type
1722 unless the expected operand type register overlap is null.
1723 Note that Acc in a template matches every size of reg. */
1726 operand_type_register_match (i386_operand_type m0
,
1727 i386_operand_type g0
,
1728 i386_operand_type t0
,
1729 i386_operand_type m1
,
1730 i386_operand_type g1
,
1731 i386_operand_type t1
)
1733 if (!operand_type_check (g0
, reg
))
1736 if (!operand_type_check (g1
, reg
))
1739 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1740 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1741 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1742 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1745 if (m0
.bitfield
.acc
)
1747 t0
.bitfield
.reg8
= 1;
1748 t0
.bitfield
.reg16
= 1;
1749 t0
.bitfield
.reg32
= 1;
1750 t0
.bitfield
.reg64
= 1;
1753 if (m1
.bitfield
.acc
)
1755 t1
.bitfield
.reg8
= 1;
1756 t1
.bitfield
.reg16
= 1;
1757 t1
.bitfield
.reg32
= 1;
1758 t1
.bitfield
.reg64
= 1;
1761 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1762 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1763 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1764 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1767 i
.error
= register_type_mismatch
;
1772 static INLINE
unsigned int
1773 register_number (const reg_entry
*r
)
1775 unsigned int nr
= r
->reg_num
;
1777 if (r
->reg_flags
& RegRex
)
1783 static INLINE
unsigned int
1784 mode_from_disp_size (i386_operand_type t
)
1786 if (t
.bitfield
.disp8
)
1788 else if (t
.bitfield
.disp16
1789 || t
.bitfield
.disp32
1790 || t
.bitfield
.disp32s
)
1797 fits_in_signed_byte (offsetT num
)
1799 return (num
>= -128) && (num
<= 127);
1803 fits_in_unsigned_byte (offsetT num
)
1805 return (num
& 0xff) == num
;
1809 fits_in_unsigned_word (offsetT num
)
1811 return (num
& 0xffff) == num
;
1815 fits_in_signed_word (offsetT num
)
1817 return (-32768 <= num
) && (num
<= 32767);
1821 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1826 return (!(((offsetT
) -1 << 31) & num
)
1827 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1829 } /* fits_in_signed_long() */
1832 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1837 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1839 } /* fits_in_unsigned_long() */
1842 fits_in_imm4 (offsetT num
)
1844 return (num
& 0xf) == num
;
1847 static i386_operand_type
1848 smallest_imm_type (offsetT num
)
1850 i386_operand_type t
;
1852 operand_type_set (&t
, 0);
1853 t
.bitfield
.imm64
= 1;
1855 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1857 /* This code is disabled on the 486 because all the Imm1 forms
1858 in the opcode table are slower on the i486. They're the
1859 versions with the implicitly specified single-position
1860 displacement, which has another syntax if you really want to
1862 t
.bitfield
.imm1
= 1;
1863 t
.bitfield
.imm8
= 1;
1864 t
.bitfield
.imm8s
= 1;
1865 t
.bitfield
.imm16
= 1;
1866 t
.bitfield
.imm32
= 1;
1867 t
.bitfield
.imm32s
= 1;
1869 else if (fits_in_signed_byte (num
))
1871 t
.bitfield
.imm8
= 1;
1872 t
.bitfield
.imm8s
= 1;
1873 t
.bitfield
.imm16
= 1;
1874 t
.bitfield
.imm32
= 1;
1875 t
.bitfield
.imm32s
= 1;
1877 else if (fits_in_unsigned_byte (num
))
1879 t
.bitfield
.imm8
= 1;
1880 t
.bitfield
.imm16
= 1;
1881 t
.bitfield
.imm32
= 1;
1882 t
.bitfield
.imm32s
= 1;
1884 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1886 t
.bitfield
.imm16
= 1;
1887 t
.bitfield
.imm32
= 1;
1888 t
.bitfield
.imm32s
= 1;
1890 else if (fits_in_signed_long (num
))
1892 t
.bitfield
.imm32
= 1;
1893 t
.bitfield
.imm32s
= 1;
1895 else if (fits_in_unsigned_long (num
))
1896 t
.bitfield
.imm32
= 1;
1902 offset_in_range (offsetT val
, int size
)
1908 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1909 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1910 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1912 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1918 /* If BFD64, sign extend val for 32bit address mode. */
1919 if (flag_code
!= CODE_64BIT
1920 || i
.prefix
[ADDR_PREFIX
])
1921 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1922 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1925 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1927 char buf1
[40], buf2
[40];
1929 sprint_value (buf1
, val
);
1930 sprint_value (buf2
, val
& mask
);
1931 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1945 a. PREFIX_EXIST if attempting to add a prefix where one from the
1946 same class already exists.
1947 b. PREFIX_LOCK if lock prefix is added.
1948 c. PREFIX_REP if rep/repne prefix is added.
1949 d. PREFIX_OTHER if other prefix is added.
1952 static enum PREFIX_GROUP
1953 add_prefix (unsigned int prefix
)
1955 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1958 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1959 && flag_code
== CODE_64BIT
)
1961 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1962 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1963 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1974 case CS_PREFIX_OPCODE
:
1975 case DS_PREFIX_OPCODE
:
1976 case ES_PREFIX_OPCODE
:
1977 case FS_PREFIX_OPCODE
:
1978 case GS_PREFIX_OPCODE
:
1979 case SS_PREFIX_OPCODE
:
1983 case REPNE_PREFIX_OPCODE
:
1984 case REPE_PREFIX_OPCODE
:
1989 case LOCK_PREFIX_OPCODE
:
1998 case ADDR_PREFIX_OPCODE
:
2002 case DATA_PREFIX_OPCODE
:
2006 if (i
.prefix
[q
] != 0)
2014 i
.prefix
[q
] |= prefix
;
2017 as_bad (_("same type of prefix used twice"));
2023 update_code_flag (int value
, int check
)
2025 PRINTF_LIKE ((*as_error
));
2027 flag_code
= (enum flag_code
) value
;
2028 if (flag_code
== CODE_64BIT
)
2030 cpu_arch_flags
.bitfield
.cpu64
= 1;
2031 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2035 cpu_arch_flags
.bitfield
.cpu64
= 0;
2036 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2038 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2041 as_error
= as_fatal
;
2044 (*as_error
) (_("64bit mode not supported on `%s'."),
2045 cpu_arch_name
? cpu_arch_name
: default_arch
);
2047 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2050 as_error
= as_fatal
;
2053 (*as_error
) (_("32bit mode not supported on `%s'."),
2054 cpu_arch_name
? cpu_arch_name
: default_arch
);
2056 stackop_size
= '\0';
2060 set_code_flag (int value
)
2062 update_code_flag (value
, 0);
2066 set_16bit_gcc_code_flag (int new_code_flag
)
2068 flag_code
= (enum flag_code
) new_code_flag
;
2069 if (flag_code
!= CODE_16BIT
)
2071 cpu_arch_flags
.bitfield
.cpu64
= 0;
2072 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2073 stackop_size
= LONG_MNEM_SUFFIX
;
2077 set_intel_syntax (int syntax_flag
)
2079 /* Find out if register prefixing is specified. */
2080 int ask_naked_reg
= 0;
2083 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2085 char *string
= input_line_pointer
;
2086 int e
= get_symbol_end ();
2088 if (strcmp (string
, "prefix") == 0)
2090 else if (strcmp (string
, "noprefix") == 0)
2093 as_bad (_("bad argument to syntax directive."));
2094 *input_line_pointer
= e
;
2096 demand_empty_rest_of_line ();
2098 intel_syntax
= syntax_flag
;
2100 if (ask_naked_reg
== 0)
2101 allow_naked_reg
= (intel_syntax
2102 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2104 allow_naked_reg
= (ask_naked_reg
< 0);
2106 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2108 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2109 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2110 register_prefix
= allow_naked_reg
? "" : "%";
2114 set_intel_mnemonic (int mnemonic_flag
)
2116 intel_mnemonic
= mnemonic_flag
;
2120 set_allow_index_reg (int flag
)
2122 allow_index_reg
= flag
;
2126 set_check (int what
)
2128 enum check_kind
*kind
;
2133 kind
= &operand_check
;
2144 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2146 char *string
= input_line_pointer
;
2147 int e
= get_symbol_end ();
2149 if (strcmp (string
, "none") == 0)
2151 else if (strcmp (string
, "warning") == 0)
2152 *kind
= check_warning
;
2153 else if (strcmp (string
, "error") == 0)
2154 *kind
= check_error
;
2156 as_bad (_("bad argument to %s_check directive."), str
);
2157 *input_line_pointer
= e
;
2160 as_bad (_("missing argument for %s_check directive"), str
);
2162 demand_empty_rest_of_line ();
2166 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2167 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2170 static const char *arch
;
2172 /* Intel LIOM is only supported on ELF. */
2178 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2179 use default_arch. */
2180 arch
= cpu_arch_name
;
2182 arch
= default_arch
;
2185 /* If we are targeting Intel L1OM, we must enable it. */
2186 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2187 || new_flag
.bitfield
.cpul1om
)
2190 /* If we are targeting Intel K1OM, we must enable it. */
2191 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2192 || new_flag
.bitfield
.cpuk1om
)
2195 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2200 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2204 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2206 char *string
= input_line_pointer
;
2207 int e
= get_symbol_end ();
2209 i386_cpu_flags flags
;
2211 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2213 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2215 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2219 cpu_arch_name
= cpu_arch
[j
].name
;
2220 cpu_sub_arch_name
= NULL
;
2221 cpu_arch_flags
= cpu_arch
[j
].flags
;
2222 if (flag_code
== CODE_64BIT
)
2224 cpu_arch_flags
.bitfield
.cpu64
= 1;
2225 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2229 cpu_arch_flags
.bitfield
.cpu64
= 0;
2230 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2232 cpu_arch_isa
= cpu_arch
[j
].type
;
2233 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2234 if (!cpu_arch_tune_set
)
2236 cpu_arch_tune
= cpu_arch_isa
;
2237 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2242 if (!cpu_arch
[j
].negated
)
2243 flags
= cpu_flags_or (cpu_arch_flags
,
2246 flags
= cpu_flags_and_not (cpu_arch_flags
,
2248 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2250 if (cpu_sub_arch_name
)
2252 char *name
= cpu_sub_arch_name
;
2253 cpu_sub_arch_name
= concat (name
,
2255 (const char *) NULL
);
2259 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2260 cpu_arch_flags
= flags
;
2261 cpu_arch_isa_flags
= flags
;
2263 *input_line_pointer
= e
;
2264 demand_empty_rest_of_line ();
2268 if (j
>= ARRAY_SIZE (cpu_arch
))
2269 as_bad (_("no such architecture: `%s'"), string
);
2271 *input_line_pointer
= e
;
2274 as_bad (_("missing cpu architecture"));
2276 no_cond_jump_promotion
= 0;
2277 if (*input_line_pointer
== ','
2278 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2280 char *string
= ++input_line_pointer
;
2281 int e
= get_symbol_end ();
2283 if (strcmp (string
, "nojumps") == 0)
2284 no_cond_jump_promotion
= 1;
2285 else if (strcmp (string
, "jumps") == 0)
2288 as_bad (_("no such architecture modifier: `%s'"), string
);
2290 *input_line_pointer
= e
;
2293 demand_empty_rest_of_line ();
2296 enum bfd_architecture
2299 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2301 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2302 || flag_code
!= CODE_64BIT
)
2303 as_fatal (_("Intel L1OM is 64bit ELF only"));
2304 return bfd_arch_l1om
;
2306 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2308 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2309 || flag_code
!= CODE_64BIT
)
2310 as_fatal (_("Intel K1OM is 64bit ELF only"));
2311 return bfd_arch_k1om
;
2314 return bfd_arch_i386
;
2320 if (!strncmp (default_arch
, "x86_64", 6))
2322 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2324 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2325 || default_arch
[6] != '\0')
2326 as_fatal (_("Intel L1OM is 64bit ELF only"));
2327 return bfd_mach_l1om
;
2329 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2331 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2332 || default_arch
[6] != '\0')
2333 as_fatal (_("Intel K1OM is 64bit ELF only"));
2334 return bfd_mach_k1om
;
2336 else if (default_arch
[6] == '\0')
2337 return bfd_mach_x86_64
;
2339 return bfd_mach_x64_32
;
2341 else if (!strcmp (default_arch
, "i386"))
2342 return bfd_mach_i386_i386
;
2344 as_fatal (_("unknown architecture"));
2350 const char *hash_err
;
2352 /* Initialize op_hash hash table. */
2353 op_hash
= hash_new ();
2356 const insn_template
*optab
;
2357 templates
*core_optab
;
2359 /* Setup for loop. */
2361 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2362 core_optab
->start
= optab
;
2367 if (optab
->name
== NULL
2368 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2370 /* different name --> ship out current template list;
2371 add to hash table; & begin anew. */
2372 core_optab
->end
= optab
;
2373 hash_err
= hash_insert (op_hash
,
2375 (void *) core_optab
);
2378 as_fatal (_("can't hash %s: %s"),
2382 if (optab
->name
== NULL
)
2384 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2385 core_optab
->start
= optab
;
2390 /* Initialize reg_hash hash table. */
2391 reg_hash
= hash_new ();
2393 const reg_entry
*regtab
;
2394 unsigned int regtab_size
= i386_regtab_size
;
2396 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2398 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2400 as_fatal (_("can't hash %s: %s"),
2406 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2411 for (c
= 0; c
< 256; c
++)
2416 mnemonic_chars
[c
] = c
;
2417 register_chars
[c
] = c
;
2418 operand_chars
[c
] = c
;
2420 else if (ISLOWER (c
))
2422 mnemonic_chars
[c
] = c
;
2423 register_chars
[c
] = c
;
2424 operand_chars
[c
] = c
;
2426 else if (ISUPPER (c
))
2428 mnemonic_chars
[c
] = TOLOWER (c
);
2429 register_chars
[c
] = mnemonic_chars
[c
];
2430 operand_chars
[c
] = c
;
2433 if (ISALPHA (c
) || ISDIGIT (c
))
2434 identifier_chars
[c
] = c
;
2437 identifier_chars
[c
] = c
;
2438 operand_chars
[c
] = c
;
2443 identifier_chars
['@'] = '@';
2446 identifier_chars
['?'] = '?';
2447 operand_chars
['?'] = '?';
2449 digit_chars
['-'] = '-';
2450 mnemonic_chars
['_'] = '_';
2451 mnemonic_chars
['-'] = '-';
2452 mnemonic_chars
['.'] = '.';
2453 identifier_chars
['_'] = '_';
2454 identifier_chars
['.'] = '.';
2456 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2457 operand_chars
[(unsigned char) *p
] = *p
;
2460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2463 record_alignment (text_section
, 2);
2464 record_alignment (data_section
, 2);
2465 record_alignment (bss_section
, 2);
2469 if (flag_code
== CODE_64BIT
)
2471 #if defined (OBJ_COFF) && defined (TE_PE)
2472 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2475 x86_dwarf2_return_column
= 16;
2477 x86_cie_data_alignment
= -8;
2481 x86_dwarf2_return_column
= 8;
2482 x86_cie_data_alignment
= -4;
2487 i386_print_statistics (FILE *file
)
2489 hash_print_statistics (file
, "i386 opcode", op_hash
);
2490 hash_print_statistics (file
, "i386 register", reg_hash
);
2495 /* Debugging routines for md_assemble. */
2496 static void pte (insn_template
*);
2497 static void pt (i386_operand_type
);
2498 static void pe (expressionS
*);
2499 static void ps (symbolS
*);
2502 pi (char *line
, i386_insn
*x
)
2506 fprintf (stdout
, "%s: template ", line
);
2508 fprintf (stdout
, " address: base %s index %s scale %x\n",
2509 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2510 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2511 x
->log2_scale_factor
);
2512 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2513 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2514 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2515 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2516 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2517 (x
->rex
& REX_W
) != 0,
2518 (x
->rex
& REX_R
) != 0,
2519 (x
->rex
& REX_X
) != 0,
2520 (x
->rex
& REX_B
) != 0);
2521 for (j
= 0; j
< x
->operands
; j
++)
2523 fprintf (stdout
, " #%d: ", j
+ 1);
2525 fprintf (stdout
, "\n");
2526 if (x
->types
[j
].bitfield
.reg8
2527 || x
->types
[j
].bitfield
.reg16
2528 || x
->types
[j
].bitfield
.reg32
2529 || x
->types
[j
].bitfield
.reg64
2530 || x
->types
[j
].bitfield
.regmmx
2531 || x
->types
[j
].bitfield
.regxmm
2532 || x
->types
[j
].bitfield
.regymm
2533 || x
->types
[j
].bitfield
.sreg2
2534 || x
->types
[j
].bitfield
.sreg3
2535 || x
->types
[j
].bitfield
.control
2536 || x
->types
[j
].bitfield
.debug
2537 || x
->types
[j
].bitfield
.test
)
2538 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2539 if (operand_type_check (x
->types
[j
], imm
))
2541 if (operand_type_check (x
->types
[j
], disp
))
2542 pe (x
->op
[j
].disps
);
2547 pte (insn_template
*t
)
2550 fprintf (stdout
, " %d operands ", t
->operands
);
2551 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2552 if (t
->extension_opcode
!= None
)
2553 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2554 if (t
->opcode_modifier
.d
)
2555 fprintf (stdout
, "D");
2556 if (t
->opcode_modifier
.w
)
2557 fprintf (stdout
, "W");
2558 fprintf (stdout
, "\n");
2559 for (j
= 0; j
< t
->operands
; j
++)
2561 fprintf (stdout
, " #%d type ", j
+ 1);
2562 pt (t
->operand_types
[j
]);
2563 fprintf (stdout
, "\n");
2570 fprintf (stdout
, " operation %d\n", e
->X_op
);
2571 fprintf (stdout
, " add_number %ld (%lx)\n",
2572 (long) e
->X_add_number
, (long) e
->X_add_number
);
2573 if (e
->X_add_symbol
)
2575 fprintf (stdout
, " add_symbol ");
2576 ps (e
->X_add_symbol
);
2577 fprintf (stdout
, "\n");
2581 fprintf (stdout
, " op_symbol ");
2582 ps (e
->X_op_symbol
);
2583 fprintf (stdout
, "\n");
2590 fprintf (stdout
, "%s type %s%s",
2592 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2593 segment_name (S_GET_SEGMENT (s
)));
2596 static struct type_name
2598 i386_operand_type mask
;
2601 const type_names
[] =
2603 { OPERAND_TYPE_REG8
, "r8" },
2604 { OPERAND_TYPE_REG16
, "r16" },
2605 { OPERAND_TYPE_REG32
, "r32" },
2606 { OPERAND_TYPE_REG64
, "r64" },
2607 { OPERAND_TYPE_IMM8
, "i8" },
2608 { OPERAND_TYPE_IMM8
, "i8s" },
2609 { OPERAND_TYPE_IMM16
, "i16" },
2610 { OPERAND_TYPE_IMM32
, "i32" },
2611 { OPERAND_TYPE_IMM32S
, "i32s" },
2612 { OPERAND_TYPE_IMM64
, "i64" },
2613 { OPERAND_TYPE_IMM1
, "i1" },
2614 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2615 { OPERAND_TYPE_DISP8
, "d8" },
2616 { OPERAND_TYPE_DISP16
, "d16" },
2617 { OPERAND_TYPE_DISP32
, "d32" },
2618 { OPERAND_TYPE_DISP32S
, "d32s" },
2619 { OPERAND_TYPE_DISP64
, "d64" },
2620 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2621 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2622 { OPERAND_TYPE_CONTROL
, "control reg" },
2623 { OPERAND_TYPE_TEST
, "test reg" },
2624 { OPERAND_TYPE_DEBUG
, "debug reg" },
2625 { OPERAND_TYPE_FLOATREG
, "FReg" },
2626 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2627 { OPERAND_TYPE_SREG2
, "SReg2" },
2628 { OPERAND_TYPE_SREG3
, "SReg3" },
2629 { OPERAND_TYPE_ACC
, "Acc" },
2630 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2631 { OPERAND_TYPE_REGMMX
, "rMMX" },
2632 { OPERAND_TYPE_REGXMM
, "rXMM" },
2633 { OPERAND_TYPE_REGYMM
, "rYMM" },
2634 { OPERAND_TYPE_ESSEG
, "es" },
2638 pt (i386_operand_type t
)
2641 i386_operand_type a
;
2643 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2645 a
= operand_type_and (t
, type_names
[j
].mask
);
2646 if (!operand_type_all_zero (&a
))
2647 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2652 #endif /* DEBUG386 */
2654 static bfd_reloc_code_real_type
2655 reloc (unsigned int size
,
2658 bfd_reloc_code_real_type other
)
2660 if (other
!= NO_RELOC
)
2662 reloc_howto_type
*rel
;
2667 case BFD_RELOC_X86_64_GOT32
:
2668 return BFD_RELOC_X86_64_GOT64
;
2670 case BFD_RELOC_X86_64_PLTOFF64
:
2671 return BFD_RELOC_X86_64_PLTOFF64
;
2673 case BFD_RELOC_X86_64_GOTPC32
:
2674 other
= BFD_RELOC_X86_64_GOTPC64
;
2676 case BFD_RELOC_X86_64_GOTPCREL
:
2677 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2679 case BFD_RELOC_X86_64_TPOFF32
:
2680 other
= BFD_RELOC_X86_64_TPOFF64
;
2682 case BFD_RELOC_X86_64_DTPOFF32
:
2683 other
= BFD_RELOC_X86_64_DTPOFF64
;
2689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2690 if (other
== BFD_RELOC_SIZE32
)
2693 return BFD_RELOC_SIZE64
;
2695 as_bad (_("there are no pc-relative size relocations"));
2699 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2700 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2703 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2705 as_bad (_("unknown relocation (%u)"), other
);
2706 else if (size
!= bfd_get_reloc_size (rel
))
2707 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2708 bfd_get_reloc_size (rel
),
2710 else if (pcrel
&& !rel
->pc_relative
)
2711 as_bad (_("non-pc-relative relocation for pc-relative field"));
2712 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2714 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2716 as_bad (_("relocated field and relocation type differ in signedness"));
2725 as_bad (_("there are no unsigned pc-relative relocations"));
2728 case 1: return BFD_RELOC_8_PCREL
;
2729 case 2: return BFD_RELOC_16_PCREL
;
2730 case 4: return BFD_RELOC_32_PCREL
;
2731 case 8: return BFD_RELOC_64_PCREL
;
2733 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2740 case 4: return BFD_RELOC_X86_64_32S
;
2745 case 1: return BFD_RELOC_8
;
2746 case 2: return BFD_RELOC_16
;
2747 case 4: return BFD_RELOC_32
;
2748 case 8: return BFD_RELOC_64
;
2750 as_bad (_("cannot do %s %u byte relocation"),
2751 sign
> 0 ? "signed" : "unsigned", size
);
2757 /* Here we decide which fixups can be adjusted to make them relative to
2758 the beginning of the section instead of the symbol. Basically we need
2759 to make sure that the dynamic relocations are done correctly, so in
2760 some cases we force the original symbol to be used. */
2763 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2769 /* Don't adjust pc-relative references to merge sections in 64-bit
2771 if (use_rela_relocations
2772 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2776 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2777 and changed later by validate_fix. */
2778 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2779 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2782 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2783 for size relocations. */
2784 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2785 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2786 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2787 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2788 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2789 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2790 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2791 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2792 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2793 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2794 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2795 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2796 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2797 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2798 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2799 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2800 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2801 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2802 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2803 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2804 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2805 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2806 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2807 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2808 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2809 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2810 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2811 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2812 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2813 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2820 intel_float_operand (const char *mnemonic
)
2822 /* Note that the value returned is meaningful only for opcodes with (memory)
2823 operands, hence the code here is free to improperly handle opcodes that
2824 have no operands (for better performance and smaller code). */
2826 if (mnemonic
[0] != 'f')
2827 return 0; /* non-math */
2829 switch (mnemonic
[1])
2831 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2832 the fs segment override prefix not currently handled because no
2833 call path can make opcodes without operands get here */
2835 return 2 /* integer op */;
2837 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2838 return 3; /* fldcw/fldenv */
2841 if (mnemonic
[2] != 'o' /* fnop */)
2842 return 3; /* non-waiting control op */
2845 if (mnemonic
[2] == 's')
2846 return 3; /* frstor/frstpm */
2849 if (mnemonic
[2] == 'a')
2850 return 3; /* fsave */
2851 if (mnemonic
[2] == 't')
2853 switch (mnemonic
[3])
2855 case 'c': /* fstcw */
2856 case 'd': /* fstdw */
2857 case 'e': /* fstenv */
2858 case 's': /* fsts[gw] */
2864 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2865 return 0; /* fxsave/fxrstor are not really math ops */
2872 /* Build the VEX prefix. */
2875 build_vex_prefix (const insn_template
*t
)
2877 unsigned int register_specifier
;
2878 unsigned int implied_prefix
;
2879 unsigned int vector_length
;
2881 /* Check register specifier. */
2882 if (i
.vex
.register_specifier
)
2883 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2885 register_specifier
= 0xf;
2887 /* Use 2-byte VEX prefix by swappping destination and source
2890 && i
.operands
== i
.reg_operands
2891 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2892 && i
.tm
.opcode_modifier
.s
2895 unsigned int xchg
= i
.operands
- 1;
2896 union i386_op temp_op
;
2897 i386_operand_type temp_type
;
2899 temp_type
= i
.types
[xchg
];
2900 i
.types
[xchg
] = i
.types
[0];
2901 i
.types
[0] = temp_type
;
2902 temp_op
= i
.op
[xchg
];
2903 i
.op
[xchg
] = i
.op
[0];
2906 gas_assert (i
.rm
.mode
== 3);
2910 i
.rm
.regmem
= i
.rm
.reg
;
2913 /* Use the next insn. */
2917 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2918 vector_length
= avxscalar
;
2920 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2922 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2927 case DATA_PREFIX_OPCODE
:
2930 case REPE_PREFIX_OPCODE
:
2933 case REPNE_PREFIX_OPCODE
:
2940 /* Use 2-byte VEX prefix if possible. */
2941 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2942 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2943 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2945 /* 2-byte VEX prefix. */
2949 i
.vex
.bytes
[0] = 0xc5;
2951 /* Check the REX.R bit. */
2952 r
= (i
.rex
& REX_R
) ? 0 : 1;
2953 i
.vex
.bytes
[1] = (r
<< 7
2954 | register_specifier
<< 3
2955 | vector_length
<< 2
2960 /* 3-byte VEX prefix. */
2965 switch (i
.tm
.opcode_modifier
.vexopcode
)
2969 i
.vex
.bytes
[0] = 0xc4;
2973 i
.vex
.bytes
[0] = 0xc4;
2977 i
.vex
.bytes
[0] = 0xc4;
2981 i
.vex
.bytes
[0] = 0x8f;
2985 i
.vex
.bytes
[0] = 0x8f;
2989 i
.vex
.bytes
[0] = 0x8f;
2995 /* The high 3 bits of the second VEX byte are 1's compliment
2996 of RXB bits from REX. */
2997 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2999 /* Check the REX.W bit. */
3000 w
= (i
.rex
& REX_W
) ? 1 : 0;
3001 if (i
.tm
.opcode_modifier
.vexw
)
3006 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3010 i
.vex
.bytes
[2] = (w
<< 7
3011 | register_specifier
<< 3
3012 | vector_length
<< 2
3018 process_immext (void)
3022 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3025 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3026 with an opcode suffix which is coded in the same place as an
3027 8-bit immediate field would be.
3028 Here we check those operands and remove them afterwards. */
3031 for (x
= 0; x
< i
.operands
; x
++)
3032 if (register_number (i
.op
[x
].regs
) != x
)
3033 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3034 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3040 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3041 which is coded in the same place as an 8-bit immediate field
3042 would be. Here we fake an 8-bit immediate operand from the
3043 opcode suffix stored in tm.extension_opcode.
3045 AVX instructions also use this encoding, for some of
3046 3 argument instructions. */
3048 gas_assert (i
.imm_operands
== 0
3050 || (i
.tm
.opcode_modifier
.vex
3051 && i
.operands
<= 4)));
3053 exp
= &im_expressions
[i
.imm_operands
++];
3054 i
.op
[i
.operands
].imms
= exp
;
3055 i
.types
[i
.operands
] = imm8
;
3057 exp
->X_op
= O_constant
;
3058 exp
->X_add_number
= i
.tm
.extension_opcode
;
3059 i
.tm
.extension_opcode
= None
;
3066 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3071 if (i
.prefix
[HLE_PREFIX
] == XACQUIRE_PREFIX_OPCODE
)
3072 as_bad (_("invalid instruction `%s' after `xacquire'"),
3075 as_bad (_("invalid instruction `%s' after `xrelease'"),
3079 if (i
.prefix
[LOCK_PREFIX
])
3081 if (i
.prefix
[HLE_PREFIX
] == XACQUIRE_PREFIX_OPCODE
)
3082 as_bad (_("missing `lock' with `xacquire'"));
3084 as_bad (_("missing `lock' with `xrelease'"));
3088 case HLEPrefixRelease
:
3089 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3091 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3095 if (i
.mem_operands
== 0
3096 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3098 as_bad (_("memory destination needed for instruction `%s'"
3099 " after `xrelease'"), i
.tm
.name
);
3106 /* This is the guts of the machine-dependent assembler. LINE points to a
3107 machine dependent instruction. This function is supposed to emit
3108 the frags/bytes it assembles to. */
3111 md_assemble (char *line
)
3114 char mnemonic
[MAX_MNEM_SIZE
];
3115 const insn_template
*t
;
3117 /* Initialize globals. */
3118 memset (&i
, '\0', sizeof (i
));
3119 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3120 i
.reloc
[j
] = NO_RELOC
;
3121 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3122 memset (im_expressions
, '\0', sizeof (im_expressions
));
3123 save_stack_p
= save_stack
;
3125 /* First parse an instruction mnemonic & call i386_operand for the operands.
3126 We assume that the scrubber has arranged it so that line[0] is the valid
3127 start of a (possibly prefixed) mnemonic. */
3129 line
= parse_insn (line
, mnemonic
);
3133 line
= parse_operands (line
, mnemonic
);
3138 /* Now we've parsed the mnemonic into a set of templates, and have the
3139 operands at hand. */
3141 /* All intel opcodes have reversed operands except for "bound" and
3142 "enter". We also don't reverse intersegment "jmp" and "call"
3143 instructions with 2 immediate operands so that the immediate segment
3144 precedes the offset, as it does when in AT&T mode. */
3147 && (strcmp (mnemonic
, "bound") != 0)
3148 && (strcmp (mnemonic
, "invlpga") != 0)
3149 && !(operand_type_check (i
.types
[0], imm
)
3150 && operand_type_check (i
.types
[1], imm
)))
3153 /* The order of the immediates should be reversed
3154 for 2 immediates extrq and insertq instructions */
3155 if (i
.imm_operands
== 2
3156 && (strcmp (mnemonic
, "extrq") == 0
3157 || strcmp (mnemonic
, "insertq") == 0))
3158 swap_2_operands (0, 1);
3163 /* Don't optimize displacement for movabs since it only takes 64bit
3166 && i
.disp_encoding
!= disp_encoding_32bit
3167 && (flag_code
!= CODE_64BIT
3168 || strcmp (mnemonic
, "movabs") != 0))
3171 /* Next, we find a template that matches the given insn,
3172 making sure the overlap of the given operands types is consistent
3173 with the template operand types. */
3175 if (!(t
= match_template ()))
3178 if (sse_check
!= check_none
3179 && !i
.tm
.opcode_modifier
.noavx
3180 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3181 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3182 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3183 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3184 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3185 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3187 (sse_check
== check_warning
3189 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3192 /* Zap movzx and movsx suffix. The suffix has been set from
3193 "word ptr" or "byte ptr" on the source operand in Intel syntax
3194 or extracted from mnemonic in AT&T syntax. But we'll use
3195 the destination register to choose the suffix for encoding. */
3196 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3198 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3199 there is no suffix, the default will be byte extension. */
3200 if (i
.reg_operands
!= 2
3203 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3208 if (i
.tm
.opcode_modifier
.fwait
)
3209 if (!add_prefix (FWAIT_OPCODE
))
3212 /* Check for lock without a lockable instruction. Destination operand
3213 must be memory unless it is xchg (0x86). */
3214 if (i
.prefix
[LOCK_PREFIX
]
3215 && (!i
.tm
.opcode_modifier
.islockable
3216 || i
.mem_operands
== 0
3217 || (i
.tm
.base_opcode
!= 0x86
3218 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3220 as_bad (_("expecting lockable instruction after `lock'"));
3224 /* Check if HLE prefix is OK. */
3225 if (i
.have_hle
&& !check_hle ())
3228 /* Check string instruction segment overrides. */
3229 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3231 if (!check_string ())
3233 i
.disp_operands
= 0;
3236 if (!process_suffix ())
3239 /* Update operand types. */
3240 for (j
= 0; j
< i
.operands
; j
++)
3241 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3243 /* Make still unresolved immediate matches conform to size of immediate
3244 given in i.suffix. */
3245 if (!finalize_imm ())
3248 if (i
.types
[0].bitfield
.imm1
)
3249 i
.imm_operands
= 0; /* kludge for shift insns. */
3251 /* We only need to check those implicit registers for instructions
3252 with 3 operands or less. */
3253 if (i
.operands
<= 3)
3254 for (j
= 0; j
< i
.operands
; j
++)
3255 if (i
.types
[j
].bitfield
.inoutportreg
3256 || i
.types
[j
].bitfield
.shiftcount
3257 || i
.types
[j
].bitfield
.acc
3258 || i
.types
[j
].bitfield
.floatacc
)
3261 /* ImmExt should be processed after SSE2AVX. */
3262 if (!i
.tm
.opcode_modifier
.sse2avx
3263 && i
.tm
.opcode_modifier
.immext
)
3266 /* For insns with operands there are more diddles to do to the opcode. */
3269 if (!process_operands ())
3272 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3274 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3275 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3278 if (i
.tm
.opcode_modifier
.vex
)
3279 build_vex_prefix (t
);
3281 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3282 instructions may define INT_OPCODE as well, so avoid this corner
3283 case for those instructions that use MODRM. */
3284 if (i
.tm
.base_opcode
== INT_OPCODE
3285 && !i
.tm
.opcode_modifier
.modrm
3286 && i
.op
[0].imms
->X_add_number
== 3)
3288 i
.tm
.base_opcode
= INT3_OPCODE
;
3292 if ((i
.tm
.opcode_modifier
.jump
3293 || i
.tm
.opcode_modifier
.jumpbyte
3294 || i
.tm
.opcode_modifier
.jumpdword
)
3295 && i
.op
[0].disps
->X_op
== O_constant
)
3297 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3298 the absolute address given by the constant. Since ix86 jumps and
3299 calls are pc relative, we need to generate a reloc. */
3300 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3301 i
.op
[0].disps
->X_op
= O_symbol
;
3304 if (i
.tm
.opcode_modifier
.rex64
)
3307 /* For 8 bit registers we need an empty rex prefix. Also if the
3308 instruction already has a prefix, we need to convert old
3309 registers to new ones. */
3311 if ((i
.types
[0].bitfield
.reg8
3312 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3313 || (i
.types
[1].bitfield
.reg8
3314 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3315 || ((i
.types
[0].bitfield
.reg8
3316 || i
.types
[1].bitfield
.reg8
)
3321 i
.rex
|= REX_OPCODE
;
3322 for (x
= 0; x
< 2; x
++)
3324 /* Look for 8 bit operand that uses old registers. */
3325 if (i
.types
[x
].bitfield
.reg8
3326 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3328 /* In case it is "hi" register, give up. */
3329 if (i
.op
[x
].regs
->reg_num
> 3)
3330 as_bad (_("can't encode register '%s%s' in an "
3331 "instruction requiring REX prefix."),
3332 register_prefix
, i
.op
[x
].regs
->reg_name
);
3334 /* Otherwise it is equivalent to the extended register.
3335 Since the encoding doesn't change this is merely
3336 cosmetic cleanup for debug output. */
3338 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3344 add_prefix (REX_OPCODE
| i
.rex
);
3346 /* We are ready to output the insn. */
3351 parse_insn (char *line
, char *mnemonic
)
3354 char *token_start
= l
;
3357 const insn_template
*t
;
3360 /* Non-zero if we found a prefix only acceptable with string insns. */
3361 const char *expecting_string_instruction
= NULL
;
3366 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3371 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3373 as_bad (_("no such instruction: `%s'"), token_start
);
3378 if (!is_space_char (*l
)
3379 && *l
!= END_OF_INSN
3381 || (*l
!= PREFIX_SEPARATOR
3384 as_bad (_("invalid character %s in mnemonic"),
3385 output_invalid (*l
));
3388 if (token_start
== l
)
3390 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3391 as_bad (_("expecting prefix; got nothing"));
3393 as_bad (_("expecting mnemonic; got nothing"));
3397 /* Look up instruction (or prefix) via hash table. */
3398 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3400 if (*l
!= END_OF_INSN
3401 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3402 && current_templates
3403 && current_templates
->start
->opcode_modifier
.isprefix
)
3405 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3407 as_bad ((flag_code
!= CODE_64BIT
3408 ? _("`%s' is only supported in 64-bit mode")
3409 : _("`%s' is not supported in 64-bit mode")),
3410 current_templates
->start
->name
);
3413 /* If we are in 16-bit mode, do not allow addr16 or data16.
3414 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3415 if ((current_templates
->start
->opcode_modifier
.size16
3416 || current_templates
->start
->opcode_modifier
.size32
)
3417 && flag_code
!= CODE_64BIT
3418 && (current_templates
->start
->opcode_modifier
.size32
3419 ^ (flag_code
== CODE_16BIT
)))
3421 as_bad (_("redundant %s prefix"),
3422 current_templates
->start
->name
);
3425 /* Add prefix, checking for repeated prefixes. */
3426 switch (add_prefix (current_templates
->start
->base_opcode
))
3431 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3434 expecting_string_instruction
= current_templates
->start
->name
;
3439 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3446 if (!current_templates
)
3448 /* Check if we should swap operand or force 32bit displacement in
3450 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3452 else if (mnem_p
- 3 == dot_p
3455 i
.disp_encoding
= disp_encoding_8bit
;
3456 else if (mnem_p
- 4 == dot_p
3460 i
.disp_encoding
= disp_encoding_32bit
;
3465 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3468 if (!current_templates
)
3471 /* See if we can get a match by trimming off a suffix. */
3474 case WORD_MNEM_SUFFIX
:
3475 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3476 i
.suffix
= SHORT_MNEM_SUFFIX
;
3478 case BYTE_MNEM_SUFFIX
:
3479 case QWORD_MNEM_SUFFIX
:
3480 i
.suffix
= mnem_p
[-1];
3482 current_templates
= (const templates
*) hash_find (op_hash
,
3485 case SHORT_MNEM_SUFFIX
:
3486 case LONG_MNEM_SUFFIX
:
3489 i
.suffix
= mnem_p
[-1];
3491 current_templates
= (const templates
*) hash_find (op_hash
,
3500 if (intel_float_operand (mnemonic
) == 1)
3501 i
.suffix
= SHORT_MNEM_SUFFIX
;
3503 i
.suffix
= LONG_MNEM_SUFFIX
;
3505 current_templates
= (const templates
*) hash_find (op_hash
,
3510 if (!current_templates
)
3512 as_bad (_("no such instruction: `%s'"), token_start
);
3517 if (current_templates
->start
->opcode_modifier
.jump
3518 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3520 /* Check for a branch hint. We allow ",pt" and ",pn" for
3521 predict taken and predict not taken respectively.
3522 I'm not sure that branch hints actually do anything on loop
3523 and jcxz insns (JumpByte) for current Pentium4 chips. They
3524 may work in the future and it doesn't hurt to accept them
3526 if (l
[0] == ',' && l
[1] == 'p')
3530 if (!add_prefix (DS_PREFIX_OPCODE
))
3534 else if (l
[2] == 'n')
3536 if (!add_prefix (CS_PREFIX_OPCODE
))
3542 /* Any other comma loses. */
3545 as_bad (_("invalid character %s in mnemonic"),
3546 output_invalid (*l
));
3550 /* Check if instruction is supported on specified architecture. */
3552 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3554 supported
|= cpu_flags_match (t
);
3555 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3559 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3561 as_bad (flag_code
== CODE_64BIT
3562 ? _("`%s' is not supported in 64-bit mode")
3563 : _("`%s' is only supported in 64-bit mode"),
3564 current_templates
->start
->name
);
3567 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3569 as_bad (_("`%s' is not supported on `%s%s'"),
3570 current_templates
->start
->name
,
3571 cpu_arch_name
? cpu_arch_name
: default_arch
,
3572 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3577 if (!cpu_arch_flags
.bitfield
.cpui386
3578 && (flag_code
!= CODE_16BIT
))
3580 as_warn (_("use .code16 to ensure correct addressing mode"));
3583 /* Check for rep/repne without a string (or other allowed) instruction. */
3584 if (expecting_string_instruction
)
3586 static templates override
;
3588 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3589 if (t
->opcode_modifier
.repprefixok
)
3591 if (t
>= current_templates
->end
)
3593 as_bad (_("expecting string instruction after `%s'"),
3594 expecting_string_instruction
);
3597 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3598 if (!t
->opcode_modifier
.repprefixok
)
3601 current_templates
= &override
;
3608 parse_operands (char *l
, const char *mnemonic
)
3612 /* 1 if operand is pending after ','. */
3613 unsigned int expecting_operand
= 0;
3615 /* Non-zero if operand parens not balanced. */
3616 unsigned int paren_not_balanced
;
3618 while (*l
!= END_OF_INSN
)
3620 /* Skip optional white space before operand. */
3621 if (is_space_char (*l
))
3623 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3625 as_bad (_("invalid character %s before operand %d"),
3626 output_invalid (*l
),
3630 token_start
= l
; /* after white space */
3631 paren_not_balanced
= 0;
3632 while (paren_not_balanced
|| *l
!= ',')
3634 if (*l
== END_OF_INSN
)
3636 if (paren_not_balanced
)
3639 as_bad (_("unbalanced parenthesis in operand %d."),
3642 as_bad (_("unbalanced brackets in operand %d."),
3647 break; /* we are done */
3649 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3651 as_bad (_("invalid character %s in operand %d"),
3652 output_invalid (*l
),
3659 ++paren_not_balanced
;
3661 --paren_not_balanced
;
3666 ++paren_not_balanced
;
3668 --paren_not_balanced
;
3672 if (l
!= token_start
)
3673 { /* Yes, we've read in another operand. */
3674 unsigned int operand_ok
;
3675 this_operand
= i
.operands
++;
3676 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3677 if (i
.operands
> MAX_OPERANDS
)
3679 as_bad (_("spurious operands; (%d operands/instruction max)"),
3683 /* Now parse operand adding info to 'i' as we go along. */
3684 END_STRING_AND_SAVE (l
);
3688 i386_intel_operand (token_start
,
3689 intel_float_operand (mnemonic
));
3691 operand_ok
= i386_att_operand (token_start
);
3693 RESTORE_END_STRING (l
);
3699 if (expecting_operand
)
3701 expecting_operand_after_comma
:
3702 as_bad (_("expecting operand after ','; got nothing"));
3707 as_bad (_("expecting operand before ','; got nothing"));
3712 /* Now *l must be either ',' or END_OF_INSN. */
3715 if (*++l
== END_OF_INSN
)
3717 /* Just skip it, if it's \n complain. */
3718 goto expecting_operand_after_comma
;
3720 expecting_operand
= 1;
3727 swap_2_operands (int xchg1
, int xchg2
)
3729 union i386_op temp_op
;
3730 i386_operand_type temp_type
;
3731 enum bfd_reloc_code_real temp_reloc
;
3733 temp_type
= i
.types
[xchg2
];
3734 i
.types
[xchg2
] = i
.types
[xchg1
];
3735 i
.types
[xchg1
] = temp_type
;
3736 temp_op
= i
.op
[xchg2
];
3737 i
.op
[xchg2
] = i
.op
[xchg1
];
3738 i
.op
[xchg1
] = temp_op
;
3739 temp_reloc
= i
.reloc
[xchg2
];
3740 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3741 i
.reloc
[xchg1
] = temp_reloc
;
3745 swap_operands (void)
3751 swap_2_operands (1, i
.operands
- 2);
3754 swap_2_operands (0, i
.operands
- 1);
3760 if (i
.mem_operands
== 2)
3762 const seg_entry
*temp_seg
;
3763 temp_seg
= i
.seg
[0];
3764 i
.seg
[0] = i
.seg
[1];
3765 i
.seg
[1] = temp_seg
;
3769 /* Try to ensure constant immediates are represented in the smallest
3774 char guess_suffix
= 0;
3778 guess_suffix
= i
.suffix
;
3779 else if (i
.reg_operands
)
3781 /* Figure out a suffix from the last register operand specified.
3782 We can't do this properly yet, ie. excluding InOutPortReg,
3783 but the following works for instructions with immediates.
3784 In any case, we can't set i.suffix yet. */
3785 for (op
= i
.operands
; --op
>= 0;)
3786 if (i
.types
[op
].bitfield
.reg8
)
3788 guess_suffix
= BYTE_MNEM_SUFFIX
;
3791 else if (i
.types
[op
].bitfield
.reg16
)
3793 guess_suffix
= WORD_MNEM_SUFFIX
;
3796 else if (i
.types
[op
].bitfield
.reg32
)
3798 guess_suffix
= LONG_MNEM_SUFFIX
;
3801 else if (i
.types
[op
].bitfield
.reg64
)
3803 guess_suffix
= QWORD_MNEM_SUFFIX
;
3807 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3808 guess_suffix
= WORD_MNEM_SUFFIX
;
3810 for (op
= i
.operands
; --op
>= 0;)
3811 if (operand_type_check (i
.types
[op
], imm
))
3813 switch (i
.op
[op
].imms
->X_op
)
3816 /* If a suffix is given, this operand may be shortened. */
3817 switch (guess_suffix
)
3819 case LONG_MNEM_SUFFIX
:
3820 i
.types
[op
].bitfield
.imm32
= 1;
3821 i
.types
[op
].bitfield
.imm64
= 1;
3823 case WORD_MNEM_SUFFIX
:
3824 i
.types
[op
].bitfield
.imm16
= 1;
3825 i
.types
[op
].bitfield
.imm32
= 1;
3826 i
.types
[op
].bitfield
.imm32s
= 1;
3827 i
.types
[op
].bitfield
.imm64
= 1;
3829 case BYTE_MNEM_SUFFIX
:
3830 i
.types
[op
].bitfield
.imm8
= 1;
3831 i
.types
[op
].bitfield
.imm8s
= 1;
3832 i
.types
[op
].bitfield
.imm16
= 1;
3833 i
.types
[op
].bitfield
.imm32
= 1;
3834 i
.types
[op
].bitfield
.imm32s
= 1;
3835 i
.types
[op
].bitfield
.imm64
= 1;
3839 /* If this operand is at most 16 bits, convert it
3840 to a signed 16 bit number before trying to see
3841 whether it will fit in an even smaller size.
3842 This allows a 16-bit operand such as $0xffe0 to
3843 be recognised as within Imm8S range. */
3844 if ((i
.types
[op
].bitfield
.imm16
)
3845 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3847 i
.op
[op
].imms
->X_add_number
=
3848 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3850 if ((i
.types
[op
].bitfield
.imm32
)
3851 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3854 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3855 ^ ((offsetT
) 1 << 31))
3856 - ((offsetT
) 1 << 31));
3859 = operand_type_or (i
.types
[op
],
3860 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3862 /* We must avoid matching of Imm32 templates when 64bit
3863 only immediate is available. */
3864 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3865 i
.types
[op
].bitfield
.imm32
= 0;
3872 /* Symbols and expressions. */
3874 /* Convert symbolic operand to proper sizes for matching, but don't
3875 prevent matching a set of insns that only supports sizes other
3876 than those matching the insn suffix. */
3878 i386_operand_type mask
, allowed
;
3879 const insn_template
*t
;
3881 operand_type_set (&mask
, 0);
3882 operand_type_set (&allowed
, 0);
3884 for (t
= current_templates
->start
;
3885 t
< current_templates
->end
;
3887 allowed
= operand_type_or (allowed
,
3888 t
->operand_types
[op
]);
3889 switch (guess_suffix
)
3891 case QWORD_MNEM_SUFFIX
:
3892 mask
.bitfield
.imm64
= 1;
3893 mask
.bitfield
.imm32s
= 1;
3895 case LONG_MNEM_SUFFIX
:
3896 mask
.bitfield
.imm32
= 1;
3898 case WORD_MNEM_SUFFIX
:
3899 mask
.bitfield
.imm16
= 1;
3901 case BYTE_MNEM_SUFFIX
:
3902 mask
.bitfield
.imm8
= 1;
3907 allowed
= operand_type_and (mask
, allowed
);
3908 if (!operand_type_all_zero (&allowed
))
3909 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3916 /* Try to use the smallest displacement type too. */
3918 optimize_disp (void)
3922 for (op
= i
.operands
; --op
>= 0;)
3923 if (operand_type_check (i
.types
[op
], disp
))
3925 if (i
.op
[op
].disps
->X_op
== O_constant
)
3927 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3929 if (i
.types
[op
].bitfield
.disp16
3930 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3932 /* If this operand is at most 16 bits, convert
3933 to a signed 16 bit number and don't use 64bit
3935 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3936 i
.types
[op
].bitfield
.disp64
= 0;
3938 if (i
.types
[op
].bitfield
.disp32
3939 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3941 /* If this operand is at most 32 bits, convert
3942 to a signed 32 bit number and don't use 64bit
3944 op_disp
&= (((offsetT
) 2 << 31) - 1);
3945 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3946 i
.types
[op
].bitfield
.disp64
= 0;
3948 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3950 i
.types
[op
].bitfield
.disp8
= 0;
3951 i
.types
[op
].bitfield
.disp16
= 0;
3952 i
.types
[op
].bitfield
.disp32
= 0;
3953 i
.types
[op
].bitfield
.disp32s
= 0;
3954 i
.types
[op
].bitfield
.disp64
= 0;
3958 else if (flag_code
== CODE_64BIT
)
3960 if (fits_in_signed_long (op_disp
))
3962 i
.types
[op
].bitfield
.disp64
= 0;
3963 i
.types
[op
].bitfield
.disp32s
= 1;
3965 if (i
.prefix
[ADDR_PREFIX
]
3966 && fits_in_unsigned_long (op_disp
))
3967 i
.types
[op
].bitfield
.disp32
= 1;
3969 if ((i
.types
[op
].bitfield
.disp32
3970 || i
.types
[op
].bitfield
.disp32s
3971 || i
.types
[op
].bitfield
.disp16
)
3972 && fits_in_signed_byte (op_disp
))
3973 i
.types
[op
].bitfield
.disp8
= 1;
3975 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3976 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3978 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3979 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3980 i
.types
[op
].bitfield
.disp8
= 0;
3981 i
.types
[op
].bitfield
.disp16
= 0;
3982 i
.types
[op
].bitfield
.disp32
= 0;
3983 i
.types
[op
].bitfield
.disp32s
= 0;
3984 i
.types
[op
].bitfield
.disp64
= 0;
3987 /* We only support 64bit displacement on constants. */
3988 i
.types
[op
].bitfield
.disp64
= 0;
3992 /* Check if operands are valid for the instruction. */
3995 check_VecOperands (const insn_template
*t
)
3997 /* Without VSIB byte, we can't have a vector register for index. */
3998 if (!t
->opcode_modifier
.vecsib
4000 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4001 || i
.index_reg
->reg_type
.bitfield
.regymm
))
4003 i
.error
= unsupported_vector_index_register
;
4007 /* For VSIB byte, we need a vector register for index, and all vector
4008 registers must be distinct. */
4009 if (t
->opcode_modifier
.vecsib
)
4012 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4013 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4014 || (t
->opcode_modifier
.vecsib
== VecSIB256
4015 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
4017 i
.error
= invalid_vsib_address
;
4021 gas_assert (i
.reg_operands
== 2);
4022 gas_assert (i
.types
[0].bitfield
.regxmm
4023 || i
.types
[0].bitfield
.regymm
);
4024 gas_assert (i
.types
[2].bitfield
.regxmm
4025 || i
.types
[2].bitfield
.regymm
);
4027 if (operand_check
== check_none
)
4029 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
4030 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
4031 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
4033 if (operand_check
== check_error
)
4035 i
.error
= invalid_vector_register_set
;
4038 as_warn (_("mask, index, and destination registers should be distinct"));
4044 /* Check if operands are valid for the instruction. Update VEX
4048 VEX_check_operands (const insn_template
*t
)
4050 if (!t
->opcode_modifier
.vex
)
4053 /* Only check VEX_Imm4, which must be the first operand. */
4054 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4056 if (i
.op
[0].imms
->X_op
!= O_constant
4057 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4063 /* Turn off Imm8 so that update_imm won't complain. */
4064 i
.types
[0] = vec_imm4
;
4070 static const insn_template
*
4071 match_template (void)
4073 /* Points to template once we've found it. */
4074 const insn_template
*t
;
4075 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4076 i386_operand_type overlap4
;
4077 unsigned int found_reverse_match
;
4078 i386_opcode_modifier suffix_check
;
4079 i386_operand_type operand_types
[MAX_OPERANDS
];
4080 int addr_prefix_disp
;
4082 unsigned int found_cpu_match
;
4083 unsigned int check_register
;
4084 enum i386_error specific_error
= 0;
4086 #if MAX_OPERANDS != 5
4087 # error "MAX_OPERANDS must be 5."
4090 found_reverse_match
= 0;
4091 addr_prefix_disp
= -1;
4093 memset (&suffix_check
, 0, sizeof (suffix_check
));
4094 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4095 suffix_check
.no_bsuf
= 1;
4096 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4097 suffix_check
.no_wsuf
= 1;
4098 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4099 suffix_check
.no_ssuf
= 1;
4100 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4101 suffix_check
.no_lsuf
= 1;
4102 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4103 suffix_check
.no_qsuf
= 1;
4104 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4105 suffix_check
.no_ldsuf
= 1;
4107 /* Must have right number of operands. */
4108 i
.error
= number_of_operands_mismatch
;
4110 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4112 addr_prefix_disp
= -1;
4114 if (i
.operands
!= t
->operands
)
4117 /* Check processor support. */
4118 i
.error
= unsupported
;
4119 found_cpu_match
= (cpu_flags_match (t
)
4120 == CPU_FLAGS_PERFECT_MATCH
);
4121 if (!found_cpu_match
)
4124 /* Check old gcc support. */
4125 i
.error
= old_gcc_only
;
4126 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4129 /* Check AT&T mnemonic. */
4130 i
.error
= unsupported_with_intel_mnemonic
;
4131 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4134 /* Check AT&T/Intel syntax. */
4135 i
.error
= unsupported_syntax
;
4136 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4137 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4140 /* Check the suffix, except for some instructions in intel mode. */
4141 i
.error
= invalid_instruction_suffix
;
4142 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4143 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4144 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4145 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4146 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4147 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4148 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4151 if (!operand_size_match (t
))
4154 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4155 operand_types
[j
] = t
->operand_types
[j
];
4157 /* In general, don't allow 64-bit operands in 32-bit mode. */
4158 if (i
.suffix
== QWORD_MNEM_SUFFIX
4159 && flag_code
!= CODE_64BIT
4161 ? (!t
->opcode_modifier
.ignoresize
4162 && !intel_float_operand (t
->name
))
4163 : intel_float_operand (t
->name
) != 2)
4164 && ((!operand_types
[0].bitfield
.regmmx
4165 && !operand_types
[0].bitfield
.regxmm
4166 && !operand_types
[0].bitfield
.regymm
)
4167 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4168 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4169 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4170 && (t
->base_opcode
!= 0x0fc7
4171 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4174 /* In general, don't allow 32-bit operands on pre-386. */
4175 else if (i
.suffix
== LONG_MNEM_SUFFIX
4176 && !cpu_arch_flags
.bitfield
.cpui386
4178 ? (!t
->opcode_modifier
.ignoresize
4179 && !intel_float_operand (t
->name
))
4180 : intel_float_operand (t
->name
) != 2)
4181 && ((!operand_types
[0].bitfield
.regmmx
4182 && !operand_types
[0].bitfield
.regxmm
)
4183 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4184 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4187 /* Do not verify operands when there are none. */
4191 /* We've found a match; break out of loop. */
4195 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4196 into Disp32/Disp16/Disp32 operand. */
4197 if (i
.prefix
[ADDR_PREFIX
] != 0)
4199 /* There should be only one Disp operand. */
4203 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4205 if (operand_types
[j
].bitfield
.disp16
)
4207 addr_prefix_disp
= j
;
4208 operand_types
[j
].bitfield
.disp32
= 1;
4209 operand_types
[j
].bitfield
.disp16
= 0;
4215 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4217 if (operand_types
[j
].bitfield
.disp32
)
4219 addr_prefix_disp
= j
;
4220 operand_types
[j
].bitfield
.disp32
= 0;
4221 operand_types
[j
].bitfield
.disp16
= 1;
4227 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4229 if (operand_types
[j
].bitfield
.disp64
)
4231 addr_prefix_disp
= j
;
4232 operand_types
[j
].bitfield
.disp64
= 0;
4233 operand_types
[j
].bitfield
.disp32
= 1;
4241 /* We check register size if needed. */
4242 check_register
= t
->opcode_modifier
.checkregsize
;
4243 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4244 switch (t
->operands
)
4247 if (!operand_type_match (overlap0
, i
.types
[0]))
4251 /* xchg %eax, %eax is a special case. It is an aliase for nop
4252 only in 32bit mode and we can use opcode 0x90. In 64bit
4253 mode, we can't use 0x90 for xchg %eax, %eax since it should
4254 zero-extend %eax to %rax. */
4255 if (flag_code
== CODE_64BIT
4256 && t
->base_opcode
== 0x90
4257 && operand_type_equal (&i
.types
[0], &acc32
)
4258 && operand_type_equal (&i
.types
[1], &acc32
))
4262 /* If we swap operand in encoding, we either match
4263 the next one or reverse direction of operands. */
4264 if (t
->opcode_modifier
.s
)
4266 else if (t
->opcode_modifier
.d
)
4271 /* If we swap operand in encoding, we match the next one. */
4272 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4276 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4277 if (!operand_type_match (overlap0
, i
.types
[0])
4278 || !operand_type_match (overlap1
, i
.types
[1])
4280 && !operand_type_register_match (overlap0
, i
.types
[0],
4282 overlap1
, i
.types
[1],
4285 /* Check if other direction is valid ... */
4286 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4290 /* Try reversing direction of operands. */
4291 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4292 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4293 if (!operand_type_match (overlap0
, i
.types
[0])
4294 || !operand_type_match (overlap1
, i
.types
[1])
4296 && !operand_type_register_match (overlap0
,
4303 /* Does not match either direction. */
4306 /* found_reverse_match holds which of D or FloatDR
4308 if (t
->opcode_modifier
.d
)
4309 found_reverse_match
= Opcode_D
;
4310 else if (t
->opcode_modifier
.floatd
)
4311 found_reverse_match
= Opcode_FloatD
;
4313 found_reverse_match
= 0;
4314 if (t
->opcode_modifier
.floatr
)
4315 found_reverse_match
|= Opcode_FloatR
;
4319 /* Found a forward 2 operand match here. */
4320 switch (t
->operands
)
4323 overlap4
= operand_type_and (i
.types
[4],
4326 overlap3
= operand_type_and (i
.types
[3],
4329 overlap2
= operand_type_and (i
.types
[2],
4334 switch (t
->operands
)
4337 if (!operand_type_match (overlap4
, i
.types
[4])
4338 || !operand_type_register_match (overlap3
,
4346 if (!operand_type_match (overlap3
, i
.types
[3])
4348 && !operand_type_register_match (overlap2
,
4356 /* Here we make use of the fact that there are no
4357 reverse match 3 operand instructions, and all 3
4358 operand instructions only need to be checked for
4359 register consistency between operands 2 and 3. */
4360 if (!operand_type_match (overlap2
, i
.types
[2])
4362 && !operand_type_register_match (overlap1
,
4372 /* Found either forward/reverse 2, 3 or 4 operand match here:
4373 slip through to break. */
4375 if (!found_cpu_match
)
4377 found_reverse_match
= 0;
4381 /* Check if vector and VEX operands are valid. */
4382 if (check_VecOperands (t
) || VEX_check_operands (t
))
4384 specific_error
= i
.error
;
4388 /* We've found a match; break out of loop. */
4392 if (t
== current_templates
->end
)
4394 /* We found no match. */
4395 const char *err_msg
;
4396 switch (specific_error
? specific_error
: i
.error
)
4400 case operand_size_mismatch
:
4401 err_msg
= _("operand size mismatch");
4403 case operand_type_mismatch
:
4404 err_msg
= _("operand type mismatch");
4406 case register_type_mismatch
:
4407 err_msg
= _("register type mismatch");
4409 case number_of_operands_mismatch
:
4410 err_msg
= _("number of operands mismatch");
4412 case invalid_instruction_suffix
:
4413 err_msg
= _("invalid instruction suffix");
4416 err_msg
= _("constant doesn't fit in 4 bits");
4419 err_msg
= _("only supported with old gcc");
4421 case unsupported_with_intel_mnemonic
:
4422 err_msg
= _("unsupported with Intel mnemonic");
4424 case unsupported_syntax
:
4425 err_msg
= _("unsupported syntax");
4428 as_bad (_("unsupported instruction `%s'"),
4429 current_templates
->start
->name
);
4431 case invalid_vsib_address
:
4432 err_msg
= _("invalid VSIB address");
4434 case invalid_vector_register_set
:
4435 err_msg
= _("mask, index, and destination registers must be distinct");
4437 case unsupported_vector_index_register
:
4438 err_msg
= _("unsupported vector index register");
4441 as_bad (_("%s for `%s'"), err_msg
,
4442 current_templates
->start
->name
);
4446 if (!quiet_warnings
)
4449 && (i
.types
[0].bitfield
.jumpabsolute
4450 != operand_types
[0].bitfield
.jumpabsolute
))
4452 as_warn (_("indirect %s without `*'"), t
->name
);
4455 if (t
->opcode_modifier
.isprefix
4456 && t
->opcode_modifier
.ignoresize
)
4458 /* Warn them that a data or address size prefix doesn't
4459 affect assembly of the next line of code. */
4460 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4464 /* Copy the template we found. */
4467 if (addr_prefix_disp
!= -1)
4468 i
.tm
.operand_types
[addr_prefix_disp
]
4469 = operand_types
[addr_prefix_disp
];
4471 if (found_reverse_match
)
4473 /* If we found a reverse match we must alter the opcode
4474 direction bit. found_reverse_match holds bits to change
4475 (different for int & float insns). */
4477 i
.tm
.base_opcode
^= found_reverse_match
;
4479 i
.tm
.operand_types
[0] = operand_types
[1];
4480 i
.tm
.operand_types
[1] = operand_types
[0];
4489 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4490 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4492 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4494 as_bad (_("`%s' operand %d must use `%ses' segment"),
4500 /* There's only ever one segment override allowed per instruction.
4501 This instruction possibly has a legal segment override on the
4502 second operand, so copy the segment to where non-string
4503 instructions store it, allowing common code. */
4504 i
.seg
[0] = i
.seg
[1];
4506 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4508 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4510 as_bad (_("`%s' operand %d must use `%ses' segment"),
4521 process_suffix (void)
4523 /* If matched instruction specifies an explicit instruction mnemonic
4525 if (i
.tm
.opcode_modifier
.size16
)
4526 i
.suffix
= WORD_MNEM_SUFFIX
;
4527 else if (i
.tm
.opcode_modifier
.size32
)
4528 i
.suffix
= LONG_MNEM_SUFFIX
;
4529 else if (i
.tm
.opcode_modifier
.size64
)
4530 i
.suffix
= QWORD_MNEM_SUFFIX
;
4531 else if (i
.reg_operands
)
4533 /* If there's no instruction mnemonic suffix we try to invent one
4534 based on register operands. */
4537 /* We take i.suffix from the last register operand specified,
4538 Destination register type is more significant than source
4539 register type. crc32 in SSE4.2 prefers source register
4541 if (i
.tm
.base_opcode
== 0xf20f38f1)
4543 if (i
.types
[0].bitfield
.reg16
)
4544 i
.suffix
= WORD_MNEM_SUFFIX
;
4545 else if (i
.types
[0].bitfield
.reg32
)
4546 i
.suffix
= LONG_MNEM_SUFFIX
;
4547 else if (i
.types
[0].bitfield
.reg64
)
4548 i
.suffix
= QWORD_MNEM_SUFFIX
;
4550 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4552 if (i
.types
[0].bitfield
.reg8
)
4553 i
.suffix
= BYTE_MNEM_SUFFIX
;
4560 if (i
.tm
.base_opcode
== 0xf20f38f1
4561 || i
.tm
.base_opcode
== 0xf20f38f0)
4563 /* We have to know the operand size for crc32. */
4564 as_bad (_("ambiguous memory operand size for `%s`"),
4569 for (op
= i
.operands
; --op
>= 0;)
4570 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4572 if (i
.types
[op
].bitfield
.reg8
)
4574 i
.suffix
= BYTE_MNEM_SUFFIX
;
4577 else if (i
.types
[op
].bitfield
.reg16
)
4579 i
.suffix
= WORD_MNEM_SUFFIX
;
4582 else if (i
.types
[op
].bitfield
.reg32
)
4584 i
.suffix
= LONG_MNEM_SUFFIX
;
4587 else if (i
.types
[op
].bitfield
.reg64
)
4589 i
.suffix
= QWORD_MNEM_SUFFIX
;
4595 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4598 && i
.tm
.opcode_modifier
.ignoresize
4599 && i
.tm
.opcode_modifier
.no_bsuf
)
4601 else if (!check_byte_reg ())
4604 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4607 && i
.tm
.opcode_modifier
.ignoresize
4608 && i
.tm
.opcode_modifier
.no_lsuf
)
4610 else if (!check_long_reg ())
4613 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4616 && i
.tm
.opcode_modifier
.ignoresize
4617 && i
.tm
.opcode_modifier
.no_qsuf
)
4619 else if (!check_qword_reg ())
4622 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4625 && i
.tm
.opcode_modifier
.ignoresize
4626 && i
.tm
.opcode_modifier
.no_wsuf
)
4628 else if (!check_word_reg ())
4631 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4632 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4634 /* Skip if the instruction has x/y suffix. match_template
4635 should check if it is a valid suffix. */
4637 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4638 /* Do nothing if the instruction is going to ignore the prefix. */
4643 else if (i
.tm
.opcode_modifier
.defaultsize
4645 /* exclude fldenv/frstor/fsave/fstenv */
4646 && i
.tm
.opcode_modifier
.no_ssuf
)
4648 i
.suffix
= stackop_size
;
4650 else if (intel_syntax
4652 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4653 || i
.tm
.opcode_modifier
.jumpbyte
4654 || i
.tm
.opcode_modifier
.jumpintersegment
4655 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4656 && i
.tm
.extension_opcode
<= 3)))
4661 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4663 i
.suffix
= QWORD_MNEM_SUFFIX
;
4667 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4668 i
.suffix
= LONG_MNEM_SUFFIX
;
4671 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4672 i
.suffix
= WORD_MNEM_SUFFIX
;
4681 if (i
.tm
.opcode_modifier
.w
)
4683 as_bad (_("no instruction mnemonic suffix given and "
4684 "no register operands; can't size instruction"));
4690 unsigned int suffixes
;
4692 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4693 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4695 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4697 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4699 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4701 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4704 /* There are more than suffix matches. */
4705 if (i
.tm
.opcode_modifier
.w
4706 || ((suffixes
& (suffixes
- 1))
4707 && !i
.tm
.opcode_modifier
.defaultsize
4708 && !i
.tm
.opcode_modifier
.ignoresize
))
4710 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4716 /* Change the opcode based on the operand size given by i.suffix;
4717 We don't need to change things for byte insns. */
4720 && i
.suffix
!= BYTE_MNEM_SUFFIX
4721 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4722 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4724 /* It's not a byte, select word/dword operation. */
4725 if (i
.tm
.opcode_modifier
.w
)
4727 if (i
.tm
.opcode_modifier
.shortform
)
4728 i
.tm
.base_opcode
|= 8;
4730 i
.tm
.base_opcode
|= 1;
4733 /* Now select between word & dword operations via the operand
4734 size prefix, except for instructions that will ignore this
4736 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4738 /* The address size override prefix changes the size of the
4740 if ((flag_code
== CODE_32BIT
4741 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4742 || (flag_code
!= CODE_32BIT
4743 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4744 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4747 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4748 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4749 && !i
.tm
.opcode_modifier
.ignoresize
4750 && !i
.tm
.opcode_modifier
.floatmf
4751 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4752 || (flag_code
== CODE_64BIT
4753 && i
.tm
.opcode_modifier
.jumpbyte
)))
4755 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4757 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4758 prefix
= ADDR_PREFIX_OPCODE
;
4760 if (!add_prefix (prefix
))
4764 /* Set mode64 for an operand. */
4765 if (i
.suffix
== QWORD_MNEM_SUFFIX
4766 && flag_code
== CODE_64BIT
4767 && !i
.tm
.opcode_modifier
.norex64
)
4769 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4770 need rex64. cmpxchg8b is also a special case. */
4771 if (! (i
.operands
== 2
4772 && i
.tm
.base_opcode
== 0x90
4773 && i
.tm
.extension_opcode
== None
4774 && operand_type_equal (&i
.types
[0], &acc64
)
4775 && operand_type_equal (&i
.types
[1], &acc64
))
4776 && ! (i
.operands
== 1
4777 && i
.tm
.base_opcode
== 0xfc7
4778 && i
.tm
.extension_opcode
== 1
4779 && !operand_type_check (i
.types
[0], reg
)
4780 && operand_type_check (i
.types
[0], anymem
)))
4784 /* Size floating point instruction. */
4785 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4786 if (i
.tm
.opcode_modifier
.floatmf
)
4787 i
.tm
.base_opcode
^= 4;
4794 check_byte_reg (void)
4798 for (op
= i
.operands
; --op
>= 0;)
4800 /* If this is an eight bit register, it's OK. If it's the 16 or
4801 32 bit version of an eight bit register, we will just use the
4802 low portion, and that's OK too. */
4803 if (i
.types
[op
].bitfield
.reg8
)
4806 /* I/O port address operands are OK too. */
4807 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4810 /* crc32 doesn't generate this warning. */
4811 if (i
.tm
.base_opcode
== 0xf20f38f0)
4814 if ((i
.types
[op
].bitfield
.reg16
4815 || i
.types
[op
].bitfield
.reg32
4816 || i
.types
[op
].bitfield
.reg64
)
4817 && i
.op
[op
].regs
->reg_num
< 4
4818 /* Prohibit these changes in 64bit mode, since the lowering
4819 would be more complicated. */
4820 && flag_code
!= CODE_64BIT
)
4822 #if REGISTER_WARNINGS
4823 if (!quiet_warnings
)
4824 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4826 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4827 ? REGNAM_AL
- REGNAM_AX
4828 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4830 i
.op
[op
].regs
->reg_name
,
4835 /* Any other register is bad. */
4836 if (i
.types
[op
].bitfield
.reg16
4837 || i
.types
[op
].bitfield
.reg32
4838 || i
.types
[op
].bitfield
.reg64
4839 || i
.types
[op
].bitfield
.regmmx
4840 || i
.types
[op
].bitfield
.regxmm
4841 || i
.types
[op
].bitfield
.regymm
4842 || i
.types
[op
].bitfield
.sreg2
4843 || i
.types
[op
].bitfield
.sreg3
4844 || i
.types
[op
].bitfield
.control
4845 || i
.types
[op
].bitfield
.debug
4846 || i
.types
[op
].bitfield
.test
4847 || i
.types
[op
].bitfield
.floatreg
4848 || i
.types
[op
].bitfield
.floatacc
)
4850 as_bad (_("`%s%s' not allowed with `%s%c'"),
4852 i
.op
[op
].regs
->reg_name
,
4862 check_long_reg (void)
4866 for (op
= i
.operands
; --op
>= 0;)
4867 /* Reject eight bit registers, except where the template requires
4868 them. (eg. movzb) */
4869 if (i
.types
[op
].bitfield
.reg8
4870 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4871 || i
.tm
.operand_types
[op
].bitfield
.reg32
4872 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4874 as_bad (_("`%s%s' not allowed with `%s%c'"),
4876 i
.op
[op
].regs
->reg_name
,
4881 /* Warn if the e prefix on a general reg is missing. */
4882 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4883 && i
.types
[op
].bitfield
.reg16
4884 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4885 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4887 /* Prohibit these changes in the 64bit mode, since the
4888 lowering is more complicated. */
4889 if (flag_code
== CODE_64BIT
)
4891 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4892 register_prefix
, i
.op
[op
].regs
->reg_name
,
4896 #if REGISTER_WARNINGS
4898 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4900 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4902 i
.op
[op
].regs
->reg_name
,
4906 /* Warn if the r prefix on a general reg is missing. */
4907 else if (i
.types
[op
].bitfield
.reg64
4908 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4909 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4912 && i
.tm
.opcode_modifier
.toqword
4913 && !i
.types
[0].bitfield
.regxmm
)
4915 /* Convert to QWORD. We want REX byte. */
4916 i
.suffix
= QWORD_MNEM_SUFFIX
;
4920 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4921 register_prefix
, i
.op
[op
].regs
->reg_name
,
4930 check_qword_reg (void)
4934 for (op
= i
.operands
; --op
>= 0; )
4935 /* Reject eight bit registers, except where the template requires
4936 them. (eg. movzb) */
4937 if (i
.types
[op
].bitfield
.reg8
4938 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4939 || i
.tm
.operand_types
[op
].bitfield
.reg32
4940 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4942 as_bad (_("`%s%s' not allowed with `%s%c'"),
4944 i
.op
[op
].regs
->reg_name
,
4949 /* Warn if the e prefix on a general reg is missing. */
4950 else if ((i
.types
[op
].bitfield
.reg16
4951 || i
.types
[op
].bitfield
.reg32
)
4952 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4953 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4955 /* Prohibit these changes in the 64bit mode, since the
4956 lowering is more complicated. */
4958 && i
.tm
.opcode_modifier
.todword
4959 && !i
.types
[0].bitfield
.regxmm
)
4961 /* Convert to DWORD. We don't want REX byte. */
4962 i
.suffix
= LONG_MNEM_SUFFIX
;
4966 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4967 register_prefix
, i
.op
[op
].regs
->reg_name
,
4976 check_word_reg (void)
4979 for (op
= i
.operands
; --op
>= 0;)
4980 /* Reject eight bit registers, except where the template requires
4981 them. (eg. movzb) */
4982 if (i
.types
[op
].bitfield
.reg8
4983 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4984 || i
.tm
.operand_types
[op
].bitfield
.reg32
4985 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4987 as_bad (_("`%s%s' not allowed with `%s%c'"),
4989 i
.op
[op
].regs
->reg_name
,
4994 /* Warn if the e prefix on a general reg is present. */
4995 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4996 && i
.types
[op
].bitfield
.reg32
4997 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4998 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5000 /* Prohibit these changes in the 64bit mode, since the
5001 lowering is more complicated. */
5002 if (flag_code
== CODE_64BIT
)
5004 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5005 register_prefix
, i
.op
[op
].regs
->reg_name
,
5010 #if REGISTER_WARNINGS
5011 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5013 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5015 i
.op
[op
].regs
->reg_name
,
5023 update_imm (unsigned int j
)
5025 i386_operand_type overlap
= i
.types
[j
];
5026 if ((overlap
.bitfield
.imm8
5027 || overlap
.bitfield
.imm8s
5028 || overlap
.bitfield
.imm16
5029 || overlap
.bitfield
.imm32
5030 || overlap
.bitfield
.imm32s
5031 || overlap
.bitfield
.imm64
)
5032 && !operand_type_equal (&overlap
, &imm8
)
5033 && !operand_type_equal (&overlap
, &imm8s
)
5034 && !operand_type_equal (&overlap
, &imm16
)
5035 && !operand_type_equal (&overlap
, &imm32
)
5036 && !operand_type_equal (&overlap
, &imm32s
)
5037 && !operand_type_equal (&overlap
, &imm64
))
5041 i386_operand_type temp
;
5043 operand_type_set (&temp
, 0);
5044 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5046 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5047 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5049 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5050 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5051 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5053 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5054 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5057 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5060 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5061 || operand_type_equal (&overlap
, &imm16_32
)
5062 || operand_type_equal (&overlap
, &imm16_32s
))
5064 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5069 if (!operand_type_equal (&overlap
, &imm8
)
5070 && !operand_type_equal (&overlap
, &imm8s
)
5071 && !operand_type_equal (&overlap
, &imm16
)
5072 && !operand_type_equal (&overlap
, &imm32
)
5073 && !operand_type_equal (&overlap
, &imm32s
)
5074 && !operand_type_equal (&overlap
, &imm64
))
5076 as_bad (_("no instruction mnemonic suffix given; "
5077 "can't determine immediate size"));
5081 i
.types
[j
] = overlap
;
5091 /* Update the first 2 immediate operands. */
5092 n
= i
.operands
> 2 ? 2 : i
.operands
;
5095 for (j
= 0; j
< n
; j
++)
5096 if (update_imm (j
) == 0)
5099 /* The 3rd operand can't be immediate operand. */
5100 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5107 bad_implicit_operand (int xmm
)
5109 const char *ireg
= xmm
? "xmm0" : "ymm0";
5112 as_bad (_("the last operand of `%s' must be `%s%s'"),
5113 i
.tm
.name
, register_prefix
, ireg
);
5115 as_bad (_("the first operand of `%s' must be `%s%s'"),
5116 i
.tm
.name
, register_prefix
, ireg
);
5121 process_operands (void)
5123 /* Default segment register this instruction will use for memory
5124 accesses. 0 means unknown. This is only for optimizing out
5125 unnecessary segment overrides. */
5126 const seg_entry
*default_seg
= 0;
5128 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5130 unsigned int dupl
= i
.operands
;
5131 unsigned int dest
= dupl
- 1;
5134 /* The destination must be an xmm register. */
5135 gas_assert (i
.reg_operands
5136 && MAX_OPERANDS
> dupl
5137 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5139 if (i
.tm
.opcode_modifier
.firstxmm0
)
5141 /* The first operand is implicit and must be xmm0. */
5142 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5143 if (register_number (i
.op
[0].regs
) != 0)
5144 return bad_implicit_operand (1);
5146 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5148 /* Keep xmm0 for instructions with VEX prefix and 3
5154 /* We remove the first xmm0 and keep the number of
5155 operands unchanged, which in fact duplicates the
5157 for (j
= 1; j
< i
.operands
; j
++)
5159 i
.op
[j
- 1] = i
.op
[j
];
5160 i
.types
[j
- 1] = i
.types
[j
];
5161 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5165 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5167 gas_assert ((MAX_OPERANDS
- 1) > dupl
5168 && (i
.tm
.opcode_modifier
.vexsources
5171 /* Add the implicit xmm0 for instructions with VEX prefix
5173 for (j
= i
.operands
; j
> 0; j
--)
5175 i
.op
[j
] = i
.op
[j
- 1];
5176 i
.types
[j
] = i
.types
[j
- 1];
5177 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5180 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5181 i
.types
[0] = regxmm
;
5182 i
.tm
.operand_types
[0] = regxmm
;
5185 i
.reg_operands
+= 2;
5190 i
.op
[dupl
] = i
.op
[dest
];
5191 i
.types
[dupl
] = i
.types
[dest
];
5192 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5201 i
.op
[dupl
] = i
.op
[dest
];
5202 i
.types
[dupl
] = i
.types
[dest
];
5203 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5206 if (i
.tm
.opcode_modifier
.immext
)
5209 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5213 /* The first operand is implicit and must be xmm0/ymm0. */
5214 gas_assert (i
.reg_operands
5215 && (operand_type_equal (&i
.types
[0], ®xmm
)
5216 || operand_type_equal (&i
.types
[0], ®ymm
)));
5217 if (register_number (i
.op
[0].regs
) != 0)
5218 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5220 for (j
= 1; j
< i
.operands
; j
++)
5222 i
.op
[j
- 1] = i
.op
[j
];
5223 i
.types
[j
- 1] = i
.types
[j
];
5225 /* We need to adjust fields in i.tm since they are used by
5226 build_modrm_byte. */
5227 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5234 else if (i
.tm
.opcode_modifier
.regkludge
)
5236 /* The imul $imm, %reg instruction is converted into
5237 imul $imm, %reg, %reg, and the clr %reg instruction
5238 is converted into xor %reg, %reg. */
5240 unsigned int first_reg_op
;
5242 if (operand_type_check (i
.types
[0], reg
))
5246 /* Pretend we saw the extra register operand. */
5247 gas_assert (i
.reg_operands
== 1
5248 && i
.op
[first_reg_op
+ 1].regs
== 0);
5249 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5250 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5255 if (i
.tm
.opcode_modifier
.shortform
)
5257 if (i
.types
[0].bitfield
.sreg2
5258 || i
.types
[0].bitfield
.sreg3
)
5260 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5261 && i
.op
[0].regs
->reg_num
== 1)
5263 as_bad (_("you can't `pop %scs'"), register_prefix
);
5266 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5267 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5272 /* The register or float register operand is in operand
5276 if (i
.types
[0].bitfield
.floatreg
5277 || operand_type_check (i
.types
[0], reg
))
5281 /* Register goes in low 3 bits of opcode. */
5282 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5283 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5285 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5287 /* Warn about some common errors, but press on regardless.
5288 The first case can be generated by gcc (<= 2.8.1). */
5289 if (i
.operands
== 2)
5291 /* Reversed arguments on faddp, fsubp, etc. */
5292 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5293 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5294 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5298 /* Extraneous `l' suffix on fp insn. */
5299 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5300 register_prefix
, i
.op
[0].regs
->reg_name
);
5305 else if (i
.tm
.opcode_modifier
.modrm
)
5307 /* The opcode is completed (modulo i.tm.extension_opcode which
5308 must be put into the modrm byte). Now, we make the modrm and
5309 index base bytes based on all the info we've collected. */
5311 default_seg
= build_modrm_byte ();
5313 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5317 else if (i
.tm
.opcode_modifier
.isstring
)
5319 /* For the string instructions that allow a segment override
5320 on one of their operands, the default segment is ds. */
5324 if (i
.tm
.base_opcode
== 0x8d /* lea */
5327 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5329 /* If a segment was explicitly specified, and the specified segment
5330 is not the default, use an opcode prefix to select it. If we
5331 never figured out what the default segment is, then default_seg
5332 will be zero at this point, and the specified segment prefix will
5334 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5336 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5342 static const seg_entry
*
5343 build_modrm_byte (void)
5345 const seg_entry
*default_seg
= 0;
5346 unsigned int source
, dest
;
5349 /* The first operand of instructions with VEX prefix and 3 sources
5350 must be VEX_Imm4. */
5351 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5354 unsigned int nds
, reg_slot
;
5357 if (i
.tm
.opcode_modifier
.veximmext
5358 && i
.tm
.opcode_modifier
.immext
)
5360 dest
= i
.operands
- 2;
5361 gas_assert (dest
== 3);
5364 dest
= i
.operands
- 1;
5367 /* There are 2 kinds of instructions:
5368 1. 5 operands: 4 register operands or 3 register operands
5369 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5370 VexW0 or VexW1. The destination must be either XMM or YMM
5372 2. 4 operands: 4 register operands or 3 register operands
5373 plus 1 memory operand, VexXDS, and VexImmExt */
5374 gas_assert ((i
.reg_operands
== 4
5375 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5376 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5377 && (i
.tm
.opcode_modifier
.veximmext
5378 || (i
.imm_operands
== 1
5379 && i
.types
[0].bitfield
.vec_imm4
5380 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5381 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5382 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5383 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5385 if (i
.imm_operands
== 0)
5387 /* When there is no immediate operand, generate an 8bit
5388 immediate operand to encode the first operand. */
5389 exp
= &im_expressions
[i
.imm_operands
++];
5390 i
.op
[i
.operands
].imms
= exp
;
5391 i
.types
[i
.operands
] = imm8
;
5393 /* If VexW1 is set, the first operand is the source and
5394 the second operand is encoded in the immediate operand. */
5395 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5406 /* FMA swaps REG and NDS. */
5407 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5415 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5417 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5419 exp
->X_op
= O_constant
;
5420 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5424 unsigned int imm_slot
;
5426 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5428 /* If VexW0 is set, the third operand is the source and
5429 the second operand is encoded in the immediate
5436 /* VexW1 is set, the second operand is the source and
5437 the third operand is encoded in the immediate
5443 if (i
.tm
.opcode_modifier
.immext
)
5445 /* When ImmExt is set, the immdiate byte is the last
5447 imm_slot
= i
.operands
- 1;
5455 /* Turn on Imm8 so that output_imm will generate it. */
5456 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5459 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5461 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5463 i
.op
[imm_slot
].imms
->X_add_number
5464 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5467 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5468 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5470 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5475 /* i.reg_operands MUST be the number of real register operands;
5476 implicit registers do not count. If there are 3 register
5477 operands, it must be a instruction with VexNDS. For a
5478 instruction with VexNDD, the destination register is encoded
5479 in VEX prefix. If there are 4 register operands, it must be
5480 a instruction with VEX prefix and 3 sources. */
5481 if (i
.mem_operands
== 0
5482 && ((i
.reg_operands
== 2
5483 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5484 || (i
.reg_operands
== 3
5485 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5486 || (i
.reg_operands
== 4 && vex_3_sources
)))
5494 /* When there are 3 operands, one of them may be immediate,
5495 which may be the first or the last operand. Otherwise,
5496 the first operand must be shift count register (cl) or it
5497 is an instruction with VexNDS. */
5498 gas_assert (i
.imm_operands
== 1
5499 || (i
.imm_operands
== 0
5500 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5501 || i
.types
[0].bitfield
.shiftcount
)));
5502 if (operand_type_check (i
.types
[0], imm
)
5503 || i
.types
[0].bitfield
.shiftcount
)
5509 /* When there are 4 operands, the first two must be 8bit
5510 immediate operands. The source operand will be the 3rd
5513 For instructions with VexNDS, if the first operand
5514 an imm8, the source operand is the 2nd one. If the last
5515 operand is imm8, the source operand is the first one. */
5516 gas_assert ((i
.imm_operands
== 2
5517 && i
.types
[0].bitfield
.imm8
5518 && i
.types
[1].bitfield
.imm8
)
5519 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5520 && i
.imm_operands
== 1
5521 && (i
.types
[0].bitfield
.imm8
5522 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5523 if (i
.imm_operands
== 2)
5527 if (i
.types
[0].bitfield
.imm8
)
5543 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5545 /* For instructions with VexNDS, the register-only
5546 source operand must be 32/64bit integer, XMM or
5547 YMM register. It is encoded in VEX prefix. We
5548 need to clear RegMem bit before calling
5549 operand_type_equal. */
5551 i386_operand_type op
;
5554 /* Check register-only source operand when two source
5555 operands are swapped. */
5556 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5557 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5565 op
= i
.tm
.operand_types
[vvvv
];
5566 op
.bitfield
.regmem
= 0;
5567 if ((dest
+ 1) >= i
.operands
5568 || (op
.bitfield
.reg32
!= 1
5569 && !op
.bitfield
.reg64
!= 1
5570 && !operand_type_equal (&op
, ®xmm
)
5571 && !operand_type_equal (&op
, ®ymm
)))
5573 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5579 /* One of the register operands will be encoded in the i.tm.reg
5580 field, the other in the combined i.tm.mode and i.tm.regmem
5581 fields. If no form of this instruction supports a memory
5582 destination operand, then we assume the source operand may
5583 sometimes be a memory operand and so we need to store the
5584 destination in the i.rm.reg field. */
5585 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5586 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5588 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5589 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5590 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5592 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5597 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5598 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5599 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5601 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5604 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5606 if (!i
.types
[0].bitfield
.control
5607 && !i
.types
[1].bitfield
.control
)
5609 i
.rex
&= ~(REX_R
| REX_B
);
5610 add_prefix (LOCK_PREFIX_OPCODE
);
5614 { /* If it's not 2 reg operands... */
5619 unsigned int fake_zero_displacement
= 0;
5622 for (op
= 0; op
< i
.operands
; op
++)
5623 if (operand_type_check (i
.types
[op
], anymem
))
5625 gas_assert (op
< i
.operands
);
5627 if (i
.tm
.opcode_modifier
.vecsib
)
5629 if (i
.index_reg
->reg_num
== RegEiz
5630 || i
.index_reg
->reg_num
== RegRiz
)
5633 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5636 i
.sib
.base
= NO_BASE_REGISTER
;
5637 i
.sib
.scale
= i
.log2_scale_factor
;
5638 i
.types
[op
].bitfield
.disp8
= 0;
5639 i
.types
[op
].bitfield
.disp16
= 0;
5640 i
.types
[op
].bitfield
.disp64
= 0;
5641 if (flag_code
!= CODE_64BIT
)
5643 /* Must be 32 bit */
5644 i
.types
[op
].bitfield
.disp32
= 1;
5645 i
.types
[op
].bitfield
.disp32s
= 0;
5649 i
.types
[op
].bitfield
.disp32
= 0;
5650 i
.types
[op
].bitfield
.disp32s
= 1;
5653 i
.sib
.index
= i
.index_reg
->reg_num
;
5654 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5660 if (i
.base_reg
== 0)
5663 if (!i
.disp_operands
)
5665 fake_zero_displacement
= 1;
5666 /* Instructions with VSIB byte need 32bit displacement
5667 if there is no base register. */
5668 if (i
.tm
.opcode_modifier
.vecsib
)
5669 i
.types
[op
].bitfield
.disp32
= 1;
5671 if (i
.index_reg
== 0)
5673 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5674 /* Operand is just <disp> */
5675 if (flag_code
== CODE_64BIT
)
5677 /* 64bit mode overwrites the 32bit absolute
5678 addressing by RIP relative addressing and
5679 absolute addressing is encoded by one of the
5680 redundant SIB forms. */
5681 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5682 i
.sib
.base
= NO_BASE_REGISTER
;
5683 i
.sib
.index
= NO_INDEX_REGISTER
;
5684 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5685 ? disp32s
: disp32
);
5687 else if ((flag_code
== CODE_16BIT
)
5688 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5690 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5691 i
.types
[op
] = disp16
;
5695 i
.rm
.regmem
= NO_BASE_REGISTER
;
5696 i
.types
[op
] = disp32
;
5699 else if (!i
.tm
.opcode_modifier
.vecsib
)
5701 /* !i.base_reg && i.index_reg */
5702 if (i
.index_reg
->reg_num
== RegEiz
5703 || i
.index_reg
->reg_num
== RegRiz
)
5704 i
.sib
.index
= NO_INDEX_REGISTER
;
5706 i
.sib
.index
= i
.index_reg
->reg_num
;
5707 i
.sib
.base
= NO_BASE_REGISTER
;
5708 i
.sib
.scale
= i
.log2_scale_factor
;
5709 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5710 i
.types
[op
].bitfield
.disp8
= 0;
5711 i
.types
[op
].bitfield
.disp16
= 0;
5712 i
.types
[op
].bitfield
.disp64
= 0;
5713 if (flag_code
!= CODE_64BIT
)
5715 /* Must be 32 bit */
5716 i
.types
[op
].bitfield
.disp32
= 1;
5717 i
.types
[op
].bitfield
.disp32s
= 0;
5721 i
.types
[op
].bitfield
.disp32
= 0;
5722 i
.types
[op
].bitfield
.disp32s
= 1;
5724 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5728 /* RIP addressing for 64bit mode. */
5729 else if (i
.base_reg
->reg_num
== RegRip
||
5730 i
.base_reg
->reg_num
== RegEip
)
5732 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5733 i
.rm
.regmem
= NO_BASE_REGISTER
;
5734 i
.types
[op
].bitfield
.disp8
= 0;
5735 i
.types
[op
].bitfield
.disp16
= 0;
5736 i
.types
[op
].bitfield
.disp32
= 0;
5737 i
.types
[op
].bitfield
.disp32s
= 1;
5738 i
.types
[op
].bitfield
.disp64
= 0;
5739 i
.flags
[op
] |= Operand_PCrel
;
5740 if (! i
.disp_operands
)
5741 fake_zero_displacement
= 1;
5743 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5745 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5746 switch (i
.base_reg
->reg_num
)
5749 if (i
.index_reg
== 0)
5751 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5752 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5756 if (i
.index_reg
== 0)
5759 if (operand_type_check (i
.types
[op
], disp
) == 0)
5761 /* fake (%bp) into 0(%bp) */
5762 i
.types
[op
].bitfield
.disp8
= 1;
5763 fake_zero_displacement
= 1;
5766 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5767 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5769 default: /* (%si) -> 4 or (%di) -> 5 */
5770 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5772 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5774 else /* i.base_reg and 32/64 bit mode */
5776 if (flag_code
== CODE_64BIT
5777 && operand_type_check (i
.types
[op
], disp
))
5779 i386_operand_type temp
;
5780 operand_type_set (&temp
, 0);
5781 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5783 if (i
.prefix
[ADDR_PREFIX
] == 0)
5784 i
.types
[op
].bitfield
.disp32s
= 1;
5786 i
.types
[op
].bitfield
.disp32
= 1;
5789 if (!i
.tm
.opcode_modifier
.vecsib
)
5790 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5791 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5793 i
.sib
.base
= i
.base_reg
->reg_num
;
5794 /* x86-64 ignores REX prefix bit here to avoid decoder
5796 if (!(i
.base_reg
->reg_flags
& RegRex
)
5797 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5798 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5800 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5802 fake_zero_displacement
= 1;
5803 i
.types
[op
].bitfield
.disp8
= 1;
5805 i
.sib
.scale
= i
.log2_scale_factor
;
5806 if (i
.index_reg
== 0)
5808 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5809 /* <disp>(%esp) becomes two byte modrm with no index
5810 register. We've already stored the code for esp
5811 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5812 Any base register besides %esp will not use the
5813 extra modrm byte. */
5814 i
.sib
.index
= NO_INDEX_REGISTER
;
5816 else if (!i
.tm
.opcode_modifier
.vecsib
)
5818 if (i
.index_reg
->reg_num
== RegEiz
5819 || i
.index_reg
->reg_num
== RegRiz
)
5820 i
.sib
.index
= NO_INDEX_REGISTER
;
5822 i
.sib
.index
= i
.index_reg
->reg_num
;
5823 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5824 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5829 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5830 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5834 if (!fake_zero_displacement
5838 fake_zero_displacement
= 1;
5839 if (i
.disp_encoding
== disp_encoding_8bit
)
5840 i
.types
[op
].bitfield
.disp8
= 1;
5842 i
.types
[op
].bitfield
.disp32
= 1;
5844 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5848 if (fake_zero_displacement
)
5850 /* Fakes a zero displacement assuming that i.types[op]
5851 holds the correct displacement size. */
5854 gas_assert (i
.op
[op
].disps
== 0);
5855 exp
= &disp_expressions
[i
.disp_operands
++];
5856 i
.op
[op
].disps
= exp
;
5857 exp
->X_op
= O_constant
;
5858 exp
->X_add_number
= 0;
5859 exp
->X_add_symbol
= (symbolS
*) 0;
5860 exp
->X_op_symbol
= (symbolS
*) 0;
5868 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5870 if (operand_type_check (i
.types
[0], imm
))
5871 i
.vex
.register_specifier
= NULL
;
5874 /* VEX.vvvv encodes one of the sources when the first
5875 operand is not an immediate. */
5876 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5877 i
.vex
.register_specifier
= i
.op
[0].regs
;
5879 i
.vex
.register_specifier
= i
.op
[1].regs
;
5882 /* Destination is a XMM register encoded in the ModRM.reg
5884 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5885 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5888 /* ModRM.rm and VEX.B encodes the other source. */
5889 if (!i
.mem_operands
)
5893 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5894 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5896 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5898 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5902 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5904 i
.vex
.register_specifier
= i
.op
[2].regs
;
5905 if (!i
.mem_operands
)
5908 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5909 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5913 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5914 (if any) based on i.tm.extension_opcode. Again, we must be
5915 careful to make sure that segment/control/debug/test/MMX
5916 registers are coded into the i.rm.reg field. */
5917 else if (i
.reg_operands
)
5920 unsigned int vex_reg
= ~0;
5922 for (op
= 0; op
< i
.operands
; op
++)
5923 if (i
.types
[op
].bitfield
.reg8
5924 || i
.types
[op
].bitfield
.reg16
5925 || i
.types
[op
].bitfield
.reg32
5926 || i
.types
[op
].bitfield
.reg64
5927 || i
.types
[op
].bitfield
.regmmx
5928 || i
.types
[op
].bitfield
.regxmm
5929 || i
.types
[op
].bitfield
.regymm
5930 || i
.types
[op
].bitfield
.sreg2
5931 || i
.types
[op
].bitfield
.sreg3
5932 || i
.types
[op
].bitfield
.control
5933 || i
.types
[op
].bitfield
.debug
5934 || i
.types
[op
].bitfield
.test
)
5939 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5941 /* For instructions with VexNDS, the register-only
5942 source operand is encoded in VEX prefix. */
5943 gas_assert (mem
!= (unsigned int) ~0);
5948 gas_assert (op
< i
.operands
);
5952 /* Check register-only source operand when two source
5953 operands are swapped. */
5954 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5955 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5959 gas_assert (mem
== (vex_reg
+ 1)
5960 && op
< i
.operands
);
5965 gas_assert (vex_reg
< i
.operands
);
5969 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5971 /* For instructions with VexNDD, the register destination
5972 is encoded in VEX prefix. */
5973 if (i
.mem_operands
== 0)
5975 /* There is no memory operand. */
5976 gas_assert ((op
+ 2) == i
.operands
);
5981 /* There are only 2 operands. */
5982 gas_assert (op
< 2 && i
.operands
== 2);
5987 gas_assert (op
< i
.operands
);
5989 if (vex_reg
!= (unsigned int) ~0)
5991 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5993 if (type
->bitfield
.reg32
!= 1
5994 && type
->bitfield
.reg64
!= 1
5995 && !operand_type_equal (type
, ®xmm
)
5996 && !operand_type_equal (type
, ®ymm
))
5999 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6002 /* Don't set OP operand twice. */
6005 /* If there is an extension opcode to put here, the
6006 register number must be put into the regmem field. */
6007 if (i
.tm
.extension_opcode
!= None
)
6009 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6010 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6015 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6016 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6021 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6022 must set it to 3 to indicate this is a register operand
6023 in the regmem field. */
6024 if (!i
.mem_operands
)
6028 /* Fill in i.rm.reg field with extension opcode (if any). */
6029 if (i
.tm
.extension_opcode
!= None
)
6030 i
.rm
.reg
= i
.tm
.extension_opcode
;
6036 output_branch (void)
6042 relax_substateT subtype
;
6046 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6047 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6050 if (i
.prefix
[DATA_PREFIX
] != 0)
6056 /* Pentium4 branch hints. */
6057 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6058 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6063 if (i
.prefix
[REX_PREFIX
] != 0)
6069 if (i
.prefixes
!= 0 && !intel_syntax
)
6070 as_warn (_("skipping prefixes on this instruction"));
6072 /* It's always a symbol; End frag & setup for relax.
6073 Make sure there is enough room in this frag for the largest
6074 instruction we may generate in md_convert_frag. This is 2
6075 bytes for the opcode and room for the prefix and largest
6077 frag_grow (prefix
+ 2 + 4);
6078 /* Prefix and 1 opcode byte go in fr_fix. */
6079 p
= frag_more (prefix
+ 1);
6080 if (i
.prefix
[DATA_PREFIX
] != 0)
6081 *p
++ = DATA_PREFIX_OPCODE
;
6082 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6083 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6084 *p
++ = i
.prefix
[SEG_PREFIX
];
6085 if (i
.prefix
[REX_PREFIX
] != 0)
6086 *p
++ = i
.prefix
[REX_PREFIX
];
6087 *p
= i
.tm
.base_opcode
;
6089 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6090 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6091 else if (cpu_arch_flags
.bitfield
.cpui386
)
6092 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6094 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6097 sym
= i
.op
[0].disps
->X_add_symbol
;
6098 off
= i
.op
[0].disps
->X_add_number
;
6100 if (i
.op
[0].disps
->X_op
!= O_constant
6101 && i
.op
[0].disps
->X_op
!= O_symbol
)
6103 /* Handle complex expressions. */
6104 sym
= make_expr_symbol (i
.op
[0].disps
);
6108 /* 1 possible extra opcode + 4 byte displacement go in var part.
6109 Pass reloc in fr_var. */
6110 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6120 if (i
.tm
.opcode_modifier
.jumpbyte
)
6122 /* This is a loop or jecxz type instruction. */
6124 if (i
.prefix
[ADDR_PREFIX
] != 0)
6126 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6129 /* Pentium4 branch hints. */
6130 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6131 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6133 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6142 if (flag_code
== CODE_16BIT
)
6145 if (i
.prefix
[DATA_PREFIX
] != 0)
6147 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6157 if (i
.prefix
[REX_PREFIX
] != 0)
6159 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6163 if (i
.prefixes
!= 0 && !intel_syntax
)
6164 as_warn (_("skipping prefixes on this instruction"));
6166 p
= frag_more (i
.tm
.opcode_length
+ size
);
6167 switch (i
.tm
.opcode_length
)
6170 *p
++ = i
.tm
.base_opcode
>> 8;
6172 *p
++ = i
.tm
.base_opcode
;
6178 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6179 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6181 /* All jumps handled here are signed, but don't use a signed limit
6182 check for 32 and 16 bit jumps as we want to allow wrap around at
6183 4G and 64k respectively. */
6185 fixP
->fx_signed
= 1;
6189 output_interseg_jump (void)
6197 if (flag_code
== CODE_16BIT
)
6201 if (i
.prefix
[DATA_PREFIX
] != 0)
6207 if (i
.prefix
[REX_PREFIX
] != 0)
6217 if (i
.prefixes
!= 0 && !intel_syntax
)
6218 as_warn (_("skipping prefixes on this instruction"));
6220 /* 1 opcode; 2 segment; offset */
6221 p
= frag_more (prefix
+ 1 + 2 + size
);
6223 if (i
.prefix
[DATA_PREFIX
] != 0)
6224 *p
++ = DATA_PREFIX_OPCODE
;
6226 if (i
.prefix
[REX_PREFIX
] != 0)
6227 *p
++ = i
.prefix
[REX_PREFIX
];
6229 *p
++ = i
.tm
.base_opcode
;
6230 if (i
.op
[1].imms
->X_op
== O_constant
)
6232 offsetT n
= i
.op
[1].imms
->X_add_number
;
6235 && !fits_in_unsigned_word (n
)
6236 && !fits_in_signed_word (n
))
6238 as_bad (_("16-bit jump out of range"));
6241 md_number_to_chars (p
, n
, size
);
6244 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6245 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6246 if (i
.op
[0].imms
->X_op
!= O_constant
)
6247 as_bad (_("can't handle non absolute segment in `%s'"),
6249 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6255 fragS
*insn_start_frag
;
6256 offsetT insn_start_off
;
6258 /* Tie dwarf2 debug info to the address at the start of the insn.
6259 We can't do this after the insn has been output as the current
6260 frag may have been closed off. eg. by frag_var. */
6261 dwarf2_emit_insn (0);
6263 insn_start_frag
= frag_now
;
6264 insn_start_off
= frag_now_fix ();
6267 if (i
.tm
.opcode_modifier
.jump
)
6269 else if (i
.tm
.opcode_modifier
.jumpbyte
6270 || i
.tm
.opcode_modifier
.jumpdword
)
6272 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6273 output_interseg_jump ();
6276 /* Output normal instructions here. */
6280 unsigned int prefix
;
6282 /* Since the VEX prefix contains the implicit prefix, we don't
6283 need the explicit prefix. */
6284 if (!i
.tm
.opcode_modifier
.vex
)
6286 switch (i
.tm
.opcode_length
)
6289 if (i
.tm
.base_opcode
& 0xff000000)
6291 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6296 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6298 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6299 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6302 if (prefix
!= REPE_PREFIX_OPCODE
6303 || (i
.prefix
[REP_PREFIX
]
6304 != REPE_PREFIX_OPCODE
))
6305 add_prefix (prefix
);
6308 add_prefix (prefix
);
6317 /* The prefix bytes. */
6318 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6320 FRAG_APPEND_1_CHAR (*q
);
6324 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6329 /* REX byte is encoded in VEX prefix. */
6333 FRAG_APPEND_1_CHAR (*q
);
6336 /* There should be no other prefixes for instructions
6341 /* Now the VEX prefix. */
6342 p
= frag_more (i
.vex
.length
);
6343 for (j
= 0; j
< i
.vex
.length
; j
++)
6344 p
[j
] = i
.vex
.bytes
[j
];
6347 /* Now the opcode; be careful about word order here! */
6348 if (i
.tm
.opcode_length
== 1)
6350 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6354 switch (i
.tm
.opcode_length
)
6358 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6368 /* Put out high byte first: can't use md_number_to_chars! */
6369 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6370 *p
= i
.tm
.base_opcode
& 0xff;
6373 /* Now the modrm byte and sib byte (if present). */
6374 if (i
.tm
.opcode_modifier
.modrm
)
6376 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6379 /* If i.rm.regmem == ESP (4)
6380 && i.rm.mode != (Register mode)
6382 ==> need second modrm byte. */
6383 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6385 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6386 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6388 | i
.sib
.scale
<< 6));
6391 if (i
.disp_operands
)
6392 output_disp (insn_start_frag
, insn_start_off
);
6395 output_imm (insn_start_frag
, insn_start_off
);
6401 pi ("" /*line*/, &i
);
6403 #endif /* DEBUG386 */
6406 /* Return the size of the displacement operand N. */
6409 disp_size (unsigned int n
)
6412 if (i
.types
[n
].bitfield
.disp64
)
6414 else if (i
.types
[n
].bitfield
.disp8
)
6416 else if (i
.types
[n
].bitfield
.disp16
)
6421 /* Return the size of the immediate operand N. */
6424 imm_size (unsigned int n
)
6427 if (i
.types
[n
].bitfield
.imm64
)
6429 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6431 else if (i
.types
[n
].bitfield
.imm16
)
6437 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6442 for (n
= 0; n
< i
.operands
; n
++)
6444 if (operand_type_check (i
.types
[n
], disp
))
6446 if (i
.op
[n
].disps
->X_op
== O_constant
)
6448 int size
= disp_size (n
);
6451 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6453 p
= frag_more (size
);
6454 md_number_to_chars (p
, val
, size
);
6458 enum bfd_reloc_code_real reloc_type
;
6459 int size
= disp_size (n
);
6460 int sign
= i
.types
[n
].bitfield
.disp32s
;
6461 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6463 /* We can't have 8 bit displacement here. */
6464 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6466 /* The PC relative address is computed relative
6467 to the instruction boundary, so in case immediate
6468 fields follows, we need to adjust the value. */
6469 if (pcrel
&& i
.imm_operands
)
6474 for (n1
= 0; n1
< i
.operands
; n1
++)
6475 if (operand_type_check (i
.types
[n1
], imm
))
6477 /* Only one immediate is allowed for PC
6478 relative address. */
6479 gas_assert (sz
== 0);
6481 i
.op
[n
].disps
->X_add_number
-= sz
;
6483 /* We should find the immediate. */
6484 gas_assert (sz
!= 0);
6487 p
= frag_more (size
);
6488 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6490 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6491 && (((reloc_type
== BFD_RELOC_32
6492 || reloc_type
== BFD_RELOC_X86_64_32S
6493 || (reloc_type
== BFD_RELOC_64
6495 && (i
.op
[n
].disps
->X_op
== O_symbol
6496 || (i
.op
[n
].disps
->X_op
== O_add
6497 && ((symbol_get_value_expression
6498 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6500 || reloc_type
== BFD_RELOC_32_PCREL
))
6504 if (insn_start_frag
== frag_now
)
6505 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6510 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6511 for (fr
= insn_start_frag
->fr_next
;
6512 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6514 add
+= p
- frag_now
->fr_literal
;
6519 reloc_type
= BFD_RELOC_386_GOTPC
;
6520 i
.op
[n
].imms
->X_add_number
+= add
;
6522 else if (reloc_type
== BFD_RELOC_64
)
6523 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6525 /* Don't do the adjustment for x86-64, as there
6526 the pcrel addressing is relative to the _next_
6527 insn, and that is taken care of in other code. */
6528 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6530 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6531 i
.op
[n
].disps
, pcrel
, reloc_type
);
6538 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6543 for (n
= 0; n
< i
.operands
; n
++)
6545 if (operand_type_check (i
.types
[n
], imm
))
6547 if (i
.op
[n
].imms
->X_op
== O_constant
)
6549 int size
= imm_size (n
);
6552 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6554 p
= frag_more (size
);
6555 md_number_to_chars (p
, val
, size
);
6559 /* Not absolute_section.
6560 Need a 32-bit fixup (don't support 8bit
6561 non-absolute imms). Try to support other
6563 enum bfd_reloc_code_real reloc_type
;
6564 int size
= imm_size (n
);
6567 if (i
.types
[n
].bitfield
.imm32s
6568 && (i
.suffix
== QWORD_MNEM_SUFFIX
6569 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6574 p
= frag_more (size
);
6575 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6577 /* This is tough to explain. We end up with this one if we
6578 * have operands that look like
6579 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6580 * obtain the absolute address of the GOT, and it is strongly
6581 * preferable from a performance point of view to avoid using
6582 * a runtime relocation for this. The actual sequence of
6583 * instructions often look something like:
6588 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6590 * The call and pop essentially return the absolute address
6591 * of the label .L66 and store it in %ebx. The linker itself
6592 * will ultimately change the first operand of the addl so
6593 * that %ebx points to the GOT, but to keep things simple, the
6594 * .o file must have this operand set so that it generates not
6595 * the absolute address of .L66, but the absolute address of
6596 * itself. This allows the linker itself simply treat a GOTPC
6597 * relocation as asking for a pcrel offset to the GOT to be
6598 * added in, and the addend of the relocation is stored in the
6599 * operand field for the instruction itself.
6601 * Our job here is to fix the operand so that it would add
6602 * the correct offset so that %ebx would point to itself. The
6603 * thing that is tricky is that .-.L66 will point to the
6604 * beginning of the instruction, so we need to further modify
6605 * the operand so that it will point to itself. There are
6606 * other cases where you have something like:
6608 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6610 * and here no correction would be required. Internally in
6611 * the assembler we treat operands of this form as not being
6612 * pcrel since the '.' is explicitly mentioned, and I wonder
6613 * whether it would simplify matters to do it this way. Who
6614 * knows. In earlier versions of the PIC patches, the
6615 * pcrel_adjust field was used to store the correction, but
6616 * since the expression is not pcrel, I felt it would be
6617 * confusing to do it this way. */
6619 if ((reloc_type
== BFD_RELOC_32
6620 || reloc_type
== BFD_RELOC_X86_64_32S
6621 || reloc_type
== BFD_RELOC_64
)
6623 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6624 && (i
.op
[n
].imms
->X_op
== O_symbol
6625 || (i
.op
[n
].imms
->X_op
== O_add
6626 && ((symbol_get_value_expression
6627 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6632 if (insn_start_frag
== frag_now
)
6633 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6638 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6639 for (fr
= insn_start_frag
->fr_next
;
6640 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6642 add
+= p
- frag_now
->fr_literal
;
6646 reloc_type
= BFD_RELOC_386_GOTPC
;
6648 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6650 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6651 i
.op
[n
].imms
->X_add_number
+= add
;
6653 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6654 i
.op
[n
].imms
, 0, reloc_type
);
6660 /* x86_cons_fix_new is called via the expression parsing code when a
6661 reloc is needed. We use this hook to get the correct .got reloc. */
6662 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6663 static int cons_sign
= -1;
6666 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6669 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6671 got_reloc
= NO_RELOC
;
6674 if (exp
->X_op
== O_secrel
)
6676 exp
->X_op
= O_symbol
;
6677 r
= BFD_RELOC_32_SECREL
;
6681 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6684 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6685 purpose of the `.dc.a' internal pseudo-op. */
6688 x86_address_bytes (void)
6690 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6692 return stdoutput
->arch_info
->bits_per_address
/ 8;
6695 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6697 # define lex_got(reloc, adjust, types) NULL
6699 /* Parse operands of the form
6700 <symbol>@GOTOFF+<nnn>
6701 and similar .plt or .got references.
6703 If we find one, set up the correct relocation in RELOC and copy the
6704 input string, minus the `@GOTOFF' into a malloc'd buffer for
6705 parsing by the calling routine. Return this buffer, and if ADJUST
6706 is non-null set it to the length of the string we removed from the
6707 input line. Otherwise return NULL. */
6709 lex_got (enum bfd_reloc_code_real
*rel
,
6711 i386_operand_type
*types
)
6713 /* Some of the relocations depend on the size of what field is to
6714 be relocated. But in our callers i386_immediate and i386_displacement
6715 we don't yet know the operand size (this will be set by insn
6716 matching). Hence we record the word32 relocation here,
6717 and adjust the reloc according to the real size in reloc(). */
6718 static const struct {
6721 const enum bfd_reloc_code_real rel
[2];
6722 const i386_operand_type types64
;
6724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6725 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
6727 OPERAND_TYPE_IMM32_64
},
6729 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6730 BFD_RELOC_X86_64_PLTOFF64
},
6731 OPERAND_TYPE_IMM64
},
6732 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6733 BFD_RELOC_X86_64_PLT32
},
6734 OPERAND_TYPE_IMM32_32S_DISP32
},
6735 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6736 BFD_RELOC_X86_64_GOTPLT64
},
6737 OPERAND_TYPE_IMM64_DISP64
},
6738 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6739 BFD_RELOC_X86_64_GOTOFF64
},
6740 OPERAND_TYPE_IMM64_DISP64
},
6741 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6742 BFD_RELOC_X86_64_GOTPCREL
},
6743 OPERAND_TYPE_IMM32_32S_DISP32
},
6744 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6745 BFD_RELOC_X86_64_TLSGD
},
6746 OPERAND_TYPE_IMM32_32S_DISP32
},
6747 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6748 _dummy_first_bfd_reloc_code_real
},
6749 OPERAND_TYPE_NONE
},
6750 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6751 BFD_RELOC_X86_64_TLSLD
},
6752 OPERAND_TYPE_IMM32_32S_DISP32
},
6753 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6754 BFD_RELOC_X86_64_GOTTPOFF
},
6755 OPERAND_TYPE_IMM32_32S_DISP32
},
6756 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6757 BFD_RELOC_X86_64_TPOFF32
},
6758 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6759 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6760 _dummy_first_bfd_reloc_code_real
},
6761 OPERAND_TYPE_NONE
},
6762 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6763 BFD_RELOC_X86_64_DTPOFF32
},
6764 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6765 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6766 _dummy_first_bfd_reloc_code_real
},
6767 OPERAND_TYPE_NONE
},
6768 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6769 _dummy_first_bfd_reloc_code_real
},
6770 OPERAND_TYPE_NONE
},
6771 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6772 BFD_RELOC_X86_64_GOT32
},
6773 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6774 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6775 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6776 OPERAND_TYPE_IMM32_32S_DISP32
},
6777 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6778 BFD_RELOC_X86_64_TLSDESC_CALL
},
6779 OPERAND_TYPE_IMM32_32S_DISP32
},
6784 #if defined (OBJ_MAYBE_ELF)
6789 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6790 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6793 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6795 int len
= gotrel
[j
].len
;
6796 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6798 if (gotrel
[j
].rel
[object_64bit
] != 0)
6801 char *tmpbuf
, *past_reloc
;
6803 *rel
= gotrel
[j
].rel
[object_64bit
];
6807 if (flag_code
!= CODE_64BIT
)
6809 types
->bitfield
.imm32
= 1;
6810 types
->bitfield
.disp32
= 1;
6813 *types
= gotrel
[j
].types64
;
6816 if (j
!= 0 && GOT_symbol
== NULL
)
6817 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6819 /* The length of the first part of our input line. */
6820 first
= cp
- input_line_pointer
;
6822 /* The second part goes from after the reloc token until
6823 (and including) an end_of_line char or comma. */
6824 past_reloc
= cp
+ 1 + len
;
6826 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6828 second
= cp
+ 1 - past_reloc
;
6830 /* Allocate and copy string. The trailing NUL shouldn't
6831 be necessary, but be safe. */
6832 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6833 memcpy (tmpbuf
, input_line_pointer
, first
);
6834 if (second
!= 0 && *past_reloc
!= ' ')
6835 /* Replace the relocation token with ' ', so that
6836 errors like foo@GOTOFF1 will be detected. */
6837 tmpbuf
[first
++] = ' ';
6839 /* Increment length by 1 if the relocation token is
6844 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6845 tmpbuf
[first
+ second
] = '\0';
6849 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6850 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6855 /* Might be a symbol version string. Don't as_bad here. */
6864 /* Parse operands of the form
6865 <symbol>@SECREL32+<nnn>
6867 If we find one, set up the correct relocation in RELOC and copy the
6868 input string, minus the `@SECREL32' into a malloc'd buffer for
6869 parsing by the calling routine. Return this buffer, and if ADJUST
6870 is non-null set it to the length of the string we removed from the
6871 input line. Otherwise return NULL.
6873 This function is copied from the ELF version above adjusted for PE targets. */
6876 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6877 int *adjust ATTRIBUTE_UNUSED
,
6878 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6884 const enum bfd_reloc_code_real rel
[2];
6885 const i386_operand_type types64
;
6889 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6890 BFD_RELOC_32_SECREL
},
6891 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6897 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6898 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6901 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6903 int len
= gotrel
[j
].len
;
6905 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6907 if (gotrel
[j
].rel
[object_64bit
] != 0)
6910 char *tmpbuf
, *past_reloc
;
6912 *rel
= gotrel
[j
].rel
[object_64bit
];
6918 if (flag_code
!= CODE_64BIT
)
6920 types
->bitfield
.imm32
= 1;
6921 types
->bitfield
.disp32
= 1;
6924 *types
= gotrel
[j
].types64
;
6927 /* The length of the first part of our input line. */
6928 first
= cp
- input_line_pointer
;
6930 /* The second part goes from after the reloc token until
6931 (and including) an end_of_line char or comma. */
6932 past_reloc
= cp
+ 1 + len
;
6934 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6936 second
= cp
+ 1 - past_reloc
;
6938 /* Allocate and copy string. The trailing NUL shouldn't
6939 be necessary, but be safe. */
6940 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6941 memcpy (tmpbuf
, input_line_pointer
, first
);
6942 if (second
!= 0 && *past_reloc
!= ' ')
6943 /* Replace the relocation token with ' ', so that
6944 errors like foo@SECLREL321 will be detected. */
6945 tmpbuf
[first
++] = ' ';
6946 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6947 tmpbuf
[first
+ second
] = '\0';
6951 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6952 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6957 /* Might be a symbol version string. Don't as_bad here. */
6964 x86_cons (expressionS
*exp
, int size
)
6966 intel_syntax
= -intel_syntax
;
6969 if (size
== 4 || (object_64bit
&& size
== 8))
6971 /* Handle @GOTOFF and the like in an expression. */
6973 char *gotfree_input_line
;
6976 save
= input_line_pointer
;
6977 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6978 if (gotfree_input_line
)
6979 input_line_pointer
= gotfree_input_line
;
6983 if (gotfree_input_line
)
6985 /* expression () has merrily parsed up to the end of line,
6986 or a comma - in the wrong buffer. Transfer how far
6987 input_line_pointer has moved to the right buffer. */
6988 input_line_pointer
= (save
6989 + (input_line_pointer
- gotfree_input_line
)
6991 free (gotfree_input_line
);
6992 if (exp
->X_op
== O_constant
6993 || exp
->X_op
== O_absent
6994 || exp
->X_op
== O_illegal
6995 || exp
->X_op
== O_register
6996 || exp
->X_op
== O_big
)
6998 char c
= *input_line_pointer
;
6999 *input_line_pointer
= 0;
7000 as_bad (_("missing or invalid expression `%s'"), save
);
7001 *input_line_pointer
= c
;
7008 intel_syntax
= -intel_syntax
;
7011 i386_intel_simplify (exp
);
7015 signed_cons (int size
)
7017 if (flag_code
== CODE_64BIT
)
7025 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7032 if (exp
.X_op
== O_symbol
)
7033 exp
.X_op
= O_secrel
;
7035 emit_expr (&exp
, 4);
7037 while (*input_line_pointer
++ == ',');
7039 input_line_pointer
--;
7040 demand_empty_rest_of_line ();
7045 i386_immediate (char *imm_start
)
7047 char *save_input_line_pointer
;
7048 char *gotfree_input_line
;
7051 i386_operand_type types
;
7053 operand_type_set (&types
, ~0);
7055 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7057 as_bad (_("at most %d immediate operands are allowed"),
7058 MAX_IMMEDIATE_OPERANDS
);
7062 exp
= &im_expressions
[i
.imm_operands
++];
7063 i
.op
[this_operand
].imms
= exp
;
7065 if (is_space_char (*imm_start
))
7068 save_input_line_pointer
= input_line_pointer
;
7069 input_line_pointer
= imm_start
;
7071 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7072 if (gotfree_input_line
)
7073 input_line_pointer
= gotfree_input_line
;
7075 exp_seg
= expression (exp
);
7078 if (*input_line_pointer
)
7079 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7081 input_line_pointer
= save_input_line_pointer
;
7082 if (gotfree_input_line
)
7084 free (gotfree_input_line
);
7086 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7087 exp
->X_op
= O_illegal
;
7090 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7094 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7095 i386_operand_type types
, const char *imm_start
)
7097 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7100 as_bad (_("missing or invalid immediate expression `%s'"),
7104 else if (exp
->X_op
== O_constant
)
7106 /* Size it properly later. */
7107 i
.types
[this_operand
].bitfield
.imm64
= 1;
7108 /* If not 64bit, sign extend val. */
7109 if (flag_code
!= CODE_64BIT
7110 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7112 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7114 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7115 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7116 && exp_seg
!= absolute_section
7117 && exp_seg
!= text_section
7118 && exp_seg
!= data_section
7119 && exp_seg
!= bss_section
7120 && exp_seg
!= undefined_section
7121 && !bfd_is_com_section (exp_seg
))
7123 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7127 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7130 as_bad (_("illegal immediate register operand %s"), imm_start
);
7135 /* This is an address. The size of the address will be
7136 determined later, depending on destination register,
7137 suffix, or the default for the section. */
7138 i
.types
[this_operand
].bitfield
.imm8
= 1;
7139 i
.types
[this_operand
].bitfield
.imm16
= 1;
7140 i
.types
[this_operand
].bitfield
.imm32
= 1;
7141 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7142 i
.types
[this_operand
].bitfield
.imm64
= 1;
7143 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7151 i386_scale (char *scale
)
7154 char *save
= input_line_pointer
;
7156 input_line_pointer
= scale
;
7157 val
= get_absolute_expression ();
7162 i
.log2_scale_factor
= 0;
7165 i
.log2_scale_factor
= 1;
7168 i
.log2_scale_factor
= 2;
7171 i
.log2_scale_factor
= 3;
7175 char sep
= *input_line_pointer
;
7177 *input_line_pointer
= '\0';
7178 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7180 *input_line_pointer
= sep
;
7181 input_line_pointer
= save
;
7185 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7187 as_warn (_("scale factor of %d without an index register"),
7188 1 << i
.log2_scale_factor
);
7189 i
.log2_scale_factor
= 0;
7191 scale
= input_line_pointer
;
7192 input_line_pointer
= save
;
7197 i386_displacement (char *disp_start
, char *disp_end
)
7201 char *save_input_line_pointer
;
7202 char *gotfree_input_line
;
7204 i386_operand_type bigdisp
, types
= anydisp
;
7207 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7209 as_bad (_("at most %d displacement operands are allowed"),
7210 MAX_MEMORY_OPERANDS
);
7214 operand_type_set (&bigdisp
, 0);
7215 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7216 || (!current_templates
->start
->opcode_modifier
.jump
7217 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7219 bigdisp
.bitfield
.disp32
= 1;
7220 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7221 if (flag_code
== CODE_64BIT
)
7225 bigdisp
.bitfield
.disp32s
= 1;
7226 bigdisp
.bitfield
.disp64
= 1;
7229 else if ((flag_code
== CODE_16BIT
) ^ override
)
7231 bigdisp
.bitfield
.disp32
= 0;
7232 bigdisp
.bitfield
.disp16
= 1;
7237 /* For PC-relative branches, the width of the displacement
7238 is dependent upon data size, not address size. */
7239 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7240 if (flag_code
== CODE_64BIT
)
7242 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7243 bigdisp
.bitfield
.disp16
= 1;
7246 bigdisp
.bitfield
.disp32
= 1;
7247 bigdisp
.bitfield
.disp32s
= 1;
7253 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7255 : LONG_MNEM_SUFFIX
));
7256 bigdisp
.bitfield
.disp32
= 1;
7257 if ((flag_code
== CODE_16BIT
) ^ override
)
7259 bigdisp
.bitfield
.disp32
= 0;
7260 bigdisp
.bitfield
.disp16
= 1;
7264 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7267 exp
= &disp_expressions
[i
.disp_operands
];
7268 i
.op
[this_operand
].disps
= exp
;
7270 save_input_line_pointer
= input_line_pointer
;
7271 input_line_pointer
= disp_start
;
7272 END_STRING_AND_SAVE (disp_end
);
7274 #ifndef GCC_ASM_O_HACK
7275 #define GCC_ASM_O_HACK 0
7278 END_STRING_AND_SAVE (disp_end
+ 1);
7279 if (i
.types
[this_operand
].bitfield
.baseIndex
7280 && displacement_string_end
[-1] == '+')
7282 /* This hack is to avoid a warning when using the "o"
7283 constraint within gcc asm statements.
7286 #define _set_tssldt_desc(n,addr,limit,type) \
7287 __asm__ __volatile__ ( \
7289 "movw %w1,2+%0\n\t" \
7291 "movb %b1,4+%0\n\t" \
7292 "movb %4,5+%0\n\t" \
7293 "movb $0,6+%0\n\t" \
7294 "movb %h1,7+%0\n\t" \
7296 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7298 This works great except that the output assembler ends
7299 up looking a bit weird if it turns out that there is
7300 no offset. You end up producing code that looks like:
7313 So here we provide the missing zero. */
7315 *displacement_string_end
= '0';
7318 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7319 if (gotfree_input_line
)
7320 input_line_pointer
= gotfree_input_line
;
7322 exp_seg
= expression (exp
);
7325 if (*input_line_pointer
)
7326 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7328 RESTORE_END_STRING (disp_end
+ 1);
7330 input_line_pointer
= save_input_line_pointer
;
7331 if (gotfree_input_line
)
7333 free (gotfree_input_line
);
7335 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7336 exp
->X_op
= O_illegal
;
7339 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7341 RESTORE_END_STRING (disp_end
);
7347 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7348 i386_operand_type types
, const char *disp_start
)
7350 i386_operand_type bigdisp
;
7353 /* We do this to make sure that the section symbol is in
7354 the symbol table. We will ultimately change the relocation
7355 to be relative to the beginning of the section. */
7356 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7357 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7358 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7360 if (exp
->X_op
!= O_symbol
)
7363 if (S_IS_LOCAL (exp
->X_add_symbol
)
7364 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7365 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7366 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7367 exp
->X_op
= O_subtract
;
7368 exp
->X_op_symbol
= GOT_symbol
;
7369 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7370 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7371 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7372 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7374 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7377 else if (exp
->X_op
== O_absent
7378 || exp
->X_op
== O_illegal
7379 || exp
->X_op
== O_big
)
7382 as_bad (_("missing or invalid displacement expression `%s'"),
7387 else if (flag_code
== CODE_64BIT
7388 && !i
.prefix
[ADDR_PREFIX
]
7389 && exp
->X_op
== O_constant
)
7391 /* Since displacement is signed extended to 64bit, don't allow
7392 disp32 and turn off disp32s if they are out of range. */
7393 i
.types
[this_operand
].bitfield
.disp32
= 0;
7394 if (!fits_in_signed_long (exp
->X_add_number
))
7396 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7397 if (i
.types
[this_operand
].bitfield
.baseindex
)
7399 as_bad (_("0x%lx out range of signed 32bit displacement"),
7400 (long) exp
->X_add_number
);
7406 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7407 else if (exp
->X_op
!= O_constant
7408 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7409 && exp_seg
!= absolute_section
7410 && exp_seg
!= text_section
7411 && exp_seg
!= data_section
7412 && exp_seg
!= bss_section
7413 && exp_seg
!= undefined_section
7414 && !bfd_is_com_section (exp_seg
))
7416 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7421 /* Check if this is a displacement only operand. */
7422 bigdisp
= i
.types
[this_operand
];
7423 bigdisp
.bitfield
.disp8
= 0;
7424 bigdisp
.bitfield
.disp16
= 0;
7425 bigdisp
.bitfield
.disp32
= 0;
7426 bigdisp
.bitfield
.disp32s
= 0;
7427 bigdisp
.bitfield
.disp64
= 0;
7428 if (operand_type_all_zero (&bigdisp
))
7429 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7435 /* Make sure the memory operand we've been dealt is valid.
7436 Return 1 on success, 0 on a failure. */
7439 i386_index_check (const char *operand_string
)
7442 const char *kind
= "base/index";
7443 #if INFER_ADDR_PREFIX
7449 if (current_templates
->start
->opcode_modifier
.isstring
7450 && !current_templates
->start
->opcode_modifier
.immext
7451 && (current_templates
->end
[-1].opcode_modifier
.isstring
7454 /* Memory operands of string insns are special in that they only allow
7455 a single register (rDI, rSI, or rBX) as their memory address. */
7456 unsigned int expected
;
7458 kind
= "string address";
7460 if (current_templates
->start
->opcode_modifier
.w
)
7462 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7464 if (!type
.bitfield
.baseindex
7465 || ((!i
.mem_operands
!= !intel_syntax
)
7466 && current_templates
->end
[-1].operand_types
[1]
7467 .bitfield
.baseindex
))
7468 type
= current_templates
->end
[-1].operand_types
[1];
7469 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7472 expected
= 3 /* rBX */;
7474 if (!i
.base_reg
|| i
.index_reg
7475 || operand_type_check (i
.types
[this_operand
], disp
))
7477 else if (!(flag_code
== CODE_64BIT
7478 ? i
.prefix
[ADDR_PREFIX
]
7479 ? i
.base_reg
->reg_type
.bitfield
.reg32
7480 : i
.base_reg
->reg_type
.bitfield
.reg64
7481 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7482 ? i
.base_reg
->reg_type
.bitfield
.reg32
7483 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7485 else if (register_number (i
.base_reg
) != expected
)
7492 for (j
= 0; j
< i386_regtab_size
; ++j
)
7493 if ((flag_code
== CODE_64BIT
7494 ? i
.prefix
[ADDR_PREFIX
]
7495 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7496 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7497 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7498 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7499 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7500 && register_number(i386_regtab
+ j
) == expected
)
7502 gas_assert (j
< i386_regtab_size
);
7503 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7505 intel_syntax
? '[' : '(',
7507 i386_regtab
[j
].reg_name
,
7508 intel_syntax
? ']' : ')');
7512 else if (flag_code
== CODE_64BIT
)
7515 && ((i
.prefix
[ADDR_PREFIX
] == 0
7516 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7517 || (i
.prefix
[ADDR_PREFIX
]
7518 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7520 || i
.base_reg
->reg_num
!=
7521 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7523 && !(i
.index_reg
->reg_type
.bitfield
.regxmm
7524 || i
.index_reg
->reg_type
.bitfield
.regymm
)
7525 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7526 || (i
.prefix
[ADDR_PREFIX
] == 0
7527 && i
.index_reg
->reg_num
!= RegRiz
7528 && !i
.index_reg
->reg_type
.bitfield
.reg64
7530 || (i
.prefix
[ADDR_PREFIX
]
7531 && i
.index_reg
->reg_num
!= RegEiz
7532 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7537 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7541 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7542 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7544 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7545 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7547 && i
.base_reg
->reg_num
< 6
7548 && i
.index_reg
->reg_num
>= 6
7549 && i
.log2_scale_factor
== 0))))
7556 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7558 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7559 && !i
.index_reg
->reg_type
.bitfield
.regymm
7560 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7561 && i
.index_reg
->reg_num
!= RegEiz
)
7562 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7568 #if INFER_ADDR_PREFIX
7569 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7571 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7573 /* Change the size of any displacement too. At most one of
7574 Disp16 or Disp32 is set.
7575 FIXME. There doesn't seem to be any real need for separate
7576 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7577 Removing them would probably clean up the code quite a lot. */
7578 if (flag_code
!= CODE_64BIT
7579 && (i
.types
[this_operand
].bitfield
.disp16
7580 || i
.types
[this_operand
].bitfield
.disp32
))
7581 i
.types
[this_operand
]
7582 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7587 as_bad (_("`%s' is not a valid %s expression"),
7592 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7594 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7595 ? flag_code
== CODE_32BIT
7604 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7608 i386_att_operand (char *operand_string
)
7612 char *op_string
= operand_string
;
7614 if (is_space_char (*op_string
))
7617 /* We check for an absolute prefix (differentiating,
7618 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7619 if (*op_string
== ABSOLUTE_PREFIX
)
7622 if (is_space_char (*op_string
))
7624 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7627 /* Check if operand is a register. */
7628 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7630 i386_operand_type temp
;
7632 /* Check for a segment override by searching for ':' after a
7633 segment register. */
7635 if (is_space_char (*op_string
))
7637 if (*op_string
== ':'
7638 && (r
->reg_type
.bitfield
.sreg2
7639 || r
->reg_type
.bitfield
.sreg3
))
7644 i
.seg
[i
.mem_operands
] = &es
;
7647 i
.seg
[i
.mem_operands
] = &cs
;
7650 i
.seg
[i
.mem_operands
] = &ss
;
7653 i
.seg
[i
.mem_operands
] = &ds
;
7656 i
.seg
[i
.mem_operands
] = &fs
;
7659 i
.seg
[i
.mem_operands
] = &gs
;
7663 /* Skip the ':' and whitespace. */
7665 if (is_space_char (*op_string
))
7668 if (!is_digit_char (*op_string
)
7669 && !is_identifier_char (*op_string
)
7670 && *op_string
!= '('
7671 && *op_string
!= ABSOLUTE_PREFIX
)
7673 as_bad (_("bad memory operand `%s'"), op_string
);
7676 /* Handle case of %es:*foo. */
7677 if (*op_string
== ABSOLUTE_PREFIX
)
7680 if (is_space_char (*op_string
))
7682 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7684 goto do_memory_reference
;
7688 as_bad (_("junk `%s' after register"), op_string
);
7692 temp
.bitfield
.baseindex
= 0;
7693 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7695 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7696 i
.op
[this_operand
].regs
= r
;
7699 else if (*op_string
== REGISTER_PREFIX
)
7701 as_bad (_("bad register name `%s'"), op_string
);
7704 else if (*op_string
== IMMEDIATE_PREFIX
)
7707 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7709 as_bad (_("immediate operand illegal with absolute jump"));
7712 if (!i386_immediate (op_string
))
7715 else if (is_digit_char (*op_string
)
7716 || is_identifier_char (*op_string
)
7717 || *op_string
== '(')
7719 /* This is a memory reference of some sort. */
7722 /* Start and end of displacement string expression (if found). */
7723 char *displacement_string_start
;
7724 char *displacement_string_end
;
7726 do_memory_reference
:
7727 if ((i
.mem_operands
== 1
7728 && !current_templates
->start
->opcode_modifier
.isstring
)
7729 || i
.mem_operands
== 2)
7731 as_bad (_("too many memory references for `%s'"),
7732 current_templates
->start
->name
);
7736 /* Check for base index form. We detect the base index form by
7737 looking for an ')' at the end of the operand, searching
7738 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7740 base_string
= op_string
+ strlen (op_string
);
7743 if (is_space_char (*base_string
))
7746 /* If we only have a displacement, set-up for it to be parsed later. */
7747 displacement_string_start
= op_string
;
7748 displacement_string_end
= base_string
+ 1;
7750 if (*base_string
== ')')
7753 unsigned int parens_balanced
= 1;
7754 /* We've already checked that the number of left & right ()'s are
7755 equal, so this loop will not be infinite. */
7759 if (*base_string
== ')')
7761 if (*base_string
== '(')
7764 while (parens_balanced
);
7766 temp_string
= base_string
;
7768 /* Skip past '(' and whitespace. */
7770 if (is_space_char (*base_string
))
7773 if (*base_string
== ','
7774 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7777 displacement_string_end
= temp_string
;
7779 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7783 base_string
= end_op
;
7784 if (is_space_char (*base_string
))
7788 /* There may be an index reg or scale factor here. */
7789 if (*base_string
== ',')
7792 if (is_space_char (*base_string
))
7795 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7798 base_string
= end_op
;
7799 if (is_space_char (*base_string
))
7801 if (*base_string
== ',')
7804 if (is_space_char (*base_string
))
7807 else if (*base_string
!= ')')
7809 as_bad (_("expecting `,' or `)' "
7810 "after index register in `%s'"),
7815 else if (*base_string
== REGISTER_PREFIX
)
7817 end_op
= strchr (base_string
, ',');
7820 as_bad (_("bad register name `%s'"), base_string
);
7824 /* Check for scale factor. */
7825 if (*base_string
!= ')')
7827 char *end_scale
= i386_scale (base_string
);
7832 base_string
= end_scale
;
7833 if (is_space_char (*base_string
))
7835 if (*base_string
!= ')')
7837 as_bad (_("expecting `)' "
7838 "after scale factor in `%s'"),
7843 else if (!i
.index_reg
)
7845 as_bad (_("expecting index register or scale factor "
7846 "after `,'; got '%c'"),
7851 else if (*base_string
!= ')')
7853 as_bad (_("expecting `,' or `)' "
7854 "after base register in `%s'"),
7859 else if (*base_string
== REGISTER_PREFIX
)
7861 end_op
= strchr (base_string
, ',');
7864 as_bad (_("bad register name `%s'"), base_string
);
7869 /* If there's an expression beginning the operand, parse it,
7870 assuming displacement_string_start and
7871 displacement_string_end are meaningful. */
7872 if (displacement_string_start
!= displacement_string_end
)
7874 if (!i386_displacement (displacement_string_start
,
7875 displacement_string_end
))
7879 /* Special case for (%dx) while doing input/output op. */
7881 && operand_type_equal (&i
.base_reg
->reg_type
,
7882 ®16_inoutportreg
)
7884 && i
.log2_scale_factor
== 0
7885 && i
.seg
[i
.mem_operands
] == 0
7886 && !operand_type_check (i
.types
[this_operand
], disp
))
7888 i
.types
[this_operand
] = inoutportreg
;
7892 if (i386_index_check (operand_string
) == 0)
7894 i
.types
[this_operand
].bitfield
.mem
= 1;
7899 /* It's not a memory operand; argh! */
7900 as_bad (_("invalid char %s beginning operand %d `%s'"),
7901 output_invalid (*op_string
),
7906 return 1; /* Normal return. */
7909 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7910 that an rs_machine_dependent frag may reach. */
7913 i386_frag_max_var (fragS
*frag
)
7915 /* The only relaxable frags are for jumps.
7916 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7917 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7918 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7921 /* md_estimate_size_before_relax()
7923 Called just before relax() for rs_machine_dependent frags. The x86
7924 assembler uses these frags to handle variable size jump
7927 Any symbol that is now undefined will not become defined.
7928 Return the correct fr_subtype in the frag.
7929 Return the initial "guess for variable size of frag" to caller.
7930 The guess is actually the growth beyond the fixed part. Whatever
7931 we do to grow the fixed or variable part contributes to our
7935 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7937 /* We've already got fragP->fr_subtype right; all we have to do is
7938 check for un-relaxable symbols. On an ELF system, we can't relax
7939 an externally visible symbol, because it may be overridden by a
7941 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7942 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7944 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7945 || S_IS_WEAK (fragP
->fr_symbol
)
7946 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7947 & BSF_GNU_INDIRECT_FUNCTION
))))
7949 #if defined (OBJ_COFF) && defined (TE_PE)
7950 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7951 && S_IS_WEAK (fragP
->fr_symbol
))
7955 /* Symbol is undefined in this segment, or we need to keep a
7956 reloc so that weak symbols can be overridden. */
7957 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7958 enum bfd_reloc_code_real reloc_type
;
7959 unsigned char *opcode
;
7962 if (fragP
->fr_var
!= NO_RELOC
)
7963 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7965 reloc_type
= BFD_RELOC_16_PCREL
;
7967 reloc_type
= BFD_RELOC_32_PCREL
;
7969 old_fr_fix
= fragP
->fr_fix
;
7970 opcode
= (unsigned char *) fragP
->fr_opcode
;
7972 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7975 /* Make jmp (0xeb) a (d)word displacement jump. */
7977 fragP
->fr_fix
+= size
;
7978 fix_new (fragP
, old_fr_fix
, size
,
7980 fragP
->fr_offset
, 1,
7986 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7988 /* Negate the condition, and branch past an
7989 unconditional jump. */
7992 /* Insert an unconditional jump. */
7994 /* We added two extra opcode bytes, and have a two byte
7996 fragP
->fr_fix
+= 2 + 2;
7997 fix_new (fragP
, old_fr_fix
+ 2, 2,
7999 fragP
->fr_offset
, 1,
8006 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8011 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8013 fragP
->fr_offset
, 1,
8015 fixP
->fx_signed
= 1;
8019 /* This changes the byte-displacement jump 0x7N
8020 to the (d)word-displacement jump 0x0f,0x8N. */
8021 opcode
[1] = opcode
[0] + 0x10;
8022 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8023 /* We've added an opcode byte. */
8024 fragP
->fr_fix
+= 1 + size
;
8025 fix_new (fragP
, old_fr_fix
+ 1, size
,
8027 fragP
->fr_offset
, 1,
8032 BAD_CASE (fragP
->fr_subtype
);
8036 return fragP
->fr_fix
- old_fr_fix
;
8039 /* Guess size depending on current relax state. Initially the relax
8040 state will correspond to a short jump and we return 1, because
8041 the variable part of the frag (the branch offset) is one byte
8042 long. However, we can relax a section more than once and in that
8043 case we must either set fr_subtype back to the unrelaxed state,
8044 or return the value for the appropriate branch. */
8045 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8048 /* Called after relax() is finished.
8050 In: Address of frag.
8051 fr_type == rs_machine_dependent.
8052 fr_subtype is what the address relaxed to.
8054 Out: Any fixSs and constants are set up.
8055 Caller will turn frag into a ".space 0". */
8058 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8061 unsigned char *opcode
;
8062 unsigned char *where_to_put_displacement
= NULL
;
8063 offsetT target_address
;
8064 offsetT opcode_address
;
8065 unsigned int extension
= 0;
8066 offsetT displacement_from_opcode_start
;
8068 opcode
= (unsigned char *) fragP
->fr_opcode
;
8070 /* Address we want to reach in file space. */
8071 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8073 /* Address opcode resides at in file space. */
8074 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8076 /* Displacement from opcode start to fill into instruction. */
8077 displacement_from_opcode_start
= target_address
- opcode_address
;
8079 if ((fragP
->fr_subtype
& BIG
) == 0)
8081 /* Don't have to change opcode. */
8082 extension
= 1; /* 1 opcode + 1 displacement */
8083 where_to_put_displacement
= &opcode
[1];
8087 if (no_cond_jump_promotion
8088 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8089 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8090 _("long jump required"));
8092 switch (fragP
->fr_subtype
)
8094 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8095 extension
= 4; /* 1 opcode + 4 displacement */
8097 where_to_put_displacement
= &opcode
[1];
8100 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8101 extension
= 2; /* 1 opcode + 2 displacement */
8103 where_to_put_displacement
= &opcode
[1];
8106 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8107 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8108 extension
= 5; /* 2 opcode + 4 displacement */
8109 opcode
[1] = opcode
[0] + 0x10;
8110 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8111 where_to_put_displacement
= &opcode
[2];
8114 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8115 extension
= 3; /* 2 opcode + 2 displacement */
8116 opcode
[1] = opcode
[0] + 0x10;
8117 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8118 where_to_put_displacement
= &opcode
[2];
8121 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8126 where_to_put_displacement
= &opcode
[3];
8130 BAD_CASE (fragP
->fr_subtype
);
8135 /* If size if less then four we are sure that the operand fits,
8136 but if it's 4, then it could be that the displacement is larger
8138 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8140 && ((addressT
) (displacement_from_opcode_start
- extension
8141 + ((addressT
) 1 << 31))
8142 > (((addressT
) 2 << 31) - 1)))
8144 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8145 _("jump target out of range"));
8146 /* Make us emit 0. */
8147 displacement_from_opcode_start
= extension
;
8149 /* Now put displacement after opcode. */
8150 md_number_to_chars ((char *) where_to_put_displacement
,
8151 (valueT
) (displacement_from_opcode_start
- extension
),
8152 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8153 fragP
->fr_fix
+= extension
;
8156 /* Apply a fixup (fixP) to segment data, once it has been determined
8157 by our caller that we have all the info we need to fix it up.
8159 Parameter valP is the pointer to the value of the bits.
8161 On the 386, immediates, displacements, and data pointers are all in
8162 the same (little-endian) format, so we don't need to care about which
8166 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8168 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8169 valueT value
= *valP
;
8171 #if !defined (TE_Mach)
8174 switch (fixP
->fx_r_type
)
8180 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8183 case BFD_RELOC_X86_64_32S
:
8184 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8187 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8190 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8195 if (fixP
->fx_addsy
!= NULL
8196 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8197 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8198 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8199 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8200 && !use_rela_relocations
)
8202 /* This is a hack. There should be a better way to handle this.
8203 This covers for the fact that bfd_install_relocation will
8204 subtract the current location (for partial_inplace, PC relative
8205 relocations); see more below. */
8209 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8212 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8217 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8220 || (symbol_section_p (fixP
->fx_addsy
)
8221 && sym_seg
!= absolute_section
))
8222 && !generic_force_reloc (fixP
))
8224 /* Yes, we add the values in twice. This is because
8225 bfd_install_relocation subtracts them out again. I think
8226 bfd_install_relocation is broken, but I don't dare change
8228 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8232 #if defined (OBJ_COFF) && defined (TE_PE)
8233 /* For some reason, the PE format does not store a
8234 section address offset for a PC relative symbol. */
8235 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8236 || S_IS_WEAK (fixP
->fx_addsy
))
8237 value
+= md_pcrel_from (fixP
);
8240 #if defined (OBJ_COFF) && defined (TE_PE)
8241 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8243 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8247 /* Fix a few things - the dynamic linker expects certain values here,
8248 and we must not disappoint it. */
8249 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8250 if (IS_ELF
&& fixP
->fx_addsy
)
8251 switch (fixP
->fx_r_type
)
8253 case BFD_RELOC_386_PLT32
:
8254 case BFD_RELOC_X86_64_PLT32
:
8255 /* Make the jump instruction point to the address of the operand. At
8256 runtime we merely add the offset to the actual PLT entry. */
8260 case BFD_RELOC_386_TLS_GD
:
8261 case BFD_RELOC_386_TLS_LDM
:
8262 case BFD_RELOC_386_TLS_IE_32
:
8263 case BFD_RELOC_386_TLS_IE
:
8264 case BFD_RELOC_386_TLS_GOTIE
:
8265 case BFD_RELOC_386_TLS_GOTDESC
:
8266 case BFD_RELOC_X86_64_TLSGD
:
8267 case BFD_RELOC_X86_64_TLSLD
:
8268 case BFD_RELOC_X86_64_GOTTPOFF
:
8269 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8270 value
= 0; /* Fully resolved at runtime. No addend. */
8272 case BFD_RELOC_386_TLS_LE
:
8273 case BFD_RELOC_386_TLS_LDO_32
:
8274 case BFD_RELOC_386_TLS_LE_32
:
8275 case BFD_RELOC_X86_64_DTPOFF32
:
8276 case BFD_RELOC_X86_64_DTPOFF64
:
8277 case BFD_RELOC_X86_64_TPOFF32
:
8278 case BFD_RELOC_X86_64_TPOFF64
:
8279 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8282 case BFD_RELOC_386_TLS_DESC_CALL
:
8283 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8284 value
= 0; /* Fully resolved at runtime. No addend. */
8285 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8289 case BFD_RELOC_386_GOT32
:
8290 case BFD_RELOC_X86_64_GOT32
:
8291 value
= 0; /* Fully resolved at runtime. No addend. */
8294 case BFD_RELOC_VTABLE_INHERIT
:
8295 case BFD_RELOC_VTABLE_ENTRY
:
8302 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8304 #endif /* !defined (TE_Mach) */
8306 /* Are we finished with this relocation now? */
8307 if (fixP
->fx_addsy
== NULL
)
8309 #if defined (OBJ_COFF) && defined (TE_PE)
8310 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8313 /* Remember value for tc_gen_reloc. */
8314 fixP
->fx_addnumber
= value
;
8315 /* Clear out the frag for now. */
8319 else if (use_rela_relocations
)
8321 fixP
->fx_no_overflow
= 1;
8322 /* Remember value for tc_gen_reloc. */
8323 fixP
->fx_addnumber
= value
;
8327 md_number_to_chars (p
, value
, fixP
->fx_size
);
8331 md_atof (int type
, char *litP
, int *sizeP
)
8333 /* This outputs the LITTLENUMs in REVERSE order;
8334 in accord with the bigendian 386. */
8335 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8338 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8341 output_invalid (int c
)
8344 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8347 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8348 "(0x%x)", (unsigned char) c
);
8349 return output_invalid_buf
;
8352 /* REG_STRING starts *before* REGISTER_PREFIX. */
8354 static const reg_entry
*
8355 parse_real_register (char *reg_string
, char **end_op
)
8357 char *s
= reg_string
;
8359 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8362 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8363 if (*s
== REGISTER_PREFIX
)
8366 if (is_space_char (*s
))
8370 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8372 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8373 return (const reg_entry
*) NULL
;
8377 /* For naked regs, make sure that we are not dealing with an identifier.
8378 This prevents confusing an identifier like `eax_var' with register
8380 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8381 return (const reg_entry
*) NULL
;
8385 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8387 /* Handle floating point regs, allowing spaces in the (i) part. */
8388 if (r
== i386_regtab
/* %st is first entry of table */)
8390 if (is_space_char (*s
))
8395 if (is_space_char (*s
))
8397 if (*s
>= '0' && *s
<= '7')
8401 if (is_space_char (*s
))
8406 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8411 /* We have "%st(" then garbage. */
8412 return (const reg_entry
*) NULL
;
8416 if (r
== NULL
|| allow_pseudo_reg
)
8419 if (operand_type_all_zero (&r
->reg_type
))
8420 return (const reg_entry
*) NULL
;
8422 if ((r
->reg_type
.bitfield
.reg32
8423 || r
->reg_type
.bitfield
.sreg3
8424 || r
->reg_type
.bitfield
.control
8425 || r
->reg_type
.bitfield
.debug
8426 || r
->reg_type
.bitfield
.test
)
8427 && !cpu_arch_flags
.bitfield
.cpui386
)
8428 return (const reg_entry
*) NULL
;
8430 if (r
->reg_type
.bitfield
.floatreg
8431 && !cpu_arch_flags
.bitfield
.cpu8087
8432 && !cpu_arch_flags
.bitfield
.cpu287
8433 && !cpu_arch_flags
.bitfield
.cpu387
)
8434 return (const reg_entry
*) NULL
;
8436 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8437 return (const reg_entry
*) NULL
;
8439 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8440 return (const reg_entry
*) NULL
;
8442 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8443 return (const reg_entry
*) NULL
;
8445 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8446 if (!allow_index_reg
8447 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8448 return (const reg_entry
*) NULL
;
8450 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8451 || r
->reg_type
.bitfield
.reg64
)
8452 && (!cpu_arch_flags
.bitfield
.cpulm
8453 || !operand_type_equal (&r
->reg_type
, &control
))
8454 && flag_code
!= CODE_64BIT
)
8455 return (const reg_entry
*) NULL
;
8457 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8458 return (const reg_entry
*) NULL
;
8463 /* REG_STRING starts *before* REGISTER_PREFIX. */
8465 static const reg_entry
*
8466 parse_register (char *reg_string
, char **end_op
)
8470 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8471 r
= parse_real_register (reg_string
, end_op
);
8476 char *save
= input_line_pointer
;
8480 input_line_pointer
= reg_string
;
8481 c
= get_symbol_end ();
8482 symbolP
= symbol_find (reg_string
);
8483 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8485 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8487 know (e
->X_op
== O_register
);
8488 know (e
->X_add_number
>= 0
8489 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8490 r
= i386_regtab
+ e
->X_add_number
;
8491 *end_op
= input_line_pointer
;
8493 *input_line_pointer
= c
;
8494 input_line_pointer
= save
;
8500 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8503 char *end
= input_line_pointer
;
8506 r
= parse_register (name
, &input_line_pointer
);
8507 if (r
&& end
<= input_line_pointer
)
8509 *nextcharP
= *input_line_pointer
;
8510 *input_line_pointer
= 0;
8511 e
->X_op
= O_register
;
8512 e
->X_add_number
= r
- i386_regtab
;
8515 input_line_pointer
= end
;
8517 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8521 md_operand (expressionS
*e
)
8526 switch (*input_line_pointer
)
8528 case REGISTER_PREFIX
:
8529 r
= parse_real_register (input_line_pointer
, &end
);
8532 e
->X_op
= O_register
;
8533 e
->X_add_number
= r
- i386_regtab
;
8534 input_line_pointer
= end
;
8539 gas_assert (intel_syntax
);
8540 end
= input_line_pointer
++;
8542 if (*input_line_pointer
== ']')
8544 ++input_line_pointer
;
8545 e
->X_op_symbol
= make_expr_symbol (e
);
8546 e
->X_add_symbol
= NULL
;
8547 e
->X_add_number
= 0;
8553 input_line_pointer
= end
;
8560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8561 const char *md_shortopts
= "kVQ:sqn";
8563 const char *md_shortopts
= "qn";
8566 #define OPTION_32 (OPTION_MD_BASE + 0)
8567 #define OPTION_64 (OPTION_MD_BASE + 1)
8568 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8569 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8570 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8571 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8572 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8573 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8574 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8575 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8576 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8577 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8578 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8579 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8580 #define OPTION_X32 (OPTION_MD_BASE + 14)
8582 struct option md_longopts
[] =
8584 {"32", no_argument
, NULL
, OPTION_32
},
8585 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8586 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8587 {"64", no_argument
, NULL
, OPTION_64
},
8589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8590 {"x32", no_argument
, NULL
, OPTION_X32
},
8592 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8593 {"march", required_argument
, NULL
, OPTION_MARCH
},
8594 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8595 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8596 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8597 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8598 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8599 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8600 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8601 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8602 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8603 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8604 {NULL
, no_argument
, NULL
, 0}
8606 size_t md_longopts_size
= sizeof (md_longopts
);
8609 md_parse_option (int c
, char *arg
)
8617 optimize_align_code
= 0;
8624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8625 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8626 should be emitted or not. FIXME: Not implemented. */
8630 /* -V: SVR4 argument to print version ID. */
8632 print_version_id ();
8635 /* -k: Ignore for FreeBSD compatibility. */
8640 /* -s: On i386 Solaris, this tells the native assembler to use
8641 .stab instead of .stab.excl. We always use .stab anyhow. */
8644 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8645 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8648 const char **list
, **l
;
8650 list
= bfd_target_list ();
8651 for (l
= list
; *l
!= NULL
; l
++)
8652 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8653 || strcmp (*l
, "coff-x86-64") == 0
8654 || strcmp (*l
, "pe-x86-64") == 0
8655 || strcmp (*l
, "pei-x86-64") == 0
8656 || strcmp (*l
, "mach-o-x86-64") == 0)
8658 default_arch
= "x86_64";
8662 as_fatal (_("no compiled in support for x86_64"));
8668 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8672 const char **list
, **l
;
8674 list
= bfd_target_list ();
8675 for (l
= list
; *l
!= NULL
; l
++)
8676 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8678 default_arch
= "x86_64:32";
8682 as_fatal (_("no compiled in support for 32bit x86_64"));
8686 as_fatal (_("32bit x86_64 is only supported for ELF"));
8691 default_arch
= "i386";
8695 #ifdef SVR4_COMMENT_CHARS
8700 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8702 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8706 i386_comment_chars
= n
;
8712 arch
= xstrdup (arg
);
8716 as_fatal (_("invalid -march= option: `%s'"), arg
);
8717 next
= strchr (arch
, '+');
8720 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8722 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8725 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8728 cpu_arch_name
= cpu_arch
[j
].name
;
8729 cpu_sub_arch_name
= NULL
;
8730 cpu_arch_flags
= cpu_arch
[j
].flags
;
8731 cpu_arch_isa
= cpu_arch
[j
].type
;
8732 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8733 if (!cpu_arch_tune_set
)
8735 cpu_arch_tune
= cpu_arch_isa
;
8736 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8740 else if (*cpu_arch
[j
].name
== '.'
8741 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8743 /* ISA entension. */
8744 i386_cpu_flags flags
;
8746 if (!cpu_arch
[j
].negated
)
8747 flags
= cpu_flags_or (cpu_arch_flags
,
8750 flags
= cpu_flags_and_not (cpu_arch_flags
,
8752 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8754 if (cpu_sub_arch_name
)
8756 char *name
= cpu_sub_arch_name
;
8757 cpu_sub_arch_name
= concat (name
,
8759 (const char *) NULL
);
8763 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8764 cpu_arch_flags
= flags
;
8765 cpu_arch_isa_flags
= flags
;
8771 if (j
>= ARRAY_SIZE (cpu_arch
))
8772 as_fatal (_("invalid -march= option: `%s'"), arg
);
8776 while (next
!= NULL
);
8781 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8782 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8784 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8786 cpu_arch_tune_set
= 1;
8787 cpu_arch_tune
= cpu_arch
[j
].type
;
8788 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8792 if (j
>= ARRAY_SIZE (cpu_arch
))
8793 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8796 case OPTION_MMNEMONIC
:
8797 if (strcasecmp (arg
, "att") == 0)
8799 else if (strcasecmp (arg
, "intel") == 0)
8802 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8805 case OPTION_MSYNTAX
:
8806 if (strcasecmp (arg
, "att") == 0)
8808 else if (strcasecmp (arg
, "intel") == 0)
8811 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8814 case OPTION_MINDEX_REG
:
8815 allow_index_reg
= 1;
8818 case OPTION_MNAKED_REG
:
8819 allow_naked_reg
= 1;
8822 case OPTION_MOLD_GCC
:
8826 case OPTION_MSSE2AVX
:
8830 case OPTION_MSSE_CHECK
:
8831 if (strcasecmp (arg
, "error") == 0)
8832 sse_check
= check_error
;
8833 else if (strcasecmp (arg
, "warning") == 0)
8834 sse_check
= check_warning
;
8835 else if (strcasecmp (arg
, "none") == 0)
8836 sse_check
= check_none
;
8838 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8841 case OPTION_MOPERAND_CHECK
:
8842 if (strcasecmp (arg
, "error") == 0)
8843 operand_check
= check_error
;
8844 else if (strcasecmp (arg
, "warning") == 0)
8845 operand_check
= check_warning
;
8846 else if (strcasecmp (arg
, "none") == 0)
8847 operand_check
= check_none
;
8849 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8852 case OPTION_MAVXSCALAR
:
8853 if (strcasecmp (arg
, "128") == 0)
8855 else if (strcasecmp (arg
, "256") == 0)
8858 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8867 #define MESSAGE_TEMPLATE \
8871 show_arch (FILE *stream
, int ext
, int check
)
8873 static char message
[] = MESSAGE_TEMPLATE
;
8874 char *start
= message
+ 27;
8876 int size
= sizeof (MESSAGE_TEMPLATE
);
8883 left
= size
- (start
- message
);
8884 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8886 /* Should it be skipped? */
8887 if (cpu_arch
[j
].skip
)
8890 name
= cpu_arch
[j
].name
;
8891 len
= cpu_arch
[j
].len
;
8894 /* It is an extension. Skip if we aren't asked to show it. */
8905 /* It is an processor. Skip if we show only extension. */
8908 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8910 /* It is an impossible processor - skip. */
8914 /* Reserve 2 spaces for ", " or ",\0" */
8917 /* Check if there is any room. */
8925 p
= mempcpy (p
, name
, len
);
8929 /* Output the current message now and start a new one. */
8932 fprintf (stream
, "%s\n", message
);
8934 left
= size
- (start
- message
) - len
- 2;
8936 gas_assert (left
>= 0);
8938 p
= mempcpy (p
, name
, len
);
8943 fprintf (stream
, "%s\n", message
);
8947 md_show_usage (FILE *stream
)
8949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8950 fprintf (stream
, _("\
8952 -V print assembler version number\n\
8955 fprintf (stream
, _("\
8956 -n Do not optimize code alignment\n\
8957 -q quieten some warnings\n"));
8958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8959 fprintf (stream
, _("\
8962 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8963 || defined (TE_PE) || defined (TE_PEP))
8964 fprintf (stream
, _("\
8965 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8967 #ifdef SVR4_COMMENT_CHARS
8968 fprintf (stream
, _("\
8969 --divide do not treat `/' as a comment character\n"));
8971 fprintf (stream
, _("\
8972 --divide ignored\n"));
8974 fprintf (stream
, _("\
8975 -march=CPU[,+EXTENSION...]\n\
8976 generate code for CPU and EXTENSION, CPU is one of:\n"));
8977 show_arch (stream
, 0, 1);
8978 fprintf (stream
, _("\
8979 EXTENSION is combination of:\n"));
8980 show_arch (stream
, 1, 0);
8981 fprintf (stream
, _("\
8982 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8983 show_arch (stream
, 0, 0);
8984 fprintf (stream
, _("\
8985 -msse2avx encode SSE instructions with VEX prefix\n"));
8986 fprintf (stream
, _("\
8987 -msse-check=[none|error|warning]\n\
8988 check SSE instructions\n"));
8989 fprintf (stream
, _("\
8990 -moperand-check=[none|error|warning]\n\
8991 check operand combinations for validity\n"));
8992 fprintf (stream
, _("\
8993 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8995 fprintf (stream
, _("\
8996 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8997 fprintf (stream
, _("\
8998 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8999 fprintf (stream
, _("\
9000 -mindex-reg support pseudo index registers\n"));
9001 fprintf (stream
, _("\
9002 -mnaked-reg don't require `%%' prefix for registers\n"));
9003 fprintf (stream
, _("\
9004 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9007 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9008 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9009 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9011 /* Pick the target format to use. */
9014 i386_target_format (void)
9016 if (!strncmp (default_arch
, "x86_64", 6))
9018 update_code_flag (CODE_64BIT
, 1);
9019 if (default_arch
[6] == '\0')
9020 x86_elf_abi
= X86_64_ABI
;
9022 x86_elf_abi
= X86_64_X32_ABI
;
9024 else if (!strcmp (default_arch
, "i386"))
9025 update_code_flag (CODE_32BIT
, 1);
9027 as_fatal (_("unknown architecture"));
9029 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9030 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9031 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9032 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9034 switch (OUTPUT_FLAVOR
)
9036 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9037 case bfd_target_aout_flavour
:
9038 return AOUT_TARGET_FORMAT
;
9040 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9041 # if defined (TE_PE) || defined (TE_PEP)
9042 case bfd_target_coff_flavour
:
9043 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9044 # elif defined (TE_GO32)
9045 case bfd_target_coff_flavour
:
9048 case bfd_target_coff_flavour
:
9052 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9053 case bfd_target_elf_flavour
:
9057 switch (x86_elf_abi
)
9060 format
= ELF_TARGET_FORMAT
;
9063 use_rela_relocations
= 1;
9065 format
= ELF_TARGET_FORMAT64
;
9067 case X86_64_X32_ABI
:
9068 use_rela_relocations
= 1;
9070 disallow_64bit_reloc
= 1;
9071 format
= ELF_TARGET_FORMAT32
;
9074 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9076 if (x86_elf_abi
!= X86_64_ABI
)
9077 as_fatal (_("Intel L1OM is 64bit only"));
9078 return ELF_TARGET_L1OM_FORMAT
;
9080 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9082 if (x86_elf_abi
!= X86_64_ABI
)
9083 as_fatal (_("Intel K1OM is 64bit only"));
9084 return ELF_TARGET_K1OM_FORMAT
;
9090 #if defined (OBJ_MACH_O)
9091 case bfd_target_mach_o_flavour
:
9092 if (flag_code
== CODE_64BIT
)
9094 use_rela_relocations
= 1;
9096 return "mach-o-x86-64";
9099 return "mach-o-i386";
9107 #endif /* OBJ_MAYBE_ more than one */
9109 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9111 i386_elf_emit_arch_note (void)
9113 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9116 asection
*seg
= now_seg
;
9117 subsegT subseg
= now_subseg
;
9118 Elf_Internal_Note i_note
;
9119 Elf_External_Note e_note
;
9120 asection
*note_secp
;
9123 /* Create the .note section. */
9124 note_secp
= subseg_new (".note", 0);
9125 bfd_set_section_flags (stdoutput
,
9127 SEC_HAS_CONTENTS
| SEC_READONLY
);
9129 /* Process the arch string. */
9130 len
= strlen (cpu_arch_name
);
9132 i_note
.namesz
= len
+ 1;
9134 i_note
.type
= NT_ARCH
;
9135 p
= frag_more (sizeof (e_note
.namesz
));
9136 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9137 p
= frag_more (sizeof (e_note
.descsz
));
9138 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9139 p
= frag_more (sizeof (e_note
.type
));
9140 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9141 p
= frag_more (len
+ 1);
9142 strcpy (p
, cpu_arch_name
);
9144 frag_align (2, 0, 0);
9146 subseg_set (seg
, subseg
);
9152 md_undefined_symbol (char *name
)
9154 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9155 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9156 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9157 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9161 if (symbol_find (name
))
9162 as_bad (_("GOT already in symbol table"));
9163 GOT_symbol
= symbol_new (name
, undefined_section
,
9164 (valueT
) 0, &zero_address_frag
);
9171 /* Round up a section size to the appropriate boundary. */
9174 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9176 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9177 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9179 /* For a.out, force the section size to be aligned. If we don't do
9180 this, BFD will align it for us, but it will not write out the
9181 final bytes of the section. This may be a bug in BFD, but it is
9182 easier to fix it here since that is how the other a.out targets
9186 align
= bfd_get_section_alignment (stdoutput
, segment
);
9187 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9194 /* On the i386, PC-relative offsets are relative to the start of the
9195 next instruction. That is, the address of the offset, plus its
9196 size, since the offset is always the last part of the insn. */
9199 md_pcrel_from (fixS
*fixP
)
9201 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9207 s_bss (int ignore ATTRIBUTE_UNUSED
)
9211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9213 obj_elf_section_change_hook ();
9215 temp
= get_absolute_expression ();
9216 subseg_set (bss_section
, (subsegT
) temp
);
9217 demand_empty_rest_of_line ();
9223 i386_validate_fix (fixS
*fixp
)
9225 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9227 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9231 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9236 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9238 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9245 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9248 bfd_reloc_code_real_type code
;
9250 switch (fixp
->fx_r_type
)
9252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9253 case BFD_RELOC_SIZE32
:
9254 case BFD_RELOC_SIZE64
:
9255 if (S_IS_DEFINED (fixp
->fx_addsy
)
9256 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
9258 /* Resolve size relocation against local symbol to size of
9259 the symbol plus addend. */
9260 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
9261 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
9262 && !fits_in_unsigned_long (value
))
9263 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9264 _("symbol size computation overflow"));
9265 fixp
->fx_addsy
= NULL
;
9266 fixp
->fx_subsy
= NULL
;
9267 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
9272 case BFD_RELOC_X86_64_PLT32
:
9273 case BFD_RELOC_X86_64_GOT32
:
9274 case BFD_RELOC_X86_64_GOTPCREL
:
9275 case BFD_RELOC_386_PLT32
:
9276 case BFD_RELOC_386_GOT32
:
9277 case BFD_RELOC_386_GOTOFF
:
9278 case BFD_RELOC_386_GOTPC
:
9279 case BFD_RELOC_386_TLS_GD
:
9280 case BFD_RELOC_386_TLS_LDM
:
9281 case BFD_RELOC_386_TLS_LDO_32
:
9282 case BFD_RELOC_386_TLS_IE_32
:
9283 case BFD_RELOC_386_TLS_IE
:
9284 case BFD_RELOC_386_TLS_GOTIE
:
9285 case BFD_RELOC_386_TLS_LE_32
:
9286 case BFD_RELOC_386_TLS_LE
:
9287 case BFD_RELOC_386_TLS_GOTDESC
:
9288 case BFD_RELOC_386_TLS_DESC_CALL
:
9289 case BFD_RELOC_X86_64_TLSGD
:
9290 case BFD_RELOC_X86_64_TLSLD
:
9291 case BFD_RELOC_X86_64_DTPOFF32
:
9292 case BFD_RELOC_X86_64_DTPOFF64
:
9293 case BFD_RELOC_X86_64_GOTTPOFF
:
9294 case BFD_RELOC_X86_64_TPOFF32
:
9295 case BFD_RELOC_X86_64_TPOFF64
:
9296 case BFD_RELOC_X86_64_GOTOFF64
:
9297 case BFD_RELOC_X86_64_GOTPC32
:
9298 case BFD_RELOC_X86_64_GOT64
:
9299 case BFD_RELOC_X86_64_GOTPCREL64
:
9300 case BFD_RELOC_X86_64_GOTPC64
:
9301 case BFD_RELOC_X86_64_GOTPLT64
:
9302 case BFD_RELOC_X86_64_PLTOFF64
:
9303 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9304 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9306 case BFD_RELOC_VTABLE_ENTRY
:
9307 case BFD_RELOC_VTABLE_INHERIT
:
9309 case BFD_RELOC_32_SECREL
:
9311 code
= fixp
->fx_r_type
;
9313 case BFD_RELOC_X86_64_32S
:
9314 if (!fixp
->fx_pcrel
)
9316 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9317 code
= fixp
->fx_r_type
;
9323 switch (fixp
->fx_size
)
9326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9327 _("can not do %d byte pc-relative relocation"),
9329 code
= BFD_RELOC_32_PCREL
;
9331 case 1: code
= BFD_RELOC_8_PCREL
; break;
9332 case 2: code
= BFD_RELOC_16_PCREL
; break;
9333 case 4: code
= BFD_RELOC_32_PCREL
; break;
9335 case 8: code
= BFD_RELOC_64_PCREL
; break;
9341 switch (fixp
->fx_size
)
9344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9345 _("can not do %d byte relocation"),
9347 code
= BFD_RELOC_32
;
9349 case 1: code
= BFD_RELOC_8
; break;
9350 case 2: code
= BFD_RELOC_16
; break;
9351 case 4: code
= BFD_RELOC_32
; break;
9353 case 8: code
= BFD_RELOC_64
; break;
9360 if ((code
== BFD_RELOC_32
9361 || code
== BFD_RELOC_32_PCREL
9362 || code
== BFD_RELOC_X86_64_32S
)
9364 && fixp
->fx_addsy
== GOT_symbol
)
9367 code
= BFD_RELOC_386_GOTPC
;
9369 code
= BFD_RELOC_X86_64_GOTPC32
;
9371 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9373 && fixp
->fx_addsy
== GOT_symbol
)
9375 code
= BFD_RELOC_X86_64_GOTPC64
;
9378 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9379 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9380 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9382 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9384 if (!use_rela_relocations
)
9386 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9387 vtable entry to be used in the relocation's section offset. */
9388 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9389 rel
->address
= fixp
->fx_offset
;
9390 #if defined (OBJ_COFF) && defined (TE_PE)
9391 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9392 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9397 /* Use the rela in 64bit mode. */
9400 if (disallow_64bit_reloc
)
9403 case BFD_RELOC_X86_64_DTPOFF64
:
9404 case BFD_RELOC_X86_64_TPOFF64
:
9405 case BFD_RELOC_64_PCREL
:
9406 case BFD_RELOC_X86_64_GOTOFF64
:
9407 case BFD_RELOC_X86_64_GOT64
:
9408 case BFD_RELOC_X86_64_GOTPCREL64
:
9409 case BFD_RELOC_X86_64_GOTPC64
:
9410 case BFD_RELOC_X86_64_GOTPLT64
:
9411 case BFD_RELOC_X86_64_PLTOFF64
:
9412 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9413 _("cannot represent relocation type %s in x32 mode"),
9414 bfd_get_reloc_code_name (code
));
9420 if (!fixp
->fx_pcrel
)
9421 rel
->addend
= fixp
->fx_offset
;
9425 case BFD_RELOC_X86_64_PLT32
:
9426 case BFD_RELOC_X86_64_GOT32
:
9427 case BFD_RELOC_X86_64_GOTPCREL
:
9428 case BFD_RELOC_X86_64_TLSGD
:
9429 case BFD_RELOC_X86_64_TLSLD
:
9430 case BFD_RELOC_X86_64_GOTTPOFF
:
9431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9432 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9433 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9436 rel
->addend
= (section
->vma
9438 + fixp
->fx_addnumber
9439 + md_pcrel_from (fixp
));
9444 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9445 if (rel
->howto
== NULL
)
9447 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9448 _("cannot represent relocation type %s"),
9449 bfd_get_reloc_code_name (code
));
9450 /* Set howto to a garbage value so that we can keep going. */
9451 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9452 gas_assert (rel
->howto
!= NULL
);
9458 #include "tc-i386-intel.c"
9461 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9463 int saved_naked_reg
;
9464 char saved_register_dot
;
9466 saved_naked_reg
= allow_naked_reg
;
9467 allow_naked_reg
= 1;
9468 saved_register_dot
= register_chars
['.'];
9469 register_chars
['.'] = '.';
9470 allow_pseudo_reg
= 1;
9471 expression_and_evaluate (exp
);
9472 allow_pseudo_reg
= 0;
9473 register_chars
['.'] = saved_register_dot
;
9474 allow_naked_reg
= saved_naked_reg
;
9476 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9478 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9480 exp
->X_op
= O_constant
;
9481 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9482 .dw2_regnum
[flag_code
>> 1];
9485 exp
->X_op
= O_illegal
;
9490 tc_x86_frame_initial_instructions (void)
9492 static unsigned int sp_regno
[2];
9494 if (!sp_regno
[flag_code
>> 1])
9496 char *saved_input
= input_line_pointer
;
9497 char sp
[][4] = {"esp", "rsp"};
9500 input_line_pointer
= sp
[flag_code
>> 1];
9501 tc_x86_parse_to_dw2regnum (&exp
);
9502 gas_assert (exp
.X_op
== O_constant
);
9503 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9504 input_line_pointer
= saved_input
;
9507 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9508 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9512 x86_dwarf2_addr_size (void)
9514 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9515 if (x86_elf_abi
== X86_64_X32_ABI
)
9518 return bfd_arch_bits_per_address (stdoutput
) / 8;
9522 i386_elf_section_type (const char *str
, size_t len
)
9524 if (flag_code
== CODE_64BIT
9525 && len
== sizeof ("unwind") - 1
9526 && strncmp (str
, "unwind", 6) == 0)
9527 return SHT_X86_64_UNWIND
;
9534 i386_solaris_fix_up_eh_frame (segT sec
)
9536 if (flag_code
== CODE_64BIT
)
9537 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9543 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9547 exp
.X_op
= O_secrel
;
9548 exp
.X_add_symbol
= symbol
;
9549 exp
.X_add_number
= 0;
9550 emit_expr (&exp
, size
);
9554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9555 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9558 x86_64_section_letter (int letter
, char **ptr_msg
)
9560 if (flag_code
== CODE_64BIT
)
9563 return SHF_X86_64_LARGE
;
9565 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9568 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9573 x86_64_section_word (char *str
, size_t len
)
9575 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9576 return SHF_X86_64_LARGE
;
9582 handle_large_common (int small ATTRIBUTE_UNUSED
)
9584 if (flag_code
!= CODE_64BIT
)
9586 s_comm_internal (0, elf_common_parse
);
9587 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9591 static segT lbss_section
;
9592 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9593 asection
*saved_bss_section
= bss_section
;
9595 if (lbss_section
== NULL
)
9597 flagword applicable
;
9599 subsegT subseg
= now_subseg
;
9601 /* The .lbss section is for local .largecomm symbols. */
9602 lbss_section
= subseg_new (".lbss", 0);
9603 applicable
= bfd_applicable_section_flags (stdoutput
);
9604 bfd_set_section_flags (stdoutput
, lbss_section
,
9605 applicable
& SEC_ALLOC
);
9606 seg_info (lbss_section
)->bss
= 1;
9608 subseg_set (seg
, subseg
);
9611 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9612 bss_section
= lbss_section
;
9614 s_comm_internal (0, elf_common_parse
);
9616 elf_com_section_ptr
= saved_com_section_ptr
;
9617 bss_section
= saved_bss_section
;
9620 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */