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x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 };
285
286 struct _i386_insn
287 {
288 /* TM holds the template for the insn were currently assembling. */
289 insn_template tm;
290
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
293 char suffix;
294
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
300 operands. */
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
306
307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
310
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
314
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
317
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
327
328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
338 modrm_byte rm;
339 rex_byte rex;
340 rex_byte vrex;
341 sib_byte sib;
342 vex_prefix vex;
343
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
363
364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
371
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
374
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
377
378 /* How to encode vector instructions. */
379 enum
380 {
381 vex_encoding_default = 0,
382 vex_encoding_vex2,
383 vex_encoding_vex3,
384 vex_encoding_evex
385 } vec_encoding;
386
387 /* REP prefix. */
388 const char *rep_prefix;
389
390 /* HLE prefix. */
391 const char *hle_prefix;
392
393 /* Have BND prefix. */
394 const char *bnd_prefix;
395
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
398
399 /* Error message. */
400 enum i386_error error;
401 };
402
403 typedef struct _i386_insn i386_insn;
404
405 /* Link RC type with corresponding string, that'll be looked for in
406 asm. */
407 struct RC_name
408 {
409 enum rc_type type;
410 const char *name;
411 unsigned int len;
412 };
413
414 static const struct RC_name RC_NamesTable[] =
415 {
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
421 };
422
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars[] = "*%-([{}"
426 #ifdef LEX_AT
427 "@"
428 #endif
429 #ifdef LEX_QM
430 "?"
431 #endif
432 ;
433
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars = "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
449
450 #else
451 const char *i386_comment_chars = "#";
452 #define PREFIX_SEPARATOR '/'
453 #endif
454
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars[] = "#/";
464
465 const char line_separator_chars[] = ";";
466
467 /* Chars that can be used to separate mant from exp in floating point
468 nums. */
469 const char EXP_CHARS[] = "eE";
470
471 /* Chars that mean this number is a floating point constant
472 As in 0f12.456
473 or 0d1.2345e12. */
474 const char FLT_CHARS[] = "fFdDxX";
475
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars[256];
478 static char register_chars[256];
479 static char operand_chars[256];
480 static char identifier_chars[256];
481 static char digit_chars[256];
482
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
490
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
493
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack[32];
499 static char *save_stack_p;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
504
505 /* The instruction we're assembling. */
506 static i386_insn i;
507
508 /* Possible templates for current insn. */
509 static const templates *current_templates;
510
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
514
515 /* Current operand we are working on. */
516 static int this_operand = -1;
517
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
519 these. */
520
521 enum flag_code {
522 CODE_32BIT,
523 CODE_16BIT,
524 CODE_64BIT };
525
526 static enum flag_code flag_code;
527 static unsigned int object_64bit;
528 static unsigned int disallow_64bit_reloc;
529 static int use_rela_relocations = 0;
530
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
534
535 /* The ELF ABI to use. */
536 enum x86_elf_abi
537 {
538 I386_ABI,
539 X86_64_ABI,
540 X86_64_X32_ABI
541 };
542
543 static enum x86_elf_abi x86_elf_abi = I386_ABI;
544 #endif
545
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj = 0;
549 #endif
550
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared = 0;
554 #endif
555
556 /* 1 for intel syntax,
557 0 if att syntax. */
558 static int intel_syntax = 0;
559
560 /* 1 for Intel64 ISA,
561 0 if AMD64 ISA. */
562 static int intel64;
563
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic = !SYSV386_COMPAT;
567
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc = OLDGCC_COMPAT;
570
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg = 0;
573
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg = 0;
576
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
579 explicitly. */
580 static int add_bnd_prefix = 0;
581
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg = 0;
584
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix = 0;
588
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence = 0;
592
593 /* 1 if the assembler should generate relax relocations. */
594
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
597
598 static enum check_kind
599 {
600 check_none = 0,
601 check_warning,
602 check_error
603 }
604 sse_check, operand_check = check_warning;
605
606 /* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 */
611 static int optimize = 0;
612
613 /* Optimization:
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
616 register.
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
618 "testb $imm7,%r8".
619 */
620 static int optimize_for_space = 0;
621
622 /* Register prefix used for error message. */
623 static const char *register_prefix = "%";
624
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size = '\0';
629
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code = 1;
632
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings = 0;
635
636 /* CPU name. */
637 static const char *cpu_arch_name = NULL;
638 static char *cpu_sub_arch_name = NULL;
639
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
642
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set = 0;
645
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
648
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags;
651
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
654
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags;
657
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion = 0;
661
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx;
664
665 /* Encode scalar AVX instructions with specific vector length. */
666 static enum
667 {
668 vex128 = 0,
669 vex256
670 } avxscalar;
671
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 static enum
674 {
675 evexl128 = 0,
676 evexl256,
677 evexl512
678 } evexlig;
679
680 /* Encode EVEX WIG instructions with specific evex.w. */
681 static enum
682 {
683 evexw0 = 0,
684 evexw1
685 } evexwig;
686
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig = rne;
689
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS *GOT_symbol;
692
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column;
695
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment;
698
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
703
704 /* Types. */
705 #define UNCOND_JUMP 0
706 #define COND_JUMP 1
707 #define COND_JUMP86 2
708
709 /* Sizes. */
710 #define CODE16 1
711 #define SMALL 0
712 #define SMALL16 (SMALL | CODE16)
713 #define BIG 2
714 #define BIG16 (BIG | CODE16)
715
716 #ifndef INLINE
717 #ifdef __GNUC__
718 #define INLINE __inline__
719 #else
720 #define INLINE
721 #endif
722 #endif
723
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
727 ((s) >> 2)
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
730
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
738
739 const relax_typeS md_relax_table[] =
740 {
741 /* The fields are:
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
746
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
752 {0, 0, 4, 0},
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
755 {0, 0, 2, 0},
756
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
762 {0, 0, 5, 0},
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
765 {0, 0, 3, 0},
766
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
772 {0, 0, 5, 0},
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
775 {0, 0, 4, 0}
776 };
777
778 static const arch_entry cpu_arch[] =
779 {
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
783 CPU_GENERIC32_FLAGS, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
785 CPU_GENERIC64_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
787 CPU_NONE_FLAGS, 0 },
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
789 CPU_I186_FLAGS, 0 },
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
791 CPU_I286_FLAGS, 0 },
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
793 CPU_I386_FLAGS, 0 },
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
795 CPU_I486_FLAGS, 0 },
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
797 CPU_I586_FLAGS, 0 },
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
799 CPU_I686_FLAGS, 0 },
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
801 CPU_I586_FLAGS, 0 },
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
803 CPU_PENTIUMPRO_FLAGS, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
805 CPU_P2_FLAGS, 0 },
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
807 CPU_P3_FLAGS, 0 },
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
809 CPU_P4_FLAGS, 0 },
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
811 CPU_CORE_FLAGS, 0 },
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
813 CPU_NOCONA_FLAGS, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
815 CPU_CORE_FLAGS, 1 },
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
817 CPU_CORE_FLAGS, 0 },
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
819 CPU_CORE2_FLAGS, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
821 CPU_CORE2_FLAGS, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
823 CPU_COREI7_FLAGS, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
825 CPU_L1OM_FLAGS, 0 },
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
827 CPU_K1OM_FLAGS, 0 },
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
829 CPU_IAMCU_FLAGS, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
831 CPU_K6_FLAGS, 0 },
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
833 CPU_K6_2_FLAGS, 0 },
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
835 CPU_ATHLON_FLAGS, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
837 CPU_K8_FLAGS, 1 },
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
839 CPU_K8_FLAGS, 0 },
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
841 CPU_K8_FLAGS, 0 },
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
843 CPU_AMDFAM10_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
845 CPU_BDVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
847 CPU_BDVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
849 CPU_BDVER3_FLAGS, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
851 CPU_BDVER4_FLAGS, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
853 CPU_ZNVER1_FLAGS, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
855 CPU_BTVER1_FLAGS, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
857 CPU_BTVER2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
859 CPU_8087_FLAGS, 0 },
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
861 CPU_287_FLAGS, 0 },
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
863 CPU_387_FLAGS, 0 },
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
865 CPU_687_FLAGS, 0 },
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
867 CPU_MMX_FLAGS, 0 },
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
869 CPU_SSE_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
871 CPU_SSE2_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
873 CPU_SSE3_FLAGS, 0 },
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
875 CPU_SSSE3_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_1_FLAGS, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
879 CPU_SSE4_2_FLAGS, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
881 CPU_SSE4_2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
883 CPU_AVX_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
885 CPU_AVX2_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
887 CPU_AVX512F_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
889 CPU_AVX512CD_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
891 CPU_AVX512ER_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
893 CPU_AVX512PF_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
895 CPU_AVX512DQ_FLAGS, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
897 CPU_AVX512BW_FLAGS, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
899 CPU_AVX512VL_FLAGS, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
901 CPU_VMX_FLAGS, 0 },
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
903 CPU_VMFUNC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
905 CPU_SMX_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
907 CPU_XSAVE_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
909 CPU_XSAVEOPT_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
911 CPU_XSAVEC_FLAGS, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
913 CPU_XSAVES_FLAGS, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
915 CPU_AES_FLAGS, 0 },
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
917 CPU_PCLMUL_FLAGS, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
919 CPU_PCLMUL_FLAGS, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
921 CPU_FSGSBASE_FLAGS, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
923 CPU_RDRND_FLAGS, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
925 CPU_F16C_FLAGS, 0 },
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
927 CPU_BMI2_FLAGS, 0 },
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
929 CPU_FMA_FLAGS, 0 },
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
931 CPU_FMA4_FLAGS, 0 },
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
933 CPU_XOP_FLAGS, 0 },
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
935 CPU_LWP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
937 CPU_MOVBE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
939 CPU_CX16_FLAGS, 0 },
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
941 CPU_EPT_FLAGS, 0 },
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
943 CPU_LZCNT_FLAGS, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
945 CPU_HLE_FLAGS, 0 },
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
947 CPU_RTM_FLAGS, 0 },
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
949 CPU_INVPCID_FLAGS, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
951 CPU_CLFLUSH_FLAGS, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
953 CPU_NOP_FLAGS, 0 },
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
955 CPU_SYSCALL_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
957 CPU_RDTSCP_FLAGS, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
959 CPU_3DNOW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
961 CPU_3DNOWA_FLAGS, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
963 CPU_PADLOCK_FLAGS, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
965 CPU_SVME_FLAGS, 1 },
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
967 CPU_SVME_FLAGS, 0 },
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
969 CPU_SSE4A_FLAGS, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
971 CPU_ABM_FLAGS, 0 },
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
973 CPU_BMI_FLAGS, 0 },
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
975 CPU_TBM_FLAGS, 0 },
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
977 CPU_ADX_FLAGS, 0 },
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
979 CPU_RDSEED_FLAGS, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
981 CPU_PRFCHW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
983 CPU_SMAP_FLAGS, 0 },
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
985 CPU_MPX_FLAGS, 0 },
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
987 CPU_SHA_FLAGS, 0 },
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
989 CPU_CLFLUSHOPT_FLAGS, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
991 CPU_PREFETCHWT1_FLAGS, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
993 CPU_SE1_FLAGS, 0 },
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
995 CPU_CLWB_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
997 CPU_AVX512IFMA_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
999 CPU_AVX512VBMI_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1013 CPU_CLZERO_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1015 CPU_MWAITX_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1017 CPU_OSPKE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1019 CPU_RDPID_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1023 CPU_IBT_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
1036 };
1037
1038 static const noarch_entry cpu_noarch[] =
1039 {
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1071 };
1072
1073 #ifdef I386COFF
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1076
1077 static symbolS *
1078 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1079 {
1080 addressT align = 0;
1081
1082 SKIP_WHITESPACE ();
1083
1084 if (needs_align
1085 && *input_line_pointer == ',')
1086 {
1087 align = parse_align (needs_align - 1);
1088
1089 if (align == (addressT) -1)
1090 return NULL;
1091 }
1092 else
1093 {
1094 if (size >= 8)
1095 align = 3;
1096 else if (size >= 4)
1097 align = 2;
1098 else if (size >= 2)
1099 align = 1;
1100 else
1101 align = 0;
1102 }
1103
1104 bss_alloc (symbolP, size, align);
1105 return symbolP;
1106 }
1107
1108 static void
1109 pe_lcomm (int needs_align)
1110 {
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1112 }
1113 #endif
1114
1115 const pseudo_typeS md_pseudo_table[] =
1116 {
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1119 #else
1120 {"align", s_align_ptwo, 0},
1121 #endif
1122 {"arch", set_cpu_arch, 0},
1123 #ifndef I386COFF
1124 {"bss", s_bss, 0},
1125 #else
1126 {"lcomm", pe_lcomm, 1},
1127 #endif
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1131 {"value", cons, 2},
1132 {"slong", signed_cons, 4},
1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
1138 #ifdef BFD64
1139 {"code64", set_code_flag, CODE_64BIT},
1140 #endif
1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
1151 #else
1152 {"file", dwarf2_directive_file, 0},
1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1155 #endif
1156 #ifdef TE_PE
1157 {"secrel32", pe_directive_secrel, 0},
1158 #endif
1159 {0, 0, 0}
1160 };
1161
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer;
1164
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control *op_hash;
1167
1168 /* Hash table for register lookup. */
1169 static struct hash_control *reg_hash;
1170 \f
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1[] =
1175 {0x90}; /* nop */
1176 static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_6[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184 static const unsigned char f32_7[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1186 static const unsigned char f16_3[] =
1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1188 static const unsigned char f16_4[] =
1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190 static const unsigned char jump_disp8[] =
1191 {0xeb}; /* jmp disp8 */
1192 static const unsigned char jump32_disp32[] =
1193 {0xe9}; /* jmp disp32 */
1194 static const unsigned char jump16_disp32[] =
1195 {0x66,0xe9}; /* jmp disp32 */
1196 /* 32-bit NOPs patterns. */
1197 static const unsigned char *const f32_patt[] = {
1198 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1199 };
1200 /* 16-bit NOPs patterns. */
1201 static const unsigned char *const f16_patt[] = {
1202 f32_1, f32_2, f16_3, f16_4
1203 };
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3[] =
1206 {0x0f,0x1f,0x00};
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* data16 nopw %cs:0L(%eax,%eax,1) */
1229 static const unsigned char alt_11[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* 32-bit and 64-bit NOPs patterns. */
1232 static const unsigned char *const alt_patt[] = {
1233 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1234 alt_9, alt_10, alt_11
1235 };
1236
1237 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1239
1240 static void
1241 i386_output_nops (char *where, const unsigned char *const *patt,
1242 int count, int max_single_nop_size)
1243
1244 {
1245 /* Place the longer NOP first. */
1246 int last;
1247 int offset;
1248 const unsigned char *nops = patt[max_single_nop_size - 1];
1249
1250 /* Use the smaller one if the requsted one isn't available. */
1251 if (nops == NULL)
1252 {
1253 max_single_nop_size--;
1254 nops = patt[max_single_nop_size - 1];
1255 }
1256
1257 last = count % max_single_nop_size;
1258
1259 count -= last;
1260 for (offset = 0; offset < count; offset += max_single_nop_size)
1261 memcpy (where + offset, nops, max_single_nop_size);
1262
1263 if (last)
1264 {
1265 nops = patt[last - 1];
1266 if (nops == NULL)
1267 {
1268 /* Use the smaller one plus one-byte NOP if the needed one
1269 isn't available. */
1270 last--;
1271 nops = patt[last - 1];
1272 memcpy (where + offset, nops, last);
1273 where[offset + last] = *patt[0];
1274 }
1275 else
1276 memcpy (where + offset, nops, last);
1277 }
1278 }
1279
1280 static INLINE int
1281 fits_in_imm7 (offsetT num)
1282 {
1283 return (num & 0x7f) == num;
1284 }
1285
1286 static INLINE int
1287 fits_in_imm31 (offsetT num)
1288 {
1289 return (num & 0x7fffffff) == num;
1290 }
1291
1292 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1294
1295 void
1296 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1297 {
1298 const unsigned char *const *patt = NULL;
1299 int max_single_nop_size;
1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops;
1302
1303 switch (fragP->fr_type)
1304 {
1305 case rs_fill_nop:
1306 case rs_align_code:
1307 break;
1308 default:
1309 return;
1310 }
1311
1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
1314
1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
1317 2. For the rest, alt_patt will be used.
1318
1319 When -mtune= isn't used, alt_patt will be used if
1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1321 be used.
1322
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1325
1326 if (flag_code == CODE_16BIT)
1327 {
1328 patt = f16_patt;
1329 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops = 2;
1332 }
1333 else
1334 {
1335 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1336 {
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune)
1339 {
1340 case PROCESSOR_UNKNOWN:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
1342 optimize with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1344 patt = alt_patt;
1345 else
1346 patt = f32_patt;
1347 break;
1348 case PROCESSOR_PENTIUM4:
1349 case PROCESSOR_NOCONA:
1350 case PROCESSOR_CORE:
1351 case PROCESSOR_CORE2:
1352 case PROCESSOR_COREI7:
1353 case PROCESSOR_L1OM:
1354 case PROCESSOR_K1OM:
1355 case PROCESSOR_GENERIC64:
1356 case PROCESSOR_K6:
1357 case PROCESSOR_ATHLON:
1358 case PROCESSOR_K8:
1359 case PROCESSOR_AMDFAM10:
1360 case PROCESSOR_BD:
1361 case PROCESSOR_ZNVER:
1362 case PROCESSOR_BT:
1363 patt = alt_patt;
1364 break;
1365 case PROCESSOR_I386:
1366 case PROCESSOR_I486:
1367 case PROCESSOR_PENTIUM:
1368 case PROCESSOR_PENTIUMPRO:
1369 case PROCESSOR_IAMCU:
1370 case PROCESSOR_GENERIC32:
1371 patt = f32_patt;
1372 break;
1373 }
1374 }
1375 else
1376 {
1377 switch (fragP->tc_frag_data.tune)
1378 {
1379 case PROCESSOR_UNKNOWN:
1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1381 PROCESSOR_UNKNOWN. */
1382 abort ();
1383 break;
1384
1385 case PROCESSOR_I386:
1386 case PROCESSOR_I486:
1387 case PROCESSOR_PENTIUM:
1388 case PROCESSOR_IAMCU:
1389 case PROCESSOR_K6:
1390 case PROCESSOR_ATHLON:
1391 case PROCESSOR_K8:
1392 case PROCESSOR_AMDFAM10:
1393 case PROCESSOR_BD:
1394 case PROCESSOR_ZNVER:
1395 case PROCESSOR_BT:
1396 case PROCESSOR_GENERIC32:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
1398 with nops. */
1399 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1400 patt = alt_patt;
1401 else
1402 patt = f32_patt;
1403 break;
1404 case PROCESSOR_PENTIUMPRO:
1405 case PROCESSOR_PENTIUM4:
1406 case PROCESSOR_NOCONA:
1407 case PROCESSOR_CORE:
1408 case PROCESSOR_CORE2:
1409 case PROCESSOR_COREI7:
1410 case PROCESSOR_L1OM:
1411 case PROCESSOR_K1OM:
1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1413 patt = alt_patt;
1414 else
1415 patt = f32_patt;
1416 break;
1417 case PROCESSOR_GENERIC64:
1418 patt = alt_patt;
1419 break;
1420 }
1421 }
1422
1423 if (patt == f32_patt)
1424 {
1425 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops = 2;
1428 }
1429 else
1430 {
1431 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops = 7;
1434 }
1435 }
1436
1437 if (limit == 0)
1438 limit = max_single_nop_size;
1439
1440 if (fragP->fr_type == rs_fill_nop)
1441 {
1442 /* Output NOPs for .nop directive. */
1443 if (limit > max_single_nop_size)
1444 {
1445 as_bad_where (fragP->fr_file, fragP->fr_line,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit, max_single_nop_size);
1449 return;
1450 }
1451 }
1452 else
1453 fragP->fr_var = count;
1454
1455 if ((count / max_single_nop_size) > max_number_of_nops)
1456 {
1457 /* Generate jump over NOPs. */
1458 offsetT disp = count - 2;
1459 if (fits_in_imm7 (disp))
1460 {
1461 /* Use "jmp disp8" if possible. */
1462 count = disp;
1463 where[0] = jump_disp8[0];
1464 where[1] = count;
1465 where += 2;
1466 }
1467 else
1468 {
1469 unsigned int size_of_jump;
1470
1471 if (flag_code == CODE_16BIT)
1472 {
1473 where[0] = jump16_disp32[0];
1474 where[1] = jump16_disp32[1];
1475 size_of_jump = 2;
1476 }
1477 else
1478 {
1479 where[0] = jump32_disp32[0];
1480 size_of_jump = 1;
1481 }
1482
1483 count -= size_of_jump + 4;
1484 if (!fits_in_imm31 (count))
1485 {
1486 as_bad_where (fragP->fr_file, fragP->fr_line,
1487 _("jump over nop padding out of range"));
1488 return;
1489 }
1490
1491 md_number_to_chars (where + size_of_jump, count, 4);
1492 where += size_of_jump + 4;
1493 }
1494 }
1495
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where, patt, count, limit);
1498 }
1499
1500 static INLINE int
1501 operand_type_all_zero (const union i386_operand_type *x)
1502 {
1503 switch (ARRAY_SIZE(x->array))
1504 {
1505 case 3:
1506 if (x->array[2])
1507 return 0;
1508 /* Fall through. */
1509 case 2:
1510 if (x->array[1])
1511 return 0;
1512 /* Fall through. */
1513 case 1:
1514 return !x->array[0];
1515 default:
1516 abort ();
1517 }
1518 }
1519
1520 static INLINE void
1521 operand_type_set (union i386_operand_type *x, unsigned int v)
1522 {
1523 switch (ARRAY_SIZE(x->array))
1524 {
1525 case 3:
1526 x->array[2] = v;
1527 /* Fall through. */
1528 case 2:
1529 x->array[1] = v;
1530 /* Fall through. */
1531 case 1:
1532 x->array[0] = v;
1533 /* Fall through. */
1534 break;
1535 default:
1536 abort ();
1537 }
1538 }
1539
1540 static INLINE int
1541 operand_type_equal (const union i386_operand_type *x,
1542 const union i386_operand_type *y)
1543 {
1544 switch (ARRAY_SIZE(x->array))
1545 {
1546 case 3:
1547 if (x->array[2] != y->array[2])
1548 return 0;
1549 /* Fall through. */
1550 case 2:
1551 if (x->array[1] != y->array[1])
1552 return 0;
1553 /* Fall through. */
1554 case 1:
1555 return x->array[0] == y->array[0];
1556 break;
1557 default:
1558 abort ();
1559 }
1560 }
1561
1562 static INLINE int
1563 cpu_flags_all_zero (const union i386_cpu_flags *x)
1564 {
1565 switch (ARRAY_SIZE(x->array))
1566 {
1567 case 4:
1568 if (x->array[3])
1569 return 0;
1570 /* Fall through. */
1571 case 3:
1572 if (x->array[2])
1573 return 0;
1574 /* Fall through. */
1575 case 2:
1576 if (x->array[1])
1577 return 0;
1578 /* Fall through. */
1579 case 1:
1580 return !x->array[0];
1581 default:
1582 abort ();
1583 }
1584 }
1585
1586 static INLINE int
1587 cpu_flags_equal (const union i386_cpu_flags *x,
1588 const union i386_cpu_flags *y)
1589 {
1590 switch (ARRAY_SIZE(x->array))
1591 {
1592 case 4:
1593 if (x->array[3] != y->array[3])
1594 return 0;
1595 /* Fall through. */
1596 case 3:
1597 if (x->array[2] != y->array[2])
1598 return 0;
1599 /* Fall through. */
1600 case 2:
1601 if (x->array[1] != y->array[1])
1602 return 0;
1603 /* Fall through. */
1604 case 1:
1605 return x->array[0] == y->array[0];
1606 break;
1607 default:
1608 abort ();
1609 }
1610 }
1611
1612 static INLINE int
1613 cpu_flags_check_cpu64 (i386_cpu_flags f)
1614 {
1615 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1616 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1617 }
1618
1619 static INLINE i386_cpu_flags
1620 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1621 {
1622 switch (ARRAY_SIZE (x.array))
1623 {
1624 case 4:
1625 x.array [3] &= y.array [3];
1626 /* Fall through. */
1627 case 3:
1628 x.array [2] &= y.array [2];
1629 /* Fall through. */
1630 case 2:
1631 x.array [1] &= y.array [1];
1632 /* Fall through. */
1633 case 1:
1634 x.array [0] &= y.array [0];
1635 break;
1636 default:
1637 abort ();
1638 }
1639 return x;
1640 }
1641
1642 static INLINE i386_cpu_flags
1643 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1644 {
1645 switch (ARRAY_SIZE (x.array))
1646 {
1647 case 4:
1648 x.array [3] |= y.array [3];
1649 /* Fall through. */
1650 case 3:
1651 x.array [2] |= y.array [2];
1652 /* Fall through. */
1653 case 2:
1654 x.array [1] |= y.array [1];
1655 /* Fall through. */
1656 case 1:
1657 x.array [0] |= y.array [0];
1658 break;
1659 default:
1660 abort ();
1661 }
1662 return x;
1663 }
1664
1665 static INLINE i386_cpu_flags
1666 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1667 {
1668 switch (ARRAY_SIZE (x.array))
1669 {
1670 case 4:
1671 x.array [3] &= ~y.array [3];
1672 /* Fall through. */
1673 case 3:
1674 x.array [2] &= ~y.array [2];
1675 /* Fall through. */
1676 case 2:
1677 x.array [1] &= ~y.array [1];
1678 /* Fall through. */
1679 case 1:
1680 x.array [0] &= ~y.array [0];
1681 break;
1682 default:
1683 abort ();
1684 }
1685 return x;
1686 }
1687
1688 #define CPU_FLAGS_ARCH_MATCH 0x1
1689 #define CPU_FLAGS_64BIT_MATCH 0x2
1690
1691 #define CPU_FLAGS_PERFECT_MATCH \
1692 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1693
1694 /* Return CPU flags match bits. */
1695
1696 static int
1697 cpu_flags_match (const insn_template *t)
1698 {
1699 i386_cpu_flags x = t->cpu_flags;
1700 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1701
1702 x.bitfield.cpu64 = 0;
1703 x.bitfield.cpuno64 = 0;
1704
1705 if (cpu_flags_all_zero (&x))
1706 {
1707 /* This instruction is available on all archs. */
1708 match |= CPU_FLAGS_ARCH_MATCH;
1709 }
1710 else
1711 {
1712 /* This instruction is available only on some archs. */
1713 i386_cpu_flags cpu = cpu_arch_flags;
1714
1715 /* AVX512VL is no standalone feature - match it and then strip it. */
1716 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1717 return match;
1718 x.bitfield.cpuavx512vl = 0;
1719
1720 cpu = cpu_flags_and (x, cpu);
1721 if (!cpu_flags_all_zero (&cpu))
1722 {
1723 if (x.bitfield.cpuavx)
1724 {
1725 /* We need to check a few extra flags with AVX. */
1726 if (cpu.bitfield.cpuavx
1727 && (!t->opcode_modifier.sse2avx || sse2avx)
1728 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1729 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1730 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1731 match |= CPU_FLAGS_ARCH_MATCH;
1732 }
1733 else if (x.bitfield.cpuavx512f)
1734 {
1735 /* We need to check a few extra flags with AVX512F. */
1736 if (cpu.bitfield.cpuavx512f
1737 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1738 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1739 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1740 match |= CPU_FLAGS_ARCH_MATCH;
1741 }
1742 else
1743 match |= CPU_FLAGS_ARCH_MATCH;
1744 }
1745 }
1746 return match;
1747 }
1748
1749 static INLINE i386_operand_type
1750 operand_type_and (i386_operand_type x, i386_operand_type y)
1751 {
1752 switch (ARRAY_SIZE (x.array))
1753 {
1754 case 3:
1755 x.array [2] &= y.array [2];
1756 /* Fall through. */
1757 case 2:
1758 x.array [1] &= y.array [1];
1759 /* Fall through. */
1760 case 1:
1761 x.array [0] &= y.array [0];
1762 break;
1763 default:
1764 abort ();
1765 }
1766 return x;
1767 }
1768
1769 static INLINE i386_operand_type
1770 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1771 {
1772 switch (ARRAY_SIZE (x.array))
1773 {
1774 case 3:
1775 x.array [2] &= ~y.array [2];
1776 /* Fall through. */
1777 case 2:
1778 x.array [1] &= ~y.array [1];
1779 /* Fall through. */
1780 case 1:
1781 x.array [0] &= ~y.array [0];
1782 break;
1783 default:
1784 abort ();
1785 }
1786 return x;
1787 }
1788
1789 static INLINE i386_operand_type
1790 operand_type_or (i386_operand_type x, i386_operand_type y)
1791 {
1792 switch (ARRAY_SIZE (x.array))
1793 {
1794 case 3:
1795 x.array [2] |= y.array [2];
1796 /* Fall through. */
1797 case 2:
1798 x.array [1] |= y.array [1];
1799 /* Fall through. */
1800 case 1:
1801 x.array [0] |= y.array [0];
1802 break;
1803 default:
1804 abort ();
1805 }
1806 return x;
1807 }
1808
1809 static INLINE i386_operand_type
1810 operand_type_xor (i386_operand_type x, i386_operand_type y)
1811 {
1812 switch (ARRAY_SIZE (x.array))
1813 {
1814 case 3:
1815 x.array [2] ^= y.array [2];
1816 /* Fall through. */
1817 case 2:
1818 x.array [1] ^= y.array [1];
1819 /* Fall through. */
1820 case 1:
1821 x.array [0] ^= y.array [0];
1822 break;
1823 default:
1824 abort ();
1825 }
1826 return x;
1827 }
1828
1829 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1830 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1831 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1832 static const i386_operand_type inoutportreg
1833 = OPERAND_TYPE_INOUTPORTREG;
1834 static const i386_operand_type reg16_inoutportreg
1835 = OPERAND_TYPE_REG16_INOUTPORTREG;
1836 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1837 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1838 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1839 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1840 static const i386_operand_type anydisp
1841 = OPERAND_TYPE_ANYDISP;
1842 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1843 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1844 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1845 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1846 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1847 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1848 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1849 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1850 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1851 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1852 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1853 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1854
1855 enum operand_type
1856 {
1857 reg,
1858 imm,
1859 disp,
1860 anymem
1861 };
1862
1863 static INLINE int
1864 operand_type_check (i386_operand_type t, enum operand_type c)
1865 {
1866 switch (c)
1867 {
1868 case reg:
1869 return t.bitfield.reg;
1870
1871 case imm:
1872 return (t.bitfield.imm8
1873 || t.bitfield.imm8s
1874 || t.bitfield.imm16
1875 || t.bitfield.imm32
1876 || t.bitfield.imm32s
1877 || t.bitfield.imm64);
1878
1879 case disp:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64);
1885
1886 case anymem:
1887 return (t.bitfield.disp8
1888 || t.bitfield.disp16
1889 || t.bitfield.disp32
1890 || t.bitfield.disp32s
1891 || t.bitfield.disp64
1892 || t.bitfield.baseindex);
1893
1894 default:
1895 abort ();
1896 }
1897
1898 return 0;
1899 }
1900
1901 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1902 operand J for instruction template T. */
1903
1904 static INLINE int
1905 match_reg_size (const insn_template *t, unsigned int j)
1906 {
1907 return !((i.types[j].bitfield.byte
1908 && !t->operand_types[j].bitfield.byte)
1909 || (i.types[j].bitfield.word
1910 && !t->operand_types[j].bitfield.word)
1911 || (i.types[j].bitfield.dword
1912 && !t->operand_types[j].bitfield.dword)
1913 || (i.types[j].bitfield.qword
1914 && !t->operand_types[j].bitfield.qword)
1915 || (i.types[j].bitfield.tbyte
1916 && !t->operand_types[j].bitfield.tbyte));
1917 }
1918
1919 /* Return 1 if there is no conflict in SIMD register on
1920 operand J for instruction template T. */
1921
1922 static INLINE int
1923 match_simd_size (const insn_template *t, unsigned int j)
1924 {
1925 return !((i.types[j].bitfield.xmmword
1926 && !t->operand_types[j].bitfield.xmmword)
1927 || (i.types[j].bitfield.ymmword
1928 && !t->operand_types[j].bitfield.ymmword)
1929 || (i.types[j].bitfield.zmmword
1930 && !t->operand_types[j].bitfield.zmmword));
1931 }
1932
1933 /* Return 1 if there is no conflict in any size on operand J for
1934 instruction template T. */
1935
1936 static INLINE int
1937 match_mem_size (const insn_template *t, unsigned int j)
1938 {
1939 return (match_reg_size (t, j)
1940 && !((i.types[j].bitfield.unspecified
1941 && !i.broadcast
1942 && !t->operand_types[j].bitfield.unspecified)
1943 || (i.types[j].bitfield.fword
1944 && !t->operand_types[j].bitfield.fword)
1945 /* For scalar opcode templates to allow register and memory
1946 operands at the same time, some special casing is needed
1947 here. */
1948 || ((t->operand_types[j].bitfield.regsimd
1949 && !t->opcode_modifier.broadcast
1950 && (t->operand_types[j].bitfield.dword
1951 || t->operand_types[j].bitfield.qword))
1952 ? (i.types[j].bitfield.xmmword
1953 || i.types[j].bitfield.ymmword
1954 || i.types[j].bitfield.zmmword)
1955 : !match_simd_size(t, j))));
1956 }
1957
1958 /* Return 1 if there is no size conflict on any operands for
1959 instruction template T. */
1960
1961 static INLINE int
1962 operand_size_match (const insn_template *t)
1963 {
1964 unsigned int j;
1965 int match = 1;
1966
1967 /* Don't check jump instructions. */
1968 if (t->opcode_modifier.jump
1969 || t->opcode_modifier.jumpbyte
1970 || t->opcode_modifier.jumpdword
1971 || t->opcode_modifier.jumpintersegment)
1972 return match;
1973
1974 /* Check memory and accumulator operand size. */
1975 for (j = 0; j < i.operands; j++)
1976 {
1977 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1978 && t->operand_types[j].bitfield.anysize)
1979 continue;
1980
1981 if (t->operand_types[j].bitfield.reg
1982 && !match_reg_size (t, j))
1983 {
1984 match = 0;
1985 break;
1986 }
1987
1988 if (t->operand_types[j].bitfield.regsimd
1989 && !match_simd_size (t, j))
1990 {
1991 match = 0;
1992 break;
1993 }
1994
1995 if (t->operand_types[j].bitfield.acc
1996 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1997 {
1998 match = 0;
1999 break;
2000 }
2001
2002 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2003 {
2004 match = 0;
2005 break;
2006 }
2007 }
2008
2009 if (match)
2010 return match;
2011 else if (!t->opcode_modifier.d)
2012 {
2013 mismatch:
2014 i.error = operand_size_mismatch;
2015 return 0;
2016 }
2017
2018 /* Check reverse. */
2019 gas_assert (i.operands == 2);
2020
2021 match = 1;
2022 for (j = 0; j < 2; j++)
2023 {
2024 if ((t->operand_types[j].bitfield.reg
2025 || t->operand_types[j].bitfield.acc)
2026 && !match_reg_size (t, j ? 0 : 1))
2027 goto mismatch;
2028
2029 if (i.types[j].bitfield.mem
2030 && !match_mem_size (t, j ? 0 : 1))
2031 goto mismatch;
2032 }
2033
2034 return match;
2035 }
2036
2037 static INLINE int
2038 operand_type_match (i386_operand_type overlap,
2039 i386_operand_type given)
2040 {
2041 i386_operand_type temp = overlap;
2042
2043 temp.bitfield.jumpabsolute = 0;
2044 temp.bitfield.unspecified = 0;
2045 temp.bitfield.byte = 0;
2046 temp.bitfield.word = 0;
2047 temp.bitfield.dword = 0;
2048 temp.bitfield.fword = 0;
2049 temp.bitfield.qword = 0;
2050 temp.bitfield.tbyte = 0;
2051 temp.bitfield.xmmword = 0;
2052 temp.bitfield.ymmword = 0;
2053 temp.bitfield.zmmword = 0;
2054 if (operand_type_all_zero (&temp))
2055 goto mismatch;
2056
2057 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2058 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2059 return 1;
2060
2061 mismatch:
2062 i.error = operand_type_mismatch;
2063 return 0;
2064 }
2065
2066 /* If given types g0 and g1 are registers they must be of the same type
2067 unless the expected operand type register overlap is null.
2068 Memory operand size of certain SIMD instructions is also being checked
2069 here. */
2070
2071 static INLINE int
2072 operand_type_register_match (i386_operand_type g0,
2073 i386_operand_type t0,
2074 i386_operand_type g1,
2075 i386_operand_type t1)
2076 {
2077 if (!g0.bitfield.reg
2078 && !g0.bitfield.regsimd
2079 && (!operand_type_check (g0, anymem)
2080 || g0.bitfield.unspecified
2081 || !t0.bitfield.regsimd))
2082 return 1;
2083
2084 if (!g1.bitfield.reg
2085 && !g1.bitfield.regsimd
2086 && (!operand_type_check (g1, anymem)
2087 || g1.bitfield.unspecified
2088 || !t1.bitfield.regsimd))
2089 return 1;
2090
2091 if (g0.bitfield.byte == g1.bitfield.byte
2092 && g0.bitfield.word == g1.bitfield.word
2093 && g0.bitfield.dword == g1.bitfield.dword
2094 && g0.bitfield.qword == g1.bitfield.qword
2095 && g0.bitfield.xmmword == g1.bitfield.xmmword
2096 && g0.bitfield.ymmword == g1.bitfield.ymmword
2097 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2098 return 1;
2099
2100 if (!(t0.bitfield.byte & t1.bitfield.byte)
2101 && !(t0.bitfield.word & t1.bitfield.word)
2102 && !(t0.bitfield.dword & t1.bitfield.dword)
2103 && !(t0.bitfield.qword & t1.bitfield.qword)
2104 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2105 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2106 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2107 return 1;
2108
2109 i.error = register_type_mismatch;
2110
2111 return 0;
2112 }
2113
2114 static INLINE unsigned int
2115 register_number (const reg_entry *r)
2116 {
2117 unsigned int nr = r->reg_num;
2118
2119 if (r->reg_flags & RegRex)
2120 nr += 8;
2121
2122 if (r->reg_flags & RegVRex)
2123 nr += 16;
2124
2125 return nr;
2126 }
2127
2128 static INLINE unsigned int
2129 mode_from_disp_size (i386_operand_type t)
2130 {
2131 if (t.bitfield.disp8)
2132 return 1;
2133 else if (t.bitfield.disp16
2134 || t.bitfield.disp32
2135 || t.bitfield.disp32s)
2136 return 2;
2137 else
2138 return 0;
2139 }
2140
2141 static INLINE int
2142 fits_in_signed_byte (addressT num)
2143 {
2144 return num + 0x80 <= 0xff;
2145 }
2146
2147 static INLINE int
2148 fits_in_unsigned_byte (addressT num)
2149 {
2150 return num <= 0xff;
2151 }
2152
2153 static INLINE int
2154 fits_in_unsigned_word (addressT num)
2155 {
2156 return num <= 0xffff;
2157 }
2158
2159 static INLINE int
2160 fits_in_signed_word (addressT num)
2161 {
2162 return num + 0x8000 <= 0xffff;
2163 }
2164
2165 static INLINE int
2166 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2167 {
2168 #ifndef BFD64
2169 return 1;
2170 #else
2171 return num + 0x80000000 <= 0xffffffff;
2172 #endif
2173 } /* fits_in_signed_long() */
2174
2175 static INLINE int
2176 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2177 {
2178 #ifndef BFD64
2179 return 1;
2180 #else
2181 return num <= 0xffffffff;
2182 #endif
2183 } /* fits_in_unsigned_long() */
2184
2185 static INLINE int
2186 fits_in_disp8 (offsetT num)
2187 {
2188 int shift = i.memshift;
2189 unsigned int mask;
2190
2191 if (shift == -1)
2192 abort ();
2193
2194 mask = (1 << shift) - 1;
2195
2196 /* Return 0 if NUM isn't properly aligned. */
2197 if ((num & mask))
2198 return 0;
2199
2200 /* Check if NUM will fit in 8bit after shift. */
2201 return fits_in_signed_byte (num >> shift);
2202 }
2203
2204 static INLINE int
2205 fits_in_imm4 (offsetT num)
2206 {
2207 return (num & 0xf) == num;
2208 }
2209
2210 static i386_operand_type
2211 smallest_imm_type (offsetT num)
2212 {
2213 i386_operand_type t;
2214
2215 operand_type_set (&t, 0);
2216 t.bitfield.imm64 = 1;
2217
2218 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2219 {
2220 /* This code is disabled on the 486 because all the Imm1 forms
2221 in the opcode table are slower on the i486. They're the
2222 versions with the implicitly specified single-position
2223 displacement, which has another syntax if you really want to
2224 use that form. */
2225 t.bitfield.imm1 = 1;
2226 t.bitfield.imm8 = 1;
2227 t.bitfield.imm8s = 1;
2228 t.bitfield.imm16 = 1;
2229 t.bitfield.imm32 = 1;
2230 t.bitfield.imm32s = 1;
2231 }
2232 else if (fits_in_signed_byte (num))
2233 {
2234 t.bitfield.imm8 = 1;
2235 t.bitfield.imm8s = 1;
2236 t.bitfield.imm16 = 1;
2237 t.bitfield.imm32 = 1;
2238 t.bitfield.imm32s = 1;
2239 }
2240 else if (fits_in_unsigned_byte (num))
2241 {
2242 t.bitfield.imm8 = 1;
2243 t.bitfield.imm16 = 1;
2244 t.bitfield.imm32 = 1;
2245 t.bitfield.imm32s = 1;
2246 }
2247 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2248 {
2249 t.bitfield.imm16 = 1;
2250 t.bitfield.imm32 = 1;
2251 t.bitfield.imm32s = 1;
2252 }
2253 else if (fits_in_signed_long (num))
2254 {
2255 t.bitfield.imm32 = 1;
2256 t.bitfield.imm32s = 1;
2257 }
2258 else if (fits_in_unsigned_long (num))
2259 t.bitfield.imm32 = 1;
2260
2261 return t;
2262 }
2263
2264 static offsetT
2265 offset_in_range (offsetT val, int size)
2266 {
2267 addressT mask;
2268
2269 switch (size)
2270 {
2271 case 1: mask = ((addressT) 1 << 8) - 1; break;
2272 case 2: mask = ((addressT) 1 << 16) - 1; break;
2273 case 4: mask = ((addressT) 2 << 31) - 1; break;
2274 #ifdef BFD64
2275 case 8: mask = ((addressT) 2 << 63) - 1; break;
2276 #endif
2277 default: abort ();
2278 }
2279
2280 #ifdef BFD64
2281 /* If BFD64, sign extend val for 32bit address mode. */
2282 if (flag_code != CODE_64BIT
2283 || i.prefix[ADDR_PREFIX])
2284 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2285 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2286 #endif
2287
2288 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2289 {
2290 char buf1[40], buf2[40];
2291
2292 sprint_value (buf1, val);
2293 sprint_value (buf2, val & mask);
2294 as_warn (_("%s shortened to %s"), buf1, buf2);
2295 }
2296 return val & mask;
2297 }
2298
2299 enum PREFIX_GROUP
2300 {
2301 PREFIX_EXIST = 0,
2302 PREFIX_LOCK,
2303 PREFIX_REP,
2304 PREFIX_DS,
2305 PREFIX_OTHER
2306 };
2307
2308 /* Returns
2309 a. PREFIX_EXIST if attempting to add a prefix where one from the
2310 same class already exists.
2311 b. PREFIX_LOCK if lock prefix is added.
2312 c. PREFIX_REP if rep/repne prefix is added.
2313 d. PREFIX_DS if ds prefix is added.
2314 e. PREFIX_OTHER if other prefix is added.
2315 */
2316
2317 static enum PREFIX_GROUP
2318 add_prefix (unsigned int prefix)
2319 {
2320 enum PREFIX_GROUP ret = PREFIX_OTHER;
2321 unsigned int q;
2322
2323 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2324 && flag_code == CODE_64BIT)
2325 {
2326 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2327 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2328 && (prefix & (REX_R | REX_X | REX_B))))
2329 ret = PREFIX_EXIST;
2330 q = REX_PREFIX;
2331 }
2332 else
2333 {
2334 switch (prefix)
2335 {
2336 default:
2337 abort ();
2338
2339 case DS_PREFIX_OPCODE:
2340 ret = PREFIX_DS;
2341 /* Fall through. */
2342 case CS_PREFIX_OPCODE:
2343 case ES_PREFIX_OPCODE:
2344 case FS_PREFIX_OPCODE:
2345 case GS_PREFIX_OPCODE:
2346 case SS_PREFIX_OPCODE:
2347 q = SEG_PREFIX;
2348 break;
2349
2350 case REPNE_PREFIX_OPCODE:
2351 case REPE_PREFIX_OPCODE:
2352 q = REP_PREFIX;
2353 ret = PREFIX_REP;
2354 break;
2355
2356 case LOCK_PREFIX_OPCODE:
2357 q = LOCK_PREFIX;
2358 ret = PREFIX_LOCK;
2359 break;
2360
2361 case FWAIT_OPCODE:
2362 q = WAIT_PREFIX;
2363 break;
2364
2365 case ADDR_PREFIX_OPCODE:
2366 q = ADDR_PREFIX;
2367 break;
2368
2369 case DATA_PREFIX_OPCODE:
2370 q = DATA_PREFIX;
2371 break;
2372 }
2373 if (i.prefix[q] != 0)
2374 ret = PREFIX_EXIST;
2375 }
2376
2377 if (ret)
2378 {
2379 if (!i.prefix[q])
2380 ++i.prefixes;
2381 i.prefix[q] |= prefix;
2382 }
2383 else
2384 as_bad (_("same type of prefix used twice"));
2385
2386 return ret;
2387 }
2388
2389 static void
2390 update_code_flag (int value, int check)
2391 {
2392 PRINTF_LIKE ((*as_error));
2393
2394 flag_code = (enum flag_code) value;
2395 if (flag_code == CODE_64BIT)
2396 {
2397 cpu_arch_flags.bitfield.cpu64 = 1;
2398 cpu_arch_flags.bitfield.cpuno64 = 0;
2399 }
2400 else
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 0;
2403 cpu_arch_flags.bitfield.cpuno64 = 1;
2404 }
2405 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2406 {
2407 if (check)
2408 as_error = as_fatal;
2409 else
2410 as_error = as_bad;
2411 (*as_error) (_("64bit mode not supported on `%s'."),
2412 cpu_arch_name ? cpu_arch_name : default_arch);
2413 }
2414 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2415 {
2416 if (check)
2417 as_error = as_fatal;
2418 else
2419 as_error = as_bad;
2420 (*as_error) (_("32bit mode not supported on `%s'."),
2421 cpu_arch_name ? cpu_arch_name : default_arch);
2422 }
2423 stackop_size = '\0';
2424 }
2425
2426 static void
2427 set_code_flag (int value)
2428 {
2429 update_code_flag (value, 0);
2430 }
2431
2432 static void
2433 set_16bit_gcc_code_flag (int new_code_flag)
2434 {
2435 flag_code = (enum flag_code) new_code_flag;
2436 if (flag_code != CODE_16BIT)
2437 abort ();
2438 cpu_arch_flags.bitfield.cpu64 = 0;
2439 cpu_arch_flags.bitfield.cpuno64 = 1;
2440 stackop_size = LONG_MNEM_SUFFIX;
2441 }
2442
2443 static void
2444 set_intel_syntax (int syntax_flag)
2445 {
2446 /* Find out if register prefixing is specified. */
2447 int ask_naked_reg = 0;
2448
2449 SKIP_WHITESPACE ();
2450 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2451 {
2452 char *string;
2453 int e = get_symbol_name (&string);
2454
2455 if (strcmp (string, "prefix") == 0)
2456 ask_naked_reg = 1;
2457 else if (strcmp (string, "noprefix") == 0)
2458 ask_naked_reg = -1;
2459 else
2460 as_bad (_("bad argument to syntax directive."));
2461 (void) restore_line_pointer (e);
2462 }
2463 demand_empty_rest_of_line ();
2464
2465 intel_syntax = syntax_flag;
2466
2467 if (ask_naked_reg == 0)
2468 allow_naked_reg = (intel_syntax
2469 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2470 else
2471 allow_naked_reg = (ask_naked_reg < 0);
2472
2473 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2474
2475 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2476 identifier_chars['$'] = intel_syntax ? '$' : 0;
2477 register_prefix = allow_naked_reg ? "" : "%";
2478 }
2479
2480 static void
2481 set_intel_mnemonic (int mnemonic_flag)
2482 {
2483 intel_mnemonic = mnemonic_flag;
2484 }
2485
2486 static void
2487 set_allow_index_reg (int flag)
2488 {
2489 allow_index_reg = flag;
2490 }
2491
2492 static void
2493 set_check (int what)
2494 {
2495 enum check_kind *kind;
2496 const char *str;
2497
2498 if (what)
2499 {
2500 kind = &operand_check;
2501 str = "operand";
2502 }
2503 else
2504 {
2505 kind = &sse_check;
2506 str = "sse";
2507 }
2508
2509 SKIP_WHITESPACE ();
2510
2511 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2512 {
2513 char *string;
2514 int e = get_symbol_name (&string);
2515
2516 if (strcmp (string, "none") == 0)
2517 *kind = check_none;
2518 else if (strcmp (string, "warning") == 0)
2519 *kind = check_warning;
2520 else if (strcmp (string, "error") == 0)
2521 *kind = check_error;
2522 else
2523 as_bad (_("bad argument to %s_check directive."), str);
2524 (void) restore_line_pointer (e);
2525 }
2526 else
2527 as_bad (_("missing argument for %s_check directive"), str);
2528
2529 demand_empty_rest_of_line ();
2530 }
2531
2532 static void
2533 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2534 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2535 {
2536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2537 static const char *arch;
2538
2539 /* Intel LIOM is only supported on ELF. */
2540 if (!IS_ELF)
2541 return;
2542
2543 if (!arch)
2544 {
2545 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2546 use default_arch. */
2547 arch = cpu_arch_name;
2548 if (!arch)
2549 arch = default_arch;
2550 }
2551
2552 /* If we are targeting Intel MCU, we must enable it. */
2553 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2554 || new_flag.bitfield.cpuiamcu)
2555 return;
2556
2557 /* If we are targeting Intel L1OM, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2559 || new_flag.bitfield.cpul1om)
2560 return;
2561
2562 /* If we are targeting Intel K1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2564 || new_flag.bitfield.cpuk1om)
2565 return;
2566
2567 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2568 #endif
2569 }
2570
2571 static void
2572 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2573 {
2574 SKIP_WHITESPACE ();
2575
2576 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2577 {
2578 char *string;
2579 int e = get_symbol_name (&string);
2580 unsigned int j;
2581 i386_cpu_flags flags;
2582
2583 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2584 {
2585 if (strcmp (string, cpu_arch[j].name) == 0)
2586 {
2587 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2588
2589 if (*string != '.')
2590 {
2591 cpu_arch_name = cpu_arch[j].name;
2592 cpu_sub_arch_name = NULL;
2593 cpu_arch_flags = cpu_arch[j].flags;
2594 if (flag_code == CODE_64BIT)
2595 {
2596 cpu_arch_flags.bitfield.cpu64 = 1;
2597 cpu_arch_flags.bitfield.cpuno64 = 0;
2598 }
2599 else
2600 {
2601 cpu_arch_flags.bitfield.cpu64 = 0;
2602 cpu_arch_flags.bitfield.cpuno64 = 1;
2603 }
2604 cpu_arch_isa = cpu_arch[j].type;
2605 cpu_arch_isa_flags = cpu_arch[j].flags;
2606 if (!cpu_arch_tune_set)
2607 {
2608 cpu_arch_tune = cpu_arch_isa;
2609 cpu_arch_tune_flags = cpu_arch_isa_flags;
2610 }
2611 break;
2612 }
2613
2614 flags = cpu_flags_or (cpu_arch_flags,
2615 cpu_arch[j].flags);
2616
2617 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2618 {
2619 if (cpu_sub_arch_name)
2620 {
2621 char *name = cpu_sub_arch_name;
2622 cpu_sub_arch_name = concat (name,
2623 cpu_arch[j].name,
2624 (const char *) NULL);
2625 free (name);
2626 }
2627 else
2628 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2629 cpu_arch_flags = flags;
2630 cpu_arch_isa_flags = flags;
2631 }
2632 (void) restore_line_pointer (e);
2633 demand_empty_rest_of_line ();
2634 return;
2635 }
2636 }
2637
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2639 {
2640 /* Disable an ISA extension. */
2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2643 {
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2647 {
2648 if (cpu_sub_arch_name)
2649 {
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2653 free (name);
2654 }
2655 else
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2659 }
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2662 return;
2663 }
2664
2665 j = ARRAY_SIZE (cpu_arch);
2666 }
2667
2668 if (j >= ARRAY_SIZE (cpu_arch))
2669 as_bad (_("no such architecture: `%s'"), string);
2670
2671 *input_line_pointer = e;
2672 }
2673 else
2674 as_bad (_("missing cpu architecture"));
2675
2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2679 {
2680 char *string;
2681 char e;
2682
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
2685
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2689 ;
2690 else
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2692
2693 (void) restore_line_pointer (e);
2694 }
2695
2696 demand_empty_rest_of_line ();
2697 }
2698
2699 enum bfd_architecture
2700 i386_arch (void)
2701 {
2702 if (cpu_arch_isa == PROCESSOR_L1OM)
2703 {
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2708 }
2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2710 {
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2715 }
2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2717 {
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2722 }
2723 else
2724 return bfd_arch_i386;
2725 }
2726
2727 unsigned long
2728 i386_mach (void)
2729 {
2730 if (!strncmp (default_arch, "x86_64", 6))
2731 {
2732 if (cpu_arch_isa == PROCESSOR_L1OM)
2733 {
2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2738 }
2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2740 {
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2745 }
2746 else if (default_arch[6] == '\0')
2747 return bfd_mach_x86_64;
2748 else
2749 return bfd_mach_x64_32;
2750 }
2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
2753 {
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2755 {
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2759 }
2760 else
2761 return bfd_mach_i386_i386;
2762 }
2763 else
2764 as_fatal (_("unknown architecture"));
2765 }
2766 \f
2767 void
2768 md_begin (void)
2769 {
2770 const char *hash_err;
2771
2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2774
2775 /* Initialize op_hash hash table. */
2776 op_hash = hash_new ();
2777
2778 {
2779 const insn_template *optab;
2780 templates *core_optab;
2781
2782 /* Setup for loop. */
2783 optab = i386_optab;
2784 core_optab = XNEW (templates);
2785 core_optab->start = optab;
2786
2787 while (1)
2788 {
2789 ++optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2792 {
2793 /* different name --> ship out current template list;
2794 add to hash table; & begin anew. */
2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2797 (optab - 1)->name,
2798 (void *) core_optab);
2799 if (hash_err)
2800 {
2801 as_fatal (_("can't hash %s: %s"),
2802 (optab - 1)->name,
2803 hash_err);
2804 }
2805 if (optab->name == NULL)
2806 break;
2807 core_optab = XNEW (templates);
2808 core_optab->start = optab;
2809 }
2810 }
2811 }
2812
2813 /* Initialize reg_hash hash table. */
2814 reg_hash = hash_new ();
2815 {
2816 const reg_entry *regtab;
2817 unsigned int regtab_size = i386_regtab_size;
2818
2819 for (regtab = i386_regtab; regtab_size--; regtab++)
2820 {
2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2822 if (hash_err)
2823 as_fatal (_("can't hash %s: %s"),
2824 regtab->reg_name,
2825 hash_err);
2826 }
2827 }
2828
2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2830 {
2831 int c;
2832 char *p;
2833
2834 for (c = 0; c < 256; c++)
2835 {
2836 if (ISDIGIT (c))
2837 {
2838 digit_chars[c] = c;
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2842 }
2843 else if (ISLOWER (c))
2844 {
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2848 }
2849 else if (ISUPPER (c))
2850 {
2851 mnemonic_chars[c] = TOLOWER (c);
2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2854 }
2855 else if (c == '{' || c == '}')
2856 {
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
2860
2861 if (ISALPHA (c) || ISDIGIT (c))
2862 identifier_chars[c] = c;
2863 else if (c >= 128)
2864 {
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2867 }
2868 }
2869
2870 #ifdef LEX_AT
2871 identifier_chars['@'] = '@';
2872 #endif
2873 #ifdef LEX_QM
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
2876 #endif
2877 digit_chars['-'] = '-';
2878 mnemonic_chars['_'] = '_';
2879 mnemonic_chars['-'] = '-';
2880 mnemonic_chars['.'] = '.';
2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2883
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2886 }
2887
2888 if (flag_code == CODE_64BIT)
2889 {
2890 #if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2892 ? 32 : 16);
2893 #else
2894 x86_dwarf2_return_column = 16;
2895 #endif
2896 x86_cie_data_alignment = -8;
2897 }
2898 else
2899 {
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2902 }
2903 }
2904
2905 void
2906 i386_print_statistics (FILE *file)
2907 {
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2910 }
2911 \f
2912 #ifdef DEBUG386
2913
2914 /* Debugging routines for md_assemble. */
2915 static void pte (insn_template *);
2916 static void pt (i386_operand_type);
2917 static void pe (expressionS *);
2918 static void ps (symbolS *);
2919
2920 static void
2921 pi (char *line, i386_insn *x)
2922 {
2923 unsigned int j;
2924
2925 fprintf (stdout, "%s: template ", line);
2926 pte (&x->tm);
2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2932 x->rm.mode, x->rm.reg, x->rm.regmem);
2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
2940 for (j = 0; j < x->operands; j++)
2941 {
2942 fprintf (stdout, " #%d: ", j + 1);
2943 pt (x->types[j]);
2944 fprintf (stdout, "\n");
2945 if (x->types[j].bitfield.reg
2946 || x->types[j].bitfield.regmmx
2947 || x->types[j].bitfield.regsimd
2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2955 pe (x->op[j].imms);
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
2958 }
2959 }
2960
2961 static void
2962 pte (insn_template *t)
2963 {
2964 unsigned int j;
2965 fprintf (stdout, " %d operands ", t->operands);
2966 fprintf (stdout, "opcode %x ", t->base_opcode);
2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
2969 if (t->opcode_modifier.d)
2970 fprintf (stdout, "D");
2971 if (t->opcode_modifier.w)
2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
2974 for (j = 0; j < t->operands; j++)
2975 {
2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
2978 fprintf (stdout, "\n");
2979 }
2980 }
2981
2982 static void
2983 pe (expressionS *e)
2984 {
2985 fprintf (stdout, " operation %d\n", e->X_op);
2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
2988 if (e->X_add_symbol)
2989 {
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2993 }
2994 if (e->X_op_symbol)
2995 {
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
2999 }
3000 }
3001
3002 static void
3003 ps (symbolS *s)
3004 {
3005 fprintf (stdout, "%s type %s%s",
3006 S_GET_NAME (s),
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3009 }
3010
3011 static struct type_name
3012 {
3013 i386_operand_type mask;
3014 const char *name;
3015 }
3016 const type_names[] =
3017 {
3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
3048 { OPERAND_TYPE_REGYMM, "rYMM" },
3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
3051 { OPERAND_TYPE_ESSEG, "es" },
3052 };
3053
3054 static void
3055 pt (i386_operand_type t)
3056 {
3057 unsigned int j;
3058 i386_operand_type a;
3059
3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3061 {
3062 a = operand_type_and (t, type_names[j].mask);
3063 if (!operand_type_all_zero (&a))
3064 fprintf (stdout, "%s, ", type_names[j].name);
3065 }
3066 fflush (stdout);
3067 }
3068
3069 #endif /* DEBUG386 */
3070 \f
3071 static bfd_reloc_code_real_type
3072 reloc (unsigned int size,
3073 int pcrel,
3074 int sign,
3075 bfd_reloc_code_real_type other)
3076 {
3077 if (other != NO_RELOC)
3078 {
3079 reloc_howto_type *rel;
3080
3081 if (size == 8)
3082 switch (other)
3083 {
3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3086 break;
3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3089 break;
3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3098 break;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3104 break;
3105 default:
3106 break;
3107 }
3108
3109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3110 if (other == BFD_RELOC_SIZE32)
3111 {
3112 if (size == 8)
3113 other = BFD_RELOC_SIZE64;
3114 if (pcrel)
3115 {
3116 as_bad (_("there are no pc-relative size relocations"));
3117 return NO_RELOC;
3118 }
3119 }
3120 #endif
3121
3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3124 sign = -1;
3125
3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3127 if (!rel)
3128 as_bad (_("unknown relocation (%u)"), other);
3129 else if (size != bfd_get_reloc_size (rel))
3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3131 bfd_get_reloc_size (rel),
3132 size);
3133 else if (pcrel && !rel->pc_relative)
3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3136 && !sign)
3137 || (rel->complain_on_overflow == complain_overflow_unsigned
3138 && sign > 0))
3139 as_bad (_("relocated field and relocation type differ in signedness"));
3140 else
3141 return other;
3142 return NO_RELOC;
3143 }
3144
3145 if (pcrel)
3146 {
3147 if (!sign)
3148 as_bad (_("there are no unsigned pc-relative relocations"));
3149 switch (size)
3150 {
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
3153 case 4: return BFD_RELOC_32_PCREL;
3154 case 8: return BFD_RELOC_64_PCREL;
3155 }
3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3157 }
3158 else
3159 {
3160 if (sign > 0)
3161 switch (size)
3162 {
3163 case 4: return BFD_RELOC_X86_64_32S;
3164 }
3165 else
3166 switch (size)
3167 {
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3172 }
3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
3175 }
3176
3177 return NO_RELOC;
3178 }
3179
3180 /* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3184
3185 int
3186 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3187 {
3188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3189 if (!IS_ELF)
3190 return 1;
3191
3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3193 mode. */
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3196 && fixP->fx_pcrel)
3197 return 0;
3198
3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3203 return 0;
3204
3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3240 return 0;
3241 #endif
3242 return 1;
3243 }
3244
3245 static int
3246 intel_float_operand (const char *mnemonic)
3247 {
3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3251
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3254
3255 switch (mnemonic[1])
3256 {
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3260 case 'i':
3261 return 2 /* integer op */;
3262 case 'l':
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3265 break;
3266 case 'n':
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3269 break;
3270 case 'r':
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3273 break;
3274 case 's':
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3278 {
3279 switch (mnemonic[3])
3280 {
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3285 return 3;
3286 }
3287 }
3288 break;
3289 case 'x':
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3292 break;
3293 }
3294
3295 return 1;
3296 }
3297
3298 /* Build the VEX prefix. */
3299
3300 static void
3301 build_vex_prefix (const insn_template *t)
3302 {
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3306
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
3309 {
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3313 }
3314 else
3315 register_specifier = 0xf;
3316
3317 /* Use 2-byte VEX prefix by swapping destination and source
3318 operand. */
3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
3321 && i.operands == i.reg_operands
3322 && i.tm.opcode_modifier.vexopcode == VEX0F
3323 && i.tm.opcode_modifier.load
3324 && i.rex == REX_B)
3325 {
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3329
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3335 i.op[0] = temp_op;
3336
3337 gas_assert (i.rm.mode == 3);
3338
3339 i.rex = REX_R;
3340 xchg = i.rm.regmem;
3341 i.rm.regmem = i.rm.reg;
3342 i.rm.reg = xchg;
3343
3344 /* Use the next insn. */
3345 i.tm = t[1];
3346 }
3347
3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
3350 else if (i.tm.opcode_modifier.vex == VEX256)
3351 vector_length = 1;
3352 else
3353 {
3354 unsigned int op;
3355
3356 vector_length = 0;
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3361 {
3362 vector_length = 1;
3363 break;
3364 }
3365 }
3366
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3368 {
3369 case 0:
3370 implied_prefix = 0;
3371 break;
3372 case DATA_PREFIX_OPCODE:
3373 implied_prefix = 1;
3374 break;
3375 case REPE_PREFIX_OPCODE:
3376 implied_prefix = 2;
3377 break;
3378 case REPNE_PREFIX_OPCODE:
3379 implied_prefix = 3;
3380 break;
3381 default:
3382 abort ();
3383 }
3384
3385 /* Use 2-byte VEX prefix if possible. */
3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
3388 && i.tm.opcode_modifier.vexw != VEXW1
3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3390 {
3391 /* 2-byte VEX prefix. */
3392 unsigned int r;
3393
3394 i.vex.length = 2;
3395 i.vex.bytes[0] = 0xc5;
3396
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3402 | implied_prefix);
3403 }
3404 else
3405 {
3406 /* 3-byte VEX prefix. */
3407 unsigned int m, w;
3408
3409 i.vex.length = 3;
3410
3411 switch (i.tm.opcode_modifier.vexopcode)
3412 {
3413 case VEX0F:
3414 m = 0x1;
3415 i.vex.bytes[0] = 0xc4;
3416 break;
3417 case VEX0F38:
3418 m = 0x2;
3419 i.vex.bytes[0] = 0xc4;
3420 break;
3421 case VEX0F3A:
3422 m = 0x3;
3423 i.vex.bytes[0] = 0xc4;
3424 break;
3425 case XOP08:
3426 m = 0x8;
3427 i.vex.bytes[0] = 0x8f;
3428 break;
3429 case XOP09:
3430 m = 0x9;
3431 i.vex.bytes[0] = 0x8f;
3432 break;
3433 case XOP0A:
3434 m = 0xa;
3435 i.vex.bytes[0] = 0x8f;
3436 break;
3437 default:
3438 abort ();
3439 }
3440
3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3444
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3448 w = 1;
3449
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3453 | implied_prefix);
3454 }
3455 }
3456
3457 /* Build the EVEX prefix. */
3458
3459 static void
3460 build_evex_prefix (void)
3461 {
3462 unsigned int register_specifier;
3463 unsigned int implied_prefix;
3464 unsigned int m, w;
3465 rex_byte vrex_used = 0;
3466
3467 /* Check register specifier. */
3468 if (i.vex.register_specifier)
3469 {
3470 gas_assert ((i.vrex & REX_X) == 0);
3471
3472 register_specifier = i.vex.register_specifier->reg_num;
3473 if ((i.vex.register_specifier->reg_flags & RegRex))
3474 register_specifier += 8;
3475 /* The upper 16 registers are encoded in the fourth byte of the
3476 EVEX prefix. */
3477 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3478 i.vex.bytes[3] = 0x8;
3479 register_specifier = ~register_specifier & 0xf;
3480 }
3481 else
3482 {
3483 register_specifier = 0xf;
3484
3485 /* Encode upper 16 vector index register in the fourth byte of
3486 the EVEX prefix. */
3487 if (!(i.vrex & REX_X))
3488 i.vex.bytes[3] = 0x8;
3489 else
3490 vrex_used |= REX_X;
3491 }
3492
3493 switch ((i.tm.base_opcode >> 8) & 0xff)
3494 {
3495 case 0:
3496 implied_prefix = 0;
3497 break;
3498 case DATA_PREFIX_OPCODE:
3499 implied_prefix = 1;
3500 break;
3501 case REPE_PREFIX_OPCODE:
3502 implied_prefix = 2;
3503 break;
3504 case REPNE_PREFIX_OPCODE:
3505 implied_prefix = 3;
3506 break;
3507 default:
3508 abort ();
3509 }
3510
3511 /* 4 byte EVEX prefix. */
3512 i.vex.length = 4;
3513 i.vex.bytes[0] = 0x62;
3514
3515 /* mmmm bits. */
3516 switch (i.tm.opcode_modifier.vexopcode)
3517 {
3518 case VEX0F:
3519 m = 1;
3520 break;
3521 case VEX0F38:
3522 m = 2;
3523 break;
3524 case VEX0F3A:
3525 m = 3;
3526 break;
3527 default:
3528 abort ();
3529 break;
3530 }
3531
3532 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3533 bits from REX. */
3534 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3535
3536 /* The fifth bit of the second EVEX byte is 1's compliment of the
3537 REX_R bit in VREX. */
3538 if (!(i.vrex & REX_R))
3539 i.vex.bytes[1] |= 0x10;
3540 else
3541 vrex_used |= REX_R;
3542
3543 if ((i.reg_operands + i.imm_operands) == i.operands)
3544 {
3545 /* When all operands are registers, the REX_X bit in REX is not
3546 used. We reuse it to encode the upper 16 registers, which is
3547 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3548 as 1's compliment. */
3549 if ((i.vrex & REX_B))
3550 {
3551 vrex_used |= REX_B;
3552 i.vex.bytes[1] &= ~0x40;
3553 }
3554 }
3555
3556 /* EVEX instructions shouldn't need the REX prefix. */
3557 i.vrex &= ~vrex_used;
3558 gas_assert (i.vrex == 0);
3559
3560 /* Check the REX.W bit. */
3561 w = (i.rex & REX_W) ? 1 : 0;
3562 if (i.tm.opcode_modifier.vexw)
3563 {
3564 if (i.tm.opcode_modifier.vexw == VEXW1)
3565 w = 1;
3566 }
3567 /* If w is not set it means we are dealing with WIG instruction. */
3568 else if (!w)
3569 {
3570 if (evexwig == evexw1)
3571 w = 1;
3572 }
3573
3574 /* Encode the U bit. */
3575 implied_prefix |= 0x4;
3576
3577 /* The third byte of the EVEX prefix. */
3578 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3579
3580 /* The fourth byte of the EVEX prefix. */
3581 /* The zeroing-masking bit. */
3582 if (i.mask && i.mask->zeroing)
3583 i.vex.bytes[3] |= 0x80;
3584
3585 /* Don't always set the broadcast bit if there is no RC. */
3586 if (!i.rounding)
3587 {
3588 /* Encode the vector length. */
3589 unsigned int vec_length;
3590
3591 switch (i.tm.opcode_modifier.evex)
3592 {
3593 case EVEXLIG: /* LL' is ignored */
3594 vec_length = evexlig << 5;
3595 break;
3596 case EVEX128:
3597 vec_length = 0 << 5;
3598 break;
3599 case EVEX256:
3600 vec_length = 1 << 5;
3601 break;
3602 case EVEX512:
3603 vec_length = 2 << 5;
3604 break;
3605 default:
3606 abort ();
3607 break;
3608 }
3609 i.vex.bytes[3] |= vec_length;
3610 /* Encode the broadcast bit. */
3611 if (i.broadcast)
3612 i.vex.bytes[3] |= 0x10;
3613 }
3614 else
3615 {
3616 if (i.rounding->type != saeonly)
3617 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3618 else
3619 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3620 }
3621
3622 if (i.mask && i.mask->mask)
3623 i.vex.bytes[3] |= i.mask->mask->reg_num;
3624 }
3625
3626 static void
3627 process_immext (void)
3628 {
3629 expressionS *exp;
3630
3631 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3632 && i.operands > 0)
3633 {
3634 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3635 with an opcode suffix which is coded in the same place as an
3636 8-bit immediate field would be.
3637 Here we check those operands and remove them afterwards. */
3638 unsigned int x;
3639
3640 for (x = 0; x < i.operands; x++)
3641 if (register_number (i.op[x].regs) != x)
3642 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3643 register_prefix, i.op[x].regs->reg_name, x + 1,
3644 i.tm.name);
3645
3646 i.operands = 0;
3647 }
3648
3649 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3650 {
3651 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3652 suffix which is coded in the same place as an 8-bit immediate
3653 field would be.
3654 Here we check those operands and remove them afterwards. */
3655 unsigned int x;
3656
3657 if (i.operands != 3)
3658 abort();
3659
3660 for (x = 0; x < 2; x++)
3661 if (register_number (i.op[x].regs) != x)
3662 goto bad_register_operand;
3663
3664 /* Check for third operand for mwaitx/monitorx insn. */
3665 if (register_number (i.op[x].regs)
3666 != (x + (i.tm.extension_opcode == 0xfb)))
3667 {
3668 bad_register_operand:
3669 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3670 register_prefix, i.op[x].regs->reg_name, x+1,
3671 i.tm.name);
3672 }
3673
3674 i.operands = 0;
3675 }
3676
3677 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3678 which is coded in the same place as an 8-bit immediate field
3679 would be. Here we fake an 8-bit immediate operand from the
3680 opcode suffix stored in tm.extension_opcode.
3681
3682 AVX instructions also use this encoding, for some of
3683 3 argument instructions. */
3684
3685 gas_assert (i.imm_operands <= 1
3686 && (i.operands <= 2
3687 || ((i.tm.opcode_modifier.vex
3688 || i.tm.opcode_modifier.evex)
3689 && i.operands <= 4)));
3690
3691 exp = &im_expressions[i.imm_operands++];
3692 i.op[i.operands].imms = exp;
3693 i.types[i.operands] = imm8;
3694 i.operands++;
3695 exp->X_op = O_constant;
3696 exp->X_add_number = i.tm.extension_opcode;
3697 i.tm.extension_opcode = None;
3698 }
3699
3700
3701 static int
3702 check_hle (void)
3703 {
3704 switch (i.tm.opcode_modifier.hleprefixok)
3705 {
3706 default:
3707 abort ();
3708 case HLEPrefixNone:
3709 as_bad (_("invalid instruction `%s' after `%s'"),
3710 i.tm.name, i.hle_prefix);
3711 return 0;
3712 case HLEPrefixLock:
3713 if (i.prefix[LOCK_PREFIX])
3714 return 1;
3715 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3716 return 0;
3717 case HLEPrefixAny:
3718 return 1;
3719 case HLEPrefixRelease:
3720 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3721 {
3722 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3723 i.tm.name);
3724 return 0;
3725 }
3726 if (i.mem_operands == 0
3727 || !operand_type_check (i.types[i.operands - 1], anymem))
3728 {
3729 as_bad (_("memory destination needed for instruction `%s'"
3730 " after `xrelease'"), i.tm.name);
3731 return 0;
3732 }
3733 return 1;
3734 }
3735 }
3736
3737 /* Try the shortest encoding by shortening operand size. */
3738
3739 static void
3740 optimize_encoding (void)
3741 {
3742 int j;
3743
3744 if (optimize_for_space
3745 && i.reg_operands == 1
3746 && i.imm_operands == 1
3747 && !i.types[1].bitfield.byte
3748 && i.op[0].imms->X_op == O_constant
3749 && fits_in_imm7 (i.op[0].imms->X_add_number)
3750 && ((i.tm.base_opcode == 0xa8
3751 && i.tm.extension_opcode == None)
3752 || (i.tm.base_opcode == 0xf6
3753 && i.tm.extension_opcode == 0x0)))
3754 {
3755 /* Optimize: -Os:
3756 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3757 */
3758 unsigned int base_regnum = i.op[1].regs->reg_num;
3759 if (flag_code == CODE_64BIT || base_regnum < 4)
3760 {
3761 i.types[1].bitfield.byte = 1;
3762 /* Ignore the suffix. */
3763 i.suffix = 0;
3764 if (base_regnum >= 4
3765 && !(i.op[1].regs->reg_flags & RegRex))
3766 {
3767 /* Handle SP, BP, SI and DI registers. */
3768 if (i.types[1].bitfield.word)
3769 j = 16;
3770 else if (i.types[1].bitfield.dword)
3771 j = 32;
3772 else
3773 j = 48;
3774 i.op[1].regs -= j;
3775 }
3776 }
3777 }
3778 else if (flag_code == CODE_64BIT
3779 && ((i.reg_operands == 1
3780 && i.imm_operands == 1
3781 && i.op[0].imms->X_op == O_constant
3782 && ((i.tm.base_opcode == 0xb0
3783 && i.tm.extension_opcode == None
3784 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3785 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3786 && (((i.tm.base_opcode == 0x24
3787 || i.tm.base_opcode == 0xa8)
3788 && i.tm.extension_opcode == None)
3789 || (i.tm.base_opcode == 0x80
3790 && i.tm.extension_opcode == 0x4)
3791 || ((i.tm.base_opcode == 0xf6
3792 || i.tm.base_opcode == 0xc6)
3793 && i.tm.extension_opcode == 0x0)))))
3794 || (i.reg_operands == 2
3795 && i.op[0].regs == i.op[1].regs
3796 && ((i.tm.base_opcode == 0x30
3797 || i.tm.base_opcode == 0x28)
3798 && i.tm.extension_opcode == None)))
3799 && i.types[1].bitfield.qword)
3800 {
3801 /* Optimize: -O:
3802 andq $imm31, %r64 -> andl $imm31, %r32
3803 testq $imm31, %r64 -> testl $imm31, %r32
3804 xorq %r64, %r64 -> xorl %r32, %r32
3805 subq %r64, %r64 -> subl %r32, %r32
3806 movq $imm31, %r64 -> movl $imm31, %r32
3807 movq $imm32, %r64 -> movl $imm32, %r32
3808 */
3809 i.tm.opcode_modifier.norex64 = 1;
3810 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3811 {
3812 /* Handle
3813 movq $imm31, %r64 -> movl $imm31, %r32
3814 movq $imm32, %r64 -> movl $imm32, %r32
3815 */
3816 i.tm.operand_types[0].bitfield.imm32 = 1;
3817 i.tm.operand_types[0].bitfield.imm32s = 0;
3818 i.tm.operand_types[0].bitfield.imm64 = 0;
3819 i.types[0].bitfield.imm32 = 1;
3820 i.types[0].bitfield.imm32s = 0;
3821 i.types[0].bitfield.imm64 = 0;
3822 i.types[1].bitfield.dword = 1;
3823 i.types[1].bitfield.qword = 0;
3824 if (i.tm.base_opcode == 0xc6)
3825 {
3826 /* Handle
3827 movq $imm31, %r64 -> movl $imm31, %r32
3828 */
3829 i.tm.base_opcode = 0xb0;
3830 i.tm.extension_opcode = None;
3831 i.tm.opcode_modifier.shortform = 1;
3832 i.tm.opcode_modifier.modrm = 0;
3833 }
3834 }
3835 }
3836 else if (optimize > 1
3837 && i.reg_operands == 3
3838 && i.op[0].regs == i.op[1].regs
3839 && !i.types[2].bitfield.xmmword
3840 && (i.tm.opcode_modifier.vex
3841 || (!i.mask
3842 && !i.rounding
3843 && i.tm.opcode_modifier.evex
3844 && cpu_arch_flags.bitfield.cpuavx512vl))
3845 && ((i.tm.base_opcode == 0x55
3846 || i.tm.base_opcode == 0x6655
3847 || i.tm.base_opcode == 0x66df
3848 || i.tm.base_opcode == 0x57
3849 || i.tm.base_opcode == 0x6657
3850 || i.tm.base_opcode == 0x66ef
3851 || i.tm.base_opcode == 0x66f8
3852 || i.tm.base_opcode == 0x66f9
3853 || i.tm.base_opcode == 0x66fa
3854 || i.tm.base_opcode == 0x66fb)
3855 && i.tm.extension_opcode == None))
3856 {
3857 /* Optimize: -O2:
3858 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3859 vpsubq and vpsubw:
3860 EVEX VOP %zmmM, %zmmM, %zmmN
3861 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3862 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3863 EVEX VOP %ymmM, %ymmM, %ymmN
3864 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3865 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3866 VEX VOP %ymmM, %ymmM, %ymmN
3867 -> VEX VOP %xmmM, %xmmM, %xmmN
3868 VOP, one of vpandn and vpxor:
3869 VEX VOP %ymmM, %ymmM, %ymmN
3870 -> VEX VOP %xmmM, %xmmM, %xmmN
3871 VOP, one of vpandnd and vpandnq:
3872 EVEX VOP %zmmM, %zmmM, %zmmN
3873 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3874 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3875 EVEX VOP %ymmM, %ymmM, %ymmN
3876 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3877 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3878 VOP, one of vpxord and vpxorq:
3879 EVEX VOP %zmmM, %zmmM, %zmmN
3880 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 EVEX VOP %ymmM, %ymmM, %ymmN
3883 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3884 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3885 */
3886 if (i.tm.opcode_modifier.evex)
3887 {
3888 /* If only lower 16 vector registers are used, we can use
3889 VEX encoding. */
3890 for (j = 0; j < 3; j++)
3891 if (register_number (i.op[j].regs) > 15)
3892 break;
3893
3894 if (j < 3)
3895 i.tm.opcode_modifier.evex = EVEX128;
3896 else
3897 {
3898 i.tm.opcode_modifier.vex = VEX128;
3899 i.tm.opcode_modifier.vexw = VEXW0;
3900 i.tm.opcode_modifier.evex = 0;
3901 }
3902 }
3903 else
3904 i.tm.opcode_modifier.vex = VEX128;
3905
3906 if (i.tm.opcode_modifier.vex)
3907 for (j = 0; j < 3; j++)
3908 {
3909 i.types[j].bitfield.xmmword = 1;
3910 i.types[j].bitfield.ymmword = 0;
3911 }
3912 }
3913 }
3914
3915 /* This is the guts of the machine-dependent assembler. LINE points to a
3916 machine dependent instruction. This function is supposed to emit
3917 the frags/bytes it assembles to. */
3918
3919 void
3920 md_assemble (char *line)
3921 {
3922 unsigned int j;
3923 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3924 const insn_template *t;
3925
3926 /* Initialize globals. */
3927 memset (&i, '\0', sizeof (i));
3928 for (j = 0; j < MAX_OPERANDS; j++)
3929 i.reloc[j] = NO_RELOC;
3930 memset (disp_expressions, '\0', sizeof (disp_expressions));
3931 memset (im_expressions, '\0', sizeof (im_expressions));
3932 save_stack_p = save_stack;
3933
3934 /* First parse an instruction mnemonic & call i386_operand for the operands.
3935 We assume that the scrubber has arranged it so that line[0] is the valid
3936 start of a (possibly prefixed) mnemonic. */
3937
3938 line = parse_insn (line, mnemonic);
3939 if (line == NULL)
3940 return;
3941 mnem_suffix = i.suffix;
3942
3943 line = parse_operands (line, mnemonic);
3944 this_operand = -1;
3945 xfree (i.memop1_string);
3946 i.memop1_string = NULL;
3947 if (line == NULL)
3948 return;
3949
3950 /* Now we've parsed the mnemonic into a set of templates, and have the
3951 operands at hand. */
3952
3953 /* All intel opcodes have reversed operands except for "bound" and
3954 "enter". We also don't reverse intersegment "jmp" and "call"
3955 instructions with 2 immediate operands so that the immediate segment
3956 precedes the offset, as it does when in AT&T mode. */
3957 if (intel_syntax
3958 && i.operands > 1
3959 && (strcmp (mnemonic, "bound") != 0)
3960 && (strcmp (mnemonic, "invlpga") != 0)
3961 && !(operand_type_check (i.types[0], imm)
3962 && operand_type_check (i.types[1], imm)))
3963 swap_operands ();
3964
3965 /* The order of the immediates should be reversed
3966 for 2 immediates extrq and insertq instructions */
3967 if (i.imm_operands == 2
3968 && (strcmp (mnemonic, "extrq") == 0
3969 || strcmp (mnemonic, "insertq") == 0))
3970 swap_2_operands (0, 1);
3971
3972 if (i.imm_operands)
3973 optimize_imm ();
3974
3975 /* Don't optimize displacement for movabs since it only takes 64bit
3976 displacement. */
3977 if (i.disp_operands
3978 && i.disp_encoding != disp_encoding_32bit
3979 && (flag_code != CODE_64BIT
3980 || strcmp (mnemonic, "movabs") != 0))
3981 optimize_disp ();
3982
3983 /* Next, we find a template that matches the given insn,
3984 making sure the overlap of the given operands types is consistent
3985 with the template operand types. */
3986
3987 if (!(t = match_template (mnem_suffix)))
3988 return;
3989
3990 if (sse_check != check_none
3991 && !i.tm.opcode_modifier.noavx
3992 && !i.tm.cpu_flags.bitfield.cpuavx
3993 && (i.tm.cpu_flags.bitfield.cpusse
3994 || i.tm.cpu_flags.bitfield.cpusse2
3995 || i.tm.cpu_flags.bitfield.cpusse3
3996 || i.tm.cpu_flags.bitfield.cpussse3
3997 || i.tm.cpu_flags.bitfield.cpusse4_1
3998 || i.tm.cpu_flags.bitfield.cpusse4_2
3999 || i.tm.cpu_flags.bitfield.cpupclmul
4000 || i.tm.cpu_flags.bitfield.cpuaes
4001 || i.tm.cpu_flags.bitfield.cpugfni))
4002 {
4003 (sse_check == check_warning
4004 ? as_warn
4005 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4006 }
4007
4008 /* Zap movzx and movsx suffix. The suffix has been set from
4009 "word ptr" or "byte ptr" on the source operand in Intel syntax
4010 or extracted from mnemonic in AT&T syntax. But we'll use
4011 the destination register to choose the suffix for encoding. */
4012 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4013 {
4014 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4015 there is no suffix, the default will be byte extension. */
4016 if (i.reg_operands != 2
4017 && !i.suffix
4018 && intel_syntax)
4019 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4020
4021 i.suffix = 0;
4022 }
4023
4024 if (i.tm.opcode_modifier.fwait)
4025 if (!add_prefix (FWAIT_OPCODE))
4026 return;
4027
4028 /* Check if REP prefix is OK. */
4029 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4030 {
4031 as_bad (_("invalid instruction `%s' after `%s'"),
4032 i.tm.name, i.rep_prefix);
4033 return;
4034 }
4035
4036 /* Check for lock without a lockable instruction. Destination operand
4037 must be memory unless it is xchg (0x86). */
4038 if (i.prefix[LOCK_PREFIX]
4039 && (!i.tm.opcode_modifier.islockable
4040 || i.mem_operands == 0
4041 || (i.tm.base_opcode != 0x86
4042 && !operand_type_check (i.types[i.operands - 1], anymem))))
4043 {
4044 as_bad (_("expecting lockable instruction after `lock'"));
4045 return;
4046 }
4047
4048 /* Check if HLE prefix is OK. */
4049 if (i.hle_prefix && !check_hle ())
4050 return;
4051
4052 /* Check BND prefix. */
4053 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4054 as_bad (_("expecting valid branch instruction after `bnd'"));
4055
4056 /* Check NOTRACK prefix. */
4057 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4058 as_bad (_("expecting indirect branch instruction after `notrack'"));
4059
4060 if (i.tm.cpu_flags.bitfield.cpumpx)
4061 {
4062 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4063 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4064 else if (flag_code != CODE_16BIT
4065 ? i.prefix[ADDR_PREFIX]
4066 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4067 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4068 }
4069
4070 /* Insert BND prefix. */
4071 if (add_bnd_prefix
4072 && i.tm.opcode_modifier.bndprefixok
4073 && !i.prefix[BND_PREFIX])
4074 add_prefix (BND_PREFIX_OPCODE);
4075
4076 /* Check string instruction segment overrides. */
4077 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4078 {
4079 if (!check_string ())
4080 return;
4081 i.disp_operands = 0;
4082 }
4083
4084 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4085 optimize_encoding ();
4086
4087 if (!process_suffix ())
4088 return;
4089
4090 /* Update operand types. */
4091 for (j = 0; j < i.operands; j++)
4092 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4093
4094 /* Make still unresolved immediate matches conform to size of immediate
4095 given in i.suffix. */
4096 if (!finalize_imm ())
4097 return;
4098
4099 if (i.types[0].bitfield.imm1)
4100 i.imm_operands = 0; /* kludge for shift insns. */
4101
4102 /* We only need to check those implicit registers for instructions
4103 with 3 operands or less. */
4104 if (i.operands <= 3)
4105 for (j = 0; j < i.operands; j++)
4106 if (i.types[j].bitfield.inoutportreg
4107 || i.types[j].bitfield.shiftcount
4108 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4109 i.reg_operands--;
4110
4111 /* ImmExt should be processed after SSE2AVX. */
4112 if (!i.tm.opcode_modifier.sse2avx
4113 && i.tm.opcode_modifier.immext)
4114 process_immext ();
4115
4116 /* For insns with operands there are more diddles to do to the opcode. */
4117 if (i.operands)
4118 {
4119 if (!process_operands ())
4120 return;
4121 }
4122 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4123 {
4124 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4125 as_warn (_("translating to `%sp'"), i.tm.name);
4126 }
4127
4128 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4129 {
4130 if (flag_code == CODE_16BIT)
4131 {
4132 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4133 i.tm.name);
4134 return;
4135 }
4136
4137 if (i.tm.opcode_modifier.vex)
4138 build_vex_prefix (t);
4139 else
4140 build_evex_prefix ();
4141 }
4142
4143 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4144 instructions may define INT_OPCODE as well, so avoid this corner
4145 case for those instructions that use MODRM. */
4146 if (i.tm.base_opcode == INT_OPCODE
4147 && !i.tm.opcode_modifier.modrm
4148 && i.op[0].imms->X_add_number == 3)
4149 {
4150 i.tm.base_opcode = INT3_OPCODE;
4151 i.imm_operands = 0;
4152 }
4153
4154 if ((i.tm.opcode_modifier.jump
4155 || i.tm.opcode_modifier.jumpbyte
4156 || i.tm.opcode_modifier.jumpdword)
4157 && i.op[0].disps->X_op == O_constant)
4158 {
4159 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4160 the absolute address given by the constant. Since ix86 jumps and
4161 calls are pc relative, we need to generate a reloc. */
4162 i.op[0].disps->X_add_symbol = &abs_symbol;
4163 i.op[0].disps->X_op = O_symbol;
4164 }
4165
4166 if (i.tm.opcode_modifier.rex64)
4167 i.rex |= REX_W;
4168
4169 /* For 8 bit registers we need an empty rex prefix. Also if the
4170 instruction already has a prefix, we need to convert old
4171 registers to new ones. */
4172
4173 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4174 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4175 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4176 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4177 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4178 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4179 && i.rex != 0))
4180 {
4181 int x;
4182
4183 i.rex |= REX_OPCODE;
4184 for (x = 0; x < 2; x++)
4185 {
4186 /* Look for 8 bit operand that uses old registers. */
4187 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4188 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4189 {
4190 /* In case it is "hi" register, give up. */
4191 if (i.op[x].regs->reg_num > 3)
4192 as_bad (_("can't encode register '%s%s' in an "
4193 "instruction requiring REX prefix."),
4194 register_prefix, i.op[x].regs->reg_name);
4195
4196 /* Otherwise it is equivalent to the extended register.
4197 Since the encoding doesn't change this is merely
4198 cosmetic cleanup for debug output. */
4199
4200 i.op[x].regs = i.op[x].regs + 8;
4201 }
4202 }
4203 }
4204
4205 if (i.rex == 0 && i.rex_encoding)
4206 {
4207 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4208 that uses legacy register. If it is "hi" register, don't add
4209 the REX_OPCODE byte. */
4210 int x;
4211 for (x = 0; x < 2; x++)
4212 if (i.types[x].bitfield.reg
4213 && i.types[x].bitfield.byte
4214 && (i.op[x].regs->reg_flags & RegRex64) == 0
4215 && i.op[x].regs->reg_num > 3)
4216 {
4217 i.rex_encoding = FALSE;
4218 break;
4219 }
4220
4221 if (i.rex_encoding)
4222 i.rex = REX_OPCODE;
4223 }
4224
4225 if (i.rex != 0)
4226 add_prefix (REX_OPCODE | i.rex);
4227
4228 /* We are ready to output the insn. */
4229 output_insn ();
4230 }
4231
4232 static char *
4233 parse_insn (char *line, char *mnemonic)
4234 {
4235 char *l = line;
4236 char *token_start = l;
4237 char *mnem_p;
4238 int supported;
4239 const insn_template *t;
4240 char *dot_p = NULL;
4241
4242 while (1)
4243 {
4244 mnem_p = mnemonic;
4245 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4246 {
4247 if (*mnem_p == '.')
4248 dot_p = mnem_p;
4249 mnem_p++;
4250 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4251 {
4252 as_bad (_("no such instruction: `%s'"), token_start);
4253 return NULL;
4254 }
4255 l++;
4256 }
4257 if (!is_space_char (*l)
4258 && *l != END_OF_INSN
4259 && (intel_syntax
4260 || (*l != PREFIX_SEPARATOR
4261 && *l != ',')))
4262 {
4263 as_bad (_("invalid character %s in mnemonic"),
4264 output_invalid (*l));
4265 return NULL;
4266 }
4267 if (token_start == l)
4268 {
4269 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4270 as_bad (_("expecting prefix; got nothing"));
4271 else
4272 as_bad (_("expecting mnemonic; got nothing"));
4273 return NULL;
4274 }
4275
4276 /* Look up instruction (or prefix) via hash table. */
4277 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4278
4279 if (*l != END_OF_INSN
4280 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4281 && current_templates
4282 && current_templates->start->opcode_modifier.isprefix)
4283 {
4284 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4285 {
4286 as_bad ((flag_code != CODE_64BIT
4287 ? _("`%s' is only supported in 64-bit mode")
4288 : _("`%s' is not supported in 64-bit mode")),
4289 current_templates->start->name);
4290 return NULL;
4291 }
4292 /* If we are in 16-bit mode, do not allow addr16 or data16.
4293 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4294 if ((current_templates->start->opcode_modifier.size16
4295 || current_templates->start->opcode_modifier.size32)
4296 && flag_code != CODE_64BIT
4297 && (current_templates->start->opcode_modifier.size32
4298 ^ (flag_code == CODE_16BIT)))
4299 {
4300 as_bad (_("redundant %s prefix"),
4301 current_templates->start->name);
4302 return NULL;
4303 }
4304 if (current_templates->start->opcode_length == 0)
4305 {
4306 /* Handle pseudo prefixes. */
4307 switch (current_templates->start->base_opcode)
4308 {
4309 case 0x0:
4310 /* {disp8} */
4311 i.disp_encoding = disp_encoding_8bit;
4312 break;
4313 case 0x1:
4314 /* {disp32} */
4315 i.disp_encoding = disp_encoding_32bit;
4316 break;
4317 case 0x2:
4318 /* {load} */
4319 i.dir_encoding = dir_encoding_load;
4320 break;
4321 case 0x3:
4322 /* {store} */
4323 i.dir_encoding = dir_encoding_store;
4324 break;
4325 case 0x4:
4326 /* {vex2} */
4327 i.vec_encoding = vex_encoding_vex2;
4328 break;
4329 case 0x5:
4330 /* {vex3} */
4331 i.vec_encoding = vex_encoding_vex3;
4332 break;
4333 case 0x6:
4334 /* {evex} */
4335 i.vec_encoding = vex_encoding_evex;
4336 break;
4337 case 0x7:
4338 /* {rex} */
4339 i.rex_encoding = TRUE;
4340 break;
4341 case 0x8:
4342 /* {nooptimize} */
4343 i.no_optimize = TRUE;
4344 break;
4345 default:
4346 abort ();
4347 }
4348 }
4349 else
4350 {
4351 /* Add prefix, checking for repeated prefixes. */
4352 switch (add_prefix (current_templates->start->base_opcode))
4353 {
4354 case PREFIX_EXIST:
4355 return NULL;
4356 case PREFIX_DS:
4357 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4358 i.notrack_prefix = current_templates->start->name;
4359 break;
4360 case PREFIX_REP:
4361 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4362 i.hle_prefix = current_templates->start->name;
4363 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4364 i.bnd_prefix = current_templates->start->name;
4365 else
4366 i.rep_prefix = current_templates->start->name;
4367 break;
4368 default:
4369 break;
4370 }
4371 }
4372 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4373 token_start = ++l;
4374 }
4375 else
4376 break;
4377 }
4378
4379 if (!current_templates)
4380 {
4381 /* Check if we should swap operand or force 32bit displacement in
4382 encoding. */
4383 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4384 i.dir_encoding = dir_encoding_store;
4385 else if (mnem_p - 3 == dot_p
4386 && dot_p[1] == 'd'
4387 && dot_p[2] == '8')
4388 i.disp_encoding = disp_encoding_8bit;
4389 else if (mnem_p - 4 == dot_p
4390 && dot_p[1] == 'd'
4391 && dot_p[2] == '3'
4392 && dot_p[3] == '2')
4393 i.disp_encoding = disp_encoding_32bit;
4394 else
4395 goto check_suffix;
4396 mnem_p = dot_p;
4397 *dot_p = '\0';
4398 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4399 }
4400
4401 if (!current_templates)
4402 {
4403 check_suffix:
4404 /* See if we can get a match by trimming off a suffix. */
4405 switch (mnem_p[-1])
4406 {
4407 case WORD_MNEM_SUFFIX:
4408 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4409 i.suffix = SHORT_MNEM_SUFFIX;
4410 else
4411 /* Fall through. */
4412 case BYTE_MNEM_SUFFIX:
4413 case QWORD_MNEM_SUFFIX:
4414 i.suffix = mnem_p[-1];
4415 mnem_p[-1] = '\0';
4416 current_templates = (const templates *) hash_find (op_hash,
4417 mnemonic);
4418 break;
4419 case SHORT_MNEM_SUFFIX:
4420 case LONG_MNEM_SUFFIX:
4421 if (!intel_syntax)
4422 {
4423 i.suffix = mnem_p[-1];
4424 mnem_p[-1] = '\0';
4425 current_templates = (const templates *) hash_find (op_hash,
4426 mnemonic);
4427 }
4428 break;
4429
4430 /* Intel Syntax. */
4431 case 'd':
4432 if (intel_syntax)
4433 {
4434 if (intel_float_operand (mnemonic) == 1)
4435 i.suffix = SHORT_MNEM_SUFFIX;
4436 else
4437 i.suffix = LONG_MNEM_SUFFIX;
4438 mnem_p[-1] = '\0';
4439 current_templates = (const templates *) hash_find (op_hash,
4440 mnemonic);
4441 }
4442 break;
4443 }
4444 if (!current_templates)
4445 {
4446 as_bad (_("no such instruction: `%s'"), token_start);
4447 return NULL;
4448 }
4449 }
4450
4451 if (current_templates->start->opcode_modifier.jump
4452 || current_templates->start->opcode_modifier.jumpbyte)
4453 {
4454 /* Check for a branch hint. We allow ",pt" and ",pn" for
4455 predict taken and predict not taken respectively.
4456 I'm not sure that branch hints actually do anything on loop
4457 and jcxz insns (JumpByte) for current Pentium4 chips. They
4458 may work in the future and it doesn't hurt to accept them
4459 now. */
4460 if (l[0] == ',' && l[1] == 'p')
4461 {
4462 if (l[2] == 't')
4463 {
4464 if (!add_prefix (DS_PREFIX_OPCODE))
4465 return NULL;
4466 l += 3;
4467 }
4468 else if (l[2] == 'n')
4469 {
4470 if (!add_prefix (CS_PREFIX_OPCODE))
4471 return NULL;
4472 l += 3;
4473 }
4474 }
4475 }
4476 /* Any other comma loses. */
4477 if (*l == ',')
4478 {
4479 as_bad (_("invalid character %s in mnemonic"),
4480 output_invalid (*l));
4481 return NULL;
4482 }
4483
4484 /* Check if instruction is supported on specified architecture. */
4485 supported = 0;
4486 for (t = current_templates->start; t < current_templates->end; ++t)
4487 {
4488 supported |= cpu_flags_match (t);
4489 if (supported == CPU_FLAGS_PERFECT_MATCH)
4490 goto skip;
4491 }
4492
4493 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4494 {
4495 as_bad (flag_code == CODE_64BIT
4496 ? _("`%s' is not supported in 64-bit mode")
4497 : _("`%s' is only supported in 64-bit mode"),
4498 current_templates->start->name);
4499 return NULL;
4500 }
4501 if (supported != CPU_FLAGS_PERFECT_MATCH)
4502 {
4503 as_bad (_("`%s' is not supported on `%s%s'"),
4504 current_templates->start->name,
4505 cpu_arch_name ? cpu_arch_name : default_arch,
4506 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4507 return NULL;
4508 }
4509
4510 skip:
4511 if (!cpu_arch_flags.bitfield.cpui386
4512 && (flag_code != CODE_16BIT))
4513 {
4514 as_warn (_("use .code16 to ensure correct addressing mode"));
4515 }
4516
4517 return l;
4518 }
4519
4520 static char *
4521 parse_operands (char *l, const char *mnemonic)
4522 {
4523 char *token_start;
4524
4525 /* 1 if operand is pending after ','. */
4526 unsigned int expecting_operand = 0;
4527
4528 /* Non-zero if operand parens not balanced. */
4529 unsigned int paren_not_balanced;
4530
4531 while (*l != END_OF_INSN)
4532 {
4533 /* Skip optional white space before operand. */
4534 if (is_space_char (*l))
4535 ++l;
4536 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4537 {
4538 as_bad (_("invalid character %s before operand %d"),
4539 output_invalid (*l),
4540 i.operands + 1);
4541 return NULL;
4542 }
4543 token_start = l; /* After white space. */
4544 paren_not_balanced = 0;
4545 while (paren_not_balanced || *l != ',')
4546 {
4547 if (*l == END_OF_INSN)
4548 {
4549 if (paren_not_balanced)
4550 {
4551 if (!intel_syntax)
4552 as_bad (_("unbalanced parenthesis in operand %d."),
4553 i.operands + 1);
4554 else
4555 as_bad (_("unbalanced brackets in operand %d."),
4556 i.operands + 1);
4557 return NULL;
4558 }
4559 else
4560 break; /* we are done */
4561 }
4562 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4563 {
4564 as_bad (_("invalid character %s in operand %d"),
4565 output_invalid (*l),
4566 i.operands + 1);
4567 return NULL;
4568 }
4569 if (!intel_syntax)
4570 {
4571 if (*l == '(')
4572 ++paren_not_balanced;
4573 if (*l == ')')
4574 --paren_not_balanced;
4575 }
4576 else
4577 {
4578 if (*l == '[')
4579 ++paren_not_balanced;
4580 if (*l == ']')
4581 --paren_not_balanced;
4582 }
4583 l++;
4584 }
4585 if (l != token_start)
4586 { /* Yes, we've read in another operand. */
4587 unsigned int operand_ok;
4588 this_operand = i.operands++;
4589 if (i.operands > MAX_OPERANDS)
4590 {
4591 as_bad (_("spurious operands; (%d operands/instruction max)"),
4592 MAX_OPERANDS);
4593 return NULL;
4594 }
4595 i.types[this_operand].bitfield.unspecified = 1;
4596 /* Now parse operand adding info to 'i' as we go along. */
4597 END_STRING_AND_SAVE (l);
4598
4599 if (intel_syntax)
4600 operand_ok =
4601 i386_intel_operand (token_start,
4602 intel_float_operand (mnemonic));
4603 else
4604 operand_ok = i386_att_operand (token_start);
4605
4606 RESTORE_END_STRING (l);
4607 if (!operand_ok)
4608 return NULL;
4609 }
4610 else
4611 {
4612 if (expecting_operand)
4613 {
4614 expecting_operand_after_comma:
4615 as_bad (_("expecting operand after ','; got nothing"));
4616 return NULL;
4617 }
4618 if (*l == ',')
4619 {
4620 as_bad (_("expecting operand before ','; got nothing"));
4621 return NULL;
4622 }
4623 }
4624
4625 /* Now *l must be either ',' or END_OF_INSN. */
4626 if (*l == ',')
4627 {
4628 if (*++l == END_OF_INSN)
4629 {
4630 /* Just skip it, if it's \n complain. */
4631 goto expecting_operand_after_comma;
4632 }
4633 expecting_operand = 1;
4634 }
4635 }
4636 return l;
4637 }
4638
4639 static void
4640 swap_2_operands (int xchg1, int xchg2)
4641 {
4642 union i386_op temp_op;
4643 i386_operand_type temp_type;
4644 enum bfd_reloc_code_real temp_reloc;
4645
4646 temp_type = i.types[xchg2];
4647 i.types[xchg2] = i.types[xchg1];
4648 i.types[xchg1] = temp_type;
4649 temp_op = i.op[xchg2];
4650 i.op[xchg2] = i.op[xchg1];
4651 i.op[xchg1] = temp_op;
4652 temp_reloc = i.reloc[xchg2];
4653 i.reloc[xchg2] = i.reloc[xchg1];
4654 i.reloc[xchg1] = temp_reloc;
4655
4656 if (i.mask)
4657 {
4658 if (i.mask->operand == xchg1)
4659 i.mask->operand = xchg2;
4660 else if (i.mask->operand == xchg2)
4661 i.mask->operand = xchg1;
4662 }
4663 if (i.broadcast)
4664 {
4665 if (i.broadcast->operand == xchg1)
4666 i.broadcast->operand = xchg2;
4667 else if (i.broadcast->operand == xchg2)
4668 i.broadcast->operand = xchg1;
4669 }
4670 if (i.rounding)
4671 {
4672 if (i.rounding->operand == xchg1)
4673 i.rounding->operand = xchg2;
4674 else if (i.rounding->operand == xchg2)
4675 i.rounding->operand = xchg1;
4676 }
4677 }
4678
4679 static void
4680 swap_operands (void)
4681 {
4682 switch (i.operands)
4683 {
4684 case 5:
4685 case 4:
4686 swap_2_operands (1, i.operands - 2);
4687 /* Fall through. */
4688 case 3:
4689 case 2:
4690 swap_2_operands (0, i.operands - 1);
4691 break;
4692 default:
4693 abort ();
4694 }
4695
4696 if (i.mem_operands == 2)
4697 {
4698 const seg_entry *temp_seg;
4699 temp_seg = i.seg[0];
4700 i.seg[0] = i.seg[1];
4701 i.seg[1] = temp_seg;
4702 }
4703 }
4704
4705 /* Try to ensure constant immediates are represented in the smallest
4706 opcode possible. */
4707 static void
4708 optimize_imm (void)
4709 {
4710 char guess_suffix = 0;
4711 int op;
4712
4713 if (i.suffix)
4714 guess_suffix = i.suffix;
4715 else if (i.reg_operands)
4716 {
4717 /* Figure out a suffix from the last register operand specified.
4718 We can't do this properly yet, ie. excluding InOutPortReg,
4719 but the following works for instructions with immediates.
4720 In any case, we can't set i.suffix yet. */
4721 for (op = i.operands; --op >= 0;)
4722 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4723 {
4724 guess_suffix = BYTE_MNEM_SUFFIX;
4725 break;
4726 }
4727 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4728 {
4729 guess_suffix = WORD_MNEM_SUFFIX;
4730 break;
4731 }
4732 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4733 {
4734 guess_suffix = LONG_MNEM_SUFFIX;
4735 break;
4736 }
4737 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4738 {
4739 guess_suffix = QWORD_MNEM_SUFFIX;
4740 break;
4741 }
4742 }
4743 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4744 guess_suffix = WORD_MNEM_SUFFIX;
4745
4746 for (op = i.operands; --op >= 0;)
4747 if (operand_type_check (i.types[op], imm))
4748 {
4749 switch (i.op[op].imms->X_op)
4750 {
4751 case O_constant:
4752 /* If a suffix is given, this operand may be shortened. */
4753 switch (guess_suffix)
4754 {
4755 case LONG_MNEM_SUFFIX:
4756 i.types[op].bitfield.imm32 = 1;
4757 i.types[op].bitfield.imm64 = 1;
4758 break;
4759 case WORD_MNEM_SUFFIX:
4760 i.types[op].bitfield.imm16 = 1;
4761 i.types[op].bitfield.imm32 = 1;
4762 i.types[op].bitfield.imm32s = 1;
4763 i.types[op].bitfield.imm64 = 1;
4764 break;
4765 case BYTE_MNEM_SUFFIX:
4766 i.types[op].bitfield.imm8 = 1;
4767 i.types[op].bitfield.imm8s = 1;
4768 i.types[op].bitfield.imm16 = 1;
4769 i.types[op].bitfield.imm32 = 1;
4770 i.types[op].bitfield.imm32s = 1;
4771 i.types[op].bitfield.imm64 = 1;
4772 break;
4773 }
4774
4775 /* If this operand is at most 16 bits, convert it
4776 to a signed 16 bit number before trying to see
4777 whether it will fit in an even smaller size.
4778 This allows a 16-bit operand such as $0xffe0 to
4779 be recognised as within Imm8S range. */
4780 if ((i.types[op].bitfield.imm16)
4781 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4782 {
4783 i.op[op].imms->X_add_number =
4784 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4785 }
4786 #ifdef BFD64
4787 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4788 if ((i.types[op].bitfield.imm32)
4789 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4790 == 0))
4791 {
4792 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4793 ^ ((offsetT) 1 << 31))
4794 - ((offsetT) 1 << 31));
4795 }
4796 #endif
4797 i.types[op]
4798 = operand_type_or (i.types[op],
4799 smallest_imm_type (i.op[op].imms->X_add_number));
4800
4801 /* We must avoid matching of Imm32 templates when 64bit
4802 only immediate is available. */
4803 if (guess_suffix == QWORD_MNEM_SUFFIX)
4804 i.types[op].bitfield.imm32 = 0;
4805 break;
4806
4807 case O_absent:
4808 case O_register:
4809 abort ();
4810
4811 /* Symbols and expressions. */
4812 default:
4813 /* Convert symbolic operand to proper sizes for matching, but don't
4814 prevent matching a set of insns that only supports sizes other
4815 than those matching the insn suffix. */
4816 {
4817 i386_operand_type mask, allowed;
4818 const insn_template *t;
4819
4820 operand_type_set (&mask, 0);
4821 operand_type_set (&allowed, 0);
4822
4823 for (t = current_templates->start;
4824 t < current_templates->end;
4825 ++t)
4826 allowed = operand_type_or (allowed,
4827 t->operand_types[op]);
4828 switch (guess_suffix)
4829 {
4830 case QWORD_MNEM_SUFFIX:
4831 mask.bitfield.imm64 = 1;
4832 mask.bitfield.imm32s = 1;
4833 break;
4834 case LONG_MNEM_SUFFIX:
4835 mask.bitfield.imm32 = 1;
4836 break;
4837 case WORD_MNEM_SUFFIX:
4838 mask.bitfield.imm16 = 1;
4839 break;
4840 case BYTE_MNEM_SUFFIX:
4841 mask.bitfield.imm8 = 1;
4842 break;
4843 default:
4844 break;
4845 }
4846 allowed = operand_type_and (mask, allowed);
4847 if (!operand_type_all_zero (&allowed))
4848 i.types[op] = operand_type_and (i.types[op], mask);
4849 }
4850 break;
4851 }
4852 }
4853 }
4854
4855 /* Try to use the smallest displacement type too. */
4856 static void
4857 optimize_disp (void)
4858 {
4859 int op;
4860
4861 for (op = i.operands; --op >= 0;)
4862 if (operand_type_check (i.types[op], disp))
4863 {
4864 if (i.op[op].disps->X_op == O_constant)
4865 {
4866 offsetT op_disp = i.op[op].disps->X_add_number;
4867
4868 if (i.types[op].bitfield.disp16
4869 && (op_disp & ~(offsetT) 0xffff) == 0)
4870 {
4871 /* If this operand is at most 16 bits, convert
4872 to a signed 16 bit number and don't use 64bit
4873 displacement. */
4874 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4875 i.types[op].bitfield.disp64 = 0;
4876 }
4877 #ifdef BFD64
4878 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4879 if (i.types[op].bitfield.disp32
4880 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4881 {
4882 /* If this operand is at most 32 bits, convert
4883 to a signed 32 bit number and don't use 64bit
4884 displacement. */
4885 op_disp &= (((offsetT) 2 << 31) - 1);
4886 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4887 i.types[op].bitfield.disp64 = 0;
4888 }
4889 #endif
4890 if (!op_disp && i.types[op].bitfield.baseindex)
4891 {
4892 i.types[op].bitfield.disp8 = 0;
4893 i.types[op].bitfield.disp16 = 0;
4894 i.types[op].bitfield.disp32 = 0;
4895 i.types[op].bitfield.disp32s = 0;
4896 i.types[op].bitfield.disp64 = 0;
4897 i.op[op].disps = 0;
4898 i.disp_operands--;
4899 }
4900 else if (flag_code == CODE_64BIT)
4901 {
4902 if (fits_in_signed_long (op_disp))
4903 {
4904 i.types[op].bitfield.disp64 = 0;
4905 i.types[op].bitfield.disp32s = 1;
4906 }
4907 if (i.prefix[ADDR_PREFIX]
4908 && fits_in_unsigned_long (op_disp))
4909 i.types[op].bitfield.disp32 = 1;
4910 }
4911 if ((i.types[op].bitfield.disp32
4912 || i.types[op].bitfield.disp32s
4913 || i.types[op].bitfield.disp16)
4914 && fits_in_disp8 (op_disp))
4915 i.types[op].bitfield.disp8 = 1;
4916 }
4917 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4918 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4919 {
4920 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4921 i.op[op].disps, 0, i.reloc[op]);
4922 i.types[op].bitfield.disp8 = 0;
4923 i.types[op].bitfield.disp16 = 0;
4924 i.types[op].bitfield.disp32 = 0;
4925 i.types[op].bitfield.disp32s = 0;
4926 i.types[op].bitfield.disp64 = 0;
4927 }
4928 else
4929 /* We only support 64bit displacement on constants. */
4930 i.types[op].bitfield.disp64 = 0;
4931 }
4932 }
4933
4934 /* Check if operands are valid for the instruction. */
4935
4936 static int
4937 check_VecOperands (const insn_template *t)
4938 {
4939 unsigned int op;
4940
4941 /* Without VSIB byte, we can't have a vector register for index. */
4942 if (!t->opcode_modifier.vecsib
4943 && i.index_reg
4944 && (i.index_reg->reg_type.bitfield.xmmword
4945 || i.index_reg->reg_type.bitfield.ymmword
4946 || i.index_reg->reg_type.bitfield.zmmword))
4947 {
4948 i.error = unsupported_vector_index_register;
4949 return 1;
4950 }
4951
4952 /* Check if default mask is allowed. */
4953 if (t->opcode_modifier.nodefmask
4954 && (!i.mask || i.mask->mask->reg_num == 0))
4955 {
4956 i.error = no_default_mask;
4957 return 1;
4958 }
4959
4960 /* For VSIB byte, we need a vector register for index, and all vector
4961 registers must be distinct. */
4962 if (t->opcode_modifier.vecsib)
4963 {
4964 if (!i.index_reg
4965 || !((t->opcode_modifier.vecsib == VecSIB128
4966 && i.index_reg->reg_type.bitfield.xmmword)
4967 || (t->opcode_modifier.vecsib == VecSIB256
4968 && i.index_reg->reg_type.bitfield.ymmword)
4969 || (t->opcode_modifier.vecsib == VecSIB512
4970 && i.index_reg->reg_type.bitfield.zmmword)))
4971 {
4972 i.error = invalid_vsib_address;
4973 return 1;
4974 }
4975
4976 gas_assert (i.reg_operands == 2 || i.mask);
4977 if (i.reg_operands == 2 && !i.mask)
4978 {
4979 gas_assert (i.types[0].bitfield.regsimd);
4980 gas_assert (i.types[0].bitfield.xmmword
4981 || i.types[0].bitfield.ymmword);
4982 gas_assert (i.types[2].bitfield.regsimd);
4983 gas_assert (i.types[2].bitfield.xmmword
4984 || i.types[2].bitfield.ymmword);
4985 if (operand_check == check_none)
4986 return 0;
4987 if (register_number (i.op[0].regs)
4988 != register_number (i.index_reg)
4989 && register_number (i.op[2].regs)
4990 != register_number (i.index_reg)
4991 && register_number (i.op[0].regs)
4992 != register_number (i.op[2].regs))
4993 return 0;
4994 if (operand_check == check_error)
4995 {
4996 i.error = invalid_vector_register_set;
4997 return 1;
4998 }
4999 as_warn (_("mask, index, and destination registers should be distinct"));
5000 }
5001 else if (i.reg_operands == 1 && i.mask)
5002 {
5003 if (i.types[1].bitfield.regsimd
5004 && (i.types[1].bitfield.xmmword
5005 || i.types[1].bitfield.ymmword
5006 || i.types[1].bitfield.zmmword)
5007 && (register_number (i.op[1].regs)
5008 == register_number (i.index_reg)))
5009 {
5010 if (operand_check == check_error)
5011 {
5012 i.error = invalid_vector_register_set;
5013 return 1;
5014 }
5015 if (operand_check != check_none)
5016 as_warn (_("index and destination registers should be distinct"));
5017 }
5018 }
5019 }
5020
5021 /* Check if broadcast is supported by the instruction and is applied
5022 to the memory operand. */
5023 if (i.broadcast)
5024 {
5025 int broadcasted_opnd_size;
5026
5027 /* Check if specified broadcast is supported in this instruction,
5028 and it's applied to memory operand of DWORD or QWORD type,
5029 depending on VecESize. */
5030 if (i.broadcast->type != t->opcode_modifier.broadcast
5031 || !i.types[i.broadcast->operand].bitfield.mem
5032 || (t->opcode_modifier.vecesize == 0
5033 && !i.types[i.broadcast->operand].bitfield.dword
5034 && !i.types[i.broadcast->operand].bitfield.unspecified)
5035 || (t->opcode_modifier.vecesize == 1
5036 && !i.types[i.broadcast->operand].bitfield.qword
5037 && !i.types[i.broadcast->operand].bitfield.unspecified))
5038 goto bad_broadcast;
5039
5040 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5041 if (i.broadcast->type == BROADCAST_1TO16)
5042 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5043 else if (i.broadcast->type == BROADCAST_1TO8)
5044 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5045 else if (i.broadcast->type == BROADCAST_1TO4)
5046 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5047 else if (i.broadcast->type == BROADCAST_1TO2)
5048 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5049 else
5050 goto bad_broadcast;
5051
5052 if ((broadcasted_opnd_size == 256
5053 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5054 || (broadcasted_opnd_size == 512
5055 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5056 {
5057 bad_broadcast:
5058 i.error = unsupported_broadcast;
5059 return 1;
5060 }
5061 }
5062 /* If broadcast is supported in this instruction, we need to check if
5063 operand of one-element size isn't specified without broadcast. */
5064 else if (t->opcode_modifier.broadcast && i.mem_operands)
5065 {
5066 /* Find memory operand. */
5067 for (op = 0; op < i.operands; op++)
5068 if (operand_type_check (i.types[op], anymem))
5069 break;
5070 gas_assert (op < i.operands);
5071 /* Check size of the memory operand. */
5072 if ((t->opcode_modifier.vecesize == 0
5073 && i.types[op].bitfield.dword)
5074 || (t->opcode_modifier.vecesize == 1
5075 && i.types[op].bitfield.qword))
5076 {
5077 i.error = broadcast_needed;
5078 return 1;
5079 }
5080 }
5081
5082 /* Check if requested masking is supported. */
5083 if (i.mask
5084 && (!t->opcode_modifier.masking
5085 || (i.mask->zeroing
5086 && t->opcode_modifier.masking == MERGING_MASKING)))
5087 {
5088 i.error = unsupported_masking;
5089 return 1;
5090 }
5091
5092 /* Check if masking is applied to dest operand. */
5093 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5094 {
5095 i.error = mask_not_on_destination;
5096 return 1;
5097 }
5098
5099 /* Check RC/SAE. */
5100 if (i.rounding)
5101 {
5102 if ((i.rounding->type != saeonly
5103 && !t->opcode_modifier.staticrounding)
5104 || (i.rounding->type == saeonly
5105 && (t->opcode_modifier.staticrounding
5106 || !t->opcode_modifier.sae)))
5107 {
5108 i.error = unsupported_rc_sae;
5109 return 1;
5110 }
5111 /* If the instruction has several immediate operands and one of
5112 them is rounding, the rounding operand should be the last
5113 immediate operand. */
5114 if (i.imm_operands > 1
5115 && i.rounding->operand != (int) (i.imm_operands - 1))
5116 {
5117 i.error = rc_sae_operand_not_last_imm;
5118 return 1;
5119 }
5120 }
5121
5122 /* Check vector Disp8 operand. */
5123 if (t->opcode_modifier.disp8memshift
5124 && i.disp_encoding != disp_encoding_32bit)
5125 {
5126 if (i.broadcast)
5127 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5128 else
5129 i.memshift = t->opcode_modifier.disp8memshift;
5130
5131 for (op = 0; op < i.operands; op++)
5132 if (operand_type_check (i.types[op], disp)
5133 && i.op[op].disps->X_op == O_constant)
5134 {
5135 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5136 {
5137 i.types[op].bitfield.disp8 = 1;
5138 return 0;
5139 }
5140 i.types[op].bitfield.disp8 = 0;
5141 }
5142 }
5143
5144 i.memshift = 0;
5145
5146 return 0;
5147 }
5148
5149 /* Check if operands are valid for the instruction. Update VEX
5150 operand types. */
5151
5152 static int
5153 VEX_check_operands (const insn_template *t)
5154 {
5155 if (i.vec_encoding == vex_encoding_evex)
5156 {
5157 /* This instruction must be encoded with EVEX prefix. */
5158 if (!t->opcode_modifier.evex)
5159 {
5160 i.error = unsupported;
5161 return 1;
5162 }
5163 return 0;
5164 }
5165
5166 if (!t->opcode_modifier.vex)
5167 {
5168 /* This instruction template doesn't have VEX prefix. */
5169 if (i.vec_encoding != vex_encoding_default)
5170 {
5171 i.error = unsupported;
5172 return 1;
5173 }
5174 return 0;
5175 }
5176
5177 /* Only check VEX_Imm4, which must be the first operand. */
5178 if (t->operand_types[0].bitfield.vec_imm4)
5179 {
5180 if (i.op[0].imms->X_op != O_constant
5181 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5182 {
5183 i.error = bad_imm4;
5184 return 1;
5185 }
5186
5187 /* Turn off Imm8 so that update_imm won't complain. */
5188 i.types[0] = vec_imm4;
5189 }
5190
5191 return 0;
5192 }
5193
5194 static const insn_template *
5195 match_template (char mnem_suffix)
5196 {
5197 /* Points to template once we've found it. */
5198 const insn_template *t;
5199 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5200 i386_operand_type overlap4;
5201 unsigned int found_reverse_match;
5202 i386_opcode_modifier suffix_check, mnemsuf_check;
5203 i386_operand_type operand_types [MAX_OPERANDS];
5204 int addr_prefix_disp;
5205 unsigned int j;
5206 unsigned int found_cpu_match;
5207 unsigned int check_register;
5208 enum i386_error specific_error = 0;
5209
5210 #if MAX_OPERANDS != 5
5211 # error "MAX_OPERANDS must be 5."
5212 #endif
5213
5214 found_reverse_match = 0;
5215 addr_prefix_disp = -1;
5216
5217 memset (&suffix_check, 0, sizeof (suffix_check));
5218 if (i.suffix == BYTE_MNEM_SUFFIX)
5219 suffix_check.no_bsuf = 1;
5220 else if (i.suffix == WORD_MNEM_SUFFIX)
5221 suffix_check.no_wsuf = 1;
5222 else if (i.suffix == SHORT_MNEM_SUFFIX)
5223 suffix_check.no_ssuf = 1;
5224 else if (i.suffix == LONG_MNEM_SUFFIX)
5225 suffix_check.no_lsuf = 1;
5226 else if (i.suffix == QWORD_MNEM_SUFFIX)
5227 suffix_check.no_qsuf = 1;
5228 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5229 suffix_check.no_ldsuf = 1;
5230
5231 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5232 if (intel_syntax)
5233 {
5234 switch (mnem_suffix)
5235 {
5236 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5237 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5238 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5239 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5240 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5241 }
5242 }
5243
5244 /* Must have right number of operands. */
5245 i.error = number_of_operands_mismatch;
5246
5247 for (t = current_templates->start; t < current_templates->end; t++)
5248 {
5249 addr_prefix_disp = -1;
5250
5251 if (i.operands != t->operands)
5252 continue;
5253
5254 /* Check processor support. */
5255 i.error = unsupported;
5256 found_cpu_match = (cpu_flags_match (t)
5257 == CPU_FLAGS_PERFECT_MATCH);
5258 if (!found_cpu_match)
5259 continue;
5260
5261 /* Check old gcc support. */
5262 i.error = old_gcc_only;
5263 if (!old_gcc && t->opcode_modifier.oldgcc)
5264 continue;
5265
5266 /* Check AT&T mnemonic. */
5267 i.error = unsupported_with_intel_mnemonic;
5268 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5269 continue;
5270
5271 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5272 i.error = unsupported_syntax;
5273 if ((intel_syntax && t->opcode_modifier.attsyntax)
5274 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5275 || (intel64 && t->opcode_modifier.amd64)
5276 || (!intel64 && t->opcode_modifier.intel64))
5277 continue;
5278
5279 /* Check the suffix, except for some instructions in intel mode. */
5280 i.error = invalid_instruction_suffix;
5281 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5282 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5283 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5284 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5285 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5286 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5287 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5288 continue;
5289 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5290 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5291 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5292 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5293 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5294 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5295 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5296 continue;
5297
5298 if (!operand_size_match (t))
5299 continue;
5300
5301 for (j = 0; j < MAX_OPERANDS; j++)
5302 operand_types[j] = t->operand_types[j];
5303
5304 /* In general, don't allow 64-bit operands in 32-bit mode. */
5305 if (i.suffix == QWORD_MNEM_SUFFIX
5306 && flag_code != CODE_64BIT
5307 && (intel_syntax
5308 ? (!t->opcode_modifier.ignoresize
5309 && !intel_float_operand (t->name))
5310 : intel_float_operand (t->name) != 2)
5311 && ((!operand_types[0].bitfield.regmmx
5312 && !operand_types[0].bitfield.regsimd)
5313 || (!operand_types[t->operands > 1].bitfield.regmmx
5314 && !operand_types[t->operands > 1].bitfield.regsimd))
5315 && (t->base_opcode != 0x0fc7
5316 || t->extension_opcode != 1 /* cmpxchg8b */))
5317 continue;
5318
5319 /* In general, don't allow 32-bit operands on pre-386. */
5320 else if (i.suffix == LONG_MNEM_SUFFIX
5321 && !cpu_arch_flags.bitfield.cpui386
5322 && (intel_syntax
5323 ? (!t->opcode_modifier.ignoresize
5324 && !intel_float_operand (t->name))
5325 : intel_float_operand (t->name) != 2)
5326 && ((!operand_types[0].bitfield.regmmx
5327 && !operand_types[0].bitfield.regsimd)
5328 || (!operand_types[t->operands > 1].bitfield.regmmx
5329 && !operand_types[t->operands > 1].bitfield.regsimd)))
5330 continue;
5331
5332 /* Do not verify operands when there are none. */
5333 else
5334 {
5335 if (!t->operands)
5336 /* We've found a match; break out of loop. */
5337 break;
5338 }
5339
5340 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5341 into Disp32/Disp16/Disp32 operand. */
5342 if (i.prefix[ADDR_PREFIX] != 0)
5343 {
5344 /* There should be only one Disp operand. */
5345 switch (flag_code)
5346 {
5347 case CODE_16BIT:
5348 for (j = 0; j < MAX_OPERANDS; j++)
5349 {
5350 if (operand_types[j].bitfield.disp16)
5351 {
5352 addr_prefix_disp = j;
5353 operand_types[j].bitfield.disp32 = 1;
5354 operand_types[j].bitfield.disp16 = 0;
5355 break;
5356 }
5357 }
5358 break;
5359 case CODE_32BIT:
5360 for (j = 0; j < MAX_OPERANDS; j++)
5361 {
5362 if (operand_types[j].bitfield.disp32)
5363 {
5364 addr_prefix_disp = j;
5365 operand_types[j].bitfield.disp32 = 0;
5366 operand_types[j].bitfield.disp16 = 1;
5367 break;
5368 }
5369 }
5370 break;
5371 case CODE_64BIT:
5372 for (j = 0; j < MAX_OPERANDS; j++)
5373 {
5374 if (operand_types[j].bitfield.disp64)
5375 {
5376 addr_prefix_disp = j;
5377 operand_types[j].bitfield.disp64 = 0;
5378 operand_types[j].bitfield.disp32 = 1;
5379 break;
5380 }
5381 }
5382 break;
5383 }
5384 }
5385
5386 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5387 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5388 continue;
5389
5390 /* We check register size if needed. */
5391 check_register = t->opcode_modifier.checkregsize;
5392 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5393 switch (t->operands)
5394 {
5395 case 1:
5396 if (!operand_type_match (overlap0, i.types[0]))
5397 continue;
5398 break;
5399 case 2:
5400 /* xchg %eax, %eax is a special case. It is an alias for nop
5401 only in 32bit mode and we can use opcode 0x90. In 64bit
5402 mode, we can't use 0x90 for xchg %eax, %eax since it should
5403 zero-extend %eax to %rax. */
5404 if (flag_code == CODE_64BIT
5405 && t->base_opcode == 0x90
5406 && operand_type_equal (&i.types [0], &acc32)
5407 && operand_type_equal (&i.types [1], &acc32))
5408 continue;
5409 /* If we want store form, we reverse direction of operands. */
5410 if (i.dir_encoding == dir_encoding_store
5411 && t->opcode_modifier.d)
5412 goto check_reverse;
5413 /* Fall through. */
5414
5415 case 3:
5416 /* If we want store form, we skip the current load. */
5417 if (i.dir_encoding == dir_encoding_store
5418 && i.mem_operands == 0
5419 && t->opcode_modifier.load)
5420 continue;
5421 /* Fall through. */
5422 case 4:
5423 case 5:
5424 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5425 if (!operand_type_match (overlap0, i.types[0])
5426 || !operand_type_match (overlap1, i.types[1])
5427 || (check_register
5428 && !operand_type_register_match (i.types[0],
5429 operand_types[0],
5430 i.types[1],
5431 operand_types[1])))
5432 {
5433 /* Check if other direction is valid ... */
5434 if (!t->opcode_modifier.d)
5435 continue;
5436
5437 check_reverse:
5438 /* Try reversing direction of operands. */
5439 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5440 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5441 if (!operand_type_match (overlap0, i.types[0])
5442 || !operand_type_match (overlap1, i.types[1])
5443 || (check_register
5444 && !operand_type_register_match (i.types[0],
5445 operand_types[1],
5446 i.types[1],
5447 operand_types[0])))
5448 {
5449 /* Does not match either direction. */
5450 continue;
5451 }
5452 /* found_reverse_match holds which of D or FloatR
5453 we've found. */
5454 if (!t->opcode_modifier.d)
5455 found_reverse_match = 0;
5456 else if (operand_types[0].bitfield.tbyte)
5457 found_reverse_match = Opcode_FloatD;
5458 else
5459 found_reverse_match = Opcode_D;
5460 if (t->opcode_modifier.floatr)
5461 found_reverse_match |= Opcode_FloatR;
5462 }
5463 else
5464 {
5465 /* Found a forward 2 operand match here. */
5466 switch (t->operands)
5467 {
5468 case 5:
5469 overlap4 = operand_type_and (i.types[4],
5470 operand_types[4]);
5471 /* Fall through. */
5472 case 4:
5473 overlap3 = operand_type_and (i.types[3],
5474 operand_types[3]);
5475 /* Fall through. */
5476 case 3:
5477 overlap2 = operand_type_and (i.types[2],
5478 operand_types[2]);
5479 break;
5480 }
5481
5482 switch (t->operands)
5483 {
5484 case 5:
5485 if (!operand_type_match (overlap4, i.types[4])
5486 || !operand_type_register_match (i.types[3],
5487 operand_types[3],
5488 i.types[4],
5489 operand_types[4]))
5490 continue;
5491 /* Fall through. */
5492 case 4:
5493 if (!operand_type_match (overlap3, i.types[3])
5494 || (check_register
5495 && !operand_type_register_match (i.types[2],
5496 operand_types[2],
5497 i.types[3],
5498 operand_types[3])))
5499 continue;
5500 /* Fall through. */
5501 case 3:
5502 /* Here we make use of the fact that there are no
5503 reverse match 3 operand instructions, and all 3
5504 operand instructions only need to be checked for
5505 register consistency between operands 2 and 3. */
5506 if (!operand_type_match (overlap2, i.types[2])
5507 || (check_register
5508 && !operand_type_register_match (i.types[1],
5509 operand_types[1],
5510 i.types[2],
5511 operand_types[2])))
5512 continue;
5513 break;
5514 }
5515 }
5516 /* Found either forward/reverse 2, 3 or 4 operand match here:
5517 slip through to break. */
5518 }
5519 if (!found_cpu_match)
5520 {
5521 found_reverse_match = 0;
5522 continue;
5523 }
5524
5525 /* Check if vector and VEX operands are valid. */
5526 if (check_VecOperands (t) || VEX_check_operands (t))
5527 {
5528 specific_error = i.error;
5529 continue;
5530 }
5531
5532 /* We've found a match; break out of loop. */
5533 break;
5534 }
5535
5536 if (t == current_templates->end)
5537 {
5538 /* We found no match. */
5539 const char *err_msg;
5540 switch (specific_error ? specific_error : i.error)
5541 {
5542 default:
5543 abort ();
5544 case operand_size_mismatch:
5545 err_msg = _("operand size mismatch");
5546 break;
5547 case operand_type_mismatch:
5548 err_msg = _("operand type mismatch");
5549 break;
5550 case register_type_mismatch:
5551 err_msg = _("register type mismatch");
5552 break;
5553 case number_of_operands_mismatch:
5554 err_msg = _("number of operands mismatch");
5555 break;
5556 case invalid_instruction_suffix:
5557 err_msg = _("invalid instruction suffix");
5558 break;
5559 case bad_imm4:
5560 err_msg = _("constant doesn't fit in 4 bits");
5561 break;
5562 case old_gcc_only:
5563 err_msg = _("only supported with old gcc");
5564 break;
5565 case unsupported_with_intel_mnemonic:
5566 err_msg = _("unsupported with Intel mnemonic");
5567 break;
5568 case unsupported_syntax:
5569 err_msg = _("unsupported syntax");
5570 break;
5571 case unsupported:
5572 as_bad (_("unsupported instruction `%s'"),
5573 current_templates->start->name);
5574 return NULL;
5575 case invalid_vsib_address:
5576 err_msg = _("invalid VSIB address");
5577 break;
5578 case invalid_vector_register_set:
5579 err_msg = _("mask, index, and destination registers must be distinct");
5580 break;
5581 case unsupported_vector_index_register:
5582 err_msg = _("unsupported vector index register");
5583 break;
5584 case unsupported_broadcast:
5585 err_msg = _("unsupported broadcast");
5586 break;
5587 case broadcast_not_on_src_operand:
5588 err_msg = _("broadcast not on source memory operand");
5589 break;
5590 case broadcast_needed:
5591 err_msg = _("broadcast is needed for operand of such type");
5592 break;
5593 case unsupported_masking:
5594 err_msg = _("unsupported masking");
5595 break;
5596 case mask_not_on_destination:
5597 err_msg = _("mask not on destination operand");
5598 break;
5599 case no_default_mask:
5600 err_msg = _("default mask isn't allowed");
5601 break;
5602 case unsupported_rc_sae:
5603 err_msg = _("unsupported static rounding/sae");
5604 break;
5605 case rc_sae_operand_not_last_imm:
5606 if (intel_syntax)
5607 err_msg = _("RC/SAE operand must precede immediate operands");
5608 else
5609 err_msg = _("RC/SAE operand must follow immediate operands");
5610 break;
5611 case invalid_register_operand:
5612 err_msg = _("invalid register operand");
5613 break;
5614 }
5615 as_bad (_("%s for `%s'"), err_msg,
5616 current_templates->start->name);
5617 return NULL;
5618 }
5619
5620 if (!quiet_warnings)
5621 {
5622 if (!intel_syntax
5623 && (i.types[0].bitfield.jumpabsolute
5624 != operand_types[0].bitfield.jumpabsolute))
5625 {
5626 as_warn (_("indirect %s without `*'"), t->name);
5627 }
5628
5629 if (t->opcode_modifier.isprefix
5630 && t->opcode_modifier.ignoresize)
5631 {
5632 /* Warn them that a data or address size prefix doesn't
5633 affect assembly of the next line of code. */
5634 as_warn (_("stand-alone `%s' prefix"), t->name);
5635 }
5636 }
5637
5638 /* Copy the template we found. */
5639 i.tm = *t;
5640
5641 if (addr_prefix_disp != -1)
5642 i.tm.operand_types[addr_prefix_disp]
5643 = operand_types[addr_prefix_disp];
5644
5645 if (found_reverse_match)
5646 {
5647 /* If we found a reverse match we must alter the opcode
5648 direction bit. found_reverse_match holds bits to change
5649 (different for int & float insns). */
5650
5651 i.tm.base_opcode ^= found_reverse_match;
5652
5653 i.tm.operand_types[0] = operand_types[1];
5654 i.tm.operand_types[1] = operand_types[0];
5655 }
5656
5657 return t;
5658 }
5659
5660 static int
5661 check_string (void)
5662 {
5663 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5664 if (i.tm.operand_types[mem_op].bitfield.esseg)
5665 {
5666 if (i.seg[0] != NULL && i.seg[0] != &es)
5667 {
5668 as_bad (_("`%s' operand %d must use `%ses' segment"),
5669 i.tm.name,
5670 mem_op + 1,
5671 register_prefix);
5672 return 0;
5673 }
5674 /* There's only ever one segment override allowed per instruction.
5675 This instruction possibly has a legal segment override on the
5676 second operand, so copy the segment to where non-string
5677 instructions store it, allowing common code. */
5678 i.seg[0] = i.seg[1];
5679 }
5680 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5681 {
5682 if (i.seg[1] != NULL && i.seg[1] != &es)
5683 {
5684 as_bad (_("`%s' operand %d must use `%ses' segment"),
5685 i.tm.name,
5686 mem_op + 2,
5687 register_prefix);
5688 return 0;
5689 }
5690 }
5691 return 1;
5692 }
5693
5694 static int
5695 process_suffix (void)
5696 {
5697 /* If matched instruction specifies an explicit instruction mnemonic
5698 suffix, use it. */
5699 if (i.tm.opcode_modifier.size16)
5700 i.suffix = WORD_MNEM_SUFFIX;
5701 else if (i.tm.opcode_modifier.size32)
5702 i.suffix = LONG_MNEM_SUFFIX;
5703 else if (i.tm.opcode_modifier.size64)
5704 i.suffix = QWORD_MNEM_SUFFIX;
5705 else if (i.reg_operands)
5706 {
5707 /* If there's no instruction mnemonic suffix we try to invent one
5708 based on register operands. */
5709 if (!i.suffix)
5710 {
5711 /* We take i.suffix from the last register operand specified,
5712 Destination register type is more significant than source
5713 register type. crc32 in SSE4.2 prefers source register
5714 type. */
5715 if (i.tm.base_opcode == 0xf20f38f1)
5716 {
5717 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5718 i.suffix = WORD_MNEM_SUFFIX;
5719 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5720 i.suffix = LONG_MNEM_SUFFIX;
5721 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5722 i.suffix = QWORD_MNEM_SUFFIX;
5723 }
5724 else if (i.tm.base_opcode == 0xf20f38f0)
5725 {
5726 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5727 i.suffix = BYTE_MNEM_SUFFIX;
5728 }
5729
5730 if (!i.suffix)
5731 {
5732 int op;
5733
5734 if (i.tm.base_opcode == 0xf20f38f1
5735 || i.tm.base_opcode == 0xf20f38f0)
5736 {
5737 /* We have to know the operand size for crc32. */
5738 as_bad (_("ambiguous memory operand size for `%s`"),
5739 i.tm.name);
5740 return 0;
5741 }
5742
5743 for (op = i.operands; --op >= 0;)
5744 if (!i.tm.operand_types[op].bitfield.inoutportreg
5745 && !i.tm.operand_types[op].bitfield.shiftcount)
5746 {
5747 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5748 {
5749 i.suffix = BYTE_MNEM_SUFFIX;
5750 break;
5751 }
5752 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5753 {
5754 i.suffix = WORD_MNEM_SUFFIX;
5755 break;
5756 }
5757 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5758 {
5759 i.suffix = LONG_MNEM_SUFFIX;
5760 break;
5761 }
5762 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5763 {
5764 i.suffix = QWORD_MNEM_SUFFIX;
5765 break;
5766 }
5767 }
5768 }
5769 }
5770 else if (i.suffix == BYTE_MNEM_SUFFIX)
5771 {
5772 if (intel_syntax
5773 && i.tm.opcode_modifier.ignoresize
5774 && i.tm.opcode_modifier.no_bsuf)
5775 i.suffix = 0;
5776 else if (!check_byte_reg ())
5777 return 0;
5778 }
5779 else if (i.suffix == LONG_MNEM_SUFFIX)
5780 {
5781 if (intel_syntax
5782 && i.tm.opcode_modifier.ignoresize
5783 && i.tm.opcode_modifier.no_lsuf)
5784 i.suffix = 0;
5785 else if (!check_long_reg ())
5786 return 0;
5787 }
5788 else if (i.suffix == QWORD_MNEM_SUFFIX)
5789 {
5790 if (intel_syntax
5791 && i.tm.opcode_modifier.ignoresize
5792 && i.tm.opcode_modifier.no_qsuf)
5793 i.suffix = 0;
5794 else if (!check_qword_reg ())
5795 return 0;
5796 }
5797 else if (i.suffix == WORD_MNEM_SUFFIX)
5798 {
5799 if (intel_syntax
5800 && i.tm.opcode_modifier.ignoresize
5801 && i.tm.opcode_modifier.no_wsuf)
5802 i.suffix = 0;
5803 else if (!check_word_reg ())
5804 return 0;
5805 }
5806 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5807 || i.suffix == YMMWORD_MNEM_SUFFIX
5808 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5809 {
5810 /* Skip if the instruction has x/y/z suffix. match_template
5811 should check if it is a valid suffix. */
5812 }
5813 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5814 /* Do nothing if the instruction is going to ignore the prefix. */
5815 ;
5816 else
5817 abort ();
5818 }
5819 else if (i.tm.opcode_modifier.defaultsize
5820 && !i.suffix
5821 /* exclude fldenv/frstor/fsave/fstenv */
5822 && i.tm.opcode_modifier.no_ssuf)
5823 {
5824 i.suffix = stackop_size;
5825 }
5826 else if (intel_syntax
5827 && !i.suffix
5828 && (i.tm.operand_types[0].bitfield.jumpabsolute
5829 || i.tm.opcode_modifier.jumpbyte
5830 || i.tm.opcode_modifier.jumpintersegment
5831 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5832 && i.tm.extension_opcode <= 3)))
5833 {
5834 switch (flag_code)
5835 {
5836 case CODE_64BIT:
5837 if (!i.tm.opcode_modifier.no_qsuf)
5838 {
5839 i.suffix = QWORD_MNEM_SUFFIX;
5840 break;
5841 }
5842 /* Fall through. */
5843 case CODE_32BIT:
5844 if (!i.tm.opcode_modifier.no_lsuf)
5845 i.suffix = LONG_MNEM_SUFFIX;
5846 break;
5847 case CODE_16BIT:
5848 if (!i.tm.opcode_modifier.no_wsuf)
5849 i.suffix = WORD_MNEM_SUFFIX;
5850 break;
5851 }
5852 }
5853
5854 if (!i.suffix)
5855 {
5856 if (!intel_syntax)
5857 {
5858 if (i.tm.opcode_modifier.w)
5859 {
5860 as_bad (_("no instruction mnemonic suffix given and "
5861 "no register operands; can't size instruction"));
5862 return 0;
5863 }
5864 }
5865 else
5866 {
5867 unsigned int suffixes;
5868
5869 suffixes = !i.tm.opcode_modifier.no_bsuf;
5870 if (!i.tm.opcode_modifier.no_wsuf)
5871 suffixes |= 1 << 1;
5872 if (!i.tm.opcode_modifier.no_lsuf)
5873 suffixes |= 1 << 2;
5874 if (!i.tm.opcode_modifier.no_ldsuf)
5875 suffixes |= 1 << 3;
5876 if (!i.tm.opcode_modifier.no_ssuf)
5877 suffixes |= 1 << 4;
5878 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5879 suffixes |= 1 << 5;
5880
5881 /* There are more than suffix matches. */
5882 if (i.tm.opcode_modifier.w
5883 || ((suffixes & (suffixes - 1))
5884 && !i.tm.opcode_modifier.defaultsize
5885 && !i.tm.opcode_modifier.ignoresize))
5886 {
5887 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5888 return 0;
5889 }
5890 }
5891 }
5892
5893 /* Change the opcode based on the operand size given by i.suffix;
5894 We don't need to change things for byte insns. */
5895
5896 if (i.suffix
5897 && i.suffix != BYTE_MNEM_SUFFIX
5898 && i.suffix != XMMWORD_MNEM_SUFFIX
5899 && i.suffix != YMMWORD_MNEM_SUFFIX
5900 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5901 {
5902 /* It's not a byte, select word/dword operation. */
5903 if (i.tm.opcode_modifier.w)
5904 {
5905 if (i.tm.opcode_modifier.shortform)
5906 i.tm.base_opcode |= 8;
5907 else
5908 i.tm.base_opcode |= 1;
5909 }
5910
5911 /* Now select between word & dword operations via the operand
5912 size prefix, except for instructions that will ignore this
5913 prefix anyway. */
5914 if (i.tm.opcode_modifier.addrprefixop0)
5915 {
5916 /* The address size override prefix changes the size of the
5917 first operand. */
5918 if ((flag_code == CODE_32BIT
5919 && i.op->regs[0].reg_type.bitfield.word)
5920 || (flag_code != CODE_32BIT
5921 && i.op->regs[0].reg_type.bitfield.dword))
5922 if (!add_prefix (ADDR_PREFIX_OPCODE))
5923 return 0;
5924 }
5925 else if (i.suffix != QWORD_MNEM_SUFFIX
5926 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5927 && !i.tm.opcode_modifier.ignoresize
5928 && !i.tm.opcode_modifier.floatmf
5929 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5930 || (flag_code == CODE_64BIT
5931 && i.tm.opcode_modifier.jumpbyte)))
5932 {
5933 unsigned int prefix = DATA_PREFIX_OPCODE;
5934
5935 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5936 prefix = ADDR_PREFIX_OPCODE;
5937
5938 if (!add_prefix (prefix))
5939 return 0;
5940 }
5941
5942 /* Set mode64 for an operand. */
5943 if (i.suffix == QWORD_MNEM_SUFFIX
5944 && flag_code == CODE_64BIT
5945 && !i.tm.opcode_modifier.norex64)
5946 {
5947 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5948 need rex64. cmpxchg8b is also a special case. */
5949 if (! (i.operands == 2
5950 && i.tm.base_opcode == 0x90
5951 && i.tm.extension_opcode == None
5952 && operand_type_equal (&i.types [0], &acc64)
5953 && operand_type_equal (&i.types [1], &acc64))
5954 && ! (i.operands == 1
5955 && i.tm.base_opcode == 0xfc7
5956 && i.tm.extension_opcode == 1
5957 && !operand_type_check (i.types [0], reg)
5958 && operand_type_check (i.types [0], anymem)))
5959 i.rex |= REX_W;
5960 }
5961
5962 /* Size floating point instruction. */
5963 if (i.suffix == LONG_MNEM_SUFFIX)
5964 if (i.tm.opcode_modifier.floatmf)
5965 i.tm.base_opcode ^= 4;
5966 }
5967
5968 return 1;
5969 }
5970
5971 static int
5972 check_byte_reg (void)
5973 {
5974 int op;
5975
5976 for (op = i.operands; --op >= 0;)
5977 {
5978 /* Skip non-register operands. */
5979 if (!i.types[op].bitfield.reg)
5980 continue;
5981
5982 /* If this is an eight bit register, it's OK. If it's the 16 or
5983 32 bit version of an eight bit register, we will just use the
5984 low portion, and that's OK too. */
5985 if (i.types[op].bitfield.byte)
5986 continue;
5987
5988 /* I/O port address operands are OK too. */
5989 if (i.tm.operand_types[op].bitfield.inoutportreg)
5990 continue;
5991
5992 /* crc32 doesn't generate this warning. */
5993 if (i.tm.base_opcode == 0xf20f38f0)
5994 continue;
5995
5996 if ((i.types[op].bitfield.word
5997 || i.types[op].bitfield.dword
5998 || i.types[op].bitfield.qword)
5999 && i.op[op].regs->reg_num < 4
6000 /* Prohibit these changes in 64bit mode, since the lowering
6001 would be more complicated. */
6002 && flag_code != CODE_64BIT)
6003 {
6004 #if REGISTER_WARNINGS
6005 if (!quiet_warnings)
6006 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6007 register_prefix,
6008 (i.op[op].regs + (i.types[op].bitfield.word
6009 ? REGNAM_AL - REGNAM_AX
6010 : REGNAM_AL - REGNAM_EAX))->reg_name,
6011 register_prefix,
6012 i.op[op].regs->reg_name,
6013 i.suffix);
6014 #endif
6015 continue;
6016 }
6017 /* Any other register is bad. */
6018 if (i.types[op].bitfield.reg
6019 || i.types[op].bitfield.regmmx
6020 || i.types[op].bitfield.regsimd
6021 || i.types[op].bitfield.sreg2
6022 || i.types[op].bitfield.sreg3
6023 || i.types[op].bitfield.control
6024 || i.types[op].bitfield.debug
6025 || i.types[op].bitfield.test)
6026 {
6027 as_bad (_("`%s%s' not allowed with `%s%c'"),
6028 register_prefix,
6029 i.op[op].regs->reg_name,
6030 i.tm.name,
6031 i.suffix);
6032 return 0;
6033 }
6034 }
6035 return 1;
6036 }
6037
6038 static int
6039 check_long_reg (void)
6040 {
6041 int op;
6042
6043 for (op = i.operands; --op >= 0;)
6044 /* Skip non-register operands. */
6045 if (!i.types[op].bitfield.reg)
6046 continue;
6047 /* Reject eight bit registers, except where the template requires
6048 them. (eg. movzb) */
6049 else if (i.types[op].bitfield.byte
6050 && (i.tm.operand_types[op].bitfield.reg
6051 || i.tm.operand_types[op].bitfield.acc)
6052 && (i.tm.operand_types[op].bitfield.word
6053 || i.tm.operand_types[op].bitfield.dword))
6054 {
6055 as_bad (_("`%s%s' not allowed with `%s%c'"),
6056 register_prefix,
6057 i.op[op].regs->reg_name,
6058 i.tm.name,
6059 i.suffix);
6060 return 0;
6061 }
6062 /* Warn if the e prefix on a general reg is missing. */
6063 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6064 && i.types[op].bitfield.word
6065 && (i.tm.operand_types[op].bitfield.reg
6066 || i.tm.operand_types[op].bitfield.acc)
6067 && i.tm.operand_types[op].bitfield.dword)
6068 {
6069 /* Prohibit these changes in the 64bit mode, since the
6070 lowering is more complicated. */
6071 if (flag_code == CODE_64BIT)
6072 {
6073 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6074 register_prefix, i.op[op].regs->reg_name,
6075 i.suffix);
6076 return 0;
6077 }
6078 #if REGISTER_WARNINGS
6079 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6080 register_prefix,
6081 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6082 register_prefix, i.op[op].regs->reg_name, i.suffix);
6083 #endif
6084 }
6085 /* Warn if the r prefix on a general reg is present. */
6086 else if (i.types[op].bitfield.qword
6087 && (i.tm.operand_types[op].bitfield.reg
6088 || i.tm.operand_types[op].bitfield.acc)
6089 && i.tm.operand_types[op].bitfield.dword)
6090 {
6091 if (intel_syntax
6092 && i.tm.opcode_modifier.toqword
6093 && !i.types[0].bitfield.regsimd)
6094 {
6095 /* Convert to QWORD. We want REX byte. */
6096 i.suffix = QWORD_MNEM_SUFFIX;
6097 }
6098 else
6099 {
6100 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6101 register_prefix, i.op[op].regs->reg_name,
6102 i.suffix);
6103 return 0;
6104 }
6105 }
6106 return 1;
6107 }
6108
6109 static int
6110 check_qword_reg (void)
6111 {
6112 int op;
6113
6114 for (op = i.operands; --op >= 0; )
6115 /* Skip non-register operands. */
6116 if (!i.types[op].bitfield.reg)
6117 continue;
6118 /* Reject eight bit registers, except where the template requires
6119 them. (eg. movzb) */
6120 else if (i.types[op].bitfield.byte
6121 && (i.tm.operand_types[op].bitfield.reg
6122 || i.tm.operand_types[op].bitfield.acc)
6123 && (i.tm.operand_types[op].bitfield.word
6124 || i.tm.operand_types[op].bitfield.dword))
6125 {
6126 as_bad (_("`%s%s' not allowed with `%s%c'"),
6127 register_prefix,
6128 i.op[op].regs->reg_name,
6129 i.tm.name,
6130 i.suffix);
6131 return 0;
6132 }
6133 /* Warn if the r prefix on a general reg is missing. */
6134 else if ((i.types[op].bitfield.word
6135 || i.types[op].bitfield.dword)
6136 && (i.tm.operand_types[op].bitfield.reg
6137 || i.tm.operand_types[op].bitfield.acc)
6138 && i.tm.operand_types[op].bitfield.qword)
6139 {
6140 /* Prohibit these changes in the 64bit mode, since the
6141 lowering is more complicated. */
6142 if (intel_syntax
6143 && i.tm.opcode_modifier.todword
6144 && !i.types[0].bitfield.regsimd)
6145 {
6146 /* Convert to DWORD. We don't want REX byte. */
6147 i.suffix = LONG_MNEM_SUFFIX;
6148 }
6149 else
6150 {
6151 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6152 register_prefix, i.op[op].regs->reg_name,
6153 i.suffix);
6154 return 0;
6155 }
6156 }
6157 return 1;
6158 }
6159
6160 static int
6161 check_word_reg (void)
6162 {
6163 int op;
6164 for (op = i.operands; --op >= 0;)
6165 /* Skip non-register operands. */
6166 if (!i.types[op].bitfield.reg)
6167 continue;
6168 /* Reject eight bit registers, except where the template requires
6169 them. (eg. movzb) */
6170 else if (i.types[op].bitfield.byte
6171 && (i.tm.operand_types[op].bitfield.reg
6172 || i.tm.operand_types[op].bitfield.acc)
6173 && (i.tm.operand_types[op].bitfield.word
6174 || i.tm.operand_types[op].bitfield.dword))
6175 {
6176 as_bad (_("`%s%s' not allowed with `%s%c'"),
6177 register_prefix,
6178 i.op[op].regs->reg_name,
6179 i.tm.name,
6180 i.suffix);
6181 return 0;
6182 }
6183 /* Warn if the e or r prefix on a general reg is present. */
6184 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6185 && (i.types[op].bitfield.dword
6186 || i.types[op].bitfield.qword)
6187 && (i.tm.operand_types[op].bitfield.reg
6188 || i.tm.operand_types[op].bitfield.acc)
6189 && i.tm.operand_types[op].bitfield.word)
6190 {
6191 /* Prohibit these changes in the 64bit mode, since the
6192 lowering is more complicated. */
6193 if (flag_code == CODE_64BIT)
6194 {
6195 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6196 register_prefix, i.op[op].regs->reg_name,
6197 i.suffix);
6198 return 0;
6199 }
6200 #if REGISTER_WARNINGS
6201 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6202 register_prefix,
6203 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6204 register_prefix, i.op[op].regs->reg_name, i.suffix);
6205 #endif
6206 }
6207 return 1;
6208 }
6209
6210 static int
6211 update_imm (unsigned int j)
6212 {
6213 i386_operand_type overlap = i.types[j];
6214 if ((overlap.bitfield.imm8
6215 || overlap.bitfield.imm8s
6216 || overlap.bitfield.imm16
6217 || overlap.bitfield.imm32
6218 || overlap.bitfield.imm32s
6219 || overlap.bitfield.imm64)
6220 && !operand_type_equal (&overlap, &imm8)
6221 && !operand_type_equal (&overlap, &imm8s)
6222 && !operand_type_equal (&overlap, &imm16)
6223 && !operand_type_equal (&overlap, &imm32)
6224 && !operand_type_equal (&overlap, &imm32s)
6225 && !operand_type_equal (&overlap, &imm64))
6226 {
6227 if (i.suffix)
6228 {
6229 i386_operand_type temp;
6230
6231 operand_type_set (&temp, 0);
6232 if (i.suffix == BYTE_MNEM_SUFFIX)
6233 {
6234 temp.bitfield.imm8 = overlap.bitfield.imm8;
6235 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6236 }
6237 else if (i.suffix == WORD_MNEM_SUFFIX)
6238 temp.bitfield.imm16 = overlap.bitfield.imm16;
6239 else if (i.suffix == QWORD_MNEM_SUFFIX)
6240 {
6241 temp.bitfield.imm64 = overlap.bitfield.imm64;
6242 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6243 }
6244 else
6245 temp.bitfield.imm32 = overlap.bitfield.imm32;
6246 overlap = temp;
6247 }
6248 else if (operand_type_equal (&overlap, &imm16_32_32s)
6249 || operand_type_equal (&overlap, &imm16_32)
6250 || operand_type_equal (&overlap, &imm16_32s))
6251 {
6252 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6253 overlap = imm16;
6254 else
6255 overlap = imm32s;
6256 }
6257 if (!operand_type_equal (&overlap, &imm8)
6258 && !operand_type_equal (&overlap, &imm8s)
6259 && !operand_type_equal (&overlap, &imm16)
6260 && !operand_type_equal (&overlap, &imm32)
6261 && !operand_type_equal (&overlap, &imm32s)
6262 && !operand_type_equal (&overlap, &imm64))
6263 {
6264 as_bad (_("no instruction mnemonic suffix given; "
6265 "can't determine immediate size"));
6266 return 0;
6267 }
6268 }
6269 i.types[j] = overlap;
6270
6271 return 1;
6272 }
6273
6274 static int
6275 finalize_imm (void)
6276 {
6277 unsigned int j, n;
6278
6279 /* Update the first 2 immediate operands. */
6280 n = i.operands > 2 ? 2 : i.operands;
6281 if (n)
6282 {
6283 for (j = 0; j < n; j++)
6284 if (update_imm (j) == 0)
6285 return 0;
6286
6287 /* The 3rd operand can't be immediate operand. */
6288 gas_assert (operand_type_check (i.types[2], imm) == 0);
6289 }
6290
6291 return 1;
6292 }
6293
6294 static int
6295 process_operands (void)
6296 {
6297 /* Default segment register this instruction will use for memory
6298 accesses. 0 means unknown. This is only for optimizing out
6299 unnecessary segment overrides. */
6300 const seg_entry *default_seg = 0;
6301
6302 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6303 {
6304 unsigned int dupl = i.operands;
6305 unsigned int dest = dupl - 1;
6306 unsigned int j;
6307
6308 /* The destination must be an xmm register. */
6309 gas_assert (i.reg_operands
6310 && MAX_OPERANDS > dupl
6311 && operand_type_equal (&i.types[dest], &regxmm));
6312
6313 if (i.tm.operand_types[0].bitfield.acc
6314 && i.tm.operand_types[0].bitfield.xmmword)
6315 {
6316 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6317 {
6318 /* Keep xmm0 for instructions with VEX prefix and 3
6319 sources. */
6320 i.tm.operand_types[0].bitfield.acc = 0;
6321 i.tm.operand_types[0].bitfield.regsimd = 1;
6322 goto duplicate;
6323 }
6324 else
6325 {
6326 /* We remove the first xmm0 and keep the number of
6327 operands unchanged, which in fact duplicates the
6328 destination. */
6329 for (j = 1; j < i.operands; j++)
6330 {
6331 i.op[j - 1] = i.op[j];
6332 i.types[j - 1] = i.types[j];
6333 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6334 }
6335 }
6336 }
6337 else if (i.tm.opcode_modifier.implicit1stxmm0)
6338 {
6339 gas_assert ((MAX_OPERANDS - 1) > dupl
6340 && (i.tm.opcode_modifier.vexsources
6341 == VEX3SOURCES));
6342
6343 /* Add the implicit xmm0 for instructions with VEX prefix
6344 and 3 sources. */
6345 for (j = i.operands; j > 0; j--)
6346 {
6347 i.op[j] = i.op[j - 1];
6348 i.types[j] = i.types[j - 1];
6349 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6350 }
6351 i.op[0].regs
6352 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6353 i.types[0] = regxmm;
6354 i.tm.operand_types[0] = regxmm;
6355
6356 i.operands += 2;
6357 i.reg_operands += 2;
6358 i.tm.operands += 2;
6359
6360 dupl++;
6361 dest++;
6362 i.op[dupl] = i.op[dest];
6363 i.types[dupl] = i.types[dest];
6364 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6365 }
6366 else
6367 {
6368 duplicate:
6369 i.operands++;
6370 i.reg_operands++;
6371 i.tm.operands++;
6372
6373 i.op[dupl] = i.op[dest];
6374 i.types[dupl] = i.types[dest];
6375 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6376 }
6377
6378 if (i.tm.opcode_modifier.immext)
6379 process_immext ();
6380 }
6381 else if (i.tm.operand_types[0].bitfield.acc
6382 && i.tm.operand_types[0].bitfield.xmmword)
6383 {
6384 unsigned int j;
6385
6386 for (j = 1; j < i.operands; j++)
6387 {
6388 i.op[j - 1] = i.op[j];
6389 i.types[j - 1] = i.types[j];
6390
6391 /* We need to adjust fields in i.tm since they are used by
6392 build_modrm_byte. */
6393 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6394 }
6395
6396 i.operands--;
6397 i.reg_operands--;
6398 i.tm.operands--;
6399 }
6400 else if (i.tm.opcode_modifier.implicitquadgroup)
6401 {
6402 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6403
6404 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6405 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6406 regnum = register_number (i.op[1].regs);
6407 first_reg_in_group = regnum & ~3;
6408 last_reg_in_group = first_reg_in_group + 3;
6409 if (regnum != first_reg_in_group)
6410 as_warn (_("source register `%s%s' implicitly denotes"
6411 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6412 register_prefix, i.op[1].regs->reg_name,
6413 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6414 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6415 i.tm.name);
6416 }
6417 else if (i.tm.opcode_modifier.regkludge)
6418 {
6419 /* The imul $imm, %reg instruction is converted into
6420 imul $imm, %reg, %reg, and the clr %reg instruction
6421 is converted into xor %reg, %reg. */
6422
6423 unsigned int first_reg_op;
6424
6425 if (operand_type_check (i.types[0], reg))
6426 first_reg_op = 0;
6427 else
6428 first_reg_op = 1;
6429 /* Pretend we saw the extra register operand. */
6430 gas_assert (i.reg_operands == 1
6431 && i.op[first_reg_op + 1].regs == 0);
6432 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6433 i.types[first_reg_op + 1] = i.types[first_reg_op];
6434 i.operands++;
6435 i.reg_operands++;
6436 }
6437
6438 if (i.tm.opcode_modifier.shortform)
6439 {
6440 if (i.types[0].bitfield.sreg2
6441 || i.types[0].bitfield.sreg3)
6442 {
6443 if (i.tm.base_opcode == POP_SEG_SHORT
6444 && i.op[0].regs->reg_num == 1)
6445 {
6446 as_bad (_("you can't `pop %scs'"), register_prefix);
6447 return 0;
6448 }
6449 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6450 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6451 i.rex |= REX_B;
6452 }
6453 else
6454 {
6455 /* The register or float register operand is in operand
6456 0 or 1. */
6457 unsigned int op;
6458
6459 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6460 || operand_type_check (i.types[0], reg))
6461 op = 0;
6462 else
6463 op = 1;
6464 /* Register goes in low 3 bits of opcode. */
6465 i.tm.base_opcode |= i.op[op].regs->reg_num;
6466 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6467 i.rex |= REX_B;
6468 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6469 {
6470 /* Warn about some common errors, but press on regardless.
6471 The first case can be generated by gcc (<= 2.8.1). */
6472 if (i.operands == 2)
6473 {
6474 /* Reversed arguments on faddp, fsubp, etc. */
6475 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6476 register_prefix, i.op[!intel_syntax].regs->reg_name,
6477 register_prefix, i.op[intel_syntax].regs->reg_name);
6478 }
6479 else
6480 {
6481 /* Extraneous `l' suffix on fp insn. */
6482 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6483 register_prefix, i.op[0].regs->reg_name);
6484 }
6485 }
6486 }
6487 }
6488 else if (i.tm.opcode_modifier.modrm)
6489 {
6490 /* The opcode is completed (modulo i.tm.extension_opcode which
6491 must be put into the modrm byte). Now, we make the modrm and
6492 index base bytes based on all the info we've collected. */
6493
6494 default_seg = build_modrm_byte ();
6495 }
6496 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6497 {
6498 default_seg = &ds;
6499 }
6500 else if (i.tm.opcode_modifier.isstring)
6501 {
6502 /* For the string instructions that allow a segment override
6503 on one of their operands, the default segment is ds. */
6504 default_seg = &ds;
6505 }
6506
6507 if (i.tm.base_opcode == 0x8d /* lea */
6508 && i.seg[0]
6509 && !quiet_warnings)
6510 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6511
6512 /* If a segment was explicitly specified, and the specified segment
6513 is not the default, use an opcode prefix to select it. If we
6514 never figured out what the default segment is, then default_seg
6515 will be zero at this point, and the specified segment prefix will
6516 always be used. */
6517 if ((i.seg[0]) && (i.seg[0] != default_seg))
6518 {
6519 if (!add_prefix (i.seg[0]->seg_prefix))
6520 return 0;
6521 }
6522 return 1;
6523 }
6524
6525 static const seg_entry *
6526 build_modrm_byte (void)
6527 {
6528 const seg_entry *default_seg = 0;
6529 unsigned int source, dest;
6530 int vex_3_sources;
6531
6532 /* The first operand of instructions with VEX prefix and 3 sources
6533 must be VEX_Imm4. */
6534 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6535 if (vex_3_sources)
6536 {
6537 unsigned int nds, reg_slot;
6538 expressionS *exp;
6539
6540 if (i.tm.opcode_modifier.veximmext
6541 && i.tm.opcode_modifier.immext)
6542 {
6543 dest = i.operands - 2;
6544 gas_assert (dest == 3);
6545 }
6546 else
6547 dest = i.operands - 1;
6548 nds = dest - 1;
6549
6550 /* There are 2 kinds of instructions:
6551 1. 5 operands: 4 register operands or 3 register operands
6552 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6553 VexW0 or VexW1. The destination must be either XMM, YMM or
6554 ZMM register.
6555 2. 4 operands: 4 register operands or 3 register operands
6556 plus 1 memory operand, VexXDS, and VexImmExt */
6557 gas_assert ((i.reg_operands == 4
6558 || (i.reg_operands == 3 && i.mem_operands == 1))
6559 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6560 && (i.tm.opcode_modifier.veximmext
6561 || (i.imm_operands == 1
6562 && i.types[0].bitfield.vec_imm4
6563 && (i.tm.opcode_modifier.vexw == VEXW0
6564 || i.tm.opcode_modifier.vexw == VEXW1)
6565 && i.tm.operand_types[dest].bitfield.regsimd)));
6566
6567 if (i.imm_operands == 0)
6568 {
6569 /* When there is no immediate operand, generate an 8bit
6570 immediate operand to encode the first operand. */
6571 exp = &im_expressions[i.imm_operands++];
6572 i.op[i.operands].imms = exp;
6573 i.types[i.operands] = imm8;
6574 i.operands++;
6575 /* If VexW1 is set, the first operand is the source and
6576 the second operand is encoded in the immediate operand. */
6577 if (i.tm.opcode_modifier.vexw == VEXW1)
6578 {
6579 source = 0;
6580 reg_slot = 1;
6581 }
6582 else
6583 {
6584 source = 1;
6585 reg_slot = 0;
6586 }
6587
6588 /* FMA swaps REG and NDS. */
6589 if (i.tm.cpu_flags.bitfield.cpufma)
6590 {
6591 unsigned int tmp;
6592 tmp = reg_slot;
6593 reg_slot = nds;
6594 nds = tmp;
6595 }
6596
6597 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6598 exp->X_op = O_constant;
6599 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6600 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6601 }
6602 else
6603 {
6604 unsigned int imm_slot;
6605
6606 if (i.tm.opcode_modifier.vexw == VEXW0)
6607 {
6608 /* If VexW0 is set, the third operand is the source and
6609 the second operand is encoded in the immediate
6610 operand. */
6611 source = 2;
6612 reg_slot = 1;
6613 }
6614 else
6615 {
6616 /* VexW1 is set, the second operand is the source and
6617 the third operand is encoded in the immediate
6618 operand. */
6619 source = 1;
6620 reg_slot = 2;
6621 }
6622
6623 if (i.tm.opcode_modifier.immext)
6624 {
6625 /* When ImmExt is set, the immediate byte is the last
6626 operand. */
6627 imm_slot = i.operands - 1;
6628 source--;
6629 reg_slot--;
6630 }
6631 else
6632 {
6633 imm_slot = 0;
6634
6635 /* Turn on Imm8 so that output_imm will generate it. */
6636 i.types[imm_slot].bitfield.imm8 = 1;
6637 }
6638
6639 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6640 i.op[imm_slot].imms->X_add_number
6641 |= register_number (i.op[reg_slot].regs) << 4;
6642 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6643 }
6644
6645 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6646 i.vex.register_specifier = i.op[nds].regs;
6647 }
6648 else
6649 source = dest = 0;
6650
6651 /* i.reg_operands MUST be the number of real register operands;
6652 implicit registers do not count. If there are 3 register
6653 operands, it must be a instruction with VexNDS. For a
6654 instruction with VexNDD, the destination register is encoded
6655 in VEX prefix. If there are 4 register operands, it must be
6656 a instruction with VEX prefix and 3 sources. */
6657 if (i.mem_operands == 0
6658 && ((i.reg_operands == 2
6659 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6660 || (i.reg_operands == 3
6661 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6662 || (i.reg_operands == 4 && vex_3_sources)))
6663 {
6664 switch (i.operands)
6665 {
6666 case 2:
6667 source = 0;
6668 break;
6669 case 3:
6670 /* When there are 3 operands, one of them may be immediate,
6671 which may be the first or the last operand. Otherwise,
6672 the first operand must be shift count register (cl) or it
6673 is an instruction with VexNDS. */
6674 gas_assert (i.imm_operands == 1
6675 || (i.imm_operands == 0
6676 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6677 || i.types[0].bitfield.shiftcount)));
6678 if (operand_type_check (i.types[0], imm)
6679 || i.types[0].bitfield.shiftcount)
6680 source = 1;
6681 else
6682 source = 0;
6683 break;
6684 case 4:
6685 /* When there are 4 operands, the first two must be 8bit
6686 immediate operands. The source operand will be the 3rd
6687 one.
6688
6689 For instructions with VexNDS, if the first operand
6690 an imm8, the source operand is the 2nd one. If the last
6691 operand is imm8, the source operand is the first one. */
6692 gas_assert ((i.imm_operands == 2
6693 && i.types[0].bitfield.imm8
6694 && i.types[1].bitfield.imm8)
6695 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6696 && i.imm_operands == 1
6697 && (i.types[0].bitfield.imm8
6698 || i.types[i.operands - 1].bitfield.imm8
6699 || i.rounding)));
6700 if (i.imm_operands == 2)
6701 source = 2;
6702 else
6703 {
6704 if (i.types[0].bitfield.imm8)
6705 source = 1;
6706 else
6707 source = 0;
6708 }
6709 break;
6710 case 5:
6711 if (i.tm.opcode_modifier.evex)
6712 {
6713 /* For EVEX instructions, when there are 5 operands, the
6714 first one must be immediate operand. If the second one
6715 is immediate operand, the source operand is the 3th
6716 one. If the last one is immediate operand, the source
6717 operand is the 2nd one. */
6718 gas_assert (i.imm_operands == 2
6719 && i.tm.opcode_modifier.sae
6720 && operand_type_check (i.types[0], imm));
6721 if (operand_type_check (i.types[1], imm))
6722 source = 2;
6723 else if (operand_type_check (i.types[4], imm))
6724 source = 1;
6725 else
6726 abort ();
6727 }
6728 break;
6729 default:
6730 abort ();
6731 }
6732
6733 if (!vex_3_sources)
6734 {
6735 dest = source + 1;
6736
6737 /* RC/SAE operand could be between DEST and SRC. That happens
6738 when one operand is GPR and the other one is XMM/YMM/ZMM
6739 register. */
6740 if (i.rounding && i.rounding->operand == (int) dest)
6741 dest++;
6742
6743 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6744 {
6745 /* For instructions with VexNDS, the register-only source
6746 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6747 register. It is encoded in VEX prefix. We need to
6748 clear RegMem bit before calling operand_type_equal. */
6749
6750 i386_operand_type op;
6751 unsigned int vvvv;
6752
6753 /* Check register-only source operand when two source
6754 operands are swapped. */
6755 if (!i.tm.operand_types[source].bitfield.baseindex
6756 && i.tm.operand_types[dest].bitfield.baseindex)
6757 {
6758 vvvv = source;
6759 source = dest;
6760 }
6761 else
6762 vvvv = dest;
6763
6764 op = i.tm.operand_types[vvvv];
6765 op.bitfield.regmem = 0;
6766 if ((dest + 1) >= i.operands
6767 || ((!op.bitfield.reg
6768 || (!op.bitfield.dword && !op.bitfield.qword))
6769 && !op.bitfield.regsimd
6770 && !operand_type_equal (&op, &regmask)))
6771 abort ();
6772 i.vex.register_specifier = i.op[vvvv].regs;
6773 dest++;
6774 }
6775 }
6776
6777 i.rm.mode = 3;
6778 /* One of the register operands will be encoded in the i.tm.reg
6779 field, the other in the combined i.tm.mode and i.tm.regmem
6780 fields. If no form of this instruction supports a memory
6781 destination operand, then we assume the source operand may
6782 sometimes be a memory operand and so we need to store the
6783 destination in the i.rm.reg field. */
6784 if (!i.tm.operand_types[dest].bitfield.regmem
6785 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6786 {
6787 i.rm.reg = i.op[dest].regs->reg_num;
6788 i.rm.regmem = i.op[source].regs->reg_num;
6789 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6790 i.rex |= REX_R;
6791 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6792 i.vrex |= REX_R;
6793 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6794 i.rex |= REX_B;
6795 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6796 i.vrex |= REX_B;
6797 }
6798 else
6799 {
6800 i.rm.reg = i.op[source].regs->reg_num;
6801 i.rm.regmem = i.op[dest].regs->reg_num;
6802 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6803 i.rex |= REX_B;
6804 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6805 i.vrex |= REX_B;
6806 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6807 i.rex |= REX_R;
6808 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6809 i.vrex |= REX_R;
6810 }
6811 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6812 {
6813 if (!i.types[0].bitfield.control
6814 && !i.types[1].bitfield.control)
6815 abort ();
6816 i.rex &= ~(REX_R | REX_B);
6817 add_prefix (LOCK_PREFIX_OPCODE);
6818 }
6819 }
6820 else
6821 { /* If it's not 2 reg operands... */
6822 unsigned int mem;
6823
6824 if (i.mem_operands)
6825 {
6826 unsigned int fake_zero_displacement = 0;
6827 unsigned int op;
6828
6829 for (op = 0; op < i.operands; op++)
6830 if (operand_type_check (i.types[op], anymem))
6831 break;
6832 gas_assert (op < i.operands);
6833
6834 if (i.tm.opcode_modifier.vecsib)
6835 {
6836 if (i.index_reg->reg_num == RegEiz
6837 || i.index_reg->reg_num == RegRiz)
6838 abort ();
6839
6840 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6841 if (!i.base_reg)
6842 {
6843 i.sib.base = NO_BASE_REGISTER;
6844 i.sib.scale = i.log2_scale_factor;
6845 i.types[op].bitfield.disp8 = 0;
6846 i.types[op].bitfield.disp16 = 0;
6847 i.types[op].bitfield.disp64 = 0;
6848 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6849 {
6850 /* Must be 32 bit */
6851 i.types[op].bitfield.disp32 = 1;
6852 i.types[op].bitfield.disp32s = 0;
6853 }
6854 else
6855 {
6856 i.types[op].bitfield.disp32 = 0;
6857 i.types[op].bitfield.disp32s = 1;
6858 }
6859 }
6860 i.sib.index = i.index_reg->reg_num;
6861 if ((i.index_reg->reg_flags & RegRex) != 0)
6862 i.rex |= REX_X;
6863 if ((i.index_reg->reg_flags & RegVRex) != 0)
6864 i.vrex |= REX_X;
6865 }
6866
6867 default_seg = &ds;
6868
6869 if (i.base_reg == 0)
6870 {
6871 i.rm.mode = 0;
6872 if (!i.disp_operands)
6873 fake_zero_displacement = 1;
6874 if (i.index_reg == 0)
6875 {
6876 i386_operand_type newdisp;
6877
6878 gas_assert (!i.tm.opcode_modifier.vecsib);
6879 /* Operand is just <disp> */
6880 if (flag_code == CODE_64BIT)
6881 {
6882 /* 64bit mode overwrites the 32bit absolute
6883 addressing by RIP relative addressing and
6884 absolute addressing is encoded by one of the
6885 redundant SIB forms. */
6886 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6887 i.sib.base = NO_BASE_REGISTER;
6888 i.sib.index = NO_INDEX_REGISTER;
6889 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6890 }
6891 else if ((flag_code == CODE_16BIT)
6892 ^ (i.prefix[ADDR_PREFIX] != 0))
6893 {
6894 i.rm.regmem = NO_BASE_REGISTER_16;
6895 newdisp = disp16;
6896 }
6897 else
6898 {
6899 i.rm.regmem = NO_BASE_REGISTER;
6900 newdisp = disp32;
6901 }
6902 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6903 i.types[op] = operand_type_or (i.types[op], newdisp);
6904 }
6905 else if (!i.tm.opcode_modifier.vecsib)
6906 {
6907 /* !i.base_reg && i.index_reg */
6908 if (i.index_reg->reg_num == RegEiz
6909 || i.index_reg->reg_num == RegRiz)
6910 i.sib.index = NO_INDEX_REGISTER;
6911 else
6912 i.sib.index = i.index_reg->reg_num;
6913 i.sib.base = NO_BASE_REGISTER;
6914 i.sib.scale = i.log2_scale_factor;
6915 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6916 i.types[op].bitfield.disp8 = 0;
6917 i.types[op].bitfield.disp16 = 0;
6918 i.types[op].bitfield.disp64 = 0;
6919 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6920 {
6921 /* Must be 32 bit */
6922 i.types[op].bitfield.disp32 = 1;
6923 i.types[op].bitfield.disp32s = 0;
6924 }
6925 else
6926 {
6927 i.types[op].bitfield.disp32 = 0;
6928 i.types[op].bitfield.disp32s = 1;
6929 }
6930 if ((i.index_reg->reg_flags & RegRex) != 0)
6931 i.rex |= REX_X;
6932 }
6933 }
6934 /* RIP addressing for 64bit mode. */
6935 else if (i.base_reg->reg_num == RegRip ||
6936 i.base_reg->reg_num == RegEip)
6937 {
6938 gas_assert (!i.tm.opcode_modifier.vecsib);
6939 i.rm.regmem = NO_BASE_REGISTER;
6940 i.types[op].bitfield.disp8 = 0;
6941 i.types[op].bitfield.disp16 = 0;
6942 i.types[op].bitfield.disp32 = 0;
6943 i.types[op].bitfield.disp32s = 1;
6944 i.types[op].bitfield.disp64 = 0;
6945 i.flags[op] |= Operand_PCrel;
6946 if (! i.disp_operands)
6947 fake_zero_displacement = 1;
6948 }
6949 else if (i.base_reg->reg_type.bitfield.word)
6950 {
6951 gas_assert (!i.tm.opcode_modifier.vecsib);
6952 switch (i.base_reg->reg_num)
6953 {
6954 case 3: /* (%bx) */
6955 if (i.index_reg == 0)
6956 i.rm.regmem = 7;
6957 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6958 i.rm.regmem = i.index_reg->reg_num - 6;
6959 break;
6960 case 5: /* (%bp) */
6961 default_seg = &ss;
6962 if (i.index_reg == 0)
6963 {
6964 i.rm.regmem = 6;
6965 if (operand_type_check (i.types[op], disp) == 0)
6966 {
6967 /* fake (%bp) into 0(%bp) */
6968 i.types[op].bitfield.disp8 = 1;
6969 fake_zero_displacement = 1;
6970 }
6971 }
6972 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6973 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6974 break;
6975 default: /* (%si) -> 4 or (%di) -> 5 */
6976 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6977 }
6978 i.rm.mode = mode_from_disp_size (i.types[op]);
6979 }
6980 else /* i.base_reg and 32/64 bit mode */
6981 {
6982 if (flag_code == CODE_64BIT
6983 && operand_type_check (i.types[op], disp))
6984 {
6985 i.types[op].bitfield.disp16 = 0;
6986 i.types[op].bitfield.disp64 = 0;
6987 if (i.prefix[ADDR_PREFIX] == 0)
6988 {
6989 i.types[op].bitfield.disp32 = 0;
6990 i.types[op].bitfield.disp32s = 1;
6991 }
6992 else
6993 {
6994 i.types[op].bitfield.disp32 = 1;
6995 i.types[op].bitfield.disp32s = 0;
6996 }
6997 }
6998
6999 if (!i.tm.opcode_modifier.vecsib)
7000 i.rm.regmem = i.base_reg->reg_num;
7001 if ((i.base_reg->reg_flags & RegRex) != 0)
7002 i.rex |= REX_B;
7003 i.sib.base = i.base_reg->reg_num;
7004 /* x86-64 ignores REX prefix bit here to avoid decoder
7005 complications. */
7006 if (!(i.base_reg->reg_flags & RegRex)
7007 && (i.base_reg->reg_num == EBP_REG_NUM
7008 || i.base_reg->reg_num == ESP_REG_NUM))
7009 default_seg = &ss;
7010 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7011 {
7012 fake_zero_displacement = 1;
7013 i.types[op].bitfield.disp8 = 1;
7014 }
7015 i.sib.scale = i.log2_scale_factor;
7016 if (i.index_reg == 0)
7017 {
7018 gas_assert (!i.tm.opcode_modifier.vecsib);
7019 /* <disp>(%esp) becomes two byte modrm with no index
7020 register. We've already stored the code for esp
7021 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7022 Any base register besides %esp will not use the
7023 extra modrm byte. */
7024 i.sib.index = NO_INDEX_REGISTER;
7025 }
7026 else if (!i.tm.opcode_modifier.vecsib)
7027 {
7028 if (i.index_reg->reg_num == RegEiz
7029 || i.index_reg->reg_num == RegRiz)
7030 i.sib.index = NO_INDEX_REGISTER;
7031 else
7032 i.sib.index = i.index_reg->reg_num;
7033 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7034 if ((i.index_reg->reg_flags & RegRex) != 0)
7035 i.rex |= REX_X;
7036 }
7037
7038 if (i.disp_operands
7039 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7040 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7041 i.rm.mode = 0;
7042 else
7043 {
7044 if (!fake_zero_displacement
7045 && !i.disp_operands
7046 && i.disp_encoding)
7047 {
7048 fake_zero_displacement = 1;
7049 if (i.disp_encoding == disp_encoding_8bit)
7050 i.types[op].bitfield.disp8 = 1;
7051 else
7052 i.types[op].bitfield.disp32 = 1;
7053 }
7054 i.rm.mode = mode_from_disp_size (i.types[op]);
7055 }
7056 }
7057
7058 if (fake_zero_displacement)
7059 {
7060 /* Fakes a zero displacement assuming that i.types[op]
7061 holds the correct displacement size. */
7062 expressionS *exp;
7063
7064 gas_assert (i.op[op].disps == 0);
7065 exp = &disp_expressions[i.disp_operands++];
7066 i.op[op].disps = exp;
7067 exp->X_op = O_constant;
7068 exp->X_add_number = 0;
7069 exp->X_add_symbol = (symbolS *) 0;
7070 exp->X_op_symbol = (symbolS *) 0;
7071 }
7072
7073 mem = op;
7074 }
7075 else
7076 mem = ~0;
7077
7078 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7079 {
7080 if (operand_type_check (i.types[0], imm))
7081 i.vex.register_specifier = NULL;
7082 else
7083 {
7084 /* VEX.vvvv encodes one of the sources when the first
7085 operand is not an immediate. */
7086 if (i.tm.opcode_modifier.vexw == VEXW0)
7087 i.vex.register_specifier = i.op[0].regs;
7088 else
7089 i.vex.register_specifier = i.op[1].regs;
7090 }
7091
7092 /* Destination is a XMM register encoded in the ModRM.reg
7093 and VEX.R bit. */
7094 i.rm.reg = i.op[2].regs->reg_num;
7095 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7096 i.rex |= REX_R;
7097
7098 /* ModRM.rm and VEX.B encodes the other source. */
7099 if (!i.mem_operands)
7100 {
7101 i.rm.mode = 3;
7102
7103 if (i.tm.opcode_modifier.vexw == VEXW0)
7104 i.rm.regmem = i.op[1].regs->reg_num;
7105 else
7106 i.rm.regmem = i.op[0].regs->reg_num;
7107
7108 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7109 i.rex |= REX_B;
7110 }
7111 }
7112 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7113 {
7114 i.vex.register_specifier = i.op[2].regs;
7115 if (!i.mem_operands)
7116 {
7117 i.rm.mode = 3;
7118 i.rm.regmem = i.op[1].regs->reg_num;
7119 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7120 i.rex |= REX_B;
7121 }
7122 }
7123 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7124 (if any) based on i.tm.extension_opcode. Again, we must be
7125 careful to make sure that segment/control/debug/test/MMX
7126 registers are coded into the i.rm.reg field. */
7127 else if (i.reg_operands)
7128 {
7129 unsigned int op;
7130 unsigned int vex_reg = ~0;
7131
7132 for (op = 0; op < i.operands; op++)
7133 if (i.types[op].bitfield.reg
7134 || i.types[op].bitfield.regmmx
7135 || i.types[op].bitfield.regsimd
7136 || i.types[op].bitfield.regbnd
7137 || i.types[op].bitfield.regmask
7138 || i.types[op].bitfield.sreg2
7139 || i.types[op].bitfield.sreg3
7140 || i.types[op].bitfield.control
7141 || i.types[op].bitfield.debug
7142 || i.types[op].bitfield.test)
7143 break;
7144
7145 if (vex_3_sources)
7146 op = dest;
7147 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7148 {
7149 /* For instructions with VexNDS, the register-only
7150 source operand is encoded in VEX prefix. */
7151 gas_assert (mem != (unsigned int) ~0);
7152
7153 if (op > mem)
7154 {
7155 vex_reg = op++;
7156 gas_assert (op < i.operands);
7157 }
7158 else
7159 {
7160 /* Check register-only source operand when two source
7161 operands are swapped. */
7162 if (!i.tm.operand_types[op].bitfield.baseindex
7163 && i.tm.operand_types[op + 1].bitfield.baseindex)
7164 {
7165 vex_reg = op;
7166 op += 2;
7167 gas_assert (mem == (vex_reg + 1)
7168 && op < i.operands);
7169 }
7170 else
7171 {
7172 vex_reg = op + 1;
7173 gas_assert (vex_reg < i.operands);
7174 }
7175 }
7176 }
7177 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7178 {
7179 /* For instructions with VexNDD, the register destination
7180 is encoded in VEX prefix. */
7181 if (i.mem_operands == 0)
7182 {
7183 /* There is no memory operand. */
7184 gas_assert ((op + 2) == i.operands);
7185 vex_reg = op + 1;
7186 }
7187 else
7188 {
7189 /* There are only 2 operands. */
7190 gas_assert (op < 2 && i.operands == 2);
7191 vex_reg = 1;
7192 }
7193 }
7194 else
7195 gas_assert (op < i.operands);
7196
7197 if (vex_reg != (unsigned int) ~0)
7198 {
7199 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7200
7201 if ((!type->bitfield.reg
7202 || (!type->bitfield.dword && !type->bitfield.qword))
7203 && !type->bitfield.regsimd
7204 && !operand_type_equal (type, &regmask))
7205 abort ();
7206
7207 i.vex.register_specifier = i.op[vex_reg].regs;
7208 }
7209
7210 /* Don't set OP operand twice. */
7211 if (vex_reg != op)
7212 {
7213 /* If there is an extension opcode to put here, the
7214 register number must be put into the regmem field. */
7215 if (i.tm.extension_opcode != None)
7216 {
7217 i.rm.regmem = i.op[op].regs->reg_num;
7218 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7219 i.rex |= REX_B;
7220 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7221 i.vrex |= REX_B;
7222 }
7223 else
7224 {
7225 i.rm.reg = i.op[op].regs->reg_num;
7226 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7227 i.rex |= REX_R;
7228 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7229 i.vrex |= REX_R;
7230 }
7231 }
7232
7233 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7234 must set it to 3 to indicate this is a register operand
7235 in the regmem field. */
7236 if (!i.mem_operands)
7237 i.rm.mode = 3;
7238 }
7239
7240 /* Fill in i.rm.reg field with extension opcode (if any). */
7241 if (i.tm.extension_opcode != None)
7242 i.rm.reg = i.tm.extension_opcode;
7243 }
7244 return default_seg;
7245 }
7246
7247 static void
7248 output_branch (void)
7249 {
7250 char *p;
7251 int size;
7252 int code16;
7253 int prefix;
7254 relax_substateT subtype;
7255 symbolS *sym;
7256 offsetT off;
7257
7258 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7259 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7260
7261 prefix = 0;
7262 if (i.prefix[DATA_PREFIX] != 0)
7263 {
7264 prefix = 1;
7265 i.prefixes -= 1;
7266 code16 ^= CODE16;
7267 }
7268 /* Pentium4 branch hints. */
7269 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7270 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7271 {
7272 prefix++;
7273 i.prefixes--;
7274 }
7275 if (i.prefix[REX_PREFIX] != 0)
7276 {
7277 prefix++;
7278 i.prefixes--;
7279 }
7280
7281 /* BND prefixed jump. */
7282 if (i.prefix[BND_PREFIX] != 0)
7283 {
7284 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7285 i.prefixes -= 1;
7286 }
7287
7288 if (i.prefixes != 0 && !intel_syntax)
7289 as_warn (_("skipping prefixes on this instruction"));
7290
7291 /* It's always a symbol; End frag & setup for relax.
7292 Make sure there is enough room in this frag for the largest
7293 instruction we may generate in md_convert_frag. This is 2
7294 bytes for the opcode and room for the prefix and largest
7295 displacement. */
7296 frag_grow (prefix + 2 + 4);
7297 /* Prefix and 1 opcode byte go in fr_fix. */
7298 p = frag_more (prefix + 1);
7299 if (i.prefix[DATA_PREFIX] != 0)
7300 *p++ = DATA_PREFIX_OPCODE;
7301 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7302 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7303 *p++ = i.prefix[SEG_PREFIX];
7304 if (i.prefix[REX_PREFIX] != 0)
7305 *p++ = i.prefix[REX_PREFIX];
7306 *p = i.tm.base_opcode;
7307
7308 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7309 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7310 else if (cpu_arch_flags.bitfield.cpui386)
7311 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7312 else
7313 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7314 subtype |= code16;
7315
7316 sym = i.op[0].disps->X_add_symbol;
7317 off = i.op[0].disps->X_add_number;
7318
7319 if (i.op[0].disps->X_op != O_constant
7320 && i.op[0].disps->X_op != O_symbol)
7321 {
7322 /* Handle complex expressions. */
7323 sym = make_expr_symbol (i.op[0].disps);
7324 off = 0;
7325 }
7326
7327 /* 1 possible extra opcode + 4 byte displacement go in var part.
7328 Pass reloc in fr_var. */
7329 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7330 }
7331
7332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7333 /* Return TRUE iff PLT32 relocation should be used for branching to
7334 symbol S. */
7335
7336 static bfd_boolean
7337 need_plt32_p (symbolS *s)
7338 {
7339 /* PLT32 relocation is ELF only. */
7340 if (!IS_ELF)
7341 return FALSE;
7342
7343 /* Since there is no need to prepare for PLT branch on x86-64, we
7344 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7345 be used as a marker for 32-bit PC-relative branches. */
7346 if (!object_64bit)
7347 return FALSE;
7348
7349 /* Weak or undefined symbol need PLT32 relocation. */
7350 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7351 return TRUE;
7352
7353 /* Non-global symbol doesn't need PLT32 relocation. */
7354 if (! S_IS_EXTERNAL (s))
7355 return FALSE;
7356
7357 /* Other global symbols need PLT32 relocation. NB: Symbol with
7358 non-default visibilities are treated as normal global symbol
7359 so that PLT32 relocation can be used as a marker for 32-bit
7360 PC-relative branches. It is useful for linker relaxation. */
7361 return TRUE;
7362 }
7363 #endif
7364
7365 static void
7366 output_jump (void)
7367 {
7368 char *p;
7369 int size;
7370 fixS *fixP;
7371 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7372
7373 if (i.tm.opcode_modifier.jumpbyte)
7374 {
7375 /* This is a loop or jecxz type instruction. */
7376 size = 1;
7377 if (i.prefix[ADDR_PREFIX] != 0)
7378 {
7379 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7380 i.prefixes -= 1;
7381 }
7382 /* Pentium4 branch hints. */
7383 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7384 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7385 {
7386 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7387 i.prefixes--;
7388 }
7389 }
7390 else
7391 {
7392 int code16;
7393
7394 code16 = 0;
7395 if (flag_code == CODE_16BIT)
7396 code16 = CODE16;
7397
7398 if (i.prefix[DATA_PREFIX] != 0)
7399 {
7400 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7401 i.prefixes -= 1;
7402 code16 ^= CODE16;
7403 }
7404
7405 size = 4;
7406 if (code16)
7407 size = 2;
7408 }
7409
7410 if (i.prefix[REX_PREFIX] != 0)
7411 {
7412 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7413 i.prefixes -= 1;
7414 }
7415
7416 /* BND prefixed jump. */
7417 if (i.prefix[BND_PREFIX] != 0)
7418 {
7419 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7420 i.prefixes -= 1;
7421 }
7422
7423 if (i.prefixes != 0 && !intel_syntax)
7424 as_warn (_("skipping prefixes on this instruction"));
7425
7426 p = frag_more (i.tm.opcode_length + size);
7427 switch (i.tm.opcode_length)
7428 {
7429 case 2:
7430 *p++ = i.tm.base_opcode >> 8;
7431 /* Fall through. */
7432 case 1:
7433 *p++ = i.tm.base_opcode;
7434 break;
7435 default:
7436 abort ();
7437 }
7438
7439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7440 if (size == 4
7441 && jump_reloc == NO_RELOC
7442 && need_plt32_p (i.op[0].disps->X_add_symbol))
7443 jump_reloc = BFD_RELOC_X86_64_PLT32;
7444 #endif
7445
7446 jump_reloc = reloc (size, 1, 1, jump_reloc);
7447
7448 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7449 i.op[0].disps, 1, jump_reloc);
7450
7451 /* All jumps handled here are signed, but don't use a signed limit
7452 check for 32 and 16 bit jumps as we want to allow wrap around at
7453 4G and 64k respectively. */
7454 if (size == 1)
7455 fixP->fx_signed = 1;
7456 }
7457
7458 static void
7459 output_interseg_jump (void)
7460 {
7461 char *p;
7462 int size;
7463 int prefix;
7464 int code16;
7465
7466 code16 = 0;
7467 if (flag_code == CODE_16BIT)
7468 code16 = CODE16;
7469
7470 prefix = 0;
7471 if (i.prefix[DATA_PREFIX] != 0)
7472 {
7473 prefix = 1;
7474 i.prefixes -= 1;
7475 code16 ^= CODE16;
7476 }
7477 if (i.prefix[REX_PREFIX] != 0)
7478 {
7479 prefix++;
7480 i.prefixes -= 1;
7481 }
7482
7483 size = 4;
7484 if (code16)
7485 size = 2;
7486
7487 if (i.prefixes != 0 && !intel_syntax)
7488 as_warn (_("skipping prefixes on this instruction"));
7489
7490 /* 1 opcode; 2 segment; offset */
7491 p = frag_more (prefix + 1 + 2 + size);
7492
7493 if (i.prefix[DATA_PREFIX] != 0)
7494 *p++ = DATA_PREFIX_OPCODE;
7495
7496 if (i.prefix[REX_PREFIX] != 0)
7497 *p++ = i.prefix[REX_PREFIX];
7498
7499 *p++ = i.tm.base_opcode;
7500 if (i.op[1].imms->X_op == O_constant)
7501 {
7502 offsetT n = i.op[1].imms->X_add_number;
7503
7504 if (size == 2
7505 && !fits_in_unsigned_word (n)
7506 && !fits_in_signed_word (n))
7507 {
7508 as_bad (_("16-bit jump out of range"));
7509 return;
7510 }
7511 md_number_to_chars (p, n, size);
7512 }
7513 else
7514 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7515 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7516 if (i.op[0].imms->X_op != O_constant)
7517 as_bad (_("can't handle non absolute segment in `%s'"),
7518 i.tm.name);
7519 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7520 }
7521
7522 static void
7523 output_insn (void)
7524 {
7525 fragS *insn_start_frag;
7526 offsetT insn_start_off;
7527
7528 /* Tie dwarf2 debug info to the address at the start of the insn.
7529 We can't do this after the insn has been output as the current
7530 frag may have been closed off. eg. by frag_var. */
7531 dwarf2_emit_insn (0);
7532
7533 insn_start_frag = frag_now;
7534 insn_start_off = frag_now_fix ();
7535
7536 /* Output jumps. */
7537 if (i.tm.opcode_modifier.jump)
7538 output_branch ();
7539 else if (i.tm.opcode_modifier.jumpbyte
7540 || i.tm.opcode_modifier.jumpdword)
7541 output_jump ();
7542 else if (i.tm.opcode_modifier.jumpintersegment)
7543 output_interseg_jump ();
7544 else
7545 {
7546 /* Output normal instructions here. */
7547 char *p;
7548 unsigned char *q;
7549 unsigned int j;
7550 unsigned int prefix;
7551
7552 if (avoid_fence
7553 && i.tm.base_opcode == 0xfae
7554 && i.operands == 1
7555 && i.imm_operands == 1
7556 && (i.op[0].imms->X_add_number == 0xe8
7557 || i.op[0].imms->X_add_number == 0xf0
7558 || i.op[0].imms->X_add_number == 0xf8))
7559 {
7560 /* Encode lfence, mfence, and sfence as
7561 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7562 offsetT val = 0x240483f0ULL;
7563 p = frag_more (5);
7564 md_number_to_chars (p, val, 5);
7565 return;
7566 }
7567
7568 /* Some processors fail on LOCK prefix. This options makes
7569 assembler ignore LOCK prefix and serves as a workaround. */
7570 if (omit_lock_prefix)
7571 {
7572 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7573 return;
7574 i.prefix[LOCK_PREFIX] = 0;
7575 }
7576
7577 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7578 don't need the explicit prefix. */
7579 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7580 {
7581 switch (i.tm.opcode_length)
7582 {
7583 case 3:
7584 if (i.tm.base_opcode & 0xff000000)
7585 {
7586 prefix = (i.tm.base_opcode >> 24) & 0xff;
7587 goto check_prefix;
7588 }
7589 break;
7590 case 2:
7591 if ((i.tm.base_opcode & 0xff0000) != 0)
7592 {
7593 prefix = (i.tm.base_opcode >> 16) & 0xff;
7594 if (i.tm.cpu_flags.bitfield.cpupadlock)
7595 {
7596 check_prefix:
7597 if (prefix != REPE_PREFIX_OPCODE
7598 || (i.prefix[REP_PREFIX]
7599 != REPE_PREFIX_OPCODE))
7600 add_prefix (prefix);
7601 }
7602 else
7603 add_prefix (prefix);
7604 }
7605 break;
7606 case 1:
7607 break;
7608 case 0:
7609 /* Check for pseudo prefixes. */
7610 as_bad_where (insn_start_frag->fr_file,
7611 insn_start_frag->fr_line,
7612 _("pseudo prefix without instruction"));
7613 return;
7614 default:
7615 abort ();
7616 }
7617
7618 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7619 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7620 R_X86_64_GOTTPOFF relocation so that linker can safely
7621 perform IE->LE optimization. */
7622 if (x86_elf_abi == X86_64_X32_ABI
7623 && i.operands == 2
7624 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7625 && i.prefix[REX_PREFIX] == 0)
7626 add_prefix (REX_OPCODE);
7627 #endif
7628
7629 /* The prefix bytes. */
7630 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7631 if (*q)
7632 FRAG_APPEND_1_CHAR (*q);
7633 }
7634 else
7635 {
7636 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7637 if (*q)
7638 switch (j)
7639 {
7640 case REX_PREFIX:
7641 /* REX byte is encoded in VEX prefix. */
7642 break;
7643 case SEG_PREFIX:
7644 case ADDR_PREFIX:
7645 FRAG_APPEND_1_CHAR (*q);
7646 break;
7647 default:
7648 /* There should be no other prefixes for instructions
7649 with VEX prefix. */
7650 abort ();
7651 }
7652
7653 /* For EVEX instructions i.vrex should become 0 after
7654 build_evex_prefix. For VEX instructions upper 16 registers
7655 aren't available, so VREX should be 0. */
7656 if (i.vrex)
7657 abort ();
7658 /* Now the VEX prefix. */
7659 p = frag_more (i.vex.length);
7660 for (j = 0; j < i.vex.length; j++)
7661 p[j] = i.vex.bytes[j];
7662 }
7663
7664 /* Now the opcode; be careful about word order here! */
7665 if (i.tm.opcode_length == 1)
7666 {
7667 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7668 }
7669 else
7670 {
7671 switch (i.tm.opcode_length)
7672 {
7673 case 4:
7674 p = frag_more (4);
7675 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7676 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7677 break;
7678 case 3:
7679 p = frag_more (3);
7680 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7681 break;
7682 case 2:
7683 p = frag_more (2);
7684 break;
7685 default:
7686 abort ();
7687 break;
7688 }
7689
7690 /* Put out high byte first: can't use md_number_to_chars! */
7691 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7692 *p = i.tm.base_opcode & 0xff;
7693 }
7694
7695 /* Now the modrm byte and sib byte (if present). */
7696 if (i.tm.opcode_modifier.modrm)
7697 {
7698 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7699 | i.rm.reg << 3
7700 | i.rm.mode << 6));
7701 /* If i.rm.regmem == ESP (4)
7702 && i.rm.mode != (Register mode)
7703 && not 16 bit
7704 ==> need second modrm byte. */
7705 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7706 && i.rm.mode != 3
7707 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7708 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7709 | i.sib.index << 3
7710 | i.sib.scale << 6));
7711 }
7712
7713 if (i.disp_operands)
7714 output_disp (insn_start_frag, insn_start_off);
7715
7716 if (i.imm_operands)
7717 output_imm (insn_start_frag, insn_start_off);
7718 }
7719
7720 #ifdef DEBUG386
7721 if (flag_debug)
7722 {
7723 pi ("" /*line*/, &i);
7724 }
7725 #endif /* DEBUG386 */
7726 }
7727
7728 /* Return the size of the displacement operand N. */
7729
7730 static int
7731 disp_size (unsigned int n)
7732 {
7733 int size = 4;
7734
7735 if (i.types[n].bitfield.disp64)
7736 size = 8;
7737 else if (i.types[n].bitfield.disp8)
7738 size = 1;
7739 else if (i.types[n].bitfield.disp16)
7740 size = 2;
7741 return size;
7742 }
7743
7744 /* Return the size of the immediate operand N. */
7745
7746 static int
7747 imm_size (unsigned int n)
7748 {
7749 int size = 4;
7750 if (i.types[n].bitfield.imm64)
7751 size = 8;
7752 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7753 size = 1;
7754 else if (i.types[n].bitfield.imm16)
7755 size = 2;
7756 return size;
7757 }
7758
7759 static void
7760 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7761 {
7762 char *p;
7763 unsigned int n;
7764
7765 for (n = 0; n < i.operands; n++)
7766 {
7767 if (operand_type_check (i.types[n], disp))
7768 {
7769 if (i.op[n].disps->X_op == O_constant)
7770 {
7771 int size = disp_size (n);
7772 offsetT val = i.op[n].disps->X_add_number;
7773
7774 val = offset_in_range (val >> i.memshift, size);
7775 p = frag_more (size);
7776 md_number_to_chars (p, val, size);
7777 }
7778 else
7779 {
7780 enum bfd_reloc_code_real reloc_type;
7781 int size = disp_size (n);
7782 int sign = i.types[n].bitfield.disp32s;
7783 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7784 fixS *fixP;
7785
7786 /* We can't have 8 bit displacement here. */
7787 gas_assert (!i.types[n].bitfield.disp8);
7788
7789 /* The PC relative address is computed relative
7790 to the instruction boundary, so in case immediate
7791 fields follows, we need to adjust the value. */
7792 if (pcrel && i.imm_operands)
7793 {
7794 unsigned int n1;
7795 int sz = 0;
7796
7797 for (n1 = 0; n1 < i.operands; n1++)
7798 if (operand_type_check (i.types[n1], imm))
7799 {
7800 /* Only one immediate is allowed for PC
7801 relative address. */
7802 gas_assert (sz == 0);
7803 sz = imm_size (n1);
7804 i.op[n].disps->X_add_number -= sz;
7805 }
7806 /* We should find the immediate. */
7807 gas_assert (sz != 0);
7808 }
7809
7810 p = frag_more (size);
7811 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7812 if (GOT_symbol
7813 && GOT_symbol == i.op[n].disps->X_add_symbol
7814 && (((reloc_type == BFD_RELOC_32
7815 || reloc_type == BFD_RELOC_X86_64_32S
7816 || (reloc_type == BFD_RELOC_64
7817 && object_64bit))
7818 && (i.op[n].disps->X_op == O_symbol
7819 || (i.op[n].disps->X_op == O_add
7820 && ((symbol_get_value_expression
7821 (i.op[n].disps->X_op_symbol)->X_op)
7822 == O_subtract))))
7823 || reloc_type == BFD_RELOC_32_PCREL))
7824 {
7825 offsetT add;
7826
7827 if (insn_start_frag == frag_now)
7828 add = (p - frag_now->fr_literal) - insn_start_off;
7829 else
7830 {
7831 fragS *fr;
7832
7833 add = insn_start_frag->fr_fix - insn_start_off;
7834 for (fr = insn_start_frag->fr_next;
7835 fr && fr != frag_now; fr = fr->fr_next)
7836 add += fr->fr_fix;
7837 add += p - frag_now->fr_literal;
7838 }
7839
7840 if (!object_64bit)
7841 {
7842 reloc_type = BFD_RELOC_386_GOTPC;
7843 i.op[n].imms->X_add_number += add;
7844 }
7845 else if (reloc_type == BFD_RELOC_64)
7846 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7847 else
7848 /* Don't do the adjustment for x86-64, as there
7849 the pcrel addressing is relative to the _next_
7850 insn, and that is taken care of in other code. */
7851 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7852 }
7853 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7854 size, i.op[n].disps, pcrel,
7855 reloc_type);
7856 /* Check for "call/jmp *mem", "mov mem, %reg",
7857 "test %reg, mem" and "binop mem, %reg" where binop
7858 is one of adc, add, and, cmp, or, sbb, sub, xor
7859 instructions. Always generate R_386_GOT32X for
7860 "sym*GOT" operand in 32-bit mode. */
7861 if ((generate_relax_relocations
7862 || (!object_64bit
7863 && i.rm.mode == 0
7864 && i.rm.regmem == 5))
7865 && (i.rm.mode == 2
7866 || (i.rm.mode == 0 && i.rm.regmem == 5))
7867 && ((i.operands == 1
7868 && i.tm.base_opcode == 0xff
7869 && (i.rm.reg == 2 || i.rm.reg == 4))
7870 || (i.operands == 2
7871 && (i.tm.base_opcode == 0x8b
7872 || i.tm.base_opcode == 0x85
7873 || (i.tm.base_opcode & 0xc7) == 0x03))))
7874 {
7875 if (object_64bit)
7876 {
7877 fixP->fx_tcbit = i.rex != 0;
7878 if (i.base_reg
7879 && (i.base_reg->reg_num == RegRip
7880 || i.base_reg->reg_num == RegEip))
7881 fixP->fx_tcbit2 = 1;
7882 }
7883 else
7884 fixP->fx_tcbit2 = 1;
7885 }
7886 }
7887 }
7888 }
7889 }
7890
7891 static void
7892 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7893 {
7894 char *p;
7895 unsigned int n;
7896
7897 for (n = 0; n < i.operands; n++)
7898 {
7899 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7900 if (i.rounding && (int) n == i.rounding->operand)
7901 continue;
7902
7903 if (operand_type_check (i.types[n], imm))
7904 {
7905 if (i.op[n].imms->X_op == O_constant)
7906 {
7907 int size = imm_size (n);
7908 offsetT val;
7909
7910 val = offset_in_range (i.op[n].imms->X_add_number,
7911 size);
7912 p = frag_more (size);
7913 md_number_to_chars (p, val, size);
7914 }
7915 else
7916 {
7917 /* Not absolute_section.
7918 Need a 32-bit fixup (don't support 8bit
7919 non-absolute imms). Try to support other
7920 sizes ... */
7921 enum bfd_reloc_code_real reloc_type;
7922 int size = imm_size (n);
7923 int sign;
7924
7925 if (i.types[n].bitfield.imm32s
7926 && (i.suffix == QWORD_MNEM_SUFFIX
7927 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7928 sign = 1;
7929 else
7930 sign = 0;
7931
7932 p = frag_more (size);
7933 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7934
7935 /* This is tough to explain. We end up with this one if we
7936 * have operands that look like
7937 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7938 * obtain the absolute address of the GOT, and it is strongly
7939 * preferable from a performance point of view to avoid using
7940 * a runtime relocation for this. The actual sequence of
7941 * instructions often look something like:
7942 *
7943 * call .L66
7944 * .L66:
7945 * popl %ebx
7946 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7947 *
7948 * The call and pop essentially return the absolute address
7949 * of the label .L66 and store it in %ebx. The linker itself
7950 * will ultimately change the first operand of the addl so
7951 * that %ebx points to the GOT, but to keep things simple, the
7952 * .o file must have this operand set so that it generates not
7953 * the absolute address of .L66, but the absolute address of
7954 * itself. This allows the linker itself simply treat a GOTPC
7955 * relocation as asking for a pcrel offset to the GOT to be
7956 * added in, and the addend of the relocation is stored in the
7957 * operand field for the instruction itself.
7958 *
7959 * Our job here is to fix the operand so that it would add
7960 * the correct offset so that %ebx would point to itself. The
7961 * thing that is tricky is that .-.L66 will point to the
7962 * beginning of the instruction, so we need to further modify
7963 * the operand so that it will point to itself. There are
7964 * other cases where you have something like:
7965 *
7966 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7967 *
7968 * and here no correction would be required. Internally in
7969 * the assembler we treat operands of this form as not being
7970 * pcrel since the '.' is explicitly mentioned, and I wonder
7971 * whether it would simplify matters to do it this way. Who
7972 * knows. In earlier versions of the PIC patches, the
7973 * pcrel_adjust field was used to store the correction, but
7974 * since the expression is not pcrel, I felt it would be
7975 * confusing to do it this way. */
7976
7977 if ((reloc_type == BFD_RELOC_32
7978 || reloc_type == BFD_RELOC_X86_64_32S
7979 || reloc_type == BFD_RELOC_64)
7980 && GOT_symbol
7981 && GOT_symbol == i.op[n].imms->X_add_symbol
7982 && (i.op[n].imms->X_op == O_symbol
7983 || (i.op[n].imms->X_op == O_add
7984 && ((symbol_get_value_expression
7985 (i.op[n].imms->X_op_symbol)->X_op)
7986 == O_subtract))))
7987 {
7988 offsetT add;
7989
7990 if (insn_start_frag == frag_now)
7991 add = (p - frag_now->fr_literal) - insn_start_off;
7992 else
7993 {
7994 fragS *fr;
7995
7996 add = insn_start_frag->fr_fix - insn_start_off;
7997 for (fr = insn_start_frag->fr_next;
7998 fr && fr != frag_now; fr = fr->fr_next)
7999 add += fr->fr_fix;
8000 add += p - frag_now->fr_literal;
8001 }
8002
8003 if (!object_64bit)
8004 reloc_type = BFD_RELOC_386_GOTPC;
8005 else if (size == 4)
8006 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8007 else if (size == 8)
8008 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8009 i.op[n].imms->X_add_number += add;
8010 }
8011 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8012 i.op[n].imms, 0, reloc_type);
8013 }
8014 }
8015 }
8016 }
8017 \f
8018 /* x86_cons_fix_new is called via the expression parsing code when a
8019 reloc is needed. We use this hook to get the correct .got reloc. */
8020 static int cons_sign = -1;
8021
8022 void
8023 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8024 expressionS *exp, bfd_reloc_code_real_type r)
8025 {
8026 r = reloc (len, 0, cons_sign, r);
8027
8028 #ifdef TE_PE
8029 if (exp->X_op == O_secrel)
8030 {
8031 exp->X_op = O_symbol;
8032 r = BFD_RELOC_32_SECREL;
8033 }
8034 #endif
8035
8036 fix_new_exp (frag, off, len, exp, 0, r);
8037 }
8038
8039 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8040 purpose of the `.dc.a' internal pseudo-op. */
8041
8042 int
8043 x86_address_bytes (void)
8044 {
8045 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8046 return 4;
8047 return stdoutput->arch_info->bits_per_address / 8;
8048 }
8049
8050 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8051 || defined (LEX_AT)
8052 # define lex_got(reloc, adjust, types) NULL
8053 #else
8054 /* Parse operands of the form
8055 <symbol>@GOTOFF+<nnn>
8056 and similar .plt or .got references.
8057
8058 If we find one, set up the correct relocation in RELOC and copy the
8059 input string, minus the `@GOTOFF' into a malloc'd buffer for
8060 parsing by the calling routine. Return this buffer, and if ADJUST
8061 is non-null set it to the length of the string we removed from the
8062 input line. Otherwise return NULL. */
8063 static char *
8064 lex_got (enum bfd_reloc_code_real *rel,
8065 int *adjust,
8066 i386_operand_type *types)
8067 {
8068 /* Some of the relocations depend on the size of what field is to
8069 be relocated. But in our callers i386_immediate and i386_displacement
8070 we don't yet know the operand size (this will be set by insn
8071 matching). Hence we record the word32 relocation here,
8072 and adjust the reloc according to the real size in reloc(). */
8073 static const struct {
8074 const char *str;
8075 int len;
8076 const enum bfd_reloc_code_real rel[2];
8077 const i386_operand_type types64;
8078 } gotrel[] = {
8079 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8080 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8081 BFD_RELOC_SIZE32 },
8082 OPERAND_TYPE_IMM32_64 },
8083 #endif
8084 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8085 BFD_RELOC_X86_64_PLTOFF64 },
8086 OPERAND_TYPE_IMM64 },
8087 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8088 BFD_RELOC_X86_64_PLT32 },
8089 OPERAND_TYPE_IMM32_32S_DISP32 },
8090 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8091 BFD_RELOC_X86_64_GOTPLT64 },
8092 OPERAND_TYPE_IMM64_DISP64 },
8093 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8094 BFD_RELOC_X86_64_GOTOFF64 },
8095 OPERAND_TYPE_IMM64_DISP64 },
8096 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8097 BFD_RELOC_X86_64_GOTPCREL },
8098 OPERAND_TYPE_IMM32_32S_DISP32 },
8099 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8100 BFD_RELOC_X86_64_TLSGD },
8101 OPERAND_TYPE_IMM32_32S_DISP32 },
8102 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8103 _dummy_first_bfd_reloc_code_real },
8104 OPERAND_TYPE_NONE },
8105 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8106 BFD_RELOC_X86_64_TLSLD },
8107 OPERAND_TYPE_IMM32_32S_DISP32 },
8108 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8109 BFD_RELOC_X86_64_GOTTPOFF },
8110 OPERAND_TYPE_IMM32_32S_DISP32 },
8111 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8112 BFD_RELOC_X86_64_TPOFF32 },
8113 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8114 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8115 _dummy_first_bfd_reloc_code_real },
8116 OPERAND_TYPE_NONE },
8117 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8118 BFD_RELOC_X86_64_DTPOFF32 },
8119 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8120 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8121 _dummy_first_bfd_reloc_code_real },
8122 OPERAND_TYPE_NONE },
8123 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8124 _dummy_first_bfd_reloc_code_real },
8125 OPERAND_TYPE_NONE },
8126 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8127 BFD_RELOC_X86_64_GOT32 },
8128 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8129 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8130 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8131 OPERAND_TYPE_IMM32_32S_DISP32 },
8132 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8133 BFD_RELOC_X86_64_TLSDESC_CALL },
8134 OPERAND_TYPE_IMM32_32S_DISP32 },
8135 };
8136 char *cp;
8137 unsigned int j;
8138
8139 #if defined (OBJ_MAYBE_ELF)
8140 if (!IS_ELF)
8141 return NULL;
8142 #endif
8143
8144 for (cp = input_line_pointer; *cp != '@'; cp++)
8145 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8146 return NULL;
8147
8148 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8149 {
8150 int len = gotrel[j].len;
8151 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8152 {
8153 if (gotrel[j].rel[object_64bit] != 0)
8154 {
8155 int first, second;
8156 char *tmpbuf, *past_reloc;
8157
8158 *rel = gotrel[j].rel[object_64bit];
8159
8160 if (types)
8161 {
8162 if (flag_code != CODE_64BIT)
8163 {
8164 types->bitfield.imm32 = 1;
8165 types->bitfield.disp32 = 1;
8166 }
8167 else
8168 *types = gotrel[j].types64;
8169 }
8170
8171 if (j != 0 && GOT_symbol == NULL)
8172 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8173
8174 /* The length of the first part of our input line. */
8175 first = cp - input_line_pointer;
8176
8177 /* The second part goes from after the reloc token until
8178 (and including) an end_of_line char or comma. */
8179 past_reloc = cp + 1 + len;
8180 cp = past_reloc;
8181 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8182 ++cp;
8183 second = cp + 1 - past_reloc;
8184
8185 /* Allocate and copy string. The trailing NUL shouldn't
8186 be necessary, but be safe. */
8187 tmpbuf = XNEWVEC (char, first + second + 2);
8188 memcpy (tmpbuf, input_line_pointer, first);
8189 if (second != 0 && *past_reloc != ' ')
8190 /* Replace the relocation token with ' ', so that
8191 errors like foo@GOTOFF1 will be detected. */
8192 tmpbuf[first++] = ' ';
8193 else
8194 /* Increment length by 1 if the relocation token is
8195 removed. */
8196 len++;
8197 if (adjust)
8198 *adjust = len;
8199 memcpy (tmpbuf + first, past_reloc, second);
8200 tmpbuf[first + second] = '\0';
8201 return tmpbuf;
8202 }
8203
8204 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8205 gotrel[j].str, 1 << (5 + object_64bit));
8206 return NULL;
8207 }
8208 }
8209
8210 /* Might be a symbol version string. Don't as_bad here. */
8211 return NULL;
8212 }
8213 #endif
8214
8215 #ifdef TE_PE
8216 #ifdef lex_got
8217 #undef lex_got
8218 #endif
8219 /* Parse operands of the form
8220 <symbol>@SECREL32+<nnn>
8221
8222 If we find one, set up the correct relocation in RELOC and copy the
8223 input string, minus the `@SECREL32' into a malloc'd buffer for
8224 parsing by the calling routine. Return this buffer, and if ADJUST
8225 is non-null set it to the length of the string we removed from the
8226 input line. Otherwise return NULL.
8227
8228 This function is copied from the ELF version above adjusted for PE targets. */
8229
8230 static char *
8231 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8232 int *adjust ATTRIBUTE_UNUSED,
8233 i386_operand_type *types)
8234 {
8235 static const struct
8236 {
8237 const char *str;
8238 int len;
8239 const enum bfd_reloc_code_real rel[2];
8240 const i386_operand_type types64;
8241 }
8242 gotrel[] =
8243 {
8244 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8245 BFD_RELOC_32_SECREL },
8246 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8247 };
8248
8249 char *cp;
8250 unsigned j;
8251
8252 for (cp = input_line_pointer; *cp != '@'; cp++)
8253 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8254 return NULL;
8255
8256 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8257 {
8258 int len = gotrel[j].len;
8259
8260 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8261 {
8262 if (gotrel[j].rel[object_64bit] != 0)
8263 {
8264 int first, second;
8265 char *tmpbuf, *past_reloc;
8266
8267 *rel = gotrel[j].rel[object_64bit];
8268 if (adjust)
8269 *adjust = len;
8270
8271 if (types)
8272 {
8273 if (flag_code != CODE_64BIT)
8274 {
8275 types->bitfield.imm32 = 1;
8276 types->bitfield.disp32 = 1;
8277 }
8278 else
8279 *types = gotrel[j].types64;
8280 }
8281
8282 /* The length of the first part of our input line. */
8283 first = cp - input_line_pointer;
8284
8285 /* The second part goes from after the reloc token until
8286 (and including) an end_of_line char or comma. */
8287 past_reloc = cp + 1 + len;
8288 cp = past_reloc;
8289 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8290 ++cp;
8291 second = cp + 1 - past_reloc;
8292
8293 /* Allocate and copy string. The trailing NUL shouldn't
8294 be necessary, but be safe. */
8295 tmpbuf = XNEWVEC (char, first + second + 2);
8296 memcpy (tmpbuf, input_line_pointer, first);
8297 if (second != 0 && *past_reloc != ' ')
8298 /* Replace the relocation token with ' ', so that
8299 errors like foo@SECLREL321 will be detected. */
8300 tmpbuf[first++] = ' ';
8301 memcpy (tmpbuf + first, past_reloc, second);
8302 tmpbuf[first + second] = '\0';
8303 return tmpbuf;
8304 }
8305
8306 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8307 gotrel[j].str, 1 << (5 + object_64bit));
8308 return NULL;
8309 }
8310 }
8311
8312 /* Might be a symbol version string. Don't as_bad here. */
8313 return NULL;
8314 }
8315
8316 #endif /* TE_PE */
8317
8318 bfd_reloc_code_real_type
8319 x86_cons (expressionS *exp, int size)
8320 {
8321 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8322
8323 intel_syntax = -intel_syntax;
8324
8325 exp->X_md = 0;
8326 if (size == 4 || (object_64bit && size == 8))
8327 {
8328 /* Handle @GOTOFF and the like in an expression. */
8329 char *save;
8330 char *gotfree_input_line;
8331 int adjust = 0;
8332
8333 save = input_line_pointer;
8334 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8335 if (gotfree_input_line)
8336 input_line_pointer = gotfree_input_line;
8337
8338 expression (exp);
8339
8340 if (gotfree_input_line)
8341 {
8342 /* expression () has merrily parsed up to the end of line,
8343 or a comma - in the wrong buffer. Transfer how far
8344 input_line_pointer has moved to the right buffer. */
8345 input_line_pointer = (save
8346 + (input_line_pointer - gotfree_input_line)
8347 + adjust);
8348 free (gotfree_input_line);
8349 if (exp->X_op == O_constant
8350 || exp->X_op == O_absent
8351 || exp->X_op == O_illegal
8352 || exp->X_op == O_register
8353 || exp->X_op == O_big)
8354 {
8355 char c = *input_line_pointer;
8356 *input_line_pointer = 0;
8357 as_bad (_("missing or invalid expression `%s'"), save);
8358 *input_line_pointer = c;
8359 }
8360 }
8361 }
8362 else
8363 expression (exp);
8364
8365 intel_syntax = -intel_syntax;
8366
8367 if (intel_syntax)
8368 i386_intel_simplify (exp);
8369
8370 return got_reloc;
8371 }
8372
8373 static void
8374 signed_cons (int size)
8375 {
8376 if (flag_code == CODE_64BIT)
8377 cons_sign = 1;
8378 cons (size);
8379 cons_sign = -1;
8380 }
8381
8382 #ifdef TE_PE
8383 static void
8384 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8385 {
8386 expressionS exp;
8387
8388 do
8389 {
8390 expression (&exp);
8391 if (exp.X_op == O_symbol)
8392 exp.X_op = O_secrel;
8393
8394 emit_expr (&exp, 4);
8395 }
8396 while (*input_line_pointer++ == ',');
8397
8398 input_line_pointer--;
8399 demand_empty_rest_of_line ();
8400 }
8401 #endif
8402
8403 /* Handle Vector operations. */
8404
8405 static char *
8406 check_VecOperations (char *op_string, char *op_end)
8407 {
8408 const reg_entry *mask;
8409 const char *saved;
8410 char *end_op;
8411
8412 while (*op_string
8413 && (op_end == NULL || op_string < op_end))
8414 {
8415 saved = op_string;
8416 if (*op_string == '{')
8417 {
8418 op_string++;
8419
8420 /* Check broadcasts. */
8421 if (strncmp (op_string, "1to", 3) == 0)
8422 {
8423 int bcst_type;
8424
8425 if (i.broadcast)
8426 goto duplicated_vec_op;
8427
8428 op_string += 3;
8429 if (*op_string == '8')
8430 bcst_type = BROADCAST_1TO8;
8431 else if (*op_string == '4')
8432 bcst_type = BROADCAST_1TO4;
8433 else if (*op_string == '2')
8434 bcst_type = BROADCAST_1TO2;
8435 else if (*op_string == '1'
8436 && *(op_string+1) == '6')
8437 {
8438 bcst_type = BROADCAST_1TO16;
8439 op_string++;
8440 }
8441 else
8442 {
8443 as_bad (_("Unsupported broadcast: `%s'"), saved);
8444 return NULL;
8445 }
8446 op_string++;
8447
8448 broadcast_op.type = bcst_type;
8449 broadcast_op.operand = this_operand;
8450 i.broadcast = &broadcast_op;
8451 }
8452 /* Check masking operation. */
8453 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8454 {
8455 /* k0 can't be used for write mask. */
8456 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8457 {
8458 as_bad (_("`%s%s' can't be used for write mask"),
8459 register_prefix, mask->reg_name);
8460 return NULL;
8461 }
8462
8463 if (!i.mask)
8464 {
8465 mask_op.mask = mask;
8466 mask_op.zeroing = 0;
8467 mask_op.operand = this_operand;
8468 i.mask = &mask_op;
8469 }
8470 else
8471 {
8472 if (i.mask->mask)
8473 goto duplicated_vec_op;
8474
8475 i.mask->mask = mask;
8476
8477 /* Only "{z}" is allowed here. No need to check
8478 zeroing mask explicitly. */
8479 if (i.mask->operand != this_operand)
8480 {
8481 as_bad (_("invalid write mask `%s'"), saved);
8482 return NULL;
8483 }
8484 }
8485
8486 op_string = end_op;
8487 }
8488 /* Check zeroing-flag for masking operation. */
8489 else if (*op_string == 'z')
8490 {
8491 if (!i.mask)
8492 {
8493 mask_op.mask = NULL;
8494 mask_op.zeroing = 1;
8495 mask_op.operand = this_operand;
8496 i.mask = &mask_op;
8497 }
8498 else
8499 {
8500 if (i.mask->zeroing)
8501 {
8502 duplicated_vec_op:
8503 as_bad (_("duplicated `%s'"), saved);
8504 return NULL;
8505 }
8506
8507 i.mask->zeroing = 1;
8508
8509 /* Only "{%k}" is allowed here. No need to check mask
8510 register explicitly. */
8511 if (i.mask->operand != this_operand)
8512 {
8513 as_bad (_("invalid zeroing-masking `%s'"),
8514 saved);
8515 return NULL;
8516 }
8517 }
8518
8519 op_string++;
8520 }
8521 else
8522 goto unknown_vec_op;
8523
8524 if (*op_string != '}')
8525 {
8526 as_bad (_("missing `}' in `%s'"), saved);
8527 return NULL;
8528 }
8529 op_string++;
8530 continue;
8531 }
8532 unknown_vec_op:
8533 /* We don't know this one. */
8534 as_bad (_("unknown vector operation: `%s'"), saved);
8535 return NULL;
8536 }
8537
8538 if (i.mask && i.mask->zeroing && !i.mask->mask)
8539 {
8540 as_bad (_("zeroing-masking only allowed with write mask"));
8541 return NULL;
8542 }
8543
8544 return op_string;
8545 }
8546
8547 static int
8548 i386_immediate (char *imm_start)
8549 {
8550 char *save_input_line_pointer;
8551 char *gotfree_input_line;
8552 segT exp_seg = 0;
8553 expressionS *exp;
8554 i386_operand_type types;
8555
8556 operand_type_set (&types, ~0);
8557
8558 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8559 {
8560 as_bad (_("at most %d immediate operands are allowed"),
8561 MAX_IMMEDIATE_OPERANDS);
8562 return 0;
8563 }
8564
8565 exp = &im_expressions[i.imm_operands++];
8566 i.op[this_operand].imms = exp;
8567
8568 if (is_space_char (*imm_start))
8569 ++imm_start;
8570
8571 save_input_line_pointer = input_line_pointer;
8572 input_line_pointer = imm_start;
8573
8574 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8575 if (gotfree_input_line)
8576 input_line_pointer = gotfree_input_line;
8577
8578 exp_seg = expression (exp);
8579
8580 SKIP_WHITESPACE ();
8581
8582 /* Handle vector operations. */
8583 if (*input_line_pointer == '{')
8584 {
8585 input_line_pointer = check_VecOperations (input_line_pointer,
8586 NULL);
8587 if (input_line_pointer == NULL)
8588 return 0;
8589 }
8590
8591 if (*input_line_pointer)
8592 as_bad (_("junk `%s' after expression"), input_line_pointer);
8593
8594 input_line_pointer = save_input_line_pointer;
8595 if (gotfree_input_line)
8596 {
8597 free (gotfree_input_line);
8598
8599 if (exp->X_op == O_constant || exp->X_op == O_register)
8600 exp->X_op = O_illegal;
8601 }
8602
8603 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8604 }
8605
8606 static int
8607 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8608 i386_operand_type types, const char *imm_start)
8609 {
8610 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8611 {
8612 if (imm_start)
8613 as_bad (_("missing or invalid immediate expression `%s'"),
8614 imm_start);
8615 return 0;
8616 }
8617 else if (exp->X_op == O_constant)
8618 {
8619 /* Size it properly later. */
8620 i.types[this_operand].bitfield.imm64 = 1;
8621 /* If not 64bit, sign extend val. */
8622 if (flag_code != CODE_64BIT
8623 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8624 exp->X_add_number
8625 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8626 }
8627 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8628 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8629 && exp_seg != absolute_section
8630 && exp_seg != text_section
8631 && exp_seg != data_section
8632 && exp_seg != bss_section
8633 && exp_seg != undefined_section
8634 && !bfd_is_com_section (exp_seg))
8635 {
8636 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8637 return 0;
8638 }
8639 #endif
8640 else if (!intel_syntax && exp_seg == reg_section)
8641 {
8642 if (imm_start)
8643 as_bad (_("illegal immediate register operand %s"), imm_start);
8644 return 0;
8645 }
8646 else
8647 {
8648 /* This is an address. The size of the address will be
8649 determined later, depending on destination register,
8650 suffix, or the default for the section. */
8651 i.types[this_operand].bitfield.imm8 = 1;
8652 i.types[this_operand].bitfield.imm16 = 1;
8653 i.types[this_operand].bitfield.imm32 = 1;
8654 i.types[this_operand].bitfield.imm32s = 1;
8655 i.types[this_operand].bitfield.imm64 = 1;
8656 i.types[this_operand] = operand_type_and (i.types[this_operand],
8657 types);
8658 }
8659
8660 return 1;
8661 }
8662
8663 static char *
8664 i386_scale (char *scale)
8665 {
8666 offsetT val;
8667 char *save = input_line_pointer;
8668
8669 input_line_pointer = scale;
8670 val = get_absolute_expression ();
8671
8672 switch (val)
8673 {
8674 case 1:
8675 i.log2_scale_factor = 0;
8676 break;
8677 case 2:
8678 i.log2_scale_factor = 1;
8679 break;
8680 case 4:
8681 i.log2_scale_factor = 2;
8682 break;
8683 case 8:
8684 i.log2_scale_factor = 3;
8685 break;
8686 default:
8687 {
8688 char sep = *input_line_pointer;
8689
8690 *input_line_pointer = '\0';
8691 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8692 scale);
8693 *input_line_pointer = sep;
8694 input_line_pointer = save;
8695 return NULL;
8696 }
8697 }
8698 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8699 {
8700 as_warn (_("scale factor of %d without an index register"),
8701 1 << i.log2_scale_factor);
8702 i.log2_scale_factor = 0;
8703 }
8704 scale = input_line_pointer;
8705 input_line_pointer = save;
8706 return scale;
8707 }
8708
8709 static int
8710 i386_displacement (char *disp_start, char *disp_end)
8711 {
8712 expressionS *exp;
8713 segT exp_seg = 0;
8714 char *save_input_line_pointer;
8715 char *gotfree_input_line;
8716 int override;
8717 i386_operand_type bigdisp, types = anydisp;
8718 int ret;
8719
8720 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8721 {
8722 as_bad (_("at most %d displacement operands are allowed"),
8723 MAX_MEMORY_OPERANDS);
8724 return 0;
8725 }
8726
8727 operand_type_set (&bigdisp, 0);
8728 if ((i.types[this_operand].bitfield.jumpabsolute)
8729 || (!current_templates->start->opcode_modifier.jump
8730 && !current_templates->start->opcode_modifier.jumpdword))
8731 {
8732 bigdisp.bitfield.disp32 = 1;
8733 override = (i.prefix[ADDR_PREFIX] != 0);
8734 if (flag_code == CODE_64BIT)
8735 {
8736 if (!override)
8737 {
8738 bigdisp.bitfield.disp32s = 1;
8739 bigdisp.bitfield.disp64 = 1;
8740 }
8741 }
8742 else if ((flag_code == CODE_16BIT) ^ override)
8743 {
8744 bigdisp.bitfield.disp32 = 0;
8745 bigdisp.bitfield.disp16 = 1;
8746 }
8747 }
8748 else
8749 {
8750 /* For PC-relative branches, the width of the displacement
8751 is dependent upon data size, not address size. */
8752 override = (i.prefix[DATA_PREFIX] != 0);
8753 if (flag_code == CODE_64BIT)
8754 {
8755 if (override || i.suffix == WORD_MNEM_SUFFIX)
8756 bigdisp.bitfield.disp16 = 1;
8757 else
8758 {
8759 bigdisp.bitfield.disp32 = 1;
8760 bigdisp.bitfield.disp32s = 1;
8761 }
8762 }
8763 else
8764 {
8765 if (!override)
8766 override = (i.suffix == (flag_code != CODE_16BIT
8767 ? WORD_MNEM_SUFFIX
8768 : LONG_MNEM_SUFFIX));
8769 bigdisp.bitfield.disp32 = 1;
8770 if ((flag_code == CODE_16BIT) ^ override)
8771 {
8772 bigdisp.bitfield.disp32 = 0;
8773 bigdisp.bitfield.disp16 = 1;
8774 }
8775 }
8776 }
8777 i.types[this_operand] = operand_type_or (i.types[this_operand],
8778 bigdisp);
8779
8780 exp = &disp_expressions[i.disp_operands];
8781 i.op[this_operand].disps = exp;
8782 i.disp_operands++;
8783 save_input_line_pointer = input_line_pointer;
8784 input_line_pointer = disp_start;
8785 END_STRING_AND_SAVE (disp_end);
8786
8787 #ifndef GCC_ASM_O_HACK
8788 #define GCC_ASM_O_HACK 0
8789 #endif
8790 #if GCC_ASM_O_HACK
8791 END_STRING_AND_SAVE (disp_end + 1);
8792 if (i.types[this_operand].bitfield.baseIndex
8793 && displacement_string_end[-1] == '+')
8794 {
8795 /* This hack is to avoid a warning when using the "o"
8796 constraint within gcc asm statements.
8797 For instance:
8798
8799 #define _set_tssldt_desc(n,addr,limit,type) \
8800 __asm__ __volatile__ ( \
8801 "movw %w2,%0\n\t" \
8802 "movw %w1,2+%0\n\t" \
8803 "rorl $16,%1\n\t" \
8804 "movb %b1,4+%0\n\t" \
8805 "movb %4,5+%0\n\t" \
8806 "movb $0,6+%0\n\t" \
8807 "movb %h1,7+%0\n\t" \
8808 "rorl $16,%1" \
8809 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8810
8811 This works great except that the output assembler ends
8812 up looking a bit weird if it turns out that there is
8813 no offset. You end up producing code that looks like:
8814
8815 #APP
8816 movw $235,(%eax)
8817 movw %dx,2+(%eax)
8818 rorl $16,%edx
8819 movb %dl,4+(%eax)
8820 movb $137,5+(%eax)
8821 movb $0,6+(%eax)
8822 movb %dh,7+(%eax)
8823 rorl $16,%edx
8824 #NO_APP
8825
8826 So here we provide the missing zero. */
8827
8828 *displacement_string_end = '0';
8829 }
8830 #endif
8831 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8832 if (gotfree_input_line)
8833 input_line_pointer = gotfree_input_line;
8834
8835 exp_seg = expression (exp);
8836
8837 SKIP_WHITESPACE ();
8838 if (*input_line_pointer)
8839 as_bad (_("junk `%s' after expression"), input_line_pointer);
8840 #if GCC_ASM_O_HACK
8841 RESTORE_END_STRING (disp_end + 1);
8842 #endif
8843 input_line_pointer = save_input_line_pointer;
8844 if (gotfree_input_line)
8845 {
8846 free (gotfree_input_line);
8847
8848 if (exp->X_op == O_constant || exp->X_op == O_register)
8849 exp->X_op = O_illegal;
8850 }
8851
8852 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8853
8854 RESTORE_END_STRING (disp_end);
8855
8856 return ret;
8857 }
8858
8859 static int
8860 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8861 i386_operand_type types, const char *disp_start)
8862 {
8863 i386_operand_type bigdisp;
8864 int ret = 1;
8865
8866 /* We do this to make sure that the section symbol is in
8867 the symbol table. We will ultimately change the relocation
8868 to be relative to the beginning of the section. */
8869 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8870 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8871 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8872 {
8873 if (exp->X_op != O_symbol)
8874 goto inv_disp;
8875
8876 if (S_IS_LOCAL (exp->X_add_symbol)
8877 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8878 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8879 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8880 exp->X_op = O_subtract;
8881 exp->X_op_symbol = GOT_symbol;
8882 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8883 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8884 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8885 i.reloc[this_operand] = BFD_RELOC_64;
8886 else
8887 i.reloc[this_operand] = BFD_RELOC_32;
8888 }
8889
8890 else if (exp->X_op == O_absent
8891 || exp->X_op == O_illegal
8892 || exp->X_op == O_big)
8893 {
8894 inv_disp:
8895 as_bad (_("missing or invalid displacement expression `%s'"),
8896 disp_start);
8897 ret = 0;
8898 }
8899
8900 else if (flag_code == CODE_64BIT
8901 && !i.prefix[ADDR_PREFIX]
8902 && exp->X_op == O_constant)
8903 {
8904 /* Since displacement is signed extended to 64bit, don't allow
8905 disp32 and turn off disp32s if they are out of range. */
8906 i.types[this_operand].bitfield.disp32 = 0;
8907 if (!fits_in_signed_long (exp->X_add_number))
8908 {
8909 i.types[this_operand].bitfield.disp32s = 0;
8910 if (i.types[this_operand].bitfield.baseindex)
8911 {
8912 as_bad (_("0x%lx out range of signed 32bit displacement"),
8913 (long) exp->X_add_number);
8914 ret = 0;
8915 }
8916 }
8917 }
8918
8919 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8920 else if (exp->X_op != O_constant
8921 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8922 && exp_seg != absolute_section
8923 && exp_seg != text_section
8924 && exp_seg != data_section
8925 && exp_seg != bss_section
8926 && exp_seg != undefined_section
8927 && !bfd_is_com_section (exp_seg))
8928 {
8929 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8930 ret = 0;
8931 }
8932 #endif
8933
8934 /* Check if this is a displacement only operand. */
8935 bigdisp = i.types[this_operand];
8936 bigdisp.bitfield.disp8 = 0;
8937 bigdisp.bitfield.disp16 = 0;
8938 bigdisp.bitfield.disp32 = 0;
8939 bigdisp.bitfield.disp32s = 0;
8940 bigdisp.bitfield.disp64 = 0;
8941 if (operand_type_all_zero (&bigdisp))
8942 i.types[this_operand] = operand_type_and (i.types[this_operand],
8943 types);
8944
8945 return ret;
8946 }
8947
8948 /* Return the active addressing mode, taking address override and
8949 registers forming the address into consideration. Update the
8950 address override prefix if necessary. */
8951
8952 static enum flag_code
8953 i386_addressing_mode (void)
8954 {
8955 enum flag_code addr_mode;
8956
8957 if (i.prefix[ADDR_PREFIX])
8958 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8959 else
8960 {
8961 addr_mode = flag_code;
8962
8963 #if INFER_ADDR_PREFIX
8964 if (i.mem_operands == 0)
8965 {
8966 /* Infer address prefix from the first memory operand. */
8967 const reg_entry *addr_reg = i.base_reg;
8968
8969 if (addr_reg == NULL)
8970 addr_reg = i.index_reg;
8971
8972 if (addr_reg)
8973 {
8974 if (addr_reg->reg_num == RegEip
8975 || addr_reg->reg_num == RegEiz
8976 || addr_reg->reg_type.bitfield.dword)
8977 addr_mode = CODE_32BIT;
8978 else if (flag_code != CODE_64BIT
8979 && addr_reg->reg_type.bitfield.word)
8980 addr_mode = CODE_16BIT;
8981
8982 if (addr_mode != flag_code)
8983 {
8984 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8985 i.prefixes += 1;
8986 /* Change the size of any displacement too. At most one
8987 of Disp16 or Disp32 is set.
8988 FIXME. There doesn't seem to be any real need for
8989 separate Disp16 and Disp32 flags. The same goes for
8990 Imm16 and Imm32. Removing them would probably clean
8991 up the code quite a lot. */
8992 if (flag_code != CODE_64BIT
8993 && (i.types[this_operand].bitfield.disp16
8994 || i.types[this_operand].bitfield.disp32))
8995 i.types[this_operand]
8996 = operand_type_xor (i.types[this_operand], disp16_32);
8997 }
8998 }
8999 }
9000 #endif
9001 }
9002
9003 return addr_mode;
9004 }
9005
9006 /* Make sure the memory operand we've been dealt is valid.
9007 Return 1 on success, 0 on a failure. */
9008
9009 static int
9010 i386_index_check (const char *operand_string)
9011 {
9012 const char *kind = "base/index";
9013 enum flag_code addr_mode = i386_addressing_mode ();
9014
9015 if (current_templates->start->opcode_modifier.isstring
9016 && !current_templates->start->opcode_modifier.immext
9017 && (current_templates->end[-1].opcode_modifier.isstring
9018 || i.mem_operands))
9019 {
9020 /* Memory operands of string insns are special in that they only allow
9021 a single register (rDI, rSI, or rBX) as their memory address. */
9022 const reg_entry *expected_reg;
9023 static const char *di_si[][2] =
9024 {
9025 { "esi", "edi" },
9026 { "si", "di" },
9027 { "rsi", "rdi" }
9028 };
9029 static const char *bx[] = { "ebx", "bx", "rbx" };
9030
9031 kind = "string address";
9032
9033 if (current_templates->start->opcode_modifier.repprefixok)
9034 {
9035 i386_operand_type type = current_templates->end[-1].operand_types[0];
9036
9037 if (!type.bitfield.baseindex
9038 || ((!i.mem_operands != !intel_syntax)
9039 && current_templates->end[-1].operand_types[1]
9040 .bitfield.baseindex))
9041 type = current_templates->end[-1].operand_types[1];
9042 expected_reg = hash_find (reg_hash,
9043 di_si[addr_mode][type.bitfield.esseg]);
9044
9045 }
9046 else
9047 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9048
9049 if (i.base_reg != expected_reg
9050 || i.index_reg
9051 || operand_type_check (i.types[this_operand], disp))
9052 {
9053 /* The second memory operand must have the same size as
9054 the first one. */
9055 if (i.mem_operands
9056 && i.base_reg
9057 && !((addr_mode == CODE_64BIT
9058 && i.base_reg->reg_type.bitfield.qword)
9059 || (addr_mode == CODE_32BIT
9060 ? i.base_reg->reg_type.bitfield.dword
9061 : i.base_reg->reg_type.bitfield.word)))
9062 goto bad_address;
9063
9064 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9065 operand_string,
9066 intel_syntax ? '[' : '(',
9067 register_prefix,
9068 expected_reg->reg_name,
9069 intel_syntax ? ']' : ')');
9070 return 1;
9071 }
9072 else
9073 return 1;
9074
9075 bad_address:
9076 as_bad (_("`%s' is not a valid %s expression"),
9077 operand_string, kind);
9078 return 0;
9079 }
9080 else
9081 {
9082 if (addr_mode != CODE_16BIT)
9083 {
9084 /* 32-bit/64-bit checks. */
9085 if ((i.base_reg
9086 && (addr_mode == CODE_64BIT
9087 ? !i.base_reg->reg_type.bitfield.qword
9088 : !i.base_reg->reg_type.bitfield.dword)
9089 && (i.index_reg
9090 || (i.base_reg->reg_num
9091 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9092 || (i.index_reg
9093 && !i.index_reg->reg_type.bitfield.xmmword
9094 && !i.index_reg->reg_type.bitfield.ymmword
9095 && !i.index_reg->reg_type.bitfield.zmmword
9096 && ((addr_mode == CODE_64BIT
9097 ? !(i.index_reg->reg_type.bitfield.qword
9098 || i.index_reg->reg_num == RegRiz)
9099 : !(i.index_reg->reg_type.bitfield.dword
9100 || i.index_reg->reg_num == RegEiz))
9101 || !i.index_reg->reg_type.bitfield.baseindex)))
9102 goto bad_address;
9103
9104 /* bndmk, bndldx, and bndstx have special restrictions. */
9105 if (current_templates->start->base_opcode == 0xf30f1b
9106 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9107 {
9108 /* They cannot use RIP-relative addressing. */
9109 if (i.base_reg && i.base_reg->reg_num == RegRip)
9110 {
9111 as_bad (_("`%s' cannot be used here"), operand_string);
9112 return 0;
9113 }
9114
9115 /* bndldx and bndstx ignore their scale factor. */
9116 if (current_templates->start->base_opcode != 0xf30f1b
9117 && i.log2_scale_factor)
9118 as_warn (_("register scaling is being ignored here"));
9119 }
9120 }
9121 else
9122 {
9123 /* 16-bit checks. */
9124 if ((i.base_reg
9125 && (!i.base_reg->reg_type.bitfield.word
9126 || !i.base_reg->reg_type.bitfield.baseindex))
9127 || (i.index_reg
9128 && (!i.index_reg->reg_type.bitfield.word
9129 || !i.index_reg->reg_type.bitfield.baseindex
9130 || !(i.base_reg
9131 && i.base_reg->reg_num < 6
9132 && i.index_reg->reg_num >= 6
9133 && i.log2_scale_factor == 0))))
9134 goto bad_address;
9135 }
9136 }
9137 return 1;
9138 }
9139
9140 /* Handle vector immediates. */
9141
9142 static int
9143 RC_SAE_immediate (const char *imm_start)
9144 {
9145 unsigned int match_found, j;
9146 const char *pstr = imm_start;
9147 expressionS *exp;
9148
9149 if (*pstr != '{')
9150 return 0;
9151
9152 pstr++;
9153 match_found = 0;
9154 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9155 {
9156 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9157 {
9158 if (!i.rounding)
9159 {
9160 rc_op.type = RC_NamesTable[j].type;
9161 rc_op.operand = this_operand;
9162 i.rounding = &rc_op;
9163 }
9164 else
9165 {
9166 as_bad (_("duplicated `%s'"), imm_start);
9167 return 0;
9168 }
9169 pstr += RC_NamesTable[j].len;
9170 match_found = 1;
9171 break;
9172 }
9173 }
9174 if (!match_found)
9175 return 0;
9176
9177 if (*pstr++ != '}')
9178 {
9179 as_bad (_("Missing '}': '%s'"), imm_start);
9180 return 0;
9181 }
9182 /* RC/SAE immediate string should contain nothing more. */;
9183 if (*pstr != 0)
9184 {
9185 as_bad (_("Junk after '}': '%s'"), imm_start);
9186 return 0;
9187 }
9188
9189 exp = &im_expressions[i.imm_operands++];
9190 i.op[this_operand].imms = exp;
9191
9192 exp->X_op = O_constant;
9193 exp->X_add_number = 0;
9194 exp->X_add_symbol = (symbolS *) 0;
9195 exp->X_op_symbol = (symbolS *) 0;
9196
9197 i.types[this_operand].bitfield.imm8 = 1;
9198 return 1;
9199 }
9200
9201 /* Only string instructions can have a second memory operand, so
9202 reduce current_templates to just those if it contains any. */
9203 static int
9204 maybe_adjust_templates (void)
9205 {
9206 const insn_template *t;
9207
9208 gas_assert (i.mem_operands == 1);
9209
9210 for (t = current_templates->start; t < current_templates->end; ++t)
9211 if (t->opcode_modifier.isstring)
9212 break;
9213
9214 if (t < current_templates->end)
9215 {
9216 static templates aux_templates;
9217 bfd_boolean recheck;
9218
9219 aux_templates.start = t;
9220 for (; t < current_templates->end; ++t)
9221 if (!t->opcode_modifier.isstring)
9222 break;
9223 aux_templates.end = t;
9224
9225 /* Determine whether to re-check the first memory operand. */
9226 recheck = (aux_templates.start != current_templates->start
9227 || t != current_templates->end);
9228
9229 current_templates = &aux_templates;
9230
9231 if (recheck)
9232 {
9233 i.mem_operands = 0;
9234 if (i.memop1_string != NULL
9235 && i386_index_check (i.memop1_string) == 0)
9236 return 0;
9237 i.mem_operands = 1;
9238 }
9239 }
9240
9241 return 1;
9242 }
9243
9244 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9245 on error. */
9246
9247 static int
9248 i386_att_operand (char *operand_string)
9249 {
9250 const reg_entry *r;
9251 char *end_op;
9252 char *op_string = operand_string;
9253
9254 if (is_space_char (*op_string))
9255 ++op_string;
9256
9257 /* We check for an absolute prefix (differentiating,
9258 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9259 if (*op_string == ABSOLUTE_PREFIX)
9260 {
9261 ++op_string;
9262 if (is_space_char (*op_string))
9263 ++op_string;
9264 i.types[this_operand].bitfield.jumpabsolute = 1;
9265 }
9266
9267 /* Check if operand is a register. */
9268 if ((r = parse_register (op_string, &end_op)) != NULL)
9269 {
9270 i386_operand_type temp;
9271
9272 /* Check for a segment override by searching for ':' after a
9273 segment register. */
9274 op_string = end_op;
9275 if (is_space_char (*op_string))
9276 ++op_string;
9277 if (*op_string == ':'
9278 && (r->reg_type.bitfield.sreg2
9279 || r->reg_type.bitfield.sreg3))
9280 {
9281 switch (r->reg_num)
9282 {
9283 case 0:
9284 i.seg[i.mem_operands] = &es;
9285 break;
9286 case 1:
9287 i.seg[i.mem_operands] = &cs;
9288 break;
9289 case 2:
9290 i.seg[i.mem_operands] = &ss;
9291 break;
9292 case 3:
9293 i.seg[i.mem_operands] = &ds;
9294 break;
9295 case 4:
9296 i.seg[i.mem_operands] = &fs;
9297 break;
9298 case 5:
9299 i.seg[i.mem_operands] = &gs;
9300 break;
9301 }
9302
9303 /* Skip the ':' and whitespace. */
9304 ++op_string;
9305 if (is_space_char (*op_string))
9306 ++op_string;
9307
9308 if (!is_digit_char (*op_string)
9309 && !is_identifier_char (*op_string)
9310 && *op_string != '('
9311 && *op_string != ABSOLUTE_PREFIX)
9312 {
9313 as_bad (_("bad memory operand `%s'"), op_string);
9314 return 0;
9315 }
9316 /* Handle case of %es:*foo. */
9317 if (*op_string == ABSOLUTE_PREFIX)
9318 {
9319 ++op_string;
9320 if (is_space_char (*op_string))
9321 ++op_string;
9322 i.types[this_operand].bitfield.jumpabsolute = 1;
9323 }
9324 goto do_memory_reference;
9325 }
9326
9327 /* Handle vector operations. */
9328 if (*op_string == '{')
9329 {
9330 op_string = check_VecOperations (op_string, NULL);
9331 if (op_string == NULL)
9332 return 0;
9333 }
9334
9335 if (*op_string)
9336 {
9337 as_bad (_("junk `%s' after register"), op_string);
9338 return 0;
9339 }
9340 temp = r->reg_type;
9341 temp.bitfield.baseindex = 0;
9342 i.types[this_operand] = operand_type_or (i.types[this_operand],
9343 temp);
9344 i.types[this_operand].bitfield.unspecified = 0;
9345 i.op[this_operand].regs = r;
9346 i.reg_operands++;
9347 }
9348 else if (*op_string == REGISTER_PREFIX)
9349 {
9350 as_bad (_("bad register name `%s'"), op_string);
9351 return 0;
9352 }
9353 else if (*op_string == IMMEDIATE_PREFIX)
9354 {
9355 ++op_string;
9356 if (i.types[this_operand].bitfield.jumpabsolute)
9357 {
9358 as_bad (_("immediate operand illegal with absolute jump"));
9359 return 0;
9360 }
9361 if (!i386_immediate (op_string))
9362 return 0;
9363 }
9364 else if (RC_SAE_immediate (operand_string))
9365 {
9366 /* If it is a RC or SAE immediate, do nothing. */
9367 ;
9368 }
9369 else if (is_digit_char (*op_string)
9370 || is_identifier_char (*op_string)
9371 || *op_string == '"'
9372 || *op_string == '(')
9373 {
9374 /* This is a memory reference of some sort. */
9375 char *base_string;
9376
9377 /* Start and end of displacement string expression (if found). */
9378 char *displacement_string_start;
9379 char *displacement_string_end;
9380 char *vop_start;
9381
9382 do_memory_reference:
9383 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9384 return 0;
9385 if ((i.mem_operands == 1
9386 && !current_templates->start->opcode_modifier.isstring)
9387 || i.mem_operands == 2)
9388 {
9389 as_bad (_("too many memory references for `%s'"),
9390 current_templates->start->name);
9391 return 0;
9392 }
9393
9394 /* Check for base index form. We detect the base index form by
9395 looking for an ')' at the end of the operand, searching
9396 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9397 after the '('. */
9398 base_string = op_string + strlen (op_string);
9399
9400 /* Handle vector operations. */
9401 vop_start = strchr (op_string, '{');
9402 if (vop_start && vop_start < base_string)
9403 {
9404 if (check_VecOperations (vop_start, base_string) == NULL)
9405 return 0;
9406 base_string = vop_start;
9407 }
9408
9409 --base_string;
9410 if (is_space_char (*base_string))
9411 --base_string;
9412
9413 /* If we only have a displacement, set-up for it to be parsed later. */
9414 displacement_string_start = op_string;
9415 displacement_string_end = base_string + 1;
9416
9417 if (*base_string == ')')
9418 {
9419 char *temp_string;
9420 unsigned int parens_balanced = 1;
9421 /* We've already checked that the number of left & right ()'s are
9422 equal, so this loop will not be infinite. */
9423 do
9424 {
9425 base_string--;
9426 if (*base_string == ')')
9427 parens_balanced++;
9428 if (*base_string == '(')
9429 parens_balanced--;
9430 }
9431 while (parens_balanced);
9432
9433 temp_string = base_string;
9434
9435 /* Skip past '(' and whitespace. */
9436 ++base_string;
9437 if (is_space_char (*base_string))
9438 ++base_string;
9439
9440 if (*base_string == ','
9441 || ((i.base_reg = parse_register (base_string, &end_op))
9442 != NULL))
9443 {
9444 displacement_string_end = temp_string;
9445
9446 i.types[this_operand].bitfield.baseindex = 1;
9447
9448 if (i.base_reg)
9449 {
9450 base_string = end_op;
9451 if (is_space_char (*base_string))
9452 ++base_string;
9453 }
9454
9455 /* There may be an index reg or scale factor here. */
9456 if (*base_string == ',')
9457 {
9458 ++base_string;
9459 if (is_space_char (*base_string))
9460 ++base_string;
9461
9462 if ((i.index_reg = parse_register (base_string, &end_op))
9463 != NULL)
9464 {
9465 base_string = end_op;
9466 if (is_space_char (*base_string))
9467 ++base_string;
9468 if (*base_string == ',')
9469 {
9470 ++base_string;
9471 if (is_space_char (*base_string))
9472 ++base_string;
9473 }
9474 else if (*base_string != ')')
9475 {
9476 as_bad (_("expecting `,' or `)' "
9477 "after index register in `%s'"),
9478 operand_string);
9479 return 0;
9480 }
9481 }
9482 else if (*base_string == REGISTER_PREFIX)
9483 {
9484 end_op = strchr (base_string, ',');
9485 if (end_op)
9486 *end_op = '\0';
9487 as_bad (_("bad register name `%s'"), base_string);
9488 return 0;
9489 }
9490
9491 /* Check for scale factor. */
9492 if (*base_string != ')')
9493 {
9494 char *end_scale = i386_scale (base_string);
9495
9496 if (!end_scale)
9497 return 0;
9498
9499 base_string = end_scale;
9500 if (is_space_char (*base_string))
9501 ++base_string;
9502 if (*base_string != ')')
9503 {
9504 as_bad (_("expecting `)' "
9505 "after scale factor in `%s'"),
9506 operand_string);
9507 return 0;
9508 }
9509 }
9510 else if (!i.index_reg)
9511 {
9512 as_bad (_("expecting index register or scale factor "
9513 "after `,'; got '%c'"),
9514 *base_string);
9515 return 0;
9516 }
9517 }
9518 else if (*base_string != ')')
9519 {
9520 as_bad (_("expecting `,' or `)' "
9521 "after base register in `%s'"),
9522 operand_string);
9523 return 0;
9524 }
9525 }
9526 else if (*base_string == REGISTER_PREFIX)
9527 {
9528 end_op = strchr (base_string, ',');
9529 if (end_op)
9530 *end_op = '\0';
9531 as_bad (_("bad register name `%s'"), base_string);
9532 return 0;
9533 }
9534 }
9535
9536 /* If there's an expression beginning the operand, parse it,
9537 assuming displacement_string_start and
9538 displacement_string_end are meaningful. */
9539 if (displacement_string_start != displacement_string_end)
9540 {
9541 if (!i386_displacement (displacement_string_start,
9542 displacement_string_end))
9543 return 0;
9544 }
9545
9546 /* Special case for (%dx) while doing input/output op. */
9547 if (i.base_reg
9548 && operand_type_equal (&i.base_reg->reg_type,
9549 &reg16_inoutportreg)
9550 && i.index_reg == 0
9551 && i.log2_scale_factor == 0
9552 && i.seg[i.mem_operands] == 0
9553 && !operand_type_check (i.types[this_operand], disp))
9554 {
9555 i.types[this_operand] = inoutportreg;
9556 return 1;
9557 }
9558
9559 if (i386_index_check (operand_string) == 0)
9560 return 0;
9561 i.types[this_operand].bitfield.mem = 1;
9562 if (i.mem_operands == 0)
9563 i.memop1_string = xstrdup (operand_string);
9564 i.mem_operands++;
9565 }
9566 else
9567 {
9568 /* It's not a memory operand; argh! */
9569 as_bad (_("invalid char %s beginning operand %d `%s'"),
9570 output_invalid (*op_string),
9571 this_operand + 1,
9572 op_string);
9573 return 0;
9574 }
9575 return 1; /* Normal return. */
9576 }
9577 \f
9578 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9579 that an rs_machine_dependent frag may reach. */
9580
9581 unsigned int
9582 i386_frag_max_var (fragS *frag)
9583 {
9584 /* The only relaxable frags are for jumps.
9585 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9586 gas_assert (frag->fr_type == rs_machine_dependent);
9587 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9588 }
9589
9590 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9591 static int
9592 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9593 {
9594 /* STT_GNU_IFUNC symbol must go through PLT. */
9595 if ((symbol_get_bfdsym (fr_symbol)->flags
9596 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9597 return 0;
9598
9599 if (!S_IS_EXTERNAL (fr_symbol))
9600 /* Symbol may be weak or local. */
9601 return !S_IS_WEAK (fr_symbol);
9602
9603 /* Global symbols with non-default visibility can't be preempted. */
9604 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9605 return 1;
9606
9607 if (fr_var != NO_RELOC)
9608 switch ((enum bfd_reloc_code_real) fr_var)
9609 {
9610 case BFD_RELOC_386_PLT32:
9611 case BFD_RELOC_X86_64_PLT32:
9612 /* Symbol with PLT relocation may be preempted. */
9613 return 0;
9614 default:
9615 abort ();
9616 }
9617
9618 /* Global symbols with default visibility in a shared library may be
9619 preempted by another definition. */
9620 return !shared;
9621 }
9622 #endif
9623
9624 /* md_estimate_size_before_relax()
9625
9626 Called just before relax() for rs_machine_dependent frags. The x86
9627 assembler uses these frags to handle variable size jump
9628 instructions.
9629
9630 Any symbol that is now undefined will not become defined.
9631 Return the correct fr_subtype in the frag.
9632 Return the initial "guess for variable size of frag" to caller.
9633 The guess is actually the growth beyond the fixed part. Whatever
9634 we do to grow the fixed or variable part contributes to our
9635 returned value. */
9636
9637 int
9638 md_estimate_size_before_relax (fragS *fragP, segT segment)
9639 {
9640 /* We've already got fragP->fr_subtype right; all we have to do is
9641 check for un-relaxable symbols. On an ELF system, we can't relax
9642 an externally visible symbol, because it may be overridden by a
9643 shared library. */
9644 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9646 || (IS_ELF
9647 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9648 fragP->fr_var))
9649 #endif
9650 #if defined (OBJ_COFF) && defined (TE_PE)
9651 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9652 && S_IS_WEAK (fragP->fr_symbol))
9653 #endif
9654 )
9655 {
9656 /* Symbol is undefined in this segment, or we need to keep a
9657 reloc so that weak symbols can be overridden. */
9658 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9659 enum bfd_reloc_code_real reloc_type;
9660 unsigned char *opcode;
9661 int old_fr_fix;
9662
9663 if (fragP->fr_var != NO_RELOC)
9664 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9665 else if (size == 2)
9666 reloc_type = BFD_RELOC_16_PCREL;
9667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9668 else if (need_plt32_p (fragP->fr_symbol))
9669 reloc_type = BFD_RELOC_X86_64_PLT32;
9670 #endif
9671 else
9672 reloc_type = BFD_RELOC_32_PCREL;
9673
9674 old_fr_fix = fragP->fr_fix;
9675 opcode = (unsigned char *) fragP->fr_opcode;
9676
9677 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9678 {
9679 case UNCOND_JUMP:
9680 /* Make jmp (0xeb) a (d)word displacement jump. */
9681 opcode[0] = 0xe9;
9682 fragP->fr_fix += size;
9683 fix_new (fragP, old_fr_fix, size,
9684 fragP->fr_symbol,
9685 fragP->fr_offset, 1,
9686 reloc_type);
9687 break;
9688
9689 case COND_JUMP86:
9690 if (size == 2
9691 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9692 {
9693 /* Negate the condition, and branch past an
9694 unconditional jump. */
9695 opcode[0] ^= 1;
9696 opcode[1] = 3;
9697 /* Insert an unconditional jump. */
9698 opcode[2] = 0xe9;
9699 /* We added two extra opcode bytes, and have a two byte
9700 offset. */
9701 fragP->fr_fix += 2 + 2;
9702 fix_new (fragP, old_fr_fix + 2, 2,
9703 fragP->fr_symbol,
9704 fragP->fr_offset, 1,
9705 reloc_type);
9706 break;
9707 }
9708 /* Fall through. */
9709
9710 case COND_JUMP:
9711 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9712 {
9713 fixS *fixP;
9714
9715 fragP->fr_fix += 1;
9716 fixP = fix_new (fragP, old_fr_fix, 1,
9717 fragP->fr_symbol,
9718 fragP->fr_offset, 1,
9719 BFD_RELOC_8_PCREL);
9720 fixP->fx_signed = 1;
9721 break;
9722 }
9723
9724 /* This changes the byte-displacement jump 0x7N
9725 to the (d)word-displacement jump 0x0f,0x8N. */
9726 opcode[1] = opcode[0] + 0x10;
9727 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9728 /* We've added an opcode byte. */
9729 fragP->fr_fix += 1 + size;
9730 fix_new (fragP, old_fr_fix + 1, size,
9731 fragP->fr_symbol,
9732 fragP->fr_offset, 1,
9733 reloc_type);
9734 break;
9735
9736 default:
9737 BAD_CASE (fragP->fr_subtype);
9738 break;
9739 }
9740 frag_wane (fragP);
9741 return fragP->fr_fix - old_fr_fix;
9742 }
9743
9744 /* Guess size depending on current relax state. Initially the relax
9745 state will correspond to a short jump and we return 1, because
9746 the variable part of the frag (the branch offset) is one byte
9747 long. However, we can relax a section more than once and in that
9748 case we must either set fr_subtype back to the unrelaxed state,
9749 or return the value for the appropriate branch. */
9750 return md_relax_table[fragP->fr_subtype].rlx_length;
9751 }
9752
9753 /* Called after relax() is finished.
9754
9755 In: Address of frag.
9756 fr_type == rs_machine_dependent.
9757 fr_subtype is what the address relaxed to.
9758
9759 Out: Any fixSs and constants are set up.
9760 Caller will turn frag into a ".space 0". */
9761
9762 void
9763 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9764 fragS *fragP)
9765 {
9766 unsigned char *opcode;
9767 unsigned char *where_to_put_displacement = NULL;
9768 offsetT target_address;
9769 offsetT opcode_address;
9770 unsigned int extension = 0;
9771 offsetT displacement_from_opcode_start;
9772
9773 opcode = (unsigned char *) fragP->fr_opcode;
9774
9775 /* Address we want to reach in file space. */
9776 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9777
9778 /* Address opcode resides at in file space. */
9779 opcode_address = fragP->fr_address + fragP->fr_fix;
9780
9781 /* Displacement from opcode start to fill into instruction. */
9782 displacement_from_opcode_start = target_address - opcode_address;
9783
9784 if ((fragP->fr_subtype & BIG) == 0)
9785 {
9786 /* Don't have to change opcode. */
9787 extension = 1; /* 1 opcode + 1 displacement */
9788 where_to_put_displacement = &opcode[1];
9789 }
9790 else
9791 {
9792 if (no_cond_jump_promotion
9793 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9794 as_warn_where (fragP->fr_file, fragP->fr_line,
9795 _("long jump required"));
9796
9797 switch (fragP->fr_subtype)
9798 {
9799 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9800 extension = 4; /* 1 opcode + 4 displacement */
9801 opcode[0] = 0xe9;
9802 where_to_put_displacement = &opcode[1];
9803 break;
9804
9805 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9806 extension = 2; /* 1 opcode + 2 displacement */
9807 opcode[0] = 0xe9;
9808 where_to_put_displacement = &opcode[1];
9809 break;
9810
9811 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9812 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9813 extension = 5; /* 2 opcode + 4 displacement */
9814 opcode[1] = opcode[0] + 0x10;
9815 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9816 where_to_put_displacement = &opcode[2];
9817 break;
9818
9819 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9820 extension = 3; /* 2 opcode + 2 displacement */
9821 opcode[1] = opcode[0] + 0x10;
9822 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9823 where_to_put_displacement = &opcode[2];
9824 break;
9825
9826 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9827 extension = 4;
9828 opcode[0] ^= 1;
9829 opcode[1] = 3;
9830 opcode[2] = 0xe9;
9831 where_to_put_displacement = &opcode[3];
9832 break;
9833
9834 default:
9835 BAD_CASE (fragP->fr_subtype);
9836 break;
9837 }
9838 }
9839
9840 /* If size if less then four we are sure that the operand fits,
9841 but if it's 4, then it could be that the displacement is larger
9842 then -/+ 2GB. */
9843 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9844 && object_64bit
9845 && ((addressT) (displacement_from_opcode_start - extension
9846 + ((addressT) 1 << 31))
9847 > (((addressT) 2 << 31) - 1)))
9848 {
9849 as_bad_where (fragP->fr_file, fragP->fr_line,
9850 _("jump target out of range"));
9851 /* Make us emit 0. */
9852 displacement_from_opcode_start = extension;
9853 }
9854 /* Now put displacement after opcode. */
9855 md_number_to_chars ((char *) where_to_put_displacement,
9856 (valueT) (displacement_from_opcode_start - extension),
9857 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9858 fragP->fr_fix += extension;
9859 }
9860 \f
9861 /* Apply a fixup (fixP) to segment data, once it has been determined
9862 by our caller that we have all the info we need to fix it up.
9863
9864 Parameter valP is the pointer to the value of the bits.
9865
9866 On the 386, immediates, displacements, and data pointers are all in
9867 the same (little-endian) format, so we don't need to care about which
9868 we are handling. */
9869
9870 void
9871 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9872 {
9873 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9874 valueT value = *valP;
9875
9876 #if !defined (TE_Mach)
9877 if (fixP->fx_pcrel)
9878 {
9879 switch (fixP->fx_r_type)
9880 {
9881 default:
9882 break;
9883
9884 case BFD_RELOC_64:
9885 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9886 break;
9887 case BFD_RELOC_32:
9888 case BFD_RELOC_X86_64_32S:
9889 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9890 break;
9891 case BFD_RELOC_16:
9892 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9893 break;
9894 case BFD_RELOC_8:
9895 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9896 break;
9897 }
9898 }
9899
9900 if (fixP->fx_addsy != NULL
9901 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9902 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9903 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9904 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9905 && !use_rela_relocations)
9906 {
9907 /* This is a hack. There should be a better way to handle this.
9908 This covers for the fact that bfd_install_relocation will
9909 subtract the current location (for partial_inplace, PC relative
9910 relocations); see more below. */
9911 #ifndef OBJ_AOUT
9912 if (IS_ELF
9913 #ifdef TE_PE
9914 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9915 #endif
9916 )
9917 value += fixP->fx_where + fixP->fx_frag->fr_address;
9918 #endif
9919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9920 if (IS_ELF)
9921 {
9922 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9923
9924 if ((sym_seg == seg
9925 || (symbol_section_p (fixP->fx_addsy)
9926 && sym_seg != absolute_section))
9927 && !generic_force_reloc (fixP))
9928 {
9929 /* Yes, we add the values in twice. This is because
9930 bfd_install_relocation subtracts them out again. I think
9931 bfd_install_relocation is broken, but I don't dare change
9932 it. FIXME. */
9933 value += fixP->fx_where + fixP->fx_frag->fr_address;
9934 }
9935 }
9936 #endif
9937 #if defined (OBJ_COFF) && defined (TE_PE)
9938 /* For some reason, the PE format does not store a
9939 section address offset for a PC relative symbol. */
9940 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9941 || S_IS_WEAK (fixP->fx_addsy))
9942 value += md_pcrel_from (fixP);
9943 #endif
9944 }
9945 #if defined (OBJ_COFF) && defined (TE_PE)
9946 if (fixP->fx_addsy != NULL
9947 && S_IS_WEAK (fixP->fx_addsy)
9948 /* PR 16858: Do not modify weak function references. */
9949 && ! fixP->fx_pcrel)
9950 {
9951 #if !defined (TE_PEP)
9952 /* For x86 PE weak function symbols are neither PC-relative
9953 nor do they set S_IS_FUNCTION. So the only reliable way
9954 to detect them is to check the flags of their containing
9955 section. */
9956 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9957 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9958 ;
9959 else
9960 #endif
9961 value -= S_GET_VALUE (fixP->fx_addsy);
9962 }
9963 #endif
9964
9965 /* Fix a few things - the dynamic linker expects certain values here,
9966 and we must not disappoint it. */
9967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9968 if (IS_ELF && fixP->fx_addsy)
9969 switch (fixP->fx_r_type)
9970 {
9971 case BFD_RELOC_386_PLT32:
9972 case BFD_RELOC_X86_64_PLT32:
9973 /* Make the jump instruction point to the address of the operand. At
9974 runtime we merely add the offset to the actual PLT entry. */
9975 value = -4;
9976 break;
9977
9978 case BFD_RELOC_386_TLS_GD:
9979 case BFD_RELOC_386_TLS_LDM:
9980 case BFD_RELOC_386_TLS_IE_32:
9981 case BFD_RELOC_386_TLS_IE:
9982 case BFD_RELOC_386_TLS_GOTIE:
9983 case BFD_RELOC_386_TLS_GOTDESC:
9984 case BFD_RELOC_X86_64_TLSGD:
9985 case BFD_RELOC_X86_64_TLSLD:
9986 case BFD_RELOC_X86_64_GOTTPOFF:
9987 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9988 value = 0; /* Fully resolved at runtime. No addend. */
9989 /* Fallthrough */
9990 case BFD_RELOC_386_TLS_LE:
9991 case BFD_RELOC_386_TLS_LDO_32:
9992 case BFD_RELOC_386_TLS_LE_32:
9993 case BFD_RELOC_X86_64_DTPOFF32:
9994 case BFD_RELOC_X86_64_DTPOFF64:
9995 case BFD_RELOC_X86_64_TPOFF32:
9996 case BFD_RELOC_X86_64_TPOFF64:
9997 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9998 break;
9999
10000 case BFD_RELOC_386_TLS_DESC_CALL:
10001 case BFD_RELOC_X86_64_TLSDESC_CALL:
10002 value = 0; /* Fully resolved at runtime. No addend. */
10003 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10004 fixP->fx_done = 0;
10005 return;
10006
10007 case BFD_RELOC_VTABLE_INHERIT:
10008 case BFD_RELOC_VTABLE_ENTRY:
10009 fixP->fx_done = 0;
10010 return;
10011
10012 default:
10013 break;
10014 }
10015 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10016 *valP = value;
10017 #endif /* !defined (TE_Mach) */
10018
10019 /* Are we finished with this relocation now? */
10020 if (fixP->fx_addsy == NULL)
10021 fixP->fx_done = 1;
10022 #if defined (OBJ_COFF) && defined (TE_PE)
10023 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10024 {
10025 fixP->fx_done = 0;
10026 /* Remember value for tc_gen_reloc. */
10027 fixP->fx_addnumber = value;
10028 /* Clear out the frag for now. */
10029 value = 0;
10030 }
10031 #endif
10032 else if (use_rela_relocations)
10033 {
10034 fixP->fx_no_overflow = 1;
10035 /* Remember value for tc_gen_reloc. */
10036 fixP->fx_addnumber = value;
10037 value = 0;
10038 }
10039
10040 md_number_to_chars (p, value, fixP->fx_size);
10041 }
10042 \f
10043 const char *
10044 md_atof (int type, char *litP, int *sizeP)
10045 {
10046 /* This outputs the LITTLENUMs in REVERSE order;
10047 in accord with the bigendian 386. */
10048 return ieee_md_atof (type, litP, sizeP, FALSE);
10049 }
10050 \f
10051 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10052
10053 static char *
10054 output_invalid (int c)
10055 {
10056 if (ISPRINT (c))
10057 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10058 "'%c'", c);
10059 else
10060 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10061 "(0x%x)", (unsigned char) c);
10062 return output_invalid_buf;
10063 }
10064
10065 /* REG_STRING starts *before* REGISTER_PREFIX. */
10066
10067 static const reg_entry *
10068 parse_real_register (char *reg_string, char **end_op)
10069 {
10070 char *s = reg_string;
10071 char *p;
10072 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10073 const reg_entry *r;
10074
10075 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10076 if (*s == REGISTER_PREFIX)
10077 ++s;
10078
10079 if (is_space_char (*s))
10080 ++s;
10081
10082 p = reg_name_given;
10083 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10084 {
10085 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10086 return (const reg_entry *) NULL;
10087 s++;
10088 }
10089
10090 /* For naked regs, make sure that we are not dealing with an identifier.
10091 This prevents confusing an identifier like `eax_var' with register
10092 `eax'. */
10093 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10094 return (const reg_entry *) NULL;
10095
10096 *end_op = s;
10097
10098 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10099
10100 /* Handle floating point regs, allowing spaces in the (i) part. */
10101 if (r == i386_regtab /* %st is first entry of table */)
10102 {
10103 if (is_space_char (*s))
10104 ++s;
10105 if (*s == '(')
10106 {
10107 ++s;
10108 if (is_space_char (*s))
10109 ++s;
10110 if (*s >= '0' && *s <= '7')
10111 {
10112 int fpr = *s - '0';
10113 ++s;
10114 if (is_space_char (*s))
10115 ++s;
10116 if (*s == ')')
10117 {
10118 *end_op = s + 1;
10119 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10120 know (r);
10121 return r + fpr;
10122 }
10123 }
10124 /* We have "%st(" then garbage. */
10125 return (const reg_entry *) NULL;
10126 }
10127 }
10128
10129 if (r == NULL || allow_pseudo_reg)
10130 return r;
10131
10132 if (operand_type_all_zero (&r->reg_type))
10133 return (const reg_entry *) NULL;
10134
10135 if ((r->reg_type.bitfield.dword
10136 || r->reg_type.bitfield.sreg3
10137 || r->reg_type.bitfield.control
10138 || r->reg_type.bitfield.debug
10139 || r->reg_type.bitfield.test)
10140 && !cpu_arch_flags.bitfield.cpui386)
10141 return (const reg_entry *) NULL;
10142
10143 if (r->reg_type.bitfield.tbyte
10144 && !cpu_arch_flags.bitfield.cpu8087
10145 && !cpu_arch_flags.bitfield.cpu287
10146 && !cpu_arch_flags.bitfield.cpu387)
10147 return (const reg_entry *) NULL;
10148
10149 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10150 return (const reg_entry *) NULL;
10151
10152 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10153 return (const reg_entry *) NULL;
10154
10155 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10156 return (const reg_entry *) NULL;
10157
10158 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10159 return (const reg_entry *) NULL;
10160
10161 if (r->reg_type.bitfield.regmask
10162 && !cpu_arch_flags.bitfield.cpuregmask)
10163 return (const reg_entry *) NULL;
10164
10165 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10166 if (!allow_index_reg
10167 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10168 return (const reg_entry *) NULL;
10169
10170 /* Upper 16 vector register is only available with VREX in 64bit
10171 mode. */
10172 if ((r->reg_flags & RegVRex))
10173 {
10174 if (i.vec_encoding == vex_encoding_default)
10175 i.vec_encoding = vex_encoding_evex;
10176
10177 if (!cpu_arch_flags.bitfield.cpuvrex
10178 || i.vec_encoding != vex_encoding_evex
10179 || flag_code != CODE_64BIT)
10180 return (const reg_entry *) NULL;
10181 }
10182
10183 if (((r->reg_flags & (RegRex64 | RegRex))
10184 || r->reg_type.bitfield.qword)
10185 && (!cpu_arch_flags.bitfield.cpulm
10186 || !operand_type_equal (&r->reg_type, &control))
10187 && flag_code != CODE_64BIT)
10188 return (const reg_entry *) NULL;
10189
10190 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10191 return (const reg_entry *) NULL;
10192
10193 return r;
10194 }
10195
10196 /* REG_STRING starts *before* REGISTER_PREFIX. */
10197
10198 static const reg_entry *
10199 parse_register (char *reg_string, char **end_op)
10200 {
10201 const reg_entry *r;
10202
10203 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10204 r = parse_real_register (reg_string, end_op);
10205 else
10206 r = NULL;
10207 if (!r)
10208 {
10209 char *save = input_line_pointer;
10210 char c;
10211 symbolS *symbolP;
10212
10213 input_line_pointer = reg_string;
10214 c = get_symbol_name (&reg_string);
10215 symbolP = symbol_find (reg_string);
10216 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10217 {
10218 const expressionS *e = symbol_get_value_expression (symbolP);
10219
10220 know (e->X_op == O_register);
10221 know (e->X_add_number >= 0
10222 && (valueT) e->X_add_number < i386_regtab_size);
10223 r = i386_regtab + e->X_add_number;
10224 if ((r->reg_flags & RegVRex))
10225 i.vec_encoding = vex_encoding_evex;
10226 *end_op = input_line_pointer;
10227 }
10228 *input_line_pointer = c;
10229 input_line_pointer = save;
10230 }
10231 return r;
10232 }
10233
10234 int
10235 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10236 {
10237 const reg_entry *r;
10238 char *end = input_line_pointer;
10239
10240 *end = *nextcharP;
10241 r = parse_register (name, &input_line_pointer);
10242 if (r && end <= input_line_pointer)
10243 {
10244 *nextcharP = *input_line_pointer;
10245 *input_line_pointer = 0;
10246 e->X_op = O_register;
10247 e->X_add_number = r - i386_regtab;
10248 return 1;
10249 }
10250 input_line_pointer = end;
10251 *end = 0;
10252 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10253 }
10254
10255 void
10256 md_operand (expressionS *e)
10257 {
10258 char *end;
10259 const reg_entry *r;
10260
10261 switch (*input_line_pointer)
10262 {
10263 case REGISTER_PREFIX:
10264 r = parse_real_register (input_line_pointer, &end);
10265 if (r)
10266 {
10267 e->X_op = O_register;
10268 e->X_add_number = r - i386_regtab;
10269 input_line_pointer = end;
10270 }
10271 break;
10272
10273 case '[':
10274 gas_assert (intel_syntax);
10275 end = input_line_pointer++;
10276 expression (e);
10277 if (*input_line_pointer == ']')
10278 {
10279 ++input_line_pointer;
10280 e->X_op_symbol = make_expr_symbol (e);
10281 e->X_add_symbol = NULL;
10282 e->X_add_number = 0;
10283 e->X_op = O_index;
10284 }
10285 else
10286 {
10287 e->X_op = O_absent;
10288 input_line_pointer = end;
10289 }
10290 break;
10291 }
10292 }
10293
10294 \f
10295 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10296 const char *md_shortopts = "kVQ:sqnO::";
10297 #else
10298 const char *md_shortopts = "qnO::";
10299 #endif
10300
10301 #define OPTION_32 (OPTION_MD_BASE + 0)
10302 #define OPTION_64 (OPTION_MD_BASE + 1)
10303 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10304 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10305 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10306 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10307 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10308 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10309 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10310 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10311 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10312 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10313 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10314 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10315 #define OPTION_X32 (OPTION_MD_BASE + 14)
10316 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10317 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10318 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10319 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10320 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10321 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10322 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10323 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10324 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10325 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10326 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10327
10328 struct option md_longopts[] =
10329 {
10330 {"32", no_argument, NULL, OPTION_32},
10331 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10332 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10333 {"64", no_argument, NULL, OPTION_64},
10334 #endif
10335 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10336 {"x32", no_argument, NULL, OPTION_X32},
10337 {"mshared", no_argument, NULL, OPTION_MSHARED},
10338 #endif
10339 {"divide", no_argument, NULL, OPTION_DIVIDE},
10340 {"march", required_argument, NULL, OPTION_MARCH},
10341 {"mtune", required_argument, NULL, OPTION_MTUNE},
10342 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10343 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10344 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10345 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10346 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10347 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10348 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10349 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10350 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10351 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10352 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10353 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10354 # if defined (TE_PE) || defined (TE_PEP)
10355 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10356 #endif
10357 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10358 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10359 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10360 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10361 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10362 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10363 {NULL, no_argument, NULL, 0}
10364 };
10365 size_t md_longopts_size = sizeof (md_longopts);
10366
10367 int
10368 md_parse_option (int c, const char *arg)
10369 {
10370 unsigned int j;
10371 char *arch, *next, *saved;
10372
10373 switch (c)
10374 {
10375 case 'n':
10376 optimize_align_code = 0;
10377 break;
10378
10379 case 'q':
10380 quiet_warnings = 1;
10381 break;
10382
10383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10384 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10385 should be emitted or not. FIXME: Not implemented. */
10386 case 'Q':
10387 break;
10388
10389 /* -V: SVR4 argument to print version ID. */
10390 case 'V':
10391 print_version_id ();
10392 break;
10393
10394 /* -k: Ignore for FreeBSD compatibility. */
10395 case 'k':
10396 break;
10397
10398 case 's':
10399 /* -s: On i386 Solaris, this tells the native assembler to use
10400 .stab instead of .stab.excl. We always use .stab anyhow. */
10401 break;
10402
10403 case OPTION_MSHARED:
10404 shared = 1;
10405 break;
10406 #endif
10407 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10408 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10409 case OPTION_64:
10410 {
10411 const char **list, **l;
10412
10413 list = bfd_target_list ();
10414 for (l = list; *l != NULL; l++)
10415 if (CONST_STRNEQ (*l, "elf64-x86-64")
10416 || strcmp (*l, "coff-x86-64") == 0
10417 || strcmp (*l, "pe-x86-64") == 0
10418 || strcmp (*l, "pei-x86-64") == 0
10419 || strcmp (*l, "mach-o-x86-64") == 0)
10420 {
10421 default_arch = "x86_64";
10422 break;
10423 }
10424 if (*l == NULL)
10425 as_fatal (_("no compiled in support for x86_64"));
10426 free (list);
10427 }
10428 break;
10429 #endif
10430
10431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10432 case OPTION_X32:
10433 if (IS_ELF)
10434 {
10435 const char **list, **l;
10436
10437 list = bfd_target_list ();
10438 for (l = list; *l != NULL; l++)
10439 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10440 {
10441 default_arch = "x86_64:32";
10442 break;
10443 }
10444 if (*l == NULL)
10445 as_fatal (_("no compiled in support for 32bit x86_64"));
10446 free (list);
10447 }
10448 else
10449 as_fatal (_("32bit x86_64 is only supported for ELF"));
10450 break;
10451 #endif
10452
10453 case OPTION_32:
10454 default_arch = "i386";
10455 break;
10456
10457 case OPTION_DIVIDE:
10458 #ifdef SVR4_COMMENT_CHARS
10459 {
10460 char *n, *t;
10461 const char *s;
10462
10463 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10464 t = n;
10465 for (s = i386_comment_chars; *s != '\0'; s++)
10466 if (*s != '/')
10467 *t++ = *s;
10468 *t = '\0';
10469 i386_comment_chars = n;
10470 }
10471 #endif
10472 break;
10473
10474 case OPTION_MARCH:
10475 saved = xstrdup (arg);
10476 arch = saved;
10477 /* Allow -march=+nosse. */
10478 if (*arch == '+')
10479 arch++;
10480 do
10481 {
10482 if (*arch == '.')
10483 as_fatal (_("invalid -march= option: `%s'"), arg);
10484 next = strchr (arch, '+');
10485 if (next)
10486 *next++ = '\0';
10487 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10488 {
10489 if (strcmp (arch, cpu_arch [j].name) == 0)
10490 {
10491 /* Processor. */
10492 if (! cpu_arch[j].flags.bitfield.cpui386)
10493 continue;
10494
10495 cpu_arch_name = cpu_arch[j].name;
10496 cpu_sub_arch_name = NULL;
10497 cpu_arch_flags = cpu_arch[j].flags;
10498 cpu_arch_isa = cpu_arch[j].type;
10499 cpu_arch_isa_flags = cpu_arch[j].flags;
10500 if (!cpu_arch_tune_set)
10501 {
10502 cpu_arch_tune = cpu_arch_isa;
10503 cpu_arch_tune_flags = cpu_arch_isa_flags;
10504 }
10505 break;
10506 }
10507 else if (*cpu_arch [j].name == '.'
10508 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10509 {
10510 /* ISA extension. */
10511 i386_cpu_flags flags;
10512
10513 flags = cpu_flags_or (cpu_arch_flags,
10514 cpu_arch[j].flags);
10515
10516 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10517 {
10518 if (cpu_sub_arch_name)
10519 {
10520 char *name = cpu_sub_arch_name;
10521 cpu_sub_arch_name = concat (name,
10522 cpu_arch[j].name,
10523 (const char *) NULL);
10524 free (name);
10525 }
10526 else
10527 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10528 cpu_arch_flags = flags;
10529 cpu_arch_isa_flags = flags;
10530 }
10531 break;
10532 }
10533 }
10534
10535 if (j >= ARRAY_SIZE (cpu_arch))
10536 {
10537 /* Disable an ISA extension. */
10538 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10539 if (strcmp (arch, cpu_noarch [j].name) == 0)
10540 {
10541 i386_cpu_flags flags;
10542
10543 flags = cpu_flags_and_not (cpu_arch_flags,
10544 cpu_noarch[j].flags);
10545 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10546 {
10547 if (cpu_sub_arch_name)
10548 {
10549 char *name = cpu_sub_arch_name;
10550 cpu_sub_arch_name = concat (arch,
10551 (const char *) NULL);
10552 free (name);
10553 }
10554 else
10555 cpu_sub_arch_name = xstrdup (arch);
10556 cpu_arch_flags = flags;
10557 cpu_arch_isa_flags = flags;
10558 }
10559 break;
10560 }
10561
10562 if (j >= ARRAY_SIZE (cpu_noarch))
10563 j = ARRAY_SIZE (cpu_arch);
10564 }
10565
10566 if (j >= ARRAY_SIZE (cpu_arch))
10567 as_fatal (_("invalid -march= option: `%s'"), arg);
10568
10569 arch = next;
10570 }
10571 while (next != NULL);
10572 free (saved);
10573 break;
10574
10575 case OPTION_MTUNE:
10576 if (*arg == '.')
10577 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10578 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10579 {
10580 if (strcmp (arg, cpu_arch [j].name) == 0)
10581 {
10582 cpu_arch_tune_set = 1;
10583 cpu_arch_tune = cpu_arch [j].type;
10584 cpu_arch_tune_flags = cpu_arch[j].flags;
10585 break;
10586 }
10587 }
10588 if (j >= ARRAY_SIZE (cpu_arch))
10589 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10590 break;
10591
10592 case OPTION_MMNEMONIC:
10593 if (strcasecmp (arg, "att") == 0)
10594 intel_mnemonic = 0;
10595 else if (strcasecmp (arg, "intel") == 0)
10596 intel_mnemonic = 1;
10597 else
10598 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10599 break;
10600
10601 case OPTION_MSYNTAX:
10602 if (strcasecmp (arg, "att") == 0)
10603 intel_syntax = 0;
10604 else if (strcasecmp (arg, "intel") == 0)
10605 intel_syntax = 1;
10606 else
10607 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10608 break;
10609
10610 case OPTION_MINDEX_REG:
10611 allow_index_reg = 1;
10612 break;
10613
10614 case OPTION_MNAKED_REG:
10615 allow_naked_reg = 1;
10616 break;
10617
10618 case OPTION_MOLD_GCC:
10619 old_gcc = 1;
10620 break;
10621
10622 case OPTION_MSSE2AVX:
10623 sse2avx = 1;
10624 break;
10625
10626 case OPTION_MSSE_CHECK:
10627 if (strcasecmp (arg, "error") == 0)
10628 sse_check = check_error;
10629 else if (strcasecmp (arg, "warning") == 0)
10630 sse_check = check_warning;
10631 else if (strcasecmp (arg, "none") == 0)
10632 sse_check = check_none;
10633 else
10634 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10635 break;
10636
10637 case OPTION_MOPERAND_CHECK:
10638 if (strcasecmp (arg, "error") == 0)
10639 operand_check = check_error;
10640 else if (strcasecmp (arg, "warning") == 0)
10641 operand_check = check_warning;
10642 else if (strcasecmp (arg, "none") == 0)
10643 operand_check = check_none;
10644 else
10645 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10646 break;
10647
10648 case OPTION_MAVXSCALAR:
10649 if (strcasecmp (arg, "128") == 0)
10650 avxscalar = vex128;
10651 else if (strcasecmp (arg, "256") == 0)
10652 avxscalar = vex256;
10653 else
10654 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10655 break;
10656
10657 case OPTION_MADD_BND_PREFIX:
10658 add_bnd_prefix = 1;
10659 break;
10660
10661 case OPTION_MEVEXLIG:
10662 if (strcmp (arg, "128") == 0)
10663 evexlig = evexl128;
10664 else if (strcmp (arg, "256") == 0)
10665 evexlig = evexl256;
10666 else if (strcmp (arg, "512") == 0)
10667 evexlig = evexl512;
10668 else
10669 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10670 break;
10671
10672 case OPTION_MEVEXRCIG:
10673 if (strcmp (arg, "rne") == 0)
10674 evexrcig = rne;
10675 else if (strcmp (arg, "rd") == 0)
10676 evexrcig = rd;
10677 else if (strcmp (arg, "ru") == 0)
10678 evexrcig = ru;
10679 else if (strcmp (arg, "rz") == 0)
10680 evexrcig = rz;
10681 else
10682 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10683 break;
10684
10685 case OPTION_MEVEXWIG:
10686 if (strcmp (arg, "0") == 0)
10687 evexwig = evexw0;
10688 else if (strcmp (arg, "1") == 0)
10689 evexwig = evexw1;
10690 else
10691 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10692 break;
10693
10694 # if defined (TE_PE) || defined (TE_PEP)
10695 case OPTION_MBIG_OBJ:
10696 use_big_obj = 1;
10697 break;
10698 #endif
10699
10700 case OPTION_MOMIT_LOCK_PREFIX:
10701 if (strcasecmp (arg, "yes") == 0)
10702 omit_lock_prefix = 1;
10703 else if (strcasecmp (arg, "no") == 0)
10704 omit_lock_prefix = 0;
10705 else
10706 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10707 break;
10708
10709 case OPTION_MFENCE_AS_LOCK_ADD:
10710 if (strcasecmp (arg, "yes") == 0)
10711 avoid_fence = 1;
10712 else if (strcasecmp (arg, "no") == 0)
10713 avoid_fence = 0;
10714 else
10715 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10716 break;
10717
10718 case OPTION_MRELAX_RELOCATIONS:
10719 if (strcasecmp (arg, "yes") == 0)
10720 generate_relax_relocations = 1;
10721 else if (strcasecmp (arg, "no") == 0)
10722 generate_relax_relocations = 0;
10723 else
10724 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10725 break;
10726
10727 case OPTION_MAMD64:
10728 intel64 = 0;
10729 break;
10730
10731 case OPTION_MINTEL64:
10732 intel64 = 1;
10733 break;
10734
10735 case 'O':
10736 if (arg == NULL)
10737 {
10738 optimize = 1;
10739 /* Turn off -Os. */
10740 optimize_for_space = 0;
10741 }
10742 else if (*arg == 's')
10743 {
10744 optimize_for_space = 1;
10745 /* Turn on all encoding optimizations. */
10746 optimize = -1;
10747 }
10748 else
10749 {
10750 optimize = atoi (arg);
10751 /* Turn off -Os. */
10752 optimize_for_space = 0;
10753 }
10754 break;
10755
10756 default:
10757 return 0;
10758 }
10759 return 1;
10760 }
10761
10762 #define MESSAGE_TEMPLATE \
10763 " "
10764
10765 static char *
10766 output_message (FILE *stream, char *p, char *message, char *start,
10767 int *left_p, const char *name, int len)
10768 {
10769 int size = sizeof (MESSAGE_TEMPLATE);
10770 int left = *left_p;
10771
10772 /* Reserve 2 spaces for ", " or ",\0" */
10773 left -= len + 2;
10774
10775 /* Check if there is any room. */
10776 if (left >= 0)
10777 {
10778 if (p != start)
10779 {
10780 *p++ = ',';
10781 *p++ = ' ';
10782 }
10783 p = mempcpy (p, name, len);
10784 }
10785 else
10786 {
10787 /* Output the current message now and start a new one. */
10788 *p++ = ',';
10789 *p = '\0';
10790 fprintf (stream, "%s\n", message);
10791 p = start;
10792 left = size - (start - message) - len - 2;
10793
10794 gas_assert (left >= 0);
10795
10796 p = mempcpy (p, name, len);
10797 }
10798
10799 *left_p = left;
10800 return p;
10801 }
10802
10803 static void
10804 show_arch (FILE *stream, int ext, int check)
10805 {
10806 static char message[] = MESSAGE_TEMPLATE;
10807 char *start = message + 27;
10808 char *p;
10809 int size = sizeof (MESSAGE_TEMPLATE);
10810 int left;
10811 const char *name;
10812 int len;
10813 unsigned int j;
10814
10815 p = start;
10816 left = size - (start - message);
10817 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10818 {
10819 /* Should it be skipped? */
10820 if (cpu_arch [j].skip)
10821 continue;
10822
10823 name = cpu_arch [j].name;
10824 len = cpu_arch [j].len;
10825 if (*name == '.')
10826 {
10827 /* It is an extension. Skip if we aren't asked to show it. */
10828 if (ext)
10829 {
10830 name++;
10831 len--;
10832 }
10833 else
10834 continue;
10835 }
10836 else if (ext)
10837 {
10838 /* It is an processor. Skip if we show only extension. */
10839 continue;
10840 }
10841 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10842 {
10843 /* It is an impossible processor - skip. */
10844 continue;
10845 }
10846
10847 p = output_message (stream, p, message, start, &left, name, len);
10848 }
10849
10850 /* Display disabled extensions. */
10851 if (ext)
10852 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10853 {
10854 name = cpu_noarch [j].name;
10855 len = cpu_noarch [j].len;
10856 p = output_message (stream, p, message, start, &left, name,
10857 len);
10858 }
10859
10860 *p = '\0';
10861 fprintf (stream, "%s\n", message);
10862 }
10863
10864 void
10865 md_show_usage (FILE *stream)
10866 {
10867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10868 fprintf (stream, _("\
10869 -Q ignored\n\
10870 -V print assembler version number\n\
10871 -k ignored\n"));
10872 #endif
10873 fprintf (stream, _("\
10874 -n Do not optimize code alignment\n\
10875 -q quieten some warnings\n"));
10876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10877 fprintf (stream, _("\
10878 -s ignored\n"));
10879 #endif
10880 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10881 || defined (TE_PE) || defined (TE_PEP))
10882 fprintf (stream, _("\
10883 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10884 #endif
10885 #ifdef SVR4_COMMENT_CHARS
10886 fprintf (stream, _("\
10887 --divide do not treat `/' as a comment character\n"));
10888 #else
10889 fprintf (stream, _("\
10890 --divide ignored\n"));
10891 #endif
10892 fprintf (stream, _("\
10893 -march=CPU[,+EXTENSION...]\n\
10894 generate code for CPU and EXTENSION, CPU is one of:\n"));
10895 show_arch (stream, 0, 1);
10896 fprintf (stream, _("\
10897 EXTENSION is combination of:\n"));
10898 show_arch (stream, 1, 0);
10899 fprintf (stream, _("\
10900 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10901 show_arch (stream, 0, 0);
10902 fprintf (stream, _("\
10903 -msse2avx encode SSE instructions with VEX prefix\n"));
10904 fprintf (stream, _("\
10905 -msse-check=[none|error|warning]\n\
10906 check SSE instructions\n"));
10907 fprintf (stream, _("\
10908 -moperand-check=[none|error|warning]\n\
10909 check operand combinations for validity\n"));
10910 fprintf (stream, _("\
10911 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10912 length\n"));
10913 fprintf (stream, _("\
10914 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10915 length\n"));
10916 fprintf (stream, _("\
10917 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10918 for EVEX.W bit ignored instructions\n"));
10919 fprintf (stream, _("\
10920 -mevexrcig=[rne|rd|ru|rz]\n\
10921 encode EVEX instructions with specific EVEX.RC value\n\
10922 for SAE-only ignored instructions\n"));
10923 fprintf (stream, _("\
10924 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10925 fprintf (stream, _("\
10926 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10927 fprintf (stream, _("\
10928 -mindex-reg support pseudo index registers\n"));
10929 fprintf (stream, _("\
10930 -mnaked-reg don't require `%%' prefix for registers\n"));
10931 fprintf (stream, _("\
10932 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10933 fprintf (stream, _("\
10934 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10935 fprintf (stream, _("\
10936 -mshared disable branch optimization for shared code\n"));
10937 # if defined (TE_PE) || defined (TE_PEP)
10938 fprintf (stream, _("\
10939 -mbig-obj generate big object files\n"));
10940 #endif
10941 fprintf (stream, _("\
10942 -momit-lock-prefix=[no|yes]\n\
10943 strip all lock prefixes\n"));
10944 fprintf (stream, _("\
10945 -mfence-as-lock-add=[no|yes]\n\
10946 encode lfence, mfence and sfence as\n\
10947 lock addl $0x0, (%%{re}sp)\n"));
10948 fprintf (stream, _("\
10949 -mrelax-relocations=[no|yes]\n\
10950 generate relax relocations\n"));
10951 fprintf (stream, _("\
10952 -mamd64 accept only AMD64 ISA\n"));
10953 fprintf (stream, _("\
10954 -mintel64 accept only Intel64 ISA\n"));
10955 }
10956
10957 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10958 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10959 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10960
10961 /* Pick the target format to use. */
10962
10963 const char *
10964 i386_target_format (void)
10965 {
10966 if (!strncmp (default_arch, "x86_64", 6))
10967 {
10968 update_code_flag (CODE_64BIT, 1);
10969 if (default_arch[6] == '\0')
10970 x86_elf_abi = X86_64_ABI;
10971 else
10972 x86_elf_abi = X86_64_X32_ABI;
10973 }
10974 else if (!strcmp (default_arch, "i386"))
10975 update_code_flag (CODE_32BIT, 1);
10976 else if (!strcmp (default_arch, "iamcu"))
10977 {
10978 update_code_flag (CODE_32BIT, 1);
10979 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10980 {
10981 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10982 cpu_arch_name = "iamcu";
10983 cpu_sub_arch_name = NULL;
10984 cpu_arch_flags = iamcu_flags;
10985 cpu_arch_isa = PROCESSOR_IAMCU;
10986 cpu_arch_isa_flags = iamcu_flags;
10987 if (!cpu_arch_tune_set)
10988 {
10989 cpu_arch_tune = cpu_arch_isa;
10990 cpu_arch_tune_flags = cpu_arch_isa_flags;
10991 }
10992 }
10993 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10994 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10995 cpu_arch_name);
10996 }
10997 else
10998 as_fatal (_("unknown architecture"));
10999
11000 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11001 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11002 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11003 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11004
11005 switch (OUTPUT_FLAVOR)
11006 {
11007 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11008 case bfd_target_aout_flavour:
11009 return AOUT_TARGET_FORMAT;
11010 #endif
11011 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11012 # if defined (TE_PE) || defined (TE_PEP)
11013 case bfd_target_coff_flavour:
11014 if (flag_code == CODE_64BIT)
11015 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11016 else
11017 return "pe-i386";
11018 # elif defined (TE_GO32)
11019 case bfd_target_coff_flavour:
11020 return "coff-go32";
11021 # else
11022 case bfd_target_coff_flavour:
11023 return "coff-i386";
11024 # endif
11025 #endif
11026 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11027 case bfd_target_elf_flavour:
11028 {
11029 const char *format;
11030
11031 switch (x86_elf_abi)
11032 {
11033 default:
11034 format = ELF_TARGET_FORMAT;
11035 break;
11036 case X86_64_ABI:
11037 use_rela_relocations = 1;
11038 object_64bit = 1;
11039 format = ELF_TARGET_FORMAT64;
11040 break;
11041 case X86_64_X32_ABI:
11042 use_rela_relocations = 1;
11043 object_64bit = 1;
11044 disallow_64bit_reloc = 1;
11045 format = ELF_TARGET_FORMAT32;
11046 break;
11047 }
11048 if (cpu_arch_isa == PROCESSOR_L1OM)
11049 {
11050 if (x86_elf_abi != X86_64_ABI)
11051 as_fatal (_("Intel L1OM is 64bit only"));
11052 return ELF_TARGET_L1OM_FORMAT;
11053 }
11054 else if (cpu_arch_isa == PROCESSOR_K1OM)
11055 {
11056 if (x86_elf_abi != X86_64_ABI)
11057 as_fatal (_("Intel K1OM is 64bit only"));
11058 return ELF_TARGET_K1OM_FORMAT;
11059 }
11060 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11061 {
11062 if (x86_elf_abi != I386_ABI)
11063 as_fatal (_("Intel MCU is 32bit only"));
11064 return ELF_TARGET_IAMCU_FORMAT;
11065 }
11066 else
11067 return format;
11068 }
11069 #endif
11070 #if defined (OBJ_MACH_O)
11071 case bfd_target_mach_o_flavour:
11072 if (flag_code == CODE_64BIT)
11073 {
11074 use_rela_relocations = 1;
11075 object_64bit = 1;
11076 return "mach-o-x86-64";
11077 }
11078 else
11079 return "mach-o-i386";
11080 #endif
11081 default:
11082 abort ();
11083 return NULL;
11084 }
11085 }
11086
11087 #endif /* OBJ_MAYBE_ more than one */
11088 \f
11089 symbolS *
11090 md_undefined_symbol (char *name)
11091 {
11092 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11093 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11094 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11095 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11096 {
11097 if (!GOT_symbol)
11098 {
11099 if (symbol_find (name))
11100 as_bad (_("GOT already in symbol table"));
11101 GOT_symbol = symbol_new (name, undefined_section,
11102 (valueT) 0, &zero_address_frag);
11103 };
11104 return GOT_symbol;
11105 }
11106 return 0;
11107 }
11108
11109 /* Round up a section size to the appropriate boundary. */
11110
11111 valueT
11112 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11113 {
11114 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11115 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11116 {
11117 /* For a.out, force the section size to be aligned. If we don't do
11118 this, BFD will align it for us, but it will not write out the
11119 final bytes of the section. This may be a bug in BFD, but it is
11120 easier to fix it here since that is how the other a.out targets
11121 work. */
11122 int align;
11123
11124 align = bfd_get_section_alignment (stdoutput, segment);
11125 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11126 }
11127 #endif
11128
11129 return size;
11130 }
11131
11132 /* On the i386, PC-relative offsets are relative to the start of the
11133 next instruction. That is, the address of the offset, plus its
11134 size, since the offset is always the last part of the insn. */
11135
11136 long
11137 md_pcrel_from (fixS *fixP)
11138 {
11139 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11140 }
11141
11142 #ifndef I386COFF
11143
11144 static void
11145 s_bss (int ignore ATTRIBUTE_UNUSED)
11146 {
11147 int temp;
11148
11149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11150 if (IS_ELF)
11151 obj_elf_section_change_hook ();
11152 #endif
11153 temp = get_absolute_expression ();
11154 subseg_set (bss_section, (subsegT) temp);
11155 demand_empty_rest_of_line ();
11156 }
11157
11158 #endif
11159
11160 void
11161 i386_validate_fix (fixS *fixp)
11162 {
11163 if (fixp->fx_subsy)
11164 {
11165 if (fixp->fx_subsy == GOT_symbol)
11166 {
11167 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11168 {
11169 if (!object_64bit)
11170 abort ();
11171 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11172 if (fixp->fx_tcbit2)
11173 fixp->fx_r_type = (fixp->fx_tcbit
11174 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11175 : BFD_RELOC_X86_64_GOTPCRELX);
11176 else
11177 #endif
11178 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11179 }
11180 else
11181 {
11182 if (!object_64bit)
11183 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11184 else
11185 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11186 }
11187 fixp->fx_subsy = 0;
11188 }
11189 }
11190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11191 else if (!object_64bit)
11192 {
11193 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11194 && fixp->fx_tcbit2)
11195 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11196 }
11197 #endif
11198 }
11199
11200 arelent *
11201 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11202 {
11203 arelent *rel;
11204 bfd_reloc_code_real_type code;
11205
11206 switch (fixp->fx_r_type)
11207 {
11208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11209 case BFD_RELOC_SIZE32:
11210 case BFD_RELOC_SIZE64:
11211 if (S_IS_DEFINED (fixp->fx_addsy)
11212 && !S_IS_EXTERNAL (fixp->fx_addsy))
11213 {
11214 /* Resolve size relocation against local symbol to size of
11215 the symbol plus addend. */
11216 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11217 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11218 && !fits_in_unsigned_long (value))
11219 as_bad_where (fixp->fx_file, fixp->fx_line,
11220 _("symbol size computation overflow"));
11221 fixp->fx_addsy = NULL;
11222 fixp->fx_subsy = NULL;
11223 md_apply_fix (fixp, (valueT *) &value, NULL);
11224 return NULL;
11225 }
11226 #endif
11227 /* Fall through. */
11228
11229 case BFD_RELOC_X86_64_PLT32:
11230 case BFD_RELOC_X86_64_GOT32:
11231 case BFD_RELOC_X86_64_GOTPCREL:
11232 case BFD_RELOC_X86_64_GOTPCRELX:
11233 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11234 case BFD_RELOC_386_PLT32:
11235 case BFD_RELOC_386_GOT32:
11236 case BFD_RELOC_386_GOT32X:
11237 case BFD_RELOC_386_GOTOFF:
11238 case BFD_RELOC_386_GOTPC:
11239 case BFD_RELOC_386_TLS_GD:
11240 case BFD_RELOC_386_TLS_LDM:
11241 case BFD_RELOC_386_TLS_LDO_32:
11242 case BFD_RELOC_386_TLS_IE_32:
11243 case BFD_RELOC_386_TLS_IE:
11244 case BFD_RELOC_386_TLS_GOTIE:
11245 case BFD_RELOC_386_TLS_LE_32:
11246 case BFD_RELOC_386_TLS_LE:
11247 case BFD_RELOC_386_TLS_GOTDESC:
11248 case BFD_RELOC_386_TLS_DESC_CALL:
11249 case BFD_RELOC_X86_64_TLSGD:
11250 case BFD_RELOC_X86_64_TLSLD:
11251 case BFD_RELOC_X86_64_DTPOFF32:
11252 case BFD_RELOC_X86_64_DTPOFF64:
11253 case BFD_RELOC_X86_64_GOTTPOFF:
11254 case BFD_RELOC_X86_64_TPOFF32:
11255 case BFD_RELOC_X86_64_TPOFF64:
11256 case BFD_RELOC_X86_64_GOTOFF64:
11257 case BFD_RELOC_X86_64_GOTPC32:
11258 case BFD_RELOC_X86_64_GOT64:
11259 case BFD_RELOC_X86_64_GOTPCREL64:
11260 case BFD_RELOC_X86_64_GOTPC64:
11261 case BFD_RELOC_X86_64_GOTPLT64:
11262 case BFD_RELOC_X86_64_PLTOFF64:
11263 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11264 case BFD_RELOC_X86_64_TLSDESC_CALL:
11265 case BFD_RELOC_RVA:
11266 case BFD_RELOC_VTABLE_ENTRY:
11267 case BFD_RELOC_VTABLE_INHERIT:
11268 #ifdef TE_PE
11269 case BFD_RELOC_32_SECREL:
11270 #endif
11271 code = fixp->fx_r_type;
11272 break;
11273 case BFD_RELOC_X86_64_32S:
11274 if (!fixp->fx_pcrel)
11275 {
11276 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11277 code = fixp->fx_r_type;
11278 break;
11279 }
11280 /* Fall through. */
11281 default:
11282 if (fixp->fx_pcrel)
11283 {
11284 switch (fixp->fx_size)
11285 {
11286 default:
11287 as_bad_where (fixp->fx_file, fixp->fx_line,
11288 _("can not do %d byte pc-relative relocation"),
11289 fixp->fx_size);
11290 code = BFD_RELOC_32_PCREL;
11291 break;
11292 case 1: code = BFD_RELOC_8_PCREL; break;
11293 case 2: code = BFD_RELOC_16_PCREL; break;
11294 case 4: code = BFD_RELOC_32_PCREL; break;
11295 #ifdef BFD64
11296 case 8: code = BFD_RELOC_64_PCREL; break;
11297 #endif
11298 }
11299 }
11300 else
11301 {
11302 switch (fixp->fx_size)
11303 {
11304 default:
11305 as_bad_where (fixp->fx_file, fixp->fx_line,
11306 _("can not do %d byte relocation"),
11307 fixp->fx_size);
11308 code = BFD_RELOC_32;
11309 break;
11310 case 1: code = BFD_RELOC_8; break;
11311 case 2: code = BFD_RELOC_16; break;
11312 case 4: code = BFD_RELOC_32; break;
11313 #ifdef BFD64
11314 case 8: code = BFD_RELOC_64; break;
11315 #endif
11316 }
11317 }
11318 break;
11319 }
11320
11321 if ((code == BFD_RELOC_32
11322 || code == BFD_RELOC_32_PCREL
11323 || code == BFD_RELOC_X86_64_32S)
11324 && GOT_symbol
11325 && fixp->fx_addsy == GOT_symbol)
11326 {
11327 if (!object_64bit)
11328 code = BFD_RELOC_386_GOTPC;
11329 else
11330 code = BFD_RELOC_X86_64_GOTPC32;
11331 }
11332 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11333 && GOT_symbol
11334 && fixp->fx_addsy == GOT_symbol)
11335 {
11336 code = BFD_RELOC_X86_64_GOTPC64;
11337 }
11338
11339 rel = XNEW (arelent);
11340 rel->sym_ptr_ptr = XNEW (asymbol *);
11341 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11342
11343 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11344
11345 if (!use_rela_relocations)
11346 {
11347 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11348 vtable entry to be used in the relocation's section offset. */
11349 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11350 rel->address = fixp->fx_offset;
11351 #if defined (OBJ_COFF) && defined (TE_PE)
11352 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11353 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11354 else
11355 #endif
11356 rel->addend = 0;
11357 }
11358 /* Use the rela in 64bit mode. */
11359 else
11360 {
11361 if (disallow_64bit_reloc)
11362 switch (code)
11363 {
11364 case BFD_RELOC_X86_64_DTPOFF64:
11365 case BFD_RELOC_X86_64_TPOFF64:
11366 case BFD_RELOC_64_PCREL:
11367 case BFD_RELOC_X86_64_GOTOFF64:
11368 case BFD_RELOC_X86_64_GOT64:
11369 case BFD_RELOC_X86_64_GOTPCREL64:
11370 case BFD_RELOC_X86_64_GOTPC64:
11371 case BFD_RELOC_X86_64_GOTPLT64:
11372 case BFD_RELOC_X86_64_PLTOFF64:
11373 as_bad_where (fixp->fx_file, fixp->fx_line,
11374 _("cannot represent relocation type %s in x32 mode"),
11375 bfd_get_reloc_code_name (code));
11376 break;
11377 default:
11378 break;
11379 }
11380
11381 if (!fixp->fx_pcrel)
11382 rel->addend = fixp->fx_offset;
11383 else
11384 switch (code)
11385 {
11386 case BFD_RELOC_X86_64_PLT32:
11387 case BFD_RELOC_X86_64_GOT32:
11388 case BFD_RELOC_X86_64_GOTPCREL:
11389 case BFD_RELOC_X86_64_GOTPCRELX:
11390 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11391 case BFD_RELOC_X86_64_TLSGD:
11392 case BFD_RELOC_X86_64_TLSLD:
11393 case BFD_RELOC_X86_64_GOTTPOFF:
11394 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11395 case BFD_RELOC_X86_64_TLSDESC_CALL:
11396 rel->addend = fixp->fx_offset - fixp->fx_size;
11397 break;
11398 default:
11399 rel->addend = (section->vma
11400 - fixp->fx_size
11401 + fixp->fx_addnumber
11402 + md_pcrel_from (fixp));
11403 break;
11404 }
11405 }
11406
11407 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11408 if (rel->howto == NULL)
11409 {
11410 as_bad_where (fixp->fx_file, fixp->fx_line,
11411 _("cannot represent relocation type %s"),
11412 bfd_get_reloc_code_name (code));
11413 /* Set howto to a garbage value so that we can keep going. */
11414 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11415 gas_assert (rel->howto != NULL);
11416 }
11417
11418 return rel;
11419 }
11420
11421 #include "tc-i386-intel.c"
11422
11423 void
11424 tc_x86_parse_to_dw2regnum (expressionS *exp)
11425 {
11426 int saved_naked_reg;
11427 char saved_register_dot;
11428
11429 saved_naked_reg = allow_naked_reg;
11430 allow_naked_reg = 1;
11431 saved_register_dot = register_chars['.'];
11432 register_chars['.'] = '.';
11433 allow_pseudo_reg = 1;
11434 expression_and_evaluate (exp);
11435 allow_pseudo_reg = 0;
11436 register_chars['.'] = saved_register_dot;
11437 allow_naked_reg = saved_naked_reg;
11438
11439 if (exp->X_op == O_register && exp->X_add_number >= 0)
11440 {
11441 if ((addressT) exp->X_add_number < i386_regtab_size)
11442 {
11443 exp->X_op = O_constant;
11444 exp->X_add_number = i386_regtab[exp->X_add_number]
11445 .dw2_regnum[flag_code >> 1];
11446 }
11447 else
11448 exp->X_op = O_illegal;
11449 }
11450 }
11451
11452 void
11453 tc_x86_frame_initial_instructions (void)
11454 {
11455 static unsigned int sp_regno[2];
11456
11457 if (!sp_regno[flag_code >> 1])
11458 {
11459 char *saved_input = input_line_pointer;
11460 char sp[][4] = {"esp", "rsp"};
11461 expressionS exp;
11462
11463 input_line_pointer = sp[flag_code >> 1];
11464 tc_x86_parse_to_dw2regnum (&exp);
11465 gas_assert (exp.X_op == O_constant);
11466 sp_regno[flag_code >> 1] = exp.X_add_number;
11467 input_line_pointer = saved_input;
11468 }
11469
11470 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11471 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11472 }
11473
11474 int
11475 x86_dwarf2_addr_size (void)
11476 {
11477 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11478 if (x86_elf_abi == X86_64_X32_ABI)
11479 return 4;
11480 #endif
11481 return bfd_arch_bits_per_address (stdoutput) / 8;
11482 }
11483
11484 int
11485 i386_elf_section_type (const char *str, size_t len)
11486 {
11487 if (flag_code == CODE_64BIT
11488 && len == sizeof ("unwind") - 1
11489 && strncmp (str, "unwind", 6) == 0)
11490 return SHT_X86_64_UNWIND;
11491
11492 return -1;
11493 }
11494
11495 #ifdef TE_SOLARIS
11496 void
11497 i386_solaris_fix_up_eh_frame (segT sec)
11498 {
11499 if (flag_code == CODE_64BIT)
11500 elf_section_type (sec) = SHT_X86_64_UNWIND;
11501 }
11502 #endif
11503
11504 #ifdef TE_PE
11505 void
11506 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11507 {
11508 expressionS exp;
11509
11510 exp.X_op = O_secrel;
11511 exp.X_add_symbol = symbol;
11512 exp.X_add_number = 0;
11513 emit_expr (&exp, size);
11514 }
11515 #endif
11516
11517 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11518 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11519
11520 bfd_vma
11521 x86_64_section_letter (int letter, const char **ptr_msg)
11522 {
11523 if (flag_code == CODE_64BIT)
11524 {
11525 if (letter == 'l')
11526 return SHF_X86_64_LARGE;
11527
11528 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11529 }
11530 else
11531 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11532 return -1;
11533 }
11534
11535 bfd_vma
11536 x86_64_section_word (char *str, size_t len)
11537 {
11538 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11539 return SHF_X86_64_LARGE;
11540
11541 return -1;
11542 }
11543
11544 static void
11545 handle_large_common (int small ATTRIBUTE_UNUSED)
11546 {
11547 if (flag_code != CODE_64BIT)
11548 {
11549 s_comm_internal (0, elf_common_parse);
11550 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11551 }
11552 else
11553 {
11554 static segT lbss_section;
11555 asection *saved_com_section_ptr = elf_com_section_ptr;
11556 asection *saved_bss_section = bss_section;
11557
11558 if (lbss_section == NULL)
11559 {
11560 flagword applicable;
11561 segT seg = now_seg;
11562 subsegT subseg = now_subseg;
11563
11564 /* The .lbss section is for local .largecomm symbols. */
11565 lbss_section = subseg_new (".lbss", 0);
11566 applicable = bfd_applicable_section_flags (stdoutput);
11567 bfd_set_section_flags (stdoutput, lbss_section,
11568 applicable & SEC_ALLOC);
11569 seg_info (lbss_section)->bss = 1;
11570
11571 subseg_set (seg, subseg);
11572 }
11573
11574 elf_com_section_ptr = &_bfd_elf_large_com_section;
11575 bss_section = lbss_section;
11576
11577 s_comm_internal (0, elf_common_parse);
11578
11579 elf_com_section_ptr = saved_com_section_ptr;
11580 bss_section = saved_bss_section;
11581 }
11582 }
11583 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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