1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
159 PROCESSOR_PENTIUMPRO
,
172 /* x86 arch names, types and features */
175 const char *name
; /* arch name */
176 enum processor_type type
; /* arch type */
177 i386_cpu_flags flags
; /* cpu feature flags */
181 static void set_code_flag (int);
182 static void set_16bit_gcc_code_flag (int);
183 static void set_intel_syntax (int);
184 static void set_intel_mnemonic (int);
185 static void set_allow_index_reg (int);
186 static void set_sse_check (int);
187 static void set_cpu_arch (int);
189 static void pe_directive_secrel (int);
191 static void signed_cons (int);
192 static char *output_invalid (int c
);
193 static int i386_att_operand (char *);
194 static int i386_intel_operand (char *, int);
195 static const reg_entry
*parse_register (char *, char **);
196 static char *parse_insn (char *, char *);
197 static char *parse_operands (char *, const char *);
198 static void swap_operands (void);
199 static void swap_2_operands (int, int);
200 static void optimize_imm (void);
201 static void optimize_disp (void);
202 static int match_template (void);
203 static int check_string (void);
204 static int process_suffix (void);
205 static int check_byte_reg (void);
206 static int check_long_reg (void);
207 static int check_qword_reg (void);
208 static int check_word_reg (void);
209 static int finalize_imm (void);
210 static void process_drex (void);
211 static int process_operands (void);
212 static const seg_entry
*build_modrm_byte (void);
213 static void output_insn (void);
214 static void output_imm (fragS
*, offsetT
);
215 static void output_disp (fragS
*, offsetT
);
217 static void s_bss (int);
219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
220 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
223 static const char *default_arch
= DEFAULT_ARCH
;
228 /* VEX prefix is either 2 byte or 3 byte. */
229 unsigned char bytes
[3];
231 /* Destination or source register specifier. */
232 const reg_entry
*register_specifier
;
235 /* 'md_assemble ()' gathers together information and puts it into a
242 const reg_entry
*regs
;
247 /* TM holds the template for the insn were currently assembling. */
250 /* SUFFIX holds the instruction size suffix for byte, word, dword
251 or qword, if given. */
254 /* OPERANDS gives the number of given operands. */
255 unsigned int operands
;
257 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
258 of given register, displacement, memory operands and immediate
260 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
262 /* TYPES [i] is the type (see above #defines) which tells us how to
263 use OP[i] for the corresponding operand. */
264 i386_operand_type types
[MAX_OPERANDS
];
266 /* Displacement expression, immediate expression, or register for each
268 union i386_op op
[MAX_OPERANDS
];
270 /* Flags for operands. */
271 unsigned int flags
[MAX_OPERANDS
];
272 #define Operand_PCrel 1
274 /* Relocation type for operand */
275 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
277 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
278 the base index byte below. */
279 const reg_entry
*base_reg
;
280 const reg_entry
*index_reg
;
281 unsigned int log2_scale_factor
;
283 /* SEG gives the seg_entries of this insn. They are zero unless
284 explicit segment overrides are given. */
285 const seg_entry
*seg
[2];
287 /* PREFIX holds all the given prefix opcodes (usually null).
288 PREFIXES is the number of prefix opcodes. */
289 unsigned int prefixes
;
290 unsigned char prefix
[MAX_PREFIXES
];
292 /* RM and SIB are the modrm byte and the sib byte where the
293 addressing modes of this insn are encoded. DREX is the byte
294 added by the SSE5 instructions. */
303 typedef struct _i386_insn i386_insn
;
305 /* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
307 const char extra_symbol_chars
[] = "*%-(["
316 #if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
318 && !defined (TE_GNU) \
319 && !defined (TE_LINUX) \
320 && !defined (TE_NETWARE) \
321 && !defined (TE_FreeBSD) \
322 && !defined (TE_NetBSD)))
323 /* This array holds the chars that always start a comment. If the
324 pre-processor is disabled, these aren't very useful. The option
325 --divide will remove '/' from this list. */
326 const char *i386_comment_chars
= "#/";
327 #define SVR4_COMMENT_CHARS 1
328 #define PREFIX_SEPARATOR '\\'
331 const char *i386_comment_chars
= "#";
332 #define PREFIX_SEPARATOR '/'
335 /* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
337 .line and .file directives will appear in the pre-processed output.
338 Note that input_file.c hand checks for '#' at the beginning of the
339 first line of the input file. This is because the compiler outputs
340 #NO_APP at the beginning of its output.
341 Also note that comments started like this one will always work if
342 '/' isn't otherwise defined. */
343 const char line_comment_chars
[] = "#/";
345 const char line_separator_chars
[] = ";";
347 /* Chars that can be used to separate mant from exp in floating point
349 const char EXP_CHARS
[] = "eE";
351 /* Chars that mean this number is a floating point constant
354 const char FLT_CHARS
[] = "fFdDxX";
356 /* Tables for lexical analysis. */
357 static char mnemonic_chars
[256];
358 static char register_chars
[256];
359 static char operand_chars
[256];
360 static char identifier_chars
[256];
361 static char digit_chars
[256];
363 /* Lexical macros. */
364 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
365 #define is_operand_char(x) (operand_chars[(unsigned char) x])
366 #define is_register_char(x) (register_chars[(unsigned char) x])
367 #define is_space_char(x) ((x) == ' ')
368 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
369 #define is_digit_char(x) (digit_chars[(unsigned char) x])
371 /* All non-digit non-letter characters that may occur in an operand. */
372 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
374 /* md_assemble() always leaves the strings it's passed unaltered. To
375 effect this we maintain a stack of saved characters that we've smashed
376 with '\0's (indicating end of strings for various sub-fields of the
377 assembler instruction). */
378 static char save_stack
[32];
379 static char *save_stack_p
;
380 #define END_STRING_AND_SAVE(s) \
381 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
382 #define RESTORE_END_STRING(s) \
383 do { *(s) = *--save_stack_p; } while (0)
385 /* The instruction we're assembling. */
388 /* Possible templates for current insn. */
389 static const templates
*current_templates
;
391 /* Per instruction expressionS buffers: max displacements & immediates. */
392 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
393 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
395 /* Current operand we are working on. */
396 static int this_operand
;
398 /* We support four different modes. FLAG_CODE variable is used to distinguish
406 static enum flag_code flag_code
;
407 static unsigned int object_64bit
;
408 static int use_rela_relocations
= 0;
410 /* The names used to print error messages. */
411 static const char *flag_code_names
[] =
418 /* 1 for intel syntax,
420 static int intel_syntax
= 0;
422 /* 1 for intel mnemonic,
423 0 if att mnemonic. */
424 static int intel_mnemonic
= !SYSV386_COMPAT
;
426 /* 1 if support old (<= 2.8.1) versions of gcc. */
427 static int old_gcc
= OLDGCC_COMPAT
;
429 /* 1 if pseudo registers are permitted. */
430 static int allow_pseudo_reg
= 0;
432 /* 1 if register prefix % not required. */
433 static int allow_naked_reg
= 0;
435 /* 1 if pseudo index register, eiz/riz, is allowed . */
436 static int allow_index_reg
= 0;
446 /* Register prefix used for error message. */
447 static const char *register_prefix
= "%";
449 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452 static char stackop_size
= '\0';
454 /* Non-zero to optimize code alignment. */
455 int optimize_align_code
= 1;
457 /* Non-zero to quieten some warnings. */
458 static int quiet_warnings
= 0;
461 static const char *cpu_arch_name
= NULL
;
462 static char *cpu_sub_arch_name
= NULL
;
464 /* CPU feature flags. */
465 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
467 /* If we have selected a cpu we are generating instructions for. */
468 static int cpu_arch_tune_set
= 0;
470 /* Cpu we are generating instructions for. */
471 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
473 /* CPU feature flags of cpu we are generating instructions for. */
474 static i386_cpu_flags cpu_arch_tune_flags
;
476 /* CPU instruction set architecture used. */
477 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
479 /* CPU feature flags of instruction set architecture used. */
480 static i386_cpu_flags cpu_arch_isa_flags
;
482 /* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484 static unsigned int no_cond_jump_promotion
= 0;
486 /* Encode SSE instructions with VEX prefix. */
487 static unsigned int sse2avx
;
489 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
490 static symbolS
*GOT_symbol
;
492 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
493 unsigned int x86_dwarf2_return_column
;
495 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
496 int x86_cie_data_alignment
;
498 /* Interface to relax_segment.
499 There are 3 major relax states for 386 jump insns because the
500 different types of jumps add different sizes to frags when we're
501 figuring out what sort of jump to choose to reach a given label. */
504 #define UNCOND_JUMP 0
506 #define COND_JUMP86 2
511 #define SMALL16 (SMALL | CODE16)
513 #define BIG16 (BIG | CODE16)
517 #define INLINE __inline__
523 #define ENCODE_RELAX_STATE(type, size) \
524 ((relax_substateT) (((type) << 2) | (size)))
525 #define TYPE_FROM_RELAX_STATE(s) \
527 #define DISP_SIZE_FROM_RELAX_STATE(s) \
528 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
530 /* This table is used by relax_frag to promote short jumps to long
531 ones where necessary. SMALL (short) jumps may be promoted to BIG
532 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
533 don't allow a short jump in a 32 bit code segment to be promoted to
534 a 16 bit offset jump because it's slower (requires data size
535 prefix), and doesn't work, unless the destination is in the bottom
536 64k of the code segment (The top 16 bits of eip are zeroed). */
538 const relax_typeS md_relax_table
[] =
541 1) most positive reach of this state,
542 2) most negative reach of this state,
543 3) how many bytes this mode will have in the variable part of the frag
544 4) which index into the table to try if we can't fit into this one. */
546 /* UNCOND_JUMP states. */
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
549 /* dword jmp adds 4 bytes to frag:
550 0 extra opcode bytes, 4 displacement bytes. */
552 /* word jmp adds 2 byte2 to frag:
553 0 extra opcode bytes, 2 displacement bytes. */
556 /* COND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
562 /* word conditionals add 3 bytes to frag:
563 1 extra opcode byte, 2 displacement bytes. */
566 /* COND_JUMP86 states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
572 /* word conditionals add 4 bytes to frag:
573 1 displacement byte and a 3 byte long branch insn. */
577 static const arch_entry cpu_arch
[] =
579 { "generic32", PROCESSOR_GENERIC32
,
580 CPU_GENERIC32_FLAGS
},
581 { "generic64", PROCESSOR_GENERIC64
,
582 CPU_GENERIC64_FLAGS
},
583 { "i8086", PROCESSOR_UNKNOWN
,
585 { "i186", PROCESSOR_UNKNOWN
,
587 { "i286", PROCESSOR_UNKNOWN
,
589 { "i386", PROCESSOR_I386
,
591 { "i486", PROCESSOR_I486
,
593 { "i586", PROCESSOR_PENTIUM
,
595 { "i686", PROCESSOR_PENTIUMPRO
,
597 { "pentium", PROCESSOR_PENTIUM
,
599 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
601 { "pentiumii", PROCESSOR_PENTIUMPRO
,
603 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
605 { "pentium4", PROCESSOR_PENTIUM4
,
607 { "prescott", PROCESSOR_NOCONA
,
609 { "nocona", PROCESSOR_NOCONA
,
611 { "yonah", PROCESSOR_CORE
,
613 { "core", PROCESSOR_CORE
,
615 { "merom", PROCESSOR_CORE2
,
617 { "core2", PROCESSOR_CORE2
,
619 { "k6", PROCESSOR_K6
,
621 { "k6_2", PROCESSOR_K6
,
623 { "athlon", PROCESSOR_ATHLON
,
625 { "sledgehammer", PROCESSOR_K8
,
627 { "opteron", PROCESSOR_K8
,
629 { "k8", PROCESSOR_K8
,
631 { "amdfam10", PROCESSOR_AMDFAM10
,
632 CPU_AMDFAM10_FLAGS
},
633 { ".mmx", PROCESSOR_UNKNOWN
,
635 { ".sse", PROCESSOR_UNKNOWN
,
637 { ".sse2", PROCESSOR_UNKNOWN
,
639 { ".sse3", PROCESSOR_UNKNOWN
,
641 { ".ssse3", PROCESSOR_UNKNOWN
,
643 { ".sse4.1", PROCESSOR_UNKNOWN
,
645 { ".sse4.2", PROCESSOR_UNKNOWN
,
647 { ".sse4", PROCESSOR_UNKNOWN
,
649 { ".avx", PROCESSOR_UNKNOWN
,
651 { ".vmx", PROCESSOR_UNKNOWN
,
653 { ".smx", PROCESSOR_UNKNOWN
,
655 { ".xsave", PROCESSOR_UNKNOWN
,
657 { ".aes", PROCESSOR_UNKNOWN
,
659 { ".pclmul", PROCESSOR_UNKNOWN
,
661 { ".clmul", PROCESSOR_UNKNOWN
,
663 { ".fma", PROCESSOR_UNKNOWN
,
665 { ".movbe", PROCESSOR_UNKNOWN
,
667 { ".ept", PROCESSOR_UNKNOWN
,
669 { ".3dnow", PROCESSOR_UNKNOWN
,
671 { ".3dnowa", PROCESSOR_UNKNOWN
,
673 { ".padlock", PROCESSOR_UNKNOWN
,
675 { ".pacifica", PROCESSOR_UNKNOWN
,
677 { ".svme", PROCESSOR_UNKNOWN
,
679 { ".sse4a", PROCESSOR_UNKNOWN
,
681 { ".abm", PROCESSOR_UNKNOWN
,
683 { ".sse5", PROCESSOR_UNKNOWN
,
687 const pseudo_typeS md_pseudo_table
[] =
689 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
690 {"align", s_align_bytes
, 0},
692 {"align", s_align_ptwo
, 0},
694 {"arch", set_cpu_arch
, 0},
698 {"ffloat", float_cons
, 'f'},
699 {"dfloat", float_cons
, 'd'},
700 {"tfloat", float_cons
, 'x'},
702 {"slong", signed_cons
, 4},
703 {"noopt", s_ignore
, 0},
704 {"optim", s_ignore
, 0},
705 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
706 {"code16", set_code_flag
, CODE_16BIT
},
707 {"code32", set_code_flag
, CODE_32BIT
},
708 {"code64", set_code_flag
, CODE_64BIT
},
709 {"intel_syntax", set_intel_syntax
, 1},
710 {"att_syntax", set_intel_syntax
, 0},
711 {"intel_mnemonic", set_intel_mnemonic
, 1},
712 {"att_mnemonic", set_intel_mnemonic
, 0},
713 {"allow_index_reg", set_allow_index_reg
, 1},
714 {"disallow_index_reg", set_allow_index_reg
, 0},
715 {"sse_check", set_sse_check
, 0},
716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 {"largecomm", handle_large_common
, 0},
719 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
720 {"loc", dwarf2_directive_loc
, 0},
721 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
724 {"secrel32", pe_directive_secrel
, 0},
729 /* For interface with expression (). */
730 extern char *input_line_pointer
;
732 /* Hash table for instruction mnemonic lookup. */
733 static struct hash_control
*op_hash
;
735 /* Hash table for register lookup. */
736 static struct hash_control
*reg_hash
;
739 i386_align_code (fragS
*fragP
, int count
)
741 /* Various efficient no-op patterns for aligning code labels.
742 Note: Don't try to assemble the instructions in the comments.
743 0L and 0w are not legal. */
744 static const char f32_1
[] =
746 static const char f32_2
[] =
747 {0x66,0x90}; /* xchg %ax,%ax */
748 static const char f32_3
[] =
749 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
750 static const char f32_4
[] =
751 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
752 static const char f32_5
[] =
754 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
755 static const char f32_6
[] =
756 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
757 static const char f32_7
[] =
758 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
759 static const char f32_8
[] =
761 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
762 static const char f32_9
[] =
763 {0x89,0xf6, /* movl %esi,%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_10
[] =
766 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
767 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
768 static const char f32_11
[] =
769 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_12
[] =
772 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
773 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
774 static const char f32_13
[] =
775 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_14
[] =
778 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
780 static const char f16_3
[] =
781 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
782 static const char f16_4
[] =
783 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
784 static const char f16_5
[] =
786 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
787 static const char f16_6
[] =
788 {0x89,0xf6, /* mov %si,%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char f16_7
[] =
791 {0x8d,0x74,0x00, /* lea 0(%si),%si */
792 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
793 static const char f16_8
[] =
794 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
795 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
796 static const char jump_31
[] =
797 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
799 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
800 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
801 static const char *const f32_patt
[] = {
802 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
803 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
805 static const char *const f16_patt
[] = {
806 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
809 static const char alt_3
[] =
811 /* nopl 0(%[re]ax) */
812 static const char alt_4
[] =
813 {0x0f,0x1f,0x40,0x00};
814 /* nopl 0(%[re]ax,%[re]ax,1) */
815 static const char alt_5
[] =
816 {0x0f,0x1f,0x44,0x00,0x00};
817 /* nopw 0(%[re]ax,%[re]ax,1) */
818 static const char alt_6
[] =
819 {0x66,0x0f,0x1f,0x44,0x00,0x00};
820 /* nopl 0L(%[re]ax) */
821 static const char alt_7
[] =
822 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
823 /* nopl 0L(%[re]ax,%[re]ax,1) */
824 static const char alt_8
[] =
825 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
826 /* nopw 0L(%[re]ax,%[re]ax,1) */
827 static const char alt_9
[] =
828 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
829 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
830 static const char alt_10
[] =
831 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_11
[] =
836 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
839 nopw %cs:0L(%[re]ax,%[re]ax,1) */
840 static const char alt_long_12
[] =
843 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
847 nopw %cs:0L(%[re]ax,%[re]ax,1) */
848 static const char alt_long_13
[] =
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_long_14
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_15
[] =
876 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1)
878 nopw 0(%[re]ax,%[re]ax,1) */
879 static const char alt_short_11
[] =
880 {0x0f,0x1f,0x44,0x00,0x00,
881 0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopw 0(%[re]ax,%[re]ax,1)
883 nopw 0(%[re]ax,%[re]ax,1) */
884 static const char alt_short_12
[] =
885 {0x66,0x0f,0x1f,0x44,0x00,0x00,
886 0x66,0x0f,0x1f,0x44,0x00,0x00};
887 /* nopw 0(%[re]ax,%[re]ax,1)
889 static const char alt_short_13
[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00,
891 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
894 static const char alt_short_14
[] =
895 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
896 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
898 nopl 0L(%[re]ax,%[re]ax,1) */
899 static const char alt_short_15
[] =
900 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
901 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 static const char *const alt_short_patt
[] = {
903 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
904 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
905 alt_short_14
, alt_short_15
907 static const char *const alt_long_patt
[] = {
908 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
909 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
910 alt_long_14
, alt_long_15
913 /* Only align for at least a positive non-zero boundary. */
914 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
917 /* We need to decide which NOP sequence to use for 32bit and
918 64bit. When -mtune= is used:
920 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
921 PROCESSOR_GENERIC32, f32_patt will be used.
922 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
923 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
924 alt_long_patt will be used.
925 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
926 PROCESSOR_AMDFAM10, alt_short_patt will be used.
928 When -mtune= isn't used, alt_long_patt will be used if
929 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
932 When -march= or .arch is used, we can't use anything beyond
933 cpu_arch_isa_flags. */
935 if (flag_code
== CODE_16BIT
)
939 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
941 /* Adjust jump offset. */
942 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
945 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
946 f16_patt
[count
- 1], count
);
950 const char *const *patt
= NULL
;
952 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
954 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
955 switch (cpu_arch_tune
)
957 case PROCESSOR_UNKNOWN
:
958 /* We use cpu_arch_isa_flags to check if we SHOULD
959 optimize for Cpu686. */
960 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
961 patt
= alt_long_patt
;
965 case PROCESSOR_PENTIUMPRO
:
966 case PROCESSOR_PENTIUM4
:
967 case PROCESSOR_NOCONA
:
969 case PROCESSOR_CORE2
:
970 case PROCESSOR_GENERIC64
:
971 patt
= alt_long_patt
;
974 case PROCESSOR_ATHLON
:
976 case PROCESSOR_AMDFAM10
:
977 patt
= alt_short_patt
;
981 case PROCESSOR_PENTIUM
:
982 case PROCESSOR_GENERIC32
:
989 switch (cpu_arch_tune
)
991 case PROCESSOR_UNKNOWN
:
992 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
993 PROCESSOR_UNKNOWN. */
999 case PROCESSOR_PENTIUM
:
1001 case PROCESSOR_ATHLON
:
1003 case PROCESSOR_AMDFAM10
:
1004 case PROCESSOR_GENERIC32
:
1005 /* We use cpu_arch_isa_flags to check if we CAN optimize
1007 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1008 patt
= alt_short_patt
;
1012 case PROCESSOR_PENTIUMPRO
:
1013 case PROCESSOR_PENTIUM4
:
1014 case PROCESSOR_NOCONA
:
1015 case PROCESSOR_CORE
:
1016 case PROCESSOR_CORE2
:
1017 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1018 patt
= alt_long_patt
;
1022 case PROCESSOR_GENERIC64
:
1023 patt
= alt_long_patt
;
1028 if (patt
== f32_patt
)
1030 /* If the padding is less than 15 bytes, we use the normal
1031 ones. Otherwise, we use a jump instruction and adjust
1034 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1035 patt
[count
- 1], count
);
1038 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1040 /* Adjust jump offset. */
1041 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1046 /* Maximum length of an instruction is 15 byte. If the
1047 padding is greater than 15 bytes and we don't use jump,
1048 we have to break it into smaller pieces. */
1049 int padding
= count
;
1050 while (padding
> 15)
1053 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1058 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1059 patt
[padding
- 1], padding
);
1062 fragP
->fr_var
= count
;
1066 operand_type_all_zero (const union i386_operand_type
*x
)
1068 switch (ARRAY_SIZE(x
->array
))
1077 return !x
->array
[0];
1084 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1086 switch (ARRAY_SIZE(x
->array
))
1101 operand_type_equal (const union i386_operand_type
*x
,
1102 const union i386_operand_type
*y
)
1104 switch (ARRAY_SIZE(x
->array
))
1107 if (x
->array
[2] != y
->array
[2])
1110 if (x
->array
[1] != y
->array
[1])
1113 return x
->array
[0] == y
->array
[0];
1121 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1123 switch (ARRAY_SIZE(x
->array
))
1132 return !x
->array
[0];
1139 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1141 switch (ARRAY_SIZE(x
->array
))
1156 cpu_flags_equal (const union i386_cpu_flags
*x
,
1157 const union i386_cpu_flags
*y
)
1159 switch (ARRAY_SIZE(x
->array
))
1162 if (x
->array
[2] != y
->array
[2])
1165 if (x
->array
[1] != y
->array
[1])
1168 return x
->array
[0] == y
->array
[0];
1176 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1178 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1179 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1182 static INLINE i386_cpu_flags
1183 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1185 switch (ARRAY_SIZE (x
.array
))
1188 x
.array
[2] &= y
.array
[2];
1190 x
.array
[1] &= y
.array
[1];
1192 x
.array
[0] &= y
.array
[0];
1200 static INLINE i386_cpu_flags
1201 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1203 switch (ARRAY_SIZE (x
.array
))
1206 x
.array
[2] |= y
.array
[2];
1208 x
.array
[1] |= y
.array
[1];
1210 x
.array
[0] |= y
.array
[0];
1218 #define CPU_FLAGS_ARCH_MATCH 0x1
1219 #define CPU_FLAGS_64BIT_MATCH 0x2
1221 #define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1222 #define CPU_FLAGS_PERFECT_MATCH \
1223 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1225 /* Return CPU flags match bits. */
1228 cpu_flags_match (const template *t
)
1230 i386_cpu_flags x
= t
->cpu_flags
;
1231 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1233 x
.bitfield
.cpu64
= 0;
1234 x
.bitfield
.cpuno64
= 0;
1236 if (cpu_flags_all_zero (&x
))
1238 /* This instruction is available on all archs. */
1239 match
|= CPU_FLAGS_32BIT_MATCH
;
1243 /* This instruction is available only on some archs. */
1244 i386_cpu_flags cpu
= cpu_arch_flags
;
1246 cpu
.bitfield
.cpu64
= 0;
1247 cpu
.bitfield
.cpuno64
= 0;
1248 cpu
= cpu_flags_and (x
, cpu
);
1249 if (!cpu_flags_all_zero (&cpu
))
1252 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1253 match
|= CPU_FLAGS_32BIT_MATCH
;
1259 static INLINE i386_operand_type
1260 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1262 switch (ARRAY_SIZE (x
.array
))
1265 x
.array
[2] &= y
.array
[2];
1267 x
.array
[1] &= y
.array
[1];
1269 x
.array
[0] &= y
.array
[0];
1277 static INLINE i386_operand_type
1278 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1280 switch (ARRAY_SIZE (x
.array
))
1283 x
.array
[2] |= y
.array
[2];
1285 x
.array
[1] |= y
.array
[1];
1287 x
.array
[0] |= y
.array
[0];
1295 static INLINE i386_operand_type
1296 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1298 switch (ARRAY_SIZE (x
.array
))
1301 x
.array
[2] ^= y
.array
[2];
1303 x
.array
[1] ^= y
.array
[1];
1305 x
.array
[0] ^= y
.array
[0];
1313 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1314 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1315 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1316 static const i386_operand_type inoutportreg
1317 = OPERAND_TYPE_INOUTPORTREG
;
1318 static const i386_operand_type reg16_inoutportreg
1319 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1320 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1321 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1322 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1323 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1324 static const i386_operand_type anydisp
1325 = OPERAND_TYPE_ANYDISP
;
1326 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1327 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1328 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1329 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1330 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1331 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1332 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1333 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1334 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1335 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1336 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1337 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1348 operand_type_check (i386_operand_type t
, enum operand_type c
)
1353 return (t
.bitfield
.reg8
1356 || t
.bitfield
.reg64
);
1359 return (t
.bitfield
.imm8
1363 || t
.bitfield
.imm32s
1364 || t
.bitfield
.imm64
);
1367 return (t
.bitfield
.disp8
1368 || t
.bitfield
.disp16
1369 || t
.bitfield
.disp32
1370 || t
.bitfield
.disp32s
1371 || t
.bitfield
.disp64
);
1374 return (t
.bitfield
.disp8
1375 || t
.bitfield
.disp16
1376 || t
.bitfield
.disp32
1377 || t
.bitfield
.disp32s
1378 || t
.bitfield
.disp64
1379 || t
.bitfield
.baseindex
);
1386 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1387 operand J for instruction template T. */
1390 match_reg_size (const template *t
, unsigned int j
)
1392 return !((i
.types
[j
].bitfield
.byte
1393 && !t
->operand_types
[j
].bitfield
.byte
)
1394 || (i
.types
[j
].bitfield
.word
1395 && !t
->operand_types
[j
].bitfield
.word
)
1396 || (i
.types
[j
].bitfield
.dword
1397 && !t
->operand_types
[j
].bitfield
.dword
)
1398 || (i
.types
[j
].bitfield
.qword
1399 && !t
->operand_types
[j
].bitfield
.qword
));
1402 /* Return 1 if there is no conflict in any size on operand J for
1403 instruction template T. */
1406 match_mem_size (const template *t
, unsigned int j
)
1408 return (match_reg_size (t
, j
)
1409 && !((i
.types
[j
].bitfield
.unspecified
1410 && !t
->operand_types
[j
].bitfield
.unspecified
)
1411 || (i
.types
[j
].bitfield
.fword
1412 && !t
->operand_types
[j
].bitfield
.fword
)
1413 || (i
.types
[j
].bitfield
.tbyte
1414 && !t
->operand_types
[j
].bitfield
.tbyte
)
1415 || (i
.types
[j
].bitfield
.xmmword
1416 && !t
->operand_types
[j
].bitfield
.xmmword
)
1417 || (i
.types
[j
].bitfield
.ymmword
1418 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1421 /* Return 1 if there is no size conflict on any operands for
1422 instruction template T. */
1425 operand_size_match (const template *t
)
1430 /* Don't check jump instructions. */
1431 if (t
->opcode_modifier
.jump
1432 || t
->opcode_modifier
.jumpbyte
1433 || t
->opcode_modifier
.jumpdword
1434 || t
->opcode_modifier
.jumpintersegment
)
1437 /* Check memory and accumulator operand size. */
1438 for (j
= 0; j
< i
.operands
; j
++)
1440 if (t
->operand_types
[j
].bitfield
.anysize
)
1443 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1449 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1457 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1460 /* Check reverse. */
1461 assert (i
.operands
== 2);
1464 for (j
= 0; j
< 2; j
++)
1466 if (t
->operand_types
[j
].bitfield
.acc
1467 && !match_reg_size (t
, j
? 0 : 1))
1473 if (i
.types
[j
].bitfield
.mem
1474 && !match_mem_size (t
, j
? 0 : 1))
1485 operand_type_match (i386_operand_type overlap
,
1486 i386_operand_type given
)
1488 i386_operand_type temp
= overlap
;
1490 temp
.bitfield
.jumpabsolute
= 0;
1491 temp
.bitfield
.unspecified
= 0;
1492 temp
.bitfield
.byte
= 0;
1493 temp
.bitfield
.word
= 0;
1494 temp
.bitfield
.dword
= 0;
1495 temp
.bitfield
.fword
= 0;
1496 temp
.bitfield
.qword
= 0;
1497 temp
.bitfield
.tbyte
= 0;
1498 temp
.bitfield
.xmmword
= 0;
1499 temp
.bitfield
.ymmword
= 0;
1500 if (operand_type_all_zero (&temp
))
1503 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1504 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1507 /* If given types g0 and g1 are registers they must be of the same type
1508 unless the expected operand type register overlap is null.
1509 Note that Acc in a template matches every size of reg. */
1512 operand_type_register_match (i386_operand_type m0
,
1513 i386_operand_type g0
,
1514 i386_operand_type t0
,
1515 i386_operand_type m1
,
1516 i386_operand_type g1
,
1517 i386_operand_type t1
)
1519 if (!operand_type_check (g0
, reg
))
1522 if (!operand_type_check (g1
, reg
))
1525 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1526 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1527 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1528 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1531 if (m0
.bitfield
.acc
)
1533 t0
.bitfield
.reg8
= 1;
1534 t0
.bitfield
.reg16
= 1;
1535 t0
.bitfield
.reg32
= 1;
1536 t0
.bitfield
.reg64
= 1;
1539 if (m1
.bitfield
.acc
)
1541 t1
.bitfield
.reg8
= 1;
1542 t1
.bitfield
.reg16
= 1;
1543 t1
.bitfield
.reg32
= 1;
1544 t1
.bitfield
.reg64
= 1;
1547 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1548 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1549 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1550 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1553 static INLINE
unsigned int
1554 mode_from_disp_size (i386_operand_type t
)
1556 if (t
.bitfield
.disp8
)
1558 else if (t
.bitfield
.disp16
1559 || t
.bitfield
.disp32
1560 || t
.bitfield
.disp32s
)
1567 fits_in_signed_byte (offsetT num
)
1569 return (num
>= -128) && (num
<= 127);
1573 fits_in_unsigned_byte (offsetT num
)
1575 return (num
& 0xff) == num
;
1579 fits_in_unsigned_word (offsetT num
)
1581 return (num
& 0xffff) == num
;
1585 fits_in_signed_word (offsetT num
)
1587 return (-32768 <= num
) && (num
<= 32767);
1591 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1596 return (!(((offsetT
) -1 << 31) & num
)
1597 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1599 } /* fits_in_signed_long() */
1602 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1607 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1609 } /* fits_in_unsigned_long() */
1612 fits_in_imm4 (offsetT num
)
1614 return (num
& 0xf) == num
;
1617 static i386_operand_type
1618 smallest_imm_type (offsetT num
)
1620 i386_operand_type t
;
1622 operand_type_set (&t
, 0);
1623 t
.bitfield
.imm64
= 1;
1625 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1627 /* This code is disabled on the 486 because all the Imm1 forms
1628 in the opcode table are slower on the i486. They're the
1629 versions with the implicitly specified single-position
1630 displacement, which has another syntax if you really want to
1632 t
.bitfield
.imm1
= 1;
1633 t
.bitfield
.imm8
= 1;
1634 t
.bitfield
.imm8s
= 1;
1635 t
.bitfield
.imm16
= 1;
1636 t
.bitfield
.imm32
= 1;
1637 t
.bitfield
.imm32s
= 1;
1639 else if (fits_in_signed_byte (num
))
1641 t
.bitfield
.imm8
= 1;
1642 t
.bitfield
.imm8s
= 1;
1643 t
.bitfield
.imm16
= 1;
1644 t
.bitfield
.imm32
= 1;
1645 t
.bitfield
.imm32s
= 1;
1647 else if (fits_in_unsigned_byte (num
))
1649 t
.bitfield
.imm8
= 1;
1650 t
.bitfield
.imm16
= 1;
1651 t
.bitfield
.imm32
= 1;
1652 t
.bitfield
.imm32s
= 1;
1654 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1656 t
.bitfield
.imm16
= 1;
1657 t
.bitfield
.imm32
= 1;
1658 t
.bitfield
.imm32s
= 1;
1660 else if (fits_in_signed_long (num
))
1662 t
.bitfield
.imm32
= 1;
1663 t
.bitfield
.imm32s
= 1;
1665 else if (fits_in_unsigned_long (num
))
1666 t
.bitfield
.imm32
= 1;
1672 offset_in_range (offsetT val
, int size
)
1678 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1679 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1680 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1682 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1687 /* If BFD64, sign extend val. */
1688 if (!use_rela_relocations
)
1689 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1690 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1692 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1694 char buf1
[40], buf2
[40];
1696 sprint_value (buf1
, val
);
1697 sprint_value (buf2
, val
& mask
);
1698 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1703 /* Returns 0 if attempting to add a prefix where one from the same
1704 class already exists, 1 if non rep/repne added, 2 if rep/repne
1707 add_prefix (unsigned int prefix
)
1712 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1713 && flag_code
== CODE_64BIT
)
1715 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1716 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1717 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1728 case CS_PREFIX_OPCODE
:
1729 case DS_PREFIX_OPCODE
:
1730 case ES_PREFIX_OPCODE
:
1731 case FS_PREFIX_OPCODE
:
1732 case GS_PREFIX_OPCODE
:
1733 case SS_PREFIX_OPCODE
:
1737 case REPNE_PREFIX_OPCODE
:
1738 case REPE_PREFIX_OPCODE
:
1741 case LOCK_PREFIX_OPCODE
:
1749 case ADDR_PREFIX_OPCODE
:
1753 case DATA_PREFIX_OPCODE
:
1757 if (i
.prefix
[q
] != 0)
1765 i
.prefix
[q
] |= prefix
;
1768 as_bad (_("same type of prefix used twice"));
1774 set_code_flag (int value
)
1777 if (flag_code
== CODE_64BIT
)
1779 cpu_arch_flags
.bitfield
.cpu64
= 1;
1780 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1784 cpu_arch_flags
.bitfield
.cpu64
= 0;
1785 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1787 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1789 as_bad (_("64bit mode not supported on this CPU."));
1791 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1793 as_bad (_("32bit mode not supported on this CPU."));
1795 stackop_size
= '\0';
1799 set_16bit_gcc_code_flag (int new_code_flag
)
1801 flag_code
= new_code_flag
;
1802 if (flag_code
!= CODE_16BIT
)
1804 cpu_arch_flags
.bitfield
.cpu64
= 0;
1805 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1806 stackop_size
= LONG_MNEM_SUFFIX
;
1810 set_intel_syntax (int syntax_flag
)
1812 /* Find out if register prefixing is specified. */
1813 int ask_naked_reg
= 0;
1816 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1818 char *string
= input_line_pointer
;
1819 int e
= get_symbol_end ();
1821 if (strcmp (string
, "prefix") == 0)
1823 else if (strcmp (string
, "noprefix") == 0)
1826 as_bad (_("bad argument to syntax directive."));
1827 *input_line_pointer
= e
;
1829 demand_empty_rest_of_line ();
1831 intel_syntax
= syntax_flag
;
1833 if (ask_naked_reg
== 0)
1834 allow_naked_reg
= (intel_syntax
1835 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1837 allow_naked_reg
= (ask_naked_reg
< 0);
1839 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1840 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1841 register_prefix
= allow_naked_reg
? "" : "%";
1845 set_intel_mnemonic (int mnemonic_flag
)
1847 intel_mnemonic
= mnemonic_flag
;
1851 set_allow_index_reg (int flag
)
1853 allow_index_reg
= flag
;
1857 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1861 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1863 char *string
= input_line_pointer
;
1864 int e
= get_symbol_end ();
1866 if (strcmp (string
, "none") == 0)
1867 sse_check
= sse_check_none
;
1868 else if (strcmp (string
, "warning") == 0)
1869 sse_check
= sse_check_warning
;
1870 else if (strcmp (string
, "error") == 0)
1871 sse_check
= sse_check_error
;
1873 as_bad (_("bad argument to sse_check directive."));
1874 *input_line_pointer
= e
;
1877 as_bad (_("missing argument for sse_check directive"));
1879 demand_empty_rest_of_line ();
1883 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1887 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1889 char *string
= input_line_pointer
;
1890 int e
= get_symbol_end ();
1892 i386_cpu_flags flags
;
1894 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1896 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1900 cpu_arch_name
= cpu_arch
[i
].name
;
1901 cpu_sub_arch_name
= NULL
;
1902 cpu_arch_flags
= cpu_arch
[i
].flags
;
1903 if (flag_code
== CODE_64BIT
)
1905 cpu_arch_flags
.bitfield
.cpu64
= 1;
1906 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1910 cpu_arch_flags
.bitfield
.cpu64
= 0;
1911 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1913 cpu_arch_isa
= cpu_arch
[i
].type
;
1914 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1915 if (!cpu_arch_tune_set
)
1917 cpu_arch_tune
= cpu_arch_isa
;
1918 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1923 flags
= cpu_flags_or (cpu_arch_flags
,
1925 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1927 if (cpu_sub_arch_name
)
1929 char *name
= cpu_sub_arch_name
;
1930 cpu_sub_arch_name
= concat (name
,
1932 (const char *) NULL
);
1936 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1937 cpu_arch_flags
= flags
;
1939 *input_line_pointer
= e
;
1940 demand_empty_rest_of_line ();
1944 if (i
>= ARRAY_SIZE (cpu_arch
))
1945 as_bad (_("no such architecture: `%s'"), string
);
1947 *input_line_pointer
= e
;
1950 as_bad (_("missing cpu architecture"));
1952 no_cond_jump_promotion
= 0;
1953 if (*input_line_pointer
== ','
1954 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1956 char *string
= ++input_line_pointer
;
1957 int e
= get_symbol_end ();
1959 if (strcmp (string
, "nojumps") == 0)
1960 no_cond_jump_promotion
= 1;
1961 else if (strcmp (string
, "jumps") == 0)
1964 as_bad (_("no such architecture modifier: `%s'"), string
);
1966 *input_line_pointer
= e
;
1969 demand_empty_rest_of_line ();
1975 if (!strcmp (default_arch
, "x86_64"))
1976 return bfd_mach_x86_64
;
1977 else if (!strcmp (default_arch
, "i386"))
1978 return bfd_mach_i386_i386
;
1980 as_fatal (_("Unknown architecture"));
1986 const char *hash_err
;
1988 /* Initialize op_hash hash table. */
1989 op_hash
= hash_new ();
1992 const template *optab
;
1993 templates
*core_optab
;
1995 /* Setup for loop. */
1997 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1998 core_optab
->start
= optab
;
2003 if (optab
->name
== NULL
2004 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2006 /* different name --> ship out current template list;
2007 add to hash table; & begin anew. */
2008 core_optab
->end
= optab
;
2009 hash_err
= hash_insert (op_hash
,
2014 as_fatal (_("Internal Error: Can't hash %s: %s"),
2018 if (optab
->name
== NULL
)
2020 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2021 core_optab
->start
= optab
;
2026 /* Initialize reg_hash hash table. */
2027 reg_hash
= hash_new ();
2029 const reg_entry
*regtab
;
2030 unsigned int regtab_size
= i386_regtab_size
;
2032 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2034 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
2036 as_fatal (_("Internal Error: Can't hash %s: %s"),
2042 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2047 for (c
= 0; c
< 256; c
++)
2052 mnemonic_chars
[c
] = c
;
2053 register_chars
[c
] = c
;
2054 operand_chars
[c
] = c
;
2056 else if (ISLOWER (c
))
2058 mnemonic_chars
[c
] = c
;
2059 register_chars
[c
] = c
;
2060 operand_chars
[c
] = c
;
2062 else if (ISUPPER (c
))
2064 mnemonic_chars
[c
] = TOLOWER (c
);
2065 register_chars
[c
] = mnemonic_chars
[c
];
2066 operand_chars
[c
] = c
;
2069 if (ISALPHA (c
) || ISDIGIT (c
))
2070 identifier_chars
[c
] = c
;
2073 identifier_chars
[c
] = c
;
2074 operand_chars
[c
] = c
;
2079 identifier_chars
['@'] = '@';
2082 identifier_chars
['?'] = '?';
2083 operand_chars
['?'] = '?';
2085 digit_chars
['-'] = '-';
2086 mnemonic_chars
['_'] = '_';
2087 mnemonic_chars
['-'] = '-';
2088 mnemonic_chars
['.'] = '.';
2089 identifier_chars
['_'] = '_';
2090 identifier_chars
['.'] = '.';
2092 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2093 operand_chars
[(unsigned char) *p
] = *p
;
2096 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2099 record_alignment (text_section
, 2);
2100 record_alignment (data_section
, 2);
2101 record_alignment (bss_section
, 2);
2105 if (flag_code
== CODE_64BIT
)
2107 x86_dwarf2_return_column
= 16;
2108 x86_cie_data_alignment
= -8;
2112 x86_dwarf2_return_column
= 8;
2113 x86_cie_data_alignment
= -4;
2118 i386_print_statistics (FILE *file
)
2120 hash_print_statistics (file
, "i386 opcode", op_hash
);
2121 hash_print_statistics (file
, "i386 register", reg_hash
);
2126 /* Debugging routines for md_assemble. */
2127 static void pte (template *);
2128 static void pt (i386_operand_type
);
2129 static void pe (expressionS
*);
2130 static void ps (symbolS
*);
2133 pi (char *line
, i386_insn
*x
)
2137 fprintf (stdout
, "%s: template ", line
);
2139 fprintf (stdout
, " address: base %s index %s scale %x\n",
2140 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2141 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2142 x
->log2_scale_factor
);
2143 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2144 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2145 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2146 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2147 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2148 (x
->rex
& REX_W
) != 0,
2149 (x
->rex
& REX_R
) != 0,
2150 (x
->rex
& REX_X
) != 0,
2151 (x
->rex
& REX_B
) != 0);
2152 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2153 x
->drex
.reg
, x
->drex
.rex
);
2154 for (i
= 0; i
< x
->operands
; i
++)
2156 fprintf (stdout
, " #%d: ", i
+ 1);
2158 fprintf (stdout
, "\n");
2159 if (x
->types
[i
].bitfield
.reg8
2160 || x
->types
[i
].bitfield
.reg16
2161 || x
->types
[i
].bitfield
.reg32
2162 || x
->types
[i
].bitfield
.reg64
2163 || x
->types
[i
].bitfield
.regmmx
2164 || x
->types
[i
].bitfield
.regxmm
2165 || x
->types
[i
].bitfield
.regymm
2166 || x
->types
[i
].bitfield
.sreg2
2167 || x
->types
[i
].bitfield
.sreg3
2168 || x
->types
[i
].bitfield
.control
2169 || x
->types
[i
].bitfield
.debug
2170 || x
->types
[i
].bitfield
.test
)
2171 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2172 if (operand_type_check (x
->types
[i
], imm
))
2174 if (operand_type_check (x
->types
[i
], disp
))
2175 pe (x
->op
[i
].disps
);
2183 fprintf (stdout
, " %d operands ", t
->operands
);
2184 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2185 if (t
->extension_opcode
!= None
)
2186 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2187 if (t
->opcode_modifier
.d
)
2188 fprintf (stdout
, "D");
2189 if (t
->opcode_modifier
.w
)
2190 fprintf (stdout
, "W");
2191 fprintf (stdout
, "\n");
2192 for (i
= 0; i
< t
->operands
; i
++)
2194 fprintf (stdout
, " #%d type ", i
+ 1);
2195 pt (t
->operand_types
[i
]);
2196 fprintf (stdout
, "\n");
2203 fprintf (stdout
, " operation %d\n", e
->X_op
);
2204 fprintf (stdout
, " add_number %ld (%lx)\n",
2205 (long) e
->X_add_number
, (long) e
->X_add_number
);
2206 if (e
->X_add_symbol
)
2208 fprintf (stdout
, " add_symbol ");
2209 ps (e
->X_add_symbol
);
2210 fprintf (stdout
, "\n");
2214 fprintf (stdout
, " op_symbol ");
2215 ps (e
->X_op_symbol
);
2216 fprintf (stdout
, "\n");
2223 fprintf (stdout
, "%s type %s%s",
2225 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2226 segment_name (S_GET_SEGMENT (s
)));
2229 static struct type_name
2231 i386_operand_type mask
;
2234 const type_names
[] =
2236 { OPERAND_TYPE_REG8
, "r8" },
2237 { OPERAND_TYPE_REG16
, "r16" },
2238 { OPERAND_TYPE_REG32
, "r32" },
2239 { OPERAND_TYPE_REG64
, "r64" },
2240 { OPERAND_TYPE_IMM8
, "i8" },
2241 { OPERAND_TYPE_IMM8
, "i8s" },
2242 { OPERAND_TYPE_IMM16
, "i16" },
2243 { OPERAND_TYPE_IMM32
, "i32" },
2244 { OPERAND_TYPE_IMM32S
, "i32s" },
2245 { OPERAND_TYPE_IMM64
, "i64" },
2246 { OPERAND_TYPE_IMM1
, "i1" },
2247 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2248 { OPERAND_TYPE_DISP8
, "d8" },
2249 { OPERAND_TYPE_DISP16
, "d16" },
2250 { OPERAND_TYPE_DISP32
, "d32" },
2251 { OPERAND_TYPE_DISP32S
, "d32s" },
2252 { OPERAND_TYPE_DISP64
, "d64" },
2253 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2254 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2255 { OPERAND_TYPE_CONTROL
, "control reg" },
2256 { OPERAND_TYPE_TEST
, "test reg" },
2257 { OPERAND_TYPE_DEBUG
, "debug reg" },
2258 { OPERAND_TYPE_FLOATREG
, "FReg" },
2259 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2260 { OPERAND_TYPE_SREG2
, "SReg2" },
2261 { OPERAND_TYPE_SREG3
, "SReg3" },
2262 { OPERAND_TYPE_ACC
, "Acc" },
2263 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2264 { OPERAND_TYPE_REGMMX
, "rMMX" },
2265 { OPERAND_TYPE_REGXMM
, "rXMM" },
2266 { OPERAND_TYPE_ESSEG
, "es" },
2267 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2271 pt (i386_operand_type t
)
2274 i386_operand_type a
;
2276 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2278 a
= operand_type_and (t
, type_names
[j
].mask
);
2279 if (!UINTS_ALL_ZERO (a
))
2280 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2285 #endif /* DEBUG386 */
2287 static bfd_reloc_code_real_type
2288 reloc (unsigned int size
,
2291 bfd_reloc_code_real_type other
)
2293 if (other
!= NO_RELOC
)
2295 reloc_howto_type
*reloc
;
2300 case BFD_RELOC_X86_64_GOT32
:
2301 return BFD_RELOC_X86_64_GOT64
;
2303 case BFD_RELOC_X86_64_PLTOFF64
:
2304 return BFD_RELOC_X86_64_PLTOFF64
;
2306 case BFD_RELOC_X86_64_GOTPC32
:
2307 other
= BFD_RELOC_X86_64_GOTPC64
;
2309 case BFD_RELOC_X86_64_GOTPCREL
:
2310 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2312 case BFD_RELOC_X86_64_TPOFF32
:
2313 other
= BFD_RELOC_X86_64_TPOFF64
;
2315 case BFD_RELOC_X86_64_DTPOFF32
:
2316 other
= BFD_RELOC_X86_64_DTPOFF64
;
2322 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2323 if (size
== 4 && flag_code
!= CODE_64BIT
)
2326 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2328 as_bad (_("unknown relocation (%u)"), other
);
2329 else if (size
!= bfd_get_reloc_size (reloc
))
2330 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2331 bfd_get_reloc_size (reloc
),
2333 else if (pcrel
&& !reloc
->pc_relative
)
2334 as_bad (_("non-pc-relative relocation for pc-relative field"));
2335 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2337 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2339 as_bad (_("relocated field and relocation type differ in signedness"));
2348 as_bad (_("there are no unsigned pc-relative relocations"));
2351 case 1: return BFD_RELOC_8_PCREL
;
2352 case 2: return BFD_RELOC_16_PCREL
;
2353 case 4: return BFD_RELOC_32_PCREL
;
2354 case 8: return BFD_RELOC_64_PCREL
;
2356 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2363 case 4: return BFD_RELOC_X86_64_32S
;
2368 case 1: return BFD_RELOC_8
;
2369 case 2: return BFD_RELOC_16
;
2370 case 4: return BFD_RELOC_32
;
2371 case 8: return BFD_RELOC_64
;
2373 as_bad (_("cannot do %s %u byte relocation"),
2374 sign
> 0 ? "signed" : "unsigned", size
);
2378 return BFD_RELOC_NONE
;
2381 /* Here we decide which fixups can be adjusted to make them relative to
2382 the beginning of the section instead of the symbol. Basically we need
2383 to make sure that the dynamic relocations are done correctly, so in
2384 some cases we force the original symbol to be used. */
2387 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2393 /* Don't adjust pc-relative references to merge sections in 64-bit
2395 if (use_rela_relocations
2396 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2400 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2401 and changed later by validate_fix. */
2402 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2403 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2406 /* adjust_reloc_syms doesn't know about the GOT. */
2407 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2408 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2409 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2410 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2411 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2412 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2413 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2414 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2415 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2416 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2417 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2418 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2419 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2425 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2426 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2427 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2428 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2429 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2430 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2431 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2432 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2433 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2434 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2441 intel_float_operand (const char *mnemonic
)
2443 /* Note that the value returned is meaningful only for opcodes with (memory)
2444 operands, hence the code here is free to improperly handle opcodes that
2445 have no operands (for better performance and smaller code). */
2447 if (mnemonic
[0] != 'f')
2448 return 0; /* non-math */
2450 switch (mnemonic
[1])
2452 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2453 the fs segment override prefix not currently handled because no
2454 call path can make opcodes without operands get here */
2456 return 2 /* integer op */;
2458 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2459 return 3; /* fldcw/fldenv */
2462 if (mnemonic
[2] != 'o' /* fnop */)
2463 return 3; /* non-waiting control op */
2466 if (mnemonic
[2] == 's')
2467 return 3; /* frstor/frstpm */
2470 if (mnemonic
[2] == 'a')
2471 return 3; /* fsave */
2472 if (mnemonic
[2] == 't')
2474 switch (mnemonic
[3])
2476 case 'c': /* fstcw */
2477 case 'd': /* fstdw */
2478 case 'e': /* fstenv */
2479 case 's': /* fsts[gw] */
2485 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2486 return 0; /* fxsave/fxrstor are not really math ops */
2493 /* Build the VEX prefix. */
2496 build_vex_prefix (void)
2498 unsigned int register_specifier
;
2499 unsigned int implied_prefix
;
2500 unsigned int vector_length
;
2502 /* Check register specifier. */
2503 if (i
.vex
.register_specifier
)
2505 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2506 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2507 register_specifier
+= 8;
2508 register_specifier
= ~register_specifier
& 0xf;
2511 register_specifier
= 0xf;
2513 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2515 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2520 case DATA_PREFIX_OPCODE
:
2523 case REPE_PREFIX_OPCODE
:
2526 case REPNE_PREFIX_OPCODE
:
2533 /* Use 2-byte VEX prefix if possible. */
2534 if (i
.tm
.opcode_modifier
.vex0f
2535 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2537 /* 2-byte VEX prefix. */
2541 i
.vex
.bytes
[0] = 0xc5;
2543 /* Check the REX.R bit. */
2544 r
= (i
.rex
& REX_R
) ? 0 : 1;
2545 i
.vex
.bytes
[1] = (r
<< 7
2546 | register_specifier
<< 3
2547 | vector_length
<< 2
2552 /* 3-byte VEX prefix. */
2555 if (i
.tm
.opcode_modifier
.vex0f
)
2557 else if (i
.tm
.opcode_modifier
.vex0f38
)
2559 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2565 i
.vex
.bytes
[0] = 0xc4;
2567 /* The high 3 bits of the second VEX byte are 1's compliment
2568 of RXB bits from REX. */
2569 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2571 /* Check the REX.W bit. */
2572 w
= (i
.rex
& REX_W
) ? 1 : 0;
2573 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2578 if (i
.tm
.opcode_modifier
.vexw1
)
2582 i
.vex
.bytes
[2] = (w
<< 7
2583 | register_specifier
<< 3
2584 | vector_length
<< 2
2590 process_immext (void)
2594 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2596 /* SSE3 Instructions have the fixed operands with an opcode
2597 suffix which is coded in the same place as an 8-bit immediate
2598 field would be. Here we check those operands and remove them
2602 for (x
= 0; x
< i
.operands
; x
++)
2603 if (i
.op
[x
].regs
->reg_num
!= x
)
2604 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2605 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2611 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2612 which is coded in the same place as an 8-bit immediate field
2613 would be. Here we fake an 8-bit immediate operand from the
2614 opcode suffix stored in tm.extension_opcode.
2616 SSE5 and AVX instructions also use this encoding, for some of
2617 3 argument instructions. */
2619 assert (i
.imm_operands
== 0
2621 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2623 || (i
.tm
.opcode_modifier
.vex
2624 && i
.operands
<= 4)));
2626 exp
= &im_expressions
[i
.imm_operands
++];
2627 i
.op
[i
.operands
].imms
= exp
;
2628 i
.types
[i
.operands
] = imm8
;
2630 exp
->X_op
= O_constant
;
2631 exp
->X_add_number
= i
.tm
.extension_opcode
;
2632 i
.tm
.extension_opcode
= None
;
2635 /* This is the guts of the machine-dependent assembler. LINE points to a
2636 machine dependent instruction. This function is supposed to emit
2637 the frags/bytes it assembles to. */
2640 md_assemble (char *line
)
2643 char mnemonic
[MAX_MNEM_SIZE
];
2645 /* Initialize globals. */
2646 memset (&i
, '\0', sizeof (i
));
2647 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2648 i
.reloc
[j
] = NO_RELOC
;
2649 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2650 memset (im_expressions
, '\0', sizeof (im_expressions
));
2651 save_stack_p
= save_stack
;
2653 /* First parse an instruction mnemonic & call i386_operand for the operands.
2654 We assume that the scrubber has arranged it so that line[0] is the valid
2655 start of a (possibly prefixed) mnemonic. */
2657 line
= parse_insn (line
, mnemonic
);
2661 line
= parse_operands (line
, mnemonic
);
2665 /* Now we've parsed the mnemonic into a set of templates, and have the
2666 operands at hand. */
2668 /* All intel opcodes have reversed operands except for "bound" and
2669 "enter". We also don't reverse intersegment "jmp" and "call"
2670 instructions with 2 immediate operands so that the immediate segment
2671 precedes the offset, as it does when in AT&T mode. */
2674 && (strcmp (mnemonic
, "bound") != 0)
2675 && (strcmp (mnemonic
, "invlpga") != 0)
2676 && !(operand_type_check (i
.types
[0], imm
)
2677 && operand_type_check (i
.types
[1], imm
)))
2680 /* The order of the immediates should be reversed
2681 for 2 immediates extrq and insertq instructions */
2682 if (i
.imm_operands
== 2
2683 && (strcmp (mnemonic
, "extrq") == 0
2684 || strcmp (mnemonic
, "insertq") == 0))
2685 swap_2_operands (0, 1);
2690 /* Don't optimize displacement for movabs since it only takes 64bit
2693 && (flag_code
!= CODE_64BIT
2694 || strcmp (mnemonic
, "movabs") != 0))
2697 /* Next, we find a template that matches the given insn,
2698 making sure the overlap of the given operands types is consistent
2699 with the template operand types. */
2701 if (!match_template ())
2704 if (sse_check
!= sse_check_none
2705 && !i
.tm
.opcode_modifier
.noavx
2706 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2707 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2708 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2709 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2710 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2711 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2713 (sse_check
== sse_check_warning
2715 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2718 /* Zap movzx and movsx suffix. The suffix has been set from
2719 "word ptr" or "byte ptr" on the source operand in Intel syntax
2720 or extracted from mnemonic in AT&T syntax. But we'll use
2721 the destination register to choose the suffix for encoding. */
2722 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2724 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2725 there is no suffix, the default will be byte extension. */
2726 if (i
.reg_operands
!= 2
2729 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2734 if (i
.tm
.opcode_modifier
.fwait
)
2735 if (!add_prefix (FWAIT_OPCODE
))
2738 /* Check string instruction segment overrides. */
2739 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2741 if (!check_string ())
2745 if (!process_suffix ())
2748 /* Make still unresolved immediate matches conform to size of immediate
2749 given in i.suffix. */
2750 if (!finalize_imm ())
2753 if (i
.types
[0].bitfield
.imm1
)
2754 i
.imm_operands
= 0; /* kludge for shift insns. */
2756 for (j
= 0; j
< 3; j
++)
2757 if (i
.types
[j
].bitfield
.inoutportreg
2758 || i
.types
[j
].bitfield
.shiftcount
2759 || i
.types
[j
].bitfield
.acc
2760 || i
.types
[j
].bitfield
.floatacc
)
2763 /* ImmExt should be processed after SSE2AVX. */
2764 if (!i
.tm
.opcode_modifier
.sse2avx
2765 && i
.tm
.opcode_modifier
.immext
)
2768 /* For insns with operands there are more diddles to do to the opcode. */
2771 if (!process_operands ())
2774 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2776 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2777 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2780 if (i
.tm
.opcode_modifier
.vex
)
2781 build_vex_prefix ();
2783 /* Handle conversion of 'int $3' --> special int3 insn. */
2784 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2786 i
.tm
.base_opcode
= INT3_OPCODE
;
2790 if ((i
.tm
.opcode_modifier
.jump
2791 || i
.tm
.opcode_modifier
.jumpbyte
2792 || i
.tm
.opcode_modifier
.jumpdword
)
2793 && i
.op
[0].disps
->X_op
== O_constant
)
2795 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2796 the absolute address given by the constant. Since ix86 jumps and
2797 calls are pc relative, we need to generate a reloc. */
2798 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2799 i
.op
[0].disps
->X_op
= O_symbol
;
2802 if (i
.tm
.opcode_modifier
.rex64
)
2805 /* For 8 bit registers we need an empty rex prefix. Also if the
2806 instruction already has a prefix, we need to convert old
2807 registers to new ones. */
2809 if ((i
.types
[0].bitfield
.reg8
2810 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2811 || (i
.types
[1].bitfield
.reg8
2812 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2813 || ((i
.types
[0].bitfield
.reg8
2814 || i
.types
[1].bitfield
.reg8
)
2819 i
.rex
|= REX_OPCODE
;
2820 for (x
= 0; x
< 2; x
++)
2822 /* Look for 8 bit operand that uses old registers. */
2823 if (i
.types
[x
].bitfield
.reg8
2824 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2826 /* In case it is "hi" register, give up. */
2827 if (i
.op
[x
].regs
->reg_num
> 3)
2828 as_bad (_("can't encode register '%s%s' in an "
2829 "instruction requiring REX prefix."),
2830 register_prefix
, i
.op
[x
].regs
->reg_name
);
2832 /* Otherwise it is equivalent to the extended register.
2833 Since the encoding doesn't change this is merely
2834 cosmetic cleanup for debug output. */
2836 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2841 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2843 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2848 else if (i
.rex
!= 0)
2849 add_prefix (REX_OPCODE
| i
.rex
);
2851 /* We are ready to output the insn. */
2856 parse_insn (char *line
, char *mnemonic
)
2859 char *token_start
= l
;
2864 /* Non-zero if we found a prefix only acceptable with string insns. */
2865 const char *expecting_string_instruction
= NULL
;
2870 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2873 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2875 as_bad (_("no such instruction: `%s'"), token_start
);
2880 if (!is_space_char (*l
)
2881 && *l
!= END_OF_INSN
2883 || (*l
!= PREFIX_SEPARATOR
2886 as_bad (_("invalid character %s in mnemonic"),
2887 output_invalid (*l
));
2890 if (token_start
== l
)
2892 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2893 as_bad (_("expecting prefix; got nothing"));
2895 as_bad (_("expecting mnemonic; got nothing"));
2899 /* Look up instruction (or prefix) via hash table. */
2900 current_templates
= hash_find (op_hash
, mnemonic
);
2902 if (*l
!= END_OF_INSN
2903 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2904 && current_templates
2905 && current_templates
->start
->opcode_modifier
.isprefix
)
2907 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2909 as_bad ((flag_code
!= CODE_64BIT
2910 ? _("`%s' is only supported in 64-bit mode")
2911 : _("`%s' is not supported in 64-bit mode")),
2912 current_templates
->start
->name
);
2915 /* If we are in 16-bit mode, do not allow addr16 or data16.
2916 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2917 if ((current_templates
->start
->opcode_modifier
.size16
2918 || current_templates
->start
->opcode_modifier
.size32
)
2919 && flag_code
!= CODE_64BIT
2920 && (current_templates
->start
->opcode_modifier
.size32
2921 ^ (flag_code
== CODE_16BIT
)))
2923 as_bad (_("redundant %s prefix"),
2924 current_templates
->start
->name
);
2927 /* Add prefix, checking for repeated prefixes. */
2928 switch (add_prefix (current_templates
->start
->base_opcode
))
2933 expecting_string_instruction
= current_templates
->start
->name
;
2936 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2943 if (!current_templates
)
2945 /* See if we can get a match by trimming off a suffix. */
2948 case WORD_MNEM_SUFFIX
:
2949 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2950 i
.suffix
= SHORT_MNEM_SUFFIX
;
2952 case BYTE_MNEM_SUFFIX
:
2953 case QWORD_MNEM_SUFFIX
:
2954 i
.suffix
= mnem_p
[-1];
2956 current_templates
= hash_find (op_hash
, mnemonic
);
2958 case SHORT_MNEM_SUFFIX
:
2959 case LONG_MNEM_SUFFIX
:
2962 i
.suffix
= mnem_p
[-1];
2964 current_templates
= hash_find (op_hash
, mnemonic
);
2972 if (intel_float_operand (mnemonic
) == 1)
2973 i
.suffix
= SHORT_MNEM_SUFFIX
;
2975 i
.suffix
= LONG_MNEM_SUFFIX
;
2977 current_templates
= hash_find (op_hash
, mnemonic
);
2981 if (!current_templates
)
2983 as_bad (_("no such instruction: `%s'"), token_start
);
2988 if (current_templates
->start
->opcode_modifier
.jump
2989 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2991 /* Check for a branch hint. We allow ",pt" and ",pn" for
2992 predict taken and predict not taken respectively.
2993 I'm not sure that branch hints actually do anything on loop
2994 and jcxz insns (JumpByte) for current Pentium4 chips. They
2995 may work in the future and it doesn't hurt to accept them
2997 if (l
[0] == ',' && l
[1] == 'p')
3001 if (!add_prefix (DS_PREFIX_OPCODE
))
3005 else if (l
[2] == 'n')
3007 if (!add_prefix (CS_PREFIX_OPCODE
))
3013 /* Any other comma loses. */
3016 as_bad (_("invalid character %s in mnemonic"),
3017 output_invalid (*l
));
3021 /* Check if instruction is supported on specified architecture. */
3023 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3025 supported
|= cpu_flags_match (t
);
3026 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3030 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3032 as_bad (flag_code
== CODE_64BIT
3033 ? _("`%s' is not supported in 64-bit mode")
3034 : _("`%s' is only supported in 64-bit mode"),
3035 current_templates
->start
->name
);
3038 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3040 as_bad (_("`%s' is not supported on `%s%s'"),
3041 current_templates
->start
->name
, cpu_arch_name
,
3042 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3047 if (!cpu_arch_flags
.bitfield
.cpui386
3048 && (flag_code
!= CODE_16BIT
))
3050 as_warn (_("use .code16 to ensure correct addressing mode"));
3053 /* Check for rep/repne without a string instruction. */
3054 if (expecting_string_instruction
)
3056 static templates override
;
3058 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3059 if (t
->opcode_modifier
.isstring
)
3061 if (t
>= current_templates
->end
)
3063 as_bad (_("expecting string instruction after `%s'"),
3064 expecting_string_instruction
);
3067 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3068 if (!t
->opcode_modifier
.isstring
)
3071 current_templates
= &override
;
3078 parse_operands (char *l
, const char *mnemonic
)
3082 /* 1 if operand is pending after ','. */
3083 unsigned int expecting_operand
= 0;
3085 /* Non-zero if operand parens not balanced. */
3086 unsigned int paren_not_balanced
;
3088 while (*l
!= END_OF_INSN
)
3090 /* Skip optional white space before operand. */
3091 if (is_space_char (*l
))
3093 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3095 as_bad (_("invalid character %s before operand %d"),
3096 output_invalid (*l
),
3100 token_start
= l
; /* after white space */
3101 paren_not_balanced
= 0;
3102 while (paren_not_balanced
|| *l
!= ',')
3104 if (*l
== END_OF_INSN
)
3106 if (paren_not_balanced
)
3109 as_bad (_("unbalanced parenthesis in operand %d."),
3112 as_bad (_("unbalanced brackets in operand %d."),
3117 break; /* we are done */
3119 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3121 as_bad (_("invalid character %s in operand %d"),
3122 output_invalid (*l
),
3129 ++paren_not_balanced
;
3131 --paren_not_balanced
;
3136 ++paren_not_balanced
;
3138 --paren_not_balanced
;
3142 if (l
!= token_start
)
3143 { /* Yes, we've read in another operand. */
3144 unsigned int operand_ok
;
3145 this_operand
= i
.operands
++;
3146 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3147 if (i
.operands
> MAX_OPERANDS
)
3149 as_bad (_("spurious operands; (%d operands/instruction max)"),
3153 /* Now parse operand adding info to 'i' as we go along. */
3154 END_STRING_AND_SAVE (l
);
3158 i386_intel_operand (token_start
,
3159 intel_float_operand (mnemonic
));
3161 operand_ok
= i386_att_operand (token_start
);
3163 RESTORE_END_STRING (l
);
3169 if (expecting_operand
)
3171 expecting_operand_after_comma
:
3172 as_bad (_("expecting operand after ','; got nothing"));
3177 as_bad (_("expecting operand before ','; got nothing"));
3182 /* Now *l must be either ',' or END_OF_INSN. */
3185 if (*++l
== END_OF_INSN
)
3187 /* Just skip it, if it's \n complain. */
3188 goto expecting_operand_after_comma
;
3190 expecting_operand
= 1;
3197 swap_2_operands (int xchg1
, int xchg2
)
3199 union i386_op temp_op
;
3200 i386_operand_type temp_type
;
3201 enum bfd_reloc_code_real temp_reloc
;
3203 temp_type
= i
.types
[xchg2
];
3204 i
.types
[xchg2
] = i
.types
[xchg1
];
3205 i
.types
[xchg1
] = temp_type
;
3206 temp_op
= i
.op
[xchg2
];
3207 i
.op
[xchg2
] = i
.op
[xchg1
];
3208 i
.op
[xchg1
] = temp_op
;
3209 temp_reloc
= i
.reloc
[xchg2
];
3210 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3211 i
.reloc
[xchg1
] = temp_reloc
;
3215 swap_operands (void)
3221 swap_2_operands (1, i
.operands
- 2);
3224 swap_2_operands (0, i
.operands
- 1);
3230 if (i
.mem_operands
== 2)
3232 const seg_entry
*temp_seg
;
3233 temp_seg
= i
.seg
[0];
3234 i
.seg
[0] = i
.seg
[1];
3235 i
.seg
[1] = temp_seg
;
3239 /* Try to ensure constant immediates are represented in the smallest
3244 char guess_suffix
= 0;
3248 guess_suffix
= i
.suffix
;
3249 else if (i
.reg_operands
)
3251 /* Figure out a suffix from the last register operand specified.
3252 We can't do this properly yet, ie. excluding InOutPortReg,
3253 but the following works for instructions with immediates.
3254 In any case, we can't set i.suffix yet. */
3255 for (op
= i
.operands
; --op
>= 0;)
3256 if (i
.types
[op
].bitfield
.reg8
)
3258 guess_suffix
= BYTE_MNEM_SUFFIX
;
3261 else if (i
.types
[op
].bitfield
.reg16
)
3263 guess_suffix
= WORD_MNEM_SUFFIX
;
3266 else if (i
.types
[op
].bitfield
.reg32
)
3268 guess_suffix
= LONG_MNEM_SUFFIX
;
3271 else if (i
.types
[op
].bitfield
.reg64
)
3273 guess_suffix
= QWORD_MNEM_SUFFIX
;
3277 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3278 guess_suffix
= WORD_MNEM_SUFFIX
;
3280 for (op
= i
.operands
; --op
>= 0;)
3281 if (operand_type_check (i
.types
[op
], imm
))
3283 switch (i
.op
[op
].imms
->X_op
)
3286 /* If a suffix is given, this operand may be shortened. */
3287 switch (guess_suffix
)
3289 case LONG_MNEM_SUFFIX
:
3290 i
.types
[op
].bitfield
.imm32
= 1;
3291 i
.types
[op
].bitfield
.imm64
= 1;
3293 case WORD_MNEM_SUFFIX
:
3294 i
.types
[op
].bitfield
.imm16
= 1;
3295 i
.types
[op
].bitfield
.imm32
= 1;
3296 i
.types
[op
].bitfield
.imm32s
= 1;
3297 i
.types
[op
].bitfield
.imm64
= 1;
3299 case BYTE_MNEM_SUFFIX
:
3300 i
.types
[op
].bitfield
.imm8
= 1;
3301 i
.types
[op
].bitfield
.imm8s
= 1;
3302 i
.types
[op
].bitfield
.imm16
= 1;
3303 i
.types
[op
].bitfield
.imm32
= 1;
3304 i
.types
[op
].bitfield
.imm32s
= 1;
3305 i
.types
[op
].bitfield
.imm64
= 1;
3309 /* If this operand is at most 16 bits, convert it
3310 to a signed 16 bit number before trying to see
3311 whether it will fit in an even smaller size.
3312 This allows a 16-bit operand such as $0xffe0 to
3313 be recognised as within Imm8S range. */
3314 if ((i
.types
[op
].bitfield
.imm16
)
3315 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3317 i
.op
[op
].imms
->X_add_number
=
3318 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3320 if ((i
.types
[op
].bitfield
.imm32
)
3321 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3324 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3325 ^ ((offsetT
) 1 << 31))
3326 - ((offsetT
) 1 << 31));
3329 = operand_type_or (i
.types
[op
],
3330 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3332 /* We must avoid matching of Imm32 templates when 64bit
3333 only immediate is available. */
3334 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3335 i
.types
[op
].bitfield
.imm32
= 0;
3342 /* Symbols and expressions. */
3344 /* Convert symbolic operand to proper sizes for matching, but don't
3345 prevent matching a set of insns that only supports sizes other
3346 than those matching the insn suffix. */
3348 i386_operand_type mask
, allowed
;
3351 operand_type_set (&mask
, 0);
3352 operand_type_set (&allowed
, 0);
3354 for (t
= current_templates
->start
;
3355 t
< current_templates
->end
;
3357 allowed
= operand_type_or (allowed
,
3358 t
->operand_types
[op
]);
3359 switch (guess_suffix
)
3361 case QWORD_MNEM_SUFFIX
:
3362 mask
.bitfield
.imm64
= 1;
3363 mask
.bitfield
.imm32s
= 1;
3365 case LONG_MNEM_SUFFIX
:
3366 mask
.bitfield
.imm32
= 1;
3368 case WORD_MNEM_SUFFIX
:
3369 mask
.bitfield
.imm16
= 1;
3371 case BYTE_MNEM_SUFFIX
:
3372 mask
.bitfield
.imm8
= 1;
3377 allowed
= operand_type_and (mask
, allowed
);
3378 if (!operand_type_all_zero (&allowed
))
3379 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3386 /* Try to use the smallest displacement type too. */
3388 optimize_disp (void)
3392 for (op
= i
.operands
; --op
>= 0;)
3393 if (operand_type_check (i
.types
[op
], disp
))
3395 if (i
.op
[op
].disps
->X_op
== O_constant
)
3397 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3399 if (i
.types
[op
].bitfield
.disp16
3400 && (disp
& ~(offsetT
) 0xffff) == 0)
3402 /* If this operand is at most 16 bits, convert
3403 to a signed 16 bit number and don't use 64bit
3405 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3406 i
.types
[op
].bitfield
.disp64
= 0;
3408 if (i
.types
[op
].bitfield
.disp32
3409 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3411 /* If this operand is at most 32 bits, convert
3412 to a signed 32 bit number and don't use 64bit
3414 disp
&= (((offsetT
) 2 << 31) - 1);
3415 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3416 i
.types
[op
].bitfield
.disp64
= 0;
3418 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3420 i
.types
[op
].bitfield
.disp8
= 0;
3421 i
.types
[op
].bitfield
.disp16
= 0;
3422 i
.types
[op
].bitfield
.disp32
= 0;
3423 i
.types
[op
].bitfield
.disp32s
= 0;
3424 i
.types
[op
].bitfield
.disp64
= 0;
3428 else if (flag_code
== CODE_64BIT
)
3430 if (fits_in_signed_long (disp
))
3432 i
.types
[op
].bitfield
.disp64
= 0;
3433 i
.types
[op
].bitfield
.disp32s
= 1;
3435 if (fits_in_unsigned_long (disp
))
3436 i
.types
[op
].bitfield
.disp32
= 1;
3438 if ((i
.types
[op
].bitfield
.disp32
3439 || i
.types
[op
].bitfield
.disp32s
3440 || i
.types
[op
].bitfield
.disp16
)
3441 && fits_in_signed_byte (disp
))
3442 i
.types
[op
].bitfield
.disp8
= 1;
3444 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3445 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3447 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3448 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3449 i
.types
[op
].bitfield
.disp8
= 0;
3450 i
.types
[op
].bitfield
.disp16
= 0;
3451 i
.types
[op
].bitfield
.disp32
= 0;
3452 i
.types
[op
].bitfield
.disp32s
= 0;
3453 i
.types
[op
].bitfield
.disp64
= 0;
3456 /* We only support 64bit displacement on constants. */
3457 i
.types
[op
].bitfield
.disp64
= 0;
3461 /* Check if operands are valid for the instrucrtion. Update VEX
3465 VEX_check_operands (const template *t
)
3467 if (!t
->opcode_modifier
.vex
)
3470 /* Only check VEX_Imm4, which must be the first operand. */
3471 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3473 if (i
.op
[0].imms
->X_op
!= O_constant
3474 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3477 /* Turn off Imm8 so that update_imm won't complain. */
3478 i
.types
[0] = vex_imm4
;
3485 match_template (void)
3487 /* Points to template once we've found it. */
3489 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3490 i386_operand_type overlap4
;
3491 unsigned int found_reverse_match
;
3492 i386_opcode_modifier suffix_check
;
3493 i386_operand_type operand_types
[MAX_OPERANDS
];
3494 int addr_prefix_disp
;
3496 unsigned int found_cpu_match
;
3497 unsigned int check_register
;
3499 #if MAX_OPERANDS != 5
3500 # error "MAX_OPERANDS must be 5."
3503 found_reverse_match
= 0;
3504 addr_prefix_disp
= -1;
3506 memset (&suffix_check
, 0, sizeof (suffix_check
));
3507 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3508 suffix_check
.no_bsuf
= 1;
3509 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3510 suffix_check
.no_wsuf
= 1;
3511 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3512 suffix_check
.no_ssuf
= 1;
3513 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3514 suffix_check
.no_lsuf
= 1;
3515 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3516 suffix_check
.no_qsuf
= 1;
3517 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3518 suffix_check
.no_ldsuf
= 1;
3520 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3522 addr_prefix_disp
= -1;
3524 /* Must have right number of operands. */
3525 if (i
.operands
!= t
->operands
)
3528 /* Check processor support. */
3529 found_cpu_match
= (cpu_flags_match (t
)
3530 == CPU_FLAGS_PERFECT_MATCH
);
3531 if (!found_cpu_match
)
3534 /* Check old gcc support. */
3535 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3538 /* Check AT&T mnemonic. */
3539 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3542 /* Check AT&T syntax Intel syntax. */
3543 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3544 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3547 /* Check the suffix, except for some instructions in intel mode. */
3548 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3549 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3550 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3551 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3552 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3553 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3554 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3557 if (!operand_size_match (t
))
3560 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3561 operand_types
[j
] = t
->operand_types
[j
];
3563 /* In general, don't allow 64-bit operands in 32-bit mode. */
3564 if (i
.suffix
== QWORD_MNEM_SUFFIX
3565 && flag_code
!= CODE_64BIT
3567 ? (!t
->opcode_modifier
.ignoresize
3568 && !intel_float_operand (t
->name
))
3569 : intel_float_operand (t
->name
) != 2)
3570 && ((!operand_types
[0].bitfield
.regmmx
3571 && !operand_types
[0].bitfield
.regxmm
3572 && !operand_types
[0].bitfield
.regymm
)
3573 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3574 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3575 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3576 && (t
->base_opcode
!= 0x0fc7
3577 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3580 /* In general, don't allow 32-bit operands on pre-386. */
3581 else if (i
.suffix
== LONG_MNEM_SUFFIX
3582 && !cpu_arch_flags
.bitfield
.cpui386
3584 ? (!t
->opcode_modifier
.ignoresize
3585 && !intel_float_operand (t
->name
))
3586 : intel_float_operand (t
->name
) != 2)
3587 && ((!operand_types
[0].bitfield
.regmmx
3588 && !operand_types
[0].bitfield
.regxmm
)
3589 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3590 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3593 /* Do not verify operands when there are none. */
3597 /* We've found a match; break out of loop. */
3601 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3602 into Disp32/Disp16/Disp32 operand. */
3603 if (i
.prefix
[ADDR_PREFIX
] != 0)
3605 /* There should be only one Disp operand. */
3609 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3611 if (operand_types
[j
].bitfield
.disp16
)
3613 addr_prefix_disp
= j
;
3614 operand_types
[j
].bitfield
.disp32
= 1;
3615 operand_types
[j
].bitfield
.disp16
= 0;
3621 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3623 if (operand_types
[j
].bitfield
.disp32
)
3625 addr_prefix_disp
= j
;
3626 operand_types
[j
].bitfield
.disp32
= 0;
3627 operand_types
[j
].bitfield
.disp16
= 1;
3633 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3635 if (operand_types
[j
].bitfield
.disp64
)
3637 addr_prefix_disp
= j
;
3638 operand_types
[j
].bitfield
.disp64
= 0;
3639 operand_types
[j
].bitfield
.disp32
= 1;
3647 /* We check register size only if size of operands can be
3648 encoded the canonical way. */
3649 check_register
= t
->opcode_modifier
.w
;
3650 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3651 switch (t
->operands
)
3654 if (!operand_type_match (overlap0
, i
.types
[0]))
3658 /* xchg %eax, %eax is a special case. It is an aliase for nop
3659 only in 32bit mode and we can use opcode 0x90. In 64bit
3660 mode, we can't use 0x90 for xchg %eax, %eax since it should
3661 zero-extend %eax to %rax. */
3662 if (flag_code
== CODE_64BIT
3663 && t
->base_opcode
== 0x90
3664 && operand_type_equal (&i
.types
[0], &acc32
)
3665 && operand_type_equal (&i
.types
[1], &acc32
))
3670 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3671 if (!operand_type_match (overlap0
, i
.types
[0])
3672 || !operand_type_match (overlap1
, i
.types
[1])
3674 && !operand_type_register_match (overlap0
, i
.types
[0],
3676 overlap1
, i
.types
[1],
3679 /* Check if other direction is valid ... */
3680 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3683 /* Try reversing direction of operands. */
3684 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3685 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3686 if (!operand_type_match (overlap0
, i
.types
[0])
3687 || !operand_type_match (overlap1
, i
.types
[1])
3689 && !operand_type_register_match (overlap0
,
3696 /* Does not match either direction. */
3699 /* found_reverse_match holds which of D or FloatDR
3701 if (t
->opcode_modifier
.d
)
3702 found_reverse_match
= Opcode_D
;
3703 else if (t
->opcode_modifier
.floatd
)
3704 found_reverse_match
= Opcode_FloatD
;
3706 found_reverse_match
= 0;
3707 if (t
->opcode_modifier
.floatr
)
3708 found_reverse_match
|= Opcode_FloatR
;
3712 /* Found a forward 2 operand match here. */
3713 switch (t
->operands
)
3716 overlap4
= operand_type_and (i
.types
[4],
3719 overlap3
= operand_type_and (i
.types
[3],
3722 overlap2
= operand_type_and (i
.types
[2],
3727 switch (t
->operands
)
3730 if (!operand_type_match (overlap4
, i
.types
[4])
3731 || !operand_type_register_match (overlap3
,
3739 if (!operand_type_match (overlap3
, i
.types
[3])
3741 && !operand_type_register_match (overlap2
,
3749 /* Here we make use of the fact that there are no
3750 reverse match 3 operand instructions, and all 3
3751 operand instructions only need to be checked for
3752 register consistency between operands 2 and 3. */
3753 if (!operand_type_match (overlap2
, i
.types
[2])
3755 && !operand_type_register_match (overlap1
,
3765 /* Found either forward/reverse 2, 3 or 4 operand match here:
3766 slip through to break. */
3768 if (!found_cpu_match
)
3770 found_reverse_match
= 0;
3774 /* Check if VEX operands are valid. */
3775 if (VEX_check_operands (t
))
3778 /* We've found a match; break out of loop. */
3782 if (t
== current_templates
->end
)
3784 /* We found no match. */
3786 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3787 current_templates
->start
->name
);
3789 as_bad (_("suffix or operands invalid for `%s'"),
3790 current_templates
->start
->name
);
3794 if (!quiet_warnings
)
3797 && (i
.types
[0].bitfield
.jumpabsolute
3798 != operand_types
[0].bitfield
.jumpabsolute
))
3800 as_warn (_("indirect %s without `*'"), t
->name
);
3803 if (t
->opcode_modifier
.isprefix
3804 && t
->opcode_modifier
.ignoresize
)
3806 /* Warn them that a data or address size prefix doesn't
3807 affect assembly of the next line of code. */
3808 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3812 /* Copy the template we found. */
3815 if (addr_prefix_disp
!= -1)
3816 i
.tm
.operand_types
[addr_prefix_disp
]
3817 = operand_types
[addr_prefix_disp
];
3819 if (found_reverse_match
)
3821 /* If we found a reverse match we must alter the opcode
3822 direction bit. found_reverse_match holds bits to change
3823 (different for int & float insns). */
3825 i
.tm
.base_opcode
^= found_reverse_match
;
3827 i
.tm
.operand_types
[0] = operand_types
[1];
3828 i
.tm
.operand_types
[1] = operand_types
[0];
3837 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3838 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3840 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3842 as_bad (_("`%s' operand %d must use `%%es' segment"),
3847 /* There's only ever one segment override allowed per instruction.
3848 This instruction possibly has a legal segment override on the
3849 second operand, so copy the segment to where non-string
3850 instructions store it, allowing common code. */
3851 i
.seg
[0] = i
.seg
[1];
3853 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3855 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3857 as_bad (_("`%s' operand %d must use `%%es' segment"),
3867 process_suffix (void)
3869 /* If matched instruction specifies an explicit instruction mnemonic
3871 if (i
.tm
.opcode_modifier
.size16
)
3872 i
.suffix
= WORD_MNEM_SUFFIX
;
3873 else if (i
.tm
.opcode_modifier
.size32
)
3874 i
.suffix
= LONG_MNEM_SUFFIX
;
3875 else if (i
.tm
.opcode_modifier
.size64
)
3876 i
.suffix
= QWORD_MNEM_SUFFIX
;
3877 else if (i
.reg_operands
)
3879 /* If there's no instruction mnemonic suffix we try to invent one
3880 based on register operands. */
3883 /* We take i.suffix from the last register operand specified,
3884 Destination register type is more significant than source
3885 register type. crc32 in SSE4.2 prefers source register
3887 if (i
.tm
.base_opcode
== 0xf20f38f1)
3889 if (i
.types
[0].bitfield
.reg16
)
3890 i
.suffix
= WORD_MNEM_SUFFIX
;
3891 else if (i
.types
[0].bitfield
.reg32
)
3892 i
.suffix
= LONG_MNEM_SUFFIX
;
3893 else if (i
.types
[0].bitfield
.reg64
)
3894 i
.suffix
= QWORD_MNEM_SUFFIX
;
3896 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3898 if (i
.types
[0].bitfield
.reg8
)
3899 i
.suffix
= BYTE_MNEM_SUFFIX
;
3906 if (i
.tm
.base_opcode
== 0xf20f38f1
3907 || i
.tm
.base_opcode
== 0xf20f38f0)
3909 /* We have to know the operand size for crc32. */
3910 as_bad (_("ambiguous memory operand size for `%s`"),
3915 for (op
= i
.operands
; --op
>= 0;)
3916 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3918 if (i
.types
[op
].bitfield
.reg8
)
3920 i
.suffix
= BYTE_MNEM_SUFFIX
;
3923 else if (i
.types
[op
].bitfield
.reg16
)
3925 i
.suffix
= WORD_MNEM_SUFFIX
;
3928 else if (i
.types
[op
].bitfield
.reg32
)
3930 i
.suffix
= LONG_MNEM_SUFFIX
;
3933 else if (i
.types
[op
].bitfield
.reg64
)
3935 i
.suffix
= QWORD_MNEM_SUFFIX
;
3941 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3943 if (!check_byte_reg ())
3946 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3948 if (!check_long_reg ())
3951 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3954 && i
.tm
.opcode_modifier
.ignoresize
3955 && i
.tm
.opcode_modifier
.no_qsuf
)
3957 else if (!check_qword_reg ())
3960 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3962 if (!check_word_reg ())
3965 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
3966 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
3968 /* Skip if the instruction has x/y suffix. match_template
3969 should check if it is a valid suffix. */
3971 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3972 /* Do nothing if the instruction is going to ignore the prefix. */
3977 else if (i
.tm
.opcode_modifier
.defaultsize
3979 /* exclude fldenv/frstor/fsave/fstenv */
3980 && i
.tm
.opcode_modifier
.no_ssuf
)
3982 i
.suffix
= stackop_size
;
3984 else if (intel_syntax
3986 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3987 || i
.tm
.opcode_modifier
.jumpbyte
3988 || i
.tm
.opcode_modifier
.jumpintersegment
3989 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3990 && i
.tm
.extension_opcode
<= 3)))
3995 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3997 i
.suffix
= QWORD_MNEM_SUFFIX
;
4001 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4002 i
.suffix
= LONG_MNEM_SUFFIX
;
4005 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4006 i
.suffix
= WORD_MNEM_SUFFIX
;
4015 if (i
.tm
.opcode_modifier
.w
)
4017 as_bad (_("no instruction mnemonic suffix given and "
4018 "no register operands; can't size instruction"));
4024 unsigned int suffixes
;
4026 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4027 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4029 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4031 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4033 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4035 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4038 /* There are more than suffix matches. */
4039 if (i
.tm
.opcode_modifier
.w
4040 || ((suffixes
& (suffixes
- 1))
4041 && !i
.tm
.opcode_modifier
.defaultsize
4042 && !i
.tm
.opcode_modifier
.ignoresize
))
4044 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4050 /* Change the opcode based on the operand size given by i.suffix;
4051 We don't need to change things for byte insns. */
4054 && i
.suffix
!= BYTE_MNEM_SUFFIX
4055 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4056 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4058 /* It's not a byte, select word/dword operation. */
4059 if (i
.tm
.opcode_modifier
.w
)
4061 if (i
.tm
.opcode_modifier
.shortform
)
4062 i
.tm
.base_opcode
|= 8;
4064 i
.tm
.base_opcode
|= 1;
4067 /* Now select between word & dword operations via the operand
4068 size prefix, except for instructions that will ignore this
4070 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4072 /* The address size override prefix changes the size of the
4074 if ((flag_code
== CODE_32BIT
4075 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4076 || (flag_code
!= CODE_32BIT
4077 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4078 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4081 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4082 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4083 && !i
.tm
.opcode_modifier
.ignoresize
4084 && !i
.tm
.opcode_modifier
.floatmf
4085 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4086 || (flag_code
== CODE_64BIT
4087 && i
.tm
.opcode_modifier
.jumpbyte
)))
4089 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4091 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4092 prefix
= ADDR_PREFIX_OPCODE
;
4094 if (!add_prefix (prefix
))
4098 /* Set mode64 for an operand. */
4099 if (i
.suffix
== QWORD_MNEM_SUFFIX
4100 && flag_code
== CODE_64BIT
4101 && !i
.tm
.opcode_modifier
.norex64
)
4103 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4104 need rex64. cmpxchg8b is also a special case. */
4105 if (! (i
.operands
== 2
4106 && i
.tm
.base_opcode
== 0x90
4107 && i
.tm
.extension_opcode
== None
4108 && operand_type_equal (&i
.types
[0], &acc64
)
4109 && operand_type_equal (&i
.types
[1], &acc64
))
4110 && ! (i
.operands
== 1
4111 && i
.tm
.base_opcode
== 0xfc7
4112 && i
.tm
.extension_opcode
== 1
4113 && !operand_type_check (i
.types
[0], reg
)
4114 && operand_type_check (i
.types
[0], anymem
)))
4118 /* Size floating point instruction. */
4119 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4120 if (i
.tm
.opcode_modifier
.floatmf
)
4121 i
.tm
.base_opcode
^= 4;
4128 check_byte_reg (void)
4132 for (op
= i
.operands
; --op
>= 0;)
4134 /* If this is an eight bit register, it's OK. If it's the 16 or
4135 32 bit version of an eight bit register, we will just use the
4136 low portion, and that's OK too. */
4137 if (i
.types
[op
].bitfield
.reg8
)
4140 /* Don't generate this warning if not needed. */
4141 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4144 /* crc32 doesn't generate this warning. */
4145 if (i
.tm
.base_opcode
== 0xf20f38f0)
4148 if ((i
.types
[op
].bitfield
.reg16
4149 || i
.types
[op
].bitfield
.reg32
4150 || i
.types
[op
].bitfield
.reg64
)
4151 && i
.op
[op
].regs
->reg_num
< 4)
4153 /* Prohibit these changes in the 64bit mode, since the
4154 lowering is more complicated. */
4155 if (flag_code
== CODE_64BIT
4156 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4158 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4159 register_prefix
, i
.op
[op
].regs
->reg_name
,
4163 #if REGISTER_WARNINGS
4165 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4166 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4168 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4169 ? REGNAM_AL
- REGNAM_AX
4170 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4172 i
.op
[op
].regs
->reg_name
,
4177 /* Any other register is bad. */
4178 if (i
.types
[op
].bitfield
.reg16
4179 || i
.types
[op
].bitfield
.reg32
4180 || i
.types
[op
].bitfield
.reg64
4181 || i
.types
[op
].bitfield
.regmmx
4182 || i
.types
[op
].bitfield
.regxmm
4183 || i
.types
[op
].bitfield
.regymm
4184 || i
.types
[op
].bitfield
.sreg2
4185 || i
.types
[op
].bitfield
.sreg3
4186 || i
.types
[op
].bitfield
.control
4187 || i
.types
[op
].bitfield
.debug
4188 || i
.types
[op
].bitfield
.test
4189 || i
.types
[op
].bitfield
.floatreg
4190 || i
.types
[op
].bitfield
.floatacc
)
4192 as_bad (_("`%s%s' not allowed with `%s%c'"),
4194 i
.op
[op
].regs
->reg_name
,
4204 check_long_reg (void)
4208 for (op
= i
.operands
; --op
>= 0;)
4209 /* Reject eight bit registers, except where the template requires
4210 them. (eg. movzb) */
4211 if (i
.types
[op
].bitfield
.reg8
4212 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4213 || i
.tm
.operand_types
[op
].bitfield
.reg32
4214 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4216 as_bad (_("`%s%s' not allowed with `%s%c'"),
4218 i
.op
[op
].regs
->reg_name
,
4223 /* Warn if the e prefix on a general reg is missing. */
4224 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4225 && i
.types
[op
].bitfield
.reg16
4226 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4227 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4229 /* Prohibit these changes in the 64bit mode, since the
4230 lowering is more complicated. */
4231 if (flag_code
== CODE_64BIT
)
4233 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4234 register_prefix
, i
.op
[op
].regs
->reg_name
,
4238 #if REGISTER_WARNINGS
4240 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4242 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4244 i
.op
[op
].regs
->reg_name
,
4248 /* Warn if the r prefix on a general reg is missing. */
4249 else if (i
.types
[op
].bitfield
.reg64
4250 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4251 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4254 && i
.tm
.opcode_modifier
.toqword
4255 && !i
.types
[0].bitfield
.regxmm
)
4257 /* Convert to QWORD. We want REX byte. */
4258 i
.suffix
= QWORD_MNEM_SUFFIX
;
4262 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4263 register_prefix
, i
.op
[op
].regs
->reg_name
,
4272 check_qword_reg (void)
4276 for (op
= i
.operands
; --op
>= 0; )
4277 /* Reject eight bit registers, except where the template requires
4278 them. (eg. movzb) */
4279 if (i
.types
[op
].bitfield
.reg8
4280 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4281 || i
.tm
.operand_types
[op
].bitfield
.reg32
4282 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4284 as_bad (_("`%s%s' not allowed with `%s%c'"),
4286 i
.op
[op
].regs
->reg_name
,
4291 /* Warn if the e prefix on a general reg is missing. */
4292 else if ((i
.types
[op
].bitfield
.reg16
4293 || i
.types
[op
].bitfield
.reg32
)
4294 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4295 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4297 /* Prohibit these changes in the 64bit mode, since the
4298 lowering is more complicated. */
4300 && i
.tm
.opcode_modifier
.todword
4301 && !i
.types
[0].bitfield
.regxmm
)
4303 /* Convert to DWORD. We don't want REX byte. */
4304 i
.suffix
= LONG_MNEM_SUFFIX
;
4308 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4309 register_prefix
, i
.op
[op
].regs
->reg_name
,
4318 check_word_reg (void)
4321 for (op
= i
.operands
; --op
>= 0;)
4322 /* Reject eight bit registers, except where the template requires
4323 them. (eg. movzb) */
4324 if (i
.types
[op
].bitfield
.reg8
4325 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4326 || i
.tm
.operand_types
[op
].bitfield
.reg32
4327 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4329 as_bad (_("`%s%s' not allowed with `%s%c'"),
4331 i
.op
[op
].regs
->reg_name
,
4336 /* Warn if the e prefix on a general reg is present. */
4337 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4338 && i
.types
[op
].bitfield
.reg32
4339 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4340 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4342 /* Prohibit these changes in the 64bit mode, since the
4343 lowering is more complicated. */
4344 if (flag_code
== CODE_64BIT
)
4346 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4347 register_prefix
, i
.op
[op
].regs
->reg_name
,
4352 #if REGISTER_WARNINGS
4353 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4355 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4357 i
.op
[op
].regs
->reg_name
,
4365 update_imm (unsigned int j
)
4367 i386_operand_type overlap
;
4369 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4370 if ((overlap
.bitfield
.imm8
4371 || overlap
.bitfield
.imm8s
4372 || overlap
.bitfield
.imm16
4373 || overlap
.bitfield
.imm32
4374 || overlap
.bitfield
.imm32s
4375 || overlap
.bitfield
.imm64
)
4376 && !operand_type_equal (&overlap
, &imm8
)
4377 && !operand_type_equal (&overlap
, &imm8s
)
4378 && !operand_type_equal (&overlap
, &imm16
)
4379 && !operand_type_equal (&overlap
, &imm32
)
4380 && !operand_type_equal (&overlap
, &imm32s
)
4381 && !operand_type_equal (&overlap
, &imm64
))
4385 i386_operand_type temp
;
4387 operand_type_set (&temp
, 0);
4388 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4390 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4391 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4393 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4394 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4395 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4397 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4398 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4401 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4404 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4405 || operand_type_equal (&overlap
, &imm16_32
)
4406 || operand_type_equal (&overlap
, &imm16_32s
))
4408 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4413 if (!operand_type_equal (&overlap
, &imm8
)
4414 && !operand_type_equal (&overlap
, &imm8s
)
4415 && !operand_type_equal (&overlap
, &imm16
)
4416 && !operand_type_equal (&overlap
, &imm32
)
4417 && !operand_type_equal (&overlap
, &imm32s
)
4418 && !operand_type_equal (&overlap
, &imm64
))
4420 as_bad (_("no instruction mnemonic suffix given; "
4421 "can't determine immediate size"));
4425 i
.types
[j
] = overlap
;
4435 for (j
= 0; j
< 2; j
++)
4436 if (update_imm (j
) == 0)
4439 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4440 assert (operand_type_check (i
.types
[2], imm
) == 0);
4448 i
.drex
.modrm_reg
= 0;
4449 i
.drex
.modrm_regmem
= 0;
4451 /* SSE5 4 operand instructions must have the destination the same as
4452 one of the inputs. Figure out the destination register and cache
4453 it away in the drex field, and remember which fields to use for
4455 if (i
.tm
.opcode_modifier
.drex
4456 && i
.tm
.opcode_modifier
.drexv
4459 i
.tm
.extension_opcode
= None
;
4461 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4462 if (i
.types
[0].bitfield
.regxmm
!= 0
4463 && i
.types
[1].bitfield
.regxmm
!= 0
4464 && i
.types
[2].bitfield
.regxmm
!= 0
4465 && i
.types
[3].bitfield
.regxmm
!= 0
4466 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4467 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4469 /* Clear the arguments that are stored in drex. */
4470 operand_type_set (&i
.types
[0], 0);
4471 operand_type_set (&i
.types
[3], 0);
4472 i
.reg_operands
-= 2;
4474 /* There are two different ways to encode a 4 operand
4475 instruction with all registers that uses OC1 set to
4476 0 or 1. Favor setting OC1 to 0 since this mimics the
4477 actions of other SSE5 assemblers. Use modrm encoding 2
4478 for register/register. Include the high order bit that
4479 is normally stored in the REX byte in the register
4481 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4482 i
.drex
.modrm_reg
= 2;
4483 i
.drex
.modrm_regmem
= 1;
4484 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4485 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4488 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4489 else if (i
.types
[0].bitfield
.regxmm
!= 0
4490 && i
.types
[1].bitfield
.regxmm
!= 0
4491 && (i
.types
[2].bitfield
.regxmm
4492 || operand_type_check (i
.types
[2], anymem
))
4493 && i
.types
[3].bitfield
.regxmm
!= 0
4494 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4495 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4497 /* clear the arguments that are stored in drex */
4498 operand_type_set (&i
.types
[0], 0);
4499 operand_type_set (&i
.types
[3], 0);
4500 i
.reg_operands
-= 2;
4502 /* Specify the modrm encoding for memory addressing. Include
4503 the high order bit that is normally stored in the REX byte
4504 in the register field. */
4505 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4506 i
.drex
.modrm_reg
= 1;
4507 i
.drex
.modrm_regmem
= 2;
4508 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4509 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4512 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4513 else if (i
.types
[0].bitfield
.regxmm
!= 0
4514 && operand_type_check (i
.types
[1], anymem
) != 0
4515 && i
.types
[2].bitfield
.regxmm
!= 0
4516 && i
.types
[3].bitfield
.regxmm
!= 0
4517 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4518 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4520 /* Clear the arguments that are stored in drex. */
4521 operand_type_set (&i
.types
[0], 0);
4522 operand_type_set (&i
.types
[3], 0);
4523 i
.reg_operands
-= 2;
4525 /* Specify the modrm encoding for memory addressing. Include
4526 the high order bit that is normally stored in the REX byte
4527 in the register field. */
4528 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4529 i
.drex
.modrm_reg
= 2;
4530 i
.drex
.modrm_regmem
= 1;
4531 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4532 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4535 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4536 else if (i
.types
[0].bitfield
.regxmm
!= 0
4537 && i
.types
[1].bitfield
.regxmm
!= 0
4538 && i
.types
[2].bitfield
.regxmm
!= 0
4539 && i
.types
[3].bitfield
.regxmm
!= 0
4540 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4541 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4543 /* clear the arguments that are stored in drex */
4544 operand_type_set (&i
.types
[2], 0);
4545 operand_type_set (&i
.types
[3], 0);
4546 i
.reg_operands
-= 2;
4548 /* There are two different ways to encode a 4 operand
4549 instruction with all registers that uses OC1 set to
4550 0 or 1. Favor setting OC1 to 0 since this mimics the
4551 actions of other SSE5 assemblers. Use modrm encoding
4552 2 for register/register. Include the high order bit that
4553 is normally stored in the REX byte in the register
4555 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4556 i
.drex
.modrm_reg
= 1;
4557 i
.drex
.modrm_regmem
= 0;
4559 /* Remember the register, including the upper bits */
4560 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4561 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4564 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4565 else if (i
.types
[0].bitfield
.regxmm
!= 0
4566 && (i
.types
[1].bitfield
.regxmm
4567 || operand_type_check (i
.types
[1], anymem
))
4568 && i
.types
[2].bitfield
.regxmm
!= 0
4569 && i
.types
[3].bitfield
.regxmm
!= 0
4570 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4571 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4573 /* Clear the arguments that are stored in drex. */
4574 operand_type_set (&i
.types
[2], 0);
4575 operand_type_set (&i
.types
[3], 0);
4576 i
.reg_operands
-= 2;
4578 /* Specify the modrm encoding and remember the register
4579 including the bits normally stored in the REX byte. */
4580 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4581 i
.drex
.modrm_reg
= 0;
4582 i
.drex
.modrm_regmem
= 1;
4583 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4584 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4587 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4588 else if (operand_type_check (i
.types
[0], anymem
) != 0
4589 && i
.types
[1].bitfield
.regxmm
!= 0
4590 && i
.types
[2].bitfield
.regxmm
!= 0
4591 && i
.types
[3].bitfield
.regxmm
!= 0
4592 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4593 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4595 /* clear the arguments that are stored in drex */
4596 operand_type_set (&i
.types
[2], 0);
4597 operand_type_set (&i
.types
[3], 0);
4598 i
.reg_operands
-= 2;
4600 /* Specify the modrm encoding and remember the register
4601 including the bits normally stored in the REX byte. */
4602 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4603 i
.drex
.modrm_reg
= 1;
4604 i
.drex
.modrm_regmem
= 0;
4605 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4606 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4610 as_bad (_("Incorrect operands for the '%s' instruction"),
4614 /* SSE5 instructions with the DREX byte where the only memory operand
4615 is in the 2nd argument, and the first and last xmm register must
4616 match, and is encoded in the DREX byte. */
4617 else if (i
.tm
.opcode_modifier
.drex
4618 && !i
.tm
.opcode_modifier
.drexv
4621 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4622 if (i
.types
[0].bitfield
.regxmm
!= 0
4623 && (i
.types
[1].bitfield
.regxmm
4624 || operand_type_check(i
.types
[1], anymem
))
4625 && i
.types
[2].bitfield
.regxmm
!= 0
4626 && i
.types
[3].bitfield
.regxmm
!= 0
4627 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4628 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4630 /* clear the arguments that are stored in drex */
4631 operand_type_set (&i
.types
[0], 0);
4632 operand_type_set (&i
.types
[3], 0);
4633 i
.reg_operands
-= 2;
4635 /* Specify the modrm encoding and remember the register
4636 including the high bit normally stored in the REX
4638 i
.drex
.modrm_reg
= 2;
4639 i
.drex
.modrm_regmem
= 1;
4640 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4641 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4645 as_bad (_("Incorrect operands for the '%s' instruction"),
4649 /* SSE5 3 operand instructions that the result is a register, being
4650 either operand can be a memory operand, using OC0 to note which
4651 one is the memory. */
4652 else if (i
.tm
.opcode_modifier
.drex
4653 && i
.tm
.opcode_modifier
.drexv
4656 i
.tm
.extension_opcode
= None
;
4658 /* Case 1: 3 operand insn, src1 = register. */
4659 if (i
.types
[0].bitfield
.regxmm
!= 0
4660 && i
.types
[1].bitfield
.regxmm
!= 0
4661 && i
.types
[2].bitfield
.regxmm
!= 0)
4663 /* Clear the arguments that are stored in drex. */
4664 operand_type_set (&i
.types
[2], 0);
4667 /* Specify the modrm encoding and remember the register
4668 including the high bit normally stored in the REX byte. */
4669 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4670 i
.drex
.modrm_reg
= 1;
4671 i
.drex
.modrm_regmem
= 0;
4672 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4673 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4676 /* Case 2: 3 operand insn, src1 = memory. */
4677 else if (operand_type_check (i
.types
[0], anymem
) != 0
4678 && i
.types
[1].bitfield
.regxmm
!= 0
4679 && i
.types
[2].bitfield
.regxmm
!= 0)
4681 /* Clear the arguments that are stored in drex. */
4682 operand_type_set (&i
.types
[2], 0);
4685 /* Specify the modrm encoding and remember the register
4686 including the high bit normally stored in the REX
4688 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4689 i
.drex
.modrm_reg
= 1;
4690 i
.drex
.modrm_regmem
= 0;
4691 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4692 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4695 /* Case 3: 3 operand insn, src2 = memory. */
4696 else if (i
.types
[0].bitfield
.regxmm
!= 0
4697 && operand_type_check (i
.types
[1], anymem
) != 0
4698 && i
.types
[2].bitfield
.regxmm
!= 0)
4700 /* Clear the arguments that are stored in drex. */
4701 operand_type_set (&i
.types
[2], 0);
4704 /* Specify the modrm encoding and remember the register
4705 including the high bit normally stored in the REX byte. */
4706 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4707 i
.drex
.modrm_reg
= 0;
4708 i
.drex
.modrm_regmem
= 1;
4709 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4710 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4714 as_bad (_("Incorrect operands for the '%s' instruction"),
4718 /* SSE5 4 operand instructions that are the comparison instructions
4719 where the first operand is the immediate value of the comparison
4721 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4723 /* Case 1: 4 operand insn, src1 = reg/memory. */
4724 if (operand_type_check (i
.types
[0], imm
) != 0
4725 && (i
.types
[1].bitfield
.regxmm
4726 || operand_type_check (i
.types
[1], anymem
))
4727 && i
.types
[2].bitfield
.regxmm
!= 0
4728 && i
.types
[3].bitfield
.regxmm
!= 0)
4730 /* clear the arguments that are stored in drex */
4731 operand_type_set (&i
.types
[3], 0);
4734 /* Specify the modrm encoding and remember the register
4735 including the high bit normally stored in the REX byte. */
4736 i
.drex
.modrm_reg
= 2;
4737 i
.drex
.modrm_regmem
= 1;
4738 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4739 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4742 /* Case 2: 3 operand insn with ImmExt that places the
4743 opcode_extension as an immediate argument. This is used for
4744 all of the varients of comparison that supplies the appropriate
4745 value as part of the instruction. */
4746 else if ((i
.types
[0].bitfield
.regxmm
4747 || operand_type_check (i
.types
[0], anymem
))
4748 && i
.types
[1].bitfield
.regxmm
!= 0
4749 && i
.types
[2].bitfield
.regxmm
!= 0
4750 && operand_type_check (i
.types
[3], imm
) != 0)
4752 /* clear the arguments that are stored in drex */
4753 operand_type_set (&i
.types
[2], 0);
4756 /* Specify the modrm encoding and remember the register
4757 including the high bit normally stored in the REX byte. */
4758 i
.drex
.modrm_reg
= 1;
4759 i
.drex
.modrm_regmem
= 0;
4760 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4761 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4765 as_bad (_("Incorrect operands for the '%s' instruction"),
4769 else if (i
.tm
.opcode_modifier
.drex
4770 || i
.tm
.opcode_modifier
.drexv
4771 || i
.tm
.opcode_modifier
.drexc
)
4772 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4776 bad_implicit_operand (int xmm
)
4778 const char *reg
= xmm
? "xmm0" : "ymm0";
4780 as_bad (_("the last operand of `%s' must be `%s%s'"),
4781 i
.tm
.name
, register_prefix
, reg
);
4783 as_bad (_("the first operand of `%s' must be `%s%s'"),
4784 i
.tm
.name
, register_prefix
, reg
);
4789 process_operands (void)
4791 /* Default segment register this instruction will use for memory
4792 accesses. 0 means unknown. This is only for optimizing out
4793 unnecessary segment overrides. */
4794 const seg_entry
*default_seg
= 0;
4796 /* Handle all of the DREX munging that SSE5 needs. */
4797 if (i
.tm
.opcode_modifier
.drex
4798 || i
.tm
.opcode_modifier
.drexv
4799 || i
.tm
.opcode_modifier
.drexc
)
4802 if (i
.tm
.opcode_modifier
.sse2avx
4803 && (i
.tm
.opcode_modifier
.vexnds
4804 || i
.tm
.opcode_modifier
.vexndd
))
4806 unsigned int dup
= i
.operands
;
4807 unsigned int dest
= dup
- 1;
4810 /* The destination must be an xmm register. */
4811 assert (i
.reg_operands
4812 && MAX_OPERANDS
> dup
4813 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4815 if (i
.tm
.opcode_modifier
.firstxmm0
)
4817 /* The first operand is implicit and must be xmm0. */
4818 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4819 if (i
.op
[0].regs
->reg_num
!= 0)
4820 return bad_implicit_operand (1);
4822 if (i
.tm
.opcode_modifier
.vex3sources
)
4824 /* Keep xmm0 for instructions with VEX prefix and 3
4830 /* We remove the first xmm0 and keep the number of
4831 operands unchanged, which in fact duplicates the
4833 for (j
= 1; j
< i
.operands
; j
++)
4835 i
.op
[j
- 1] = i
.op
[j
];
4836 i
.types
[j
- 1] = i
.types
[j
];
4837 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4841 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4843 assert ((MAX_OPERANDS
- 1) > dup
4844 && i
.tm
.opcode_modifier
.vex3sources
);
4846 /* Add the implicit xmm0 for instructions with VEX prefix
4848 for (j
= i
.operands
; j
> 0; j
--)
4850 i
.op
[j
] = i
.op
[j
- 1];
4851 i
.types
[j
] = i
.types
[j
- 1];
4852 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4855 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4856 i
.types
[0] = regxmm
;
4857 i
.tm
.operand_types
[0] = regxmm
;
4860 i
.reg_operands
+= 2;
4865 i
.op
[dup
] = i
.op
[dest
];
4866 i
.types
[dup
] = i
.types
[dest
];
4867 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4876 i
.op
[dup
] = i
.op
[dest
];
4877 i
.types
[dup
] = i
.types
[dest
];
4878 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4881 if (i
.tm
.opcode_modifier
.immext
)
4884 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4888 /* The first operand is implicit and must be xmm0/ymm0. */
4889 assert (i
.reg_operands
4890 && (operand_type_equal (&i
.types
[0], ®xmm
)
4891 || operand_type_equal (&i
.types
[0], ®ymm
)));
4892 if (i
.op
[0].regs
->reg_num
!= 0)
4893 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4895 for (j
= 1; j
< i
.operands
; j
++)
4897 i
.op
[j
- 1] = i
.op
[j
];
4898 i
.types
[j
- 1] = i
.types
[j
];
4900 /* We need to adjust fields in i.tm since they are used by
4901 build_modrm_byte. */
4902 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4909 else if (i
.tm
.opcode_modifier
.regkludge
)
4911 /* The imul $imm, %reg instruction is converted into
4912 imul $imm, %reg, %reg, and the clr %reg instruction
4913 is converted into xor %reg, %reg. */
4915 unsigned int first_reg_op
;
4917 if (operand_type_check (i
.types
[0], reg
))
4921 /* Pretend we saw the extra register operand. */
4922 assert (i
.reg_operands
== 1
4923 && i
.op
[first_reg_op
+ 1].regs
== 0);
4924 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4925 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4930 if (i
.tm
.opcode_modifier
.shortform
)
4932 if (i
.types
[0].bitfield
.sreg2
4933 || i
.types
[0].bitfield
.sreg3
)
4935 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4936 && i
.op
[0].regs
->reg_num
== 1)
4938 as_bad (_("you can't `pop %%cs'"));
4941 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4942 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4947 /* The register or float register operand is in operand
4951 if (i
.types
[0].bitfield
.floatreg
4952 || operand_type_check (i
.types
[0], reg
))
4956 /* Register goes in low 3 bits of opcode. */
4957 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4958 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4960 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4962 /* Warn about some common errors, but press on regardless.
4963 The first case can be generated by gcc (<= 2.8.1). */
4964 if (i
.operands
== 2)
4966 /* Reversed arguments on faddp, fsubp, etc. */
4967 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4968 register_prefix
, i
.op
[1].regs
->reg_name
,
4969 register_prefix
, i
.op
[0].regs
->reg_name
);
4973 /* Extraneous `l' suffix on fp insn. */
4974 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4975 register_prefix
, i
.op
[0].regs
->reg_name
);
4980 else if (i
.tm
.opcode_modifier
.modrm
)
4982 /* The opcode is completed (modulo i.tm.extension_opcode which
4983 must be put into the modrm byte). Now, we make the modrm and
4984 index base bytes based on all the info we've collected. */
4986 default_seg
= build_modrm_byte ();
4988 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4992 else if (i
.tm
.opcode_modifier
.isstring
)
4994 /* For the string instructions that allow a segment override
4995 on one of their operands, the default segment is ds. */
4999 if (i
.tm
.base_opcode
== 0x8d /* lea */
5002 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5004 /* If a segment was explicitly specified, and the specified segment
5005 is not the default, use an opcode prefix to select it. If we
5006 never figured out what the default segment is, then default_seg
5007 will be zero at this point, and the specified segment prefix will
5009 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5011 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5017 static const seg_entry
*
5018 build_modrm_byte (void)
5020 const seg_entry
*default_seg
= 0;
5021 unsigned int source
, dest
;
5024 /* The first operand of instructions with VEX prefix and 3 sources
5025 must be VEX_Imm4. */
5026 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5029 unsigned int nds
, reg
;
5031 if (i
.tm
.opcode_modifier
.veximmext
5032 && i
.tm
.opcode_modifier
.immext
)
5034 dest
= i
.operands
- 2;
5038 dest
= i
.operands
- 1;
5041 /* There are 2 kinds of instructions:
5042 1. 5 operands: one immediate operand and 4 register
5043 operands or 3 register operands plus 1 memory operand.
5044 It must have VexNDS and VexW0 or VexW1. The destination
5045 must be either XMM or YMM register.
5046 2. 4 operands: 4 register operands or 3 register operands
5047 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5048 if (!((i
.reg_operands
== 4
5049 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5050 && i
.tm
.opcode_modifier
.vexnds
5051 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5052 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
5054 && i
.imm_operands
== 1
5055 && i
.types
[0].bitfield
.vex_imm4
5056 && (i
.tm
.opcode_modifier
.vexw0
5057 || i
.tm
.opcode_modifier
.vexw1
))
5059 && (i
.imm_operands
== 0
5060 || (i
.imm_operands
== 1
5061 && i
.tm
.opcode_modifier
.immext
))
5062 && i
.tm
.opcode_modifier
.veximmext
))))
5065 if (i
.imm_operands
== 0)
5067 /* When there is no immediate operand, generate an 8bit
5068 immediate operand to encode the first operand. */
5069 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5070 i
.op
[i
.operands
].imms
= exp
;
5071 i
.types
[i
.operands
] = imm8
;
5073 /* If VexW1 is set, the first operand is the source and
5074 the second operand is encoded in the immediate operand. */
5075 if (i
.tm
.opcode_modifier
.vexw1
)
5086 /* FMA swaps REG and NDS. */
5087 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5095 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5096 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5098 exp
->X_op
= O_constant
;
5100 = ((i
.op
[reg
].regs
->reg_num
5101 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5107 if (i
.tm
.opcode_modifier
.vexw0
)
5109 /* If VexW0 is set, the third operand is the source and
5110 the second operand is encoded in the immediate
5117 /* VexW1 is set, the second operand is the source and
5118 the third operand is encoded in the immediate
5124 if (i
.tm
.opcode_modifier
.immext
)
5126 /* When ImmExt is set, the immdiate byte is the last
5128 imm
= i
.operands
- 1;
5136 /* Turn on Imm8 so that output_imm will generate it. */
5137 i
.types
[imm
].bitfield
.imm8
= 1;
5140 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5141 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5143 i
.op
[imm
].imms
->X_add_number
5144 |= ((i
.op
[reg
].regs
->reg_num
5145 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5148 assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5149 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
));
5150 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5156 /* SSE5 4 operand instructions are encoded in such a way that one of
5157 the inputs must match the destination register. Process_drex hides
5158 the 3rd argument in the drex field, so that by the time we get
5159 here, it looks to GAS as if this is a 2 operand instruction. */
5160 if ((i
.tm
.opcode_modifier
.drex
5161 || i
.tm
.opcode_modifier
.drexv
5162 || i
.tm
.opcode_modifier
.drexc
)
5163 && i
.reg_operands
== 2)
5165 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5166 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5168 i
.rm
.reg
= reg
->reg_num
;
5169 i
.rm
.regmem
= regmem
->reg_num
;
5171 if ((reg
->reg_flags
& RegRex
) != 0)
5173 if ((regmem
->reg_flags
& RegRex
) != 0)
5177 /* i.reg_operands MUST be the number of real register operands;
5178 implicit registers do not count. If there are 3 register
5179 operands, it must be a instruction with VexNDS. For a
5180 instruction with VexNDD, the destination register is encoded
5181 in VEX prefix. If there are 4 register operands, it must be
5182 a instruction with VEX prefix and 3 sources. */
5183 else if (i
.mem_operands
== 0
5184 && ((i
.reg_operands
== 2
5185 && !i
.tm
.opcode_modifier
.vexndd
)
5186 || (i
.reg_operands
== 3
5187 && i
.tm
.opcode_modifier
.vexnds
)
5188 || (i
.reg_operands
== 4 && vex_3_sources
)))
5196 /* When there are 3 operands, one of them may be immediate,
5197 which may be the first or the last operand. Otherwise,
5198 the first operand must be shift count register (cl) or it
5199 is an instruction with VexNDS. */
5200 assert (i
.imm_operands
== 1
5201 || (i
.imm_operands
== 0
5202 && (i
.tm
.opcode_modifier
.vexnds
5203 || i
.types
[0].bitfield
.shiftcount
)));
5204 if (operand_type_check (i
.types
[0], imm
)
5205 || i
.types
[0].bitfield
.shiftcount
)
5211 /* When there are 4 operands, the first two must be 8bit
5212 immediate operands. The source operand will be the 3rd
5215 For instructions with VexNDS, if the first operand
5216 an imm8, the source operand is the 2nd one. If the last
5217 operand is imm8, the source operand is the first one. */
5218 assert ((i
.imm_operands
== 2
5219 && i
.types
[0].bitfield
.imm8
5220 && i
.types
[1].bitfield
.imm8
)
5221 || (i
.tm
.opcode_modifier
.vexnds
5222 && i
.imm_operands
== 1
5223 && (i
.types
[0].bitfield
.imm8
5224 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5225 if (i
.tm
.opcode_modifier
.vexnds
)
5227 if (i
.types
[0].bitfield
.imm8
)
5245 if (i
.tm
.opcode_modifier
.vexnds
)
5247 /* For instructions with VexNDS, the register-only
5248 source operand must be XMM or YMM register. It is
5249 encoded in VEX prefix. */
5250 if ((dest
+ 1) >= i
.operands
5251 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5253 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5256 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5262 /* One of the register operands will be encoded in the i.tm.reg
5263 field, the other in the combined i.tm.mode and i.tm.regmem
5264 fields. If no form of this instruction supports a memory
5265 destination operand, then we assume the source operand may
5266 sometimes be a memory operand and so we need to store the
5267 destination in the i.rm.reg field. */
5268 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5269 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5271 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5272 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5273 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5275 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5280 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5281 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5282 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5284 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5287 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5289 if (!i
.types
[0].bitfield
.control
5290 && !i
.types
[1].bitfield
.control
)
5292 i
.rex
&= ~(REX_R
| REX_B
);
5293 add_prefix (LOCK_PREFIX_OPCODE
);
5297 { /* If it's not 2 reg operands... */
5302 unsigned int fake_zero_displacement
= 0;
5305 /* This has been precalculated for SSE5 instructions
5306 that have a DREX field earlier in process_drex. */
5307 if (i
.tm
.opcode_modifier
.drex
5308 || i
.tm
.opcode_modifier
.drexv
5309 || i
.tm
.opcode_modifier
.drexc
)
5310 op
= i
.drex
.modrm_regmem
;
5313 for (op
= 0; op
< i
.operands
; op
++)
5314 if (operand_type_check (i
.types
[op
], anymem
))
5316 assert (op
< i
.operands
);
5321 if (i
.base_reg
== 0)
5324 if (!i
.disp_operands
)
5325 fake_zero_displacement
= 1;
5326 if (i
.index_reg
== 0)
5328 /* Operand is just <disp> */
5329 if (flag_code
== CODE_64BIT
)
5331 /* 64bit mode overwrites the 32bit absolute
5332 addressing by RIP relative addressing and
5333 absolute addressing is encoded by one of the
5334 redundant SIB forms. */
5335 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5336 i
.sib
.base
= NO_BASE_REGISTER
;
5337 i
.sib
.index
= NO_INDEX_REGISTER
;
5338 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5339 ? disp32s
: disp32
);
5341 else if ((flag_code
== CODE_16BIT
)
5342 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5344 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5345 i
.types
[op
] = disp16
;
5349 i
.rm
.regmem
= NO_BASE_REGISTER
;
5350 i
.types
[op
] = disp32
;
5353 else /* !i.base_reg && i.index_reg */
5355 if (i
.index_reg
->reg_num
== RegEiz
5356 || i
.index_reg
->reg_num
== RegRiz
)
5357 i
.sib
.index
= NO_INDEX_REGISTER
;
5359 i
.sib
.index
= i
.index_reg
->reg_num
;
5360 i
.sib
.base
= NO_BASE_REGISTER
;
5361 i
.sib
.scale
= i
.log2_scale_factor
;
5362 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5363 i
.types
[op
].bitfield
.disp8
= 0;
5364 i
.types
[op
].bitfield
.disp16
= 0;
5365 i
.types
[op
].bitfield
.disp64
= 0;
5366 if (flag_code
!= CODE_64BIT
)
5368 /* Must be 32 bit */
5369 i
.types
[op
].bitfield
.disp32
= 1;
5370 i
.types
[op
].bitfield
.disp32s
= 0;
5374 i
.types
[op
].bitfield
.disp32
= 0;
5375 i
.types
[op
].bitfield
.disp32s
= 1;
5377 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5381 /* RIP addressing for 64bit mode. */
5382 else if (i
.base_reg
->reg_num
== RegRip
||
5383 i
.base_reg
->reg_num
== RegEip
)
5385 i
.rm
.regmem
= NO_BASE_REGISTER
;
5386 i
.types
[op
].bitfield
.disp8
= 0;
5387 i
.types
[op
].bitfield
.disp16
= 0;
5388 i
.types
[op
].bitfield
.disp32
= 0;
5389 i
.types
[op
].bitfield
.disp32s
= 1;
5390 i
.types
[op
].bitfield
.disp64
= 0;
5391 i
.flags
[op
] |= Operand_PCrel
;
5392 if (! i
.disp_operands
)
5393 fake_zero_displacement
= 1;
5395 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5397 switch (i
.base_reg
->reg_num
)
5400 if (i
.index_reg
== 0)
5402 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5403 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5407 if (i
.index_reg
== 0)
5410 if (operand_type_check (i
.types
[op
], disp
) == 0)
5412 /* fake (%bp) into 0(%bp) */
5413 i
.types
[op
].bitfield
.disp8
= 1;
5414 fake_zero_displacement
= 1;
5417 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5418 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5420 default: /* (%si) -> 4 or (%di) -> 5 */
5421 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5423 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5425 else /* i.base_reg and 32/64 bit mode */
5427 if (flag_code
== CODE_64BIT
5428 && operand_type_check (i
.types
[op
], disp
))
5430 i386_operand_type temp
;
5431 operand_type_set (&temp
, 0);
5432 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5434 if (i
.prefix
[ADDR_PREFIX
] == 0)
5435 i
.types
[op
].bitfield
.disp32s
= 1;
5437 i
.types
[op
].bitfield
.disp32
= 1;
5440 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5441 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5443 i
.sib
.base
= i
.base_reg
->reg_num
;
5444 /* x86-64 ignores REX prefix bit here to avoid decoder
5446 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5449 if (i
.disp_operands
== 0)
5451 fake_zero_displacement
= 1;
5452 i
.types
[op
].bitfield
.disp8
= 1;
5455 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5459 i
.sib
.scale
= i
.log2_scale_factor
;
5460 if (i
.index_reg
== 0)
5462 /* <disp>(%esp) becomes two byte modrm with no index
5463 register. We've already stored the code for esp
5464 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5465 Any base register besides %esp will not use the
5466 extra modrm byte. */
5467 i
.sib
.index
= NO_INDEX_REGISTER
;
5471 if (i
.index_reg
->reg_num
== RegEiz
5472 || i
.index_reg
->reg_num
== RegRiz
)
5473 i
.sib
.index
= NO_INDEX_REGISTER
;
5475 i
.sib
.index
= i
.index_reg
->reg_num
;
5476 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5477 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5482 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5483 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5489 if (fake_zero_displacement
)
5491 /* Fakes a zero displacement assuming that i.types[op]
5492 holds the correct displacement size. */
5495 assert (i
.op
[op
].disps
== 0);
5496 exp
= &disp_expressions
[i
.disp_operands
++];
5497 i
.op
[op
].disps
= exp
;
5498 exp
->X_op
= O_constant
;
5499 exp
->X_add_number
= 0;
5500 exp
->X_add_symbol
= (symbolS
*) 0;
5501 exp
->X_op_symbol
= (symbolS
*) 0;
5509 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5510 (if any) based on i.tm.extension_opcode. Again, we must be
5511 careful to make sure that segment/control/debug/test/MMX
5512 registers are coded into the i.rm.reg field. */
5517 /* This has been precalculated for SSE5 instructions
5518 that have a DREX field earlier in process_drex. */
5519 if (i
.tm
.opcode_modifier
.drex
5520 || i
.tm
.opcode_modifier
.drexv
5521 || i
.tm
.opcode_modifier
.drexc
)
5523 op
= i
.drex
.modrm_reg
;
5524 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5525 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5530 unsigned int vex_reg
= ~0;
5532 for (op
= 0; op
< i
.operands
; op
++)
5533 if (i
.types
[op
].bitfield
.reg8
5534 || i
.types
[op
].bitfield
.reg16
5535 || i
.types
[op
].bitfield
.reg32
5536 || i
.types
[op
].bitfield
.reg64
5537 || i
.types
[op
].bitfield
.regmmx
5538 || i
.types
[op
].bitfield
.regxmm
5539 || i
.types
[op
].bitfield
.regymm
5540 || i
.types
[op
].bitfield
.sreg2
5541 || i
.types
[op
].bitfield
.sreg3
5542 || i
.types
[op
].bitfield
.control
5543 || i
.types
[op
].bitfield
.debug
5544 || i
.types
[op
].bitfield
.test
)
5549 else if (i
.tm
.opcode_modifier
.vexnds
)
5551 /* For instructions with VexNDS, the register-only
5552 source operand is encoded in VEX prefix. */
5553 assert (mem
!= (unsigned int) ~0);
5558 assert (op
< i
.operands
);
5563 assert (vex_reg
< i
.operands
);
5566 else if (i
.tm
.opcode_modifier
.vexndd
)
5568 /* For instructions with VexNDD, there should be
5569 no memory operand and the register destination
5570 is encoded in VEX prefix. */
5571 assert (i
.mem_operands
== 0
5572 && (op
+ 2) == i
.operands
);
5576 assert (op
< i
.operands
);
5578 if (vex_reg
!= (unsigned int) ~0)
5580 assert (i
.reg_operands
== 2);
5582 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5584 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5587 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5590 /* If there is an extension opcode to put here, the
5591 register number must be put into the regmem field. */
5592 if (i
.tm
.extension_opcode
!= None
)
5594 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5595 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5600 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5601 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5606 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5607 must set it to 3 to indicate this is a register operand
5608 in the regmem field. */
5609 if (!i
.mem_operands
)
5613 /* Fill in i.rm.reg field with extension opcode (if any). */
5614 if (i
.tm
.extension_opcode
!= None
5615 && !(i
.tm
.opcode_modifier
.drex
5616 || i
.tm
.opcode_modifier
.drexv
5617 || i
.tm
.opcode_modifier
.drexc
))
5618 i
.rm
.reg
= i
.tm
.extension_opcode
;
5624 output_branch (void)
5629 relax_substateT subtype
;
5634 if (flag_code
== CODE_16BIT
)
5638 if (i
.prefix
[DATA_PREFIX
] != 0)
5644 /* Pentium4 branch hints. */
5645 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5646 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5651 if (i
.prefix
[REX_PREFIX
] != 0)
5657 if (i
.prefixes
!= 0 && !intel_syntax
)
5658 as_warn (_("skipping prefixes on this instruction"));
5660 /* It's always a symbol; End frag & setup for relax.
5661 Make sure there is enough room in this frag for the largest
5662 instruction we may generate in md_convert_frag. This is 2
5663 bytes for the opcode and room for the prefix and largest
5665 frag_grow (prefix
+ 2 + 4);
5666 /* Prefix and 1 opcode byte go in fr_fix. */
5667 p
= frag_more (prefix
+ 1);
5668 if (i
.prefix
[DATA_PREFIX
] != 0)
5669 *p
++ = DATA_PREFIX_OPCODE
;
5670 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5671 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5672 *p
++ = i
.prefix
[SEG_PREFIX
];
5673 if (i
.prefix
[REX_PREFIX
] != 0)
5674 *p
++ = i
.prefix
[REX_PREFIX
];
5675 *p
= i
.tm
.base_opcode
;
5677 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5678 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5679 else if (cpu_arch_flags
.bitfield
.cpui386
)
5680 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5682 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5685 sym
= i
.op
[0].disps
->X_add_symbol
;
5686 off
= i
.op
[0].disps
->X_add_number
;
5688 if (i
.op
[0].disps
->X_op
!= O_constant
5689 && i
.op
[0].disps
->X_op
!= O_symbol
)
5691 /* Handle complex expressions. */
5692 sym
= make_expr_symbol (i
.op
[0].disps
);
5696 /* 1 possible extra opcode + 4 byte displacement go in var part.
5697 Pass reloc in fr_var. */
5698 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5708 if (i
.tm
.opcode_modifier
.jumpbyte
)
5710 /* This is a loop or jecxz type instruction. */
5712 if (i
.prefix
[ADDR_PREFIX
] != 0)
5714 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5717 /* Pentium4 branch hints. */
5718 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5719 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5721 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5730 if (flag_code
== CODE_16BIT
)
5733 if (i
.prefix
[DATA_PREFIX
] != 0)
5735 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5745 if (i
.prefix
[REX_PREFIX
] != 0)
5747 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5751 if (i
.prefixes
!= 0 && !intel_syntax
)
5752 as_warn (_("skipping prefixes on this instruction"));
5754 p
= frag_more (1 + size
);
5755 *p
++ = i
.tm
.base_opcode
;
5757 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5758 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5760 /* All jumps handled here are signed, but don't use a signed limit
5761 check for 32 and 16 bit jumps as we want to allow wrap around at
5762 4G and 64k respectively. */
5764 fixP
->fx_signed
= 1;
5768 output_interseg_jump (void)
5776 if (flag_code
== CODE_16BIT
)
5780 if (i
.prefix
[DATA_PREFIX
] != 0)
5786 if (i
.prefix
[REX_PREFIX
] != 0)
5796 if (i
.prefixes
!= 0 && !intel_syntax
)
5797 as_warn (_("skipping prefixes on this instruction"));
5799 /* 1 opcode; 2 segment; offset */
5800 p
= frag_more (prefix
+ 1 + 2 + size
);
5802 if (i
.prefix
[DATA_PREFIX
] != 0)
5803 *p
++ = DATA_PREFIX_OPCODE
;
5805 if (i
.prefix
[REX_PREFIX
] != 0)
5806 *p
++ = i
.prefix
[REX_PREFIX
];
5808 *p
++ = i
.tm
.base_opcode
;
5809 if (i
.op
[1].imms
->X_op
== O_constant
)
5811 offsetT n
= i
.op
[1].imms
->X_add_number
;
5814 && !fits_in_unsigned_word (n
)
5815 && !fits_in_signed_word (n
))
5817 as_bad (_("16-bit jump out of range"));
5820 md_number_to_chars (p
, n
, size
);
5823 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5824 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5825 if (i
.op
[0].imms
->X_op
!= O_constant
)
5826 as_bad (_("can't handle non absolute segment in `%s'"),
5828 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5834 fragS
*insn_start_frag
;
5835 offsetT insn_start_off
;
5837 /* Tie dwarf2 debug info to the address at the start of the insn.
5838 We can't do this after the insn has been output as the current
5839 frag may have been closed off. eg. by frag_var. */
5840 dwarf2_emit_insn (0);
5842 insn_start_frag
= frag_now
;
5843 insn_start_off
= frag_now_fix ();
5846 if (i
.tm
.opcode_modifier
.jump
)
5848 else if (i
.tm
.opcode_modifier
.jumpbyte
5849 || i
.tm
.opcode_modifier
.jumpdword
)
5851 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5852 output_interseg_jump ();
5855 /* Output normal instructions here. */
5859 unsigned int prefix
;
5861 /* Since the VEX prefix contains the implicit prefix, we don't
5862 need the explicit prefix. */
5863 if (!i
.tm
.opcode_modifier
.vex
)
5865 switch (i
.tm
.opcode_length
)
5868 if (i
.tm
.base_opcode
& 0xff000000)
5870 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5875 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5877 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5878 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5881 if (prefix
!= REPE_PREFIX_OPCODE
5882 || (i
.prefix
[LOCKREP_PREFIX
]
5883 != REPE_PREFIX_OPCODE
))
5884 add_prefix (prefix
);
5887 add_prefix (prefix
);
5896 /* The prefix bytes. */
5897 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5899 FRAG_APPEND_1_CHAR (*q
);
5902 if (i
.tm
.opcode_modifier
.vex
)
5904 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5909 /* REX byte is encoded in VEX prefix. */
5913 FRAG_APPEND_1_CHAR (*q
);
5916 /* There should be no other prefixes for instructions
5921 /* Now the VEX prefix. */
5922 p
= frag_more (i
.vex
.length
);
5923 for (j
= 0; j
< i
.vex
.length
; j
++)
5924 p
[j
] = i
.vex
.bytes
[j
];
5927 /* Now the opcode; be careful about word order here! */
5928 if (i
.tm
.opcode_length
== 1)
5930 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5934 switch (i
.tm
.opcode_length
)
5938 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5948 /* Put out high byte first: can't use md_number_to_chars! */
5949 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5950 *p
= i
.tm
.base_opcode
& 0xff;
5952 /* On SSE5, encode the OC1 bit in the DREX field if this
5953 encoding has multiple formats. */
5954 if (i
.tm
.opcode_modifier
.drex
5955 && i
.tm
.opcode_modifier
.drexv
5956 && DREX_OC1 (i
.tm
.extension_opcode
))
5957 *p
|= DREX_OC1_MASK
;
5960 /* Now the modrm byte and sib byte (if present). */
5961 if (i
.tm
.opcode_modifier
.modrm
)
5963 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5966 /* If i.rm.regmem == ESP (4)
5967 && i.rm.mode != (Register mode)
5969 ==> need second modrm byte. */
5970 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5972 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5973 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5975 | i
.sib
.scale
<< 6));
5978 /* Write the DREX byte if needed. */
5979 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5982 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5984 /* Encode the OC0 bit if this encoding has multiple
5986 if ((i
.tm
.opcode_modifier
.drex
5987 || i
.tm
.opcode_modifier
.drexv
)
5988 && DREX_OC0 (i
.tm
.extension_opcode
))
5989 *p
|= DREX_OC0_MASK
;
5992 if (i
.disp_operands
)
5993 output_disp (insn_start_frag
, insn_start_off
);
5996 output_imm (insn_start_frag
, insn_start_off
);
6002 pi ("" /*line*/, &i
);
6004 #endif /* DEBUG386 */
6007 /* Return the size of the displacement operand N. */
6010 disp_size (unsigned int n
)
6013 if (i
.types
[n
].bitfield
.disp64
)
6015 else if (i
.types
[n
].bitfield
.disp8
)
6017 else if (i
.types
[n
].bitfield
.disp16
)
6022 /* Return the size of the immediate operand N. */
6025 imm_size (unsigned int n
)
6028 if (i
.types
[n
].bitfield
.imm64
)
6030 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6032 else if (i
.types
[n
].bitfield
.imm16
)
6038 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6043 for (n
= 0; n
< i
.operands
; n
++)
6045 if (operand_type_check (i
.types
[n
], disp
))
6047 if (i
.op
[n
].disps
->X_op
== O_constant
)
6049 int size
= disp_size (n
);
6052 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6054 p
= frag_more (size
);
6055 md_number_to_chars (p
, val
, size
);
6059 enum bfd_reloc_code_real reloc_type
;
6060 int size
= disp_size (n
);
6061 int sign
= i
.types
[n
].bitfield
.disp32s
;
6062 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6064 /* We can't have 8 bit displacement here. */
6065 assert (!i
.types
[n
].bitfield
.disp8
);
6067 /* The PC relative address is computed relative
6068 to the instruction boundary, so in case immediate
6069 fields follows, we need to adjust the value. */
6070 if (pcrel
&& i
.imm_operands
)
6075 for (n1
= 0; n1
< i
.operands
; n1
++)
6076 if (operand_type_check (i
.types
[n1
], imm
))
6078 /* Only one immediate is allowed for PC
6079 relative address. */
6082 i
.op
[n
].disps
->X_add_number
-= sz
;
6084 /* We should find the immediate. */
6088 p
= frag_more (size
);
6089 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6091 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6092 && (((reloc_type
== BFD_RELOC_32
6093 || reloc_type
== BFD_RELOC_X86_64_32S
6094 || (reloc_type
== BFD_RELOC_64
6096 && (i
.op
[n
].disps
->X_op
== O_symbol
6097 || (i
.op
[n
].disps
->X_op
== O_add
6098 && ((symbol_get_value_expression
6099 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6101 || reloc_type
== BFD_RELOC_32_PCREL
))
6105 if (insn_start_frag
== frag_now
)
6106 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6111 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6112 for (fr
= insn_start_frag
->fr_next
;
6113 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6115 add
+= p
- frag_now
->fr_literal
;
6120 reloc_type
= BFD_RELOC_386_GOTPC
;
6121 i
.op
[n
].imms
->X_add_number
+= add
;
6123 else if (reloc_type
== BFD_RELOC_64
)
6124 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6126 /* Don't do the adjustment for x86-64, as there
6127 the pcrel addressing is relative to the _next_
6128 insn, and that is taken care of in other code. */
6129 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6131 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6132 i
.op
[n
].disps
, pcrel
, reloc_type
);
6139 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6144 for (n
= 0; n
< i
.operands
; n
++)
6146 if (operand_type_check (i
.types
[n
], imm
))
6148 if (i
.op
[n
].imms
->X_op
== O_constant
)
6150 int size
= imm_size (n
);
6153 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6155 p
= frag_more (size
);
6156 md_number_to_chars (p
, val
, size
);
6160 /* Not absolute_section.
6161 Need a 32-bit fixup (don't support 8bit
6162 non-absolute imms). Try to support other
6164 enum bfd_reloc_code_real reloc_type
;
6165 int size
= imm_size (n
);
6168 if (i
.types
[n
].bitfield
.imm32s
6169 && (i
.suffix
== QWORD_MNEM_SUFFIX
6170 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6175 p
= frag_more (size
);
6176 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6178 /* This is tough to explain. We end up with this one if we
6179 * have operands that look like
6180 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6181 * obtain the absolute address of the GOT, and it is strongly
6182 * preferable from a performance point of view to avoid using
6183 * a runtime relocation for this. The actual sequence of
6184 * instructions often look something like:
6189 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6191 * The call and pop essentially return the absolute address
6192 * of the label .L66 and store it in %ebx. The linker itself
6193 * will ultimately change the first operand of the addl so
6194 * that %ebx points to the GOT, but to keep things simple, the
6195 * .o file must have this operand set so that it generates not
6196 * the absolute address of .L66, but the absolute address of
6197 * itself. This allows the linker itself simply treat a GOTPC
6198 * relocation as asking for a pcrel offset to the GOT to be
6199 * added in, and the addend of the relocation is stored in the
6200 * operand field for the instruction itself.
6202 * Our job here is to fix the operand so that it would add
6203 * the correct offset so that %ebx would point to itself. The
6204 * thing that is tricky is that .-.L66 will point to the
6205 * beginning of the instruction, so we need to further modify
6206 * the operand so that it will point to itself. There are
6207 * other cases where you have something like:
6209 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6211 * and here no correction would be required. Internally in
6212 * the assembler we treat operands of this form as not being
6213 * pcrel since the '.' is explicitly mentioned, and I wonder
6214 * whether it would simplify matters to do it this way. Who
6215 * knows. In earlier versions of the PIC patches, the
6216 * pcrel_adjust field was used to store the correction, but
6217 * since the expression is not pcrel, I felt it would be
6218 * confusing to do it this way. */
6220 if ((reloc_type
== BFD_RELOC_32
6221 || reloc_type
== BFD_RELOC_X86_64_32S
6222 || reloc_type
== BFD_RELOC_64
)
6224 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6225 && (i
.op
[n
].imms
->X_op
== O_symbol
6226 || (i
.op
[n
].imms
->X_op
== O_add
6227 && ((symbol_get_value_expression
6228 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6233 if (insn_start_frag
== frag_now
)
6234 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6239 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6240 for (fr
= insn_start_frag
->fr_next
;
6241 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6243 add
+= p
- frag_now
->fr_literal
;
6247 reloc_type
= BFD_RELOC_386_GOTPC
;
6249 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6251 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6252 i
.op
[n
].imms
->X_add_number
+= add
;
6254 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6255 i
.op
[n
].imms
, 0, reloc_type
);
6261 /* x86_cons_fix_new is called via the expression parsing code when a
6262 reloc is needed. We use this hook to get the correct .got reloc. */
6263 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6264 static int cons_sign
= -1;
6267 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6270 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6272 got_reloc
= NO_RELOC
;
6275 if (exp
->X_op
== O_secrel
)
6277 exp
->X_op
= O_symbol
;
6278 r
= BFD_RELOC_32_SECREL
;
6282 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6285 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6286 # define lex_got(reloc, adjust, types) NULL
6288 /* Parse operands of the form
6289 <symbol>@GOTOFF+<nnn>
6290 and similar .plt or .got references.
6292 If we find one, set up the correct relocation in RELOC and copy the
6293 input string, minus the `@GOTOFF' into a malloc'd buffer for
6294 parsing by the calling routine. Return this buffer, and if ADJUST
6295 is non-null set it to the length of the string we removed from the
6296 input line. Otherwise return NULL. */
6298 lex_got (enum bfd_reloc_code_real
*reloc
,
6300 i386_operand_type
*types
)
6302 /* Some of the relocations depend on the size of what field is to
6303 be relocated. But in our callers i386_immediate and i386_displacement
6304 we don't yet know the operand size (this will be set by insn
6305 matching). Hence we record the word32 relocation here,
6306 and adjust the reloc according to the real size in reloc(). */
6307 static const struct {
6309 const enum bfd_reloc_code_real rel
[2];
6310 const i386_operand_type types64
;
6313 BFD_RELOC_X86_64_PLTOFF64
},
6314 OPERAND_TYPE_IMM64
},
6315 { "PLT", { BFD_RELOC_386_PLT32
,
6316 BFD_RELOC_X86_64_PLT32
},
6317 OPERAND_TYPE_IMM32_32S_DISP32
},
6319 BFD_RELOC_X86_64_GOTPLT64
},
6320 OPERAND_TYPE_IMM64_DISP64
},
6321 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6322 BFD_RELOC_X86_64_GOTOFF64
},
6323 OPERAND_TYPE_IMM64_DISP64
},
6325 BFD_RELOC_X86_64_GOTPCREL
},
6326 OPERAND_TYPE_IMM32_32S_DISP32
},
6327 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6328 BFD_RELOC_X86_64_TLSGD
},
6329 OPERAND_TYPE_IMM32_32S_DISP32
},
6330 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6332 OPERAND_TYPE_NONE
},
6334 BFD_RELOC_X86_64_TLSLD
},
6335 OPERAND_TYPE_IMM32_32S_DISP32
},
6336 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6337 BFD_RELOC_X86_64_GOTTPOFF
},
6338 OPERAND_TYPE_IMM32_32S_DISP32
},
6339 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6340 BFD_RELOC_X86_64_TPOFF32
},
6341 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6342 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6344 OPERAND_TYPE_NONE
},
6345 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6346 BFD_RELOC_X86_64_DTPOFF32
},
6348 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6349 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6351 OPERAND_TYPE_NONE
},
6352 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6354 OPERAND_TYPE_NONE
},
6355 { "GOT", { BFD_RELOC_386_GOT32
,
6356 BFD_RELOC_X86_64_GOT32
},
6357 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6358 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6359 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6360 OPERAND_TYPE_IMM32_32S_DISP32
},
6361 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6362 BFD_RELOC_X86_64_TLSDESC_CALL
},
6363 OPERAND_TYPE_IMM32_32S_DISP32
},
6371 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6372 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6375 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6379 len
= strlen (gotrel
[j
].str
);
6380 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6382 if (gotrel
[j
].rel
[object_64bit
] != 0)
6385 char *tmpbuf
, *past_reloc
;
6387 *reloc
= gotrel
[j
].rel
[object_64bit
];
6393 if (flag_code
!= CODE_64BIT
)
6395 types
->bitfield
.imm32
= 1;
6396 types
->bitfield
.disp32
= 1;
6399 *types
= gotrel
[j
].types64
;
6402 if (GOT_symbol
== NULL
)
6403 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6405 /* The length of the first part of our input line. */
6406 first
= cp
- input_line_pointer
;
6408 /* The second part goes from after the reloc token until
6409 (and including) an end_of_line char or comma. */
6410 past_reloc
= cp
+ 1 + len
;
6412 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6414 second
= cp
+ 1 - past_reloc
;
6416 /* Allocate and copy string. The trailing NUL shouldn't
6417 be necessary, but be safe. */
6418 tmpbuf
= xmalloc (first
+ second
+ 2);
6419 memcpy (tmpbuf
, input_line_pointer
, first
);
6420 if (second
!= 0 && *past_reloc
!= ' ')
6421 /* Replace the relocation token with ' ', so that
6422 errors like foo@GOTOFF1 will be detected. */
6423 tmpbuf
[first
++] = ' ';
6424 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6425 tmpbuf
[first
+ second
] = '\0';
6429 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6430 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6435 /* Might be a symbol version string. Don't as_bad here. */
6440 x86_cons (expressionS
*exp
, int size
)
6442 if (size
== 4 || (object_64bit
&& size
== 8))
6444 /* Handle @GOTOFF and the like in an expression. */
6446 char *gotfree_input_line
;
6449 save
= input_line_pointer
;
6450 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6451 if (gotfree_input_line
)
6452 input_line_pointer
= gotfree_input_line
;
6456 if (gotfree_input_line
)
6458 /* expression () has merrily parsed up to the end of line,
6459 or a comma - in the wrong buffer. Transfer how far
6460 input_line_pointer has moved to the right buffer. */
6461 input_line_pointer
= (save
6462 + (input_line_pointer
- gotfree_input_line
)
6464 free (gotfree_input_line
);
6465 if (exp
->X_op
== O_constant
6466 || exp
->X_op
== O_absent
6467 || exp
->X_op
== O_illegal
6468 || exp
->X_op
== O_register
6469 || exp
->X_op
== O_big
)
6471 char c
= *input_line_pointer
;
6472 *input_line_pointer
= 0;
6473 as_bad (_("missing or invalid expression `%s'"), save
);
6474 *input_line_pointer
= c
;
6483 static void signed_cons (int size
)
6485 if (flag_code
== CODE_64BIT
)
6493 pe_directive_secrel (dummy
)
6494 int dummy ATTRIBUTE_UNUSED
;
6501 if (exp
.X_op
== O_symbol
)
6502 exp
.X_op
= O_secrel
;
6504 emit_expr (&exp
, 4);
6506 while (*input_line_pointer
++ == ',');
6508 input_line_pointer
--;
6509 demand_empty_rest_of_line ();
6514 i386_immediate (char *imm_start
)
6516 char *save_input_line_pointer
;
6517 char *gotfree_input_line
;
6520 i386_operand_type types
;
6522 operand_type_set (&types
, ~0);
6524 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6526 as_bad (_("at most %d immediate operands are allowed"),
6527 MAX_IMMEDIATE_OPERANDS
);
6531 exp
= &im_expressions
[i
.imm_operands
++];
6532 i
.op
[this_operand
].imms
= exp
;
6534 if (is_space_char (*imm_start
))
6537 save_input_line_pointer
= input_line_pointer
;
6538 input_line_pointer
= imm_start
;
6540 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6541 if (gotfree_input_line
)
6542 input_line_pointer
= gotfree_input_line
;
6544 exp_seg
= expression (exp
);
6547 if (*input_line_pointer
)
6548 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6550 input_line_pointer
= save_input_line_pointer
;
6551 if (gotfree_input_line
)
6552 free (gotfree_input_line
);
6554 if (exp
->X_op
== O_absent
6555 || exp
->X_op
== O_illegal
6556 || exp
->X_op
== O_big
6557 || (gotfree_input_line
6558 && (exp
->X_op
== O_constant
6559 || exp
->X_op
== O_register
)))
6561 as_bad (_("missing or invalid immediate expression `%s'"),
6565 else if (exp
->X_op
== O_constant
)
6567 /* Size it properly later. */
6568 i
.types
[this_operand
].bitfield
.imm64
= 1;
6569 /* If BFD64, sign extend val. */
6570 if (!use_rela_relocations
6571 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6573 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6575 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6576 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6577 && exp_seg
!= absolute_section
6578 && exp_seg
!= text_section
6579 && exp_seg
!= data_section
6580 && exp_seg
!= bss_section
6581 && exp_seg
!= undefined_section
6582 && !bfd_is_com_section (exp_seg
))
6584 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6588 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6590 as_bad (_("illegal immediate register operand %s"), imm_start
);
6595 /* This is an address. The size of the address will be
6596 determined later, depending on destination register,
6597 suffix, or the default for the section. */
6598 i
.types
[this_operand
].bitfield
.imm8
= 1;
6599 i
.types
[this_operand
].bitfield
.imm16
= 1;
6600 i
.types
[this_operand
].bitfield
.imm32
= 1;
6601 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6602 i
.types
[this_operand
].bitfield
.imm64
= 1;
6603 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6611 i386_scale (char *scale
)
6614 char *save
= input_line_pointer
;
6616 input_line_pointer
= scale
;
6617 val
= get_absolute_expression ();
6622 i
.log2_scale_factor
= 0;
6625 i
.log2_scale_factor
= 1;
6628 i
.log2_scale_factor
= 2;
6631 i
.log2_scale_factor
= 3;
6635 char sep
= *input_line_pointer
;
6637 *input_line_pointer
= '\0';
6638 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6640 *input_line_pointer
= sep
;
6641 input_line_pointer
= save
;
6645 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6647 as_warn (_("scale factor of %d without an index register"),
6648 1 << i
.log2_scale_factor
);
6649 i
.log2_scale_factor
= 0;
6651 scale
= input_line_pointer
;
6652 input_line_pointer
= save
;
6657 i386_displacement (char *disp_start
, char *disp_end
)
6661 char *save_input_line_pointer
;
6662 char *gotfree_input_line
;
6664 i386_operand_type bigdisp
, types
= anydisp
;
6667 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6669 as_bad (_("at most %d displacement operands are allowed"),
6670 MAX_MEMORY_OPERANDS
);
6674 operand_type_set (&bigdisp
, 0);
6675 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6676 || (!current_templates
->start
->opcode_modifier
.jump
6677 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6679 bigdisp
.bitfield
.disp32
= 1;
6680 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6681 if (flag_code
== CODE_64BIT
)
6685 bigdisp
.bitfield
.disp32s
= 1;
6686 bigdisp
.bitfield
.disp64
= 1;
6689 else if ((flag_code
== CODE_16BIT
) ^ override
)
6691 bigdisp
.bitfield
.disp32
= 0;
6692 bigdisp
.bitfield
.disp16
= 1;
6697 /* For PC-relative branches, the width of the displacement
6698 is dependent upon data size, not address size. */
6699 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6700 if (flag_code
== CODE_64BIT
)
6702 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6703 bigdisp
.bitfield
.disp16
= 1;
6706 bigdisp
.bitfield
.disp32
= 1;
6707 bigdisp
.bitfield
.disp32s
= 1;
6713 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6715 : LONG_MNEM_SUFFIX
));
6716 bigdisp
.bitfield
.disp32
= 1;
6717 if ((flag_code
== CODE_16BIT
) ^ override
)
6719 bigdisp
.bitfield
.disp32
= 0;
6720 bigdisp
.bitfield
.disp16
= 1;
6724 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6727 exp
= &disp_expressions
[i
.disp_operands
];
6728 i
.op
[this_operand
].disps
= exp
;
6730 save_input_line_pointer
= input_line_pointer
;
6731 input_line_pointer
= disp_start
;
6732 END_STRING_AND_SAVE (disp_end
);
6734 #ifndef GCC_ASM_O_HACK
6735 #define GCC_ASM_O_HACK 0
6738 END_STRING_AND_SAVE (disp_end
+ 1);
6739 if (i
.types
[this_operand
].bitfield
.baseIndex
6740 && displacement_string_end
[-1] == '+')
6742 /* This hack is to avoid a warning when using the "o"
6743 constraint within gcc asm statements.
6746 #define _set_tssldt_desc(n,addr,limit,type) \
6747 __asm__ __volatile__ ( \
6749 "movw %w1,2+%0\n\t" \
6751 "movb %b1,4+%0\n\t" \
6752 "movb %4,5+%0\n\t" \
6753 "movb $0,6+%0\n\t" \
6754 "movb %h1,7+%0\n\t" \
6756 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6758 This works great except that the output assembler ends
6759 up looking a bit weird if it turns out that there is
6760 no offset. You end up producing code that looks like:
6773 So here we provide the missing zero. */
6775 *displacement_string_end
= '0';
6778 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6779 if (gotfree_input_line
)
6780 input_line_pointer
= gotfree_input_line
;
6782 exp_seg
= expression (exp
);
6785 if (*input_line_pointer
)
6786 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6788 RESTORE_END_STRING (disp_end
+ 1);
6790 input_line_pointer
= save_input_line_pointer
;
6791 if (gotfree_input_line
)
6792 free (gotfree_input_line
);
6795 /* We do this to make sure that the section symbol is in
6796 the symbol table. We will ultimately change the relocation
6797 to be relative to the beginning of the section. */
6798 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6799 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6800 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6802 if (exp
->X_op
!= O_symbol
)
6805 if (S_IS_LOCAL (exp
->X_add_symbol
)
6806 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6807 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6808 exp
->X_op
= O_subtract
;
6809 exp
->X_op_symbol
= GOT_symbol
;
6810 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6811 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6812 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6813 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6815 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6818 else if (exp
->X_op
== O_absent
6819 || exp
->X_op
== O_illegal
6820 || exp
->X_op
== O_big
6821 || (gotfree_input_line
6822 && (exp
->X_op
== O_constant
6823 || exp
->X_op
== O_register
)))
6826 as_bad (_("missing or invalid displacement expression `%s'"),
6831 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6832 else if (exp
->X_op
!= O_constant
6833 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6834 && exp_seg
!= absolute_section
6835 && exp_seg
!= text_section
6836 && exp_seg
!= data_section
6837 && exp_seg
!= bss_section
6838 && exp_seg
!= undefined_section
6839 && !bfd_is_com_section (exp_seg
))
6841 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6846 RESTORE_END_STRING (disp_end
);
6848 /* Check if this is a displacement only operand. */
6849 bigdisp
= i
.types
[this_operand
];
6850 bigdisp
.bitfield
.disp8
= 0;
6851 bigdisp
.bitfield
.disp16
= 0;
6852 bigdisp
.bitfield
.disp32
= 0;
6853 bigdisp
.bitfield
.disp32s
= 0;
6854 bigdisp
.bitfield
.disp64
= 0;
6855 if (operand_type_all_zero (&bigdisp
))
6856 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6862 /* Make sure the memory operand we've been dealt is valid.
6863 Return 1 on success, 0 on a failure. */
6866 i386_index_check (const char *operand_string
)
6869 #if INFER_ADDR_PREFIX
6875 if (flag_code
== CODE_64BIT
)
6878 && ((i
.prefix
[ADDR_PREFIX
] == 0
6879 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6880 || (i
.prefix
[ADDR_PREFIX
]
6881 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6883 || i
.base_reg
->reg_num
!=
6884 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6886 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6887 || (i
.prefix
[ADDR_PREFIX
] == 0
6888 && i
.index_reg
->reg_num
!= RegRiz
6889 && !i
.index_reg
->reg_type
.bitfield
.reg64
6891 || (i
.prefix
[ADDR_PREFIX
]
6892 && i
.index_reg
->reg_num
!= RegEiz
6893 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6898 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6902 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6903 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6905 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6906 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6908 && i
.base_reg
->reg_num
< 6
6909 && i
.index_reg
->reg_num
>= 6
6910 && i
.log2_scale_factor
== 0))))
6917 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6919 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6920 && i
.index_reg
->reg_num
!= RegEiz
)
6921 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6927 #if INFER_ADDR_PREFIX
6928 if (i
.prefix
[ADDR_PREFIX
] == 0)
6930 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6932 /* Change the size of any displacement too. At most one of
6933 Disp16 or Disp32 is set.
6934 FIXME. There doesn't seem to be any real need for separate
6935 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6936 Removing them would probably clean up the code quite a lot. */
6937 if (flag_code
!= CODE_64BIT
6938 && (i
.types
[this_operand
].bitfield
.disp16
6939 || i
.types
[this_operand
].bitfield
.disp32
))
6940 i
.types
[this_operand
]
6941 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6946 as_bad (_("`%s' is not a valid base/index expression"),
6950 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6952 flag_code_names
[flag_code
]);
6957 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6961 i386_att_operand (char *operand_string
)
6965 char *op_string
= operand_string
;
6967 if (is_space_char (*op_string
))
6970 /* We check for an absolute prefix (differentiating,
6971 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6972 if (*op_string
== ABSOLUTE_PREFIX
)
6975 if (is_space_char (*op_string
))
6977 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6980 /* Check if operand is a register. */
6981 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6983 i386_operand_type temp
;
6985 /* Check for a segment override by searching for ':' after a
6986 segment register. */
6988 if (is_space_char (*op_string
))
6990 if (*op_string
== ':'
6991 && (r
->reg_type
.bitfield
.sreg2
6992 || r
->reg_type
.bitfield
.sreg3
))
6997 i
.seg
[i
.mem_operands
] = &es
;
7000 i
.seg
[i
.mem_operands
] = &cs
;
7003 i
.seg
[i
.mem_operands
] = &ss
;
7006 i
.seg
[i
.mem_operands
] = &ds
;
7009 i
.seg
[i
.mem_operands
] = &fs
;
7012 i
.seg
[i
.mem_operands
] = &gs
;
7016 /* Skip the ':' and whitespace. */
7018 if (is_space_char (*op_string
))
7021 if (!is_digit_char (*op_string
)
7022 && !is_identifier_char (*op_string
)
7023 && *op_string
!= '('
7024 && *op_string
!= ABSOLUTE_PREFIX
)
7026 as_bad (_("bad memory operand `%s'"), op_string
);
7029 /* Handle case of %es:*foo. */
7030 if (*op_string
== ABSOLUTE_PREFIX
)
7033 if (is_space_char (*op_string
))
7035 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7037 goto do_memory_reference
;
7041 as_bad (_("junk `%s' after register"), op_string
);
7045 temp
.bitfield
.baseindex
= 0;
7046 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7048 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7049 i
.op
[this_operand
].regs
= r
;
7052 else if (*op_string
== REGISTER_PREFIX
)
7054 as_bad (_("bad register name `%s'"), op_string
);
7057 else if (*op_string
== IMMEDIATE_PREFIX
)
7060 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7062 as_bad (_("immediate operand illegal with absolute jump"));
7065 if (!i386_immediate (op_string
))
7068 else if (is_digit_char (*op_string
)
7069 || is_identifier_char (*op_string
)
7070 || *op_string
== '(')
7072 /* This is a memory reference of some sort. */
7075 /* Start and end of displacement string expression (if found). */
7076 char *displacement_string_start
;
7077 char *displacement_string_end
;
7079 do_memory_reference
:
7080 if ((i
.mem_operands
== 1
7081 && !current_templates
->start
->opcode_modifier
.isstring
)
7082 || i
.mem_operands
== 2)
7084 as_bad (_("too many memory references for `%s'"),
7085 current_templates
->start
->name
);
7089 /* Check for base index form. We detect the base index form by
7090 looking for an ')' at the end of the operand, searching
7091 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7093 base_string
= op_string
+ strlen (op_string
);
7096 if (is_space_char (*base_string
))
7099 /* If we only have a displacement, set-up for it to be parsed later. */
7100 displacement_string_start
= op_string
;
7101 displacement_string_end
= base_string
+ 1;
7103 if (*base_string
== ')')
7106 unsigned int parens_balanced
= 1;
7107 /* We've already checked that the number of left & right ()'s are
7108 equal, so this loop will not be infinite. */
7112 if (*base_string
== ')')
7114 if (*base_string
== '(')
7117 while (parens_balanced
);
7119 temp_string
= base_string
;
7121 /* Skip past '(' and whitespace. */
7123 if (is_space_char (*base_string
))
7126 if (*base_string
== ','
7127 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7130 displacement_string_end
= temp_string
;
7132 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7136 base_string
= end_op
;
7137 if (is_space_char (*base_string
))
7141 /* There may be an index reg or scale factor here. */
7142 if (*base_string
== ',')
7145 if (is_space_char (*base_string
))
7148 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7151 base_string
= end_op
;
7152 if (is_space_char (*base_string
))
7154 if (*base_string
== ',')
7157 if (is_space_char (*base_string
))
7160 else if (*base_string
!= ')')
7162 as_bad (_("expecting `,' or `)' "
7163 "after index register in `%s'"),
7168 else if (*base_string
== REGISTER_PREFIX
)
7170 as_bad (_("bad register name `%s'"), base_string
);
7174 /* Check for scale factor. */
7175 if (*base_string
!= ')')
7177 char *end_scale
= i386_scale (base_string
);
7182 base_string
= end_scale
;
7183 if (is_space_char (*base_string
))
7185 if (*base_string
!= ')')
7187 as_bad (_("expecting `)' "
7188 "after scale factor in `%s'"),
7193 else if (!i
.index_reg
)
7195 as_bad (_("expecting index register or scale factor "
7196 "after `,'; got '%c'"),
7201 else if (*base_string
!= ')')
7203 as_bad (_("expecting `,' or `)' "
7204 "after base register in `%s'"),
7209 else if (*base_string
== REGISTER_PREFIX
)
7211 as_bad (_("bad register name `%s'"), base_string
);
7216 /* If there's an expression beginning the operand, parse it,
7217 assuming displacement_string_start and
7218 displacement_string_end are meaningful. */
7219 if (displacement_string_start
!= displacement_string_end
)
7221 if (!i386_displacement (displacement_string_start
,
7222 displacement_string_end
))
7226 /* Special case for (%dx) while doing input/output op. */
7228 && operand_type_equal (&i
.base_reg
->reg_type
,
7229 ®16_inoutportreg
)
7231 && i
.log2_scale_factor
== 0
7232 && i
.seg
[i
.mem_operands
] == 0
7233 && !operand_type_check (i
.types
[this_operand
], disp
))
7235 i
.types
[this_operand
] = inoutportreg
;
7239 if (i386_index_check (operand_string
) == 0)
7241 i
.types
[this_operand
].bitfield
.mem
= 1;
7246 /* It's not a memory operand; argh! */
7247 as_bad (_("invalid char %s beginning operand %d `%s'"),
7248 output_invalid (*op_string
),
7253 return 1; /* Normal return. */
7256 /* md_estimate_size_before_relax()
7258 Called just before relax() for rs_machine_dependent frags. The x86
7259 assembler uses these frags to handle variable size jump
7262 Any symbol that is now undefined will not become defined.
7263 Return the correct fr_subtype in the frag.
7264 Return the initial "guess for variable size of frag" to caller.
7265 The guess is actually the growth beyond the fixed part. Whatever
7266 we do to grow the fixed or variable part contributes to our
7270 md_estimate_size_before_relax (fragP
, segment
)
7274 /* We've already got fragP->fr_subtype right; all we have to do is
7275 check for un-relaxable symbols. On an ELF system, we can't relax
7276 an externally visible symbol, because it may be overridden by a
7278 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7281 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7282 || S_IS_WEAK (fragP
->fr_symbol
)))
7286 /* Symbol is undefined in this segment, or we need to keep a
7287 reloc so that weak symbols can be overridden. */
7288 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7289 enum bfd_reloc_code_real reloc_type
;
7290 unsigned char *opcode
;
7293 if (fragP
->fr_var
!= NO_RELOC
)
7294 reloc_type
= fragP
->fr_var
;
7296 reloc_type
= BFD_RELOC_16_PCREL
;
7298 reloc_type
= BFD_RELOC_32_PCREL
;
7300 old_fr_fix
= fragP
->fr_fix
;
7301 opcode
= (unsigned char *) fragP
->fr_opcode
;
7303 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7306 /* Make jmp (0xeb) a (d)word displacement jump. */
7308 fragP
->fr_fix
+= size
;
7309 fix_new (fragP
, old_fr_fix
, size
,
7311 fragP
->fr_offset
, 1,
7317 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7319 /* Negate the condition, and branch past an
7320 unconditional jump. */
7323 /* Insert an unconditional jump. */
7325 /* We added two extra opcode bytes, and have a two byte
7327 fragP
->fr_fix
+= 2 + 2;
7328 fix_new (fragP
, old_fr_fix
+ 2, 2,
7330 fragP
->fr_offset
, 1,
7337 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7342 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7344 fragP
->fr_offset
, 1,
7346 fixP
->fx_signed
= 1;
7350 /* This changes the byte-displacement jump 0x7N
7351 to the (d)word-displacement jump 0x0f,0x8N. */
7352 opcode
[1] = opcode
[0] + 0x10;
7353 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7354 /* We've added an opcode byte. */
7355 fragP
->fr_fix
+= 1 + size
;
7356 fix_new (fragP
, old_fr_fix
+ 1, size
,
7358 fragP
->fr_offset
, 1,
7363 BAD_CASE (fragP
->fr_subtype
);
7367 return fragP
->fr_fix
- old_fr_fix
;
7370 /* Guess size depending on current relax state. Initially the relax
7371 state will correspond to a short jump and we return 1, because
7372 the variable part of the frag (the branch offset) is one byte
7373 long. However, we can relax a section more than once and in that
7374 case we must either set fr_subtype back to the unrelaxed state,
7375 or return the value for the appropriate branch. */
7376 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7379 /* Called after relax() is finished.
7381 In: Address of frag.
7382 fr_type == rs_machine_dependent.
7383 fr_subtype is what the address relaxed to.
7385 Out: Any fixSs and constants are set up.
7386 Caller will turn frag into a ".space 0". */
7389 md_convert_frag (abfd
, sec
, fragP
)
7390 bfd
*abfd ATTRIBUTE_UNUSED
;
7391 segT sec ATTRIBUTE_UNUSED
;
7394 unsigned char *opcode
;
7395 unsigned char *where_to_put_displacement
= NULL
;
7396 offsetT target_address
;
7397 offsetT opcode_address
;
7398 unsigned int extension
= 0;
7399 offsetT displacement_from_opcode_start
;
7401 opcode
= (unsigned char *) fragP
->fr_opcode
;
7403 /* Address we want to reach in file space. */
7404 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7406 /* Address opcode resides at in file space. */
7407 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7409 /* Displacement from opcode start to fill into instruction. */
7410 displacement_from_opcode_start
= target_address
- opcode_address
;
7412 if ((fragP
->fr_subtype
& BIG
) == 0)
7414 /* Don't have to change opcode. */
7415 extension
= 1; /* 1 opcode + 1 displacement */
7416 where_to_put_displacement
= &opcode
[1];
7420 if (no_cond_jump_promotion
7421 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7422 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7423 _("long jump required"));
7425 switch (fragP
->fr_subtype
)
7427 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7428 extension
= 4; /* 1 opcode + 4 displacement */
7430 where_to_put_displacement
= &opcode
[1];
7433 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7434 extension
= 2; /* 1 opcode + 2 displacement */
7436 where_to_put_displacement
= &opcode
[1];
7439 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7440 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7441 extension
= 5; /* 2 opcode + 4 displacement */
7442 opcode
[1] = opcode
[0] + 0x10;
7443 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7444 where_to_put_displacement
= &opcode
[2];
7447 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7448 extension
= 3; /* 2 opcode + 2 displacement */
7449 opcode
[1] = opcode
[0] + 0x10;
7450 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7451 where_to_put_displacement
= &opcode
[2];
7454 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7459 where_to_put_displacement
= &opcode
[3];
7463 BAD_CASE (fragP
->fr_subtype
);
7468 /* If size if less then four we are sure that the operand fits,
7469 but if it's 4, then it could be that the displacement is larger
7471 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7473 && ((addressT
) (displacement_from_opcode_start
- extension
7474 + ((addressT
) 1 << 31))
7475 > (((addressT
) 2 << 31) - 1)))
7477 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7478 _("jump target out of range"));
7479 /* Make us emit 0. */
7480 displacement_from_opcode_start
= extension
;
7482 /* Now put displacement after opcode. */
7483 md_number_to_chars ((char *) where_to_put_displacement
,
7484 (valueT
) (displacement_from_opcode_start
- extension
),
7485 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7486 fragP
->fr_fix
+= extension
;
7489 /* Apply a fixup (fixS) to segment data, once it has been determined
7490 by our caller that we have all the info we need to fix it up.
7492 On the 386, immediates, displacements, and data pointers are all in
7493 the same (little-endian) format, so we don't need to care about which
7497 md_apply_fix (fixP
, valP
, seg
)
7498 /* The fix we're to put in. */
7500 /* Pointer to the value of the bits. */
7502 /* Segment fix is from. */
7503 segT seg ATTRIBUTE_UNUSED
;
7505 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7506 valueT value
= *valP
;
7508 #if !defined (TE_Mach)
7511 switch (fixP
->fx_r_type
)
7517 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7520 case BFD_RELOC_X86_64_32S
:
7521 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7524 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7527 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7532 if (fixP
->fx_addsy
!= NULL
7533 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7534 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7535 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7536 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7537 && !use_rela_relocations
)
7539 /* This is a hack. There should be a better way to handle this.
7540 This covers for the fact that bfd_install_relocation will
7541 subtract the current location (for partial_inplace, PC relative
7542 relocations); see more below. */
7546 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7549 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7554 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7557 || (symbol_section_p (fixP
->fx_addsy
)
7558 && sym_seg
!= absolute_section
))
7559 && !generic_force_reloc (fixP
))
7561 /* Yes, we add the values in twice. This is because
7562 bfd_install_relocation subtracts them out again. I think
7563 bfd_install_relocation is broken, but I don't dare change
7565 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7569 #if defined (OBJ_COFF) && defined (TE_PE)
7570 /* For some reason, the PE format does not store a
7571 section address offset for a PC relative symbol. */
7572 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7573 || S_IS_WEAK (fixP
->fx_addsy
))
7574 value
+= md_pcrel_from (fixP
);
7578 /* Fix a few things - the dynamic linker expects certain values here,
7579 and we must not disappoint it. */
7580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7581 if (IS_ELF
&& fixP
->fx_addsy
)
7582 switch (fixP
->fx_r_type
)
7584 case BFD_RELOC_386_PLT32
:
7585 case BFD_RELOC_X86_64_PLT32
:
7586 /* Make the jump instruction point to the address of the operand. At
7587 runtime we merely add the offset to the actual PLT entry. */
7591 case BFD_RELOC_386_TLS_GD
:
7592 case BFD_RELOC_386_TLS_LDM
:
7593 case BFD_RELOC_386_TLS_IE_32
:
7594 case BFD_RELOC_386_TLS_IE
:
7595 case BFD_RELOC_386_TLS_GOTIE
:
7596 case BFD_RELOC_386_TLS_GOTDESC
:
7597 case BFD_RELOC_X86_64_TLSGD
:
7598 case BFD_RELOC_X86_64_TLSLD
:
7599 case BFD_RELOC_X86_64_GOTTPOFF
:
7600 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7601 value
= 0; /* Fully resolved at runtime. No addend. */
7603 case BFD_RELOC_386_TLS_LE
:
7604 case BFD_RELOC_386_TLS_LDO_32
:
7605 case BFD_RELOC_386_TLS_LE_32
:
7606 case BFD_RELOC_X86_64_DTPOFF32
:
7607 case BFD_RELOC_X86_64_DTPOFF64
:
7608 case BFD_RELOC_X86_64_TPOFF32
:
7609 case BFD_RELOC_X86_64_TPOFF64
:
7610 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7613 case BFD_RELOC_386_TLS_DESC_CALL
:
7614 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7615 value
= 0; /* Fully resolved at runtime. No addend. */
7616 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7620 case BFD_RELOC_386_GOT32
:
7621 case BFD_RELOC_X86_64_GOT32
:
7622 value
= 0; /* Fully resolved at runtime. No addend. */
7625 case BFD_RELOC_VTABLE_INHERIT
:
7626 case BFD_RELOC_VTABLE_ENTRY
:
7633 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7635 #endif /* !defined (TE_Mach) */
7637 /* Are we finished with this relocation now? */
7638 if (fixP
->fx_addsy
== NULL
)
7640 else if (use_rela_relocations
)
7642 fixP
->fx_no_overflow
= 1;
7643 /* Remember value for tc_gen_reloc. */
7644 fixP
->fx_addnumber
= value
;
7648 md_number_to_chars (p
, value
, fixP
->fx_size
);
7652 md_atof (int type
, char *litP
, int *sizeP
)
7654 /* This outputs the LITTLENUMs in REVERSE order;
7655 in accord with the bigendian 386. */
7656 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7659 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7662 output_invalid (int c
)
7665 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7668 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7669 "(0x%x)", (unsigned char) c
);
7670 return output_invalid_buf
;
7673 /* REG_STRING starts *before* REGISTER_PREFIX. */
7675 static const reg_entry
*
7676 parse_real_register (char *reg_string
, char **end_op
)
7678 char *s
= reg_string
;
7680 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7683 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7684 if (*s
== REGISTER_PREFIX
)
7687 if (is_space_char (*s
))
7691 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7693 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7694 return (const reg_entry
*) NULL
;
7698 /* For naked regs, make sure that we are not dealing with an identifier.
7699 This prevents confusing an identifier like `eax_var' with register
7701 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7702 return (const reg_entry
*) NULL
;
7706 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7708 /* Handle floating point regs, allowing spaces in the (i) part. */
7709 if (r
== i386_regtab
/* %st is first entry of table */)
7711 if (is_space_char (*s
))
7716 if (is_space_char (*s
))
7718 if (*s
>= '0' && *s
<= '7')
7722 if (is_space_char (*s
))
7727 r
= hash_find (reg_hash
, "st(0)");
7732 /* We have "%st(" then garbage. */
7733 return (const reg_entry
*) NULL
;
7737 if (r
== NULL
|| allow_pseudo_reg
)
7740 if (operand_type_all_zero (&r
->reg_type
))
7741 return (const reg_entry
*) NULL
;
7743 if ((r
->reg_type
.bitfield
.reg32
7744 || r
->reg_type
.bitfield
.sreg3
7745 || r
->reg_type
.bitfield
.control
7746 || r
->reg_type
.bitfield
.debug
7747 || r
->reg_type
.bitfield
.test
)
7748 && !cpu_arch_flags
.bitfield
.cpui386
)
7749 return (const reg_entry
*) NULL
;
7751 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7752 return (const reg_entry
*) NULL
;
7754 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7755 return (const reg_entry
*) NULL
;
7757 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7758 return (const reg_entry
*) NULL
;
7760 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7761 if (!allow_index_reg
7762 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7763 return (const reg_entry
*) NULL
;
7765 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7766 || r
->reg_type
.bitfield
.reg64
)
7767 && (!cpu_arch_flags
.bitfield
.cpulm
7768 || !operand_type_equal (&r
->reg_type
, &control
))
7769 && flag_code
!= CODE_64BIT
)
7770 return (const reg_entry
*) NULL
;
7772 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7773 return (const reg_entry
*) NULL
;
7778 /* REG_STRING starts *before* REGISTER_PREFIX. */
7780 static const reg_entry
*
7781 parse_register (char *reg_string
, char **end_op
)
7785 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7786 r
= parse_real_register (reg_string
, end_op
);
7791 char *save
= input_line_pointer
;
7795 input_line_pointer
= reg_string
;
7796 c
= get_symbol_end ();
7797 symbolP
= symbol_find (reg_string
);
7798 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7800 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7802 know (e
->X_op
== O_register
);
7803 know (e
->X_add_number
>= 0
7804 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7805 r
= i386_regtab
+ e
->X_add_number
;
7806 *end_op
= input_line_pointer
;
7808 *input_line_pointer
= c
;
7809 input_line_pointer
= save
;
7815 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7818 char *end
= input_line_pointer
;
7821 r
= parse_register (name
, &input_line_pointer
);
7822 if (r
&& end
<= input_line_pointer
)
7824 *nextcharP
= *input_line_pointer
;
7825 *input_line_pointer
= 0;
7826 e
->X_op
= O_register
;
7827 e
->X_add_number
= r
- i386_regtab
;
7830 input_line_pointer
= end
;
7836 md_operand (expressionS
*e
)
7838 if (*input_line_pointer
== REGISTER_PREFIX
)
7841 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7845 e
->X_op
= O_register
;
7846 e
->X_add_number
= r
- i386_regtab
;
7847 input_line_pointer
= end
;
7853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7854 const char *md_shortopts
= "kVQ:sqn";
7856 const char *md_shortopts
= "qn";
7859 #define OPTION_32 (OPTION_MD_BASE + 0)
7860 #define OPTION_64 (OPTION_MD_BASE + 1)
7861 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7862 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7863 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7864 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7865 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7866 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7867 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7868 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7869 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7870 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7872 struct option md_longopts
[] =
7874 {"32", no_argument
, NULL
, OPTION_32
},
7875 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7876 {"64", no_argument
, NULL
, OPTION_64
},
7878 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7879 {"march", required_argument
, NULL
, OPTION_MARCH
},
7880 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7881 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7882 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7883 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7884 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7885 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7886 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7887 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7888 {NULL
, no_argument
, NULL
, 0}
7890 size_t md_longopts_size
= sizeof (md_longopts
);
7893 md_parse_option (int c
, char *arg
)
7901 optimize_align_code
= 0;
7908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7909 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7910 should be emitted or not. FIXME: Not implemented. */
7914 /* -V: SVR4 argument to print version ID. */
7916 print_version_id ();
7919 /* -k: Ignore for FreeBSD compatibility. */
7924 /* -s: On i386 Solaris, this tells the native assembler to use
7925 .stab instead of .stab.excl. We always use .stab anyhow. */
7928 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7931 const char **list
, **l
;
7933 list
= bfd_target_list ();
7934 for (l
= list
; *l
!= NULL
; l
++)
7935 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7936 || strcmp (*l
, "coff-x86-64") == 0
7937 || strcmp (*l
, "pe-x86-64") == 0
7938 || strcmp (*l
, "pei-x86-64") == 0)
7940 default_arch
= "x86_64";
7944 as_fatal (_("No compiled in support for x86_64"));
7951 default_arch
= "i386";
7955 #ifdef SVR4_COMMENT_CHARS
7960 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7962 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7966 i386_comment_chars
= n
;
7972 arch
= xstrdup (arg
);
7976 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7977 next
= strchr (arch
, '+');
7980 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7982 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7985 cpu_arch_name
= cpu_arch
[i
].name
;
7986 cpu_sub_arch_name
= NULL
;
7987 cpu_arch_flags
= cpu_arch
[i
].flags
;
7988 cpu_arch_isa
= cpu_arch
[i
].type
;
7989 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7990 if (!cpu_arch_tune_set
)
7992 cpu_arch_tune
= cpu_arch_isa
;
7993 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7997 else if (*cpu_arch
[i
].name
== '.'
7998 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8000 /* ISA entension. */
8001 i386_cpu_flags flags
;
8002 flags
= cpu_flags_or (cpu_arch_flags
,
8004 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8006 if (cpu_sub_arch_name
)
8008 char *name
= cpu_sub_arch_name
;
8009 cpu_sub_arch_name
= concat (name
,
8011 (const char *) NULL
);
8015 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8016 cpu_arch_flags
= flags
;
8022 if (i
>= ARRAY_SIZE (cpu_arch
))
8023 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8027 while (next
!= NULL
);
8032 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8033 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8035 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8037 cpu_arch_tune_set
= 1;
8038 cpu_arch_tune
= cpu_arch
[i
].type
;
8039 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8043 if (i
>= ARRAY_SIZE (cpu_arch
))
8044 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8047 case OPTION_MMNEMONIC
:
8048 if (strcasecmp (arg
, "att") == 0)
8050 else if (strcasecmp (arg
, "intel") == 0)
8053 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8056 case OPTION_MSYNTAX
:
8057 if (strcasecmp (arg
, "att") == 0)
8059 else if (strcasecmp (arg
, "intel") == 0)
8062 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8065 case OPTION_MINDEX_REG
:
8066 allow_index_reg
= 1;
8069 case OPTION_MNAKED_REG
:
8070 allow_naked_reg
= 1;
8073 case OPTION_MOLD_GCC
:
8077 case OPTION_MSSE2AVX
:
8081 case OPTION_MSSE_CHECK
:
8082 if (strcasecmp (arg
, "error") == 0)
8083 sse_check
= sse_check_error
;
8084 else if (strcasecmp (arg
, "warning") == 0)
8085 sse_check
= sse_check_warning
;
8086 else if (strcasecmp (arg
, "none") == 0)
8087 sse_check
= sse_check_none
;
8089 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8099 md_show_usage (stream
)
8102 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8103 fprintf (stream
, _("\
8105 -V print assembler version number\n\
8108 fprintf (stream
, _("\
8109 -n Do not optimize code alignment\n\
8110 -q quieten some warnings\n"));
8111 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8112 fprintf (stream
, _("\
8115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8116 fprintf (stream
, _("\
8117 --32/--64 generate 32bit/64bit code\n"));
8119 #ifdef SVR4_COMMENT_CHARS
8120 fprintf (stream
, _("\
8121 --divide do not treat `/' as a comment character\n"));
8123 fprintf (stream
, _("\
8124 --divide ignored\n"));
8126 fprintf (stream
, _("\
8127 -march=CPU[,+EXTENSION...]\n\
8128 generate code for CPU and EXTENSION, CPU is one of:\n\
8129 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8130 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8131 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8132 generic32, generic64\n\
8133 EXTENSION is combination of:\n\
8134 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8135 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8136 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8137 fprintf (stream
, _("\
8138 -mtune=CPU optimize for CPU, CPU is one of:\n\
8139 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8140 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8141 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8142 generic32, generic64\n"));
8143 fprintf (stream
, _("\
8144 -msse2avx encode SSE instructions with VEX prefix\n"));
8145 fprintf (stream
, _("\
8146 -msse-check=[none|error|warning]\n\
8147 check SSE instructions\n"));
8148 fprintf (stream
, _("\
8149 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8150 fprintf (stream
, _("\
8151 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8152 fprintf (stream
, _("\
8153 -mindex-reg support pseudo index registers\n"));
8154 fprintf (stream
, _("\
8155 -mnaked-reg don't require `%%' prefix for registers\n"));
8156 fprintf (stream
, _("\
8157 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8160 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8161 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8163 /* Pick the target format to use. */
8166 i386_target_format (void)
8168 if (!strcmp (default_arch
, "x86_64"))
8170 set_code_flag (CODE_64BIT
);
8171 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8173 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8174 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8175 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8176 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8177 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8178 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8179 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8180 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8181 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8182 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8184 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8186 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8187 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8188 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8189 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8190 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8191 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8192 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8193 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8194 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8195 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8198 else if (!strcmp (default_arch
, "i386"))
8200 set_code_flag (CODE_32BIT
);
8201 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8203 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8204 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8205 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8207 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8209 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8210 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8211 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8215 as_fatal (_("Unknown architecture"));
8216 switch (OUTPUT_FLAVOR
)
8219 case bfd_target_coff_flavour
:
8220 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
8223 #ifdef OBJ_MAYBE_AOUT
8224 case bfd_target_aout_flavour
:
8225 return AOUT_TARGET_FORMAT
;
8227 #ifdef OBJ_MAYBE_COFF
8228 case bfd_target_coff_flavour
:
8231 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8232 case bfd_target_elf_flavour
:
8234 if (flag_code
== CODE_64BIT
)
8237 use_rela_relocations
= 1;
8239 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8248 #endif /* OBJ_MAYBE_ more than one */
8250 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8252 i386_elf_emit_arch_note (void)
8254 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8257 asection
*seg
= now_seg
;
8258 subsegT subseg
= now_subseg
;
8259 Elf_Internal_Note i_note
;
8260 Elf_External_Note e_note
;
8261 asection
*note_secp
;
8264 /* Create the .note section. */
8265 note_secp
= subseg_new (".note", 0);
8266 bfd_set_section_flags (stdoutput
,
8268 SEC_HAS_CONTENTS
| SEC_READONLY
);
8270 /* Process the arch string. */
8271 len
= strlen (cpu_arch_name
);
8273 i_note
.namesz
= len
+ 1;
8275 i_note
.type
= NT_ARCH
;
8276 p
= frag_more (sizeof (e_note
.namesz
));
8277 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8278 p
= frag_more (sizeof (e_note
.descsz
));
8279 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8280 p
= frag_more (sizeof (e_note
.type
));
8281 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8282 p
= frag_more (len
+ 1);
8283 strcpy (p
, cpu_arch_name
);
8285 frag_align (2, 0, 0);
8287 subseg_set (seg
, subseg
);
8293 md_undefined_symbol (name
)
8296 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8297 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8298 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8299 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8303 if (symbol_find (name
))
8304 as_bad (_("GOT already in symbol table"));
8305 GOT_symbol
= symbol_new (name
, undefined_section
,
8306 (valueT
) 0, &zero_address_frag
);
8313 /* Round up a section size to the appropriate boundary. */
8316 md_section_align (segment
, size
)
8317 segT segment ATTRIBUTE_UNUSED
;
8320 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8321 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8323 /* For a.out, force the section size to be aligned. If we don't do
8324 this, BFD will align it for us, but it will not write out the
8325 final bytes of the section. This may be a bug in BFD, but it is
8326 easier to fix it here since that is how the other a.out targets
8330 align
= bfd_get_section_alignment (stdoutput
, segment
);
8331 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8338 /* On the i386, PC-relative offsets are relative to the start of the
8339 next instruction. That is, the address of the offset, plus its
8340 size, since the offset is always the last part of the insn. */
8343 md_pcrel_from (fixS
*fixP
)
8345 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8351 s_bss (int ignore ATTRIBUTE_UNUSED
)
8355 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8357 obj_elf_section_change_hook ();
8359 temp
= get_absolute_expression ();
8360 subseg_set (bss_section
, (subsegT
) temp
);
8361 demand_empty_rest_of_line ();
8367 i386_validate_fix (fixS
*fixp
)
8369 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8371 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8375 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8380 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8382 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8389 tc_gen_reloc (section
, fixp
)
8390 asection
*section ATTRIBUTE_UNUSED
;
8394 bfd_reloc_code_real_type code
;
8396 switch (fixp
->fx_r_type
)
8398 case BFD_RELOC_X86_64_PLT32
:
8399 case BFD_RELOC_X86_64_GOT32
:
8400 case BFD_RELOC_X86_64_GOTPCREL
:
8401 case BFD_RELOC_386_PLT32
:
8402 case BFD_RELOC_386_GOT32
:
8403 case BFD_RELOC_386_GOTOFF
:
8404 case BFD_RELOC_386_GOTPC
:
8405 case BFD_RELOC_386_TLS_GD
:
8406 case BFD_RELOC_386_TLS_LDM
:
8407 case BFD_RELOC_386_TLS_LDO_32
:
8408 case BFD_RELOC_386_TLS_IE_32
:
8409 case BFD_RELOC_386_TLS_IE
:
8410 case BFD_RELOC_386_TLS_GOTIE
:
8411 case BFD_RELOC_386_TLS_LE_32
:
8412 case BFD_RELOC_386_TLS_LE
:
8413 case BFD_RELOC_386_TLS_GOTDESC
:
8414 case BFD_RELOC_386_TLS_DESC_CALL
:
8415 case BFD_RELOC_X86_64_TLSGD
:
8416 case BFD_RELOC_X86_64_TLSLD
:
8417 case BFD_RELOC_X86_64_DTPOFF32
:
8418 case BFD_RELOC_X86_64_DTPOFF64
:
8419 case BFD_RELOC_X86_64_GOTTPOFF
:
8420 case BFD_RELOC_X86_64_TPOFF32
:
8421 case BFD_RELOC_X86_64_TPOFF64
:
8422 case BFD_RELOC_X86_64_GOTOFF64
:
8423 case BFD_RELOC_X86_64_GOTPC32
:
8424 case BFD_RELOC_X86_64_GOT64
:
8425 case BFD_RELOC_X86_64_GOTPCREL64
:
8426 case BFD_RELOC_X86_64_GOTPC64
:
8427 case BFD_RELOC_X86_64_GOTPLT64
:
8428 case BFD_RELOC_X86_64_PLTOFF64
:
8429 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8430 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8432 case BFD_RELOC_VTABLE_ENTRY
:
8433 case BFD_RELOC_VTABLE_INHERIT
:
8435 case BFD_RELOC_32_SECREL
:
8437 code
= fixp
->fx_r_type
;
8439 case BFD_RELOC_X86_64_32S
:
8440 if (!fixp
->fx_pcrel
)
8442 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8443 code
= fixp
->fx_r_type
;
8449 switch (fixp
->fx_size
)
8452 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8453 _("can not do %d byte pc-relative relocation"),
8455 code
= BFD_RELOC_32_PCREL
;
8457 case 1: code
= BFD_RELOC_8_PCREL
; break;
8458 case 2: code
= BFD_RELOC_16_PCREL
; break;
8459 case 4: code
= BFD_RELOC_32_PCREL
; break;
8461 case 8: code
= BFD_RELOC_64_PCREL
; break;
8467 switch (fixp
->fx_size
)
8470 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8471 _("can not do %d byte relocation"),
8473 code
= BFD_RELOC_32
;
8475 case 1: code
= BFD_RELOC_8
; break;
8476 case 2: code
= BFD_RELOC_16
; break;
8477 case 4: code
= BFD_RELOC_32
; break;
8479 case 8: code
= BFD_RELOC_64
; break;
8486 if ((code
== BFD_RELOC_32
8487 || code
== BFD_RELOC_32_PCREL
8488 || code
== BFD_RELOC_X86_64_32S
)
8490 && fixp
->fx_addsy
== GOT_symbol
)
8493 code
= BFD_RELOC_386_GOTPC
;
8495 code
= BFD_RELOC_X86_64_GOTPC32
;
8497 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8499 && fixp
->fx_addsy
== GOT_symbol
)
8501 code
= BFD_RELOC_X86_64_GOTPC64
;
8504 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8505 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8506 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8508 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8510 if (!use_rela_relocations
)
8512 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8513 vtable entry to be used in the relocation's section offset. */
8514 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8515 rel
->address
= fixp
->fx_offset
;
8519 /* Use the rela in 64bit mode. */
8522 if (!fixp
->fx_pcrel
)
8523 rel
->addend
= fixp
->fx_offset
;
8527 case BFD_RELOC_X86_64_PLT32
:
8528 case BFD_RELOC_X86_64_GOT32
:
8529 case BFD_RELOC_X86_64_GOTPCREL
:
8530 case BFD_RELOC_X86_64_TLSGD
:
8531 case BFD_RELOC_X86_64_TLSLD
:
8532 case BFD_RELOC_X86_64_GOTTPOFF
:
8533 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8534 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8535 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8538 rel
->addend
= (section
->vma
8540 + fixp
->fx_addnumber
8541 + md_pcrel_from (fixp
));
8546 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8547 if (rel
->howto
== NULL
)
8549 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8550 _("cannot represent relocation type %s"),
8551 bfd_get_reloc_code_name (code
));
8552 /* Set howto to a garbage value so that we can keep going. */
8553 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8554 assert (rel
->howto
!= NULL
);
8561 /* Parse operands using Intel syntax. This implements a recursive descent
8562 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8565 FIXME: We do not recognize the full operand grammar defined in the MASM
8566 documentation. In particular, all the structure/union and
8567 high-level macro operands are missing.
8569 Uppercase words are terminals, lower case words are non-terminals.
8570 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8571 bars '|' denote choices. Most grammar productions are implemented in
8572 functions called 'intel_<production>'.
8574 Initial production is 'expr'.
8580 binOp & | AND | \| | OR | ^ | XOR
8582 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8584 constant digits [[ radixOverride ]]
8586 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8624 => expr expr cmpOp e04
8627 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8628 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8630 hexdigit a | b | c | d | e | f
8631 | A | B | C | D | E | F
8637 mulOp * | / | % | MOD | << | SHL | >> | SHR
8641 register specialRegister
8645 segmentRegister CS | DS | ES | FS | GS | SS
8647 specialRegister CR0 | CR2 | CR3 | CR4
8648 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8649 | TR3 | TR4 | TR5 | TR6 | TR7
8651 We simplify the grammar in obvious places (e.g., register parsing is
8652 done by calling parse_register) and eliminate immediate left recursion
8653 to implement a recursive-descent parser.
8657 expr' cmpOp e04 expr'
8709 /* Parsing structure for the intel syntax parser. Used to implement the
8710 semantic actions for the operand grammar. */
8711 struct intel_parser_s
8713 char *op_string
; /* The string being parsed. */
8714 int got_a_float
; /* Whether the operand is a float. */
8715 int op_modifier
; /* Operand modifier. */
8716 int is_mem
; /* 1 if operand is memory reference. */
8717 int in_offset
; /* >=1 if parsing operand of offset. */
8718 int in_bracket
; /* >=1 if parsing operand in brackets. */
8719 const reg_entry
*reg
; /* Last register reference found. */
8720 char *disp
; /* Displacement string being built. */
8721 char *next_operand
; /* Resume point when splitting operands. */
8724 static struct intel_parser_s intel_parser
;
8726 /* Token structure for parsing intel syntax. */
8729 int code
; /* Token code. */
8730 const reg_entry
*reg
; /* Register entry for register tokens. */
8731 char *str
; /* String representation. */
8734 static struct intel_token cur_token
, prev_token
;
8736 /* Token codes for the intel parser. Since T_SHORT is already used
8737 by COFF, undefine it first to prevent a warning. */
8755 #define T_YMMWORD 16
8757 /* Prototypes for intel parser functions. */
8758 static int intel_match_token (int);
8759 static void intel_putback_token (void);
8760 static void intel_get_token (void);
8761 static int intel_expr (void);
8762 static int intel_e04 (void);
8763 static int intel_e05 (void);
8764 static int intel_e06 (void);
8765 static int intel_e09 (void);
8766 static int intel_e10 (void);
8767 static int intel_e11 (void);
8770 i386_intel_operand (char *operand_string
, int got_a_float
)
8775 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8776 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8780 /* Initialize token holders. */
8781 cur_token
.code
= prev_token
.code
= T_NIL
;
8782 cur_token
.reg
= prev_token
.reg
= NULL
;
8783 cur_token
.str
= prev_token
.str
= NULL
;
8785 /* Initialize parser structure. */
8786 intel_parser
.got_a_float
= got_a_float
;
8787 intel_parser
.op_modifier
= 0;
8788 intel_parser
.is_mem
= 0;
8789 intel_parser
.in_offset
= 0;
8790 intel_parser
.in_bracket
= 0;
8791 intel_parser
.reg
= NULL
;
8792 intel_parser
.disp
[0] = '\0';
8793 intel_parser
.next_operand
= NULL
;
8795 /* Read the first token and start the parser. */
8797 ret
= intel_expr ();
8802 if (cur_token
.code
!= T_NIL
)
8804 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8805 current_templates
->start
->name
, cur_token
.str
);
8808 /* If we found a memory reference, hand it over to i386_displacement
8809 to fill in the rest of the operand fields. */
8810 else if (intel_parser
.is_mem
)
8812 if ((i
.mem_operands
== 1
8813 && !current_templates
->start
->opcode_modifier
.isstring
)
8814 || i
.mem_operands
== 2)
8816 as_bad (_("too many memory references for '%s'"),
8817 current_templates
->start
->name
);
8822 char *s
= intel_parser
.disp
;
8823 i
.types
[this_operand
].bitfield
.mem
= 1;
8826 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8827 /* See the comments in intel_bracket_expr. */
8828 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8830 /* Add the displacement expression. */
8832 ret
= i386_displacement (s
, s
+ strlen (s
));
8835 /* Swap base and index in 16-bit memory operands like
8836 [si+bx]. Since i386_index_check is also used in AT&T
8837 mode we have to do that here. */
8840 && i
.base_reg
->reg_type
.bitfield
.reg16
8841 && i
.index_reg
->reg_type
.bitfield
.reg16
8842 && i
.base_reg
->reg_num
>= 6
8843 && i
.index_reg
->reg_num
< 6)
8845 const reg_entry
*base
= i
.index_reg
;
8847 i
.index_reg
= i
.base_reg
;
8850 ret
= i386_index_check (operand_string
);
8855 /* Constant and OFFSET expressions are handled by i386_immediate. */
8856 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8857 || intel_parser
.reg
== NULL
)
8859 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8861 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8862 as_warn (_("Segment override ignored"));
8863 i
.seg
[i
.mem_operands
] = NULL
;
8865 ret
= i386_immediate (intel_parser
.disp
);
8868 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8870 if (!ret
|| !intel_parser
.next_operand
)
8872 intel_parser
.op_string
= intel_parser
.next_operand
;
8873 this_operand
= i
.operands
++;
8874 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8878 free (intel_parser
.disp
);
8883 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8887 expr' cmpOp e04 expr'
8892 /* XXX Implement the comparison operators. */
8893 return intel_e04 ();
8910 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8911 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
8913 if (cur_token
.code
== '+')
8915 else if (cur_token
.code
== '-')
8916 nregs
= NUM_ADDRESS_REGS
;
8920 strcat (intel_parser
.disp
, cur_token
.str
);
8921 intel_match_token (cur_token
.code
);
8932 int nregs
= ~NUM_ADDRESS_REGS
;
8939 if (cur_token
.code
== '&'
8940 || cur_token
.code
== '|'
8941 || cur_token
.code
== '^')
8945 str
[0] = cur_token
.code
;
8947 strcat (intel_parser
.disp
, str
);
8952 intel_match_token (cur_token
.code
);
8957 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8958 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
8969 int nregs
= ~NUM_ADDRESS_REGS
;
8976 if (cur_token
.code
== '*'
8977 || cur_token
.code
== '/'
8978 || cur_token
.code
== '%')
8982 str
[0] = cur_token
.code
;
8984 strcat (intel_parser
.disp
, str
);
8986 else if (cur_token
.code
== T_SHL
)
8987 strcat (intel_parser
.disp
, "<<");
8988 else if (cur_token
.code
== T_SHR
)
8989 strcat (intel_parser
.disp
, ">>");
8993 intel_match_token (cur_token
.code
);
8998 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8999 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9017 int nregs
= ~NUM_ADDRESS_REGS
;
9022 /* Don't consume constants here. */
9023 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9025 /* Need to look one token ahead - if the next token
9026 is a constant, the current token is its sign. */
9029 intel_match_token (cur_token
.code
);
9030 next_code
= cur_token
.code
;
9031 intel_putback_token ();
9032 if (next_code
== T_CONST
)
9036 /* e09 OFFSET e09 */
9037 if (cur_token
.code
== T_OFFSET
)
9040 ++intel_parser
.in_offset
;
9044 else if (cur_token
.code
== T_SHORT
)
9045 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9048 else if (cur_token
.code
== '+')
9049 strcat (intel_parser
.disp
, "+");
9054 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9060 str
[0] = cur_token
.code
;
9062 strcat (intel_parser
.disp
, str
);
9069 intel_match_token (cur_token
.code
);
9077 /* e09' PTR e10 e09' */
9078 if (cur_token
.code
== T_PTR
)
9082 if (prev_token
.code
== T_BYTE
)
9084 suffix
= BYTE_MNEM_SUFFIX
;
9085 i
.types
[this_operand
].bitfield
.byte
= 1;
9088 else if (prev_token
.code
== T_WORD
)
9090 if ((current_templates
->start
->name
[0] == 'l'
9091 && current_templates
->start
->name
[2] == 's'
9092 && current_templates
->start
->name
[3] == 0)
9093 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9094 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9095 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9096 suffix
= SHORT_MNEM_SUFFIX
;
9098 suffix
= WORD_MNEM_SUFFIX
;
9099 i
.types
[this_operand
].bitfield
.word
= 1;
9102 else if (prev_token
.code
== T_DWORD
)
9104 if ((current_templates
->start
->name
[0] == 'l'
9105 && current_templates
->start
->name
[2] == 's'
9106 && current_templates
->start
->name
[3] == 0)
9107 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9108 suffix
= WORD_MNEM_SUFFIX
;
9109 else if (flag_code
== CODE_16BIT
9110 && (current_templates
->start
->opcode_modifier
.jump
9111 || current_templates
->start
->opcode_modifier
.jumpdword
))
9112 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9113 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9114 suffix
= SHORT_MNEM_SUFFIX
;
9116 suffix
= LONG_MNEM_SUFFIX
;
9117 i
.types
[this_operand
].bitfield
.dword
= 1;
9120 else if (prev_token
.code
== T_FWORD
)
9122 if (current_templates
->start
->name
[0] == 'l'
9123 && current_templates
->start
->name
[2] == 's'
9124 && current_templates
->start
->name
[3] == 0)
9125 suffix
= LONG_MNEM_SUFFIX
;
9126 else if (!intel_parser
.got_a_float
)
9128 if (flag_code
== CODE_16BIT
)
9129 add_prefix (DATA_PREFIX_OPCODE
);
9130 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9133 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9134 i
.types
[this_operand
].bitfield
.fword
= 1;
9137 else if (prev_token
.code
== T_QWORD
)
9139 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9140 || intel_parser
.got_a_float
== 1) /* "f..." */
9141 suffix
= LONG_MNEM_SUFFIX
;
9143 suffix
= QWORD_MNEM_SUFFIX
;
9144 i
.types
[this_operand
].bitfield
.qword
= 1;
9147 else if (prev_token
.code
== T_TBYTE
)
9149 if (intel_parser
.got_a_float
== 1)
9150 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9152 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9155 else if (prev_token
.code
== T_XMMWORD
)
9157 suffix
= XMMWORD_MNEM_SUFFIX
;
9158 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9161 else if (prev_token
.code
== T_YMMWORD
)
9163 suffix
= YMMWORD_MNEM_SUFFIX
;
9164 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9169 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9173 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9175 /* Operands for jump/call using 'ptr' notation denote absolute
9177 if (current_templates
->start
->opcode_modifier
.jump
9178 || current_templates
->start
->opcode_modifier
.jumpdword
)
9179 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9181 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9185 else if (i
.suffix
!= suffix
)
9187 as_bad (_("Conflicting operand modifiers"));
9193 /* e09' : e10 e09' */
9194 else if (cur_token
.code
== ':')
9196 if (prev_token
.code
!= T_REG
)
9198 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9199 segment/group identifier (which we don't have), using comma
9200 as the operand separator there is even less consistent, since
9201 there all branches only have a single operand. */
9202 if (this_operand
!= 0
9203 || intel_parser
.in_offset
9204 || intel_parser
.in_bracket
9205 || (!current_templates
->start
->opcode_modifier
.jump
9206 && !current_templates
->start
->opcode_modifier
.jumpdword
9207 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9208 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9209 return intel_match_token (T_NIL
);
9210 /* Remember the start of the 2nd operand and terminate 1st
9212 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9213 another expression), but it gets at least the simplest case
9214 (a plain number or symbol on the left side) right. */
9215 intel_parser
.next_operand
= intel_parser
.op_string
;
9216 *--intel_parser
.op_string
= '\0';
9217 return intel_match_token (':');
9225 intel_match_token (cur_token
.code
);
9231 --intel_parser
.in_offset
;
9234 if (NUM_ADDRESS_REGS
> nregs
)
9236 as_bad (_("Invalid operand to `OFFSET'"));
9239 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9242 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9243 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9248 intel_bracket_expr (void)
9250 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9251 const char *start
= intel_parser
.op_string
;
9254 if (i
.op
[this_operand
].regs
)
9255 return intel_match_token (T_NIL
);
9257 intel_match_token ('[');
9259 /* Mark as a memory operand only if it's not already known to be an
9260 offset expression. If it's an offset expression, we need to keep
9262 if (!intel_parser
.in_offset
)
9264 ++intel_parser
.in_bracket
;
9266 /* Operands for jump/call inside brackets denote absolute addresses. */
9267 if (current_templates
->start
->opcode_modifier
.jump
9268 || current_templates
->start
->opcode_modifier
.jumpdword
)
9269 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9271 /* Unfortunately gas always diverged from MASM in a respect that can't
9272 be easily fixed without risking to break code sequences likely to be
9273 encountered (the testsuite even check for this): MASM doesn't consider
9274 an expression inside brackets unconditionally as a memory reference.
9275 When that is e.g. a constant, an offset expression, or the sum of the
9276 two, this is still taken as a constant load. gas, however, always
9277 treated these as memory references. As a compromise, we'll try to make
9278 offset expressions inside brackets work the MASM way (since that's
9279 less likely to be found in real world code), but make constants alone
9280 continue to work the traditional gas way. In either case, issue a
9282 intel_parser
.op_modifier
&= ~was_offset
;
9285 strcat (intel_parser
.disp
, "[");
9287 /* Add a '+' to the displacement string if necessary. */
9288 if (*intel_parser
.disp
!= '\0'
9289 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9290 strcat (intel_parser
.disp
, "+");
9293 && (len
= intel_parser
.op_string
- start
- 1,
9294 intel_match_token (']')))
9296 /* Preserve brackets when the operand is an offset expression. */
9297 if (intel_parser
.in_offset
)
9298 strcat (intel_parser
.disp
, "]");
9301 --intel_parser
.in_bracket
;
9302 if (i
.base_reg
|| i
.index_reg
)
9303 intel_parser
.is_mem
= 1;
9304 if (!intel_parser
.is_mem
)
9306 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9307 /* Defer the warning until all of the operand was parsed. */
9308 intel_parser
.is_mem
= -1;
9309 else if (!quiet_warnings
)
9310 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9311 len
, start
, len
, start
);
9314 intel_parser
.op_modifier
|= was_offset
;
9331 while (cur_token
.code
== '[')
9333 if (!intel_bracket_expr ())
9359 switch (cur_token
.code
)
9363 intel_match_token ('(');
9364 strcat (intel_parser
.disp
, "(");
9366 if (intel_expr () && intel_match_token (')'))
9368 strcat (intel_parser
.disp
, ")");
9375 return intel_bracket_expr ();
9380 strcat (intel_parser
.disp
, cur_token
.str
);
9381 intel_match_token (cur_token
.code
);
9383 /* Mark as a memory operand only if it's not already known to be an
9384 offset expression. */
9385 if (!intel_parser
.in_offset
)
9386 intel_parser
.is_mem
= 1;
9393 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9395 intel_match_token (T_REG
);
9397 /* Check for segment change. */
9398 if (cur_token
.code
== ':')
9400 if (!reg
->reg_type
.bitfield
.sreg2
9401 && !reg
->reg_type
.bitfield
.sreg3
)
9403 as_bad (_("`%s' is not a valid segment register"),
9407 else if (i
.mem_operands
>= 2)
9408 as_warn (_("Segment override ignored"));
9409 else if (i
.seg
[i
.mem_operands
])
9410 as_warn (_("Extra segment override ignored"));
9413 if (!intel_parser
.in_offset
)
9414 intel_parser
.is_mem
= 1;
9415 switch (reg
->reg_num
)
9418 i
.seg
[i
.mem_operands
] = &es
;
9421 i
.seg
[i
.mem_operands
] = &cs
;
9424 i
.seg
[i
.mem_operands
] = &ss
;
9427 i
.seg
[i
.mem_operands
] = &ds
;
9430 i
.seg
[i
.mem_operands
] = &fs
;
9433 i
.seg
[i
.mem_operands
] = &gs
;
9439 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9441 as_bad (_("cannot use `FLAT' here"));
9445 /* Not a segment register. Check for register scaling. */
9446 else if (cur_token
.code
== '*')
9448 if (!intel_parser
.in_bracket
)
9450 as_bad (_("Register scaling only allowed in memory operands"));
9454 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9455 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9456 else if (i
.index_reg
)
9457 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9459 /* What follows must be a valid scale. */
9460 intel_match_token ('*');
9462 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9464 /* Set the scale after setting the register (otherwise,
9465 i386_scale will complain) */
9466 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9468 char *str
, sign
= cur_token
.code
;
9469 intel_match_token (cur_token
.code
);
9470 if (cur_token
.code
!= T_CONST
)
9472 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9476 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9477 strcpy (str
+ 1, cur_token
.str
);
9479 if (!i386_scale (str
))
9483 else if (!i386_scale (cur_token
.str
))
9485 intel_match_token (cur_token
.code
);
9488 /* No scaling. If this is a memory operand, the register is either a
9489 base register (first occurrence) or an index register (second
9491 else if (intel_parser
.in_bracket
)
9496 else if (!i
.index_reg
)
9500 as_bad (_("Too many register references in memory operand"));
9504 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9507 /* It's neither base nor index. */
9508 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9510 i386_operand_type temp
= reg
->reg_type
;
9511 temp
.bitfield
.baseindex
= 0;
9512 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9514 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9515 i
.op
[this_operand
].regs
= reg
;
9520 as_bad (_("Invalid use of register"));
9524 /* Since registers are not part of the displacement string (except
9525 when we're parsing offset operands), we may need to remove any
9526 preceding '+' from the displacement string. */
9527 if (*intel_parser
.disp
!= '\0'
9528 && !intel_parser
.in_offset
)
9530 char *s
= intel_parser
.disp
;
9531 s
+= strlen (s
) - 1;
9556 intel_match_token (cur_token
.code
);
9558 if (cur_token
.code
== T_PTR
)
9561 /* It must have been an identifier. */
9562 intel_putback_token ();
9563 cur_token
.code
= T_ID
;
9569 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9573 /* The identifier represents a memory reference only if it's not
9574 preceded by an offset modifier and if it's not an equate. */
9575 symbolP
= symbol_find(cur_token
.str
);
9576 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9577 intel_parser
.is_mem
= 1;
9585 char *save_str
, sign
= 0;
9587 /* Allow constants that start with `+' or `-'. */
9588 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9590 sign
= cur_token
.code
;
9591 intel_match_token (cur_token
.code
);
9592 if (cur_token
.code
!= T_CONST
)
9594 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9600 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9601 strcpy (save_str
+ !!sign
, cur_token
.str
);
9605 /* Get the next token to check for register scaling. */
9606 intel_match_token (cur_token
.code
);
9608 /* Check if this constant is a scaling factor for an
9610 if (cur_token
.code
== '*')
9612 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9614 const reg_entry
*reg
= cur_token
.reg
;
9616 if (!intel_parser
.in_bracket
)
9618 as_bad (_("Register scaling only allowed "
9619 "in memory operands"));
9623 /* Disallow things like [1*si].
9624 sp and esp are invalid as index. */
9625 if (reg
->reg_type
.bitfield
.reg16
)
9626 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9627 else if (i
.index_reg
)
9628 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9630 /* The constant is followed by `* reg', so it must be
9633 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9635 /* Set the scale after setting the register (otherwise,
9636 i386_scale will complain) */
9637 if (!i386_scale (save_str
))
9639 intel_match_token (T_REG
);
9641 /* Since registers are not part of the displacement
9642 string, we may need to remove any preceding '+' from
9643 the displacement string. */
9644 if (*intel_parser
.disp
!= '\0')
9646 char *s
= intel_parser
.disp
;
9647 s
+= strlen (s
) - 1;
9657 /* The constant was not used for register scaling. Since we have
9658 already consumed the token following `*' we now need to put it
9659 back in the stream. */
9660 intel_putback_token ();
9663 /* Add the constant to the displacement string. */
9664 strcat (intel_parser
.disp
, save_str
);
9671 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9675 /* Match the given token against cur_token. If they match, read the next
9676 token from the operand string. */
9678 intel_match_token (int code
)
9680 if (cur_token
.code
== code
)
9687 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9692 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9694 intel_get_token (void)
9697 const reg_entry
*reg
;
9698 struct intel_token new_token
;
9700 new_token
.code
= T_NIL
;
9701 new_token
.reg
= NULL
;
9702 new_token
.str
= NULL
;
9704 /* Free the memory allocated to the previous token and move
9705 cur_token to prev_token. */
9707 free (prev_token
.str
);
9709 prev_token
= cur_token
;
9711 /* Skip whitespace. */
9712 while (is_space_char (*intel_parser
.op_string
))
9713 intel_parser
.op_string
++;
9715 /* Return an empty token if we find nothing else on the line. */
9716 if (*intel_parser
.op_string
== '\0')
9718 cur_token
= new_token
;
9722 /* The new token cannot be larger than the remainder of the operand
9724 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9725 new_token
.str
[0] = '\0';
9727 if (strchr ("0123456789", *intel_parser
.op_string
))
9729 char *p
= new_token
.str
;
9730 char *q
= intel_parser
.op_string
;
9731 new_token
.code
= T_CONST
;
9733 /* Allow any kind of identifier char to encompass floating point and
9734 hexadecimal numbers. */
9735 while (is_identifier_char (*q
))
9739 /* Recognize special symbol names [0-9][bf]. */
9740 if (strlen (intel_parser
.op_string
) == 2
9741 && (intel_parser
.op_string
[1] == 'b'
9742 || intel_parser
.op_string
[1] == 'f'))
9743 new_token
.code
= T_ID
;
9746 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9748 size_t len
= end_op
- intel_parser
.op_string
;
9750 new_token
.code
= T_REG
;
9751 new_token
.reg
= reg
;
9753 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9754 new_token
.str
[len
] = '\0';
9757 else if (is_identifier_char (*intel_parser
.op_string
))
9759 char *p
= new_token
.str
;
9760 char *q
= intel_parser
.op_string
;
9762 /* A '.' or '$' followed by an identifier char is an identifier.
9763 Otherwise, it's operator '.' followed by an expression. */
9764 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9766 new_token
.code
= '.';
9767 new_token
.str
[0] = '.';
9768 new_token
.str
[1] = '\0';
9772 while (is_identifier_char (*q
) || *q
== '@')
9776 if (strcasecmp (new_token
.str
, "NOT") == 0)
9777 new_token
.code
= '~';
9779 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9780 new_token
.code
= '%';
9782 else if (strcasecmp (new_token
.str
, "AND") == 0)
9783 new_token
.code
= '&';
9785 else if (strcasecmp (new_token
.str
, "OR") == 0)
9786 new_token
.code
= '|';
9788 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9789 new_token
.code
= '^';
9791 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9792 new_token
.code
= T_SHL
;
9794 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9795 new_token
.code
= T_SHR
;
9797 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9798 new_token
.code
= T_BYTE
;
9800 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9801 new_token
.code
= T_WORD
;
9803 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9804 new_token
.code
= T_DWORD
;
9806 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9807 new_token
.code
= T_FWORD
;
9809 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9810 new_token
.code
= T_QWORD
;
9812 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9813 /* XXX remove (gcc still uses it) */
9814 || strcasecmp (new_token
.str
, "XWORD") == 0)
9815 new_token
.code
= T_TBYTE
;
9817 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9818 || strcasecmp (new_token
.str
, "OWORD") == 0)
9819 new_token
.code
= T_XMMWORD
;
9821 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9822 new_token
.code
= T_YMMWORD
;
9824 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9825 new_token
.code
= T_PTR
;
9827 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9828 new_token
.code
= T_SHORT
;
9830 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9832 new_token
.code
= T_OFFSET
;
9834 /* ??? This is not mentioned in the MASM grammar but gcc
9835 makes use of it with -mintel-syntax. OFFSET may be
9836 followed by FLAT: */
9837 if (strncasecmp (q
, " FLAT:", 6) == 0)
9838 strcat (new_token
.str
, " FLAT:");
9842 new_token
.code
= T_ID
;
9846 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9848 new_token
.code
= *intel_parser
.op_string
;
9849 new_token
.str
[0] = *intel_parser
.op_string
;
9850 new_token
.str
[1] = '\0';
9853 else if (strchr ("<>", *intel_parser
.op_string
)
9854 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9856 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9857 new_token
.str
[0] = *intel_parser
.op_string
;
9858 new_token
.str
[1] = *intel_parser
.op_string
;
9859 new_token
.str
[2] = '\0';
9863 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9865 intel_parser
.op_string
+= strlen (new_token
.str
);
9866 cur_token
= new_token
;
9869 /* Put cur_token back into the token stream and make cur_token point to
9872 intel_putback_token (void)
9874 if (cur_token
.code
!= T_NIL
)
9876 intel_parser
.op_string
-= strlen (cur_token
.str
);
9877 free (cur_token
.str
);
9879 cur_token
= prev_token
;
9881 /* Forget prev_token. */
9882 prev_token
.code
= T_NIL
;
9883 prev_token
.reg
= NULL
;
9884 prev_token
.str
= NULL
;
9888 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9890 int saved_naked_reg
;
9891 char saved_register_dot
;
9893 saved_naked_reg
= allow_naked_reg
;
9894 allow_naked_reg
= 1;
9895 saved_register_dot
= register_chars
['.'];
9896 register_chars
['.'] = '.';
9897 allow_pseudo_reg
= 1;
9898 expression_and_evaluate (exp
);
9899 allow_pseudo_reg
= 0;
9900 register_chars
['.'] = saved_register_dot
;
9901 allow_naked_reg
= saved_naked_reg
;
9903 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9905 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9907 exp
->X_op
= O_constant
;
9908 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9909 .dw2_regnum
[flag_code
>> 1];
9912 exp
->X_op
= O_illegal
;
9917 tc_x86_frame_initial_instructions (void)
9919 static unsigned int sp_regno
[2];
9921 if (!sp_regno
[flag_code
>> 1])
9923 char *saved_input
= input_line_pointer
;
9924 char sp
[][4] = {"esp", "rsp"};
9927 input_line_pointer
= sp
[flag_code
>> 1];
9928 tc_x86_parse_to_dw2regnum (&exp
);
9929 assert (exp
.X_op
== O_constant
);
9930 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9931 input_line_pointer
= saved_input
;
9934 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9935 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9939 i386_elf_section_type (const char *str
, size_t len
)
9941 if (flag_code
== CODE_64BIT
9942 && len
== sizeof ("unwind") - 1
9943 && strncmp (str
, "unwind", 6) == 0)
9944 return SHT_X86_64_UNWIND
;
9951 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9955 expr
.X_op
= O_secrel
;
9956 expr
.X_add_symbol
= symbol
;
9957 expr
.X_add_number
= 0;
9958 emit_expr (&expr
, size
);
9962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9963 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9966 x86_64_section_letter (int letter
, char **ptr_msg
)
9968 if (flag_code
== CODE_64BIT
)
9971 return SHF_X86_64_LARGE
;
9973 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9976 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9981 x86_64_section_word (char *str
, size_t len
)
9983 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9984 return SHF_X86_64_LARGE
;
9990 handle_large_common (int small ATTRIBUTE_UNUSED
)
9992 if (flag_code
!= CODE_64BIT
)
9994 s_comm_internal (0, elf_common_parse
);
9995 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9999 static segT lbss_section
;
10000 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10001 asection
*saved_bss_section
= bss_section
;
10003 if (lbss_section
== NULL
)
10005 flagword applicable
;
10006 segT seg
= now_seg
;
10007 subsegT subseg
= now_subseg
;
10009 /* The .lbss section is for local .largecomm symbols. */
10010 lbss_section
= subseg_new (".lbss", 0);
10011 applicable
= bfd_applicable_section_flags (stdoutput
);
10012 bfd_set_section_flags (stdoutput
, lbss_section
,
10013 applicable
& SEC_ALLOC
);
10014 seg_info (lbss_section
)->bss
= 1;
10016 subseg_set (seg
, subseg
);
10019 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10020 bss_section
= lbss_section
;
10022 s_comm_internal (0, elf_common_parse
);
10024 elf_com_section_ptr
= saved_com_section_ptr
;
10025 bss_section
= saved_bss_section
;
10028 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */