1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
962 CPU_AVX512IFMA_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512VBMI_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
966 CPU_AVX512_4FMAPS_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
968 CPU_AVX512_4VNNIW_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
970 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
972 CPU_CLZERO_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
974 CPU_MWAITX_FLAGS
, 0 },
975 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
976 CPU_OSPKE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
978 CPU_RDPID_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
980 CPU_PTWRITE_FLAGS
, 0 },
983 static const noarch_entry cpu_noarch
[] =
985 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
986 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
987 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
988 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
989 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
990 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
991 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
992 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
993 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
994 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
995 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
996 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
997 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
998 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
999 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1002 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1003 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1004 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1005 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1006 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1007 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1008 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1009 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1010 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1014 /* Like s_lcomm_internal in gas/read.c but the alignment string
1015 is allowed to be optional. */
1018 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1025 && *input_line_pointer
== ',')
1027 align
= parse_align (needs_align
- 1);
1029 if (align
== (addressT
) -1)
1044 bss_alloc (symbolP
, size
, align
);
1049 pe_lcomm (int needs_align
)
1051 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1055 const pseudo_typeS md_pseudo_table
[] =
1057 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1058 {"align", s_align_bytes
, 0},
1060 {"align", s_align_ptwo
, 0},
1062 {"arch", set_cpu_arch
, 0},
1066 {"lcomm", pe_lcomm
, 1},
1068 {"ffloat", float_cons
, 'f'},
1069 {"dfloat", float_cons
, 'd'},
1070 {"tfloat", float_cons
, 'x'},
1072 {"slong", signed_cons
, 4},
1073 {"noopt", s_ignore
, 0},
1074 {"optim", s_ignore
, 0},
1075 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1076 {"code16", set_code_flag
, CODE_16BIT
},
1077 {"code32", set_code_flag
, CODE_32BIT
},
1078 {"code64", set_code_flag
, CODE_64BIT
},
1079 {"intel_syntax", set_intel_syntax
, 1},
1080 {"att_syntax", set_intel_syntax
, 0},
1081 {"intel_mnemonic", set_intel_mnemonic
, 1},
1082 {"att_mnemonic", set_intel_mnemonic
, 0},
1083 {"allow_index_reg", set_allow_index_reg
, 1},
1084 {"disallow_index_reg", set_allow_index_reg
, 0},
1085 {"sse_check", set_check
, 0},
1086 {"operand_check", set_check
, 1},
1087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1088 {"largecomm", handle_large_common
, 0},
1090 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1091 {"loc", dwarf2_directive_loc
, 0},
1092 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1095 {"secrel32", pe_directive_secrel
, 0},
1100 /* For interface with expression (). */
1101 extern char *input_line_pointer
;
1103 /* Hash table for instruction mnemonic lookup. */
1104 static struct hash_control
*op_hash
;
1106 /* Hash table for register lookup. */
1107 static struct hash_control
*reg_hash
;
1110 i386_align_code (fragS
*fragP
, int count
)
1112 /* Various efficient no-op patterns for aligning code labels.
1113 Note: Don't try to assemble the instructions in the comments.
1114 0L and 0w are not legal. */
1115 static const unsigned char f32_1
[] =
1117 static const unsigned char f32_2
[] =
1118 {0x66,0x90}; /* xchg %ax,%ax */
1119 static const unsigned char f32_3
[] =
1120 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1121 static const unsigned char f32_4
[] =
1122 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1123 static const unsigned char f32_5
[] =
1125 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1126 static const unsigned char f32_6
[] =
1127 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1128 static const unsigned char f32_7
[] =
1129 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1130 static const unsigned char f32_8
[] =
1132 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1133 static const unsigned char f32_9
[] =
1134 {0x89,0xf6, /* movl %esi,%esi */
1135 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1136 static const unsigned char f32_10
[] =
1137 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1139 static const unsigned char f32_11
[] =
1140 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1141 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1142 static const unsigned char f32_12
[] =
1143 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1144 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1145 static const unsigned char f32_13
[] =
1146 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1147 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1148 static const unsigned char f32_14
[] =
1149 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1150 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1151 static const unsigned char f16_3
[] =
1152 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1153 static const unsigned char f16_4
[] =
1154 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1155 static const unsigned char f16_5
[] =
1157 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1158 static const unsigned char f16_6
[] =
1159 {0x89,0xf6, /* mov %si,%si */
1160 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1161 static const unsigned char f16_7
[] =
1162 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1163 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1164 static const unsigned char f16_8
[] =
1165 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1166 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1167 static const unsigned char jump_31
[] =
1168 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1169 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1170 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1171 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1172 static const unsigned char *const f32_patt
[] = {
1173 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1174 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1176 static const unsigned char *const f16_patt
[] = {
1177 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1179 /* nopl (%[re]ax) */
1180 static const unsigned char alt_3
[] =
1182 /* nopl 0(%[re]ax) */
1183 static const unsigned char alt_4
[] =
1184 {0x0f,0x1f,0x40,0x00};
1185 /* nopl 0(%[re]ax,%[re]ax,1) */
1186 static const unsigned char alt_5
[] =
1187 {0x0f,0x1f,0x44,0x00,0x00};
1188 /* nopw 0(%[re]ax,%[re]ax,1) */
1189 static const unsigned char alt_6
[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1191 /* nopl 0L(%[re]ax) */
1192 static const unsigned char alt_7
[] =
1193 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1194 /* nopl 0L(%[re]ax,%[re]ax,1) */
1195 static const unsigned char alt_8
[] =
1196 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1197 /* nopw 0L(%[re]ax,%[re]ax,1) */
1198 static const unsigned char alt_9
[] =
1199 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1200 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1201 static const unsigned char alt_10
[] =
1202 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1203 static const unsigned char *const alt_patt
[] = {
1204 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1208 /* Only align for at least a positive non-zero boundary. */
1209 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1212 /* We need to decide which NOP sequence to use for 32bit and
1213 64bit. When -mtune= is used:
1215 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1216 PROCESSOR_GENERIC32, f32_patt will be used.
1217 2. For the rest, alt_patt will be used.
1219 When -mtune= isn't used, alt_patt will be used if
1220 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1223 When -march= or .arch is used, we can't use anything beyond
1224 cpu_arch_isa_flags. */
1226 if (flag_code
== CODE_16BIT
)
1230 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1232 /* Adjust jump offset. */
1233 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1236 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1237 f16_patt
[count
- 1], count
);
1241 const unsigned char *const *patt
= NULL
;
1243 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1245 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1246 switch (cpu_arch_tune
)
1248 case PROCESSOR_UNKNOWN
:
1249 /* We use cpu_arch_isa_flags to check if we SHOULD
1250 optimize with nops. */
1251 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1256 case PROCESSOR_PENTIUM4
:
1257 case PROCESSOR_NOCONA
:
1258 case PROCESSOR_CORE
:
1259 case PROCESSOR_CORE2
:
1260 case PROCESSOR_COREI7
:
1261 case PROCESSOR_L1OM
:
1262 case PROCESSOR_K1OM
:
1263 case PROCESSOR_GENERIC64
:
1265 case PROCESSOR_ATHLON
:
1267 case PROCESSOR_AMDFAM10
:
1269 case PROCESSOR_ZNVER
:
1273 case PROCESSOR_I386
:
1274 case PROCESSOR_I486
:
1275 case PROCESSOR_PENTIUM
:
1276 case PROCESSOR_PENTIUMPRO
:
1277 case PROCESSOR_IAMCU
:
1278 case PROCESSOR_GENERIC32
:
1285 switch (fragP
->tc_frag_data
.tune
)
1287 case PROCESSOR_UNKNOWN
:
1288 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1289 PROCESSOR_UNKNOWN. */
1293 case PROCESSOR_I386
:
1294 case PROCESSOR_I486
:
1295 case PROCESSOR_PENTIUM
:
1296 case PROCESSOR_IAMCU
:
1298 case PROCESSOR_ATHLON
:
1300 case PROCESSOR_AMDFAM10
:
1302 case PROCESSOR_ZNVER
:
1304 case PROCESSOR_GENERIC32
:
1305 /* We use cpu_arch_isa_flags to check if we CAN optimize
1307 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1312 case PROCESSOR_PENTIUMPRO
:
1313 case PROCESSOR_PENTIUM4
:
1314 case PROCESSOR_NOCONA
:
1315 case PROCESSOR_CORE
:
1316 case PROCESSOR_CORE2
:
1317 case PROCESSOR_COREI7
:
1318 case PROCESSOR_L1OM
:
1319 case PROCESSOR_K1OM
:
1320 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1325 case PROCESSOR_GENERIC64
:
1331 if (patt
== f32_patt
)
1333 /* If the padding is less than 15 bytes, we use the normal
1334 ones. Otherwise, we use a jump instruction and adjust
1338 /* For 64bit, the limit is 3 bytes. */
1339 if (flag_code
== CODE_64BIT
1340 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1345 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1346 patt
[count
- 1], count
);
1349 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1351 /* Adjust jump offset. */
1352 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1357 /* Maximum length of an instruction is 10 byte. If the
1358 padding is greater than 10 bytes and we don't use jump,
1359 we have to break it into smaller pieces. */
1360 int padding
= count
;
1361 while (padding
> 10)
1364 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1369 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1370 patt
[padding
- 1], padding
);
1373 fragP
->fr_var
= count
;
1377 operand_type_all_zero (const union i386_operand_type
*x
)
1379 switch (ARRAY_SIZE(x
->array
))
1390 return !x
->array
[0];
1397 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1399 switch (ARRAY_SIZE(x
->array
))
1417 operand_type_equal (const union i386_operand_type
*x
,
1418 const union i386_operand_type
*y
)
1420 switch (ARRAY_SIZE(x
->array
))
1423 if (x
->array
[2] != y
->array
[2])
1427 if (x
->array
[1] != y
->array
[1])
1431 return x
->array
[0] == y
->array
[0];
1439 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1441 switch (ARRAY_SIZE(x
->array
))
1452 return !x
->array
[0];
1459 cpu_flags_equal (const union i386_cpu_flags
*x
,
1460 const union i386_cpu_flags
*y
)
1462 switch (ARRAY_SIZE(x
->array
))
1465 if (x
->array
[2] != y
->array
[2])
1469 if (x
->array
[1] != y
->array
[1])
1473 return x
->array
[0] == y
->array
[0];
1481 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1483 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1484 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1487 static INLINE i386_cpu_flags
1488 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1490 switch (ARRAY_SIZE (x
.array
))
1493 x
.array
[2] &= y
.array
[2];
1496 x
.array
[1] &= y
.array
[1];
1499 x
.array
[0] &= y
.array
[0];
1507 static INLINE i386_cpu_flags
1508 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1510 switch (ARRAY_SIZE (x
.array
))
1513 x
.array
[2] |= y
.array
[2];
1516 x
.array
[1] |= y
.array
[1];
1519 x
.array
[0] |= y
.array
[0];
1527 static INLINE i386_cpu_flags
1528 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1530 switch (ARRAY_SIZE (x
.array
))
1533 x
.array
[2] &= ~y
.array
[2];
1536 x
.array
[1] &= ~y
.array
[1];
1539 x
.array
[0] &= ~y
.array
[0];
1547 #define CPU_FLAGS_ARCH_MATCH 0x1
1548 #define CPU_FLAGS_64BIT_MATCH 0x2
1549 #define CPU_FLAGS_AES_MATCH 0x4
1550 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1551 #define CPU_FLAGS_AVX_MATCH 0x10
1553 #define CPU_FLAGS_32BIT_MATCH \
1554 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1555 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1556 #define CPU_FLAGS_PERFECT_MATCH \
1557 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1559 /* Return CPU flags match bits. */
1562 cpu_flags_match (const insn_template
*t
)
1564 i386_cpu_flags x
= t
->cpu_flags
;
1565 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1567 x
.bitfield
.cpu64
= 0;
1568 x
.bitfield
.cpuno64
= 0;
1570 if (cpu_flags_all_zero (&x
))
1572 /* This instruction is available on all archs. */
1573 match
|= CPU_FLAGS_32BIT_MATCH
;
1577 /* This instruction is available only on some archs. */
1578 i386_cpu_flags cpu
= cpu_arch_flags
;
1580 cpu
= cpu_flags_and (x
, cpu
);
1581 if (!cpu_flags_all_zero (&cpu
))
1583 if (x
.bitfield
.cpuavx
)
1585 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1586 if (cpu
.bitfield
.cpuavx
)
1588 /* Check SSE2AVX. */
1589 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1591 match
|= (CPU_FLAGS_ARCH_MATCH
1592 | CPU_FLAGS_AVX_MATCH
);
1594 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1595 match
|= CPU_FLAGS_AES_MATCH
;
1597 if (!x
.bitfield
.cpupclmul
1598 || cpu
.bitfield
.cpupclmul
)
1599 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1603 match
|= CPU_FLAGS_ARCH_MATCH
;
1605 else if (x
.bitfield
.cpuavx512vl
)
1607 /* Match AVX512VL. */
1608 if (cpu
.bitfield
.cpuavx512vl
)
1610 /* Need another match. */
1611 cpu
.bitfield
.cpuavx512vl
= 0;
1612 if (!cpu_flags_all_zero (&cpu
))
1613 match
|= CPU_FLAGS_32BIT_MATCH
;
1615 match
|= CPU_FLAGS_ARCH_MATCH
;
1618 match
|= CPU_FLAGS_ARCH_MATCH
;
1621 match
|= CPU_FLAGS_32BIT_MATCH
;
1627 static INLINE i386_operand_type
1628 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1630 switch (ARRAY_SIZE (x
.array
))
1633 x
.array
[2] &= y
.array
[2];
1636 x
.array
[1] &= y
.array
[1];
1639 x
.array
[0] &= y
.array
[0];
1647 static INLINE i386_operand_type
1648 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1650 switch (ARRAY_SIZE (x
.array
))
1653 x
.array
[2] |= y
.array
[2];
1656 x
.array
[1] |= y
.array
[1];
1659 x
.array
[0] |= y
.array
[0];
1667 static INLINE i386_operand_type
1668 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1670 switch (ARRAY_SIZE (x
.array
))
1673 x
.array
[2] ^= y
.array
[2];
1676 x
.array
[1] ^= y
.array
[1];
1679 x
.array
[0] ^= y
.array
[0];
1687 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1688 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1689 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1690 static const i386_operand_type inoutportreg
1691 = OPERAND_TYPE_INOUTPORTREG
;
1692 static const i386_operand_type reg16_inoutportreg
1693 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1694 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1695 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1696 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1697 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1698 static const i386_operand_type anydisp
1699 = OPERAND_TYPE_ANYDISP
;
1700 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1701 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1702 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1703 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1704 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1705 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1706 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1707 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1708 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1709 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1710 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1711 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1712 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1713 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1724 operand_type_check (i386_operand_type t
, enum operand_type c
)
1729 return (t
.bitfield
.reg8
1732 || t
.bitfield
.reg64
);
1735 return (t
.bitfield
.imm8
1739 || t
.bitfield
.imm32s
1740 || t
.bitfield
.imm64
);
1743 return (t
.bitfield
.disp8
1744 || t
.bitfield
.disp16
1745 || t
.bitfield
.disp32
1746 || t
.bitfield
.disp32s
1747 || t
.bitfield
.disp64
);
1750 return (t
.bitfield
.disp8
1751 || t
.bitfield
.disp16
1752 || t
.bitfield
.disp32
1753 || t
.bitfield
.disp32s
1754 || t
.bitfield
.disp64
1755 || t
.bitfield
.baseindex
);
1764 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1765 operand J for instruction template T. */
1768 match_reg_size (const insn_template
*t
, unsigned int j
)
1770 return !((i
.types
[j
].bitfield
.byte
1771 && !t
->operand_types
[j
].bitfield
.byte
)
1772 || (i
.types
[j
].bitfield
.word
1773 && !t
->operand_types
[j
].bitfield
.word
)
1774 || (i
.types
[j
].bitfield
.dword
1775 && !t
->operand_types
[j
].bitfield
.dword
)
1776 || (i
.types
[j
].bitfield
.qword
1777 && !t
->operand_types
[j
].bitfield
.qword
));
1780 /* Return 1 if there is no conflict in any size on operand J for
1781 instruction template T. */
1784 match_mem_size (const insn_template
*t
, unsigned int j
)
1786 return (match_reg_size (t
, j
)
1787 && !((i
.types
[j
].bitfield
.unspecified
1789 && !t
->operand_types
[j
].bitfield
.unspecified
)
1790 || (i
.types
[j
].bitfield
.fword
1791 && !t
->operand_types
[j
].bitfield
.fword
)
1792 || (i
.types
[j
].bitfield
.tbyte
1793 && !t
->operand_types
[j
].bitfield
.tbyte
)
1794 || (i
.types
[j
].bitfield
.xmmword
1795 && !t
->operand_types
[j
].bitfield
.xmmword
)
1796 || (i
.types
[j
].bitfield
.ymmword
1797 && !t
->operand_types
[j
].bitfield
.ymmword
)
1798 || (i
.types
[j
].bitfield
.zmmword
1799 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1802 /* Return 1 if there is no size conflict on any operands for
1803 instruction template T. */
1806 operand_size_match (const insn_template
*t
)
1811 /* Don't check jump instructions. */
1812 if (t
->opcode_modifier
.jump
1813 || t
->opcode_modifier
.jumpbyte
1814 || t
->opcode_modifier
.jumpdword
1815 || t
->opcode_modifier
.jumpintersegment
)
1818 /* Check memory and accumulator operand size. */
1819 for (j
= 0; j
< i
.operands
; j
++)
1821 if (t
->operand_types
[j
].bitfield
.anysize
)
1824 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1830 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1839 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1842 i
.error
= operand_size_mismatch
;
1846 /* Check reverse. */
1847 gas_assert (i
.operands
== 2);
1850 for (j
= 0; j
< 2; j
++)
1852 if (t
->operand_types
[j
].bitfield
.acc
1853 && !match_reg_size (t
, j
? 0 : 1))
1856 if (i
.types
[j
].bitfield
.mem
1857 && !match_mem_size (t
, j
? 0 : 1))
1865 operand_type_match (i386_operand_type overlap
,
1866 i386_operand_type given
)
1868 i386_operand_type temp
= overlap
;
1870 temp
.bitfield
.jumpabsolute
= 0;
1871 temp
.bitfield
.unspecified
= 0;
1872 temp
.bitfield
.byte
= 0;
1873 temp
.bitfield
.word
= 0;
1874 temp
.bitfield
.dword
= 0;
1875 temp
.bitfield
.fword
= 0;
1876 temp
.bitfield
.qword
= 0;
1877 temp
.bitfield
.tbyte
= 0;
1878 temp
.bitfield
.xmmword
= 0;
1879 temp
.bitfield
.ymmword
= 0;
1880 temp
.bitfield
.zmmword
= 0;
1881 if (operand_type_all_zero (&temp
))
1884 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1885 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1889 i
.error
= operand_type_mismatch
;
1893 /* If given types g0 and g1 are registers they must be of the same type
1894 unless the expected operand type register overlap is null.
1895 Note that Acc in a template matches every size of reg. */
1898 operand_type_register_match (i386_operand_type m0
,
1899 i386_operand_type g0
,
1900 i386_operand_type t0
,
1901 i386_operand_type m1
,
1902 i386_operand_type g1
,
1903 i386_operand_type t1
)
1905 if (!operand_type_check (g0
, reg
))
1908 if (!operand_type_check (g1
, reg
))
1911 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1912 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1913 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1914 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1917 if (m0
.bitfield
.acc
)
1919 t0
.bitfield
.reg8
= 1;
1920 t0
.bitfield
.reg16
= 1;
1921 t0
.bitfield
.reg32
= 1;
1922 t0
.bitfield
.reg64
= 1;
1925 if (m1
.bitfield
.acc
)
1927 t1
.bitfield
.reg8
= 1;
1928 t1
.bitfield
.reg16
= 1;
1929 t1
.bitfield
.reg32
= 1;
1930 t1
.bitfield
.reg64
= 1;
1933 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1934 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1935 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1936 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1939 i
.error
= register_type_mismatch
;
1944 static INLINE
unsigned int
1945 register_number (const reg_entry
*r
)
1947 unsigned int nr
= r
->reg_num
;
1949 if (r
->reg_flags
& RegRex
)
1952 if (r
->reg_flags
& RegVRex
)
1958 static INLINE
unsigned int
1959 mode_from_disp_size (i386_operand_type t
)
1961 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1963 else if (t
.bitfield
.disp16
1964 || t
.bitfield
.disp32
1965 || t
.bitfield
.disp32s
)
1972 fits_in_signed_byte (addressT num
)
1974 return num
+ 0x80 <= 0xff;
1978 fits_in_unsigned_byte (addressT num
)
1984 fits_in_unsigned_word (addressT num
)
1986 return num
<= 0xffff;
1990 fits_in_signed_word (addressT num
)
1992 return num
+ 0x8000 <= 0xffff;
1996 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2001 return num
+ 0x80000000 <= 0xffffffff;
2003 } /* fits_in_signed_long() */
2006 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2011 return num
<= 0xffffffff;
2013 } /* fits_in_unsigned_long() */
2016 fits_in_vec_disp8 (offsetT num
)
2018 int shift
= i
.memshift
;
2024 mask
= (1 << shift
) - 1;
2026 /* Return 0 if NUM isn't properly aligned. */
2030 /* Check if NUM will fit in 8bit after shift. */
2031 return fits_in_signed_byte (num
>> shift
);
2035 fits_in_imm4 (offsetT num
)
2037 return (num
& 0xf) == num
;
2040 static i386_operand_type
2041 smallest_imm_type (offsetT num
)
2043 i386_operand_type t
;
2045 operand_type_set (&t
, 0);
2046 t
.bitfield
.imm64
= 1;
2048 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2050 /* This code is disabled on the 486 because all the Imm1 forms
2051 in the opcode table are slower on the i486. They're the
2052 versions with the implicitly specified single-position
2053 displacement, which has another syntax if you really want to
2055 t
.bitfield
.imm1
= 1;
2056 t
.bitfield
.imm8
= 1;
2057 t
.bitfield
.imm8s
= 1;
2058 t
.bitfield
.imm16
= 1;
2059 t
.bitfield
.imm32
= 1;
2060 t
.bitfield
.imm32s
= 1;
2062 else if (fits_in_signed_byte (num
))
2064 t
.bitfield
.imm8
= 1;
2065 t
.bitfield
.imm8s
= 1;
2066 t
.bitfield
.imm16
= 1;
2067 t
.bitfield
.imm32
= 1;
2068 t
.bitfield
.imm32s
= 1;
2070 else if (fits_in_unsigned_byte (num
))
2072 t
.bitfield
.imm8
= 1;
2073 t
.bitfield
.imm16
= 1;
2074 t
.bitfield
.imm32
= 1;
2075 t
.bitfield
.imm32s
= 1;
2077 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2079 t
.bitfield
.imm16
= 1;
2080 t
.bitfield
.imm32
= 1;
2081 t
.bitfield
.imm32s
= 1;
2083 else if (fits_in_signed_long (num
))
2085 t
.bitfield
.imm32
= 1;
2086 t
.bitfield
.imm32s
= 1;
2088 else if (fits_in_unsigned_long (num
))
2089 t
.bitfield
.imm32
= 1;
2095 offset_in_range (offsetT val
, int size
)
2101 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2102 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2103 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2105 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2111 /* If BFD64, sign extend val for 32bit address mode. */
2112 if (flag_code
!= CODE_64BIT
2113 || i
.prefix
[ADDR_PREFIX
])
2114 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2115 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2118 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2120 char buf1
[40], buf2
[40];
2122 sprint_value (buf1
, val
);
2123 sprint_value (buf2
, val
& mask
);
2124 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2138 a. PREFIX_EXIST if attempting to add a prefix where one from the
2139 same class already exists.
2140 b. PREFIX_LOCK if lock prefix is added.
2141 c. PREFIX_REP if rep/repne prefix is added.
2142 d. PREFIX_OTHER if other prefix is added.
2145 static enum PREFIX_GROUP
2146 add_prefix (unsigned int prefix
)
2148 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2151 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2152 && flag_code
== CODE_64BIT
)
2154 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2155 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2156 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2167 case CS_PREFIX_OPCODE
:
2168 case DS_PREFIX_OPCODE
:
2169 case ES_PREFIX_OPCODE
:
2170 case FS_PREFIX_OPCODE
:
2171 case GS_PREFIX_OPCODE
:
2172 case SS_PREFIX_OPCODE
:
2176 case REPNE_PREFIX_OPCODE
:
2177 case REPE_PREFIX_OPCODE
:
2182 case LOCK_PREFIX_OPCODE
:
2191 case ADDR_PREFIX_OPCODE
:
2195 case DATA_PREFIX_OPCODE
:
2199 if (i
.prefix
[q
] != 0)
2207 i
.prefix
[q
] |= prefix
;
2210 as_bad (_("same type of prefix used twice"));
2216 update_code_flag (int value
, int check
)
2218 PRINTF_LIKE ((*as_error
));
2220 flag_code
= (enum flag_code
) value
;
2221 if (flag_code
== CODE_64BIT
)
2223 cpu_arch_flags
.bitfield
.cpu64
= 1;
2224 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2228 cpu_arch_flags
.bitfield
.cpu64
= 0;
2229 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2231 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2234 as_error
= as_fatal
;
2237 (*as_error
) (_("64bit mode not supported on `%s'."),
2238 cpu_arch_name
? cpu_arch_name
: default_arch
);
2240 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2243 as_error
= as_fatal
;
2246 (*as_error
) (_("32bit mode not supported on `%s'."),
2247 cpu_arch_name
? cpu_arch_name
: default_arch
);
2249 stackop_size
= '\0';
2253 set_code_flag (int value
)
2255 update_code_flag (value
, 0);
2259 set_16bit_gcc_code_flag (int new_code_flag
)
2261 flag_code
= (enum flag_code
) new_code_flag
;
2262 if (flag_code
!= CODE_16BIT
)
2264 cpu_arch_flags
.bitfield
.cpu64
= 0;
2265 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2266 stackop_size
= LONG_MNEM_SUFFIX
;
2270 set_intel_syntax (int syntax_flag
)
2272 /* Find out if register prefixing is specified. */
2273 int ask_naked_reg
= 0;
2276 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2279 int e
= get_symbol_name (&string
);
2281 if (strcmp (string
, "prefix") == 0)
2283 else if (strcmp (string
, "noprefix") == 0)
2286 as_bad (_("bad argument to syntax directive."));
2287 (void) restore_line_pointer (e
);
2289 demand_empty_rest_of_line ();
2291 intel_syntax
= syntax_flag
;
2293 if (ask_naked_reg
== 0)
2294 allow_naked_reg
= (intel_syntax
2295 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2297 allow_naked_reg
= (ask_naked_reg
< 0);
2299 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2301 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2302 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2303 register_prefix
= allow_naked_reg
? "" : "%";
2307 set_intel_mnemonic (int mnemonic_flag
)
2309 intel_mnemonic
= mnemonic_flag
;
2313 set_allow_index_reg (int flag
)
2315 allow_index_reg
= flag
;
2319 set_check (int what
)
2321 enum check_kind
*kind
;
2326 kind
= &operand_check
;
2337 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2340 int e
= get_symbol_name (&string
);
2342 if (strcmp (string
, "none") == 0)
2344 else if (strcmp (string
, "warning") == 0)
2345 *kind
= check_warning
;
2346 else if (strcmp (string
, "error") == 0)
2347 *kind
= check_error
;
2349 as_bad (_("bad argument to %s_check directive."), str
);
2350 (void) restore_line_pointer (e
);
2353 as_bad (_("missing argument for %s_check directive"), str
);
2355 demand_empty_rest_of_line ();
2359 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2360 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2363 static const char *arch
;
2365 /* Intel LIOM is only supported on ELF. */
2371 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2372 use default_arch. */
2373 arch
= cpu_arch_name
;
2375 arch
= default_arch
;
2378 /* If we are targeting Intel MCU, we must enable it. */
2379 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2380 || new_flag
.bitfield
.cpuiamcu
)
2383 /* If we are targeting Intel L1OM, we must enable it. */
2384 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2385 || new_flag
.bitfield
.cpul1om
)
2388 /* If we are targeting Intel K1OM, we must enable it. */
2389 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2390 || new_flag
.bitfield
.cpuk1om
)
2393 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2398 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2402 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2405 int e
= get_symbol_name (&string
);
2407 i386_cpu_flags flags
;
2409 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2411 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2413 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2417 cpu_arch_name
= cpu_arch
[j
].name
;
2418 cpu_sub_arch_name
= NULL
;
2419 cpu_arch_flags
= cpu_arch
[j
].flags
;
2420 if (flag_code
== CODE_64BIT
)
2422 cpu_arch_flags
.bitfield
.cpu64
= 1;
2423 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2427 cpu_arch_flags
.bitfield
.cpu64
= 0;
2428 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2430 cpu_arch_isa
= cpu_arch
[j
].type
;
2431 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2432 if (!cpu_arch_tune_set
)
2434 cpu_arch_tune
= cpu_arch_isa
;
2435 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2440 flags
= cpu_flags_or (cpu_arch_flags
,
2443 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2445 if (cpu_sub_arch_name
)
2447 char *name
= cpu_sub_arch_name
;
2448 cpu_sub_arch_name
= concat (name
,
2450 (const char *) NULL
);
2454 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2455 cpu_arch_flags
= flags
;
2456 cpu_arch_isa_flags
= flags
;
2458 (void) restore_line_pointer (e
);
2459 demand_empty_rest_of_line ();
2464 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2466 /* Disable an ISA entension. */
2467 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2468 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2470 flags
= cpu_flags_and_not (cpu_arch_flags
,
2471 cpu_noarch
[j
].flags
);
2472 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2474 if (cpu_sub_arch_name
)
2476 char *name
= cpu_sub_arch_name
;
2477 cpu_sub_arch_name
= concat (name
, string
,
2478 (const char *) NULL
);
2482 cpu_sub_arch_name
= xstrdup (string
);
2483 cpu_arch_flags
= flags
;
2484 cpu_arch_isa_flags
= flags
;
2486 (void) restore_line_pointer (e
);
2487 demand_empty_rest_of_line ();
2491 j
= ARRAY_SIZE (cpu_arch
);
2494 if (j
>= ARRAY_SIZE (cpu_arch
))
2495 as_bad (_("no such architecture: `%s'"), string
);
2497 *input_line_pointer
= e
;
2500 as_bad (_("missing cpu architecture"));
2502 no_cond_jump_promotion
= 0;
2503 if (*input_line_pointer
== ','
2504 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2509 ++input_line_pointer
;
2510 e
= get_symbol_name (&string
);
2512 if (strcmp (string
, "nojumps") == 0)
2513 no_cond_jump_promotion
= 1;
2514 else if (strcmp (string
, "jumps") == 0)
2517 as_bad (_("no such architecture modifier: `%s'"), string
);
2519 (void) restore_line_pointer (e
);
2522 demand_empty_rest_of_line ();
2525 enum bfd_architecture
2528 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2530 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2531 || flag_code
!= CODE_64BIT
)
2532 as_fatal (_("Intel L1OM is 64bit ELF only"));
2533 return bfd_arch_l1om
;
2535 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2537 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2538 || flag_code
!= CODE_64BIT
)
2539 as_fatal (_("Intel K1OM is 64bit ELF only"));
2540 return bfd_arch_k1om
;
2542 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2544 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2545 || flag_code
== CODE_64BIT
)
2546 as_fatal (_("Intel MCU is 32bit ELF only"));
2547 return bfd_arch_iamcu
;
2550 return bfd_arch_i386
;
2556 if (!strncmp (default_arch
, "x86_64", 6))
2558 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2560 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2561 || default_arch
[6] != '\0')
2562 as_fatal (_("Intel L1OM is 64bit ELF only"));
2563 return bfd_mach_l1om
;
2565 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2567 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2568 || default_arch
[6] != '\0')
2569 as_fatal (_("Intel K1OM is 64bit ELF only"));
2570 return bfd_mach_k1om
;
2572 else if (default_arch
[6] == '\0')
2573 return bfd_mach_x86_64
;
2575 return bfd_mach_x64_32
;
2577 else if (!strcmp (default_arch
, "i386")
2578 || !strcmp (default_arch
, "iamcu"))
2580 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2582 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2583 as_fatal (_("Intel MCU is 32bit ELF only"));
2584 return bfd_mach_i386_iamcu
;
2587 return bfd_mach_i386_i386
;
2590 as_fatal (_("unknown architecture"));
2596 const char *hash_err
;
2598 /* Initialize op_hash hash table. */
2599 op_hash
= hash_new ();
2602 const insn_template
*optab
;
2603 templates
*core_optab
;
2605 /* Setup for loop. */
2607 core_optab
= XNEW (templates
);
2608 core_optab
->start
= optab
;
2613 if (optab
->name
== NULL
2614 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2616 /* different name --> ship out current template list;
2617 add to hash table; & begin anew. */
2618 core_optab
->end
= optab
;
2619 hash_err
= hash_insert (op_hash
,
2621 (void *) core_optab
);
2624 as_fatal (_("can't hash %s: %s"),
2628 if (optab
->name
== NULL
)
2630 core_optab
= XNEW (templates
);
2631 core_optab
->start
= optab
;
2636 /* Initialize reg_hash hash table. */
2637 reg_hash
= hash_new ();
2639 const reg_entry
*regtab
;
2640 unsigned int regtab_size
= i386_regtab_size
;
2642 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2644 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2646 as_fatal (_("can't hash %s: %s"),
2652 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2657 for (c
= 0; c
< 256; c
++)
2662 mnemonic_chars
[c
] = c
;
2663 register_chars
[c
] = c
;
2664 operand_chars
[c
] = c
;
2666 else if (ISLOWER (c
))
2668 mnemonic_chars
[c
] = c
;
2669 register_chars
[c
] = c
;
2670 operand_chars
[c
] = c
;
2672 else if (ISUPPER (c
))
2674 mnemonic_chars
[c
] = TOLOWER (c
);
2675 register_chars
[c
] = mnemonic_chars
[c
];
2676 operand_chars
[c
] = c
;
2678 else if (c
== '{' || c
== '}')
2679 operand_chars
[c
] = c
;
2681 if (ISALPHA (c
) || ISDIGIT (c
))
2682 identifier_chars
[c
] = c
;
2685 identifier_chars
[c
] = c
;
2686 operand_chars
[c
] = c
;
2691 identifier_chars
['@'] = '@';
2694 identifier_chars
['?'] = '?';
2695 operand_chars
['?'] = '?';
2697 digit_chars
['-'] = '-';
2698 mnemonic_chars
['_'] = '_';
2699 mnemonic_chars
['-'] = '-';
2700 mnemonic_chars
['.'] = '.';
2701 identifier_chars
['_'] = '_';
2702 identifier_chars
['.'] = '.';
2704 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2705 operand_chars
[(unsigned char) *p
] = *p
;
2708 if (flag_code
== CODE_64BIT
)
2710 #if defined (OBJ_COFF) && defined (TE_PE)
2711 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2714 x86_dwarf2_return_column
= 16;
2716 x86_cie_data_alignment
= -8;
2720 x86_dwarf2_return_column
= 8;
2721 x86_cie_data_alignment
= -4;
2726 i386_print_statistics (FILE *file
)
2728 hash_print_statistics (file
, "i386 opcode", op_hash
);
2729 hash_print_statistics (file
, "i386 register", reg_hash
);
2734 /* Debugging routines for md_assemble. */
2735 static void pte (insn_template
*);
2736 static void pt (i386_operand_type
);
2737 static void pe (expressionS
*);
2738 static void ps (symbolS
*);
2741 pi (char *line
, i386_insn
*x
)
2745 fprintf (stdout
, "%s: template ", line
);
2747 fprintf (stdout
, " address: base %s index %s scale %x\n",
2748 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2749 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2750 x
->log2_scale_factor
);
2751 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2752 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2753 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2754 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2755 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2756 (x
->rex
& REX_W
) != 0,
2757 (x
->rex
& REX_R
) != 0,
2758 (x
->rex
& REX_X
) != 0,
2759 (x
->rex
& REX_B
) != 0);
2760 for (j
= 0; j
< x
->operands
; j
++)
2762 fprintf (stdout
, " #%d: ", j
+ 1);
2764 fprintf (stdout
, "\n");
2765 if (x
->types
[j
].bitfield
.reg8
2766 || x
->types
[j
].bitfield
.reg16
2767 || x
->types
[j
].bitfield
.reg32
2768 || x
->types
[j
].bitfield
.reg64
2769 || x
->types
[j
].bitfield
.regmmx
2770 || x
->types
[j
].bitfield
.regxmm
2771 || x
->types
[j
].bitfield
.regymm
2772 || x
->types
[j
].bitfield
.regzmm
2773 || x
->types
[j
].bitfield
.sreg2
2774 || x
->types
[j
].bitfield
.sreg3
2775 || x
->types
[j
].bitfield
.control
2776 || x
->types
[j
].bitfield
.debug
2777 || x
->types
[j
].bitfield
.test
)
2778 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2779 if (operand_type_check (x
->types
[j
], imm
))
2781 if (operand_type_check (x
->types
[j
], disp
))
2782 pe (x
->op
[j
].disps
);
2787 pte (insn_template
*t
)
2790 fprintf (stdout
, " %d operands ", t
->operands
);
2791 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2792 if (t
->extension_opcode
!= None
)
2793 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2794 if (t
->opcode_modifier
.d
)
2795 fprintf (stdout
, "D");
2796 if (t
->opcode_modifier
.w
)
2797 fprintf (stdout
, "W");
2798 fprintf (stdout
, "\n");
2799 for (j
= 0; j
< t
->operands
; j
++)
2801 fprintf (stdout
, " #%d type ", j
+ 1);
2802 pt (t
->operand_types
[j
]);
2803 fprintf (stdout
, "\n");
2810 fprintf (stdout
, " operation %d\n", e
->X_op
);
2811 fprintf (stdout
, " add_number %ld (%lx)\n",
2812 (long) e
->X_add_number
, (long) e
->X_add_number
);
2813 if (e
->X_add_symbol
)
2815 fprintf (stdout
, " add_symbol ");
2816 ps (e
->X_add_symbol
);
2817 fprintf (stdout
, "\n");
2821 fprintf (stdout
, " op_symbol ");
2822 ps (e
->X_op_symbol
);
2823 fprintf (stdout
, "\n");
2830 fprintf (stdout
, "%s type %s%s",
2832 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2833 segment_name (S_GET_SEGMENT (s
)));
2836 static struct type_name
2838 i386_operand_type mask
;
2841 const type_names
[] =
2843 { OPERAND_TYPE_REG8
, "r8" },
2844 { OPERAND_TYPE_REG16
, "r16" },
2845 { OPERAND_TYPE_REG32
, "r32" },
2846 { OPERAND_TYPE_REG64
, "r64" },
2847 { OPERAND_TYPE_IMM8
, "i8" },
2848 { OPERAND_TYPE_IMM8
, "i8s" },
2849 { OPERAND_TYPE_IMM16
, "i16" },
2850 { OPERAND_TYPE_IMM32
, "i32" },
2851 { OPERAND_TYPE_IMM32S
, "i32s" },
2852 { OPERAND_TYPE_IMM64
, "i64" },
2853 { OPERAND_TYPE_IMM1
, "i1" },
2854 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2855 { OPERAND_TYPE_DISP8
, "d8" },
2856 { OPERAND_TYPE_DISP16
, "d16" },
2857 { OPERAND_TYPE_DISP32
, "d32" },
2858 { OPERAND_TYPE_DISP32S
, "d32s" },
2859 { OPERAND_TYPE_DISP64
, "d64" },
2860 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2861 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2862 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2863 { OPERAND_TYPE_CONTROL
, "control reg" },
2864 { OPERAND_TYPE_TEST
, "test reg" },
2865 { OPERAND_TYPE_DEBUG
, "debug reg" },
2866 { OPERAND_TYPE_FLOATREG
, "FReg" },
2867 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2868 { OPERAND_TYPE_SREG2
, "SReg2" },
2869 { OPERAND_TYPE_SREG3
, "SReg3" },
2870 { OPERAND_TYPE_ACC
, "Acc" },
2871 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2872 { OPERAND_TYPE_REGMMX
, "rMMX" },
2873 { OPERAND_TYPE_REGXMM
, "rXMM" },
2874 { OPERAND_TYPE_REGYMM
, "rYMM" },
2875 { OPERAND_TYPE_REGZMM
, "rZMM" },
2876 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2877 { OPERAND_TYPE_ESSEG
, "es" },
2881 pt (i386_operand_type t
)
2884 i386_operand_type a
;
2886 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2888 a
= operand_type_and (t
, type_names
[j
].mask
);
2889 if (!operand_type_all_zero (&a
))
2890 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2895 #endif /* DEBUG386 */
2897 static bfd_reloc_code_real_type
2898 reloc (unsigned int size
,
2901 bfd_reloc_code_real_type other
)
2903 if (other
!= NO_RELOC
)
2905 reloc_howto_type
*rel
;
2910 case BFD_RELOC_X86_64_GOT32
:
2911 return BFD_RELOC_X86_64_GOT64
;
2913 case BFD_RELOC_X86_64_GOTPLT64
:
2914 return BFD_RELOC_X86_64_GOTPLT64
;
2916 case BFD_RELOC_X86_64_PLTOFF64
:
2917 return BFD_RELOC_X86_64_PLTOFF64
;
2919 case BFD_RELOC_X86_64_GOTPC32
:
2920 other
= BFD_RELOC_X86_64_GOTPC64
;
2922 case BFD_RELOC_X86_64_GOTPCREL
:
2923 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2925 case BFD_RELOC_X86_64_TPOFF32
:
2926 other
= BFD_RELOC_X86_64_TPOFF64
;
2928 case BFD_RELOC_X86_64_DTPOFF32
:
2929 other
= BFD_RELOC_X86_64_DTPOFF64
;
2935 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2936 if (other
== BFD_RELOC_SIZE32
)
2939 other
= BFD_RELOC_SIZE64
;
2942 as_bad (_("there are no pc-relative size relocations"));
2948 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2949 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2952 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2954 as_bad (_("unknown relocation (%u)"), other
);
2955 else if (size
!= bfd_get_reloc_size (rel
))
2956 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2957 bfd_get_reloc_size (rel
),
2959 else if (pcrel
&& !rel
->pc_relative
)
2960 as_bad (_("non-pc-relative relocation for pc-relative field"));
2961 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2963 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2965 as_bad (_("relocated field and relocation type differ in signedness"));
2974 as_bad (_("there are no unsigned pc-relative relocations"));
2977 case 1: return BFD_RELOC_8_PCREL
;
2978 case 2: return BFD_RELOC_16_PCREL
;
2979 case 4: return BFD_RELOC_32_PCREL
;
2980 case 8: return BFD_RELOC_64_PCREL
;
2982 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2989 case 4: return BFD_RELOC_X86_64_32S
;
2994 case 1: return BFD_RELOC_8
;
2995 case 2: return BFD_RELOC_16
;
2996 case 4: return BFD_RELOC_32
;
2997 case 8: return BFD_RELOC_64
;
2999 as_bad (_("cannot do %s %u byte relocation"),
3000 sign
> 0 ? "signed" : "unsigned", size
);
3006 /* Here we decide which fixups can be adjusted to make them relative to
3007 the beginning of the section instead of the symbol. Basically we need
3008 to make sure that the dynamic relocations are done correctly, so in
3009 some cases we force the original symbol to be used. */
3012 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3018 /* Don't adjust pc-relative references to merge sections in 64-bit
3020 if (use_rela_relocations
3021 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3025 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3026 and changed later by validate_fix. */
3027 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3028 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3031 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3032 for size relocations. */
3033 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3034 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3035 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3036 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3037 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3038 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3039 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3040 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3041 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3042 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3043 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3044 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3045 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3046 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3047 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3048 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3049 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3050 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3055 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3056 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3057 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3058 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3059 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3060 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3061 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3062 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3063 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3064 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3065 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3072 intel_float_operand (const char *mnemonic
)
3074 /* Note that the value returned is meaningful only for opcodes with (memory)
3075 operands, hence the code here is free to improperly handle opcodes that
3076 have no operands (for better performance and smaller code). */
3078 if (mnemonic
[0] != 'f')
3079 return 0; /* non-math */
3081 switch (mnemonic
[1])
3083 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3084 the fs segment override prefix not currently handled because no
3085 call path can make opcodes without operands get here */
3087 return 2 /* integer op */;
3089 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3090 return 3; /* fldcw/fldenv */
3093 if (mnemonic
[2] != 'o' /* fnop */)
3094 return 3; /* non-waiting control op */
3097 if (mnemonic
[2] == 's')
3098 return 3; /* frstor/frstpm */
3101 if (mnemonic
[2] == 'a')
3102 return 3; /* fsave */
3103 if (mnemonic
[2] == 't')
3105 switch (mnemonic
[3])
3107 case 'c': /* fstcw */
3108 case 'd': /* fstdw */
3109 case 'e': /* fstenv */
3110 case 's': /* fsts[gw] */
3116 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3117 return 0; /* fxsave/fxrstor are not really math ops */
3124 /* Build the VEX prefix. */
3127 build_vex_prefix (const insn_template
*t
)
3129 unsigned int register_specifier
;
3130 unsigned int implied_prefix
;
3131 unsigned int vector_length
;
3133 /* Check register specifier. */
3134 if (i
.vex
.register_specifier
)
3136 register_specifier
=
3137 ~register_number (i
.vex
.register_specifier
) & 0xf;
3138 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3141 register_specifier
= 0xf;
3143 /* Use 2-byte VEX prefix by swappping destination and source
3146 && i
.operands
== i
.reg_operands
3147 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3148 && i
.tm
.opcode_modifier
.s
3151 unsigned int xchg
= i
.operands
- 1;
3152 union i386_op temp_op
;
3153 i386_operand_type temp_type
;
3155 temp_type
= i
.types
[xchg
];
3156 i
.types
[xchg
] = i
.types
[0];
3157 i
.types
[0] = temp_type
;
3158 temp_op
= i
.op
[xchg
];
3159 i
.op
[xchg
] = i
.op
[0];
3162 gas_assert (i
.rm
.mode
== 3);
3166 i
.rm
.regmem
= i
.rm
.reg
;
3169 /* Use the next insn. */
3173 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3174 vector_length
= avxscalar
;
3176 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3178 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3183 case DATA_PREFIX_OPCODE
:
3186 case REPE_PREFIX_OPCODE
:
3189 case REPNE_PREFIX_OPCODE
:
3196 /* Use 2-byte VEX prefix if possible. */
3197 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3198 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3199 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3201 /* 2-byte VEX prefix. */
3205 i
.vex
.bytes
[0] = 0xc5;
3207 /* Check the REX.R bit. */
3208 r
= (i
.rex
& REX_R
) ? 0 : 1;
3209 i
.vex
.bytes
[1] = (r
<< 7
3210 | register_specifier
<< 3
3211 | vector_length
<< 2
3216 /* 3-byte VEX prefix. */
3221 switch (i
.tm
.opcode_modifier
.vexopcode
)
3225 i
.vex
.bytes
[0] = 0xc4;
3229 i
.vex
.bytes
[0] = 0xc4;
3233 i
.vex
.bytes
[0] = 0xc4;
3237 i
.vex
.bytes
[0] = 0x8f;
3241 i
.vex
.bytes
[0] = 0x8f;
3245 i
.vex
.bytes
[0] = 0x8f;
3251 /* The high 3 bits of the second VEX byte are 1's compliment
3252 of RXB bits from REX. */
3253 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3255 /* Check the REX.W bit. */
3256 w
= (i
.rex
& REX_W
) ? 1 : 0;
3257 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3260 i
.vex
.bytes
[2] = (w
<< 7
3261 | register_specifier
<< 3
3262 | vector_length
<< 2
3267 /* Build the EVEX prefix. */
3270 build_evex_prefix (void)
3272 unsigned int register_specifier
;
3273 unsigned int implied_prefix
;
3275 rex_byte vrex_used
= 0;
3277 /* Check register specifier. */
3278 if (i
.vex
.register_specifier
)
3280 gas_assert ((i
.vrex
& REX_X
) == 0);
3282 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3283 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3284 register_specifier
+= 8;
3285 /* The upper 16 registers are encoded in the fourth byte of the
3287 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3288 i
.vex
.bytes
[3] = 0x8;
3289 register_specifier
= ~register_specifier
& 0xf;
3293 register_specifier
= 0xf;
3295 /* Encode upper 16 vector index register in the fourth byte of
3297 if (!(i
.vrex
& REX_X
))
3298 i
.vex
.bytes
[3] = 0x8;
3303 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3308 case DATA_PREFIX_OPCODE
:
3311 case REPE_PREFIX_OPCODE
:
3314 case REPNE_PREFIX_OPCODE
:
3321 /* 4 byte EVEX prefix. */
3323 i
.vex
.bytes
[0] = 0x62;
3326 switch (i
.tm
.opcode_modifier
.vexopcode
)
3342 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3344 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3346 /* The fifth bit of the second EVEX byte is 1's compliment of the
3347 REX_R bit in VREX. */
3348 if (!(i
.vrex
& REX_R
))
3349 i
.vex
.bytes
[1] |= 0x10;
3353 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3355 /* When all operands are registers, the REX_X bit in REX is not
3356 used. We reuse it to encode the upper 16 registers, which is
3357 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3358 as 1's compliment. */
3359 if ((i
.vrex
& REX_B
))
3362 i
.vex
.bytes
[1] &= ~0x40;
3366 /* EVEX instructions shouldn't need the REX prefix. */
3367 i
.vrex
&= ~vrex_used
;
3368 gas_assert (i
.vrex
== 0);
3370 /* Check the REX.W bit. */
3371 w
= (i
.rex
& REX_W
) ? 1 : 0;
3372 if (i
.tm
.opcode_modifier
.vexw
)
3374 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3377 /* If w is not set it means we are dealing with WIG instruction. */
3380 if (evexwig
== evexw1
)
3384 /* Encode the U bit. */
3385 implied_prefix
|= 0x4;
3387 /* The third byte of the EVEX prefix. */
3388 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3390 /* The fourth byte of the EVEX prefix. */
3391 /* The zeroing-masking bit. */
3392 if (i
.mask
&& i
.mask
->zeroing
)
3393 i
.vex
.bytes
[3] |= 0x80;
3395 /* Don't always set the broadcast bit if there is no RC. */
3398 /* Encode the vector length. */
3399 unsigned int vec_length
;
3401 switch (i
.tm
.opcode_modifier
.evex
)
3403 case EVEXLIG
: /* LL' is ignored */
3404 vec_length
= evexlig
<< 5;
3407 vec_length
= 0 << 5;
3410 vec_length
= 1 << 5;
3413 vec_length
= 2 << 5;
3419 i
.vex
.bytes
[3] |= vec_length
;
3420 /* Encode the broadcast bit. */
3422 i
.vex
.bytes
[3] |= 0x10;
3426 if (i
.rounding
->type
!= saeonly
)
3427 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3429 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3432 if (i
.mask
&& i
.mask
->mask
)
3433 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3437 process_immext (void)
3441 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3444 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3445 with an opcode suffix which is coded in the same place as an
3446 8-bit immediate field would be.
3447 Here we check those operands and remove them afterwards. */
3450 for (x
= 0; x
< i
.operands
; x
++)
3451 if (register_number (i
.op
[x
].regs
) != x
)
3452 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3453 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3459 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3461 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3462 suffix which is coded in the same place as an 8-bit immediate
3464 Here we check those operands and remove them afterwards. */
3467 if (i
.operands
!= 3)
3470 for (x
= 0; x
< 2; x
++)
3471 if (register_number (i
.op
[x
].regs
) != x
)
3472 goto bad_register_operand
;
3474 /* Check for third operand for mwaitx/monitorx insn. */
3475 if (register_number (i
.op
[x
].regs
)
3476 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3478 bad_register_operand
:
3479 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3480 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3487 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3488 which is coded in the same place as an 8-bit immediate field
3489 would be. Here we fake an 8-bit immediate operand from the
3490 opcode suffix stored in tm.extension_opcode.
3492 AVX instructions also use this encoding, for some of
3493 3 argument instructions. */
3495 gas_assert (i
.imm_operands
<= 1
3497 || ((i
.tm
.opcode_modifier
.vex
3498 || i
.tm
.opcode_modifier
.evex
)
3499 && i
.operands
<= 4)));
3501 exp
= &im_expressions
[i
.imm_operands
++];
3502 i
.op
[i
.operands
].imms
= exp
;
3503 i
.types
[i
.operands
] = imm8
;
3505 exp
->X_op
= O_constant
;
3506 exp
->X_add_number
= i
.tm
.extension_opcode
;
3507 i
.tm
.extension_opcode
= None
;
3514 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3519 as_bad (_("invalid instruction `%s' after `%s'"),
3520 i
.tm
.name
, i
.hle_prefix
);
3523 if (i
.prefix
[LOCK_PREFIX
])
3525 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3529 case HLEPrefixRelease
:
3530 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3532 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3536 if (i
.mem_operands
== 0
3537 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3539 as_bad (_("memory destination needed for instruction `%s'"
3540 " after `xrelease'"), i
.tm
.name
);
3547 /* This is the guts of the machine-dependent assembler. LINE points to a
3548 machine dependent instruction. This function is supposed to emit
3549 the frags/bytes it assembles to. */
3552 md_assemble (char *line
)
3555 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3556 const insn_template
*t
;
3558 /* Initialize globals. */
3559 memset (&i
, '\0', sizeof (i
));
3560 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3561 i
.reloc
[j
] = NO_RELOC
;
3562 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3563 memset (im_expressions
, '\0', sizeof (im_expressions
));
3564 save_stack_p
= save_stack
;
3566 /* First parse an instruction mnemonic & call i386_operand for the operands.
3567 We assume that the scrubber has arranged it so that line[0] is the valid
3568 start of a (possibly prefixed) mnemonic. */
3570 line
= parse_insn (line
, mnemonic
);
3573 mnem_suffix
= i
.suffix
;
3575 line
= parse_operands (line
, mnemonic
);
3577 xfree (i
.memop1_string
);
3578 i
.memop1_string
= NULL
;
3582 /* Now we've parsed the mnemonic into a set of templates, and have the
3583 operands at hand. */
3585 /* All intel opcodes have reversed operands except for "bound" and
3586 "enter". We also don't reverse intersegment "jmp" and "call"
3587 instructions with 2 immediate operands so that the immediate segment
3588 precedes the offset, as it does when in AT&T mode. */
3591 && (strcmp (mnemonic
, "bound") != 0)
3592 && (strcmp (mnemonic
, "invlpga") != 0)
3593 && !(operand_type_check (i
.types
[0], imm
)
3594 && operand_type_check (i
.types
[1], imm
)))
3597 /* The order of the immediates should be reversed
3598 for 2 immediates extrq and insertq instructions */
3599 if (i
.imm_operands
== 2
3600 && (strcmp (mnemonic
, "extrq") == 0
3601 || strcmp (mnemonic
, "insertq") == 0))
3602 swap_2_operands (0, 1);
3607 /* Don't optimize displacement for movabs since it only takes 64bit
3610 && i
.disp_encoding
!= disp_encoding_32bit
3611 && (flag_code
!= CODE_64BIT
3612 || strcmp (mnemonic
, "movabs") != 0))
3615 /* Next, we find a template that matches the given insn,
3616 making sure the overlap of the given operands types is consistent
3617 with the template operand types. */
3619 if (!(t
= match_template (mnem_suffix
)))
3622 if (sse_check
!= check_none
3623 && !i
.tm
.opcode_modifier
.noavx
3624 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3625 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3626 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3627 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3628 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3629 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3631 (sse_check
== check_warning
3633 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3636 /* Zap movzx and movsx suffix. The suffix has been set from
3637 "word ptr" or "byte ptr" on the source operand in Intel syntax
3638 or extracted from mnemonic in AT&T syntax. But we'll use
3639 the destination register to choose the suffix for encoding. */
3640 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3642 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3643 there is no suffix, the default will be byte extension. */
3644 if (i
.reg_operands
!= 2
3647 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3652 if (i
.tm
.opcode_modifier
.fwait
)
3653 if (!add_prefix (FWAIT_OPCODE
))
3656 /* Check if REP prefix is OK. */
3657 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3659 as_bad (_("invalid instruction `%s' after `%s'"),
3660 i
.tm
.name
, i
.rep_prefix
);
3664 /* Check for lock without a lockable instruction. Destination operand
3665 must be memory unless it is xchg (0x86). */
3666 if (i
.prefix
[LOCK_PREFIX
]
3667 && (!i
.tm
.opcode_modifier
.islockable
3668 || i
.mem_operands
== 0
3669 || (i
.tm
.base_opcode
!= 0x86
3670 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3672 as_bad (_("expecting lockable instruction after `lock'"));
3676 /* Check if HLE prefix is OK. */
3677 if (i
.hle_prefix
&& !check_hle ())
3680 /* Check BND prefix. */
3681 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3682 as_bad (_("expecting valid branch instruction after `bnd'"));
3684 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3686 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3687 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3688 else if (flag_code
!= CODE_16BIT
3689 ? i
.prefix
[ADDR_PREFIX
]
3690 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3691 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3694 /* Insert BND prefix. */
3696 && i
.tm
.opcode_modifier
.bndprefixok
3697 && !i
.prefix
[BND_PREFIX
])
3698 add_prefix (BND_PREFIX_OPCODE
);
3700 /* Check string instruction segment overrides. */
3701 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3703 if (!check_string ())
3705 i
.disp_operands
= 0;
3708 if (!process_suffix ())
3711 /* Update operand types. */
3712 for (j
= 0; j
< i
.operands
; j
++)
3713 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3715 /* Make still unresolved immediate matches conform to size of immediate
3716 given in i.suffix. */
3717 if (!finalize_imm ())
3720 if (i
.types
[0].bitfield
.imm1
)
3721 i
.imm_operands
= 0; /* kludge for shift insns. */
3723 /* We only need to check those implicit registers for instructions
3724 with 3 operands or less. */
3725 if (i
.operands
<= 3)
3726 for (j
= 0; j
< i
.operands
; j
++)
3727 if (i
.types
[j
].bitfield
.inoutportreg
3728 || i
.types
[j
].bitfield
.shiftcount
3729 || i
.types
[j
].bitfield
.acc
3730 || i
.types
[j
].bitfield
.floatacc
)
3733 /* ImmExt should be processed after SSE2AVX. */
3734 if (!i
.tm
.opcode_modifier
.sse2avx
3735 && i
.tm
.opcode_modifier
.immext
)
3738 /* For insns with operands there are more diddles to do to the opcode. */
3741 if (!process_operands ())
3744 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3746 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3747 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3750 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3752 if (flag_code
== CODE_16BIT
)
3754 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3759 if (i
.tm
.opcode_modifier
.vex
)
3760 build_vex_prefix (t
);
3762 build_evex_prefix ();
3765 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3766 instructions may define INT_OPCODE as well, so avoid this corner
3767 case for those instructions that use MODRM. */
3768 if (i
.tm
.base_opcode
== INT_OPCODE
3769 && !i
.tm
.opcode_modifier
.modrm
3770 && i
.op
[0].imms
->X_add_number
== 3)
3772 i
.tm
.base_opcode
= INT3_OPCODE
;
3776 if ((i
.tm
.opcode_modifier
.jump
3777 || i
.tm
.opcode_modifier
.jumpbyte
3778 || i
.tm
.opcode_modifier
.jumpdword
)
3779 && i
.op
[0].disps
->X_op
== O_constant
)
3781 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3782 the absolute address given by the constant. Since ix86 jumps and
3783 calls are pc relative, we need to generate a reloc. */
3784 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3785 i
.op
[0].disps
->X_op
= O_symbol
;
3788 if (i
.tm
.opcode_modifier
.rex64
)
3791 /* For 8 bit registers we need an empty rex prefix. Also if the
3792 instruction already has a prefix, we need to convert old
3793 registers to new ones. */
3795 if ((i
.types
[0].bitfield
.reg8
3796 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3797 || (i
.types
[1].bitfield
.reg8
3798 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3799 || ((i
.types
[0].bitfield
.reg8
3800 || i
.types
[1].bitfield
.reg8
)
3805 i
.rex
|= REX_OPCODE
;
3806 for (x
= 0; x
< 2; x
++)
3808 /* Look for 8 bit operand that uses old registers. */
3809 if (i
.types
[x
].bitfield
.reg8
3810 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3812 /* In case it is "hi" register, give up. */
3813 if (i
.op
[x
].regs
->reg_num
> 3)
3814 as_bad (_("can't encode register '%s%s' in an "
3815 "instruction requiring REX prefix."),
3816 register_prefix
, i
.op
[x
].regs
->reg_name
);
3818 /* Otherwise it is equivalent to the extended register.
3819 Since the encoding doesn't change this is merely
3820 cosmetic cleanup for debug output. */
3822 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3828 add_prefix (REX_OPCODE
| i
.rex
);
3830 /* We are ready to output the insn. */
3835 parse_insn (char *line
, char *mnemonic
)
3838 char *token_start
= l
;
3841 const insn_template
*t
;
3847 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3852 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3854 as_bad (_("no such instruction: `%s'"), token_start
);
3859 if (!is_space_char (*l
)
3860 && *l
!= END_OF_INSN
3862 || (*l
!= PREFIX_SEPARATOR
3865 as_bad (_("invalid character %s in mnemonic"),
3866 output_invalid (*l
));
3869 if (token_start
== l
)
3871 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3872 as_bad (_("expecting prefix; got nothing"));
3874 as_bad (_("expecting mnemonic; got nothing"));
3878 /* Look up instruction (or prefix) via hash table. */
3879 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3881 if (*l
!= END_OF_INSN
3882 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3883 && current_templates
3884 && current_templates
->start
->opcode_modifier
.isprefix
)
3886 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3888 as_bad ((flag_code
!= CODE_64BIT
3889 ? _("`%s' is only supported in 64-bit mode")
3890 : _("`%s' is not supported in 64-bit mode")),
3891 current_templates
->start
->name
);
3894 /* If we are in 16-bit mode, do not allow addr16 or data16.
3895 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3896 if ((current_templates
->start
->opcode_modifier
.size16
3897 || current_templates
->start
->opcode_modifier
.size32
)
3898 && flag_code
!= CODE_64BIT
3899 && (current_templates
->start
->opcode_modifier
.size32
3900 ^ (flag_code
== CODE_16BIT
)))
3902 as_bad (_("redundant %s prefix"),
3903 current_templates
->start
->name
);
3906 /* Add prefix, checking for repeated prefixes. */
3907 switch (add_prefix (current_templates
->start
->base_opcode
))
3912 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3913 i
.hle_prefix
= current_templates
->start
->name
;
3914 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3915 i
.bnd_prefix
= current_templates
->start
->name
;
3917 i
.rep_prefix
= current_templates
->start
->name
;
3922 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3929 if (!current_templates
)
3931 /* Check if we should swap operand or force 32bit displacement in
3933 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3935 else if (mnem_p
- 3 == dot_p
3938 i
.disp_encoding
= disp_encoding_8bit
;
3939 else if (mnem_p
- 4 == dot_p
3943 i
.disp_encoding
= disp_encoding_32bit
;
3948 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3951 if (!current_templates
)
3954 /* See if we can get a match by trimming off a suffix. */
3957 case WORD_MNEM_SUFFIX
:
3958 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3959 i
.suffix
= SHORT_MNEM_SUFFIX
;
3962 case BYTE_MNEM_SUFFIX
:
3963 case QWORD_MNEM_SUFFIX
:
3964 i
.suffix
= mnem_p
[-1];
3966 current_templates
= (const templates
*) hash_find (op_hash
,
3969 case SHORT_MNEM_SUFFIX
:
3970 case LONG_MNEM_SUFFIX
:
3973 i
.suffix
= mnem_p
[-1];
3975 current_templates
= (const templates
*) hash_find (op_hash
,
3984 if (intel_float_operand (mnemonic
) == 1)
3985 i
.suffix
= SHORT_MNEM_SUFFIX
;
3987 i
.suffix
= LONG_MNEM_SUFFIX
;
3989 current_templates
= (const templates
*) hash_find (op_hash
,
3994 if (!current_templates
)
3996 as_bad (_("no such instruction: `%s'"), token_start
);
4001 if (current_templates
->start
->opcode_modifier
.jump
4002 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4004 /* Check for a branch hint. We allow ",pt" and ",pn" for
4005 predict taken and predict not taken respectively.
4006 I'm not sure that branch hints actually do anything on loop
4007 and jcxz insns (JumpByte) for current Pentium4 chips. They
4008 may work in the future and it doesn't hurt to accept them
4010 if (l
[0] == ',' && l
[1] == 'p')
4014 if (!add_prefix (DS_PREFIX_OPCODE
))
4018 else if (l
[2] == 'n')
4020 if (!add_prefix (CS_PREFIX_OPCODE
))
4026 /* Any other comma loses. */
4029 as_bad (_("invalid character %s in mnemonic"),
4030 output_invalid (*l
));
4034 /* Check if instruction is supported on specified architecture. */
4036 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4038 supported
|= cpu_flags_match (t
);
4039 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4043 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4045 as_bad (flag_code
== CODE_64BIT
4046 ? _("`%s' is not supported in 64-bit mode")
4047 : _("`%s' is only supported in 64-bit mode"),
4048 current_templates
->start
->name
);
4051 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4053 as_bad (_("`%s' is not supported on `%s%s'"),
4054 current_templates
->start
->name
,
4055 cpu_arch_name
? cpu_arch_name
: default_arch
,
4056 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4061 if (!cpu_arch_flags
.bitfield
.cpui386
4062 && (flag_code
!= CODE_16BIT
))
4064 as_warn (_("use .code16 to ensure correct addressing mode"));
4071 parse_operands (char *l
, const char *mnemonic
)
4075 /* 1 if operand is pending after ','. */
4076 unsigned int expecting_operand
= 0;
4078 /* Non-zero if operand parens not balanced. */
4079 unsigned int paren_not_balanced
;
4081 while (*l
!= END_OF_INSN
)
4083 /* Skip optional white space before operand. */
4084 if (is_space_char (*l
))
4086 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4088 as_bad (_("invalid character %s before operand %d"),
4089 output_invalid (*l
),
4093 token_start
= l
; /* After white space. */
4094 paren_not_balanced
= 0;
4095 while (paren_not_balanced
|| *l
!= ',')
4097 if (*l
== END_OF_INSN
)
4099 if (paren_not_balanced
)
4102 as_bad (_("unbalanced parenthesis in operand %d."),
4105 as_bad (_("unbalanced brackets in operand %d."),
4110 break; /* we are done */
4112 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4114 as_bad (_("invalid character %s in operand %d"),
4115 output_invalid (*l
),
4122 ++paren_not_balanced
;
4124 --paren_not_balanced
;
4129 ++paren_not_balanced
;
4131 --paren_not_balanced
;
4135 if (l
!= token_start
)
4136 { /* Yes, we've read in another operand. */
4137 unsigned int operand_ok
;
4138 this_operand
= i
.operands
++;
4139 if (i
.operands
> MAX_OPERANDS
)
4141 as_bad (_("spurious operands; (%d operands/instruction max)"),
4145 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4146 /* Now parse operand adding info to 'i' as we go along. */
4147 END_STRING_AND_SAVE (l
);
4151 i386_intel_operand (token_start
,
4152 intel_float_operand (mnemonic
));
4154 operand_ok
= i386_att_operand (token_start
);
4156 RESTORE_END_STRING (l
);
4162 if (expecting_operand
)
4164 expecting_operand_after_comma
:
4165 as_bad (_("expecting operand after ','; got nothing"));
4170 as_bad (_("expecting operand before ','; got nothing"));
4175 /* Now *l must be either ',' or END_OF_INSN. */
4178 if (*++l
== END_OF_INSN
)
4180 /* Just skip it, if it's \n complain. */
4181 goto expecting_operand_after_comma
;
4183 expecting_operand
= 1;
4190 swap_2_operands (int xchg1
, int xchg2
)
4192 union i386_op temp_op
;
4193 i386_operand_type temp_type
;
4194 enum bfd_reloc_code_real temp_reloc
;
4196 temp_type
= i
.types
[xchg2
];
4197 i
.types
[xchg2
] = i
.types
[xchg1
];
4198 i
.types
[xchg1
] = temp_type
;
4199 temp_op
= i
.op
[xchg2
];
4200 i
.op
[xchg2
] = i
.op
[xchg1
];
4201 i
.op
[xchg1
] = temp_op
;
4202 temp_reloc
= i
.reloc
[xchg2
];
4203 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4204 i
.reloc
[xchg1
] = temp_reloc
;
4208 if (i
.mask
->operand
== xchg1
)
4209 i
.mask
->operand
= xchg2
;
4210 else if (i
.mask
->operand
== xchg2
)
4211 i
.mask
->operand
= xchg1
;
4215 if (i
.broadcast
->operand
== xchg1
)
4216 i
.broadcast
->operand
= xchg2
;
4217 else if (i
.broadcast
->operand
== xchg2
)
4218 i
.broadcast
->operand
= xchg1
;
4222 if (i
.rounding
->operand
== xchg1
)
4223 i
.rounding
->operand
= xchg2
;
4224 else if (i
.rounding
->operand
== xchg2
)
4225 i
.rounding
->operand
= xchg1
;
4230 swap_operands (void)
4236 swap_2_operands (1, i
.operands
- 2);
4240 swap_2_operands (0, i
.operands
- 1);
4246 if (i
.mem_operands
== 2)
4248 const seg_entry
*temp_seg
;
4249 temp_seg
= i
.seg
[0];
4250 i
.seg
[0] = i
.seg
[1];
4251 i
.seg
[1] = temp_seg
;
4255 /* Try to ensure constant immediates are represented in the smallest
4260 char guess_suffix
= 0;
4264 guess_suffix
= i
.suffix
;
4265 else if (i
.reg_operands
)
4267 /* Figure out a suffix from the last register operand specified.
4268 We can't do this properly yet, ie. excluding InOutPortReg,
4269 but the following works for instructions with immediates.
4270 In any case, we can't set i.suffix yet. */
4271 for (op
= i
.operands
; --op
>= 0;)
4272 if (i
.types
[op
].bitfield
.reg8
)
4274 guess_suffix
= BYTE_MNEM_SUFFIX
;
4277 else if (i
.types
[op
].bitfield
.reg16
)
4279 guess_suffix
= WORD_MNEM_SUFFIX
;
4282 else if (i
.types
[op
].bitfield
.reg32
)
4284 guess_suffix
= LONG_MNEM_SUFFIX
;
4287 else if (i
.types
[op
].bitfield
.reg64
)
4289 guess_suffix
= QWORD_MNEM_SUFFIX
;
4293 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4294 guess_suffix
= WORD_MNEM_SUFFIX
;
4296 for (op
= i
.operands
; --op
>= 0;)
4297 if (operand_type_check (i
.types
[op
], imm
))
4299 switch (i
.op
[op
].imms
->X_op
)
4302 /* If a suffix is given, this operand may be shortened. */
4303 switch (guess_suffix
)
4305 case LONG_MNEM_SUFFIX
:
4306 i
.types
[op
].bitfield
.imm32
= 1;
4307 i
.types
[op
].bitfield
.imm64
= 1;
4309 case WORD_MNEM_SUFFIX
:
4310 i
.types
[op
].bitfield
.imm16
= 1;
4311 i
.types
[op
].bitfield
.imm32
= 1;
4312 i
.types
[op
].bitfield
.imm32s
= 1;
4313 i
.types
[op
].bitfield
.imm64
= 1;
4315 case BYTE_MNEM_SUFFIX
:
4316 i
.types
[op
].bitfield
.imm8
= 1;
4317 i
.types
[op
].bitfield
.imm8s
= 1;
4318 i
.types
[op
].bitfield
.imm16
= 1;
4319 i
.types
[op
].bitfield
.imm32
= 1;
4320 i
.types
[op
].bitfield
.imm32s
= 1;
4321 i
.types
[op
].bitfield
.imm64
= 1;
4325 /* If this operand is at most 16 bits, convert it
4326 to a signed 16 bit number before trying to see
4327 whether it will fit in an even smaller size.
4328 This allows a 16-bit operand such as $0xffe0 to
4329 be recognised as within Imm8S range. */
4330 if ((i
.types
[op
].bitfield
.imm16
)
4331 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4333 i
.op
[op
].imms
->X_add_number
=
4334 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4337 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4338 if ((i
.types
[op
].bitfield
.imm32
)
4339 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4342 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4343 ^ ((offsetT
) 1 << 31))
4344 - ((offsetT
) 1 << 31));
4348 = operand_type_or (i
.types
[op
],
4349 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4351 /* We must avoid matching of Imm32 templates when 64bit
4352 only immediate is available. */
4353 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4354 i
.types
[op
].bitfield
.imm32
= 0;
4361 /* Symbols and expressions. */
4363 /* Convert symbolic operand to proper sizes for matching, but don't
4364 prevent matching a set of insns that only supports sizes other
4365 than those matching the insn suffix. */
4367 i386_operand_type mask
, allowed
;
4368 const insn_template
*t
;
4370 operand_type_set (&mask
, 0);
4371 operand_type_set (&allowed
, 0);
4373 for (t
= current_templates
->start
;
4374 t
< current_templates
->end
;
4376 allowed
= operand_type_or (allowed
,
4377 t
->operand_types
[op
]);
4378 switch (guess_suffix
)
4380 case QWORD_MNEM_SUFFIX
:
4381 mask
.bitfield
.imm64
= 1;
4382 mask
.bitfield
.imm32s
= 1;
4384 case LONG_MNEM_SUFFIX
:
4385 mask
.bitfield
.imm32
= 1;
4387 case WORD_MNEM_SUFFIX
:
4388 mask
.bitfield
.imm16
= 1;
4390 case BYTE_MNEM_SUFFIX
:
4391 mask
.bitfield
.imm8
= 1;
4396 allowed
= operand_type_and (mask
, allowed
);
4397 if (!operand_type_all_zero (&allowed
))
4398 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4405 /* Try to use the smallest displacement type too. */
4407 optimize_disp (void)
4411 for (op
= i
.operands
; --op
>= 0;)
4412 if (operand_type_check (i
.types
[op
], disp
))
4414 if (i
.op
[op
].disps
->X_op
== O_constant
)
4416 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4418 if (i
.types
[op
].bitfield
.disp16
4419 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4421 /* If this operand is at most 16 bits, convert
4422 to a signed 16 bit number and don't use 64bit
4424 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4425 i
.types
[op
].bitfield
.disp64
= 0;
4428 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4429 if (i
.types
[op
].bitfield
.disp32
4430 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4432 /* If this operand is at most 32 bits, convert
4433 to a signed 32 bit number and don't use 64bit
4435 op_disp
&= (((offsetT
) 2 << 31) - 1);
4436 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4437 i
.types
[op
].bitfield
.disp64
= 0;
4440 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4442 i
.types
[op
].bitfield
.disp8
= 0;
4443 i
.types
[op
].bitfield
.disp16
= 0;
4444 i
.types
[op
].bitfield
.disp32
= 0;
4445 i
.types
[op
].bitfield
.disp32s
= 0;
4446 i
.types
[op
].bitfield
.disp64
= 0;
4450 else if (flag_code
== CODE_64BIT
)
4452 if (fits_in_signed_long (op_disp
))
4454 i
.types
[op
].bitfield
.disp64
= 0;
4455 i
.types
[op
].bitfield
.disp32s
= 1;
4457 if (i
.prefix
[ADDR_PREFIX
]
4458 && fits_in_unsigned_long (op_disp
))
4459 i
.types
[op
].bitfield
.disp32
= 1;
4461 if ((i
.types
[op
].bitfield
.disp32
4462 || i
.types
[op
].bitfield
.disp32s
4463 || i
.types
[op
].bitfield
.disp16
)
4464 && fits_in_signed_byte (op_disp
))
4465 i
.types
[op
].bitfield
.disp8
= 1;
4467 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4468 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4470 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4471 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4472 i
.types
[op
].bitfield
.disp8
= 0;
4473 i
.types
[op
].bitfield
.disp16
= 0;
4474 i
.types
[op
].bitfield
.disp32
= 0;
4475 i
.types
[op
].bitfield
.disp32s
= 0;
4476 i
.types
[op
].bitfield
.disp64
= 0;
4479 /* We only support 64bit displacement on constants. */
4480 i
.types
[op
].bitfield
.disp64
= 0;
4484 /* Check if operands are valid for the instruction. */
4487 check_VecOperands (const insn_template
*t
)
4491 /* Without VSIB byte, we can't have a vector register for index. */
4492 if (!t
->opcode_modifier
.vecsib
4494 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4495 || i
.index_reg
->reg_type
.bitfield
.regymm
4496 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4498 i
.error
= unsupported_vector_index_register
;
4502 /* Check if default mask is allowed. */
4503 if (t
->opcode_modifier
.nodefmask
4504 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4506 i
.error
= no_default_mask
;
4510 /* For VSIB byte, we need a vector register for index, and all vector
4511 registers must be distinct. */
4512 if (t
->opcode_modifier
.vecsib
)
4515 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4516 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4517 || (t
->opcode_modifier
.vecsib
== VecSIB256
4518 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4519 || (t
->opcode_modifier
.vecsib
== VecSIB512
4520 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4522 i
.error
= invalid_vsib_address
;
4526 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4527 if (i
.reg_operands
== 2 && !i
.mask
)
4529 gas_assert (i
.types
[0].bitfield
.regxmm
4530 || i
.types
[0].bitfield
.regymm
);
4531 gas_assert (i
.types
[2].bitfield
.regxmm
4532 || i
.types
[2].bitfield
.regymm
);
4533 if (operand_check
== check_none
)
4535 if (register_number (i
.op
[0].regs
)
4536 != register_number (i
.index_reg
)
4537 && register_number (i
.op
[2].regs
)
4538 != register_number (i
.index_reg
)
4539 && register_number (i
.op
[0].regs
)
4540 != register_number (i
.op
[2].regs
))
4542 if (operand_check
== check_error
)
4544 i
.error
= invalid_vector_register_set
;
4547 as_warn (_("mask, index, and destination registers should be distinct"));
4549 else if (i
.reg_operands
== 1 && i
.mask
)
4551 if ((i
.types
[1].bitfield
.regymm
4552 || i
.types
[1].bitfield
.regzmm
)
4553 && (register_number (i
.op
[1].regs
)
4554 == register_number (i
.index_reg
)))
4556 if (operand_check
== check_error
)
4558 i
.error
= invalid_vector_register_set
;
4561 if (operand_check
!= check_none
)
4562 as_warn (_("index and destination registers should be distinct"));
4567 /* Check if broadcast is supported by the instruction and is applied
4568 to the memory operand. */
4571 int broadcasted_opnd_size
;
4573 /* Check if specified broadcast is supported in this instruction,
4574 and it's applied to memory operand of DWORD or QWORD type,
4575 depending on VecESize. */
4576 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4577 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4578 || (t
->opcode_modifier
.vecesize
== 0
4579 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4580 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4581 || (t
->opcode_modifier
.vecesize
== 1
4582 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4583 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4586 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4587 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4588 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4589 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4590 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4591 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4592 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4593 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4594 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4598 if ((broadcasted_opnd_size
== 256
4599 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4600 || (broadcasted_opnd_size
== 512
4601 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4604 i
.error
= unsupported_broadcast
;
4608 /* If broadcast is supported in this instruction, we need to check if
4609 operand of one-element size isn't specified without broadcast. */
4610 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4612 /* Find memory operand. */
4613 for (op
= 0; op
< i
.operands
; op
++)
4614 if (operand_type_check (i
.types
[op
], anymem
))
4616 gas_assert (op
< i
.operands
);
4617 /* Check size of the memory operand. */
4618 if ((t
->opcode_modifier
.vecesize
== 0
4619 && i
.types
[op
].bitfield
.dword
)
4620 || (t
->opcode_modifier
.vecesize
== 1
4621 && i
.types
[op
].bitfield
.qword
))
4623 i
.error
= broadcast_needed
;
4628 /* Check if requested masking is supported. */
4630 && (!t
->opcode_modifier
.masking
4632 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4634 i
.error
= unsupported_masking
;
4638 /* Check if masking is applied to dest operand. */
4639 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4641 i
.error
= mask_not_on_destination
;
4648 if ((i
.rounding
->type
!= saeonly
4649 && !t
->opcode_modifier
.staticrounding
)
4650 || (i
.rounding
->type
== saeonly
4651 && (t
->opcode_modifier
.staticrounding
4652 || !t
->opcode_modifier
.sae
)))
4654 i
.error
= unsupported_rc_sae
;
4657 /* If the instruction has several immediate operands and one of
4658 them is rounding, the rounding operand should be the last
4659 immediate operand. */
4660 if (i
.imm_operands
> 1
4661 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4663 i
.error
= rc_sae_operand_not_last_imm
;
4668 /* Check vector Disp8 operand. */
4669 if (t
->opcode_modifier
.disp8memshift
)
4672 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4674 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4676 for (op
= 0; op
< i
.operands
; op
++)
4677 if (operand_type_check (i
.types
[op
], disp
)
4678 && i
.op
[op
].disps
->X_op
== O_constant
)
4680 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4682 = (i
.disp_encoding
!= disp_encoding_32bit
4683 && fits_in_vec_disp8 (value
));
4684 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4687 i
.types
[op
].bitfield
.vec_disp8
= 1;
4690 /* Vector insn can only have Vec_Disp8/Disp32 in
4691 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4693 i
.types
[op
].bitfield
.disp8
= 0;
4694 if (flag_code
!= CODE_16BIT
)
4695 i
.types
[op
].bitfield
.disp16
= 0;
4698 else if (flag_code
!= CODE_16BIT
)
4700 /* One form of this instruction supports vector Disp8.
4701 Try vector Disp8 if we need to use Disp32. */
4702 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4704 i
.error
= try_vector_disp8
;
4716 /* Check if operands are valid for the instruction. Update VEX
4720 VEX_check_operands (const insn_template
*t
)
4722 /* VREX is only valid with EVEX prefix. */
4723 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4725 i
.error
= invalid_register_operand
;
4729 if (!t
->opcode_modifier
.vex
)
4732 /* Only check VEX_Imm4, which must be the first operand. */
4733 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4735 if (i
.op
[0].imms
->X_op
!= O_constant
4736 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4742 /* Turn off Imm8 so that update_imm won't complain. */
4743 i
.types
[0] = vec_imm4
;
4749 static const insn_template
*
4750 match_template (char mnem_suffix
)
4752 /* Points to template once we've found it. */
4753 const insn_template
*t
;
4754 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4755 i386_operand_type overlap4
;
4756 unsigned int found_reverse_match
;
4757 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4758 i386_operand_type operand_types
[MAX_OPERANDS
];
4759 int addr_prefix_disp
;
4761 unsigned int found_cpu_match
;
4762 unsigned int check_register
;
4763 enum i386_error specific_error
= 0;
4765 #if MAX_OPERANDS != 5
4766 # error "MAX_OPERANDS must be 5."
4769 found_reverse_match
= 0;
4770 addr_prefix_disp
= -1;
4772 memset (&suffix_check
, 0, sizeof (suffix_check
));
4773 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4774 suffix_check
.no_bsuf
= 1;
4775 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4776 suffix_check
.no_wsuf
= 1;
4777 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4778 suffix_check
.no_ssuf
= 1;
4779 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4780 suffix_check
.no_lsuf
= 1;
4781 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4782 suffix_check
.no_qsuf
= 1;
4783 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4784 suffix_check
.no_ldsuf
= 1;
4786 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4789 switch (mnem_suffix
)
4791 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4792 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4793 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4794 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4795 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4799 /* Must have right number of operands. */
4800 i
.error
= number_of_operands_mismatch
;
4802 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4804 addr_prefix_disp
= -1;
4806 if (i
.operands
!= t
->operands
)
4809 /* Check processor support. */
4810 i
.error
= unsupported
;
4811 found_cpu_match
= (cpu_flags_match (t
)
4812 == CPU_FLAGS_PERFECT_MATCH
);
4813 if (!found_cpu_match
)
4816 /* Check old gcc support. */
4817 i
.error
= old_gcc_only
;
4818 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4821 /* Check AT&T mnemonic. */
4822 i
.error
= unsupported_with_intel_mnemonic
;
4823 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4826 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4827 i
.error
= unsupported_syntax
;
4828 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4829 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4830 || (intel64
&& t
->opcode_modifier
.amd64
)
4831 || (!intel64
&& t
->opcode_modifier
.intel64
))
4834 /* Check the suffix, except for some instructions in intel mode. */
4835 i
.error
= invalid_instruction_suffix
;
4836 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4837 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4838 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4839 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4840 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4841 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4842 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4844 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4845 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4846 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4847 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4848 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4849 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4850 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4853 if (!operand_size_match (t
))
4856 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4857 operand_types
[j
] = t
->operand_types
[j
];
4859 /* In general, don't allow 64-bit operands in 32-bit mode. */
4860 if (i
.suffix
== QWORD_MNEM_SUFFIX
4861 && flag_code
!= CODE_64BIT
4863 ? (!t
->opcode_modifier
.ignoresize
4864 && !intel_float_operand (t
->name
))
4865 : intel_float_operand (t
->name
) != 2)
4866 && ((!operand_types
[0].bitfield
.regmmx
4867 && !operand_types
[0].bitfield
.regxmm
4868 && !operand_types
[0].bitfield
.regymm
4869 && !operand_types
[0].bitfield
.regzmm
)
4870 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4871 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4872 && operand_types
[t
->operands
> 1].bitfield
.regymm
4873 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4874 && (t
->base_opcode
!= 0x0fc7
4875 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4878 /* In general, don't allow 32-bit operands on pre-386. */
4879 else if (i
.suffix
== LONG_MNEM_SUFFIX
4880 && !cpu_arch_flags
.bitfield
.cpui386
4882 ? (!t
->opcode_modifier
.ignoresize
4883 && !intel_float_operand (t
->name
))
4884 : intel_float_operand (t
->name
) != 2)
4885 && ((!operand_types
[0].bitfield
.regmmx
4886 && !operand_types
[0].bitfield
.regxmm
)
4887 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4888 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4891 /* Do not verify operands when there are none. */
4895 /* We've found a match; break out of loop. */
4899 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4900 into Disp32/Disp16/Disp32 operand. */
4901 if (i
.prefix
[ADDR_PREFIX
] != 0)
4903 /* There should be only one Disp operand. */
4907 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4909 if (operand_types
[j
].bitfield
.disp16
)
4911 addr_prefix_disp
= j
;
4912 operand_types
[j
].bitfield
.disp32
= 1;
4913 operand_types
[j
].bitfield
.disp16
= 0;
4919 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4921 if (operand_types
[j
].bitfield
.disp32
)
4923 addr_prefix_disp
= j
;
4924 operand_types
[j
].bitfield
.disp32
= 0;
4925 operand_types
[j
].bitfield
.disp16
= 1;
4931 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4933 if (operand_types
[j
].bitfield
.disp64
)
4935 addr_prefix_disp
= j
;
4936 operand_types
[j
].bitfield
.disp64
= 0;
4937 operand_types
[j
].bitfield
.disp32
= 1;
4945 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4946 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4949 /* We check register size if needed. */
4950 check_register
= t
->opcode_modifier
.checkregsize
;
4951 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4952 switch (t
->operands
)
4955 if (!operand_type_match (overlap0
, i
.types
[0]))
4959 /* xchg %eax, %eax is a special case. It is an aliase for nop
4960 only in 32bit mode and we can use opcode 0x90. In 64bit
4961 mode, we can't use 0x90 for xchg %eax, %eax since it should
4962 zero-extend %eax to %rax. */
4963 if (flag_code
== CODE_64BIT
4964 && t
->base_opcode
== 0x90
4965 && operand_type_equal (&i
.types
[0], &acc32
)
4966 && operand_type_equal (&i
.types
[1], &acc32
))
4970 /* If we swap operand in encoding, we either match
4971 the next one or reverse direction of operands. */
4972 if (t
->opcode_modifier
.s
)
4974 else if (t
->opcode_modifier
.d
)
4980 /* If we swap operand in encoding, we match the next one. */
4981 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4986 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4987 if (!operand_type_match (overlap0
, i
.types
[0])
4988 || !operand_type_match (overlap1
, i
.types
[1])
4990 && !operand_type_register_match (overlap0
, i
.types
[0],
4992 overlap1
, i
.types
[1],
4995 /* Check if other direction is valid ... */
4996 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5000 /* Try reversing direction of operands. */
5001 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5002 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5003 if (!operand_type_match (overlap0
, i
.types
[0])
5004 || !operand_type_match (overlap1
, i
.types
[1])
5006 && !operand_type_register_match (overlap0
,
5013 /* Does not match either direction. */
5016 /* found_reverse_match holds which of D or FloatDR
5018 if (t
->opcode_modifier
.d
)
5019 found_reverse_match
= Opcode_D
;
5020 else if (t
->opcode_modifier
.floatd
)
5021 found_reverse_match
= Opcode_FloatD
;
5023 found_reverse_match
= 0;
5024 if (t
->opcode_modifier
.floatr
)
5025 found_reverse_match
|= Opcode_FloatR
;
5029 /* Found a forward 2 operand match here. */
5030 switch (t
->operands
)
5033 overlap4
= operand_type_and (i
.types
[4],
5037 overlap3
= operand_type_and (i
.types
[3],
5041 overlap2
= operand_type_and (i
.types
[2],
5046 switch (t
->operands
)
5049 if (!operand_type_match (overlap4
, i
.types
[4])
5050 || !operand_type_register_match (overlap3
,
5059 if (!operand_type_match (overlap3
, i
.types
[3])
5061 && !operand_type_register_match (overlap2
,
5070 /* Here we make use of the fact that there are no
5071 reverse match 3 operand instructions, and all 3
5072 operand instructions only need to be checked for
5073 register consistency between operands 2 and 3. */
5074 if (!operand_type_match (overlap2
, i
.types
[2])
5076 && !operand_type_register_match (overlap1
,
5086 /* Found either forward/reverse 2, 3 or 4 operand match here:
5087 slip through to break. */
5089 if (!found_cpu_match
)
5091 found_reverse_match
= 0;
5095 /* Check if vector and VEX operands are valid. */
5096 if (check_VecOperands (t
) || VEX_check_operands (t
))
5098 specific_error
= i
.error
;
5102 /* We've found a match; break out of loop. */
5106 if (t
== current_templates
->end
)
5108 /* We found no match. */
5109 const char *err_msg
;
5110 switch (specific_error
? specific_error
: i
.error
)
5114 case operand_size_mismatch
:
5115 err_msg
= _("operand size mismatch");
5117 case operand_type_mismatch
:
5118 err_msg
= _("operand type mismatch");
5120 case register_type_mismatch
:
5121 err_msg
= _("register type mismatch");
5123 case number_of_operands_mismatch
:
5124 err_msg
= _("number of operands mismatch");
5126 case invalid_instruction_suffix
:
5127 err_msg
= _("invalid instruction suffix");
5130 err_msg
= _("constant doesn't fit in 4 bits");
5133 err_msg
= _("only supported with old gcc");
5135 case unsupported_with_intel_mnemonic
:
5136 err_msg
= _("unsupported with Intel mnemonic");
5138 case unsupported_syntax
:
5139 err_msg
= _("unsupported syntax");
5142 as_bad (_("unsupported instruction `%s'"),
5143 current_templates
->start
->name
);
5145 case invalid_vsib_address
:
5146 err_msg
= _("invalid VSIB address");
5148 case invalid_vector_register_set
:
5149 err_msg
= _("mask, index, and destination registers must be distinct");
5151 case unsupported_vector_index_register
:
5152 err_msg
= _("unsupported vector index register");
5154 case unsupported_broadcast
:
5155 err_msg
= _("unsupported broadcast");
5157 case broadcast_not_on_src_operand
:
5158 err_msg
= _("broadcast not on source memory operand");
5160 case broadcast_needed
:
5161 err_msg
= _("broadcast is needed for operand of such type");
5163 case unsupported_masking
:
5164 err_msg
= _("unsupported masking");
5166 case mask_not_on_destination
:
5167 err_msg
= _("mask not on destination operand");
5169 case no_default_mask
:
5170 err_msg
= _("default mask isn't allowed");
5172 case unsupported_rc_sae
:
5173 err_msg
= _("unsupported static rounding/sae");
5175 case rc_sae_operand_not_last_imm
:
5177 err_msg
= _("RC/SAE operand must precede immediate operands");
5179 err_msg
= _("RC/SAE operand must follow immediate operands");
5181 case invalid_register_operand
:
5182 err_msg
= _("invalid register operand");
5185 as_bad (_("%s for `%s'"), err_msg
,
5186 current_templates
->start
->name
);
5190 if (!quiet_warnings
)
5193 && (i
.types
[0].bitfield
.jumpabsolute
5194 != operand_types
[0].bitfield
.jumpabsolute
))
5196 as_warn (_("indirect %s without `*'"), t
->name
);
5199 if (t
->opcode_modifier
.isprefix
5200 && t
->opcode_modifier
.ignoresize
)
5202 /* Warn them that a data or address size prefix doesn't
5203 affect assembly of the next line of code. */
5204 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5208 /* Copy the template we found. */
5211 if (addr_prefix_disp
!= -1)
5212 i
.tm
.operand_types
[addr_prefix_disp
]
5213 = operand_types
[addr_prefix_disp
];
5215 if (found_reverse_match
)
5217 /* If we found a reverse match we must alter the opcode
5218 direction bit. found_reverse_match holds bits to change
5219 (different for int & float insns). */
5221 i
.tm
.base_opcode
^= found_reverse_match
;
5223 i
.tm
.operand_types
[0] = operand_types
[1];
5224 i
.tm
.operand_types
[1] = operand_types
[0];
5233 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5234 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5236 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5238 as_bad (_("`%s' operand %d must use `%ses' segment"),
5244 /* There's only ever one segment override allowed per instruction.
5245 This instruction possibly has a legal segment override on the
5246 second operand, so copy the segment to where non-string
5247 instructions store it, allowing common code. */
5248 i
.seg
[0] = i
.seg
[1];
5250 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5252 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5254 as_bad (_("`%s' operand %d must use `%ses' segment"),
5265 process_suffix (void)
5267 /* If matched instruction specifies an explicit instruction mnemonic
5269 if (i
.tm
.opcode_modifier
.size16
)
5270 i
.suffix
= WORD_MNEM_SUFFIX
;
5271 else if (i
.tm
.opcode_modifier
.size32
)
5272 i
.suffix
= LONG_MNEM_SUFFIX
;
5273 else if (i
.tm
.opcode_modifier
.size64
)
5274 i
.suffix
= QWORD_MNEM_SUFFIX
;
5275 else if (i
.reg_operands
)
5277 /* If there's no instruction mnemonic suffix we try to invent one
5278 based on register operands. */
5281 /* We take i.suffix from the last register operand specified,
5282 Destination register type is more significant than source
5283 register type. crc32 in SSE4.2 prefers source register
5285 if (i
.tm
.base_opcode
== 0xf20f38f1)
5287 if (i
.types
[0].bitfield
.reg16
)
5288 i
.suffix
= WORD_MNEM_SUFFIX
;
5289 else if (i
.types
[0].bitfield
.reg32
)
5290 i
.suffix
= LONG_MNEM_SUFFIX
;
5291 else if (i
.types
[0].bitfield
.reg64
)
5292 i
.suffix
= QWORD_MNEM_SUFFIX
;
5294 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5296 if (i
.types
[0].bitfield
.reg8
)
5297 i
.suffix
= BYTE_MNEM_SUFFIX
;
5304 if (i
.tm
.base_opcode
== 0xf20f38f1
5305 || i
.tm
.base_opcode
== 0xf20f38f0)
5307 /* We have to know the operand size for crc32. */
5308 as_bad (_("ambiguous memory operand size for `%s`"),
5313 for (op
= i
.operands
; --op
>= 0;)
5314 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5316 if (i
.types
[op
].bitfield
.reg8
)
5318 i
.suffix
= BYTE_MNEM_SUFFIX
;
5321 else if (i
.types
[op
].bitfield
.reg16
)
5323 i
.suffix
= WORD_MNEM_SUFFIX
;
5326 else if (i
.types
[op
].bitfield
.reg32
)
5328 i
.suffix
= LONG_MNEM_SUFFIX
;
5331 else if (i
.types
[op
].bitfield
.reg64
)
5333 i
.suffix
= QWORD_MNEM_SUFFIX
;
5339 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5342 && i
.tm
.opcode_modifier
.ignoresize
5343 && i
.tm
.opcode_modifier
.no_bsuf
)
5345 else if (!check_byte_reg ())
5348 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5351 && i
.tm
.opcode_modifier
.ignoresize
5352 && i
.tm
.opcode_modifier
.no_lsuf
)
5354 else if (!check_long_reg ())
5357 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5360 && i
.tm
.opcode_modifier
.ignoresize
5361 && i
.tm
.opcode_modifier
.no_qsuf
)
5363 else if (!check_qword_reg ())
5366 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5369 && i
.tm
.opcode_modifier
.ignoresize
5370 && i
.tm
.opcode_modifier
.no_wsuf
)
5372 else if (!check_word_reg ())
5375 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5376 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5377 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5379 /* Skip if the instruction has x/y/z suffix. match_template
5380 should check if it is a valid suffix. */
5382 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5383 /* Do nothing if the instruction is going to ignore the prefix. */
5388 else if (i
.tm
.opcode_modifier
.defaultsize
5390 /* exclude fldenv/frstor/fsave/fstenv */
5391 && i
.tm
.opcode_modifier
.no_ssuf
)
5393 i
.suffix
= stackop_size
;
5395 else if (intel_syntax
5397 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5398 || i
.tm
.opcode_modifier
.jumpbyte
5399 || i
.tm
.opcode_modifier
.jumpintersegment
5400 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5401 && i
.tm
.extension_opcode
<= 3)))
5406 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5408 i
.suffix
= QWORD_MNEM_SUFFIX
;
5413 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5414 i
.suffix
= LONG_MNEM_SUFFIX
;
5417 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5418 i
.suffix
= WORD_MNEM_SUFFIX
;
5427 if (i
.tm
.opcode_modifier
.w
)
5429 as_bad (_("no instruction mnemonic suffix given and "
5430 "no register operands; can't size instruction"));
5436 unsigned int suffixes
;
5438 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5439 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5441 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5443 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5445 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5447 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5450 /* There are more than suffix matches. */
5451 if (i
.tm
.opcode_modifier
.w
5452 || ((suffixes
& (suffixes
- 1))
5453 && !i
.tm
.opcode_modifier
.defaultsize
5454 && !i
.tm
.opcode_modifier
.ignoresize
))
5456 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5462 /* Change the opcode based on the operand size given by i.suffix;
5463 We don't need to change things for byte insns. */
5466 && i
.suffix
!= BYTE_MNEM_SUFFIX
5467 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5468 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5469 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5471 /* It's not a byte, select word/dword operation. */
5472 if (i
.tm
.opcode_modifier
.w
)
5474 if (i
.tm
.opcode_modifier
.shortform
)
5475 i
.tm
.base_opcode
|= 8;
5477 i
.tm
.base_opcode
|= 1;
5480 /* Now select between word & dword operations via the operand
5481 size prefix, except for instructions that will ignore this
5483 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5485 /* The address size override prefix changes the size of the
5487 if ((flag_code
== CODE_32BIT
5488 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5489 || (flag_code
!= CODE_32BIT
5490 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5491 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5494 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5495 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5496 && !i
.tm
.opcode_modifier
.ignoresize
5497 && !i
.tm
.opcode_modifier
.floatmf
5498 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5499 || (flag_code
== CODE_64BIT
5500 && i
.tm
.opcode_modifier
.jumpbyte
)))
5502 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5504 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5505 prefix
= ADDR_PREFIX_OPCODE
;
5507 if (!add_prefix (prefix
))
5511 /* Set mode64 for an operand. */
5512 if (i
.suffix
== QWORD_MNEM_SUFFIX
5513 && flag_code
== CODE_64BIT
5514 && !i
.tm
.opcode_modifier
.norex64
)
5516 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5517 need rex64. cmpxchg8b is also a special case. */
5518 if (! (i
.operands
== 2
5519 && i
.tm
.base_opcode
== 0x90
5520 && i
.tm
.extension_opcode
== None
5521 && operand_type_equal (&i
.types
[0], &acc64
)
5522 && operand_type_equal (&i
.types
[1], &acc64
))
5523 && ! (i
.operands
== 1
5524 && i
.tm
.base_opcode
== 0xfc7
5525 && i
.tm
.extension_opcode
== 1
5526 && !operand_type_check (i
.types
[0], reg
)
5527 && operand_type_check (i
.types
[0], anymem
)))
5531 /* Size floating point instruction. */
5532 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5533 if (i
.tm
.opcode_modifier
.floatmf
)
5534 i
.tm
.base_opcode
^= 4;
5541 check_byte_reg (void)
5545 for (op
= i
.operands
; --op
>= 0;)
5547 /* If this is an eight bit register, it's OK. If it's the 16 or
5548 32 bit version of an eight bit register, we will just use the
5549 low portion, and that's OK too. */
5550 if (i
.types
[op
].bitfield
.reg8
)
5553 /* I/O port address operands are OK too. */
5554 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5557 /* crc32 doesn't generate this warning. */
5558 if (i
.tm
.base_opcode
== 0xf20f38f0)
5561 if ((i
.types
[op
].bitfield
.reg16
5562 || i
.types
[op
].bitfield
.reg32
5563 || i
.types
[op
].bitfield
.reg64
)
5564 && i
.op
[op
].regs
->reg_num
< 4
5565 /* Prohibit these changes in 64bit mode, since the lowering
5566 would be more complicated. */
5567 && flag_code
!= CODE_64BIT
)
5569 #if REGISTER_WARNINGS
5570 if (!quiet_warnings
)
5571 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5573 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5574 ? REGNAM_AL
- REGNAM_AX
5575 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5577 i
.op
[op
].regs
->reg_name
,
5582 /* Any other register is bad. */
5583 if (i
.types
[op
].bitfield
.reg16
5584 || i
.types
[op
].bitfield
.reg32
5585 || i
.types
[op
].bitfield
.reg64
5586 || i
.types
[op
].bitfield
.regmmx
5587 || i
.types
[op
].bitfield
.regxmm
5588 || i
.types
[op
].bitfield
.regymm
5589 || i
.types
[op
].bitfield
.regzmm
5590 || i
.types
[op
].bitfield
.sreg2
5591 || i
.types
[op
].bitfield
.sreg3
5592 || i
.types
[op
].bitfield
.control
5593 || i
.types
[op
].bitfield
.debug
5594 || i
.types
[op
].bitfield
.test
5595 || i
.types
[op
].bitfield
.floatreg
5596 || i
.types
[op
].bitfield
.floatacc
)
5598 as_bad (_("`%s%s' not allowed with `%s%c'"),
5600 i
.op
[op
].regs
->reg_name
,
5610 check_long_reg (void)
5614 for (op
= i
.operands
; --op
>= 0;)
5615 /* Reject eight bit registers, except where the template requires
5616 them. (eg. movzb) */
5617 if (i
.types
[op
].bitfield
.reg8
5618 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5619 || i
.tm
.operand_types
[op
].bitfield
.reg32
5620 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5622 as_bad (_("`%s%s' not allowed with `%s%c'"),
5624 i
.op
[op
].regs
->reg_name
,
5629 /* Warn if the e prefix on a general reg is missing. */
5630 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5631 && i
.types
[op
].bitfield
.reg16
5632 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5633 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5635 /* Prohibit these changes in the 64bit mode, since the
5636 lowering is more complicated. */
5637 if (flag_code
== CODE_64BIT
)
5639 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5640 register_prefix
, i
.op
[op
].regs
->reg_name
,
5644 #if REGISTER_WARNINGS
5645 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5647 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5648 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5651 /* Warn if the r prefix on a general reg is present. */
5652 else if (i
.types
[op
].bitfield
.reg64
5653 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5654 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5657 && i
.tm
.opcode_modifier
.toqword
5658 && !i
.types
[0].bitfield
.regxmm
)
5660 /* Convert to QWORD. We want REX byte. */
5661 i
.suffix
= QWORD_MNEM_SUFFIX
;
5665 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5666 register_prefix
, i
.op
[op
].regs
->reg_name
,
5675 check_qword_reg (void)
5679 for (op
= i
.operands
; --op
>= 0; )
5680 /* Reject eight bit registers, except where the template requires
5681 them. (eg. movzb) */
5682 if (i
.types
[op
].bitfield
.reg8
5683 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5684 || i
.tm
.operand_types
[op
].bitfield
.reg32
5685 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5687 as_bad (_("`%s%s' not allowed with `%s%c'"),
5689 i
.op
[op
].regs
->reg_name
,
5694 /* Warn if the r prefix on a general reg is missing. */
5695 else if ((i
.types
[op
].bitfield
.reg16
5696 || i
.types
[op
].bitfield
.reg32
)
5697 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5698 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5700 /* Prohibit these changes in the 64bit mode, since the
5701 lowering is more complicated. */
5703 && i
.tm
.opcode_modifier
.todword
5704 && !i
.types
[0].bitfield
.regxmm
)
5706 /* Convert to DWORD. We don't want REX byte. */
5707 i
.suffix
= LONG_MNEM_SUFFIX
;
5711 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5712 register_prefix
, i
.op
[op
].regs
->reg_name
,
5721 check_word_reg (void)
5724 for (op
= i
.operands
; --op
>= 0;)
5725 /* Reject eight bit registers, except where the template requires
5726 them. (eg. movzb) */
5727 if (i
.types
[op
].bitfield
.reg8
5728 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5729 || i
.tm
.operand_types
[op
].bitfield
.reg32
5730 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5732 as_bad (_("`%s%s' not allowed with `%s%c'"),
5734 i
.op
[op
].regs
->reg_name
,
5739 /* Warn if the e or r prefix on a general reg is present. */
5740 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5741 && (i
.types
[op
].bitfield
.reg32
5742 || i
.types
[op
].bitfield
.reg64
)
5743 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5744 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5746 /* Prohibit these changes in the 64bit mode, since the
5747 lowering is more complicated. */
5748 if (flag_code
== CODE_64BIT
)
5750 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5751 register_prefix
, i
.op
[op
].regs
->reg_name
,
5755 #if REGISTER_WARNINGS
5756 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5758 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5759 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5766 update_imm (unsigned int j
)
5768 i386_operand_type overlap
= i
.types
[j
];
5769 if ((overlap
.bitfield
.imm8
5770 || overlap
.bitfield
.imm8s
5771 || overlap
.bitfield
.imm16
5772 || overlap
.bitfield
.imm32
5773 || overlap
.bitfield
.imm32s
5774 || overlap
.bitfield
.imm64
)
5775 && !operand_type_equal (&overlap
, &imm8
)
5776 && !operand_type_equal (&overlap
, &imm8s
)
5777 && !operand_type_equal (&overlap
, &imm16
)
5778 && !operand_type_equal (&overlap
, &imm32
)
5779 && !operand_type_equal (&overlap
, &imm32s
)
5780 && !operand_type_equal (&overlap
, &imm64
))
5784 i386_operand_type temp
;
5786 operand_type_set (&temp
, 0);
5787 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5789 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5790 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5792 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5793 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5794 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5796 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5797 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5800 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5803 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5804 || operand_type_equal (&overlap
, &imm16_32
)
5805 || operand_type_equal (&overlap
, &imm16_32s
))
5807 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5812 if (!operand_type_equal (&overlap
, &imm8
)
5813 && !operand_type_equal (&overlap
, &imm8s
)
5814 && !operand_type_equal (&overlap
, &imm16
)
5815 && !operand_type_equal (&overlap
, &imm32
)
5816 && !operand_type_equal (&overlap
, &imm32s
)
5817 && !operand_type_equal (&overlap
, &imm64
))
5819 as_bad (_("no instruction mnemonic suffix given; "
5820 "can't determine immediate size"));
5824 i
.types
[j
] = overlap
;
5834 /* Update the first 2 immediate operands. */
5835 n
= i
.operands
> 2 ? 2 : i
.operands
;
5838 for (j
= 0; j
< n
; j
++)
5839 if (update_imm (j
) == 0)
5842 /* The 3rd operand can't be immediate operand. */
5843 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5850 bad_implicit_operand (int xmm
)
5852 const char *ireg
= xmm
? "xmm0" : "ymm0";
5855 as_bad (_("the last operand of `%s' must be `%s%s'"),
5856 i
.tm
.name
, register_prefix
, ireg
);
5858 as_bad (_("the first operand of `%s' must be `%s%s'"),
5859 i
.tm
.name
, register_prefix
, ireg
);
5864 process_operands (void)
5866 /* Default segment register this instruction will use for memory
5867 accesses. 0 means unknown. This is only for optimizing out
5868 unnecessary segment overrides. */
5869 const seg_entry
*default_seg
= 0;
5871 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5873 unsigned int dupl
= i
.operands
;
5874 unsigned int dest
= dupl
- 1;
5877 /* The destination must be an xmm register. */
5878 gas_assert (i
.reg_operands
5879 && MAX_OPERANDS
> dupl
5880 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5882 if (i
.tm
.opcode_modifier
.firstxmm0
)
5884 /* The first operand is implicit and must be xmm0. */
5885 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5886 if (register_number (i
.op
[0].regs
) != 0)
5887 return bad_implicit_operand (1);
5889 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5891 /* Keep xmm0 for instructions with VEX prefix and 3
5897 /* We remove the first xmm0 and keep the number of
5898 operands unchanged, which in fact duplicates the
5900 for (j
= 1; j
< i
.operands
; j
++)
5902 i
.op
[j
- 1] = i
.op
[j
];
5903 i
.types
[j
- 1] = i
.types
[j
];
5904 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5908 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5910 gas_assert ((MAX_OPERANDS
- 1) > dupl
5911 && (i
.tm
.opcode_modifier
.vexsources
5914 /* Add the implicit xmm0 for instructions with VEX prefix
5916 for (j
= i
.operands
; j
> 0; j
--)
5918 i
.op
[j
] = i
.op
[j
- 1];
5919 i
.types
[j
] = i
.types
[j
- 1];
5920 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5923 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5924 i
.types
[0] = regxmm
;
5925 i
.tm
.operand_types
[0] = regxmm
;
5928 i
.reg_operands
+= 2;
5933 i
.op
[dupl
] = i
.op
[dest
];
5934 i
.types
[dupl
] = i
.types
[dest
];
5935 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5944 i
.op
[dupl
] = i
.op
[dest
];
5945 i
.types
[dupl
] = i
.types
[dest
];
5946 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5949 if (i
.tm
.opcode_modifier
.immext
)
5952 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5956 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5957 gas_assert (i
.reg_operands
5958 && (operand_type_equal (&i
.types
[0], ®xmm
)
5959 || operand_type_equal (&i
.types
[0], ®ymm
)
5960 || operand_type_equal (&i
.types
[0], ®zmm
)));
5961 if (register_number (i
.op
[0].regs
) != 0)
5962 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5964 for (j
= 1; j
< i
.operands
; j
++)
5966 i
.op
[j
- 1] = i
.op
[j
];
5967 i
.types
[j
- 1] = i
.types
[j
];
5969 /* We need to adjust fields in i.tm since they are used by
5970 build_modrm_byte. */
5971 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5978 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
5980 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
5981 gas_assert (i
.operands
>= 2
5982 && (operand_type_equal (&i
.types
[1], ®xmm
)
5983 || operand_type_equal (&i
.types
[1], ®ymm
)
5984 || operand_type_equal (&i
.types
[1], ®zmm
)));
5985 unsigned int regnum
= register_number (i
.op
[1].regs
);
5986 unsigned int first_reg_in_group
= regnum
& ~3;
5987 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
5988 if (regnum
!= first_reg_in_group
) {
5989 as_warn (_("the second source register `%s%s' implicitly denotes"
5990 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
5991 register_prefix
, i
.op
[1].regs
->reg_name
,
5992 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
5993 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
5997 else if (i
.tm
.opcode_modifier
.regkludge
)
5999 /* The imul $imm, %reg instruction is converted into
6000 imul $imm, %reg, %reg, and the clr %reg instruction
6001 is converted into xor %reg, %reg. */
6003 unsigned int first_reg_op
;
6005 if (operand_type_check (i
.types
[0], reg
))
6009 /* Pretend we saw the extra register operand. */
6010 gas_assert (i
.reg_operands
== 1
6011 && i
.op
[first_reg_op
+ 1].regs
== 0);
6012 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6013 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6018 if (i
.tm
.opcode_modifier
.shortform
)
6020 if (i
.types
[0].bitfield
.sreg2
6021 || i
.types
[0].bitfield
.sreg3
)
6023 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6024 && i
.op
[0].regs
->reg_num
== 1)
6026 as_bad (_("you can't `pop %scs'"), register_prefix
);
6029 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6030 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6035 /* The register or float register operand is in operand
6039 if (i
.types
[0].bitfield
.floatreg
6040 || operand_type_check (i
.types
[0], reg
))
6044 /* Register goes in low 3 bits of opcode. */
6045 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6046 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6048 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6050 /* Warn about some common errors, but press on regardless.
6051 The first case can be generated by gcc (<= 2.8.1). */
6052 if (i
.operands
== 2)
6054 /* Reversed arguments on faddp, fsubp, etc. */
6055 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6056 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6057 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6061 /* Extraneous `l' suffix on fp insn. */
6062 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6063 register_prefix
, i
.op
[0].regs
->reg_name
);
6068 else if (i
.tm
.opcode_modifier
.modrm
)
6070 /* The opcode is completed (modulo i.tm.extension_opcode which
6071 must be put into the modrm byte). Now, we make the modrm and
6072 index base bytes based on all the info we've collected. */
6074 default_seg
= build_modrm_byte ();
6076 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6080 else if (i
.tm
.opcode_modifier
.isstring
)
6082 /* For the string instructions that allow a segment override
6083 on one of their operands, the default segment is ds. */
6087 if (i
.tm
.base_opcode
== 0x8d /* lea */
6090 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6092 /* If a segment was explicitly specified, and the specified segment
6093 is not the default, use an opcode prefix to select it. If we
6094 never figured out what the default segment is, then default_seg
6095 will be zero at this point, and the specified segment prefix will
6097 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6099 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6105 static const seg_entry
*
6106 build_modrm_byte (void)
6108 const seg_entry
*default_seg
= 0;
6109 unsigned int source
, dest
;
6112 /* The first operand of instructions with VEX prefix and 3 sources
6113 must be VEX_Imm4. */
6114 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6117 unsigned int nds
, reg_slot
;
6120 if (i
.tm
.opcode_modifier
.veximmext
6121 && i
.tm
.opcode_modifier
.immext
)
6123 dest
= i
.operands
- 2;
6124 gas_assert (dest
== 3);
6127 dest
= i
.operands
- 1;
6130 /* There are 2 kinds of instructions:
6131 1. 5 operands: 4 register operands or 3 register operands
6132 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6133 VexW0 or VexW1. The destination must be either XMM, YMM or
6135 2. 4 operands: 4 register operands or 3 register operands
6136 plus 1 memory operand, VexXDS, and VexImmExt */
6137 gas_assert ((i
.reg_operands
== 4
6138 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6139 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6140 && (i
.tm
.opcode_modifier
.veximmext
6141 || (i
.imm_operands
== 1
6142 && i
.types
[0].bitfield
.vec_imm4
6143 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6144 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6145 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6146 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6147 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6149 if (i
.imm_operands
== 0)
6151 /* When there is no immediate operand, generate an 8bit
6152 immediate operand to encode the first operand. */
6153 exp
= &im_expressions
[i
.imm_operands
++];
6154 i
.op
[i
.operands
].imms
= exp
;
6155 i
.types
[i
.operands
] = imm8
;
6157 /* If VexW1 is set, the first operand is the source and
6158 the second operand is encoded in the immediate operand. */
6159 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6170 /* FMA swaps REG and NDS. */
6171 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6179 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6181 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6183 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6185 exp
->X_op
= O_constant
;
6186 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6187 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6191 unsigned int imm_slot
;
6193 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6195 /* If VexW0 is set, the third operand is the source and
6196 the second operand is encoded in the immediate
6203 /* VexW1 is set, the second operand is the source and
6204 the third operand is encoded in the immediate
6210 if (i
.tm
.opcode_modifier
.immext
)
6212 /* When ImmExt is set, the immdiate byte is the last
6214 imm_slot
= i
.operands
- 1;
6222 /* Turn on Imm8 so that output_imm will generate it. */
6223 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6226 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6228 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6230 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6232 i
.op
[imm_slot
].imms
->X_add_number
6233 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6234 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6237 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6238 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6240 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6242 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6247 /* i.reg_operands MUST be the number of real register operands;
6248 implicit registers do not count. If there are 3 register
6249 operands, it must be a instruction with VexNDS. For a
6250 instruction with VexNDD, the destination register is encoded
6251 in VEX prefix. If there are 4 register operands, it must be
6252 a instruction with VEX prefix and 3 sources. */
6253 if (i
.mem_operands
== 0
6254 && ((i
.reg_operands
== 2
6255 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6256 || (i
.reg_operands
== 3
6257 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6258 || (i
.reg_operands
== 4 && vex_3_sources
)))
6266 /* When there are 3 operands, one of them may be immediate,
6267 which may be the first or the last operand. Otherwise,
6268 the first operand must be shift count register (cl) or it
6269 is an instruction with VexNDS. */
6270 gas_assert (i
.imm_operands
== 1
6271 || (i
.imm_operands
== 0
6272 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6273 || i
.types
[0].bitfield
.shiftcount
)));
6274 if (operand_type_check (i
.types
[0], imm
)
6275 || i
.types
[0].bitfield
.shiftcount
)
6281 /* When there are 4 operands, the first two must be 8bit
6282 immediate operands. The source operand will be the 3rd
6285 For instructions with VexNDS, if the first operand
6286 an imm8, the source operand is the 2nd one. If the last
6287 operand is imm8, the source operand is the first one. */
6288 gas_assert ((i
.imm_operands
== 2
6289 && i
.types
[0].bitfield
.imm8
6290 && i
.types
[1].bitfield
.imm8
)
6291 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6292 && i
.imm_operands
== 1
6293 && (i
.types
[0].bitfield
.imm8
6294 || i
.types
[i
.operands
- 1].bitfield
.imm8
6296 if (i
.imm_operands
== 2)
6300 if (i
.types
[0].bitfield
.imm8
)
6307 if (i
.tm
.opcode_modifier
.evex
)
6309 /* For EVEX instructions, when there are 5 operands, the
6310 first one must be immediate operand. If the second one
6311 is immediate operand, the source operand is the 3th
6312 one. If the last one is immediate operand, the source
6313 operand is the 2nd one. */
6314 gas_assert (i
.imm_operands
== 2
6315 && i
.tm
.opcode_modifier
.sae
6316 && operand_type_check (i
.types
[0], imm
));
6317 if (operand_type_check (i
.types
[1], imm
))
6319 else if (operand_type_check (i
.types
[4], imm
))
6333 /* RC/SAE operand could be between DEST and SRC. That happens
6334 when one operand is GPR and the other one is XMM/YMM/ZMM
6336 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6339 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6341 /* For instructions with VexNDS, the register-only source
6342 operand must be 32/64bit integer, XMM, YMM or ZMM
6343 register. It is encoded in VEX prefix. We need to
6344 clear RegMem bit before calling operand_type_equal. */
6346 i386_operand_type op
;
6349 /* Check register-only source operand when two source
6350 operands are swapped. */
6351 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6352 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6360 op
= i
.tm
.operand_types
[vvvv
];
6361 op
.bitfield
.regmem
= 0;
6362 if ((dest
+ 1) >= i
.operands
6363 || (!op
.bitfield
.reg32
6364 && op
.bitfield
.reg64
6365 && !operand_type_equal (&op
, ®xmm
)
6366 && !operand_type_equal (&op
, ®ymm
)
6367 && !operand_type_equal (&op
, ®zmm
)
6368 && !operand_type_equal (&op
, ®mask
)))
6370 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6376 /* One of the register operands will be encoded in the i.tm.reg
6377 field, the other in the combined i.tm.mode and i.tm.regmem
6378 fields. If no form of this instruction supports a memory
6379 destination operand, then we assume the source operand may
6380 sometimes be a memory operand and so we need to store the
6381 destination in the i.rm.reg field. */
6382 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6383 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6385 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6386 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6387 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6389 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6391 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6393 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6398 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6399 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6400 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6402 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6404 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6406 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6409 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6411 if (!i
.types
[0].bitfield
.control
6412 && !i
.types
[1].bitfield
.control
)
6414 i
.rex
&= ~(REX_R
| REX_B
);
6415 add_prefix (LOCK_PREFIX_OPCODE
);
6419 { /* If it's not 2 reg operands... */
6424 unsigned int fake_zero_displacement
= 0;
6427 for (op
= 0; op
< i
.operands
; op
++)
6428 if (operand_type_check (i
.types
[op
], anymem
))
6430 gas_assert (op
< i
.operands
);
6432 if (i
.tm
.opcode_modifier
.vecsib
)
6434 if (i
.index_reg
->reg_num
== RegEiz
6435 || i
.index_reg
->reg_num
== RegRiz
)
6438 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6441 i
.sib
.base
= NO_BASE_REGISTER
;
6442 i
.sib
.scale
= i
.log2_scale_factor
;
6443 /* No Vec_Disp8 if there is no base. */
6444 i
.types
[op
].bitfield
.vec_disp8
= 0;
6445 i
.types
[op
].bitfield
.disp8
= 0;
6446 i
.types
[op
].bitfield
.disp16
= 0;
6447 i
.types
[op
].bitfield
.disp64
= 0;
6448 if (flag_code
!= CODE_64BIT
)
6450 /* Must be 32 bit */
6451 i
.types
[op
].bitfield
.disp32
= 1;
6452 i
.types
[op
].bitfield
.disp32s
= 0;
6456 i
.types
[op
].bitfield
.disp32
= 0;
6457 i
.types
[op
].bitfield
.disp32s
= 1;
6460 i
.sib
.index
= i
.index_reg
->reg_num
;
6461 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6463 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6469 if (i
.base_reg
== 0)
6472 if (!i
.disp_operands
)
6474 fake_zero_displacement
= 1;
6475 /* Instructions with VSIB byte need 32bit displacement
6476 if there is no base register. */
6477 if (i
.tm
.opcode_modifier
.vecsib
)
6478 i
.types
[op
].bitfield
.disp32
= 1;
6480 if (i
.index_reg
== 0)
6482 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6483 /* Operand is just <disp> */
6484 if (flag_code
== CODE_64BIT
)
6486 /* 64bit mode overwrites the 32bit absolute
6487 addressing by RIP relative addressing and
6488 absolute addressing is encoded by one of the
6489 redundant SIB forms. */
6490 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6491 i
.sib
.base
= NO_BASE_REGISTER
;
6492 i
.sib
.index
= NO_INDEX_REGISTER
;
6493 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6494 ? disp32s
: disp32
);
6496 else if ((flag_code
== CODE_16BIT
)
6497 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6499 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6500 i
.types
[op
] = disp16
;
6504 i
.rm
.regmem
= NO_BASE_REGISTER
;
6505 i
.types
[op
] = disp32
;
6508 else if (!i
.tm
.opcode_modifier
.vecsib
)
6510 /* !i.base_reg && i.index_reg */
6511 if (i
.index_reg
->reg_num
== RegEiz
6512 || i
.index_reg
->reg_num
== RegRiz
)
6513 i
.sib
.index
= NO_INDEX_REGISTER
;
6515 i
.sib
.index
= i
.index_reg
->reg_num
;
6516 i
.sib
.base
= NO_BASE_REGISTER
;
6517 i
.sib
.scale
= i
.log2_scale_factor
;
6518 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6519 /* No Vec_Disp8 if there is no base. */
6520 i
.types
[op
].bitfield
.vec_disp8
= 0;
6521 i
.types
[op
].bitfield
.disp8
= 0;
6522 i
.types
[op
].bitfield
.disp16
= 0;
6523 i
.types
[op
].bitfield
.disp64
= 0;
6524 if (flag_code
!= CODE_64BIT
)
6526 /* Must be 32 bit */
6527 i
.types
[op
].bitfield
.disp32
= 1;
6528 i
.types
[op
].bitfield
.disp32s
= 0;
6532 i
.types
[op
].bitfield
.disp32
= 0;
6533 i
.types
[op
].bitfield
.disp32s
= 1;
6535 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6539 /* RIP addressing for 64bit mode. */
6540 else if (i
.base_reg
->reg_num
== RegRip
||
6541 i
.base_reg
->reg_num
== RegEip
)
6543 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6544 i
.rm
.regmem
= NO_BASE_REGISTER
;
6545 i
.types
[op
].bitfield
.disp8
= 0;
6546 i
.types
[op
].bitfield
.disp16
= 0;
6547 i
.types
[op
].bitfield
.disp32
= 0;
6548 i
.types
[op
].bitfield
.disp32s
= 1;
6549 i
.types
[op
].bitfield
.disp64
= 0;
6550 i
.types
[op
].bitfield
.vec_disp8
= 0;
6551 i
.flags
[op
] |= Operand_PCrel
;
6552 if (! i
.disp_operands
)
6553 fake_zero_displacement
= 1;
6555 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6557 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6558 switch (i
.base_reg
->reg_num
)
6561 if (i
.index_reg
== 0)
6563 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6564 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6568 if (i
.index_reg
== 0)
6571 if (operand_type_check (i
.types
[op
], disp
) == 0)
6573 /* fake (%bp) into 0(%bp) */
6574 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6575 i
.types
[op
].bitfield
.vec_disp8
= 1;
6577 i
.types
[op
].bitfield
.disp8
= 1;
6578 fake_zero_displacement
= 1;
6581 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6582 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6584 default: /* (%si) -> 4 or (%di) -> 5 */
6585 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6587 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6589 else /* i.base_reg and 32/64 bit mode */
6591 if (flag_code
== CODE_64BIT
6592 && operand_type_check (i
.types
[op
], disp
))
6594 i386_operand_type temp
;
6595 operand_type_set (&temp
, 0);
6596 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6597 temp
.bitfield
.vec_disp8
6598 = i
.types
[op
].bitfield
.vec_disp8
;
6600 if (i
.prefix
[ADDR_PREFIX
] == 0)
6601 i
.types
[op
].bitfield
.disp32s
= 1;
6603 i
.types
[op
].bitfield
.disp32
= 1;
6606 if (!i
.tm
.opcode_modifier
.vecsib
)
6607 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6608 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6610 i
.sib
.base
= i
.base_reg
->reg_num
;
6611 /* x86-64 ignores REX prefix bit here to avoid decoder
6613 if (!(i
.base_reg
->reg_flags
& RegRex
)
6614 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6615 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6617 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6619 fake_zero_displacement
= 1;
6620 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6621 i
.types
[op
].bitfield
.vec_disp8
= 1;
6623 i
.types
[op
].bitfield
.disp8
= 1;
6625 i
.sib
.scale
= i
.log2_scale_factor
;
6626 if (i
.index_reg
== 0)
6628 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6629 /* <disp>(%esp) becomes two byte modrm with no index
6630 register. We've already stored the code for esp
6631 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6632 Any base register besides %esp will not use the
6633 extra modrm byte. */
6634 i
.sib
.index
= NO_INDEX_REGISTER
;
6636 else if (!i
.tm
.opcode_modifier
.vecsib
)
6638 if (i
.index_reg
->reg_num
== RegEiz
6639 || i
.index_reg
->reg_num
== RegRiz
)
6640 i
.sib
.index
= NO_INDEX_REGISTER
;
6642 i
.sib
.index
= i
.index_reg
->reg_num
;
6643 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6644 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6649 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6650 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6654 if (!fake_zero_displacement
6658 fake_zero_displacement
= 1;
6659 if (i
.disp_encoding
== disp_encoding_8bit
)
6660 i
.types
[op
].bitfield
.disp8
= 1;
6662 i
.types
[op
].bitfield
.disp32
= 1;
6664 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6668 if (fake_zero_displacement
)
6670 /* Fakes a zero displacement assuming that i.types[op]
6671 holds the correct displacement size. */
6674 gas_assert (i
.op
[op
].disps
== 0);
6675 exp
= &disp_expressions
[i
.disp_operands
++];
6676 i
.op
[op
].disps
= exp
;
6677 exp
->X_op
= O_constant
;
6678 exp
->X_add_number
= 0;
6679 exp
->X_add_symbol
= (symbolS
*) 0;
6680 exp
->X_op_symbol
= (symbolS
*) 0;
6688 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6690 if (operand_type_check (i
.types
[0], imm
))
6691 i
.vex
.register_specifier
= NULL
;
6694 /* VEX.vvvv encodes one of the sources when the first
6695 operand is not an immediate. */
6696 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6697 i
.vex
.register_specifier
= i
.op
[0].regs
;
6699 i
.vex
.register_specifier
= i
.op
[1].regs
;
6702 /* Destination is a XMM register encoded in the ModRM.reg
6704 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6705 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6708 /* ModRM.rm and VEX.B encodes the other source. */
6709 if (!i
.mem_operands
)
6713 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6714 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6716 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6718 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6722 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6724 i
.vex
.register_specifier
= i
.op
[2].regs
;
6725 if (!i
.mem_operands
)
6728 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6729 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6733 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6734 (if any) based on i.tm.extension_opcode. Again, we must be
6735 careful to make sure that segment/control/debug/test/MMX
6736 registers are coded into the i.rm.reg field. */
6737 else if (i
.reg_operands
)
6740 unsigned int vex_reg
= ~0;
6742 for (op
= 0; op
< i
.operands
; op
++)
6743 if (i
.types
[op
].bitfield
.reg8
6744 || i
.types
[op
].bitfield
.reg16
6745 || i
.types
[op
].bitfield
.reg32
6746 || i
.types
[op
].bitfield
.reg64
6747 || i
.types
[op
].bitfield
.regmmx
6748 || i
.types
[op
].bitfield
.regxmm
6749 || i
.types
[op
].bitfield
.regymm
6750 || i
.types
[op
].bitfield
.regbnd
6751 || i
.types
[op
].bitfield
.regzmm
6752 || i
.types
[op
].bitfield
.regmask
6753 || i
.types
[op
].bitfield
.sreg2
6754 || i
.types
[op
].bitfield
.sreg3
6755 || i
.types
[op
].bitfield
.control
6756 || i
.types
[op
].bitfield
.debug
6757 || i
.types
[op
].bitfield
.test
)
6762 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6764 /* For instructions with VexNDS, the register-only
6765 source operand is encoded in VEX prefix. */
6766 gas_assert (mem
!= (unsigned int) ~0);
6771 gas_assert (op
< i
.operands
);
6775 /* Check register-only source operand when two source
6776 operands are swapped. */
6777 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6778 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6782 gas_assert (mem
== (vex_reg
+ 1)
6783 && op
< i
.operands
);
6788 gas_assert (vex_reg
< i
.operands
);
6792 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6794 /* For instructions with VexNDD, the register destination
6795 is encoded in VEX prefix. */
6796 if (i
.mem_operands
== 0)
6798 /* There is no memory operand. */
6799 gas_assert ((op
+ 2) == i
.operands
);
6804 /* There are only 2 operands. */
6805 gas_assert (op
< 2 && i
.operands
== 2);
6810 gas_assert (op
< i
.operands
);
6812 if (vex_reg
!= (unsigned int) ~0)
6814 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6816 if (type
->bitfield
.reg32
!= 1
6817 && type
->bitfield
.reg64
!= 1
6818 && !operand_type_equal (type
, ®xmm
)
6819 && !operand_type_equal (type
, ®ymm
)
6820 && !operand_type_equal (type
, ®zmm
)
6821 && !operand_type_equal (type
, ®mask
))
6824 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6827 /* Don't set OP operand twice. */
6830 /* If there is an extension opcode to put here, the
6831 register number must be put into the regmem field. */
6832 if (i
.tm
.extension_opcode
!= None
)
6834 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6835 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6837 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6842 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6843 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6845 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6850 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6851 must set it to 3 to indicate this is a register operand
6852 in the regmem field. */
6853 if (!i
.mem_operands
)
6857 /* Fill in i.rm.reg field with extension opcode (if any). */
6858 if (i
.tm
.extension_opcode
!= None
)
6859 i
.rm
.reg
= i
.tm
.extension_opcode
;
6865 output_branch (void)
6871 relax_substateT subtype
;
6875 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6876 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6879 if (i
.prefix
[DATA_PREFIX
] != 0)
6885 /* Pentium4 branch hints. */
6886 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6887 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6892 if (i
.prefix
[REX_PREFIX
] != 0)
6898 /* BND prefixed jump. */
6899 if (i
.prefix
[BND_PREFIX
] != 0)
6901 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6905 if (i
.prefixes
!= 0 && !intel_syntax
)
6906 as_warn (_("skipping prefixes on this instruction"));
6908 /* It's always a symbol; End frag & setup for relax.
6909 Make sure there is enough room in this frag for the largest
6910 instruction we may generate in md_convert_frag. This is 2
6911 bytes for the opcode and room for the prefix and largest
6913 frag_grow (prefix
+ 2 + 4);
6914 /* Prefix and 1 opcode byte go in fr_fix. */
6915 p
= frag_more (prefix
+ 1);
6916 if (i
.prefix
[DATA_PREFIX
] != 0)
6917 *p
++ = DATA_PREFIX_OPCODE
;
6918 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6919 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6920 *p
++ = i
.prefix
[SEG_PREFIX
];
6921 if (i
.prefix
[REX_PREFIX
] != 0)
6922 *p
++ = i
.prefix
[REX_PREFIX
];
6923 *p
= i
.tm
.base_opcode
;
6925 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6926 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6927 else if (cpu_arch_flags
.bitfield
.cpui386
)
6928 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6930 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6933 sym
= i
.op
[0].disps
->X_add_symbol
;
6934 off
= i
.op
[0].disps
->X_add_number
;
6936 if (i
.op
[0].disps
->X_op
!= O_constant
6937 && i
.op
[0].disps
->X_op
!= O_symbol
)
6939 /* Handle complex expressions. */
6940 sym
= make_expr_symbol (i
.op
[0].disps
);
6944 /* 1 possible extra opcode + 4 byte displacement go in var part.
6945 Pass reloc in fr_var. */
6946 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6956 if (i
.tm
.opcode_modifier
.jumpbyte
)
6958 /* This is a loop or jecxz type instruction. */
6960 if (i
.prefix
[ADDR_PREFIX
] != 0)
6962 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6965 /* Pentium4 branch hints. */
6966 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6967 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6969 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6978 if (flag_code
== CODE_16BIT
)
6981 if (i
.prefix
[DATA_PREFIX
] != 0)
6983 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6993 if (i
.prefix
[REX_PREFIX
] != 0)
6995 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6999 /* BND prefixed jump. */
7000 if (i
.prefix
[BND_PREFIX
] != 0)
7002 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7006 if (i
.prefixes
!= 0 && !intel_syntax
)
7007 as_warn (_("skipping prefixes on this instruction"));
7009 p
= frag_more (i
.tm
.opcode_length
+ size
);
7010 switch (i
.tm
.opcode_length
)
7013 *p
++ = i
.tm
.base_opcode
>> 8;
7016 *p
++ = i
.tm
.base_opcode
;
7022 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7023 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7025 /* All jumps handled here are signed, but don't use a signed limit
7026 check for 32 and 16 bit jumps as we want to allow wrap around at
7027 4G and 64k respectively. */
7029 fixP
->fx_signed
= 1;
7033 output_interseg_jump (void)
7041 if (flag_code
== CODE_16BIT
)
7045 if (i
.prefix
[DATA_PREFIX
] != 0)
7051 if (i
.prefix
[REX_PREFIX
] != 0)
7061 if (i
.prefixes
!= 0 && !intel_syntax
)
7062 as_warn (_("skipping prefixes on this instruction"));
7064 /* 1 opcode; 2 segment; offset */
7065 p
= frag_more (prefix
+ 1 + 2 + size
);
7067 if (i
.prefix
[DATA_PREFIX
] != 0)
7068 *p
++ = DATA_PREFIX_OPCODE
;
7070 if (i
.prefix
[REX_PREFIX
] != 0)
7071 *p
++ = i
.prefix
[REX_PREFIX
];
7073 *p
++ = i
.tm
.base_opcode
;
7074 if (i
.op
[1].imms
->X_op
== O_constant
)
7076 offsetT n
= i
.op
[1].imms
->X_add_number
;
7079 && !fits_in_unsigned_word (n
)
7080 && !fits_in_signed_word (n
))
7082 as_bad (_("16-bit jump out of range"));
7085 md_number_to_chars (p
, n
, size
);
7088 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7089 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7090 if (i
.op
[0].imms
->X_op
!= O_constant
)
7091 as_bad (_("can't handle non absolute segment in `%s'"),
7093 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7099 fragS
*insn_start_frag
;
7100 offsetT insn_start_off
;
7102 /* Tie dwarf2 debug info to the address at the start of the insn.
7103 We can't do this after the insn has been output as the current
7104 frag may have been closed off. eg. by frag_var. */
7105 dwarf2_emit_insn (0);
7107 insn_start_frag
= frag_now
;
7108 insn_start_off
= frag_now_fix ();
7111 if (i
.tm
.opcode_modifier
.jump
)
7113 else if (i
.tm
.opcode_modifier
.jumpbyte
7114 || i
.tm
.opcode_modifier
.jumpdword
)
7116 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7117 output_interseg_jump ();
7120 /* Output normal instructions here. */
7124 unsigned int prefix
;
7127 && i
.tm
.base_opcode
== 0xfae
7129 && i
.imm_operands
== 1
7130 && (i
.op
[0].imms
->X_add_number
== 0xe8
7131 || i
.op
[0].imms
->X_add_number
== 0xf0
7132 || i
.op
[0].imms
->X_add_number
== 0xf8))
7134 /* Encode lfence, mfence, and sfence as
7135 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7136 offsetT val
= 0x240483f0ULL
;
7138 md_number_to_chars (p
, val
, 5);
7142 /* Some processors fail on LOCK prefix. This options makes
7143 assembler ignore LOCK prefix and serves as a workaround. */
7144 if (omit_lock_prefix
)
7146 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7148 i
.prefix
[LOCK_PREFIX
] = 0;
7151 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7152 don't need the explicit prefix. */
7153 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7155 switch (i
.tm
.opcode_length
)
7158 if (i
.tm
.base_opcode
& 0xff000000)
7160 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7165 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7167 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7168 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7171 if (prefix
!= REPE_PREFIX_OPCODE
7172 || (i
.prefix
[REP_PREFIX
]
7173 != REPE_PREFIX_OPCODE
))
7174 add_prefix (prefix
);
7177 add_prefix (prefix
);
7186 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7187 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7188 R_X86_64_GOTTPOFF relocation so that linker can safely
7189 perform IE->LE optimization. */
7190 if (x86_elf_abi
== X86_64_X32_ABI
7192 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7193 && i
.prefix
[REX_PREFIX
] == 0)
7194 add_prefix (REX_OPCODE
);
7197 /* The prefix bytes. */
7198 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7200 FRAG_APPEND_1_CHAR (*q
);
7204 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7209 /* REX byte is encoded in VEX prefix. */
7213 FRAG_APPEND_1_CHAR (*q
);
7216 /* There should be no other prefixes for instructions
7221 /* For EVEX instructions i.vrex should become 0 after
7222 build_evex_prefix. For VEX instructions upper 16 registers
7223 aren't available, so VREX should be 0. */
7226 /* Now the VEX prefix. */
7227 p
= frag_more (i
.vex
.length
);
7228 for (j
= 0; j
< i
.vex
.length
; j
++)
7229 p
[j
] = i
.vex
.bytes
[j
];
7232 /* Now the opcode; be careful about word order here! */
7233 if (i
.tm
.opcode_length
== 1)
7235 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7239 switch (i
.tm
.opcode_length
)
7243 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7244 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7248 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7258 /* Put out high byte first: can't use md_number_to_chars! */
7259 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7260 *p
= i
.tm
.base_opcode
& 0xff;
7263 /* Now the modrm byte and sib byte (if present). */
7264 if (i
.tm
.opcode_modifier
.modrm
)
7266 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7269 /* If i.rm.regmem == ESP (4)
7270 && i.rm.mode != (Register mode)
7272 ==> need second modrm byte. */
7273 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7275 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7276 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7278 | i
.sib
.scale
<< 6));
7281 if (i
.disp_operands
)
7282 output_disp (insn_start_frag
, insn_start_off
);
7285 output_imm (insn_start_frag
, insn_start_off
);
7291 pi ("" /*line*/, &i
);
7293 #endif /* DEBUG386 */
7296 /* Return the size of the displacement operand N. */
7299 disp_size (unsigned int n
)
7303 /* Vec_Disp8 has to be 8bit. */
7304 if (i
.types
[n
].bitfield
.vec_disp8
)
7306 else if (i
.types
[n
].bitfield
.disp64
)
7308 else if (i
.types
[n
].bitfield
.disp8
)
7310 else if (i
.types
[n
].bitfield
.disp16
)
7315 /* Return the size of the immediate operand N. */
7318 imm_size (unsigned int n
)
7321 if (i
.types
[n
].bitfield
.imm64
)
7323 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7325 else if (i
.types
[n
].bitfield
.imm16
)
7331 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7336 for (n
= 0; n
< i
.operands
; n
++)
7338 if (i
.types
[n
].bitfield
.vec_disp8
7339 || operand_type_check (i
.types
[n
], disp
))
7341 if (i
.op
[n
].disps
->X_op
== O_constant
)
7343 int size
= disp_size (n
);
7344 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7346 if (i
.types
[n
].bitfield
.vec_disp8
)
7348 val
= offset_in_range (val
, size
);
7349 p
= frag_more (size
);
7350 md_number_to_chars (p
, val
, size
);
7354 enum bfd_reloc_code_real reloc_type
;
7355 int size
= disp_size (n
);
7356 int sign
= i
.types
[n
].bitfield
.disp32s
;
7357 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7360 /* We can't have 8 bit displacement here. */
7361 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7363 /* The PC relative address is computed relative
7364 to the instruction boundary, so in case immediate
7365 fields follows, we need to adjust the value. */
7366 if (pcrel
&& i
.imm_operands
)
7371 for (n1
= 0; n1
< i
.operands
; n1
++)
7372 if (operand_type_check (i
.types
[n1
], imm
))
7374 /* Only one immediate is allowed for PC
7375 relative address. */
7376 gas_assert (sz
== 0);
7378 i
.op
[n
].disps
->X_add_number
-= sz
;
7380 /* We should find the immediate. */
7381 gas_assert (sz
!= 0);
7384 p
= frag_more (size
);
7385 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7387 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7388 && (((reloc_type
== BFD_RELOC_32
7389 || reloc_type
== BFD_RELOC_X86_64_32S
7390 || (reloc_type
== BFD_RELOC_64
7392 && (i
.op
[n
].disps
->X_op
== O_symbol
7393 || (i
.op
[n
].disps
->X_op
== O_add
7394 && ((symbol_get_value_expression
7395 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7397 || reloc_type
== BFD_RELOC_32_PCREL
))
7401 if (insn_start_frag
== frag_now
)
7402 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7407 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7408 for (fr
= insn_start_frag
->fr_next
;
7409 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7411 add
+= p
- frag_now
->fr_literal
;
7416 reloc_type
= BFD_RELOC_386_GOTPC
;
7417 i
.op
[n
].imms
->X_add_number
+= add
;
7419 else if (reloc_type
== BFD_RELOC_64
)
7420 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7422 /* Don't do the adjustment for x86-64, as there
7423 the pcrel addressing is relative to the _next_
7424 insn, and that is taken care of in other code. */
7425 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7427 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7428 size
, i
.op
[n
].disps
, pcrel
,
7430 /* Check for "call/jmp *mem", "mov mem, %reg",
7431 "test %reg, mem" and "binop mem, %reg" where binop
7432 is one of adc, add, and, cmp, or, sbb, sub, xor
7433 instructions. Always generate R_386_GOT32X for
7434 "sym*GOT" operand in 32-bit mode. */
7435 if ((generate_relax_relocations
7438 && i
.rm
.regmem
== 5))
7440 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7441 && ((i
.operands
== 1
7442 && i
.tm
.base_opcode
== 0xff
7443 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7445 && (i
.tm
.base_opcode
== 0x8b
7446 || i
.tm
.base_opcode
== 0x85
7447 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7451 fixP
->fx_tcbit
= i
.rex
!= 0;
7453 && (i
.base_reg
->reg_num
== RegRip
7454 || i
.base_reg
->reg_num
== RegEip
))
7455 fixP
->fx_tcbit2
= 1;
7458 fixP
->fx_tcbit2
= 1;
7466 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7471 for (n
= 0; n
< i
.operands
; n
++)
7473 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7474 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7477 if (operand_type_check (i
.types
[n
], imm
))
7479 if (i
.op
[n
].imms
->X_op
== O_constant
)
7481 int size
= imm_size (n
);
7484 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7486 p
= frag_more (size
);
7487 md_number_to_chars (p
, val
, size
);
7491 /* Not absolute_section.
7492 Need a 32-bit fixup (don't support 8bit
7493 non-absolute imms). Try to support other
7495 enum bfd_reloc_code_real reloc_type
;
7496 int size
= imm_size (n
);
7499 if (i
.types
[n
].bitfield
.imm32s
7500 && (i
.suffix
== QWORD_MNEM_SUFFIX
7501 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7506 p
= frag_more (size
);
7507 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7509 /* This is tough to explain. We end up with this one if we
7510 * have operands that look like
7511 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7512 * obtain the absolute address of the GOT, and it is strongly
7513 * preferable from a performance point of view to avoid using
7514 * a runtime relocation for this. The actual sequence of
7515 * instructions often look something like:
7520 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7522 * The call and pop essentially return the absolute address
7523 * of the label .L66 and store it in %ebx. The linker itself
7524 * will ultimately change the first operand of the addl so
7525 * that %ebx points to the GOT, but to keep things simple, the
7526 * .o file must have this operand set so that it generates not
7527 * the absolute address of .L66, but the absolute address of
7528 * itself. This allows the linker itself simply treat a GOTPC
7529 * relocation as asking for a pcrel offset to the GOT to be
7530 * added in, and the addend of the relocation is stored in the
7531 * operand field for the instruction itself.
7533 * Our job here is to fix the operand so that it would add
7534 * the correct offset so that %ebx would point to itself. The
7535 * thing that is tricky is that .-.L66 will point to the
7536 * beginning of the instruction, so we need to further modify
7537 * the operand so that it will point to itself. There are
7538 * other cases where you have something like:
7540 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7542 * and here no correction would be required. Internally in
7543 * the assembler we treat operands of this form as not being
7544 * pcrel since the '.' is explicitly mentioned, and I wonder
7545 * whether it would simplify matters to do it this way. Who
7546 * knows. In earlier versions of the PIC patches, the
7547 * pcrel_adjust field was used to store the correction, but
7548 * since the expression is not pcrel, I felt it would be
7549 * confusing to do it this way. */
7551 if ((reloc_type
== BFD_RELOC_32
7552 || reloc_type
== BFD_RELOC_X86_64_32S
7553 || reloc_type
== BFD_RELOC_64
)
7555 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7556 && (i
.op
[n
].imms
->X_op
== O_symbol
7557 || (i
.op
[n
].imms
->X_op
== O_add
7558 && ((symbol_get_value_expression
7559 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7564 if (insn_start_frag
== frag_now
)
7565 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7570 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7571 for (fr
= insn_start_frag
->fr_next
;
7572 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7574 add
+= p
- frag_now
->fr_literal
;
7578 reloc_type
= BFD_RELOC_386_GOTPC
;
7580 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7582 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7583 i
.op
[n
].imms
->X_add_number
+= add
;
7585 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7586 i
.op
[n
].imms
, 0, reloc_type
);
7592 /* x86_cons_fix_new is called via the expression parsing code when a
7593 reloc is needed. We use this hook to get the correct .got reloc. */
7594 static int cons_sign
= -1;
7597 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7598 expressionS
*exp
, bfd_reloc_code_real_type r
)
7600 r
= reloc (len
, 0, cons_sign
, r
);
7603 if (exp
->X_op
== O_secrel
)
7605 exp
->X_op
= O_symbol
;
7606 r
= BFD_RELOC_32_SECREL
;
7610 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7613 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7614 purpose of the `.dc.a' internal pseudo-op. */
7617 x86_address_bytes (void)
7619 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7621 return stdoutput
->arch_info
->bits_per_address
/ 8;
7624 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7626 # define lex_got(reloc, adjust, types) NULL
7628 /* Parse operands of the form
7629 <symbol>@GOTOFF+<nnn>
7630 and similar .plt or .got references.
7632 If we find one, set up the correct relocation in RELOC and copy the
7633 input string, minus the `@GOTOFF' into a malloc'd buffer for
7634 parsing by the calling routine. Return this buffer, and if ADJUST
7635 is non-null set it to the length of the string we removed from the
7636 input line. Otherwise return NULL. */
7638 lex_got (enum bfd_reloc_code_real
*rel
,
7640 i386_operand_type
*types
)
7642 /* Some of the relocations depend on the size of what field is to
7643 be relocated. But in our callers i386_immediate and i386_displacement
7644 we don't yet know the operand size (this will be set by insn
7645 matching). Hence we record the word32 relocation here,
7646 and adjust the reloc according to the real size in reloc(). */
7647 static const struct {
7650 const enum bfd_reloc_code_real rel
[2];
7651 const i386_operand_type types64
;
7653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7654 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7656 OPERAND_TYPE_IMM32_64
},
7658 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7659 BFD_RELOC_X86_64_PLTOFF64
},
7660 OPERAND_TYPE_IMM64
},
7661 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7662 BFD_RELOC_X86_64_PLT32
},
7663 OPERAND_TYPE_IMM32_32S_DISP32
},
7664 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7665 BFD_RELOC_X86_64_GOTPLT64
},
7666 OPERAND_TYPE_IMM64_DISP64
},
7667 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7668 BFD_RELOC_X86_64_GOTOFF64
},
7669 OPERAND_TYPE_IMM64_DISP64
},
7670 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7671 BFD_RELOC_X86_64_GOTPCREL
},
7672 OPERAND_TYPE_IMM32_32S_DISP32
},
7673 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7674 BFD_RELOC_X86_64_TLSGD
},
7675 OPERAND_TYPE_IMM32_32S_DISP32
},
7676 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7677 _dummy_first_bfd_reloc_code_real
},
7678 OPERAND_TYPE_NONE
},
7679 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7680 BFD_RELOC_X86_64_TLSLD
},
7681 OPERAND_TYPE_IMM32_32S_DISP32
},
7682 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7683 BFD_RELOC_X86_64_GOTTPOFF
},
7684 OPERAND_TYPE_IMM32_32S_DISP32
},
7685 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7686 BFD_RELOC_X86_64_TPOFF32
},
7687 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7688 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7689 _dummy_first_bfd_reloc_code_real
},
7690 OPERAND_TYPE_NONE
},
7691 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7692 BFD_RELOC_X86_64_DTPOFF32
},
7693 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7694 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7695 _dummy_first_bfd_reloc_code_real
},
7696 OPERAND_TYPE_NONE
},
7697 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7698 _dummy_first_bfd_reloc_code_real
},
7699 OPERAND_TYPE_NONE
},
7700 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7701 BFD_RELOC_X86_64_GOT32
},
7702 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7703 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7704 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7705 OPERAND_TYPE_IMM32_32S_DISP32
},
7706 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7707 BFD_RELOC_X86_64_TLSDESC_CALL
},
7708 OPERAND_TYPE_IMM32_32S_DISP32
},
7713 #if defined (OBJ_MAYBE_ELF)
7718 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7719 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7722 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7724 int len
= gotrel
[j
].len
;
7725 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7727 if (gotrel
[j
].rel
[object_64bit
] != 0)
7730 char *tmpbuf
, *past_reloc
;
7732 *rel
= gotrel
[j
].rel
[object_64bit
];
7736 if (flag_code
!= CODE_64BIT
)
7738 types
->bitfield
.imm32
= 1;
7739 types
->bitfield
.disp32
= 1;
7742 *types
= gotrel
[j
].types64
;
7745 if (j
!= 0 && GOT_symbol
== NULL
)
7746 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7748 /* The length of the first part of our input line. */
7749 first
= cp
- input_line_pointer
;
7751 /* The second part goes from after the reloc token until
7752 (and including) an end_of_line char or comma. */
7753 past_reloc
= cp
+ 1 + len
;
7755 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7757 second
= cp
+ 1 - past_reloc
;
7759 /* Allocate and copy string. The trailing NUL shouldn't
7760 be necessary, but be safe. */
7761 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7762 memcpy (tmpbuf
, input_line_pointer
, first
);
7763 if (second
!= 0 && *past_reloc
!= ' ')
7764 /* Replace the relocation token with ' ', so that
7765 errors like foo@GOTOFF1 will be detected. */
7766 tmpbuf
[first
++] = ' ';
7768 /* Increment length by 1 if the relocation token is
7773 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7774 tmpbuf
[first
+ second
] = '\0';
7778 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7779 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7784 /* Might be a symbol version string. Don't as_bad here. */
7793 /* Parse operands of the form
7794 <symbol>@SECREL32+<nnn>
7796 If we find one, set up the correct relocation in RELOC and copy the
7797 input string, minus the `@SECREL32' into a malloc'd buffer for
7798 parsing by the calling routine. Return this buffer, and if ADJUST
7799 is non-null set it to the length of the string we removed from the
7800 input line. Otherwise return NULL.
7802 This function is copied from the ELF version above adjusted for PE targets. */
7805 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7806 int *adjust ATTRIBUTE_UNUSED
,
7807 i386_operand_type
*types
)
7813 const enum bfd_reloc_code_real rel
[2];
7814 const i386_operand_type types64
;
7818 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7819 BFD_RELOC_32_SECREL
},
7820 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7826 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7827 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7830 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7832 int len
= gotrel
[j
].len
;
7834 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7836 if (gotrel
[j
].rel
[object_64bit
] != 0)
7839 char *tmpbuf
, *past_reloc
;
7841 *rel
= gotrel
[j
].rel
[object_64bit
];
7847 if (flag_code
!= CODE_64BIT
)
7849 types
->bitfield
.imm32
= 1;
7850 types
->bitfield
.disp32
= 1;
7853 *types
= gotrel
[j
].types64
;
7856 /* The length of the first part of our input line. */
7857 first
= cp
- input_line_pointer
;
7859 /* The second part goes from after the reloc token until
7860 (and including) an end_of_line char or comma. */
7861 past_reloc
= cp
+ 1 + len
;
7863 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7865 second
= cp
+ 1 - past_reloc
;
7867 /* Allocate and copy string. The trailing NUL shouldn't
7868 be necessary, but be safe. */
7869 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7870 memcpy (tmpbuf
, input_line_pointer
, first
);
7871 if (second
!= 0 && *past_reloc
!= ' ')
7872 /* Replace the relocation token with ' ', so that
7873 errors like foo@SECLREL321 will be detected. */
7874 tmpbuf
[first
++] = ' ';
7875 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7876 tmpbuf
[first
+ second
] = '\0';
7880 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7881 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7886 /* Might be a symbol version string. Don't as_bad here. */
7892 bfd_reloc_code_real_type
7893 x86_cons (expressionS
*exp
, int size
)
7895 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7897 intel_syntax
= -intel_syntax
;
7900 if (size
== 4 || (object_64bit
&& size
== 8))
7902 /* Handle @GOTOFF and the like in an expression. */
7904 char *gotfree_input_line
;
7907 save
= input_line_pointer
;
7908 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7909 if (gotfree_input_line
)
7910 input_line_pointer
= gotfree_input_line
;
7914 if (gotfree_input_line
)
7916 /* expression () has merrily parsed up to the end of line,
7917 or a comma - in the wrong buffer. Transfer how far
7918 input_line_pointer has moved to the right buffer. */
7919 input_line_pointer
= (save
7920 + (input_line_pointer
- gotfree_input_line
)
7922 free (gotfree_input_line
);
7923 if (exp
->X_op
== O_constant
7924 || exp
->X_op
== O_absent
7925 || exp
->X_op
== O_illegal
7926 || exp
->X_op
== O_register
7927 || exp
->X_op
== O_big
)
7929 char c
= *input_line_pointer
;
7930 *input_line_pointer
= 0;
7931 as_bad (_("missing or invalid expression `%s'"), save
);
7932 *input_line_pointer
= c
;
7939 intel_syntax
= -intel_syntax
;
7942 i386_intel_simplify (exp
);
7948 signed_cons (int size
)
7950 if (flag_code
== CODE_64BIT
)
7958 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7965 if (exp
.X_op
== O_symbol
)
7966 exp
.X_op
= O_secrel
;
7968 emit_expr (&exp
, 4);
7970 while (*input_line_pointer
++ == ',');
7972 input_line_pointer
--;
7973 demand_empty_rest_of_line ();
7977 /* Handle Vector operations. */
7980 check_VecOperations (char *op_string
, char *op_end
)
7982 const reg_entry
*mask
;
7987 && (op_end
== NULL
|| op_string
< op_end
))
7990 if (*op_string
== '{')
7994 /* Check broadcasts. */
7995 if (strncmp (op_string
, "1to", 3) == 0)
8000 goto duplicated_vec_op
;
8003 if (*op_string
== '8')
8004 bcst_type
= BROADCAST_1TO8
;
8005 else if (*op_string
== '4')
8006 bcst_type
= BROADCAST_1TO4
;
8007 else if (*op_string
== '2')
8008 bcst_type
= BROADCAST_1TO2
;
8009 else if (*op_string
== '1'
8010 && *(op_string
+1) == '6')
8012 bcst_type
= BROADCAST_1TO16
;
8017 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8022 broadcast_op
.type
= bcst_type
;
8023 broadcast_op
.operand
= this_operand
;
8024 i
.broadcast
= &broadcast_op
;
8026 /* Check masking operation. */
8027 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8029 /* k0 can't be used for write mask. */
8030 if (mask
->reg_num
== 0)
8032 as_bad (_("`%s' can't be used for write mask"),
8039 mask_op
.mask
= mask
;
8040 mask_op
.zeroing
= 0;
8041 mask_op
.operand
= this_operand
;
8047 goto duplicated_vec_op
;
8049 i
.mask
->mask
= mask
;
8051 /* Only "{z}" is allowed here. No need to check
8052 zeroing mask explicitly. */
8053 if (i
.mask
->operand
!= this_operand
)
8055 as_bad (_("invalid write mask `%s'"), saved
);
8062 /* Check zeroing-flag for masking operation. */
8063 else if (*op_string
== 'z')
8067 mask_op
.mask
= NULL
;
8068 mask_op
.zeroing
= 1;
8069 mask_op
.operand
= this_operand
;
8074 if (i
.mask
->zeroing
)
8077 as_bad (_("duplicated `%s'"), saved
);
8081 i
.mask
->zeroing
= 1;
8083 /* Only "{%k}" is allowed here. No need to check mask
8084 register explicitly. */
8085 if (i
.mask
->operand
!= this_operand
)
8087 as_bad (_("invalid zeroing-masking `%s'"),
8096 goto unknown_vec_op
;
8098 if (*op_string
!= '}')
8100 as_bad (_("missing `}' in `%s'"), saved
);
8107 /* We don't know this one. */
8108 as_bad (_("unknown vector operation: `%s'"), saved
);
8116 i386_immediate (char *imm_start
)
8118 char *save_input_line_pointer
;
8119 char *gotfree_input_line
;
8122 i386_operand_type types
;
8124 operand_type_set (&types
, ~0);
8126 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8128 as_bad (_("at most %d immediate operands are allowed"),
8129 MAX_IMMEDIATE_OPERANDS
);
8133 exp
= &im_expressions
[i
.imm_operands
++];
8134 i
.op
[this_operand
].imms
= exp
;
8136 if (is_space_char (*imm_start
))
8139 save_input_line_pointer
= input_line_pointer
;
8140 input_line_pointer
= imm_start
;
8142 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8143 if (gotfree_input_line
)
8144 input_line_pointer
= gotfree_input_line
;
8146 exp_seg
= expression (exp
);
8150 /* Handle vector operations. */
8151 if (*input_line_pointer
== '{')
8153 input_line_pointer
= check_VecOperations (input_line_pointer
,
8155 if (input_line_pointer
== NULL
)
8159 if (*input_line_pointer
)
8160 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8162 input_line_pointer
= save_input_line_pointer
;
8163 if (gotfree_input_line
)
8165 free (gotfree_input_line
);
8167 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8168 exp
->X_op
= O_illegal
;
8171 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8175 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8176 i386_operand_type types
, const char *imm_start
)
8178 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8181 as_bad (_("missing or invalid immediate expression `%s'"),
8185 else if (exp
->X_op
== O_constant
)
8187 /* Size it properly later. */
8188 i
.types
[this_operand
].bitfield
.imm64
= 1;
8189 /* If not 64bit, sign extend val. */
8190 if (flag_code
!= CODE_64BIT
8191 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8193 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8195 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8196 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8197 && exp_seg
!= absolute_section
8198 && exp_seg
!= text_section
8199 && exp_seg
!= data_section
8200 && exp_seg
!= bss_section
8201 && exp_seg
!= undefined_section
8202 && !bfd_is_com_section (exp_seg
))
8204 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8208 else if (!intel_syntax
&& exp_seg
== reg_section
)
8211 as_bad (_("illegal immediate register operand %s"), imm_start
);
8216 /* This is an address. The size of the address will be
8217 determined later, depending on destination register,
8218 suffix, or the default for the section. */
8219 i
.types
[this_operand
].bitfield
.imm8
= 1;
8220 i
.types
[this_operand
].bitfield
.imm16
= 1;
8221 i
.types
[this_operand
].bitfield
.imm32
= 1;
8222 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8223 i
.types
[this_operand
].bitfield
.imm64
= 1;
8224 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8232 i386_scale (char *scale
)
8235 char *save
= input_line_pointer
;
8237 input_line_pointer
= scale
;
8238 val
= get_absolute_expression ();
8243 i
.log2_scale_factor
= 0;
8246 i
.log2_scale_factor
= 1;
8249 i
.log2_scale_factor
= 2;
8252 i
.log2_scale_factor
= 3;
8256 char sep
= *input_line_pointer
;
8258 *input_line_pointer
= '\0';
8259 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8261 *input_line_pointer
= sep
;
8262 input_line_pointer
= save
;
8266 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8268 as_warn (_("scale factor of %d without an index register"),
8269 1 << i
.log2_scale_factor
);
8270 i
.log2_scale_factor
= 0;
8272 scale
= input_line_pointer
;
8273 input_line_pointer
= save
;
8278 i386_displacement (char *disp_start
, char *disp_end
)
8282 char *save_input_line_pointer
;
8283 char *gotfree_input_line
;
8285 i386_operand_type bigdisp
, types
= anydisp
;
8288 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8290 as_bad (_("at most %d displacement operands are allowed"),
8291 MAX_MEMORY_OPERANDS
);
8295 operand_type_set (&bigdisp
, 0);
8296 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8297 || (!current_templates
->start
->opcode_modifier
.jump
8298 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8300 bigdisp
.bitfield
.disp32
= 1;
8301 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8302 if (flag_code
== CODE_64BIT
)
8306 bigdisp
.bitfield
.disp32s
= 1;
8307 bigdisp
.bitfield
.disp64
= 1;
8310 else if ((flag_code
== CODE_16BIT
) ^ override
)
8312 bigdisp
.bitfield
.disp32
= 0;
8313 bigdisp
.bitfield
.disp16
= 1;
8318 /* For PC-relative branches, the width of the displacement
8319 is dependent upon data size, not address size. */
8320 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8321 if (flag_code
== CODE_64BIT
)
8323 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8324 bigdisp
.bitfield
.disp16
= 1;
8327 bigdisp
.bitfield
.disp32
= 1;
8328 bigdisp
.bitfield
.disp32s
= 1;
8334 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8336 : LONG_MNEM_SUFFIX
));
8337 bigdisp
.bitfield
.disp32
= 1;
8338 if ((flag_code
== CODE_16BIT
) ^ override
)
8340 bigdisp
.bitfield
.disp32
= 0;
8341 bigdisp
.bitfield
.disp16
= 1;
8345 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8348 exp
= &disp_expressions
[i
.disp_operands
];
8349 i
.op
[this_operand
].disps
= exp
;
8351 save_input_line_pointer
= input_line_pointer
;
8352 input_line_pointer
= disp_start
;
8353 END_STRING_AND_SAVE (disp_end
);
8355 #ifndef GCC_ASM_O_HACK
8356 #define GCC_ASM_O_HACK 0
8359 END_STRING_AND_SAVE (disp_end
+ 1);
8360 if (i
.types
[this_operand
].bitfield
.baseIndex
8361 && displacement_string_end
[-1] == '+')
8363 /* This hack is to avoid a warning when using the "o"
8364 constraint within gcc asm statements.
8367 #define _set_tssldt_desc(n,addr,limit,type) \
8368 __asm__ __volatile__ ( \
8370 "movw %w1,2+%0\n\t" \
8372 "movb %b1,4+%0\n\t" \
8373 "movb %4,5+%0\n\t" \
8374 "movb $0,6+%0\n\t" \
8375 "movb %h1,7+%0\n\t" \
8377 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8379 This works great except that the output assembler ends
8380 up looking a bit weird if it turns out that there is
8381 no offset. You end up producing code that looks like:
8394 So here we provide the missing zero. */
8396 *displacement_string_end
= '0';
8399 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8400 if (gotfree_input_line
)
8401 input_line_pointer
= gotfree_input_line
;
8403 exp_seg
= expression (exp
);
8406 if (*input_line_pointer
)
8407 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8409 RESTORE_END_STRING (disp_end
+ 1);
8411 input_line_pointer
= save_input_line_pointer
;
8412 if (gotfree_input_line
)
8414 free (gotfree_input_line
);
8416 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8417 exp
->X_op
= O_illegal
;
8420 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8422 RESTORE_END_STRING (disp_end
);
8428 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8429 i386_operand_type types
, const char *disp_start
)
8431 i386_operand_type bigdisp
;
8434 /* We do this to make sure that the section symbol is in
8435 the symbol table. We will ultimately change the relocation
8436 to be relative to the beginning of the section. */
8437 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8438 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8439 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8441 if (exp
->X_op
!= O_symbol
)
8444 if (S_IS_LOCAL (exp
->X_add_symbol
)
8445 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8446 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8447 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8448 exp
->X_op
= O_subtract
;
8449 exp
->X_op_symbol
= GOT_symbol
;
8450 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8451 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8452 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8453 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8455 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8458 else if (exp
->X_op
== O_absent
8459 || exp
->X_op
== O_illegal
8460 || exp
->X_op
== O_big
)
8463 as_bad (_("missing or invalid displacement expression `%s'"),
8468 else if (flag_code
== CODE_64BIT
8469 && !i
.prefix
[ADDR_PREFIX
]
8470 && exp
->X_op
== O_constant
)
8472 /* Since displacement is signed extended to 64bit, don't allow
8473 disp32 and turn off disp32s if they are out of range. */
8474 i
.types
[this_operand
].bitfield
.disp32
= 0;
8475 if (!fits_in_signed_long (exp
->X_add_number
))
8477 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8478 if (i
.types
[this_operand
].bitfield
.baseindex
)
8480 as_bad (_("0x%lx out range of signed 32bit displacement"),
8481 (long) exp
->X_add_number
);
8487 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8488 else if (exp
->X_op
!= O_constant
8489 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8490 && exp_seg
!= absolute_section
8491 && exp_seg
!= text_section
8492 && exp_seg
!= data_section
8493 && exp_seg
!= bss_section
8494 && exp_seg
!= undefined_section
8495 && !bfd_is_com_section (exp_seg
))
8497 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8502 /* Check if this is a displacement only operand. */
8503 bigdisp
= i
.types
[this_operand
];
8504 bigdisp
.bitfield
.disp8
= 0;
8505 bigdisp
.bitfield
.disp16
= 0;
8506 bigdisp
.bitfield
.disp32
= 0;
8507 bigdisp
.bitfield
.disp32s
= 0;
8508 bigdisp
.bitfield
.disp64
= 0;
8509 if (operand_type_all_zero (&bigdisp
))
8510 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8516 /* Make sure the memory operand we've been dealt is valid.
8517 Return 1 on success, 0 on a failure. */
8520 i386_index_check (const char *operand_string
)
8522 const char *kind
= "base/index";
8523 enum flag_code addr_mode
;
8525 if (i
.prefix
[ADDR_PREFIX
])
8526 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8529 addr_mode
= flag_code
;
8531 #if INFER_ADDR_PREFIX
8532 if (i
.mem_operands
== 0)
8534 /* Infer address prefix from the first memory operand. */
8535 const reg_entry
*addr_reg
= i
.base_reg
;
8537 if (addr_reg
== NULL
)
8538 addr_reg
= i
.index_reg
;
8542 if (addr_reg
->reg_num
== RegEip
8543 || addr_reg
->reg_num
== RegEiz
8544 || addr_reg
->reg_type
.bitfield
.reg32
)
8545 addr_mode
= CODE_32BIT
;
8546 else if (flag_code
!= CODE_64BIT
8547 && addr_reg
->reg_type
.bitfield
.reg16
)
8548 addr_mode
= CODE_16BIT
;
8550 if (addr_mode
!= flag_code
)
8552 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8554 /* Change the size of any displacement too. At most one
8555 of Disp16 or Disp32 is set.
8556 FIXME. There doesn't seem to be any real need for
8557 separate Disp16 and Disp32 flags. The same goes for
8558 Imm16 and Imm32. Removing them would probably clean
8559 up the code quite a lot. */
8560 if (flag_code
!= CODE_64BIT
8561 && (i
.types
[this_operand
].bitfield
.disp16
8562 || i
.types
[this_operand
].bitfield
.disp32
))
8563 i
.types
[this_operand
]
8564 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8571 if (current_templates
->start
->opcode_modifier
.isstring
8572 && !current_templates
->start
->opcode_modifier
.immext
8573 && (current_templates
->end
[-1].opcode_modifier
.isstring
8576 /* Memory operands of string insns are special in that they only allow
8577 a single register (rDI, rSI, or rBX) as their memory address. */
8578 const reg_entry
*expected_reg
;
8579 static const char *di_si
[][2] =
8585 static const char *bx
[] = { "ebx", "bx", "rbx" };
8587 kind
= "string address";
8589 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8591 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8593 if (!type
.bitfield
.baseindex
8594 || ((!i
.mem_operands
!= !intel_syntax
)
8595 && current_templates
->end
[-1].operand_types
[1]
8596 .bitfield
.baseindex
))
8597 type
= current_templates
->end
[-1].operand_types
[1];
8598 expected_reg
= hash_find (reg_hash
,
8599 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8603 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8605 if (i
.base_reg
!= expected_reg
8607 || operand_type_check (i
.types
[this_operand
], disp
))
8609 /* The second memory operand must have the same size as
8613 && !((addr_mode
== CODE_64BIT
8614 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8615 || (addr_mode
== CODE_32BIT
8616 ? i
.base_reg
->reg_type
.bitfield
.reg32
8617 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8620 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8622 intel_syntax
? '[' : '(',
8624 expected_reg
->reg_name
,
8625 intel_syntax
? ']' : ')');
8632 as_bad (_("`%s' is not a valid %s expression"),
8633 operand_string
, kind
);
8638 if (addr_mode
!= CODE_16BIT
)
8640 /* 32-bit/64-bit checks. */
8642 && (addr_mode
== CODE_64BIT
8643 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8644 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8646 || (i
.base_reg
->reg_num
8647 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8649 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8650 && !i
.index_reg
->reg_type
.bitfield
.regymm
8651 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8652 && ((addr_mode
== CODE_64BIT
8653 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8654 || i
.index_reg
->reg_num
== RegRiz
)
8655 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8656 || i
.index_reg
->reg_num
== RegEiz
))
8657 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8660 /* bndmk, bndldx, and bndstx have special restrictions. */
8661 if (current_templates
->start
->base_opcode
== 0xf30f1b
8662 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8664 /* They cannot use RIP-relative addressing. */
8665 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8667 as_bad (_("`%s' cannot be used here"), operand_string
);
8671 /* bndldx and bndstx ignore their scale factor. */
8672 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8673 && i
.log2_scale_factor
)
8674 as_warn (_("register scaling is being ignored here"));
8679 /* 16-bit checks. */
8681 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8682 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8684 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8685 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8687 && i
.base_reg
->reg_num
< 6
8688 && i
.index_reg
->reg_num
>= 6
8689 && i
.log2_scale_factor
== 0))))
8696 /* Handle vector immediates. */
8699 RC_SAE_immediate (const char *imm_start
)
8701 unsigned int match_found
, j
;
8702 const char *pstr
= imm_start
;
8710 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8712 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8716 rc_op
.type
= RC_NamesTable
[j
].type
;
8717 rc_op
.operand
= this_operand
;
8718 i
.rounding
= &rc_op
;
8722 as_bad (_("duplicated `%s'"), imm_start
);
8725 pstr
+= RC_NamesTable
[j
].len
;
8735 as_bad (_("Missing '}': '%s'"), imm_start
);
8738 /* RC/SAE immediate string should contain nothing more. */;
8741 as_bad (_("Junk after '}': '%s'"), imm_start
);
8745 exp
= &im_expressions
[i
.imm_operands
++];
8746 i
.op
[this_operand
].imms
= exp
;
8748 exp
->X_op
= O_constant
;
8749 exp
->X_add_number
= 0;
8750 exp
->X_add_symbol
= (symbolS
*) 0;
8751 exp
->X_op_symbol
= (symbolS
*) 0;
8753 i
.types
[this_operand
].bitfield
.imm8
= 1;
8757 /* Only string instructions can have a second memory operand, so
8758 reduce current_templates to just those if it contains any. */
8760 maybe_adjust_templates (void)
8762 const insn_template
*t
;
8764 gas_assert (i
.mem_operands
== 1);
8766 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8767 if (t
->opcode_modifier
.isstring
)
8770 if (t
< current_templates
->end
)
8772 static templates aux_templates
;
8773 bfd_boolean recheck
;
8775 aux_templates
.start
= t
;
8776 for (; t
< current_templates
->end
; ++t
)
8777 if (!t
->opcode_modifier
.isstring
)
8779 aux_templates
.end
= t
;
8781 /* Determine whether to re-check the first memory operand. */
8782 recheck
= (aux_templates
.start
!= current_templates
->start
8783 || t
!= current_templates
->end
);
8785 current_templates
= &aux_templates
;
8790 if (i
.memop1_string
!= NULL
8791 && i386_index_check (i
.memop1_string
) == 0)
8800 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8804 i386_att_operand (char *operand_string
)
8808 char *op_string
= operand_string
;
8810 if (is_space_char (*op_string
))
8813 /* We check for an absolute prefix (differentiating,
8814 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8815 if (*op_string
== ABSOLUTE_PREFIX
)
8818 if (is_space_char (*op_string
))
8820 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8823 /* Check if operand is a register. */
8824 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8826 i386_operand_type temp
;
8828 /* Check for a segment override by searching for ':' after a
8829 segment register. */
8831 if (is_space_char (*op_string
))
8833 if (*op_string
== ':'
8834 && (r
->reg_type
.bitfield
.sreg2
8835 || r
->reg_type
.bitfield
.sreg3
))
8840 i
.seg
[i
.mem_operands
] = &es
;
8843 i
.seg
[i
.mem_operands
] = &cs
;
8846 i
.seg
[i
.mem_operands
] = &ss
;
8849 i
.seg
[i
.mem_operands
] = &ds
;
8852 i
.seg
[i
.mem_operands
] = &fs
;
8855 i
.seg
[i
.mem_operands
] = &gs
;
8859 /* Skip the ':' and whitespace. */
8861 if (is_space_char (*op_string
))
8864 if (!is_digit_char (*op_string
)
8865 && !is_identifier_char (*op_string
)
8866 && *op_string
!= '('
8867 && *op_string
!= ABSOLUTE_PREFIX
)
8869 as_bad (_("bad memory operand `%s'"), op_string
);
8872 /* Handle case of %es:*foo. */
8873 if (*op_string
== ABSOLUTE_PREFIX
)
8876 if (is_space_char (*op_string
))
8878 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8880 goto do_memory_reference
;
8883 /* Handle vector operations. */
8884 if (*op_string
== '{')
8886 op_string
= check_VecOperations (op_string
, NULL
);
8887 if (op_string
== NULL
)
8893 as_bad (_("junk `%s' after register"), op_string
);
8897 temp
.bitfield
.baseindex
= 0;
8898 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8900 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8901 i
.op
[this_operand
].regs
= r
;
8904 else if (*op_string
== REGISTER_PREFIX
)
8906 as_bad (_("bad register name `%s'"), op_string
);
8909 else if (*op_string
== IMMEDIATE_PREFIX
)
8912 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8914 as_bad (_("immediate operand illegal with absolute jump"));
8917 if (!i386_immediate (op_string
))
8920 else if (RC_SAE_immediate (operand_string
))
8922 /* If it is a RC or SAE immediate, do nothing. */
8925 else if (is_digit_char (*op_string
)
8926 || is_identifier_char (*op_string
)
8927 || *op_string
== '"'
8928 || *op_string
== '(')
8930 /* This is a memory reference of some sort. */
8933 /* Start and end of displacement string expression (if found). */
8934 char *displacement_string_start
;
8935 char *displacement_string_end
;
8938 do_memory_reference
:
8939 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8941 if ((i
.mem_operands
== 1
8942 && !current_templates
->start
->opcode_modifier
.isstring
)
8943 || i
.mem_operands
== 2)
8945 as_bad (_("too many memory references for `%s'"),
8946 current_templates
->start
->name
);
8950 /* Check for base index form. We detect the base index form by
8951 looking for an ')' at the end of the operand, searching
8952 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8954 base_string
= op_string
+ strlen (op_string
);
8956 /* Handle vector operations. */
8957 vop_start
= strchr (op_string
, '{');
8958 if (vop_start
&& vop_start
< base_string
)
8960 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8962 base_string
= vop_start
;
8966 if (is_space_char (*base_string
))
8969 /* If we only have a displacement, set-up for it to be parsed later. */
8970 displacement_string_start
= op_string
;
8971 displacement_string_end
= base_string
+ 1;
8973 if (*base_string
== ')')
8976 unsigned int parens_balanced
= 1;
8977 /* We've already checked that the number of left & right ()'s are
8978 equal, so this loop will not be infinite. */
8982 if (*base_string
== ')')
8984 if (*base_string
== '(')
8987 while (parens_balanced
);
8989 temp_string
= base_string
;
8991 /* Skip past '(' and whitespace. */
8993 if (is_space_char (*base_string
))
8996 if (*base_string
== ','
8997 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9000 displacement_string_end
= temp_string
;
9002 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9006 base_string
= end_op
;
9007 if (is_space_char (*base_string
))
9011 /* There may be an index reg or scale factor here. */
9012 if (*base_string
== ',')
9015 if (is_space_char (*base_string
))
9018 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9021 base_string
= end_op
;
9022 if (is_space_char (*base_string
))
9024 if (*base_string
== ',')
9027 if (is_space_char (*base_string
))
9030 else if (*base_string
!= ')')
9032 as_bad (_("expecting `,' or `)' "
9033 "after index register in `%s'"),
9038 else if (*base_string
== REGISTER_PREFIX
)
9040 end_op
= strchr (base_string
, ',');
9043 as_bad (_("bad register name `%s'"), base_string
);
9047 /* Check for scale factor. */
9048 if (*base_string
!= ')')
9050 char *end_scale
= i386_scale (base_string
);
9055 base_string
= end_scale
;
9056 if (is_space_char (*base_string
))
9058 if (*base_string
!= ')')
9060 as_bad (_("expecting `)' "
9061 "after scale factor in `%s'"),
9066 else if (!i
.index_reg
)
9068 as_bad (_("expecting index register or scale factor "
9069 "after `,'; got '%c'"),
9074 else if (*base_string
!= ')')
9076 as_bad (_("expecting `,' or `)' "
9077 "after base register in `%s'"),
9082 else if (*base_string
== REGISTER_PREFIX
)
9084 end_op
= strchr (base_string
, ',');
9087 as_bad (_("bad register name `%s'"), base_string
);
9092 /* If there's an expression beginning the operand, parse it,
9093 assuming displacement_string_start and
9094 displacement_string_end are meaningful. */
9095 if (displacement_string_start
!= displacement_string_end
)
9097 if (!i386_displacement (displacement_string_start
,
9098 displacement_string_end
))
9102 /* Special case for (%dx) while doing input/output op. */
9104 && operand_type_equal (&i
.base_reg
->reg_type
,
9105 ®16_inoutportreg
)
9107 && i
.log2_scale_factor
== 0
9108 && i
.seg
[i
.mem_operands
] == 0
9109 && !operand_type_check (i
.types
[this_operand
], disp
))
9111 i
.types
[this_operand
] = inoutportreg
;
9115 if (i386_index_check (operand_string
) == 0)
9117 i
.types
[this_operand
].bitfield
.mem
= 1;
9118 if (i
.mem_operands
== 0)
9119 i
.memop1_string
= xstrdup (operand_string
);
9124 /* It's not a memory operand; argh! */
9125 as_bad (_("invalid char %s beginning operand %d `%s'"),
9126 output_invalid (*op_string
),
9131 return 1; /* Normal return. */
9134 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9135 that an rs_machine_dependent frag may reach. */
9138 i386_frag_max_var (fragS
*frag
)
9140 /* The only relaxable frags are for jumps.
9141 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9142 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9143 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9148 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9150 /* STT_GNU_IFUNC symbol must go through PLT. */
9151 if ((symbol_get_bfdsym (fr_symbol
)->flags
9152 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9155 if (!S_IS_EXTERNAL (fr_symbol
))
9156 /* Symbol may be weak or local. */
9157 return !S_IS_WEAK (fr_symbol
);
9159 /* Global symbols with non-default visibility can't be preempted. */
9160 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9163 if (fr_var
!= NO_RELOC
)
9164 switch ((enum bfd_reloc_code_real
) fr_var
)
9166 case BFD_RELOC_386_PLT32
:
9167 case BFD_RELOC_X86_64_PLT32
:
9168 /* Symbol with PLT relocatin may be preempted. */
9174 /* Global symbols with default visibility in a shared library may be
9175 preempted by another definition. */
9180 /* md_estimate_size_before_relax()
9182 Called just before relax() for rs_machine_dependent frags. The x86
9183 assembler uses these frags to handle variable size jump
9186 Any symbol that is now undefined will not become defined.
9187 Return the correct fr_subtype in the frag.
9188 Return the initial "guess for variable size of frag" to caller.
9189 The guess is actually the growth beyond the fixed part. Whatever
9190 we do to grow the fixed or variable part contributes to our
9194 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9196 /* We've already got fragP->fr_subtype right; all we have to do is
9197 check for un-relaxable symbols. On an ELF system, we can't relax
9198 an externally visible symbol, because it may be overridden by a
9200 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9203 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9206 #if defined (OBJ_COFF) && defined (TE_PE)
9207 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9208 && S_IS_WEAK (fragP
->fr_symbol
))
9212 /* Symbol is undefined in this segment, or we need to keep a
9213 reloc so that weak symbols can be overridden. */
9214 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9215 enum bfd_reloc_code_real reloc_type
;
9216 unsigned char *opcode
;
9219 if (fragP
->fr_var
!= NO_RELOC
)
9220 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9222 reloc_type
= BFD_RELOC_16_PCREL
;
9224 reloc_type
= BFD_RELOC_32_PCREL
;
9226 old_fr_fix
= fragP
->fr_fix
;
9227 opcode
= (unsigned char *) fragP
->fr_opcode
;
9229 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9232 /* Make jmp (0xeb) a (d)word displacement jump. */
9234 fragP
->fr_fix
+= size
;
9235 fix_new (fragP
, old_fr_fix
, size
,
9237 fragP
->fr_offset
, 1,
9243 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9245 /* Negate the condition, and branch past an
9246 unconditional jump. */
9249 /* Insert an unconditional jump. */
9251 /* We added two extra opcode bytes, and have a two byte
9253 fragP
->fr_fix
+= 2 + 2;
9254 fix_new (fragP
, old_fr_fix
+ 2, 2,
9256 fragP
->fr_offset
, 1,
9263 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9268 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9270 fragP
->fr_offset
, 1,
9272 fixP
->fx_signed
= 1;
9276 /* This changes the byte-displacement jump 0x7N
9277 to the (d)word-displacement jump 0x0f,0x8N. */
9278 opcode
[1] = opcode
[0] + 0x10;
9279 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9280 /* We've added an opcode byte. */
9281 fragP
->fr_fix
+= 1 + size
;
9282 fix_new (fragP
, old_fr_fix
+ 1, size
,
9284 fragP
->fr_offset
, 1,
9289 BAD_CASE (fragP
->fr_subtype
);
9293 return fragP
->fr_fix
- old_fr_fix
;
9296 /* Guess size depending on current relax state. Initially the relax
9297 state will correspond to a short jump and we return 1, because
9298 the variable part of the frag (the branch offset) is one byte
9299 long. However, we can relax a section more than once and in that
9300 case we must either set fr_subtype back to the unrelaxed state,
9301 or return the value for the appropriate branch. */
9302 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9305 /* Called after relax() is finished.
9307 In: Address of frag.
9308 fr_type == rs_machine_dependent.
9309 fr_subtype is what the address relaxed to.
9311 Out: Any fixSs and constants are set up.
9312 Caller will turn frag into a ".space 0". */
9315 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9318 unsigned char *opcode
;
9319 unsigned char *where_to_put_displacement
= NULL
;
9320 offsetT target_address
;
9321 offsetT opcode_address
;
9322 unsigned int extension
= 0;
9323 offsetT displacement_from_opcode_start
;
9325 opcode
= (unsigned char *) fragP
->fr_opcode
;
9327 /* Address we want to reach in file space. */
9328 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9330 /* Address opcode resides at in file space. */
9331 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9333 /* Displacement from opcode start to fill into instruction. */
9334 displacement_from_opcode_start
= target_address
- opcode_address
;
9336 if ((fragP
->fr_subtype
& BIG
) == 0)
9338 /* Don't have to change opcode. */
9339 extension
= 1; /* 1 opcode + 1 displacement */
9340 where_to_put_displacement
= &opcode
[1];
9344 if (no_cond_jump_promotion
9345 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9346 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9347 _("long jump required"));
9349 switch (fragP
->fr_subtype
)
9351 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9352 extension
= 4; /* 1 opcode + 4 displacement */
9354 where_to_put_displacement
= &opcode
[1];
9357 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9358 extension
= 2; /* 1 opcode + 2 displacement */
9360 where_to_put_displacement
= &opcode
[1];
9363 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9364 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9365 extension
= 5; /* 2 opcode + 4 displacement */
9366 opcode
[1] = opcode
[0] + 0x10;
9367 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9368 where_to_put_displacement
= &opcode
[2];
9371 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9372 extension
= 3; /* 2 opcode + 2 displacement */
9373 opcode
[1] = opcode
[0] + 0x10;
9374 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9375 where_to_put_displacement
= &opcode
[2];
9378 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9383 where_to_put_displacement
= &opcode
[3];
9387 BAD_CASE (fragP
->fr_subtype
);
9392 /* If size if less then four we are sure that the operand fits,
9393 but if it's 4, then it could be that the displacement is larger
9395 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9397 && ((addressT
) (displacement_from_opcode_start
- extension
9398 + ((addressT
) 1 << 31))
9399 > (((addressT
) 2 << 31) - 1)))
9401 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9402 _("jump target out of range"));
9403 /* Make us emit 0. */
9404 displacement_from_opcode_start
= extension
;
9406 /* Now put displacement after opcode. */
9407 md_number_to_chars ((char *) where_to_put_displacement
,
9408 (valueT
) (displacement_from_opcode_start
- extension
),
9409 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9410 fragP
->fr_fix
+= extension
;
9413 /* Apply a fixup (fixP) to segment data, once it has been determined
9414 by our caller that we have all the info we need to fix it up.
9416 Parameter valP is the pointer to the value of the bits.
9418 On the 386, immediates, displacements, and data pointers are all in
9419 the same (little-endian) format, so we don't need to care about which
9423 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9425 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9426 valueT value
= *valP
;
9428 #if !defined (TE_Mach)
9431 switch (fixP
->fx_r_type
)
9437 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9440 case BFD_RELOC_X86_64_32S
:
9441 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9444 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9447 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9452 if (fixP
->fx_addsy
!= NULL
9453 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9454 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9455 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9456 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9457 && !use_rela_relocations
)
9459 /* This is a hack. There should be a better way to handle this.
9460 This covers for the fact that bfd_install_relocation will
9461 subtract the current location (for partial_inplace, PC relative
9462 relocations); see more below. */
9466 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9469 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9474 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9477 || (symbol_section_p (fixP
->fx_addsy
)
9478 && sym_seg
!= absolute_section
))
9479 && !generic_force_reloc (fixP
))
9481 /* Yes, we add the values in twice. This is because
9482 bfd_install_relocation subtracts them out again. I think
9483 bfd_install_relocation is broken, but I don't dare change
9485 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9489 #if defined (OBJ_COFF) && defined (TE_PE)
9490 /* For some reason, the PE format does not store a
9491 section address offset for a PC relative symbol. */
9492 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9493 || S_IS_WEAK (fixP
->fx_addsy
))
9494 value
+= md_pcrel_from (fixP
);
9497 #if defined (OBJ_COFF) && defined (TE_PE)
9498 if (fixP
->fx_addsy
!= NULL
9499 && S_IS_WEAK (fixP
->fx_addsy
)
9500 /* PR 16858: Do not modify weak function references. */
9501 && ! fixP
->fx_pcrel
)
9503 #if !defined (TE_PEP)
9504 /* For x86 PE weak function symbols are neither PC-relative
9505 nor do they set S_IS_FUNCTION. So the only reliable way
9506 to detect them is to check the flags of their containing
9508 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9509 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9513 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9517 /* Fix a few things - the dynamic linker expects certain values here,
9518 and we must not disappoint it. */
9519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9520 if (IS_ELF
&& fixP
->fx_addsy
)
9521 switch (fixP
->fx_r_type
)
9523 case BFD_RELOC_386_PLT32
:
9524 case BFD_RELOC_X86_64_PLT32
:
9525 /* Make the jump instruction point to the address of the operand. At
9526 runtime we merely add the offset to the actual PLT entry. */
9530 case BFD_RELOC_386_TLS_GD
:
9531 case BFD_RELOC_386_TLS_LDM
:
9532 case BFD_RELOC_386_TLS_IE_32
:
9533 case BFD_RELOC_386_TLS_IE
:
9534 case BFD_RELOC_386_TLS_GOTIE
:
9535 case BFD_RELOC_386_TLS_GOTDESC
:
9536 case BFD_RELOC_X86_64_TLSGD
:
9537 case BFD_RELOC_X86_64_TLSLD
:
9538 case BFD_RELOC_X86_64_GOTTPOFF
:
9539 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9540 value
= 0; /* Fully resolved at runtime. No addend. */
9542 case BFD_RELOC_386_TLS_LE
:
9543 case BFD_RELOC_386_TLS_LDO_32
:
9544 case BFD_RELOC_386_TLS_LE_32
:
9545 case BFD_RELOC_X86_64_DTPOFF32
:
9546 case BFD_RELOC_X86_64_DTPOFF64
:
9547 case BFD_RELOC_X86_64_TPOFF32
:
9548 case BFD_RELOC_X86_64_TPOFF64
:
9549 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9552 case BFD_RELOC_386_TLS_DESC_CALL
:
9553 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9554 value
= 0; /* Fully resolved at runtime. No addend. */
9555 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9559 case BFD_RELOC_VTABLE_INHERIT
:
9560 case BFD_RELOC_VTABLE_ENTRY
:
9567 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9569 #endif /* !defined (TE_Mach) */
9571 /* Are we finished with this relocation now? */
9572 if (fixP
->fx_addsy
== NULL
)
9574 #if defined (OBJ_COFF) && defined (TE_PE)
9575 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9578 /* Remember value for tc_gen_reloc. */
9579 fixP
->fx_addnumber
= value
;
9580 /* Clear out the frag for now. */
9584 else if (use_rela_relocations
)
9586 fixP
->fx_no_overflow
= 1;
9587 /* Remember value for tc_gen_reloc. */
9588 fixP
->fx_addnumber
= value
;
9592 md_number_to_chars (p
, value
, fixP
->fx_size
);
9596 md_atof (int type
, char *litP
, int *sizeP
)
9598 /* This outputs the LITTLENUMs in REVERSE order;
9599 in accord with the bigendian 386. */
9600 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9603 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9606 output_invalid (int c
)
9609 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9612 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9613 "(0x%x)", (unsigned char) c
);
9614 return output_invalid_buf
;
9617 /* REG_STRING starts *before* REGISTER_PREFIX. */
9619 static const reg_entry
*
9620 parse_real_register (char *reg_string
, char **end_op
)
9622 char *s
= reg_string
;
9624 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9627 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9628 if (*s
== REGISTER_PREFIX
)
9631 if (is_space_char (*s
))
9635 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9637 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9638 return (const reg_entry
*) NULL
;
9642 /* For naked regs, make sure that we are not dealing with an identifier.
9643 This prevents confusing an identifier like `eax_var' with register
9645 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9646 return (const reg_entry
*) NULL
;
9650 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9652 /* Handle floating point regs, allowing spaces in the (i) part. */
9653 if (r
== i386_regtab
/* %st is first entry of table */)
9655 if (is_space_char (*s
))
9660 if (is_space_char (*s
))
9662 if (*s
>= '0' && *s
<= '7')
9666 if (is_space_char (*s
))
9671 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9676 /* We have "%st(" then garbage. */
9677 return (const reg_entry
*) NULL
;
9681 if (r
== NULL
|| allow_pseudo_reg
)
9684 if (operand_type_all_zero (&r
->reg_type
))
9685 return (const reg_entry
*) NULL
;
9687 if ((r
->reg_type
.bitfield
.reg32
9688 || r
->reg_type
.bitfield
.sreg3
9689 || r
->reg_type
.bitfield
.control
9690 || r
->reg_type
.bitfield
.debug
9691 || r
->reg_type
.bitfield
.test
)
9692 && !cpu_arch_flags
.bitfield
.cpui386
)
9693 return (const reg_entry
*) NULL
;
9695 if (r
->reg_type
.bitfield
.floatreg
9696 && !cpu_arch_flags
.bitfield
.cpu8087
9697 && !cpu_arch_flags
.bitfield
.cpu287
9698 && !cpu_arch_flags
.bitfield
.cpu387
)
9699 return (const reg_entry
*) NULL
;
9701 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9702 return (const reg_entry
*) NULL
;
9704 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9705 return (const reg_entry
*) NULL
;
9707 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9708 return (const reg_entry
*) NULL
;
9710 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9711 return (const reg_entry
*) NULL
;
9713 if (r
->reg_type
.bitfield
.regmask
9714 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9715 return (const reg_entry
*) NULL
;
9717 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9718 if (!allow_index_reg
9719 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9720 return (const reg_entry
*) NULL
;
9722 /* Upper 16 vector register is only available with VREX in 64bit
9724 if ((r
->reg_flags
& RegVRex
))
9726 if (!cpu_arch_flags
.bitfield
.cpuvrex
9727 || flag_code
!= CODE_64BIT
)
9728 return (const reg_entry
*) NULL
;
9733 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9734 || r
->reg_type
.bitfield
.reg64
)
9735 && (!cpu_arch_flags
.bitfield
.cpulm
9736 || !operand_type_equal (&r
->reg_type
, &control
))
9737 && flag_code
!= CODE_64BIT
)
9738 return (const reg_entry
*) NULL
;
9740 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9741 return (const reg_entry
*) NULL
;
9746 /* REG_STRING starts *before* REGISTER_PREFIX. */
9748 static const reg_entry
*
9749 parse_register (char *reg_string
, char **end_op
)
9753 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9754 r
= parse_real_register (reg_string
, end_op
);
9759 char *save
= input_line_pointer
;
9763 input_line_pointer
= reg_string
;
9764 c
= get_symbol_name (®_string
);
9765 symbolP
= symbol_find (reg_string
);
9766 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9768 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9770 know (e
->X_op
== O_register
);
9771 know (e
->X_add_number
>= 0
9772 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9773 r
= i386_regtab
+ e
->X_add_number
;
9774 if ((r
->reg_flags
& RegVRex
))
9776 *end_op
= input_line_pointer
;
9778 *input_line_pointer
= c
;
9779 input_line_pointer
= save
;
9785 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9788 char *end
= input_line_pointer
;
9791 r
= parse_register (name
, &input_line_pointer
);
9792 if (r
&& end
<= input_line_pointer
)
9794 *nextcharP
= *input_line_pointer
;
9795 *input_line_pointer
= 0;
9796 e
->X_op
= O_register
;
9797 e
->X_add_number
= r
- i386_regtab
;
9800 input_line_pointer
= end
;
9802 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9806 md_operand (expressionS
*e
)
9811 switch (*input_line_pointer
)
9813 case REGISTER_PREFIX
:
9814 r
= parse_real_register (input_line_pointer
, &end
);
9817 e
->X_op
= O_register
;
9818 e
->X_add_number
= r
- i386_regtab
;
9819 input_line_pointer
= end
;
9824 gas_assert (intel_syntax
);
9825 end
= input_line_pointer
++;
9827 if (*input_line_pointer
== ']')
9829 ++input_line_pointer
;
9830 e
->X_op_symbol
= make_expr_symbol (e
);
9831 e
->X_add_symbol
= NULL
;
9832 e
->X_add_number
= 0;
9838 input_line_pointer
= end
;
9845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9846 const char *md_shortopts
= "kVQ:sqn";
9848 const char *md_shortopts
= "qn";
9851 #define OPTION_32 (OPTION_MD_BASE + 0)
9852 #define OPTION_64 (OPTION_MD_BASE + 1)
9853 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9854 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9855 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9856 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9857 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9858 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9859 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9860 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9861 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9862 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9863 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9864 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9865 #define OPTION_X32 (OPTION_MD_BASE + 14)
9866 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9867 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9868 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9869 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9870 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9871 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9872 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9873 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9874 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9875 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9876 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9878 struct option md_longopts
[] =
9880 {"32", no_argument
, NULL
, OPTION_32
},
9881 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9882 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9883 {"64", no_argument
, NULL
, OPTION_64
},
9885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9886 {"x32", no_argument
, NULL
, OPTION_X32
},
9887 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9889 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9890 {"march", required_argument
, NULL
, OPTION_MARCH
},
9891 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9892 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9893 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9894 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9895 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9896 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9897 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9898 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9899 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9900 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9901 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9902 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9903 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9904 # if defined (TE_PE) || defined (TE_PEP)
9905 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9907 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9908 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9909 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9910 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9911 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9912 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9913 {NULL
, no_argument
, NULL
, 0}
9915 size_t md_longopts_size
= sizeof (md_longopts
);
9918 md_parse_option (int c
, const char *arg
)
9921 char *arch
, *next
, *saved
;
9926 optimize_align_code
= 0;
9933 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9934 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9935 should be emitted or not. FIXME: Not implemented. */
9939 /* -V: SVR4 argument to print version ID. */
9941 print_version_id ();
9944 /* -k: Ignore for FreeBSD compatibility. */
9949 /* -s: On i386 Solaris, this tells the native assembler to use
9950 .stab instead of .stab.excl. We always use .stab anyhow. */
9953 case OPTION_MSHARED
:
9957 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9958 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9961 const char **list
, **l
;
9963 list
= bfd_target_list ();
9964 for (l
= list
; *l
!= NULL
; l
++)
9965 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9966 || strcmp (*l
, "coff-x86-64") == 0
9967 || strcmp (*l
, "pe-x86-64") == 0
9968 || strcmp (*l
, "pei-x86-64") == 0
9969 || strcmp (*l
, "mach-o-x86-64") == 0)
9971 default_arch
= "x86_64";
9975 as_fatal (_("no compiled in support for x86_64"));
9981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9985 const char **list
, **l
;
9987 list
= bfd_target_list ();
9988 for (l
= list
; *l
!= NULL
; l
++)
9989 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9991 default_arch
= "x86_64:32";
9995 as_fatal (_("no compiled in support for 32bit x86_64"));
9999 as_fatal (_("32bit x86_64 is only supported for ELF"));
10004 default_arch
= "i386";
10007 case OPTION_DIVIDE
:
10008 #ifdef SVR4_COMMENT_CHARS
10013 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10015 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10019 i386_comment_chars
= n
;
10025 saved
= xstrdup (arg
);
10027 /* Allow -march=+nosse. */
10033 as_fatal (_("invalid -march= option: `%s'"), arg
);
10034 next
= strchr (arch
, '+');
10037 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10039 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10042 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10045 cpu_arch_name
= cpu_arch
[j
].name
;
10046 cpu_sub_arch_name
= NULL
;
10047 cpu_arch_flags
= cpu_arch
[j
].flags
;
10048 cpu_arch_isa
= cpu_arch
[j
].type
;
10049 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10050 if (!cpu_arch_tune_set
)
10052 cpu_arch_tune
= cpu_arch_isa
;
10053 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10057 else if (*cpu_arch
[j
].name
== '.'
10058 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10060 /* ISA entension. */
10061 i386_cpu_flags flags
;
10063 flags
= cpu_flags_or (cpu_arch_flags
,
10064 cpu_arch
[j
].flags
);
10066 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10068 if (cpu_sub_arch_name
)
10070 char *name
= cpu_sub_arch_name
;
10071 cpu_sub_arch_name
= concat (name
,
10073 (const char *) NULL
);
10077 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10078 cpu_arch_flags
= flags
;
10079 cpu_arch_isa_flags
= flags
;
10085 if (j
>= ARRAY_SIZE (cpu_arch
))
10087 /* Disable an ISA entension. */
10088 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10089 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10091 i386_cpu_flags flags
;
10093 flags
= cpu_flags_and_not (cpu_arch_flags
,
10094 cpu_noarch
[j
].flags
);
10095 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10097 if (cpu_sub_arch_name
)
10099 char *name
= cpu_sub_arch_name
;
10100 cpu_sub_arch_name
= concat (arch
,
10101 (const char *) NULL
);
10105 cpu_sub_arch_name
= xstrdup (arch
);
10106 cpu_arch_flags
= flags
;
10107 cpu_arch_isa_flags
= flags
;
10112 if (j
>= ARRAY_SIZE (cpu_noarch
))
10113 j
= ARRAY_SIZE (cpu_arch
);
10116 if (j
>= ARRAY_SIZE (cpu_arch
))
10117 as_fatal (_("invalid -march= option: `%s'"), arg
);
10121 while (next
!= NULL
);
10127 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10128 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10130 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10132 cpu_arch_tune_set
= 1;
10133 cpu_arch_tune
= cpu_arch
[j
].type
;
10134 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10138 if (j
>= ARRAY_SIZE (cpu_arch
))
10139 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10142 case OPTION_MMNEMONIC
:
10143 if (strcasecmp (arg
, "att") == 0)
10144 intel_mnemonic
= 0;
10145 else if (strcasecmp (arg
, "intel") == 0)
10146 intel_mnemonic
= 1;
10148 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10151 case OPTION_MSYNTAX
:
10152 if (strcasecmp (arg
, "att") == 0)
10154 else if (strcasecmp (arg
, "intel") == 0)
10157 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10160 case OPTION_MINDEX_REG
:
10161 allow_index_reg
= 1;
10164 case OPTION_MNAKED_REG
:
10165 allow_naked_reg
= 1;
10168 case OPTION_MOLD_GCC
:
10172 case OPTION_MSSE2AVX
:
10176 case OPTION_MSSE_CHECK
:
10177 if (strcasecmp (arg
, "error") == 0)
10178 sse_check
= check_error
;
10179 else if (strcasecmp (arg
, "warning") == 0)
10180 sse_check
= check_warning
;
10181 else if (strcasecmp (arg
, "none") == 0)
10182 sse_check
= check_none
;
10184 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10187 case OPTION_MOPERAND_CHECK
:
10188 if (strcasecmp (arg
, "error") == 0)
10189 operand_check
= check_error
;
10190 else if (strcasecmp (arg
, "warning") == 0)
10191 operand_check
= check_warning
;
10192 else if (strcasecmp (arg
, "none") == 0)
10193 operand_check
= check_none
;
10195 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10198 case OPTION_MAVXSCALAR
:
10199 if (strcasecmp (arg
, "128") == 0)
10200 avxscalar
= vex128
;
10201 else if (strcasecmp (arg
, "256") == 0)
10202 avxscalar
= vex256
;
10204 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10207 case OPTION_MADD_BND_PREFIX
:
10208 add_bnd_prefix
= 1;
10211 case OPTION_MEVEXLIG
:
10212 if (strcmp (arg
, "128") == 0)
10213 evexlig
= evexl128
;
10214 else if (strcmp (arg
, "256") == 0)
10215 evexlig
= evexl256
;
10216 else if (strcmp (arg
, "512") == 0)
10217 evexlig
= evexl512
;
10219 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10222 case OPTION_MEVEXRCIG
:
10223 if (strcmp (arg
, "rne") == 0)
10225 else if (strcmp (arg
, "rd") == 0)
10227 else if (strcmp (arg
, "ru") == 0)
10229 else if (strcmp (arg
, "rz") == 0)
10232 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10235 case OPTION_MEVEXWIG
:
10236 if (strcmp (arg
, "0") == 0)
10238 else if (strcmp (arg
, "1") == 0)
10241 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10244 # if defined (TE_PE) || defined (TE_PEP)
10245 case OPTION_MBIG_OBJ
:
10250 case OPTION_MOMIT_LOCK_PREFIX
:
10251 if (strcasecmp (arg
, "yes") == 0)
10252 omit_lock_prefix
= 1;
10253 else if (strcasecmp (arg
, "no") == 0)
10254 omit_lock_prefix
= 0;
10256 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10259 case OPTION_MFENCE_AS_LOCK_ADD
:
10260 if (strcasecmp (arg
, "yes") == 0)
10262 else if (strcasecmp (arg
, "no") == 0)
10265 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10268 case OPTION_MRELAX_RELOCATIONS
:
10269 if (strcasecmp (arg
, "yes") == 0)
10270 generate_relax_relocations
= 1;
10271 else if (strcasecmp (arg
, "no") == 0)
10272 generate_relax_relocations
= 0;
10274 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10277 case OPTION_MAMD64
:
10281 case OPTION_MINTEL64
:
10291 #define MESSAGE_TEMPLATE \
10295 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10296 int *left_p
, const char *name
, int len
)
10298 int size
= sizeof (MESSAGE_TEMPLATE
);
10299 int left
= *left_p
;
10301 /* Reserve 2 spaces for ", " or ",\0" */
10304 /* Check if there is any room. */
10312 p
= mempcpy (p
, name
, len
);
10316 /* Output the current message now and start a new one. */
10319 fprintf (stream
, "%s\n", message
);
10321 left
= size
- (start
- message
) - len
- 2;
10323 gas_assert (left
>= 0);
10325 p
= mempcpy (p
, name
, len
);
10333 show_arch (FILE *stream
, int ext
, int check
)
10335 static char message
[] = MESSAGE_TEMPLATE
;
10336 char *start
= message
+ 27;
10338 int size
= sizeof (MESSAGE_TEMPLATE
);
10345 left
= size
- (start
- message
);
10346 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10348 /* Should it be skipped? */
10349 if (cpu_arch
[j
].skip
)
10352 name
= cpu_arch
[j
].name
;
10353 len
= cpu_arch
[j
].len
;
10356 /* It is an extension. Skip if we aren't asked to show it. */
10367 /* It is an processor. Skip if we show only extension. */
10370 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10372 /* It is an impossible processor - skip. */
10376 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10379 /* Display disabled extensions. */
10381 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10383 name
= cpu_noarch
[j
].name
;
10384 len
= cpu_noarch
[j
].len
;
10385 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10390 fprintf (stream
, "%s\n", message
);
10394 md_show_usage (FILE *stream
)
10396 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10397 fprintf (stream
, _("\
10399 -V print assembler version number\n\
10402 fprintf (stream
, _("\
10403 -n Do not optimize code alignment\n\
10404 -q quieten some warnings\n"));
10405 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10406 fprintf (stream
, _("\
10409 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10410 || defined (TE_PE) || defined (TE_PEP))
10411 fprintf (stream
, _("\
10412 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10414 #ifdef SVR4_COMMENT_CHARS
10415 fprintf (stream
, _("\
10416 --divide do not treat `/' as a comment character\n"));
10418 fprintf (stream
, _("\
10419 --divide ignored\n"));
10421 fprintf (stream
, _("\
10422 -march=CPU[,+EXTENSION...]\n\
10423 generate code for CPU and EXTENSION, CPU is one of:\n"));
10424 show_arch (stream
, 0, 1);
10425 fprintf (stream
, _("\
10426 EXTENSION is combination of:\n"));
10427 show_arch (stream
, 1, 0);
10428 fprintf (stream
, _("\
10429 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10430 show_arch (stream
, 0, 0);
10431 fprintf (stream
, _("\
10432 -msse2avx encode SSE instructions with VEX prefix\n"));
10433 fprintf (stream
, _("\
10434 -msse-check=[none|error|warning]\n\
10435 check SSE instructions\n"));
10436 fprintf (stream
, _("\
10437 -moperand-check=[none|error|warning]\n\
10438 check operand combinations for validity\n"));
10439 fprintf (stream
, _("\
10440 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10442 fprintf (stream
, _("\
10443 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10445 fprintf (stream
, _("\
10446 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10447 for EVEX.W bit ignored instructions\n"));
10448 fprintf (stream
, _("\
10449 -mevexrcig=[rne|rd|ru|rz]\n\
10450 encode EVEX instructions with specific EVEX.RC value\n\
10451 for SAE-only ignored instructions\n"));
10452 fprintf (stream
, _("\
10453 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10454 fprintf (stream
, _("\
10455 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10456 fprintf (stream
, _("\
10457 -mindex-reg support pseudo index registers\n"));
10458 fprintf (stream
, _("\
10459 -mnaked-reg don't require `%%' prefix for registers\n"));
10460 fprintf (stream
, _("\
10461 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10462 fprintf (stream
, _("\
10463 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10464 fprintf (stream
, _("\
10465 -mshared disable branch optimization for shared code\n"));
10466 # if defined (TE_PE) || defined (TE_PEP)
10467 fprintf (stream
, _("\
10468 -mbig-obj generate big object files\n"));
10470 fprintf (stream
, _("\
10471 -momit-lock-prefix=[no|yes]\n\
10472 strip all lock prefixes\n"));
10473 fprintf (stream
, _("\
10474 -mfence-as-lock-add=[no|yes]\n\
10475 encode lfence, mfence and sfence as\n\
10476 lock addl $0x0, (%%{re}sp)\n"));
10477 fprintf (stream
, _("\
10478 -mrelax-relocations=[no|yes]\n\
10479 generate relax relocations\n"));
10480 fprintf (stream
, _("\
10481 -mamd64 accept only AMD64 ISA\n"));
10482 fprintf (stream
, _("\
10483 -mintel64 accept only Intel64 ISA\n"));
10486 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10487 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10488 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10490 /* Pick the target format to use. */
10493 i386_target_format (void)
10495 if (!strncmp (default_arch
, "x86_64", 6))
10497 update_code_flag (CODE_64BIT
, 1);
10498 if (default_arch
[6] == '\0')
10499 x86_elf_abi
= X86_64_ABI
;
10501 x86_elf_abi
= X86_64_X32_ABI
;
10503 else if (!strcmp (default_arch
, "i386"))
10504 update_code_flag (CODE_32BIT
, 1);
10505 else if (!strcmp (default_arch
, "iamcu"))
10507 update_code_flag (CODE_32BIT
, 1);
10508 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10510 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10511 cpu_arch_name
= "iamcu";
10512 cpu_sub_arch_name
= NULL
;
10513 cpu_arch_flags
= iamcu_flags
;
10514 cpu_arch_isa
= PROCESSOR_IAMCU
;
10515 cpu_arch_isa_flags
= iamcu_flags
;
10516 if (!cpu_arch_tune_set
)
10518 cpu_arch_tune
= cpu_arch_isa
;
10519 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10522 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10523 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10527 as_fatal (_("unknown architecture"));
10529 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10530 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10531 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10532 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10534 switch (OUTPUT_FLAVOR
)
10536 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10537 case bfd_target_aout_flavour
:
10538 return AOUT_TARGET_FORMAT
;
10540 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10541 # if defined (TE_PE) || defined (TE_PEP)
10542 case bfd_target_coff_flavour
:
10543 if (flag_code
== CODE_64BIT
)
10544 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10547 # elif defined (TE_GO32)
10548 case bfd_target_coff_flavour
:
10549 return "coff-go32";
10551 case bfd_target_coff_flavour
:
10552 return "coff-i386";
10555 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10556 case bfd_target_elf_flavour
:
10558 const char *format
;
10560 switch (x86_elf_abi
)
10563 format
= ELF_TARGET_FORMAT
;
10566 use_rela_relocations
= 1;
10568 format
= ELF_TARGET_FORMAT64
;
10570 case X86_64_X32_ABI
:
10571 use_rela_relocations
= 1;
10573 disallow_64bit_reloc
= 1;
10574 format
= ELF_TARGET_FORMAT32
;
10577 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10579 if (x86_elf_abi
!= X86_64_ABI
)
10580 as_fatal (_("Intel L1OM is 64bit only"));
10581 return ELF_TARGET_L1OM_FORMAT
;
10583 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10585 if (x86_elf_abi
!= X86_64_ABI
)
10586 as_fatal (_("Intel K1OM is 64bit only"));
10587 return ELF_TARGET_K1OM_FORMAT
;
10589 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10591 if (x86_elf_abi
!= I386_ABI
)
10592 as_fatal (_("Intel MCU is 32bit only"));
10593 return ELF_TARGET_IAMCU_FORMAT
;
10599 #if defined (OBJ_MACH_O)
10600 case bfd_target_mach_o_flavour
:
10601 if (flag_code
== CODE_64BIT
)
10603 use_rela_relocations
= 1;
10605 return "mach-o-x86-64";
10608 return "mach-o-i386";
10616 #endif /* OBJ_MAYBE_ more than one */
10619 md_undefined_symbol (char *name
)
10621 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10622 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10623 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10624 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10628 if (symbol_find (name
))
10629 as_bad (_("GOT already in symbol table"));
10630 GOT_symbol
= symbol_new (name
, undefined_section
,
10631 (valueT
) 0, &zero_address_frag
);
10638 /* Round up a section size to the appropriate boundary. */
10641 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10643 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10644 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10646 /* For a.out, force the section size to be aligned. If we don't do
10647 this, BFD will align it for us, but it will not write out the
10648 final bytes of the section. This may be a bug in BFD, but it is
10649 easier to fix it here since that is how the other a.out targets
10653 align
= bfd_get_section_alignment (stdoutput
, segment
);
10654 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10661 /* On the i386, PC-relative offsets are relative to the start of the
10662 next instruction. That is, the address of the offset, plus its
10663 size, since the offset is always the last part of the insn. */
10666 md_pcrel_from (fixS
*fixP
)
10668 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10674 s_bss (int ignore ATTRIBUTE_UNUSED
)
10678 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10680 obj_elf_section_change_hook ();
10682 temp
= get_absolute_expression ();
10683 subseg_set (bss_section
, (subsegT
) temp
);
10684 demand_empty_rest_of_line ();
10690 i386_validate_fix (fixS
*fixp
)
10692 if (fixp
->fx_subsy
)
10694 if (fixp
->fx_subsy
== GOT_symbol
)
10696 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10700 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10701 if (fixp
->fx_tcbit2
)
10702 fixp
->fx_r_type
= (fixp
->fx_tcbit
10703 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10704 : BFD_RELOC_X86_64_GOTPCRELX
);
10707 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10712 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10714 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10716 fixp
->fx_subsy
= 0;
10719 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10720 else if (!object_64bit
)
10722 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10723 && fixp
->fx_tcbit2
)
10724 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10730 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10733 bfd_reloc_code_real_type code
;
10735 switch (fixp
->fx_r_type
)
10737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10738 case BFD_RELOC_SIZE32
:
10739 case BFD_RELOC_SIZE64
:
10740 if (S_IS_DEFINED (fixp
->fx_addsy
)
10741 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10743 /* Resolve size relocation against local symbol to size of
10744 the symbol plus addend. */
10745 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10746 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10747 && !fits_in_unsigned_long (value
))
10748 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10749 _("symbol size computation overflow"));
10750 fixp
->fx_addsy
= NULL
;
10751 fixp
->fx_subsy
= NULL
;
10752 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10756 /* Fall through. */
10758 case BFD_RELOC_X86_64_PLT32
:
10759 case BFD_RELOC_X86_64_GOT32
:
10760 case BFD_RELOC_X86_64_GOTPCREL
:
10761 case BFD_RELOC_X86_64_GOTPCRELX
:
10762 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10763 case BFD_RELOC_386_PLT32
:
10764 case BFD_RELOC_386_GOT32
:
10765 case BFD_RELOC_386_GOT32X
:
10766 case BFD_RELOC_386_GOTOFF
:
10767 case BFD_RELOC_386_GOTPC
:
10768 case BFD_RELOC_386_TLS_GD
:
10769 case BFD_RELOC_386_TLS_LDM
:
10770 case BFD_RELOC_386_TLS_LDO_32
:
10771 case BFD_RELOC_386_TLS_IE_32
:
10772 case BFD_RELOC_386_TLS_IE
:
10773 case BFD_RELOC_386_TLS_GOTIE
:
10774 case BFD_RELOC_386_TLS_LE_32
:
10775 case BFD_RELOC_386_TLS_LE
:
10776 case BFD_RELOC_386_TLS_GOTDESC
:
10777 case BFD_RELOC_386_TLS_DESC_CALL
:
10778 case BFD_RELOC_X86_64_TLSGD
:
10779 case BFD_RELOC_X86_64_TLSLD
:
10780 case BFD_RELOC_X86_64_DTPOFF32
:
10781 case BFD_RELOC_X86_64_DTPOFF64
:
10782 case BFD_RELOC_X86_64_GOTTPOFF
:
10783 case BFD_RELOC_X86_64_TPOFF32
:
10784 case BFD_RELOC_X86_64_TPOFF64
:
10785 case BFD_RELOC_X86_64_GOTOFF64
:
10786 case BFD_RELOC_X86_64_GOTPC32
:
10787 case BFD_RELOC_X86_64_GOT64
:
10788 case BFD_RELOC_X86_64_GOTPCREL64
:
10789 case BFD_RELOC_X86_64_GOTPC64
:
10790 case BFD_RELOC_X86_64_GOTPLT64
:
10791 case BFD_RELOC_X86_64_PLTOFF64
:
10792 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10793 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10794 case BFD_RELOC_RVA
:
10795 case BFD_RELOC_VTABLE_ENTRY
:
10796 case BFD_RELOC_VTABLE_INHERIT
:
10798 case BFD_RELOC_32_SECREL
:
10800 code
= fixp
->fx_r_type
;
10802 case BFD_RELOC_X86_64_32S
:
10803 if (!fixp
->fx_pcrel
)
10805 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10806 code
= fixp
->fx_r_type
;
10809 /* Fall through. */
10811 if (fixp
->fx_pcrel
)
10813 switch (fixp
->fx_size
)
10816 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10817 _("can not do %d byte pc-relative relocation"),
10819 code
= BFD_RELOC_32_PCREL
;
10821 case 1: code
= BFD_RELOC_8_PCREL
; break;
10822 case 2: code
= BFD_RELOC_16_PCREL
; break;
10823 case 4: code
= BFD_RELOC_32_PCREL
; break;
10825 case 8: code
= BFD_RELOC_64_PCREL
; break;
10831 switch (fixp
->fx_size
)
10834 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10835 _("can not do %d byte relocation"),
10837 code
= BFD_RELOC_32
;
10839 case 1: code
= BFD_RELOC_8
; break;
10840 case 2: code
= BFD_RELOC_16
; break;
10841 case 4: code
= BFD_RELOC_32
; break;
10843 case 8: code
= BFD_RELOC_64
; break;
10850 if ((code
== BFD_RELOC_32
10851 || code
== BFD_RELOC_32_PCREL
10852 || code
== BFD_RELOC_X86_64_32S
)
10854 && fixp
->fx_addsy
== GOT_symbol
)
10857 code
= BFD_RELOC_386_GOTPC
;
10859 code
= BFD_RELOC_X86_64_GOTPC32
;
10861 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10863 && fixp
->fx_addsy
== GOT_symbol
)
10865 code
= BFD_RELOC_X86_64_GOTPC64
;
10868 rel
= XNEW (arelent
);
10869 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10870 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10872 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10874 if (!use_rela_relocations
)
10876 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10877 vtable entry to be used in the relocation's section offset. */
10878 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10879 rel
->address
= fixp
->fx_offset
;
10880 #if defined (OBJ_COFF) && defined (TE_PE)
10881 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10882 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10887 /* Use the rela in 64bit mode. */
10890 if (disallow_64bit_reloc
)
10893 case BFD_RELOC_X86_64_DTPOFF64
:
10894 case BFD_RELOC_X86_64_TPOFF64
:
10895 case BFD_RELOC_64_PCREL
:
10896 case BFD_RELOC_X86_64_GOTOFF64
:
10897 case BFD_RELOC_X86_64_GOT64
:
10898 case BFD_RELOC_X86_64_GOTPCREL64
:
10899 case BFD_RELOC_X86_64_GOTPC64
:
10900 case BFD_RELOC_X86_64_GOTPLT64
:
10901 case BFD_RELOC_X86_64_PLTOFF64
:
10902 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10903 _("cannot represent relocation type %s in x32 mode"),
10904 bfd_get_reloc_code_name (code
));
10910 if (!fixp
->fx_pcrel
)
10911 rel
->addend
= fixp
->fx_offset
;
10915 case BFD_RELOC_X86_64_PLT32
:
10916 case BFD_RELOC_X86_64_GOT32
:
10917 case BFD_RELOC_X86_64_GOTPCREL
:
10918 case BFD_RELOC_X86_64_GOTPCRELX
:
10919 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10920 case BFD_RELOC_X86_64_TLSGD
:
10921 case BFD_RELOC_X86_64_TLSLD
:
10922 case BFD_RELOC_X86_64_GOTTPOFF
:
10923 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10924 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10925 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10928 rel
->addend
= (section
->vma
10930 + fixp
->fx_addnumber
10931 + md_pcrel_from (fixp
));
10936 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10937 if (rel
->howto
== NULL
)
10939 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10940 _("cannot represent relocation type %s"),
10941 bfd_get_reloc_code_name (code
));
10942 /* Set howto to a garbage value so that we can keep going. */
10943 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10944 gas_assert (rel
->howto
!= NULL
);
10950 #include "tc-i386-intel.c"
10953 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10955 int saved_naked_reg
;
10956 char saved_register_dot
;
10958 saved_naked_reg
= allow_naked_reg
;
10959 allow_naked_reg
= 1;
10960 saved_register_dot
= register_chars
['.'];
10961 register_chars
['.'] = '.';
10962 allow_pseudo_reg
= 1;
10963 expression_and_evaluate (exp
);
10964 allow_pseudo_reg
= 0;
10965 register_chars
['.'] = saved_register_dot
;
10966 allow_naked_reg
= saved_naked_reg
;
10968 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10970 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10972 exp
->X_op
= O_constant
;
10973 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10974 .dw2_regnum
[flag_code
>> 1];
10977 exp
->X_op
= O_illegal
;
10982 tc_x86_frame_initial_instructions (void)
10984 static unsigned int sp_regno
[2];
10986 if (!sp_regno
[flag_code
>> 1])
10988 char *saved_input
= input_line_pointer
;
10989 char sp
[][4] = {"esp", "rsp"};
10992 input_line_pointer
= sp
[flag_code
>> 1];
10993 tc_x86_parse_to_dw2regnum (&exp
);
10994 gas_assert (exp
.X_op
== O_constant
);
10995 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10996 input_line_pointer
= saved_input
;
10999 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11000 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11004 x86_dwarf2_addr_size (void)
11006 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11007 if (x86_elf_abi
== X86_64_X32_ABI
)
11010 return bfd_arch_bits_per_address (stdoutput
) / 8;
11014 i386_elf_section_type (const char *str
, size_t len
)
11016 if (flag_code
== CODE_64BIT
11017 && len
== sizeof ("unwind") - 1
11018 && strncmp (str
, "unwind", 6) == 0)
11019 return SHT_X86_64_UNWIND
;
11026 i386_solaris_fix_up_eh_frame (segT sec
)
11028 if (flag_code
== CODE_64BIT
)
11029 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11035 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11039 exp
.X_op
= O_secrel
;
11040 exp
.X_add_symbol
= symbol
;
11041 exp
.X_add_number
= 0;
11042 emit_expr (&exp
, size
);
11046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11047 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11050 x86_64_section_letter (int letter
, const char **ptr_msg
)
11052 if (flag_code
== CODE_64BIT
)
11055 return SHF_X86_64_LARGE
;
11057 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11060 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11065 x86_64_section_word (char *str
, size_t len
)
11067 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11068 return SHF_X86_64_LARGE
;
11074 handle_large_common (int small ATTRIBUTE_UNUSED
)
11076 if (flag_code
!= CODE_64BIT
)
11078 s_comm_internal (0, elf_common_parse
);
11079 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11083 static segT lbss_section
;
11084 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11085 asection
*saved_bss_section
= bss_section
;
11087 if (lbss_section
== NULL
)
11089 flagword applicable
;
11090 segT seg
= now_seg
;
11091 subsegT subseg
= now_subseg
;
11093 /* The .lbss section is for local .largecomm symbols. */
11094 lbss_section
= subseg_new (".lbss", 0);
11095 applicable
= bfd_applicable_section_flags (stdoutput
);
11096 bfd_set_section_flags (stdoutput
, lbss_section
,
11097 applicable
& SEC_ALLOC
);
11098 seg_info (lbss_section
)->bss
= 1;
11100 subseg_set (seg
, subseg
);
11103 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11104 bss_section
= lbss_section
;
11106 s_comm_internal (0, elf_common_parse
);
11108 elf_com_section_ptr
= saved_com_section_ptr
;
11109 bss_section
= saved_bss_section
;
11112 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */