1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig
= rne
;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS
*GOT_symbol
;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column
;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment
;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table
[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch
[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
719 CPU_GENERIC32_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
721 CPU_GENERIC64_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
723 CPU_NONE_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
725 CPU_I186_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
727 CPU_I286_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
729 CPU_I386_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
731 CPU_I486_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
733 CPU_I586_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
735 CPU_I686_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
737 CPU_I586_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
739 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
741 CPU_P2_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
743 CPU_P3_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
745 CPU_P4_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
747 CPU_CORE_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
749 CPU_NOCONA_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
751 CPU_CORE_FLAGS
, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
755 CPU_CORE2_FLAGS
, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
757 CPU_CORE2_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
759 CPU_COREI7_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
761 CPU_L1OM_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
763 CPU_K1OM_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
765 CPU_K6_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
767 CPU_K6_2_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
769 CPU_ATHLON_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
771 CPU_K8_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
773 CPU_K8_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
775 CPU_K8_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
777 CPU_AMDFAM10_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
779 CPU_BDVER1_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
781 CPU_BDVER2_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
783 CPU_BDVER3_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
785 CPU_BDVER4_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
787 CPU_BTVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
789 CPU_BTVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
791 CPU_8087_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
793 CPU_287_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
795 CPU_387_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
797 CPU_ANY87_FLAGS
, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
799 CPU_MMX_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
801 CPU_3DNOWA_FLAGS
, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
803 CPU_SSE_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
805 CPU_SSE2_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
807 CPU_SSE3_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
809 CPU_SSSE3_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
811 CPU_SSE4_1_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE4_2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
815 CPU_SSE4_2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
817 CPU_ANY_SSE_FLAGS
, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
819 CPU_AVX_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
821 CPU_AVX2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
823 CPU_AVX512F_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
825 CPU_AVX512CD_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
827 CPU_AVX512ER_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
829 CPU_AVX512PF_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
831 CPU_AVX512DQ_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512BW_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512VL_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
837 CPU_ANY_AVX_FLAGS
, 0, 1 },
838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
839 CPU_VMX_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
841 CPU_VMFUNC_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
843 CPU_SMX_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
845 CPU_XSAVE_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
847 CPU_XSAVEOPT_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
849 CPU_XSAVEC_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
851 CPU_XSAVES_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
853 CPU_AES_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
855 CPU_PCLMUL_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
857 CPU_PCLMUL_FLAGS
, 1, 0 },
858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
859 CPU_FSGSBASE_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
861 CPU_RDRND_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
863 CPU_F16C_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
865 CPU_BMI2_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
867 CPU_FMA_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
869 CPU_FMA4_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
871 CPU_XOP_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
873 CPU_LWP_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
875 CPU_MOVBE_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
877 CPU_CX16_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
879 CPU_EPT_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
881 CPU_LZCNT_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
883 CPU_HLE_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
885 CPU_RTM_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
887 CPU_INVPCID_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
889 CPU_CLFLUSH_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
891 CPU_NOP_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
893 CPU_SYSCALL_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
895 CPU_RDTSCP_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
897 CPU_3DNOW_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
899 CPU_3DNOWA_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
901 CPU_PADLOCK_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
903 CPU_SVME_FLAGS
, 1, 0 },
904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
905 CPU_SVME_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
907 CPU_SSE4A_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
909 CPU_ABM_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
911 CPU_BMI_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
913 CPU_TBM_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
915 CPU_ADX_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
917 CPU_RDSEED_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
919 CPU_PRFCHW_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
921 CPU_SMAP_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
923 CPU_MPX_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
925 CPU_SHA_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
927 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
929 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
931 CPU_SE1_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
933 CPU_CLWB_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
935 CPU_PCOMMIT_FLAGS
, 0, 0 },
939 /* Like s_lcomm_internal in gas/read.c but the alignment string
940 is allowed to be optional. */
943 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
950 && *input_line_pointer
== ',')
952 align
= parse_align (needs_align
- 1);
954 if (align
== (addressT
) -1)
969 bss_alloc (symbolP
, size
, align
);
974 pe_lcomm (int needs_align
)
976 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
980 const pseudo_typeS md_pseudo_table
[] =
982 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
983 {"align", s_align_bytes
, 0},
985 {"align", s_align_ptwo
, 0},
987 {"arch", set_cpu_arch
, 0},
991 {"lcomm", pe_lcomm
, 1},
993 {"ffloat", float_cons
, 'f'},
994 {"dfloat", float_cons
, 'd'},
995 {"tfloat", float_cons
, 'x'},
997 {"slong", signed_cons
, 4},
998 {"noopt", s_ignore
, 0},
999 {"optim", s_ignore
, 0},
1000 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1001 {"code16", set_code_flag
, CODE_16BIT
},
1002 {"code32", set_code_flag
, CODE_32BIT
},
1003 {"code64", set_code_flag
, CODE_64BIT
},
1004 {"intel_syntax", set_intel_syntax
, 1},
1005 {"att_syntax", set_intel_syntax
, 0},
1006 {"intel_mnemonic", set_intel_mnemonic
, 1},
1007 {"att_mnemonic", set_intel_mnemonic
, 0},
1008 {"allow_index_reg", set_allow_index_reg
, 1},
1009 {"disallow_index_reg", set_allow_index_reg
, 0},
1010 {"sse_check", set_check
, 0},
1011 {"operand_check", set_check
, 1},
1012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1013 {"largecomm", handle_large_common
, 0},
1015 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1016 {"loc", dwarf2_directive_loc
, 0},
1017 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1020 {"secrel32", pe_directive_secrel
, 0},
1025 /* For interface with expression (). */
1026 extern char *input_line_pointer
;
1028 /* Hash table for instruction mnemonic lookup. */
1029 static struct hash_control
*op_hash
;
1031 /* Hash table for register lookup. */
1032 static struct hash_control
*reg_hash
;
1035 i386_align_code (fragS
*fragP
, int count
)
1037 /* Various efficient no-op patterns for aligning code labels.
1038 Note: Don't try to assemble the instructions in the comments.
1039 0L and 0w are not legal. */
1040 static const char f32_1
[] =
1042 static const char f32_2
[] =
1043 {0x66,0x90}; /* xchg %ax,%ax */
1044 static const char f32_3
[] =
1045 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1046 static const char f32_4
[] =
1047 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1048 static const char f32_5
[] =
1050 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1051 static const char f32_6
[] =
1052 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1053 static const char f32_7
[] =
1054 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1055 static const char f32_8
[] =
1057 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1058 static const char f32_9
[] =
1059 {0x89,0xf6, /* movl %esi,%esi */
1060 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1061 static const char f32_10
[] =
1062 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1063 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1064 static const char f32_11
[] =
1065 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1066 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1067 static const char f32_12
[] =
1068 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1069 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1070 static const char f32_13
[] =
1071 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1072 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1073 static const char f32_14
[] =
1074 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1075 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1076 static const char f16_3
[] =
1077 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1078 static const char f16_4
[] =
1079 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1080 static const char f16_5
[] =
1082 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1083 static const char f16_6
[] =
1084 {0x89,0xf6, /* mov %si,%si */
1085 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1086 static const char f16_7
[] =
1087 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1088 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1089 static const char f16_8
[] =
1090 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1091 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1092 static const char jump_31
[] =
1093 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1094 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1095 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1096 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1097 static const char *const f32_patt
[] = {
1098 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1099 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1101 static const char *const f16_patt
[] = {
1102 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1104 /* nopl (%[re]ax) */
1105 static const char alt_3
[] =
1107 /* nopl 0(%[re]ax) */
1108 static const char alt_4
[] =
1109 {0x0f,0x1f,0x40,0x00};
1110 /* nopl 0(%[re]ax,%[re]ax,1) */
1111 static const char alt_5
[] =
1112 {0x0f,0x1f,0x44,0x00,0x00};
1113 /* nopw 0(%[re]ax,%[re]ax,1) */
1114 static const char alt_6
[] =
1115 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1116 /* nopl 0L(%[re]ax) */
1117 static const char alt_7
[] =
1118 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1119 /* nopl 0L(%[re]ax,%[re]ax,1) */
1120 static const char alt_8
[] =
1121 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1122 /* nopw 0L(%[re]ax,%[re]ax,1) */
1123 static const char alt_9
[] =
1124 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1125 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1126 static const char alt_10
[] =
1127 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_long_11
[] =
1132 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1135 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1136 static const char alt_long_12
[] =
1139 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1143 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1144 static const char alt_long_13
[] =
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1154 static const char alt_long_14
[] =
1159 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1165 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_long_15
[] =
1172 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1173 /* nopl 0(%[re]ax,%[re]ax,1)
1174 nopw 0(%[re]ax,%[re]ax,1) */
1175 static const char alt_short_11
[] =
1176 {0x0f,0x1f,0x44,0x00,0x00,
1177 0x66,0x0f,0x1f,0x44,0x00,0x00};
1178 /* nopw 0(%[re]ax,%[re]ax,1)
1179 nopw 0(%[re]ax,%[re]ax,1) */
1180 static const char alt_short_12
[] =
1181 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1182 0x66,0x0f,0x1f,0x44,0x00,0x00};
1183 /* nopw 0(%[re]ax,%[re]ax,1)
1185 static const char alt_short_13
[] =
1186 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1187 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1190 static const char alt_short_14
[] =
1191 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1192 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1194 nopl 0L(%[re]ax,%[re]ax,1) */
1195 static const char alt_short_15
[] =
1196 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1197 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1198 static const char *const alt_short_patt
[] = {
1199 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1200 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1201 alt_short_14
, alt_short_15
1203 static const char *const alt_long_patt
[] = {
1204 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1205 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1206 alt_long_14
, alt_long_15
1209 /* Only align for at least a positive non-zero boundary. */
1210 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1213 /* We need to decide which NOP sequence to use for 32bit and
1214 64bit. When -mtune= is used:
1216 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1217 PROCESSOR_GENERIC32, f32_patt will be used.
1218 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1219 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1220 PROCESSOR_GENERIC64, alt_long_patt will be used.
1221 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1222 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1225 When -mtune= isn't used, alt_long_patt will be used if
1226 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1229 When -march= or .arch is used, we can't use anything beyond
1230 cpu_arch_isa_flags. */
1232 if (flag_code
== CODE_16BIT
)
1236 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1238 /* Adjust jump offset. */
1239 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1242 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1243 f16_patt
[count
- 1], count
);
1247 const char *const *patt
= NULL
;
1249 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1251 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1252 switch (cpu_arch_tune
)
1254 case PROCESSOR_UNKNOWN
:
1255 /* We use cpu_arch_isa_flags to check if we SHOULD
1256 optimize with nops. */
1257 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1258 patt
= alt_long_patt
;
1262 case PROCESSOR_PENTIUM4
:
1263 case PROCESSOR_NOCONA
:
1264 case PROCESSOR_CORE
:
1265 case PROCESSOR_CORE2
:
1266 case PROCESSOR_COREI7
:
1267 case PROCESSOR_L1OM
:
1268 case PROCESSOR_K1OM
:
1269 case PROCESSOR_GENERIC64
:
1270 patt
= alt_long_patt
;
1273 case PROCESSOR_ATHLON
:
1275 case PROCESSOR_AMDFAM10
:
1278 patt
= alt_short_patt
;
1280 case PROCESSOR_I386
:
1281 case PROCESSOR_I486
:
1282 case PROCESSOR_PENTIUM
:
1283 case PROCESSOR_PENTIUMPRO
:
1284 case PROCESSOR_GENERIC32
:
1291 switch (fragP
->tc_frag_data
.tune
)
1293 case PROCESSOR_UNKNOWN
:
1294 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1295 PROCESSOR_UNKNOWN. */
1299 case PROCESSOR_I386
:
1300 case PROCESSOR_I486
:
1301 case PROCESSOR_PENTIUM
:
1303 case PROCESSOR_ATHLON
:
1305 case PROCESSOR_AMDFAM10
:
1308 case PROCESSOR_GENERIC32
:
1309 /* We use cpu_arch_isa_flags to check if we CAN optimize
1311 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1312 patt
= alt_short_patt
;
1316 case PROCESSOR_PENTIUMPRO
:
1317 case PROCESSOR_PENTIUM4
:
1318 case PROCESSOR_NOCONA
:
1319 case PROCESSOR_CORE
:
1320 case PROCESSOR_CORE2
:
1321 case PROCESSOR_COREI7
:
1322 case PROCESSOR_L1OM
:
1323 case PROCESSOR_K1OM
:
1324 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1325 patt
= alt_long_patt
;
1329 case PROCESSOR_GENERIC64
:
1330 patt
= alt_long_patt
;
1335 if (patt
== f32_patt
)
1337 /* If the padding is less than 15 bytes, we use the normal
1338 ones. Otherwise, we use a jump instruction and adjust
1342 /* For 64bit, the limit is 3 bytes. */
1343 if (flag_code
== CODE_64BIT
1344 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1349 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1350 patt
[count
- 1], count
);
1353 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1355 /* Adjust jump offset. */
1356 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1361 /* Maximum length of an instruction is 15 byte. If the
1362 padding is greater than 15 bytes and we don't use jump,
1363 we have to break it into smaller pieces. */
1364 int padding
= count
;
1365 while (padding
> 15)
1368 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1373 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1374 patt
[padding
- 1], padding
);
1377 fragP
->fr_var
= count
;
1381 operand_type_all_zero (const union i386_operand_type
*x
)
1383 switch (ARRAY_SIZE(x
->array
))
1392 return !x
->array
[0];
1399 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1401 switch (ARRAY_SIZE(x
->array
))
1416 operand_type_equal (const union i386_operand_type
*x
,
1417 const union i386_operand_type
*y
)
1419 switch (ARRAY_SIZE(x
->array
))
1422 if (x
->array
[2] != y
->array
[2])
1425 if (x
->array
[1] != y
->array
[1])
1428 return x
->array
[0] == y
->array
[0];
1436 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1438 switch (ARRAY_SIZE(x
->array
))
1447 return !x
->array
[0];
1454 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1456 switch (ARRAY_SIZE(x
->array
))
1471 cpu_flags_equal (const union i386_cpu_flags
*x
,
1472 const union i386_cpu_flags
*y
)
1474 switch (ARRAY_SIZE(x
->array
))
1477 if (x
->array
[2] != y
->array
[2])
1480 if (x
->array
[1] != y
->array
[1])
1483 return x
->array
[0] == y
->array
[0];
1491 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1493 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1494 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1497 static INLINE i386_cpu_flags
1498 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1500 switch (ARRAY_SIZE (x
.array
))
1503 x
.array
[2] &= y
.array
[2];
1505 x
.array
[1] &= y
.array
[1];
1507 x
.array
[0] &= y
.array
[0];
1515 static INLINE i386_cpu_flags
1516 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1518 switch (ARRAY_SIZE (x
.array
))
1521 x
.array
[2] |= y
.array
[2];
1523 x
.array
[1] |= y
.array
[1];
1525 x
.array
[0] |= y
.array
[0];
1533 static INLINE i386_cpu_flags
1534 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1536 switch (ARRAY_SIZE (x
.array
))
1539 x
.array
[2] &= ~y
.array
[2];
1541 x
.array
[1] &= ~y
.array
[1];
1543 x
.array
[0] &= ~y
.array
[0];
1551 #define CPU_FLAGS_ARCH_MATCH 0x1
1552 #define CPU_FLAGS_64BIT_MATCH 0x2
1553 #define CPU_FLAGS_AES_MATCH 0x4
1554 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1555 #define CPU_FLAGS_AVX_MATCH 0x10
1557 #define CPU_FLAGS_32BIT_MATCH \
1558 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1559 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1560 #define CPU_FLAGS_PERFECT_MATCH \
1561 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1563 /* Return CPU flags match bits. */
1566 cpu_flags_match (const insn_template
*t
)
1568 i386_cpu_flags x
= t
->cpu_flags
;
1569 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1571 x
.bitfield
.cpu64
= 0;
1572 x
.bitfield
.cpuno64
= 0;
1574 if (cpu_flags_all_zero (&x
))
1576 /* This instruction is available on all archs. */
1577 match
|= CPU_FLAGS_32BIT_MATCH
;
1581 /* This instruction is available only on some archs. */
1582 i386_cpu_flags cpu
= cpu_arch_flags
;
1584 cpu
.bitfield
.cpu64
= 0;
1585 cpu
.bitfield
.cpuno64
= 0;
1586 cpu
= cpu_flags_and (x
, cpu
);
1587 if (!cpu_flags_all_zero (&cpu
))
1589 if (x
.bitfield
.cpuavx
)
1591 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1592 if (cpu
.bitfield
.cpuavx
)
1594 /* Check SSE2AVX. */
1595 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1597 match
|= (CPU_FLAGS_ARCH_MATCH
1598 | CPU_FLAGS_AVX_MATCH
);
1600 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1601 match
|= CPU_FLAGS_AES_MATCH
;
1603 if (!x
.bitfield
.cpupclmul
1604 || cpu
.bitfield
.cpupclmul
)
1605 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1609 match
|= CPU_FLAGS_ARCH_MATCH
;
1612 match
|= CPU_FLAGS_32BIT_MATCH
;
1618 static INLINE i386_operand_type
1619 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1621 switch (ARRAY_SIZE (x
.array
))
1624 x
.array
[2] &= y
.array
[2];
1626 x
.array
[1] &= y
.array
[1];
1628 x
.array
[0] &= y
.array
[0];
1636 static INLINE i386_operand_type
1637 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1639 switch (ARRAY_SIZE (x
.array
))
1642 x
.array
[2] |= y
.array
[2];
1644 x
.array
[1] |= y
.array
[1];
1646 x
.array
[0] |= y
.array
[0];
1654 static INLINE i386_operand_type
1655 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1657 switch (ARRAY_SIZE (x
.array
))
1660 x
.array
[2] ^= y
.array
[2];
1662 x
.array
[1] ^= y
.array
[1];
1664 x
.array
[0] ^= y
.array
[0];
1672 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1673 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1674 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1675 static const i386_operand_type inoutportreg
1676 = OPERAND_TYPE_INOUTPORTREG
;
1677 static const i386_operand_type reg16_inoutportreg
1678 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1679 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1680 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1681 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1682 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1683 static const i386_operand_type anydisp
1684 = OPERAND_TYPE_ANYDISP
;
1685 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1686 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1687 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1688 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1689 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1690 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1691 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1692 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1693 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1694 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1695 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1696 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1697 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1698 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1709 operand_type_check (i386_operand_type t
, enum operand_type c
)
1714 return (t
.bitfield
.reg8
1717 || t
.bitfield
.reg64
);
1720 return (t
.bitfield
.imm8
1724 || t
.bitfield
.imm32s
1725 || t
.bitfield
.imm64
);
1728 return (t
.bitfield
.disp8
1729 || t
.bitfield
.disp16
1730 || t
.bitfield
.disp32
1731 || t
.bitfield
.disp32s
1732 || t
.bitfield
.disp64
);
1735 return (t
.bitfield
.disp8
1736 || t
.bitfield
.disp16
1737 || t
.bitfield
.disp32
1738 || t
.bitfield
.disp32s
1739 || t
.bitfield
.disp64
1740 || t
.bitfield
.baseindex
);
1749 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1750 operand J for instruction template T. */
1753 match_reg_size (const insn_template
*t
, unsigned int j
)
1755 return !((i
.types
[j
].bitfield
.byte
1756 && !t
->operand_types
[j
].bitfield
.byte
)
1757 || (i
.types
[j
].bitfield
.word
1758 && !t
->operand_types
[j
].bitfield
.word
)
1759 || (i
.types
[j
].bitfield
.dword
1760 && !t
->operand_types
[j
].bitfield
.dword
)
1761 || (i
.types
[j
].bitfield
.qword
1762 && !t
->operand_types
[j
].bitfield
.qword
));
1765 /* Return 1 if there is no conflict in any size on operand J for
1766 instruction template T. */
1769 match_mem_size (const insn_template
*t
, unsigned int j
)
1771 return (match_reg_size (t
, j
)
1772 && !((i
.types
[j
].bitfield
.unspecified
1773 && !t
->operand_types
[j
].bitfield
.unspecified
)
1774 || (i
.types
[j
].bitfield
.fword
1775 && !t
->operand_types
[j
].bitfield
.fword
)
1776 || (i
.types
[j
].bitfield
.tbyte
1777 && !t
->operand_types
[j
].bitfield
.tbyte
)
1778 || (i
.types
[j
].bitfield
.xmmword
1779 && !t
->operand_types
[j
].bitfield
.xmmword
)
1780 || (i
.types
[j
].bitfield
.ymmword
1781 && !t
->operand_types
[j
].bitfield
.ymmword
)
1782 || (i
.types
[j
].bitfield
.zmmword
1783 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1786 /* Return 1 if there is no size conflict on any operands for
1787 instruction template T. */
1790 operand_size_match (const insn_template
*t
)
1795 /* Don't check jump instructions. */
1796 if (t
->opcode_modifier
.jump
1797 || t
->opcode_modifier
.jumpbyte
1798 || t
->opcode_modifier
.jumpdword
1799 || t
->opcode_modifier
.jumpintersegment
)
1802 /* Check memory and accumulator operand size. */
1803 for (j
= 0; j
< i
.operands
; j
++)
1805 if (t
->operand_types
[j
].bitfield
.anysize
)
1808 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1814 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1823 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1826 i
.error
= operand_size_mismatch
;
1830 /* Check reverse. */
1831 gas_assert (i
.operands
== 2);
1834 for (j
= 0; j
< 2; j
++)
1836 if (t
->operand_types
[j
].bitfield
.acc
1837 && !match_reg_size (t
, j
? 0 : 1))
1840 if (i
.types
[j
].bitfield
.mem
1841 && !match_mem_size (t
, j
? 0 : 1))
1849 operand_type_match (i386_operand_type overlap
,
1850 i386_operand_type given
)
1852 i386_operand_type temp
= overlap
;
1854 temp
.bitfield
.jumpabsolute
= 0;
1855 temp
.bitfield
.unspecified
= 0;
1856 temp
.bitfield
.byte
= 0;
1857 temp
.bitfield
.word
= 0;
1858 temp
.bitfield
.dword
= 0;
1859 temp
.bitfield
.fword
= 0;
1860 temp
.bitfield
.qword
= 0;
1861 temp
.bitfield
.tbyte
= 0;
1862 temp
.bitfield
.xmmword
= 0;
1863 temp
.bitfield
.ymmword
= 0;
1864 temp
.bitfield
.zmmword
= 0;
1865 if (operand_type_all_zero (&temp
))
1868 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1869 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1873 i
.error
= operand_type_mismatch
;
1877 /* If given types g0 and g1 are registers they must be of the same type
1878 unless the expected operand type register overlap is null.
1879 Note that Acc in a template matches every size of reg. */
1882 operand_type_register_match (i386_operand_type m0
,
1883 i386_operand_type g0
,
1884 i386_operand_type t0
,
1885 i386_operand_type m1
,
1886 i386_operand_type g1
,
1887 i386_operand_type t1
)
1889 if (!operand_type_check (g0
, reg
))
1892 if (!operand_type_check (g1
, reg
))
1895 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1896 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1897 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1898 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1901 if (m0
.bitfield
.acc
)
1903 t0
.bitfield
.reg8
= 1;
1904 t0
.bitfield
.reg16
= 1;
1905 t0
.bitfield
.reg32
= 1;
1906 t0
.bitfield
.reg64
= 1;
1909 if (m1
.bitfield
.acc
)
1911 t1
.bitfield
.reg8
= 1;
1912 t1
.bitfield
.reg16
= 1;
1913 t1
.bitfield
.reg32
= 1;
1914 t1
.bitfield
.reg64
= 1;
1917 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1918 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1919 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1920 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1923 i
.error
= register_type_mismatch
;
1928 static INLINE
unsigned int
1929 register_number (const reg_entry
*r
)
1931 unsigned int nr
= r
->reg_num
;
1933 if (r
->reg_flags
& RegRex
)
1939 static INLINE
unsigned int
1940 mode_from_disp_size (i386_operand_type t
)
1942 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1944 else if (t
.bitfield
.disp16
1945 || t
.bitfield
.disp32
1946 || t
.bitfield
.disp32s
)
1953 fits_in_signed_byte (addressT num
)
1955 return num
+ 0x80 <= 0xff;
1959 fits_in_unsigned_byte (addressT num
)
1965 fits_in_unsigned_word (addressT num
)
1967 return num
<= 0xffff;
1971 fits_in_signed_word (addressT num
)
1973 return num
+ 0x8000 <= 0xffff;
1977 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1982 return num
+ 0x80000000 <= 0xffffffff;
1984 } /* fits_in_signed_long() */
1987 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1992 return num
<= 0xffffffff;
1994 } /* fits_in_unsigned_long() */
1997 fits_in_vec_disp8 (offsetT num
)
1999 int shift
= i
.memshift
;
2005 mask
= (1 << shift
) - 1;
2007 /* Return 0 if NUM isn't properly aligned. */
2011 /* Check if NUM will fit in 8bit after shift. */
2012 return fits_in_signed_byte (num
>> shift
);
2016 fits_in_imm4 (offsetT num
)
2018 return (num
& 0xf) == num
;
2021 static i386_operand_type
2022 smallest_imm_type (offsetT num
)
2024 i386_operand_type t
;
2026 operand_type_set (&t
, 0);
2027 t
.bitfield
.imm64
= 1;
2029 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2031 /* This code is disabled on the 486 because all the Imm1 forms
2032 in the opcode table are slower on the i486. They're the
2033 versions with the implicitly specified single-position
2034 displacement, which has another syntax if you really want to
2036 t
.bitfield
.imm1
= 1;
2037 t
.bitfield
.imm8
= 1;
2038 t
.bitfield
.imm8s
= 1;
2039 t
.bitfield
.imm16
= 1;
2040 t
.bitfield
.imm32
= 1;
2041 t
.bitfield
.imm32s
= 1;
2043 else if (fits_in_signed_byte (num
))
2045 t
.bitfield
.imm8
= 1;
2046 t
.bitfield
.imm8s
= 1;
2047 t
.bitfield
.imm16
= 1;
2048 t
.bitfield
.imm32
= 1;
2049 t
.bitfield
.imm32s
= 1;
2051 else if (fits_in_unsigned_byte (num
))
2053 t
.bitfield
.imm8
= 1;
2054 t
.bitfield
.imm16
= 1;
2055 t
.bitfield
.imm32
= 1;
2056 t
.bitfield
.imm32s
= 1;
2058 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2060 t
.bitfield
.imm16
= 1;
2061 t
.bitfield
.imm32
= 1;
2062 t
.bitfield
.imm32s
= 1;
2064 else if (fits_in_signed_long (num
))
2066 t
.bitfield
.imm32
= 1;
2067 t
.bitfield
.imm32s
= 1;
2069 else if (fits_in_unsigned_long (num
))
2070 t
.bitfield
.imm32
= 1;
2076 offset_in_range (offsetT val
, int size
)
2082 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2083 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2084 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2086 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2092 /* If BFD64, sign extend val for 32bit address mode. */
2093 if (flag_code
!= CODE_64BIT
2094 || i
.prefix
[ADDR_PREFIX
])
2095 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2096 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2099 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2101 char buf1
[40], buf2
[40];
2103 sprint_value (buf1
, val
);
2104 sprint_value (buf2
, val
& mask
);
2105 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2119 a. PREFIX_EXIST if attempting to add a prefix where one from the
2120 same class already exists.
2121 b. PREFIX_LOCK if lock prefix is added.
2122 c. PREFIX_REP if rep/repne prefix is added.
2123 d. PREFIX_OTHER if other prefix is added.
2126 static enum PREFIX_GROUP
2127 add_prefix (unsigned int prefix
)
2129 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2132 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2133 && flag_code
== CODE_64BIT
)
2135 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2136 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2137 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2148 case CS_PREFIX_OPCODE
:
2149 case DS_PREFIX_OPCODE
:
2150 case ES_PREFIX_OPCODE
:
2151 case FS_PREFIX_OPCODE
:
2152 case GS_PREFIX_OPCODE
:
2153 case SS_PREFIX_OPCODE
:
2157 case REPNE_PREFIX_OPCODE
:
2158 case REPE_PREFIX_OPCODE
:
2163 case LOCK_PREFIX_OPCODE
:
2172 case ADDR_PREFIX_OPCODE
:
2176 case DATA_PREFIX_OPCODE
:
2180 if (i
.prefix
[q
] != 0)
2188 i
.prefix
[q
] |= prefix
;
2191 as_bad (_("same type of prefix used twice"));
2197 update_code_flag (int value
, int check
)
2199 PRINTF_LIKE ((*as_error
));
2201 flag_code
= (enum flag_code
) value
;
2202 if (flag_code
== CODE_64BIT
)
2204 cpu_arch_flags
.bitfield
.cpu64
= 1;
2205 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2209 cpu_arch_flags
.bitfield
.cpu64
= 0;
2210 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2212 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2215 as_error
= as_fatal
;
2218 (*as_error
) (_("64bit mode not supported on `%s'."),
2219 cpu_arch_name
? cpu_arch_name
: default_arch
);
2221 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2224 as_error
= as_fatal
;
2227 (*as_error
) (_("32bit mode not supported on `%s'."),
2228 cpu_arch_name
? cpu_arch_name
: default_arch
);
2230 stackop_size
= '\0';
2234 set_code_flag (int value
)
2236 update_code_flag (value
, 0);
2240 set_16bit_gcc_code_flag (int new_code_flag
)
2242 flag_code
= (enum flag_code
) new_code_flag
;
2243 if (flag_code
!= CODE_16BIT
)
2245 cpu_arch_flags
.bitfield
.cpu64
= 0;
2246 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2247 stackop_size
= LONG_MNEM_SUFFIX
;
2251 set_intel_syntax (int syntax_flag
)
2253 /* Find out if register prefixing is specified. */
2254 int ask_naked_reg
= 0;
2257 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2259 char *string
= input_line_pointer
;
2260 int e
= get_symbol_end ();
2262 if (strcmp (string
, "prefix") == 0)
2264 else if (strcmp (string
, "noprefix") == 0)
2267 as_bad (_("bad argument to syntax directive."));
2268 *input_line_pointer
= e
;
2270 demand_empty_rest_of_line ();
2272 intel_syntax
= syntax_flag
;
2274 if (ask_naked_reg
== 0)
2275 allow_naked_reg
= (intel_syntax
2276 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2278 allow_naked_reg
= (ask_naked_reg
< 0);
2280 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2282 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2283 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2284 register_prefix
= allow_naked_reg
? "" : "%";
2288 set_intel_mnemonic (int mnemonic_flag
)
2290 intel_mnemonic
= mnemonic_flag
;
2294 set_allow_index_reg (int flag
)
2296 allow_index_reg
= flag
;
2300 set_check (int what
)
2302 enum check_kind
*kind
;
2307 kind
= &operand_check
;
2318 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2320 char *string
= input_line_pointer
;
2321 int e
= get_symbol_end ();
2323 if (strcmp (string
, "none") == 0)
2325 else if (strcmp (string
, "warning") == 0)
2326 *kind
= check_warning
;
2327 else if (strcmp (string
, "error") == 0)
2328 *kind
= check_error
;
2330 as_bad (_("bad argument to %s_check directive."), str
);
2331 *input_line_pointer
= e
;
2334 as_bad (_("missing argument for %s_check directive"), str
);
2336 demand_empty_rest_of_line ();
2340 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2341 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2343 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2344 static const char *arch
;
2346 /* Intel LIOM is only supported on ELF. */
2352 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2353 use default_arch. */
2354 arch
= cpu_arch_name
;
2356 arch
= default_arch
;
2359 /* If we are targeting Intel L1OM, we must enable it. */
2360 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2361 || new_flag
.bitfield
.cpul1om
)
2364 /* If we are targeting Intel K1OM, we must enable it. */
2365 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2366 || new_flag
.bitfield
.cpuk1om
)
2369 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2374 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2378 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2380 char *string
= input_line_pointer
;
2381 int e
= get_symbol_end ();
2383 i386_cpu_flags flags
;
2385 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2387 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2389 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2393 cpu_arch_name
= cpu_arch
[j
].name
;
2394 cpu_sub_arch_name
= NULL
;
2395 cpu_arch_flags
= cpu_arch
[j
].flags
;
2396 if (flag_code
== CODE_64BIT
)
2398 cpu_arch_flags
.bitfield
.cpu64
= 1;
2399 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2403 cpu_arch_flags
.bitfield
.cpu64
= 0;
2404 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2406 cpu_arch_isa
= cpu_arch
[j
].type
;
2407 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2408 if (!cpu_arch_tune_set
)
2410 cpu_arch_tune
= cpu_arch_isa
;
2411 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2416 if (!cpu_arch
[j
].negated
)
2417 flags
= cpu_flags_or (cpu_arch_flags
,
2420 flags
= cpu_flags_and_not (cpu_arch_flags
,
2422 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2424 if (cpu_sub_arch_name
)
2426 char *name
= cpu_sub_arch_name
;
2427 cpu_sub_arch_name
= concat (name
,
2429 (const char *) NULL
);
2433 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2434 cpu_arch_flags
= flags
;
2435 cpu_arch_isa_flags
= flags
;
2437 *input_line_pointer
= e
;
2438 demand_empty_rest_of_line ();
2442 if (j
>= ARRAY_SIZE (cpu_arch
))
2443 as_bad (_("no such architecture: `%s'"), string
);
2445 *input_line_pointer
= e
;
2448 as_bad (_("missing cpu architecture"));
2450 no_cond_jump_promotion
= 0;
2451 if (*input_line_pointer
== ','
2452 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2454 char *string
= ++input_line_pointer
;
2455 int e
= get_symbol_end ();
2457 if (strcmp (string
, "nojumps") == 0)
2458 no_cond_jump_promotion
= 1;
2459 else if (strcmp (string
, "jumps") == 0)
2462 as_bad (_("no such architecture modifier: `%s'"), string
);
2464 *input_line_pointer
= e
;
2467 demand_empty_rest_of_line ();
2470 enum bfd_architecture
2473 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2475 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2476 || flag_code
!= CODE_64BIT
)
2477 as_fatal (_("Intel L1OM is 64bit ELF only"));
2478 return bfd_arch_l1om
;
2480 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2482 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2483 || flag_code
!= CODE_64BIT
)
2484 as_fatal (_("Intel K1OM is 64bit ELF only"));
2485 return bfd_arch_k1om
;
2488 return bfd_arch_i386
;
2494 if (!strncmp (default_arch
, "x86_64", 6))
2496 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2498 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2499 || default_arch
[6] != '\0')
2500 as_fatal (_("Intel L1OM is 64bit ELF only"));
2501 return bfd_mach_l1om
;
2503 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2505 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2506 || default_arch
[6] != '\0')
2507 as_fatal (_("Intel K1OM is 64bit ELF only"));
2508 return bfd_mach_k1om
;
2510 else if (default_arch
[6] == '\0')
2511 return bfd_mach_x86_64
;
2513 return bfd_mach_x64_32
;
2515 else if (!strcmp (default_arch
, "i386"))
2516 return bfd_mach_i386_i386
;
2518 as_fatal (_("unknown architecture"));
2524 const char *hash_err
;
2526 /* Initialize op_hash hash table. */
2527 op_hash
= hash_new ();
2530 const insn_template
*optab
;
2531 templates
*core_optab
;
2533 /* Setup for loop. */
2535 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2536 core_optab
->start
= optab
;
2541 if (optab
->name
== NULL
2542 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2544 /* different name --> ship out current template list;
2545 add to hash table; & begin anew. */
2546 core_optab
->end
= optab
;
2547 hash_err
= hash_insert (op_hash
,
2549 (void *) core_optab
);
2552 as_fatal (_("can't hash %s: %s"),
2556 if (optab
->name
== NULL
)
2558 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2559 core_optab
->start
= optab
;
2564 /* Initialize reg_hash hash table. */
2565 reg_hash
= hash_new ();
2567 const reg_entry
*regtab
;
2568 unsigned int regtab_size
= i386_regtab_size
;
2570 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2572 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2574 as_fatal (_("can't hash %s: %s"),
2580 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2585 for (c
= 0; c
< 256; c
++)
2590 mnemonic_chars
[c
] = c
;
2591 register_chars
[c
] = c
;
2592 operand_chars
[c
] = c
;
2594 else if (ISLOWER (c
))
2596 mnemonic_chars
[c
] = c
;
2597 register_chars
[c
] = c
;
2598 operand_chars
[c
] = c
;
2600 else if (ISUPPER (c
))
2602 mnemonic_chars
[c
] = TOLOWER (c
);
2603 register_chars
[c
] = mnemonic_chars
[c
];
2604 operand_chars
[c
] = c
;
2606 else if (c
== '{' || c
== '}')
2607 operand_chars
[c
] = c
;
2609 if (ISALPHA (c
) || ISDIGIT (c
))
2610 identifier_chars
[c
] = c
;
2613 identifier_chars
[c
] = c
;
2614 operand_chars
[c
] = c
;
2619 identifier_chars
['@'] = '@';
2622 identifier_chars
['?'] = '?';
2623 operand_chars
['?'] = '?';
2625 digit_chars
['-'] = '-';
2626 mnemonic_chars
['_'] = '_';
2627 mnemonic_chars
['-'] = '-';
2628 mnemonic_chars
['.'] = '.';
2629 identifier_chars
['_'] = '_';
2630 identifier_chars
['.'] = '.';
2632 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2633 operand_chars
[(unsigned char) *p
] = *p
;
2636 if (flag_code
== CODE_64BIT
)
2638 #if defined (OBJ_COFF) && defined (TE_PE)
2639 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2642 x86_dwarf2_return_column
= 16;
2644 x86_cie_data_alignment
= -8;
2648 x86_dwarf2_return_column
= 8;
2649 x86_cie_data_alignment
= -4;
2654 i386_print_statistics (FILE *file
)
2656 hash_print_statistics (file
, "i386 opcode", op_hash
);
2657 hash_print_statistics (file
, "i386 register", reg_hash
);
2662 /* Debugging routines for md_assemble. */
2663 static void pte (insn_template
*);
2664 static void pt (i386_operand_type
);
2665 static void pe (expressionS
*);
2666 static void ps (symbolS
*);
2669 pi (char *line
, i386_insn
*x
)
2673 fprintf (stdout
, "%s: template ", line
);
2675 fprintf (stdout
, " address: base %s index %s scale %x\n",
2676 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2677 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2678 x
->log2_scale_factor
);
2679 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2680 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2681 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2682 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2683 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2684 (x
->rex
& REX_W
) != 0,
2685 (x
->rex
& REX_R
) != 0,
2686 (x
->rex
& REX_X
) != 0,
2687 (x
->rex
& REX_B
) != 0);
2688 for (j
= 0; j
< x
->operands
; j
++)
2690 fprintf (stdout
, " #%d: ", j
+ 1);
2692 fprintf (stdout
, "\n");
2693 if (x
->types
[j
].bitfield
.reg8
2694 || x
->types
[j
].bitfield
.reg16
2695 || x
->types
[j
].bitfield
.reg32
2696 || x
->types
[j
].bitfield
.reg64
2697 || x
->types
[j
].bitfield
.regmmx
2698 || x
->types
[j
].bitfield
.regxmm
2699 || x
->types
[j
].bitfield
.regymm
2700 || x
->types
[j
].bitfield
.regzmm
2701 || x
->types
[j
].bitfield
.sreg2
2702 || x
->types
[j
].bitfield
.sreg3
2703 || x
->types
[j
].bitfield
.control
2704 || x
->types
[j
].bitfield
.debug
2705 || x
->types
[j
].bitfield
.test
)
2706 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2707 if (operand_type_check (x
->types
[j
], imm
))
2709 if (operand_type_check (x
->types
[j
], disp
))
2710 pe (x
->op
[j
].disps
);
2715 pte (insn_template
*t
)
2718 fprintf (stdout
, " %d operands ", t
->operands
);
2719 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2720 if (t
->extension_opcode
!= None
)
2721 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2722 if (t
->opcode_modifier
.d
)
2723 fprintf (stdout
, "D");
2724 if (t
->opcode_modifier
.w
)
2725 fprintf (stdout
, "W");
2726 fprintf (stdout
, "\n");
2727 for (j
= 0; j
< t
->operands
; j
++)
2729 fprintf (stdout
, " #%d type ", j
+ 1);
2730 pt (t
->operand_types
[j
]);
2731 fprintf (stdout
, "\n");
2738 fprintf (stdout
, " operation %d\n", e
->X_op
);
2739 fprintf (stdout
, " add_number %ld (%lx)\n",
2740 (long) e
->X_add_number
, (long) e
->X_add_number
);
2741 if (e
->X_add_symbol
)
2743 fprintf (stdout
, " add_symbol ");
2744 ps (e
->X_add_symbol
);
2745 fprintf (stdout
, "\n");
2749 fprintf (stdout
, " op_symbol ");
2750 ps (e
->X_op_symbol
);
2751 fprintf (stdout
, "\n");
2758 fprintf (stdout
, "%s type %s%s",
2760 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2761 segment_name (S_GET_SEGMENT (s
)));
2764 static struct type_name
2766 i386_operand_type mask
;
2769 const type_names
[] =
2771 { OPERAND_TYPE_REG8
, "r8" },
2772 { OPERAND_TYPE_REG16
, "r16" },
2773 { OPERAND_TYPE_REG32
, "r32" },
2774 { OPERAND_TYPE_REG64
, "r64" },
2775 { OPERAND_TYPE_IMM8
, "i8" },
2776 { OPERAND_TYPE_IMM8
, "i8s" },
2777 { OPERAND_TYPE_IMM16
, "i16" },
2778 { OPERAND_TYPE_IMM32
, "i32" },
2779 { OPERAND_TYPE_IMM32S
, "i32s" },
2780 { OPERAND_TYPE_IMM64
, "i64" },
2781 { OPERAND_TYPE_IMM1
, "i1" },
2782 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2783 { OPERAND_TYPE_DISP8
, "d8" },
2784 { OPERAND_TYPE_DISP16
, "d16" },
2785 { OPERAND_TYPE_DISP32
, "d32" },
2786 { OPERAND_TYPE_DISP32S
, "d32s" },
2787 { OPERAND_TYPE_DISP64
, "d64" },
2788 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2789 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2790 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2791 { OPERAND_TYPE_CONTROL
, "control reg" },
2792 { OPERAND_TYPE_TEST
, "test reg" },
2793 { OPERAND_TYPE_DEBUG
, "debug reg" },
2794 { OPERAND_TYPE_FLOATREG
, "FReg" },
2795 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2796 { OPERAND_TYPE_SREG2
, "SReg2" },
2797 { OPERAND_TYPE_SREG3
, "SReg3" },
2798 { OPERAND_TYPE_ACC
, "Acc" },
2799 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2800 { OPERAND_TYPE_REGMMX
, "rMMX" },
2801 { OPERAND_TYPE_REGXMM
, "rXMM" },
2802 { OPERAND_TYPE_REGYMM
, "rYMM" },
2803 { OPERAND_TYPE_REGZMM
, "rZMM" },
2804 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2805 { OPERAND_TYPE_ESSEG
, "es" },
2809 pt (i386_operand_type t
)
2812 i386_operand_type a
;
2814 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2816 a
= operand_type_and (t
, type_names
[j
].mask
);
2817 if (!operand_type_all_zero (&a
))
2818 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2823 #endif /* DEBUG386 */
2825 static bfd_reloc_code_real_type
2826 reloc (unsigned int size
,
2830 bfd_reloc_code_real_type other
)
2832 if (other
!= NO_RELOC
)
2834 reloc_howto_type
*rel
;
2839 case BFD_RELOC_X86_64_GOT32
:
2840 return BFD_RELOC_X86_64_GOT64
;
2842 case BFD_RELOC_X86_64_GOTPLT64
:
2843 return BFD_RELOC_X86_64_GOTPLT64
;
2845 case BFD_RELOC_X86_64_PLTOFF64
:
2846 return BFD_RELOC_X86_64_PLTOFF64
;
2848 case BFD_RELOC_X86_64_GOTPC32
:
2849 other
= BFD_RELOC_X86_64_GOTPC64
;
2851 case BFD_RELOC_X86_64_GOTPCREL
:
2852 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2854 case BFD_RELOC_X86_64_TPOFF32
:
2855 other
= BFD_RELOC_X86_64_TPOFF64
;
2857 case BFD_RELOC_X86_64_DTPOFF32
:
2858 other
= BFD_RELOC_X86_64_DTPOFF64
;
2864 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2865 if (other
== BFD_RELOC_SIZE32
)
2868 other
= BFD_RELOC_SIZE64
;
2871 as_bad (_("there are no pc-relative size relocations"));
2877 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2878 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2881 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2883 as_bad (_("unknown relocation (%u)"), other
);
2884 else if (size
!= bfd_get_reloc_size (rel
))
2885 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2886 bfd_get_reloc_size (rel
),
2888 else if (pcrel
&& !rel
->pc_relative
)
2889 as_bad (_("non-pc-relative relocation for pc-relative field"));
2890 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2892 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2894 as_bad (_("relocated field and relocation type differ in signedness"));
2903 as_bad (_("there are no unsigned pc-relative relocations"));
2906 case 1: return BFD_RELOC_8_PCREL
;
2907 case 2: return BFD_RELOC_16_PCREL
;
2908 case 4: return (bnd_prefix
&& object_64bit
2909 ? BFD_RELOC_X86_64_PC32_BND
2910 : BFD_RELOC_32_PCREL
);
2911 case 8: return BFD_RELOC_64_PCREL
;
2913 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2920 case 4: return BFD_RELOC_X86_64_32S
;
2925 case 1: return BFD_RELOC_8
;
2926 case 2: return BFD_RELOC_16
;
2927 case 4: return BFD_RELOC_32
;
2928 case 8: return BFD_RELOC_64
;
2930 as_bad (_("cannot do %s %u byte relocation"),
2931 sign
> 0 ? "signed" : "unsigned", size
);
2937 /* Here we decide which fixups can be adjusted to make them relative to
2938 the beginning of the section instead of the symbol. Basically we need
2939 to make sure that the dynamic relocations are done correctly, so in
2940 some cases we force the original symbol to be used. */
2943 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2949 /* Don't adjust pc-relative references to merge sections in 64-bit
2951 if (use_rela_relocations
2952 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2956 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2957 and changed later by validate_fix. */
2958 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2959 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2962 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2963 for size relocations. */
2964 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2965 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2966 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2967 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2968 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2969 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2970 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2971 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2972 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2973 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2974 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2975 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2976 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2977 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2978 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2979 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2980 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2981 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2982 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2983 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2984 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2985 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2986 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2987 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2988 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2989 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2990 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2991 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2992 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2993 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3000 intel_float_operand (const char *mnemonic
)
3002 /* Note that the value returned is meaningful only for opcodes with (memory)
3003 operands, hence the code here is free to improperly handle opcodes that
3004 have no operands (for better performance and smaller code). */
3006 if (mnemonic
[0] != 'f')
3007 return 0; /* non-math */
3009 switch (mnemonic
[1])
3011 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3012 the fs segment override prefix not currently handled because no
3013 call path can make opcodes without operands get here */
3015 return 2 /* integer op */;
3017 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3018 return 3; /* fldcw/fldenv */
3021 if (mnemonic
[2] != 'o' /* fnop */)
3022 return 3; /* non-waiting control op */
3025 if (mnemonic
[2] == 's')
3026 return 3; /* frstor/frstpm */
3029 if (mnemonic
[2] == 'a')
3030 return 3; /* fsave */
3031 if (mnemonic
[2] == 't')
3033 switch (mnemonic
[3])
3035 case 'c': /* fstcw */
3036 case 'd': /* fstdw */
3037 case 'e': /* fstenv */
3038 case 's': /* fsts[gw] */
3044 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3045 return 0; /* fxsave/fxrstor are not really math ops */
3052 /* Build the VEX prefix. */
3055 build_vex_prefix (const insn_template
*t
)
3057 unsigned int register_specifier
;
3058 unsigned int implied_prefix
;
3059 unsigned int vector_length
;
3061 /* Check register specifier. */
3062 if (i
.vex
.register_specifier
)
3064 register_specifier
=
3065 ~register_number (i
.vex
.register_specifier
) & 0xf;
3066 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3069 register_specifier
= 0xf;
3071 /* Use 2-byte VEX prefix by swappping destination and source
3074 && i
.operands
== i
.reg_operands
3075 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3076 && i
.tm
.opcode_modifier
.s
3079 unsigned int xchg
= i
.operands
- 1;
3080 union i386_op temp_op
;
3081 i386_operand_type temp_type
;
3083 temp_type
= i
.types
[xchg
];
3084 i
.types
[xchg
] = i
.types
[0];
3085 i
.types
[0] = temp_type
;
3086 temp_op
= i
.op
[xchg
];
3087 i
.op
[xchg
] = i
.op
[0];
3090 gas_assert (i
.rm
.mode
== 3);
3094 i
.rm
.regmem
= i
.rm
.reg
;
3097 /* Use the next insn. */
3101 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3102 vector_length
= avxscalar
;
3104 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3106 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3111 case DATA_PREFIX_OPCODE
:
3114 case REPE_PREFIX_OPCODE
:
3117 case REPNE_PREFIX_OPCODE
:
3124 /* Use 2-byte VEX prefix if possible. */
3125 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3126 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3127 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3129 /* 2-byte VEX prefix. */
3133 i
.vex
.bytes
[0] = 0xc5;
3135 /* Check the REX.R bit. */
3136 r
= (i
.rex
& REX_R
) ? 0 : 1;
3137 i
.vex
.bytes
[1] = (r
<< 7
3138 | register_specifier
<< 3
3139 | vector_length
<< 2
3144 /* 3-byte VEX prefix. */
3149 switch (i
.tm
.opcode_modifier
.vexopcode
)
3153 i
.vex
.bytes
[0] = 0xc4;
3157 i
.vex
.bytes
[0] = 0xc4;
3161 i
.vex
.bytes
[0] = 0xc4;
3165 i
.vex
.bytes
[0] = 0x8f;
3169 i
.vex
.bytes
[0] = 0x8f;
3173 i
.vex
.bytes
[0] = 0x8f;
3179 /* The high 3 bits of the second VEX byte are 1's compliment
3180 of RXB bits from REX. */
3181 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3183 /* Check the REX.W bit. */
3184 w
= (i
.rex
& REX_W
) ? 1 : 0;
3185 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3188 i
.vex
.bytes
[2] = (w
<< 7
3189 | register_specifier
<< 3
3190 | vector_length
<< 2
3195 /* Build the EVEX prefix. */
3198 build_evex_prefix (void)
3200 unsigned int register_specifier
;
3201 unsigned int implied_prefix
;
3203 rex_byte vrex_used
= 0;
3205 /* Check register specifier. */
3206 if (i
.vex
.register_specifier
)
3208 gas_assert ((i
.vrex
& REX_X
) == 0);
3210 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3211 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3212 register_specifier
+= 8;
3213 /* The upper 16 registers are encoded in the fourth byte of the
3215 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3216 i
.vex
.bytes
[3] = 0x8;
3217 register_specifier
= ~register_specifier
& 0xf;
3221 register_specifier
= 0xf;
3223 /* Encode upper 16 vector index register in the fourth byte of
3225 if (!(i
.vrex
& REX_X
))
3226 i
.vex
.bytes
[3] = 0x8;
3231 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3236 case DATA_PREFIX_OPCODE
:
3239 case REPE_PREFIX_OPCODE
:
3242 case REPNE_PREFIX_OPCODE
:
3249 /* 4 byte EVEX prefix. */
3251 i
.vex
.bytes
[0] = 0x62;
3254 switch (i
.tm
.opcode_modifier
.vexopcode
)
3270 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3272 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3274 /* The fifth bit of the second EVEX byte is 1's compliment of the
3275 REX_R bit in VREX. */
3276 if (!(i
.vrex
& REX_R
))
3277 i
.vex
.bytes
[1] |= 0x10;
3281 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3283 /* When all operands are registers, the REX_X bit in REX is not
3284 used. We reuse it to encode the upper 16 registers, which is
3285 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3286 as 1's compliment. */
3287 if ((i
.vrex
& REX_B
))
3290 i
.vex
.bytes
[1] &= ~0x40;
3294 /* EVEX instructions shouldn't need the REX prefix. */
3295 i
.vrex
&= ~vrex_used
;
3296 gas_assert (i
.vrex
== 0);
3298 /* Check the REX.W bit. */
3299 w
= (i
.rex
& REX_W
) ? 1 : 0;
3300 if (i
.tm
.opcode_modifier
.vexw
)
3302 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3305 /* If w is not set it means we are dealing with WIG instruction. */
3308 if (evexwig
== evexw1
)
3312 /* Encode the U bit. */
3313 implied_prefix
|= 0x4;
3315 /* The third byte of the EVEX prefix. */
3316 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3318 /* The fourth byte of the EVEX prefix. */
3319 /* The zeroing-masking bit. */
3320 if (i
.mask
&& i
.mask
->zeroing
)
3321 i
.vex
.bytes
[3] |= 0x80;
3323 /* Don't always set the broadcast bit if there is no RC. */
3326 /* Encode the vector length. */
3327 unsigned int vec_length
;
3329 switch (i
.tm
.opcode_modifier
.evex
)
3331 case EVEXLIG
: /* LL' is ignored */
3332 vec_length
= evexlig
<< 5;
3335 vec_length
= 0 << 5;
3338 vec_length
= 1 << 5;
3341 vec_length
= 2 << 5;
3347 i
.vex
.bytes
[3] |= vec_length
;
3348 /* Encode the broadcast bit. */
3350 i
.vex
.bytes
[3] |= 0x10;
3354 if (i
.rounding
->type
!= saeonly
)
3355 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3357 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3360 if (i
.mask
&& i
.mask
->mask
)
3361 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3365 process_immext (void)
3369 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3372 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3373 with an opcode suffix which is coded in the same place as an
3374 8-bit immediate field would be.
3375 Here we check those operands and remove them afterwards. */
3378 for (x
= 0; x
< i
.operands
; x
++)
3379 if (register_number (i
.op
[x
].regs
) != x
)
3380 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3381 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3387 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3388 which is coded in the same place as an 8-bit immediate field
3389 would be. Here we fake an 8-bit immediate operand from the
3390 opcode suffix stored in tm.extension_opcode.
3392 AVX instructions also use this encoding, for some of
3393 3 argument instructions. */
3395 gas_assert (i
.imm_operands
<= 1
3397 || ((i
.tm
.opcode_modifier
.vex
3398 || i
.tm
.opcode_modifier
.evex
)
3399 && i
.operands
<= 4)));
3401 exp
= &im_expressions
[i
.imm_operands
++];
3402 i
.op
[i
.operands
].imms
= exp
;
3403 i
.types
[i
.operands
] = imm8
;
3405 exp
->X_op
= O_constant
;
3406 exp
->X_add_number
= i
.tm
.extension_opcode
;
3407 i
.tm
.extension_opcode
= None
;
3414 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3419 as_bad (_("invalid instruction `%s' after `%s'"),
3420 i
.tm
.name
, i
.hle_prefix
);
3423 if (i
.prefix
[LOCK_PREFIX
])
3425 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3429 case HLEPrefixRelease
:
3430 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3432 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3436 if (i
.mem_operands
== 0
3437 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3439 as_bad (_("memory destination needed for instruction `%s'"
3440 " after `xrelease'"), i
.tm
.name
);
3447 /* This is the guts of the machine-dependent assembler. LINE points to a
3448 machine dependent instruction. This function is supposed to emit
3449 the frags/bytes it assembles to. */
3452 md_assemble (char *line
)
3455 char mnemonic
[MAX_MNEM_SIZE
];
3456 const insn_template
*t
;
3458 /* Initialize globals. */
3459 memset (&i
, '\0', sizeof (i
));
3460 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3461 i
.reloc
[j
] = NO_RELOC
;
3462 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3463 memset (im_expressions
, '\0', sizeof (im_expressions
));
3464 save_stack_p
= save_stack
;
3466 /* First parse an instruction mnemonic & call i386_operand for the operands.
3467 We assume that the scrubber has arranged it so that line[0] is the valid
3468 start of a (possibly prefixed) mnemonic. */
3470 line
= parse_insn (line
, mnemonic
);
3474 line
= parse_operands (line
, mnemonic
);
3479 /* Now we've parsed the mnemonic into a set of templates, and have the
3480 operands at hand. */
3482 /* All intel opcodes have reversed operands except for "bound" and
3483 "enter". We also don't reverse intersegment "jmp" and "call"
3484 instructions with 2 immediate operands so that the immediate segment
3485 precedes the offset, as it does when in AT&T mode. */
3488 && (strcmp (mnemonic
, "bound") != 0)
3489 && (strcmp (mnemonic
, "invlpga") != 0)
3490 && !(operand_type_check (i
.types
[0], imm
)
3491 && operand_type_check (i
.types
[1], imm
)))
3494 /* The order of the immediates should be reversed
3495 for 2 immediates extrq and insertq instructions */
3496 if (i
.imm_operands
== 2
3497 && (strcmp (mnemonic
, "extrq") == 0
3498 || strcmp (mnemonic
, "insertq") == 0))
3499 swap_2_operands (0, 1);
3504 /* Don't optimize displacement for movabs since it only takes 64bit
3507 && i
.disp_encoding
!= disp_encoding_32bit
3508 && (flag_code
!= CODE_64BIT
3509 || strcmp (mnemonic
, "movabs") != 0))
3512 /* Next, we find a template that matches the given insn,
3513 making sure the overlap of the given operands types is consistent
3514 with the template operand types. */
3516 if (!(t
= match_template ()))
3519 if (sse_check
!= check_none
3520 && !i
.tm
.opcode_modifier
.noavx
3521 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3522 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3523 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3524 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3525 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3526 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3528 (sse_check
== check_warning
3530 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3533 /* Zap movzx and movsx suffix. The suffix has been set from
3534 "word ptr" or "byte ptr" on the source operand in Intel syntax
3535 or extracted from mnemonic in AT&T syntax. But we'll use
3536 the destination register to choose the suffix for encoding. */
3537 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3539 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3540 there is no suffix, the default will be byte extension. */
3541 if (i
.reg_operands
!= 2
3544 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3549 if (i
.tm
.opcode_modifier
.fwait
)
3550 if (!add_prefix (FWAIT_OPCODE
))
3553 /* Check if REP prefix is OK. */
3554 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3556 as_bad (_("invalid instruction `%s' after `%s'"),
3557 i
.tm
.name
, i
.rep_prefix
);
3561 /* Check for lock without a lockable instruction. Destination operand
3562 must be memory unless it is xchg (0x86). */
3563 if (i
.prefix
[LOCK_PREFIX
]
3564 && (!i
.tm
.opcode_modifier
.islockable
3565 || i
.mem_operands
== 0
3566 || (i
.tm
.base_opcode
!= 0x86
3567 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3569 as_bad (_("expecting lockable instruction after `lock'"));
3573 /* Check if HLE prefix is OK. */
3574 if (i
.hle_prefix
&& !check_hle ())
3577 /* Check BND prefix. */
3578 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3579 as_bad (_("expecting valid branch instruction after `bnd'"));
3581 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3582 && flag_code
== CODE_64BIT
3583 && i
.prefix
[ADDR_PREFIX
])
3584 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3586 /* Insert BND prefix. */
3588 && i
.tm
.opcode_modifier
.bndprefixok
3589 && !i
.prefix
[BND_PREFIX
])
3590 add_prefix (BND_PREFIX_OPCODE
);
3592 /* Check string instruction segment overrides. */
3593 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3595 if (!check_string ())
3597 i
.disp_operands
= 0;
3600 if (!process_suffix ())
3603 /* Update operand types. */
3604 for (j
= 0; j
< i
.operands
; j
++)
3605 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3607 /* Make still unresolved immediate matches conform to size of immediate
3608 given in i.suffix. */
3609 if (!finalize_imm ())
3612 if (i
.types
[0].bitfield
.imm1
)
3613 i
.imm_operands
= 0; /* kludge for shift insns. */
3615 /* We only need to check those implicit registers for instructions
3616 with 3 operands or less. */
3617 if (i
.operands
<= 3)
3618 for (j
= 0; j
< i
.operands
; j
++)
3619 if (i
.types
[j
].bitfield
.inoutportreg
3620 || i
.types
[j
].bitfield
.shiftcount
3621 || i
.types
[j
].bitfield
.acc
3622 || i
.types
[j
].bitfield
.floatacc
)
3625 /* ImmExt should be processed after SSE2AVX. */
3626 if (!i
.tm
.opcode_modifier
.sse2avx
3627 && i
.tm
.opcode_modifier
.immext
)
3630 /* For insns with operands there are more diddles to do to the opcode. */
3633 if (!process_operands ())
3636 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3638 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3639 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3642 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3644 if (flag_code
== CODE_16BIT
)
3646 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3651 if (i
.tm
.opcode_modifier
.vex
)
3652 build_vex_prefix (t
);
3654 build_evex_prefix ();
3657 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3658 instructions may define INT_OPCODE as well, so avoid this corner
3659 case for those instructions that use MODRM. */
3660 if (i
.tm
.base_opcode
== INT_OPCODE
3661 && !i
.tm
.opcode_modifier
.modrm
3662 && i
.op
[0].imms
->X_add_number
== 3)
3664 i
.tm
.base_opcode
= INT3_OPCODE
;
3668 if ((i
.tm
.opcode_modifier
.jump
3669 || i
.tm
.opcode_modifier
.jumpbyte
3670 || i
.tm
.opcode_modifier
.jumpdword
)
3671 && i
.op
[0].disps
->X_op
== O_constant
)
3673 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3674 the absolute address given by the constant. Since ix86 jumps and
3675 calls are pc relative, we need to generate a reloc. */
3676 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3677 i
.op
[0].disps
->X_op
= O_symbol
;
3680 if (i
.tm
.opcode_modifier
.rex64
)
3683 /* For 8 bit registers we need an empty rex prefix. Also if the
3684 instruction already has a prefix, we need to convert old
3685 registers to new ones. */
3687 if ((i
.types
[0].bitfield
.reg8
3688 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3689 || (i
.types
[1].bitfield
.reg8
3690 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3691 || ((i
.types
[0].bitfield
.reg8
3692 || i
.types
[1].bitfield
.reg8
)
3697 i
.rex
|= REX_OPCODE
;
3698 for (x
= 0; x
< 2; x
++)
3700 /* Look for 8 bit operand that uses old registers. */
3701 if (i
.types
[x
].bitfield
.reg8
3702 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3704 /* In case it is "hi" register, give up. */
3705 if (i
.op
[x
].regs
->reg_num
> 3)
3706 as_bad (_("can't encode register '%s%s' in an "
3707 "instruction requiring REX prefix."),
3708 register_prefix
, i
.op
[x
].regs
->reg_name
);
3710 /* Otherwise it is equivalent to the extended register.
3711 Since the encoding doesn't change this is merely
3712 cosmetic cleanup for debug output. */
3714 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3720 add_prefix (REX_OPCODE
| i
.rex
);
3722 /* We are ready to output the insn. */
3727 parse_insn (char *line
, char *mnemonic
)
3730 char *token_start
= l
;
3733 const insn_template
*t
;
3739 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3744 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3746 as_bad (_("no such instruction: `%s'"), token_start
);
3751 if (!is_space_char (*l
)
3752 && *l
!= END_OF_INSN
3754 || (*l
!= PREFIX_SEPARATOR
3757 as_bad (_("invalid character %s in mnemonic"),
3758 output_invalid (*l
));
3761 if (token_start
== l
)
3763 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3764 as_bad (_("expecting prefix; got nothing"));
3766 as_bad (_("expecting mnemonic; got nothing"));
3770 /* Look up instruction (or prefix) via hash table. */
3771 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3773 if (*l
!= END_OF_INSN
3774 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3775 && current_templates
3776 && current_templates
->start
->opcode_modifier
.isprefix
)
3778 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3780 as_bad ((flag_code
!= CODE_64BIT
3781 ? _("`%s' is only supported in 64-bit mode")
3782 : _("`%s' is not supported in 64-bit mode")),
3783 current_templates
->start
->name
);
3786 /* If we are in 16-bit mode, do not allow addr16 or data16.
3787 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3788 if ((current_templates
->start
->opcode_modifier
.size16
3789 || current_templates
->start
->opcode_modifier
.size32
)
3790 && flag_code
!= CODE_64BIT
3791 && (current_templates
->start
->opcode_modifier
.size32
3792 ^ (flag_code
== CODE_16BIT
)))
3794 as_bad (_("redundant %s prefix"),
3795 current_templates
->start
->name
);
3798 /* Add prefix, checking for repeated prefixes. */
3799 switch (add_prefix (current_templates
->start
->base_opcode
))
3804 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3805 i
.hle_prefix
= current_templates
->start
->name
;
3806 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3807 i
.bnd_prefix
= current_templates
->start
->name
;
3809 i
.rep_prefix
= current_templates
->start
->name
;
3814 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3821 if (!current_templates
)
3823 /* Check if we should swap operand or force 32bit displacement in
3825 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3827 else if (mnem_p
- 3 == dot_p
3830 i
.disp_encoding
= disp_encoding_8bit
;
3831 else if (mnem_p
- 4 == dot_p
3835 i
.disp_encoding
= disp_encoding_32bit
;
3840 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3843 if (!current_templates
)
3846 /* See if we can get a match by trimming off a suffix. */
3849 case WORD_MNEM_SUFFIX
:
3850 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3851 i
.suffix
= SHORT_MNEM_SUFFIX
;
3853 case BYTE_MNEM_SUFFIX
:
3854 case QWORD_MNEM_SUFFIX
:
3855 i
.suffix
= mnem_p
[-1];
3857 current_templates
= (const templates
*) hash_find (op_hash
,
3860 case SHORT_MNEM_SUFFIX
:
3861 case LONG_MNEM_SUFFIX
:
3864 i
.suffix
= mnem_p
[-1];
3866 current_templates
= (const templates
*) hash_find (op_hash
,
3875 if (intel_float_operand (mnemonic
) == 1)
3876 i
.suffix
= SHORT_MNEM_SUFFIX
;
3878 i
.suffix
= LONG_MNEM_SUFFIX
;
3880 current_templates
= (const templates
*) hash_find (op_hash
,
3885 if (!current_templates
)
3887 as_bad (_("no such instruction: `%s'"), token_start
);
3892 if (current_templates
->start
->opcode_modifier
.jump
3893 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3895 /* Check for a branch hint. We allow ",pt" and ",pn" for
3896 predict taken and predict not taken respectively.
3897 I'm not sure that branch hints actually do anything on loop
3898 and jcxz insns (JumpByte) for current Pentium4 chips. They
3899 may work in the future and it doesn't hurt to accept them
3901 if (l
[0] == ',' && l
[1] == 'p')
3905 if (!add_prefix (DS_PREFIX_OPCODE
))
3909 else if (l
[2] == 'n')
3911 if (!add_prefix (CS_PREFIX_OPCODE
))
3917 /* Any other comma loses. */
3920 as_bad (_("invalid character %s in mnemonic"),
3921 output_invalid (*l
));
3925 /* Check if instruction is supported on specified architecture. */
3927 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3929 supported
|= cpu_flags_match (t
);
3930 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3934 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3936 as_bad (flag_code
== CODE_64BIT
3937 ? _("`%s' is not supported in 64-bit mode")
3938 : _("`%s' is only supported in 64-bit mode"),
3939 current_templates
->start
->name
);
3942 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3944 as_bad (_("`%s' is not supported on `%s%s'"),
3945 current_templates
->start
->name
,
3946 cpu_arch_name
? cpu_arch_name
: default_arch
,
3947 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3952 if (!cpu_arch_flags
.bitfield
.cpui386
3953 && (flag_code
!= CODE_16BIT
))
3955 as_warn (_("use .code16 to ensure correct addressing mode"));
3962 parse_operands (char *l
, const char *mnemonic
)
3966 /* 1 if operand is pending after ','. */
3967 unsigned int expecting_operand
= 0;
3969 /* Non-zero if operand parens not balanced. */
3970 unsigned int paren_not_balanced
;
3972 while (*l
!= END_OF_INSN
)
3974 /* Skip optional white space before operand. */
3975 if (is_space_char (*l
))
3977 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3979 as_bad (_("invalid character %s before operand %d"),
3980 output_invalid (*l
),
3984 token_start
= l
; /* after white space */
3985 paren_not_balanced
= 0;
3986 while (paren_not_balanced
|| *l
!= ',')
3988 if (*l
== END_OF_INSN
)
3990 if (paren_not_balanced
)
3993 as_bad (_("unbalanced parenthesis in operand %d."),
3996 as_bad (_("unbalanced brackets in operand %d."),
4001 break; /* we are done */
4003 else if (!is_operand_char (*l
) && !is_space_char (*l
))
4005 as_bad (_("invalid character %s in operand %d"),
4006 output_invalid (*l
),
4013 ++paren_not_balanced
;
4015 --paren_not_balanced
;
4020 ++paren_not_balanced
;
4022 --paren_not_balanced
;
4026 if (l
!= token_start
)
4027 { /* Yes, we've read in another operand. */
4028 unsigned int operand_ok
;
4029 this_operand
= i
.operands
++;
4030 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4031 if (i
.operands
> MAX_OPERANDS
)
4033 as_bad (_("spurious operands; (%d operands/instruction max)"),
4037 /* Now parse operand adding info to 'i' as we go along. */
4038 END_STRING_AND_SAVE (l
);
4042 i386_intel_operand (token_start
,
4043 intel_float_operand (mnemonic
));
4045 operand_ok
= i386_att_operand (token_start
);
4047 RESTORE_END_STRING (l
);
4053 if (expecting_operand
)
4055 expecting_operand_after_comma
:
4056 as_bad (_("expecting operand after ','; got nothing"));
4061 as_bad (_("expecting operand before ','; got nothing"));
4066 /* Now *l must be either ',' or END_OF_INSN. */
4069 if (*++l
== END_OF_INSN
)
4071 /* Just skip it, if it's \n complain. */
4072 goto expecting_operand_after_comma
;
4074 expecting_operand
= 1;
4081 swap_2_operands (int xchg1
, int xchg2
)
4083 union i386_op temp_op
;
4084 i386_operand_type temp_type
;
4085 enum bfd_reloc_code_real temp_reloc
;
4087 temp_type
= i
.types
[xchg2
];
4088 i
.types
[xchg2
] = i
.types
[xchg1
];
4089 i
.types
[xchg1
] = temp_type
;
4090 temp_op
= i
.op
[xchg2
];
4091 i
.op
[xchg2
] = i
.op
[xchg1
];
4092 i
.op
[xchg1
] = temp_op
;
4093 temp_reloc
= i
.reloc
[xchg2
];
4094 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4095 i
.reloc
[xchg1
] = temp_reloc
;
4099 if (i
.mask
->operand
== xchg1
)
4100 i
.mask
->operand
= xchg2
;
4101 else if (i
.mask
->operand
== xchg2
)
4102 i
.mask
->operand
= xchg1
;
4106 if (i
.broadcast
->operand
== xchg1
)
4107 i
.broadcast
->operand
= xchg2
;
4108 else if (i
.broadcast
->operand
== xchg2
)
4109 i
.broadcast
->operand
= xchg1
;
4113 if (i
.rounding
->operand
== xchg1
)
4114 i
.rounding
->operand
= xchg2
;
4115 else if (i
.rounding
->operand
== xchg2
)
4116 i
.rounding
->operand
= xchg1
;
4121 swap_operands (void)
4127 swap_2_operands (1, i
.operands
- 2);
4130 swap_2_operands (0, i
.operands
- 1);
4136 if (i
.mem_operands
== 2)
4138 const seg_entry
*temp_seg
;
4139 temp_seg
= i
.seg
[0];
4140 i
.seg
[0] = i
.seg
[1];
4141 i
.seg
[1] = temp_seg
;
4145 /* Try to ensure constant immediates are represented in the smallest
4150 char guess_suffix
= 0;
4154 guess_suffix
= i
.suffix
;
4155 else if (i
.reg_operands
)
4157 /* Figure out a suffix from the last register operand specified.
4158 We can't do this properly yet, ie. excluding InOutPortReg,
4159 but the following works for instructions with immediates.
4160 In any case, we can't set i.suffix yet. */
4161 for (op
= i
.operands
; --op
>= 0;)
4162 if (i
.types
[op
].bitfield
.reg8
)
4164 guess_suffix
= BYTE_MNEM_SUFFIX
;
4167 else if (i
.types
[op
].bitfield
.reg16
)
4169 guess_suffix
= WORD_MNEM_SUFFIX
;
4172 else if (i
.types
[op
].bitfield
.reg32
)
4174 guess_suffix
= LONG_MNEM_SUFFIX
;
4177 else if (i
.types
[op
].bitfield
.reg64
)
4179 guess_suffix
= QWORD_MNEM_SUFFIX
;
4183 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4184 guess_suffix
= WORD_MNEM_SUFFIX
;
4186 for (op
= i
.operands
; --op
>= 0;)
4187 if (operand_type_check (i
.types
[op
], imm
))
4189 switch (i
.op
[op
].imms
->X_op
)
4192 /* If a suffix is given, this operand may be shortened. */
4193 switch (guess_suffix
)
4195 case LONG_MNEM_SUFFIX
:
4196 i
.types
[op
].bitfield
.imm32
= 1;
4197 i
.types
[op
].bitfield
.imm64
= 1;
4199 case WORD_MNEM_SUFFIX
:
4200 i
.types
[op
].bitfield
.imm16
= 1;
4201 i
.types
[op
].bitfield
.imm32
= 1;
4202 i
.types
[op
].bitfield
.imm32s
= 1;
4203 i
.types
[op
].bitfield
.imm64
= 1;
4205 case BYTE_MNEM_SUFFIX
:
4206 i
.types
[op
].bitfield
.imm8
= 1;
4207 i
.types
[op
].bitfield
.imm8s
= 1;
4208 i
.types
[op
].bitfield
.imm16
= 1;
4209 i
.types
[op
].bitfield
.imm32
= 1;
4210 i
.types
[op
].bitfield
.imm32s
= 1;
4211 i
.types
[op
].bitfield
.imm64
= 1;
4215 /* If this operand is at most 16 bits, convert it
4216 to a signed 16 bit number before trying to see
4217 whether it will fit in an even smaller size.
4218 This allows a 16-bit operand such as $0xffe0 to
4219 be recognised as within Imm8S range. */
4220 if ((i
.types
[op
].bitfield
.imm16
)
4221 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4223 i
.op
[op
].imms
->X_add_number
=
4224 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4226 if ((i
.types
[op
].bitfield
.imm32
)
4227 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4230 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4231 ^ ((offsetT
) 1 << 31))
4232 - ((offsetT
) 1 << 31));
4235 = operand_type_or (i
.types
[op
],
4236 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4238 /* We must avoid matching of Imm32 templates when 64bit
4239 only immediate is available. */
4240 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4241 i
.types
[op
].bitfield
.imm32
= 0;
4248 /* Symbols and expressions. */
4250 /* Convert symbolic operand to proper sizes for matching, but don't
4251 prevent matching a set of insns that only supports sizes other
4252 than those matching the insn suffix. */
4254 i386_operand_type mask
, allowed
;
4255 const insn_template
*t
;
4257 operand_type_set (&mask
, 0);
4258 operand_type_set (&allowed
, 0);
4260 for (t
= current_templates
->start
;
4261 t
< current_templates
->end
;
4263 allowed
= operand_type_or (allowed
,
4264 t
->operand_types
[op
]);
4265 switch (guess_suffix
)
4267 case QWORD_MNEM_SUFFIX
:
4268 mask
.bitfield
.imm64
= 1;
4269 mask
.bitfield
.imm32s
= 1;
4271 case LONG_MNEM_SUFFIX
:
4272 mask
.bitfield
.imm32
= 1;
4274 case WORD_MNEM_SUFFIX
:
4275 mask
.bitfield
.imm16
= 1;
4277 case BYTE_MNEM_SUFFIX
:
4278 mask
.bitfield
.imm8
= 1;
4283 allowed
= operand_type_and (mask
, allowed
);
4284 if (!operand_type_all_zero (&allowed
))
4285 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4292 /* Try to use the smallest displacement type too. */
4294 optimize_disp (void)
4298 for (op
= i
.operands
; --op
>= 0;)
4299 if (operand_type_check (i
.types
[op
], disp
))
4301 if (i
.op
[op
].disps
->X_op
== O_constant
)
4303 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4305 if (i
.types
[op
].bitfield
.disp16
4306 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4308 /* If this operand is at most 16 bits, convert
4309 to a signed 16 bit number and don't use 64bit
4311 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4312 i
.types
[op
].bitfield
.disp64
= 0;
4314 if (i
.types
[op
].bitfield
.disp32
4315 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4317 /* If this operand is at most 32 bits, convert
4318 to a signed 32 bit number and don't use 64bit
4320 op_disp
&= (((offsetT
) 2 << 31) - 1);
4321 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4322 i
.types
[op
].bitfield
.disp64
= 0;
4324 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4326 i
.types
[op
].bitfield
.disp8
= 0;
4327 i
.types
[op
].bitfield
.disp16
= 0;
4328 i
.types
[op
].bitfield
.disp32
= 0;
4329 i
.types
[op
].bitfield
.disp32s
= 0;
4330 i
.types
[op
].bitfield
.disp64
= 0;
4334 else if (flag_code
== CODE_64BIT
)
4336 if (fits_in_signed_long (op_disp
))
4338 i
.types
[op
].bitfield
.disp64
= 0;
4339 i
.types
[op
].bitfield
.disp32s
= 1;
4341 if (i
.prefix
[ADDR_PREFIX
]
4342 && fits_in_unsigned_long (op_disp
))
4343 i
.types
[op
].bitfield
.disp32
= 1;
4345 if ((i
.types
[op
].bitfield
.disp32
4346 || i
.types
[op
].bitfield
.disp32s
4347 || i
.types
[op
].bitfield
.disp16
)
4348 && fits_in_signed_byte (op_disp
))
4349 i
.types
[op
].bitfield
.disp8
= 1;
4351 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4352 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4354 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4355 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4356 i
.types
[op
].bitfield
.disp8
= 0;
4357 i
.types
[op
].bitfield
.disp16
= 0;
4358 i
.types
[op
].bitfield
.disp32
= 0;
4359 i
.types
[op
].bitfield
.disp32s
= 0;
4360 i
.types
[op
].bitfield
.disp64
= 0;
4363 /* We only support 64bit displacement on constants. */
4364 i
.types
[op
].bitfield
.disp64
= 0;
4368 /* Check if operands are valid for the instruction. */
4371 check_VecOperands (const insn_template
*t
)
4375 /* Without VSIB byte, we can't have a vector register for index. */
4376 if (!t
->opcode_modifier
.vecsib
4378 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4379 || i
.index_reg
->reg_type
.bitfield
.regymm
4380 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4382 i
.error
= unsupported_vector_index_register
;
4386 /* Check if default mask is allowed. */
4387 if (t
->opcode_modifier
.nodefmask
4388 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4390 i
.error
= no_default_mask
;
4394 /* For VSIB byte, we need a vector register for index, and all vector
4395 registers must be distinct. */
4396 if (t
->opcode_modifier
.vecsib
)
4399 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4400 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4401 || (t
->opcode_modifier
.vecsib
== VecSIB256
4402 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4403 || (t
->opcode_modifier
.vecsib
== VecSIB512
4404 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4406 i
.error
= invalid_vsib_address
;
4410 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4411 if (i
.reg_operands
== 2 && !i
.mask
)
4413 gas_assert (i
.types
[0].bitfield
.regxmm
4414 || i
.types
[0].bitfield
.regymm
);
4415 gas_assert (i
.types
[2].bitfield
.regxmm
4416 || i
.types
[2].bitfield
.regymm
);
4417 if (operand_check
== check_none
)
4419 if (register_number (i
.op
[0].regs
)
4420 != register_number (i
.index_reg
)
4421 && register_number (i
.op
[2].regs
)
4422 != register_number (i
.index_reg
)
4423 && register_number (i
.op
[0].regs
)
4424 != register_number (i
.op
[2].regs
))
4426 if (operand_check
== check_error
)
4428 i
.error
= invalid_vector_register_set
;
4431 as_warn (_("mask, index, and destination registers should be distinct"));
4433 else if (i
.reg_operands
== 1 && i
.mask
)
4435 if ((i
.types
[1].bitfield
.regymm
4436 || i
.types
[1].bitfield
.regzmm
)
4437 && (register_number (i
.op
[1].regs
)
4438 == register_number (i
.index_reg
)))
4440 if (operand_check
== check_error
)
4442 i
.error
= invalid_vector_register_set
;
4445 if (operand_check
!= check_none
)
4446 as_warn (_("index and destination registers should be distinct"));
4451 /* Check if broadcast is supported by the instruction and is applied
4452 to the memory operand. */
4455 int broadcasted_opnd_size
;
4457 /* Check if specified broadcast is supported in this instruction,
4458 and it's applied to memory operand of DWORD or QWORD type,
4459 depending on VecESize. */
4460 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4461 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4462 || (t
->opcode_modifier
.vecesize
== 0
4463 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4464 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4465 || (t
->opcode_modifier
.vecesize
== 1
4466 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4467 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4470 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4471 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4472 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4473 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4474 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4475 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4476 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4477 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4478 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4482 if ((broadcasted_opnd_size
== 256
4483 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4484 || (broadcasted_opnd_size
== 512
4485 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4488 i
.error
= unsupported_broadcast
;
4492 /* If broadcast is supported in this instruction, we need to check if
4493 operand of one-element size isn't specified without broadcast. */
4494 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4496 /* Find memory operand. */
4497 for (op
= 0; op
< i
.operands
; op
++)
4498 if (operand_type_check (i
.types
[op
], anymem
))
4500 gas_assert (op
< i
.operands
);
4501 /* Check size of the memory operand. */
4502 if ((t
->opcode_modifier
.vecesize
== 0
4503 && i
.types
[op
].bitfield
.dword
)
4504 || (t
->opcode_modifier
.vecesize
== 1
4505 && i
.types
[op
].bitfield
.qword
))
4507 i
.error
= broadcast_needed
;
4512 /* Check if requested masking is supported. */
4514 && (!t
->opcode_modifier
.masking
4516 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4518 i
.error
= unsupported_masking
;
4522 /* Check if masking is applied to dest operand. */
4523 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4525 i
.error
= mask_not_on_destination
;
4532 if ((i
.rounding
->type
!= saeonly
4533 && !t
->opcode_modifier
.staticrounding
)
4534 || (i
.rounding
->type
== saeonly
4535 && (t
->opcode_modifier
.staticrounding
4536 || !t
->opcode_modifier
.sae
)))
4538 i
.error
= unsupported_rc_sae
;
4541 /* If the instruction has several immediate operands and one of
4542 them is rounding, the rounding operand should be the last
4543 immediate operand. */
4544 if (i
.imm_operands
> 1
4545 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4547 i
.error
= rc_sae_operand_not_last_imm
;
4552 /* Check vector Disp8 operand. */
4553 if (t
->opcode_modifier
.disp8memshift
)
4556 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4558 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4560 for (op
= 0; op
< i
.operands
; op
++)
4561 if (operand_type_check (i
.types
[op
], disp
)
4562 && i
.op
[op
].disps
->X_op
== O_constant
)
4564 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4565 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4566 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4569 i
.types
[op
].bitfield
.vec_disp8
= 1;
4572 /* Vector insn can only have Vec_Disp8/Disp32 in
4573 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4575 i
.types
[op
].bitfield
.disp8
= 0;
4576 if (flag_code
!= CODE_16BIT
)
4577 i
.types
[op
].bitfield
.disp16
= 0;
4580 else if (flag_code
!= CODE_16BIT
)
4582 /* One form of this instruction supports vector Disp8.
4583 Try vector Disp8 if we need to use Disp32. */
4584 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4586 i
.error
= try_vector_disp8
;
4598 /* Check if operands are valid for the instruction. Update VEX
4602 VEX_check_operands (const insn_template
*t
)
4604 /* VREX is only valid with EVEX prefix. */
4605 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4607 i
.error
= invalid_register_operand
;
4611 if (!t
->opcode_modifier
.vex
)
4614 /* Only check VEX_Imm4, which must be the first operand. */
4615 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4617 if (i
.op
[0].imms
->X_op
!= O_constant
4618 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4624 /* Turn off Imm8 so that update_imm won't complain. */
4625 i
.types
[0] = vec_imm4
;
4631 static const insn_template
*
4632 match_template (void)
4634 /* Points to template once we've found it. */
4635 const insn_template
*t
;
4636 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4637 i386_operand_type overlap4
;
4638 unsigned int found_reverse_match
;
4639 i386_opcode_modifier suffix_check
;
4640 i386_operand_type operand_types
[MAX_OPERANDS
];
4641 int addr_prefix_disp
;
4643 unsigned int found_cpu_match
;
4644 unsigned int check_register
;
4645 enum i386_error specific_error
= 0;
4647 #if MAX_OPERANDS != 5
4648 # error "MAX_OPERANDS must be 5."
4651 found_reverse_match
= 0;
4652 addr_prefix_disp
= -1;
4654 memset (&suffix_check
, 0, sizeof (suffix_check
));
4655 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4656 suffix_check
.no_bsuf
= 1;
4657 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4658 suffix_check
.no_wsuf
= 1;
4659 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4660 suffix_check
.no_ssuf
= 1;
4661 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4662 suffix_check
.no_lsuf
= 1;
4663 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4664 suffix_check
.no_qsuf
= 1;
4665 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4666 suffix_check
.no_ldsuf
= 1;
4668 /* Must have right number of operands. */
4669 i
.error
= number_of_operands_mismatch
;
4671 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4673 addr_prefix_disp
= -1;
4675 if (i
.operands
!= t
->operands
)
4678 /* Check processor support. */
4679 i
.error
= unsupported
;
4680 found_cpu_match
= (cpu_flags_match (t
)
4681 == CPU_FLAGS_PERFECT_MATCH
);
4682 if (!found_cpu_match
)
4685 /* Check old gcc support. */
4686 i
.error
= old_gcc_only
;
4687 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4690 /* Check AT&T mnemonic. */
4691 i
.error
= unsupported_with_intel_mnemonic
;
4692 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4695 /* Check AT&T/Intel syntax. */
4696 i
.error
= unsupported_syntax
;
4697 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4698 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4701 /* Check the suffix, except for some instructions in intel mode. */
4702 i
.error
= invalid_instruction_suffix
;
4703 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4704 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4705 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4706 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4707 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4708 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4709 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4712 if (!operand_size_match (t
))
4715 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4716 operand_types
[j
] = t
->operand_types
[j
];
4718 /* In general, don't allow 64-bit operands in 32-bit mode. */
4719 if (i
.suffix
== QWORD_MNEM_SUFFIX
4720 && flag_code
!= CODE_64BIT
4722 ? (!t
->opcode_modifier
.ignoresize
4723 && !intel_float_operand (t
->name
))
4724 : intel_float_operand (t
->name
) != 2)
4725 && ((!operand_types
[0].bitfield
.regmmx
4726 && !operand_types
[0].bitfield
.regxmm
4727 && !operand_types
[0].bitfield
.regymm
4728 && !operand_types
[0].bitfield
.regzmm
)
4729 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4730 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4731 && operand_types
[t
->operands
> 1].bitfield
.regymm
4732 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4733 && (t
->base_opcode
!= 0x0fc7
4734 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4737 /* In general, don't allow 32-bit operands on pre-386. */
4738 else if (i
.suffix
== LONG_MNEM_SUFFIX
4739 && !cpu_arch_flags
.bitfield
.cpui386
4741 ? (!t
->opcode_modifier
.ignoresize
4742 && !intel_float_operand (t
->name
))
4743 : intel_float_operand (t
->name
) != 2)
4744 && ((!operand_types
[0].bitfield
.regmmx
4745 && !operand_types
[0].bitfield
.regxmm
)
4746 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4747 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4750 /* Do not verify operands when there are none. */
4754 /* We've found a match; break out of loop. */
4758 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4759 into Disp32/Disp16/Disp32 operand. */
4760 if (i
.prefix
[ADDR_PREFIX
] != 0)
4762 /* There should be only one Disp operand. */
4766 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4768 if (operand_types
[j
].bitfield
.disp16
)
4770 addr_prefix_disp
= j
;
4771 operand_types
[j
].bitfield
.disp32
= 1;
4772 operand_types
[j
].bitfield
.disp16
= 0;
4778 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4780 if (operand_types
[j
].bitfield
.disp32
)
4782 addr_prefix_disp
= j
;
4783 operand_types
[j
].bitfield
.disp32
= 0;
4784 operand_types
[j
].bitfield
.disp16
= 1;
4790 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4792 if (operand_types
[j
].bitfield
.disp64
)
4794 addr_prefix_disp
= j
;
4795 operand_types
[j
].bitfield
.disp64
= 0;
4796 operand_types
[j
].bitfield
.disp32
= 1;
4804 /* We check register size if needed. */
4805 check_register
= t
->opcode_modifier
.checkregsize
;
4806 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4807 switch (t
->operands
)
4810 if (!operand_type_match (overlap0
, i
.types
[0]))
4814 /* xchg %eax, %eax is a special case. It is an aliase for nop
4815 only in 32bit mode and we can use opcode 0x90. In 64bit
4816 mode, we can't use 0x90 for xchg %eax, %eax since it should
4817 zero-extend %eax to %rax. */
4818 if (flag_code
== CODE_64BIT
4819 && t
->base_opcode
== 0x90
4820 && operand_type_equal (&i
.types
[0], &acc32
)
4821 && operand_type_equal (&i
.types
[1], &acc32
))
4825 /* If we swap operand in encoding, we either match
4826 the next one or reverse direction of operands. */
4827 if (t
->opcode_modifier
.s
)
4829 else if (t
->opcode_modifier
.d
)
4834 /* If we swap operand in encoding, we match the next one. */
4835 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4839 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4840 if (!operand_type_match (overlap0
, i
.types
[0])
4841 || !operand_type_match (overlap1
, i
.types
[1])
4843 && !operand_type_register_match (overlap0
, i
.types
[0],
4845 overlap1
, i
.types
[1],
4848 /* Check if other direction is valid ... */
4849 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4853 /* Try reversing direction of operands. */
4854 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4855 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4856 if (!operand_type_match (overlap0
, i
.types
[0])
4857 || !operand_type_match (overlap1
, i
.types
[1])
4859 && !operand_type_register_match (overlap0
,
4866 /* Does not match either direction. */
4869 /* found_reverse_match holds which of D or FloatDR
4871 if (t
->opcode_modifier
.d
)
4872 found_reverse_match
= Opcode_D
;
4873 else if (t
->opcode_modifier
.floatd
)
4874 found_reverse_match
= Opcode_FloatD
;
4876 found_reverse_match
= 0;
4877 if (t
->opcode_modifier
.floatr
)
4878 found_reverse_match
|= Opcode_FloatR
;
4882 /* Found a forward 2 operand match here. */
4883 switch (t
->operands
)
4886 overlap4
= operand_type_and (i
.types
[4],
4889 overlap3
= operand_type_and (i
.types
[3],
4892 overlap2
= operand_type_and (i
.types
[2],
4897 switch (t
->operands
)
4900 if (!operand_type_match (overlap4
, i
.types
[4])
4901 || !operand_type_register_match (overlap3
,
4909 if (!operand_type_match (overlap3
, i
.types
[3])
4911 && !operand_type_register_match (overlap2
,
4919 /* Here we make use of the fact that there are no
4920 reverse match 3 operand instructions, and all 3
4921 operand instructions only need to be checked for
4922 register consistency between operands 2 and 3. */
4923 if (!operand_type_match (overlap2
, i
.types
[2])
4925 && !operand_type_register_match (overlap1
,
4935 /* Found either forward/reverse 2, 3 or 4 operand match here:
4936 slip through to break. */
4938 if (!found_cpu_match
)
4940 found_reverse_match
= 0;
4944 /* Check if vector and VEX operands are valid. */
4945 if (check_VecOperands (t
) || VEX_check_operands (t
))
4947 specific_error
= i
.error
;
4951 /* We've found a match; break out of loop. */
4955 if (t
== current_templates
->end
)
4957 /* We found no match. */
4958 const char *err_msg
;
4959 switch (specific_error
? specific_error
: i
.error
)
4963 case operand_size_mismatch
:
4964 err_msg
= _("operand size mismatch");
4966 case operand_type_mismatch
:
4967 err_msg
= _("operand type mismatch");
4969 case register_type_mismatch
:
4970 err_msg
= _("register type mismatch");
4972 case number_of_operands_mismatch
:
4973 err_msg
= _("number of operands mismatch");
4975 case invalid_instruction_suffix
:
4976 err_msg
= _("invalid instruction suffix");
4979 err_msg
= _("constant doesn't fit in 4 bits");
4982 err_msg
= _("only supported with old gcc");
4984 case unsupported_with_intel_mnemonic
:
4985 err_msg
= _("unsupported with Intel mnemonic");
4987 case unsupported_syntax
:
4988 err_msg
= _("unsupported syntax");
4991 as_bad (_("unsupported instruction `%s'"),
4992 current_templates
->start
->name
);
4994 case invalid_vsib_address
:
4995 err_msg
= _("invalid VSIB address");
4997 case invalid_vector_register_set
:
4998 err_msg
= _("mask, index, and destination registers must be distinct");
5000 case unsupported_vector_index_register
:
5001 err_msg
= _("unsupported vector index register");
5003 case unsupported_broadcast
:
5004 err_msg
= _("unsupported broadcast");
5006 case broadcast_not_on_src_operand
:
5007 err_msg
= _("broadcast not on source memory operand");
5009 case broadcast_needed
:
5010 err_msg
= _("broadcast is needed for operand of such type");
5012 case unsupported_masking
:
5013 err_msg
= _("unsupported masking");
5015 case mask_not_on_destination
:
5016 err_msg
= _("mask not on destination operand");
5018 case no_default_mask
:
5019 err_msg
= _("default mask isn't allowed");
5021 case unsupported_rc_sae
:
5022 err_msg
= _("unsupported static rounding/sae");
5024 case rc_sae_operand_not_last_imm
:
5026 err_msg
= _("RC/SAE operand must precede immediate operands");
5028 err_msg
= _("RC/SAE operand must follow immediate operands");
5030 case invalid_register_operand
:
5031 err_msg
= _("invalid register operand");
5034 as_bad (_("%s for `%s'"), err_msg
,
5035 current_templates
->start
->name
);
5039 if (!quiet_warnings
)
5042 && (i
.types
[0].bitfield
.jumpabsolute
5043 != operand_types
[0].bitfield
.jumpabsolute
))
5045 as_warn (_("indirect %s without `*'"), t
->name
);
5048 if (t
->opcode_modifier
.isprefix
5049 && t
->opcode_modifier
.ignoresize
)
5051 /* Warn them that a data or address size prefix doesn't
5052 affect assembly of the next line of code. */
5053 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5057 /* Copy the template we found. */
5060 if (addr_prefix_disp
!= -1)
5061 i
.tm
.operand_types
[addr_prefix_disp
]
5062 = operand_types
[addr_prefix_disp
];
5064 if (found_reverse_match
)
5066 /* If we found a reverse match we must alter the opcode
5067 direction bit. found_reverse_match holds bits to change
5068 (different for int & float insns). */
5070 i
.tm
.base_opcode
^= found_reverse_match
;
5072 i
.tm
.operand_types
[0] = operand_types
[1];
5073 i
.tm
.operand_types
[1] = operand_types
[0];
5082 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5083 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5085 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5087 as_bad (_("`%s' operand %d must use `%ses' segment"),
5093 /* There's only ever one segment override allowed per instruction.
5094 This instruction possibly has a legal segment override on the
5095 second operand, so copy the segment to where non-string
5096 instructions store it, allowing common code. */
5097 i
.seg
[0] = i
.seg
[1];
5099 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5101 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5103 as_bad (_("`%s' operand %d must use `%ses' segment"),
5114 process_suffix (void)
5116 /* If matched instruction specifies an explicit instruction mnemonic
5118 if (i
.tm
.opcode_modifier
.size16
)
5119 i
.suffix
= WORD_MNEM_SUFFIX
;
5120 else if (i
.tm
.opcode_modifier
.size32
)
5121 i
.suffix
= LONG_MNEM_SUFFIX
;
5122 else if (i
.tm
.opcode_modifier
.size64
)
5123 i
.suffix
= QWORD_MNEM_SUFFIX
;
5124 else if (i
.reg_operands
)
5126 /* If there's no instruction mnemonic suffix we try to invent one
5127 based on register operands. */
5130 /* We take i.suffix from the last register operand specified,
5131 Destination register type is more significant than source
5132 register type. crc32 in SSE4.2 prefers source register
5134 if (i
.tm
.base_opcode
== 0xf20f38f1)
5136 if (i
.types
[0].bitfield
.reg16
)
5137 i
.suffix
= WORD_MNEM_SUFFIX
;
5138 else if (i
.types
[0].bitfield
.reg32
)
5139 i
.suffix
= LONG_MNEM_SUFFIX
;
5140 else if (i
.types
[0].bitfield
.reg64
)
5141 i
.suffix
= QWORD_MNEM_SUFFIX
;
5143 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5145 if (i
.types
[0].bitfield
.reg8
)
5146 i
.suffix
= BYTE_MNEM_SUFFIX
;
5153 if (i
.tm
.base_opcode
== 0xf20f38f1
5154 || i
.tm
.base_opcode
== 0xf20f38f0)
5156 /* We have to know the operand size for crc32. */
5157 as_bad (_("ambiguous memory operand size for `%s`"),
5162 for (op
= i
.operands
; --op
>= 0;)
5163 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5165 if (i
.types
[op
].bitfield
.reg8
)
5167 i
.suffix
= BYTE_MNEM_SUFFIX
;
5170 else if (i
.types
[op
].bitfield
.reg16
)
5172 i
.suffix
= WORD_MNEM_SUFFIX
;
5175 else if (i
.types
[op
].bitfield
.reg32
)
5177 i
.suffix
= LONG_MNEM_SUFFIX
;
5180 else if (i
.types
[op
].bitfield
.reg64
)
5182 i
.suffix
= QWORD_MNEM_SUFFIX
;
5188 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5191 && i
.tm
.opcode_modifier
.ignoresize
5192 && i
.tm
.opcode_modifier
.no_bsuf
)
5194 else if (!check_byte_reg ())
5197 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5200 && i
.tm
.opcode_modifier
.ignoresize
5201 && i
.tm
.opcode_modifier
.no_lsuf
)
5203 else if (!check_long_reg ())
5206 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5209 && i
.tm
.opcode_modifier
.ignoresize
5210 && i
.tm
.opcode_modifier
.no_qsuf
)
5212 else if (!check_qword_reg ())
5215 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5218 && i
.tm
.opcode_modifier
.ignoresize
5219 && i
.tm
.opcode_modifier
.no_wsuf
)
5221 else if (!check_word_reg ())
5224 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5225 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5226 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5228 /* Skip if the instruction has x/y/z suffix. match_template
5229 should check if it is a valid suffix. */
5231 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5232 /* Do nothing if the instruction is going to ignore the prefix. */
5237 else if (i
.tm
.opcode_modifier
.defaultsize
5239 /* exclude fldenv/frstor/fsave/fstenv */
5240 && i
.tm
.opcode_modifier
.no_ssuf
)
5242 i
.suffix
= stackop_size
;
5244 else if (intel_syntax
5246 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5247 || i
.tm
.opcode_modifier
.jumpbyte
5248 || i
.tm
.opcode_modifier
.jumpintersegment
5249 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5250 && i
.tm
.extension_opcode
<= 3)))
5255 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5257 i
.suffix
= QWORD_MNEM_SUFFIX
;
5261 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5262 i
.suffix
= LONG_MNEM_SUFFIX
;
5265 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5266 i
.suffix
= WORD_MNEM_SUFFIX
;
5275 if (i
.tm
.opcode_modifier
.w
)
5277 as_bad (_("no instruction mnemonic suffix given and "
5278 "no register operands; can't size instruction"));
5284 unsigned int suffixes
;
5286 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5287 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5289 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5291 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5293 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5295 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5298 /* There are more than suffix matches. */
5299 if (i
.tm
.opcode_modifier
.w
5300 || ((suffixes
& (suffixes
- 1))
5301 && !i
.tm
.opcode_modifier
.defaultsize
5302 && !i
.tm
.opcode_modifier
.ignoresize
))
5304 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5310 /* Change the opcode based on the operand size given by i.suffix;
5311 We don't need to change things for byte insns. */
5314 && i
.suffix
!= BYTE_MNEM_SUFFIX
5315 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5316 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5317 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5319 /* It's not a byte, select word/dword operation. */
5320 if (i
.tm
.opcode_modifier
.w
)
5322 if (i
.tm
.opcode_modifier
.shortform
)
5323 i
.tm
.base_opcode
|= 8;
5325 i
.tm
.base_opcode
|= 1;
5328 /* Now select between word & dword operations via the operand
5329 size prefix, except for instructions that will ignore this
5331 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5333 /* The address size override prefix changes the size of the
5335 if ((flag_code
== CODE_32BIT
5336 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5337 || (flag_code
!= CODE_32BIT
5338 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5339 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5342 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5343 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5344 && !i
.tm
.opcode_modifier
.ignoresize
5345 && !i
.tm
.opcode_modifier
.floatmf
5346 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5347 || (flag_code
== CODE_64BIT
5348 && i
.tm
.opcode_modifier
.jumpbyte
)))
5350 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5352 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5353 prefix
= ADDR_PREFIX_OPCODE
;
5355 if (!add_prefix (prefix
))
5359 /* Set mode64 for an operand. */
5360 if (i
.suffix
== QWORD_MNEM_SUFFIX
5361 && flag_code
== CODE_64BIT
5362 && !i
.tm
.opcode_modifier
.norex64
)
5364 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5365 need rex64. cmpxchg8b is also a special case. */
5366 if (! (i
.operands
== 2
5367 && i
.tm
.base_opcode
== 0x90
5368 && i
.tm
.extension_opcode
== None
5369 && operand_type_equal (&i
.types
[0], &acc64
)
5370 && operand_type_equal (&i
.types
[1], &acc64
))
5371 && ! (i
.operands
== 1
5372 && i
.tm
.base_opcode
== 0xfc7
5373 && i
.tm
.extension_opcode
== 1
5374 && !operand_type_check (i
.types
[0], reg
)
5375 && operand_type_check (i
.types
[0], anymem
)))
5379 /* Size floating point instruction. */
5380 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5381 if (i
.tm
.opcode_modifier
.floatmf
)
5382 i
.tm
.base_opcode
^= 4;
5389 check_byte_reg (void)
5393 for (op
= i
.operands
; --op
>= 0;)
5395 /* If this is an eight bit register, it's OK. If it's the 16 or
5396 32 bit version of an eight bit register, we will just use the
5397 low portion, and that's OK too. */
5398 if (i
.types
[op
].bitfield
.reg8
)
5401 /* I/O port address operands are OK too. */
5402 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5405 /* crc32 doesn't generate this warning. */
5406 if (i
.tm
.base_opcode
== 0xf20f38f0)
5409 if ((i
.types
[op
].bitfield
.reg16
5410 || i
.types
[op
].bitfield
.reg32
5411 || i
.types
[op
].bitfield
.reg64
)
5412 && i
.op
[op
].regs
->reg_num
< 4
5413 /* Prohibit these changes in 64bit mode, since the lowering
5414 would be more complicated. */
5415 && flag_code
!= CODE_64BIT
)
5417 #if REGISTER_WARNINGS
5418 if (!quiet_warnings
)
5419 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5421 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5422 ? REGNAM_AL
- REGNAM_AX
5423 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5425 i
.op
[op
].regs
->reg_name
,
5430 /* Any other register is bad. */
5431 if (i
.types
[op
].bitfield
.reg16
5432 || i
.types
[op
].bitfield
.reg32
5433 || i
.types
[op
].bitfield
.reg64
5434 || i
.types
[op
].bitfield
.regmmx
5435 || i
.types
[op
].bitfield
.regxmm
5436 || i
.types
[op
].bitfield
.regymm
5437 || i
.types
[op
].bitfield
.regzmm
5438 || i
.types
[op
].bitfield
.sreg2
5439 || i
.types
[op
].bitfield
.sreg3
5440 || i
.types
[op
].bitfield
.control
5441 || i
.types
[op
].bitfield
.debug
5442 || i
.types
[op
].bitfield
.test
5443 || i
.types
[op
].bitfield
.floatreg
5444 || i
.types
[op
].bitfield
.floatacc
)
5446 as_bad (_("`%s%s' not allowed with `%s%c'"),
5448 i
.op
[op
].regs
->reg_name
,
5458 check_long_reg (void)
5462 for (op
= i
.operands
; --op
>= 0;)
5463 /* Reject eight bit registers, except where the template requires
5464 them. (eg. movzb) */
5465 if (i
.types
[op
].bitfield
.reg8
5466 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5467 || i
.tm
.operand_types
[op
].bitfield
.reg32
5468 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5470 as_bad (_("`%s%s' not allowed with `%s%c'"),
5472 i
.op
[op
].regs
->reg_name
,
5477 /* Warn if the e prefix on a general reg is missing. */
5478 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5479 && i
.types
[op
].bitfield
.reg16
5480 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5481 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5483 /* Prohibit these changes in the 64bit mode, since the
5484 lowering is more complicated. */
5485 if (flag_code
== CODE_64BIT
)
5487 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5488 register_prefix
, i
.op
[op
].regs
->reg_name
,
5492 #if REGISTER_WARNINGS
5493 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5495 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5496 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5499 /* Warn if the r prefix on a general reg is present. */
5500 else if (i
.types
[op
].bitfield
.reg64
5501 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5502 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5505 && i
.tm
.opcode_modifier
.toqword
5506 && !i
.types
[0].bitfield
.regxmm
)
5508 /* Convert to QWORD. We want REX byte. */
5509 i
.suffix
= QWORD_MNEM_SUFFIX
;
5513 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5514 register_prefix
, i
.op
[op
].regs
->reg_name
,
5523 check_qword_reg (void)
5527 for (op
= i
.operands
; --op
>= 0; )
5528 /* Reject eight bit registers, except where the template requires
5529 them. (eg. movzb) */
5530 if (i
.types
[op
].bitfield
.reg8
5531 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5532 || i
.tm
.operand_types
[op
].bitfield
.reg32
5533 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5535 as_bad (_("`%s%s' not allowed with `%s%c'"),
5537 i
.op
[op
].regs
->reg_name
,
5542 /* Warn if the r prefix on a general reg is missing. */
5543 else if ((i
.types
[op
].bitfield
.reg16
5544 || i
.types
[op
].bitfield
.reg32
)
5545 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5546 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5548 /* Prohibit these changes in the 64bit mode, since the
5549 lowering is more complicated. */
5551 && i
.tm
.opcode_modifier
.todword
5552 && !i
.types
[0].bitfield
.regxmm
)
5554 /* Convert to DWORD. We don't want REX byte. */
5555 i
.suffix
= LONG_MNEM_SUFFIX
;
5559 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5560 register_prefix
, i
.op
[op
].regs
->reg_name
,
5569 check_word_reg (void)
5572 for (op
= i
.operands
; --op
>= 0;)
5573 /* Reject eight bit registers, except where the template requires
5574 them. (eg. movzb) */
5575 if (i
.types
[op
].bitfield
.reg8
5576 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5577 || i
.tm
.operand_types
[op
].bitfield
.reg32
5578 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5580 as_bad (_("`%s%s' not allowed with `%s%c'"),
5582 i
.op
[op
].regs
->reg_name
,
5587 /* Warn if the e or r prefix on a general reg is present. */
5588 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5589 && (i
.types
[op
].bitfield
.reg32
5590 || i
.types
[op
].bitfield
.reg64
)
5591 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5592 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5594 /* Prohibit these changes in the 64bit mode, since the
5595 lowering is more complicated. */
5596 if (flag_code
== CODE_64BIT
)
5598 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5599 register_prefix
, i
.op
[op
].regs
->reg_name
,
5603 #if REGISTER_WARNINGS
5604 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5606 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5607 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5614 update_imm (unsigned int j
)
5616 i386_operand_type overlap
= i
.types
[j
];
5617 if ((overlap
.bitfield
.imm8
5618 || overlap
.bitfield
.imm8s
5619 || overlap
.bitfield
.imm16
5620 || overlap
.bitfield
.imm32
5621 || overlap
.bitfield
.imm32s
5622 || overlap
.bitfield
.imm64
)
5623 && !operand_type_equal (&overlap
, &imm8
)
5624 && !operand_type_equal (&overlap
, &imm8s
)
5625 && !operand_type_equal (&overlap
, &imm16
)
5626 && !operand_type_equal (&overlap
, &imm32
)
5627 && !operand_type_equal (&overlap
, &imm32s
)
5628 && !operand_type_equal (&overlap
, &imm64
))
5632 i386_operand_type temp
;
5634 operand_type_set (&temp
, 0);
5635 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5637 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5638 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5640 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5641 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5642 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5644 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5645 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5648 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5651 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5652 || operand_type_equal (&overlap
, &imm16_32
)
5653 || operand_type_equal (&overlap
, &imm16_32s
))
5655 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5660 if (!operand_type_equal (&overlap
, &imm8
)
5661 && !operand_type_equal (&overlap
, &imm8s
)
5662 && !operand_type_equal (&overlap
, &imm16
)
5663 && !operand_type_equal (&overlap
, &imm32
)
5664 && !operand_type_equal (&overlap
, &imm32s
)
5665 && !operand_type_equal (&overlap
, &imm64
))
5667 as_bad (_("no instruction mnemonic suffix given; "
5668 "can't determine immediate size"));
5672 i
.types
[j
] = overlap
;
5682 /* Update the first 2 immediate operands. */
5683 n
= i
.operands
> 2 ? 2 : i
.operands
;
5686 for (j
= 0; j
< n
; j
++)
5687 if (update_imm (j
) == 0)
5690 /* The 3rd operand can't be immediate operand. */
5691 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5698 bad_implicit_operand (int xmm
)
5700 const char *ireg
= xmm
? "xmm0" : "ymm0";
5703 as_bad (_("the last operand of `%s' must be `%s%s'"),
5704 i
.tm
.name
, register_prefix
, ireg
);
5706 as_bad (_("the first operand of `%s' must be `%s%s'"),
5707 i
.tm
.name
, register_prefix
, ireg
);
5712 process_operands (void)
5714 /* Default segment register this instruction will use for memory
5715 accesses. 0 means unknown. This is only for optimizing out
5716 unnecessary segment overrides. */
5717 const seg_entry
*default_seg
= 0;
5719 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5721 unsigned int dupl
= i
.operands
;
5722 unsigned int dest
= dupl
- 1;
5725 /* The destination must be an xmm register. */
5726 gas_assert (i
.reg_operands
5727 && MAX_OPERANDS
> dupl
5728 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5730 if (i
.tm
.opcode_modifier
.firstxmm0
)
5732 /* The first operand is implicit and must be xmm0. */
5733 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5734 if (register_number (i
.op
[0].regs
) != 0)
5735 return bad_implicit_operand (1);
5737 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5739 /* Keep xmm0 for instructions with VEX prefix and 3
5745 /* We remove the first xmm0 and keep the number of
5746 operands unchanged, which in fact duplicates the
5748 for (j
= 1; j
< i
.operands
; j
++)
5750 i
.op
[j
- 1] = i
.op
[j
];
5751 i
.types
[j
- 1] = i
.types
[j
];
5752 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5756 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5758 gas_assert ((MAX_OPERANDS
- 1) > dupl
5759 && (i
.tm
.opcode_modifier
.vexsources
5762 /* Add the implicit xmm0 for instructions with VEX prefix
5764 for (j
= i
.operands
; j
> 0; j
--)
5766 i
.op
[j
] = i
.op
[j
- 1];
5767 i
.types
[j
] = i
.types
[j
- 1];
5768 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5771 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5772 i
.types
[0] = regxmm
;
5773 i
.tm
.operand_types
[0] = regxmm
;
5776 i
.reg_operands
+= 2;
5781 i
.op
[dupl
] = i
.op
[dest
];
5782 i
.types
[dupl
] = i
.types
[dest
];
5783 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5792 i
.op
[dupl
] = i
.op
[dest
];
5793 i
.types
[dupl
] = i
.types
[dest
];
5794 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5797 if (i
.tm
.opcode_modifier
.immext
)
5800 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5804 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5805 gas_assert (i
.reg_operands
5806 && (operand_type_equal (&i
.types
[0], ®xmm
)
5807 || operand_type_equal (&i
.types
[0], ®ymm
)
5808 || operand_type_equal (&i
.types
[0], ®zmm
)));
5809 if (register_number (i
.op
[0].regs
) != 0)
5810 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5812 for (j
= 1; j
< i
.operands
; j
++)
5814 i
.op
[j
- 1] = i
.op
[j
];
5815 i
.types
[j
- 1] = i
.types
[j
];
5817 /* We need to adjust fields in i.tm since they are used by
5818 build_modrm_byte. */
5819 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5826 else if (i
.tm
.opcode_modifier
.regkludge
)
5828 /* The imul $imm, %reg instruction is converted into
5829 imul $imm, %reg, %reg, and the clr %reg instruction
5830 is converted into xor %reg, %reg. */
5832 unsigned int first_reg_op
;
5834 if (operand_type_check (i
.types
[0], reg
))
5838 /* Pretend we saw the extra register operand. */
5839 gas_assert (i
.reg_operands
== 1
5840 && i
.op
[first_reg_op
+ 1].regs
== 0);
5841 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5842 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5847 if (i
.tm
.opcode_modifier
.shortform
)
5849 if (i
.types
[0].bitfield
.sreg2
5850 || i
.types
[0].bitfield
.sreg3
)
5852 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5853 && i
.op
[0].regs
->reg_num
== 1)
5855 as_bad (_("you can't `pop %scs'"), register_prefix
);
5858 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5859 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5864 /* The register or float register operand is in operand
5868 if (i
.types
[0].bitfield
.floatreg
5869 || operand_type_check (i
.types
[0], reg
))
5873 /* Register goes in low 3 bits of opcode. */
5874 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5875 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5877 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5879 /* Warn about some common errors, but press on regardless.
5880 The first case can be generated by gcc (<= 2.8.1). */
5881 if (i
.operands
== 2)
5883 /* Reversed arguments on faddp, fsubp, etc. */
5884 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5885 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5886 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5890 /* Extraneous `l' suffix on fp insn. */
5891 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5892 register_prefix
, i
.op
[0].regs
->reg_name
);
5897 else if (i
.tm
.opcode_modifier
.modrm
)
5899 /* The opcode is completed (modulo i.tm.extension_opcode which
5900 must be put into the modrm byte). Now, we make the modrm and
5901 index base bytes based on all the info we've collected. */
5903 default_seg
= build_modrm_byte ();
5905 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5909 else if (i
.tm
.opcode_modifier
.isstring
)
5911 /* For the string instructions that allow a segment override
5912 on one of their operands, the default segment is ds. */
5916 if (i
.tm
.base_opcode
== 0x8d /* lea */
5919 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5921 /* If a segment was explicitly specified, and the specified segment
5922 is not the default, use an opcode prefix to select it. If we
5923 never figured out what the default segment is, then default_seg
5924 will be zero at this point, and the specified segment prefix will
5926 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5928 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5934 static const seg_entry
*
5935 build_modrm_byte (void)
5937 const seg_entry
*default_seg
= 0;
5938 unsigned int source
, dest
;
5941 /* The first operand of instructions with VEX prefix and 3 sources
5942 must be VEX_Imm4. */
5943 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5946 unsigned int nds
, reg_slot
;
5949 if (i
.tm
.opcode_modifier
.veximmext
5950 && i
.tm
.opcode_modifier
.immext
)
5952 dest
= i
.operands
- 2;
5953 gas_assert (dest
== 3);
5956 dest
= i
.operands
- 1;
5959 /* There are 2 kinds of instructions:
5960 1. 5 operands: 4 register operands or 3 register operands
5961 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5962 VexW0 or VexW1. The destination must be either XMM, YMM or
5964 2. 4 operands: 4 register operands or 3 register operands
5965 plus 1 memory operand, VexXDS, and VexImmExt */
5966 gas_assert ((i
.reg_operands
== 4
5967 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5968 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5969 && (i
.tm
.opcode_modifier
.veximmext
5970 || (i
.imm_operands
== 1
5971 && i
.types
[0].bitfield
.vec_imm4
5972 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5973 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5974 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5975 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5976 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5978 if (i
.imm_operands
== 0)
5980 /* When there is no immediate operand, generate an 8bit
5981 immediate operand to encode the first operand. */
5982 exp
= &im_expressions
[i
.imm_operands
++];
5983 i
.op
[i
.operands
].imms
= exp
;
5984 i
.types
[i
.operands
] = imm8
;
5986 /* If VexW1 is set, the first operand is the source and
5987 the second operand is encoded in the immediate operand. */
5988 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5999 /* FMA swaps REG and NDS. */
6000 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6008 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6010 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6012 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6014 exp
->X_op
= O_constant
;
6015 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6016 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6020 unsigned int imm_slot
;
6022 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6024 /* If VexW0 is set, the third operand is the source and
6025 the second operand is encoded in the immediate
6032 /* VexW1 is set, the second operand is the source and
6033 the third operand is encoded in the immediate
6039 if (i
.tm
.opcode_modifier
.immext
)
6041 /* When ImmExt is set, the immdiate byte is the last
6043 imm_slot
= i
.operands
- 1;
6051 /* Turn on Imm8 so that output_imm will generate it. */
6052 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6055 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6057 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6059 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6061 i
.op
[imm_slot
].imms
->X_add_number
6062 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6063 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6066 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6067 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6069 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6071 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6076 /* i.reg_operands MUST be the number of real register operands;
6077 implicit registers do not count. If there are 3 register
6078 operands, it must be a instruction with VexNDS. For a
6079 instruction with VexNDD, the destination register is encoded
6080 in VEX prefix. If there are 4 register operands, it must be
6081 a instruction with VEX prefix and 3 sources. */
6082 if (i
.mem_operands
== 0
6083 && ((i
.reg_operands
== 2
6084 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6085 || (i
.reg_operands
== 3
6086 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6087 || (i
.reg_operands
== 4 && vex_3_sources
)))
6095 /* When there are 3 operands, one of them may be immediate,
6096 which may be the first or the last operand. Otherwise,
6097 the first operand must be shift count register (cl) or it
6098 is an instruction with VexNDS. */
6099 gas_assert (i
.imm_operands
== 1
6100 || (i
.imm_operands
== 0
6101 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6102 || i
.types
[0].bitfield
.shiftcount
)));
6103 if (operand_type_check (i
.types
[0], imm
)
6104 || i
.types
[0].bitfield
.shiftcount
)
6110 /* When there are 4 operands, the first two must be 8bit
6111 immediate operands. The source operand will be the 3rd
6114 For instructions with VexNDS, if the first operand
6115 an imm8, the source operand is the 2nd one. If the last
6116 operand is imm8, the source operand is the first one. */
6117 gas_assert ((i
.imm_operands
== 2
6118 && i
.types
[0].bitfield
.imm8
6119 && i
.types
[1].bitfield
.imm8
)
6120 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6121 && i
.imm_operands
== 1
6122 && (i
.types
[0].bitfield
.imm8
6123 || i
.types
[i
.operands
- 1].bitfield
.imm8
6125 if (i
.imm_operands
== 2)
6129 if (i
.types
[0].bitfield
.imm8
)
6136 if (i
.tm
.opcode_modifier
.evex
)
6138 /* For EVEX instructions, when there are 5 operands, the
6139 first one must be immediate operand. If the second one
6140 is immediate operand, the source operand is the 3th
6141 one. If the last one is immediate operand, the source
6142 operand is the 2nd one. */
6143 gas_assert (i
.imm_operands
== 2
6144 && i
.tm
.opcode_modifier
.sae
6145 && operand_type_check (i
.types
[0], imm
));
6146 if (operand_type_check (i
.types
[1], imm
))
6148 else if (operand_type_check (i
.types
[4], imm
))
6162 /* RC/SAE operand could be between DEST and SRC. That happens
6163 when one operand is GPR and the other one is XMM/YMM/ZMM
6165 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6168 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6170 /* For instructions with VexNDS, the register-only source
6171 operand must be 32/64bit integer, XMM, YMM or ZMM
6172 register. It is encoded in VEX prefix. We need to
6173 clear RegMem bit before calling operand_type_equal. */
6175 i386_operand_type op
;
6178 /* Check register-only source operand when two source
6179 operands are swapped. */
6180 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6181 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6189 op
= i
.tm
.operand_types
[vvvv
];
6190 op
.bitfield
.regmem
= 0;
6191 if ((dest
+ 1) >= i
.operands
6192 || (!op
.bitfield
.reg32
6193 && op
.bitfield
.reg64
6194 && !operand_type_equal (&op
, ®xmm
)
6195 && !operand_type_equal (&op
, ®ymm
)
6196 && !operand_type_equal (&op
, ®zmm
)
6197 && !operand_type_equal (&op
, ®mask
)))
6199 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6205 /* One of the register operands will be encoded in the i.tm.reg
6206 field, the other in the combined i.tm.mode and i.tm.regmem
6207 fields. If no form of this instruction supports a memory
6208 destination operand, then we assume the source operand may
6209 sometimes be a memory operand and so we need to store the
6210 destination in the i.rm.reg field. */
6211 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6212 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6214 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6215 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6216 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6218 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6220 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6222 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6227 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6228 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6229 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6231 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6233 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6235 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6238 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6240 if (!i
.types
[0].bitfield
.control
6241 && !i
.types
[1].bitfield
.control
)
6243 i
.rex
&= ~(REX_R
| REX_B
);
6244 add_prefix (LOCK_PREFIX_OPCODE
);
6248 { /* If it's not 2 reg operands... */
6253 unsigned int fake_zero_displacement
= 0;
6256 for (op
= 0; op
< i
.operands
; op
++)
6257 if (operand_type_check (i
.types
[op
], anymem
))
6259 gas_assert (op
< i
.operands
);
6261 if (i
.tm
.opcode_modifier
.vecsib
)
6263 if (i
.index_reg
->reg_num
== RegEiz
6264 || i
.index_reg
->reg_num
== RegRiz
)
6267 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6270 i
.sib
.base
= NO_BASE_REGISTER
;
6271 i
.sib
.scale
= i
.log2_scale_factor
;
6272 /* No Vec_Disp8 if there is no base. */
6273 i
.types
[op
].bitfield
.vec_disp8
= 0;
6274 i
.types
[op
].bitfield
.disp8
= 0;
6275 i
.types
[op
].bitfield
.disp16
= 0;
6276 i
.types
[op
].bitfield
.disp64
= 0;
6277 if (flag_code
!= CODE_64BIT
)
6279 /* Must be 32 bit */
6280 i
.types
[op
].bitfield
.disp32
= 1;
6281 i
.types
[op
].bitfield
.disp32s
= 0;
6285 i
.types
[op
].bitfield
.disp32
= 0;
6286 i
.types
[op
].bitfield
.disp32s
= 1;
6289 i
.sib
.index
= i
.index_reg
->reg_num
;
6290 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6292 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6298 if (i
.base_reg
== 0)
6301 if (!i
.disp_operands
)
6303 fake_zero_displacement
= 1;
6304 /* Instructions with VSIB byte need 32bit displacement
6305 if there is no base register. */
6306 if (i
.tm
.opcode_modifier
.vecsib
)
6307 i
.types
[op
].bitfield
.disp32
= 1;
6309 if (i
.index_reg
== 0)
6311 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6312 /* Operand is just <disp> */
6313 if (flag_code
== CODE_64BIT
)
6315 /* 64bit mode overwrites the 32bit absolute
6316 addressing by RIP relative addressing and
6317 absolute addressing is encoded by one of the
6318 redundant SIB forms. */
6319 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6320 i
.sib
.base
= NO_BASE_REGISTER
;
6321 i
.sib
.index
= NO_INDEX_REGISTER
;
6322 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6323 ? disp32s
: disp32
);
6325 else if ((flag_code
== CODE_16BIT
)
6326 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6328 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6329 i
.types
[op
] = disp16
;
6333 i
.rm
.regmem
= NO_BASE_REGISTER
;
6334 i
.types
[op
] = disp32
;
6337 else if (!i
.tm
.opcode_modifier
.vecsib
)
6339 /* !i.base_reg && i.index_reg */
6340 if (i
.index_reg
->reg_num
== RegEiz
6341 || i
.index_reg
->reg_num
== RegRiz
)
6342 i
.sib
.index
= NO_INDEX_REGISTER
;
6344 i
.sib
.index
= i
.index_reg
->reg_num
;
6345 i
.sib
.base
= NO_BASE_REGISTER
;
6346 i
.sib
.scale
= i
.log2_scale_factor
;
6347 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6348 /* No Vec_Disp8 if there is no base. */
6349 i
.types
[op
].bitfield
.vec_disp8
= 0;
6350 i
.types
[op
].bitfield
.disp8
= 0;
6351 i
.types
[op
].bitfield
.disp16
= 0;
6352 i
.types
[op
].bitfield
.disp64
= 0;
6353 if (flag_code
!= CODE_64BIT
)
6355 /* Must be 32 bit */
6356 i
.types
[op
].bitfield
.disp32
= 1;
6357 i
.types
[op
].bitfield
.disp32s
= 0;
6361 i
.types
[op
].bitfield
.disp32
= 0;
6362 i
.types
[op
].bitfield
.disp32s
= 1;
6364 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6368 /* RIP addressing for 64bit mode. */
6369 else if (i
.base_reg
->reg_num
== RegRip
||
6370 i
.base_reg
->reg_num
== RegEip
)
6372 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6373 i
.rm
.regmem
= NO_BASE_REGISTER
;
6374 i
.types
[op
].bitfield
.disp8
= 0;
6375 i
.types
[op
].bitfield
.disp16
= 0;
6376 i
.types
[op
].bitfield
.disp32
= 0;
6377 i
.types
[op
].bitfield
.disp32s
= 1;
6378 i
.types
[op
].bitfield
.disp64
= 0;
6379 i
.types
[op
].bitfield
.vec_disp8
= 0;
6380 i
.flags
[op
] |= Operand_PCrel
;
6381 if (! i
.disp_operands
)
6382 fake_zero_displacement
= 1;
6384 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6386 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6387 switch (i
.base_reg
->reg_num
)
6390 if (i
.index_reg
== 0)
6392 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6393 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6397 if (i
.index_reg
== 0)
6400 if (operand_type_check (i
.types
[op
], disp
) == 0)
6402 /* fake (%bp) into 0(%bp) */
6403 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6404 i
.types
[op
].bitfield
.vec_disp8
= 1;
6406 i
.types
[op
].bitfield
.disp8
= 1;
6407 fake_zero_displacement
= 1;
6410 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6411 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6413 default: /* (%si) -> 4 or (%di) -> 5 */
6414 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6416 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6418 else /* i.base_reg and 32/64 bit mode */
6420 if (flag_code
== CODE_64BIT
6421 && operand_type_check (i
.types
[op
], disp
))
6423 i386_operand_type temp
;
6424 operand_type_set (&temp
, 0);
6425 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6426 temp
.bitfield
.vec_disp8
6427 = i
.types
[op
].bitfield
.vec_disp8
;
6429 if (i
.prefix
[ADDR_PREFIX
] == 0)
6430 i
.types
[op
].bitfield
.disp32s
= 1;
6432 i
.types
[op
].bitfield
.disp32
= 1;
6435 if (!i
.tm
.opcode_modifier
.vecsib
)
6436 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6437 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6439 i
.sib
.base
= i
.base_reg
->reg_num
;
6440 /* x86-64 ignores REX prefix bit here to avoid decoder
6442 if (!(i
.base_reg
->reg_flags
& RegRex
)
6443 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6444 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6446 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6448 fake_zero_displacement
= 1;
6449 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6450 i
.types
[op
].bitfield
.vec_disp8
= 1;
6452 i
.types
[op
].bitfield
.disp8
= 1;
6454 i
.sib
.scale
= i
.log2_scale_factor
;
6455 if (i
.index_reg
== 0)
6457 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6458 /* <disp>(%esp) becomes two byte modrm with no index
6459 register. We've already stored the code for esp
6460 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6461 Any base register besides %esp will not use the
6462 extra modrm byte. */
6463 i
.sib
.index
= NO_INDEX_REGISTER
;
6465 else if (!i
.tm
.opcode_modifier
.vecsib
)
6467 if (i
.index_reg
->reg_num
== RegEiz
6468 || i
.index_reg
->reg_num
== RegRiz
)
6469 i
.sib
.index
= NO_INDEX_REGISTER
;
6471 i
.sib
.index
= i
.index_reg
->reg_num
;
6472 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6473 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6478 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6479 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6483 if (!fake_zero_displacement
6487 fake_zero_displacement
= 1;
6488 if (i
.disp_encoding
== disp_encoding_8bit
)
6489 i
.types
[op
].bitfield
.disp8
= 1;
6491 i
.types
[op
].bitfield
.disp32
= 1;
6493 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6497 if (fake_zero_displacement
)
6499 /* Fakes a zero displacement assuming that i.types[op]
6500 holds the correct displacement size. */
6503 gas_assert (i
.op
[op
].disps
== 0);
6504 exp
= &disp_expressions
[i
.disp_operands
++];
6505 i
.op
[op
].disps
= exp
;
6506 exp
->X_op
= O_constant
;
6507 exp
->X_add_number
= 0;
6508 exp
->X_add_symbol
= (symbolS
*) 0;
6509 exp
->X_op_symbol
= (symbolS
*) 0;
6517 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6519 if (operand_type_check (i
.types
[0], imm
))
6520 i
.vex
.register_specifier
= NULL
;
6523 /* VEX.vvvv encodes one of the sources when the first
6524 operand is not an immediate. */
6525 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6526 i
.vex
.register_specifier
= i
.op
[0].regs
;
6528 i
.vex
.register_specifier
= i
.op
[1].regs
;
6531 /* Destination is a XMM register encoded in the ModRM.reg
6533 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6534 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6537 /* ModRM.rm and VEX.B encodes the other source. */
6538 if (!i
.mem_operands
)
6542 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6543 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6545 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6547 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6551 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6553 i
.vex
.register_specifier
= i
.op
[2].regs
;
6554 if (!i
.mem_operands
)
6557 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6558 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6562 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6563 (if any) based on i.tm.extension_opcode. Again, we must be
6564 careful to make sure that segment/control/debug/test/MMX
6565 registers are coded into the i.rm.reg field. */
6566 else if (i
.reg_operands
)
6569 unsigned int vex_reg
= ~0;
6571 for (op
= 0; op
< i
.operands
; op
++)
6572 if (i
.types
[op
].bitfield
.reg8
6573 || i
.types
[op
].bitfield
.reg16
6574 || i
.types
[op
].bitfield
.reg32
6575 || i
.types
[op
].bitfield
.reg64
6576 || i
.types
[op
].bitfield
.regmmx
6577 || i
.types
[op
].bitfield
.regxmm
6578 || i
.types
[op
].bitfield
.regymm
6579 || i
.types
[op
].bitfield
.regbnd
6580 || i
.types
[op
].bitfield
.regzmm
6581 || i
.types
[op
].bitfield
.regmask
6582 || i
.types
[op
].bitfield
.sreg2
6583 || i
.types
[op
].bitfield
.sreg3
6584 || i
.types
[op
].bitfield
.control
6585 || i
.types
[op
].bitfield
.debug
6586 || i
.types
[op
].bitfield
.test
)
6591 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6593 /* For instructions with VexNDS, the register-only
6594 source operand is encoded in VEX prefix. */
6595 gas_assert (mem
!= (unsigned int) ~0);
6600 gas_assert (op
< i
.operands
);
6604 /* Check register-only source operand when two source
6605 operands are swapped. */
6606 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6607 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6611 gas_assert (mem
== (vex_reg
+ 1)
6612 && op
< i
.operands
);
6617 gas_assert (vex_reg
< i
.operands
);
6621 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6623 /* For instructions with VexNDD, the register destination
6624 is encoded in VEX prefix. */
6625 if (i
.mem_operands
== 0)
6627 /* There is no memory operand. */
6628 gas_assert ((op
+ 2) == i
.operands
);
6633 /* There are only 2 operands. */
6634 gas_assert (op
< 2 && i
.operands
== 2);
6639 gas_assert (op
< i
.operands
);
6641 if (vex_reg
!= (unsigned int) ~0)
6643 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6645 if (type
->bitfield
.reg32
!= 1
6646 && type
->bitfield
.reg64
!= 1
6647 && !operand_type_equal (type
, ®xmm
)
6648 && !operand_type_equal (type
, ®ymm
)
6649 && !operand_type_equal (type
, ®zmm
)
6650 && !operand_type_equal (type
, ®mask
))
6653 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6656 /* Don't set OP operand twice. */
6659 /* If there is an extension opcode to put here, the
6660 register number must be put into the regmem field. */
6661 if (i
.tm
.extension_opcode
!= None
)
6663 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6664 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6666 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6671 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6672 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6674 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6679 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6680 must set it to 3 to indicate this is a register operand
6681 in the regmem field. */
6682 if (!i
.mem_operands
)
6686 /* Fill in i.rm.reg field with extension opcode (if any). */
6687 if (i
.tm
.extension_opcode
!= None
)
6688 i
.rm
.reg
= i
.tm
.extension_opcode
;
6694 output_branch (void)
6700 relax_substateT subtype
;
6704 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6705 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6708 if (i
.prefix
[DATA_PREFIX
] != 0)
6714 /* Pentium4 branch hints. */
6715 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6716 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6721 if (i
.prefix
[REX_PREFIX
] != 0)
6727 /* BND prefixed jump. */
6728 if (i
.prefix
[BND_PREFIX
] != 0)
6730 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6734 if (i
.prefixes
!= 0 && !intel_syntax
)
6735 as_warn (_("skipping prefixes on this instruction"));
6737 /* It's always a symbol; End frag & setup for relax.
6738 Make sure there is enough room in this frag for the largest
6739 instruction we may generate in md_convert_frag. This is 2
6740 bytes for the opcode and room for the prefix and largest
6742 frag_grow (prefix
+ 2 + 4);
6743 /* Prefix and 1 opcode byte go in fr_fix. */
6744 p
= frag_more (prefix
+ 1);
6745 if (i
.prefix
[DATA_PREFIX
] != 0)
6746 *p
++ = DATA_PREFIX_OPCODE
;
6747 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6748 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6749 *p
++ = i
.prefix
[SEG_PREFIX
];
6750 if (i
.prefix
[REX_PREFIX
] != 0)
6751 *p
++ = i
.prefix
[REX_PREFIX
];
6752 *p
= i
.tm
.base_opcode
;
6754 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6755 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6756 else if (cpu_arch_flags
.bitfield
.cpui386
)
6757 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6759 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6762 sym
= i
.op
[0].disps
->X_add_symbol
;
6763 off
= i
.op
[0].disps
->X_add_number
;
6765 if (i
.op
[0].disps
->X_op
!= O_constant
6766 && i
.op
[0].disps
->X_op
!= O_symbol
)
6768 /* Handle complex expressions. */
6769 sym
= make_expr_symbol (i
.op
[0].disps
);
6773 /* 1 possible extra opcode + 4 byte displacement go in var part.
6774 Pass reloc in fr_var. */
6775 frag_var (rs_machine_dependent
, 5,
6777 || i
.reloc
[0] != NO_RELOC
6778 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6780 : BFD_RELOC_X86_64_PC32_BND
),
6781 subtype
, sym
, off
, p
);
6791 if (i
.tm
.opcode_modifier
.jumpbyte
)
6793 /* This is a loop or jecxz type instruction. */
6795 if (i
.prefix
[ADDR_PREFIX
] != 0)
6797 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6800 /* Pentium4 branch hints. */
6801 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6802 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6804 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6813 if (flag_code
== CODE_16BIT
)
6816 if (i
.prefix
[DATA_PREFIX
] != 0)
6818 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6828 if (i
.prefix
[REX_PREFIX
] != 0)
6830 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6834 /* BND prefixed jump. */
6835 if (i
.prefix
[BND_PREFIX
] != 0)
6837 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6841 if (i
.prefixes
!= 0 && !intel_syntax
)
6842 as_warn (_("skipping prefixes on this instruction"));
6844 p
= frag_more (i
.tm
.opcode_length
+ size
);
6845 switch (i
.tm
.opcode_length
)
6848 *p
++ = i
.tm
.base_opcode
>> 8;
6850 *p
++ = i
.tm
.base_opcode
;
6856 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6857 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6858 (i
.bnd_prefix
!= NULL
6862 /* All jumps handled here are signed, but don't use a signed limit
6863 check for 32 and 16 bit jumps as we want to allow wrap around at
6864 4G and 64k respectively. */
6866 fixP
->fx_signed
= 1;
6870 output_interseg_jump (void)
6878 if (flag_code
== CODE_16BIT
)
6882 if (i
.prefix
[DATA_PREFIX
] != 0)
6888 if (i
.prefix
[REX_PREFIX
] != 0)
6898 if (i
.prefixes
!= 0 && !intel_syntax
)
6899 as_warn (_("skipping prefixes on this instruction"));
6901 /* 1 opcode; 2 segment; offset */
6902 p
= frag_more (prefix
+ 1 + 2 + size
);
6904 if (i
.prefix
[DATA_PREFIX
] != 0)
6905 *p
++ = DATA_PREFIX_OPCODE
;
6907 if (i
.prefix
[REX_PREFIX
] != 0)
6908 *p
++ = i
.prefix
[REX_PREFIX
];
6910 *p
++ = i
.tm
.base_opcode
;
6911 if (i
.op
[1].imms
->X_op
== O_constant
)
6913 offsetT n
= i
.op
[1].imms
->X_add_number
;
6916 && !fits_in_unsigned_word (n
)
6917 && !fits_in_signed_word (n
))
6919 as_bad (_("16-bit jump out of range"));
6922 md_number_to_chars (p
, n
, size
);
6925 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6926 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6927 if (i
.op
[0].imms
->X_op
!= O_constant
)
6928 as_bad (_("can't handle non absolute segment in `%s'"),
6930 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6936 fragS
*insn_start_frag
;
6937 offsetT insn_start_off
;
6939 /* Tie dwarf2 debug info to the address at the start of the insn.
6940 We can't do this after the insn has been output as the current
6941 frag may have been closed off. eg. by frag_var. */
6942 dwarf2_emit_insn (0);
6944 insn_start_frag
= frag_now
;
6945 insn_start_off
= frag_now_fix ();
6948 if (i
.tm
.opcode_modifier
.jump
)
6950 else if (i
.tm
.opcode_modifier
.jumpbyte
6951 || i
.tm
.opcode_modifier
.jumpdword
)
6953 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6954 output_interseg_jump ();
6957 /* Output normal instructions here. */
6961 unsigned int prefix
;
6963 /* Some processors fail on LOCK prefix. This options makes
6964 assembler ignore LOCK prefix and serves as a workaround. */
6965 if (omit_lock_prefix
)
6967 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6969 i
.prefix
[LOCK_PREFIX
] = 0;
6972 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6973 don't need the explicit prefix. */
6974 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6976 switch (i
.tm
.opcode_length
)
6979 if (i
.tm
.base_opcode
& 0xff000000)
6981 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6986 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6988 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6989 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6992 if (prefix
!= REPE_PREFIX_OPCODE
6993 || (i
.prefix
[REP_PREFIX
]
6994 != REPE_PREFIX_OPCODE
))
6995 add_prefix (prefix
);
6998 add_prefix (prefix
);
7007 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7008 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7009 R_X86_64_GOTTPOFF relocation so that linker can safely
7010 perform IE->LE optimization. */
7011 if (x86_elf_abi
== X86_64_X32_ABI
7013 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7014 && i
.prefix
[REX_PREFIX
] == 0)
7015 add_prefix (REX_OPCODE
);
7018 /* The prefix bytes. */
7019 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7021 FRAG_APPEND_1_CHAR (*q
);
7025 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7030 /* REX byte is encoded in VEX prefix. */
7034 FRAG_APPEND_1_CHAR (*q
);
7037 /* There should be no other prefixes for instructions
7042 /* For EVEX instructions i.vrex should become 0 after
7043 build_evex_prefix. For VEX instructions upper 16 registers
7044 aren't available, so VREX should be 0. */
7047 /* Now the VEX prefix. */
7048 p
= frag_more (i
.vex
.length
);
7049 for (j
= 0; j
< i
.vex
.length
; j
++)
7050 p
[j
] = i
.vex
.bytes
[j
];
7053 /* Now the opcode; be careful about word order here! */
7054 if (i
.tm
.opcode_length
== 1)
7056 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7060 switch (i
.tm
.opcode_length
)
7064 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7065 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7069 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7079 /* Put out high byte first: can't use md_number_to_chars! */
7080 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7081 *p
= i
.tm
.base_opcode
& 0xff;
7084 /* Now the modrm byte and sib byte (if present). */
7085 if (i
.tm
.opcode_modifier
.modrm
)
7087 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7090 /* If i.rm.regmem == ESP (4)
7091 && i.rm.mode != (Register mode)
7093 ==> need second modrm byte. */
7094 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7096 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7097 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7099 | i
.sib
.scale
<< 6));
7102 if (i
.disp_operands
)
7103 output_disp (insn_start_frag
, insn_start_off
);
7106 output_imm (insn_start_frag
, insn_start_off
);
7112 pi ("" /*line*/, &i
);
7114 #endif /* DEBUG386 */
7117 /* Return the size of the displacement operand N. */
7120 disp_size (unsigned int n
)
7124 /* Vec_Disp8 has to be 8bit. */
7125 if (i
.types
[n
].bitfield
.vec_disp8
)
7127 else if (i
.types
[n
].bitfield
.disp64
)
7129 else if (i
.types
[n
].bitfield
.disp8
)
7131 else if (i
.types
[n
].bitfield
.disp16
)
7136 /* Return the size of the immediate operand N. */
7139 imm_size (unsigned int n
)
7142 if (i
.types
[n
].bitfield
.imm64
)
7144 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7146 else if (i
.types
[n
].bitfield
.imm16
)
7152 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7157 for (n
= 0; n
< i
.operands
; n
++)
7159 if (i
.types
[n
].bitfield
.vec_disp8
7160 || operand_type_check (i
.types
[n
], disp
))
7162 if (i
.op
[n
].disps
->X_op
== O_constant
)
7164 int size
= disp_size (n
);
7165 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7167 if (i
.types
[n
].bitfield
.vec_disp8
)
7169 val
= offset_in_range (val
, size
);
7170 p
= frag_more (size
);
7171 md_number_to_chars (p
, val
, size
);
7175 enum bfd_reloc_code_real reloc_type
;
7176 int size
= disp_size (n
);
7177 int sign
= i
.types
[n
].bitfield
.disp32s
;
7178 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7180 /* We can't have 8 bit displacement here. */
7181 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7183 /* The PC relative address is computed relative
7184 to the instruction boundary, so in case immediate
7185 fields follows, we need to adjust the value. */
7186 if (pcrel
&& i
.imm_operands
)
7191 for (n1
= 0; n1
< i
.operands
; n1
++)
7192 if (operand_type_check (i
.types
[n1
], imm
))
7194 /* Only one immediate is allowed for PC
7195 relative address. */
7196 gas_assert (sz
== 0);
7198 i
.op
[n
].disps
->X_add_number
-= sz
;
7200 /* We should find the immediate. */
7201 gas_assert (sz
!= 0);
7204 p
= frag_more (size
);
7205 reloc_type
= reloc (size
, pcrel
, sign
,
7206 (i
.bnd_prefix
!= NULL
7210 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7211 && (((reloc_type
== BFD_RELOC_32
7212 || reloc_type
== BFD_RELOC_X86_64_32S
7213 || (reloc_type
== BFD_RELOC_64
7215 && (i
.op
[n
].disps
->X_op
== O_symbol
7216 || (i
.op
[n
].disps
->X_op
== O_add
7217 && ((symbol_get_value_expression
7218 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7220 || reloc_type
== BFD_RELOC_32_PCREL
))
7224 if (insn_start_frag
== frag_now
)
7225 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7230 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7231 for (fr
= insn_start_frag
->fr_next
;
7232 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7234 add
+= p
- frag_now
->fr_literal
;
7239 reloc_type
= BFD_RELOC_386_GOTPC
;
7240 i
.op
[n
].imms
->X_add_number
+= add
;
7242 else if (reloc_type
== BFD_RELOC_64
)
7243 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7245 /* Don't do the adjustment for x86-64, as there
7246 the pcrel addressing is relative to the _next_
7247 insn, and that is taken care of in other code. */
7248 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7250 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7251 i
.op
[n
].disps
, pcrel
, reloc_type
);
7258 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7263 for (n
= 0; n
< i
.operands
; n
++)
7265 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7266 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7269 if (operand_type_check (i
.types
[n
], imm
))
7271 if (i
.op
[n
].imms
->X_op
== O_constant
)
7273 int size
= imm_size (n
);
7276 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7278 p
= frag_more (size
);
7279 md_number_to_chars (p
, val
, size
);
7283 /* Not absolute_section.
7284 Need a 32-bit fixup (don't support 8bit
7285 non-absolute imms). Try to support other
7287 enum bfd_reloc_code_real reloc_type
;
7288 int size
= imm_size (n
);
7291 if (i
.types
[n
].bitfield
.imm32s
7292 && (i
.suffix
== QWORD_MNEM_SUFFIX
7293 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7298 p
= frag_more (size
);
7299 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7301 /* This is tough to explain. We end up with this one if we
7302 * have operands that look like
7303 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7304 * obtain the absolute address of the GOT, and it is strongly
7305 * preferable from a performance point of view to avoid using
7306 * a runtime relocation for this. The actual sequence of
7307 * instructions often look something like:
7312 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7314 * The call and pop essentially return the absolute address
7315 * of the label .L66 and store it in %ebx. The linker itself
7316 * will ultimately change the first operand of the addl so
7317 * that %ebx points to the GOT, but to keep things simple, the
7318 * .o file must have this operand set so that it generates not
7319 * the absolute address of .L66, but the absolute address of
7320 * itself. This allows the linker itself simply treat a GOTPC
7321 * relocation as asking for a pcrel offset to the GOT to be
7322 * added in, and the addend of the relocation is stored in the
7323 * operand field for the instruction itself.
7325 * Our job here is to fix the operand so that it would add
7326 * the correct offset so that %ebx would point to itself. The
7327 * thing that is tricky is that .-.L66 will point to the
7328 * beginning of the instruction, so we need to further modify
7329 * the operand so that it will point to itself. There are
7330 * other cases where you have something like:
7332 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7334 * and here no correction would be required. Internally in
7335 * the assembler we treat operands of this form as not being
7336 * pcrel since the '.' is explicitly mentioned, and I wonder
7337 * whether it would simplify matters to do it this way. Who
7338 * knows. In earlier versions of the PIC patches, the
7339 * pcrel_adjust field was used to store the correction, but
7340 * since the expression is not pcrel, I felt it would be
7341 * confusing to do it this way. */
7343 if ((reloc_type
== BFD_RELOC_32
7344 || reloc_type
== BFD_RELOC_X86_64_32S
7345 || reloc_type
== BFD_RELOC_64
)
7347 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7348 && (i
.op
[n
].imms
->X_op
== O_symbol
7349 || (i
.op
[n
].imms
->X_op
== O_add
7350 && ((symbol_get_value_expression
7351 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7356 if (insn_start_frag
== frag_now
)
7357 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7362 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7363 for (fr
= insn_start_frag
->fr_next
;
7364 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7366 add
+= p
- frag_now
->fr_literal
;
7370 reloc_type
= BFD_RELOC_386_GOTPC
;
7372 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7374 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7375 i
.op
[n
].imms
->X_add_number
+= add
;
7377 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7378 i
.op
[n
].imms
, 0, reloc_type
);
7384 /* x86_cons_fix_new is called via the expression parsing code when a
7385 reloc is needed. We use this hook to get the correct .got reloc. */
7386 static int cons_sign
= -1;
7389 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7390 expressionS
*exp
, bfd_reloc_code_real_type r
)
7392 r
= reloc (len
, 0, cons_sign
, 0, r
);
7395 if (exp
->X_op
== O_secrel
)
7397 exp
->X_op
= O_symbol
;
7398 r
= BFD_RELOC_32_SECREL
;
7402 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7405 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7406 purpose of the `.dc.a' internal pseudo-op. */
7409 x86_address_bytes (void)
7411 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7413 return stdoutput
->arch_info
->bits_per_address
/ 8;
7416 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7418 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7420 /* Parse operands of the form
7421 <symbol>@GOTOFF+<nnn>
7422 and similar .plt or .got references.
7424 If we find one, set up the correct relocation in RELOC and copy the
7425 input string, minus the `@GOTOFF' into a malloc'd buffer for
7426 parsing by the calling routine. Return this buffer, and if ADJUST
7427 is non-null set it to the length of the string we removed from the
7428 input line. Otherwise return NULL. */
7430 lex_got (enum bfd_reloc_code_real
*rel
,
7432 i386_operand_type
*types
,
7435 /* Some of the relocations depend on the size of what field is to
7436 be relocated. But in our callers i386_immediate and i386_displacement
7437 we don't yet know the operand size (this will be set by insn
7438 matching). Hence we record the word32 relocation here,
7439 and adjust the reloc according to the real size in reloc(). */
7440 static const struct {
7443 const enum bfd_reloc_code_real rel
[2];
7444 const i386_operand_type types64
;
7446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7447 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7449 OPERAND_TYPE_IMM32_64
},
7451 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7452 BFD_RELOC_X86_64_PLTOFF64
},
7453 OPERAND_TYPE_IMM64
},
7454 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7455 BFD_RELOC_X86_64_PLT32
},
7456 OPERAND_TYPE_IMM32_32S_DISP32
},
7457 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7458 BFD_RELOC_X86_64_GOTPLT64
},
7459 OPERAND_TYPE_IMM64_DISP64
},
7460 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7461 BFD_RELOC_X86_64_GOTOFF64
},
7462 OPERAND_TYPE_IMM64_DISP64
},
7463 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7464 BFD_RELOC_X86_64_GOTPCREL
},
7465 OPERAND_TYPE_IMM32_32S_DISP32
},
7466 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7467 BFD_RELOC_X86_64_TLSGD
},
7468 OPERAND_TYPE_IMM32_32S_DISP32
},
7469 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7470 _dummy_first_bfd_reloc_code_real
},
7471 OPERAND_TYPE_NONE
},
7472 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7473 BFD_RELOC_X86_64_TLSLD
},
7474 OPERAND_TYPE_IMM32_32S_DISP32
},
7475 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7476 BFD_RELOC_X86_64_GOTTPOFF
},
7477 OPERAND_TYPE_IMM32_32S_DISP32
},
7478 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7479 BFD_RELOC_X86_64_TPOFF32
},
7480 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7481 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7482 _dummy_first_bfd_reloc_code_real
},
7483 OPERAND_TYPE_NONE
},
7484 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7485 BFD_RELOC_X86_64_DTPOFF32
},
7486 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7487 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7488 _dummy_first_bfd_reloc_code_real
},
7489 OPERAND_TYPE_NONE
},
7490 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7491 _dummy_first_bfd_reloc_code_real
},
7492 OPERAND_TYPE_NONE
},
7493 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7494 BFD_RELOC_X86_64_GOT32
},
7495 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7496 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7497 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7498 OPERAND_TYPE_IMM32_32S_DISP32
},
7499 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7500 BFD_RELOC_X86_64_TLSDESC_CALL
},
7501 OPERAND_TYPE_IMM32_32S_DISP32
},
7506 #if defined (OBJ_MAYBE_ELF)
7511 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7512 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7515 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7517 int len
= gotrel
[j
].len
;
7518 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7520 if (gotrel
[j
].rel
[object_64bit
] != 0)
7523 char *tmpbuf
, *past_reloc
;
7525 *rel
= gotrel
[j
].rel
[object_64bit
];
7529 if (flag_code
!= CODE_64BIT
)
7531 types
->bitfield
.imm32
= 1;
7532 types
->bitfield
.disp32
= 1;
7535 *types
= gotrel
[j
].types64
;
7538 if (j
!= 0 && GOT_symbol
== NULL
)
7539 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7541 /* The length of the first part of our input line. */
7542 first
= cp
- input_line_pointer
;
7544 /* The second part goes from after the reloc token until
7545 (and including) an end_of_line char or comma. */
7546 past_reloc
= cp
+ 1 + len
;
7548 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7550 second
= cp
+ 1 - past_reloc
;
7552 /* Allocate and copy string. The trailing NUL shouldn't
7553 be necessary, but be safe. */
7554 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7555 memcpy (tmpbuf
, input_line_pointer
, first
);
7556 if (second
!= 0 && *past_reloc
!= ' ')
7557 /* Replace the relocation token with ' ', so that
7558 errors like foo@GOTOFF1 will be detected. */
7559 tmpbuf
[first
++] = ' ';
7561 /* Increment length by 1 if the relocation token is
7566 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7567 tmpbuf
[first
+ second
] = '\0';
7568 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7569 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7573 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7574 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7579 /* Might be a symbol version string. Don't as_bad here. */
7588 /* Parse operands of the form
7589 <symbol>@SECREL32+<nnn>
7591 If we find one, set up the correct relocation in RELOC and copy the
7592 input string, minus the `@SECREL32' into a malloc'd buffer for
7593 parsing by the calling routine. Return this buffer, and if ADJUST
7594 is non-null set it to the length of the string we removed from the
7595 input line. Otherwise return NULL.
7597 This function is copied from the ELF version above adjusted for PE targets. */
7600 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7601 int *adjust ATTRIBUTE_UNUSED
,
7602 i386_operand_type
*types
,
7603 int bnd_prefix ATTRIBUTE_UNUSED
)
7609 const enum bfd_reloc_code_real rel
[2];
7610 const i386_operand_type types64
;
7614 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7615 BFD_RELOC_32_SECREL
},
7616 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7622 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7623 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7626 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7628 int len
= gotrel
[j
].len
;
7630 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7632 if (gotrel
[j
].rel
[object_64bit
] != 0)
7635 char *tmpbuf
, *past_reloc
;
7637 *rel
= gotrel
[j
].rel
[object_64bit
];
7643 if (flag_code
!= CODE_64BIT
)
7645 types
->bitfield
.imm32
= 1;
7646 types
->bitfield
.disp32
= 1;
7649 *types
= gotrel
[j
].types64
;
7652 /* The length of the first part of our input line. */
7653 first
= cp
- input_line_pointer
;
7655 /* The second part goes from after the reloc token until
7656 (and including) an end_of_line char or comma. */
7657 past_reloc
= cp
+ 1 + len
;
7659 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7661 second
= cp
+ 1 - past_reloc
;
7663 /* Allocate and copy string. The trailing NUL shouldn't
7664 be necessary, but be safe. */
7665 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7666 memcpy (tmpbuf
, input_line_pointer
, first
);
7667 if (second
!= 0 && *past_reloc
!= ' ')
7668 /* Replace the relocation token with ' ', so that
7669 errors like foo@SECLREL321 will be detected. */
7670 tmpbuf
[first
++] = ' ';
7671 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7672 tmpbuf
[first
+ second
] = '\0';
7676 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7677 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7682 /* Might be a symbol version string. Don't as_bad here. */
7688 bfd_reloc_code_real_type
7689 x86_cons (expressionS
*exp
, int size
)
7691 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7693 intel_syntax
= -intel_syntax
;
7696 if (size
== 4 || (object_64bit
&& size
== 8))
7698 /* Handle @GOTOFF and the like in an expression. */
7700 char *gotfree_input_line
;
7703 save
= input_line_pointer
;
7704 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7705 if (gotfree_input_line
)
7706 input_line_pointer
= gotfree_input_line
;
7710 if (gotfree_input_line
)
7712 /* expression () has merrily parsed up to the end of line,
7713 or a comma - in the wrong buffer. Transfer how far
7714 input_line_pointer has moved to the right buffer. */
7715 input_line_pointer
= (save
7716 + (input_line_pointer
- gotfree_input_line
)
7718 free (gotfree_input_line
);
7719 if (exp
->X_op
== O_constant
7720 || exp
->X_op
== O_absent
7721 || exp
->X_op
== O_illegal
7722 || exp
->X_op
== O_register
7723 || exp
->X_op
== O_big
)
7725 char c
= *input_line_pointer
;
7726 *input_line_pointer
= 0;
7727 as_bad (_("missing or invalid expression `%s'"), save
);
7728 *input_line_pointer
= c
;
7735 intel_syntax
= -intel_syntax
;
7738 i386_intel_simplify (exp
);
7744 signed_cons (int size
)
7746 if (flag_code
== CODE_64BIT
)
7754 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7761 if (exp
.X_op
== O_symbol
)
7762 exp
.X_op
= O_secrel
;
7764 emit_expr (&exp
, 4);
7766 while (*input_line_pointer
++ == ',');
7768 input_line_pointer
--;
7769 demand_empty_rest_of_line ();
7773 /* Handle Vector operations. */
7776 check_VecOperations (char *op_string
, char *op_end
)
7778 const reg_entry
*mask
;
7783 && (op_end
== NULL
|| op_string
< op_end
))
7786 if (*op_string
== '{')
7790 /* Check broadcasts. */
7791 if (strncmp (op_string
, "1to", 3) == 0)
7796 goto duplicated_vec_op
;
7799 if (*op_string
== '8')
7800 bcst_type
= BROADCAST_1TO8
;
7801 else if (*op_string
== '4')
7802 bcst_type
= BROADCAST_1TO4
;
7803 else if (*op_string
== '2')
7804 bcst_type
= BROADCAST_1TO2
;
7805 else if (*op_string
== '1'
7806 && *(op_string
+1) == '6')
7808 bcst_type
= BROADCAST_1TO16
;
7813 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7818 broadcast_op
.type
= bcst_type
;
7819 broadcast_op
.operand
= this_operand
;
7820 i
.broadcast
= &broadcast_op
;
7822 /* Check masking operation. */
7823 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7825 /* k0 can't be used for write mask. */
7826 if (mask
->reg_num
== 0)
7828 as_bad (_("`%s' can't be used for write mask"),
7835 mask_op
.mask
= mask
;
7836 mask_op
.zeroing
= 0;
7837 mask_op
.operand
= this_operand
;
7843 goto duplicated_vec_op
;
7845 i
.mask
->mask
= mask
;
7847 /* Only "{z}" is allowed here. No need to check
7848 zeroing mask explicitly. */
7849 if (i
.mask
->operand
!= this_operand
)
7851 as_bad (_("invalid write mask `%s'"), saved
);
7858 /* Check zeroing-flag for masking operation. */
7859 else if (*op_string
== 'z')
7863 mask_op
.mask
= NULL
;
7864 mask_op
.zeroing
= 1;
7865 mask_op
.operand
= this_operand
;
7870 if (i
.mask
->zeroing
)
7873 as_bad (_("duplicated `%s'"), saved
);
7877 i
.mask
->zeroing
= 1;
7879 /* Only "{%k}" is allowed here. No need to check mask
7880 register explicitly. */
7881 if (i
.mask
->operand
!= this_operand
)
7883 as_bad (_("invalid zeroing-masking `%s'"),
7892 goto unknown_vec_op
;
7894 if (*op_string
!= '}')
7896 as_bad (_("missing `}' in `%s'"), saved
);
7903 /* We don't know this one. */
7904 as_bad (_("unknown vector operation: `%s'"), saved
);
7912 i386_immediate (char *imm_start
)
7914 char *save_input_line_pointer
;
7915 char *gotfree_input_line
;
7918 i386_operand_type types
;
7920 operand_type_set (&types
, ~0);
7922 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7924 as_bad (_("at most %d immediate operands are allowed"),
7925 MAX_IMMEDIATE_OPERANDS
);
7929 exp
= &im_expressions
[i
.imm_operands
++];
7930 i
.op
[this_operand
].imms
= exp
;
7932 if (is_space_char (*imm_start
))
7935 save_input_line_pointer
= input_line_pointer
;
7936 input_line_pointer
= imm_start
;
7938 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7939 (i
.bnd_prefix
!= NULL
7940 || add_bnd_prefix
));
7941 if (gotfree_input_line
)
7942 input_line_pointer
= gotfree_input_line
;
7944 exp_seg
= expression (exp
);
7948 /* Handle vector operations. */
7949 if (*input_line_pointer
== '{')
7951 input_line_pointer
= check_VecOperations (input_line_pointer
,
7953 if (input_line_pointer
== NULL
)
7957 if (*input_line_pointer
)
7958 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7960 input_line_pointer
= save_input_line_pointer
;
7961 if (gotfree_input_line
)
7963 free (gotfree_input_line
);
7965 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7966 exp
->X_op
= O_illegal
;
7969 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7973 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7974 i386_operand_type types
, const char *imm_start
)
7976 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7979 as_bad (_("missing or invalid immediate expression `%s'"),
7983 else if (exp
->X_op
== O_constant
)
7985 /* Size it properly later. */
7986 i
.types
[this_operand
].bitfield
.imm64
= 1;
7987 /* If not 64bit, sign extend val. */
7988 if (flag_code
!= CODE_64BIT
7989 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7991 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7993 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7994 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7995 && exp_seg
!= absolute_section
7996 && exp_seg
!= text_section
7997 && exp_seg
!= data_section
7998 && exp_seg
!= bss_section
7999 && exp_seg
!= undefined_section
8000 && !bfd_is_com_section (exp_seg
))
8002 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8006 else if (!intel_syntax
&& exp_seg
== reg_section
)
8009 as_bad (_("illegal immediate register operand %s"), imm_start
);
8014 /* This is an address. The size of the address will be
8015 determined later, depending on destination register,
8016 suffix, or the default for the section. */
8017 i
.types
[this_operand
].bitfield
.imm8
= 1;
8018 i
.types
[this_operand
].bitfield
.imm16
= 1;
8019 i
.types
[this_operand
].bitfield
.imm32
= 1;
8020 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8021 i
.types
[this_operand
].bitfield
.imm64
= 1;
8022 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8030 i386_scale (char *scale
)
8033 char *save
= input_line_pointer
;
8035 input_line_pointer
= scale
;
8036 val
= get_absolute_expression ();
8041 i
.log2_scale_factor
= 0;
8044 i
.log2_scale_factor
= 1;
8047 i
.log2_scale_factor
= 2;
8050 i
.log2_scale_factor
= 3;
8054 char sep
= *input_line_pointer
;
8056 *input_line_pointer
= '\0';
8057 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8059 *input_line_pointer
= sep
;
8060 input_line_pointer
= save
;
8064 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8066 as_warn (_("scale factor of %d without an index register"),
8067 1 << i
.log2_scale_factor
);
8068 i
.log2_scale_factor
= 0;
8070 scale
= input_line_pointer
;
8071 input_line_pointer
= save
;
8076 i386_displacement (char *disp_start
, char *disp_end
)
8080 char *save_input_line_pointer
;
8081 char *gotfree_input_line
;
8083 i386_operand_type bigdisp
, types
= anydisp
;
8086 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8088 as_bad (_("at most %d displacement operands are allowed"),
8089 MAX_MEMORY_OPERANDS
);
8093 operand_type_set (&bigdisp
, 0);
8094 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8095 || (!current_templates
->start
->opcode_modifier
.jump
8096 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8098 bigdisp
.bitfield
.disp32
= 1;
8099 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8100 if (flag_code
== CODE_64BIT
)
8104 bigdisp
.bitfield
.disp32s
= 1;
8105 bigdisp
.bitfield
.disp64
= 1;
8108 else if ((flag_code
== CODE_16BIT
) ^ override
)
8110 bigdisp
.bitfield
.disp32
= 0;
8111 bigdisp
.bitfield
.disp16
= 1;
8116 /* For PC-relative branches, the width of the displacement
8117 is dependent upon data size, not address size. */
8118 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8119 if (flag_code
== CODE_64BIT
)
8121 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8122 bigdisp
.bitfield
.disp16
= 1;
8125 bigdisp
.bitfield
.disp32
= 1;
8126 bigdisp
.bitfield
.disp32s
= 1;
8132 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8134 : LONG_MNEM_SUFFIX
));
8135 bigdisp
.bitfield
.disp32
= 1;
8136 if ((flag_code
== CODE_16BIT
) ^ override
)
8138 bigdisp
.bitfield
.disp32
= 0;
8139 bigdisp
.bitfield
.disp16
= 1;
8143 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8146 exp
= &disp_expressions
[i
.disp_operands
];
8147 i
.op
[this_operand
].disps
= exp
;
8149 save_input_line_pointer
= input_line_pointer
;
8150 input_line_pointer
= disp_start
;
8151 END_STRING_AND_SAVE (disp_end
);
8153 #ifndef GCC_ASM_O_HACK
8154 #define GCC_ASM_O_HACK 0
8157 END_STRING_AND_SAVE (disp_end
+ 1);
8158 if (i
.types
[this_operand
].bitfield
.baseIndex
8159 && displacement_string_end
[-1] == '+')
8161 /* This hack is to avoid a warning when using the "o"
8162 constraint within gcc asm statements.
8165 #define _set_tssldt_desc(n,addr,limit,type) \
8166 __asm__ __volatile__ ( \
8168 "movw %w1,2+%0\n\t" \
8170 "movb %b1,4+%0\n\t" \
8171 "movb %4,5+%0\n\t" \
8172 "movb $0,6+%0\n\t" \
8173 "movb %h1,7+%0\n\t" \
8175 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8177 This works great except that the output assembler ends
8178 up looking a bit weird if it turns out that there is
8179 no offset. You end up producing code that looks like:
8192 So here we provide the missing zero. */
8194 *displacement_string_end
= '0';
8197 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8198 (i
.bnd_prefix
!= NULL
8199 || add_bnd_prefix
));
8200 if (gotfree_input_line
)
8201 input_line_pointer
= gotfree_input_line
;
8203 exp_seg
= expression (exp
);
8206 if (*input_line_pointer
)
8207 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8209 RESTORE_END_STRING (disp_end
+ 1);
8211 input_line_pointer
= save_input_line_pointer
;
8212 if (gotfree_input_line
)
8214 free (gotfree_input_line
);
8216 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8217 exp
->X_op
= O_illegal
;
8220 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8222 RESTORE_END_STRING (disp_end
);
8228 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8229 i386_operand_type types
, const char *disp_start
)
8231 i386_operand_type bigdisp
;
8234 /* We do this to make sure that the section symbol is in
8235 the symbol table. We will ultimately change the relocation
8236 to be relative to the beginning of the section. */
8237 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8238 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8239 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8241 if (exp
->X_op
!= O_symbol
)
8244 if (S_IS_LOCAL (exp
->X_add_symbol
)
8245 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8246 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8247 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8248 exp
->X_op
= O_subtract
;
8249 exp
->X_op_symbol
= GOT_symbol
;
8250 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8251 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8252 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8253 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8255 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8258 else if (exp
->X_op
== O_absent
8259 || exp
->X_op
== O_illegal
8260 || exp
->X_op
== O_big
)
8263 as_bad (_("missing or invalid displacement expression `%s'"),
8268 else if (flag_code
== CODE_64BIT
8269 && !i
.prefix
[ADDR_PREFIX
]
8270 && exp
->X_op
== O_constant
)
8272 /* Since displacement is signed extended to 64bit, don't allow
8273 disp32 and turn off disp32s if they are out of range. */
8274 i
.types
[this_operand
].bitfield
.disp32
= 0;
8275 if (!fits_in_signed_long (exp
->X_add_number
))
8277 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8278 if (i
.types
[this_operand
].bitfield
.baseindex
)
8280 as_bad (_("0x%lx out range of signed 32bit displacement"),
8281 (long) exp
->X_add_number
);
8287 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8288 else if (exp
->X_op
!= O_constant
8289 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8290 && exp_seg
!= absolute_section
8291 && exp_seg
!= text_section
8292 && exp_seg
!= data_section
8293 && exp_seg
!= bss_section
8294 && exp_seg
!= undefined_section
8295 && !bfd_is_com_section (exp_seg
))
8297 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8302 /* Check if this is a displacement only operand. */
8303 bigdisp
= i
.types
[this_operand
];
8304 bigdisp
.bitfield
.disp8
= 0;
8305 bigdisp
.bitfield
.disp16
= 0;
8306 bigdisp
.bitfield
.disp32
= 0;
8307 bigdisp
.bitfield
.disp32s
= 0;
8308 bigdisp
.bitfield
.disp64
= 0;
8309 if (operand_type_all_zero (&bigdisp
))
8310 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8316 /* Make sure the memory operand we've been dealt is valid.
8317 Return 1 on success, 0 on a failure. */
8320 i386_index_check (const char *operand_string
)
8322 const char *kind
= "base/index";
8323 enum flag_code addr_mode
;
8325 if (i
.prefix
[ADDR_PREFIX
])
8326 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8329 addr_mode
= flag_code
;
8331 #if INFER_ADDR_PREFIX
8332 if (i
.mem_operands
== 0)
8334 /* Infer address prefix from the first memory operand. */
8335 const reg_entry
*addr_reg
= i
.base_reg
;
8337 if (addr_reg
== NULL
)
8338 addr_reg
= i
.index_reg
;
8342 if (addr_reg
->reg_num
== RegEip
8343 || addr_reg
->reg_num
== RegEiz
8344 || addr_reg
->reg_type
.bitfield
.reg32
)
8345 addr_mode
= CODE_32BIT
;
8346 else if (flag_code
!= CODE_64BIT
8347 && addr_reg
->reg_type
.bitfield
.reg16
)
8348 addr_mode
= CODE_16BIT
;
8350 if (addr_mode
!= flag_code
)
8352 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8354 /* Change the size of any displacement too. At most one
8355 of Disp16 or Disp32 is set.
8356 FIXME. There doesn't seem to be any real need for
8357 separate Disp16 and Disp32 flags. The same goes for
8358 Imm16 and Imm32. Removing them would probably clean
8359 up the code quite a lot. */
8360 if (flag_code
!= CODE_64BIT
8361 && (i
.types
[this_operand
].bitfield
.disp16
8362 || i
.types
[this_operand
].bitfield
.disp32
))
8363 i
.types
[this_operand
]
8364 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8371 if (current_templates
->start
->opcode_modifier
.isstring
8372 && !current_templates
->start
->opcode_modifier
.immext
8373 && (current_templates
->end
[-1].opcode_modifier
.isstring
8376 /* Memory operands of string insns are special in that they only allow
8377 a single register (rDI, rSI, or rBX) as their memory address. */
8378 const reg_entry
*expected_reg
;
8379 static const char *di_si
[][2] =
8385 static const char *bx
[] = { "ebx", "bx", "rbx" };
8387 kind
= "string address";
8389 if (current_templates
->start
->opcode_modifier
.w
)
8391 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8393 if (!type
.bitfield
.baseindex
8394 || ((!i
.mem_operands
!= !intel_syntax
)
8395 && current_templates
->end
[-1].operand_types
[1]
8396 .bitfield
.baseindex
))
8397 type
= current_templates
->end
[-1].operand_types
[1];
8398 expected_reg
= hash_find (reg_hash
,
8399 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8403 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8405 if (i
.base_reg
!= expected_reg
8407 || operand_type_check (i
.types
[this_operand
], disp
))
8409 /* The second memory operand must have the same size as
8413 && !((addr_mode
== CODE_64BIT
8414 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8415 || (addr_mode
== CODE_32BIT
8416 ? i
.base_reg
->reg_type
.bitfield
.reg32
8417 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8420 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8422 intel_syntax
? '[' : '(',
8424 expected_reg
->reg_name
,
8425 intel_syntax
? ']' : ')');
8432 as_bad (_("`%s' is not a valid %s expression"),
8433 operand_string
, kind
);
8438 if (addr_mode
!= CODE_16BIT
)
8440 /* 32-bit/64-bit checks. */
8442 && (addr_mode
== CODE_64BIT
8443 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8444 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8446 || (i
.base_reg
->reg_num
8447 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8449 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8450 && !i
.index_reg
->reg_type
.bitfield
.regymm
8451 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8452 && ((addr_mode
== CODE_64BIT
8453 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8454 || i
.index_reg
->reg_num
== RegRiz
)
8455 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8456 || i
.index_reg
->reg_num
== RegEiz
))
8457 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8462 /* 16-bit checks. */
8464 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8465 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8467 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8468 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8470 && i
.base_reg
->reg_num
< 6
8471 && i
.index_reg
->reg_num
>= 6
8472 && i
.log2_scale_factor
== 0))))
8479 /* Handle vector immediates. */
8482 RC_SAE_immediate (const char *imm_start
)
8484 unsigned int match_found
, j
;
8485 const char *pstr
= imm_start
;
8493 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8495 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8499 rc_op
.type
= RC_NamesTable
[j
].type
;
8500 rc_op
.operand
= this_operand
;
8501 i
.rounding
= &rc_op
;
8505 as_bad (_("duplicated `%s'"), imm_start
);
8508 pstr
+= RC_NamesTable
[j
].len
;
8518 as_bad (_("Missing '}': '%s'"), imm_start
);
8521 /* RC/SAE immediate string should contain nothing more. */;
8524 as_bad (_("Junk after '}': '%s'"), imm_start
);
8528 exp
= &im_expressions
[i
.imm_operands
++];
8529 i
.op
[this_operand
].imms
= exp
;
8531 exp
->X_op
= O_constant
;
8532 exp
->X_add_number
= 0;
8533 exp
->X_add_symbol
= (symbolS
*) 0;
8534 exp
->X_op_symbol
= (symbolS
*) 0;
8536 i
.types
[this_operand
].bitfield
.imm8
= 1;
8540 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8544 i386_att_operand (char *operand_string
)
8548 char *op_string
= operand_string
;
8550 if (is_space_char (*op_string
))
8553 /* We check for an absolute prefix (differentiating,
8554 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8555 if (*op_string
== ABSOLUTE_PREFIX
)
8558 if (is_space_char (*op_string
))
8560 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8563 /* Check if operand is a register. */
8564 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8566 i386_operand_type temp
;
8568 /* Check for a segment override by searching for ':' after a
8569 segment register. */
8571 if (is_space_char (*op_string
))
8573 if (*op_string
== ':'
8574 && (r
->reg_type
.bitfield
.sreg2
8575 || r
->reg_type
.bitfield
.sreg3
))
8580 i
.seg
[i
.mem_operands
] = &es
;
8583 i
.seg
[i
.mem_operands
] = &cs
;
8586 i
.seg
[i
.mem_operands
] = &ss
;
8589 i
.seg
[i
.mem_operands
] = &ds
;
8592 i
.seg
[i
.mem_operands
] = &fs
;
8595 i
.seg
[i
.mem_operands
] = &gs
;
8599 /* Skip the ':' and whitespace. */
8601 if (is_space_char (*op_string
))
8604 if (!is_digit_char (*op_string
)
8605 && !is_identifier_char (*op_string
)
8606 && *op_string
!= '('
8607 && *op_string
!= ABSOLUTE_PREFIX
)
8609 as_bad (_("bad memory operand `%s'"), op_string
);
8612 /* Handle case of %es:*foo. */
8613 if (*op_string
== ABSOLUTE_PREFIX
)
8616 if (is_space_char (*op_string
))
8618 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8620 goto do_memory_reference
;
8623 /* Handle vector operations. */
8624 if (*op_string
== '{')
8626 op_string
= check_VecOperations (op_string
, NULL
);
8627 if (op_string
== NULL
)
8633 as_bad (_("junk `%s' after register"), op_string
);
8637 temp
.bitfield
.baseindex
= 0;
8638 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8640 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8641 i
.op
[this_operand
].regs
= r
;
8644 else if (*op_string
== REGISTER_PREFIX
)
8646 as_bad (_("bad register name `%s'"), op_string
);
8649 else if (*op_string
== IMMEDIATE_PREFIX
)
8652 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8654 as_bad (_("immediate operand illegal with absolute jump"));
8657 if (!i386_immediate (op_string
))
8660 else if (RC_SAE_immediate (operand_string
))
8662 /* If it is a RC or SAE immediate, do nothing. */
8665 else if (is_digit_char (*op_string
)
8666 || is_identifier_char (*op_string
)
8667 || *op_string
== '(')
8669 /* This is a memory reference of some sort. */
8672 /* Start and end of displacement string expression (if found). */
8673 char *displacement_string_start
;
8674 char *displacement_string_end
;
8677 do_memory_reference
:
8678 if ((i
.mem_operands
== 1
8679 && !current_templates
->start
->opcode_modifier
.isstring
)
8680 || i
.mem_operands
== 2)
8682 as_bad (_("too many memory references for `%s'"),
8683 current_templates
->start
->name
);
8687 /* Check for base index form. We detect the base index form by
8688 looking for an ')' at the end of the operand, searching
8689 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8691 base_string
= op_string
+ strlen (op_string
);
8693 /* Handle vector operations. */
8694 vop_start
= strchr (op_string
, '{');
8695 if (vop_start
&& vop_start
< base_string
)
8697 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8699 base_string
= vop_start
;
8703 if (is_space_char (*base_string
))
8706 /* If we only have a displacement, set-up for it to be parsed later. */
8707 displacement_string_start
= op_string
;
8708 displacement_string_end
= base_string
+ 1;
8710 if (*base_string
== ')')
8713 unsigned int parens_balanced
= 1;
8714 /* We've already checked that the number of left & right ()'s are
8715 equal, so this loop will not be infinite. */
8719 if (*base_string
== ')')
8721 if (*base_string
== '(')
8724 while (parens_balanced
);
8726 temp_string
= base_string
;
8728 /* Skip past '(' and whitespace. */
8730 if (is_space_char (*base_string
))
8733 if (*base_string
== ','
8734 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8737 displacement_string_end
= temp_string
;
8739 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8743 base_string
= end_op
;
8744 if (is_space_char (*base_string
))
8748 /* There may be an index reg or scale factor here. */
8749 if (*base_string
== ',')
8752 if (is_space_char (*base_string
))
8755 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8758 base_string
= end_op
;
8759 if (is_space_char (*base_string
))
8761 if (*base_string
== ',')
8764 if (is_space_char (*base_string
))
8767 else if (*base_string
!= ')')
8769 as_bad (_("expecting `,' or `)' "
8770 "after index register in `%s'"),
8775 else if (*base_string
== REGISTER_PREFIX
)
8777 end_op
= strchr (base_string
, ',');
8780 as_bad (_("bad register name `%s'"), base_string
);
8784 /* Check for scale factor. */
8785 if (*base_string
!= ')')
8787 char *end_scale
= i386_scale (base_string
);
8792 base_string
= end_scale
;
8793 if (is_space_char (*base_string
))
8795 if (*base_string
!= ')')
8797 as_bad (_("expecting `)' "
8798 "after scale factor in `%s'"),
8803 else if (!i
.index_reg
)
8805 as_bad (_("expecting index register or scale factor "
8806 "after `,'; got '%c'"),
8811 else if (*base_string
!= ')')
8813 as_bad (_("expecting `,' or `)' "
8814 "after base register in `%s'"),
8819 else if (*base_string
== REGISTER_PREFIX
)
8821 end_op
= strchr (base_string
, ',');
8824 as_bad (_("bad register name `%s'"), base_string
);
8829 /* If there's an expression beginning the operand, parse it,
8830 assuming displacement_string_start and
8831 displacement_string_end are meaningful. */
8832 if (displacement_string_start
!= displacement_string_end
)
8834 if (!i386_displacement (displacement_string_start
,
8835 displacement_string_end
))
8839 /* Special case for (%dx) while doing input/output op. */
8841 && operand_type_equal (&i
.base_reg
->reg_type
,
8842 ®16_inoutportreg
)
8844 && i
.log2_scale_factor
== 0
8845 && i
.seg
[i
.mem_operands
] == 0
8846 && !operand_type_check (i
.types
[this_operand
], disp
))
8848 i
.types
[this_operand
] = inoutportreg
;
8852 if (i386_index_check (operand_string
) == 0)
8854 i
.types
[this_operand
].bitfield
.mem
= 1;
8859 /* It's not a memory operand; argh! */
8860 as_bad (_("invalid char %s beginning operand %d `%s'"),
8861 output_invalid (*op_string
),
8866 return 1; /* Normal return. */
8869 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8870 that an rs_machine_dependent frag may reach. */
8873 i386_frag_max_var (fragS
*frag
)
8875 /* The only relaxable frags are for jumps.
8876 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8877 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8878 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8881 /* md_estimate_size_before_relax()
8883 Called just before relax() for rs_machine_dependent frags. The x86
8884 assembler uses these frags to handle variable size jump
8887 Any symbol that is now undefined will not become defined.
8888 Return the correct fr_subtype in the frag.
8889 Return the initial "guess for variable size of frag" to caller.
8890 The guess is actually the growth beyond the fixed part. Whatever
8891 we do to grow the fixed or variable part contributes to our
8895 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8897 /* We've already got fragP->fr_subtype right; all we have to do is
8898 check for un-relaxable symbols. On an ELF system, we can't relax
8899 an externally visible symbol, because it may be overridden by a
8901 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8904 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8905 || S_IS_WEAK (fragP
->fr_symbol
)
8906 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8907 & BSF_GNU_INDIRECT_FUNCTION
))))
8909 #if defined (OBJ_COFF) && defined (TE_PE)
8910 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8911 && S_IS_WEAK (fragP
->fr_symbol
))
8915 /* Symbol is undefined in this segment, or we need to keep a
8916 reloc so that weak symbols can be overridden. */
8917 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8918 enum bfd_reloc_code_real reloc_type
;
8919 unsigned char *opcode
;
8922 if (fragP
->fr_var
!= NO_RELOC
)
8923 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8925 reloc_type
= BFD_RELOC_16_PCREL
;
8927 reloc_type
= BFD_RELOC_32_PCREL
;
8929 old_fr_fix
= fragP
->fr_fix
;
8930 opcode
= (unsigned char *) fragP
->fr_opcode
;
8932 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8935 /* Make jmp (0xeb) a (d)word displacement jump. */
8937 fragP
->fr_fix
+= size
;
8938 fix_new (fragP
, old_fr_fix
, size
,
8940 fragP
->fr_offset
, 1,
8946 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8948 /* Negate the condition, and branch past an
8949 unconditional jump. */
8952 /* Insert an unconditional jump. */
8954 /* We added two extra opcode bytes, and have a two byte
8956 fragP
->fr_fix
+= 2 + 2;
8957 fix_new (fragP
, old_fr_fix
+ 2, 2,
8959 fragP
->fr_offset
, 1,
8966 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8971 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8973 fragP
->fr_offset
, 1,
8975 fixP
->fx_signed
= 1;
8979 /* This changes the byte-displacement jump 0x7N
8980 to the (d)word-displacement jump 0x0f,0x8N. */
8981 opcode
[1] = opcode
[0] + 0x10;
8982 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8983 /* We've added an opcode byte. */
8984 fragP
->fr_fix
+= 1 + size
;
8985 fix_new (fragP
, old_fr_fix
+ 1, size
,
8987 fragP
->fr_offset
, 1,
8992 BAD_CASE (fragP
->fr_subtype
);
8996 return fragP
->fr_fix
- old_fr_fix
;
8999 /* Guess size depending on current relax state. Initially the relax
9000 state will correspond to a short jump and we return 1, because
9001 the variable part of the frag (the branch offset) is one byte
9002 long. However, we can relax a section more than once and in that
9003 case we must either set fr_subtype back to the unrelaxed state,
9004 or return the value for the appropriate branch. */
9005 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9008 /* Called after relax() is finished.
9010 In: Address of frag.
9011 fr_type == rs_machine_dependent.
9012 fr_subtype is what the address relaxed to.
9014 Out: Any fixSs and constants are set up.
9015 Caller will turn frag into a ".space 0". */
9018 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9021 unsigned char *opcode
;
9022 unsigned char *where_to_put_displacement
= NULL
;
9023 offsetT target_address
;
9024 offsetT opcode_address
;
9025 unsigned int extension
= 0;
9026 offsetT displacement_from_opcode_start
;
9028 opcode
= (unsigned char *) fragP
->fr_opcode
;
9030 /* Address we want to reach in file space. */
9031 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9033 /* Address opcode resides at in file space. */
9034 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9036 /* Displacement from opcode start to fill into instruction. */
9037 displacement_from_opcode_start
= target_address
- opcode_address
;
9039 if ((fragP
->fr_subtype
& BIG
) == 0)
9041 /* Don't have to change opcode. */
9042 extension
= 1; /* 1 opcode + 1 displacement */
9043 where_to_put_displacement
= &opcode
[1];
9047 if (no_cond_jump_promotion
9048 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9049 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9050 _("long jump required"));
9052 switch (fragP
->fr_subtype
)
9054 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9055 extension
= 4; /* 1 opcode + 4 displacement */
9057 where_to_put_displacement
= &opcode
[1];
9060 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9061 extension
= 2; /* 1 opcode + 2 displacement */
9063 where_to_put_displacement
= &opcode
[1];
9066 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9067 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9068 extension
= 5; /* 2 opcode + 4 displacement */
9069 opcode
[1] = opcode
[0] + 0x10;
9070 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9071 where_to_put_displacement
= &opcode
[2];
9074 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9075 extension
= 3; /* 2 opcode + 2 displacement */
9076 opcode
[1] = opcode
[0] + 0x10;
9077 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9078 where_to_put_displacement
= &opcode
[2];
9081 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9086 where_to_put_displacement
= &opcode
[3];
9090 BAD_CASE (fragP
->fr_subtype
);
9095 /* If size if less then four we are sure that the operand fits,
9096 but if it's 4, then it could be that the displacement is larger
9098 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9100 && ((addressT
) (displacement_from_opcode_start
- extension
9101 + ((addressT
) 1 << 31))
9102 > (((addressT
) 2 << 31) - 1)))
9104 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9105 _("jump target out of range"));
9106 /* Make us emit 0. */
9107 displacement_from_opcode_start
= extension
;
9109 /* Now put displacement after opcode. */
9110 md_number_to_chars ((char *) where_to_put_displacement
,
9111 (valueT
) (displacement_from_opcode_start
- extension
),
9112 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9113 fragP
->fr_fix
+= extension
;
9116 /* Apply a fixup (fixP) to segment data, once it has been determined
9117 by our caller that we have all the info we need to fix it up.
9119 Parameter valP is the pointer to the value of the bits.
9121 On the 386, immediates, displacements, and data pointers are all in
9122 the same (little-endian) format, so we don't need to care about which
9126 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9128 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9129 valueT value
= *valP
;
9131 #if !defined (TE_Mach)
9134 switch (fixP
->fx_r_type
)
9140 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9143 case BFD_RELOC_X86_64_32S
:
9144 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9147 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9150 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9155 if (fixP
->fx_addsy
!= NULL
9156 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9157 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9158 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9159 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9160 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9161 && !use_rela_relocations
)
9163 /* This is a hack. There should be a better way to handle this.
9164 This covers for the fact that bfd_install_relocation will
9165 subtract the current location (for partial_inplace, PC relative
9166 relocations); see more below. */
9170 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9173 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9178 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9181 || (symbol_section_p (fixP
->fx_addsy
)
9182 && sym_seg
!= absolute_section
))
9183 && !generic_force_reloc (fixP
))
9185 /* Yes, we add the values in twice. This is because
9186 bfd_install_relocation subtracts them out again. I think
9187 bfd_install_relocation is broken, but I don't dare change
9189 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9193 #if defined (OBJ_COFF) && defined (TE_PE)
9194 /* For some reason, the PE format does not store a
9195 section address offset for a PC relative symbol. */
9196 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9197 || S_IS_WEAK (fixP
->fx_addsy
))
9198 value
+= md_pcrel_from (fixP
);
9201 #if defined (OBJ_COFF) && defined (TE_PE)
9202 if (fixP
->fx_addsy
!= NULL
9203 && S_IS_WEAK (fixP
->fx_addsy
)
9204 /* PR 16858: Do not modify weak function references. */
9205 && ! fixP
->fx_pcrel
)
9207 #if !defined (TE_PEP)
9208 /* For x86 PE weak function symbols are neither PC-relative
9209 nor do they set S_IS_FUNCTION. So the only reliable way
9210 to detect them is to check the flags of their containing
9212 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9213 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9217 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9221 /* Fix a few things - the dynamic linker expects certain values here,
9222 and we must not disappoint it. */
9223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9224 if (IS_ELF
&& fixP
->fx_addsy
)
9225 switch (fixP
->fx_r_type
)
9227 case BFD_RELOC_386_PLT32
:
9228 case BFD_RELOC_X86_64_PLT32
:
9229 case BFD_RELOC_X86_64_PLT32_BND
:
9230 /* Make the jump instruction point to the address of the operand. At
9231 runtime we merely add the offset to the actual PLT entry. */
9235 case BFD_RELOC_386_TLS_GD
:
9236 case BFD_RELOC_386_TLS_LDM
:
9237 case BFD_RELOC_386_TLS_IE_32
:
9238 case BFD_RELOC_386_TLS_IE
:
9239 case BFD_RELOC_386_TLS_GOTIE
:
9240 case BFD_RELOC_386_TLS_GOTDESC
:
9241 case BFD_RELOC_X86_64_TLSGD
:
9242 case BFD_RELOC_X86_64_TLSLD
:
9243 case BFD_RELOC_X86_64_GOTTPOFF
:
9244 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9245 value
= 0; /* Fully resolved at runtime. No addend. */
9247 case BFD_RELOC_386_TLS_LE
:
9248 case BFD_RELOC_386_TLS_LDO_32
:
9249 case BFD_RELOC_386_TLS_LE_32
:
9250 case BFD_RELOC_X86_64_DTPOFF32
:
9251 case BFD_RELOC_X86_64_DTPOFF64
:
9252 case BFD_RELOC_X86_64_TPOFF32
:
9253 case BFD_RELOC_X86_64_TPOFF64
:
9254 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9257 case BFD_RELOC_386_TLS_DESC_CALL
:
9258 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9259 value
= 0; /* Fully resolved at runtime. No addend. */
9260 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9264 case BFD_RELOC_386_GOT32
:
9265 case BFD_RELOC_X86_64_GOT32
:
9266 value
= 0; /* Fully resolved at runtime. No addend. */
9269 case BFD_RELOC_VTABLE_INHERIT
:
9270 case BFD_RELOC_VTABLE_ENTRY
:
9277 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9279 #endif /* !defined (TE_Mach) */
9281 /* Are we finished with this relocation now? */
9282 if (fixP
->fx_addsy
== NULL
)
9284 #if defined (OBJ_COFF) && defined (TE_PE)
9285 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9288 /* Remember value for tc_gen_reloc. */
9289 fixP
->fx_addnumber
= value
;
9290 /* Clear out the frag for now. */
9294 else if (use_rela_relocations
)
9296 fixP
->fx_no_overflow
= 1;
9297 /* Remember value for tc_gen_reloc. */
9298 fixP
->fx_addnumber
= value
;
9302 md_number_to_chars (p
, value
, fixP
->fx_size
);
9306 md_atof (int type
, char *litP
, int *sizeP
)
9308 /* This outputs the LITTLENUMs in REVERSE order;
9309 in accord with the bigendian 386. */
9310 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9313 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9316 output_invalid (int c
)
9319 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9322 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9323 "(0x%x)", (unsigned char) c
);
9324 return output_invalid_buf
;
9327 /* REG_STRING starts *before* REGISTER_PREFIX. */
9329 static const reg_entry
*
9330 parse_real_register (char *reg_string
, char **end_op
)
9332 char *s
= reg_string
;
9334 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9337 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9338 if (*s
== REGISTER_PREFIX
)
9341 if (is_space_char (*s
))
9345 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9347 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9348 return (const reg_entry
*) NULL
;
9352 /* For naked regs, make sure that we are not dealing with an identifier.
9353 This prevents confusing an identifier like `eax_var' with register
9355 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9356 return (const reg_entry
*) NULL
;
9360 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9362 /* Handle floating point regs, allowing spaces in the (i) part. */
9363 if (r
== i386_regtab
/* %st is first entry of table */)
9365 if (is_space_char (*s
))
9370 if (is_space_char (*s
))
9372 if (*s
>= '0' && *s
<= '7')
9376 if (is_space_char (*s
))
9381 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9386 /* We have "%st(" then garbage. */
9387 return (const reg_entry
*) NULL
;
9391 if (r
== NULL
|| allow_pseudo_reg
)
9394 if (operand_type_all_zero (&r
->reg_type
))
9395 return (const reg_entry
*) NULL
;
9397 if ((r
->reg_type
.bitfield
.reg32
9398 || r
->reg_type
.bitfield
.sreg3
9399 || r
->reg_type
.bitfield
.control
9400 || r
->reg_type
.bitfield
.debug
9401 || r
->reg_type
.bitfield
.test
)
9402 && !cpu_arch_flags
.bitfield
.cpui386
)
9403 return (const reg_entry
*) NULL
;
9405 if (r
->reg_type
.bitfield
.floatreg
9406 && !cpu_arch_flags
.bitfield
.cpu8087
9407 && !cpu_arch_flags
.bitfield
.cpu287
9408 && !cpu_arch_flags
.bitfield
.cpu387
)
9409 return (const reg_entry
*) NULL
;
9411 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9412 return (const reg_entry
*) NULL
;
9414 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9415 return (const reg_entry
*) NULL
;
9417 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9418 return (const reg_entry
*) NULL
;
9420 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9421 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9422 return (const reg_entry
*) NULL
;
9424 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9425 if (!allow_index_reg
9426 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9427 return (const reg_entry
*) NULL
;
9429 /* Upper 16 vector register is only available with VREX in 64bit
9431 if ((r
->reg_flags
& RegVRex
))
9433 if (!cpu_arch_flags
.bitfield
.cpuvrex
9434 || flag_code
!= CODE_64BIT
)
9435 return (const reg_entry
*) NULL
;
9440 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9441 || r
->reg_type
.bitfield
.reg64
)
9442 && (!cpu_arch_flags
.bitfield
.cpulm
9443 || !operand_type_equal (&r
->reg_type
, &control
))
9444 && flag_code
!= CODE_64BIT
)
9445 return (const reg_entry
*) NULL
;
9447 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9448 return (const reg_entry
*) NULL
;
9453 /* REG_STRING starts *before* REGISTER_PREFIX. */
9455 static const reg_entry
*
9456 parse_register (char *reg_string
, char **end_op
)
9460 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9461 r
= parse_real_register (reg_string
, end_op
);
9466 char *save
= input_line_pointer
;
9470 input_line_pointer
= reg_string
;
9471 c
= get_symbol_end ();
9472 symbolP
= symbol_find (reg_string
);
9473 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9475 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9477 know (e
->X_op
== O_register
);
9478 know (e
->X_add_number
>= 0
9479 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9480 r
= i386_regtab
+ e
->X_add_number
;
9481 if ((r
->reg_flags
& RegVRex
))
9483 *end_op
= input_line_pointer
;
9485 *input_line_pointer
= c
;
9486 input_line_pointer
= save
;
9492 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9495 char *end
= input_line_pointer
;
9498 r
= parse_register (name
, &input_line_pointer
);
9499 if (r
&& end
<= input_line_pointer
)
9501 *nextcharP
= *input_line_pointer
;
9502 *input_line_pointer
= 0;
9503 e
->X_op
= O_register
;
9504 e
->X_add_number
= r
- i386_regtab
;
9507 input_line_pointer
= end
;
9509 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9513 md_operand (expressionS
*e
)
9518 switch (*input_line_pointer
)
9520 case REGISTER_PREFIX
:
9521 r
= parse_real_register (input_line_pointer
, &end
);
9524 e
->X_op
= O_register
;
9525 e
->X_add_number
= r
- i386_regtab
;
9526 input_line_pointer
= end
;
9531 gas_assert (intel_syntax
);
9532 end
= input_line_pointer
++;
9534 if (*input_line_pointer
== ']')
9536 ++input_line_pointer
;
9537 e
->X_op_symbol
= make_expr_symbol (e
);
9538 e
->X_add_symbol
= NULL
;
9539 e
->X_add_number
= 0;
9545 input_line_pointer
= end
;
9552 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9553 const char *md_shortopts
= "kVQ:sqn";
9555 const char *md_shortopts
= "qn";
9558 #define OPTION_32 (OPTION_MD_BASE + 0)
9559 #define OPTION_64 (OPTION_MD_BASE + 1)
9560 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9561 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9562 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9563 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9564 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9565 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9566 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9567 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9568 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9569 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9570 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9571 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9572 #define OPTION_X32 (OPTION_MD_BASE + 14)
9573 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9574 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9575 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9576 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9577 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9578 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9580 struct option md_longopts
[] =
9582 {"32", no_argument
, NULL
, OPTION_32
},
9583 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9584 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9585 {"64", no_argument
, NULL
, OPTION_64
},
9587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9588 {"x32", no_argument
, NULL
, OPTION_X32
},
9590 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9591 {"march", required_argument
, NULL
, OPTION_MARCH
},
9592 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9593 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9594 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9595 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9596 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9597 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9598 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9599 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9600 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9601 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9602 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9603 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9604 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9605 # if defined (TE_PE) || defined (TE_PEP)
9606 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9608 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9609 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9610 {NULL
, no_argument
, NULL
, 0}
9612 size_t md_longopts_size
= sizeof (md_longopts
);
9615 md_parse_option (int c
, char *arg
)
9623 optimize_align_code
= 0;
9630 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9631 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9632 should be emitted or not. FIXME: Not implemented. */
9636 /* -V: SVR4 argument to print version ID. */
9638 print_version_id ();
9641 /* -k: Ignore for FreeBSD compatibility. */
9646 /* -s: On i386 Solaris, this tells the native assembler to use
9647 .stab instead of .stab.excl. We always use .stab anyhow. */
9650 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9651 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9654 const char **list
, **l
;
9656 list
= bfd_target_list ();
9657 for (l
= list
; *l
!= NULL
; l
++)
9658 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9659 || strcmp (*l
, "coff-x86-64") == 0
9660 || strcmp (*l
, "pe-x86-64") == 0
9661 || strcmp (*l
, "pei-x86-64") == 0
9662 || strcmp (*l
, "mach-o-x86-64") == 0)
9664 default_arch
= "x86_64";
9668 as_fatal (_("no compiled in support for x86_64"));
9674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9678 const char **list
, **l
;
9680 list
= bfd_target_list ();
9681 for (l
= list
; *l
!= NULL
; l
++)
9682 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9684 default_arch
= "x86_64:32";
9688 as_fatal (_("no compiled in support for 32bit x86_64"));
9692 as_fatal (_("32bit x86_64 is only supported for ELF"));
9697 default_arch
= "i386";
9701 #ifdef SVR4_COMMENT_CHARS
9706 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9708 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9712 i386_comment_chars
= n
;
9718 arch
= xstrdup (arg
);
9722 as_fatal (_("invalid -march= option: `%s'"), arg
);
9723 next
= strchr (arch
, '+');
9726 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9728 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9731 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9734 cpu_arch_name
= cpu_arch
[j
].name
;
9735 cpu_sub_arch_name
= NULL
;
9736 cpu_arch_flags
= cpu_arch
[j
].flags
;
9737 cpu_arch_isa
= cpu_arch
[j
].type
;
9738 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9739 if (!cpu_arch_tune_set
)
9741 cpu_arch_tune
= cpu_arch_isa
;
9742 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9746 else if (*cpu_arch
[j
].name
== '.'
9747 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9749 /* ISA entension. */
9750 i386_cpu_flags flags
;
9752 if (!cpu_arch
[j
].negated
)
9753 flags
= cpu_flags_or (cpu_arch_flags
,
9756 flags
= cpu_flags_and_not (cpu_arch_flags
,
9758 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9760 if (cpu_sub_arch_name
)
9762 char *name
= cpu_sub_arch_name
;
9763 cpu_sub_arch_name
= concat (name
,
9765 (const char *) NULL
);
9769 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9770 cpu_arch_flags
= flags
;
9771 cpu_arch_isa_flags
= flags
;
9777 if (j
>= ARRAY_SIZE (cpu_arch
))
9778 as_fatal (_("invalid -march= option: `%s'"), arg
);
9782 while (next
!= NULL
);
9787 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9788 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9790 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9792 cpu_arch_tune_set
= 1;
9793 cpu_arch_tune
= cpu_arch
[j
].type
;
9794 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9798 if (j
>= ARRAY_SIZE (cpu_arch
))
9799 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9802 case OPTION_MMNEMONIC
:
9803 if (strcasecmp (arg
, "att") == 0)
9805 else if (strcasecmp (arg
, "intel") == 0)
9808 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9811 case OPTION_MSYNTAX
:
9812 if (strcasecmp (arg
, "att") == 0)
9814 else if (strcasecmp (arg
, "intel") == 0)
9817 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9820 case OPTION_MINDEX_REG
:
9821 allow_index_reg
= 1;
9824 case OPTION_MNAKED_REG
:
9825 allow_naked_reg
= 1;
9828 case OPTION_MOLD_GCC
:
9832 case OPTION_MSSE2AVX
:
9836 case OPTION_MSSE_CHECK
:
9837 if (strcasecmp (arg
, "error") == 0)
9838 sse_check
= check_error
;
9839 else if (strcasecmp (arg
, "warning") == 0)
9840 sse_check
= check_warning
;
9841 else if (strcasecmp (arg
, "none") == 0)
9842 sse_check
= check_none
;
9844 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9847 case OPTION_MOPERAND_CHECK
:
9848 if (strcasecmp (arg
, "error") == 0)
9849 operand_check
= check_error
;
9850 else if (strcasecmp (arg
, "warning") == 0)
9851 operand_check
= check_warning
;
9852 else if (strcasecmp (arg
, "none") == 0)
9853 operand_check
= check_none
;
9855 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9858 case OPTION_MAVXSCALAR
:
9859 if (strcasecmp (arg
, "128") == 0)
9861 else if (strcasecmp (arg
, "256") == 0)
9864 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9867 case OPTION_MADD_BND_PREFIX
:
9871 case OPTION_MEVEXLIG
:
9872 if (strcmp (arg
, "128") == 0)
9874 else if (strcmp (arg
, "256") == 0)
9876 else if (strcmp (arg
, "512") == 0)
9879 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9882 case OPTION_MEVEXRCIG
:
9883 if (strcmp (arg
, "rne") == 0)
9885 else if (strcmp (arg
, "rd") == 0)
9887 else if (strcmp (arg
, "ru") == 0)
9889 else if (strcmp (arg
, "rz") == 0)
9892 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9895 case OPTION_MEVEXWIG
:
9896 if (strcmp (arg
, "0") == 0)
9898 else if (strcmp (arg
, "1") == 0)
9901 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9904 # if defined (TE_PE) || defined (TE_PEP)
9905 case OPTION_MBIG_OBJ
:
9910 case OPTION_OMIT_LOCK_PREFIX
:
9911 if (strcasecmp (arg
, "yes") == 0)
9912 omit_lock_prefix
= 1;
9913 else if (strcasecmp (arg
, "no") == 0)
9914 omit_lock_prefix
= 0;
9916 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9925 #define MESSAGE_TEMPLATE \
9929 show_arch (FILE *stream
, int ext
, int check
)
9931 static char message
[] = MESSAGE_TEMPLATE
;
9932 char *start
= message
+ 27;
9934 int size
= sizeof (MESSAGE_TEMPLATE
);
9941 left
= size
- (start
- message
);
9942 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9944 /* Should it be skipped? */
9945 if (cpu_arch
[j
].skip
)
9948 name
= cpu_arch
[j
].name
;
9949 len
= cpu_arch
[j
].len
;
9952 /* It is an extension. Skip if we aren't asked to show it. */
9963 /* It is an processor. Skip if we show only extension. */
9966 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9968 /* It is an impossible processor - skip. */
9972 /* Reserve 2 spaces for ", " or ",\0" */
9975 /* Check if there is any room. */
9983 p
= mempcpy (p
, name
, len
);
9987 /* Output the current message now and start a new one. */
9990 fprintf (stream
, "%s\n", message
);
9992 left
= size
- (start
- message
) - len
- 2;
9994 gas_assert (left
>= 0);
9996 p
= mempcpy (p
, name
, len
);
10001 fprintf (stream
, "%s\n", message
);
10005 md_show_usage (FILE *stream
)
10007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10008 fprintf (stream
, _("\
10010 -V print assembler version number\n\
10013 fprintf (stream
, _("\
10014 -n Do not optimize code alignment\n\
10015 -q quieten some warnings\n"));
10016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10017 fprintf (stream
, _("\
10020 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10021 || defined (TE_PE) || defined (TE_PEP))
10022 fprintf (stream
, _("\
10023 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10025 #ifdef SVR4_COMMENT_CHARS
10026 fprintf (stream
, _("\
10027 --divide do not treat `/' as a comment character\n"));
10029 fprintf (stream
, _("\
10030 --divide ignored\n"));
10032 fprintf (stream
, _("\
10033 -march=CPU[,+EXTENSION...]\n\
10034 generate code for CPU and EXTENSION, CPU is one of:\n"));
10035 show_arch (stream
, 0, 1);
10036 fprintf (stream
, _("\
10037 EXTENSION is combination of:\n"));
10038 show_arch (stream
, 1, 0);
10039 fprintf (stream
, _("\
10040 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10041 show_arch (stream
, 0, 0);
10042 fprintf (stream
, _("\
10043 -msse2avx encode SSE instructions with VEX prefix\n"));
10044 fprintf (stream
, _("\
10045 -msse-check=[none|error|warning]\n\
10046 check SSE instructions\n"));
10047 fprintf (stream
, _("\
10048 -moperand-check=[none|error|warning]\n\
10049 check operand combinations for validity\n"));
10050 fprintf (stream
, _("\
10051 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10053 fprintf (stream
, _("\
10054 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10056 fprintf (stream
, _("\
10057 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10058 for EVEX.W bit ignored instructions\n"));
10059 fprintf (stream
, _("\
10060 -mevexrcig=[rne|rd|ru|rz]\n\
10061 encode EVEX instructions with specific EVEX.RC value\n\
10062 for SAE-only ignored instructions\n"));
10063 fprintf (stream
, _("\
10064 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10065 fprintf (stream
, _("\
10066 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10067 fprintf (stream
, _("\
10068 -mindex-reg support pseudo index registers\n"));
10069 fprintf (stream
, _("\
10070 -mnaked-reg don't require `%%' prefix for registers\n"));
10071 fprintf (stream
, _("\
10072 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10073 fprintf (stream
, _("\
10074 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10075 # if defined (TE_PE) || defined (TE_PEP)
10076 fprintf (stream
, _("\
10077 -mbig-obj generate big object files\n"));
10079 fprintf (stream
, _("\
10080 -momit-lock-prefix=[no|yes]\n\
10081 strip all lock prefixes\n"));
10084 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10085 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10086 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10088 /* Pick the target format to use. */
10091 i386_target_format (void)
10093 if (!strncmp (default_arch
, "x86_64", 6))
10095 update_code_flag (CODE_64BIT
, 1);
10096 if (default_arch
[6] == '\0')
10097 x86_elf_abi
= X86_64_ABI
;
10099 x86_elf_abi
= X86_64_X32_ABI
;
10101 else if (!strcmp (default_arch
, "i386"))
10102 update_code_flag (CODE_32BIT
, 1);
10104 as_fatal (_("unknown architecture"));
10106 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10107 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10108 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10109 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10111 switch (OUTPUT_FLAVOR
)
10113 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10114 case bfd_target_aout_flavour
:
10115 return AOUT_TARGET_FORMAT
;
10117 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10118 # if defined (TE_PE) || defined (TE_PEP)
10119 case bfd_target_coff_flavour
:
10120 if (flag_code
== CODE_64BIT
)
10121 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10124 # elif defined (TE_GO32)
10125 case bfd_target_coff_flavour
:
10126 return "coff-go32";
10128 case bfd_target_coff_flavour
:
10129 return "coff-i386";
10132 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10133 case bfd_target_elf_flavour
:
10135 const char *format
;
10137 switch (x86_elf_abi
)
10140 format
= ELF_TARGET_FORMAT
;
10143 use_rela_relocations
= 1;
10145 format
= ELF_TARGET_FORMAT64
;
10147 case X86_64_X32_ABI
:
10148 use_rela_relocations
= 1;
10150 disallow_64bit_reloc
= 1;
10151 format
= ELF_TARGET_FORMAT32
;
10154 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10156 if (x86_elf_abi
!= X86_64_ABI
)
10157 as_fatal (_("Intel L1OM is 64bit only"));
10158 return ELF_TARGET_L1OM_FORMAT
;
10160 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10162 if (x86_elf_abi
!= X86_64_ABI
)
10163 as_fatal (_("Intel K1OM is 64bit only"));
10164 return ELF_TARGET_K1OM_FORMAT
;
10170 #if defined (OBJ_MACH_O)
10171 case bfd_target_mach_o_flavour
:
10172 if (flag_code
== CODE_64BIT
)
10174 use_rela_relocations
= 1;
10176 return "mach-o-x86-64";
10179 return "mach-o-i386";
10187 #endif /* OBJ_MAYBE_ more than one */
10189 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10191 i386_elf_emit_arch_note (void)
10193 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10196 asection
*seg
= now_seg
;
10197 subsegT subseg
= now_subseg
;
10198 Elf_Internal_Note i_note
;
10199 Elf_External_Note e_note
;
10200 asection
*note_secp
;
10203 /* Create the .note section. */
10204 note_secp
= subseg_new (".note", 0);
10205 bfd_set_section_flags (stdoutput
,
10207 SEC_HAS_CONTENTS
| SEC_READONLY
);
10209 /* Process the arch string. */
10210 len
= strlen (cpu_arch_name
);
10212 i_note
.namesz
= len
+ 1;
10214 i_note
.type
= NT_ARCH
;
10215 p
= frag_more (sizeof (e_note
.namesz
));
10216 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10217 p
= frag_more (sizeof (e_note
.descsz
));
10218 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10219 p
= frag_more (sizeof (e_note
.type
));
10220 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10221 p
= frag_more (len
+ 1);
10222 strcpy (p
, cpu_arch_name
);
10224 frag_align (2, 0, 0);
10226 subseg_set (seg
, subseg
);
10232 md_undefined_symbol (char *name
)
10234 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10235 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10236 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10237 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10241 if (symbol_find (name
))
10242 as_bad (_("GOT already in symbol table"));
10243 GOT_symbol
= symbol_new (name
, undefined_section
,
10244 (valueT
) 0, &zero_address_frag
);
10251 /* Round up a section size to the appropriate boundary. */
10254 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10256 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10257 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10259 /* For a.out, force the section size to be aligned. If we don't do
10260 this, BFD will align it for us, but it will not write out the
10261 final bytes of the section. This may be a bug in BFD, but it is
10262 easier to fix it here since that is how the other a.out targets
10266 align
= bfd_get_section_alignment (stdoutput
, segment
);
10267 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10274 /* On the i386, PC-relative offsets are relative to the start of the
10275 next instruction. That is, the address of the offset, plus its
10276 size, since the offset is always the last part of the insn. */
10279 md_pcrel_from (fixS
*fixP
)
10281 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10287 s_bss (int ignore ATTRIBUTE_UNUSED
)
10291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10293 obj_elf_section_change_hook ();
10295 temp
= get_absolute_expression ();
10296 subseg_set (bss_section
, (subsegT
) temp
);
10297 demand_empty_rest_of_line ();
10303 i386_validate_fix (fixS
*fixp
)
10305 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10307 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10311 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10316 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10318 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10320 fixp
->fx_subsy
= 0;
10325 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10328 bfd_reloc_code_real_type code
;
10330 switch (fixp
->fx_r_type
)
10332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10333 case BFD_RELOC_SIZE32
:
10334 case BFD_RELOC_SIZE64
:
10335 if (S_IS_DEFINED (fixp
->fx_addsy
)
10336 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10338 /* Resolve size relocation against local symbol to size of
10339 the symbol plus addend. */
10340 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10341 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10342 && !fits_in_unsigned_long (value
))
10343 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10344 _("symbol size computation overflow"));
10345 fixp
->fx_addsy
= NULL
;
10346 fixp
->fx_subsy
= NULL
;
10347 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10352 case BFD_RELOC_X86_64_PLT32
:
10353 case BFD_RELOC_X86_64_PLT32_BND
:
10354 case BFD_RELOC_X86_64_GOT32
:
10355 case BFD_RELOC_X86_64_GOTPCREL
:
10356 case BFD_RELOC_386_PLT32
:
10357 case BFD_RELOC_386_GOT32
:
10358 case BFD_RELOC_386_GOTOFF
:
10359 case BFD_RELOC_386_GOTPC
:
10360 case BFD_RELOC_386_TLS_GD
:
10361 case BFD_RELOC_386_TLS_LDM
:
10362 case BFD_RELOC_386_TLS_LDO_32
:
10363 case BFD_RELOC_386_TLS_IE_32
:
10364 case BFD_RELOC_386_TLS_IE
:
10365 case BFD_RELOC_386_TLS_GOTIE
:
10366 case BFD_RELOC_386_TLS_LE_32
:
10367 case BFD_RELOC_386_TLS_LE
:
10368 case BFD_RELOC_386_TLS_GOTDESC
:
10369 case BFD_RELOC_386_TLS_DESC_CALL
:
10370 case BFD_RELOC_X86_64_TLSGD
:
10371 case BFD_RELOC_X86_64_TLSLD
:
10372 case BFD_RELOC_X86_64_DTPOFF32
:
10373 case BFD_RELOC_X86_64_DTPOFF64
:
10374 case BFD_RELOC_X86_64_GOTTPOFF
:
10375 case BFD_RELOC_X86_64_TPOFF32
:
10376 case BFD_RELOC_X86_64_TPOFF64
:
10377 case BFD_RELOC_X86_64_GOTOFF64
:
10378 case BFD_RELOC_X86_64_GOTPC32
:
10379 case BFD_RELOC_X86_64_GOT64
:
10380 case BFD_RELOC_X86_64_GOTPCREL64
:
10381 case BFD_RELOC_X86_64_GOTPC64
:
10382 case BFD_RELOC_X86_64_GOTPLT64
:
10383 case BFD_RELOC_X86_64_PLTOFF64
:
10384 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10385 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10386 case BFD_RELOC_RVA
:
10387 case BFD_RELOC_VTABLE_ENTRY
:
10388 case BFD_RELOC_VTABLE_INHERIT
:
10390 case BFD_RELOC_32_SECREL
:
10392 code
= fixp
->fx_r_type
;
10394 case BFD_RELOC_X86_64_32S
:
10395 if (!fixp
->fx_pcrel
)
10397 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10398 code
= fixp
->fx_r_type
;
10402 if (fixp
->fx_pcrel
)
10404 switch (fixp
->fx_size
)
10407 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10408 _("can not do %d byte pc-relative relocation"),
10410 code
= BFD_RELOC_32_PCREL
;
10412 case 1: code
= BFD_RELOC_8_PCREL
; break;
10413 case 2: code
= BFD_RELOC_16_PCREL
; break;
10415 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10416 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10419 case 8: code
= BFD_RELOC_64_PCREL
; break;
10425 switch (fixp
->fx_size
)
10428 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10429 _("can not do %d byte relocation"),
10431 code
= BFD_RELOC_32
;
10433 case 1: code
= BFD_RELOC_8
; break;
10434 case 2: code
= BFD_RELOC_16
; break;
10435 case 4: code
= BFD_RELOC_32
; break;
10437 case 8: code
= BFD_RELOC_64
; break;
10444 if ((code
== BFD_RELOC_32
10445 || code
== BFD_RELOC_32_PCREL
10446 || code
== BFD_RELOC_X86_64_32S
)
10448 && fixp
->fx_addsy
== GOT_symbol
)
10451 code
= BFD_RELOC_386_GOTPC
;
10453 code
= BFD_RELOC_X86_64_GOTPC32
;
10455 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10457 && fixp
->fx_addsy
== GOT_symbol
)
10459 code
= BFD_RELOC_X86_64_GOTPC64
;
10462 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10463 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10464 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10466 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10468 if (!use_rela_relocations
)
10470 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10471 vtable entry to be used in the relocation's section offset. */
10472 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10473 rel
->address
= fixp
->fx_offset
;
10474 #if defined (OBJ_COFF) && defined (TE_PE)
10475 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10476 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10481 /* Use the rela in 64bit mode. */
10484 if (disallow_64bit_reloc
)
10487 case BFD_RELOC_X86_64_DTPOFF64
:
10488 case BFD_RELOC_X86_64_TPOFF64
:
10489 case BFD_RELOC_64_PCREL
:
10490 case BFD_RELOC_X86_64_GOTOFF64
:
10491 case BFD_RELOC_X86_64_GOT64
:
10492 case BFD_RELOC_X86_64_GOTPCREL64
:
10493 case BFD_RELOC_X86_64_GOTPC64
:
10494 case BFD_RELOC_X86_64_GOTPLT64
:
10495 case BFD_RELOC_X86_64_PLTOFF64
:
10496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10497 _("cannot represent relocation type %s in x32 mode"),
10498 bfd_get_reloc_code_name (code
));
10504 if (!fixp
->fx_pcrel
)
10505 rel
->addend
= fixp
->fx_offset
;
10509 case BFD_RELOC_X86_64_PLT32
:
10510 case BFD_RELOC_X86_64_PLT32_BND
:
10511 case BFD_RELOC_X86_64_GOT32
:
10512 case BFD_RELOC_X86_64_GOTPCREL
:
10513 case BFD_RELOC_X86_64_TLSGD
:
10514 case BFD_RELOC_X86_64_TLSLD
:
10515 case BFD_RELOC_X86_64_GOTTPOFF
:
10516 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10517 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10518 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10521 rel
->addend
= (section
->vma
10523 + fixp
->fx_addnumber
10524 + md_pcrel_from (fixp
));
10529 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10530 if (rel
->howto
== NULL
)
10532 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10533 _("cannot represent relocation type %s"),
10534 bfd_get_reloc_code_name (code
));
10535 /* Set howto to a garbage value so that we can keep going. */
10536 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10537 gas_assert (rel
->howto
!= NULL
);
10543 #include "tc-i386-intel.c"
10546 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10548 int saved_naked_reg
;
10549 char saved_register_dot
;
10551 saved_naked_reg
= allow_naked_reg
;
10552 allow_naked_reg
= 1;
10553 saved_register_dot
= register_chars
['.'];
10554 register_chars
['.'] = '.';
10555 allow_pseudo_reg
= 1;
10556 expression_and_evaluate (exp
);
10557 allow_pseudo_reg
= 0;
10558 register_chars
['.'] = saved_register_dot
;
10559 allow_naked_reg
= saved_naked_reg
;
10561 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10563 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10565 exp
->X_op
= O_constant
;
10566 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10567 .dw2_regnum
[flag_code
>> 1];
10570 exp
->X_op
= O_illegal
;
10575 tc_x86_frame_initial_instructions (void)
10577 static unsigned int sp_regno
[2];
10579 if (!sp_regno
[flag_code
>> 1])
10581 char *saved_input
= input_line_pointer
;
10582 char sp
[][4] = {"esp", "rsp"};
10585 input_line_pointer
= sp
[flag_code
>> 1];
10586 tc_x86_parse_to_dw2regnum (&exp
);
10587 gas_assert (exp
.X_op
== O_constant
);
10588 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10589 input_line_pointer
= saved_input
;
10592 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10593 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10597 x86_dwarf2_addr_size (void)
10599 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10600 if (x86_elf_abi
== X86_64_X32_ABI
)
10603 return bfd_arch_bits_per_address (stdoutput
) / 8;
10607 i386_elf_section_type (const char *str
, size_t len
)
10609 if (flag_code
== CODE_64BIT
10610 && len
== sizeof ("unwind") - 1
10611 && strncmp (str
, "unwind", 6) == 0)
10612 return SHT_X86_64_UNWIND
;
10619 i386_solaris_fix_up_eh_frame (segT sec
)
10621 if (flag_code
== CODE_64BIT
)
10622 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10628 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10632 exp
.X_op
= O_secrel
;
10633 exp
.X_add_symbol
= symbol
;
10634 exp
.X_add_number
= 0;
10635 emit_expr (&exp
, size
);
10639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10640 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10643 x86_64_section_letter (int letter
, char **ptr_msg
)
10645 if (flag_code
== CODE_64BIT
)
10648 return SHF_X86_64_LARGE
;
10650 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10653 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10658 x86_64_section_word (char *str
, size_t len
)
10660 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10661 return SHF_X86_64_LARGE
;
10667 handle_large_common (int small ATTRIBUTE_UNUSED
)
10669 if (flag_code
!= CODE_64BIT
)
10671 s_comm_internal (0, elf_common_parse
);
10672 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10676 static segT lbss_section
;
10677 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10678 asection
*saved_bss_section
= bss_section
;
10680 if (lbss_section
== NULL
)
10682 flagword applicable
;
10683 segT seg
= now_seg
;
10684 subsegT subseg
= now_subseg
;
10686 /* The .lbss section is for local .largecomm symbols. */
10687 lbss_section
= subseg_new (".lbss", 0);
10688 applicable
= bfd_applicable_section_flags (stdoutput
);
10689 bfd_set_section_flags (stdoutput
, lbss_section
,
10690 applicable
& SEC_ALLOC
);
10691 seg_info (lbss_section
)->bss
= 1;
10693 subseg_set (seg
, subseg
);
10696 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10697 bss_section
= lbss_section
;
10699 s_comm_internal (0, elf_common_parse
);
10701 elf_com_section_ptr
= saved_com_section_ptr
;
10702 bss_section
= saved_bss_section
;
10705 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */