i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifdef HAVE_LIMITS_H
37 #include <limits.h>
38 #else
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
41 #endif
42 #ifndef INT_MAX
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
44 #endif
45 #endif
46
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
49 #endif
50
51 #ifndef DEFAULT_ARCH
52 #define DEFAULT_ARCH "i386"
53 #endif
54
55 #ifndef INLINE
56 #if __GNUC__ >= 2
57 #define INLINE __inline__
58 #else
59 #define INLINE
60 #endif
61 #endif
62
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
68 #define WAIT_PREFIX 0
69 #define SEG_PREFIX 1
70 #define ADDR_PREFIX 2
71 #define DATA_PREFIX 3
72 #define REP_PREFIX 4
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
75 #define LOCK_PREFIX 5
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
83
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 in instructions. */
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94
95 #define END_OF_INSN '\0'
96
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
99
100 /*
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
105 END.
106 */
107 typedef struct
108 {
109 const insn_template *start;
110 const insn_template *end;
111 }
112 templates;
113
114 /* 386 operand encoding bytes: see 386 book for details of this. */
115 typedef struct
116 {
117 unsigned int regmem; /* codes register or memory operand */
118 unsigned int reg; /* codes register operand (or extended opcode) */
119 unsigned int mode; /* how to interpret regmem & reg */
120 }
121 modrm_byte;
122
123 /* x86-64 extension prefix. */
124 typedef int rex_byte;
125
126 /* 386 opcode byte to code indirect addressing. */
127 typedef struct
128 {
129 unsigned base;
130 unsigned index;
131 unsigned scale;
132 }
133 sib_byte;
134
135 /* x86 arch names, types and features */
136 typedef struct
137 {
138 const char *name; /* arch name */
139 unsigned int len; /* arch string length */
140 enum processor_type type; /* arch type */
141 i386_cpu_flags flags; /* cpu feature flags */
142 unsigned int skip; /* show_arch should skip this. */
143 }
144 arch_entry;
145
146 /* Used to turn off indicated flags. */
147 typedef struct
148 {
149 const char *name; /* arch name */
150 unsigned int len; /* arch string length */
151 i386_cpu_flags flags; /* cpu feature flags */
152 }
153 noarch_entry;
154
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
163 #ifdef TE_PE
164 static void pe_directive_secrel (int);
165 #endif
166 static void signed_cons (int);
167 static char *output_invalid (int c);
168 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
169 const char *);
170 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
171 const char *);
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS *);
175 static int i386_intel_parse_name (const char *, expressionS *);
176 static const reg_entry *parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template *match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry *build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS *, offsetT);
196 static void output_disp (fragS *, offsetT);
197 #ifndef I386COFF
198 static void s_bss (int);
199 #endif
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED);
202
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
209 #endif
210
211 static const char *default_arch = DEFAULT_ARCH;
212
213 /* This struct describes rounding control and SAE in the instruction. */
214 struct RC_Operation
215 {
216 enum rc_type
217 {
218 rne = 0,
219 rd,
220 ru,
221 rz,
222 saeonly
223 } type;
224 int operand;
225 };
226
227 static struct RC_Operation rc_op;
228
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
233 {
234 const reg_entry *mask;
235 unsigned int zeroing;
236 /* The operand where this operation is associated. */
237 int operand;
238 };
239
240 static struct Mask_Operation mask_op;
241
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
243 broadcast factor. */
244 struct Broadcast_Operation
245 {
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
247 int type;
248
249 /* Index of broadcasted operand. */
250 int operand;
251
252 /* Number of bytes to broadcast. */
253 int bytes;
254 };
255
256 static struct Broadcast_Operation broadcast_op;
257
258 /* VEX prefix. */
259 typedef struct
260 {
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes[4];
263 unsigned int length;
264 /* Destination or source register specifier. */
265 const reg_entry *register_specifier;
266 } vex_prefix;
267
268 /* 'md_assemble ()' gathers together information and puts it into a
269 i386_insn. */
270
271 union i386_op
272 {
273 expressionS *disps;
274 expressionS *imms;
275 const reg_entry *regs;
276 };
277
278 enum i386_error
279 {
280 operand_size_mismatch,
281 operand_type_mismatch,
282 register_type_mismatch,
283 number_of_operands_mismatch,
284 invalid_instruction_suffix,
285 bad_imm4,
286 unsupported_with_intel_mnemonic,
287 unsupported_syntax,
288 unsupported,
289 invalid_vsib_address,
290 invalid_vector_register_set,
291 unsupported_vector_index_register,
292 unsupported_broadcast,
293 broadcast_needed,
294 unsupported_masking,
295 mask_not_on_destination,
296 no_default_mask,
297 unsupported_rc_sae,
298 rc_sae_operand_not_last_imm,
299 invalid_register_operand,
300 };
301
302 struct _i386_insn
303 {
304 /* TM holds the template for the insn were currently assembling. */
305 insn_template tm;
306
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
309 char suffix;
310
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands;
313
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
316 operands. */
317 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
318
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types[MAX_OPERANDS];
322
323 /* Displacement expression, immediate expression, or register for each
324 operand. */
325 union i386_op op[MAX_OPERANDS];
326
327 /* Flags for operands. */
328 unsigned int flags[MAX_OPERANDS];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
331
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
334
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry *base_reg;
338 const reg_entry *index_reg;
339 unsigned int log2_scale_factor;
340
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry *seg[2];
344
345 /* Copied first memory operand string, for re-checking. */
346 char *memop1_string;
347
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes;
351 unsigned char prefix[MAX_PREFIXES];
352
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form;
355
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute;
358
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx;
361
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm;
364
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm;
367
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm;
370
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc;
373
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
376 modrm_byte rm;
377 rex_byte rex;
378 rex_byte vrex;
379 sib_byte sib;
380 vex_prefix vex;
381
382 /* Masking attributes. */
383 struct Mask_Operation *mask;
384
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation *rounding;
387
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation *broadcast;
390
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift;
393
394 /* Prefer load or store in encoding. */
395 enum
396 {
397 dir_encoding_default = 0,
398 dir_encoding_load,
399 dir_encoding_store,
400 dir_encoding_swap
401 } dir_encoding;
402
403 /* Prefer 8bit or 32bit displacement in encoding. */
404 enum
405 {
406 disp_encoding_default = 0,
407 disp_encoding_8bit,
408 disp_encoding_32bit
409 } disp_encoding;
410
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding;
413
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize;
416
417 /* How to encode vector instructions. */
418 enum
419 {
420 vex_encoding_default = 0,
421 vex_encoding_vex,
422 vex_encoding_vex3,
423 vex_encoding_evex
424 } vec_encoding;
425
426 /* REP prefix. */
427 const char *rep_prefix;
428
429 /* HLE prefix. */
430 const char *hle_prefix;
431
432 /* Have BND prefix. */
433 const char *bnd_prefix;
434
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix;
437
438 /* Error message. */
439 enum i386_error error;
440 };
441
442 typedef struct _i386_insn i386_insn;
443
444 /* Link RC type with corresponding string, that'll be looked for in
445 asm. */
446 struct RC_name
447 {
448 enum rc_type type;
449 const char *name;
450 unsigned int len;
451 };
452
453 static const struct RC_name RC_NamesTable[] =
454 {
455 { rne, STRING_COMMA_LEN ("rn-sae") },
456 { rd, STRING_COMMA_LEN ("rd-sae") },
457 { ru, STRING_COMMA_LEN ("ru-sae") },
458 { rz, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly, STRING_COMMA_LEN ("sae") },
460 };
461
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars[] = "*%-([{}"
465 #ifdef LEX_AT
466 "@"
467 #endif
468 #ifdef LEX_QM
469 "?"
470 #endif
471 ;
472
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars = "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
487
488 #else
489 const char *i386_comment_chars = "#";
490 #define PREFIX_SEPARATOR '/'
491 #endif
492
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars[] = "#/";
502
503 const char line_separator_chars[] = ";";
504
505 /* Chars that can be used to separate mant from exp in floating point
506 nums. */
507 const char EXP_CHARS[] = "eE";
508
509 /* Chars that mean this number is a floating point constant
510 As in 0f12.456
511 or 0d1.2345e12. */
512 const char FLT_CHARS[] = "fFdDxX";
513
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars[256];
516 static char register_chars[256];
517 static char operand_chars[256];
518 static char identifier_chars[256];
519 static char digit_chars[256];
520
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
528
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
531
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack[32];
537 static char *save_stack_p;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
542
543 /* The instruction we're assembling. */
544 static i386_insn i;
545
546 /* Possible templates for current insn. */
547 static const templates *current_templates;
548
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
551 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
552
553 /* Current operand we are working on. */
554 static int this_operand = -1;
555
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
557 these. */
558
559 enum flag_code {
560 CODE_32BIT,
561 CODE_16BIT,
562 CODE_64BIT };
563
564 static enum flag_code flag_code;
565 static unsigned int object_64bit;
566 static unsigned int disallow_64bit_reloc;
567 static int use_rela_relocations = 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr;
570
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
574
575 /* The ELF ABI to use. */
576 enum x86_elf_abi
577 {
578 I386_ABI,
579 X86_64_ABI,
580 X86_64_X32_ABI
581 };
582
583 static enum x86_elf_abi x86_elf_abi = I386_ABI;
584 #endif
585
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj = 0;
589 #endif
590
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared = 0;
594 #endif
595
596 /* 1 for intel syntax,
597 0 if att syntax. */
598 static int intel_syntax = 0;
599
600 static enum x86_64_isa
601 {
602 amd64 = 1, /* AMD64 ISA. */
603 intel64 /* Intel64 ISA. */
604 } isa64;
605
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic = !SYSV386_COMPAT;
609
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg = 0;
612
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg = 0;
615
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
618 explicitly. */
619 static int add_bnd_prefix = 0;
620
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg = 0;
623
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix = 0;
627
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence = 0;
631
632 /* 1 if lfence should be inserted after every load. */
633 static int lfence_after_load = 0;
634
635 /* Non-zero if lfence should be inserted before indirect branch. */
636 static enum lfence_before_indirect_branch_kind
637 {
638 lfence_branch_none = 0,
639 lfence_branch_register,
640 lfence_branch_memory,
641 lfence_branch_all
642 }
643 lfence_before_indirect_branch;
644
645 /* Non-zero if lfence should be inserted before ret. */
646 static enum lfence_before_ret_kind
647 {
648 lfence_before_ret_none = 0,
649 lfence_before_ret_not,
650 lfence_before_ret_or
651 }
652 lfence_before_ret;
653
654 /* Types of previous instruction is .byte or prefix. */
655 static struct
656 {
657 segT seg;
658 const char *file;
659 const char *name;
660 unsigned int line;
661 enum last_insn_kind
662 {
663 last_insn_other = 0,
664 last_insn_directive,
665 last_insn_prefix
666 } kind;
667 } last_insn;
668
669 /* 1 if the assembler should generate relax relocations. */
670
671 static int generate_relax_relocations
672 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
673
674 static enum check_kind
675 {
676 check_none = 0,
677 check_warning,
678 check_error
679 }
680 sse_check, operand_check = check_warning;
681
682 /* Non-zero if branches should be aligned within power of 2 boundary. */
683 static int align_branch_power = 0;
684
685 /* Types of branches to align. */
686 enum align_branch_kind
687 {
688 align_branch_none = 0,
689 align_branch_jcc = 1,
690 align_branch_fused = 2,
691 align_branch_jmp = 3,
692 align_branch_call = 4,
693 align_branch_indirect = 5,
694 align_branch_ret = 6
695 };
696
697 /* Type bits of branches to align. */
698 enum align_branch_bit
699 {
700 align_branch_jcc_bit = 1 << align_branch_jcc,
701 align_branch_fused_bit = 1 << align_branch_fused,
702 align_branch_jmp_bit = 1 << align_branch_jmp,
703 align_branch_call_bit = 1 << align_branch_call,
704 align_branch_indirect_bit = 1 << align_branch_indirect,
705 align_branch_ret_bit = 1 << align_branch_ret
706 };
707
708 static unsigned int align_branch = (align_branch_jcc_bit
709 | align_branch_fused_bit
710 | align_branch_jmp_bit);
711
712 /* Types of condition jump used by macro-fusion. */
713 enum mf_jcc_kind
714 {
715 mf_jcc_jo = 0, /* base opcode 0x70 */
716 mf_jcc_jc, /* base opcode 0x72 */
717 mf_jcc_je, /* base opcode 0x74 */
718 mf_jcc_jna, /* base opcode 0x76 */
719 mf_jcc_js, /* base opcode 0x78 */
720 mf_jcc_jp, /* base opcode 0x7a */
721 mf_jcc_jl, /* base opcode 0x7c */
722 mf_jcc_jle, /* base opcode 0x7e */
723 };
724
725 /* Types of compare flag-modifying insntructions used by macro-fusion. */
726 enum mf_cmp_kind
727 {
728 mf_cmp_test_and, /* test/cmp */
729 mf_cmp_alu_cmp, /* add/sub/cmp */
730 mf_cmp_incdec /* inc/dec */
731 };
732
733 /* The maximum padding size for fused jcc. CMP like instruction can
734 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
735 prefixes. */
736 #define MAX_FUSED_JCC_PADDING_SIZE 20
737
738 /* The maximum number of prefixes added for an instruction. */
739 static unsigned int align_branch_prefix_size = 5;
740
741 /* Optimization:
742 1. Clear the REX_W bit with register operand if possible.
743 2. Above plus use 128bit vector instruction to clear the full vector
744 register.
745 */
746 static int optimize = 0;
747
748 /* Optimization:
749 1. Clear the REX_W bit with register operand if possible.
750 2. Above plus use 128bit vector instruction to clear the full vector
751 register.
752 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
753 "testb $imm7,%r8".
754 */
755 static int optimize_for_space = 0;
756
757 /* Register prefix used for error message. */
758 static const char *register_prefix = "%";
759
760 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
761 leave, push, and pop instructions so that gcc has the same stack
762 frame as in 32 bit mode. */
763 static char stackop_size = '\0';
764
765 /* Non-zero to optimize code alignment. */
766 int optimize_align_code = 1;
767
768 /* Non-zero to quieten some warnings. */
769 static int quiet_warnings = 0;
770
771 /* CPU name. */
772 static const char *cpu_arch_name = NULL;
773 static char *cpu_sub_arch_name = NULL;
774
775 /* CPU feature flags. */
776 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
777
778 /* If we have selected a cpu we are generating instructions for. */
779 static int cpu_arch_tune_set = 0;
780
781 /* Cpu we are generating instructions for. */
782 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
783
784 /* CPU feature flags of cpu we are generating instructions for. */
785 static i386_cpu_flags cpu_arch_tune_flags;
786
787 /* CPU instruction set architecture used. */
788 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
789
790 /* CPU feature flags of instruction set architecture used. */
791 i386_cpu_flags cpu_arch_isa_flags;
792
793 /* If set, conditional jumps are not automatically promoted to handle
794 larger than a byte offset. */
795 static unsigned int no_cond_jump_promotion = 0;
796
797 /* Encode SSE instructions with VEX prefix. */
798 static unsigned int sse2avx;
799
800 /* Encode scalar AVX instructions with specific vector length. */
801 static enum
802 {
803 vex128 = 0,
804 vex256
805 } avxscalar;
806
807 /* Encode VEX WIG instructions with specific vex.w. */
808 static enum
809 {
810 vexw0 = 0,
811 vexw1
812 } vexwig;
813
814 /* Encode scalar EVEX LIG instructions with specific vector length. */
815 static enum
816 {
817 evexl128 = 0,
818 evexl256,
819 evexl512
820 } evexlig;
821
822 /* Encode EVEX WIG instructions with specific evex.w. */
823 static enum
824 {
825 evexw0 = 0,
826 evexw1
827 } evexwig;
828
829 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
830 static enum rc_type evexrcig = rne;
831
832 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
833 static symbolS *GOT_symbol;
834
835 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
836 unsigned int x86_dwarf2_return_column;
837
838 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
839 int x86_cie_data_alignment;
840
841 /* Interface to relax_segment.
842 There are 3 major relax states for 386 jump insns because the
843 different types of jumps add different sizes to frags when we're
844 figuring out what sort of jump to choose to reach a given label.
845
846 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
847 branches which are handled by md_estimate_size_before_relax() and
848 i386_generic_table_relax_frag(). */
849
850 /* Types. */
851 #define UNCOND_JUMP 0
852 #define COND_JUMP 1
853 #define COND_JUMP86 2
854 #define BRANCH_PADDING 3
855 #define BRANCH_PREFIX 4
856 #define FUSED_JCC_PADDING 5
857
858 /* Sizes. */
859 #define CODE16 1
860 #define SMALL 0
861 #define SMALL16 (SMALL | CODE16)
862 #define BIG 2
863 #define BIG16 (BIG | CODE16)
864
865 #ifndef INLINE
866 #ifdef __GNUC__
867 #define INLINE __inline__
868 #else
869 #define INLINE
870 #endif
871 #endif
872
873 #define ENCODE_RELAX_STATE(type, size) \
874 ((relax_substateT) (((type) << 2) | (size)))
875 #define TYPE_FROM_RELAX_STATE(s) \
876 ((s) >> 2)
877 #define DISP_SIZE_FROM_RELAX_STATE(s) \
878 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
879
880 /* This table is used by relax_frag to promote short jumps to long
881 ones where necessary. SMALL (short) jumps may be promoted to BIG
882 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
883 don't allow a short jump in a 32 bit code segment to be promoted to
884 a 16 bit offset jump because it's slower (requires data size
885 prefix), and doesn't work, unless the destination is in the bottom
886 64k of the code segment (The top 16 bits of eip are zeroed). */
887
888 const relax_typeS md_relax_table[] =
889 {
890 /* The fields are:
891 1) most positive reach of this state,
892 2) most negative reach of this state,
893 3) how many bytes this mode will have in the variable part of the frag
894 4) which index into the table to try if we can't fit into this one. */
895
896 /* UNCOND_JUMP states. */
897 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
898 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
899 /* dword jmp adds 4 bytes to frag:
900 0 extra opcode bytes, 4 displacement bytes. */
901 {0, 0, 4, 0},
902 /* word jmp adds 2 byte2 to frag:
903 0 extra opcode bytes, 2 displacement bytes. */
904 {0, 0, 2, 0},
905
906 /* COND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
909 /* dword conditionals adds 5 bytes to frag:
910 1 extra opcode byte, 4 displacement bytes. */
911 {0, 0, 5, 0},
912 /* word conditionals add 3 bytes to frag:
913 1 extra opcode byte, 2 displacement bytes. */
914 {0, 0, 3, 0},
915
916 /* COND_JUMP86 states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
921 {0, 0, 5, 0},
922 /* word conditionals add 4 bytes to frag:
923 1 displacement byte and a 3 byte long branch insn. */
924 {0, 0, 4, 0}
925 };
926
927 static const arch_entry cpu_arch[] =
928 {
929 /* Do not replace the first two entries - i386_target_format()
930 relies on them being there in this order. */
931 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
932 CPU_GENERIC32_FLAGS, 0 },
933 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
934 CPU_GENERIC64_FLAGS, 0 },
935 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
936 CPU_NONE_FLAGS, 0 },
937 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
938 CPU_I186_FLAGS, 0 },
939 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
940 CPU_I286_FLAGS, 0 },
941 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
942 CPU_I386_FLAGS, 0 },
943 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
944 CPU_I486_FLAGS, 0 },
945 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
946 CPU_I586_FLAGS, 0 },
947 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
948 CPU_I686_FLAGS, 0 },
949 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
950 CPU_I586_FLAGS, 0 },
951 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
952 CPU_PENTIUMPRO_FLAGS, 0 },
953 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
954 CPU_P2_FLAGS, 0 },
955 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
956 CPU_P3_FLAGS, 0 },
957 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
958 CPU_P4_FLAGS, 0 },
959 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
960 CPU_CORE_FLAGS, 0 },
961 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
962 CPU_NOCONA_FLAGS, 0 },
963 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
964 CPU_CORE_FLAGS, 1 },
965 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
966 CPU_CORE_FLAGS, 0 },
967 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
968 CPU_CORE2_FLAGS, 1 },
969 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
970 CPU_CORE2_FLAGS, 0 },
971 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
972 CPU_COREI7_FLAGS, 0 },
973 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
974 CPU_L1OM_FLAGS, 0 },
975 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
976 CPU_K1OM_FLAGS, 0 },
977 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
978 CPU_IAMCU_FLAGS, 0 },
979 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
980 CPU_K6_FLAGS, 0 },
981 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
982 CPU_K6_2_FLAGS, 0 },
983 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
984 CPU_ATHLON_FLAGS, 0 },
985 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
986 CPU_K8_FLAGS, 1 },
987 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
988 CPU_K8_FLAGS, 0 },
989 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
990 CPU_K8_FLAGS, 0 },
991 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
992 CPU_AMDFAM10_FLAGS, 0 },
993 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
994 CPU_BDVER1_FLAGS, 0 },
995 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
996 CPU_BDVER2_FLAGS, 0 },
997 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
998 CPU_BDVER3_FLAGS, 0 },
999 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
1000 CPU_BDVER4_FLAGS, 0 },
1001 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
1002 CPU_ZNVER1_FLAGS, 0 },
1003 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
1004 CPU_ZNVER2_FLAGS, 0 },
1005 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
1006 CPU_BTVER1_FLAGS, 0 },
1007 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
1008 CPU_BTVER2_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
1010 CPU_8087_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
1012 CPU_287_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
1014 CPU_387_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
1016 CPU_687_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
1018 CPU_CMOV_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
1020 CPU_FXSR_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
1022 CPU_MMX_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
1024 CPU_SSE_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
1026 CPU_SSE2_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
1028 CPU_SSE3_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1030 CPU_SSE4A_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
1032 CPU_SSSE3_FLAGS, 0 },
1033 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
1034 CPU_SSE4_1_FLAGS, 0 },
1035 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
1036 CPU_SSE4_2_FLAGS, 0 },
1037 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
1038 CPU_SSE4_2_FLAGS, 0 },
1039 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
1040 CPU_AVX_FLAGS, 0 },
1041 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
1042 CPU_AVX2_FLAGS, 0 },
1043 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
1044 CPU_AVX512F_FLAGS, 0 },
1045 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
1046 CPU_AVX512CD_FLAGS, 0 },
1047 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
1048 CPU_AVX512ER_FLAGS, 0 },
1049 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
1050 CPU_AVX512PF_FLAGS, 0 },
1051 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
1052 CPU_AVX512DQ_FLAGS, 0 },
1053 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
1054 CPU_AVX512BW_FLAGS, 0 },
1055 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
1056 CPU_AVX512VL_FLAGS, 0 },
1057 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
1058 CPU_VMX_FLAGS, 0 },
1059 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
1060 CPU_VMFUNC_FLAGS, 0 },
1061 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
1062 CPU_SMX_FLAGS, 0 },
1063 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
1064 CPU_XSAVE_FLAGS, 0 },
1065 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
1066 CPU_XSAVEOPT_FLAGS, 0 },
1067 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
1068 CPU_XSAVEC_FLAGS, 0 },
1069 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
1070 CPU_XSAVES_FLAGS, 0 },
1071 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
1072 CPU_AES_FLAGS, 0 },
1073 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
1074 CPU_PCLMUL_FLAGS, 0 },
1075 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
1076 CPU_PCLMUL_FLAGS, 1 },
1077 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
1078 CPU_FSGSBASE_FLAGS, 0 },
1079 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
1080 CPU_RDRND_FLAGS, 0 },
1081 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
1082 CPU_F16C_FLAGS, 0 },
1083 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
1084 CPU_BMI2_FLAGS, 0 },
1085 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
1086 CPU_FMA_FLAGS, 0 },
1087 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
1088 CPU_FMA4_FLAGS, 0 },
1089 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
1090 CPU_XOP_FLAGS, 0 },
1091 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
1092 CPU_LWP_FLAGS, 0 },
1093 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
1094 CPU_MOVBE_FLAGS, 0 },
1095 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
1096 CPU_CX16_FLAGS, 0 },
1097 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
1098 CPU_EPT_FLAGS, 0 },
1099 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
1100 CPU_LZCNT_FLAGS, 0 },
1101 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN,
1102 CPU_POPCNT_FLAGS, 0 },
1103 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
1104 CPU_HLE_FLAGS, 0 },
1105 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
1106 CPU_RTM_FLAGS, 0 },
1107 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
1108 CPU_INVPCID_FLAGS, 0 },
1109 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
1110 CPU_CLFLUSH_FLAGS, 0 },
1111 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
1112 CPU_NOP_FLAGS, 0 },
1113 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
1114 CPU_SYSCALL_FLAGS, 0 },
1115 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
1116 CPU_RDTSCP_FLAGS, 0 },
1117 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
1118 CPU_3DNOW_FLAGS, 0 },
1119 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
1120 CPU_3DNOWA_FLAGS, 0 },
1121 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
1122 CPU_PADLOCK_FLAGS, 0 },
1123 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
1124 CPU_SVME_FLAGS, 1 },
1125 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
1126 CPU_SVME_FLAGS, 0 },
1127 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1128 CPU_SSE4A_FLAGS, 0 },
1129 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
1130 CPU_ABM_FLAGS, 0 },
1131 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
1132 CPU_BMI_FLAGS, 0 },
1133 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
1134 CPU_TBM_FLAGS, 0 },
1135 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
1136 CPU_ADX_FLAGS, 0 },
1137 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
1138 CPU_RDSEED_FLAGS, 0 },
1139 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1140 CPU_PRFCHW_FLAGS, 0 },
1141 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1142 CPU_SMAP_FLAGS, 0 },
1143 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1144 CPU_MPX_FLAGS, 0 },
1145 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1146 CPU_SHA_FLAGS, 0 },
1147 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1148 CPU_CLFLUSHOPT_FLAGS, 0 },
1149 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1150 CPU_PREFETCHWT1_FLAGS, 0 },
1151 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1152 CPU_SE1_FLAGS, 0 },
1153 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1154 CPU_CLWB_FLAGS, 0 },
1155 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1156 CPU_AVX512IFMA_FLAGS, 0 },
1157 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1158 CPU_AVX512VBMI_FLAGS, 0 },
1159 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1160 CPU_AVX512_4FMAPS_FLAGS, 0 },
1161 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1162 CPU_AVX512_4VNNIW_FLAGS, 0 },
1163 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1164 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1165 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1166 CPU_AVX512_VBMI2_FLAGS, 0 },
1167 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1168 CPU_AVX512_VNNI_FLAGS, 0 },
1169 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1170 CPU_AVX512_BITALG_FLAGS, 0 },
1171 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1172 CPU_CLZERO_FLAGS, 0 },
1173 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1174 CPU_MWAITX_FLAGS, 0 },
1175 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1176 CPU_OSPKE_FLAGS, 0 },
1177 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1178 CPU_RDPID_FLAGS, 0 },
1179 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1180 CPU_PTWRITE_FLAGS, 0 },
1181 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1182 CPU_IBT_FLAGS, 0 },
1183 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1184 CPU_SHSTK_FLAGS, 0 },
1185 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1186 CPU_GFNI_FLAGS, 0 },
1187 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1188 CPU_VAES_FLAGS, 0 },
1189 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1190 CPU_VPCLMULQDQ_FLAGS, 0 },
1191 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1192 CPU_WBNOINVD_FLAGS, 0 },
1193 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1194 CPU_PCONFIG_FLAGS, 0 },
1195 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1196 CPU_WAITPKG_FLAGS, 0 },
1197 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1198 CPU_CLDEMOTE_FLAGS, 0 },
1199 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1200 CPU_MOVDIRI_FLAGS, 0 },
1201 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1202 CPU_MOVDIR64B_FLAGS, 0 },
1203 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
1204 CPU_AVX512_BF16_FLAGS, 0 },
1205 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
1206 CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
1207 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
1208 CPU_ENQCMD_FLAGS, 0 },
1209 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN,
1210 CPU_RDPRU_FLAGS, 0 },
1211 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN,
1212 CPU_MCOMMIT_FLAGS, 0 },
1213 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN,
1214 CPU_SEV_ES_FLAGS, 0 },
1215 };
1216
1217 static const noarch_entry cpu_noarch[] =
1218 {
1219 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1220 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1221 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1222 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1223 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1224 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1225 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1226 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1227 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1228 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1229 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS },
1230 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1231 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1232 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1233 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1234 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1235 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1236 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1237 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1238 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1239 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1240 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1241 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1242 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1243 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1244 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1245 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1246 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1247 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1248 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1249 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1250 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1251 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1252 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1253 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1254 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1255 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
1256 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS },
1257 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
1258 };
1259
1260 #ifdef I386COFF
1261 /* Like s_lcomm_internal in gas/read.c but the alignment string
1262 is allowed to be optional. */
1263
1264 static symbolS *
1265 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1266 {
1267 addressT align = 0;
1268
1269 SKIP_WHITESPACE ();
1270
1271 if (needs_align
1272 && *input_line_pointer == ',')
1273 {
1274 align = parse_align (needs_align - 1);
1275
1276 if (align == (addressT) -1)
1277 return NULL;
1278 }
1279 else
1280 {
1281 if (size >= 8)
1282 align = 3;
1283 else if (size >= 4)
1284 align = 2;
1285 else if (size >= 2)
1286 align = 1;
1287 else
1288 align = 0;
1289 }
1290
1291 bss_alloc (symbolP, size, align);
1292 return symbolP;
1293 }
1294
1295 static void
1296 pe_lcomm (int needs_align)
1297 {
1298 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1299 }
1300 #endif
1301
1302 const pseudo_typeS md_pseudo_table[] =
1303 {
1304 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1305 {"align", s_align_bytes, 0},
1306 #else
1307 {"align", s_align_ptwo, 0},
1308 #endif
1309 {"arch", set_cpu_arch, 0},
1310 #ifndef I386COFF
1311 {"bss", s_bss, 0},
1312 #else
1313 {"lcomm", pe_lcomm, 1},
1314 #endif
1315 {"ffloat", float_cons, 'f'},
1316 {"dfloat", float_cons, 'd'},
1317 {"tfloat", float_cons, 'x'},
1318 {"value", cons, 2},
1319 {"slong", signed_cons, 4},
1320 {"noopt", s_ignore, 0},
1321 {"optim", s_ignore, 0},
1322 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1323 {"code16", set_code_flag, CODE_16BIT},
1324 {"code32", set_code_flag, CODE_32BIT},
1325 #ifdef BFD64
1326 {"code64", set_code_flag, CODE_64BIT},
1327 #endif
1328 {"intel_syntax", set_intel_syntax, 1},
1329 {"att_syntax", set_intel_syntax, 0},
1330 {"intel_mnemonic", set_intel_mnemonic, 1},
1331 {"att_mnemonic", set_intel_mnemonic, 0},
1332 {"allow_index_reg", set_allow_index_reg, 1},
1333 {"disallow_index_reg", set_allow_index_reg, 0},
1334 {"sse_check", set_check, 0},
1335 {"operand_check", set_check, 1},
1336 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1337 {"largecomm", handle_large_common, 0},
1338 #else
1339 {"file", dwarf2_directive_file, 0},
1340 {"loc", dwarf2_directive_loc, 0},
1341 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1342 #endif
1343 #ifdef TE_PE
1344 {"secrel32", pe_directive_secrel, 0},
1345 #endif
1346 {0, 0, 0}
1347 };
1348
1349 /* For interface with expression (). */
1350 extern char *input_line_pointer;
1351
1352 /* Hash table for instruction mnemonic lookup. */
1353 static struct hash_control *op_hash;
1354
1355 /* Hash table for register lookup. */
1356 static struct hash_control *reg_hash;
1357 \f
1358 /* Various efficient no-op patterns for aligning code labels.
1359 Note: Don't try to assemble the instructions in the comments.
1360 0L and 0w are not legal. */
1361 static const unsigned char f32_1[] =
1362 {0x90}; /* nop */
1363 static const unsigned char f32_2[] =
1364 {0x66,0x90}; /* xchg %ax,%ax */
1365 static const unsigned char f32_3[] =
1366 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1367 static const unsigned char f32_4[] =
1368 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1369 static const unsigned char f32_6[] =
1370 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1371 static const unsigned char f32_7[] =
1372 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1373 static const unsigned char f16_3[] =
1374 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1375 static const unsigned char f16_4[] =
1376 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1377 static const unsigned char jump_disp8[] =
1378 {0xeb}; /* jmp disp8 */
1379 static const unsigned char jump32_disp32[] =
1380 {0xe9}; /* jmp disp32 */
1381 static const unsigned char jump16_disp32[] =
1382 {0x66,0xe9}; /* jmp disp32 */
1383 /* 32-bit NOPs patterns. */
1384 static const unsigned char *const f32_patt[] = {
1385 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1386 };
1387 /* 16-bit NOPs patterns. */
1388 static const unsigned char *const f16_patt[] = {
1389 f32_1, f32_2, f16_3, f16_4
1390 };
1391 /* nopl (%[re]ax) */
1392 static const unsigned char alt_3[] =
1393 {0x0f,0x1f,0x00};
1394 /* nopl 0(%[re]ax) */
1395 static const unsigned char alt_4[] =
1396 {0x0f,0x1f,0x40,0x00};
1397 /* nopl 0(%[re]ax,%[re]ax,1) */
1398 static const unsigned char alt_5[] =
1399 {0x0f,0x1f,0x44,0x00,0x00};
1400 /* nopw 0(%[re]ax,%[re]ax,1) */
1401 static const unsigned char alt_6[] =
1402 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1403 /* nopl 0L(%[re]ax) */
1404 static const unsigned char alt_7[] =
1405 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1406 /* nopl 0L(%[re]ax,%[re]ax,1) */
1407 static const unsigned char alt_8[] =
1408 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1409 /* nopw 0L(%[re]ax,%[re]ax,1) */
1410 static const unsigned char alt_9[] =
1411 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1412 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1413 static const unsigned char alt_10[] =
1414 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1415 /* data16 nopw %cs:0L(%eax,%eax,1) */
1416 static const unsigned char alt_11[] =
1417 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1418 /* 32-bit and 64-bit NOPs patterns. */
1419 static const unsigned char *const alt_patt[] = {
1420 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1421 alt_9, alt_10, alt_11
1422 };
1423
1424 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1425 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1426
1427 static void
1428 i386_output_nops (char *where, const unsigned char *const *patt,
1429 int count, int max_single_nop_size)
1430
1431 {
1432 /* Place the longer NOP first. */
1433 int last;
1434 int offset;
1435 const unsigned char *nops;
1436
1437 if (max_single_nop_size < 1)
1438 {
1439 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1440 max_single_nop_size);
1441 return;
1442 }
1443
1444 nops = patt[max_single_nop_size - 1];
1445
1446 /* Use the smaller one if the requsted one isn't available. */
1447 if (nops == NULL)
1448 {
1449 max_single_nop_size--;
1450 nops = patt[max_single_nop_size - 1];
1451 }
1452
1453 last = count % max_single_nop_size;
1454
1455 count -= last;
1456 for (offset = 0; offset < count; offset += max_single_nop_size)
1457 memcpy (where + offset, nops, max_single_nop_size);
1458
1459 if (last)
1460 {
1461 nops = patt[last - 1];
1462 if (nops == NULL)
1463 {
1464 /* Use the smaller one plus one-byte NOP if the needed one
1465 isn't available. */
1466 last--;
1467 nops = patt[last - 1];
1468 memcpy (where + offset, nops, last);
1469 where[offset + last] = *patt[0];
1470 }
1471 else
1472 memcpy (where + offset, nops, last);
1473 }
1474 }
1475
1476 static INLINE int
1477 fits_in_imm7 (offsetT num)
1478 {
1479 return (num & 0x7f) == num;
1480 }
1481
1482 static INLINE int
1483 fits_in_imm31 (offsetT num)
1484 {
1485 return (num & 0x7fffffff) == num;
1486 }
1487
1488 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1489 single NOP instruction LIMIT. */
1490
1491 void
1492 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1493 {
1494 const unsigned char *const *patt = NULL;
1495 int max_single_nop_size;
1496 /* Maximum number of NOPs before switching to jump over NOPs. */
1497 int max_number_of_nops;
1498
1499 switch (fragP->fr_type)
1500 {
1501 case rs_fill_nop:
1502 case rs_align_code:
1503 break;
1504 case rs_machine_dependent:
1505 /* Allow NOP padding for jumps and calls. */
1506 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
1507 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
1508 break;
1509 /* Fall through. */
1510 default:
1511 return;
1512 }
1513
1514 /* We need to decide which NOP sequence to use for 32bit and
1515 64bit. When -mtune= is used:
1516
1517 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1518 PROCESSOR_GENERIC32, f32_patt will be used.
1519 2. For the rest, alt_patt will be used.
1520
1521 When -mtune= isn't used, alt_patt will be used if
1522 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1523 be used.
1524
1525 When -march= or .arch is used, we can't use anything beyond
1526 cpu_arch_isa_flags. */
1527
1528 if (flag_code == CODE_16BIT)
1529 {
1530 patt = f16_patt;
1531 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1532 /* Limit number of NOPs to 2 in 16-bit mode. */
1533 max_number_of_nops = 2;
1534 }
1535 else
1536 {
1537 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1538 {
1539 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1540 switch (cpu_arch_tune)
1541 {
1542 case PROCESSOR_UNKNOWN:
1543 /* We use cpu_arch_isa_flags to check if we SHOULD
1544 optimize with nops. */
1545 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1546 patt = alt_patt;
1547 else
1548 patt = f32_patt;
1549 break;
1550 case PROCESSOR_PENTIUM4:
1551 case PROCESSOR_NOCONA:
1552 case PROCESSOR_CORE:
1553 case PROCESSOR_CORE2:
1554 case PROCESSOR_COREI7:
1555 case PROCESSOR_L1OM:
1556 case PROCESSOR_K1OM:
1557 case PROCESSOR_GENERIC64:
1558 case PROCESSOR_K6:
1559 case PROCESSOR_ATHLON:
1560 case PROCESSOR_K8:
1561 case PROCESSOR_AMDFAM10:
1562 case PROCESSOR_BD:
1563 case PROCESSOR_ZNVER:
1564 case PROCESSOR_BT:
1565 patt = alt_patt;
1566 break;
1567 case PROCESSOR_I386:
1568 case PROCESSOR_I486:
1569 case PROCESSOR_PENTIUM:
1570 case PROCESSOR_PENTIUMPRO:
1571 case PROCESSOR_IAMCU:
1572 case PROCESSOR_GENERIC32:
1573 patt = f32_patt;
1574 break;
1575 }
1576 }
1577 else
1578 {
1579 switch (fragP->tc_frag_data.tune)
1580 {
1581 case PROCESSOR_UNKNOWN:
1582 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1583 PROCESSOR_UNKNOWN. */
1584 abort ();
1585 break;
1586
1587 case PROCESSOR_I386:
1588 case PROCESSOR_I486:
1589 case PROCESSOR_PENTIUM:
1590 case PROCESSOR_IAMCU:
1591 case PROCESSOR_K6:
1592 case PROCESSOR_ATHLON:
1593 case PROCESSOR_K8:
1594 case PROCESSOR_AMDFAM10:
1595 case PROCESSOR_BD:
1596 case PROCESSOR_ZNVER:
1597 case PROCESSOR_BT:
1598 case PROCESSOR_GENERIC32:
1599 /* We use cpu_arch_isa_flags to check if we CAN optimize
1600 with nops. */
1601 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1602 patt = alt_patt;
1603 else
1604 patt = f32_patt;
1605 break;
1606 case PROCESSOR_PENTIUMPRO:
1607 case PROCESSOR_PENTIUM4:
1608 case PROCESSOR_NOCONA:
1609 case PROCESSOR_CORE:
1610 case PROCESSOR_CORE2:
1611 case PROCESSOR_COREI7:
1612 case PROCESSOR_L1OM:
1613 case PROCESSOR_K1OM:
1614 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1615 patt = alt_patt;
1616 else
1617 patt = f32_patt;
1618 break;
1619 case PROCESSOR_GENERIC64:
1620 patt = alt_patt;
1621 break;
1622 }
1623 }
1624
1625 if (patt == f32_patt)
1626 {
1627 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1628 /* Limit number of NOPs to 2 for older processors. */
1629 max_number_of_nops = 2;
1630 }
1631 else
1632 {
1633 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1634 /* Limit number of NOPs to 7 for newer processors. */
1635 max_number_of_nops = 7;
1636 }
1637 }
1638
1639 if (limit == 0)
1640 limit = max_single_nop_size;
1641
1642 if (fragP->fr_type == rs_fill_nop)
1643 {
1644 /* Output NOPs for .nop directive. */
1645 if (limit > max_single_nop_size)
1646 {
1647 as_bad_where (fragP->fr_file, fragP->fr_line,
1648 _("invalid single nop size: %d "
1649 "(expect within [0, %d])"),
1650 limit, max_single_nop_size);
1651 return;
1652 }
1653 }
1654 else if (fragP->fr_type != rs_machine_dependent)
1655 fragP->fr_var = count;
1656
1657 if ((count / max_single_nop_size) > max_number_of_nops)
1658 {
1659 /* Generate jump over NOPs. */
1660 offsetT disp = count - 2;
1661 if (fits_in_imm7 (disp))
1662 {
1663 /* Use "jmp disp8" if possible. */
1664 count = disp;
1665 where[0] = jump_disp8[0];
1666 where[1] = count;
1667 where += 2;
1668 }
1669 else
1670 {
1671 unsigned int size_of_jump;
1672
1673 if (flag_code == CODE_16BIT)
1674 {
1675 where[0] = jump16_disp32[0];
1676 where[1] = jump16_disp32[1];
1677 size_of_jump = 2;
1678 }
1679 else
1680 {
1681 where[0] = jump32_disp32[0];
1682 size_of_jump = 1;
1683 }
1684
1685 count -= size_of_jump + 4;
1686 if (!fits_in_imm31 (count))
1687 {
1688 as_bad_where (fragP->fr_file, fragP->fr_line,
1689 _("jump over nop padding out of range"));
1690 return;
1691 }
1692
1693 md_number_to_chars (where + size_of_jump, count, 4);
1694 where += size_of_jump + 4;
1695 }
1696 }
1697
1698 /* Generate multiple NOPs. */
1699 i386_output_nops (where, patt, count, limit);
1700 }
1701
1702 static INLINE int
1703 operand_type_all_zero (const union i386_operand_type *x)
1704 {
1705 switch (ARRAY_SIZE(x->array))
1706 {
1707 case 3:
1708 if (x->array[2])
1709 return 0;
1710 /* Fall through. */
1711 case 2:
1712 if (x->array[1])
1713 return 0;
1714 /* Fall through. */
1715 case 1:
1716 return !x->array[0];
1717 default:
1718 abort ();
1719 }
1720 }
1721
1722 static INLINE void
1723 operand_type_set (union i386_operand_type *x, unsigned int v)
1724 {
1725 switch (ARRAY_SIZE(x->array))
1726 {
1727 case 3:
1728 x->array[2] = v;
1729 /* Fall through. */
1730 case 2:
1731 x->array[1] = v;
1732 /* Fall through. */
1733 case 1:
1734 x->array[0] = v;
1735 /* Fall through. */
1736 break;
1737 default:
1738 abort ();
1739 }
1740
1741 x->bitfield.class = ClassNone;
1742 x->bitfield.instance = InstanceNone;
1743 }
1744
1745 static INLINE int
1746 operand_type_equal (const union i386_operand_type *x,
1747 const union i386_operand_type *y)
1748 {
1749 switch (ARRAY_SIZE(x->array))
1750 {
1751 case 3:
1752 if (x->array[2] != y->array[2])
1753 return 0;
1754 /* Fall through. */
1755 case 2:
1756 if (x->array[1] != y->array[1])
1757 return 0;
1758 /* Fall through. */
1759 case 1:
1760 return x->array[0] == y->array[0];
1761 break;
1762 default:
1763 abort ();
1764 }
1765 }
1766
1767 static INLINE int
1768 cpu_flags_all_zero (const union i386_cpu_flags *x)
1769 {
1770 switch (ARRAY_SIZE(x->array))
1771 {
1772 case 4:
1773 if (x->array[3])
1774 return 0;
1775 /* Fall through. */
1776 case 3:
1777 if (x->array[2])
1778 return 0;
1779 /* Fall through. */
1780 case 2:
1781 if (x->array[1])
1782 return 0;
1783 /* Fall through. */
1784 case 1:
1785 return !x->array[0];
1786 default:
1787 abort ();
1788 }
1789 }
1790
1791 static INLINE int
1792 cpu_flags_equal (const union i386_cpu_flags *x,
1793 const union i386_cpu_flags *y)
1794 {
1795 switch (ARRAY_SIZE(x->array))
1796 {
1797 case 4:
1798 if (x->array[3] != y->array[3])
1799 return 0;
1800 /* Fall through. */
1801 case 3:
1802 if (x->array[2] != y->array[2])
1803 return 0;
1804 /* Fall through. */
1805 case 2:
1806 if (x->array[1] != y->array[1])
1807 return 0;
1808 /* Fall through. */
1809 case 1:
1810 return x->array[0] == y->array[0];
1811 break;
1812 default:
1813 abort ();
1814 }
1815 }
1816
1817 static INLINE int
1818 cpu_flags_check_cpu64 (i386_cpu_flags f)
1819 {
1820 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1821 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1822 }
1823
1824 static INLINE i386_cpu_flags
1825 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1826 {
1827 switch (ARRAY_SIZE (x.array))
1828 {
1829 case 4:
1830 x.array [3] &= y.array [3];
1831 /* Fall through. */
1832 case 3:
1833 x.array [2] &= y.array [2];
1834 /* Fall through. */
1835 case 2:
1836 x.array [1] &= y.array [1];
1837 /* Fall through. */
1838 case 1:
1839 x.array [0] &= y.array [0];
1840 break;
1841 default:
1842 abort ();
1843 }
1844 return x;
1845 }
1846
1847 static INLINE i386_cpu_flags
1848 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1849 {
1850 switch (ARRAY_SIZE (x.array))
1851 {
1852 case 4:
1853 x.array [3] |= y.array [3];
1854 /* Fall through. */
1855 case 3:
1856 x.array [2] |= y.array [2];
1857 /* Fall through. */
1858 case 2:
1859 x.array [1] |= y.array [1];
1860 /* Fall through. */
1861 case 1:
1862 x.array [0] |= y.array [0];
1863 break;
1864 default:
1865 abort ();
1866 }
1867 return x;
1868 }
1869
1870 static INLINE i386_cpu_flags
1871 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1872 {
1873 switch (ARRAY_SIZE (x.array))
1874 {
1875 case 4:
1876 x.array [3] &= ~y.array [3];
1877 /* Fall through. */
1878 case 3:
1879 x.array [2] &= ~y.array [2];
1880 /* Fall through. */
1881 case 2:
1882 x.array [1] &= ~y.array [1];
1883 /* Fall through. */
1884 case 1:
1885 x.array [0] &= ~y.array [0];
1886 break;
1887 default:
1888 abort ();
1889 }
1890 return x;
1891 }
1892
1893 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
1894
1895 #define CPU_FLAGS_ARCH_MATCH 0x1
1896 #define CPU_FLAGS_64BIT_MATCH 0x2
1897
1898 #define CPU_FLAGS_PERFECT_MATCH \
1899 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1900
1901 /* Return CPU flags match bits. */
1902
1903 static int
1904 cpu_flags_match (const insn_template *t)
1905 {
1906 i386_cpu_flags x = t->cpu_flags;
1907 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1908
1909 x.bitfield.cpu64 = 0;
1910 x.bitfield.cpuno64 = 0;
1911
1912 if (cpu_flags_all_zero (&x))
1913 {
1914 /* This instruction is available on all archs. */
1915 match |= CPU_FLAGS_ARCH_MATCH;
1916 }
1917 else
1918 {
1919 /* This instruction is available only on some archs. */
1920 i386_cpu_flags cpu = cpu_arch_flags;
1921
1922 /* AVX512VL is no standalone feature - match it and then strip it. */
1923 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1924 return match;
1925 x.bitfield.cpuavx512vl = 0;
1926
1927 cpu = cpu_flags_and (x, cpu);
1928 if (!cpu_flags_all_zero (&cpu))
1929 {
1930 if (x.bitfield.cpuavx)
1931 {
1932 /* We need to check a few extra flags with AVX. */
1933 if (cpu.bitfield.cpuavx
1934 && (!t->opcode_modifier.sse2avx || sse2avx)
1935 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1936 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1937 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1938 match |= CPU_FLAGS_ARCH_MATCH;
1939 }
1940 else if (x.bitfield.cpuavx512f)
1941 {
1942 /* We need to check a few extra flags with AVX512F. */
1943 if (cpu.bitfield.cpuavx512f
1944 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1945 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1946 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1947 match |= CPU_FLAGS_ARCH_MATCH;
1948 }
1949 else
1950 match |= CPU_FLAGS_ARCH_MATCH;
1951 }
1952 }
1953 return match;
1954 }
1955
1956 static INLINE i386_operand_type
1957 operand_type_and (i386_operand_type x, i386_operand_type y)
1958 {
1959 if (x.bitfield.class != y.bitfield.class)
1960 x.bitfield.class = ClassNone;
1961 if (x.bitfield.instance != y.bitfield.instance)
1962 x.bitfield.instance = InstanceNone;
1963
1964 switch (ARRAY_SIZE (x.array))
1965 {
1966 case 3:
1967 x.array [2] &= y.array [2];
1968 /* Fall through. */
1969 case 2:
1970 x.array [1] &= y.array [1];
1971 /* Fall through. */
1972 case 1:
1973 x.array [0] &= y.array [0];
1974 break;
1975 default:
1976 abort ();
1977 }
1978 return x;
1979 }
1980
1981 static INLINE i386_operand_type
1982 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1983 {
1984 gas_assert (y.bitfield.class == ClassNone);
1985 gas_assert (y.bitfield.instance == InstanceNone);
1986
1987 switch (ARRAY_SIZE (x.array))
1988 {
1989 case 3:
1990 x.array [2] &= ~y.array [2];
1991 /* Fall through. */
1992 case 2:
1993 x.array [1] &= ~y.array [1];
1994 /* Fall through. */
1995 case 1:
1996 x.array [0] &= ~y.array [0];
1997 break;
1998 default:
1999 abort ();
2000 }
2001 return x;
2002 }
2003
2004 static INLINE i386_operand_type
2005 operand_type_or (i386_operand_type x, i386_operand_type y)
2006 {
2007 gas_assert (x.bitfield.class == ClassNone ||
2008 y.bitfield.class == ClassNone ||
2009 x.bitfield.class == y.bitfield.class);
2010 gas_assert (x.bitfield.instance == InstanceNone ||
2011 y.bitfield.instance == InstanceNone ||
2012 x.bitfield.instance == y.bitfield.instance);
2013
2014 switch (ARRAY_SIZE (x.array))
2015 {
2016 case 3:
2017 x.array [2] |= y.array [2];
2018 /* Fall through. */
2019 case 2:
2020 x.array [1] |= y.array [1];
2021 /* Fall through. */
2022 case 1:
2023 x.array [0] |= y.array [0];
2024 break;
2025 default:
2026 abort ();
2027 }
2028 return x;
2029 }
2030
2031 static INLINE i386_operand_type
2032 operand_type_xor (i386_operand_type x, i386_operand_type y)
2033 {
2034 gas_assert (y.bitfield.class == ClassNone);
2035 gas_assert (y.bitfield.instance == InstanceNone);
2036
2037 switch (ARRAY_SIZE (x.array))
2038 {
2039 case 3:
2040 x.array [2] ^= y.array [2];
2041 /* Fall through. */
2042 case 2:
2043 x.array [1] ^= y.array [1];
2044 /* Fall through. */
2045 case 1:
2046 x.array [0] ^= y.array [0];
2047 break;
2048 default:
2049 abort ();
2050 }
2051 return x;
2052 }
2053
2054 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
2055 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
2056 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
2057 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
2058 static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
2059 static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
2060 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
2061 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
2062 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
2063 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
2064 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
2065 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
2066 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
2067 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
2068 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
2069 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
2070 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
2071
2072 enum operand_type
2073 {
2074 reg,
2075 imm,
2076 disp,
2077 anymem
2078 };
2079
2080 static INLINE int
2081 operand_type_check (i386_operand_type t, enum operand_type c)
2082 {
2083 switch (c)
2084 {
2085 case reg:
2086 return t.bitfield.class == Reg;
2087
2088 case imm:
2089 return (t.bitfield.imm8
2090 || t.bitfield.imm8s
2091 || t.bitfield.imm16
2092 || t.bitfield.imm32
2093 || t.bitfield.imm32s
2094 || t.bitfield.imm64);
2095
2096 case disp:
2097 return (t.bitfield.disp8
2098 || t.bitfield.disp16
2099 || t.bitfield.disp32
2100 || t.bitfield.disp32s
2101 || t.bitfield.disp64);
2102
2103 case anymem:
2104 return (t.bitfield.disp8
2105 || t.bitfield.disp16
2106 || t.bitfield.disp32
2107 || t.bitfield.disp32s
2108 || t.bitfield.disp64
2109 || t.bitfield.baseindex);
2110
2111 default:
2112 abort ();
2113 }
2114
2115 return 0;
2116 }
2117
2118 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2119 between operand GIVEN and opeand WANTED for instruction template T. */
2120
2121 static INLINE int
2122 match_operand_size (const insn_template *t, unsigned int wanted,
2123 unsigned int given)
2124 {
2125 return !((i.types[given].bitfield.byte
2126 && !t->operand_types[wanted].bitfield.byte)
2127 || (i.types[given].bitfield.word
2128 && !t->operand_types[wanted].bitfield.word)
2129 || (i.types[given].bitfield.dword
2130 && !t->operand_types[wanted].bitfield.dword)
2131 || (i.types[given].bitfield.qword
2132 && !t->operand_types[wanted].bitfield.qword)
2133 || (i.types[given].bitfield.tbyte
2134 && !t->operand_types[wanted].bitfield.tbyte));
2135 }
2136
2137 /* Return 1 if there is no conflict in SIMD register between operand
2138 GIVEN and opeand WANTED for instruction template T. */
2139
2140 static INLINE int
2141 match_simd_size (const insn_template *t, unsigned int wanted,
2142 unsigned int given)
2143 {
2144 return !((i.types[given].bitfield.xmmword
2145 && !t->operand_types[wanted].bitfield.xmmword)
2146 || (i.types[given].bitfield.ymmword
2147 && !t->operand_types[wanted].bitfield.ymmword)
2148 || (i.types[given].bitfield.zmmword
2149 && !t->operand_types[wanted].bitfield.zmmword));
2150 }
2151
2152 /* Return 1 if there is no conflict in any size between operand GIVEN
2153 and opeand WANTED for instruction template T. */
2154
2155 static INLINE int
2156 match_mem_size (const insn_template *t, unsigned int wanted,
2157 unsigned int given)
2158 {
2159 return (match_operand_size (t, wanted, given)
2160 && !((i.types[given].bitfield.unspecified
2161 && !i.broadcast
2162 && !t->operand_types[wanted].bitfield.unspecified)
2163 || (i.types[given].bitfield.fword
2164 && !t->operand_types[wanted].bitfield.fword)
2165 /* For scalar opcode templates to allow register and memory
2166 operands at the same time, some special casing is needed
2167 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2168 down-conversion vpmov*. */
2169 || ((t->operand_types[wanted].bitfield.class == RegSIMD
2170 && t->operand_types[wanted].bitfield.byte
2171 + t->operand_types[wanted].bitfield.word
2172 + t->operand_types[wanted].bitfield.dword
2173 + t->operand_types[wanted].bitfield.qword
2174 > !!t->opcode_modifier.broadcast)
2175 ? (i.types[given].bitfield.xmmword
2176 || i.types[given].bitfield.ymmword
2177 || i.types[given].bitfield.zmmword)
2178 : !match_simd_size(t, wanted, given))));
2179 }
2180
2181 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2182 operands for instruction template T, and it has MATCH_REVERSE set if there
2183 is no size conflict on any operands for the template with operands reversed
2184 (and the template allows for reversing in the first place). */
2185
2186 #define MATCH_STRAIGHT 1
2187 #define MATCH_REVERSE 2
2188
2189 static INLINE unsigned int
2190 operand_size_match (const insn_template *t)
2191 {
2192 unsigned int j, match = MATCH_STRAIGHT;
2193
2194 /* Don't check non-absolute jump instructions. */
2195 if (t->opcode_modifier.jump
2196 && t->opcode_modifier.jump != JUMP_ABSOLUTE)
2197 return match;
2198
2199 /* Check memory and accumulator operand size. */
2200 for (j = 0; j < i.operands; j++)
2201 {
2202 if (i.types[j].bitfield.class != Reg
2203 && i.types[j].bitfield.class != RegSIMD
2204 && t->opcode_modifier.anysize)
2205 continue;
2206
2207 if (t->operand_types[j].bitfield.class == Reg
2208 && !match_operand_size (t, j, j))
2209 {
2210 match = 0;
2211 break;
2212 }
2213
2214 if (t->operand_types[j].bitfield.class == RegSIMD
2215 && !match_simd_size (t, j, j))
2216 {
2217 match = 0;
2218 break;
2219 }
2220
2221 if (t->operand_types[j].bitfield.instance == Accum
2222 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2223 {
2224 match = 0;
2225 break;
2226 }
2227
2228 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2229 {
2230 match = 0;
2231 break;
2232 }
2233 }
2234
2235 if (!t->opcode_modifier.d)
2236 {
2237 mismatch:
2238 if (!match)
2239 i.error = operand_size_mismatch;
2240 return match;
2241 }
2242
2243 /* Check reverse. */
2244 gas_assert (i.operands >= 2 && i.operands <= 3);
2245
2246 for (j = 0; j < i.operands; j++)
2247 {
2248 unsigned int given = i.operands - j - 1;
2249
2250 if (t->operand_types[j].bitfield.class == Reg
2251 && !match_operand_size (t, j, given))
2252 goto mismatch;
2253
2254 if (t->operand_types[j].bitfield.class == RegSIMD
2255 && !match_simd_size (t, j, given))
2256 goto mismatch;
2257
2258 if (t->operand_types[j].bitfield.instance == Accum
2259 && (!match_operand_size (t, j, given)
2260 || !match_simd_size (t, j, given)))
2261 goto mismatch;
2262
2263 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2264 goto mismatch;
2265 }
2266
2267 return match | MATCH_REVERSE;
2268 }
2269
2270 static INLINE int
2271 operand_type_match (i386_operand_type overlap,
2272 i386_operand_type given)
2273 {
2274 i386_operand_type temp = overlap;
2275
2276 temp.bitfield.unspecified = 0;
2277 temp.bitfield.byte = 0;
2278 temp.bitfield.word = 0;
2279 temp.bitfield.dword = 0;
2280 temp.bitfield.fword = 0;
2281 temp.bitfield.qword = 0;
2282 temp.bitfield.tbyte = 0;
2283 temp.bitfield.xmmword = 0;
2284 temp.bitfield.ymmword = 0;
2285 temp.bitfield.zmmword = 0;
2286 if (operand_type_all_zero (&temp))
2287 goto mismatch;
2288
2289 if (given.bitfield.baseindex == overlap.bitfield.baseindex)
2290 return 1;
2291
2292 mismatch:
2293 i.error = operand_type_mismatch;
2294 return 0;
2295 }
2296
2297 /* If given types g0 and g1 are registers they must be of the same type
2298 unless the expected operand type register overlap is null.
2299 Some Intel syntax memory operand size checking also happens here. */
2300
2301 static INLINE int
2302 operand_type_register_match (i386_operand_type g0,
2303 i386_operand_type t0,
2304 i386_operand_type g1,
2305 i386_operand_type t1)
2306 {
2307 if (g0.bitfield.class != Reg
2308 && g0.bitfield.class != RegSIMD
2309 && (!operand_type_check (g0, anymem)
2310 || g0.bitfield.unspecified
2311 || (t0.bitfield.class != Reg
2312 && t0.bitfield.class != RegSIMD)))
2313 return 1;
2314
2315 if (g1.bitfield.class != Reg
2316 && g1.bitfield.class != RegSIMD
2317 && (!operand_type_check (g1, anymem)
2318 || g1.bitfield.unspecified
2319 || (t1.bitfield.class != Reg
2320 && t1.bitfield.class != RegSIMD)))
2321 return 1;
2322
2323 if (g0.bitfield.byte == g1.bitfield.byte
2324 && g0.bitfield.word == g1.bitfield.word
2325 && g0.bitfield.dword == g1.bitfield.dword
2326 && g0.bitfield.qword == g1.bitfield.qword
2327 && g0.bitfield.xmmword == g1.bitfield.xmmword
2328 && g0.bitfield.ymmword == g1.bitfield.ymmword
2329 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2330 return 1;
2331
2332 if (!(t0.bitfield.byte & t1.bitfield.byte)
2333 && !(t0.bitfield.word & t1.bitfield.word)
2334 && !(t0.bitfield.dword & t1.bitfield.dword)
2335 && !(t0.bitfield.qword & t1.bitfield.qword)
2336 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2337 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2338 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2339 return 1;
2340
2341 i.error = register_type_mismatch;
2342
2343 return 0;
2344 }
2345
2346 static INLINE unsigned int
2347 register_number (const reg_entry *r)
2348 {
2349 unsigned int nr = r->reg_num;
2350
2351 if (r->reg_flags & RegRex)
2352 nr += 8;
2353
2354 if (r->reg_flags & RegVRex)
2355 nr += 16;
2356
2357 return nr;
2358 }
2359
2360 static INLINE unsigned int
2361 mode_from_disp_size (i386_operand_type t)
2362 {
2363 if (t.bitfield.disp8)
2364 return 1;
2365 else if (t.bitfield.disp16
2366 || t.bitfield.disp32
2367 || t.bitfield.disp32s)
2368 return 2;
2369 else
2370 return 0;
2371 }
2372
2373 static INLINE int
2374 fits_in_signed_byte (addressT num)
2375 {
2376 return num + 0x80 <= 0xff;
2377 }
2378
2379 static INLINE int
2380 fits_in_unsigned_byte (addressT num)
2381 {
2382 return num <= 0xff;
2383 }
2384
2385 static INLINE int
2386 fits_in_unsigned_word (addressT num)
2387 {
2388 return num <= 0xffff;
2389 }
2390
2391 static INLINE int
2392 fits_in_signed_word (addressT num)
2393 {
2394 return num + 0x8000 <= 0xffff;
2395 }
2396
2397 static INLINE int
2398 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2399 {
2400 #ifndef BFD64
2401 return 1;
2402 #else
2403 return num + 0x80000000 <= 0xffffffff;
2404 #endif
2405 } /* fits_in_signed_long() */
2406
2407 static INLINE int
2408 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2409 {
2410 #ifndef BFD64
2411 return 1;
2412 #else
2413 return num <= 0xffffffff;
2414 #endif
2415 } /* fits_in_unsigned_long() */
2416
2417 static INLINE int
2418 fits_in_disp8 (offsetT num)
2419 {
2420 int shift = i.memshift;
2421 unsigned int mask;
2422
2423 if (shift == -1)
2424 abort ();
2425
2426 mask = (1 << shift) - 1;
2427
2428 /* Return 0 if NUM isn't properly aligned. */
2429 if ((num & mask))
2430 return 0;
2431
2432 /* Check if NUM will fit in 8bit after shift. */
2433 return fits_in_signed_byte (num >> shift);
2434 }
2435
2436 static INLINE int
2437 fits_in_imm4 (offsetT num)
2438 {
2439 return (num & 0xf) == num;
2440 }
2441
2442 static i386_operand_type
2443 smallest_imm_type (offsetT num)
2444 {
2445 i386_operand_type t;
2446
2447 operand_type_set (&t, 0);
2448 t.bitfield.imm64 = 1;
2449
2450 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2451 {
2452 /* This code is disabled on the 486 because all the Imm1 forms
2453 in the opcode table are slower on the i486. They're the
2454 versions with the implicitly specified single-position
2455 displacement, which has another syntax if you really want to
2456 use that form. */
2457 t.bitfield.imm1 = 1;
2458 t.bitfield.imm8 = 1;
2459 t.bitfield.imm8s = 1;
2460 t.bitfield.imm16 = 1;
2461 t.bitfield.imm32 = 1;
2462 t.bitfield.imm32s = 1;
2463 }
2464 else if (fits_in_signed_byte (num))
2465 {
2466 t.bitfield.imm8 = 1;
2467 t.bitfield.imm8s = 1;
2468 t.bitfield.imm16 = 1;
2469 t.bitfield.imm32 = 1;
2470 t.bitfield.imm32s = 1;
2471 }
2472 else if (fits_in_unsigned_byte (num))
2473 {
2474 t.bitfield.imm8 = 1;
2475 t.bitfield.imm16 = 1;
2476 t.bitfield.imm32 = 1;
2477 t.bitfield.imm32s = 1;
2478 }
2479 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2480 {
2481 t.bitfield.imm16 = 1;
2482 t.bitfield.imm32 = 1;
2483 t.bitfield.imm32s = 1;
2484 }
2485 else if (fits_in_signed_long (num))
2486 {
2487 t.bitfield.imm32 = 1;
2488 t.bitfield.imm32s = 1;
2489 }
2490 else if (fits_in_unsigned_long (num))
2491 t.bitfield.imm32 = 1;
2492
2493 return t;
2494 }
2495
2496 static offsetT
2497 offset_in_range (offsetT val, int size)
2498 {
2499 addressT mask;
2500
2501 switch (size)
2502 {
2503 case 1: mask = ((addressT) 1 << 8) - 1; break;
2504 case 2: mask = ((addressT) 1 << 16) - 1; break;
2505 case 4: mask = ((addressT) 2 << 31) - 1; break;
2506 #ifdef BFD64
2507 case 8: mask = ((addressT) 2 << 63) - 1; break;
2508 #endif
2509 default: abort ();
2510 }
2511
2512 #ifdef BFD64
2513 /* If BFD64, sign extend val for 32bit address mode. */
2514 if (flag_code != CODE_64BIT
2515 || i.prefix[ADDR_PREFIX])
2516 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2517 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2518 #endif
2519
2520 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2521 {
2522 char buf1[40], buf2[40];
2523
2524 sprint_value (buf1, val);
2525 sprint_value (buf2, val & mask);
2526 as_warn (_("%s shortened to %s"), buf1, buf2);
2527 }
2528 return val & mask;
2529 }
2530
2531 enum PREFIX_GROUP
2532 {
2533 PREFIX_EXIST = 0,
2534 PREFIX_LOCK,
2535 PREFIX_REP,
2536 PREFIX_DS,
2537 PREFIX_OTHER
2538 };
2539
2540 /* Returns
2541 a. PREFIX_EXIST if attempting to add a prefix where one from the
2542 same class already exists.
2543 b. PREFIX_LOCK if lock prefix is added.
2544 c. PREFIX_REP if rep/repne prefix is added.
2545 d. PREFIX_DS if ds prefix is added.
2546 e. PREFIX_OTHER if other prefix is added.
2547 */
2548
2549 static enum PREFIX_GROUP
2550 add_prefix (unsigned int prefix)
2551 {
2552 enum PREFIX_GROUP ret = PREFIX_OTHER;
2553 unsigned int q;
2554
2555 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2556 && flag_code == CODE_64BIT)
2557 {
2558 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2559 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2560 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2561 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2562 ret = PREFIX_EXIST;
2563 q = REX_PREFIX;
2564 }
2565 else
2566 {
2567 switch (prefix)
2568 {
2569 default:
2570 abort ();
2571
2572 case DS_PREFIX_OPCODE:
2573 ret = PREFIX_DS;
2574 /* Fall through. */
2575 case CS_PREFIX_OPCODE:
2576 case ES_PREFIX_OPCODE:
2577 case FS_PREFIX_OPCODE:
2578 case GS_PREFIX_OPCODE:
2579 case SS_PREFIX_OPCODE:
2580 q = SEG_PREFIX;
2581 break;
2582
2583 case REPNE_PREFIX_OPCODE:
2584 case REPE_PREFIX_OPCODE:
2585 q = REP_PREFIX;
2586 ret = PREFIX_REP;
2587 break;
2588
2589 case LOCK_PREFIX_OPCODE:
2590 q = LOCK_PREFIX;
2591 ret = PREFIX_LOCK;
2592 break;
2593
2594 case FWAIT_OPCODE:
2595 q = WAIT_PREFIX;
2596 break;
2597
2598 case ADDR_PREFIX_OPCODE:
2599 q = ADDR_PREFIX;
2600 break;
2601
2602 case DATA_PREFIX_OPCODE:
2603 q = DATA_PREFIX;
2604 break;
2605 }
2606 if (i.prefix[q] != 0)
2607 ret = PREFIX_EXIST;
2608 }
2609
2610 if (ret)
2611 {
2612 if (!i.prefix[q])
2613 ++i.prefixes;
2614 i.prefix[q] |= prefix;
2615 }
2616 else
2617 as_bad (_("same type of prefix used twice"));
2618
2619 return ret;
2620 }
2621
2622 static void
2623 update_code_flag (int value, int check)
2624 {
2625 PRINTF_LIKE ((*as_error));
2626
2627 flag_code = (enum flag_code) value;
2628 if (flag_code == CODE_64BIT)
2629 {
2630 cpu_arch_flags.bitfield.cpu64 = 1;
2631 cpu_arch_flags.bitfield.cpuno64 = 0;
2632 }
2633 else
2634 {
2635 cpu_arch_flags.bitfield.cpu64 = 0;
2636 cpu_arch_flags.bitfield.cpuno64 = 1;
2637 }
2638 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2639 {
2640 if (check)
2641 as_error = as_fatal;
2642 else
2643 as_error = as_bad;
2644 (*as_error) (_("64bit mode not supported on `%s'."),
2645 cpu_arch_name ? cpu_arch_name : default_arch);
2646 }
2647 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2648 {
2649 if (check)
2650 as_error = as_fatal;
2651 else
2652 as_error = as_bad;
2653 (*as_error) (_("32bit mode not supported on `%s'."),
2654 cpu_arch_name ? cpu_arch_name : default_arch);
2655 }
2656 stackop_size = '\0';
2657 }
2658
2659 static void
2660 set_code_flag (int value)
2661 {
2662 update_code_flag (value, 0);
2663 }
2664
2665 static void
2666 set_16bit_gcc_code_flag (int new_code_flag)
2667 {
2668 flag_code = (enum flag_code) new_code_flag;
2669 if (flag_code != CODE_16BIT)
2670 abort ();
2671 cpu_arch_flags.bitfield.cpu64 = 0;
2672 cpu_arch_flags.bitfield.cpuno64 = 1;
2673 stackop_size = LONG_MNEM_SUFFIX;
2674 }
2675
2676 static void
2677 set_intel_syntax (int syntax_flag)
2678 {
2679 /* Find out if register prefixing is specified. */
2680 int ask_naked_reg = 0;
2681
2682 SKIP_WHITESPACE ();
2683 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2684 {
2685 char *string;
2686 int e = get_symbol_name (&string);
2687
2688 if (strcmp (string, "prefix") == 0)
2689 ask_naked_reg = 1;
2690 else if (strcmp (string, "noprefix") == 0)
2691 ask_naked_reg = -1;
2692 else
2693 as_bad (_("bad argument to syntax directive."));
2694 (void) restore_line_pointer (e);
2695 }
2696 demand_empty_rest_of_line ();
2697
2698 intel_syntax = syntax_flag;
2699
2700 if (ask_naked_reg == 0)
2701 allow_naked_reg = (intel_syntax
2702 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2703 else
2704 allow_naked_reg = (ask_naked_reg < 0);
2705
2706 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2707
2708 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2709 identifier_chars['$'] = intel_syntax ? '$' : 0;
2710 register_prefix = allow_naked_reg ? "" : "%";
2711 }
2712
2713 static void
2714 set_intel_mnemonic (int mnemonic_flag)
2715 {
2716 intel_mnemonic = mnemonic_flag;
2717 }
2718
2719 static void
2720 set_allow_index_reg (int flag)
2721 {
2722 allow_index_reg = flag;
2723 }
2724
2725 static void
2726 set_check (int what)
2727 {
2728 enum check_kind *kind;
2729 const char *str;
2730
2731 if (what)
2732 {
2733 kind = &operand_check;
2734 str = "operand";
2735 }
2736 else
2737 {
2738 kind = &sse_check;
2739 str = "sse";
2740 }
2741
2742 SKIP_WHITESPACE ();
2743
2744 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2745 {
2746 char *string;
2747 int e = get_symbol_name (&string);
2748
2749 if (strcmp (string, "none") == 0)
2750 *kind = check_none;
2751 else if (strcmp (string, "warning") == 0)
2752 *kind = check_warning;
2753 else if (strcmp (string, "error") == 0)
2754 *kind = check_error;
2755 else
2756 as_bad (_("bad argument to %s_check directive."), str);
2757 (void) restore_line_pointer (e);
2758 }
2759 else
2760 as_bad (_("missing argument for %s_check directive"), str);
2761
2762 demand_empty_rest_of_line ();
2763 }
2764
2765 static void
2766 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2767 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2768 {
2769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2770 static const char *arch;
2771
2772 /* Intel LIOM is only supported on ELF. */
2773 if (!IS_ELF)
2774 return;
2775
2776 if (!arch)
2777 {
2778 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2779 use default_arch. */
2780 arch = cpu_arch_name;
2781 if (!arch)
2782 arch = default_arch;
2783 }
2784
2785 /* If we are targeting Intel MCU, we must enable it. */
2786 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2787 || new_flag.bitfield.cpuiamcu)
2788 return;
2789
2790 /* If we are targeting Intel L1OM, we must enable it. */
2791 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2792 || new_flag.bitfield.cpul1om)
2793 return;
2794
2795 /* If we are targeting Intel K1OM, we must enable it. */
2796 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2797 || new_flag.bitfield.cpuk1om)
2798 return;
2799
2800 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2801 #endif
2802 }
2803
2804 static void
2805 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2806 {
2807 SKIP_WHITESPACE ();
2808
2809 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2810 {
2811 char *string;
2812 int e = get_symbol_name (&string);
2813 unsigned int j;
2814 i386_cpu_flags flags;
2815
2816 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2817 {
2818 if (strcmp (string, cpu_arch[j].name) == 0)
2819 {
2820 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2821
2822 if (*string != '.')
2823 {
2824 cpu_arch_name = cpu_arch[j].name;
2825 cpu_sub_arch_name = NULL;
2826 cpu_arch_flags = cpu_arch[j].flags;
2827 if (flag_code == CODE_64BIT)
2828 {
2829 cpu_arch_flags.bitfield.cpu64 = 1;
2830 cpu_arch_flags.bitfield.cpuno64 = 0;
2831 }
2832 else
2833 {
2834 cpu_arch_flags.bitfield.cpu64 = 0;
2835 cpu_arch_flags.bitfield.cpuno64 = 1;
2836 }
2837 cpu_arch_isa = cpu_arch[j].type;
2838 cpu_arch_isa_flags = cpu_arch[j].flags;
2839 if (!cpu_arch_tune_set)
2840 {
2841 cpu_arch_tune = cpu_arch_isa;
2842 cpu_arch_tune_flags = cpu_arch_isa_flags;
2843 }
2844 break;
2845 }
2846
2847 flags = cpu_flags_or (cpu_arch_flags,
2848 cpu_arch[j].flags);
2849
2850 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2851 {
2852 if (cpu_sub_arch_name)
2853 {
2854 char *name = cpu_sub_arch_name;
2855 cpu_sub_arch_name = concat (name,
2856 cpu_arch[j].name,
2857 (const char *) NULL);
2858 free (name);
2859 }
2860 else
2861 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2862 cpu_arch_flags = flags;
2863 cpu_arch_isa_flags = flags;
2864 }
2865 else
2866 cpu_arch_isa_flags
2867 = cpu_flags_or (cpu_arch_isa_flags,
2868 cpu_arch[j].flags);
2869 (void) restore_line_pointer (e);
2870 demand_empty_rest_of_line ();
2871 return;
2872 }
2873 }
2874
2875 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2876 {
2877 /* Disable an ISA extension. */
2878 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2879 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2880 {
2881 flags = cpu_flags_and_not (cpu_arch_flags,
2882 cpu_noarch[j].flags);
2883 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2884 {
2885 if (cpu_sub_arch_name)
2886 {
2887 char *name = cpu_sub_arch_name;
2888 cpu_sub_arch_name = concat (name, string,
2889 (const char *) NULL);
2890 free (name);
2891 }
2892 else
2893 cpu_sub_arch_name = xstrdup (string);
2894 cpu_arch_flags = flags;
2895 cpu_arch_isa_flags = flags;
2896 }
2897 (void) restore_line_pointer (e);
2898 demand_empty_rest_of_line ();
2899 return;
2900 }
2901
2902 j = ARRAY_SIZE (cpu_arch);
2903 }
2904
2905 if (j >= ARRAY_SIZE (cpu_arch))
2906 as_bad (_("no such architecture: `%s'"), string);
2907
2908 *input_line_pointer = e;
2909 }
2910 else
2911 as_bad (_("missing cpu architecture"));
2912
2913 no_cond_jump_promotion = 0;
2914 if (*input_line_pointer == ','
2915 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2916 {
2917 char *string;
2918 char e;
2919
2920 ++input_line_pointer;
2921 e = get_symbol_name (&string);
2922
2923 if (strcmp (string, "nojumps") == 0)
2924 no_cond_jump_promotion = 1;
2925 else if (strcmp (string, "jumps") == 0)
2926 ;
2927 else
2928 as_bad (_("no such architecture modifier: `%s'"), string);
2929
2930 (void) restore_line_pointer (e);
2931 }
2932
2933 demand_empty_rest_of_line ();
2934 }
2935
2936 enum bfd_architecture
2937 i386_arch (void)
2938 {
2939 if (cpu_arch_isa == PROCESSOR_L1OM)
2940 {
2941 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2942 || flag_code != CODE_64BIT)
2943 as_fatal (_("Intel L1OM is 64bit ELF only"));
2944 return bfd_arch_l1om;
2945 }
2946 else if (cpu_arch_isa == PROCESSOR_K1OM)
2947 {
2948 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2949 || flag_code != CODE_64BIT)
2950 as_fatal (_("Intel K1OM is 64bit ELF only"));
2951 return bfd_arch_k1om;
2952 }
2953 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2954 {
2955 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2956 || flag_code == CODE_64BIT)
2957 as_fatal (_("Intel MCU is 32bit ELF only"));
2958 return bfd_arch_iamcu;
2959 }
2960 else
2961 return bfd_arch_i386;
2962 }
2963
2964 unsigned long
2965 i386_mach (void)
2966 {
2967 if (!strncmp (default_arch, "x86_64", 6))
2968 {
2969 if (cpu_arch_isa == PROCESSOR_L1OM)
2970 {
2971 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2972 || default_arch[6] != '\0')
2973 as_fatal (_("Intel L1OM is 64bit ELF only"));
2974 return bfd_mach_l1om;
2975 }
2976 else if (cpu_arch_isa == PROCESSOR_K1OM)
2977 {
2978 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2979 || default_arch[6] != '\0')
2980 as_fatal (_("Intel K1OM is 64bit ELF only"));
2981 return bfd_mach_k1om;
2982 }
2983 else if (default_arch[6] == '\0')
2984 return bfd_mach_x86_64;
2985 else
2986 return bfd_mach_x64_32;
2987 }
2988 else if (!strcmp (default_arch, "i386")
2989 || !strcmp (default_arch, "iamcu"))
2990 {
2991 if (cpu_arch_isa == PROCESSOR_IAMCU)
2992 {
2993 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2994 as_fatal (_("Intel MCU is 32bit ELF only"));
2995 return bfd_mach_i386_iamcu;
2996 }
2997 else
2998 return bfd_mach_i386_i386;
2999 }
3000 else
3001 as_fatal (_("unknown architecture"));
3002 }
3003 \f
3004 void
3005 md_begin (void)
3006 {
3007 const char *hash_err;
3008
3009 /* Support pseudo prefixes like {disp32}. */
3010 lex_type ['{'] = LEX_BEGIN_NAME;
3011
3012 /* Initialize op_hash hash table. */
3013 op_hash = hash_new ();
3014
3015 {
3016 const insn_template *optab;
3017 templates *core_optab;
3018
3019 /* Setup for loop. */
3020 optab = i386_optab;
3021 core_optab = XNEW (templates);
3022 core_optab->start = optab;
3023
3024 while (1)
3025 {
3026 ++optab;
3027 if (optab->name == NULL
3028 || strcmp (optab->name, (optab - 1)->name) != 0)
3029 {
3030 /* different name --> ship out current template list;
3031 add to hash table; & begin anew. */
3032 core_optab->end = optab;
3033 hash_err = hash_insert (op_hash,
3034 (optab - 1)->name,
3035 (void *) core_optab);
3036 if (hash_err)
3037 {
3038 as_fatal (_("can't hash %s: %s"),
3039 (optab - 1)->name,
3040 hash_err);
3041 }
3042 if (optab->name == NULL)
3043 break;
3044 core_optab = XNEW (templates);
3045 core_optab->start = optab;
3046 }
3047 }
3048 }
3049
3050 /* Initialize reg_hash hash table. */
3051 reg_hash = hash_new ();
3052 {
3053 const reg_entry *regtab;
3054 unsigned int regtab_size = i386_regtab_size;
3055
3056 for (regtab = i386_regtab; regtab_size--; regtab++)
3057 {
3058 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
3059 if (hash_err)
3060 as_fatal (_("can't hash %s: %s"),
3061 regtab->reg_name,
3062 hash_err);
3063 }
3064 }
3065
3066 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3067 {
3068 int c;
3069 char *p;
3070
3071 for (c = 0; c < 256; c++)
3072 {
3073 if (ISDIGIT (c))
3074 {
3075 digit_chars[c] = c;
3076 mnemonic_chars[c] = c;
3077 register_chars[c] = c;
3078 operand_chars[c] = c;
3079 }
3080 else if (ISLOWER (c))
3081 {
3082 mnemonic_chars[c] = c;
3083 register_chars[c] = c;
3084 operand_chars[c] = c;
3085 }
3086 else if (ISUPPER (c))
3087 {
3088 mnemonic_chars[c] = TOLOWER (c);
3089 register_chars[c] = mnemonic_chars[c];
3090 operand_chars[c] = c;
3091 }
3092 else if (c == '{' || c == '}')
3093 {
3094 mnemonic_chars[c] = c;
3095 operand_chars[c] = c;
3096 }
3097
3098 if (ISALPHA (c) || ISDIGIT (c))
3099 identifier_chars[c] = c;
3100 else if (c >= 128)
3101 {
3102 identifier_chars[c] = c;
3103 operand_chars[c] = c;
3104 }
3105 }
3106
3107 #ifdef LEX_AT
3108 identifier_chars['@'] = '@';
3109 #endif
3110 #ifdef LEX_QM
3111 identifier_chars['?'] = '?';
3112 operand_chars['?'] = '?';
3113 #endif
3114 digit_chars['-'] = '-';
3115 mnemonic_chars['_'] = '_';
3116 mnemonic_chars['-'] = '-';
3117 mnemonic_chars['.'] = '.';
3118 identifier_chars['_'] = '_';
3119 identifier_chars['.'] = '.';
3120
3121 for (p = operand_special_chars; *p != '\0'; p++)
3122 operand_chars[(unsigned char) *p] = *p;
3123 }
3124
3125 if (flag_code == CODE_64BIT)
3126 {
3127 #if defined (OBJ_COFF) && defined (TE_PE)
3128 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
3129 ? 32 : 16);
3130 #else
3131 x86_dwarf2_return_column = 16;
3132 #endif
3133 x86_cie_data_alignment = -8;
3134 }
3135 else
3136 {
3137 x86_dwarf2_return_column = 8;
3138 x86_cie_data_alignment = -4;
3139 }
3140
3141 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3142 can be turned into BRANCH_PREFIX frag. */
3143 if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE)
3144 abort ();
3145 }
3146
3147 void
3148 i386_print_statistics (FILE *file)
3149 {
3150 hash_print_statistics (file, "i386 opcode", op_hash);
3151 hash_print_statistics (file, "i386 register", reg_hash);
3152 }
3153 \f
3154 #ifdef DEBUG386
3155
3156 /* Debugging routines for md_assemble. */
3157 static void pte (insn_template *);
3158 static void pt (i386_operand_type);
3159 static void pe (expressionS *);
3160 static void ps (symbolS *);
3161
3162 static void
3163 pi (const char *line, i386_insn *x)
3164 {
3165 unsigned int j;
3166
3167 fprintf (stdout, "%s: template ", line);
3168 pte (&x->tm);
3169 fprintf (stdout, " address: base %s index %s scale %x\n",
3170 x->base_reg ? x->base_reg->reg_name : "none",
3171 x->index_reg ? x->index_reg->reg_name : "none",
3172 x->log2_scale_factor);
3173 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
3174 x->rm.mode, x->rm.reg, x->rm.regmem);
3175 fprintf (stdout, " sib: base %x index %x scale %x\n",
3176 x->sib.base, x->sib.index, x->sib.scale);
3177 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
3178 (x->rex & REX_W) != 0,
3179 (x->rex & REX_R) != 0,
3180 (x->rex & REX_X) != 0,
3181 (x->rex & REX_B) != 0);
3182 for (j = 0; j < x->operands; j++)
3183 {
3184 fprintf (stdout, " #%d: ", j + 1);
3185 pt (x->types[j]);
3186 fprintf (stdout, "\n");
3187 if (x->types[j].bitfield.class == Reg
3188 || x->types[j].bitfield.class == RegMMX
3189 || x->types[j].bitfield.class == RegSIMD
3190 || x->types[j].bitfield.class == SReg
3191 || x->types[j].bitfield.class == RegCR
3192 || x->types[j].bitfield.class == RegDR
3193 || x->types[j].bitfield.class == RegTR)
3194 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3195 if (operand_type_check (x->types[j], imm))
3196 pe (x->op[j].imms);
3197 if (operand_type_check (x->types[j], disp))
3198 pe (x->op[j].disps);
3199 }
3200 }
3201
3202 static void
3203 pte (insn_template *t)
3204 {
3205 unsigned int j;
3206 fprintf (stdout, " %d operands ", t->operands);
3207 fprintf (stdout, "opcode %x ", t->base_opcode);
3208 if (t->extension_opcode != None)
3209 fprintf (stdout, "ext %x ", t->extension_opcode);
3210 if (t->opcode_modifier.d)
3211 fprintf (stdout, "D");
3212 if (t->opcode_modifier.w)
3213 fprintf (stdout, "W");
3214 fprintf (stdout, "\n");
3215 for (j = 0; j < t->operands; j++)
3216 {
3217 fprintf (stdout, " #%d type ", j + 1);
3218 pt (t->operand_types[j]);
3219 fprintf (stdout, "\n");
3220 }
3221 }
3222
3223 static void
3224 pe (expressionS *e)
3225 {
3226 fprintf (stdout, " operation %d\n", e->X_op);
3227 fprintf (stdout, " add_number %ld (%lx)\n",
3228 (long) e->X_add_number, (long) e->X_add_number);
3229 if (e->X_add_symbol)
3230 {
3231 fprintf (stdout, " add_symbol ");
3232 ps (e->X_add_symbol);
3233 fprintf (stdout, "\n");
3234 }
3235 if (e->X_op_symbol)
3236 {
3237 fprintf (stdout, " op_symbol ");
3238 ps (e->X_op_symbol);
3239 fprintf (stdout, "\n");
3240 }
3241 }
3242
3243 static void
3244 ps (symbolS *s)
3245 {
3246 fprintf (stdout, "%s type %s%s",
3247 S_GET_NAME (s),
3248 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3249 segment_name (S_GET_SEGMENT (s)));
3250 }
3251
3252 static struct type_name
3253 {
3254 i386_operand_type mask;
3255 const char *name;
3256 }
3257 const type_names[] =
3258 {
3259 { OPERAND_TYPE_REG8, "r8" },
3260 { OPERAND_TYPE_REG16, "r16" },
3261 { OPERAND_TYPE_REG32, "r32" },
3262 { OPERAND_TYPE_REG64, "r64" },
3263 { OPERAND_TYPE_ACC8, "acc8" },
3264 { OPERAND_TYPE_ACC16, "acc16" },
3265 { OPERAND_TYPE_ACC32, "acc32" },
3266 { OPERAND_TYPE_ACC64, "acc64" },
3267 { OPERAND_TYPE_IMM8, "i8" },
3268 { OPERAND_TYPE_IMM8, "i8s" },
3269 { OPERAND_TYPE_IMM16, "i16" },
3270 { OPERAND_TYPE_IMM32, "i32" },
3271 { OPERAND_TYPE_IMM32S, "i32s" },
3272 { OPERAND_TYPE_IMM64, "i64" },
3273 { OPERAND_TYPE_IMM1, "i1" },
3274 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3275 { OPERAND_TYPE_DISP8, "d8" },
3276 { OPERAND_TYPE_DISP16, "d16" },
3277 { OPERAND_TYPE_DISP32, "d32" },
3278 { OPERAND_TYPE_DISP32S, "d32s" },
3279 { OPERAND_TYPE_DISP64, "d64" },
3280 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3281 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3282 { OPERAND_TYPE_CONTROL, "control reg" },
3283 { OPERAND_TYPE_TEST, "test reg" },
3284 { OPERAND_TYPE_DEBUG, "debug reg" },
3285 { OPERAND_TYPE_FLOATREG, "FReg" },
3286 { OPERAND_TYPE_FLOATACC, "FAcc" },
3287 { OPERAND_TYPE_SREG, "SReg" },
3288 { OPERAND_TYPE_REGMMX, "rMMX" },
3289 { OPERAND_TYPE_REGXMM, "rXMM" },
3290 { OPERAND_TYPE_REGYMM, "rYMM" },
3291 { OPERAND_TYPE_REGZMM, "rZMM" },
3292 { OPERAND_TYPE_REGMASK, "Mask reg" },
3293 };
3294
3295 static void
3296 pt (i386_operand_type t)
3297 {
3298 unsigned int j;
3299 i386_operand_type a;
3300
3301 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3302 {
3303 a = operand_type_and (t, type_names[j].mask);
3304 if (operand_type_equal (&a, &type_names[j].mask))
3305 fprintf (stdout, "%s, ", type_names[j].name);
3306 }
3307 fflush (stdout);
3308 }
3309
3310 #endif /* DEBUG386 */
3311 \f
3312 static bfd_reloc_code_real_type
3313 reloc (unsigned int size,
3314 int pcrel,
3315 int sign,
3316 bfd_reloc_code_real_type other)
3317 {
3318 if (other != NO_RELOC)
3319 {
3320 reloc_howto_type *rel;
3321
3322 if (size == 8)
3323 switch (other)
3324 {
3325 case BFD_RELOC_X86_64_GOT32:
3326 return BFD_RELOC_X86_64_GOT64;
3327 break;
3328 case BFD_RELOC_X86_64_GOTPLT64:
3329 return BFD_RELOC_X86_64_GOTPLT64;
3330 break;
3331 case BFD_RELOC_X86_64_PLTOFF64:
3332 return BFD_RELOC_X86_64_PLTOFF64;
3333 break;
3334 case BFD_RELOC_X86_64_GOTPC32:
3335 other = BFD_RELOC_X86_64_GOTPC64;
3336 break;
3337 case BFD_RELOC_X86_64_GOTPCREL:
3338 other = BFD_RELOC_X86_64_GOTPCREL64;
3339 break;
3340 case BFD_RELOC_X86_64_TPOFF32:
3341 other = BFD_RELOC_X86_64_TPOFF64;
3342 break;
3343 case BFD_RELOC_X86_64_DTPOFF32:
3344 other = BFD_RELOC_X86_64_DTPOFF64;
3345 break;
3346 default:
3347 break;
3348 }
3349
3350 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3351 if (other == BFD_RELOC_SIZE32)
3352 {
3353 if (size == 8)
3354 other = BFD_RELOC_SIZE64;
3355 if (pcrel)
3356 {
3357 as_bad (_("there are no pc-relative size relocations"));
3358 return NO_RELOC;
3359 }
3360 }
3361 #endif
3362
3363 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3364 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3365 sign = -1;
3366
3367 rel = bfd_reloc_type_lookup (stdoutput, other);
3368 if (!rel)
3369 as_bad (_("unknown relocation (%u)"), other);
3370 else if (size != bfd_get_reloc_size (rel))
3371 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3372 bfd_get_reloc_size (rel),
3373 size);
3374 else if (pcrel && !rel->pc_relative)
3375 as_bad (_("non-pc-relative relocation for pc-relative field"));
3376 else if ((rel->complain_on_overflow == complain_overflow_signed
3377 && !sign)
3378 || (rel->complain_on_overflow == complain_overflow_unsigned
3379 && sign > 0))
3380 as_bad (_("relocated field and relocation type differ in signedness"));
3381 else
3382 return other;
3383 return NO_RELOC;
3384 }
3385
3386 if (pcrel)
3387 {
3388 if (!sign)
3389 as_bad (_("there are no unsigned pc-relative relocations"));
3390 switch (size)
3391 {
3392 case 1: return BFD_RELOC_8_PCREL;
3393 case 2: return BFD_RELOC_16_PCREL;
3394 case 4: return BFD_RELOC_32_PCREL;
3395 case 8: return BFD_RELOC_64_PCREL;
3396 }
3397 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3398 }
3399 else
3400 {
3401 if (sign > 0)
3402 switch (size)
3403 {
3404 case 4: return BFD_RELOC_X86_64_32S;
3405 }
3406 else
3407 switch (size)
3408 {
3409 case 1: return BFD_RELOC_8;
3410 case 2: return BFD_RELOC_16;
3411 case 4: return BFD_RELOC_32;
3412 case 8: return BFD_RELOC_64;
3413 }
3414 as_bad (_("cannot do %s %u byte relocation"),
3415 sign > 0 ? "signed" : "unsigned", size);
3416 }
3417
3418 return NO_RELOC;
3419 }
3420
3421 /* Here we decide which fixups can be adjusted to make them relative to
3422 the beginning of the section instead of the symbol. Basically we need
3423 to make sure that the dynamic relocations are done correctly, so in
3424 some cases we force the original symbol to be used. */
3425
3426 int
3427 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3428 {
3429 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3430 if (!IS_ELF)
3431 return 1;
3432
3433 /* Don't adjust pc-relative references to merge sections in 64-bit
3434 mode. */
3435 if (use_rela_relocations
3436 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3437 && fixP->fx_pcrel)
3438 return 0;
3439
3440 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3441 and changed later by validate_fix. */
3442 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3443 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3444 return 0;
3445
3446 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3447 for size relocations. */
3448 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3449 || fixP->fx_r_type == BFD_RELOC_SIZE64
3450 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3451 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3452 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3453 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3454 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3455 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3456 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3457 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3458 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3459 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3460 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3461 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3462 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3463 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3464 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3465 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3466 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3467 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3468 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3469 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3470 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3471 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3472 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3473 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3474 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3475 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3476 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3477 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3478 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3479 return 0;
3480 #endif
3481 return 1;
3482 }
3483
3484 static int
3485 intel_float_operand (const char *mnemonic)
3486 {
3487 /* Note that the value returned is meaningful only for opcodes with (memory)
3488 operands, hence the code here is free to improperly handle opcodes that
3489 have no operands (for better performance and smaller code). */
3490
3491 if (mnemonic[0] != 'f')
3492 return 0; /* non-math */
3493
3494 switch (mnemonic[1])
3495 {
3496 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3497 the fs segment override prefix not currently handled because no
3498 call path can make opcodes without operands get here */
3499 case 'i':
3500 return 2 /* integer op */;
3501 case 'l':
3502 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3503 return 3; /* fldcw/fldenv */
3504 break;
3505 case 'n':
3506 if (mnemonic[2] != 'o' /* fnop */)
3507 return 3; /* non-waiting control op */
3508 break;
3509 case 'r':
3510 if (mnemonic[2] == 's')
3511 return 3; /* frstor/frstpm */
3512 break;
3513 case 's':
3514 if (mnemonic[2] == 'a')
3515 return 3; /* fsave */
3516 if (mnemonic[2] == 't')
3517 {
3518 switch (mnemonic[3])
3519 {
3520 case 'c': /* fstcw */
3521 case 'd': /* fstdw */
3522 case 'e': /* fstenv */
3523 case 's': /* fsts[gw] */
3524 return 3;
3525 }
3526 }
3527 break;
3528 case 'x':
3529 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3530 return 0; /* fxsave/fxrstor are not really math ops */
3531 break;
3532 }
3533
3534 return 1;
3535 }
3536
3537 /* Build the VEX prefix. */
3538
3539 static void
3540 build_vex_prefix (const insn_template *t)
3541 {
3542 unsigned int register_specifier;
3543 unsigned int implied_prefix;
3544 unsigned int vector_length;
3545 unsigned int w;
3546
3547 /* Check register specifier. */
3548 if (i.vex.register_specifier)
3549 {
3550 register_specifier =
3551 ~register_number (i.vex.register_specifier) & 0xf;
3552 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3553 }
3554 else
3555 register_specifier = 0xf;
3556
3557 /* Use 2-byte VEX prefix by swapping destination and source operand
3558 if there are more than 1 register operand. */
3559 if (i.reg_operands > 1
3560 && i.vec_encoding != vex_encoding_vex3
3561 && i.dir_encoding == dir_encoding_default
3562 && i.operands == i.reg_operands
3563 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3564 && i.tm.opcode_modifier.vexopcode == VEX0F
3565 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3566 && i.rex == REX_B)
3567 {
3568 unsigned int xchg = i.operands - 1;
3569 union i386_op temp_op;
3570 i386_operand_type temp_type;
3571
3572 temp_type = i.types[xchg];
3573 i.types[xchg] = i.types[0];
3574 i.types[0] = temp_type;
3575 temp_op = i.op[xchg];
3576 i.op[xchg] = i.op[0];
3577 i.op[0] = temp_op;
3578
3579 gas_assert (i.rm.mode == 3);
3580
3581 i.rex = REX_R;
3582 xchg = i.rm.regmem;
3583 i.rm.regmem = i.rm.reg;
3584 i.rm.reg = xchg;
3585
3586 if (i.tm.opcode_modifier.d)
3587 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3588 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3589 else /* Use the next insn. */
3590 i.tm = t[1];
3591 }
3592
3593 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3594 are no memory operands and at least 3 register ones. */
3595 if (i.reg_operands >= 3
3596 && i.vec_encoding != vex_encoding_vex3
3597 && i.reg_operands == i.operands - i.imm_operands
3598 && i.tm.opcode_modifier.vex
3599 && i.tm.opcode_modifier.commutative
3600 && (i.tm.opcode_modifier.sse2avx || optimize > 1)
3601 && i.rex == REX_B
3602 && i.vex.register_specifier
3603 && !(i.vex.register_specifier->reg_flags & RegRex))
3604 {
3605 unsigned int xchg = i.operands - i.reg_operands;
3606 union i386_op temp_op;
3607 i386_operand_type temp_type;
3608
3609 gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F);
3610 gas_assert (!i.tm.opcode_modifier.sae);
3611 gas_assert (operand_type_equal (&i.types[i.operands - 2],
3612 &i.types[i.operands - 3]));
3613 gas_assert (i.rm.mode == 3);
3614
3615 temp_type = i.types[xchg];
3616 i.types[xchg] = i.types[xchg + 1];
3617 i.types[xchg + 1] = temp_type;
3618 temp_op = i.op[xchg];
3619 i.op[xchg] = i.op[xchg + 1];
3620 i.op[xchg + 1] = temp_op;
3621
3622 i.rex = 0;
3623 xchg = i.rm.regmem | 8;
3624 i.rm.regmem = ~register_specifier & 0xf;
3625 gas_assert (!(i.rm.regmem & 8));
3626 i.vex.register_specifier += xchg - i.rm.regmem;
3627 register_specifier = ~xchg & 0xf;
3628 }
3629
3630 if (i.tm.opcode_modifier.vex == VEXScalar)
3631 vector_length = avxscalar;
3632 else if (i.tm.opcode_modifier.vex == VEX256)
3633 vector_length = 1;
3634 else
3635 {
3636 unsigned int op;
3637
3638 /* Determine vector length from the last multi-length vector
3639 operand. */
3640 vector_length = 0;
3641 for (op = t->operands; op--;)
3642 if (t->operand_types[op].bitfield.xmmword
3643 && t->operand_types[op].bitfield.ymmword
3644 && i.types[op].bitfield.ymmword)
3645 {
3646 vector_length = 1;
3647 break;
3648 }
3649 }
3650
3651 switch ((i.tm.base_opcode >> 8) & 0xff)
3652 {
3653 case 0:
3654 implied_prefix = 0;
3655 break;
3656 case DATA_PREFIX_OPCODE:
3657 implied_prefix = 1;
3658 break;
3659 case REPE_PREFIX_OPCODE:
3660 implied_prefix = 2;
3661 break;
3662 case REPNE_PREFIX_OPCODE:
3663 implied_prefix = 3;
3664 break;
3665 default:
3666 abort ();
3667 }
3668
3669 /* Check the REX.W bit and VEXW. */
3670 if (i.tm.opcode_modifier.vexw == VEXWIG)
3671 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3672 else if (i.tm.opcode_modifier.vexw)
3673 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3674 else
3675 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3676
3677 /* Use 2-byte VEX prefix if possible. */
3678 if (w == 0
3679 && i.vec_encoding != vex_encoding_vex3
3680 && i.tm.opcode_modifier.vexopcode == VEX0F
3681 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3682 {
3683 /* 2-byte VEX prefix. */
3684 unsigned int r;
3685
3686 i.vex.length = 2;
3687 i.vex.bytes[0] = 0xc5;
3688
3689 /* Check the REX.R bit. */
3690 r = (i.rex & REX_R) ? 0 : 1;
3691 i.vex.bytes[1] = (r << 7
3692 | register_specifier << 3
3693 | vector_length << 2
3694 | implied_prefix);
3695 }
3696 else
3697 {
3698 /* 3-byte VEX prefix. */
3699 unsigned int m;
3700
3701 i.vex.length = 3;
3702
3703 switch (i.tm.opcode_modifier.vexopcode)
3704 {
3705 case VEX0F:
3706 m = 0x1;
3707 i.vex.bytes[0] = 0xc4;
3708 break;
3709 case VEX0F38:
3710 m = 0x2;
3711 i.vex.bytes[0] = 0xc4;
3712 break;
3713 case VEX0F3A:
3714 m = 0x3;
3715 i.vex.bytes[0] = 0xc4;
3716 break;
3717 case XOP08:
3718 m = 0x8;
3719 i.vex.bytes[0] = 0x8f;
3720 break;
3721 case XOP09:
3722 m = 0x9;
3723 i.vex.bytes[0] = 0x8f;
3724 break;
3725 case XOP0A:
3726 m = 0xa;
3727 i.vex.bytes[0] = 0x8f;
3728 break;
3729 default:
3730 abort ();
3731 }
3732
3733 /* The high 3 bits of the second VEX byte are 1's compliment
3734 of RXB bits from REX. */
3735 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3736
3737 i.vex.bytes[2] = (w << 7
3738 | register_specifier << 3
3739 | vector_length << 2
3740 | implied_prefix);
3741 }
3742 }
3743
3744 static INLINE bfd_boolean
3745 is_evex_encoding (const insn_template *t)
3746 {
3747 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3748 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3749 || t->opcode_modifier.sae;
3750 }
3751
3752 static INLINE bfd_boolean
3753 is_any_vex_encoding (const insn_template *t)
3754 {
3755 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3756 || is_evex_encoding (t);
3757 }
3758
3759 /* Build the EVEX prefix. */
3760
3761 static void
3762 build_evex_prefix (void)
3763 {
3764 unsigned int register_specifier;
3765 unsigned int implied_prefix;
3766 unsigned int m, w;
3767 rex_byte vrex_used = 0;
3768
3769 /* Check register specifier. */
3770 if (i.vex.register_specifier)
3771 {
3772 gas_assert ((i.vrex & REX_X) == 0);
3773
3774 register_specifier = i.vex.register_specifier->reg_num;
3775 if ((i.vex.register_specifier->reg_flags & RegRex))
3776 register_specifier += 8;
3777 /* The upper 16 registers are encoded in the fourth byte of the
3778 EVEX prefix. */
3779 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3780 i.vex.bytes[3] = 0x8;
3781 register_specifier = ~register_specifier & 0xf;
3782 }
3783 else
3784 {
3785 register_specifier = 0xf;
3786
3787 /* Encode upper 16 vector index register in the fourth byte of
3788 the EVEX prefix. */
3789 if (!(i.vrex & REX_X))
3790 i.vex.bytes[3] = 0x8;
3791 else
3792 vrex_used |= REX_X;
3793 }
3794
3795 switch ((i.tm.base_opcode >> 8) & 0xff)
3796 {
3797 case 0:
3798 implied_prefix = 0;
3799 break;
3800 case DATA_PREFIX_OPCODE:
3801 implied_prefix = 1;
3802 break;
3803 case REPE_PREFIX_OPCODE:
3804 implied_prefix = 2;
3805 break;
3806 case REPNE_PREFIX_OPCODE:
3807 implied_prefix = 3;
3808 break;
3809 default:
3810 abort ();
3811 }
3812
3813 /* 4 byte EVEX prefix. */
3814 i.vex.length = 4;
3815 i.vex.bytes[0] = 0x62;
3816
3817 /* mmmm bits. */
3818 switch (i.tm.opcode_modifier.vexopcode)
3819 {
3820 case VEX0F:
3821 m = 1;
3822 break;
3823 case VEX0F38:
3824 m = 2;
3825 break;
3826 case VEX0F3A:
3827 m = 3;
3828 break;
3829 default:
3830 abort ();
3831 break;
3832 }
3833
3834 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3835 bits from REX. */
3836 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3837
3838 /* The fifth bit of the second EVEX byte is 1's compliment of the
3839 REX_R bit in VREX. */
3840 if (!(i.vrex & REX_R))
3841 i.vex.bytes[1] |= 0x10;
3842 else
3843 vrex_used |= REX_R;
3844
3845 if ((i.reg_operands + i.imm_operands) == i.operands)
3846 {
3847 /* When all operands are registers, the REX_X bit in REX is not
3848 used. We reuse it to encode the upper 16 registers, which is
3849 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3850 as 1's compliment. */
3851 if ((i.vrex & REX_B))
3852 {
3853 vrex_used |= REX_B;
3854 i.vex.bytes[1] &= ~0x40;
3855 }
3856 }
3857
3858 /* EVEX instructions shouldn't need the REX prefix. */
3859 i.vrex &= ~vrex_used;
3860 gas_assert (i.vrex == 0);
3861
3862 /* Check the REX.W bit and VEXW. */
3863 if (i.tm.opcode_modifier.vexw == VEXWIG)
3864 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3865 else if (i.tm.opcode_modifier.vexw)
3866 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3867 else
3868 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
3869
3870 /* Encode the U bit. */
3871 implied_prefix |= 0x4;
3872
3873 /* The third byte of the EVEX prefix. */
3874 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3875
3876 /* The fourth byte of the EVEX prefix. */
3877 /* The zeroing-masking bit. */
3878 if (i.mask && i.mask->zeroing)
3879 i.vex.bytes[3] |= 0x80;
3880
3881 /* Don't always set the broadcast bit if there is no RC. */
3882 if (!i.rounding)
3883 {
3884 /* Encode the vector length. */
3885 unsigned int vec_length;
3886
3887 if (!i.tm.opcode_modifier.evex
3888 || i.tm.opcode_modifier.evex == EVEXDYN)
3889 {
3890 unsigned int op;
3891
3892 /* Determine vector length from the last multi-length vector
3893 operand. */
3894 vec_length = 0;
3895 for (op = i.operands; op--;)
3896 if (i.tm.operand_types[op].bitfield.xmmword
3897 + i.tm.operand_types[op].bitfield.ymmword
3898 + i.tm.operand_types[op].bitfield.zmmword > 1)
3899 {
3900 if (i.types[op].bitfield.zmmword)
3901 {
3902 i.tm.opcode_modifier.evex = EVEX512;
3903 break;
3904 }
3905 else if (i.types[op].bitfield.ymmword)
3906 {
3907 i.tm.opcode_modifier.evex = EVEX256;
3908 break;
3909 }
3910 else if (i.types[op].bitfield.xmmword)
3911 {
3912 i.tm.opcode_modifier.evex = EVEX128;
3913 break;
3914 }
3915 else if (i.broadcast && (int) op == i.broadcast->operand)
3916 {
3917 switch (i.broadcast->bytes)
3918 {
3919 case 64:
3920 i.tm.opcode_modifier.evex = EVEX512;
3921 break;
3922 case 32:
3923 i.tm.opcode_modifier.evex = EVEX256;
3924 break;
3925 case 16:
3926 i.tm.opcode_modifier.evex = EVEX128;
3927 break;
3928 default:
3929 abort ();
3930 }
3931 break;
3932 }
3933 }
3934
3935 if (op >= MAX_OPERANDS)
3936 abort ();
3937 }
3938
3939 switch (i.tm.opcode_modifier.evex)
3940 {
3941 case EVEXLIG: /* LL' is ignored */
3942 vec_length = evexlig << 5;
3943 break;
3944 case EVEX128:
3945 vec_length = 0 << 5;
3946 break;
3947 case EVEX256:
3948 vec_length = 1 << 5;
3949 break;
3950 case EVEX512:
3951 vec_length = 2 << 5;
3952 break;
3953 default:
3954 abort ();
3955 break;
3956 }
3957 i.vex.bytes[3] |= vec_length;
3958 /* Encode the broadcast bit. */
3959 if (i.broadcast)
3960 i.vex.bytes[3] |= 0x10;
3961 }
3962 else
3963 {
3964 if (i.rounding->type != saeonly)
3965 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3966 else
3967 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3968 }
3969
3970 if (i.mask && i.mask->mask)
3971 i.vex.bytes[3] |= i.mask->mask->reg_num;
3972 }
3973
3974 static void
3975 process_immext (void)
3976 {
3977 expressionS *exp;
3978
3979 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3980 which is coded in the same place as an 8-bit immediate field
3981 would be. Here we fake an 8-bit immediate operand from the
3982 opcode suffix stored in tm.extension_opcode.
3983
3984 AVX instructions also use this encoding, for some of
3985 3 argument instructions. */
3986
3987 gas_assert (i.imm_operands <= 1
3988 && (i.operands <= 2
3989 || (is_any_vex_encoding (&i.tm)
3990 && i.operands <= 4)));
3991
3992 exp = &im_expressions[i.imm_operands++];
3993 i.op[i.operands].imms = exp;
3994 i.types[i.operands] = imm8;
3995 i.operands++;
3996 exp->X_op = O_constant;
3997 exp->X_add_number = i.tm.extension_opcode;
3998 i.tm.extension_opcode = None;
3999 }
4000
4001
4002 static int
4003 check_hle (void)
4004 {
4005 switch (i.tm.opcode_modifier.hleprefixok)
4006 {
4007 default:
4008 abort ();
4009 case HLEPrefixNone:
4010 as_bad (_("invalid instruction `%s' after `%s'"),
4011 i.tm.name, i.hle_prefix);
4012 return 0;
4013 case HLEPrefixLock:
4014 if (i.prefix[LOCK_PREFIX])
4015 return 1;
4016 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
4017 return 0;
4018 case HLEPrefixAny:
4019 return 1;
4020 case HLEPrefixRelease:
4021 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
4022 {
4023 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4024 i.tm.name);
4025 return 0;
4026 }
4027 if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem))
4028 {
4029 as_bad (_("memory destination needed for instruction `%s'"
4030 " after `xrelease'"), i.tm.name);
4031 return 0;
4032 }
4033 return 1;
4034 }
4035 }
4036
4037 /* Try the shortest encoding by shortening operand size. */
4038
4039 static void
4040 optimize_encoding (void)
4041 {
4042 unsigned int j;
4043
4044 if (optimize_for_space
4045 && !is_any_vex_encoding (&i.tm)
4046 && i.reg_operands == 1
4047 && i.imm_operands == 1
4048 && !i.types[1].bitfield.byte
4049 && i.op[0].imms->X_op == O_constant
4050 && fits_in_imm7 (i.op[0].imms->X_add_number)
4051 && (i.tm.base_opcode == 0xa8
4052 || (i.tm.base_opcode == 0xf6
4053 && i.tm.extension_opcode == 0x0)))
4054 {
4055 /* Optimize: -Os:
4056 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4057 */
4058 unsigned int base_regnum = i.op[1].regs->reg_num;
4059 if (flag_code == CODE_64BIT || base_regnum < 4)
4060 {
4061 i.types[1].bitfield.byte = 1;
4062 /* Ignore the suffix. */
4063 i.suffix = 0;
4064 /* Convert to byte registers. */
4065 if (i.types[1].bitfield.word)
4066 j = 16;
4067 else if (i.types[1].bitfield.dword)
4068 j = 32;
4069 else
4070 j = 48;
4071 if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4)
4072 j += 8;
4073 i.op[1].regs -= j;
4074 }
4075 }
4076 else if (flag_code == CODE_64BIT
4077 && !is_any_vex_encoding (&i.tm)
4078 && ((i.types[1].bitfield.qword
4079 && i.reg_operands == 1
4080 && i.imm_operands == 1
4081 && i.op[0].imms->X_op == O_constant
4082 && ((i.tm.base_opcode == 0xb8
4083 && i.tm.extension_opcode == None
4084 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
4085 || (fits_in_imm31 (i.op[0].imms->X_add_number)
4086 && ((i.tm.base_opcode == 0x24
4087 || i.tm.base_opcode == 0xa8)
4088 || (i.tm.base_opcode == 0x80
4089 && i.tm.extension_opcode == 0x4)
4090 || ((i.tm.base_opcode == 0xf6
4091 || (i.tm.base_opcode | 1) == 0xc7)
4092 && i.tm.extension_opcode == 0x0)))
4093 || (fits_in_imm7 (i.op[0].imms->X_add_number)
4094 && i.tm.base_opcode == 0x83
4095 && i.tm.extension_opcode == 0x4)))
4096 || (i.types[0].bitfield.qword
4097 && ((i.reg_operands == 2
4098 && i.op[0].regs == i.op[1].regs
4099 && (i.tm.base_opcode == 0x30
4100 || i.tm.base_opcode == 0x28))
4101 || (i.reg_operands == 1
4102 && i.operands == 1
4103 && i.tm.base_opcode == 0x30)))))
4104 {
4105 /* Optimize: -O:
4106 andq $imm31, %r64 -> andl $imm31, %r32
4107 andq $imm7, %r64 -> andl $imm7, %r32
4108 testq $imm31, %r64 -> testl $imm31, %r32
4109 xorq %r64, %r64 -> xorl %r32, %r32
4110 subq %r64, %r64 -> subl %r32, %r32
4111 movq $imm31, %r64 -> movl $imm31, %r32
4112 movq $imm32, %r64 -> movl $imm32, %r32
4113 */
4114 i.tm.opcode_modifier.norex64 = 1;
4115 if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7)
4116 {
4117 /* Handle
4118 movq $imm31, %r64 -> movl $imm31, %r32
4119 movq $imm32, %r64 -> movl $imm32, %r32
4120 */
4121 i.tm.operand_types[0].bitfield.imm32 = 1;
4122 i.tm.operand_types[0].bitfield.imm32s = 0;
4123 i.tm.operand_types[0].bitfield.imm64 = 0;
4124 i.types[0].bitfield.imm32 = 1;
4125 i.types[0].bitfield.imm32s = 0;
4126 i.types[0].bitfield.imm64 = 0;
4127 i.types[1].bitfield.dword = 1;
4128 i.types[1].bitfield.qword = 0;
4129 if ((i.tm.base_opcode | 1) == 0xc7)
4130 {
4131 /* Handle
4132 movq $imm31, %r64 -> movl $imm31, %r32
4133 */
4134 i.tm.base_opcode = 0xb8;
4135 i.tm.extension_opcode = None;
4136 i.tm.opcode_modifier.w = 0;
4137 i.tm.opcode_modifier.modrm = 0;
4138 }
4139 }
4140 }
4141 else if (optimize > 1
4142 && !optimize_for_space
4143 && !is_any_vex_encoding (&i.tm)
4144 && i.reg_operands == 2
4145 && i.op[0].regs == i.op[1].regs
4146 && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8
4147 || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20)
4148 && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
4149 {
4150 /* Optimize: -O2:
4151 andb %rN, %rN -> testb %rN, %rN
4152 andw %rN, %rN -> testw %rN, %rN
4153 andq %rN, %rN -> testq %rN, %rN
4154 orb %rN, %rN -> testb %rN, %rN
4155 orw %rN, %rN -> testw %rN, %rN
4156 orq %rN, %rN -> testq %rN, %rN
4157
4158 and outside of 64-bit mode
4159
4160 andl %rN, %rN -> testl %rN, %rN
4161 orl %rN, %rN -> testl %rN, %rN
4162 */
4163 i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
4164 }
4165 else if (i.reg_operands == 3
4166 && i.op[0].regs == i.op[1].regs
4167 && !i.types[2].bitfield.xmmword
4168 && (i.tm.opcode_modifier.vex
4169 || ((!i.mask || i.mask->zeroing)
4170 && !i.rounding
4171 && is_evex_encoding (&i.tm)
4172 && (i.vec_encoding != vex_encoding_evex
4173 || cpu_arch_isa_flags.bitfield.cpuavx512vl
4174 || i.tm.cpu_flags.bitfield.cpuavx512vl
4175 || (i.tm.operand_types[2].bitfield.zmmword
4176 && i.types[2].bitfield.ymmword))))
4177 && ((i.tm.base_opcode == 0x55
4178 || i.tm.base_opcode == 0x6655
4179 || i.tm.base_opcode == 0x66df
4180 || i.tm.base_opcode == 0x57
4181 || i.tm.base_opcode == 0x6657
4182 || i.tm.base_opcode == 0x66ef
4183 || i.tm.base_opcode == 0x66f8
4184 || i.tm.base_opcode == 0x66f9
4185 || i.tm.base_opcode == 0x66fa
4186 || i.tm.base_opcode == 0x66fb
4187 || i.tm.base_opcode == 0x42
4188 || i.tm.base_opcode == 0x6642
4189 || i.tm.base_opcode == 0x47
4190 || i.tm.base_opcode == 0x6647)
4191 && i.tm.extension_opcode == None))
4192 {
4193 /* Optimize: -O1:
4194 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4195 vpsubq and vpsubw:
4196 EVEX VOP %zmmM, %zmmM, %zmmN
4197 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4198 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4199 EVEX VOP %ymmM, %ymmM, %ymmN
4200 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4201 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4202 VEX VOP %ymmM, %ymmM, %ymmN
4203 -> VEX VOP %xmmM, %xmmM, %xmmN
4204 VOP, one of vpandn and vpxor:
4205 VEX VOP %ymmM, %ymmM, %ymmN
4206 -> VEX VOP %xmmM, %xmmM, %xmmN
4207 VOP, one of vpandnd and vpandnq:
4208 EVEX VOP %zmmM, %zmmM, %zmmN
4209 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4210 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4211 EVEX VOP %ymmM, %ymmM, %ymmN
4212 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 VOP, one of vpxord and vpxorq:
4215 EVEX VOP %zmmM, %zmmM, %zmmN
4216 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4217 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4218 EVEX VOP %ymmM, %ymmM, %ymmN
4219 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4220 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4221 VOP, one of kxord and kxorq:
4222 VEX VOP %kM, %kM, %kN
4223 -> VEX kxorw %kM, %kM, %kN
4224 VOP, one of kandnd and kandnq:
4225 VEX VOP %kM, %kM, %kN
4226 -> VEX kandnw %kM, %kM, %kN
4227 */
4228 if (is_evex_encoding (&i.tm))
4229 {
4230 if (i.vec_encoding != vex_encoding_evex)
4231 {
4232 i.tm.opcode_modifier.vex = VEX128;
4233 i.tm.opcode_modifier.vexw = VEXW0;
4234 i.tm.opcode_modifier.evex = 0;
4235 }
4236 else if (optimize > 1)
4237 i.tm.opcode_modifier.evex = EVEX128;
4238 else
4239 return;
4240 }
4241 else if (i.tm.operand_types[0].bitfield.class == RegMask)
4242 {
4243 i.tm.base_opcode &= 0xff;
4244 i.tm.opcode_modifier.vexw = VEXW0;
4245 }
4246 else
4247 i.tm.opcode_modifier.vex = VEX128;
4248
4249 if (i.tm.opcode_modifier.vex)
4250 for (j = 0; j < 3; j++)
4251 {
4252 i.types[j].bitfield.xmmword = 1;
4253 i.types[j].bitfield.ymmword = 0;
4254 }
4255 }
4256 else if (i.vec_encoding != vex_encoding_evex
4257 && !i.types[0].bitfield.zmmword
4258 && !i.types[1].bitfield.zmmword
4259 && !i.mask
4260 && !i.broadcast
4261 && is_evex_encoding (&i.tm)
4262 && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f
4263 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f
4264 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f
4265 || (i.tm.base_opcode & ~4) == 0x66db
4266 || (i.tm.base_opcode & ~4) == 0x66eb)
4267 && i.tm.extension_opcode == None)
4268 {
4269 /* Optimize: -O1:
4270 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4271 vmovdqu32 and vmovdqu64:
4272 EVEX VOP %xmmM, %xmmN
4273 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4274 EVEX VOP %ymmM, %ymmN
4275 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4276 EVEX VOP %xmmM, mem
4277 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4278 EVEX VOP %ymmM, mem
4279 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4280 EVEX VOP mem, %xmmN
4281 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4282 EVEX VOP mem, %ymmN
4283 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4284 VOP, one of vpand, vpandn, vpor, vpxor:
4285 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4286 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4287 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4288 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4289 EVEX VOP{d,q} mem, %xmmM, %xmmN
4290 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4291 EVEX VOP{d,q} mem, %ymmM, %ymmN
4292 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4293 */
4294 for (j = 0; j < i.operands; j++)
4295 if (operand_type_check (i.types[j], disp)
4296 && i.op[j].disps->X_op == O_constant)
4297 {
4298 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4299 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4300 bytes, we choose EVEX Disp8 over VEX Disp32. */
4301 int evex_disp8, vex_disp8;
4302 unsigned int memshift = i.memshift;
4303 offsetT n = i.op[j].disps->X_add_number;
4304
4305 evex_disp8 = fits_in_disp8 (n);
4306 i.memshift = 0;
4307 vex_disp8 = fits_in_disp8 (n);
4308 if (evex_disp8 != vex_disp8)
4309 {
4310 i.memshift = memshift;
4311 return;
4312 }
4313
4314 i.types[j].bitfield.disp8 = vex_disp8;
4315 break;
4316 }
4317 if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f)
4318 i.tm.base_opcode ^= 0xf36f ^ 0xf26f;
4319 i.tm.opcode_modifier.vex
4320 = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4321 i.tm.opcode_modifier.vexw = VEXW0;
4322 /* VPAND, VPOR, and VPXOR are commutative. */
4323 if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df)
4324 i.tm.opcode_modifier.commutative = 1;
4325 i.tm.opcode_modifier.evex = 0;
4326 i.tm.opcode_modifier.masking = 0;
4327 i.tm.opcode_modifier.broadcast = 0;
4328 i.tm.opcode_modifier.disp8memshift = 0;
4329 i.memshift = 0;
4330 if (j < i.operands)
4331 i.types[j].bitfield.disp8
4332 = fits_in_disp8 (i.op[j].disps->X_add_number);
4333 }
4334 }
4335
4336 /* Return non-zero for load instruction. */
4337
4338 static int
4339 load_insn_p (void)
4340 {
4341 unsigned int dest;
4342 int any_vex_p = is_any_vex_encoding (&i.tm);
4343 unsigned int base_opcode = i.tm.base_opcode | 1;
4344
4345 if (!any_vex_p)
4346 {
4347 /* lea */
4348 if (i.tm.base_opcode == 0x8d)
4349 return 0;
4350
4351 /* pop */
4352 if ((i.tm.base_opcode & ~7) == 0x58
4353 || (i.tm.base_opcode == 0x8f && i.tm.extension_opcode == 0))
4354 return 1;
4355
4356 /* movs, cmps, lods, scas. */
4357 if ((i.tm.base_opcode | 0xb) == 0xaf)
4358 return 1;
4359
4360 /* outs */
4361 if (base_opcode == 0x6f)
4362 return 1;
4363 }
4364
4365 /* No memory operand. */
4366 if (!i.mem_operands)
4367 return 0;
4368
4369 if (any_vex_p)
4370 {
4371 /* vldmxcsr. */
4372 if (i.tm.base_opcode == 0xae
4373 && i.tm.opcode_modifier.vex
4374 && i.tm.opcode_modifier.vexopcode == VEX0F
4375 && i.tm.extension_opcode == 2)
4376 return 1;
4377 }
4378 else
4379 {
4380 /* test, not, neg, mul, imul, div, idiv. */
4381 if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7)
4382 && i.tm.extension_opcode != 1)
4383 return 1;
4384
4385 /* inc, dec. */
4386 if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
4387 return 1;
4388
4389 /* add, or, adc, sbb, and, sub, xor, cmp. */
4390 if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
4391 return 1;
4392
4393 /* bt, bts, btr, btc. */
4394 if (i.tm.base_opcode == 0xfba
4395 && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7))
4396 return 1;
4397
4398 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4399 if ((base_opcode == 0xc1
4400 || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3))
4401 && i.tm.extension_opcode != 6)
4402 return 1;
4403
4404 /* cmpxchg8b, cmpxchg16b, xrstors. */
4405 if (i.tm.base_opcode == 0xfc7
4406 && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3))
4407 return 1;
4408
4409 /* fxrstor, ldmxcsr, xrstor. */
4410 if (i.tm.base_opcode == 0xfae
4411 && (i.tm.extension_opcode == 1
4412 || i.tm.extension_opcode == 2
4413 || i.tm.extension_opcode == 5))
4414 return 1;
4415
4416 /* lgdt, lidt, lmsw. */
4417 if (i.tm.base_opcode == 0xf01
4418 && (i.tm.extension_opcode == 2
4419 || i.tm.extension_opcode == 3
4420 || i.tm.extension_opcode == 6))
4421 return 1;
4422
4423 /* vmptrld */
4424 if (i.tm.base_opcode == 0xfc7
4425 && i.tm.extension_opcode == 6)
4426 return 1;
4427
4428 /* Check for x87 instructions. */
4429 if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf)
4430 {
4431 /* Skip fst, fstp, fstenv, fstcw. */
4432 if (i.tm.base_opcode == 0xd9
4433 && (i.tm.extension_opcode == 2
4434 || i.tm.extension_opcode == 3
4435 || i.tm.extension_opcode == 6
4436 || i.tm.extension_opcode == 7))
4437 return 0;
4438
4439 /* Skip fisttp, fist, fistp, fstp. */
4440 if (i.tm.base_opcode == 0xdb
4441 && (i.tm.extension_opcode == 1
4442 || i.tm.extension_opcode == 2
4443 || i.tm.extension_opcode == 3
4444 || i.tm.extension_opcode == 7))
4445 return 0;
4446
4447 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4448 if (i.tm.base_opcode == 0xdd
4449 && (i.tm.extension_opcode == 1
4450 || i.tm.extension_opcode == 2
4451 || i.tm.extension_opcode == 3
4452 || i.tm.extension_opcode == 6
4453 || i.tm.extension_opcode == 7))
4454 return 0;
4455
4456 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4457 if (i.tm.base_opcode == 0xdf
4458 && (i.tm.extension_opcode == 1
4459 || i.tm.extension_opcode == 2
4460 || i.tm.extension_opcode == 3
4461 || i.tm.extension_opcode == 6
4462 || i.tm.extension_opcode == 7))
4463 return 0;
4464
4465 return 1;
4466 }
4467 }
4468
4469 dest = i.operands - 1;
4470
4471 /* Check fake imm8 operand and 3 source operands. */
4472 if ((i.tm.opcode_modifier.immext
4473 || i.tm.opcode_modifier.vexsources == VEX3SOURCES)
4474 && i.types[dest].bitfield.imm8)
4475 dest--;
4476
4477 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4478 if (!any_vex_p
4479 && (base_opcode == 0x1
4480 || base_opcode == 0x9
4481 || base_opcode == 0x11
4482 || base_opcode == 0x19
4483 || base_opcode == 0x21
4484 || base_opcode == 0x29
4485 || base_opcode == 0x31
4486 || base_opcode == 0x39
4487 || (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87)
4488 || base_opcode == 0xfc1))
4489 return 1;
4490
4491 /* Check for load instruction. */
4492 return (i.types[dest].bitfield.class != ClassNone
4493 || i.types[dest].bitfield.instance == Accum);
4494 }
4495
4496 /* Output lfence, 0xfaee8, after instruction. */
4497
4498 static void
4499 insert_lfence_after (void)
4500 {
4501 if (lfence_after_load && load_insn_p ())
4502 {
4503 char *p = frag_more (3);
4504 *p++ = 0xf;
4505 *p++ = 0xae;
4506 *p = 0xe8;
4507 }
4508 }
4509
4510 /* Output lfence, 0xfaee8, before instruction. */
4511
4512 static void
4513 insert_lfence_before (void)
4514 {
4515 char *p;
4516
4517 if (is_any_vex_encoding (&i.tm))
4518 return;
4519
4520 if (i.tm.base_opcode == 0xff
4521 && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
4522 {
4523 /* Insert lfence before indirect branch if needed. */
4524
4525 if (lfence_before_indirect_branch == lfence_branch_none)
4526 return;
4527
4528 if (i.operands != 1)
4529 abort ();
4530
4531 if (i.reg_operands == 1)
4532 {
4533 /* Indirect branch via register. Don't insert lfence with
4534 -mlfence-after-load=yes. */
4535 if (lfence_after_load
4536 || lfence_before_indirect_branch == lfence_branch_memory)
4537 return;
4538 }
4539 else if (i.mem_operands == 1
4540 && lfence_before_indirect_branch != lfence_branch_register)
4541 {
4542 as_warn (_("indirect `%s` with memory operand should be avoided"),
4543 i.tm.name);
4544 return;
4545 }
4546 else
4547 return;
4548
4549 if (last_insn.kind != last_insn_other
4550 && last_insn.seg == now_seg)
4551 {
4552 as_warn_where (last_insn.file, last_insn.line,
4553 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4554 last_insn.name, i.tm.name);
4555 return;
4556 }
4557
4558 p = frag_more (3);
4559 *p++ = 0xf;
4560 *p++ = 0xae;
4561 *p = 0xe8;
4562 return;
4563 }
4564
4565 /* Output or/not and lfence before ret. */
4566 if (lfence_before_ret != lfence_before_ret_none
4567 && (i.tm.base_opcode == 0xc2
4568 || i.tm.base_opcode == 0xc3
4569 || i.tm.base_opcode == 0xca
4570 || i.tm.base_opcode == 0xcb))
4571 {
4572 if (last_insn.kind != last_insn_other
4573 && last_insn.seg == now_seg)
4574 {
4575 as_warn_where (last_insn.file, last_insn.line,
4576 _("`%s` skips -mlfence-before-ret on `%s`"),
4577 last_insn.name, i.tm.name);
4578 return;
4579 }
4580 if (lfence_before_ret == lfence_before_ret_or)
4581 {
4582 /* orl: 0x830c2400. */
4583 p = frag_more ((flag_code == CODE_64BIT ? 1 : 0) + 4 + 3);
4584 if (flag_code == CODE_64BIT)
4585 *p++ = 0x48;
4586 *p++ = 0x83;
4587 *p++ = 0xc;
4588 *p++ = 0x24;
4589 *p++ = 0x0;
4590 }
4591 else
4592 {
4593 p = frag_more ((flag_code == CODE_64BIT ? 2 : 0) + 6 + 3);
4594 /* notl: 0xf71424. */
4595 if (flag_code == CODE_64BIT)
4596 *p++ = 0x48;
4597 *p++ = 0xf7;
4598 *p++ = 0x14;
4599 *p++ = 0x24;
4600 /* notl: 0xf71424. */
4601 if (flag_code == CODE_64BIT)
4602 *p++ = 0x48;
4603 *p++ = 0xf7;
4604 *p++ = 0x14;
4605 *p++ = 0x24;
4606 }
4607 *p++ = 0xf;
4608 *p++ = 0xae;
4609 *p = 0xe8;
4610 }
4611 }
4612
4613 /* This is the guts of the machine-dependent assembler. LINE points to a
4614 machine dependent instruction. This function is supposed to emit
4615 the frags/bytes it assembles to. */
4616
4617 void
4618 md_assemble (char *line)
4619 {
4620 unsigned int j;
4621 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4622 const insn_template *t;
4623
4624 /* Initialize globals. */
4625 memset (&i, '\0', sizeof (i));
4626 for (j = 0; j < MAX_OPERANDS; j++)
4627 i.reloc[j] = NO_RELOC;
4628 memset (disp_expressions, '\0', sizeof (disp_expressions));
4629 memset (im_expressions, '\0', sizeof (im_expressions));
4630 save_stack_p = save_stack;
4631
4632 /* First parse an instruction mnemonic & call i386_operand for the operands.
4633 We assume that the scrubber has arranged it so that line[0] is the valid
4634 start of a (possibly prefixed) mnemonic. */
4635
4636 line = parse_insn (line, mnemonic);
4637 if (line == NULL)
4638 return;
4639 mnem_suffix = i.suffix;
4640
4641 line = parse_operands (line, mnemonic);
4642 this_operand = -1;
4643 xfree (i.memop1_string);
4644 i.memop1_string = NULL;
4645 if (line == NULL)
4646 return;
4647
4648 /* Now we've parsed the mnemonic into a set of templates, and have the
4649 operands at hand. */
4650
4651 /* All Intel opcodes have reversed operands except for "bound", "enter",
4652 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4653 intersegment "jmp" and "call" instructions with 2 immediate operands so
4654 that the immediate segment precedes the offset, as it does when in AT&T
4655 mode. */
4656 if (intel_syntax
4657 && i.operands > 1
4658 && (strcmp (mnemonic, "bound") != 0)
4659 && (strcmp (mnemonic, "invlpga") != 0)
4660 && (strncmp (mnemonic, "monitor", 7) != 0)
4661 && (strncmp (mnemonic, "mwait", 5) != 0)
4662 && (strcmp (mnemonic, "tpause") != 0)
4663 && (strcmp (mnemonic, "umwait") != 0)
4664 && !(operand_type_check (i.types[0], imm)
4665 && operand_type_check (i.types[1], imm)))
4666 swap_operands ();
4667
4668 /* The order of the immediates should be reversed
4669 for 2 immediates extrq and insertq instructions */
4670 if (i.imm_operands == 2
4671 && (strcmp (mnemonic, "extrq") == 0
4672 || strcmp (mnemonic, "insertq") == 0))
4673 swap_2_operands (0, 1);
4674
4675 if (i.imm_operands)
4676 optimize_imm ();
4677
4678 /* Don't optimize displacement for movabs since it only takes 64bit
4679 displacement. */
4680 if (i.disp_operands
4681 && i.disp_encoding != disp_encoding_32bit
4682 && (flag_code != CODE_64BIT
4683 || strcmp (mnemonic, "movabs") != 0))
4684 optimize_disp ();
4685
4686 /* Next, we find a template that matches the given insn,
4687 making sure the overlap of the given operands types is consistent
4688 with the template operand types. */
4689
4690 if (!(t = match_template (mnem_suffix)))
4691 return;
4692
4693 if (sse_check != check_none
4694 && !i.tm.opcode_modifier.noavx
4695 && !i.tm.cpu_flags.bitfield.cpuavx
4696 && !i.tm.cpu_flags.bitfield.cpuavx512f
4697 && (i.tm.cpu_flags.bitfield.cpusse
4698 || i.tm.cpu_flags.bitfield.cpusse2
4699 || i.tm.cpu_flags.bitfield.cpusse3
4700 || i.tm.cpu_flags.bitfield.cpussse3
4701 || i.tm.cpu_flags.bitfield.cpusse4_1
4702 || i.tm.cpu_flags.bitfield.cpusse4_2
4703 || i.tm.cpu_flags.bitfield.cpusse4a
4704 || i.tm.cpu_flags.bitfield.cpupclmul
4705 || i.tm.cpu_flags.bitfield.cpuaes
4706 || i.tm.cpu_flags.bitfield.cpusha
4707 || i.tm.cpu_flags.bitfield.cpugfni))
4708 {
4709 (sse_check == check_warning
4710 ? as_warn
4711 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4712 }
4713
4714 if (i.tm.opcode_modifier.fwait)
4715 if (!add_prefix (FWAIT_OPCODE))
4716 return;
4717
4718 /* Check if REP prefix is OK. */
4719 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4720 {
4721 as_bad (_("invalid instruction `%s' after `%s'"),
4722 i.tm.name, i.rep_prefix);
4723 return;
4724 }
4725
4726 /* Check for lock without a lockable instruction. Destination operand
4727 must be memory unless it is xchg (0x86). */
4728 if (i.prefix[LOCK_PREFIX]
4729 && (!i.tm.opcode_modifier.islockable
4730 || i.mem_operands == 0
4731 || (i.tm.base_opcode != 0x86
4732 && !(i.flags[i.operands - 1] & Operand_Mem))))
4733 {
4734 as_bad (_("expecting lockable instruction after `lock'"));
4735 return;
4736 }
4737
4738 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4739 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4740 {
4741 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4742 return;
4743 }
4744
4745 /* Check if HLE prefix is OK. */
4746 if (i.hle_prefix && !check_hle ())
4747 return;
4748
4749 /* Check BND prefix. */
4750 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4751 as_bad (_("expecting valid branch instruction after `bnd'"));
4752
4753 /* Check NOTRACK prefix. */
4754 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4755 as_bad (_("expecting indirect branch instruction after `notrack'"));
4756
4757 if (i.tm.cpu_flags.bitfield.cpumpx)
4758 {
4759 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4760 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4761 else if (flag_code != CODE_16BIT
4762 ? i.prefix[ADDR_PREFIX]
4763 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4764 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4765 }
4766
4767 /* Insert BND prefix. */
4768 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4769 {
4770 if (!i.prefix[BND_PREFIX])
4771 add_prefix (BND_PREFIX_OPCODE);
4772 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4773 {
4774 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4775 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4776 }
4777 }
4778
4779 /* Check string instruction segment overrides. */
4780 if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0)
4781 {
4782 gas_assert (i.mem_operands);
4783 if (!check_string ())
4784 return;
4785 i.disp_operands = 0;
4786 }
4787
4788 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4789 optimize_encoding ();
4790
4791 if (!process_suffix ())
4792 return;
4793
4794 /* Update operand types. */
4795 for (j = 0; j < i.operands; j++)
4796 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4797
4798 /* Make still unresolved immediate matches conform to size of immediate
4799 given in i.suffix. */
4800 if (!finalize_imm ())
4801 return;
4802
4803 if (i.types[0].bitfield.imm1)
4804 i.imm_operands = 0; /* kludge for shift insns. */
4805
4806 /* We only need to check those implicit registers for instructions
4807 with 3 operands or less. */
4808 if (i.operands <= 3)
4809 for (j = 0; j < i.operands; j++)
4810 if (i.types[j].bitfield.instance != InstanceNone
4811 && !i.types[j].bitfield.xmmword)
4812 i.reg_operands--;
4813
4814 /* ImmExt should be processed after SSE2AVX. */
4815 if (!i.tm.opcode_modifier.sse2avx
4816 && i.tm.opcode_modifier.immext)
4817 process_immext ();
4818
4819 /* For insns with operands there are more diddles to do to the opcode. */
4820 if (i.operands)
4821 {
4822 if (!process_operands ())
4823 return;
4824 }
4825 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4826 {
4827 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4828 as_warn (_("translating to `%sp'"), i.tm.name);
4829 }
4830
4831 if (is_any_vex_encoding (&i.tm))
4832 {
4833 if (!cpu_arch_flags.bitfield.cpui286)
4834 {
4835 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4836 i.tm.name);
4837 return;
4838 }
4839
4840 if (i.tm.opcode_modifier.vex)
4841 build_vex_prefix (t);
4842 else
4843 build_evex_prefix ();
4844 }
4845
4846 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4847 instructions may define INT_OPCODE as well, so avoid this corner
4848 case for those instructions that use MODRM. */
4849 if (i.tm.base_opcode == INT_OPCODE
4850 && !i.tm.opcode_modifier.modrm
4851 && i.op[0].imms->X_add_number == 3)
4852 {
4853 i.tm.base_opcode = INT3_OPCODE;
4854 i.imm_operands = 0;
4855 }
4856
4857 if ((i.tm.opcode_modifier.jump == JUMP
4858 || i.tm.opcode_modifier.jump == JUMP_BYTE
4859 || i.tm.opcode_modifier.jump == JUMP_DWORD)
4860 && i.op[0].disps->X_op == O_constant)
4861 {
4862 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4863 the absolute address given by the constant. Since ix86 jumps and
4864 calls are pc relative, we need to generate a reloc. */
4865 i.op[0].disps->X_add_symbol = &abs_symbol;
4866 i.op[0].disps->X_op = O_symbol;
4867 }
4868
4869 /* For 8 bit registers we need an empty rex prefix. Also if the
4870 instruction already has a prefix, we need to convert old
4871 registers to new ones. */
4872
4873 if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte
4874 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4875 || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte
4876 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4877 || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte)
4878 || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte))
4879 && i.rex != 0))
4880 {
4881 int x;
4882
4883 i.rex |= REX_OPCODE;
4884 for (x = 0; x < 2; x++)
4885 {
4886 /* Look for 8 bit operand that uses old registers. */
4887 if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
4888 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4889 {
4890 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4891 /* In case it is "hi" register, give up. */
4892 if (i.op[x].regs->reg_num > 3)
4893 as_bad (_("can't encode register '%s%s' in an "
4894 "instruction requiring REX prefix."),
4895 register_prefix, i.op[x].regs->reg_name);
4896
4897 /* Otherwise it is equivalent to the extended register.
4898 Since the encoding doesn't change this is merely
4899 cosmetic cleanup for debug output. */
4900
4901 i.op[x].regs = i.op[x].regs + 8;
4902 }
4903 }
4904 }
4905
4906 if (i.rex == 0 && i.rex_encoding)
4907 {
4908 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4909 that uses legacy register. If it is "hi" register, don't add
4910 the REX_OPCODE byte. */
4911 int x;
4912 for (x = 0; x < 2; x++)
4913 if (i.types[x].bitfield.class == Reg
4914 && i.types[x].bitfield.byte
4915 && (i.op[x].regs->reg_flags & RegRex64) == 0
4916 && i.op[x].regs->reg_num > 3)
4917 {
4918 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4919 i.rex_encoding = FALSE;
4920 break;
4921 }
4922
4923 if (i.rex_encoding)
4924 i.rex = REX_OPCODE;
4925 }
4926
4927 if (i.rex != 0)
4928 add_prefix (REX_OPCODE | i.rex);
4929
4930 insert_lfence_before ();
4931
4932 /* We are ready to output the insn. */
4933 output_insn ();
4934
4935 insert_lfence_after ();
4936
4937 last_insn.seg = now_seg;
4938
4939 if (i.tm.opcode_modifier.isprefix)
4940 {
4941 last_insn.kind = last_insn_prefix;
4942 last_insn.name = i.tm.name;
4943 last_insn.file = as_where (&last_insn.line);
4944 }
4945 else
4946 last_insn.kind = last_insn_other;
4947 }
4948
4949 static char *
4950 parse_insn (char *line, char *mnemonic)
4951 {
4952 char *l = line;
4953 char *token_start = l;
4954 char *mnem_p;
4955 int supported;
4956 const insn_template *t;
4957 char *dot_p = NULL;
4958
4959 while (1)
4960 {
4961 mnem_p = mnemonic;
4962 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4963 {
4964 if (*mnem_p == '.')
4965 dot_p = mnem_p;
4966 mnem_p++;
4967 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4968 {
4969 as_bad (_("no such instruction: `%s'"), token_start);
4970 return NULL;
4971 }
4972 l++;
4973 }
4974 if (!is_space_char (*l)
4975 && *l != END_OF_INSN
4976 && (intel_syntax
4977 || (*l != PREFIX_SEPARATOR
4978 && *l != ',')))
4979 {
4980 as_bad (_("invalid character %s in mnemonic"),
4981 output_invalid (*l));
4982 return NULL;
4983 }
4984 if (token_start == l)
4985 {
4986 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4987 as_bad (_("expecting prefix; got nothing"));
4988 else
4989 as_bad (_("expecting mnemonic; got nothing"));
4990 return NULL;
4991 }
4992
4993 /* Look up instruction (or prefix) via hash table. */
4994 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4995
4996 if (*l != END_OF_INSN
4997 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4998 && current_templates
4999 && current_templates->start->opcode_modifier.isprefix)
5000 {
5001 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
5002 {
5003 as_bad ((flag_code != CODE_64BIT
5004 ? _("`%s' is only supported in 64-bit mode")
5005 : _("`%s' is not supported in 64-bit mode")),
5006 current_templates->start->name);
5007 return NULL;
5008 }
5009 /* If we are in 16-bit mode, do not allow addr16 or data16.
5010 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5011 if ((current_templates->start->opcode_modifier.size == SIZE16
5012 || current_templates->start->opcode_modifier.size == SIZE32)
5013 && flag_code != CODE_64BIT
5014 && ((current_templates->start->opcode_modifier.size == SIZE32)
5015 ^ (flag_code == CODE_16BIT)))
5016 {
5017 as_bad (_("redundant %s prefix"),
5018 current_templates->start->name);
5019 return NULL;
5020 }
5021 if (current_templates->start->opcode_length == 0)
5022 {
5023 /* Handle pseudo prefixes. */
5024 switch (current_templates->start->base_opcode)
5025 {
5026 case 0x0:
5027 /* {disp8} */
5028 i.disp_encoding = disp_encoding_8bit;
5029 break;
5030 case 0x1:
5031 /* {disp32} */
5032 i.disp_encoding = disp_encoding_32bit;
5033 break;
5034 case 0x2:
5035 /* {load} */
5036 i.dir_encoding = dir_encoding_load;
5037 break;
5038 case 0x3:
5039 /* {store} */
5040 i.dir_encoding = dir_encoding_store;
5041 break;
5042 case 0x4:
5043 /* {vex} */
5044 i.vec_encoding = vex_encoding_vex;
5045 break;
5046 case 0x5:
5047 /* {vex3} */
5048 i.vec_encoding = vex_encoding_vex3;
5049 break;
5050 case 0x6:
5051 /* {evex} */
5052 i.vec_encoding = vex_encoding_evex;
5053 break;
5054 case 0x7:
5055 /* {rex} */
5056 i.rex_encoding = TRUE;
5057 break;
5058 case 0x8:
5059 /* {nooptimize} */
5060 i.no_optimize = TRUE;
5061 break;
5062 default:
5063 abort ();
5064 }
5065 }
5066 else
5067 {
5068 /* Add prefix, checking for repeated prefixes. */
5069 switch (add_prefix (current_templates->start->base_opcode))
5070 {
5071 case PREFIX_EXIST:
5072 return NULL;
5073 case PREFIX_DS:
5074 if (current_templates->start->cpu_flags.bitfield.cpuibt)
5075 i.notrack_prefix = current_templates->start->name;
5076 break;
5077 case PREFIX_REP:
5078 if (current_templates->start->cpu_flags.bitfield.cpuhle)
5079 i.hle_prefix = current_templates->start->name;
5080 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
5081 i.bnd_prefix = current_templates->start->name;
5082 else
5083 i.rep_prefix = current_templates->start->name;
5084 break;
5085 default:
5086 break;
5087 }
5088 }
5089 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5090 token_start = ++l;
5091 }
5092 else
5093 break;
5094 }
5095
5096 if (!current_templates)
5097 {
5098 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5099 Check if we should swap operand or force 32bit displacement in
5100 encoding. */
5101 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
5102 i.dir_encoding = dir_encoding_swap;
5103 else if (mnem_p - 3 == dot_p
5104 && dot_p[1] == 'd'
5105 && dot_p[2] == '8')
5106 i.disp_encoding = disp_encoding_8bit;
5107 else if (mnem_p - 4 == dot_p
5108 && dot_p[1] == 'd'
5109 && dot_p[2] == '3'
5110 && dot_p[3] == '2')
5111 i.disp_encoding = disp_encoding_32bit;
5112 else
5113 goto check_suffix;
5114 mnem_p = dot_p;
5115 *dot_p = '\0';
5116 current_templates = (const templates *) hash_find (op_hash, mnemonic);
5117 }
5118
5119 if (!current_templates)
5120 {
5121 check_suffix:
5122 if (mnem_p > mnemonic)
5123 {
5124 /* See if we can get a match by trimming off a suffix. */
5125 switch (mnem_p[-1])
5126 {
5127 case WORD_MNEM_SUFFIX:
5128 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
5129 i.suffix = SHORT_MNEM_SUFFIX;
5130 else
5131 /* Fall through. */
5132 case BYTE_MNEM_SUFFIX:
5133 case QWORD_MNEM_SUFFIX:
5134 i.suffix = mnem_p[-1];
5135 mnem_p[-1] = '\0';
5136 current_templates = (const templates *) hash_find (op_hash,
5137 mnemonic);
5138 break;
5139 case SHORT_MNEM_SUFFIX:
5140 case LONG_MNEM_SUFFIX:
5141 if (!intel_syntax)
5142 {
5143 i.suffix = mnem_p[-1];
5144 mnem_p[-1] = '\0';
5145 current_templates = (const templates *) hash_find (op_hash,
5146 mnemonic);
5147 }
5148 break;
5149
5150 /* Intel Syntax. */
5151 case 'd':
5152 if (intel_syntax)
5153 {
5154 if (intel_float_operand (mnemonic) == 1)
5155 i.suffix = SHORT_MNEM_SUFFIX;
5156 else
5157 i.suffix = LONG_MNEM_SUFFIX;
5158 mnem_p[-1] = '\0';
5159 current_templates = (const templates *) hash_find (op_hash,
5160 mnemonic);
5161 }
5162 break;
5163 }
5164 }
5165
5166 if (!current_templates)
5167 {
5168 as_bad (_("no such instruction: `%s'"), token_start);
5169 return NULL;
5170 }
5171 }
5172
5173 if (current_templates->start->opcode_modifier.jump == JUMP
5174 || current_templates->start->opcode_modifier.jump == JUMP_BYTE)
5175 {
5176 /* Check for a branch hint. We allow ",pt" and ",pn" for
5177 predict taken and predict not taken respectively.
5178 I'm not sure that branch hints actually do anything on loop
5179 and jcxz insns (JumpByte) for current Pentium4 chips. They
5180 may work in the future and it doesn't hurt to accept them
5181 now. */
5182 if (l[0] == ',' && l[1] == 'p')
5183 {
5184 if (l[2] == 't')
5185 {
5186 if (!add_prefix (DS_PREFIX_OPCODE))
5187 return NULL;
5188 l += 3;
5189 }
5190 else if (l[2] == 'n')
5191 {
5192 if (!add_prefix (CS_PREFIX_OPCODE))
5193 return NULL;
5194 l += 3;
5195 }
5196 }
5197 }
5198 /* Any other comma loses. */
5199 if (*l == ',')
5200 {
5201 as_bad (_("invalid character %s in mnemonic"),
5202 output_invalid (*l));
5203 return NULL;
5204 }
5205
5206 /* Check if instruction is supported on specified architecture. */
5207 supported = 0;
5208 for (t = current_templates->start; t < current_templates->end; ++t)
5209 {
5210 supported |= cpu_flags_match (t);
5211 if (supported == CPU_FLAGS_PERFECT_MATCH)
5212 {
5213 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
5214 as_warn (_("use .code16 to ensure correct addressing mode"));
5215
5216 return l;
5217 }
5218 }
5219
5220 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5221 as_bad (flag_code == CODE_64BIT
5222 ? _("`%s' is not supported in 64-bit mode")
5223 : _("`%s' is only supported in 64-bit mode"),
5224 current_templates->start->name);
5225 else
5226 as_bad (_("`%s' is not supported on `%s%s'"),
5227 current_templates->start->name,
5228 cpu_arch_name ? cpu_arch_name : default_arch,
5229 cpu_sub_arch_name ? cpu_sub_arch_name : "");
5230
5231 return NULL;
5232 }
5233
5234 static char *
5235 parse_operands (char *l, const char *mnemonic)
5236 {
5237 char *token_start;
5238
5239 /* 1 if operand is pending after ','. */
5240 unsigned int expecting_operand = 0;
5241
5242 /* Non-zero if operand parens not balanced. */
5243 unsigned int paren_not_balanced;
5244
5245 while (*l != END_OF_INSN)
5246 {
5247 /* Skip optional white space before operand. */
5248 if (is_space_char (*l))
5249 ++l;
5250 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
5251 {
5252 as_bad (_("invalid character %s before operand %d"),
5253 output_invalid (*l),
5254 i.operands + 1);
5255 return NULL;
5256 }
5257 token_start = l; /* After white space. */
5258 paren_not_balanced = 0;
5259 while (paren_not_balanced || *l != ',')
5260 {
5261 if (*l == END_OF_INSN)
5262 {
5263 if (paren_not_balanced)
5264 {
5265 if (!intel_syntax)
5266 as_bad (_("unbalanced parenthesis in operand %d."),
5267 i.operands + 1);
5268 else
5269 as_bad (_("unbalanced brackets in operand %d."),
5270 i.operands + 1);
5271 return NULL;
5272 }
5273 else
5274 break; /* we are done */
5275 }
5276 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
5277 {
5278 as_bad (_("invalid character %s in operand %d"),
5279 output_invalid (*l),
5280 i.operands + 1);
5281 return NULL;
5282 }
5283 if (!intel_syntax)
5284 {
5285 if (*l == '(')
5286 ++paren_not_balanced;
5287 if (*l == ')')
5288 --paren_not_balanced;
5289 }
5290 else
5291 {
5292 if (*l == '[')
5293 ++paren_not_balanced;
5294 if (*l == ']')
5295 --paren_not_balanced;
5296 }
5297 l++;
5298 }
5299 if (l != token_start)
5300 { /* Yes, we've read in another operand. */
5301 unsigned int operand_ok;
5302 this_operand = i.operands++;
5303 if (i.operands > MAX_OPERANDS)
5304 {
5305 as_bad (_("spurious operands; (%d operands/instruction max)"),
5306 MAX_OPERANDS);
5307 return NULL;
5308 }
5309 i.types[this_operand].bitfield.unspecified = 1;
5310 /* Now parse operand adding info to 'i' as we go along. */
5311 END_STRING_AND_SAVE (l);
5312
5313 if (i.mem_operands > 1)
5314 {
5315 as_bad (_("too many memory references for `%s'"),
5316 mnemonic);
5317 return 0;
5318 }
5319
5320 if (intel_syntax)
5321 operand_ok =
5322 i386_intel_operand (token_start,
5323 intel_float_operand (mnemonic));
5324 else
5325 operand_ok = i386_att_operand (token_start);
5326
5327 RESTORE_END_STRING (l);
5328 if (!operand_ok)
5329 return NULL;
5330 }
5331 else
5332 {
5333 if (expecting_operand)
5334 {
5335 expecting_operand_after_comma:
5336 as_bad (_("expecting operand after ','; got nothing"));
5337 return NULL;
5338 }
5339 if (*l == ',')
5340 {
5341 as_bad (_("expecting operand before ','; got nothing"));
5342 return NULL;
5343 }
5344 }
5345
5346 /* Now *l must be either ',' or END_OF_INSN. */
5347 if (*l == ',')
5348 {
5349 if (*++l == END_OF_INSN)
5350 {
5351 /* Just skip it, if it's \n complain. */
5352 goto expecting_operand_after_comma;
5353 }
5354 expecting_operand = 1;
5355 }
5356 }
5357 return l;
5358 }
5359
5360 static void
5361 swap_2_operands (int xchg1, int xchg2)
5362 {
5363 union i386_op temp_op;
5364 i386_operand_type temp_type;
5365 unsigned int temp_flags;
5366 enum bfd_reloc_code_real temp_reloc;
5367
5368 temp_type = i.types[xchg2];
5369 i.types[xchg2] = i.types[xchg1];
5370 i.types[xchg1] = temp_type;
5371
5372 temp_flags = i.flags[xchg2];
5373 i.flags[xchg2] = i.flags[xchg1];
5374 i.flags[xchg1] = temp_flags;
5375
5376 temp_op = i.op[xchg2];
5377 i.op[xchg2] = i.op[xchg1];
5378 i.op[xchg1] = temp_op;
5379
5380 temp_reloc = i.reloc[xchg2];
5381 i.reloc[xchg2] = i.reloc[xchg1];
5382 i.reloc[xchg1] = temp_reloc;
5383
5384 if (i.mask)
5385 {
5386 if (i.mask->operand == xchg1)
5387 i.mask->operand = xchg2;
5388 else if (i.mask->operand == xchg2)
5389 i.mask->operand = xchg1;
5390 }
5391 if (i.broadcast)
5392 {
5393 if (i.broadcast->operand == xchg1)
5394 i.broadcast->operand = xchg2;
5395 else if (i.broadcast->operand == xchg2)
5396 i.broadcast->operand = xchg1;
5397 }
5398 if (i.rounding)
5399 {
5400 if (i.rounding->operand == xchg1)
5401 i.rounding->operand = xchg2;
5402 else if (i.rounding->operand == xchg2)
5403 i.rounding->operand = xchg1;
5404 }
5405 }
5406
5407 static void
5408 swap_operands (void)
5409 {
5410 switch (i.operands)
5411 {
5412 case 5:
5413 case 4:
5414 swap_2_operands (1, i.operands - 2);
5415 /* Fall through. */
5416 case 3:
5417 case 2:
5418 swap_2_operands (0, i.operands - 1);
5419 break;
5420 default:
5421 abort ();
5422 }
5423
5424 if (i.mem_operands == 2)
5425 {
5426 const seg_entry *temp_seg;
5427 temp_seg = i.seg[0];
5428 i.seg[0] = i.seg[1];
5429 i.seg[1] = temp_seg;
5430 }
5431 }
5432
5433 /* Try to ensure constant immediates are represented in the smallest
5434 opcode possible. */
5435 static void
5436 optimize_imm (void)
5437 {
5438 char guess_suffix = 0;
5439 int op;
5440
5441 if (i.suffix)
5442 guess_suffix = i.suffix;
5443 else if (i.reg_operands)
5444 {
5445 /* Figure out a suffix from the last register operand specified.
5446 We can't do this properly yet, i.e. excluding special register
5447 instances, but the following works for instructions with
5448 immediates. In any case, we can't set i.suffix yet. */
5449 for (op = i.operands; --op >= 0;)
5450 if (i.types[op].bitfield.class != Reg)
5451 continue;
5452 else if (i.types[op].bitfield.byte)
5453 {
5454 guess_suffix = BYTE_MNEM_SUFFIX;
5455 break;
5456 }
5457 else if (i.types[op].bitfield.word)
5458 {
5459 guess_suffix = WORD_MNEM_SUFFIX;
5460 break;
5461 }
5462 else if (i.types[op].bitfield.dword)
5463 {
5464 guess_suffix = LONG_MNEM_SUFFIX;
5465 break;
5466 }
5467 else if (i.types[op].bitfield.qword)
5468 {
5469 guess_suffix = QWORD_MNEM_SUFFIX;
5470 break;
5471 }
5472 }
5473 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5474 guess_suffix = WORD_MNEM_SUFFIX;
5475
5476 for (op = i.operands; --op >= 0;)
5477 if (operand_type_check (i.types[op], imm))
5478 {
5479 switch (i.op[op].imms->X_op)
5480 {
5481 case O_constant:
5482 /* If a suffix is given, this operand may be shortened. */
5483 switch (guess_suffix)
5484 {
5485 case LONG_MNEM_SUFFIX:
5486 i.types[op].bitfield.imm32 = 1;
5487 i.types[op].bitfield.imm64 = 1;
5488 break;
5489 case WORD_MNEM_SUFFIX:
5490 i.types[op].bitfield.imm16 = 1;
5491 i.types[op].bitfield.imm32 = 1;
5492 i.types[op].bitfield.imm32s = 1;
5493 i.types[op].bitfield.imm64 = 1;
5494 break;
5495 case BYTE_MNEM_SUFFIX:
5496 i.types[op].bitfield.imm8 = 1;
5497 i.types[op].bitfield.imm8s = 1;
5498 i.types[op].bitfield.imm16 = 1;
5499 i.types[op].bitfield.imm32 = 1;
5500 i.types[op].bitfield.imm32s = 1;
5501 i.types[op].bitfield.imm64 = 1;
5502 break;
5503 }
5504
5505 /* If this operand is at most 16 bits, convert it
5506 to a signed 16 bit number before trying to see
5507 whether it will fit in an even smaller size.
5508 This allows a 16-bit operand such as $0xffe0 to
5509 be recognised as within Imm8S range. */
5510 if ((i.types[op].bitfield.imm16)
5511 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
5512 {
5513 i.op[op].imms->X_add_number =
5514 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
5515 }
5516 #ifdef BFD64
5517 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5518 if ((i.types[op].bitfield.imm32)
5519 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
5520 == 0))
5521 {
5522 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
5523 ^ ((offsetT) 1 << 31))
5524 - ((offsetT) 1 << 31));
5525 }
5526 #endif
5527 i.types[op]
5528 = operand_type_or (i.types[op],
5529 smallest_imm_type (i.op[op].imms->X_add_number));
5530
5531 /* We must avoid matching of Imm32 templates when 64bit
5532 only immediate is available. */
5533 if (guess_suffix == QWORD_MNEM_SUFFIX)
5534 i.types[op].bitfield.imm32 = 0;
5535 break;
5536
5537 case O_absent:
5538 case O_register:
5539 abort ();
5540
5541 /* Symbols and expressions. */
5542 default:
5543 /* Convert symbolic operand to proper sizes for matching, but don't
5544 prevent matching a set of insns that only supports sizes other
5545 than those matching the insn suffix. */
5546 {
5547 i386_operand_type mask, allowed;
5548 const insn_template *t;
5549
5550 operand_type_set (&mask, 0);
5551 operand_type_set (&allowed, 0);
5552
5553 for (t = current_templates->start;
5554 t < current_templates->end;
5555 ++t)
5556 {
5557 allowed = operand_type_or (allowed, t->operand_types[op]);
5558 allowed = operand_type_and (allowed, anyimm);
5559 }
5560 switch (guess_suffix)
5561 {
5562 case QWORD_MNEM_SUFFIX:
5563 mask.bitfield.imm64 = 1;
5564 mask.bitfield.imm32s = 1;
5565 break;
5566 case LONG_MNEM_SUFFIX:
5567 mask.bitfield.imm32 = 1;
5568 break;
5569 case WORD_MNEM_SUFFIX:
5570 mask.bitfield.imm16 = 1;
5571 break;
5572 case BYTE_MNEM_SUFFIX:
5573 mask.bitfield.imm8 = 1;
5574 break;
5575 default:
5576 break;
5577 }
5578 allowed = operand_type_and (mask, allowed);
5579 if (!operand_type_all_zero (&allowed))
5580 i.types[op] = operand_type_and (i.types[op], mask);
5581 }
5582 break;
5583 }
5584 }
5585 }
5586
5587 /* Try to use the smallest displacement type too. */
5588 static void
5589 optimize_disp (void)
5590 {
5591 int op;
5592
5593 for (op = i.operands; --op >= 0;)
5594 if (operand_type_check (i.types[op], disp))
5595 {
5596 if (i.op[op].disps->X_op == O_constant)
5597 {
5598 offsetT op_disp = i.op[op].disps->X_add_number;
5599
5600 if (i.types[op].bitfield.disp16
5601 && (op_disp & ~(offsetT) 0xffff) == 0)
5602 {
5603 /* If this operand is at most 16 bits, convert
5604 to a signed 16 bit number and don't use 64bit
5605 displacement. */
5606 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5607 i.types[op].bitfield.disp64 = 0;
5608 }
5609 #ifdef BFD64
5610 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5611 if (i.types[op].bitfield.disp32
5612 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5613 {
5614 /* If this operand is at most 32 bits, convert
5615 to a signed 32 bit number and don't use 64bit
5616 displacement. */
5617 op_disp &= (((offsetT) 2 << 31) - 1);
5618 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5619 i.types[op].bitfield.disp64 = 0;
5620 }
5621 #endif
5622 if (!op_disp && i.types[op].bitfield.baseindex)
5623 {
5624 i.types[op].bitfield.disp8 = 0;
5625 i.types[op].bitfield.disp16 = 0;
5626 i.types[op].bitfield.disp32 = 0;
5627 i.types[op].bitfield.disp32s = 0;
5628 i.types[op].bitfield.disp64 = 0;
5629 i.op[op].disps = 0;
5630 i.disp_operands--;
5631 }
5632 else if (flag_code == CODE_64BIT)
5633 {
5634 if (fits_in_signed_long (op_disp))
5635 {
5636 i.types[op].bitfield.disp64 = 0;
5637 i.types[op].bitfield.disp32s = 1;
5638 }
5639 if (i.prefix[ADDR_PREFIX]
5640 && fits_in_unsigned_long (op_disp))
5641 i.types[op].bitfield.disp32 = 1;
5642 }
5643 if ((i.types[op].bitfield.disp32
5644 || i.types[op].bitfield.disp32s
5645 || i.types[op].bitfield.disp16)
5646 && fits_in_disp8 (op_disp))
5647 i.types[op].bitfield.disp8 = 1;
5648 }
5649 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5650 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5651 {
5652 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5653 i.op[op].disps, 0, i.reloc[op]);
5654 i.types[op].bitfield.disp8 = 0;
5655 i.types[op].bitfield.disp16 = 0;
5656 i.types[op].bitfield.disp32 = 0;
5657 i.types[op].bitfield.disp32s = 0;
5658 i.types[op].bitfield.disp64 = 0;
5659 }
5660 else
5661 /* We only support 64bit displacement on constants. */
5662 i.types[op].bitfield.disp64 = 0;
5663 }
5664 }
5665
5666 /* Return 1 if there is a match in broadcast bytes between operand
5667 GIVEN and instruction template T. */
5668
5669 static INLINE int
5670 match_broadcast_size (const insn_template *t, unsigned int given)
5671 {
5672 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5673 && i.types[given].bitfield.byte)
5674 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5675 && i.types[given].bitfield.word)
5676 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5677 && i.types[given].bitfield.dword)
5678 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5679 && i.types[given].bitfield.qword));
5680 }
5681
5682 /* Check if operands are valid for the instruction. */
5683
5684 static int
5685 check_VecOperands (const insn_template *t)
5686 {
5687 unsigned int op;
5688 i386_cpu_flags cpu;
5689
5690 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5691 any one operand are implicity requiring AVX512VL support if the actual
5692 operand size is YMMword or XMMword. Since this function runs after
5693 template matching, there's no need to check for YMMword/XMMword in
5694 the template. */
5695 cpu = cpu_flags_and (t->cpu_flags, avx512);
5696 if (!cpu_flags_all_zero (&cpu)
5697 && !t->cpu_flags.bitfield.cpuavx512vl
5698 && !cpu_arch_flags.bitfield.cpuavx512vl)
5699 {
5700 for (op = 0; op < t->operands; ++op)
5701 {
5702 if (t->operand_types[op].bitfield.zmmword
5703 && (i.types[op].bitfield.ymmword
5704 || i.types[op].bitfield.xmmword))
5705 {
5706 i.error = unsupported;
5707 return 1;
5708 }
5709 }
5710 }
5711
5712 /* Without VSIB byte, we can't have a vector register for index. */
5713 if (!t->opcode_modifier.vecsib
5714 && i.index_reg
5715 && (i.index_reg->reg_type.bitfield.xmmword
5716 || i.index_reg->reg_type.bitfield.ymmword
5717 || i.index_reg->reg_type.bitfield.zmmword))
5718 {
5719 i.error = unsupported_vector_index_register;
5720 return 1;
5721 }
5722
5723 /* Check if default mask is allowed. */
5724 if (t->opcode_modifier.nodefmask
5725 && (!i.mask || i.mask->mask->reg_num == 0))
5726 {
5727 i.error = no_default_mask;
5728 return 1;
5729 }
5730
5731 /* For VSIB byte, we need a vector register for index, and all vector
5732 registers must be distinct. */
5733 if (t->opcode_modifier.vecsib)
5734 {
5735 if (!i.index_reg
5736 || !((t->opcode_modifier.vecsib == VecSIB128
5737 && i.index_reg->reg_type.bitfield.xmmword)
5738 || (t->opcode_modifier.vecsib == VecSIB256
5739 && i.index_reg->reg_type.bitfield.ymmword)
5740 || (t->opcode_modifier.vecsib == VecSIB512
5741 && i.index_reg->reg_type.bitfield.zmmword)))
5742 {
5743 i.error = invalid_vsib_address;
5744 return 1;
5745 }
5746
5747 gas_assert (i.reg_operands == 2 || i.mask);
5748 if (i.reg_operands == 2 && !i.mask)
5749 {
5750 gas_assert (i.types[0].bitfield.class == RegSIMD);
5751 gas_assert (i.types[0].bitfield.xmmword
5752 || i.types[0].bitfield.ymmword);
5753 gas_assert (i.types[2].bitfield.class == RegSIMD);
5754 gas_assert (i.types[2].bitfield.xmmword
5755 || i.types[2].bitfield.ymmword);
5756 if (operand_check == check_none)
5757 return 0;
5758 if (register_number (i.op[0].regs)
5759 != register_number (i.index_reg)
5760 && register_number (i.op[2].regs)
5761 != register_number (i.index_reg)
5762 && register_number (i.op[0].regs)
5763 != register_number (i.op[2].regs))
5764 return 0;
5765 if (operand_check == check_error)
5766 {
5767 i.error = invalid_vector_register_set;
5768 return 1;
5769 }
5770 as_warn (_("mask, index, and destination registers should be distinct"));
5771 }
5772 else if (i.reg_operands == 1 && i.mask)
5773 {
5774 if (i.types[1].bitfield.class == RegSIMD
5775 && (i.types[1].bitfield.xmmword
5776 || i.types[1].bitfield.ymmword
5777 || i.types[1].bitfield.zmmword)
5778 && (register_number (i.op[1].regs)
5779 == register_number (i.index_reg)))
5780 {
5781 if (operand_check == check_error)
5782 {
5783 i.error = invalid_vector_register_set;
5784 return 1;
5785 }
5786 if (operand_check != check_none)
5787 as_warn (_("index and destination registers should be distinct"));
5788 }
5789 }
5790 }
5791
5792 /* Check if broadcast is supported by the instruction and is applied
5793 to the memory operand. */
5794 if (i.broadcast)
5795 {
5796 i386_operand_type type, overlap;
5797
5798 /* Check if specified broadcast is supported in this instruction,
5799 and its broadcast bytes match the memory operand. */
5800 op = i.broadcast->operand;
5801 if (!t->opcode_modifier.broadcast
5802 || !(i.flags[op] & Operand_Mem)
5803 || (!i.types[op].bitfield.unspecified
5804 && !match_broadcast_size (t, op)))
5805 {
5806 bad_broadcast:
5807 i.error = unsupported_broadcast;
5808 return 1;
5809 }
5810
5811 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5812 * i.broadcast->type);
5813 operand_type_set (&type, 0);
5814 switch (i.broadcast->bytes)
5815 {
5816 case 2:
5817 type.bitfield.word = 1;
5818 break;
5819 case 4:
5820 type.bitfield.dword = 1;
5821 break;
5822 case 8:
5823 type.bitfield.qword = 1;
5824 break;
5825 case 16:
5826 type.bitfield.xmmword = 1;
5827 break;
5828 case 32:
5829 type.bitfield.ymmword = 1;
5830 break;
5831 case 64:
5832 type.bitfield.zmmword = 1;
5833 break;
5834 default:
5835 goto bad_broadcast;
5836 }
5837
5838 overlap = operand_type_and (type, t->operand_types[op]);
5839 if (t->operand_types[op].bitfield.class == RegSIMD
5840 && t->operand_types[op].bitfield.byte
5841 + t->operand_types[op].bitfield.word
5842 + t->operand_types[op].bitfield.dword
5843 + t->operand_types[op].bitfield.qword > 1)
5844 {
5845 overlap.bitfield.xmmword = 0;
5846 overlap.bitfield.ymmword = 0;
5847 overlap.bitfield.zmmword = 0;
5848 }
5849 if (operand_type_all_zero (&overlap))
5850 goto bad_broadcast;
5851
5852 if (t->opcode_modifier.checkregsize)
5853 {
5854 unsigned int j;
5855
5856 type.bitfield.baseindex = 1;
5857 for (j = 0; j < i.operands; ++j)
5858 {
5859 if (j != op
5860 && !operand_type_register_match(i.types[j],
5861 t->operand_types[j],
5862 type,
5863 t->operand_types[op]))
5864 goto bad_broadcast;
5865 }
5866 }
5867 }
5868 /* If broadcast is supported in this instruction, we need to check if
5869 operand of one-element size isn't specified without broadcast. */
5870 else if (t->opcode_modifier.broadcast && i.mem_operands)
5871 {
5872 /* Find memory operand. */
5873 for (op = 0; op < i.operands; op++)
5874 if (i.flags[op] & Operand_Mem)
5875 break;
5876 gas_assert (op < i.operands);
5877 /* Check size of the memory operand. */
5878 if (match_broadcast_size (t, op))
5879 {
5880 i.error = broadcast_needed;
5881 return 1;
5882 }
5883 }
5884 else
5885 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5886
5887 /* Check if requested masking is supported. */
5888 if (i.mask)
5889 {
5890 switch (t->opcode_modifier.masking)
5891 {
5892 case BOTH_MASKING:
5893 break;
5894 case MERGING_MASKING:
5895 if (i.mask->zeroing)
5896 {
5897 case 0:
5898 i.error = unsupported_masking;
5899 return 1;
5900 }
5901 break;
5902 case DYNAMIC_MASKING:
5903 /* Memory destinations allow only merging masking. */
5904 if (i.mask->zeroing && i.mem_operands)
5905 {
5906 /* Find memory operand. */
5907 for (op = 0; op < i.operands; op++)
5908 if (i.flags[op] & Operand_Mem)
5909 break;
5910 gas_assert (op < i.operands);
5911 if (op == i.operands - 1)
5912 {
5913 i.error = unsupported_masking;
5914 return 1;
5915 }
5916 }
5917 break;
5918 default:
5919 abort ();
5920 }
5921 }
5922
5923 /* Check if masking is applied to dest operand. */
5924 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5925 {
5926 i.error = mask_not_on_destination;
5927 return 1;
5928 }
5929
5930 /* Check RC/SAE. */
5931 if (i.rounding)
5932 {
5933 if (!t->opcode_modifier.sae
5934 || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding))
5935 {
5936 i.error = unsupported_rc_sae;
5937 return 1;
5938 }
5939 /* If the instruction has several immediate operands and one of
5940 them is rounding, the rounding operand should be the last
5941 immediate operand. */
5942 if (i.imm_operands > 1
5943 && i.rounding->operand != (int) (i.imm_operands - 1))
5944 {
5945 i.error = rc_sae_operand_not_last_imm;
5946 return 1;
5947 }
5948 }
5949
5950 /* Check vector Disp8 operand. */
5951 if (t->opcode_modifier.disp8memshift
5952 && i.disp_encoding != disp_encoding_32bit)
5953 {
5954 if (i.broadcast)
5955 i.memshift = t->opcode_modifier.broadcast - 1;
5956 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5957 i.memshift = t->opcode_modifier.disp8memshift;
5958 else
5959 {
5960 const i386_operand_type *type = NULL;
5961
5962 i.memshift = 0;
5963 for (op = 0; op < i.operands; op++)
5964 if (i.flags[op] & Operand_Mem)
5965 {
5966 if (t->opcode_modifier.evex == EVEXLIG)
5967 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5968 else if (t->operand_types[op].bitfield.xmmword
5969 + t->operand_types[op].bitfield.ymmword
5970 + t->operand_types[op].bitfield.zmmword <= 1)
5971 type = &t->operand_types[op];
5972 else if (!i.types[op].bitfield.unspecified)
5973 type = &i.types[op];
5974 }
5975 else if (i.types[op].bitfield.class == RegSIMD
5976 && t->opcode_modifier.evex != EVEXLIG)
5977 {
5978 if (i.types[op].bitfield.zmmword)
5979 i.memshift = 6;
5980 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5981 i.memshift = 5;
5982 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5983 i.memshift = 4;
5984 }
5985
5986 if (type)
5987 {
5988 if (type->bitfield.zmmword)
5989 i.memshift = 6;
5990 else if (type->bitfield.ymmword)
5991 i.memshift = 5;
5992 else if (type->bitfield.xmmword)
5993 i.memshift = 4;
5994 }
5995
5996 /* For the check in fits_in_disp8(). */
5997 if (i.memshift == 0)
5998 i.memshift = -1;
5999 }
6000
6001 for (op = 0; op < i.operands; op++)
6002 if (operand_type_check (i.types[op], disp)
6003 && i.op[op].disps->X_op == O_constant)
6004 {
6005 if (fits_in_disp8 (i.op[op].disps->X_add_number))
6006 {
6007 i.types[op].bitfield.disp8 = 1;
6008 return 0;
6009 }
6010 i.types[op].bitfield.disp8 = 0;
6011 }
6012 }
6013
6014 i.memshift = 0;
6015
6016 return 0;
6017 }
6018
6019 /* Check if operands are valid for the instruction. Update VEX
6020 operand types. */
6021
6022 static int
6023 VEX_check_operands (const insn_template *t)
6024 {
6025 if (i.vec_encoding == vex_encoding_evex)
6026 {
6027 /* This instruction must be encoded with EVEX prefix. */
6028 if (!is_evex_encoding (t))
6029 {
6030 i.error = unsupported;
6031 return 1;
6032 }
6033 return 0;
6034 }
6035
6036 if (!t->opcode_modifier.vex)
6037 {
6038 /* This instruction template doesn't have VEX prefix. */
6039 if (i.vec_encoding != vex_encoding_default)
6040 {
6041 i.error = unsupported;
6042 return 1;
6043 }
6044 return 0;
6045 }
6046
6047 /* Check the special Imm4 cases; must be the first operand. */
6048 if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
6049 {
6050 if (i.op[0].imms->X_op != O_constant
6051 || !fits_in_imm4 (i.op[0].imms->X_add_number))
6052 {
6053 i.error = bad_imm4;
6054 return 1;
6055 }
6056
6057 /* Turn off Imm<N> so that update_imm won't complain. */
6058 operand_type_set (&i.types[0], 0);
6059 }
6060
6061 return 0;
6062 }
6063
6064 static const insn_template *
6065 match_template (char mnem_suffix)
6066 {
6067 /* Points to template once we've found it. */
6068 const insn_template *t;
6069 i386_operand_type overlap0, overlap1, overlap2, overlap3;
6070 i386_operand_type overlap4;
6071 unsigned int found_reverse_match;
6072 i386_opcode_modifier suffix_check;
6073 i386_operand_type operand_types [MAX_OPERANDS];
6074 int addr_prefix_disp;
6075 unsigned int j, size_match, check_register;
6076 enum i386_error specific_error = 0;
6077
6078 #if MAX_OPERANDS != 5
6079 # error "MAX_OPERANDS must be 5."
6080 #endif
6081
6082 found_reverse_match = 0;
6083 addr_prefix_disp = -1;
6084
6085 /* Prepare for mnemonic suffix check. */
6086 memset (&suffix_check, 0, sizeof (suffix_check));
6087 switch (mnem_suffix)
6088 {
6089 case BYTE_MNEM_SUFFIX:
6090 suffix_check.no_bsuf = 1;
6091 break;
6092 case WORD_MNEM_SUFFIX:
6093 suffix_check.no_wsuf = 1;
6094 break;
6095 case SHORT_MNEM_SUFFIX:
6096 suffix_check.no_ssuf = 1;
6097 break;
6098 case LONG_MNEM_SUFFIX:
6099 suffix_check.no_lsuf = 1;
6100 break;
6101 case QWORD_MNEM_SUFFIX:
6102 suffix_check.no_qsuf = 1;
6103 break;
6104 default:
6105 /* NB: In Intel syntax, normally we can check for memory operand
6106 size when there is no mnemonic suffix. But jmp and call have
6107 2 different encodings with Dword memory operand size, one with
6108 No_ldSuf and the other without. i.suffix is set to
6109 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6110 if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
6111 suffix_check.no_ldsuf = 1;
6112 }
6113
6114 /* Must have right number of operands. */
6115 i.error = number_of_operands_mismatch;
6116
6117 for (t = current_templates->start; t < current_templates->end; t++)
6118 {
6119 addr_prefix_disp = -1;
6120 found_reverse_match = 0;
6121
6122 if (i.operands != t->operands)
6123 continue;
6124
6125 /* Check processor support. */
6126 i.error = unsupported;
6127 if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
6128 continue;
6129
6130 /* Check AT&T mnemonic. */
6131 i.error = unsupported_with_intel_mnemonic;
6132 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
6133 continue;
6134
6135 /* Check AT&T/Intel syntax. */
6136 i.error = unsupported_syntax;
6137 if ((intel_syntax && t->opcode_modifier.attsyntax)
6138 || (!intel_syntax && t->opcode_modifier.intelsyntax))
6139 continue;
6140
6141 /* Check Intel64/AMD64 ISA. */
6142 switch (isa64)
6143 {
6144 default:
6145 /* Default: Don't accept Intel64. */
6146 if (t->opcode_modifier.isa64 == INTEL64)
6147 continue;
6148 break;
6149 case amd64:
6150 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6151 if (t->opcode_modifier.isa64 >= INTEL64)
6152 continue;
6153 break;
6154 case intel64:
6155 /* -mintel64: Don't accept AMD64. */
6156 if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT)
6157 continue;
6158 break;
6159 }
6160
6161 /* Check the suffix. */
6162 i.error = invalid_instruction_suffix;
6163 if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
6164 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
6165 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
6166 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
6167 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
6168 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))
6169 continue;
6170
6171 size_match = operand_size_match (t);
6172 if (!size_match)
6173 continue;
6174
6175 /* This is intentionally not
6176
6177 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6178
6179 as the case of a missing * on the operand is accepted (perhaps with
6180 a warning, issued further down). */
6181 if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE)
6182 {
6183 i.error = operand_type_mismatch;
6184 continue;
6185 }
6186
6187 for (j = 0; j < MAX_OPERANDS; j++)
6188 operand_types[j] = t->operand_types[j];
6189
6190 /* In general, don't allow
6191 - 64-bit operands outside of 64-bit mode,
6192 - 32-bit operands on pre-386. */
6193 j = i.imm_operands + (t->operands > i.imm_operands + 1);
6194 if (((i.suffix == QWORD_MNEM_SUFFIX
6195 && flag_code != CODE_64BIT
6196 && (t->base_opcode != 0x0fc7
6197 || t->extension_opcode != 1 /* cmpxchg8b */))
6198 || (i.suffix == LONG_MNEM_SUFFIX
6199 && !cpu_arch_flags.bitfield.cpui386))
6200 && (intel_syntax
6201 ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
6202 && !intel_float_operand (t->name))
6203 : intel_float_operand (t->name) != 2)
6204 && (t->operands == i.imm_operands
6205 || (operand_types[i.imm_operands].bitfield.class != RegMMX
6206 && operand_types[i.imm_operands].bitfield.class != RegSIMD
6207 && operand_types[i.imm_operands].bitfield.class != RegMask)
6208 || (operand_types[j].bitfield.class != RegMMX
6209 && operand_types[j].bitfield.class != RegSIMD
6210 && operand_types[j].bitfield.class != RegMask))
6211 && !t->opcode_modifier.vecsib)
6212 continue;
6213
6214 /* Do not verify operands when there are none. */
6215 if (!t->operands)
6216 /* We've found a match; break out of loop. */
6217 break;
6218
6219 if (!t->opcode_modifier.jump
6220 || t->opcode_modifier.jump == JUMP_ABSOLUTE)
6221 {
6222 /* There should be only one Disp operand. */
6223 for (j = 0; j < MAX_OPERANDS; j++)
6224 if (operand_type_check (operand_types[j], disp))
6225 break;
6226 if (j < MAX_OPERANDS)
6227 {
6228 bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0);
6229
6230 addr_prefix_disp = j;
6231
6232 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6233 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6234 switch (flag_code)
6235 {
6236 case CODE_16BIT:
6237 override = !override;
6238 /* Fall through. */
6239 case CODE_32BIT:
6240 if (operand_types[j].bitfield.disp32
6241 && operand_types[j].bitfield.disp16)
6242 {
6243 operand_types[j].bitfield.disp16 = override;
6244 operand_types[j].bitfield.disp32 = !override;
6245 }
6246 operand_types[j].bitfield.disp32s = 0;
6247 operand_types[j].bitfield.disp64 = 0;
6248 break;
6249
6250 case CODE_64BIT:
6251 if (operand_types[j].bitfield.disp32s
6252 || operand_types[j].bitfield.disp64)
6253 {
6254 operand_types[j].bitfield.disp64 &= !override;
6255 operand_types[j].bitfield.disp32s &= !override;
6256 operand_types[j].bitfield.disp32 = override;
6257 }
6258 operand_types[j].bitfield.disp16 = 0;
6259 break;
6260 }
6261 }
6262 }
6263
6264 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6265 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
6266 continue;
6267
6268 /* We check register size if needed. */
6269 if (t->opcode_modifier.checkregsize)
6270 {
6271 check_register = (1 << t->operands) - 1;
6272 if (i.broadcast)
6273 check_register &= ~(1 << i.broadcast->operand);
6274 }
6275 else
6276 check_register = 0;
6277
6278 overlap0 = operand_type_and (i.types[0], operand_types[0]);
6279 switch (t->operands)
6280 {
6281 case 1:
6282 if (!operand_type_match (overlap0, i.types[0]))
6283 continue;
6284 break;
6285 case 2:
6286 /* xchg %eax, %eax is a special case. It is an alias for nop
6287 only in 32bit mode and we can use opcode 0x90. In 64bit
6288 mode, we can't use 0x90 for xchg %eax, %eax since it should
6289 zero-extend %eax to %rax. */
6290 if (flag_code == CODE_64BIT
6291 && t->base_opcode == 0x90
6292 && i.types[0].bitfield.instance == Accum
6293 && i.types[0].bitfield.dword
6294 && i.types[1].bitfield.instance == Accum
6295 && i.types[1].bitfield.dword)
6296 continue;
6297 /* xrelease mov %eax, <disp> is another special case. It must not
6298 match the accumulator-only encoding of mov. */
6299 if (flag_code != CODE_64BIT
6300 && i.hle_prefix
6301 && t->base_opcode == 0xa0
6302 && i.types[0].bitfield.instance == Accum
6303 && (i.flags[1] & Operand_Mem))
6304 continue;
6305 /* Fall through. */
6306
6307 case 3:
6308 if (!(size_match & MATCH_STRAIGHT))
6309 goto check_reverse;
6310 /* Reverse direction of operands if swapping is possible in the first
6311 place (operands need to be symmetric) and
6312 - the load form is requested, and the template is a store form,
6313 - the store form is requested, and the template is a load form,
6314 - the non-default (swapped) form is requested. */
6315 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
6316 if (t->opcode_modifier.d && i.reg_operands == i.operands
6317 && !operand_type_all_zero (&overlap1))
6318 switch (i.dir_encoding)
6319 {
6320 case dir_encoding_load:
6321 if (operand_type_check (operand_types[i.operands - 1], anymem)
6322 || t->opcode_modifier.regmem)
6323 goto check_reverse;
6324 break;
6325
6326 case dir_encoding_store:
6327 if (!operand_type_check (operand_types[i.operands - 1], anymem)
6328 && !t->opcode_modifier.regmem)
6329 goto check_reverse;
6330 break;
6331
6332 case dir_encoding_swap:
6333 goto check_reverse;
6334
6335 case dir_encoding_default:
6336 break;
6337 }
6338 /* If we want store form, we skip the current load. */
6339 if ((i.dir_encoding == dir_encoding_store
6340 || i.dir_encoding == dir_encoding_swap)
6341 && i.mem_operands == 0
6342 && t->opcode_modifier.load)
6343 continue;
6344 /* Fall through. */
6345 case 4:
6346 case 5:
6347 overlap1 = operand_type_and (i.types[1], operand_types[1]);
6348 if (!operand_type_match (overlap0, i.types[0])
6349 || !operand_type_match (overlap1, i.types[1])
6350 || ((check_register & 3) == 3
6351 && !operand_type_register_match (i.types[0],
6352 operand_types[0],
6353 i.types[1],
6354 operand_types[1])))
6355 {
6356 /* Check if other direction is valid ... */
6357 if (!t->opcode_modifier.d)
6358 continue;
6359
6360 check_reverse:
6361 if (!(size_match & MATCH_REVERSE))
6362 continue;
6363 /* Try reversing direction of operands. */
6364 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
6365 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
6366 if (!operand_type_match (overlap0, i.types[0])
6367 || !operand_type_match (overlap1, i.types[i.operands - 1])
6368 || (check_register
6369 && !operand_type_register_match (i.types[0],
6370 operand_types[i.operands - 1],
6371 i.types[i.operands - 1],
6372 operand_types[0])))
6373 {
6374 /* Does not match either direction. */
6375 continue;
6376 }
6377 /* found_reverse_match holds which of D or FloatR
6378 we've found. */
6379 if (!t->opcode_modifier.d)
6380 found_reverse_match = 0;
6381 else if (operand_types[0].bitfield.tbyte)
6382 found_reverse_match = Opcode_FloatD;
6383 else if (operand_types[0].bitfield.xmmword
6384 || operand_types[i.operands - 1].bitfield.xmmword
6385 || operand_types[0].bitfield.class == RegMMX
6386 || operand_types[i.operands - 1].bitfield.class == RegMMX
6387 || is_any_vex_encoding(t))
6388 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
6389 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
6390 else
6391 found_reverse_match = Opcode_D;
6392 if (t->opcode_modifier.floatr)
6393 found_reverse_match |= Opcode_FloatR;
6394 }
6395 else
6396 {
6397 /* Found a forward 2 operand match here. */
6398 switch (t->operands)
6399 {
6400 case 5:
6401 overlap4 = operand_type_and (i.types[4],
6402 operand_types[4]);
6403 /* Fall through. */
6404 case 4:
6405 overlap3 = operand_type_and (i.types[3],
6406 operand_types[3]);
6407 /* Fall through. */
6408 case 3:
6409 overlap2 = operand_type_and (i.types[2],
6410 operand_types[2]);
6411 break;
6412 }
6413
6414 switch (t->operands)
6415 {
6416 case 5:
6417 if (!operand_type_match (overlap4, i.types[4])
6418 || !operand_type_register_match (i.types[3],
6419 operand_types[3],
6420 i.types[4],
6421 operand_types[4]))
6422 continue;
6423 /* Fall through. */
6424 case 4:
6425 if (!operand_type_match (overlap3, i.types[3])
6426 || ((check_register & 0xa) == 0xa
6427 && !operand_type_register_match (i.types[1],
6428 operand_types[1],
6429 i.types[3],
6430 operand_types[3]))
6431 || ((check_register & 0xc) == 0xc
6432 && !operand_type_register_match (i.types[2],
6433 operand_types[2],
6434 i.types[3],
6435 operand_types[3])))
6436 continue;
6437 /* Fall through. */
6438 case 3:
6439 /* Here we make use of the fact that there are no
6440 reverse match 3 operand instructions. */
6441 if (!operand_type_match (overlap2, i.types[2])
6442 || ((check_register & 5) == 5
6443 && !operand_type_register_match (i.types[0],
6444 operand_types[0],
6445 i.types[2],
6446 operand_types[2]))
6447 || ((check_register & 6) == 6
6448 && !operand_type_register_match (i.types[1],
6449 operand_types[1],
6450 i.types[2],
6451 operand_types[2])))
6452 continue;
6453 break;
6454 }
6455 }
6456 /* Found either forward/reverse 2, 3 or 4 operand match here:
6457 slip through to break. */
6458 }
6459
6460 /* Check if vector and VEX operands are valid. */
6461 if (check_VecOperands (t) || VEX_check_operands (t))
6462 {
6463 specific_error = i.error;
6464 continue;
6465 }
6466
6467 /* We've found a match; break out of loop. */
6468 break;
6469 }
6470
6471 if (t == current_templates->end)
6472 {
6473 /* We found no match. */
6474 const char *err_msg;
6475 switch (specific_error ? specific_error : i.error)
6476 {
6477 default:
6478 abort ();
6479 case operand_size_mismatch:
6480 err_msg = _("operand size mismatch");
6481 break;
6482 case operand_type_mismatch:
6483 err_msg = _("operand type mismatch");
6484 break;
6485 case register_type_mismatch:
6486 err_msg = _("register type mismatch");
6487 break;
6488 case number_of_operands_mismatch:
6489 err_msg = _("number of operands mismatch");
6490 break;
6491 case invalid_instruction_suffix:
6492 err_msg = _("invalid instruction suffix");
6493 break;
6494 case bad_imm4:
6495 err_msg = _("constant doesn't fit in 4 bits");
6496 break;
6497 case unsupported_with_intel_mnemonic:
6498 err_msg = _("unsupported with Intel mnemonic");
6499 break;
6500 case unsupported_syntax:
6501 err_msg = _("unsupported syntax");
6502 break;
6503 case unsupported:
6504 as_bad (_("unsupported instruction `%s'"),
6505 current_templates->start->name);
6506 return NULL;
6507 case invalid_vsib_address:
6508 err_msg = _("invalid VSIB address");
6509 break;
6510 case invalid_vector_register_set:
6511 err_msg = _("mask, index, and destination registers must be distinct");
6512 break;
6513 case unsupported_vector_index_register:
6514 err_msg = _("unsupported vector index register");
6515 break;
6516 case unsupported_broadcast:
6517 err_msg = _("unsupported broadcast");
6518 break;
6519 case broadcast_needed:
6520 err_msg = _("broadcast is needed for operand of such type");
6521 break;
6522 case unsupported_masking:
6523 err_msg = _("unsupported masking");
6524 break;
6525 case mask_not_on_destination:
6526 err_msg = _("mask not on destination operand");
6527 break;
6528 case no_default_mask:
6529 err_msg = _("default mask isn't allowed");
6530 break;
6531 case unsupported_rc_sae:
6532 err_msg = _("unsupported static rounding/sae");
6533 break;
6534 case rc_sae_operand_not_last_imm:
6535 if (intel_syntax)
6536 err_msg = _("RC/SAE operand must precede immediate operands");
6537 else
6538 err_msg = _("RC/SAE operand must follow immediate operands");
6539 break;
6540 case invalid_register_operand:
6541 err_msg = _("invalid register operand");
6542 break;
6543 }
6544 as_bad (_("%s for `%s'"), err_msg,
6545 current_templates->start->name);
6546 return NULL;
6547 }
6548
6549 if (!quiet_warnings)
6550 {
6551 if (!intel_syntax
6552 && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)))
6553 as_warn (_("indirect %s without `*'"), t->name);
6554
6555 if (t->opcode_modifier.isprefix
6556 && t->opcode_modifier.mnemonicsize == IGNORESIZE)
6557 {
6558 /* Warn them that a data or address size prefix doesn't
6559 affect assembly of the next line of code. */
6560 as_warn (_("stand-alone `%s' prefix"), t->name);
6561 }
6562 }
6563
6564 /* Copy the template we found. */
6565 i.tm = *t;
6566
6567 if (addr_prefix_disp != -1)
6568 i.tm.operand_types[addr_prefix_disp]
6569 = operand_types[addr_prefix_disp];
6570
6571 if (found_reverse_match)
6572 {
6573 /* If we found a reverse match we must alter the opcode direction
6574 bit and clear/flip the regmem modifier one. found_reverse_match
6575 holds bits to change (different for int & float insns). */
6576
6577 i.tm.base_opcode ^= found_reverse_match;
6578
6579 i.tm.operand_types[0] = operand_types[i.operands - 1];
6580 i.tm.operand_types[i.operands - 1] = operand_types[0];
6581
6582 /* Certain SIMD insns have their load forms specified in the opcode
6583 table, and hence we need to _set_ RegMem instead of clearing it.
6584 We need to avoid setting the bit though on insns like KMOVW. */
6585 i.tm.opcode_modifier.regmem
6586 = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
6587 && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
6588 && !i.tm.opcode_modifier.regmem;
6589 }
6590
6591 return t;
6592 }
6593
6594 static int
6595 check_string (void)
6596 {
6597 unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0;
6598 unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0;
6599
6600 if (i.seg[op] != NULL && i.seg[op] != &es)
6601 {
6602 as_bad (_("`%s' operand %u must use `%ses' segment"),
6603 i.tm.name,
6604 intel_syntax ? i.tm.operands - es_op : es_op + 1,
6605 register_prefix);
6606 return 0;
6607 }
6608
6609 /* There's only ever one segment override allowed per instruction.
6610 This instruction possibly has a legal segment override on the
6611 second operand, so copy the segment to where non-string
6612 instructions store it, allowing common code. */
6613 i.seg[op] = i.seg[1];
6614
6615 return 1;
6616 }
6617
6618 static int
6619 process_suffix (void)
6620 {
6621 /* If matched instruction specifies an explicit instruction mnemonic
6622 suffix, use it. */
6623 if (i.tm.opcode_modifier.size == SIZE16)
6624 i.suffix = WORD_MNEM_SUFFIX;
6625 else if (i.tm.opcode_modifier.size == SIZE32)
6626 i.suffix = LONG_MNEM_SUFFIX;
6627 else if (i.tm.opcode_modifier.size == SIZE64)
6628 i.suffix = QWORD_MNEM_SUFFIX;
6629 else if (i.reg_operands
6630 && (i.operands > 1 || i.types[0].bitfield.class == Reg)
6631 && !i.tm.opcode_modifier.addrprefixopreg)
6632 {
6633 unsigned int numop = i.operands;
6634
6635 /* movsx/movzx want only their source operand considered here, for the
6636 ambiguity checking below. The suffix will be replaced afterwards
6637 to represent the destination (register). */
6638 if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w)
6639 || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
6640 --i.operands;
6641
6642 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6643 if (i.tm.base_opcode == 0xf20f38f0
6644 && i.tm.operand_types[1].bitfield.qword)
6645 i.rex |= REX_W;
6646
6647 /* If there's no instruction mnemonic suffix we try to invent one
6648 based on GPR operands. */
6649 if (!i.suffix)
6650 {
6651 /* We take i.suffix from the last register operand specified,
6652 Destination register type is more significant than source
6653 register type. crc32 in SSE4.2 prefers source register
6654 type. */
6655 unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
6656
6657 while (op--)
6658 if (i.tm.operand_types[op].bitfield.instance == InstanceNone
6659 || i.tm.operand_types[op].bitfield.instance == Accum)
6660 {
6661 if (i.types[op].bitfield.class != Reg)
6662 continue;
6663 if (i.types[op].bitfield.byte)
6664 i.suffix = BYTE_MNEM_SUFFIX;
6665 else if (i.types[op].bitfield.word)
6666 i.suffix = WORD_MNEM_SUFFIX;
6667 else if (i.types[op].bitfield.dword)
6668 i.suffix = LONG_MNEM_SUFFIX;
6669 else if (i.types[op].bitfield.qword)
6670 i.suffix = QWORD_MNEM_SUFFIX;
6671 else
6672 continue;
6673 break;
6674 }
6675
6676 /* As an exception, movsx/movzx silently default to a byte source
6677 in AT&T mode. */
6678 if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w
6679 && !i.suffix && !intel_syntax)
6680 i.suffix = BYTE_MNEM_SUFFIX;
6681 }
6682 else if (i.suffix == BYTE_MNEM_SUFFIX)
6683 {
6684 if (intel_syntax
6685 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6686 && i.tm.opcode_modifier.no_bsuf)
6687 i.suffix = 0;
6688 else if (!check_byte_reg ())
6689 return 0;
6690 }
6691 else if (i.suffix == LONG_MNEM_SUFFIX)
6692 {
6693 if (intel_syntax
6694 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6695 && i.tm.opcode_modifier.no_lsuf
6696 && !i.tm.opcode_modifier.todword
6697 && !i.tm.opcode_modifier.toqword)
6698 i.suffix = 0;
6699 else if (!check_long_reg ())
6700 return 0;
6701 }
6702 else if (i.suffix == QWORD_MNEM_SUFFIX)
6703 {
6704 if (intel_syntax
6705 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6706 && i.tm.opcode_modifier.no_qsuf
6707 && !i.tm.opcode_modifier.todword
6708 && !i.tm.opcode_modifier.toqword)
6709 i.suffix = 0;
6710 else if (!check_qword_reg ())
6711 return 0;
6712 }
6713 else if (i.suffix == WORD_MNEM_SUFFIX)
6714 {
6715 if (intel_syntax
6716 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6717 && i.tm.opcode_modifier.no_wsuf)
6718 i.suffix = 0;
6719 else if (!check_word_reg ())
6720 return 0;
6721 }
6722 else if (intel_syntax
6723 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
6724 /* Do nothing if the instruction is going to ignore the prefix. */
6725 ;
6726 else
6727 abort ();
6728
6729 /* Undo the movsx/movzx change done above. */
6730 i.operands = numop;
6731 }
6732 else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE
6733 && !i.suffix)
6734 {
6735 i.suffix = stackop_size;
6736 if (stackop_size == LONG_MNEM_SUFFIX)
6737 {
6738 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6739 .code16gcc directive to support 16-bit mode with
6740 32-bit address. For IRET without a suffix, generate
6741 16-bit IRET (opcode 0xcf) to return from an interrupt
6742 handler. */
6743 if (i.tm.base_opcode == 0xcf)
6744 {
6745 i.suffix = WORD_MNEM_SUFFIX;
6746 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6747 }
6748 /* Warn about changed behavior for segment register push/pop. */
6749 else if ((i.tm.base_opcode | 1) == 0x07)
6750 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6751 i.tm.name);
6752 }
6753 }
6754 else if (!i.suffix
6755 && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
6756 || i.tm.opcode_modifier.jump == JUMP_BYTE
6757 || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
6758 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6759 && i.tm.extension_opcode <= 3)))
6760 {
6761 switch (flag_code)
6762 {
6763 case CODE_64BIT:
6764 if (!i.tm.opcode_modifier.no_qsuf)
6765 {
6766 i.suffix = QWORD_MNEM_SUFFIX;
6767 break;
6768 }
6769 /* Fall through. */
6770 case CODE_32BIT:
6771 if (!i.tm.opcode_modifier.no_lsuf)
6772 i.suffix = LONG_MNEM_SUFFIX;
6773 break;
6774 case CODE_16BIT:
6775 if (!i.tm.opcode_modifier.no_wsuf)
6776 i.suffix = WORD_MNEM_SUFFIX;
6777 break;
6778 }
6779 }
6780
6781 if (!i.suffix
6782 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
6783 /* Also cover lret/retf/iret in 64-bit mode. */
6784 || (flag_code == CODE_64BIT
6785 && !i.tm.opcode_modifier.no_lsuf
6786 && !i.tm.opcode_modifier.no_qsuf))
6787 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
6788 /* Accept FLDENV et al without suffix. */
6789 && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
6790 {
6791 unsigned int suffixes, evex = 0;
6792
6793 suffixes = !i.tm.opcode_modifier.no_bsuf;
6794 if (!i.tm.opcode_modifier.no_wsuf)
6795 suffixes |= 1 << 1;
6796 if (!i.tm.opcode_modifier.no_lsuf)
6797 suffixes |= 1 << 2;
6798 if (!i.tm.opcode_modifier.no_ldsuf)
6799 suffixes |= 1 << 3;
6800 if (!i.tm.opcode_modifier.no_ssuf)
6801 suffixes |= 1 << 4;
6802 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6803 suffixes |= 1 << 5;
6804
6805 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6806 also suitable for AT&T syntax mode, it was requested that this be
6807 restricted to just Intel syntax. */
6808 if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast)
6809 {
6810 unsigned int op;
6811
6812 for (op = 0; op < i.tm.operands; ++op)
6813 {
6814 if (is_evex_encoding (&i.tm)
6815 && !cpu_arch_flags.bitfield.cpuavx512vl)
6816 {
6817 if (i.tm.operand_types[op].bitfield.ymmword)
6818 i.tm.operand_types[op].bitfield.xmmword = 0;
6819 if (i.tm.operand_types[op].bitfield.zmmword)
6820 i.tm.operand_types[op].bitfield.ymmword = 0;
6821 if (!i.tm.opcode_modifier.evex
6822 || i.tm.opcode_modifier.evex == EVEXDYN)
6823 i.tm.opcode_modifier.evex = EVEX512;
6824 }
6825
6826 if (i.tm.operand_types[op].bitfield.xmmword
6827 + i.tm.operand_types[op].bitfield.ymmword
6828 + i.tm.operand_types[op].bitfield.zmmword < 2)
6829 continue;
6830
6831 /* Any properly sized operand disambiguates the insn. */
6832 if (i.types[op].bitfield.xmmword
6833 || i.types[op].bitfield.ymmword
6834 || i.types[op].bitfield.zmmword)
6835 {
6836 suffixes &= ~(7 << 6);
6837 evex = 0;
6838 break;
6839 }
6840
6841 if ((i.flags[op] & Operand_Mem)
6842 && i.tm.operand_types[op].bitfield.unspecified)
6843 {
6844 if (i.tm.operand_types[op].bitfield.xmmword)
6845 suffixes |= 1 << 6;
6846 if (i.tm.operand_types[op].bitfield.ymmword)
6847 suffixes |= 1 << 7;
6848 if (i.tm.operand_types[op].bitfield.zmmword)
6849 suffixes |= 1 << 8;
6850 if (is_evex_encoding (&i.tm))
6851 evex = EVEX512;
6852 }
6853 }
6854 }
6855
6856 /* Are multiple suffixes / operand sizes allowed? */
6857 if (suffixes & (suffixes - 1))
6858 {
6859 if (intel_syntax
6860 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
6861 || operand_check == check_error))
6862 {
6863 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6864 return 0;
6865 }
6866 if (operand_check == check_error)
6867 {
6868 as_bad (_("no instruction mnemonic suffix given and "
6869 "no register operands; can't size `%s'"), i.tm.name);
6870 return 0;
6871 }
6872 if (operand_check == check_warning)
6873 as_warn (_("%s; using default for `%s'"),
6874 intel_syntax
6875 ? _("ambiguous operand size")
6876 : _("no instruction mnemonic suffix given and "
6877 "no register operands"),
6878 i.tm.name);
6879
6880 if (i.tm.opcode_modifier.floatmf)
6881 i.suffix = SHORT_MNEM_SUFFIX;
6882 else if ((i.tm.base_opcode | 8) == 0xfbe
6883 || (i.tm.base_opcode == 0x63
6884 && i.tm.cpu_flags.bitfield.cpu64))
6885 /* handled below */;
6886 else if (evex)
6887 i.tm.opcode_modifier.evex = evex;
6888 else if (flag_code == CODE_16BIT)
6889 i.suffix = WORD_MNEM_SUFFIX;
6890 else if (!i.tm.opcode_modifier.no_lsuf)
6891 i.suffix = LONG_MNEM_SUFFIX;
6892 else
6893 i.suffix = QWORD_MNEM_SUFFIX;
6894 }
6895 }
6896
6897 if ((i.tm.base_opcode | 8) == 0xfbe
6898 || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
6899 {
6900 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6901 In AT&T syntax, if there is no suffix (warned about above), the default
6902 will be byte extension. */
6903 if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
6904 i.tm.base_opcode |= 1;
6905
6906 /* For further processing, the suffix should represent the destination
6907 (register). This is already the case when one was used with
6908 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6909 no suffix to begin with. */
6910 if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
6911 {
6912 if (i.types[1].bitfield.word)
6913 i.suffix = WORD_MNEM_SUFFIX;
6914 else if (i.types[1].bitfield.qword)
6915 i.suffix = QWORD_MNEM_SUFFIX;
6916 else
6917 i.suffix = LONG_MNEM_SUFFIX;
6918
6919 i.tm.opcode_modifier.w = 0;
6920 }
6921 }
6922
6923 if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3)
6924 i.short_form = (i.tm.operand_types[0].bitfield.class == Reg)
6925 != (i.tm.operand_types[1].bitfield.class == Reg);
6926
6927 /* Change the opcode based on the operand size given by i.suffix. */
6928 switch (i.suffix)
6929 {
6930 /* Size floating point instruction. */
6931 case LONG_MNEM_SUFFIX:
6932 if (i.tm.opcode_modifier.floatmf)
6933 {
6934 i.tm.base_opcode ^= 4;
6935 break;
6936 }
6937 /* fall through */
6938 case WORD_MNEM_SUFFIX:
6939 case QWORD_MNEM_SUFFIX:
6940 /* It's not a byte, select word/dword operation. */
6941 if (i.tm.opcode_modifier.w)
6942 {
6943 if (i.short_form)
6944 i.tm.base_opcode |= 8;
6945 else
6946 i.tm.base_opcode |= 1;
6947 }
6948 /* fall through */
6949 case SHORT_MNEM_SUFFIX:
6950 /* Now select between word & dword operations via the operand
6951 size prefix, except for instructions that will ignore this
6952 prefix anyway. */
6953 if (i.suffix != QWORD_MNEM_SUFFIX
6954 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
6955 && !i.tm.opcode_modifier.floatmf
6956 && !is_any_vex_encoding (&i.tm)
6957 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6958 || (flag_code == CODE_64BIT
6959 && i.tm.opcode_modifier.jump == JUMP_BYTE)))
6960 {
6961 unsigned int prefix = DATA_PREFIX_OPCODE;
6962
6963 if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */
6964 prefix = ADDR_PREFIX_OPCODE;
6965
6966 if (!add_prefix (prefix))
6967 return 0;
6968 }
6969
6970 /* Set mode64 for an operand. */
6971 if (i.suffix == QWORD_MNEM_SUFFIX
6972 && flag_code == CODE_64BIT
6973 && !i.tm.opcode_modifier.norex64
6974 && !i.tm.opcode_modifier.vexw
6975 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6976 need rex64. */
6977 && ! (i.operands == 2
6978 && i.tm.base_opcode == 0x90
6979 && i.tm.extension_opcode == None
6980 && i.types[0].bitfield.instance == Accum
6981 && i.types[0].bitfield.qword
6982 && i.types[1].bitfield.instance == Accum
6983 && i.types[1].bitfield.qword))
6984 i.rex |= REX_W;
6985
6986 break;
6987 }
6988
6989 if (i.tm.opcode_modifier.addrprefixopreg)
6990 {
6991 gas_assert (!i.suffix);
6992 gas_assert (i.reg_operands);
6993
6994 if (i.tm.operand_types[0].bitfield.instance == Accum
6995 || i.operands == 1)
6996 {
6997 /* The address size override prefix changes the size of the
6998 first operand. */
6999 if (flag_code == CODE_64BIT
7000 && i.op[0].regs->reg_type.bitfield.word)
7001 {
7002 as_bad (_("16-bit addressing unavailable for `%s'"),
7003 i.tm.name);
7004 return 0;
7005 }
7006
7007 if ((flag_code == CODE_32BIT
7008 ? i.op[0].regs->reg_type.bitfield.word
7009 : i.op[0].regs->reg_type.bitfield.dword)
7010 && !add_prefix (ADDR_PREFIX_OPCODE))
7011 return 0;
7012 }
7013 else
7014 {
7015 /* Check invalid register operand when the address size override
7016 prefix changes the size of register operands. */
7017 unsigned int op;
7018 enum { need_word, need_dword, need_qword } need;
7019
7020 if (flag_code == CODE_32BIT)
7021 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
7022 else if (i.prefix[ADDR_PREFIX])
7023 need = need_dword;
7024 else
7025 need = flag_code == CODE_64BIT ? need_qword : need_word;
7026
7027 for (op = 0; op < i.operands; op++)
7028 {
7029 if (i.types[op].bitfield.class != Reg)
7030 continue;
7031
7032 switch (need)
7033 {
7034 case need_word:
7035 if (i.op[op].regs->reg_type.bitfield.word)
7036 continue;
7037 break;
7038 case need_dword:
7039 if (i.op[op].regs->reg_type.bitfield.dword)
7040 continue;
7041 break;
7042 case need_qword:
7043 if (i.op[op].regs->reg_type.bitfield.qword)
7044 continue;
7045 break;
7046 }
7047
7048 as_bad (_("invalid register operand size for `%s'"),
7049 i.tm.name);
7050 return 0;
7051 }
7052 }
7053 }
7054
7055 return 1;
7056 }
7057
7058 static int
7059 check_byte_reg (void)
7060 {
7061 int op;
7062
7063 for (op = i.operands; --op >= 0;)
7064 {
7065 /* Skip non-register operands. */
7066 if (i.types[op].bitfield.class != Reg)
7067 continue;
7068
7069 /* If this is an eight bit register, it's OK. If it's the 16 or
7070 32 bit version of an eight bit register, we will just use the
7071 low portion, and that's OK too. */
7072 if (i.types[op].bitfield.byte)
7073 continue;
7074
7075 /* I/O port address operands are OK too. */
7076 if (i.tm.operand_types[op].bitfield.instance == RegD
7077 && i.tm.operand_types[op].bitfield.word)
7078 continue;
7079
7080 /* crc32 only wants its source operand checked here. */
7081 if (i.tm.base_opcode == 0xf20f38f0 && op)
7082 continue;
7083
7084 /* Any other register is bad. */
7085 if (i.types[op].bitfield.class == Reg
7086 || i.types[op].bitfield.class == RegMMX
7087 || i.types[op].bitfield.class == RegSIMD
7088 || i.types[op].bitfield.class == SReg
7089 || i.types[op].bitfield.class == RegCR
7090 || i.types[op].bitfield.class == RegDR
7091 || i.types[op].bitfield.class == RegTR)
7092 {
7093 as_bad (_("`%s%s' not allowed with `%s%c'"),
7094 register_prefix,
7095 i.op[op].regs->reg_name,
7096 i.tm.name,
7097 i.suffix);
7098 return 0;
7099 }
7100 }
7101 return 1;
7102 }
7103
7104 static int
7105 check_long_reg (void)
7106 {
7107 int op;
7108
7109 for (op = i.operands; --op >= 0;)
7110 /* Skip non-register operands. */
7111 if (i.types[op].bitfield.class != Reg)
7112 continue;
7113 /* Reject eight bit registers, except where the template requires
7114 them. (eg. movzb) */
7115 else if (i.types[op].bitfield.byte
7116 && (i.tm.operand_types[op].bitfield.class == Reg
7117 || i.tm.operand_types[op].bitfield.instance == Accum)
7118 && (i.tm.operand_types[op].bitfield.word
7119 || i.tm.operand_types[op].bitfield.dword))
7120 {
7121 as_bad (_("`%s%s' not allowed with `%s%c'"),
7122 register_prefix,
7123 i.op[op].regs->reg_name,
7124 i.tm.name,
7125 i.suffix);
7126 return 0;
7127 }
7128 /* Error if the e prefix on a general reg is missing. */
7129 else if (i.types[op].bitfield.word
7130 && (i.tm.operand_types[op].bitfield.class == Reg
7131 || i.tm.operand_types[op].bitfield.instance == Accum)
7132 && i.tm.operand_types[op].bitfield.dword)
7133 {
7134 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7135 register_prefix, i.op[op].regs->reg_name,
7136 i.suffix);
7137 return 0;
7138 }
7139 /* Warn if the r prefix on a general reg is present. */
7140 else if (i.types[op].bitfield.qword
7141 && (i.tm.operand_types[op].bitfield.class == Reg
7142 || i.tm.operand_types[op].bitfield.instance == Accum)
7143 && i.tm.operand_types[op].bitfield.dword)
7144 {
7145 if (intel_syntax
7146 && i.tm.opcode_modifier.toqword
7147 && i.types[0].bitfield.class != RegSIMD)
7148 {
7149 /* Convert to QWORD. We want REX byte. */
7150 i.suffix = QWORD_MNEM_SUFFIX;
7151 }
7152 else
7153 {
7154 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7155 register_prefix, i.op[op].regs->reg_name,
7156 i.suffix);
7157 return 0;
7158 }
7159 }
7160 return 1;
7161 }
7162
7163 static int
7164 check_qword_reg (void)
7165 {
7166 int op;
7167
7168 for (op = i.operands; --op >= 0; )
7169 /* Skip non-register operands. */
7170 if (i.types[op].bitfield.class != Reg)
7171 continue;
7172 /* Reject eight bit registers, except where the template requires
7173 them. (eg. movzb) */
7174 else if (i.types[op].bitfield.byte
7175 && (i.tm.operand_types[op].bitfield.class == Reg
7176 || i.tm.operand_types[op].bitfield.instance == Accum)
7177 && (i.tm.operand_types[op].bitfield.word
7178 || i.tm.operand_types[op].bitfield.dword))
7179 {
7180 as_bad (_("`%s%s' not allowed with `%s%c'"),
7181 register_prefix,
7182 i.op[op].regs->reg_name,
7183 i.tm.name,
7184 i.suffix);
7185 return 0;
7186 }
7187 /* Warn if the r prefix on a general reg is missing. */
7188 else if ((i.types[op].bitfield.word
7189 || i.types[op].bitfield.dword)
7190 && (i.tm.operand_types[op].bitfield.class == Reg
7191 || i.tm.operand_types[op].bitfield.instance == Accum)
7192 && i.tm.operand_types[op].bitfield.qword)
7193 {
7194 /* Prohibit these changes in the 64bit mode, since the
7195 lowering is more complicated. */
7196 if (intel_syntax
7197 && i.tm.opcode_modifier.todword
7198 && i.types[0].bitfield.class != RegSIMD)
7199 {
7200 /* Convert to DWORD. We don't want REX byte. */
7201 i.suffix = LONG_MNEM_SUFFIX;
7202 }
7203 else
7204 {
7205 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7206 register_prefix, i.op[op].regs->reg_name,
7207 i.suffix);
7208 return 0;
7209 }
7210 }
7211 return 1;
7212 }
7213
7214 static int
7215 check_word_reg (void)
7216 {
7217 int op;
7218 for (op = i.operands; --op >= 0;)
7219 /* Skip non-register operands. */
7220 if (i.types[op].bitfield.class != Reg)
7221 continue;
7222 /* Reject eight bit registers, except where the template requires
7223 them. (eg. movzb) */
7224 else if (i.types[op].bitfield.byte
7225 && (i.tm.operand_types[op].bitfield.class == Reg
7226 || i.tm.operand_types[op].bitfield.instance == Accum)
7227 && (i.tm.operand_types[op].bitfield.word
7228 || i.tm.operand_types[op].bitfield.dword))
7229 {
7230 as_bad (_("`%s%s' not allowed with `%s%c'"),
7231 register_prefix,
7232 i.op[op].regs->reg_name,
7233 i.tm.name,
7234 i.suffix);
7235 return 0;
7236 }
7237 /* Error if the e or r prefix on a general reg is present. */
7238 else if ((i.types[op].bitfield.dword
7239 || i.types[op].bitfield.qword)
7240 && (i.tm.operand_types[op].bitfield.class == Reg
7241 || i.tm.operand_types[op].bitfield.instance == Accum)
7242 && i.tm.operand_types[op].bitfield.word)
7243 {
7244 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7245 register_prefix, i.op[op].regs->reg_name,
7246 i.suffix);
7247 return 0;
7248 }
7249 return 1;
7250 }
7251
7252 static int
7253 update_imm (unsigned int j)
7254 {
7255 i386_operand_type overlap = i.types[j];
7256 if ((overlap.bitfield.imm8
7257 || overlap.bitfield.imm8s
7258 || overlap.bitfield.imm16
7259 || overlap.bitfield.imm32
7260 || overlap.bitfield.imm32s
7261 || overlap.bitfield.imm64)
7262 && !operand_type_equal (&overlap, &imm8)
7263 && !operand_type_equal (&overlap, &imm8s)
7264 && !operand_type_equal (&overlap, &imm16)
7265 && !operand_type_equal (&overlap, &imm32)
7266 && !operand_type_equal (&overlap, &imm32s)
7267 && !operand_type_equal (&overlap, &imm64))
7268 {
7269 if (i.suffix)
7270 {
7271 i386_operand_type temp;
7272
7273 operand_type_set (&temp, 0);
7274 if (i.suffix == BYTE_MNEM_SUFFIX)
7275 {
7276 temp.bitfield.imm8 = overlap.bitfield.imm8;
7277 temp.bitfield.imm8s = overlap.bitfield.imm8s;
7278 }
7279 else if (i.suffix == WORD_MNEM_SUFFIX)
7280 temp.bitfield.imm16 = overlap.bitfield.imm16;
7281 else if (i.suffix == QWORD_MNEM_SUFFIX)
7282 {
7283 temp.bitfield.imm64 = overlap.bitfield.imm64;
7284 temp.bitfield.imm32s = overlap.bitfield.imm32s;
7285 }
7286 else
7287 temp.bitfield.imm32 = overlap.bitfield.imm32;
7288 overlap = temp;
7289 }
7290 else if (operand_type_equal (&overlap, &imm16_32_32s)
7291 || operand_type_equal (&overlap, &imm16_32)
7292 || operand_type_equal (&overlap, &imm16_32s))
7293 {
7294 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
7295 overlap = imm16;
7296 else
7297 overlap = imm32s;
7298 }
7299 if (!operand_type_equal (&overlap, &imm8)
7300 && !operand_type_equal (&overlap, &imm8s)
7301 && !operand_type_equal (&overlap, &imm16)
7302 && !operand_type_equal (&overlap, &imm32)
7303 && !operand_type_equal (&overlap, &imm32s)
7304 && !operand_type_equal (&overlap, &imm64))
7305 {
7306 as_bad (_("no instruction mnemonic suffix given; "
7307 "can't determine immediate size"));
7308 return 0;
7309 }
7310 }
7311 i.types[j] = overlap;
7312
7313 return 1;
7314 }
7315
7316 static int
7317 finalize_imm (void)
7318 {
7319 unsigned int j, n;
7320
7321 /* Update the first 2 immediate operands. */
7322 n = i.operands > 2 ? 2 : i.operands;
7323 if (n)
7324 {
7325 for (j = 0; j < n; j++)
7326 if (update_imm (j) == 0)
7327 return 0;
7328
7329 /* The 3rd operand can't be immediate operand. */
7330 gas_assert (operand_type_check (i.types[2], imm) == 0);
7331 }
7332
7333 return 1;
7334 }
7335
7336 static int
7337 process_operands (void)
7338 {
7339 /* Default segment register this instruction will use for memory
7340 accesses. 0 means unknown. This is only for optimizing out
7341 unnecessary segment overrides. */
7342 const seg_entry *default_seg = 0;
7343
7344 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
7345 {
7346 unsigned int dupl = i.operands;
7347 unsigned int dest = dupl - 1;
7348 unsigned int j;
7349
7350 /* The destination must be an xmm register. */
7351 gas_assert (i.reg_operands
7352 && MAX_OPERANDS > dupl
7353 && operand_type_equal (&i.types[dest], &regxmm));
7354
7355 if (i.tm.operand_types[0].bitfield.instance == Accum
7356 && i.tm.operand_types[0].bitfield.xmmword)
7357 {
7358 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
7359 {
7360 /* Keep xmm0 for instructions with VEX prefix and 3
7361 sources. */
7362 i.tm.operand_types[0].bitfield.instance = InstanceNone;
7363 i.tm.operand_types[0].bitfield.class = RegSIMD;
7364 goto duplicate;
7365 }
7366 else
7367 {
7368 /* We remove the first xmm0 and keep the number of
7369 operands unchanged, which in fact duplicates the
7370 destination. */
7371 for (j = 1; j < i.operands; j++)
7372 {
7373 i.op[j - 1] = i.op[j];
7374 i.types[j - 1] = i.types[j];
7375 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
7376 i.flags[j - 1] = i.flags[j];
7377 }
7378 }
7379 }
7380 else if (i.tm.opcode_modifier.implicit1stxmm0)
7381 {
7382 gas_assert ((MAX_OPERANDS - 1) > dupl
7383 && (i.tm.opcode_modifier.vexsources
7384 == VEX3SOURCES));
7385
7386 /* Add the implicit xmm0 for instructions with VEX prefix
7387 and 3 sources. */
7388 for (j = i.operands; j > 0; j--)
7389 {
7390 i.op[j] = i.op[j - 1];
7391 i.types[j] = i.types[j - 1];
7392 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
7393 i.flags[j] = i.flags[j - 1];
7394 }
7395 i.op[0].regs
7396 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7397 i.types[0] = regxmm;
7398 i.tm.operand_types[0] = regxmm;
7399
7400 i.operands += 2;
7401 i.reg_operands += 2;
7402 i.tm.operands += 2;
7403
7404 dupl++;
7405 dest++;
7406 i.op[dupl] = i.op[dest];
7407 i.types[dupl] = i.types[dest];
7408 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
7409 i.flags[dupl] = i.flags[dest];
7410 }
7411 else
7412 {
7413 duplicate:
7414 i.operands++;
7415 i.reg_operands++;
7416 i.tm.operands++;
7417
7418 i.op[dupl] = i.op[dest];
7419 i.types[dupl] = i.types[dest];
7420 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
7421 i.flags[dupl] = i.flags[dest];
7422 }
7423
7424 if (i.tm.opcode_modifier.immext)
7425 process_immext ();
7426 }
7427 else if (i.tm.operand_types[0].bitfield.instance == Accum
7428 && i.tm.operand_types[0].bitfield.xmmword)
7429 {
7430 unsigned int j;
7431
7432 for (j = 1; j < i.operands; j++)
7433 {
7434 i.op[j - 1] = i.op[j];
7435 i.types[j - 1] = i.types[j];
7436
7437 /* We need to adjust fields in i.tm since they are used by
7438 build_modrm_byte. */
7439 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
7440
7441 i.flags[j - 1] = i.flags[j];
7442 }
7443
7444 i.operands--;
7445 i.reg_operands--;
7446 i.tm.operands--;
7447 }
7448 else if (i.tm.opcode_modifier.implicitquadgroup)
7449 {
7450 unsigned int regnum, first_reg_in_group, last_reg_in_group;
7451
7452 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7453 gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
7454 regnum = register_number (i.op[1].regs);
7455 first_reg_in_group = regnum & ~3;
7456 last_reg_in_group = first_reg_in_group + 3;
7457 if (regnum != first_reg_in_group)
7458 as_warn (_("source register `%s%s' implicitly denotes"
7459 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7460 register_prefix, i.op[1].regs->reg_name,
7461 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
7462 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
7463 i.tm.name);
7464 }
7465 else if (i.tm.opcode_modifier.regkludge)
7466 {
7467 /* The imul $imm, %reg instruction is converted into
7468 imul $imm, %reg, %reg, and the clr %reg instruction
7469 is converted into xor %reg, %reg. */
7470
7471 unsigned int first_reg_op;
7472
7473 if (operand_type_check (i.types[0], reg))
7474 first_reg_op = 0;
7475 else
7476 first_reg_op = 1;
7477 /* Pretend we saw the extra register operand. */
7478 gas_assert (i.reg_operands == 1
7479 && i.op[first_reg_op + 1].regs == 0);
7480 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
7481 i.types[first_reg_op + 1] = i.types[first_reg_op];
7482 i.operands++;
7483 i.reg_operands++;
7484 }
7485
7486 if (i.tm.opcode_modifier.modrm)
7487 {
7488 /* The opcode is completed (modulo i.tm.extension_opcode which
7489 must be put into the modrm byte). Now, we make the modrm and
7490 index base bytes based on all the info we've collected. */
7491
7492 default_seg = build_modrm_byte ();
7493 }
7494 else if (i.types[0].bitfield.class == SReg)
7495 {
7496 if (flag_code != CODE_64BIT
7497 ? i.tm.base_opcode == POP_SEG_SHORT
7498 && i.op[0].regs->reg_num == 1
7499 : (i.tm.base_opcode | 1) == POP_SEG386_SHORT
7500 && i.op[0].regs->reg_num < 4)
7501 {
7502 as_bad (_("you can't `%s %s%s'"),
7503 i.tm.name, register_prefix, i.op[0].regs->reg_name);
7504 return 0;
7505 }
7506 if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
7507 {
7508 i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
7509 i.tm.opcode_length = 2;
7510 }
7511 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
7512 }
7513 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
7514 {
7515 default_seg = &ds;
7516 }
7517 else if (i.tm.opcode_modifier.isstring)
7518 {
7519 /* For the string instructions that allow a segment override
7520 on one of their operands, the default segment is ds. */
7521 default_seg = &ds;
7522 }
7523 else if (i.short_form)
7524 {
7525 /* The register or float register operand is in operand
7526 0 or 1. */
7527 unsigned int op = i.tm.operand_types[0].bitfield.class != Reg;
7528
7529 /* Register goes in low 3 bits of opcode. */
7530 i.tm.base_opcode |= i.op[op].regs->reg_num;
7531 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7532 i.rex |= REX_B;
7533 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
7534 {
7535 /* Warn about some common errors, but press on regardless.
7536 The first case can be generated by gcc (<= 2.8.1). */
7537 if (i.operands == 2)
7538 {
7539 /* Reversed arguments on faddp, fsubp, etc. */
7540 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
7541 register_prefix, i.op[!intel_syntax].regs->reg_name,
7542 register_prefix, i.op[intel_syntax].regs->reg_name);
7543 }
7544 else
7545 {
7546 /* Extraneous `l' suffix on fp insn. */
7547 as_warn (_("translating to `%s %s%s'"), i.tm.name,
7548 register_prefix, i.op[0].regs->reg_name);
7549 }
7550 }
7551 }
7552
7553 if ((i.seg[0] || i.prefix[SEG_PREFIX])
7554 && i.tm.base_opcode == 0x8d /* lea */
7555 && !is_any_vex_encoding(&i.tm))
7556 {
7557 if (!quiet_warnings)
7558 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
7559 if (optimize)
7560 {
7561 i.seg[0] = NULL;
7562 i.prefix[SEG_PREFIX] = 0;
7563 }
7564 }
7565
7566 /* If a segment was explicitly specified, and the specified segment
7567 is neither the default nor the one already recorded from a prefix,
7568 use an opcode prefix to select it. If we never figured out what
7569 the default segment is, then default_seg will be zero at this
7570 point, and the specified segment prefix will always be used. */
7571 if (i.seg[0]
7572 && i.seg[0] != default_seg
7573 && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX])
7574 {
7575 if (!add_prefix (i.seg[0]->seg_prefix))
7576 return 0;
7577 }
7578 return 1;
7579 }
7580
7581 static const seg_entry *
7582 build_modrm_byte (void)
7583 {
7584 const seg_entry *default_seg = 0;
7585 unsigned int source, dest;
7586 int vex_3_sources;
7587
7588 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
7589 if (vex_3_sources)
7590 {
7591 unsigned int nds, reg_slot;
7592 expressionS *exp;
7593
7594 dest = i.operands - 1;
7595 nds = dest - 1;
7596
7597 /* There are 2 kinds of instructions:
7598 1. 5 operands: 4 register operands or 3 register operands
7599 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7600 VexW0 or VexW1. The destination must be either XMM, YMM or
7601 ZMM register.
7602 2. 4 operands: 4 register operands or 3 register operands
7603 plus 1 memory operand, with VexXDS. */
7604 gas_assert ((i.reg_operands == 4
7605 || (i.reg_operands == 3 && i.mem_operands == 1))
7606 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7607 && i.tm.opcode_modifier.vexw
7608 && i.tm.operand_types[dest].bitfield.class == RegSIMD);
7609
7610 /* If VexW1 is set, the first non-immediate operand is the source and
7611 the second non-immediate one is encoded in the immediate operand. */
7612 if (i.tm.opcode_modifier.vexw == VEXW1)
7613 {
7614 source = i.imm_operands;
7615 reg_slot = i.imm_operands + 1;
7616 }
7617 else
7618 {
7619 source = i.imm_operands + 1;
7620 reg_slot = i.imm_operands;
7621 }
7622
7623 if (i.imm_operands == 0)
7624 {
7625 /* When there is no immediate operand, generate an 8bit
7626 immediate operand to encode the first operand. */
7627 exp = &im_expressions[i.imm_operands++];
7628 i.op[i.operands].imms = exp;
7629 i.types[i.operands] = imm8;
7630 i.operands++;
7631
7632 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
7633 exp->X_op = O_constant;
7634 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
7635 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7636 }
7637 else
7638 {
7639 gas_assert (i.imm_operands == 1);
7640 gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
7641 gas_assert (!i.tm.opcode_modifier.immext);
7642
7643 /* Turn on Imm8 again so that output_imm will generate it. */
7644 i.types[0].bitfield.imm8 = 1;
7645
7646 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
7647 i.op[0].imms->X_add_number
7648 |= register_number (i.op[reg_slot].regs) << 4;
7649 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7650 }
7651
7652 gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
7653 i.vex.register_specifier = i.op[nds].regs;
7654 }
7655 else
7656 source = dest = 0;
7657
7658 /* i.reg_operands MUST be the number of real register operands;
7659 implicit registers do not count. If there are 3 register
7660 operands, it must be a instruction with VexNDS. For a
7661 instruction with VexNDD, the destination register is encoded
7662 in VEX prefix. If there are 4 register operands, it must be
7663 a instruction with VEX prefix and 3 sources. */
7664 if (i.mem_operands == 0
7665 && ((i.reg_operands == 2
7666 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7667 || (i.reg_operands == 3
7668 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7669 || (i.reg_operands == 4 && vex_3_sources)))
7670 {
7671 switch (i.operands)
7672 {
7673 case 2:
7674 source = 0;
7675 break;
7676 case 3:
7677 /* When there are 3 operands, one of them may be immediate,
7678 which may be the first or the last operand. Otherwise,
7679 the first operand must be shift count register (cl) or it
7680 is an instruction with VexNDS. */
7681 gas_assert (i.imm_operands == 1
7682 || (i.imm_operands == 0
7683 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7684 || (i.types[0].bitfield.instance == RegC
7685 && i.types[0].bitfield.byte))));
7686 if (operand_type_check (i.types[0], imm)
7687 || (i.types[0].bitfield.instance == RegC
7688 && i.types[0].bitfield.byte))
7689 source = 1;
7690 else
7691 source = 0;
7692 break;
7693 case 4:
7694 /* When there are 4 operands, the first two must be 8bit
7695 immediate operands. The source operand will be the 3rd
7696 one.
7697
7698 For instructions with VexNDS, if the first operand
7699 an imm8, the source operand is the 2nd one. If the last
7700 operand is imm8, the source operand is the first one. */
7701 gas_assert ((i.imm_operands == 2
7702 && i.types[0].bitfield.imm8
7703 && i.types[1].bitfield.imm8)
7704 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7705 && i.imm_operands == 1
7706 && (i.types[0].bitfield.imm8
7707 || i.types[i.operands - 1].bitfield.imm8
7708 || i.rounding)));
7709 if (i.imm_operands == 2)
7710 source = 2;
7711 else
7712 {
7713 if (i.types[0].bitfield.imm8)
7714 source = 1;
7715 else
7716 source = 0;
7717 }
7718 break;
7719 case 5:
7720 if (is_evex_encoding (&i.tm))
7721 {
7722 /* For EVEX instructions, when there are 5 operands, the
7723 first one must be immediate operand. If the second one
7724 is immediate operand, the source operand is the 3th
7725 one. If the last one is immediate operand, the source
7726 operand is the 2nd one. */
7727 gas_assert (i.imm_operands == 2
7728 && i.tm.opcode_modifier.sae
7729 && operand_type_check (i.types[0], imm));
7730 if (operand_type_check (i.types[1], imm))
7731 source = 2;
7732 else if (operand_type_check (i.types[4], imm))
7733 source = 1;
7734 else
7735 abort ();
7736 }
7737 break;
7738 default:
7739 abort ();
7740 }
7741
7742 if (!vex_3_sources)
7743 {
7744 dest = source + 1;
7745
7746 /* RC/SAE operand could be between DEST and SRC. That happens
7747 when one operand is GPR and the other one is XMM/YMM/ZMM
7748 register. */
7749 if (i.rounding && i.rounding->operand == (int) dest)
7750 dest++;
7751
7752 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7753 {
7754 /* For instructions with VexNDS, the register-only source
7755 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7756 register. It is encoded in VEX prefix. */
7757
7758 i386_operand_type op;
7759 unsigned int vvvv;
7760
7761 /* Check register-only source operand when two source
7762 operands are swapped. */
7763 if (!i.tm.operand_types[source].bitfield.baseindex
7764 && i.tm.operand_types[dest].bitfield.baseindex)
7765 {
7766 vvvv = source;
7767 source = dest;
7768 }
7769 else
7770 vvvv = dest;
7771
7772 op = i.tm.operand_types[vvvv];
7773 if ((dest + 1) >= i.operands
7774 || ((op.bitfield.class != Reg
7775 || (!op.bitfield.dword && !op.bitfield.qword))
7776 && op.bitfield.class != RegSIMD
7777 && !operand_type_equal (&op, &regmask)))
7778 abort ();
7779 i.vex.register_specifier = i.op[vvvv].regs;
7780 dest++;
7781 }
7782 }
7783
7784 i.rm.mode = 3;
7785 /* One of the register operands will be encoded in the i.rm.reg
7786 field, the other in the combined i.rm.mode and i.rm.regmem
7787 fields. If no form of this instruction supports a memory
7788 destination operand, then we assume the source operand may
7789 sometimes be a memory operand and so we need to store the
7790 destination in the i.rm.reg field. */
7791 if (!i.tm.opcode_modifier.regmem
7792 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7793 {
7794 i.rm.reg = i.op[dest].regs->reg_num;
7795 i.rm.regmem = i.op[source].regs->reg_num;
7796 if (i.op[dest].regs->reg_type.bitfield.class == RegMMX
7797 || i.op[source].regs->reg_type.bitfield.class == RegMMX)
7798 i.has_regmmx = TRUE;
7799 else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD
7800 || i.op[source].regs->reg_type.bitfield.class == RegSIMD)
7801 {
7802 if (i.types[dest].bitfield.zmmword
7803 || i.types[source].bitfield.zmmword)
7804 i.has_regzmm = TRUE;
7805 else if (i.types[dest].bitfield.ymmword
7806 || i.types[source].bitfield.ymmword)
7807 i.has_regymm = TRUE;
7808 else
7809 i.has_regxmm = TRUE;
7810 }
7811 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7812 i.rex |= REX_R;
7813 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7814 i.vrex |= REX_R;
7815 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7816 i.rex |= REX_B;
7817 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7818 i.vrex |= REX_B;
7819 }
7820 else
7821 {
7822 i.rm.reg = i.op[source].regs->reg_num;
7823 i.rm.regmem = i.op[dest].regs->reg_num;
7824 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7825 i.rex |= REX_B;
7826 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7827 i.vrex |= REX_B;
7828 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7829 i.rex |= REX_R;
7830 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7831 i.vrex |= REX_R;
7832 }
7833 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7834 {
7835 if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
7836 abort ();
7837 i.rex &= ~REX_R;
7838 add_prefix (LOCK_PREFIX_OPCODE);
7839 }
7840 }
7841 else
7842 { /* If it's not 2 reg operands... */
7843 unsigned int mem;
7844
7845 if (i.mem_operands)
7846 {
7847 unsigned int fake_zero_displacement = 0;
7848 unsigned int op;
7849
7850 for (op = 0; op < i.operands; op++)
7851 if (i.flags[op] & Operand_Mem)
7852 break;
7853 gas_assert (op < i.operands);
7854
7855 if (i.tm.opcode_modifier.vecsib)
7856 {
7857 if (i.index_reg->reg_num == RegIZ)
7858 abort ();
7859
7860 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7861 if (!i.base_reg)
7862 {
7863 i.sib.base = NO_BASE_REGISTER;
7864 i.sib.scale = i.log2_scale_factor;
7865 i.types[op].bitfield.disp8 = 0;
7866 i.types[op].bitfield.disp16 = 0;
7867 i.types[op].bitfield.disp64 = 0;
7868 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7869 {
7870 /* Must be 32 bit */
7871 i.types[op].bitfield.disp32 = 1;
7872 i.types[op].bitfield.disp32s = 0;
7873 }
7874 else
7875 {
7876 i.types[op].bitfield.disp32 = 0;
7877 i.types[op].bitfield.disp32s = 1;
7878 }
7879 }
7880 i.sib.index = i.index_reg->reg_num;
7881 if ((i.index_reg->reg_flags & RegRex) != 0)
7882 i.rex |= REX_X;
7883 if ((i.index_reg->reg_flags & RegVRex) != 0)
7884 i.vrex |= REX_X;
7885 }
7886
7887 default_seg = &ds;
7888
7889 if (i.base_reg == 0)
7890 {
7891 i.rm.mode = 0;
7892 if (!i.disp_operands)
7893 fake_zero_displacement = 1;
7894 if (i.index_reg == 0)
7895 {
7896 i386_operand_type newdisp;
7897
7898 gas_assert (!i.tm.opcode_modifier.vecsib);
7899 /* Operand is just <disp> */
7900 if (flag_code == CODE_64BIT)
7901 {
7902 /* 64bit mode overwrites the 32bit absolute
7903 addressing by RIP relative addressing and
7904 absolute addressing is encoded by one of the
7905 redundant SIB forms. */
7906 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7907 i.sib.base = NO_BASE_REGISTER;
7908 i.sib.index = NO_INDEX_REGISTER;
7909 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7910 }
7911 else if ((flag_code == CODE_16BIT)
7912 ^ (i.prefix[ADDR_PREFIX] != 0))
7913 {
7914 i.rm.regmem = NO_BASE_REGISTER_16;
7915 newdisp = disp16;
7916 }
7917 else
7918 {
7919 i.rm.regmem = NO_BASE_REGISTER;
7920 newdisp = disp32;
7921 }
7922 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7923 i.types[op] = operand_type_or (i.types[op], newdisp);
7924 }
7925 else if (!i.tm.opcode_modifier.vecsib)
7926 {
7927 /* !i.base_reg && i.index_reg */
7928 if (i.index_reg->reg_num == RegIZ)
7929 i.sib.index = NO_INDEX_REGISTER;
7930 else
7931 i.sib.index = i.index_reg->reg_num;
7932 i.sib.base = NO_BASE_REGISTER;
7933 i.sib.scale = i.log2_scale_factor;
7934 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7935 i.types[op].bitfield.disp8 = 0;
7936 i.types[op].bitfield.disp16 = 0;
7937 i.types[op].bitfield.disp64 = 0;
7938 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7939 {
7940 /* Must be 32 bit */
7941 i.types[op].bitfield.disp32 = 1;
7942 i.types[op].bitfield.disp32s = 0;
7943 }
7944 else
7945 {
7946 i.types[op].bitfield.disp32 = 0;
7947 i.types[op].bitfield.disp32s = 1;
7948 }
7949 if ((i.index_reg->reg_flags & RegRex) != 0)
7950 i.rex |= REX_X;
7951 }
7952 }
7953 /* RIP addressing for 64bit mode. */
7954 else if (i.base_reg->reg_num == RegIP)
7955 {
7956 gas_assert (!i.tm.opcode_modifier.vecsib);
7957 i.rm.regmem = NO_BASE_REGISTER;
7958 i.types[op].bitfield.disp8 = 0;
7959 i.types[op].bitfield.disp16 = 0;
7960 i.types[op].bitfield.disp32 = 0;
7961 i.types[op].bitfield.disp32s = 1;
7962 i.types[op].bitfield.disp64 = 0;
7963 i.flags[op] |= Operand_PCrel;
7964 if (! i.disp_operands)
7965 fake_zero_displacement = 1;
7966 }
7967 else if (i.base_reg->reg_type.bitfield.word)
7968 {
7969 gas_assert (!i.tm.opcode_modifier.vecsib);
7970 switch (i.base_reg->reg_num)
7971 {
7972 case 3: /* (%bx) */
7973 if (i.index_reg == 0)
7974 i.rm.regmem = 7;
7975 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7976 i.rm.regmem = i.index_reg->reg_num - 6;
7977 break;
7978 case 5: /* (%bp) */
7979 default_seg = &ss;
7980 if (i.index_reg == 0)
7981 {
7982 i.rm.regmem = 6;
7983 if (operand_type_check (i.types[op], disp) == 0)
7984 {
7985 /* fake (%bp) into 0(%bp) */
7986 i.types[op].bitfield.disp8 = 1;
7987 fake_zero_displacement = 1;
7988 }
7989 }
7990 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7991 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7992 break;
7993 default: /* (%si) -> 4 or (%di) -> 5 */
7994 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7995 }
7996 i.rm.mode = mode_from_disp_size (i.types[op]);
7997 }
7998 else /* i.base_reg and 32/64 bit mode */
7999 {
8000 if (flag_code == CODE_64BIT
8001 && operand_type_check (i.types[op], disp))
8002 {
8003 i.types[op].bitfield.disp16 = 0;
8004 i.types[op].bitfield.disp64 = 0;
8005 if (i.prefix[ADDR_PREFIX] == 0)
8006 {
8007 i.types[op].bitfield.disp32 = 0;
8008 i.types[op].bitfield.disp32s = 1;
8009 }
8010 else
8011 {
8012 i.types[op].bitfield.disp32 = 1;
8013 i.types[op].bitfield.disp32s = 0;
8014 }
8015 }
8016
8017 if (!i.tm.opcode_modifier.vecsib)
8018 i.rm.regmem = i.base_reg->reg_num;
8019 if ((i.base_reg->reg_flags & RegRex) != 0)
8020 i.rex |= REX_B;
8021 i.sib.base = i.base_reg->reg_num;
8022 /* x86-64 ignores REX prefix bit here to avoid decoder
8023 complications. */
8024 if (!(i.base_reg->reg_flags & RegRex)
8025 && (i.base_reg->reg_num == EBP_REG_NUM
8026 || i.base_reg->reg_num == ESP_REG_NUM))
8027 default_seg = &ss;
8028 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
8029 {
8030 fake_zero_displacement = 1;
8031 i.types[op].bitfield.disp8 = 1;
8032 }
8033 i.sib.scale = i.log2_scale_factor;
8034 if (i.index_reg == 0)
8035 {
8036 gas_assert (!i.tm.opcode_modifier.vecsib);
8037 /* <disp>(%esp) becomes two byte modrm with no index
8038 register. We've already stored the code for esp
8039 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8040 Any base register besides %esp will not use the
8041 extra modrm byte. */
8042 i.sib.index = NO_INDEX_REGISTER;
8043 }
8044 else if (!i.tm.opcode_modifier.vecsib)
8045 {
8046 if (i.index_reg->reg_num == RegIZ)
8047 i.sib.index = NO_INDEX_REGISTER;
8048 else
8049 i.sib.index = i.index_reg->reg_num;
8050 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
8051 if ((i.index_reg->reg_flags & RegRex) != 0)
8052 i.rex |= REX_X;
8053 }
8054
8055 if (i.disp_operands
8056 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
8057 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
8058 i.rm.mode = 0;
8059 else
8060 {
8061 if (!fake_zero_displacement
8062 && !i.disp_operands
8063 && i.disp_encoding)
8064 {
8065 fake_zero_displacement = 1;
8066 if (i.disp_encoding == disp_encoding_8bit)
8067 i.types[op].bitfield.disp8 = 1;
8068 else
8069 i.types[op].bitfield.disp32 = 1;
8070 }
8071 i.rm.mode = mode_from_disp_size (i.types[op]);
8072 }
8073 }
8074
8075 if (fake_zero_displacement)
8076 {
8077 /* Fakes a zero displacement assuming that i.types[op]
8078 holds the correct displacement size. */
8079 expressionS *exp;
8080
8081 gas_assert (i.op[op].disps == 0);
8082 exp = &disp_expressions[i.disp_operands++];
8083 i.op[op].disps = exp;
8084 exp->X_op = O_constant;
8085 exp->X_add_number = 0;
8086 exp->X_add_symbol = (symbolS *) 0;
8087 exp->X_op_symbol = (symbolS *) 0;
8088 }
8089
8090 mem = op;
8091 }
8092 else
8093 mem = ~0;
8094
8095 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
8096 {
8097 if (operand_type_check (i.types[0], imm))
8098 i.vex.register_specifier = NULL;
8099 else
8100 {
8101 /* VEX.vvvv encodes one of the sources when the first
8102 operand is not an immediate. */
8103 if (i.tm.opcode_modifier.vexw == VEXW0)
8104 i.vex.register_specifier = i.op[0].regs;
8105 else
8106 i.vex.register_specifier = i.op[1].regs;
8107 }
8108
8109 /* Destination is a XMM register encoded in the ModRM.reg
8110 and VEX.R bit. */
8111 i.rm.reg = i.op[2].regs->reg_num;
8112 if ((i.op[2].regs->reg_flags & RegRex) != 0)
8113 i.rex |= REX_R;
8114
8115 /* ModRM.rm and VEX.B encodes the other source. */
8116 if (!i.mem_operands)
8117 {
8118 i.rm.mode = 3;
8119
8120 if (i.tm.opcode_modifier.vexw == VEXW0)
8121 i.rm.regmem = i.op[1].regs->reg_num;
8122 else
8123 i.rm.regmem = i.op[0].regs->reg_num;
8124
8125 if ((i.op[1].regs->reg_flags & RegRex) != 0)
8126 i.rex |= REX_B;
8127 }
8128 }
8129 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
8130 {
8131 i.vex.register_specifier = i.op[2].regs;
8132 if (!i.mem_operands)
8133 {
8134 i.rm.mode = 3;
8135 i.rm.regmem = i.op[1].regs->reg_num;
8136 if ((i.op[1].regs->reg_flags & RegRex) != 0)
8137 i.rex |= REX_B;
8138 }
8139 }
8140 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8141 (if any) based on i.tm.extension_opcode. Again, we must be
8142 careful to make sure that segment/control/debug/test/MMX
8143 registers are coded into the i.rm.reg field. */
8144 else if (i.reg_operands)
8145 {
8146 unsigned int op;
8147 unsigned int vex_reg = ~0;
8148
8149 for (op = 0; op < i.operands; op++)
8150 {
8151 if (i.types[op].bitfield.class == Reg
8152 || i.types[op].bitfield.class == RegBND
8153 || i.types[op].bitfield.class == RegMask
8154 || i.types[op].bitfield.class == SReg
8155 || i.types[op].bitfield.class == RegCR
8156 || i.types[op].bitfield.class == RegDR
8157 || i.types[op].bitfield.class == RegTR)
8158 break;
8159 if (i.types[op].bitfield.class == RegSIMD)
8160 {
8161 if (i.types[op].bitfield.zmmword)
8162 i.has_regzmm = TRUE;
8163 else if (i.types[op].bitfield.ymmword)
8164 i.has_regymm = TRUE;
8165 else
8166 i.has_regxmm = TRUE;
8167 break;
8168 }
8169 if (i.types[op].bitfield.class == RegMMX)
8170 {
8171 i.has_regmmx = TRUE;
8172 break;
8173 }
8174 }
8175
8176 if (vex_3_sources)
8177 op = dest;
8178 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
8179 {
8180 /* For instructions with VexNDS, the register-only
8181 source operand is encoded in VEX prefix. */
8182 gas_assert (mem != (unsigned int) ~0);
8183
8184 if (op > mem)
8185 {
8186 vex_reg = op++;
8187 gas_assert (op < i.operands);
8188 }
8189 else
8190 {
8191 /* Check register-only source operand when two source
8192 operands are swapped. */
8193 if (!i.tm.operand_types[op].bitfield.baseindex
8194 && i.tm.operand_types[op + 1].bitfield.baseindex)
8195 {
8196 vex_reg = op;
8197 op += 2;
8198 gas_assert (mem == (vex_reg + 1)
8199 && op < i.operands);
8200 }
8201 else
8202 {
8203 vex_reg = op + 1;
8204 gas_assert (vex_reg < i.operands);
8205 }
8206 }
8207 }
8208 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
8209 {
8210 /* For instructions with VexNDD, the register destination
8211 is encoded in VEX prefix. */
8212 if (i.mem_operands == 0)
8213 {
8214 /* There is no memory operand. */
8215 gas_assert ((op + 2) == i.operands);
8216 vex_reg = op + 1;
8217 }
8218 else
8219 {
8220 /* There are only 2 non-immediate operands. */
8221 gas_assert (op < i.imm_operands + 2
8222 && i.operands == i.imm_operands + 2);
8223 vex_reg = i.imm_operands + 1;
8224 }
8225 }
8226 else
8227 gas_assert (op < i.operands);
8228
8229 if (vex_reg != (unsigned int) ~0)
8230 {
8231 i386_operand_type *type = &i.tm.operand_types[vex_reg];
8232
8233 if ((type->bitfield.class != Reg
8234 || (!type->bitfield.dword && !type->bitfield.qword))
8235 && type->bitfield.class != RegSIMD
8236 && !operand_type_equal (type, &regmask))
8237 abort ();
8238
8239 i.vex.register_specifier = i.op[vex_reg].regs;
8240 }
8241
8242 /* Don't set OP operand twice. */
8243 if (vex_reg != op)
8244 {
8245 /* If there is an extension opcode to put here, the
8246 register number must be put into the regmem field. */
8247 if (i.tm.extension_opcode != None)
8248 {
8249 i.rm.regmem = i.op[op].regs->reg_num;
8250 if ((i.op[op].regs->reg_flags & RegRex) != 0)
8251 i.rex |= REX_B;
8252 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
8253 i.vrex |= REX_B;
8254 }
8255 else
8256 {
8257 i.rm.reg = i.op[op].regs->reg_num;
8258 if ((i.op[op].regs->reg_flags & RegRex) != 0)
8259 i.rex |= REX_R;
8260 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
8261 i.vrex |= REX_R;
8262 }
8263 }
8264
8265 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8266 must set it to 3 to indicate this is a register operand
8267 in the regmem field. */
8268 if (!i.mem_operands)
8269 i.rm.mode = 3;
8270 }
8271
8272 /* Fill in i.rm.reg field with extension opcode (if any). */
8273 if (i.tm.extension_opcode != None)
8274 i.rm.reg = i.tm.extension_opcode;
8275 }
8276 return default_seg;
8277 }
8278
8279 static unsigned int
8280 flip_code16 (unsigned int code16)
8281 {
8282 gas_assert (i.tm.operands == 1);
8283
8284 return !(i.prefix[REX_PREFIX] & REX_W)
8285 && (code16 ? i.tm.operand_types[0].bitfield.disp32
8286 || i.tm.operand_types[0].bitfield.disp32s
8287 : i.tm.operand_types[0].bitfield.disp16)
8288 ? CODE16 : 0;
8289 }
8290
8291 static void
8292 output_branch (void)
8293 {
8294 char *p;
8295 int size;
8296 int code16;
8297 int prefix;
8298 relax_substateT subtype;
8299 symbolS *sym;
8300 offsetT off;
8301
8302 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
8303 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
8304
8305 prefix = 0;
8306 if (i.prefix[DATA_PREFIX] != 0)
8307 {
8308 prefix = 1;
8309 i.prefixes -= 1;
8310 code16 ^= flip_code16(code16);
8311 }
8312 /* Pentium4 branch hints. */
8313 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
8314 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
8315 {
8316 prefix++;
8317 i.prefixes--;
8318 }
8319 if (i.prefix[REX_PREFIX] != 0)
8320 {
8321 prefix++;
8322 i.prefixes--;
8323 }
8324
8325 /* BND prefixed jump. */
8326 if (i.prefix[BND_PREFIX] != 0)
8327 {
8328 prefix++;
8329 i.prefixes--;
8330 }
8331
8332 if (i.prefixes != 0)
8333 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8334
8335 /* It's always a symbol; End frag & setup for relax.
8336 Make sure there is enough room in this frag for the largest
8337 instruction we may generate in md_convert_frag. This is 2
8338 bytes for the opcode and room for the prefix and largest
8339 displacement. */
8340 frag_grow (prefix + 2 + 4);
8341 /* Prefix and 1 opcode byte go in fr_fix. */
8342 p = frag_more (prefix + 1);
8343 if (i.prefix[DATA_PREFIX] != 0)
8344 *p++ = DATA_PREFIX_OPCODE;
8345 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
8346 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
8347 *p++ = i.prefix[SEG_PREFIX];
8348 if (i.prefix[BND_PREFIX] != 0)
8349 *p++ = BND_PREFIX_OPCODE;
8350 if (i.prefix[REX_PREFIX] != 0)
8351 *p++ = i.prefix[REX_PREFIX];
8352 *p = i.tm.base_opcode;
8353
8354 if ((unsigned char) *p == JUMP_PC_RELATIVE)
8355 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
8356 else if (cpu_arch_flags.bitfield.cpui386)
8357 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
8358 else
8359 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
8360 subtype |= code16;
8361
8362 sym = i.op[0].disps->X_add_symbol;
8363 off = i.op[0].disps->X_add_number;
8364
8365 if (i.op[0].disps->X_op != O_constant
8366 && i.op[0].disps->X_op != O_symbol)
8367 {
8368 /* Handle complex expressions. */
8369 sym = make_expr_symbol (i.op[0].disps);
8370 off = 0;
8371 }
8372
8373 /* 1 possible extra opcode + 4 byte displacement go in var part.
8374 Pass reloc in fr_var. */
8375 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
8376 }
8377
8378 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8379 /* Return TRUE iff PLT32 relocation should be used for branching to
8380 symbol S. */
8381
8382 static bfd_boolean
8383 need_plt32_p (symbolS *s)
8384 {
8385 /* PLT32 relocation is ELF only. */
8386 if (!IS_ELF)
8387 return FALSE;
8388
8389 #ifdef TE_SOLARIS
8390 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8391 krtld support it. */
8392 return FALSE;
8393 #endif
8394
8395 /* Since there is no need to prepare for PLT branch on x86-64, we
8396 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8397 be used as a marker for 32-bit PC-relative branches. */
8398 if (!object_64bit)
8399 return FALSE;
8400
8401 /* Weak or undefined symbol need PLT32 relocation. */
8402 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
8403 return TRUE;
8404
8405 /* Non-global symbol doesn't need PLT32 relocation. */
8406 if (! S_IS_EXTERNAL (s))
8407 return FALSE;
8408
8409 /* Other global symbols need PLT32 relocation. NB: Symbol with
8410 non-default visibilities are treated as normal global symbol
8411 so that PLT32 relocation can be used as a marker for 32-bit
8412 PC-relative branches. It is useful for linker relaxation. */
8413 return TRUE;
8414 }
8415 #endif
8416
8417 static void
8418 output_jump (void)
8419 {
8420 char *p;
8421 int size;
8422 fixS *fixP;
8423 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
8424
8425 if (i.tm.opcode_modifier.jump == JUMP_BYTE)
8426 {
8427 /* This is a loop or jecxz type instruction. */
8428 size = 1;
8429 if (i.prefix[ADDR_PREFIX] != 0)
8430 {
8431 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
8432 i.prefixes -= 1;
8433 }
8434 /* Pentium4 branch hints. */
8435 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
8436 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
8437 {
8438 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
8439 i.prefixes--;
8440 }
8441 }
8442 else
8443 {
8444 int code16;
8445
8446 code16 = 0;
8447 if (flag_code == CODE_16BIT)
8448 code16 = CODE16;
8449
8450 if (i.prefix[DATA_PREFIX] != 0)
8451 {
8452 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
8453 i.prefixes -= 1;
8454 code16 ^= flip_code16(code16);
8455 }
8456
8457 size = 4;
8458 if (code16)
8459 size = 2;
8460 }
8461
8462 /* BND prefixed jump. */
8463 if (i.prefix[BND_PREFIX] != 0)
8464 {
8465 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
8466 i.prefixes -= 1;
8467 }
8468
8469 if (i.prefix[REX_PREFIX] != 0)
8470 {
8471 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
8472 i.prefixes -= 1;
8473 }
8474
8475 if (i.prefixes != 0)
8476 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8477
8478 p = frag_more (i.tm.opcode_length + size);
8479 switch (i.tm.opcode_length)
8480 {
8481 case 2:
8482 *p++ = i.tm.base_opcode >> 8;
8483 /* Fall through. */
8484 case 1:
8485 *p++ = i.tm.base_opcode;
8486 break;
8487 default:
8488 abort ();
8489 }
8490
8491 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8492 if (size == 4
8493 && jump_reloc == NO_RELOC
8494 && need_plt32_p (i.op[0].disps->X_add_symbol))
8495 jump_reloc = BFD_RELOC_X86_64_PLT32;
8496 #endif
8497
8498 jump_reloc = reloc (size, 1, 1, jump_reloc);
8499
8500 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8501 i.op[0].disps, 1, jump_reloc);
8502
8503 /* All jumps handled here are signed, but don't use a signed limit
8504 check for 32 and 16 bit jumps as we want to allow wrap around at
8505 4G and 64k respectively. */
8506 if (size == 1)
8507 fixP->fx_signed = 1;
8508 }
8509
8510 static void
8511 output_interseg_jump (void)
8512 {
8513 char *p;
8514 int size;
8515 int prefix;
8516 int code16;
8517
8518 code16 = 0;
8519 if (flag_code == CODE_16BIT)
8520 code16 = CODE16;
8521
8522 prefix = 0;
8523 if (i.prefix[DATA_PREFIX] != 0)
8524 {
8525 prefix = 1;
8526 i.prefixes -= 1;
8527 code16 ^= CODE16;
8528 }
8529
8530 gas_assert (!i.prefix[REX_PREFIX]);
8531
8532 size = 4;
8533 if (code16)
8534 size = 2;
8535
8536 if (i.prefixes != 0)
8537 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8538
8539 /* 1 opcode; 2 segment; offset */
8540 p = frag_more (prefix + 1 + 2 + size);
8541
8542 if (i.prefix[DATA_PREFIX] != 0)
8543 *p++ = DATA_PREFIX_OPCODE;
8544
8545 if (i.prefix[REX_PREFIX] != 0)
8546 *p++ = i.prefix[REX_PREFIX];
8547
8548 *p++ = i.tm.base_opcode;
8549 if (i.op[1].imms->X_op == O_constant)
8550 {
8551 offsetT n = i.op[1].imms->X_add_number;
8552
8553 if (size == 2
8554 && !fits_in_unsigned_word (n)
8555 && !fits_in_signed_word (n))
8556 {
8557 as_bad (_("16-bit jump out of range"));
8558 return;
8559 }
8560 md_number_to_chars (p, n, size);
8561 }
8562 else
8563 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8564 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
8565 if (i.op[0].imms->X_op != O_constant)
8566 as_bad (_("can't handle non absolute segment in `%s'"),
8567 i.tm.name);
8568 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
8569 }
8570
8571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8572 void
8573 x86_cleanup (void)
8574 {
8575 char *p;
8576 asection *seg = now_seg;
8577 subsegT subseg = now_subseg;
8578 asection *sec;
8579 unsigned int alignment, align_size_1;
8580 unsigned int isa_1_descsz, feature_2_descsz, descsz;
8581 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
8582 unsigned int padding;
8583
8584 if (!IS_ELF || !x86_used_note)
8585 return;
8586
8587 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
8588
8589 /* The .note.gnu.property section layout:
8590
8591 Field Length Contents
8592 ---- ---- ----
8593 n_namsz 4 4
8594 n_descsz 4 The note descriptor size
8595 n_type 4 NT_GNU_PROPERTY_TYPE_0
8596 n_name 4 "GNU"
8597 n_desc n_descsz The program property array
8598 .... .... ....
8599 */
8600
8601 /* Create the .note.gnu.property section. */
8602 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
8603 bfd_set_section_flags (sec,
8604 (SEC_ALLOC
8605 | SEC_LOAD
8606 | SEC_DATA
8607 | SEC_HAS_CONTENTS
8608 | SEC_READONLY));
8609
8610 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
8611 {
8612 align_size_1 = 7;
8613 alignment = 3;
8614 }
8615 else
8616 {
8617 align_size_1 = 3;
8618 alignment = 2;
8619 }
8620
8621 bfd_set_section_alignment (sec, alignment);
8622 elf_section_type (sec) = SHT_NOTE;
8623
8624 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8625 + 4-byte data */
8626 isa_1_descsz_raw = 4 + 4 + 4;
8627 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8628 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
8629
8630 feature_2_descsz_raw = isa_1_descsz;
8631 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8632 + 4-byte data */
8633 feature_2_descsz_raw += 4 + 4 + 4;
8634 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8635 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
8636 & ~align_size_1);
8637
8638 descsz = feature_2_descsz;
8639 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8640 p = frag_more (4 + 4 + 4 + 4 + descsz);
8641
8642 /* Write n_namsz. */
8643 md_number_to_chars (p, (valueT) 4, 4);
8644
8645 /* Write n_descsz. */
8646 md_number_to_chars (p + 4, (valueT) descsz, 4);
8647
8648 /* Write n_type. */
8649 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
8650
8651 /* Write n_name. */
8652 memcpy (p + 4 * 3, "GNU", 4);
8653
8654 /* Write 4-byte type. */
8655 md_number_to_chars (p + 4 * 4,
8656 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
8657
8658 /* Write 4-byte data size. */
8659 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
8660
8661 /* Write 4-byte data. */
8662 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
8663
8664 /* Zero out paddings. */
8665 padding = isa_1_descsz - isa_1_descsz_raw;
8666 if (padding)
8667 memset (p + 4 * 7, 0, padding);
8668
8669 /* Write 4-byte type. */
8670 md_number_to_chars (p + isa_1_descsz + 4 * 4,
8671 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
8672
8673 /* Write 4-byte data size. */
8674 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
8675
8676 /* Write 4-byte data. */
8677 md_number_to_chars (p + isa_1_descsz + 4 * 6,
8678 (valueT) x86_feature_2_used, 4);
8679
8680 /* Zero out paddings. */
8681 padding = feature_2_descsz - feature_2_descsz_raw;
8682 if (padding)
8683 memset (p + isa_1_descsz + 4 * 7, 0, padding);
8684
8685 /* We probably can't restore the current segment, for there likely
8686 isn't one yet... */
8687 if (seg && subseg)
8688 subseg_set (seg, subseg);
8689 }
8690 #endif
8691
8692 static unsigned int
8693 encoding_length (const fragS *start_frag, offsetT start_off,
8694 const char *frag_now_ptr)
8695 {
8696 unsigned int len = 0;
8697
8698 if (start_frag != frag_now)
8699 {
8700 const fragS *fr = start_frag;
8701
8702 do {
8703 len += fr->fr_fix;
8704 fr = fr->fr_next;
8705 } while (fr && fr != frag_now);
8706 }
8707
8708 return len - start_off + (frag_now_ptr - frag_now->fr_literal);
8709 }
8710
8711 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8712 be macro-fused with conditional jumps.
8713 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8714 or is one of the following format:
8715
8716 cmp m, imm
8717 add m, imm
8718 sub m, imm
8719 test m, imm
8720 and m, imm
8721 inc m
8722 dec m
8723
8724 it is unfusible. */
8725
8726 static int
8727 maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
8728 {
8729 /* No RIP address. */
8730 if (i.base_reg && i.base_reg->reg_num == RegIP)
8731 return 0;
8732
8733 /* No VEX/EVEX encoding. */
8734 if (is_any_vex_encoding (&i.tm))
8735 return 0;
8736
8737 /* add, sub without add/sub m, imm. */
8738 if (i.tm.base_opcode <= 5
8739 || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
8740 || ((i.tm.base_opcode | 3) == 0x83
8741 && (i.tm.extension_opcode == 0x5
8742 || i.tm.extension_opcode == 0x0)))
8743 {
8744 *mf_cmp_p = mf_cmp_alu_cmp;
8745 return !(i.mem_operands && i.imm_operands);
8746 }
8747
8748 /* and without and m, imm. */
8749 if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
8750 || ((i.tm.base_opcode | 3) == 0x83
8751 && i.tm.extension_opcode == 0x4))
8752 {
8753 *mf_cmp_p = mf_cmp_test_and;
8754 return !(i.mem_operands && i.imm_operands);
8755 }
8756
8757 /* test without test m imm. */
8758 if ((i.tm.base_opcode | 1) == 0x85
8759 || (i.tm.base_opcode | 1) == 0xa9
8760 || ((i.tm.base_opcode | 1) == 0xf7
8761 && i.tm.extension_opcode == 0))
8762 {
8763 *mf_cmp_p = mf_cmp_test_and;
8764 return !(i.mem_operands && i.imm_operands);
8765 }
8766
8767 /* cmp without cmp m, imm. */
8768 if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
8769 || ((i.tm.base_opcode | 3) == 0x83
8770 && (i.tm.extension_opcode == 0x7)))
8771 {
8772 *mf_cmp_p = mf_cmp_alu_cmp;
8773 return !(i.mem_operands && i.imm_operands);
8774 }
8775
8776 /* inc, dec without inc/dec m. */
8777 if ((i.tm.cpu_flags.bitfield.cpuno64
8778 && (i.tm.base_opcode | 0xf) == 0x4f)
8779 || ((i.tm.base_opcode | 1) == 0xff
8780 && i.tm.extension_opcode <= 0x1))
8781 {
8782 *mf_cmp_p = mf_cmp_incdec;
8783 return !i.mem_operands;
8784 }
8785
8786 return 0;
8787 }
8788
8789 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8790
8791 static int
8792 add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p)
8793 {
8794 /* NB: Don't work with COND_JUMP86 without i386. */
8795 if (!align_branch_power
8796 || now_seg == absolute_section
8797 || !cpu_arch_flags.bitfield.cpui386
8798 || !(align_branch & align_branch_fused_bit))
8799 return 0;
8800
8801 if (maybe_fused_with_jcc_p (mf_cmp_p))
8802 {
8803 if (last_insn.kind == last_insn_other
8804 || last_insn.seg != now_seg)
8805 return 1;
8806 if (flag_debug)
8807 as_warn_where (last_insn.file, last_insn.line,
8808 _("`%s` skips -malign-branch-boundary on `%s`"),
8809 last_insn.name, i.tm.name);
8810 }
8811
8812 return 0;
8813 }
8814
8815 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8816
8817 static int
8818 add_branch_prefix_frag_p (void)
8819 {
8820 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8821 to PadLock instructions since they include prefixes in opcode. */
8822 if (!align_branch_power
8823 || !align_branch_prefix_size
8824 || now_seg == absolute_section
8825 || i.tm.cpu_flags.bitfield.cpupadlock
8826 || !cpu_arch_flags.bitfield.cpui386)
8827 return 0;
8828
8829 /* Don't add prefix if it is a prefix or there is no operand in case
8830 that segment prefix is special. */
8831 if (!i.operands || i.tm.opcode_modifier.isprefix)
8832 return 0;
8833
8834 if (last_insn.kind == last_insn_other
8835 || last_insn.seg != now_seg)
8836 return 1;
8837
8838 if (flag_debug)
8839 as_warn_where (last_insn.file, last_insn.line,
8840 _("`%s` skips -malign-branch-boundary on `%s`"),
8841 last_insn.name, i.tm.name);
8842
8843 return 0;
8844 }
8845
8846 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8847
8848 static int
8849 add_branch_padding_frag_p (enum align_branch_kind *branch_p,
8850 enum mf_jcc_kind *mf_jcc_p)
8851 {
8852 int add_padding;
8853
8854 /* NB: Don't work with COND_JUMP86 without i386. */
8855 if (!align_branch_power
8856 || now_seg == absolute_section
8857 || !cpu_arch_flags.bitfield.cpui386)
8858 return 0;
8859
8860 add_padding = 0;
8861
8862 /* Check for jcc and direct jmp. */
8863 if (i.tm.opcode_modifier.jump == JUMP)
8864 {
8865 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
8866 {
8867 *branch_p = align_branch_jmp;
8868 add_padding = align_branch & align_branch_jmp_bit;
8869 }
8870 else
8871 {
8872 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8873 igore the lowest bit. */
8874 *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
8875 *branch_p = align_branch_jcc;
8876 if ((align_branch & align_branch_jcc_bit))
8877 add_padding = 1;
8878 }
8879 }
8880 else if (is_any_vex_encoding (&i.tm))
8881 return 0;
8882 else if ((i.tm.base_opcode | 1) == 0xc3)
8883 {
8884 /* Near ret. */
8885 *branch_p = align_branch_ret;
8886 if ((align_branch & align_branch_ret_bit))
8887 add_padding = 1;
8888 }
8889 else
8890 {
8891 /* Check for indirect jmp, direct and indirect calls. */
8892 if (i.tm.base_opcode == 0xe8)
8893 {
8894 /* Direct call. */
8895 *branch_p = align_branch_call;
8896 if ((align_branch & align_branch_call_bit))
8897 add_padding = 1;
8898 }
8899 else if (i.tm.base_opcode == 0xff
8900 && (i.tm.extension_opcode == 2
8901 || i.tm.extension_opcode == 4))
8902 {
8903 /* Indirect call and jmp. */
8904 *branch_p = align_branch_indirect;
8905 if ((align_branch & align_branch_indirect_bit))
8906 add_padding = 1;
8907 }
8908
8909 if (add_padding
8910 && i.disp_operands
8911 && tls_get_addr
8912 && (i.op[0].disps->X_op == O_symbol
8913 || (i.op[0].disps->X_op == O_subtract
8914 && i.op[0].disps->X_op_symbol == GOT_symbol)))
8915 {
8916 symbolS *s = i.op[0].disps->X_add_symbol;
8917 /* No padding to call to global or undefined tls_get_addr. */
8918 if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s))
8919 && strcmp (S_GET_NAME (s), tls_get_addr) == 0)
8920 return 0;
8921 }
8922 }
8923
8924 if (add_padding
8925 && last_insn.kind != last_insn_other
8926 && last_insn.seg == now_seg)
8927 {
8928 if (flag_debug)
8929 as_warn_where (last_insn.file, last_insn.line,
8930 _("`%s` skips -malign-branch-boundary on `%s`"),
8931 last_insn.name, i.tm.name);
8932 return 0;
8933 }
8934
8935 return add_padding;
8936 }
8937
8938 static void
8939 output_insn (void)
8940 {
8941 fragS *insn_start_frag;
8942 offsetT insn_start_off;
8943 fragS *fragP = NULL;
8944 enum align_branch_kind branch = align_branch_none;
8945 /* The initializer is arbitrary just to avoid uninitialized error.
8946 it's actually either assigned in add_branch_padding_frag_p
8947 or never be used. */
8948 enum mf_jcc_kind mf_jcc = mf_jcc_jo;
8949
8950 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8951 if (IS_ELF && x86_used_note)
8952 {
8953 if (i.tm.cpu_flags.bitfield.cpucmov)
8954 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
8955 if (i.tm.cpu_flags.bitfield.cpusse)
8956 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
8957 if (i.tm.cpu_flags.bitfield.cpusse2)
8958 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
8959 if (i.tm.cpu_flags.bitfield.cpusse3)
8960 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
8961 if (i.tm.cpu_flags.bitfield.cpussse3)
8962 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
8963 if (i.tm.cpu_flags.bitfield.cpusse4_1)
8964 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
8965 if (i.tm.cpu_flags.bitfield.cpusse4_2)
8966 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
8967 if (i.tm.cpu_flags.bitfield.cpuavx)
8968 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
8969 if (i.tm.cpu_flags.bitfield.cpuavx2)
8970 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
8971 if (i.tm.cpu_flags.bitfield.cpufma)
8972 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
8973 if (i.tm.cpu_flags.bitfield.cpuavx512f)
8974 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
8975 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
8976 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
8977 if (i.tm.cpu_flags.bitfield.cpuavx512er)
8978 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
8979 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
8980 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
8981 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
8982 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
8983 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
8984 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
8985 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8986 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8987 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8988 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8989 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8990 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8991 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8992 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8993 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8994 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8995 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8996 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8997 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8998 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8999 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
9000 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
9001 if (i.tm.cpu_flags.bitfield.cpuavx512_bf16)
9002 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16;
9003
9004 if (i.tm.cpu_flags.bitfield.cpu8087
9005 || i.tm.cpu_flags.bitfield.cpu287
9006 || i.tm.cpu_flags.bitfield.cpu387
9007 || i.tm.cpu_flags.bitfield.cpu687
9008 || i.tm.cpu_flags.bitfield.cpufisttp)
9009 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
9010 if (i.has_regmmx
9011 || i.tm.base_opcode == 0xf77 /* emms */
9012 || i.tm.base_opcode == 0xf0e /* femms */
9013 || i.tm.base_opcode == 0xf2a /* cvtpi2ps */
9014 || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */)
9015 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
9016 if (i.has_regxmm)
9017 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
9018 if (i.has_regymm)
9019 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
9020 if (i.has_regzmm)
9021 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
9022 if (i.tm.cpu_flags.bitfield.cpufxsr)
9023 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
9024 if (i.tm.cpu_flags.bitfield.cpuxsave)
9025 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
9026 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
9027 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
9028 if (i.tm.cpu_flags.bitfield.cpuxsavec)
9029 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
9030 }
9031 #endif
9032
9033 /* Tie dwarf2 debug info to the address at the start of the insn.
9034 We can't do this after the insn has been output as the current
9035 frag may have been closed off. eg. by frag_var. */
9036 dwarf2_emit_insn (0);
9037
9038 insn_start_frag = frag_now;
9039 insn_start_off = frag_now_fix ();
9040
9041 if (add_branch_padding_frag_p (&branch, &mf_jcc))
9042 {
9043 char *p;
9044 /* Branch can be 8 bytes. Leave some room for prefixes. */
9045 unsigned int max_branch_padding_size = 14;
9046
9047 /* Align section to boundary. */
9048 record_alignment (now_seg, align_branch_power);
9049
9050 /* Make room for padding. */
9051 frag_grow (max_branch_padding_size);
9052
9053 /* Start of the padding. */
9054 p = frag_more (0);
9055
9056 fragP = frag_now;
9057
9058 frag_var (rs_machine_dependent, max_branch_padding_size, 0,
9059 ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
9060 NULL, 0, p);
9061
9062 fragP->tc_frag_data.mf_type = mf_jcc;
9063 fragP->tc_frag_data.branch_type = branch;
9064 fragP->tc_frag_data.max_bytes = max_branch_padding_size;
9065 }
9066
9067 /* Output jumps. */
9068 if (i.tm.opcode_modifier.jump == JUMP)
9069 output_branch ();
9070 else if (i.tm.opcode_modifier.jump == JUMP_BYTE
9071 || i.tm.opcode_modifier.jump == JUMP_DWORD)
9072 output_jump ();
9073 else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT)
9074 output_interseg_jump ();
9075 else
9076 {
9077 /* Output normal instructions here. */
9078 char *p;
9079 unsigned char *q;
9080 unsigned int j;
9081 unsigned int prefix;
9082 enum mf_cmp_kind mf_cmp;
9083
9084 if (avoid_fence
9085 && (i.tm.base_opcode == 0xfaee8
9086 || i.tm.base_opcode == 0xfaef0
9087 || i.tm.base_opcode == 0xfaef8))
9088 {
9089 /* Encode lfence, mfence, and sfence as
9090 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9091 offsetT val = 0x240483f0ULL;
9092 p = frag_more (5);
9093 md_number_to_chars (p, val, 5);
9094 return;
9095 }
9096
9097 /* Some processors fail on LOCK prefix. This options makes
9098 assembler ignore LOCK prefix and serves as a workaround. */
9099 if (omit_lock_prefix)
9100 {
9101 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
9102 return;
9103 i.prefix[LOCK_PREFIX] = 0;
9104 }
9105
9106 if (branch)
9107 /* Skip if this is a branch. */
9108 ;
9109 else if (add_fused_jcc_padding_frag_p (&mf_cmp))
9110 {
9111 /* Make room for padding. */
9112 frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
9113 p = frag_more (0);
9114
9115 fragP = frag_now;
9116
9117 frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0,
9118 ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
9119 NULL, 0, p);
9120
9121 fragP->tc_frag_data.mf_type = mf_cmp;
9122 fragP->tc_frag_data.branch_type = align_branch_fused;
9123 fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
9124 }
9125 else if (add_branch_prefix_frag_p ())
9126 {
9127 unsigned int max_prefix_size = align_branch_prefix_size;
9128
9129 /* Make room for padding. */
9130 frag_grow (max_prefix_size);
9131 p = frag_more (0);
9132
9133 fragP = frag_now;
9134
9135 frag_var (rs_machine_dependent, max_prefix_size, 0,
9136 ENCODE_RELAX_STATE (BRANCH_PREFIX, 0),
9137 NULL, 0, p);
9138
9139 fragP->tc_frag_data.max_bytes = max_prefix_size;
9140 }
9141
9142 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9143 don't need the explicit prefix. */
9144 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
9145 {
9146 switch (i.tm.opcode_length)
9147 {
9148 case 3:
9149 if (i.tm.base_opcode & 0xff000000)
9150 {
9151 prefix = (i.tm.base_opcode >> 24) & 0xff;
9152 if (!i.tm.cpu_flags.bitfield.cpupadlock
9153 || prefix != REPE_PREFIX_OPCODE
9154 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
9155 add_prefix (prefix);
9156 }
9157 break;
9158 case 2:
9159 if ((i.tm.base_opcode & 0xff0000) != 0)
9160 {
9161 prefix = (i.tm.base_opcode >> 16) & 0xff;
9162 add_prefix (prefix);
9163 }
9164 break;
9165 case 1:
9166 break;
9167 case 0:
9168 /* Check for pseudo prefixes. */
9169 as_bad_where (insn_start_frag->fr_file,
9170 insn_start_frag->fr_line,
9171 _("pseudo prefix without instruction"));
9172 return;
9173 default:
9174 abort ();
9175 }
9176
9177 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9178 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9179 R_X86_64_GOTTPOFF relocation so that linker can safely
9180 perform IE->LE optimization. A dummy REX_OPCODE prefix
9181 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9182 relocation for GDesc -> IE/LE optimization. */
9183 if (x86_elf_abi == X86_64_X32_ABI
9184 && i.operands == 2
9185 && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
9186 || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
9187 && i.prefix[REX_PREFIX] == 0)
9188 add_prefix (REX_OPCODE);
9189 #endif
9190
9191 /* The prefix bytes. */
9192 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
9193 if (*q)
9194 FRAG_APPEND_1_CHAR (*q);
9195 }
9196 else
9197 {
9198 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
9199 if (*q)
9200 switch (j)
9201 {
9202 case REX_PREFIX:
9203 /* REX byte is encoded in VEX prefix. */
9204 break;
9205 case SEG_PREFIX:
9206 case ADDR_PREFIX:
9207 FRAG_APPEND_1_CHAR (*q);
9208 break;
9209 default:
9210 /* There should be no other prefixes for instructions
9211 with VEX prefix. */
9212 abort ();
9213 }
9214
9215 /* For EVEX instructions i.vrex should become 0 after
9216 build_evex_prefix. For VEX instructions upper 16 registers
9217 aren't available, so VREX should be 0. */
9218 if (i.vrex)
9219 abort ();
9220 /* Now the VEX prefix. */
9221 p = frag_more (i.vex.length);
9222 for (j = 0; j < i.vex.length; j++)
9223 p[j] = i.vex.bytes[j];
9224 }
9225
9226 /* Now the opcode; be careful about word order here! */
9227 if (i.tm.opcode_length == 1)
9228 {
9229 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
9230 }
9231 else
9232 {
9233 switch (i.tm.opcode_length)
9234 {
9235 case 4:
9236 p = frag_more (4);
9237 *p++ = (i.tm.base_opcode >> 24) & 0xff;
9238 *p++ = (i.tm.base_opcode >> 16) & 0xff;
9239 break;
9240 case 3:
9241 p = frag_more (3);
9242 *p++ = (i.tm.base_opcode >> 16) & 0xff;
9243 break;
9244 case 2:
9245 p = frag_more (2);
9246 break;
9247 default:
9248 abort ();
9249 break;
9250 }
9251
9252 /* Put out high byte first: can't use md_number_to_chars! */
9253 *p++ = (i.tm.base_opcode >> 8) & 0xff;
9254 *p = i.tm.base_opcode & 0xff;
9255 }
9256
9257 /* Now the modrm byte and sib byte (if present). */
9258 if (i.tm.opcode_modifier.modrm)
9259 {
9260 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
9261 | i.rm.reg << 3
9262 | i.rm.mode << 6));
9263 /* If i.rm.regmem == ESP (4)
9264 && i.rm.mode != (Register mode)
9265 && not 16 bit
9266 ==> need second modrm byte. */
9267 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
9268 && i.rm.mode != 3
9269 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
9270 FRAG_APPEND_1_CHAR ((i.sib.base << 0
9271 | i.sib.index << 3
9272 | i.sib.scale << 6));
9273 }
9274
9275 if (i.disp_operands)
9276 output_disp (insn_start_frag, insn_start_off);
9277
9278 if (i.imm_operands)
9279 output_imm (insn_start_frag, insn_start_off);
9280
9281 /*
9282 * frag_now_fix () returning plain abs_section_offset when we're in the
9283 * absolute section, and abs_section_offset not getting updated as data
9284 * gets added to the frag breaks the logic below.
9285 */
9286 if (now_seg != absolute_section)
9287 {
9288 j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
9289 if (j > 15)
9290 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9291 j);
9292 else if (fragP)
9293 {
9294 /* NB: Don't add prefix with GOTPC relocation since
9295 output_disp() above depends on the fixed encoding
9296 length. Can't add prefix with TLS relocation since
9297 it breaks TLS linker optimization. */
9298 unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j;
9299 /* Prefix count on the current instruction. */
9300 unsigned int count = i.vex.length;
9301 unsigned int k;
9302 for (k = 0; k < ARRAY_SIZE (i.prefix); k++)
9303 /* REX byte is encoded in VEX/EVEX prefix. */
9304 if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length))
9305 count++;
9306
9307 /* Count prefixes for extended opcode maps. */
9308 if (!i.vex.length)
9309 switch (i.tm.opcode_length)
9310 {
9311 case 3:
9312 if (((i.tm.base_opcode >> 16) & 0xff) == 0xf)
9313 {
9314 count++;
9315 switch ((i.tm.base_opcode >> 8) & 0xff)
9316 {
9317 case 0x38:
9318 case 0x3a:
9319 count++;
9320 break;
9321 default:
9322 break;
9323 }
9324 }
9325 break;
9326 case 2:
9327 if (((i.tm.base_opcode >> 8) & 0xff) == 0xf)
9328 count++;
9329 break;
9330 case 1:
9331 break;
9332 default:
9333 abort ();
9334 }
9335
9336 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
9337 == BRANCH_PREFIX)
9338 {
9339 /* Set the maximum prefix size in BRANCH_PREFIX
9340 frag. */
9341 if (fragP->tc_frag_data.max_bytes > max)
9342 fragP->tc_frag_data.max_bytes = max;
9343 if (fragP->tc_frag_data.max_bytes > count)
9344 fragP->tc_frag_data.max_bytes -= count;
9345 else
9346 fragP->tc_frag_data.max_bytes = 0;
9347 }
9348 else
9349 {
9350 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9351 frag. */
9352 unsigned int max_prefix_size;
9353 if (align_branch_prefix_size > max)
9354 max_prefix_size = max;
9355 else
9356 max_prefix_size = align_branch_prefix_size;
9357 if (max_prefix_size > count)
9358 fragP->tc_frag_data.max_prefix_length
9359 = max_prefix_size - count;
9360 }
9361
9362 /* Use existing segment prefix if possible. Use CS
9363 segment prefix in 64-bit mode. In 32-bit mode, use SS
9364 segment prefix with ESP/EBP base register and use DS
9365 segment prefix without ESP/EBP base register. */
9366 if (i.prefix[SEG_PREFIX])
9367 fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX];
9368 else if (flag_code == CODE_64BIT)
9369 fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE;
9370 else if (i.base_reg
9371 && (i.base_reg->reg_num == 4
9372 || i.base_reg->reg_num == 5))
9373 fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE;
9374 else
9375 fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE;
9376 }
9377 }
9378 }
9379
9380 /* NB: Don't work with COND_JUMP86 without i386. */
9381 if (align_branch_power
9382 && now_seg != absolute_section
9383 && cpu_arch_flags.bitfield.cpui386)
9384 {
9385 /* Terminate each frag so that we can add prefix and check for
9386 fused jcc. */
9387 frag_wane (frag_now);
9388 frag_new (0);
9389 }
9390
9391 #ifdef DEBUG386
9392 if (flag_debug)
9393 {
9394 pi ("" /*line*/, &i);
9395 }
9396 #endif /* DEBUG386 */
9397 }
9398
9399 /* Return the size of the displacement operand N. */
9400
9401 static int
9402 disp_size (unsigned int n)
9403 {
9404 int size = 4;
9405
9406 if (i.types[n].bitfield.disp64)
9407 size = 8;
9408 else if (i.types[n].bitfield.disp8)
9409 size = 1;
9410 else if (i.types[n].bitfield.disp16)
9411 size = 2;
9412 return size;
9413 }
9414
9415 /* Return the size of the immediate operand N. */
9416
9417 static int
9418 imm_size (unsigned int n)
9419 {
9420 int size = 4;
9421 if (i.types[n].bitfield.imm64)
9422 size = 8;
9423 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
9424 size = 1;
9425 else if (i.types[n].bitfield.imm16)
9426 size = 2;
9427 return size;
9428 }
9429
9430 static void
9431 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
9432 {
9433 char *p;
9434 unsigned int n;
9435
9436 for (n = 0; n < i.operands; n++)
9437 {
9438 if (operand_type_check (i.types[n], disp))
9439 {
9440 if (i.op[n].disps->X_op == O_constant)
9441 {
9442 int size = disp_size (n);
9443 offsetT val = i.op[n].disps->X_add_number;
9444
9445 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
9446 size);
9447 p = frag_more (size);
9448 md_number_to_chars (p, val, size);
9449 }
9450 else
9451 {
9452 enum bfd_reloc_code_real reloc_type;
9453 int size = disp_size (n);
9454 int sign = i.types[n].bitfield.disp32s;
9455 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
9456 fixS *fixP;
9457
9458 /* We can't have 8 bit displacement here. */
9459 gas_assert (!i.types[n].bitfield.disp8);
9460
9461 /* The PC relative address is computed relative
9462 to the instruction boundary, so in case immediate
9463 fields follows, we need to adjust the value. */
9464 if (pcrel && i.imm_operands)
9465 {
9466 unsigned int n1;
9467 int sz = 0;
9468
9469 for (n1 = 0; n1 < i.operands; n1++)
9470 if (operand_type_check (i.types[n1], imm))
9471 {
9472 /* Only one immediate is allowed for PC
9473 relative address. */
9474 gas_assert (sz == 0);
9475 sz = imm_size (n1);
9476 i.op[n].disps->X_add_number -= sz;
9477 }
9478 /* We should find the immediate. */
9479 gas_assert (sz != 0);
9480 }
9481
9482 p = frag_more (size);
9483 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
9484 if (GOT_symbol
9485 && GOT_symbol == i.op[n].disps->X_add_symbol
9486 && (((reloc_type == BFD_RELOC_32
9487 || reloc_type == BFD_RELOC_X86_64_32S
9488 || (reloc_type == BFD_RELOC_64
9489 && object_64bit))
9490 && (i.op[n].disps->X_op == O_symbol
9491 || (i.op[n].disps->X_op == O_add
9492 && ((symbol_get_value_expression
9493 (i.op[n].disps->X_op_symbol)->X_op)
9494 == O_subtract))))
9495 || reloc_type == BFD_RELOC_32_PCREL))
9496 {
9497 if (!object_64bit)
9498 {
9499 reloc_type = BFD_RELOC_386_GOTPC;
9500 i.has_gotpc_tls_reloc = TRUE;
9501 i.op[n].imms->X_add_number +=
9502 encoding_length (insn_start_frag, insn_start_off, p);
9503 }
9504 else if (reloc_type == BFD_RELOC_64)
9505 reloc_type = BFD_RELOC_X86_64_GOTPC64;
9506 else
9507 /* Don't do the adjustment for x86-64, as there
9508 the pcrel addressing is relative to the _next_
9509 insn, and that is taken care of in other code. */
9510 reloc_type = BFD_RELOC_X86_64_GOTPC32;
9511 }
9512 else if (align_branch_power)
9513 {
9514 switch (reloc_type)
9515 {
9516 case BFD_RELOC_386_TLS_GD:
9517 case BFD_RELOC_386_TLS_LDM:
9518 case BFD_RELOC_386_TLS_IE:
9519 case BFD_RELOC_386_TLS_IE_32:
9520 case BFD_RELOC_386_TLS_GOTIE:
9521 case BFD_RELOC_386_TLS_GOTDESC:
9522 case BFD_RELOC_386_TLS_DESC_CALL:
9523 case BFD_RELOC_X86_64_TLSGD:
9524 case BFD_RELOC_X86_64_TLSLD:
9525 case BFD_RELOC_X86_64_GOTTPOFF:
9526 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9527 case BFD_RELOC_X86_64_TLSDESC_CALL:
9528 i.has_gotpc_tls_reloc = TRUE;
9529 default:
9530 break;
9531 }
9532 }
9533 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
9534 size, i.op[n].disps, pcrel,
9535 reloc_type);
9536 /* Check for "call/jmp *mem", "mov mem, %reg",
9537 "test %reg, mem" and "binop mem, %reg" where binop
9538 is one of adc, add, and, cmp, or, sbb, sub, xor
9539 instructions without data prefix. Always generate
9540 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9541 if (i.prefix[DATA_PREFIX] == 0
9542 && (generate_relax_relocations
9543 || (!object_64bit
9544 && i.rm.mode == 0
9545 && i.rm.regmem == 5))
9546 && (i.rm.mode == 2
9547 || (i.rm.mode == 0 && i.rm.regmem == 5))
9548 && !is_any_vex_encoding(&i.tm)
9549 && ((i.operands == 1
9550 && i.tm.base_opcode == 0xff
9551 && (i.rm.reg == 2 || i.rm.reg == 4))
9552 || (i.operands == 2
9553 && (i.tm.base_opcode == 0x8b
9554 || i.tm.base_opcode == 0x85
9555 || (i.tm.base_opcode & ~0x38) == 0x03))))
9556 {
9557 if (object_64bit)
9558 {
9559 fixP->fx_tcbit = i.rex != 0;
9560 if (i.base_reg
9561 && (i.base_reg->reg_num == RegIP))
9562 fixP->fx_tcbit2 = 1;
9563 }
9564 else
9565 fixP->fx_tcbit2 = 1;
9566 }
9567 }
9568 }
9569 }
9570 }
9571
9572 static void
9573 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
9574 {
9575 char *p;
9576 unsigned int n;
9577
9578 for (n = 0; n < i.operands; n++)
9579 {
9580 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9581 if (i.rounding && (int) n == i.rounding->operand)
9582 continue;
9583
9584 if (operand_type_check (i.types[n], imm))
9585 {
9586 if (i.op[n].imms->X_op == O_constant)
9587 {
9588 int size = imm_size (n);
9589 offsetT val;
9590
9591 val = offset_in_range (i.op[n].imms->X_add_number,
9592 size);
9593 p = frag_more (size);
9594 md_number_to_chars (p, val, size);
9595 }
9596 else
9597 {
9598 /* Not absolute_section.
9599 Need a 32-bit fixup (don't support 8bit
9600 non-absolute imms). Try to support other
9601 sizes ... */
9602 enum bfd_reloc_code_real reloc_type;
9603 int size = imm_size (n);
9604 int sign;
9605
9606 if (i.types[n].bitfield.imm32s
9607 && (i.suffix == QWORD_MNEM_SUFFIX
9608 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
9609 sign = 1;
9610 else
9611 sign = 0;
9612
9613 p = frag_more (size);
9614 reloc_type = reloc (size, 0, sign, i.reloc[n]);
9615
9616 /* This is tough to explain. We end up with this one if we
9617 * have operands that look like
9618 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9619 * obtain the absolute address of the GOT, and it is strongly
9620 * preferable from a performance point of view to avoid using
9621 * a runtime relocation for this. The actual sequence of
9622 * instructions often look something like:
9623 *
9624 * call .L66
9625 * .L66:
9626 * popl %ebx
9627 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9628 *
9629 * The call and pop essentially return the absolute address
9630 * of the label .L66 and store it in %ebx. The linker itself
9631 * will ultimately change the first operand of the addl so
9632 * that %ebx points to the GOT, but to keep things simple, the
9633 * .o file must have this operand set so that it generates not
9634 * the absolute address of .L66, but the absolute address of
9635 * itself. This allows the linker itself simply treat a GOTPC
9636 * relocation as asking for a pcrel offset to the GOT to be
9637 * added in, and the addend of the relocation is stored in the
9638 * operand field for the instruction itself.
9639 *
9640 * Our job here is to fix the operand so that it would add
9641 * the correct offset so that %ebx would point to itself. The
9642 * thing that is tricky is that .-.L66 will point to the
9643 * beginning of the instruction, so we need to further modify
9644 * the operand so that it will point to itself. There are
9645 * other cases where you have something like:
9646 *
9647 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9648 *
9649 * and here no correction would be required. Internally in
9650 * the assembler we treat operands of this form as not being
9651 * pcrel since the '.' is explicitly mentioned, and I wonder
9652 * whether it would simplify matters to do it this way. Who
9653 * knows. In earlier versions of the PIC patches, the
9654 * pcrel_adjust field was used to store the correction, but
9655 * since the expression is not pcrel, I felt it would be
9656 * confusing to do it this way. */
9657
9658 if ((reloc_type == BFD_RELOC_32
9659 || reloc_type == BFD_RELOC_X86_64_32S
9660 || reloc_type == BFD_RELOC_64)
9661 && GOT_symbol
9662 && GOT_symbol == i.op[n].imms->X_add_symbol
9663 && (i.op[n].imms->X_op == O_symbol
9664 || (i.op[n].imms->X_op == O_add
9665 && ((symbol_get_value_expression
9666 (i.op[n].imms->X_op_symbol)->X_op)
9667 == O_subtract))))
9668 {
9669 if (!object_64bit)
9670 reloc_type = BFD_RELOC_386_GOTPC;
9671 else if (size == 4)
9672 reloc_type = BFD_RELOC_X86_64_GOTPC32;
9673 else if (size == 8)
9674 reloc_type = BFD_RELOC_X86_64_GOTPC64;
9675 i.has_gotpc_tls_reloc = TRUE;
9676 i.op[n].imms->X_add_number +=
9677 encoding_length (insn_start_frag, insn_start_off, p);
9678 }
9679 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
9680 i.op[n].imms, 0, reloc_type);
9681 }
9682 }
9683 }
9684 }
9685 \f
9686 /* x86_cons_fix_new is called via the expression parsing code when a
9687 reloc is needed. We use this hook to get the correct .got reloc. */
9688 static int cons_sign = -1;
9689
9690 void
9691 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
9692 expressionS *exp, bfd_reloc_code_real_type r)
9693 {
9694 r = reloc (len, 0, cons_sign, r);
9695
9696 #ifdef TE_PE
9697 if (exp->X_op == O_secrel)
9698 {
9699 exp->X_op = O_symbol;
9700 r = BFD_RELOC_32_SECREL;
9701 }
9702 #endif
9703
9704 fix_new_exp (frag, off, len, exp, 0, r);
9705 }
9706
9707 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9708 purpose of the `.dc.a' internal pseudo-op. */
9709
9710 int
9711 x86_address_bytes (void)
9712 {
9713 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
9714 return 4;
9715 return stdoutput->arch_info->bits_per_address / 8;
9716 }
9717
9718 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9719 || defined (LEX_AT)
9720 # define lex_got(reloc, adjust, types) NULL
9721 #else
9722 /* Parse operands of the form
9723 <symbol>@GOTOFF+<nnn>
9724 and similar .plt or .got references.
9725
9726 If we find one, set up the correct relocation in RELOC and copy the
9727 input string, minus the `@GOTOFF' into a malloc'd buffer for
9728 parsing by the calling routine. Return this buffer, and if ADJUST
9729 is non-null set it to the length of the string we removed from the
9730 input line. Otherwise return NULL. */
9731 static char *
9732 lex_got (enum bfd_reloc_code_real *rel,
9733 int *adjust,
9734 i386_operand_type *types)
9735 {
9736 /* Some of the relocations depend on the size of what field is to
9737 be relocated. But in our callers i386_immediate and i386_displacement
9738 we don't yet know the operand size (this will be set by insn
9739 matching). Hence we record the word32 relocation here,
9740 and adjust the reloc according to the real size in reloc(). */
9741 static const struct {
9742 const char *str;
9743 int len;
9744 const enum bfd_reloc_code_real rel[2];
9745 const i386_operand_type types64;
9746 } gotrel[] = {
9747 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9748 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
9749 BFD_RELOC_SIZE32 },
9750 OPERAND_TYPE_IMM32_64 },
9751 #endif
9752 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
9753 BFD_RELOC_X86_64_PLTOFF64 },
9754 OPERAND_TYPE_IMM64 },
9755 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
9756 BFD_RELOC_X86_64_PLT32 },
9757 OPERAND_TYPE_IMM32_32S_DISP32 },
9758 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
9759 BFD_RELOC_X86_64_GOTPLT64 },
9760 OPERAND_TYPE_IMM64_DISP64 },
9761 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
9762 BFD_RELOC_X86_64_GOTOFF64 },
9763 OPERAND_TYPE_IMM64_DISP64 },
9764 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
9765 BFD_RELOC_X86_64_GOTPCREL },
9766 OPERAND_TYPE_IMM32_32S_DISP32 },
9767 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
9768 BFD_RELOC_X86_64_TLSGD },
9769 OPERAND_TYPE_IMM32_32S_DISP32 },
9770 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
9771 _dummy_first_bfd_reloc_code_real },
9772 OPERAND_TYPE_NONE },
9773 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
9774 BFD_RELOC_X86_64_TLSLD },
9775 OPERAND_TYPE_IMM32_32S_DISP32 },
9776 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
9777 BFD_RELOC_X86_64_GOTTPOFF },
9778 OPERAND_TYPE_IMM32_32S_DISP32 },
9779 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
9780 BFD_RELOC_X86_64_TPOFF32 },
9781 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9782 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
9783 _dummy_first_bfd_reloc_code_real },
9784 OPERAND_TYPE_NONE },
9785 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
9786 BFD_RELOC_X86_64_DTPOFF32 },
9787 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9788 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
9789 _dummy_first_bfd_reloc_code_real },
9790 OPERAND_TYPE_NONE },
9791 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
9792 _dummy_first_bfd_reloc_code_real },
9793 OPERAND_TYPE_NONE },
9794 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
9795 BFD_RELOC_X86_64_GOT32 },
9796 OPERAND_TYPE_IMM32_32S_64_DISP32 },
9797 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
9798 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
9799 OPERAND_TYPE_IMM32_32S_DISP32 },
9800 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
9801 BFD_RELOC_X86_64_TLSDESC_CALL },
9802 OPERAND_TYPE_IMM32_32S_DISP32 },
9803 };
9804 char *cp;
9805 unsigned int j;
9806
9807 #if defined (OBJ_MAYBE_ELF)
9808 if (!IS_ELF)
9809 return NULL;
9810 #endif
9811
9812 for (cp = input_line_pointer; *cp != '@'; cp++)
9813 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
9814 return NULL;
9815
9816 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
9817 {
9818 int len = gotrel[j].len;
9819 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
9820 {
9821 if (gotrel[j].rel[object_64bit] != 0)
9822 {
9823 int first, second;
9824 char *tmpbuf, *past_reloc;
9825
9826 *rel = gotrel[j].rel[object_64bit];
9827
9828 if (types)
9829 {
9830 if (flag_code != CODE_64BIT)
9831 {
9832 types->bitfield.imm32 = 1;
9833 types->bitfield.disp32 = 1;
9834 }
9835 else
9836 *types = gotrel[j].types64;
9837 }
9838
9839 if (j != 0 && GOT_symbol == NULL)
9840 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
9841
9842 /* The length of the first part of our input line. */
9843 first = cp - input_line_pointer;
9844
9845 /* The second part goes from after the reloc token until
9846 (and including) an end_of_line char or comma. */
9847 past_reloc = cp + 1 + len;
9848 cp = past_reloc;
9849 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
9850 ++cp;
9851 second = cp + 1 - past_reloc;
9852
9853 /* Allocate and copy string. The trailing NUL shouldn't
9854 be necessary, but be safe. */
9855 tmpbuf = XNEWVEC (char, first + second + 2);
9856 memcpy (tmpbuf, input_line_pointer, first);
9857 if (second != 0 && *past_reloc != ' ')
9858 /* Replace the relocation token with ' ', so that
9859 errors like foo@GOTOFF1 will be detected. */
9860 tmpbuf[first++] = ' ';
9861 else
9862 /* Increment length by 1 if the relocation token is
9863 removed. */
9864 len++;
9865 if (adjust)
9866 *adjust = len;
9867 memcpy (tmpbuf + first, past_reloc, second);
9868 tmpbuf[first + second] = '\0';
9869 return tmpbuf;
9870 }
9871
9872 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9873 gotrel[j].str, 1 << (5 + object_64bit));
9874 return NULL;
9875 }
9876 }
9877
9878 /* Might be a symbol version string. Don't as_bad here. */
9879 return NULL;
9880 }
9881 #endif
9882
9883 #ifdef TE_PE
9884 #ifdef lex_got
9885 #undef lex_got
9886 #endif
9887 /* Parse operands of the form
9888 <symbol>@SECREL32+<nnn>
9889
9890 If we find one, set up the correct relocation in RELOC and copy the
9891 input string, minus the `@SECREL32' into a malloc'd buffer for
9892 parsing by the calling routine. Return this buffer, and if ADJUST
9893 is non-null set it to the length of the string we removed from the
9894 input line. Otherwise return NULL.
9895
9896 This function is copied from the ELF version above adjusted for PE targets. */
9897
9898 static char *
9899 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
9900 int *adjust ATTRIBUTE_UNUSED,
9901 i386_operand_type *types)
9902 {
9903 static const struct
9904 {
9905 const char *str;
9906 int len;
9907 const enum bfd_reloc_code_real rel[2];
9908 const i386_operand_type types64;
9909 }
9910 gotrel[] =
9911 {
9912 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
9913 BFD_RELOC_32_SECREL },
9914 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9915 };
9916
9917 char *cp;
9918 unsigned j;
9919
9920 for (cp = input_line_pointer; *cp != '@'; cp++)
9921 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
9922 return NULL;
9923
9924 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
9925 {
9926 int len = gotrel[j].len;
9927
9928 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
9929 {
9930 if (gotrel[j].rel[object_64bit] != 0)
9931 {
9932 int first, second;
9933 char *tmpbuf, *past_reloc;
9934
9935 *rel = gotrel[j].rel[object_64bit];
9936 if (adjust)
9937 *adjust = len;
9938
9939 if (types)
9940 {
9941 if (flag_code != CODE_64BIT)
9942 {
9943 types->bitfield.imm32 = 1;
9944 types->bitfield.disp32 = 1;
9945 }
9946 else
9947 *types = gotrel[j].types64;
9948 }
9949
9950 /* The length of the first part of our input line. */
9951 first = cp - input_line_pointer;
9952
9953 /* The second part goes from after the reloc token until
9954 (and including) an end_of_line char or comma. */
9955 past_reloc = cp + 1 + len;
9956 cp = past_reloc;
9957 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
9958 ++cp;
9959 second = cp + 1 - past_reloc;
9960
9961 /* Allocate and copy string. The trailing NUL shouldn't
9962 be necessary, but be safe. */
9963 tmpbuf = XNEWVEC (char, first + second + 2);
9964 memcpy (tmpbuf, input_line_pointer, first);
9965 if (second != 0 && *past_reloc != ' ')
9966 /* Replace the relocation token with ' ', so that
9967 errors like foo@SECLREL321 will be detected. */
9968 tmpbuf[first++] = ' ';
9969 memcpy (tmpbuf + first, past_reloc, second);
9970 tmpbuf[first + second] = '\0';
9971 return tmpbuf;
9972 }
9973
9974 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9975 gotrel[j].str, 1 << (5 + object_64bit));
9976 return NULL;
9977 }
9978 }
9979
9980 /* Might be a symbol version string. Don't as_bad here. */
9981 return NULL;
9982 }
9983
9984 #endif /* TE_PE */
9985
9986 bfd_reloc_code_real_type
9987 x86_cons (expressionS *exp, int size)
9988 {
9989 bfd_reloc_code_real_type got_reloc = NO_RELOC;
9990
9991 intel_syntax = -intel_syntax;
9992
9993 exp->X_md = 0;
9994 if (size == 4 || (object_64bit && size == 8))
9995 {
9996 /* Handle @GOTOFF and the like in an expression. */
9997 char *save;
9998 char *gotfree_input_line;
9999 int adjust = 0;
10000
10001 save = input_line_pointer;
10002 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
10003 if (gotfree_input_line)
10004 input_line_pointer = gotfree_input_line;
10005
10006 expression (exp);
10007
10008 if (gotfree_input_line)
10009 {
10010 /* expression () has merrily parsed up to the end of line,
10011 or a comma - in the wrong buffer. Transfer how far
10012 input_line_pointer has moved to the right buffer. */
10013 input_line_pointer = (save
10014 + (input_line_pointer - gotfree_input_line)
10015 + adjust);
10016 free (gotfree_input_line);
10017 if (exp->X_op == O_constant
10018 || exp->X_op == O_absent
10019 || exp->X_op == O_illegal
10020 || exp->X_op == O_register
10021 || exp->X_op == O_big)
10022 {
10023 char c = *input_line_pointer;
10024 *input_line_pointer = 0;
10025 as_bad (_("missing or invalid expression `%s'"), save);
10026 *input_line_pointer = c;
10027 }
10028 else if ((got_reloc == BFD_RELOC_386_PLT32
10029 || got_reloc == BFD_RELOC_X86_64_PLT32)
10030 && exp->X_op != O_symbol)
10031 {
10032 char c = *input_line_pointer;
10033 *input_line_pointer = 0;
10034 as_bad (_("invalid PLT expression `%s'"), save);
10035 *input_line_pointer = c;
10036 }
10037 }
10038 }
10039 else
10040 expression (exp);
10041
10042 intel_syntax = -intel_syntax;
10043
10044 if (intel_syntax)
10045 i386_intel_simplify (exp);
10046
10047 return got_reloc;
10048 }
10049
10050 static void
10051 signed_cons (int size)
10052 {
10053 if (flag_code == CODE_64BIT)
10054 cons_sign = 1;
10055 cons (size);
10056 cons_sign = -1;
10057 }
10058
10059 #ifdef TE_PE
10060 static void
10061 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
10062 {
10063 expressionS exp;
10064
10065 do
10066 {
10067 expression (&exp);
10068 if (exp.X_op == O_symbol)
10069 exp.X_op = O_secrel;
10070
10071 emit_expr (&exp, 4);
10072 }
10073 while (*input_line_pointer++ == ',');
10074
10075 input_line_pointer--;
10076 demand_empty_rest_of_line ();
10077 }
10078 #endif
10079
10080 /* Handle Vector operations. */
10081
10082 static char *
10083 check_VecOperations (char *op_string, char *op_end)
10084 {
10085 const reg_entry *mask;
10086 const char *saved;
10087 char *end_op;
10088
10089 while (*op_string
10090 && (op_end == NULL || op_string < op_end))
10091 {
10092 saved = op_string;
10093 if (*op_string == '{')
10094 {
10095 op_string++;
10096
10097 /* Check broadcasts. */
10098 if (strncmp (op_string, "1to", 3) == 0)
10099 {
10100 int bcst_type;
10101
10102 if (i.broadcast)
10103 goto duplicated_vec_op;
10104
10105 op_string += 3;
10106 if (*op_string == '8')
10107 bcst_type = 8;
10108 else if (*op_string == '4')
10109 bcst_type = 4;
10110 else if (*op_string == '2')
10111 bcst_type = 2;
10112 else if (*op_string == '1'
10113 && *(op_string+1) == '6')
10114 {
10115 bcst_type = 16;
10116 op_string++;
10117 }
10118 else
10119 {
10120 as_bad (_("Unsupported broadcast: `%s'"), saved);
10121 return NULL;
10122 }
10123 op_string++;
10124
10125 broadcast_op.type = bcst_type;
10126 broadcast_op.operand = this_operand;
10127 broadcast_op.bytes = 0;
10128 i.broadcast = &broadcast_op;
10129 }
10130 /* Check masking operation. */
10131 else if ((mask = parse_register (op_string, &end_op)) != NULL)
10132 {
10133 /* k0 can't be used for write mask. */
10134 if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
10135 {
10136 as_bad (_("`%s%s' can't be used for write mask"),
10137 register_prefix, mask->reg_name);
10138 return NULL;
10139 }
10140
10141 if (!i.mask)
10142 {
10143 mask_op.mask = mask;
10144 mask_op.zeroing = 0;
10145 mask_op.operand = this_operand;
10146 i.mask = &mask_op;
10147 }
10148 else
10149 {
10150 if (i.mask->mask)
10151 goto duplicated_vec_op;
10152
10153 i.mask->mask = mask;
10154
10155 /* Only "{z}" is allowed here. No need to check
10156 zeroing mask explicitly. */
10157 if (i.mask->operand != this_operand)
10158 {
10159 as_bad (_("invalid write mask `%s'"), saved);
10160 return NULL;
10161 }
10162 }
10163
10164 op_string = end_op;
10165 }
10166 /* Check zeroing-flag for masking operation. */
10167 else if (*op_string == 'z')
10168 {
10169 if (!i.mask)
10170 {
10171 mask_op.mask = NULL;
10172 mask_op.zeroing = 1;
10173 mask_op.operand = this_operand;
10174 i.mask = &mask_op;
10175 }
10176 else
10177 {
10178 if (i.mask->zeroing)
10179 {
10180 duplicated_vec_op:
10181 as_bad (_("duplicated `%s'"), saved);
10182 return NULL;
10183 }
10184
10185 i.mask->zeroing = 1;
10186
10187 /* Only "{%k}" is allowed here. No need to check mask
10188 register explicitly. */
10189 if (i.mask->operand != this_operand)
10190 {
10191 as_bad (_("invalid zeroing-masking `%s'"),
10192 saved);
10193 return NULL;
10194 }
10195 }
10196
10197 op_string++;
10198 }
10199 else
10200 goto unknown_vec_op;
10201
10202 if (*op_string != '}')
10203 {
10204 as_bad (_("missing `}' in `%s'"), saved);
10205 return NULL;
10206 }
10207 op_string++;
10208
10209 /* Strip whitespace since the addition of pseudo prefixes
10210 changed how the scrubber treats '{'. */
10211 if (is_space_char (*op_string))
10212 ++op_string;
10213
10214 continue;
10215 }
10216 unknown_vec_op:
10217 /* We don't know this one. */
10218 as_bad (_("unknown vector operation: `%s'"), saved);
10219 return NULL;
10220 }
10221
10222 if (i.mask && i.mask->zeroing && !i.mask->mask)
10223 {
10224 as_bad (_("zeroing-masking only allowed with write mask"));
10225 return NULL;
10226 }
10227
10228 return op_string;
10229 }
10230
10231 static int
10232 i386_immediate (char *imm_start)
10233 {
10234 char *save_input_line_pointer;
10235 char *gotfree_input_line;
10236 segT exp_seg = 0;
10237 expressionS *exp;
10238 i386_operand_type types;
10239
10240 operand_type_set (&types, ~0);
10241
10242 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
10243 {
10244 as_bad (_("at most %d immediate operands are allowed"),
10245 MAX_IMMEDIATE_OPERANDS);
10246 return 0;
10247 }
10248
10249 exp = &im_expressions[i.imm_operands++];
10250 i.op[this_operand].imms = exp;
10251
10252 if (is_space_char (*imm_start))
10253 ++imm_start;
10254
10255 save_input_line_pointer = input_line_pointer;
10256 input_line_pointer = imm_start;
10257
10258 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
10259 if (gotfree_input_line)
10260 input_line_pointer = gotfree_input_line;
10261
10262 exp_seg = expression (exp);
10263
10264 SKIP_WHITESPACE ();
10265
10266 /* Handle vector operations. */
10267 if (*input_line_pointer == '{')
10268 {
10269 input_line_pointer = check_VecOperations (input_line_pointer,
10270 NULL);
10271 if (input_line_pointer == NULL)
10272 return 0;
10273 }
10274
10275 if (*input_line_pointer)
10276 as_bad (_("junk `%s' after expression"), input_line_pointer);
10277
10278 input_line_pointer = save_input_line_pointer;
10279 if (gotfree_input_line)
10280 {
10281 free (gotfree_input_line);
10282
10283 if (exp->X_op == O_constant || exp->X_op == O_register)
10284 exp->X_op = O_illegal;
10285 }
10286
10287 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
10288 }
10289
10290 static int
10291 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
10292 i386_operand_type types, const char *imm_start)
10293 {
10294 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
10295 {
10296 if (imm_start)
10297 as_bad (_("missing or invalid immediate expression `%s'"),
10298 imm_start);
10299 return 0;
10300 }
10301 else if (exp->X_op == O_constant)
10302 {
10303 /* Size it properly later. */
10304 i.types[this_operand].bitfield.imm64 = 1;
10305 /* If not 64bit, sign extend val. */
10306 if (flag_code != CODE_64BIT
10307 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
10308 exp->X_add_number
10309 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
10310 }
10311 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10312 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
10313 && exp_seg != absolute_section
10314 && exp_seg != text_section
10315 && exp_seg != data_section
10316 && exp_seg != bss_section
10317 && exp_seg != undefined_section
10318 && !bfd_is_com_section (exp_seg))
10319 {
10320 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
10321 return 0;
10322 }
10323 #endif
10324 else if (!intel_syntax && exp_seg == reg_section)
10325 {
10326 if (imm_start)
10327 as_bad (_("illegal immediate register operand %s"), imm_start);
10328 return 0;
10329 }
10330 else
10331 {
10332 /* This is an address. The size of the address will be
10333 determined later, depending on destination register,
10334 suffix, or the default for the section. */
10335 i.types[this_operand].bitfield.imm8 = 1;
10336 i.types[this_operand].bitfield.imm16 = 1;
10337 i.types[this_operand].bitfield.imm32 = 1;
10338 i.types[this_operand].bitfield.imm32s = 1;
10339 i.types[this_operand].bitfield.imm64 = 1;
10340 i.types[this_operand] = operand_type_and (i.types[this_operand],
10341 types);
10342 }
10343
10344 return 1;
10345 }
10346
10347 static char *
10348 i386_scale (char *scale)
10349 {
10350 offsetT val;
10351 char *save = input_line_pointer;
10352
10353 input_line_pointer = scale;
10354 val = get_absolute_expression ();
10355
10356 switch (val)
10357 {
10358 case 1:
10359 i.log2_scale_factor = 0;
10360 break;
10361 case 2:
10362 i.log2_scale_factor = 1;
10363 break;
10364 case 4:
10365 i.log2_scale_factor = 2;
10366 break;
10367 case 8:
10368 i.log2_scale_factor = 3;
10369 break;
10370 default:
10371 {
10372 char sep = *input_line_pointer;
10373
10374 *input_line_pointer = '\0';
10375 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10376 scale);
10377 *input_line_pointer = sep;
10378 input_line_pointer = save;
10379 return NULL;
10380 }
10381 }
10382 if (i.log2_scale_factor != 0 && i.index_reg == 0)
10383 {
10384 as_warn (_("scale factor of %d without an index register"),
10385 1 << i.log2_scale_factor);
10386 i.log2_scale_factor = 0;
10387 }
10388 scale = input_line_pointer;
10389 input_line_pointer = save;
10390 return scale;
10391 }
10392
10393 static int
10394 i386_displacement (char *disp_start, char *disp_end)
10395 {
10396 expressionS *exp;
10397 segT exp_seg = 0;
10398 char *save_input_line_pointer;
10399 char *gotfree_input_line;
10400 int override;
10401 i386_operand_type bigdisp, types = anydisp;
10402 int ret;
10403
10404 if (i.disp_operands == MAX_MEMORY_OPERANDS)
10405 {
10406 as_bad (_("at most %d displacement operands are allowed"),
10407 MAX_MEMORY_OPERANDS);
10408 return 0;
10409 }
10410
10411 operand_type_set (&bigdisp, 0);
10412 if (i.jumpabsolute
10413 || i.types[this_operand].bitfield.baseindex
10414 || (current_templates->start->opcode_modifier.jump != JUMP
10415 && current_templates->start->opcode_modifier.jump != JUMP_DWORD))
10416 {
10417 i386_addressing_mode ();
10418 override = (i.prefix[ADDR_PREFIX] != 0);
10419 if (flag_code == CODE_64BIT)
10420 {
10421 if (!override)
10422 {
10423 bigdisp.bitfield.disp32s = 1;
10424 bigdisp.bitfield.disp64 = 1;
10425 }
10426 else
10427 bigdisp.bitfield.disp32 = 1;
10428 }
10429 else if ((flag_code == CODE_16BIT) ^ override)
10430 bigdisp.bitfield.disp16 = 1;
10431 else
10432 bigdisp.bitfield.disp32 = 1;
10433 }
10434 else
10435 {
10436 /* For PC-relative branches, the width of the displacement may be
10437 dependent upon data size, but is never dependent upon address size.
10438 Also make sure to not unintentionally match against a non-PC-relative
10439 branch template. */
10440 static templates aux_templates;
10441 const insn_template *t = current_templates->start;
10442 bfd_boolean has_intel64 = FALSE;
10443
10444 aux_templates.start = t;
10445 while (++t < current_templates->end)
10446 {
10447 if (t->opcode_modifier.jump
10448 != current_templates->start->opcode_modifier.jump)
10449 break;
10450 if ((t->opcode_modifier.isa64 >= INTEL64))
10451 has_intel64 = TRUE;
10452 }
10453 if (t < current_templates->end)
10454 {
10455 aux_templates.end = t;
10456 current_templates = &aux_templates;
10457 }
10458
10459 override = (i.prefix[DATA_PREFIX] != 0);
10460 if (flag_code == CODE_64BIT)
10461 {
10462 if ((override || i.suffix == WORD_MNEM_SUFFIX)
10463 && (!intel64 || !has_intel64))
10464 bigdisp.bitfield.disp16 = 1;
10465 else
10466 bigdisp.bitfield.disp32s = 1;
10467 }
10468 else
10469 {
10470 if (!override)
10471 override = (i.suffix == (flag_code != CODE_16BIT
10472 ? WORD_MNEM_SUFFIX
10473 : LONG_MNEM_SUFFIX));
10474 bigdisp.bitfield.disp32 = 1;
10475 if ((flag_code == CODE_16BIT) ^ override)
10476 {
10477 bigdisp.bitfield.disp32 = 0;
10478 bigdisp.bitfield.disp16 = 1;
10479 }
10480 }
10481 }
10482 i.types[this_operand] = operand_type_or (i.types[this_operand],
10483 bigdisp);
10484
10485 exp = &disp_expressions[i.disp_operands];
10486 i.op[this_operand].disps = exp;
10487 i.disp_operands++;
10488 save_input_line_pointer = input_line_pointer;
10489 input_line_pointer = disp_start;
10490 END_STRING_AND_SAVE (disp_end);
10491
10492 #ifndef GCC_ASM_O_HACK
10493 #define GCC_ASM_O_HACK 0
10494 #endif
10495 #if GCC_ASM_O_HACK
10496 END_STRING_AND_SAVE (disp_end + 1);
10497 if (i.types[this_operand].bitfield.baseIndex
10498 && displacement_string_end[-1] == '+')
10499 {
10500 /* This hack is to avoid a warning when using the "o"
10501 constraint within gcc asm statements.
10502 For instance:
10503
10504 #define _set_tssldt_desc(n,addr,limit,type) \
10505 __asm__ __volatile__ ( \
10506 "movw %w2,%0\n\t" \
10507 "movw %w1,2+%0\n\t" \
10508 "rorl $16,%1\n\t" \
10509 "movb %b1,4+%0\n\t" \
10510 "movb %4,5+%0\n\t" \
10511 "movb $0,6+%0\n\t" \
10512 "movb %h1,7+%0\n\t" \
10513 "rorl $16,%1" \
10514 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10515
10516 This works great except that the output assembler ends
10517 up looking a bit weird if it turns out that there is
10518 no offset. You end up producing code that looks like:
10519
10520 #APP
10521 movw $235,(%eax)
10522 movw %dx,2+(%eax)
10523 rorl $16,%edx
10524 movb %dl,4+(%eax)
10525 movb $137,5+(%eax)
10526 movb $0,6+(%eax)
10527 movb %dh,7+(%eax)
10528 rorl $16,%edx
10529 #NO_APP
10530
10531 So here we provide the missing zero. */
10532
10533 *displacement_string_end = '0';
10534 }
10535 #endif
10536 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
10537 if (gotfree_input_line)
10538 input_line_pointer = gotfree_input_line;
10539
10540 exp_seg = expression (exp);
10541
10542 SKIP_WHITESPACE ();
10543 if (*input_line_pointer)
10544 as_bad (_("junk `%s' after expression"), input_line_pointer);
10545 #if GCC_ASM_O_HACK
10546 RESTORE_END_STRING (disp_end + 1);
10547 #endif
10548 input_line_pointer = save_input_line_pointer;
10549 if (gotfree_input_line)
10550 {
10551 free (gotfree_input_line);
10552
10553 if (exp->X_op == O_constant || exp->X_op == O_register)
10554 exp->X_op = O_illegal;
10555 }
10556
10557 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
10558
10559 RESTORE_END_STRING (disp_end);
10560
10561 return ret;
10562 }
10563
10564 static int
10565 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
10566 i386_operand_type types, const char *disp_start)
10567 {
10568 i386_operand_type bigdisp;
10569 int ret = 1;
10570
10571 /* We do this to make sure that the section symbol is in
10572 the symbol table. We will ultimately change the relocation
10573 to be relative to the beginning of the section. */
10574 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
10575 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
10576 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
10577 {
10578 if (exp->X_op != O_symbol)
10579 goto inv_disp;
10580
10581 if (S_IS_LOCAL (exp->X_add_symbol)
10582 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
10583 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
10584 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
10585 exp->X_op = O_subtract;
10586 exp->X_op_symbol = GOT_symbol;
10587 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
10588 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
10589 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
10590 i.reloc[this_operand] = BFD_RELOC_64;
10591 else
10592 i.reloc[this_operand] = BFD_RELOC_32;
10593 }
10594
10595 else if (exp->X_op == O_absent
10596 || exp->X_op == O_illegal
10597 || exp->X_op == O_big)
10598 {
10599 inv_disp:
10600 as_bad (_("missing or invalid displacement expression `%s'"),
10601 disp_start);
10602 ret = 0;
10603 }
10604
10605 else if (flag_code == CODE_64BIT
10606 && !i.prefix[ADDR_PREFIX]
10607 && exp->X_op == O_constant)
10608 {
10609 /* Since displacement is signed extended to 64bit, don't allow
10610 disp32 and turn off disp32s if they are out of range. */
10611 i.types[this_operand].bitfield.disp32 = 0;
10612 if (!fits_in_signed_long (exp->X_add_number))
10613 {
10614 i.types[this_operand].bitfield.disp32s = 0;
10615 if (i.types[this_operand].bitfield.baseindex)
10616 {
10617 as_bad (_("0x%lx out range of signed 32bit displacement"),
10618 (long) exp->X_add_number);
10619 ret = 0;
10620 }
10621 }
10622 }
10623
10624 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10625 else if (exp->X_op != O_constant
10626 && OUTPUT_FLAVOR == bfd_target_aout_flavour
10627 && exp_seg != absolute_section
10628 && exp_seg != text_section
10629 && exp_seg != data_section
10630 && exp_seg != bss_section
10631 && exp_seg != undefined_section
10632 && !bfd_is_com_section (exp_seg))
10633 {
10634 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
10635 ret = 0;
10636 }
10637 #endif
10638
10639 if (current_templates->start->opcode_modifier.jump == JUMP_BYTE
10640 /* Constants get taken care of by optimize_disp(). */
10641 && exp->X_op != O_constant)
10642 i.types[this_operand].bitfield.disp8 = 1;
10643
10644 /* Check if this is a displacement only operand. */
10645 bigdisp = i.types[this_operand];
10646 bigdisp.bitfield.disp8 = 0;
10647 bigdisp.bitfield.disp16 = 0;
10648 bigdisp.bitfield.disp32 = 0;
10649 bigdisp.bitfield.disp32s = 0;
10650 bigdisp.bitfield.disp64 = 0;
10651 if (operand_type_all_zero (&bigdisp))
10652 i.types[this_operand] = operand_type_and (i.types[this_operand],
10653 types);
10654
10655 return ret;
10656 }
10657
10658 /* Return the active addressing mode, taking address override and
10659 registers forming the address into consideration. Update the
10660 address override prefix if necessary. */
10661
10662 static enum flag_code
10663 i386_addressing_mode (void)
10664 {
10665 enum flag_code addr_mode;
10666
10667 if (i.prefix[ADDR_PREFIX])
10668 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
10669 else if (flag_code == CODE_16BIT
10670 && current_templates->start->cpu_flags.bitfield.cpumpx
10671 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10672 from md_assemble() by "is not a valid base/index expression"
10673 when there is a base and/or index. */
10674 && !i.types[this_operand].bitfield.baseindex)
10675 {
10676 /* MPX insn memory operands with neither base nor index must be forced
10677 to use 32-bit addressing in 16-bit mode. */
10678 addr_mode = CODE_32BIT;
10679 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
10680 ++i.prefixes;
10681 gas_assert (!i.types[this_operand].bitfield.disp16);
10682 gas_assert (!i.types[this_operand].bitfield.disp32);
10683 }
10684 else
10685 {
10686 addr_mode = flag_code;
10687
10688 #if INFER_ADDR_PREFIX
10689 if (i.mem_operands == 0)
10690 {
10691 /* Infer address prefix from the first memory operand. */
10692 const reg_entry *addr_reg = i.base_reg;
10693
10694 if (addr_reg == NULL)
10695 addr_reg = i.index_reg;
10696
10697 if (addr_reg)
10698 {
10699 if (addr_reg->reg_type.bitfield.dword)
10700 addr_mode = CODE_32BIT;
10701 else if (flag_code != CODE_64BIT
10702 && addr_reg->reg_type.bitfield.word)
10703 addr_mode = CODE_16BIT;
10704
10705 if (addr_mode != flag_code)
10706 {
10707 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
10708 i.prefixes += 1;
10709 /* Change the size of any displacement too. At most one
10710 of Disp16 or Disp32 is set.
10711 FIXME. There doesn't seem to be any real need for
10712 separate Disp16 and Disp32 flags. The same goes for
10713 Imm16 and Imm32. Removing them would probably clean
10714 up the code quite a lot. */
10715 if (flag_code != CODE_64BIT
10716 && (i.types[this_operand].bitfield.disp16
10717 || i.types[this_operand].bitfield.disp32))
10718 i.types[this_operand]
10719 = operand_type_xor (i.types[this_operand], disp16_32);
10720 }
10721 }
10722 }
10723 #endif
10724 }
10725
10726 return addr_mode;
10727 }
10728
10729 /* Make sure the memory operand we've been dealt is valid.
10730 Return 1 on success, 0 on a failure. */
10731
10732 static int
10733 i386_index_check (const char *operand_string)
10734 {
10735 const char *kind = "base/index";
10736 enum flag_code addr_mode = i386_addressing_mode ();
10737
10738 if (current_templates->start->opcode_modifier.isstring
10739 && !current_templates->start->cpu_flags.bitfield.cpupadlock
10740 && (current_templates->end[-1].opcode_modifier.isstring
10741 || i.mem_operands))
10742 {
10743 /* Memory operands of string insns are special in that they only allow
10744 a single register (rDI, rSI, or rBX) as their memory address. */
10745 const reg_entry *expected_reg;
10746 static const char *di_si[][2] =
10747 {
10748 { "esi", "edi" },
10749 { "si", "di" },
10750 { "rsi", "rdi" }
10751 };
10752 static const char *bx[] = { "ebx", "bx", "rbx" };
10753
10754 kind = "string address";
10755
10756 if (current_templates->start->opcode_modifier.repprefixok)
10757 {
10758 int es_op = current_templates->end[-1].opcode_modifier.isstring
10759 - IS_STRING_ES_OP0;
10760 int op = 0;
10761
10762 if (!current_templates->end[-1].operand_types[0].bitfield.baseindex
10763 || ((!i.mem_operands != !intel_syntax)
10764 && current_templates->end[-1].operand_types[1]
10765 .bitfield.baseindex))
10766 op = 1;
10767 expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]);
10768 }
10769 else
10770 expected_reg = hash_find (reg_hash, bx[addr_mode]);
10771
10772 if (i.base_reg != expected_reg
10773 || i.index_reg
10774 || operand_type_check (i.types[this_operand], disp))
10775 {
10776 /* The second memory operand must have the same size as
10777 the first one. */
10778 if (i.mem_operands
10779 && i.base_reg
10780 && !((addr_mode == CODE_64BIT
10781 && i.base_reg->reg_type.bitfield.qword)
10782 || (addr_mode == CODE_32BIT
10783 ? i.base_reg->reg_type.bitfield.dword
10784 : i.base_reg->reg_type.bitfield.word)))
10785 goto bad_address;
10786
10787 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10788 operand_string,
10789 intel_syntax ? '[' : '(',
10790 register_prefix,
10791 expected_reg->reg_name,
10792 intel_syntax ? ']' : ')');
10793 return 1;
10794 }
10795 else
10796 return 1;
10797
10798 bad_address:
10799 as_bad (_("`%s' is not a valid %s expression"),
10800 operand_string, kind);
10801 return 0;
10802 }
10803 else
10804 {
10805 if (addr_mode != CODE_16BIT)
10806 {
10807 /* 32-bit/64-bit checks. */
10808 if ((i.base_reg
10809 && ((addr_mode == CODE_64BIT
10810 ? !i.base_reg->reg_type.bitfield.qword
10811 : !i.base_reg->reg_type.bitfield.dword)
10812 || (i.index_reg && i.base_reg->reg_num == RegIP)
10813 || i.base_reg->reg_num == RegIZ))
10814 || (i.index_reg
10815 && !i.index_reg->reg_type.bitfield.xmmword
10816 && !i.index_reg->reg_type.bitfield.ymmword
10817 && !i.index_reg->reg_type.bitfield.zmmword
10818 && ((addr_mode == CODE_64BIT
10819 ? !i.index_reg->reg_type.bitfield.qword
10820 : !i.index_reg->reg_type.bitfield.dword)
10821 || !i.index_reg->reg_type.bitfield.baseindex)))
10822 goto bad_address;
10823
10824 /* bndmk, bndldx, and bndstx have special restrictions. */
10825 if (current_templates->start->base_opcode == 0xf30f1b
10826 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
10827 {
10828 /* They cannot use RIP-relative addressing. */
10829 if (i.base_reg && i.base_reg->reg_num == RegIP)
10830 {
10831 as_bad (_("`%s' cannot be used here"), operand_string);
10832 return 0;
10833 }
10834
10835 /* bndldx and bndstx ignore their scale factor. */
10836 if (current_templates->start->base_opcode != 0xf30f1b
10837 && i.log2_scale_factor)
10838 as_warn (_("register scaling is being ignored here"));
10839 }
10840 }
10841 else
10842 {
10843 /* 16-bit checks. */
10844 if ((i.base_reg
10845 && (!i.base_reg->reg_type.bitfield.word
10846 || !i.base_reg->reg_type.bitfield.baseindex))
10847 || (i.index_reg
10848 && (!i.index_reg->reg_type.bitfield.word
10849 || !i.index_reg->reg_type.bitfield.baseindex
10850 || !(i.base_reg
10851 && i.base_reg->reg_num < 6
10852 && i.index_reg->reg_num >= 6
10853 && i.log2_scale_factor == 0))))
10854 goto bad_address;
10855 }
10856 }
10857 return 1;
10858 }
10859
10860 /* Handle vector immediates. */
10861
10862 static int
10863 RC_SAE_immediate (const char *imm_start)
10864 {
10865 unsigned int match_found, j;
10866 const char *pstr = imm_start;
10867 expressionS *exp;
10868
10869 if (*pstr != '{')
10870 return 0;
10871
10872 pstr++;
10873 match_found = 0;
10874 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
10875 {
10876 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
10877 {
10878 if (!i.rounding)
10879 {
10880 rc_op.type = RC_NamesTable[j].type;
10881 rc_op.operand = this_operand;
10882 i.rounding = &rc_op;
10883 }
10884 else
10885 {
10886 as_bad (_("duplicated `%s'"), imm_start);
10887 return 0;
10888 }
10889 pstr += RC_NamesTable[j].len;
10890 match_found = 1;
10891 break;
10892 }
10893 }
10894 if (!match_found)
10895 return 0;
10896
10897 if (*pstr++ != '}')
10898 {
10899 as_bad (_("Missing '}': '%s'"), imm_start);
10900 return 0;
10901 }
10902 /* RC/SAE immediate string should contain nothing more. */;
10903 if (*pstr != 0)
10904 {
10905 as_bad (_("Junk after '}': '%s'"), imm_start);
10906 return 0;
10907 }
10908
10909 exp = &im_expressions[i.imm_operands++];
10910 i.op[this_operand].imms = exp;
10911
10912 exp->X_op = O_constant;
10913 exp->X_add_number = 0;
10914 exp->X_add_symbol = (symbolS *) 0;
10915 exp->X_op_symbol = (symbolS *) 0;
10916
10917 i.types[this_operand].bitfield.imm8 = 1;
10918 return 1;
10919 }
10920
10921 /* Only string instructions can have a second memory operand, so
10922 reduce current_templates to just those if it contains any. */
10923 static int
10924 maybe_adjust_templates (void)
10925 {
10926 const insn_template *t;
10927
10928 gas_assert (i.mem_operands == 1);
10929
10930 for (t = current_templates->start; t < current_templates->end; ++t)
10931 if (t->opcode_modifier.isstring)
10932 break;
10933
10934 if (t < current_templates->end)
10935 {
10936 static templates aux_templates;
10937 bfd_boolean recheck;
10938
10939 aux_templates.start = t;
10940 for (; t < current_templates->end; ++t)
10941 if (!t->opcode_modifier.isstring)
10942 break;
10943 aux_templates.end = t;
10944
10945 /* Determine whether to re-check the first memory operand. */
10946 recheck = (aux_templates.start != current_templates->start
10947 || t != current_templates->end);
10948
10949 current_templates = &aux_templates;
10950
10951 if (recheck)
10952 {
10953 i.mem_operands = 0;
10954 if (i.memop1_string != NULL
10955 && i386_index_check (i.memop1_string) == 0)
10956 return 0;
10957 i.mem_operands = 1;
10958 }
10959 }
10960
10961 return 1;
10962 }
10963
10964 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10965 on error. */
10966
10967 static int
10968 i386_att_operand (char *operand_string)
10969 {
10970 const reg_entry *r;
10971 char *end_op;
10972 char *op_string = operand_string;
10973
10974 if (is_space_char (*op_string))
10975 ++op_string;
10976
10977 /* We check for an absolute prefix (differentiating,
10978 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10979 if (*op_string == ABSOLUTE_PREFIX)
10980 {
10981 ++op_string;
10982 if (is_space_char (*op_string))
10983 ++op_string;
10984 i.jumpabsolute = TRUE;
10985 }
10986
10987 /* Check if operand is a register. */
10988 if ((r = parse_register (op_string, &end_op)) != NULL)
10989 {
10990 i386_operand_type temp;
10991
10992 /* Check for a segment override by searching for ':' after a
10993 segment register. */
10994 op_string = end_op;
10995 if (is_space_char (*op_string))
10996 ++op_string;
10997 if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
10998 {
10999 switch (r->reg_num)
11000 {
11001 case 0:
11002 i.seg[i.mem_operands] = &es;
11003 break;
11004 case 1:
11005 i.seg[i.mem_operands] = &cs;
11006 break;
11007 case 2:
11008 i.seg[i.mem_operands] = &ss;
11009 break;
11010 case 3:
11011 i.seg[i.mem_operands] = &ds;
11012 break;
11013 case 4:
11014 i.seg[i.mem_operands] = &fs;
11015 break;
11016 case 5:
11017 i.seg[i.mem_operands] = &gs;
11018 break;
11019 }
11020
11021 /* Skip the ':' and whitespace. */
11022 ++op_string;
11023 if (is_space_char (*op_string))
11024 ++op_string;
11025
11026 if (!is_digit_char (*op_string)
11027 && !is_identifier_char (*op_string)
11028 && *op_string != '('
11029 && *op_string != ABSOLUTE_PREFIX)
11030 {
11031 as_bad (_("bad memory operand `%s'"), op_string);
11032 return 0;
11033 }
11034 /* Handle case of %es:*foo. */
11035 if (*op_string == ABSOLUTE_PREFIX)
11036 {
11037 ++op_string;
11038 if (is_space_char (*op_string))
11039 ++op_string;
11040 i.jumpabsolute = TRUE;
11041 }
11042 goto do_memory_reference;
11043 }
11044
11045 /* Handle vector operations. */
11046 if (*op_string == '{')
11047 {
11048 op_string = check_VecOperations (op_string, NULL);
11049 if (op_string == NULL)
11050 return 0;
11051 }
11052
11053 if (*op_string)
11054 {
11055 as_bad (_("junk `%s' after register"), op_string);
11056 return 0;
11057 }
11058 temp = r->reg_type;
11059 temp.bitfield.baseindex = 0;
11060 i.types[this_operand] = operand_type_or (i.types[this_operand],
11061 temp);
11062 i.types[this_operand].bitfield.unspecified = 0;
11063 i.op[this_operand].regs = r;
11064 i.reg_operands++;
11065 }
11066 else if (*op_string == REGISTER_PREFIX)
11067 {
11068 as_bad (_("bad register name `%s'"), op_string);
11069 return 0;
11070 }
11071 else if (*op_string == IMMEDIATE_PREFIX)
11072 {
11073 ++op_string;
11074 if (i.jumpabsolute)
11075 {
11076 as_bad (_("immediate operand illegal with absolute jump"));
11077 return 0;
11078 }
11079 if (!i386_immediate (op_string))
11080 return 0;
11081 }
11082 else if (RC_SAE_immediate (operand_string))
11083 {
11084 /* If it is a RC or SAE immediate, do nothing. */
11085 ;
11086 }
11087 else if (is_digit_char (*op_string)
11088 || is_identifier_char (*op_string)
11089 || *op_string == '"'
11090 || *op_string == '(')
11091 {
11092 /* This is a memory reference of some sort. */
11093 char *base_string;
11094
11095 /* Start and end of displacement string expression (if found). */
11096 char *displacement_string_start;
11097 char *displacement_string_end;
11098 char *vop_start;
11099
11100 do_memory_reference:
11101 if (i.mem_operands == 1 && !maybe_adjust_templates ())
11102 return 0;
11103 if ((i.mem_operands == 1
11104 && !current_templates->start->opcode_modifier.isstring)
11105 || i.mem_operands == 2)
11106 {
11107 as_bad (_("too many memory references for `%s'"),
11108 current_templates->start->name);
11109 return 0;
11110 }
11111
11112 /* Check for base index form. We detect the base index form by
11113 looking for an ')' at the end of the operand, searching
11114 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11115 after the '('. */
11116 base_string = op_string + strlen (op_string);
11117
11118 /* Handle vector operations. */
11119 vop_start = strchr (op_string, '{');
11120 if (vop_start && vop_start < base_string)
11121 {
11122 if (check_VecOperations (vop_start, base_string) == NULL)
11123 return 0;
11124 base_string = vop_start;
11125 }
11126
11127 --base_string;
11128 if (is_space_char (*base_string))
11129 --base_string;
11130
11131 /* If we only have a displacement, set-up for it to be parsed later. */
11132 displacement_string_start = op_string;
11133 displacement_string_end = base_string + 1;
11134
11135 if (*base_string == ')')
11136 {
11137 char *temp_string;
11138 unsigned int parens_balanced = 1;
11139 /* We've already checked that the number of left & right ()'s are
11140 equal, so this loop will not be infinite. */
11141 do
11142 {
11143 base_string--;
11144 if (*base_string == ')')
11145 parens_balanced++;
11146 if (*base_string == '(')
11147 parens_balanced--;
11148 }
11149 while (parens_balanced);
11150
11151 temp_string = base_string;
11152
11153 /* Skip past '(' and whitespace. */
11154 ++base_string;
11155 if (is_space_char (*base_string))
11156 ++base_string;
11157
11158 if (*base_string == ','
11159 || ((i.base_reg = parse_register (base_string, &end_op))
11160 != NULL))
11161 {
11162 displacement_string_end = temp_string;
11163
11164 i.types[this_operand].bitfield.baseindex = 1;
11165
11166 if (i.base_reg)
11167 {
11168 base_string = end_op;
11169 if (is_space_char (*base_string))
11170 ++base_string;
11171 }
11172
11173 /* There may be an index reg or scale factor here. */
11174 if (*base_string == ',')
11175 {
11176 ++base_string;
11177 if (is_space_char (*base_string))
11178 ++base_string;
11179
11180 if ((i.index_reg = parse_register (base_string, &end_op))
11181 != NULL)
11182 {
11183 base_string = end_op;
11184 if (is_space_char (*base_string))
11185 ++base_string;
11186 if (*base_string == ',')
11187 {
11188 ++base_string;
11189 if (is_space_char (*base_string))
11190 ++base_string;
11191 }
11192 else if (*base_string != ')')
11193 {
11194 as_bad (_("expecting `,' or `)' "
11195 "after index register in `%s'"),
11196 operand_string);
11197 return 0;
11198 }
11199 }
11200 else if (*base_string == REGISTER_PREFIX)
11201 {
11202 end_op = strchr (base_string, ',');
11203 if (end_op)
11204 *end_op = '\0';
11205 as_bad (_("bad register name `%s'"), base_string);
11206 return 0;
11207 }
11208
11209 /* Check for scale factor. */
11210 if (*base_string != ')')
11211 {
11212 char *end_scale = i386_scale (base_string);
11213
11214 if (!end_scale)
11215 return 0;
11216
11217 base_string = end_scale;
11218 if (is_space_char (*base_string))
11219 ++base_string;
11220 if (*base_string != ')')
11221 {
11222 as_bad (_("expecting `)' "
11223 "after scale factor in `%s'"),
11224 operand_string);
11225 return 0;
11226 }
11227 }
11228 else if (!i.index_reg)
11229 {
11230 as_bad (_("expecting index register or scale factor "
11231 "after `,'; got '%c'"),
11232 *base_string);
11233 return 0;
11234 }
11235 }
11236 else if (*base_string != ')')
11237 {
11238 as_bad (_("expecting `,' or `)' "
11239 "after base register in `%s'"),
11240 operand_string);
11241 return 0;
11242 }
11243 }
11244 else if (*base_string == REGISTER_PREFIX)
11245 {
11246 end_op = strchr (base_string, ',');
11247 if (end_op)
11248 *end_op = '\0';
11249 as_bad (_("bad register name `%s'"), base_string);
11250 return 0;
11251 }
11252 }
11253
11254 /* If there's an expression beginning the operand, parse it,
11255 assuming displacement_string_start and
11256 displacement_string_end are meaningful. */
11257 if (displacement_string_start != displacement_string_end)
11258 {
11259 if (!i386_displacement (displacement_string_start,
11260 displacement_string_end))
11261 return 0;
11262 }
11263
11264 /* Special case for (%dx) while doing input/output op. */
11265 if (i.base_reg
11266 && i.base_reg->reg_type.bitfield.instance == RegD
11267 && i.base_reg->reg_type.bitfield.word
11268 && i.index_reg == 0
11269 && i.log2_scale_factor == 0
11270 && i.seg[i.mem_operands] == 0
11271 && !operand_type_check (i.types[this_operand], disp))
11272 {
11273 i.types[this_operand] = i.base_reg->reg_type;
11274 return 1;
11275 }
11276
11277 if (i386_index_check (operand_string) == 0)
11278 return 0;
11279 i.flags[this_operand] |= Operand_Mem;
11280 if (i.mem_operands == 0)
11281 i.memop1_string = xstrdup (operand_string);
11282 i.mem_operands++;
11283 }
11284 else
11285 {
11286 /* It's not a memory operand; argh! */
11287 as_bad (_("invalid char %s beginning operand %d `%s'"),
11288 output_invalid (*op_string),
11289 this_operand + 1,
11290 op_string);
11291 return 0;
11292 }
11293 return 1; /* Normal return. */
11294 }
11295 \f
11296 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11297 that an rs_machine_dependent frag may reach. */
11298
11299 unsigned int
11300 i386_frag_max_var (fragS *frag)
11301 {
11302 /* The only relaxable frags are for jumps.
11303 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11304 gas_assert (frag->fr_type == rs_machine_dependent);
11305 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
11306 }
11307
11308 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11309 static int
11310 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
11311 {
11312 /* STT_GNU_IFUNC symbol must go through PLT. */
11313 if ((symbol_get_bfdsym (fr_symbol)->flags
11314 & BSF_GNU_INDIRECT_FUNCTION) != 0)
11315 return 0;
11316
11317 if (!S_IS_EXTERNAL (fr_symbol))
11318 /* Symbol may be weak or local. */
11319 return !S_IS_WEAK (fr_symbol);
11320
11321 /* Global symbols with non-default visibility can't be preempted. */
11322 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
11323 return 1;
11324
11325 if (fr_var != NO_RELOC)
11326 switch ((enum bfd_reloc_code_real) fr_var)
11327 {
11328 case BFD_RELOC_386_PLT32:
11329 case BFD_RELOC_X86_64_PLT32:
11330 /* Symbol with PLT relocation may be preempted. */
11331 return 0;
11332 default:
11333 abort ();
11334 }
11335
11336 /* Global symbols with default visibility in a shared library may be
11337 preempted by another definition. */
11338 return !shared;
11339 }
11340 #endif
11341
11342 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11343 Note also work for Skylake and Cascadelake.
11344 ---------------------------------------------------------------------
11345 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11346 | ------ | ----------- | ------- | -------- |
11347 | Jo | N | N | Y |
11348 | Jno | N | N | Y |
11349 | Jc/Jb | Y | N | Y |
11350 | Jae/Jnb | Y | N | Y |
11351 | Je/Jz | Y | Y | Y |
11352 | Jne/Jnz | Y | Y | Y |
11353 | Jna/Jbe | Y | N | Y |
11354 | Ja/Jnbe | Y | N | Y |
11355 | Js | N | N | Y |
11356 | Jns | N | N | Y |
11357 | Jp/Jpe | N | N | Y |
11358 | Jnp/Jpo | N | N | Y |
11359 | Jl/Jnge | Y | Y | Y |
11360 | Jge/Jnl | Y | Y | Y |
11361 | Jle/Jng | Y | Y | Y |
11362 | Jg/Jnle | Y | Y | Y |
11363 --------------------------------------------------------------------- */
11364 static int
11365 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
11366 {
11367 if (mf_cmp == mf_cmp_alu_cmp)
11368 return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
11369 || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
11370 if (mf_cmp == mf_cmp_incdec)
11371 return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
11372 || mf_jcc == mf_jcc_jle);
11373 if (mf_cmp == mf_cmp_test_and)
11374 return 1;
11375 return 0;
11376 }
11377
11378 /* Return the next non-empty frag. */
11379
11380 static fragS *
11381 i386_next_non_empty_frag (fragS *fragP)
11382 {
11383 /* There may be a frag with a ".fill 0" when there is no room in
11384 the current frag for frag_grow in output_insn. */
11385 for (fragP = fragP->fr_next;
11386 (fragP != NULL
11387 && fragP->fr_type == rs_fill
11388 && fragP->fr_fix == 0);
11389 fragP = fragP->fr_next)
11390 ;
11391 return fragP;
11392 }
11393
11394 /* Return the next jcc frag after BRANCH_PADDING. */
11395
11396 static fragS *
11397 i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
11398 {
11399 fragS *branch_fragP;
11400 if (!pad_fragP)
11401 return NULL;
11402
11403 if (pad_fragP->fr_type == rs_machine_dependent
11404 && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
11405 == BRANCH_PADDING))
11406 {
11407 branch_fragP = i386_next_non_empty_frag (pad_fragP);
11408 if (branch_fragP->fr_type != rs_machine_dependent)
11409 return NULL;
11410 if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
11411 && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
11412 pad_fragP->tc_frag_data.mf_type))
11413 return branch_fragP;
11414 }
11415
11416 return NULL;
11417 }
11418
11419 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11420
11421 static void
11422 i386_classify_machine_dependent_frag (fragS *fragP)
11423 {
11424 fragS *cmp_fragP;
11425 fragS *pad_fragP;
11426 fragS *branch_fragP;
11427 fragS *next_fragP;
11428 unsigned int max_prefix_length;
11429
11430 if (fragP->tc_frag_data.classified)
11431 return;
11432
11433 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11434 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11435 for (next_fragP = fragP;
11436 next_fragP != NULL;
11437 next_fragP = next_fragP->fr_next)
11438 {
11439 next_fragP->tc_frag_data.classified = 1;
11440 if (next_fragP->fr_type == rs_machine_dependent)
11441 switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype))
11442 {
11443 case BRANCH_PADDING:
11444 /* The BRANCH_PADDING frag must be followed by a branch
11445 frag. */
11446 branch_fragP = i386_next_non_empty_frag (next_fragP);
11447 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
11448 break;
11449 case FUSED_JCC_PADDING:
11450 /* Check if this is a fused jcc:
11451 FUSED_JCC_PADDING
11452 CMP like instruction
11453 BRANCH_PADDING
11454 COND_JUMP
11455 */
11456 cmp_fragP = i386_next_non_empty_frag (next_fragP);
11457 pad_fragP = i386_next_non_empty_frag (cmp_fragP);
11458 branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
11459 if (branch_fragP)
11460 {
11461 /* The BRANCH_PADDING frag is merged with the
11462 FUSED_JCC_PADDING frag. */
11463 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
11464 /* CMP like instruction size. */
11465 next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix;
11466 frag_wane (pad_fragP);
11467 /* Skip to branch_fragP. */
11468 next_fragP = branch_fragP;
11469 }
11470 else if (next_fragP->tc_frag_data.max_prefix_length)
11471 {
11472 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11473 a fused jcc. */
11474 next_fragP->fr_subtype
11475 = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0);
11476 next_fragP->tc_frag_data.max_bytes
11477 = next_fragP->tc_frag_data.max_prefix_length;
11478 /* This will be updated in the BRANCH_PREFIX scan. */
11479 next_fragP->tc_frag_data.max_prefix_length = 0;
11480 }
11481 else
11482 frag_wane (next_fragP);
11483 break;
11484 }
11485 }
11486
11487 /* Stop if there is no BRANCH_PREFIX. */
11488 if (!align_branch_prefix_size)
11489 return;
11490
11491 /* Scan for BRANCH_PREFIX. */
11492 for (; fragP != NULL; fragP = fragP->fr_next)
11493 {
11494 if (fragP->fr_type != rs_machine_dependent
11495 || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11496 != BRANCH_PREFIX))
11497 continue;
11498
11499 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11500 COND_JUMP_PREFIX. */
11501 max_prefix_length = 0;
11502 for (next_fragP = fragP;
11503 next_fragP != NULL;
11504 next_fragP = next_fragP->fr_next)
11505 {
11506 if (next_fragP->fr_type == rs_fill)
11507 /* Skip rs_fill frags. */
11508 continue;
11509 else if (next_fragP->fr_type != rs_machine_dependent)
11510 /* Stop for all other frags. */
11511 break;
11512
11513 /* rs_machine_dependent frags. */
11514 if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11515 == BRANCH_PREFIX)
11516 {
11517 /* Count BRANCH_PREFIX frags. */
11518 if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE)
11519 {
11520 max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE;
11521 frag_wane (next_fragP);
11522 }
11523 else
11524 max_prefix_length
11525 += next_fragP->tc_frag_data.max_bytes;
11526 }
11527 else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11528 == BRANCH_PADDING)
11529 || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11530 == FUSED_JCC_PADDING))
11531 {
11532 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11533 fragP->tc_frag_data.u.padding_fragP = next_fragP;
11534 break;
11535 }
11536 else
11537 /* Stop for other rs_machine_dependent frags. */
11538 break;
11539 }
11540
11541 fragP->tc_frag_data.max_prefix_length = max_prefix_length;
11542
11543 /* Skip to the next frag. */
11544 fragP = next_fragP;
11545 }
11546 }
11547
11548 /* Compute padding size for
11549
11550 FUSED_JCC_PADDING
11551 CMP like instruction
11552 BRANCH_PADDING
11553 COND_JUMP/UNCOND_JUMP
11554
11555 or
11556
11557 BRANCH_PADDING
11558 COND_JUMP/UNCOND_JUMP
11559 */
11560
11561 static int
11562 i386_branch_padding_size (fragS *fragP, offsetT address)
11563 {
11564 unsigned int offset, size, padding_size;
11565 fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP;
11566
11567 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11568 if (!address)
11569 address = fragP->fr_address;
11570 address += fragP->fr_fix;
11571
11572 /* CMP like instrunction size. */
11573 size = fragP->tc_frag_data.cmp_size;
11574
11575 /* The base size of the branch frag. */
11576 size += branch_fragP->fr_fix;
11577
11578 /* Add opcode and displacement bytes for the rs_machine_dependent
11579 branch frag. */
11580 if (branch_fragP->fr_type == rs_machine_dependent)
11581 size += md_relax_table[branch_fragP->fr_subtype].rlx_length;
11582
11583 /* Check if branch is within boundary and doesn't end at the last
11584 byte. */
11585 offset = address & ((1U << align_branch_power) - 1);
11586 if ((offset + size) >= (1U << align_branch_power))
11587 /* Padding needed to avoid crossing boundary. */
11588 padding_size = (1U << align_branch_power) - offset;
11589 else
11590 /* No padding needed. */
11591 padding_size = 0;
11592
11593 /* The return value may be saved in tc_frag_data.length which is
11594 unsigned byte. */
11595 if (!fits_in_unsigned_byte (padding_size))
11596 abort ();
11597
11598 return padding_size;
11599 }
11600
11601 /* i386_generic_table_relax_frag()
11602
11603 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11604 grow/shrink padding to align branch frags. Hand others to
11605 relax_frag(). */
11606
11607 long
11608 i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch)
11609 {
11610 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11611 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
11612 {
11613 long padding_size = i386_branch_padding_size (fragP, 0);
11614 long grow = padding_size - fragP->tc_frag_data.length;
11615
11616 /* When the BRANCH_PREFIX frag is used, the computed address
11617 must match the actual address and there should be no padding. */
11618 if (fragP->tc_frag_data.padding_address
11619 && (fragP->tc_frag_data.padding_address != fragP->fr_address
11620 || padding_size))
11621 abort ();
11622
11623 /* Update the padding size. */
11624 if (grow)
11625 fragP->tc_frag_data.length = padding_size;
11626
11627 return grow;
11628 }
11629 else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
11630 {
11631 fragS *padding_fragP, *next_fragP;
11632 long padding_size, left_size, last_size;
11633
11634 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
11635 if (!padding_fragP)
11636 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11637 return (fragP->tc_frag_data.length
11638 - fragP->tc_frag_data.last_length);
11639
11640 /* Compute the relative address of the padding frag in the very
11641 first time where the BRANCH_PREFIX frag sizes are zero. */
11642 if (!fragP->tc_frag_data.padding_address)
11643 fragP->tc_frag_data.padding_address
11644 = padding_fragP->fr_address - (fragP->fr_address - stretch);
11645
11646 /* First update the last length from the previous interation. */
11647 left_size = fragP->tc_frag_data.prefix_length;
11648 for (next_fragP = fragP;
11649 next_fragP != padding_fragP;
11650 next_fragP = next_fragP->fr_next)
11651 if (next_fragP->fr_type == rs_machine_dependent
11652 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11653 == BRANCH_PREFIX))
11654 {
11655 if (left_size)
11656 {
11657 int max = next_fragP->tc_frag_data.max_bytes;
11658 if (max)
11659 {
11660 int size;
11661 if (max > left_size)
11662 size = left_size;
11663 else
11664 size = max;
11665 left_size -= size;
11666 next_fragP->tc_frag_data.last_length = size;
11667 }
11668 }
11669 else
11670 next_fragP->tc_frag_data.last_length = 0;
11671 }
11672
11673 /* Check the padding size for the padding frag. */
11674 padding_size = i386_branch_padding_size
11675 (padding_fragP, (fragP->fr_address
11676 + fragP->tc_frag_data.padding_address));
11677
11678 last_size = fragP->tc_frag_data.prefix_length;
11679 /* Check if there is change from the last interation. */
11680 if (padding_size == last_size)
11681 {
11682 /* Update the expected address of the padding frag. */
11683 padding_fragP->tc_frag_data.padding_address
11684 = (fragP->fr_address + padding_size
11685 + fragP->tc_frag_data.padding_address);
11686 return 0;
11687 }
11688
11689 if (padding_size > fragP->tc_frag_data.max_prefix_length)
11690 {
11691 /* No padding if there is no sufficient room. Clear the
11692 expected address of the padding frag. */
11693 padding_fragP->tc_frag_data.padding_address = 0;
11694 padding_size = 0;
11695 }
11696 else
11697 /* Store the expected address of the padding frag. */
11698 padding_fragP->tc_frag_data.padding_address
11699 = (fragP->fr_address + padding_size
11700 + fragP->tc_frag_data.padding_address);
11701
11702 fragP->tc_frag_data.prefix_length = padding_size;
11703
11704 /* Update the length for the current interation. */
11705 left_size = padding_size;
11706 for (next_fragP = fragP;
11707 next_fragP != padding_fragP;
11708 next_fragP = next_fragP->fr_next)
11709 if (next_fragP->fr_type == rs_machine_dependent
11710 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11711 == BRANCH_PREFIX))
11712 {
11713 if (left_size)
11714 {
11715 int max = next_fragP->tc_frag_data.max_bytes;
11716 if (max)
11717 {
11718 int size;
11719 if (max > left_size)
11720 size = left_size;
11721 else
11722 size = max;
11723 left_size -= size;
11724 next_fragP->tc_frag_data.length = size;
11725 }
11726 }
11727 else
11728 next_fragP->tc_frag_data.length = 0;
11729 }
11730
11731 return (fragP->tc_frag_data.length
11732 - fragP->tc_frag_data.last_length);
11733 }
11734 return relax_frag (segment, fragP, stretch);
11735 }
11736
11737 /* md_estimate_size_before_relax()
11738
11739 Called just before relax() for rs_machine_dependent frags. The x86
11740 assembler uses these frags to handle variable size jump
11741 instructions.
11742
11743 Any symbol that is now undefined will not become defined.
11744 Return the correct fr_subtype in the frag.
11745 Return the initial "guess for variable size of frag" to caller.
11746 The guess is actually the growth beyond the fixed part. Whatever
11747 we do to grow the fixed or variable part contributes to our
11748 returned value. */
11749
11750 int
11751 md_estimate_size_before_relax (fragS *fragP, segT segment)
11752 {
11753 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11754 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX
11755 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
11756 {
11757 i386_classify_machine_dependent_frag (fragP);
11758 return fragP->tc_frag_data.length;
11759 }
11760
11761 /* We've already got fragP->fr_subtype right; all we have to do is
11762 check for un-relaxable symbols. On an ELF system, we can't relax
11763 an externally visible symbol, because it may be overridden by a
11764 shared library. */
11765 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
11766 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11767 || (IS_ELF
11768 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
11769 fragP->fr_var))
11770 #endif
11771 #if defined (OBJ_COFF) && defined (TE_PE)
11772 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
11773 && S_IS_WEAK (fragP->fr_symbol))
11774 #endif
11775 )
11776 {
11777 /* Symbol is undefined in this segment, or we need to keep a
11778 reloc so that weak symbols can be overridden. */
11779 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
11780 enum bfd_reloc_code_real reloc_type;
11781 unsigned char *opcode;
11782 int old_fr_fix;
11783
11784 if (fragP->fr_var != NO_RELOC)
11785 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
11786 else if (size == 2)
11787 reloc_type = BFD_RELOC_16_PCREL;
11788 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11789 else if (need_plt32_p (fragP->fr_symbol))
11790 reloc_type = BFD_RELOC_X86_64_PLT32;
11791 #endif
11792 else
11793 reloc_type = BFD_RELOC_32_PCREL;
11794
11795 old_fr_fix = fragP->fr_fix;
11796 opcode = (unsigned char *) fragP->fr_opcode;
11797
11798 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
11799 {
11800 case UNCOND_JUMP:
11801 /* Make jmp (0xeb) a (d)word displacement jump. */
11802 opcode[0] = 0xe9;
11803 fragP->fr_fix += size;
11804 fix_new (fragP, old_fr_fix, size,
11805 fragP->fr_symbol,
11806 fragP->fr_offset, 1,
11807 reloc_type);
11808 break;
11809
11810 case COND_JUMP86:
11811 if (size == 2
11812 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
11813 {
11814 /* Negate the condition, and branch past an
11815 unconditional jump. */
11816 opcode[0] ^= 1;
11817 opcode[1] = 3;
11818 /* Insert an unconditional jump. */
11819 opcode[2] = 0xe9;
11820 /* We added two extra opcode bytes, and have a two byte
11821 offset. */
11822 fragP->fr_fix += 2 + 2;
11823 fix_new (fragP, old_fr_fix + 2, 2,
11824 fragP->fr_symbol,
11825 fragP->fr_offset, 1,
11826 reloc_type);
11827 break;
11828 }
11829 /* Fall through. */
11830
11831 case COND_JUMP:
11832 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
11833 {
11834 fixS *fixP;
11835
11836 fragP->fr_fix += 1;
11837 fixP = fix_new (fragP, old_fr_fix, 1,
11838 fragP->fr_symbol,
11839 fragP->fr_offset, 1,
11840 BFD_RELOC_8_PCREL);
11841 fixP->fx_signed = 1;
11842 break;
11843 }
11844
11845 /* This changes the byte-displacement jump 0x7N
11846 to the (d)word-displacement jump 0x0f,0x8N. */
11847 opcode[1] = opcode[0] + 0x10;
11848 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
11849 /* We've added an opcode byte. */
11850 fragP->fr_fix += 1 + size;
11851 fix_new (fragP, old_fr_fix + 1, size,
11852 fragP->fr_symbol,
11853 fragP->fr_offset, 1,
11854 reloc_type);
11855 break;
11856
11857 default:
11858 BAD_CASE (fragP->fr_subtype);
11859 break;
11860 }
11861 frag_wane (fragP);
11862 return fragP->fr_fix - old_fr_fix;
11863 }
11864
11865 /* Guess size depending on current relax state. Initially the relax
11866 state will correspond to a short jump and we return 1, because
11867 the variable part of the frag (the branch offset) is one byte
11868 long. However, we can relax a section more than once and in that
11869 case we must either set fr_subtype back to the unrelaxed state,
11870 or return the value for the appropriate branch. */
11871 return md_relax_table[fragP->fr_subtype].rlx_length;
11872 }
11873
11874 /* Called after relax() is finished.
11875
11876 In: Address of frag.
11877 fr_type == rs_machine_dependent.
11878 fr_subtype is what the address relaxed to.
11879
11880 Out: Any fixSs and constants are set up.
11881 Caller will turn frag into a ".space 0". */
11882
11883 void
11884 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
11885 fragS *fragP)
11886 {
11887 unsigned char *opcode;
11888 unsigned char *where_to_put_displacement = NULL;
11889 offsetT target_address;
11890 offsetT opcode_address;
11891 unsigned int extension = 0;
11892 offsetT displacement_from_opcode_start;
11893
11894 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11895 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING
11896 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
11897 {
11898 /* Generate nop padding. */
11899 unsigned int size = fragP->tc_frag_data.length;
11900 if (size)
11901 {
11902 if (size > fragP->tc_frag_data.max_bytes)
11903 abort ();
11904
11905 if (flag_debug)
11906 {
11907 const char *msg;
11908 const char *branch = "branch";
11909 const char *prefix = "";
11910 fragS *padding_fragP;
11911 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11912 == BRANCH_PREFIX)
11913 {
11914 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
11915 switch (fragP->tc_frag_data.default_prefix)
11916 {
11917 default:
11918 abort ();
11919 break;
11920 case CS_PREFIX_OPCODE:
11921 prefix = " cs";
11922 break;
11923 case DS_PREFIX_OPCODE:
11924 prefix = " ds";
11925 break;
11926 case ES_PREFIX_OPCODE:
11927 prefix = " es";
11928 break;
11929 case FS_PREFIX_OPCODE:
11930 prefix = " fs";
11931 break;
11932 case GS_PREFIX_OPCODE:
11933 prefix = " gs";
11934 break;
11935 case SS_PREFIX_OPCODE:
11936 prefix = " ss";
11937 break;
11938 }
11939 if (padding_fragP)
11940 msg = _("%s:%u: add %d%s at 0x%llx to align "
11941 "%s within %d-byte boundary\n");
11942 else
11943 msg = _("%s:%u: add additional %d%s at 0x%llx to "
11944 "align %s within %d-byte boundary\n");
11945 }
11946 else
11947 {
11948 padding_fragP = fragP;
11949 msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11950 "%s within %d-byte boundary\n");
11951 }
11952
11953 if (padding_fragP)
11954 switch (padding_fragP->tc_frag_data.branch_type)
11955 {
11956 case align_branch_jcc:
11957 branch = "jcc";
11958 break;
11959 case align_branch_fused:
11960 branch = "fused jcc";
11961 break;
11962 case align_branch_jmp:
11963 branch = "jmp";
11964 break;
11965 case align_branch_call:
11966 branch = "call";
11967 break;
11968 case align_branch_indirect:
11969 branch = "indiret branch";
11970 break;
11971 case align_branch_ret:
11972 branch = "ret";
11973 break;
11974 default:
11975 break;
11976 }
11977
11978 fprintf (stdout, msg,
11979 fragP->fr_file, fragP->fr_line, size, prefix,
11980 (long long) fragP->fr_address, branch,
11981 1 << align_branch_power);
11982 }
11983 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
11984 memset (fragP->fr_opcode,
11985 fragP->tc_frag_data.default_prefix, size);
11986 else
11987 i386_generate_nops (fragP, (char *) fragP->fr_opcode,
11988 size, 0);
11989 fragP->fr_fix += size;
11990 }
11991 return;
11992 }
11993
11994 opcode = (unsigned char *) fragP->fr_opcode;
11995
11996 /* Address we want to reach in file space. */
11997 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
11998
11999 /* Address opcode resides at in file space. */
12000 opcode_address = fragP->fr_address + fragP->fr_fix;
12001
12002 /* Displacement from opcode start to fill into instruction. */
12003 displacement_from_opcode_start = target_address - opcode_address;
12004
12005 if ((fragP->fr_subtype & BIG) == 0)
12006 {
12007 /* Don't have to change opcode. */
12008 extension = 1; /* 1 opcode + 1 displacement */
12009 where_to_put_displacement = &opcode[1];
12010 }
12011 else
12012 {
12013 if (no_cond_jump_promotion
12014 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
12015 as_warn_where (fragP->fr_file, fragP->fr_line,
12016 _("long jump required"));
12017
12018 switch (fragP->fr_subtype)
12019 {
12020 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
12021 extension = 4; /* 1 opcode + 4 displacement */
12022 opcode[0] = 0xe9;
12023 where_to_put_displacement = &opcode[1];
12024 break;
12025
12026 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
12027 extension = 2; /* 1 opcode + 2 displacement */
12028 opcode[0] = 0xe9;
12029 where_to_put_displacement = &opcode[1];
12030 break;
12031
12032 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
12033 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
12034 extension = 5; /* 2 opcode + 4 displacement */
12035 opcode[1] = opcode[0] + 0x10;
12036 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12037 where_to_put_displacement = &opcode[2];
12038 break;
12039
12040 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
12041 extension = 3; /* 2 opcode + 2 displacement */
12042 opcode[1] = opcode[0] + 0x10;
12043 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12044 where_to_put_displacement = &opcode[2];
12045 break;
12046
12047 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
12048 extension = 4;
12049 opcode[0] ^= 1;
12050 opcode[1] = 3;
12051 opcode[2] = 0xe9;
12052 where_to_put_displacement = &opcode[3];
12053 break;
12054
12055 default:
12056 BAD_CASE (fragP->fr_subtype);
12057 break;
12058 }
12059 }
12060
12061 /* If size if less then four we are sure that the operand fits,
12062 but if it's 4, then it could be that the displacement is larger
12063 then -/+ 2GB. */
12064 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
12065 && object_64bit
12066 && ((addressT) (displacement_from_opcode_start - extension
12067 + ((addressT) 1 << 31))
12068 > (((addressT) 2 << 31) - 1)))
12069 {
12070 as_bad_where (fragP->fr_file, fragP->fr_line,
12071 _("jump target out of range"));
12072 /* Make us emit 0. */
12073 displacement_from_opcode_start = extension;
12074 }
12075 /* Now put displacement after opcode. */
12076 md_number_to_chars ((char *) where_to_put_displacement,
12077 (valueT) (displacement_from_opcode_start - extension),
12078 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
12079 fragP->fr_fix += extension;
12080 }
12081 \f
12082 /* Apply a fixup (fixP) to segment data, once it has been determined
12083 by our caller that we have all the info we need to fix it up.
12084
12085 Parameter valP is the pointer to the value of the bits.
12086
12087 On the 386, immediates, displacements, and data pointers are all in
12088 the same (little-endian) format, so we don't need to care about which
12089 we are handling. */
12090
12091 void
12092 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12093 {
12094 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
12095 valueT value = *valP;
12096
12097 #if !defined (TE_Mach)
12098 if (fixP->fx_pcrel)
12099 {
12100 switch (fixP->fx_r_type)
12101 {
12102 default:
12103 break;
12104
12105 case BFD_RELOC_64:
12106 fixP->fx_r_type = BFD_RELOC_64_PCREL;
12107 break;
12108 case BFD_RELOC_32:
12109 case BFD_RELOC_X86_64_32S:
12110 fixP->fx_r_type = BFD_RELOC_32_PCREL;
12111 break;
12112 case BFD_RELOC_16:
12113 fixP->fx_r_type = BFD_RELOC_16_PCREL;
12114 break;
12115 case BFD_RELOC_8:
12116 fixP->fx_r_type = BFD_RELOC_8_PCREL;
12117 break;
12118 }
12119 }
12120
12121 if (fixP->fx_addsy != NULL
12122 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
12123 || fixP->fx_r_type == BFD_RELOC_64_PCREL
12124 || fixP->fx_r_type == BFD_RELOC_16_PCREL
12125 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
12126 && !use_rela_relocations)
12127 {
12128 /* This is a hack. There should be a better way to handle this.
12129 This covers for the fact that bfd_install_relocation will
12130 subtract the current location (for partial_inplace, PC relative
12131 relocations); see more below. */
12132 #ifndef OBJ_AOUT
12133 if (IS_ELF
12134 #ifdef TE_PE
12135 || OUTPUT_FLAVOR == bfd_target_coff_flavour
12136 #endif
12137 )
12138 value += fixP->fx_where + fixP->fx_frag->fr_address;
12139 #endif
12140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12141 if (IS_ELF)
12142 {
12143 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
12144
12145 if ((sym_seg == seg
12146 || (symbol_section_p (fixP->fx_addsy)
12147 && sym_seg != absolute_section))
12148 && !generic_force_reloc (fixP))
12149 {
12150 /* Yes, we add the values in twice. This is because
12151 bfd_install_relocation subtracts them out again. I think
12152 bfd_install_relocation is broken, but I don't dare change
12153 it. FIXME. */
12154 value += fixP->fx_where + fixP->fx_frag->fr_address;
12155 }
12156 }
12157 #endif
12158 #if defined (OBJ_COFF) && defined (TE_PE)
12159 /* For some reason, the PE format does not store a
12160 section address offset for a PC relative symbol. */
12161 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
12162 || S_IS_WEAK (fixP->fx_addsy))
12163 value += md_pcrel_from (fixP);
12164 #endif
12165 }
12166 #if defined (OBJ_COFF) && defined (TE_PE)
12167 if (fixP->fx_addsy != NULL
12168 && S_IS_WEAK (fixP->fx_addsy)
12169 /* PR 16858: Do not modify weak function references. */
12170 && ! fixP->fx_pcrel)
12171 {
12172 #if !defined (TE_PEP)
12173 /* For x86 PE weak function symbols are neither PC-relative
12174 nor do they set S_IS_FUNCTION. So the only reliable way
12175 to detect them is to check the flags of their containing
12176 section. */
12177 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
12178 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
12179 ;
12180 else
12181 #endif
12182 value -= S_GET_VALUE (fixP->fx_addsy);
12183 }
12184 #endif
12185
12186 /* Fix a few things - the dynamic linker expects certain values here,
12187 and we must not disappoint it. */
12188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12189 if (IS_ELF && fixP->fx_addsy)
12190 switch (fixP->fx_r_type)
12191 {
12192 case BFD_RELOC_386_PLT32:
12193 case BFD_RELOC_X86_64_PLT32:
12194 /* Make the jump instruction point to the address of the operand.
12195 At runtime we merely add the offset to the actual PLT entry.
12196 NB: Subtract the offset size only for jump instructions. */
12197 if (fixP->fx_pcrel)
12198 value = -4;
12199 break;
12200
12201 case BFD_RELOC_386_TLS_GD:
12202 case BFD_RELOC_386_TLS_LDM:
12203 case BFD_RELOC_386_TLS_IE_32:
12204 case BFD_RELOC_386_TLS_IE:
12205 case BFD_RELOC_386_TLS_GOTIE:
12206 case BFD_RELOC_386_TLS_GOTDESC:
12207 case BFD_RELOC_X86_64_TLSGD:
12208 case BFD_RELOC_X86_64_TLSLD:
12209 case BFD_RELOC_X86_64_GOTTPOFF:
12210 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12211 value = 0; /* Fully resolved at runtime. No addend. */
12212 /* Fallthrough */
12213 case BFD_RELOC_386_TLS_LE:
12214 case BFD_RELOC_386_TLS_LDO_32:
12215 case BFD_RELOC_386_TLS_LE_32:
12216 case BFD_RELOC_X86_64_DTPOFF32:
12217 case BFD_RELOC_X86_64_DTPOFF64:
12218 case BFD_RELOC_X86_64_TPOFF32:
12219 case BFD_RELOC_X86_64_TPOFF64:
12220 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12221 break;
12222
12223 case BFD_RELOC_386_TLS_DESC_CALL:
12224 case BFD_RELOC_X86_64_TLSDESC_CALL:
12225 value = 0; /* Fully resolved at runtime. No addend. */
12226 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12227 fixP->fx_done = 0;
12228 return;
12229
12230 case BFD_RELOC_VTABLE_INHERIT:
12231 case BFD_RELOC_VTABLE_ENTRY:
12232 fixP->fx_done = 0;
12233 return;
12234
12235 default:
12236 break;
12237 }
12238 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12239 *valP = value;
12240 #endif /* !defined (TE_Mach) */
12241
12242 /* Are we finished with this relocation now? */
12243 if (fixP->fx_addsy == NULL)
12244 fixP->fx_done = 1;
12245 #if defined (OBJ_COFF) && defined (TE_PE)
12246 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
12247 {
12248 fixP->fx_done = 0;
12249 /* Remember value for tc_gen_reloc. */
12250 fixP->fx_addnumber = value;
12251 /* Clear out the frag for now. */
12252 value = 0;
12253 }
12254 #endif
12255 else if (use_rela_relocations)
12256 {
12257 fixP->fx_no_overflow = 1;
12258 /* Remember value for tc_gen_reloc. */
12259 fixP->fx_addnumber = value;
12260 value = 0;
12261 }
12262
12263 md_number_to_chars (p, value, fixP->fx_size);
12264 }
12265 \f
12266 const char *
12267 md_atof (int type, char *litP, int *sizeP)
12268 {
12269 /* This outputs the LITTLENUMs in REVERSE order;
12270 in accord with the bigendian 386. */
12271 return ieee_md_atof (type, litP, sizeP, FALSE);
12272 }
12273 \f
12274 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
12275
12276 static char *
12277 output_invalid (int c)
12278 {
12279 if (ISPRINT (c))
12280 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
12281 "'%c'", c);
12282 else
12283 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
12284 "(0x%x)", (unsigned char) c);
12285 return output_invalid_buf;
12286 }
12287
12288 /* REG_STRING starts *before* REGISTER_PREFIX. */
12289
12290 static const reg_entry *
12291 parse_real_register (char *reg_string, char **end_op)
12292 {
12293 char *s = reg_string;
12294 char *p;
12295 char reg_name_given[MAX_REG_NAME_SIZE + 1];
12296 const reg_entry *r;
12297
12298 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12299 if (*s == REGISTER_PREFIX)
12300 ++s;
12301
12302 if (is_space_char (*s))
12303 ++s;
12304
12305 p = reg_name_given;
12306 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
12307 {
12308 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
12309 return (const reg_entry *) NULL;
12310 s++;
12311 }
12312
12313 /* For naked regs, make sure that we are not dealing with an identifier.
12314 This prevents confusing an identifier like `eax_var' with register
12315 `eax'. */
12316 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
12317 return (const reg_entry *) NULL;
12318
12319 *end_op = s;
12320
12321 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
12322
12323 /* Handle floating point regs, allowing spaces in the (i) part. */
12324 if (r == i386_regtab /* %st is first entry of table */)
12325 {
12326 if (!cpu_arch_flags.bitfield.cpu8087
12327 && !cpu_arch_flags.bitfield.cpu287
12328 && !cpu_arch_flags.bitfield.cpu387)
12329 return (const reg_entry *) NULL;
12330
12331 if (is_space_char (*s))
12332 ++s;
12333 if (*s == '(')
12334 {
12335 ++s;
12336 if (is_space_char (*s))
12337 ++s;
12338 if (*s >= '0' && *s <= '7')
12339 {
12340 int fpr = *s - '0';
12341 ++s;
12342 if (is_space_char (*s))
12343 ++s;
12344 if (*s == ')')
12345 {
12346 *end_op = s + 1;
12347 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
12348 know (r);
12349 return r + fpr;
12350 }
12351 }
12352 /* We have "%st(" then garbage. */
12353 return (const reg_entry *) NULL;
12354 }
12355 }
12356
12357 if (r == NULL || allow_pseudo_reg)
12358 return r;
12359
12360 if (operand_type_all_zero (&r->reg_type))
12361 return (const reg_entry *) NULL;
12362
12363 if ((r->reg_type.bitfield.dword
12364 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
12365 || r->reg_type.bitfield.class == RegCR
12366 || r->reg_type.bitfield.class == RegDR
12367 || r->reg_type.bitfield.class == RegTR)
12368 && !cpu_arch_flags.bitfield.cpui386)
12369 return (const reg_entry *) NULL;
12370
12371 if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
12372 return (const reg_entry *) NULL;
12373
12374 if (!cpu_arch_flags.bitfield.cpuavx512f)
12375 {
12376 if (r->reg_type.bitfield.zmmword
12377 || r->reg_type.bitfield.class == RegMask)
12378 return (const reg_entry *) NULL;
12379
12380 if (!cpu_arch_flags.bitfield.cpuavx)
12381 {
12382 if (r->reg_type.bitfield.ymmword)
12383 return (const reg_entry *) NULL;
12384
12385 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
12386 return (const reg_entry *) NULL;
12387 }
12388 }
12389
12390 if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
12391 return (const reg_entry *) NULL;
12392
12393 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12394 if (!allow_index_reg && r->reg_num == RegIZ)
12395 return (const reg_entry *) NULL;
12396
12397 /* Upper 16 vector registers are only available with VREX in 64bit
12398 mode, and require EVEX encoding. */
12399 if (r->reg_flags & RegVRex)
12400 {
12401 if (!cpu_arch_flags.bitfield.cpuavx512f
12402 || flag_code != CODE_64BIT)
12403 return (const reg_entry *) NULL;
12404
12405 i.vec_encoding = vex_encoding_evex;
12406 }
12407
12408 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
12409 && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
12410 && flag_code != CODE_64BIT)
12411 return (const reg_entry *) NULL;
12412
12413 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
12414 && !intel_syntax)
12415 return (const reg_entry *) NULL;
12416
12417 return r;
12418 }
12419
12420 /* REG_STRING starts *before* REGISTER_PREFIX. */
12421
12422 static const reg_entry *
12423 parse_register (char *reg_string, char **end_op)
12424 {
12425 const reg_entry *r;
12426
12427 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
12428 r = parse_real_register (reg_string, end_op);
12429 else
12430 r = NULL;
12431 if (!r)
12432 {
12433 char *save = input_line_pointer;
12434 char c;
12435 symbolS *symbolP;
12436
12437 input_line_pointer = reg_string;
12438 c = get_symbol_name (&reg_string);
12439 symbolP = symbol_find (reg_string);
12440 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
12441 {
12442 const expressionS *e = symbol_get_value_expression (symbolP);
12443
12444 know (e->X_op == O_register);
12445 know (e->X_add_number >= 0
12446 && (valueT) e->X_add_number < i386_regtab_size);
12447 r = i386_regtab + e->X_add_number;
12448 if ((r->reg_flags & RegVRex))
12449 i.vec_encoding = vex_encoding_evex;
12450 *end_op = input_line_pointer;
12451 }
12452 *input_line_pointer = c;
12453 input_line_pointer = save;
12454 }
12455 return r;
12456 }
12457
12458 int
12459 i386_parse_name (char *name, expressionS *e, char *nextcharP)
12460 {
12461 const reg_entry *r;
12462 char *end = input_line_pointer;
12463
12464 *end = *nextcharP;
12465 r = parse_register (name, &input_line_pointer);
12466 if (r && end <= input_line_pointer)
12467 {
12468 *nextcharP = *input_line_pointer;
12469 *input_line_pointer = 0;
12470 e->X_op = O_register;
12471 e->X_add_number = r - i386_regtab;
12472 return 1;
12473 }
12474 input_line_pointer = end;
12475 *end = 0;
12476 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
12477 }
12478
12479 void
12480 md_operand (expressionS *e)
12481 {
12482 char *end;
12483 const reg_entry *r;
12484
12485 switch (*input_line_pointer)
12486 {
12487 case REGISTER_PREFIX:
12488 r = parse_real_register (input_line_pointer, &end);
12489 if (r)
12490 {
12491 e->X_op = O_register;
12492 e->X_add_number = r - i386_regtab;
12493 input_line_pointer = end;
12494 }
12495 break;
12496
12497 case '[':
12498 gas_assert (intel_syntax);
12499 end = input_line_pointer++;
12500 expression (e);
12501 if (*input_line_pointer == ']')
12502 {
12503 ++input_line_pointer;
12504 e->X_op_symbol = make_expr_symbol (e);
12505 e->X_add_symbol = NULL;
12506 e->X_add_number = 0;
12507 e->X_op = O_index;
12508 }
12509 else
12510 {
12511 e->X_op = O_absent;
12512 input_line_pointer = end;
12513 }
12514 break;
12515 }
12516 }
12517
12518 \f
12519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12520 const char *md_shortopts = "kVQ:sqnO::";
12521 #else
12522 const char *md_shortopts = "qnO::";
12523 #endif
12524
12525 #define OPTION_32 (OPTION_MD_BASE + 0)
12526 #define OPTION_64 (OPTION_MD_BASE + 1)
12527 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12528 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12529 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12530 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12531 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12532 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12533 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12534 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12535 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12536 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12537 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12538 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12539 #define OPTION_X32 (OPTION_MD_BASE + 14)
12540 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12541 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12542 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12543 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12544 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12545 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12546 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12547 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12548 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12549 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12550 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12551 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12552 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12553 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12554 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12555 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12556 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12557 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12558 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12559
12560 struct option md_longopts[] =
12561 {
12562 {"32", no_argument, NULL, OPTION_32},
12563 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12564 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12565 {"64", no_argument, NULL, OPTION_64},
12566 #endif
12567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12568 {"x32", no_argument, NULL, OPTION_X32},
12569 {"mshared", no_argument, NULL, OPTION_MSHARED},
12570 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
12571 #endif
12572 {"divide", no_argument, NULL, OPTION_DIVIDE},
12573 {"march", required_argument, NULL, OPTION_MARCH},
12574 {"mtune", required_argument, NULL, OPTION_MTUNE},
12575 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
12576 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
12577 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
12578 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
12579 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
12580 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
12581 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
12582 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
12583 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
12584 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
12585 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
12586 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
12587 # if defined (TE_PE) || defined (TE_PEP)
12588 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
12589 #endif
12590 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
12591 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
12592 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
12593 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
12594 {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY},
12595 {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
12596 {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
12597 {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
12598 {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
12599 {"mlfence-before-indirect-branch", required_argument, NULL,
12600 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
12601 {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
12602 {"mamd64", no_argument, NULL, OPTION_MAMD64},
12603 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
12604 {NULL, no_argument, NULL, 0}
12605 };
12606 size_t md_longopts_size = sizeof (md_longopts);
12607
12608 int
12609 md_parse_option (int c, const char *arg)
12610 {
12611 unsigned int j;
12612 char *arch, *next, *saved, *type;
12613
12614 switch (c)
12615 {
12616 case 'n':
12617 optimize_align_code = 0;
12618 break;
12619
12620 case 'q':
12621 quiet_warnings = 1;
12622 break;
12623
12624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12625 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12626 should be emitted or not. FIXME: Not implemented. */
12627 case 'Q':
12628 if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
12629 return 0;
12630 break;
12631
12632 /* -V: SVR4 argument to print version ID. */
12633 case 'V':
12634 print_version_id ();
12635 break;
12636
12637 /* -k: Ignore for FreeBSD compatibility. */
12638 case 'k':
12639 break;
12640
12641 case 's':
12642 /* -s: On i386 Solaris, this tells the native assembler to use
12643 .stab instead of .stab.excl. We always use .stab anyhow. */
12644 break;
12645
12646 case OPTION_MSHARED:
12647 shared = 1;
12648 break;
12649
12650 case OPTION_X86_USED_NOTE:
12651 if (strcasecmp (arg, "yes") == 0)
12652 x86_used_note = 1;
12653 else if (strcasecmp (arg, "no") == 0)
12654 x86_used_note = 0;
12655 else
12656 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
12657 break;
12658
12659
12660 #endif
12661 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12662 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12663 case OPTION_64:
12664 {
12665 const char **list, **l;
12666
12667 list = bfd_target_list ();
12668 for (l = list; *l != NULL; l++)
12669 if (CONST_STRNEQ (*l, "elf64-x86-64")
12670 || strcmp (*l, "coff-x86-64") == 0
12671 || strcmp (*l, "pe-x86-64") == 0
12672 || strcmp (*l, "pei-x86-64") == 0
12673 || strcmp (*l, "mach-o-x86-64") == 0)
12674 {
12675 default_arch = "x86_64";
12676 break;
12677 }
12678 if (*l == NULL)
12679 as_fatal (_("no compiled in support for x86_64"));
12680 free (list);
12681 }
12682 break;
12683 #endif
12684
12685 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12686 case OPTION_X32:
12687 if (IS_ELF)
12688 {
12689 const char **list, **l;
12690
12691 list = bfd_target_list ();
12692 for (l = list; *l != NULL; l++)
12693 if (CONST_STRNEQ (*l, "elf32-x86-64"))
12694 {
12695 default_arch = "x86_64:32";
12696 break;
12697 }
12698 if (*l == NULL)
12699 as_fatal (_("no compiled in support for 32bit x86_64"));
12700 free (list);
12701 }
12702 else
12703 as_fatal (_("32bit x86_64 is only supported for ELF"));
12704 break;
12705 #endif
12706
12707 case OPTION_32:
12708 default_arch = "i386";
12709 break;
12710
12711 case OPTION_DIVIDE:
12712 #ifdef SVR4_COMMENT_CHARS
12713 {
12714 char *n, *t;
12715 const char *s;
12716
12717 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
12718 t = n;
12719 for (s = i386_comment_chars; *s != '\0'; s++)
12720 if (*s != '/')
12721 *t++ = *s;
12722 *t = '\0';
12723 i386_comment_chars = n;
12724 }
12725 #endif
12726 break;
12727
12728 case OPTION_MARCH:
12729 saved = xstrdup (arg);
12730 arch = saved;
12731 /* Allow -march=+nosse. */
12732 if (*arch == '+')
12733 arch++;
12734 do
12735 {
12736 if (*arch == '.')
12737 as_fatal (_("invalid -march= option: `%s'"), arg);
12738 next = strchr (arch, '+');
12739 if (next)
12740 *next++ = '\0';
12741 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
12742 {
12743 if (strcmp (arch, cpu_arch [j].name) == 0)
12744 {
12745 /* Processor. */
12746 if (! cpu_arch[j].flags.bitfield.cpui386)
12747 continue;
12748
12749 cpu_arch_name = cpu_arch[j].name;
12750 cpu_sub_arch_name = NULL;
12751 cpu_arch_flags = cpu_arch[j].flags;
12752 cpu_arch_isa = cpu_arch[j].type;
12753 cpu_arch_isa_flags = cpu_arch[j].flags;
12754 if (!cpu_arch_tune_set)
12755 {
12756 cpu_arch_tune = cpu_arch_isa;
12757 cpu_arch_tune_flags = cpu_arch_isa_flags;
12758 }
12759 break;
12760 }
12761 else if (*cpu_arch [j].name == '.'
12762 && strcmp (arch, cpu_arch [j].name + 1) == 0)
12763 {
12764 /* ISA extension. */
12765 i386_cpu_flags flags;
12766
12767 flags = cpu_flags_or (cpu_arch_flags,
12768 cpu_arch[j].flags);
12769
12770 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
12771 {
12772 if (cpu_sub_arch_name)
12773 {
12774 char *name = cpu_sub_arch_name;
12775 cpu_sub_arch_name = concat (name,
12776 cpu_arch[j].name,
12777 (const char *) NULL);
12778 free (name);
12779 }
12780 else
12781 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
12782 cpu_arch_flags = flags;
12783 cpu_arch_isa_flags = flags;
12784 }
12785 else
12786 cpu_arch_isa_flags
12787 = cpu_flags_or (cpu_arch_isa_flags,
12788 cpu_arch[j].flags);
12789 break;
12790 }
12791 }
12792
12793 if (j >= ARRAY_SIZE (cpu_arch))
12794 {
12795 /* Disable an ISA extension. */
12796 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
12797 if (strcmp (arch, cpu_noarch [j].name) == 0)
12798 {
12799 i386_cpu_flags flags;
12800
12801 flags = cpu_flags_and_not (cpu_arch_flags,
12802 cpu_noarch[j].flags);
12803 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
12804 {
12805 if (cpu_sub_arch_name)
12806 {
12807 char *name = cpu_sub_arch_name;
12808 cpu_sub_arch_name = concat (arch,
12809 (const char *) NULL);
12810 free (name);
12811 }
12812 else
12813 cpu_sub_arch_name = xstrdup (arch);
12814 cpu_arch_flags = flags;
12815 cpu_arch_isa_flags = flags;
12816 }
12817 break;
12818 }
12819
12820 if (j >= ARRAY_SIZE (cpu_noarch))
12821 j = ARRAY_SIZE (cpu_arch);
12822 }
12823
12824 if (j >= ARRAY_SIZE (cpu_arch))
12825 as_fatal (_("invalid -march= option: `%s'"), arg);
12826
12827 arch = next;
12828 }
12829 while (next != NULL);
12830 free (saved);
12831 break;
12832
12833 case OPTION_MTUNE:
12834 if (*arg == '.')
12835 as_fatal (_("invalid -mtune= option: `%s'"), arg);
12836 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
12837 {
12838 if (strcmp (arg, cpu_arch [j].name) == 0)
12839 {
12840 cpu_arch_tune_set = 1;
12841 cpu_arch_tune = cpu_arch [j].type;
12842 cpu_arch_tune_flags = cpu_arch[j].flags;
12843 break;
12844 }
12845 }
12846 if (j >= ARRAY_SIZE (cpu_arch))
12847 as_fatal (_("invalid -mtune= option: `%s'"), arg);
12848 break;
12849
12850 case OPTION_MMNEMONIC:
12851 if (strcasecmp (arg, "att") == 0)
12852 intel_mnemonic = 0;
12853 else if (strcasecmp (arg, "intel") == 0)
12854 intel_mnemonic = 1;
12855 else
12856 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
12857 break;
12858
12859 case OPTION_MSYNTAX:
12860 if (strcasecmp (arg, "att") == 0)
12861 intel_syntax = 0;
12862 else if (strcasecmp (arg, "intel") == 0)
12863 intel_syntax = 1;
12864 else
12865 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
12866 break;
12867
12868 case OPTION_MINDEX_REG:
12869 allow_index_reg = 1;
12870 break;
12871
12872 case OPTION_MNAKED_REG:
12873 allow_naked_reg = 1;
12874 break;
12875
12876 case OPTION_MSSE2AVX:
12877 sse2avx = 1;
12878 break;
12879
12880 case OPTION_MSSE_CHECK:
12881 if (strcasecmp (arg, "error") == 0)
12882 sse_check = check_error;
12883 else if (strcasecmp (arg, "warning") == 0)
12884 sse_check = check_warning;
12885 else if (strcasecmp (arg, "none") == 0)
12886 sse_check = check_none;
12887 else
12888 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
12889 break;
12890
12891 case OPTION_MOPERAND_CHECK:
12892 if (strcasecmp (arg, "error") == 0)
12893 operand_check = check_error;
12894 else if (strcasecmp (arg, "warning") == 0)
12895 operand_check = check_warning;
12896 else if (strcasecmp (arg, "none") == 0)
12897 operand_check = check_none;
12898 else
12899 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
12900 break;
12901
12902 case OPTION_MAVXSCALAR:
12903 if (strcasecmp (arg, "128") == 0)
12904 avxscalar = vex128;
12905 else if (strcasecmp (arg, "256") == 0)
12906 avxscalar = vex256;
12907 else
12908 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
12909 break;
12910
12911 case OPTION_MVEXWIG:
12912 if (strcmp (arg, "0") == 0)
12913 vexwig = vexw0;
12914 else if (strcmp (arg, "1") == 0)
12915 vexwig = vexw1;
12916 else
12917 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
12918 break;
12919
12920 case OPTION_MADD_BND_PREFIX:
12921 add_bnd_prefix = 1;
12922 break;
12923
12924 case OPTION_MEVEXLIG:
12925 if (strcmp (arg, "128") == 0)
12926 evexlig = evexl128;
12927 else if (strcmp (arg, "256") == 0)
12928 evexlig = evexl256;
12929 else if (strcmp (arg, "512") == 0)
12930 evexlig = evexl512;
12931 else
12932 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
12933 break;
12934
12935 case OPTION_MEVEXRCIG:
12936 if (strcmp (arg, "rne") == 0)
12937 evexrcig = rne;
12938 else if (strcmp (arg, "rd") == 0)
12939 evexrcig = rd;
12940 else if (strcmp (arg, "ru") == 0)
12941 evexrcig = ru;
12942 else if (strcmp (arg, "rz") == 0)
12943 evexrcig = rz;
12944 else
12945 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
12946 break;
12947
12948 case OPTION_MEVEXWIG:
12949 if (strcmp (arg, "0") == 0)
12950 evexwig = evexw0;
12951 else if (strcmp (arg, "1") == 0)
12952 evexwig = evexw1;
12953 else
12954 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
12955 break;
12956
12957 # if defined (TE_PE) || defined (TE_PEP)
12958 case OPTION_MBIG_OBJ:
12959 use_big_obj = 1;
12960 break;
12961 #endif
12962
12963 case OPTION_MOMIT_LOCK_PREFIX:
12964 if (strcasecmp (arg, "yes") == 0)
12965 omit_lock_prefix = 1;
12966 else if (strcasecmp (arg, "no") == 0)
12967 omit_lock_prefix = 0;
12968 else
12969 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
12970 break;
12971
12972 case OPTION_MFENCE_AS_LOCK_ADD:
12973 if (strcasecmp (arg, "yes") == 0)
12974 avoid_fence = 1;
12975 else if (strcasecmp (arg, "no") == 0)
12976 avoid_fence = 0;
12977 else
12978 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
12979 break;
12980
12981 case OPTION_MLFENCE_AFTER_LOAD:
12982 if (strcasecmp (arg, "yes") == 0)
12983 lfence_after_load = 1;
12984 else if (strcasecmp (arg, "no") == 0)
12985 lfence_after_load = 0;
12986 else
12987 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
12988 break;
12989
12990 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
12991 if (strcasecmp (arg, "all") == 0)
12992 lfence_before_indirect_branch = lfence_branch_all;
12993 else if (strcasecmp (arg, "memory") == 0)
12994 lfence_before_indirect_branch = lfence_branch_memory;
12995 else if (strcasecmp (arg, "register") == 0)
12996 lfence_before_indirect_branch = lfence_branch_register;
12997 else if (strcasecmp (arg, "none") == 0)
12998 lfence_before_indirect_branch = lfence_branch_none;
12999 else
13000 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13001 arg);
13002 break;
13003
13004 case OPTION_MLFENCE_BEFORE_RET:
13005 if (strcasecmp (arg, "or") == 0)
13006 lfence_before_ret = lfence_before_ret_or;
13007 else if (strcasecmp (arg, "not") == 0)
13008 lfence_before_ret = lfence_before_ret_not;
13009 else if (strcasecmp (arg, "none") == 0)
13010 lfence_before_ret = lfence_before_ret_none;
13011 else
13012 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13013 arg);
13014 break;
13015
13016 case OPTION_MRELAX_RELOCATIONS:
13017 if (strcasecmp (arg, "yes") == 0)
13018 generate_relax_relocations = 1;
13019 else if (strcasecmp (arg, "no") == 0)
13020 generate_relax_relocations = 0;
13021 else
13022 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
13023 break;
13024
13025 case OPTION_MALIGN_BRANCH_BOUNDARY:
13026 {
13027 char *end;
13028 long int align = strtoul (arg, &end, 0);
13029 if (*end == '\0')
13030 {
13031 if (align == 0)
13032 {
13033 align_branch_power = 0;
13034 break;
13035 }
13036 else if (align >= 16)
13037 {
13038 int align_power;
13039 for (align_power = 0;
13040 (align & 1) == 0;
13041 align >>= 1, align_power++)
13042 continue;
13043 /* Limit alignment power to 31. */
13044 if (align == 1 && align_power < 32)
13045 {
13046 align_branch_power = align_power;
13047 break;
13048 }
13049 }
13050 }
13051 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg);
13052 }
13053 break;
13054
13055 case OPTION_MALIGN_BRANCH_PREFIX_SIZE:
13056 {
13057 char *end;
13058 int align = strtoul (arg, &end, 0);
13059 /* Some processors only support 5 prefixes. */
13060 if (*end == '\0' && align >= 0 && align < 6)
13061 {
13062 align_branch_prefix_size = align;
13063 break;
13064 }
13065 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13066 arg);
13067 }
13068 break;
13069
13070 case OPTION_MALIGN_BRANCH:
13071 align_branch = 0;
13072 saved = xstrdup (arg);
13073 type = saved;
13074 do
13075 {
13076 next = strchr (type, '+');
13077 if (next)
13078 *next++ = '\0';
13079 if (strcasecmp (type, "jcc") == 0)
13080 align_branch |= align_branch_jcc_bit;
13081 else if (strcasecmp (type, "fused") == 0)
13082 align_branch |= align_branch_fused_bit;
13083 else if (strcasecmp (type, "jmp") == 0)
13084 align_branch |= align_branch_jmp_bit;
13085 else if (strcasecmp (type, "call") == 0)
13086 align_branch |= align_branch_call_bit;
13087 else if (strcasecmp (type, "ret") == 0)
13088 align_branch |= align_branch_ret_bit;
13089 else if (strcasecmp (type, "indirect") == 0)
13090 align_branch |= align_branch_indirect_bit;
13091 else
13092 as_fatal (_("invalid -malign-branch= option: `%s'"), arg);
13093 type = next;
13094 }
13095 while (next != NULL);
13096 free (saved);
13097 break;
13098
13099 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES:
13100 align_branch_power = 5;
13101 align_branch_prefix_size = 5;
13102 align_branch = (align_branch_jcc_bit
13103 | align_branch_fused_bit
13104 | align_branch_jmp_bit);
13105 break;
13106
13107 case OPTION_MAMD64:
13108 isa64 = amd64;
13109 break;
13110
13111 case OPTION_MINTEL64:
13112 isa64 = intel64;
13113 break;
13114
13115 case 'O':
13116 if (arg == NULL)
13117 {
13118 optimize = 1;
13119 /* Turn off -Os. */
13120 optimize_for_space = 0;
13121 }
13122 else if (*arg == 's')
13123 {
13124 optimize_for_space = 1;
13125 /* Turn on all encoding optimizations. */
13126 optimize = INT_MAX;
13127 }
13128 else
13129 {
13130 optimize = atoi (arg);
13131 /* Turn off -Os. */
13132 optimize_for_space = 0;
13133 }
13134 break;
13135
13136 default:
13137 return 0;
13138 }
13139 return 1;
13140 }
13141
13142 #define MESSAGE_TEMPLATE \
13143 " "
13144
13145 static char *
13146 output_message (FILE *stream, char *p, char *message, char *start,
13147 int *left_p, const char *name, int len)
13148 {
13149 int size = sizeof (MESSAGE_TEMPLATE);
13150 int left = *left_p;
13151
13152 /* Reserve 2 spaces for ", " or ",\0" */
13153 left -= len + 2;
13154
13155 /* Check if there is any room. */
13156 if (left >= 0)
13157 {
13158 if (p != start)
13159 {
13160 *p++ = ',';
13161 *p++ = ' ';
13162 }
13163 p = mempcpy (p, name, len);
13164 }
13165 else
13166 {
13167 /* Output the current message now and start a new one. */
13168 *p++ = ',';
13169 *p = '\0';
13170 fprintf (stream, "%s\n", message);
13171 p = start;
13172 left = size - (start - message) - len - 2;
13173
13174 gas_assert (left >= 0);
13175
13176 p = mempcpy (p, name, len);
13177 }
13178
13179 *left_p = left;
13180 return p;
13181 }
13182
13183 static void
13184 show_arch (FILE *stream, int ext, int check)
13185 {
13186 static char message[] = MESSAGE_TEMPLATE;
13187 char *start = message + 27;
13188 char *p;
13189 int size = sizeof (MESSAGE_TEMPLATE);
13190 int left;
13191 const char *name;
13192 int len;
13193 unsigned int j;
13194
13195 p = start;
13196 left = size - (start - message);
13197 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
13198 {
13199 /* Should it be skipped? */
13200 if (cpu_arch [j].skip)
13201 continue;
13202
13203 name = cpu_arch [j].name;
13204 len = cpu_arch [j].len;
13205 if (*name == '.')
13206 {
13207 /* It is an extension. Skip if we aren't asked to show it. */
13208 if (ext)
13209 {
13210 name++;
13211 len--;
13212 }
13213 else
13214 continue;
13215 }
13216 else if (ext)
13217 {
13218 /* It is an processor. Skip if we show only extension. */
13219 continue;
13220 }
13221 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
13222 {
13223 /* It is an impossible processor - skip. */
13224 continue;
13225 }
13226
13227 p = output_message (stream, p, message, start, &left, name, len);
13228 }
13229
13230 /* Display disabled extensions. */
13231 if (ext)
13232 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
13233 {
13234 name = cpu_noarch [j].name;
13235 len = cpu_noarch [j].len;
13236 p = output_message (stream, p, message, start, &left, name,
13237 len);
13238 }
13239
13240 *p = '\0';
13241 fprintf (stream, "%s\n", message);
13242 }
13243
13244 void
13245 md_show_usage (FILE *stream)
13246 {
13247 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13248 fprintf (stream, _("\
13249 -Qy, -Qn ignored\n\
13250 -V print assembler version number\n\
13251 -k ignored\n"));
13252 #endif
13253 fprintf (stream, _("\
13254 -n Do not optimize code alignment\n\
13255 -q quieten some warnings\n"));
13256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13257 fprintf (stream, _("\
13258 -s ignored\n"));
13259 #endif
13260 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13261 || defined (TE_PE) || defined (TE_PEP))
13262 fprintf (stream, _("\
13263 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13264 #endif
13265 #ifdef SVR4_COMMENT_CHARS
13266 fprintf (stream, _("\
13267 --divide do not treat `/' as a comment character\n"));
13268 #else
13269 fprintf (stream, _("\
13270 --divide ignored\n"));
13271 #endif
13272 fprintf (stream, _("\
13273 -march=CPU[,+EXTENSION...]\n\
13274 generate code for CPU and EXTENSION, CPU is one of:\n"));
13275 show_arch (stream, 0, 1);
13276 fprintf (stream, _("\
13277 EXTENSION is combination of:\n"));
13278 show_arch (stream, 1, 0);
13279 fprintf (stream, _("\
13280 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13281 show_arch (stream, 0, 0);
13282 fprintf (stream, _("\
13283 -msse2avx encode SSE instructions with VEX prefix\n"));
13284 fprintf (stream, _("\
13285 -msse-check=[none|error|warning] (default: warning)\n\
13286 check SSE instructions\n"));
13287 fprintf (stream, _("\
13288 -moperand-check=[none|error|warning] (default: warning)\n\
13289 check operand combinations for validity\n"));
13290 fprintf (stream, _("\
13291 -mavxscalar=[128|256] (default: 128)\n\
13292 encode scalar AVX instructions with specific vector\n\
13293 length\n"));
13294 fprintf (stream, _("\
13295 -mvexwig=[0|1] (default: 0)\n\
13296 encode VEX instructions with specific VEX.W value\n\
13297 for VEX.W bit ignored instructions\n"));
13298 fprintf (stream, _("\
13299 -mevexlig=[128|256|512] (default: 128)\n\
13300 encode scalar EVEX instructions with specific vector\n\
13301 length\n"));
13302 fprintf (stream, _("\
13303 -mevexwig=[0|1] (default: 0)\n\
13304 encode EVEX instructions with specific EVEX.W value\n\
13305 for EVEX.W bit ignored instructions\n"));
13306 fprintf (stream, _("\
13307 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13308 encode EVEX instructions with specific EVEX.RC value\n\
13309 for SAE-only ignored instructions\n"));
13310 fprintf (stream, _("\
13311 -mmnemonic=[att|intel] "));
13312 if (SYSV386_COMPAT)
13313 fprintf (stream, _("(default: att)\n"));
13314 else
13315 fprintf (stream, _("(default: intel)\n"));
13316 fprintf (stream, _("\
13317 use AT&T/Intel mnemonic\n"));
13318 fprintf (stream, _("\
13319 -msyntax=[att|intel] (default: att)\n\
13320 use AT&T/Intel syntax\n"));
13321 fprintf (stream, _("\
13322 -mindex-reg support pseudo index registers\n"));
13323 fprintf (stream, _("\
13324 -mnaked-reg don't require `%%' prefix for registers\n"));
13325 fprintf (stream, _("\
13326 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13328 fprintf (stream, _("\
13329 -mshared disable branch optimization for shared code\n"));
13330 fprintf (stream, _("\
13331 -mx86-used-note=[no|yes] "));
13332 if (DEFAULT_X86_USED_NOTE)
13333 fprintf (stream, _("(default: yes)\n"));
13334 else
13335 fprintf (stream, _("(default: no)\n"));
13336 fprintf (stream, _("\
13337 generate x86 used ISA and feature properties\n"));
13338 #endif
13339 #if defined (TE_PE) || defined (TE_PEP)
13340 fprintf (stream, _("\
13341 -mbig-obj generate big object files\n"));
13342 #endif
13343 fprintf (stream, _("\
13344 -momit-lock-prefix=[no|yes] (default: no)\n\
13345 strip all lock prefixes\n"));
13346 fprintf (stream, _("\
13347 -mfence-as-lock-add=[no|yes] (default: no)\n\
13348 encode lfence, mfence and sfence as\n\
13349 lock addl $0x0, (%%{re}sp)\n"));
13350 fprintf (stream, _("\
13351 -mrelax-relocations=[no|yes] "));
13352 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
13353 fprintf (stream, _("(default: yes)\n"));
13354 else
13355 fprintf (stream, _("(default: no)\n"));
13356 fprintf (stream, _("\
13357 generate relax relocations\n"));
13358 fprintf (stream, _("\
13359 -malign-branch-boundary=NUM (default: 0)\n\
13360 align branches within NUM byte boundary\n"));
13361 fprintf (stream, _("\
13362 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13363 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13364 indirect\n\
13365 specify types of branches to align\n"));
13366 fprintf (stream, _("\
13367 -malign-branch-prefix-size=NUM (default: 5)\n\
13368 align branches with NUM prefixes per instruction\n"));
13369 fprintf (stream, _("\
13370 -mbranches-within-32B-boundaries\n\
13371 align branches within 32 byte boundary\n"));
13372 fprintf (stream, _("\
13373 -mlfence-after-load=[no|yes] (default: no)\n\
13374 generate lfence after load\n"));
13375 fprintf (stream, _("\
13376 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13377 generate lfence before indirect near branch\n"));
13378 fprintf (stream, _("\
13379 -mlfence-before-ret=[none|or|not] (default: none)\n\
13380 generate lfence before ret\n"));
13381 fprintf (stream, _("\
13382 -mamd64 accept only AMD64 ISA [default]\n"));
13383 fprintf (stream, _("\
13384 -mintel64 accept only Intel64 ISA\n"));
13385 }
13386
13387 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13388 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13389 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13390
13391 /* Pick the target format to use. */
13392
13393 const char *
13394 i386_target_format (void)
13395 {
13396 if (!strncmp (default_arch, "x86_64", 6))
13397 {
13398 update_code_flag (CODE_64BIT, 1);
13399 if (default_arch[6] == '\0')
13400 x86_elf_abi = X86_64_ABI;
13401 else
13402 x86_elf_abi = X86_64_X32_ABI;
13403 }
13404 else if (!strcmp (default_arch, "i386"))
13405 update_code_flag (CODE_32BIT, 1);
13406 else if (!strcmp (default_arch, "iamcu"))
13407 {
13408 update_code_flag (CODE_32BIT, 1);
13409 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
13410 {
13411 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
13412 cpu_arch_name = "iamcu";
13413 cpu_sub_arch_name = NULL;
13414 cpu_arch_flags = iamcu_flags;
13415 cpu_arch_isa = PROCESSOR_IAMCU;
13416 cpu_arch_isa_flags = iamcu_flags;
13417 if (!cpu_arch_tune_set)
13418 {
13419 cpu_arch_tune = cpu_arch_isa;
13420 cpu_arch_tune_flags = cpu_arch_isa_flags;
13421 }
13422 }
13423 else if (cpu_arch_isa != PROCESSOR_IAMCU)
13424 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13425 cpu_arch_name);
13426 }
13427 else
13428 as_fatal (_("unknown architecture"));
13429
13430 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
13431 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
13432 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
13433 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
13434
13435 switch (OUTPUT_FLAVOR)
13436 {
13437 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13438 case bfd_target_aout_flavour:
13439 return AOUT_TARGET_FORMAT;
13440 #endif
13441 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13442 # if defined (TE_PE) || defined (TE_PEP)
13443 case bfd_target_coff_flavour:
13444 if (flag_code == CODE_64BIT)
13445 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
13446 else
13447 return "pe-i386";
13448 # elif defined (TE_GO32)
13449 case bfd_target_coff_flavour:
13450 return "coff-go32";
13451 # else
13452 case bfd_target_coff_flavour:
13453 return "coff-i386";
13454 # endif
13455 #endif
13456 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13457 case bfd_target_elf_flavour:
13458 {
13459 const char *format;
13460
13461 switch (x86_elf_abi)
13462 {
13463 default:
13464 format = ELF_TARGET_FORMAT;
13465 #ifndef TE_SOLARIS
13466 tls_get_addr = "___tls_get_addr";
13467 #endif
13468 break;
13469 case X86_64_ABI:
13470 use_rela_relocations = 1;
13471 object_64bit = 1;
13472 #ifndef TE_SOLARIS
13473 tls_get_addr = "__tls_get_addr";
13474 #endif
13475 format = ELF_TARGET_FORMAT64;
13476 break;
13477 case X86_64_X32_ABI:
13478 use_rela_relocations = 1;
13479 object_64bit = 1;
13480 #ifndef TE_SOLARIS
13481 tls_get_addr = "__tls_get_addr";
13482 #endif
13483 disallow_64bit_reloc = 1;
13484 format = ELF_TARGET_FORMAT32;
13485 break;
13486 }
13487 if (cpu_arch_isa == PROCESSOR_L1OM)
13488 {
13489 if (x86_elf_abi != X86_64_ABI)
13490 as_fatal (_("Intel L1OM is 64bit only"));
13491 return ELF_TARGET_L1OM_FORMAT;
13492 }
13493 else if (cpu_arch_isa == PROCESSOR_K1OM)
13494 {
13495 if (x86_elf_abi != X86_64_ABI)
13496 as_fatal (_("Intel K1OM is 64bit only"));
13497 return ELF_TARGET_K1OM_FORMAT;
13498 }
13499 else if (cpu_arch_isa == PROCESSOR_IAMCU)
13500 {
13501 if (x86_elf_abi != I386_ABI)
13502 as_fatal (_("Intel MCU is 32bit only"));
13503 return ELF_TARGET_IAMCU_FORMAT;
13504 }
13505 else
13506 return format;
13507 }
13508 #endif
13509 #if defined (OBJ_MACH_O)
13510 case bfd_target_mach_o_flavour:
13511 if (flag_code == CODE_64BIT)
13512 {
13513 use_rela_relocations = 1;
13514 object_64bit = 1;
13515 return "mach-o-x86-64";
13516 }
13517 else
13518 return "mach-o-i386";
13519 #endif
13520 default:
13521 abort ();
13522 return NULL;
13523 }
13524 }
13525
13526 #endif /* OBJ_MAYBE_ more than one */
13527 \f
13528 symbolS *
13529 md_undefined_symbol (char *name)
13530 {
13531 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
13532 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
13533 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
13534 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
13535 {
13536 if (!GOT_symbol)
13537 {
13538 if (symbol_find (name))
13539 as_bad (_("GOT already in symbol table"));
13540 GOT_symbol = symbol_new (name, undefined_section,
13541 (valueT) 0, &zero_address_frag);
13542 };
13543 return GOT_symbol;
13544 }
13545 return 0;
13546 }
13547
13548 /* Round up a section size to the appropriate boundary. */
13549
13550 valueT
13551 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
13552 {
13553 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13554 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
13555 {
13556 /* For a.out, force the section size to be aligned. If we don't do
13557 this, BFD will align it for us, but it will not write out the
13558 final bytes of the section. This may be a bug in BFD, but it is
13559 easier to fix it here since that is how the other a.out targets
13560 work. */
13561 int align;
13562
13563 align = bfd_section_alignment (segment);
13564 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
13565 }
13566 #endif
13567
13568 return size;
13569 }
13570
13571 /* On the i386, PC-relative offsets are relative to the start of the
13572 next instruction. That is, the address of the offset, plus its
13573 size, since the offset is always the last part of the insn. */
13574
13575 long
13576 md_pcrel_from (fixS *fixP)
13577 {
13578 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
13579 }
13580
13581 #ifndef I386COFF
13582
13583 static void
13584 s_bss (int ignore ATTRIBUTE_UNUSED)
13585 {
13586 int temp;
13587
13588 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13589 if (IS_ELF)
13590 obj_elf_section_change_hook ();
13591 #endif
13592 temp = get_absolute_expression ();
13593 subseg_set (bss_section, (subsegT) temp);
13594 demand_empty_rest_of_line ();
13595 }
13596
13597 #endif
13598
13599 /* Remember constant directive. */
13600
13601 void
13602 i386_cons_align (int ignore ATTRIBUTE_UNUSED)
13603 {
13604 if (last_insn.kind != last_insn_directive
13605 && (bfd_section_flags (now_seg) & SEC_CODE))
13606 {
13607 last_insn.seg = now_seg;
13608 last_insn.kind = last_insn_directive;
13609 last_insn.name = "constant directive";
13610 last_insn.file = as_where (&last_insn.line);
13611 if (lfence_before_ret != lfence_before_ret_none)
13612 {
13613 if (lfence_before_indirect_branch != lfence_branch_none)
13614 as_warn (_("constant directive skips -mlfence-before-ret "
13615 "and -mlfence-before-indirect-branch"));
13616 else
13617 as_warn (_("constant directive skips -mlfence-before-ret"));
13618 }
13619 else if (lfence_before_indirect_branch != lfence_branch_none)
13620 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13621 }
13622 }
13623
13624 void
13625 i386_validate_fix (fixS *fixp)
13626 {
13627 if (fixp->fx_subsy)
13628 {
13629 if (fixp->fx_subsy == GOT_symbol)
13630 {
13631 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
13632 {
13633 if (!object_64bit)
13634 abort ();
13635 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13636 if (fixp->fx_tcbit2)
13637 fixp->fx_r_type = (fixp->fx_tcbit
13638 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13639 : BFD_RELOC_X86_64_GOTPCRELX);
13640 else
13641 #endif
13642 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
13643 }
13644 else
13645 {
13646 if (!object_64bit)
13647 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
13648 else
13649 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
13650 }
13651 fixp->fx_subsy = 0;
13652 }
13653 }
13654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13655 else if (!object_64bit)
13656 {
13657 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
13658 && fixp->fx_tcbit2)
13659 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
13660 }
13661 #endif
13662 }
13663
13664 arelent *
13665 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13666 {
13667 arelent *rel;
13668 bfd_reloc_code_real_type code;
13669
13670 switch (fixp->fx_r_type)
13671 {
13672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13673 case BFD_RELOC_SIZE32:
13674 case BFD_RELOC_SIZE64:
13675 if (S_IS_DEFINED (fixp->fx_addsy)
13676 && !S_IS_EXTERNAL (fixp->fx_addsy))
13677 {
13678 /* Resolve size relocation against local symbol to size of
13679 the symbol plus addend. */
13680 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
13681 if (fixp->fx_r_type == BFD_RELOC_SIZE32
13682 && !fits_in_unsigned_long (value))
13683 as_bad_where (fixp->fx_file, fixp->fx_line,
13684 _("symbol size computation overflow"));
13685 fixp->fx_addsy = NULL;
13686 fixp->fx_subsy = NULL;
13687 md_apply_fix (fixp, (valueT *) &value, NULL);
13688 return NULL;
13689 }
13690 #endif
13691 /* Fall through. */
13692
13693 case BFD_RELOC_X86_64_PLT32:
13694 case BFD_RELOC_X86_64_GOT32:
13695 case BFD_RELOC_X86_64_GOTPCREL:
13696 case BFD_RELOC_X86_64_GOTPCRELX:
13697 case BFD_RELOC_X86_64_REX_GOTPCRELX:
13698 case BFD_RELOC_386_PLT32:
13699 case BFD_RELOC_386_GOT32:
13700 case BFD_RELOC_386_GOT32X:
13701 case BFD_RELOC_386_GOTOFF:
13702 case BFD_RELOC_386_GOTPC:
13703 case BFD_RELOC_386_TLS_GD:
13704 case BFD_RELOC_386_TLS_LDM:
13705 case BFD_RELOC_386_TLS_LDO_32:
13706 case BFD_RELOC_386_TLS_IE_32:
13707 case BFD_RELOC_386_TLS_IE:
13708 case BFD_RELOC_386_TLS_GOTIE:
13709 case BFD_RELOC_386_TLS_LE_32:
13710 case BFD_RELOC_386_TLS_LE:
13711 case BFD_RELOC_386_TLS_GOTDESC:
13712 case BFD_RELOC_386_TLS_DESC_CALL:
13713 case BFD_RELOC_X86_64_TLSGD:
13714 case BFD_RELOC_X86_64_TLSLD:
13715 case BFD_RELOC_X86_64_DTPOFF32:
13716 case BFD_RELOC_X86_64_DTPOFF64:
13717 case BFD_RELOC_X86_64_GOTTPOFF:
13718 case BFD_RELOC_X86_64_TPOFF32:
13719 case BFD_RELOC_X86_64_TPOFF64:
13720 case BFD_RELOC_X86_64_GOTOFF64:
13721 case BFD_RELOC_X86_64_GOTPC32:
13722 case BFD_RELOC_X86_64_GOT64:
13723 case BFD_RELOC_X86_64_GOTPCREL64:
13724 case BFD_RELOC_X86_64_GOTPC64:
13725 case BFD_RELOC_X86_64_GOTPLT64:
13726 case BFD_RELOC_X86_64_PLTOFF64:
13727 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
13728 case BFD_RELOC_X86_64_TLSDESC_CALL:
13729 case BFD_RELOC_RVA:
13730 case BFD_RELOC_VTABLE_ENTRY:
13731 case BFD_RELOC_VTABLE_INHERIT:
13732 #ifdef TE_PE
13733 case BFD_RELOC_32_SECREL:
13734 #endif
13735 code = fixp->fx_r_type;
13736 break;
13737 case BFD_RELOC_X86_64_32S:
13738 if (!fixp->fx_pcrel)
13739 {
13740 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13741 code = fixp->fx_r_type;
13742 break;
13743 }
13744 /* Fall through. */
13745 default:
13746 if (fixp->fx_pcrel)
13747 {
13748 switch (fixp->fx_size)
13749 {
13750 default:
13751 as_bad_where (fixp->fx_file, fixp->fx_line,
13752 _("can not do %d byte pc-relative relocation"),
13753 fixp->fx_size);
13754 code = BFD_RELOC_32_PCREL;
13755 break;
13756 case 1: code = BFD_RELOC_8_PCREL; break;
13757 case 2: code = BFD_RELOC_16_PCREL; break;
13758 case 4: code = BFD_RELOC_32_PCREL; break;
13759 #ifdef BFD64
13760 case 8: code = BFD_RELOC_64_PCREL; break;
13761 #endif
13762 }
13763 }
13764 else
13765 {
13766 switch (fixp->fx_size)
13767 {
13768 default:
13769 as_bad_where (fixp->fx_file, fixp->fx_line,
13770 _("can not do %d byte relocation"),
13771 fixp->fx_size);
13772 code = BFD_RELOC_32;
13773 break;
13774 case 1: code = BFD_RELOC_8; break;
13775 case 2: code = BFD_RELOC_16; break;
13776 case 4: code = BFD_RELOC_32; break;
13777 #ifdef BFD64
13778 case 8: code = BFD_RELOC_64; break;
13779 #endif
13780 }
13781 }
13782 break;
13783 }
13784
13785 if ((code == BFD_RELOC_32
13786 || code == BFD_RELOC_32_PCREL
13787 || code == BFD_RELOC_X86_64_32S)
13788 && GOT_symbol
13789 && fixp->fx_addsy == GOT_symbol)
13790 {
13791 if (!object_64bit)
13792 code = BFD_RELOC_386_GOTPC;
13793 else
13794 code = BFD_RELOC_X86_64_GOTPC32;
13795 }
13796 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
13797 && GOT_symbol
13798 && fixp->fx_addsy == GOT_symbol)
13799 {
13800 code = BFD_RELOC_X86_64_GOTPC64;
13801 }
13802
13803 rel = XNEW (arelent);
13804 rel->sym_ptr_ptr = XNEW (asymbol *);
13805 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13806
13807 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
13808
13809 if (!use_rela_relocations)
13810 {
13811 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13812 vtable entry to be used in the relocation's section offset. */
13813 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13814 rel->address = fixp->fx_offset;
13815 #if defined (OBJ_COFF) && defined (TE_PE)
13816 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
13817 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
13818 else
13819 #endif
13820 rel->addend = 0;
13821 }
13822 /* Use the rela in 64bit mode. */
13823 else
13824 {
13825 if (disallow_64bit_reloc)
13826 switch (code)
13827 {
13828 case BFD_RELOC_X86_64_DTPOFF64:
13829 case BFD_RELOC_X86_64_TPOFF64:
13830 case BFD_RELOC_64_PCREL:
13831 case BFD_RELOC_X86_64_GOTOFF64:
13832 case BFD_RELOC_X86_64_GOT64:
13833 case BFD_RELOC_X86_64_GOTPCREL64:
13834 case BFD_RELOC_X86_64_GOTPC64:
13835 case BFD_RELOC_X86_64_GOTPLT64:
13836 case BFD_RELOC_X86_64_PLTOFF64:
13837 as_bad_where (fixp->fx_file, fixp->fx_line,
13838 _("cannot represent relocation type %s in x32 mode"),
13839 bfd_get_reloc_code_name (code));
13840 break;
13841 default:
13842 break;
13843 }
13844
13845 if (!fixp->fx_pcrel)
13846 rel->addend = fixp->fx_offset;
13847 else
13848 switch (code)
13849 {
13850 case BFD_RELOC_X86_64_PLT32:
13851 case BFD_RELOC_X86_64_GOT32:
13852 case BFD_RELOC_X86_64_GOTPCREL:
13853 case BFD_RELOC_X86_64_GOTPCRELX:
13854 case BFD_RELOC_X86_64_REX_GOTPCRELX:
13855 case BFD_RELOC_X86_64_TLSGD:
13856 case BFD_RELOC_X86_64_TLSLD:
13857 case BFD_RELOC_X86_64_GOTTPOFF:
13858 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
13859 case BFD_RELOC_X86_64_TLSDESC_CALL:
13860 rel->addend = fixp->fx_offset - fixp->fx_size;
13861 break;
13862 default:
13863 rel->addend = (section->vma
13864 - fixp->fx_size
13865 + fixp->fx_addnumber
13866 + md_pcrel_from (fixp));
13867 break;
13868 }
13869 }
13870
13871 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
13872 if (rel->howto == NULL)
13873 {
13874 as_bad_where (fixp->fx_file, fixp->fx_line,
13875 _("cannot represent relocation type %s"),
13876 bfd_get_reloc_code_name (code));
13877 /* Set howto to a garbage value so that we can keep going. */
13878 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
13879 gas_assert (rel->howto != NULL);
13880 }
13881
13882 return rel;
13883 }
13884
13885 #include "tc-i386-intel.c"
13886
13887 void
13888 tc_x86_parse_to_dw2regnum (expressionS *exp)
13889 {
13890 int saved_naked_reg;
13891 char saved_register_dot;
13892
13893 saved_naked_reg = allow_naked_reg;
13894 allow_naked_reg = 1;
13895 saved_register_dot = register_chars['.'];
13896 register_chars['.'] = '.';
13897 allow_pseudo_reg = 1;
13898 expression_and_evaluate (exp);
13899 allow_pseudo_reg = 0;
13900 register_chars['.'] = saved_register_dot;
13901 allow_naked_reg = saved_naked_reg;
13902
13903 if (exp->X_op == O_register && exp->X_add_number >= 0)
13904 {
13905 if ((addressT) exp->X_add_number < i386_regtab_size)
13906 {
13907 exp->X_op = O_constant;
13908 exp->X_add_number = i386_regtab[exp->X_add_number]
13909 .dw2_regnum[flag_code >> 1];
13910 }
13911 else
13912 exp->X_op = O_illegal;
13913 }
13914 }
13915
13916 void
13917 tc_x86_frame_initial_instructions (void)
13918 {
13919 static unsigned int sp_regno[2];
13920
13921 if (!sp_regno[flag_code >> 1])
13922 {
13923 char *saved_input = input_line_pointer;
13924 char sp[][4] = {"esp", "rsp"};
13925 expressionS exp;
13926
13927 input_line_pointer = sp[flag_code >> 1];
13928 tc_x86_parse_to_dw2regnum (&exp);
13929 gas_assert (exp.X_op == O_constant);
13930 sp_regno[flag_code >> 1] = exp.X_add_number;
13931 input_line_pointer = saved_input;
13932 }
13933
13934 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
13935 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
13936 }
13937
13938 int
13939 x86_dwarf2_addr_size (void)
13940 {
13941 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13942 if (x86_elf_abi == X86_64_X32_ABI)
13943 return 4;
13944 #endif
13945 return bfd_arch_bits_per_address (stdoutput) / 8;
13946 }
13947
13948 int
13949 i386_elf_section_type (const char *str, size_t len)
13950 {
13951 if (flag_code == CODE_64BIT
13952 && len == sizeof ("unwind") - 1
13953 && strncmp (str, "unwind", 6) == 0)
13954 return SHT_X86_64_UNWIND;
13955
13956 return -1;
13957 }
13958
13959 #ifdef TE_SOLARIS
13960 void
13961 i386_solaris_fix_up_eh_frame (segT sec)
13962 {
13963 if (flag_code == CODE_64BIT)
13964 elf_section_type (sec) = SHT_X86_64_UNWIND;
13965 }
13966 #endif
13967
13968 #ifdef TE_PE
13969 void
13970 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
13971 {
13972 expressionS exp;
13973
13974 exp.X_op = O_secrel;
13975 exp.X_add_symbol = symbol;
13976 exp.X_add_number = 0;
13977 emit_expr (&exp, size);
13978 }
13979 #endif
13980
13981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13982 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13983
13984 bfd_vma
13985 x86_64_section_letter (int letter, const char **ptr_msg)
13986 {
13987 if (flag_code == CODE_64BIT)
13988 {
13989 if (letter == 'l')
13990 return SHF_X86_64_LARGE;
13991
13992 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13993 }
13994 else
13995 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
13996 return -1;
13997 }
13998
13999 bfd_vma
14000 x86_64_section_word (char *str, size_t len)
14001 {
14002 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
14003 return SHF_X86_64_LARGE;
14004
14005 return -1;
14006 }
14007
14008 static void
14009 handle_large_common (int small ATTRIBUTE_UNUSED)
14010 {
14011 if (flag_code != CODE_64BIT)
14012 {
14013 s_comm_internal (0, elf_common_parse);
14014 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14015 }
14016 else
14017 {
14018 static segT lbss_section;
14019 asection *saved_com_section_ptr = elf_com_section_ptr;
14020 asection *saved_bss_section = bss_section;
14021
14022 if (lbss_section == NULL)
14023 {
14024 flagword applicable;
14025 segT seg = now_seg;
14026 subsegT subseg = now_subseg;
14027
14028 /* The .lbss section is for local .largecomm symbols. */
14029 lbss_section = subseg_new (".lbss", 0);
14030 applicable = bfd_applicable_section_flags (stdoutput);
14031 bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC);
14032 seg_info (lbss_section)->bss = 1;
14033
14034 subseg_set (seg, subseg);
14035 }
14036
14037 elf_com_section_ptr = &_bfd_elf_large_com_section;
14038 bss_section = lbss_section;
14039
14040 s_comm_internal (0, elf_common_parse);
14041
14042 elf_com_section_ptr = saved_com_section_ptr;
14043 bss_section = saved_bss_section;
14044 }
14045 }
14046 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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