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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 };
285
286 struct _i386_insn
287 {
288 /* TM holds the template for the insn were currently assembling. */
289 insn_template tm;
290
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
293 char suffix;
294
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
300 operands. */
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
306
307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
310
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
314
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
317
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
327
328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
338 modrm_byte rm;
339 rex_byte rex;
340 rex_byte vrex;
341 sib_byte sib;
342 vex_prefix vex;
343
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
363
364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
371
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
374
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
377
378 /* How to encode vector instructions. */
379 enum
380 {
381 vex_encoding_default = 0,
382 vex_encoding_vex2,
383 vex_encoding_vex3,
384 vex_encoding_evex
385 } vec_encoding;
386
387 /* REP prefix. */
388 const char *rep_prefix;
389
390 /* HLE prefix. */
391 const char *hle_prefix;
392
393 /* Have BND prefix. */
394 const char *bnd_prefix;
395
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
398
399 /* Error message. */
400 enum i386_error error;
401 };
402
403 typedef struct _i386_insn i386_insn;
404
405 /* Link RC type with corresponding string, that'll be looked for in
406 asm. */
407 struct RC_name
408 {
409 enum rc_type type;
410 const char *name;
411 unsigned int len;
412 };
413
414 static const struct RC_name RC_NamesTable[] =
415 {
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
421 };
422
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars[] = "*%-([{}"
426 #ifdef LEX_AT
427 "@"
428 #endif
429 #ifdef LEX_QM
430 "?"
431 #endif
432 ;
433
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars = "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
449
450 #else
451 const char *i386_comment_chars = "#";
452 #define PREFIX_SEPARATOR '/'
453 #endif
454
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars[] = "#/";
464
465 const char line_separator_chars[] = ";";
466
467 /* Chars that can be used to separate mant from exp in floating point
468 nums. */
469 const char EXP_CHARS[] = "eE";
470
471 /* Chars that mean this number is a floating point constant
472 As in 0f12.456
473 or 0d1.2345e12. */
474 const char FLT_CHARS[] = "fFdDxX";
475
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars[256];
478 static char register_chars[256];
479 static char operand_chars[256];
480 static char identifier_chars[256];
481 static char digit_chars[256];
482
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
490
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
493
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack[32];
499 static char *save_stack_p;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
504
505 /* The instruction we're assembling. */
506 static i386_insn i;
507
508 /* Possible templates for current insn. */
509 static const templates *current_templates;
510
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
514
515 /* Current operand we are working on. */
516 static int this_operand = -1;
517
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
519 these. */
520
521 enum flag_code {
522 CODE_32BIT,
523 CODE_16BIT,
524 CODE_64BIT };
525
526 static enum flag_code flag_code;
527 static unsigned int object_64bit;
528 static unsigned int disallow_64bit_reloc;
529 static int use_rela_relocations = 0;
530
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
534
535 /* The ELF ABI to use. */
536 enum x86_elf_abi
537 {
538 I386_ABI,
539 X86_64_ABI,
540 X86_64_X32_ABI
541 };
542
543 static enum x86_elf_abi x86_elf_abi = I386_ABI;
544 #endif
545
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj = 0;
549 #endif
550
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared = 0;
554 #endif
555
556 /* 1 for intel syntax,
557 0 if att syntax. */
558 static int intel_syntax = 0;
559
560 /* 1 for Intel64 ISA,
561 0 if AMD64 ISA. */
562 static int intel64;
563
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic = !SYSV386_COMPAT;
567
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc = OLDGCC_COMPAT;
570
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg = 0;
573
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg = 0;
576
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
579 explicitly. */
580 static int add_bnd_prefix = 0;
581
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg = 0;
584
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix = 0;
588
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence = 0;
592
593 /* 1 if the assembler should generate relax relocations. */
594
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
597
598 static enum check_kind
599 {
600 check_none = 0,
601 check_warning,
602 check_error
603 }
604 sse_check, operand_check = check_warning;
605
606 /* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 */
611 static int optimize = 0;
612
613 /* Optimization:
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
616 register.
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
618 "testb $imm7,%r8".
619 */
620 static int optimize_for_space = 0;
621
622 /* Register prefix used for error message. */
623 static const char *register_prefix = "%";
624
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size = '\0';
629
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code = 1;
632
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings = 0;
635
636 /* CPU name. */
637 static const char *cpu_arch_name = NULL;
638 static char *cpu_sub_arch_name = NULL;
639
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
642
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set = 0;
645
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
648
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags;
651
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
654
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags;
657
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion = 0;
661
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx;
664
665 /* Encode scalar AVX instructions with specific vector length. */
666 static enum
667 {
668 vex128 = 0,
669 vex256
670 } avxscalar;
671
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 static enum
674 {
675 evexl128 = 0,
676 evexl256,
677 evexl512
678 } evexlig;
679
680 /* Encode EVEX WIG instructions with specific evex.w. */
681 static enum
682 {
683 evexw0 = 0,
684 evexw1
685 } evexwig;
686
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig = rne;
689
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS *GOT_symbol;
692
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column;
695
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment;
698
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
703
704 /* Types. */
705 #define UNCOND_JUMP 0
706 #define COND_JUMP 1
707 #define COND_JUMP86 2
708
709 /* Sizes. */
710 #define CODE16 1
711 #define SMALL 0
712 #define SMALL16 (SMALL | CODE16)
713 #define BIG 2
714 #define BIG16 (BIG | CODE16)
715
716 #ifndef INLINE
717 #ifdef __GNUC__
718 #define INLINE __inline__
719 #else
720 #define INLINE
721 #endif
722 #endif
723
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
727 ((s) >> 2)
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
730
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
738
739 const relax_typeS md_relax_table[] =
740 {
741 /* The fields are:
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
746
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
752 {0, 0, 4, 0},
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
755 {0, 0, 2, 0},
756
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
762 {0, 0, 5, 0},
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
765 {0, 0, 3, 0},
766
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
772 {0, 0, 5, 0},
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
775 {0, 0, 4, 0}
776 };
777
778 static const arch_entry cpu_arch[] =
779 {
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
783 CPU_GENERIC32_FLAGS, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
785 CPU_GENERIC64_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
787 CPU_NONE_FLAGS, 0 },
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
789 CPU_I186_FLAGS, 0 },
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
791 CPU_I286_FLAGS, 0 },
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
793 CPU_I386_FLAGS, 0 },
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
795 CPU_I486_FLAGS, 0 },
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
797 CPU_I586_FLAGS, 0 },
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
799 CPU_I686_FLAGS, 0 },
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
801 CPU_I586_FLAGS, 0 },
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
803 CPU_PENTIUMPRO_FLAGS, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
805 CPU_P2_FLAGS, 0 },
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
807 CPU_P3_FLAGS, 0 },
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
809 CPU_P4_FLAGS, 0 },
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
811 CPU_CORE_FLAGS, 0 },
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
813 CPU_NOCONA_FLAGS, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
815 CPU_CORE_FLAGS, 1 },
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
817 CPU_CORE_FLAGS, 0 },
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
819 CPU_CORE2_FLAGS, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
821 CPU_CORE2_FLAGS, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
823 CPU_COREI7_FLAGS, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
825 CPU_L1OM_FLAGS, 0 },
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
827 CPU_K1OM_FLAGS, 0 },
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
829 CPU_IAMCU_FLAGS, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
831 CPU_K6_FLAGS, 0 },
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
833 CPU_K6_2_FLAGS, 0 },
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
835 CPU_ATHLON_FLAGS, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
837 CPU_K8_FLAGS, 1 },
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
839 CPU_K8_FLAGS, 0 },
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
841 CPU_K8_FLAGS, 0 },
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
843 CPU_AMDFAM10_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
845 CPU_BDVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
847 CPU_BDVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
849 CPU_BDVER3_FLAGS, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
851 CPU_BDVER4_FLAGS, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
853 CPU_ZNVER1_FLAGS, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
855 CPU_BTVER1_FLAGS, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
857 CPU_BTVER2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
859 CPU_8087_FLAGS, 0 },
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
861 CPU_287_FLAGS, 0 },
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
863 CPU_387_FLAGS, 0 },
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
865 CPU_687_FLAGS, 0 },
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
867 CPU_MMX_FLAGS, 0 },
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
869 CPU_SSE_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
871 CPU_SSE2_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
873 CPU_SSE3_FLAGS, 0 },
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
875 CPU_SSSE3_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_1_FLAGS, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
879 CPU_SSE4_2_FLAGS, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
881 CPU_SSE4_2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
883 CPU_AVX_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
885 CPU_AVX2_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
887 CPU_AVX512F_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
889 CPU_AVX512CD_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
891 CPU_AVX512ER_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
893 CPU_AVX512PF_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
895 CPU_AVX512DQ_FLAGS, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
897 CPU_AVX512BW_FLAGS, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
899 CPU_AVX512VL_FLAGS, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
901 CPU_VMX_FLAGS, 0 },
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
903 CPU_VMFUNC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
905 CPU_SMX_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
907 CPU_XSAVE_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
909 CPU_XSAVEOPT_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
911 CPU_XSAVEC_FLAGS, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
913 CPU_XSAVES_FLAGS, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
915 CPU_AES_FLAGS, 0 },
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
917 CPU_PCLMUL_FLAGS, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
919 CPU_PCLMUL_FLAGS, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
921 CPU_FSGSBASE_FLAGS, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
923 CPU_RDRND_FLAGS, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
925 CPU_F16C_FLAGS, 0 },
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
927 CPU_BMI2_FLAGS, 0 },
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
929 CPU_FMA_FLAGS, 0 },
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
931 CPU_FMA4_FLAGS, 0 },
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
933 CPU_XOP_FLAGS, 0 },
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
935 CPU_LWP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
937 CPU_MOVBE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
939 CPU_CX16_FLAGS, 0 },
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
941 CPU_EPT_FLAGS, 0 },
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
943 CPU_LZCNT_FLAGS, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
945 CPU_HLE_FLAGS, 0 },
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
947 CPU_RTM_FLAGS, 0 },
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
949 CPU_INVPCID_FLAGS, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
951 CPU_CLFLUSH_FLAGS, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
953 CPU_NOP_FLAGS, 0 },
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
955 CPU_SYSCALL_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
957 CPU_RDTSCP_FLAGS, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
959 CPU_3DNOW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
961 CPU_3DNOWA_FLAGS, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
963 CPU_PADLOCK_FLAGS, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
965 CPU_SVME_FLAGS, 1 },
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
967 CPU_SVME_FLAGS, 0 },
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
969 CPU_SSE4A_FLAGS, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
971 CPU_ABM_FLAGS, 0 },
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
973 CPU_BMI_FLAGS, 0 },
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
975 CPU_TBM_FLAGS, 0 },
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
977 CPU_ADX_FLAGS, 0 },
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
979 CPU_RDSEED_FLAGS, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
981 CPU_PRFCHW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
983 CPU_SMAP_FLAGS, 0 },
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
985 CPU_MPX_FLAGS, 0 },
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
987 CPU_SHA_FLAGS, 0 },
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
989 CPU_CLFLUSHOPT_FLAGS, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
991 CPU_PREFETCHWT1_FLAGS, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
993 CPU_SE1_FLAGS, 0 },
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
995 CPU_CLWB_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
997 CPU_AVX512IFMA_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
999 CPU_AVX512VBMI_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1013 CPU_CLZERO_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1015 CPU_MWAITX_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1017 CPU_OSPKE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1019 CPU_RDPID_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1023 CPU_IBT_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
1036 };
1037
1038 static const noarch_entry cpu_noarch[] =
1039 {
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1071 };
1072
1073 #ifdef I386COFF
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1076
1077 static symbolS *
1078 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1079 {
1080 addressT align = 0;
1081
1082 SKIP_WHITESPACE ();
1083
1084 if (needs_align
1085 && *input_line_pointer == ',')
1086 {
1087 align = parse_align (needs_align - 1);
1088
1089 if (align == (addressT) -1)
1090 return NULL;
1091 }
1092 else
1093 {
1094 if (size >= 8)
1095 align = 3;
1096 else if (size >= 4)
1097 align = 2;
1098 else if (size >= 2)
1099 align = 1;
1100 else
1101 align = 0;
1102 }
1103
1104 bss_alloc (symbolP, size, align);
1105 return symbolP;
1106 }
1107
1108 static void
1109 pe_lcomm (int needs_align)
1110 {
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1112 }
1113 #endif
1114
1115 const pseudo_typeS md_pseudo_table[] =
1116 {
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1119 #else
1120 {"align", s_align_ptwo, 0},
1121 #endif
1122 {"arch", set_cpu_arch, 0},
1123 #ifndef I386COFF
1124 {"bss", s_bss, 0},
1125 #else
1126 {"lcomm", pe_lcomm, 1},
1127 #endif
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1131 {"value", cons, 2},
1132 {"slong", signed_cons, 4},
1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
1138 #ifdef BFD64
1139 {"code64", set_code_flag, CODE_64BIT},
1140 #endif
1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
1151 #else
1152 {"file", dwarf2_directive_file, 0},
1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1155 #endif
1156 #ifdef TE_PE
1157 {"secrel32", pe_directive_secrel, 0},
1158 #endif
1159 {0, 0, 0}
1160 };
1161
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer;
1164
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control *op_hash;
1167
1168 /* Hash table for register lookup. */
1169 static struct hash_control *reg_hash;
1170 \f
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1[] =
1175 {0x90}; /* nop */
1176 static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_5[] =
1183 {0x90, /* nop */
1184 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1185 static const unsigned char f32_6[] =
1186 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1187 static const unsigned char f32_7[] =
1188 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1189 static const unsigned char f32_8[] =
1190 {0x90, /* nop */
1191 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1192 static const unsigned char f32_9[] =
1193 {0x89,0xf6, /* movl %esi,%esi */
1194 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1195 static const unsigned char f32_10[] =
1196 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1197 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1198 static const unsigned char f32_11[] =
1199 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1200 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1201 static const unsigned char f32_12[] =
1202 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1203 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1204 static const unsigned char f32_13[] =
1205 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1206 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1207 static const unsigned char f32_14[] =
1208 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1209 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1210 static const unsigned char f16_3[] =
1211 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1212 static const unsigned char f16_4[] =
1213 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1214 static const unsigned char f16_5[] =
1215 {0x90, /* nop */
1216 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1217 static const unsigned char f16_6[] =
1218 {0x89,0xf6, /* mov %si,%si */
1219 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1220 static const unsigned char f16_7[] =
1221 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1222 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1223 static const unsigned char f16_8[] =
1224 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1225 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1226 static const unsigned char jump_31[] =
1227 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1228 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1229 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1230 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1231 /* 32-bit NOPs patterns. */
1232 static const unsigned char *const f32_patt[] = {
1233 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1234 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1235 };
1236 /* 16-bit NOPs patterns. */
1237 static const unsigned char *const f16_patt[] = {
1238 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1239 };
1240 /* nopl (%[re]ax) */
1241 static const unsigned char alt_3[] =
1242 {0x0f,0x1f,0x00};
1243 /* nopl 0(%[re]ax) */
1244 static const unsigned char alt_4[] =
1245 {0x0f,0x1f,0x40,0x00};
1246 /* nopl 0(%[re]ax,%[re]ax,1) */
1247 static const unsigned char alt_5[] =
1248 {0x0f,0x1f,0x44,0x00,0x00};
1249 /* nopw 0(%[re]ax,%[re]ax,1) */
1250 static const unsigned char alt_6[] =
1251 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1252 /* nopl 0L(%[re]ax) */
1253 static const unsigned char alt_7[] =
1254 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1255 /* nopl 0L(%[re]ax,%[re]ax,1) */
1256 static const unsigned char alt_8[] =
1257 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1258 /* nopw 0L(%[re]ax,%[re]ax,1) */
1259 static const unsigned char alt_9[] =
1260 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1261 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1262 static const unsigned char alt_10[] =
1263 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1264 /* 32-bit and 64-bit NOPs patterns. */
1265 static const unsigned char *const alt_patt[] = {
1266 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1267 alt_9, alt_10
1268 };
1269 /* 64-bit only: nopw %cs:0L(%eax,%eax,1) */
1270 static const unsigned char alt64_11[] =
1271 {0x67,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1272 /* 64-bit NOPs patterns. */
1273 static const unsigned char *const alt64_patt[] = {
1274 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1275 alt_9, alt_10, alt64_11
1276 };
1277
1278 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1279 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1280
1281 static void
1282 i386_output_nops (char *where, const unsigned char *const *patt,
1283 int count, int max_single_nop_size)
1284
1285 {
1286 while (count > max_single_nop_size)
1287 {
1288 count -= max_single_nop_size;
1289 memcpy (where + count, patt[max_single_nop_size - 1],
1290 max_single_nop_size);
1291 }
1292
1293 if (count)
1294 memcpy (where, patt[count - 1], count);
1295 }
1296
1297
1298 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1299 single NOP instruction LIMIT. */
1300
1301 void
1302 i386_generate_nops (fragS *f, char *where, offsetT count, int limit)
1303 {
1304 /* Output NOPs for .nop directive. */
1305 int max_single_nop_size;
1306 const unsigned char *const *patt;
1307
1308 if (flag_code == CODE_16BIT)
1309 {
1310 patt = f16_patt;
1311 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1312 }
1313 else if (flag_code == CODE_64BIT)
1314 {
1315 patt = alt64_patt;
1316 max_single_nop_size = sizeof (alt64_patt) / sizeof (alt64_patt[0]);
1317 }
1318 else
1319 {
1320 patt = alt_patt;
1321 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1322 }
1323 if (limit == 0)
1324 limit = max_single_nop_size;
1325 else if (limit > max_single_nop_size)
1326 {
1327 as_bad_where (f->fr_file, f->fr_line,
1328 _("invalide single nop size: %d (expect within [0, %d])"),
1329 limit, max_single_nop_size);
1330 return;
1331 }
1332
1333 i386_output_nops (where, patt, count, limit);
1334 }
1335
1336 void
1337 i386_align_code (fragS *fragP, int count)
1338 {
1339 /* Only align for at least a positive non-zero boundary. */
1340 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1341 return;
1342
1343 /* We need to decide which NOP sequence to use for 32bit and
1344 64bit. When -mtune= is used:
1345
1346 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1347 PROCESSOR_GENERIC32, f32_patt will be used.
1348 2. For the rest, alt_patt will be used.
1349
1350 When -mtune= isn't used, alt_patt will be used if
1351 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1352 be used.
1353
1354 When -march= or .arch is used, we can't use anything beyond
1355 cpu_arch_isa_flags. */
1356
1357 if (flag_code == CODE_16BIT)
1358 {
1359 if (count > 8)
1360 {
1361 memcpy (fragP->fr_literal + fragP->fr_fix,
1362 jump_31, count);
1363 /* Adjust jump offset. */
1364 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1365 }
1366 else
1367 memcpy (fragP->fr_literal + fragP->fr_fix,
1368 f16_patt[count - 1], count);
1369 }
1370 else
1371 {
1372 const unsigned char *const *patt = NULL;
1373
1374 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1375 {
1376 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1377 switch (cpu_arch_tune)
1378 {
1379 case PROCESSOR_UNKNOWN:
1380 /* We use cpu_arch_isa_flags to check if we SHOULD
1381 optimize with nops. */
1382 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1383 patt = alt_patt;
1384 else
1385 patt = f32_patt;
1386 break;
1387 case PROCESSOR_PENTIUM4:
1388 case PROCESSOR_NOCONA:
1389 case PROCESSOR_CORE:
1390 case PROCESSOR_CORE2:
1391 case PROCESSOR_COREI7:
1392 case PROCESSOR_L1OM:
1393 case PROCESSOR_K1OM:
1394 case PROCESSOR_GENERIC64:
1395 case PROCESSOR_K6:
1396 case PROCESSOR_ATHLON:
1397 case PROCESSOR_K8:
1398 case PROCESSOR_AMDFAM10:
1399 case PROCESSOR_BD:
1400 case PROCESSOR_ZNVER:
1401 case PROCESSOR_BT:
1402 patt = alt_patt;
1403 break;
1404 case PROCESSOR_I386:
1405 case PROCESSOR_I486:
1406 case PROCESSOR_PENTIUM:
1407 case PROCESSOR_PENTIUMPRO:
1408 case PROCESSOR_IAMCU:
1409 case PROCESSOR_GENERIC32:
1410 patt = f32_patt;
1411 break;
1412 }
1413 }
1414 else
1415 {
1416 switch (fragP->tc_frag_data.tune)
1417 {
1418 case PROCESSOR_UNKNOWN:
1419 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1420 PROCESSOR_UNKNOWN. */
1421 abort ();
1422 break;
1423
1424 case PROCESSOR_I386:
1425 case PROCESSOR_I486:
1426 case PROCESSOR_PENTIUM:
1427 case PROCESSOR_IAMCU:
1428 case PROCESSOR_K6:
1429 case PROCESSOR_ATHLON:
1430 case PROCESSOR_K8:
1431 case PROCESSOR_AMDFAM10:
1432 case PROCESSOR_BD:
1433 case PROCESSOR_ZNVER:
1434 case PROCESSOR_BT:
1435 case PROCESSOR_GENERIC32:
1436 /* We use cpu_arch_isa_flags to check if we CAN optimize
1437 with nops. */
1438 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1439 patt = alt_patt;
1440 else
1441 patt = f32_patt;
1442 break;
1443 case PROCESSOR_PENTIUMPRO:
1444 case PROCESSOR_PENTIUM4:
1445 case PROCESSOR_NOCONA:
1446 case PROCESSOR_CORE:
1447 case PROCESSOR_CORE2:
1448 case PROCESSOR_COREI7:
1449 case PROCESSOR_L1OM:
1450 case PROCESSOR_K1OM:
1451 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1452 patt = alt_patt;
1453 else
1454 patt = f32_patt;
1455 break;
1456 case PROCESSOR_GENERIC64:
1457 patt = alt_patt;
1458 break;
1459 }
1460 }
1461
1462 if (patt == f32_patt)
1463 {
1464 /* If the padding is less than 15 bytes, we use the normal
1465 ones. Otherwise, we use a jump instruction and adjust
1466 its offset. */
1467 int limit;
1468
1469 /* For 64bit, the limit is 3 bytes. */
1470 if (flag_code == CODE_64BIT
1471 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1472 limit = 3;
1473 else
1474 limit = 15;
1475 if (count < limit)
1476 memcpy (fragP->fr_literal + fragP->fr_fix,
1477 patt[count - 1], count);
1478 else
1479 {
1480 memcpy (fragP->fr_literal + fragP->fr_fix,
1481 jump_31, count);
1482 /* Adjust jump offset. */
1483 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1484 }
1485 }
1486 else
1487 {
1488 /* Maximum length of an instruction is 10 byte. If the
1489 padding is greater than 10 bytes and we don't use jump,
1490 we have to break it into smaller pieces. */
1491 i386_output_nops (fragP->fr_literal + fragP->fr_fix,
1492 patt, count, 10);
1493 }
1494 }
1495 fragP->fr_var = count;
1496 }
1497
1498 static INLINE int
1499 operand_type_all_zero (const union i386_operand_type *x)
1500 {
1501 switch (ARRAY_SIZE(x->array))
1502 {
1503 case 3:
1504 if (x->array[2])
1505 return 0;
1506 /* Fall through. */
1507 case 2:
1508 if (x->array[1])
1509 return 0;
1510 /* Fall through. */
1511 case 1:
1512 return !x->array[0];
1513 default:
1514 abort ();
1515 }
1516 }
1517
1518 static INLINE void
1519 operand_type_set (union i386_operand_type *x, unsigned int v)
1520 {
1521 switch (ARRAY_SIZE(x->array))
1522 {
1523 case 3:
1524 x->array[2] = v;
1525 /* Fall through. */
1526 case 2:
1527 x->array[1] = v;
1528 /* Fall through. */
1529 case 1:
1530 x->array[0] = v;
1531 /* Fall through. */
1532 break;
1533 default:
1534 abort ();
1535 }
1536 }
1537
1538 static INLINE int
1539 operand_type_equal (const union i386_operand_type *x,
1540 const union i386_operand_type *y)
1541 {
1542 switch (ARRAY_SIZE(x->array))
1543 {
1544 case 3:
1545 if (x->array[2] != y->array[2])
1546 return 0;
1547 /* Fall through. */
1548 case 2:
1549 if (x->array[1] != y->array[1])
1550 return 0;
1551 /* Fall through. */
1552 case 1:
1553 return x->array[0] == y->array[0];
1554 break;
1555 default:
1556 abort ();
1557 }
1558 }
1559
1560 static INLINE int
1561 cpu_flags_all_zero (const union i386_cpu_flags *x)
1562 {
1563 switch (ARRAY_SIZE(x->array))
1564 {
1565 case 4:
1566 if (x->array[3])
1567 return 0;
1568 /* Fall through. */
1569 case 3:
1570 if (x->array[2])
1571 return 0;
1572 /* Fall through. */
1573 case 2:
1574 if (x->array[1])
1575 return 0;
1576 /* Fall through. */
1577 case 1:
1578 return !x->array[0];
1579 default:
1580 abort ();
1581 }
1582 }
1583
1584 static INLINE int
1585 cpu_flags_equal (const union i386_cpu_flags *x,
1586 const union i386_cpu_flags *y)
1587 {
1588 switch (ARRAY_SIZE(x->array))
1589 {
1590 case 4:
1591 if (x->array[3] != y->array[3])
1592 return 0;
1593 /* Fall through. */
1594 case 3:
1595 if (x->array[2] != y->array[2])
1596 return 0;
1597 /* Fall through. */
1598 case 2:
1599 if (x->array[1] != y->array[1])
1600 return 0;
1601 /* Fall through. */
1602 case 1:
1603 return x->array[0] == y->array[0];
1604 break;
1605 default:
1606 abort ();
1607 }
1608 }
1609
1610 static INLINE int
1611 cpu_flags_check_cpu64 (i386_cpu_flags f)
1612 {
1613 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1614 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1615 }
1616
1617 static INLINE i386_cpu_flags
1618 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1619 {
1620 switch (ARRAY_SIZE (x.array))
1621 {
1622 case 4:
1623 x.array [3] &= y.array [3];
1624 /* Fall through. */
1625 case 3:
1626 x.array [2] &= y.array [2];
1627 /* Fall through. */
1628 case 2:
1629 x.array [1] &= y.array [1];
1630 /* Fall through. */
1631 case 1:
1632 x.array [0] &= y.array [0];
1633 break;
1634 default:
1635 abort ();
1636 }
1637 return x;
1638 }
1639
1640 static INLINE i386_cpu_flags
1641 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1642 {
1643 switch (ARRAY_SIZE (x.array))
1644 {
1645 case 4:
1646 x.array [3] |= y.array [3];
1647 /* Fall through. */
1648 case 3:
1649 x.array [2] |= y.array [2];
1650 /* Fall through. */
1651 case 2:
1652 x.array [1] |= y.array [1];
1653 /* Fall through. */
1654 case 1:
1655 x.array [0] |= y.array [0];
1656 break;
1657 default:
1658 abort ();
1659 }
1660 return x;
1661 }
1662
1663 static INLINE i386_cpu_flags
1664 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1665 {
1666 switch (ARRAY_SIZE (x.array))
1667 {
1668 case 4:
1669 x.array [3] &= ~y.array [3];
1670 /* Fall through. */
1671 case 3:
1672 x.array [2] &= ~y.array [2];
1673 /* Fall through. */
1674 case 2:
1675 x.array [1] &= ~y.array [1];
1676 /* Fall through. */
1677 case 1:
1678 x.array [0] &= ~y.array [0];
1679 break;
1680 default:
1681 abort ();
1682 }
1683 return x;
1684 }
1685
1686 #define CPU_FLAGS_ARCH_MATCH 0x1
1687 #define CPU_FLAGS_64BIT_MATCH 0x2
1688 #define CPU_FLAGS_AES_MATCH 0x4
1689 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1690 #define CPU_FLAGS_AVX_MATCH 0x10
1691
1692 #define CPU_FLAGS_32BIT_MATCH \
1693 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1694 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1697
1698 /* Return CPU flags match bits. */
1699
1700 static int
1701 cpu_flags_match (const insn_template *t)
1702 {
1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1705
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1708
1709 if (cpu_flags_all_zero (&x))
1710 {
1711 /* This instruction is available on all archs. */
1712 match |= CPU_FLAGS_32BIT_MATCH;
1713 }
1714 else
1715 {
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu = cpu_arch_flags;
1718
1719 cpu = cpu_flags_and (x, cpu);
1720 if (!cpu_flags_all_zero (&cpu))
1721 {
1722 if (x.bitfield.cpuavx)
1723 {
1724 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1725 if (cpu.bitfield.cpuavx)
1726 {
1727 /* Check SSE2AVX. */
1728 if (!t->opcode_modifier.sse2avx|| sse2avx)
1729 {
1730 match |= (CPU_FLAGS_ARCH_MATCH
1731 | CPU_FLAGS_AVX_MATCH);
1732 /* Check AES. */
1733 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1734 match |= CPU_FLAGS_AES_MATCH;
1735 /* Check PCLMUL. */
1736 if (!x.bitfield.cpupclmul
1737 || cpu.bitfield.cpupclmul)
1738 match |= CPU_FLAGS_PCLMUL_MATCH;
1739 }
1740 }
1741 else
1742 match |= CPU_FLAGS_ARCH_MATCH;
1743 }
1744 else if (x.bitfield.cpuavx512vl)
1745 {
1746 /* Match AVX512VL. */
1747 if (cpu.bitfield.cpuavx512vl)
1748 {
1749 /* Need another match. */
1750 cpu.bitfield.cpuavx512vl = 0;
1751 if (!cpu_flags_all_zero (&cpu))
1752 match |= CPU_FLAGS_32BIT_MATCH;
1753 else
1754 match |= CPU_FLAGS_ARCH_MATCH;
1755 }
1756 else
1757 match |= CPU_FLAGS_ARCH_MATCH;
1758 }
1759 else
1760 match |= CPU_FLAGS_32BIT_MATCH;
1761 }
1762 }
1763 return match;
1764 }
1765
1766 static INLINE i386_operand_type
1767 operand_type_and (i386_operand_type x, i386_operand_type y)
1768 {
1769 switch (ARRAY_SIZE (x.array))
1770 {
1771 case 3:
1772 x.array [2] &= y.array [2];
1773 /* Fall through. */
1774 case 2:
1775 x.array [1] &= y.array [1];
1776 /* Fall through. */
1777 case 1:
1778 x.array [0] &= y.array [0];
1779 break;
1780 default:
1781 abort ();
1782 }
1783 return x;
1784 }
1785
1786 static INLINE i386_operand_type
1787 operand_type_or (i386_operand_type x, i386_operand_type y)
1788 {
1789 switch (ARRAY_SIZE (x.array))
1790 {
1791 case 3:
1792 x.array [2] |= y.array [2];
1793 /* Fall through. */
1794 case 2:
1795 x.array [1] |= y.array [1];
1796 /* Fall through. */
1797 case 1:
1798 x.array [0] |= y.array [0];
1799 break;
1800 default:
1801 abort ();
1802 }
1803 return x;
1804 }
1805
1806 static INLINE i386_operand_type
1807 operand_type_xor (i386_operand_type x, i386_operand_type y)
1808 {
1809 switch (ARRAY_SIZE (x.array))
1810 {
1811 case 3:
1812 x.array [2] ^= y.array [2];
1813 /* Fall through. */
1814 case 2:
1815 x.array [1] ^= y.array [1];
1816 /* Fall through. */
1817 case 1:
1818 x.array [0] ^= y.array [0];
1819 break;
1820 default:
1821 abort ();
1822 }
1823 return x;
1824 }
1825
1826 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1827 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1828 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1829 static const i386_operand_type inoutportreg
1830 = OPERAND_TYPE_INOUTPORTREG;
1831 static const i386_operand_type reg16_inoutportreg
1832 = OPERAND_TYPE_REG16_INOUTPORTREG;
1833 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1834 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1835 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1836 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1837 static const i386_operand_type anydisp
1838 = OPERAND_TYPE_ANYDISP;
1839 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1840 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1841 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1842 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1843 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1844 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1845 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1846 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1847 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1848 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1849 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1850 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1851
1852 enum operand_type
1853 {
1854 reg,
1855 imm,
1856 disp,
1857 anymem
1858 };
1859
1860 static INLINE int
1861 operand_type_check (i386_operand_type t, enum operand_type c)
1862 {
1863 switch (c)
1864 {
1865 case reg:
1866 return t.bitfield.reg;
1867
1868 case imm:
1869 return (t.bitfield.imm8
1870 || t.bitfield.imm8s
1871 || t.bitfield.imm16
1872 || t.bitfield.imm32
1873 || t.bitfield.imm32s
1874 || t.bitfield.imm64);
1875
1876 case disp:
1877 return (t.bitfield.disp8
1878 || t.bitfield.disp16
1879 || t.bitfield.disp32
1880 || t.bitfield.disp32s
1881 || t.bitfield.disp64);
1882
1883 case anymem:
1884 return (t.bitfield.disp8
1885 || t.bitfield.disp16
1886 || t.bitfield.disp32
1887 || t.bitfield.disp32s
1888 || t.bitfield.disp64
1889 || t.bitfield.baseindex);
1890
1891 default:
1892 abort ();
1893 }
1894
1895 return 0;
1896 }
1897
1898 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1899 operand J for instruction template T. */
1900
1901 static INLINE int
1902 match_reg_size (const insn_template *t, unsigned int j)
1903 {
1904 return !((i.types[j].bitfield.byte
1905 && !t->operand_types[j].bitfield.byte)
1906 || (i.types[j].bitfield.word
1907 && !t->operand_types[j].bitfield.word)
1908 || (i.types[j].bitfield.dword
1909 && !t->operand_types[j].bitfield.dword)
1910 || (i.types[j].bitfield.qword
1911 && !t->operand_types[j].bitfield.qword)
1912 || (i.types[j].bitfield.tbyte
1913 && !t->operand_types[j].bitfield.tbyte));
1914 }
1915
1916 /* Return 1 if there is no conflict in SIMD register on
1917 operand J for instruction template T. */
1918
1919 static INLINE int
1920 match_simd_size (const insn_template *t, unsigned int j)
1921 {
1922 return !((i.types[j].bitfield.xmmword
1923 && !t->operand_types[j].bitfield.xmmword)
1924 || (i.types[j].bitfield.ymmword
1925 && !t->operand_types[j].bitfield.ymmword)
1926 || (i.types[j].bitfield.zmmword
1927 && !t->operand_types[j].bitfield.zmmword));
1928 }
1929
1930 /* Return 1 if there is no conflict in any size on operand J for
1931 instruction template T. */
1932
1933 static INLINE int
1934 match_mem_size (const insn_template *t, unsigned int j)
1935 {
1936 return (match_reg_size (t, j)
1937 && !((i.types[j].bitfield.unspecified
1938 && !i.broadcast
1939 && !t->operand_types[j].bitfield.unspecified)
1940 || (i.types[j].bitfield.fword
1941 && !t->operand_types[j].bitfield.fword)
1942 /* For scalar opcode templates to allow register and memory
1943 operands at the same time, some special casing is needed
1944 here. */
1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
1947 && (t->operand_types[j].bitfield.dword
1948 || t->operand_types[j].bitfield.qword))
1949 ? (i.types[j].bitfield.xmmword
1950 || i.types[j].bitfield.ymmword
1951 || i.types[j].bitfield.zmmword)
1952 : !match_simd_size(t, j))));
1953 }
1954
1955 /* Return 1 if there is no size conflict on any operands for
1956 instruction template T. */
1957
1958 static INLINE int
1959 operand_size_match (const insn_template *t)
1960 {
1961 unsigned int j;
1962 int match = 1;
1963
1964 /* Don't check jump instructions. */
1965 if (t->opcode_modifier.jump
1966 || t->opcode_modifier.jumpbyte
1967 || t->opcode_modifier.jumpdword
1968 || t->opcode_modifier.jumpintersegment)
1969 return match;
1970
1971 /* Check memory and accumulator operand size. */
1972 for (j = 0; j < i.operands; j++)
1973 {
1974 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1975 && t->operand_types[j].bitfield.anysize)
1976 continue;
1977
1978 if (t->operand_types[j].bitfield.reg
1979 && !match_reg_size (t, j))
1980 {
1981 match = 0;
1982 break;
1983 }
1984
1985 if (t->operand_types[j].bitfield.regsimd
1986 && !match_simd_size (t, j))
1987 {
1988 match = 0;
1989 break;
1990 }
1991
1992 if (t->operand_types[j].bitfield.acc
1993 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1994 {
1995 match = 0;
1996 break;
1997 }
1998
1999 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2000 {
2001 match = 0;
2002 break;
2003 }
2004 }
2005
2006 if (match)
2007 return match;
2008 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
2009 {
2010 mismatch:
2011 i.error = operand_size_mismatch;
2012 return 0;
2013 }
2014
2015 /* Check reverse. */
2016 gas_assert (i.operands == 2);
2017
2018 match = 1;
2019 for (j = 0; j < 2; j++)
2020 {
2021 if ((t->operand_types[j].bitfield.reg
2022 || t->operand_types[j].bitfield.acc)
2023 && !match_reg_size (t, j ? 0 : 1))
2024 goto mismatch;
2025
2026 if (i.types[j].bitfield.mem
2027 && !match_mem_size (t, j ? 0 : 1))
2028 goto mismatch;
2029 }
2030
2031 return match;
2032 }
2033
2034 static INLINE int
2035 operand_type_match (i386_operand_type overlap,
2036 i386_operand_type given)
2037 {
2038 i386_operand_type temp = overlap;
2039
2040 temp.bitfield.jumpabsolute = 0;
2041 temp.bitfield.unspecified = 0;
2042 temp.bitfield.byte = 0;
2043 temp.bitfield.word = 0;
2044 temp.bitfield.dword = 0;
2045 temp.bitfield.fword = 0;
2046 temp.bitfield.qword = 0;
2047 temp.bitfield.tbyte = 0;
2048 temp.bitfield.xmmword = 0;
2049 temp.bitfield.ymmword = 0;
2050 temp.bitfield.zmmword = 0;
2051 if (operand_type_all_zero (&temp))
2052 goto mismatch;
2053
2054 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2055 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2056 return 1;
2057
2058 mismatch:
2059 i.error = operand_type_mismatch;
2060 return 0;
2061 }
2062
2063 /* If given types g0 and g1 are registers they must be of the same type
2064 unless the expected operand type register overlap is null.
2065 Memory operand size of certain SIMD instructions is also being checked
2066 here. */
2067
2068 static INLINE int
2069 operand_type_register_match (i386_operand_type g0,
2070 i386_operand_type t0,
2071 i386_operand_type g1,
2072 i386_operand_type t1)
2073 {
2074 if (!g0.bitfield.reg
2075 && !g0.bitfield.regsimd
2076 && (!operand_type_check (g0, anymem)
2077 || g0.bitfield.unspecified
2078 || !t0.bitfield.regsimd))
2079 return 1;
2080
2081 if (!g1.bitfield.reg
2082 && !g1.bitfield.regsimd
2083 && (!operand_type_check (g1, anymem)
2084 || g1.bitfield.unspecified
2085 || !t1.bitfield.regsimd))
2086 return 1;
2087
2088 if (g0.bitfield.byte == g1.bitfield.byte
2089 && g0.bitfield.word == g1.bitfield.word
2090 && g0.bitfield.dword == g1.bitfield.dword
2091 && g0.bitfield.qword == g1.bitfield.qword
2092 && g0.bitfield.xmmword == g1.bitfield.xmmword
2093 && g0.bitfield.ymmword == g1.bitfield.ymmword
2094 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2095 return 1;
2096
2097 if (!(t0.bitfield.byte & t1.bitfield.byte)
2098 && !(t0.bitfield.word & t1.bitfield.word)
2099 && !(t0.bitfield.dword & t1.bitfield.dword)
2100 && !(t0.bitfield.qword & t1.bitfield.qword)
2101 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2102 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2103 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2104 return 1;
2105
2106 i.error = register_type_mismatch;
2107
2108 return 0;
2109 }
2110
2111 static INLINE unsigned int
2112 register_number (const reg_entry *r)
2113 {
2114 unsigned int nr = r->reg_num;
2115
2116 if (r->reg_flags & RegRex)
2117 nr += 8;
2118
2119 if (r->reg_flags & RegVRex)
2120 nr += 16;
2121
2122 return nr;
2123 }
2124
2125 static INLINE unsigned int
2126 mode_from_disp_size (i386_operand_type t)
2127 {
2128 if (t.bitfield.disp8)
2129 return 1;
2130 else if (t.bitfield.disp16
2131 || t.bitfield.disp32
2132 || t.bitfield.disp32s)
2133 return 2;
2134 else
2135 return 0;
2136 }
2137
2138 static INLINE int
2139 fits_in_signed_byte (addressT num)
2140 {
2141 return num + 0x80 <= 0xff;
2142 }
2143
2144 static INLINE int
2145 fits_in_unsigned_byte (addressT num)
2146 {
2147 return num <= 0xff;
2148 }
2149
2150 static INLINE int
2151 fits_in_unsigned_word (addressT num)
2152 {
2153 return num <= 0xffff;
2154 }
2155
2156 static INLINE int
2157 fits_in_signed_word (addressT num)
2158 {
2159 return num + 0x8000 <= 0xffff;
2160 }
2161
2162 static INLINE int
2163 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2164 {
2165 #ifndef BFD64
2166 return 1;
2167 #else
2168 return num + 0x80000000 <= 0xffffffff;
2169 #endif
2170 } /* fits_in_signed_long() */
2171
2172 static INLINE int
2173 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2174 {
2175 #ifndef BFD64
2176 return 1;
2177 #else
2178 return num <= 0xffffffff;
2179 #endif
2180 } /* fits_in_unsigned_long() */
2181
2182 static INLINE int
2183 fits_in_disp8 (offsetT num)
2184 {
2185 int shift = i.memshift;
2186 unsigned int mask;
2187
2188 if (shift == -1)
2189 abort ();
2190
2191 mask = (1 << shift) - 1;
2192
2193 /* Return 0 if NUM isn't properly aligned. */
2194 if ((num & mask))
2195 return 0;
2196
2197 /* Check if NUM will fit in 8bit after shift. */
2198 return fits_in_signed_byte (num >> shift);
2199 }
2200
2201 static INLINE int
2202 fits_in_imm4 (offsetT num)
2203 {
2204 return (num & 0xf) == num;
2205 }
2206
2207 static INLINE int
2208 fits_in_imm7 (offsetT num)
2209 {
2210 return (num & 0x7f) == num;
2211 }
2212
2213 static INLINE int
2214 fits_in_imm31 (offsetT num)
2215 {
2216 return (num & 0x7fffffff) == num;
2217 }
2218
2219 static i386_operand_type
2220 smallest_imm_type (offsetT num)
2221 {
2222 i386_operand_type t;
2223
2224 operand_type_set (&t, 0);
2225 t.bitfield.imm64 = 1;
2226
2227 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2228 {
2229 /* This code is disabled on the 486 because all the Imm1 forms
2230 in the opcode table are slower on the i486. They're the
2231 versions with the implicitly specified single-position
2232 displacement, which has another syntax if you really want to
2233 use that form. */
2234 t.bitfield.imm1 = 1;
2235 t.bitfield.imm8 = 1;
2236 t.bitfield.imm8s = 1;
2237 t.bitfield.imm16 = 1;
2238 t.bitfield.imm32 = 1;
2239 t.bitfield.imm32s = 1;
2240 }
2241 else if (fits_in_signed_byte (num))
2242 {
2243 t.bitfield.imm8 = 1;
2244 t.bitfield.imm8s = 1;
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2248 }
2249 else if (fits_in_unsigned_byte (num))
2250 {
2251 t.bitfield.imm8 = 1;
2252 t.bitfield.imm16 = 1;
2253 t.bitfield.imm32 = 1;
2254 t.bitfield.imm32s = 1;
2255 }
2256 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2257 {
2258 t.bitfield.imm16 = 1;
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2261 }
2262 else if (fits_in_signed_long (num))
2263 {
2264 t.bitfield.imm32 = 1;
2265 t.bitfield.imm32s = 1;
2266 }
2267 else if (fits_in_unsigned_long (num))
2268 t.bitfield.imm32 = 1;
2269
2270 return t;
2271 }
2272
2273 static offsetT
2274 offset_in_range (offsetT val, int size)
2275 {
2276 addressT mask;
2277
2278 switch (size)
2279 {
2280 case 1: mask = ((addressT) 1 << 8) - 1; break;
2281 case 2: mask = ((addressT) 1 << 16) - 1; break;
2282 case 4: mask = ((addressT) 2 << 31) - 1; break;
2283 #ifdef BFD64
2284 case 8: mask = ((addressT) 2 << 63) - 1; break;
2285 #endif
2286 default: abort ();
2287 }
2288
2289 #ifdef BFD64
2290 /* If BFD64, sign extend val for 32bit address mode. */
2291 if (flag_code != CODE_64BIT
2292 || i.prefix[ADDR_PREFIX])
2293 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2294 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2295 #endif
2296
2297 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2298 {
2299 char buf1[40], buf2[40];
2300
2301 sprint_value (buf1, val);
2302 sprint_value (buf2, val & mask);
2303 as_warn (_("%s shortened to %s"), buf1, buf2);
2304 }
2305 return val & mask;
2306 }
2307
2308 enum PREFIX_GROUP
2309 {
2310 PREFIX_EXIST = 0,
2311 PREFIX_LOCK,
2312 PREFIX_REP,
2313 PREFIX_DS,
2314 PREFIX_OTHER
2315 };
2316
2317 /* Returns
2318 a. PREFIX_EXIST if attempting to add a prefix where one from the
2319 same class already exists.
2320 b. PREFIX_LOCK if lock prefix is added.
2321 c. PREFIX_REP if rep/repne prefix is added.
2322 d. PREFIX_DS if ds prefix is added.
2323 e. PREFIX_OTHER if other prefix is added.
2324 */
2325
2326 static enum PREFIX_GROUP
2327 add_prefix (unsigned int prefix)
2328 {
2329 enum PREFIX_GROUP ret = PREFIX_OTHER;
2330 unsigned int q;
2331
2332 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2333 && flag_code == CODE_64BIT)
2334 {
2335 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2336 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2337 && (prefix & (REX_R | REX_X | REX_B))))
2338 ret = PREFIX_EXIST;
2339 q = REX_PREFIX;
2340 }
2341 else
2342 {
2343 switch (prefix)
2344 {
2345 default:
2346 abort ();
2347
2348 case DS_PREFIX_OPCODE:
2349 ret = PREFIX_DS;
2350 /* Fall through. */
2351 case CS_PREFIX_OPCODE:
2352 case ES_PREFIX_OPCODE:
2353 case FS_PREFIX_OPCODE:
2354 case GS_PREFIX_OPCODE:
2355 case SS_PREFIX_OPCODE:
2356 q = SEG_PREFIX;
2357 break;
2358
2359 case REPNE_PREFIX_OPCODE:
2360 case REPE_PREFIX_OPCODE:
2361 q = REP_PREFIX;
2362 ret = PREFIX_REP;
2363 break;
2364
2365 case LOCK_PREFIX_OPCODE:
2366 q = LOCK_PREFIX;
2367 ret = PREFIX_LOCK;
2368 break;
2369
2370 case FWAIT_OPCODE:
2371 q = WAIT_PREFIX;
2372 break;
2373
2374 case ADDR_PREFIX_OPCODE:
2375 q = ADDR_PREFIX;
2376 break;
2377
2378 case DATA_PREFIX_OPCODE:
2379 q = DATA_PREFIX;
2380 break;
2381 }
2382 if (i.prefix[q] != 0)
2383 ret = PREFIX_EXIST;
2384 }
2385
2386 if (ret)
2387 {
2388 if (!i.prefix[q])
2389 ++i.prefixes;
2390 i.prefix[q] |= prefix;
2391 }
2392 else
2393 as_bad (_("same type of prefix used twice"));
2394
2395 return ret;
2396 }
2397
2398 static void
2399 update_code_flag (int value, int check)
2400 {
2401 PRINTF_LIKE ((*as_error));
2402
2403 flag_code = (enum flag_code) value;
2404 if (flag_code == CODE_64BIT)
2405 {
2406 cpu_arch_flags.bitfield.cpu64 = 1;
2407 cpu_arch_flags.bitfield.cpuno64 = 0;
2408 }
2409 else
2410 {
2411 cpu_arch_flags.bitfield.cpu64 = 0;
2412 cpu_arch_flags.bitfield.cpuno64 = 1;
2413 }
2414 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2415 {
2416 if (check)
2417 as_error = as_fatal;
2418 else
2419 as_error = as_bad;
2420 (*as_error) (_("64bit mode not supported on `%s'."),
2421 cpu_arch_name ? cpu_arch_name : default_arch);
2422 }
2423 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2424 {
2425 if (check)
2426 as_error = as_fatal;
2427 else
2428 as_error = as_bad;
2429 (*as_error) (_("32bit mode not supported on `%s'."),
2430 cpu_arch_name ? cpu_arch_name : default_arch);
2431 }
2432 stackop_size = '\0';
2433 }
2434
2435 static void
2436 set_code_flag (int value)
2437 {
2438 update_code_flag (value, 0);
2439 }
2440
2441 static void
2442 set_16bit_gcc_code_flag (int new_code_flag)
2443 {
2444 flag_code = (enum flag_code) new_code_flag;
2445 if (flag_code != CODE_16BIT)
2446 abort ();
2447 cpu_arch_flags.bitfield.cpu64 = 0;
2448 cpu_arch_flags.bitfield.cpuno64 = 1;
2449 stackop_size = LONG_MNEM_SUFFIX;
2450 }
2451
2452 static void
2453 set_intel_syntax (int syntax_flag)
2454 {
2455 /* Find out if register prefixing is specified. */
2456 int ask_naked_reg = 0;
2457
2458 SKIP_WHITESPACE ();
2459 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2460 {
2461 char *string;
2462 int e = get_symbol_name (&string);
2463
2464 if (strcmp (string, "prefix") == 0)
2465 ask_naked_reg = 1;
2466 else if (strcmp (string, "noprefix") == 0)
2467 ask_naked_reg = -1;
2468 else
2469 as_bad (_("bad argument to syntax directive."));
2470 (void) restore_line_pointer (e);
2471 }
2472 demand_empty_rest_of_line ();
2473
2474 intel_syntax = syntax_flag;
2475
2476 if (ask_naked_reg == 0)
2477 allow_naked_reg = (intel_syntax
2478 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2479 else
2480 allow_naked_reg = (ask_naked_reg < 0);
2481
2482 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2483
2484 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2485 identifier_chars['$'] = intel_syntax ? '$' : 0;
2486 register_prefix = allow_naked_reg ? "" : "%";
2487 }
2488
2489 static void
2490 set_intel_mnemonic (int mnemonic_flag)
2491 {
2492 intel_mnemonic = mnemonic_flag;
2493 }
2494
2495 static void
2496 set_allow_index_reg (int flag)
2497 {
2498 allow_index_reg = flag;
2499 }
2500
2501 static void
2502 set_check (int what)
2503 {
2504 enum check_kind *kind;
2505 const char *str;
2506
2507 if (what)
2508 {
2509 kind = &operand_check;
2510 str = "operand";
2511 }
2512 else
2513 {
2514 kind = &sse_check;
2515 str = "sse";
2516 }
2517
2518 SKIP_WHITESPACE ();
2519
2520 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2521 {
2522 char *string;
2523 int e = get_symbol_name (&string);
2524
2525 if (strcmp (string, "none") == 0)
2526 *kind = check_none;
2527 else if (strcmp (string, "warning") == 0)
2528 *kind = check_warning;
2529 else if (strcmp (string, "error") == 0)
2530 *kind = check_error;
2531 else
2532 as_bad (_("bad argument to %s_check directive."), str);
2533 (void) restore_line_pointer (e);
2534 }
2535 else
2536 as_bad (_("missing argument for %s_check directive"), str);
2537
2538 demand_empty_rest_of_line ();
2539 }
2540
2541 static void
2542 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2543 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2544 {
2545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2546 static const char *arch;
2547
2548 /* Intel LIOM is only supported on ELF. */
2549 if (!IS_ELF)
2550 return;
2551
2552 if (!arch)
2553 {
2554 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2555 use default_arch. */
2556 arch = cpu_arch_name;
2557 if (!arch)
2558 arch = default_arch;
2559 }
2560
2561 /* If we are targeting Intel MCU, we must enable it. */
2562 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2563 || new_flag.bitfield.cpuiamcu)
2564 return;
2565
2566 /* If we are targeting Intel L1OM, we must enable it. */
2567 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2568 || new_flag.bitfield.cpul1om)
2569 return;
2570
2571 /* If we are targeting Intel K1OM, we must enable it. */
2572 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2573 || new_flag.bitfield.cpuk1om)
2574 return;
2575
2576 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2577 #endif
2578 }
2579
2580 static void
2581 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2582 {
2583 SKIP_WHITESPACE ();
2584
2585 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2586 {
2587 char *string;
2588 int e = get_symbol_name (&string);
2589 unsigned int j;
2590 i386_cpu_flags flags;
2591
2592 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2593 {
2594 if (strcmp (string, cpu_arch[j].name) == 0)
2595 {
2596 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2597
2598 if (*string != '.')
2599 {
2600 cpu_arch_name = cpu_arch[j].name;
2601 cpu_sub_arch_name = NULL;
2602 cpu_arch_flags = cpu_arch[j].flags;
2603 if (flag_code == CODE_64BIT)
2604 {
2605 cpu_arch_flags.bitfield.cpu64 = 1;
2606 cpu_arch_flags.bitfield.cpuno64 = 0;
2607 }
2608 else
2609 {
2610 cpu_arch_flags.bitfield.cpu64 = 0;
2611 cpu_arch_flags.bitfield.cpuno64 = 1;
2612 }
2613 cpu_arch_isa = cpu_arch[j].type;
2614 cpu_arch_isa_flags = cpu_arch[j].flags;
2615 if (!cpu_arch_tune_set)
2616 {
2617 cpu_arch_tune = cpu_arch_isa;
2618 cpu_arch_tune_flags = cpu_arch_isa_flags;
2619 }
2620 break;
2621 }
2622
2623 flags = cpu_flags_or (cpu_arch_flags,
2624 cpu_arch[j].flags);
2625
2626 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2627 {
2628 if (cpu_sub_arch_name)
2629 {
2630 char *name = cpu_sub_arch_name;
2631 cpu_sub_arch_name = concat (name,
2632 cpu_arch[j].name,
2633 (const char *) NULL);
2634 free (name);
2635 }
2636 else
2637 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2638 cpu_arch_flags = flags;
2639 cpu_arch_isa_flags = flags;
2640 }
2641 (void) restore_line_pointer (e);
2642 demand_empty_rest_of_line ();
2643 return;
2644 }
2645 }
2646
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2648 {
2649 /* Disable an ISA extension. */
2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2652 {
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2656 {
2657 if (cpu_sub_arch_name)
2658 {
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2662 free (name);
2663 }
2664 else
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2668 }
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2671 return;
2672 }
2673
2674 j = ARRAY_SIZE (cpu_arch);
2675 }
2676
2677 if (j >= ARRAY_SIZE (cpu_arch))
2678 as_bad (_("no such architecture: `%s'"), string);
2679
2680 *input_line_pointer = e;
2681 }
2682 else
2683 as_bad (_("missing cpu architecture"));
2684
2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2688 {
2689 char *string;
2690 char e;
2691
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
2694
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2698 ;
2699 else
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2701
2702 (void) restore_line_pointer (e);
2703 }
2704
2705 demand_empty_rest_of_line ();
2706 }
2707
2708 enum bfd_architecture
2709 i386_arch (void)
2710 {
2711 if (cpu_arch_isa == PROCESSOR_L1OM)
2712 {
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2717 }
2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2719 {
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2724 }
2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2726 {
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2731 }
2732 else
2733 return bfd_arch_i386;
2734 }
2735
2736 unsigned long
2737 i386_mach (void)
2738 {
2739 if (!strncmp (default_arch, "x86_64", 6))
2740 {
2741 if (cpu_arch_isa == PROCESSOR_L1OM)
2742 {
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2747 }
2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2749 {
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2754 }
2755 else if (default_arch[6] == '\0')
2756 return bfd_mach_x86_64;
2757 else
2758 return bfd_mach_x64_32;
2759 }
2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
2762 {
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2764 {
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2768 }
2769 else
2770 return bfd_mach_i386_i386;
2771 }
2772 else
2773 as_fatal (_("unknown architecture"));
2774 }
2775 \f
2776 void
2777 md_begin (void)
2778 {
2779 const char *hash_err;
2780
2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2783
2784 /* Initialize op_hash hash table. */
2785 op_hash = hash_new ();
2786
2787 {
2788 const insn_template *optab;
2789 templates *core_optab;
2790
2791 /* Setup for loop. */
2792 optab = i386_optab;
2793 core_optab = XNEW (templates);
2794 core_optab->start = optab;
2795
2796 while (1)
2797 {
2798 ++optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2801 {
2802 /* different name --> ship out current template list;
2803 add to hash table; & begin anew. */
2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2806 (optab - 1)->name,
2807 (void *) core_optab);
2808 if (hash_err)
2809 {
2810 as_fatal (_("can't hash %s: %s"),
2811 (optab - 1)->name,
2812 hash_err);
2813 }
2814 if (optab->name == NULL)
2815 break;
2816 core_optab = XNEW (templates);
2817 core_optab->start = optab;
2818 }
2819 }
2820 }
2821
2822 /* Initialize reg_hash hash table. */
2823 reg_hash = hash_new ();
2824 {
2825 const reg_entry *regtab;
2826 unsigned int regtab_size = i386_regtab_size;
2827
2828 for (regtab = i386_regtab; regtab_size--; regtab++)
2829 {
2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2831 if (hash_err)
2832 as_fatal (_("can't hash %s: %s"),
2833 regtab->reg_name,
2834 hash_err);
2835 }
2836 }
2837
2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2839 {
2840 int c;
2841 char *p;
2842
2843 for (c = 0; c < 256; c++)
2844 {
2845 if (ISDIGIT (c))
2846 {
2847 digit_chars[c] = c;
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2851 }
2852 else if (ISLOWER (c))
2853 {
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2857 }
2858 else if (ISUPPER (c))
2859 {
2860 mnemonic_chars[c] = TOLOWER (c);
2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2863 }
2864 else if (c == '{' || c == '}')
2865 {
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2868 }
2869
2870 if (ISALPHA (c) || ISDIGIT (c))
2871 identifier_chars[c] = c;
2872 else if (c >= 128)
2873 {
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2876 }
2877 }
2878
2879 #ifdef LEX_AT
2880 identifier_chars['@'] = '@';
2881 #endif
2882 #ifdef LEX_QM
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
2885 #endif
2886 digit_chars['-'] = '-';
2887 mnemonic_chars['_'] = '_';
2888 mnemonic_chars['-'] = '-';
2889 mnemonic_chars['.'] = '.';
2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2892
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2895 }
2896
2897 if (flag_code == CODE_64BIT)
2898 {
2899 #if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2901 ? 32 : 16);
2902 #else
2903 x86_dwarf2_return_column = 16;
2904 #endif
2905 x86_cie_data_alignment = -8;
2906 }
2907 else
2908 {
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2911 }
2912 }
2913
2914 void
2915 i386_print_statistics (FILE *file)
2916 {
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2919 }
2920 \f
2921 #ifdef DEBUG386
2922
2923 /* Debugging routines for md_assemble. */
2924 static void pte (insn_template *);
2925 static void pt (i386_operand_type);
2926 static void pe (expressionS *);
2927 static void ps (symbolS *);
2928
2929 static void
2930 pi (char *line, i386_insn *x)
2931 {
2932 unsigned int j;
2933
2934 fprintf (stdout, "%s: template ", line);
2935 pte (&x->tm);
2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2941 x->rm.mode, x->rm.reg, x->rm.regmem);
2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
2949 for (j = 0; j < x->operands; j++)
2950 {
2951 fprintf (stdout, " #%d: ", j + 1);
2952 pt (x->types[j]);
2953 fprintf (stdout, "\n");
2954 if (x->types[j].bitfield.reg
2955 || x->types[j].bitfield.regmmx
2956 || x->types[j].bitfield.regsimd
2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2964 pe (x->op[j].imms);
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
2967 }
2968 }
2969
2970 static void
2971 pte (insn_template *t)
2972 {
2973 unsigned int j;
2974 fprintf (stdout, " %d operands ", t->operands);
2975 fprintf (stdout, "opcode %x ", t->base_opcode);
2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
2978 if (t->opcode_modifier.d)
2979 fprintf (stdout, "D");
2980 if (t->opcode_modifier.w)
2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
2983 for (j = 0; j < t->operands; j++)
2984 {
2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
2987 fprintf (stdout, "\n");
2988 }
2989 }
2990
2991 static void
2992 pe (expressionS *e)
2993 {
2994 fprintf (stdout, " operation %d\n", e->X_op);
2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
2997 if (e->X_add_symbol)
2998 {
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3002 }
3003 if (e->X_op_symbol)
3004 {
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3008 }
3009 }
3010
3011 static void
3012 ps (symbolS *s)
3013 {
3014 fprintf (stdout, "%s type %s%s",
3015 S_GET_NAME (s),
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3018 }
3019
3020 static struct type_name
3021 {
3022 i386_operand_type mask;
3023 const char *name;
3024 }
3025 const type_names[] =
3026 {
3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
3057 { OPERAND_TYPE_REGYMM, "rYMM" },
3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
3060 { OPERAND_TYPE_ESSEG, "es" },
3061 };
3062
3063 static void
3064 pt (i386_operand_type t)
3065 {
3066 unsigned int j;
3067 i386_operand_type a;
3068
3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3070 {
3071 a = operand_type_and (t, type_names[j].mask);
3072 if (!operand_type_all_zero (&a))
3073 fprintf (stdout, "%s, ", type_names[j].name);
3074 }
3075 fflush (stdout);
3076 }
3077
3078 #endif /* DEBUG386 */
3079 \f
3080 static bfd_reloc_code_real_type
3081 reloc (unsigned int size,
3082 int pcrel,
3083 int sign,
3084 bfd_reloc_code_real_type other)
3085 {
3086 if (other != NO_RELOC)
3087 {
3088 reloc_howto_type *rel;
3089
3090 if (size == 8)
3091 switch (other)
3092 {
3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3098 break;
3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3104 break;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3107 break;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3110 break;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3113 break;
3114 default:
3115 break;
3116 }
3117
3118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3119 if (other == BFD_RELOC_SIZE32)
3120 {
3121 if (size == 8)
3122 other = BFD_RELOC_SIZE64;
3123 if (pcrel)
3124 {
3125 as_bad (_("there are no pc-relative size relocations"));
3126 return NO_RELOC;
3127 }
3128 }
3129 #endif
3130
3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3133 sign = -1;
3134
3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3136 if (!rel)
3137 as_bad (_("unknown relocation (%u)"), other);
3138 else if (size != bfd_get_reloc_size (rel))
3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3140 bfd_get_reloc_size (rel),
3141 size);
3142 else if (pcrel && !rel->pc_relative)
3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3145 && !sign)
3146 || (rel->complain_on_overflow == complain_overflow_unsigned
3147 && sign > 0))
3148 as_bad (_("relocated field and relocation type differ in signedness"));
3149 else
3150 return other;
3151 return NO_RELOC;
3152 }
3153
3154 if (pcrel)
3155 {
3156 if (!sign)
3157 as_bad (_("there are no unsigned pc-relative relocations"));
3158 switch (size)
3159 {
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
3162 case 4: return BFD_RELOC_32_PCREL;
3163 case 8: return BFD_RELOC_64_PCREL;
3164 }
3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3166 }
3167 else
3168 {
3169 if (sign > 0)
3170 switch (size)
3171 {
3172 case 4: return BFD_RELOC_X86_64_32S;
3173 }
3174 else
3175 switch (size)
3176 {
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3181 }
3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
3184 }
3185
3186 return NO_RELOC;
3187 }
3188
3189 /* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3193
3194 int
3195 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3196 {
3197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3198 if (!IS_ELF)
3199 return 1;
3200
3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3202 mode. */
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3205 && fixP->fx_pcrel)
3206 return 0;
3207
3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3212 return 0;
3213
3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3249 return 0;
3250 #endif
3251 return 1;
3252 }
3253
3254 static int
3255 intel_float_operand (const char *mnemonic)
3256 {
3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3260
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3263
3264 switch (mnemonic[1])
3265 {
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3269 case 'i':
3270 return 2 /* integer op */;
3271 case 'l':
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3274 break;
3275 case 'n':
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3278 break;
3279 case 'r':
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3282 break;
3283 case 's':
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3287 {
3288 switch (mnemonic[3])
3289 {
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3294 return 3;
3295 }
3296 }
3297 break;
3298 case 'x':
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3301 break;
3302 }
3303
3304 return 1;
3305 }
3306
3307 /* Build the VEX prefix. */
3308
3309 static void
3310 build_vex_prefix (const insn_template *t)
3311 {
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3315
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
3318 {
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3322 }
3323 else
3324 register_specifier = 0xf;
3325
3326 /* Use 2-byte VEX prefix by swapping destination and source
3327 operand. */
3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
3330 && i.operands == i.reg_operands
3331 && i.tm.opcode_modifier.vexopcode == VEX0F
3332 && i.tm.opcode_modifier.load
3333 && i.rex == REX_B)
3334 {
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3338
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3344 i.op[0] = temp_op;
3345
3346 gas_assert (i.rm.mode == 3);
3347
3348 i.rex = REX_R;
3349 xchg = i.rm.regmem;
3350 i.rm.regmem = i.rm.reg;
3351 i.rm.reg = xchg;
3352
3353 /* Use the next insn. */
3354 i.tm = t[1];
3355 }
3356
3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
3359 else if (i.tm.opcode_modifier.vex == VEX256)
3360 vector_length = 1;
3361 else
3362 {
3363 unsigned int op;
3364
3365 vector_length = 0;
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3370 {
3371 vector_length = 1;
3372 break;
3373 }
3374 }
3375
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3377 {
3378 case 0:
3379 implied_prefix = 0;
3380 break;
3381 case DATA_PREFIX_OPCODE:
3382 implied_prefix = 1;
3383 break;
3384 case REPE_PREFIX_OPCODE:
3385 implied_prefix = 2;
3386 break;
3387 case REPNE_PREFIX_OPCODE:
3388 implied_prefix = 3;
3389 break;
3390 default:
3391 abort ();
3392 }
3393
3394 /* Use 2-byte VEX prefix if possible. */
3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
3397 && i.tm.opcode_modifier.vexw != VEXW1
3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3399 {
3400 /* 2-byte VEX prefix. */
3401 unsigned int r;
3402
3403 i.vex.length = 2;
3404 i.vex.bytes[0] = 0xc5;
3405
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3411 | implied_prefix);
3412 }
3413 else
3414 {
3415 /* 3-byte VEX prefix. */
3416 unsigned int m, w;
3417
3418 i.vex.length = 3;
3419
3420 switch (i.tm.opcode_modifier.vexopcode)
3421 {
3422 case VEX0F:
3423 m = 0x1;
3424 i.vex.bytes[0] = 0xc4;
3425 break;
3426 case VEX0F38:
3427 m = 0x2;
3428 i.vex.bytes[0] = 0xc4;
3429 break;
3430 case VEX0F3A:
3431 m = 0x3;
3432 i.vex.bytes[0] = 0xc4;
3433 break;
3434 case XOP08:
3435 m = 0x8;
3436 i.vex.bytes[0] = 0x8f;
3437 break;
3438 case XOP09:
3439 m = 0x9;
3440 i.vex.bytes[0] = 0x8f;
3441 break;
3442 case XOP0A:
3443 m = 0xa;
3444 i.vex.bytes[0] = 0x8f;
3445 break;
3446 default:
3447 abort ();
3448 }
3449
3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3453
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3457 w = 1;
3458
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3462 | implied_prefix);
3463 }
3464 }
3465
3466 /* Build the EVEX prefix. */
3467
3468 static void
3469 build_evex_prefix (void)
3470 {
3471 unsigned int register_specifier;
3472 unsigned int implied_prefix;
3473 unsigned int m, w;
3474 rex_byte vrex_used = 0;
3475
3476 /* Check register specifier. */
3477 if (i.vex.register_specifier)
3478 {
3479 gas_assert ((i.vrex & REX_X) == 0);
3480
3481 register_specifier = i.vex.register_specifier->reg_num;
3482 if ((i.vex.register_specifier->reg_flags & RegRex))
3483 register_specifier += 8;
3484 /* The upper 16 registers are encoded in the fourth byte of the
3485 EVEX prefix. */
3486 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3487 i.vex.bytes[3] = 0x8;
3488 register_specifier = ~register_specifier & 0xf;
3489 }
3490 else
3491 {
3492 register_specifier = 0xf;
3493
3494 /* Encode upper 16 vector index register in the fourth byte of
3495 the EVEX prefix. */
3496 if (!(i.vrex & REX_X))
3497 i.vex.bytes[3] = 0x8;
3498 else
3499 vrex_used |= REX_X;
3500 }
3501
3502 switch ((i.tm.base_opcode >> 8) & 0xff)
3503 {
3504 case 0:
3505 implied_prefix = 0;
3506 break;
3507 case DATA_PREFIX_OPCODE:
3508 implied_prefix = 1;
3509 break;
3510 case REPE_PREFIX_OPCODE:
3511 implied_prefix = 2;
3512 break;
3513 case REPNE_PREFIX_OPCODE:
3514 implied_prefix = 3;
3515 break;
3516 default:
3517 abort ();
3518 }
3519
3520 /* 4 byte EVEX prefix. */
3521 i.vex.length = 4;
3522 i.vex.bytes[0] = 0x62;
3523
3524 /* mmmm bits. */
3525 switch (i.tm.opcode_modifier.vexopcode)
3526 {
3527 case VEX0F:
3528 m = 1;
3529 break;
3530 case VEX0F38:
3531 m = 2;
3532 break;
3533 case VEX0F3A:
3534 m = 3;
3535 break;
3536 default:
3537 abort ();
3538 break;
3539 }
3540
3541 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3542 bits from REX. */
3543 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3544
3545 /* The fifth bit of the second EVEX byte is 1's compliment of the
3546 REX_R bit in VREX. */
3547 if (!(i.vrex & REX_R))
3548 i.vex.bytes[1] |= 0x10;
3549 else
3550 vrex_used |= REX_R;
3551
3552 if ((i.reg_operands + i.imm_operands) == i.operands)
3553 {
3554 /* When all operands are registers, the REX_X bit in REX is not
3555 used. We reuse it to encode the upper 16 registers, which is
3556 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3557 as 1's compliment. */
3558 if ((i.vrex & REX_B))
3559 {
3560 vrex_used |= REX_B;
3561 i.vex.bytes[1] &= ~0x40;
3562 }
3563 }
3564
3565 /* EVEX instructions shouldn't need the REX prefix. */
3566 i.vrex &= ~vrex_used;
3567 gas_assert (i.vrex == 0);
3568
3569 /* Check the REX.W bit. */
3570 w = (i.rex & REX_W) ? 1 : 0;
3571 if (i.tm.opcode_modifier.vexw)
3572 {
3573 if (i.tm.opcode_modifier.vexw == VEXW1)
3574 w = 1;
3575 }
3576 /* If w is not set it means we are dealing with WIG instruction. */
3577 else if (!w)
3578 {
3579 if (evexwig == evexw1)
3580 w = 1;
3581 }
3582
3583 /* Encode the U bit. */
3584 implied_prefix |= 0x4;
3585
3586 /* The third byte of the EVEX prefix. */
3587 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3588
3589 /* The fourth byte of the EVEX prefix. */
3590 /* The zeroing-masking bit. */
3591 if (i.mask && i.mask->zeroing)
3592 i.vex.bytes[3] |= 0x80;
3593
3594 /* Don't always set the broadcast bit if there is no RC. */
3595 if (!i.rounding)
3596 {
3597 /* Encode the vector length. */
3598 unsigned int vec_length;
3599
3600 switch (i.tm.opcode_modifier.evex)
3601 {
3602 case EVEXLIG: /* LL' is ignored */
3603 vec_length = evexlig << 5;
3604 break;
3605 case EVEX128:
3606 vec_length = 0 << 5;
3607 break;
3608 case EVEX256:
3609 vec_length = 1 << 5;
3610 break;
3611 case EVEX512:
3612 vec_length = 2 << 5;
3613 break;
3614 default:
3615 abort ();
3616 break;
3617 }
3618 i.vex.bytes[3] |= vec_length;
3619 /* Encode the broadcast bit. */
3620 if (i.broadcast)
3621 i.vex.bytes[3] |= 0x10;
3622 }
3623 else
3624 {
3625 if (i.rounding->type != saeonly)
3626 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3627 else
3628 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3629 }
3630
3631 if (i.mask && i.mask->mask)
3632 i.vex.bytes[3] |= i.mask->mask->reg_num;
3633 }
3634
3635 static void
3636 process_immext (void)
3637 {
3638 expressionS *exp;
3639
3640 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3641 && i.operands > 0)
3642 {
3643 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3644 with an opcode suffix which is coded in the same place as an
3645 8-bit immediate field would be.
3646 Here we check those operands and remove them afterwards. */
3647 unsigned int x;
3648
3649 for (x = 0; x < i.operands; x++)
3650 if (register_number (i.op[x].regs) != x)
3651 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3652 register_prefix, i.op[x].regs->reg_name, x + 1,
3653 i.tm.name);
3654
3655 i.operands = 0;
3656 }
3657
3658 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3659 {
3660 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3661 suffix which is coded in the same place as an 8-bit immediate
3662 field would be.
3663 Here we check those operands and remove them afterwards. */
3664 unsigned int x;
3665
3666 if (i.operands != 3)
3667 abort();
3668
3669 for (x = 0; x < 2; x++)
3670 if (register_number (i.op[x].regs) != x)
3671 goto bad_register_operand;
3672
3673 /* Check for third operand for mwaitx/monitorx insn. */
3674 if (register_number (i.op[x].regs)
3675 != (x + (i.tm.extension_opcode == 0xfb)))
3676 {
3677 bad_register_operand:
3678 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3679 register_prefix, i.op[x].regs->reg_name, x+1,
3680 i.tm.name);
3681 }
3682
3683 i.operands = 0;
3684 }
3685
3686 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3687 which is coded in the same place as an 8-bit immediate field
3688 would be. Here we fake an 8-bit immediate operand from the
3689 opcode suffix stored in tm.extension_opcode.
3690
3691 AVX instructions also use this encoding, for some of
3692 3 argument instructions. */
3693
3694 gas_assert (i.imm_operands <= 1
3695 && (i.operands <= 2
3696 || ((i.tm.opcode_modifier.vex
3697 || i.tm.opcode_modifier.evex)
3698 && i.operands <= 4)));
3699
3700 exp = &im_expressions[i.imm_operands++];
3701 i.op[i.operands].imms = exp;
3702 i.types[i.operands] = imm8;
3703 i.operands++;
3704 exp->X_op = O_constant;
3705 exp->X_add_number = i.tm.extension_opcode;
3706 i.tm.extension_opcode = None;
3707 }
3708
3709
3710 static int
3711 check_hle (void)
3712 {
3713 switch (i.tm.opcode_modifier.hleprefixok)
3714 {
3715 default:
3716 abort ();
3717 case HLEPrefixNone:
3718 as_bad (_("invalid instruction `%s' after `%s'"),
3719 i.tm.name, i.hle_prefix);
3720 return 0;
3721 case HLEPrefixLock:
3722 if (i.prefix[LOCK_PREFIX])
3723 return 1;
3724 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3725 return 0;
3726 case HLEPrefixAny:
3727 return 1;
3728 case HLEPrefixRelease:
3729 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3730 {
3731 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3732 i.tm.name);
3733 return 0;
3734 }
3735 if (i.mem_operands == 0
3736 || !operand_type_check (i.types[i.operands - 1], anymem))
3737 {
3738 as_bad (_("memory destination needed for instruction `%s'"
3739 " after `xrelease'"), i.tm.name);
3740 return 0;
3741 }
3742 return 1;
3743 }
3744 }
3745
3746 /* Try the shortest encoding by shortening operand size. */
3747
3748 static void
3749 optimize_encoding (void)
3750 {
3751 int j;
3752
3753 if (optimize_for_space
3754 && i.reg_operands == 1
3755 && i.imm_operands == 1
3756 && !i.types[1].bitfield.byte
3757 && i.op[0].imms->X_op == O_constant
3758 && fits_in_imm7 (i.op[0].imms->X_add_number)
3759 && ((i.tm.base_opcode == 0xa8
3760 && i.tm.extension_opcode == None)
3761 || (i.tm.base_opcode == 0xf6
3762 && i.tm.extension_opcode == 0x0)))
3763 {
3764 /* Optimize: -Os:
3765 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3766 */
3767 unsigned int base_regnum = i.op[1].regs->reg_num;
3768 if (flag_code == CODE_64BIT || base_regnum < 4)
3769 {
3770 i.types[1].bitfield.byte = 1;
3771 /* Ignore the suffix. */
3772 i.suffix = 0;
3773 if (base_regnum >= 4
3774 && !(i.op[1].regs->reg_flags & RegRex))
3775 {
3776 /* Handle SP, BP, SI and DI registers. */
3777 if (i.types[1].bitfield.word)
3778 j = 16;
3779 else if (i.types[1].bitfield.dword)
3780 j = 32;
3781 else
3782 j = 48;
3783 i.op[1].regs -= j;
3784 }
3785 }
3786 }
3787 else if (flag_code == CODE_64BIT
3788 && ((i.reg_operands == 1
3789 && i.imm_operands == 1
3790 && i.op[0].imms->X_op == O_constant
3791 && ((i.tm.base_opcode == 0xb0
3792 && i.tm.extension_opcode == None
3793 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3794 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3795 && (((i.tm.base_opcode == 0x24
3796 || i.tm.base_opcode == 0xa8)
3797 && i.tm.extension_opcode == None)
3798 || (i.tm.base_opcode == 0x80
3799 && i.tm.extension_opcode == 0x4)
3800 || ((i.tm.base_opcode == 0xf6
3801 || i.tm.base_opcode == 0xc6)
3802 && i.tm.extension_opcode == 0x0)))))
3803 || (i.reg_operands == 2
3804 && i.op[0].regs == i.op[1].regs
3805 && ((i.tm.base_opcode == 0x30
3806 || i.tm.base_opcode == 0x28)
3807 && i.tm.extension_opcode == None)))
3808 && i.types[1].bitfield.qword)
3809 {
3810 /* Optimize: -O:
3811 andq $imm31, %r64 -> andl $imm31, %r32
3812 testq $imm31, %r64 -> testl $imm31, %r32
3813 xorq %r64, %r64 -> xorl %r32, %r32
3814 subq %r64, %r64 -> subl %r32, %r32
3815 movq $imm31, %r64 -> movl $imm31, %r32
3816 movq $imm32, %r64 -> movl $imm32, %r32
3817 */
3818 i.tm.opcode_modifier.norex64 = 1;
3819 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3820 {
3821 /* Handle
3822 movq $imm31, %r64 -> movl $imm31, %r32
3823 movq $imm32, %r64 -> movl $imm32, %r32
3824 */
3825 i.tm.operand_types[0].bitfield.imm32 = 1;
3826 i.tm.operand_types[0].bitfield.imm32s = 0;
3827 i.tm.operand_types[0].bitfield.imm64 = 0;
3828 i.types[0].bitfield.imm32 = 1;
3829 i.types[0].bitfield.imm32s = 0;
3830 i.types[0].bitfield.imm64 = 0;
3831 i.types[1].bitfield.dword = 1;
3832 i.types[1].bitfield.qword = 0;
3833 if (i.tm.base_opcode == 0xc6)
3834 {
3835 /* Handle
3836 movq $imm31, %r64 -> movl $imm31, %r32
3837 */
3838 i.tm.base_opcode = 0xb0;
3839 i.tm.extension_opcode = None;
3840 i.tm.opcode_modifier.shortform = 1;
3841 i.tm.opcode_modifier.modrm = 0;
3842 }
3843 }
3844 }
3845 else if (optimize > 1
3846 && i.reg_operands == 3
3847 && i.op[0].regs == i.op[1].regs
3848 && !i.types[2].bitfield.xmmword
3849 && (i.tm.opcode_modifier.vex
3850 || (!i.mask
3851 && !i.rounding
3852 && i.tm.opcode_modifier.evex
3853 && cpu_arch_flags.bitfield.cpuavx512vl))
3854 && ((i.tm.base_opcode == 0x55
3855 || i.tm.base_opcode == 0x6655
3856 || i.tm.base_opcode == 0x66df
3857 || i.tm.base_opcode == 0x57
3858 || i.tm.base_opcode == 0x6657
3859 || i.tm.base_opcode == 0x66ef)
3860 && i.tm.extension_opcode == None))
3861 {
3862 /* Optimize: -O2:
3863 VOP, one of vandnps, vandnpd, vxorps and vxorpd:
3864 EVEX VOP %zmmM, %zmmM, %zmmN
3865 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3866 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3867 EVEX VOP %ymmM, %ymmM, %ymmN
3868 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3869 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3870 VEX VOP %ymmM, %ymmM, %ymmN
3871 -> VEX VOP %xmmM, %xmmM, %xmmN
3872 VOP, one of vpandn and vpxor:
3873 VEX VOP %ymmM, %ymmM, %ymmN
3874 -> VEX VOP %xmmM, %xmmM, %xmmN
3875 VOP, one of vpandnd and vpandnq:
3876 EVEX VOP %zmmM, %zmmM, %zmmN
3877 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3878 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3879 EVEX VOP %ymmM, %ymmM, %ymmN
3880 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 VOP, one of vpxord and vpxorq:
3883 EVEX VOP %zmmM, %zmmM, %zmmN
3884 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3885 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3886 EVEX VOP %ymmM, %ymmM, %ymmN
3887 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3888 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3889 */
3890 if (i.tm.opcode_modifier.evex)
3891 {
3892 /* If only lower 16 vector registers are used, we can use
3893 VEX encoding. */
3894 for (j = 0; j < 3; j++)
3895 if (register_number (i.op[j].regs) > 15)
3896 break;
3897
3898 if (j < 3)
3899 i.tm.opcode_modifier.evex = EVEX128;
3900 else
3901 {
3902 i.tm.opcode_modifier.vex = VEX128;
3903 i.tm.opcode_modifier.vexw = VEXW0;
3904 i.tm.opcode_modifier.evex = 0;
3905 }
3906 }
3907 else
3908 i.tm.opcode_modifier.vex = VEX128;
3909
3910 if (i.tm.opcode_modifier.vex)
3911 for (j = 0; j < 3; j++)
3912 {
3913 i.types[j].bitfield.xmmword = 1;
3914 i.types[j].bitfield.ymmword = 0;
3915 }
3916 }
3917 }
3918
3919 /* This is the guts of the machine-dependent assembler. LINE points to a
3920 machine dependent instruction. This function is supposed to emit
3921 the frags/bytes it assembles to. */
3922
3923 void
3924 md_assemble (char *line)
3925 {
3926 unsigned int j;
3927 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3928 const insn_template *t;
3929
3930 /* Initialize globals. */
3931 memset (&i, '\0', sizeof (i));
3932 for (j = 0; j < MAX_OPERANDS; j++)
3933 i.reloc[j] = NO_RELOC;
3934 memset (disp_expressions, '\0', sizeof (disp_expressions));
3935 memset (im_expressions, '\0', sizeof (im_expressions));
3936 save_stack_p = save_stack;
3937
3938 /* First parse an instruction mnemonic & call i386_operand for the operands.
3939 We assume that the scrubber has arranged it so that line[0] is the valid
3940 start of a (possibly prefixed) mnemonic. */
3941
3942 line = parse_insn (line, mnemonic);
3943 if (line == NULL)
3944 return;
3945 mnem_suffix = i.suffix;
3946
3947 line = parse_operands (line, mnemonic);
3948 this_operand = -1;
3949 xfree (i.memop1_string);
3950 i.memop1_string = NULL;
3951 if (line == NULL)
3952 return;
3953
3954 /* Now we've parsed the mnemonic into a set of templates, and have the
3955 operands at hand. */
3956
3957 /* All intel opcodes have reversed operands except for "bound" and
3958 "enter". We also don't reverse intersegment "jmp" and "call"
3959 instructions with 2 immediate operands so that the immediate segment
3960 precedes the offset, as it does when in AT&T mode. */
3961 if (intel_syntax
3962 && i.operands > 1
3963 && (strcmp (mnemonic, "bound") != 0)
3964 && (strcmp (mnemonic, "invlpga") != 0)
3965 && !(operand_type_check (i.types[0], imm)
3966 && operand_type_check (i.types[1], imm)))
3967 swap_operands ();
3968
3969 /* The order of the immediates should be reversed
3970 for 2 immediates extrq and insertq instructions */
3971 if (i.imm_operands == 2
3972 && (strcmp (mnemonic, "extrq") == 0
3973 || strcmp (mnemonic, "insertq") == 0))
3974 swap_2_operands (0, 1);
3975
3976 if (i.imm_operands)
3977 optimize_imm ();
3978
3979 /* Don't optimize displacement for movabs since it only takes 64bit
3980 displacement. */
3981 if (i.disp_operands
3982 && i.disp_encoding != disp_encoding_32bit
3983 && (flag_code != CODE_64BIT
3984 || strcmp (mnemonic, "movabs") != 0))
3985 optimize_disp ();
3986
3987 /* Next, we find a template that matches the given insn,
3988 making sure the overlap of the given operands types is consistent
3989 with the template operand types. */
3990
3991 if (!(t = match_template (mnem_suffix)))
3992 return;
3993
3994 if (sse_check != check_none
3995 && !i.tm.opcode_modifier.noavx
3996 && (i.tm.cpu_flags.bitfield.cpusse
3997 || i.tm.cpu_flags.bitfield.cpusse2
3998 || i.tm.cpu_flags.bitfield.cpusse3
3999 || i.tm.cpu_flags.bitfield.cpussse3
4000 || i.tm.cpu_flags.bitfield.cpusse4_1
4001 || i.tm.cpu_flags.bitfield.cpusse4_2))
4002 {
4003 (sse_check == check_warning
4004 ? as_warn
4005 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4006 }
4007
4008 /* Zap movzx and movsx suffix. The suffix has been set from
4009 "word ptr" or "byte ptr" on the source operand in Intel syntax
4010 or extracted from mnemonic in AT&T syntax. But we'll use
4011 the destination register to choose the suffix for encoding. */
4012 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4013 {
4014 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4015 there is no suffix, the default will be byte extension. */
4016 if (i.reg_operands != 2
4017 && !i.suffix
4018 && intel_syntax)
4019 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4020
4021 i.suffix = 0;
4022 }
4023
4024 if (i.tm.opcode_modifier.fwait)
4025 if (!add_prefix (FWAIT_OPCODE))
4026 return;
4027
4028 /* Check if REP prefix is OK. */
4029 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4030 {
4031 as_bad (_("invalid instruction `%s' after `%s'"),
4032 i.tm.name, i.rep_prefix);
4033 return;
4034 }
4035
4036 /* Check for lock without a lockable instruction. Destination operand
4037 must be memory unless it is xchg (0x86). */
4038 if (i.prefix[LOCK_PREFIX]
4039 && (!i.tm.opcode_modifier.islockable
4040 || i.mem_operands == 0
4041 || (i.tm.base_opcode != 0x86
4042 && !operand_type_check (i.types[i.operands - 1], anymem))))
4043 {
4044 as_bad (_("expecting lockable instruction after `lock'"));
4045 return;
4046 }
4047
4048 /* Check if HLE prefix is OK. */
4049 if (i.hle_prefix && !check_hle ())
4050 return;
4051
4052 /* Check BND prefix. */
4053 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4054 as_bad (_("expecting valid branch instruction after `bnd'"));
4055
4056 /* Check NOTRACK prefix. */
4057 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4058 as_bad (_("expecting indirect branch instruction after `notrack'"));
4059
4060 if (i.tm.cpu_flags.bitfield.cpumpx)
4061 {
4062 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4063 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4064 else if (flag_code != CODE_16BIT
4065 ? i.prefix[ADDR_PREFIX]
4066 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4067 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4068 }
4069
4070 /* Insert BND prefix. */
4071 if (add_bnd_prefix
4072 && i.tm.opcode_modifier.bndprefixok
4073 && !i.prefix[BND_PREFIX])
4074 add_prefix (BND_PREFIX_OPCODE);
4075
4076 /* Check string instruction segment overrides. */
4077 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4078 {
4079 if (!check_string ())
4080 return;
4081 i.disp_operands = 0;
4082 }
4083
4084 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4085 optimize_encoding ();
4086
4087 if (!process_suffix ())
4088 return;
4089
4090 /* Update operand types. */
4091 for (j = 0; j < i.operands; j++)
4092 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4093
4094 /* Make still unresolved immediate matches conform to size of immediate
4095 given in i.suffix. */
4096 if (!finalize_imm ())
4097 return;
4098
4099 if (i.types[0].bitfield.imm1)
4100 i.imm_operands = 0; /* kludge for shift insns. */
4101
4102 /* We only need to check those implicit registers for instructions
4103 with 3 operands or less. */
4104 if (i.operands <= 3)
4105 for (j = 0; j < i.operands; j++)
4106 if (i.types[j].bitfield.inoutportreg
4107 || i.types[j].bitfield.shiftcount
4108 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4109 i.reg_operands--;
4110
4111 /* ImmExt should be processed after SSE2AVX. */
4112 if (!i.tm.opcode_modifier.sse2avx
4113 && i.tm.opcode_modifier.immext)
4114 process_immext ();
4115
4116 /* For insns with operands there are more diddles to do to the opcode. */
4117 if (i.operands)
4118 {
4119 if (!process_operands ())
4120 return;
4121 }
4122 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4123 {
4124 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4125 as_warn (_("translating to `%sp'"), i.tm.name);
4126 }
4127
4128 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4129 {
4130 if (flag_code == CODE_16BIT)
4131 {
4132 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4133 i.tm.name);
4134 return;
4135 }
4136
4137 if (i.tm.opcode_modifier.vex)
4138 build_vex_prefix (t);
4139 else
4140 build_evex_prefix ();
4141 }
4142
4143 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4144 instructions may define INT_OPCODE as well, so avoid this corner
4145 case for those instructions that use MODRM. */
4146 if (i.tm.base_opcode == INT_OPCODE
4147 && !i.tm.opcode_modifier.modrm
4148 && i.op[0].imms->X_add_number == 3)
4149 {
4150 i.tm.base_opcode = INT3_OPCODE;
4151 i.imm_operands = 0;
4152 }
4153
4154 if ((i.tm.opcode_modifier.jump
4155 || i.tm.opcode_modifier.jumpbyte
4156 || i.tm.opcode_modifier.jumpdword)
4157 && i.op[0].disps->X_op == O_constant)
4158 {
4159 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4160 the absolute address given by the constant. Since ix86 jumps and
4161 calls are pc relative, we need to generate a reloc. */
4162 i.op[0].disps->X_add_symbol = &abs_symbol;
4163 i.op[0].disps->X_op = O_symbol;
4164 }
4165
4166 if (i.tm.opcode_modifier.rex64)
4167 i.rex |= REX_W;
4168
4169 /* For 8 bit registers we need an empty rex prefix. Also if the
4170 instruction already has a prefix, we need to convert old
4171 registers to new ones. */
4172
4173 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4174 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4175 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4176 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4177 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4178 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4179 && i.rex != 0))
4180 {
4181 int x;
4182
4183 i.rex |= REX_OPCODE;
4184 for (x = 0; x < 2; x++)
4185 {
4186 /* Look for 8 bit operand that uses old registers. */
4187 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4188 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4189 {
4190 /* In case it is "hi" register, give up. */
4191 if (i.op[x].regs->reg_num > 3)
4192 as_bad (_("can't encode register '%s%s' in an "
4193 "instruction requiring REX prefix."),
4194 register_prefix, i.op[x].regs->reg_name);
4195
4196 /* Otherwise it is equivalent to the extended register.
4197 Since the encoding doesn't change this is merely
4198 cosmetic cleanup for debug output. */
4199
4200 i.op[x].regs = i.op[x].regs + 8;
4201 }
4202 }
4203 }
4204
4205 if (i.rex == 0 && i.rex_encoding)
4206 {
4207 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4208 that uses legacy register. If it is "hi" register, don't add
4209 the REX_OPCODE byte. */
4210 int x;
4211 for (x = 0; x < 2; x++)
4212 if (i.types[x].bitfield.reg
4213 && i.types[x].bitfield.byte
4214 && (i.op[x].regs->reg_flags & RegRex64) == 0
4215 && i.op[x].regs->reg_num > 3)
4216 {
4217 i.rex_encoding = FALSE;
4218 break;
4219 }
4220
4221 if (i.rex_encoding)
4222 i.rex = REX_OPCODE;
4223 }
4224
4225 if (i.rex != 0)
4226 add_prefix (REX_OPCODE | i.rex);
4227
4228 /* We are ready to output the insn. */
4229 output_insn ();
4230 }
4231
4232 static char *
4233 parse_insn (char *line, char *mnemonic)
4234 {
4235 char *l = line;
4236 char *token_start = l;
4237 char *mnem_p;
4238 int supported;
4239 const insn_template *t;
4240 char *dot_p = NULL;
4241
4242 while (1)
4243 {
4244 mnem_p = mnemonic;
4245 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4246 {
4247 if (*mnem_p == '.')
4248 dot_p = mnem_p;
4249 mnem_p++;
4250 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4251 {
4252 as_bad (_("no such instruction: `%s'"), token_start);
4253 return NULL;
4254 }
4255 l++;
4256 }
4257 if (!is_space_char (*l)
4258 && *l != END_OF_INSN
4259 && (intel_syntax
4260 || (*l != PREFIX_SEPARATOR
4261 && *l != ',')))
4262 {
4263 as_bad (_("invalid character %s in mnemonic"),
4264 output_invalid (*l));
4265 return NULL;
4266 }
4267 if (token_start == l)
4268 {
4269 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4270 as_bad (_("expecting prefix; got nothing"));
4271 else
4272 as_bad (_("expecting mnemonic; got nothing"));
4273 return NULL;
4274 }
4275
4276 /* Look up instruction (or prefix) via hash table. */
4277 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4278
4279 if (*l != END_OF_INSN
4280 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4281 && current_templates
4282 && current_templates->start->opcode_modifier.isprefix)
4283 {
4284 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4285 {
4286 as_bad ((flag_code != CODE_64BIT
4287 ? _("`%s' is only supported in 64-bit mode")
4288 : _("`%s' is not supported in 64-bit mode")),
4289 current_templates->start->name);
4290 return NULL;
4291 }
4292 /* If we are in 16-bit mode, do not allow addr16 or data16.
4293 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4294 if ((current_templates->start->opcode_modifier.size16
4295 || current_templates->start->opcode_modifier.size32)
4296 && flag_code != CODE_64BIT
4297 && (current_templates->start->opcode_modifier.size32
4298 ^ (flag_code == CODE_16BIT)))
4299 {
4300 as_bad (_("redundant %s prefix"),
4301 current_templates->start->name);
4302 return NULL;
4303 }
4304 if (current_templates->start->opcode_length == 0)
4305 {
4306 /* Handle pseudo prefixes. */
4307 switch (current_templates->start->base_opcode)
4308 {
4309 case 0x0:
4310 /* {disp8} */
4311 i.disp_encoding = disp_encoding_8bit;
4312 break;
4313 case 0x1:
4314 /* {disp32} */
4315 i.disp_encoding = disp_encoding_32bit;
4316 break;
4317 case 0x2:
4318 /* {load} */
4319 i.dir_encoding = dir_encoding_load;
4320 break;
4321 case 0x3:
4322 /* {store} */
4323 i.dir_encoding = dir_encoding_store;
4324 break;
4325 case 0x4:
4326 /* {vex2} */
4327 i.vec_encoding = vex_encoding_vex2;
4328 break;
4329 case 0x5:
4330 /* {vex3} */
4331 i.vec_encoding = vex_encoding_vex3;
4332 break;
4333 case 0x6:
4334 /* {evex} */
4335 i.vec_encoding = vex_encoding_evex;
4336 break;
4337 case 0x7:
4338 /* {rex} */
4339 i.rex_encoding = TRUE;
4340 break;
4341 case 0x8:
4342 /* {nooptimize} */
4343 i.no_optimize = TRUE;
4344 break;
4345 default:
4346 abort ();
4347 }
4348 }
4349 else
4350 {
4351 /* Add prefix, checking for repeated prefixes. */
4352 switch (add_prefix (current_templates->start->base_opcode))
4353 {
4354 case PREFIX_EXIST:
4355 return NULL;
4356 case PREFIX_DS:
4357 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4358 i.notrack_prefix = current_templates->start->name;
4359 break;
4360 case PREFIX_REP:
4361 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4362 i.hle_prefix = current_templates->start->name;
4363 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4364 i.bnd_prefix = current_templates->start->name;
4365 else
4366 i.rep_prefix = current_templates->start->name;
4367 break;
4368 default:
4369 break;
4370 }
4371 }
4372 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4373 token_start = ++l;
4374 }
4375 else
4376 break;
4377 }
4378
4379 if (!current_templates)
4380 {
4381 /* Check if we should swap operand or force 32bit displacement in
4382 encoding. */
4383 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4384 i.dir_encoding = dir_encoding_store;
4385 else if (mnem_p - 3 == dot_p
4386 && dot_p[1] == 'd'
4387 && dot_p[2] == '8')
4388 i.disp_encoding = disp_encoding_8bit;
4389 else if (mnem_p - 4 == dot_p
4390 && dot_p[1] == 'd'
4391 && dot_p[2] == '3'
4392 && dot_p[3] == '2')
4393 i.disp_encoding = disp_encoding_32bit;
4394 else
4395 goto check_suffix;
4396 mnem_p = dot_p;
4397 *dot_p = '\0';
4398 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4399 }
4400
4401 if (!current_templates)
4402 {
4403 check_suffix:
4404 /* See if we can get a match by trimming off a suffix. */
4405 switch (mnem_p[-1])
4406 {
4407 case WORD_MNEM_SUFFIX:
4408 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4409 i.suffix = SHORT_MNEM_SUFFIX;
4410 else
4411 /* Fall through. */
4412 case BYTE_MNEM_SUFFIX:
4413 case QWORD_MNEM_SUFFIX:
4414 i.suffix = mnem_p[-1];
4415 mnem_p[-1] = '\0';
4416 current_templates = (const templates *) hash_find (op_hash,
4417 mnemonic);
4418 break;
4419 case SHORT_MNEM_SUFFIX:
4420 case LONG_MNEM_SUFFIX:
4421 if (!intel_syntax)
4422 {
4423 i.suffix = mnem_p[-1];
4424 mnem_p[-1] = '\0';
4425 current_templates = (const templates *) hash_find (op_hash,
4426 mnemonic);
4427 }
4428 break;
4429
4430 /* Intel Syntax. */
4431 case 'd':
4432 if (intel_syntax)
4433 {
4434 if (intel_float_operand (mnemonic) == 1)
4435 i.suffix = SHORT_MNEM_SUFFIX;
4436 else
4437 i.suffix = LONG_MNEM_SUFFIX;
4438 mnem_p[-1] = '\0';
4439 current_templates = (const templates *) hash_find (op_hash,
4440 mnemonic);
4441 }
4442 break;
4443 }
4444 if (!current_templates)
4445 {
4446 as_bad (_("no such instruction: `%s'"), token_start);
4447 return NULL;
4448 }
4449 }
4450
4451 if (current_templates->start->opcode_modifier.jump
4452 || current_templates->start->opcode_modifier.jumpbyte)
4453 {
4454 /* Check for a branch hint. We allow ",pt" and ",pn" for
4455 predict taken and predict not taken respectively.
4456 I'm not sure that branch hints actually do anything on loop
4457 and jcxz insns (JumpByte) for current Pentium4 chips. They
4458 may work in the future and it doesn't hurt to accept them
4459 now. */
4460 if (l[0] == ',' && l[1] == 'p')
4461 {
4462 if (l[2] == 't')
4463 {
4464 if (!add_prefix (DS_PREFIX_OPCODE))
4465 return NULL;
4466 l += 3;
4467 }
4468 else if (l[2] == 'n')
4469 {
4470 if (!add_prefix (CS_PREFIX_OPCODE))
4471 return NULL;
4472 l += 3;
4473 }
4474 }
4475 }
4476 /* Any other comma loses. */
4477 if (*l == ',')
4478 {
4479 as_bad (_("invalid character %s in mnemonic"),
4480 output_invalid (*l));
4481 return NULL;
4482 }
4483
4484 /* Check if instruction is supported on specified architecture. */
4485 supported = 0;
4486 for (t = current_templates->start; t < current_templates->end; ++t)
4487 {
4488 supported |= cpu_flags_match (t);
4489 if (supported == CPU_FLAGS_PERFECT_MATCH)
4490 goto skip;
4491 }
4492
4493 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4494 {
4495 as_bad (flag_code == CODE_64BIT
4496 ? _("`%s' is not supported in 64-bit mode")
4497 : _("`%s' is only supported in 64-bit mode"),
4498 current_templates->start->name);
4499 return NULL;
4500 }
4501 if (supported != CPU_FLAGS_PERFECT_MATCH)
4502 {
4503 as_bad (_("`%s' is not supported on `%s%s'"),
4504 current_templates->start->name,
4505 cpu_arch_name ? cpu_arch_name : default_arch,
4506 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4507 return NULL;
4508 }
4509
4510 skip:
4511 if (!cpu_arch_flags.bitfield.cpui386
4512 && (flag_code != CODE_16BIT))
4513 {
4514 as_warn (_("use .code16 to ensure correct addressing mode"));
4515 }
4516
4517 return l;
4518 }
4519
4520 static char *
4521 parse_operands (char *l, const char *mnemonic)
4522 {
4523 char *token_start;
4524
4525 /* 1 if operand is pending after ','. */
4526 unsigned int expecting_operand = 0;
4527
4528 /* Non-zero if operand parens not balanced. */
4529 unsigned int paren_not_balanced;
4530
4531 while (*l != END_OF_INSN)
4532 {
4533 /* Skip optional white space before operand. */
4534 if (is_space_char (*l))
4535 ++l;
4536 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4537 {
4538 as_bad (_("invalid character %s before operand %d"),
4539 output_invalid (*l),
4540 i.operands + 1);
4541 return NULL;
4542 }
4543 token_start = l; /* After white space. */
4544 paren_not_balanced = 0;
4545 while (paren_not_balanced || *l != ',')
4546 {
4547 if (*l == END_OF_INSN)
4548 {
4549 if (paren_not_balanced)
4550 {
4551 if (!intel_syntax)
4552 as_bad (_("unbalanced parenthesis in operand %d."),
4553 i.operands + 1);
4554 else
4555 as_bad (_("unbalanced brackets in operand %d."),
4556 i.operands + 1);
4557 return NULL;
4558 }
4559 else
4560 break; /* we are done */
4561 }
4562 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4563 {
4564 as_bad (_("invalid character %s in operand %d"),
4565 output_invalid (*l),
4566 i.operands + 1);
4567 return NULL;
4568 }
4569 if (!intel_syntax)
4570 {
4571 if (*l == '(')
4572 ++paren_not_balanced;
4573 if (*l == ')')
4574 --paren_not_balanced;
4575 }
4576 else
4577 {
4578 if (*l == '[')
4579 ++paren_not_balanced;
4580 if (*l == ']')
4581 --paren_not_balanced;
4582 }
4583 l++;
4584 }
4585 if (l != token_start)
4586 { /* Yes, we've read in another operand. */
4587 unsigned int operand_ok;
4588 this_operand = i.operands++;
4589 if (i.operands > MAX_OPERANDS)
4590 {
4591 as_bad (_("spurious operands; (%d operands/instruction max)"),
4592 MAX_OPERANDS);
4593 return NULL;
4594 }
4595 i.types[this_operand].bitfield.unspecified = 1;
4596 /* Now parse operand adding info to 'i' as we go along. */
4597 END_STRING_AND_SAVE (l);
4598
4599 if (intel_syntax)
4600 operand_ok =
4601 i386_intel_operand (token_start,
4602 intel_float_operand (mnemonic));
4603 else
4604 operand_ok = i386_att_operand (token_start);
4605
4606 RESTORE_END_STRING (l);
4607 if (!operand_ok)
4608 return NULL;
4609 }
4610 else
4611 {
4612 if (expecting_operand)
4613 {
4614 expecting_operand_after_comma:
4615 as_bad (_("expecting operand after ','; got nothing"));
4616 return NULL;
4617 }
4618 if (*l == ',')
4619 {
4620 as_bad (_("expecting operand before ','; got nothing"));
4621 return NULL;
4622 }
4623 }
4624
4625 /* Now *l must be either ',' or END_OF_INSN. */
4626 if (*l == ',')
4627 {
4628 if (*++l == END_OF_INSN)
4629 {
4630 /* Just skip it, if it's \n complain. */
4631 goto expecting_operand_after_comma;
4632 }
4633 expecting_operand = 1;
4634 }
4635 }
4636 return l;
4637 }
4638
4639 static void
4640 swap_2_operands (int xchg1, int xchg2)
4641 {
4642 union i386_op temp_op;
4643 i386_operand_type temp_type;
4644 enum bfd_reloc_code_real temp_reloc;
4645
4646 temp_type = i.types[xchg2];
4647 i.types[xchg2] = i.types[xchg1];
4648 i.types[xchg1] = temp_type;
4649 temp_op = i.op[xchg2];
4650 i.op[xchg2] = i.op[xchg1];
4651 i.op[xchg1] = temp_op;
4652 temp_reloc = i.reloc[xchg2];
4653 i.reloc[xchg2] = i.reloc[xchg1];
4654 i.reloc[xchg1] = temp_reloc;
4655
4656 if (i.mask)
4657 {
4658 if (i.mask->operand == xchg1)
4659 i.mask->operand = xchg2;
4660 else if (i.mask->operand == xchg2)
4661 i.mask->operand = xchg1;
4662 }
4663 if (i.broadcast)
4664 {
4665 if (i.broadcast->operand == xchg1)
4666 i.broadcast->operand = xchg2;
4667 else if (i.broadcast->operand == xchg2)
4668 i.broadcast->operand = xchg1;
4669 }
4670 if (i.rounding)
4671 {
4672 if (i.rounding->operand == xchg1)
4673 i.rounding->operand = xchg2;
4674 else if (i.rounding->operand == xchg2)
4675 i.rounding->operand = xchg1;
4676 }
4677 }
4678
4679 static void
4680 swap_operands (void)
4681 {
4682 switch (i.operands)
4683 {
4684 case 5:
4685 case 4:
4686 swap_2_operands (1, i.operands - 2);
4687 /* Fall through. */
4688 case 3:
4689 case 2:
4690 swap_2_operands (0, i.operands - 1);
4691 break;
4692 default:
4693 abort ();
4694 }
4695
4696 if (i.mem_operands == 2)
4697 {
4698 const seg_entry *temp_seg;
4699 temp_seg = i.seg[0];
4700 i.seg[0] = i.seg[1];
4701 i.seg[1] = temp_seg;
4702 }
4703 }
4704
4705 /* Try to ensure constant immediates are represented in the smallest
4706 opcode possible. */
4707 static void
4708 optimize_imm (void)
4709 {
4710 char guess_suffix = 0;
4711 int op;
4712
4713 if (i.suffix)
4714 guess_suffix = i.suffix;
4715 else if (i.reg_operands)
4716 {
4717 /* Figure out a suffix from the last register operand specified.
4718 We can't do this properly yet, ie. excluding InOutPortReg,
4719 but the following works for instructions with immediates.
4720 In any case, we can't set i.suffix yet. */
4721 for (op = i.operands; --op >= 0;)
4722 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4723 {
4724 guess_suffix = BYTE_MNEM_SUFFIX;
4725 break;
4726 }
4727 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4728 {
4729 guess_suffix = WORD_MNEM_SUFFIX;
4730 break;
4731 }
4732 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4733 {
4734 guess_suffix = LONG_MNEM_SUFFIX;
4735 break;
4736 }
4737 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4738 {
4739 guess_suffix = QWORD_MNEM_SUFFIX;
4740 break;
4741 }
4742 }
4743 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4744 guess_suffix = WORD_MNEM_SUFFIX;
4745
4746 for (op = i.operands; --op >= 0;)
4747 if (operand_type_check (i.types[op], imm))
4748 {
4749 switch (i.op[op].imms->X_op)
4750 {
4751 case O_constant:
4752 /* If a suffix is given, this operand may be shortened. */
4753 switch (guess_suffix)
4754 {
4755 case LONG_MNEM_SUFFIX:
4756 i.types[op].bitfield.imm32 = 1;
4757 i.types[op].bitfield.imm64 = 1;
4758 break;
4759 case WORD_MNEM_SUFFIX:
4760 i.types[op].bitfield.imm16 = 1;
4761 i.types[op].bitfield.imm32 = 1;
4762 i.types[op].bitfield.imm32s = 1;
4763 i.types[op].bitfield.imm64 = 1;
4764 break;
4765 case BYTE_MNEM_SUFFIX:
4766 i.types[op].bitfield.imm8 = 1;
4767 i.types[op].bitfield.imm8s = 1;
4768 i.types[op].bitfield.imm16 = 1;
4769 i.types[op].bitfield.imm32 = 1;
4770 i.types[op].bitfield.imm32s = 1;
4771 i.types[op].bitfield.imm64 = 1;
4772 break;
4773 }
4774
4775 /* If this operand is at most 16 bits, convert it
4776 to a signed 16 bit number before trying to see
4777 whether it will fit in an even smaller size.
4778 This allows a 16-bit operand such as $0xffe0 to
4779 be recognised as within Imm8S range. */
4780 if ((i.types[op].bitfield.imm16)
4781 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4782 {
4783 i.op[op].imms->X_add_number =
4784 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4785 }
4786 #ifdef BFD64
4787 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4788 if ((i.types[op].bitfield.imm32)
4789 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4790 == 0))
4791 {
4792 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4793 ^ ((offsetT) 1 << 31))
4794 - ((offsetT) 1 << 31));
4795 }
4796 #endif
4797 i.types[op]
4798 = operand_type_or (i.types[op],
4799 smallest_imm_type (i.op[op].imms->X_add_number));
4800
4801 /* We must avoid matching of Imm32 templates when 64bit
4802 only immediate is available. */
4803 if (guess_suffix == QWORD_MNEM_SUFFIX)
4804 i.types[op].bitfield.imm32 = 0;
4805 break;
4806
4807 case O_absent:
4808 case O_register:
4809 abort ();
4810
4811 /* Symbols and expressions. */
4812 default:
4813 /* Convert symbolic operand to proper sizes for matching, but don't
4814 prevent matching a set of insns that only supports sizes other
4815 than those matching the insn suffix. */
4816 {
4817 i386_operand_type mask, allowed;
4818 const insn_template *t;
4819
4820 operand_type_set (&mask, 0);
4821 operand_type_set (&allowed, 0);
4822
4823 for (t = current_templates->start;
4824 t < current_templates->end;
4825 ++t)
4826 allowed = operand_type_or (allowed,
4827 t->operand_types[op]);
4828 switch (guess_suffix)
4829 {
4830 case QWORD_MNEM_SUFFIX:
4831 mask.bitfield.imm64 = 1;
4832 mask.bitfield.imm32s = 1;
4833 break;
4834 case LONG_MNEM_SUFFIX:
4835 mask.bitfield.imm32 = 1;
4836 break;
4837 case WORD_MNEM_SUFFIX:
4838 mask.bitfield.imm16 = 1;
4839 break;
4840 case BYTE_MNEM_SUFFIX:
4841 mask.bitfield.imm8 = 1;
4842 break;
4843 default:
4844 break;
4845 }
4846 allowed = operand_type_and (mask, allowed);
4847 if (!operand_type_all_zero (&allowed))
4848 i.types[op] = operand_type_and (i.types[op], mask);
4849 }
4850 break;
4851 }
4852 }
4853 }
4854
4855 /* Try to use the smallest displacement type too. */
4856 static void
4857 optimize_disp (void)
4858 {
4859 int op;
4860
4861 for (op = i.operands; --op >= 0;)
4862 if (operand_type_check (i.types[op], disp))
4863 {
4864 if (i.op[op].disps->X_op == O_constant)
4865 {
4866 offsetT op_disp = i.op[op].disps->X_add_number;
4867
4868 if (i.types[op].bitfield.disp16
4869 && (op_disp & ~(offsetT) 0xffff) == 0)
4870 {
4871 /* If this operand is at most 16 bits, convert
4872 to a signed 16 bit number and don't use 64bit
4873 displacement. */
4874 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4875 i.types[op].bitfield.disp64 = 0;
4876 }
4877 #ifdef BFD64
4878 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4879 if (i.types[op].bitfield.disp32
4880 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4881 {
4882 /* If this operand is at most 32 bits, convert
4883 to a signed 32 bit number and don't use 64bit
4884 displacement. */
4885 op_disp &= (((offsetT) 2 << 31) - 1);
4886 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4887 i.types[op].bitfield.disp64 = 0;
4888 }
4889 #endif
4890 if (!op_disp && i.types[op].bitfield.baseindex)
4891 {
4892 i.types[op].bitfield.disp8 = 0;
4893 i.types[op].bitfield.disp16 = 0;
4894 i.types[op].bitfield.disp32 = 0;
4895 i.types[op].bitfield.disp32s = 0;
4896 i.types[op].bitfield.disp64 = 0;
4897 i.op[op].disps = 0;
4898 i.disp_operands--;
4899 }
4900 else if (flag_code == CODE_64BIT)
4901 {
4902 if (fits_in_signed_long (op_disp))
4903 {
4904 i.types[op].bitfield.disp64 = 0;
4905 i.types[op].bitfield.disp32s = 1;
4906 }
4907 if (i.prefix[ADDR_PREFIX]
4908 && fits_in_unsigned_long (op_disp))
4909 i.types[op].bitfield.disp32 = 1;
4910 }
4911 if ((i.types[op].bitfield.disp32
4912 || i.types[op].bitfield.disp32s
4913 || i.types[op].bitfield.disp16)
4914 && fits_in_disp8 (op_disp))
4915 i.types[op].bitfield.disp8 = 1;
4916 }
4917 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4918 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4919 {
4920 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4921 i.op[op].disps, 0, i.reloc[op]);
4922 i.types[op].bitfield.disp8 = 0;
4923 i.types[op].bitfield.disp16 = 0;
4924 i.types[op].bitfield.disp32 = 0;
4925 i.types[op].bitfield.disp32s = 0;
4926 i.types[op].bitfield.disp64 = 0;
4927 }
4928 else
4929 /* We only support 64bit displacement on constants. */
4930 i.types[op].bitfield.disp64 = 0;
4931 }
4932 }
4933
4934 /* Check if operands are valid for the instruction. */
4935
4936 static int
4937 check_VecOperands (const insn_template *t)
4938 {
4939 unsigned int op;
4940
4941 /* Without VSIB byte, we can't have a vector register for index. */
4942 if (!t->opcode_modifier.vecsib
4943 && i.index_reg
4944 && (i.index_reg->reg_type.bitfield.xmmword
4945 || i.index_reg->reg_type.bitfield.ymmword
4946 || i.index_reg->reg_type.bitfield.zmmword))
4947 {
4948 i.error = unsupported_vector_index_register;
4949 return 1;
4950 }
4951
4952 /* Check if default mask is allowed. */
4953 if (t->opcode_modifier.nodefmask
4954 && (!i.mask || i.mask->mask->reg_num == 0))
4955 {
4956 i.error = no_default_mask;
4957 return 1;
4958 }
4959
4960 /* For VSIB byte, we need a vector register for index, and all vector
4961 registers must be distinct. */
4962 if (t->opcode_modifier.vecsib)
4963 {
4964 if (!i.index_reg
4965 || !((t->opcode_modifier.vecsib == VecSIB128
4966 && i.index_reg->reg_type.bitfield.xmmword)
4967 || (t->opcode_modifier.vecsib == VecSIB256
4968 && i.index_reg->reg_type.bitfield.ymmword)
4969 || (t->opcode_modifier.vecsib == VecSIB512
4970 && i.index_reg->reg_type.bitfield.zmmword)))
4971 {
4972 i.error = invalid_vsib_address;
4973 return 1;
4974 }
4975
4976 gas_assert (i.reg_operands == 2 || i.mask);
4977 if (i.reg_operands == 2 && !i.mask)
4978 {
4979 gas_assert (i.types[0].bitfield.regsimd);
4980 gas_assert (i.types[0].bitfield.xmmword
4981 || i.types[0].bitfield.ymmword);
4982 gas_assert (i.types[2].bitfield.regsimd);
4983 gas_assert (i.types[2].bitfield.xmmword
4984 || i.types[2].bitfield.ymmword);
4985 if (operand_check == check_none)
4986 return 0;
4987 if (register_number (i.op[0].regs)
4988 != register_number (i.index_reg)
4989 && register_number (i.op[2].regs)
4990 != register_number (i.index_reg)
4991 && register_number (i.op[0].regs)
4992 != register_number (i.op[2].regs))
4993 return 0;
4994 if (operand_check == check_error)
4995 {
4996 i.error = invalid_vector_register_set;
4997 return 1;
4998 }
4999 as_warn (_("mask, index, and destination registers should be distinct"));
5000 }
5001 else if (i.reg_operands == 1 && i.mask)
5002 {
5003 if (i.types[1].bitfield.regsimd
5004 && (i.types[1].bitfield.xmmword
5005 || i.types[1].bitfield.ymmword
5006 || i.types[1].bitfield.zmmword)
5007 && (register_number (i.op[1].regs)
5008 == register_number (i.index_reg)))
5009 {
5010 if (operand_check == check_error)
5011 {
5012 i.error = invalid_vector_register_set;
5013 return 1;
5014 }
5015 if (operand_check != check_none)
5016 as_warn (_("index and destination registers should be distinct"));
5017 }
5018 }
5019 }
5020
5021 /* Check if broadcast is supported by the instruction and is applied
5022 to the memory operand. */
5023 if (i.broadcast)
5024 {
5025 int broadcasted_opnd_size;
5026
5027 /* Check if specified broadcast is supported in this instruction,
5028 and it's applied to memory operand of DWORD or QWORD type,
5029 depending on VecESize. */
5030 if (i.broadcast->type != t->opcode_modifier.broadcast
5031 || !i.types[i.broadcast->operand].bitfield.mem
5032 || (t->opcode_modifier.vecesize == 0
5033 && !i.types[i.broadcast->operand].bitfield.dword
5034 && !i.types[i.broadcast->operand].bitfield.unspecified)
5035 || (t->opcode_modifier.vecesize == 1
5036 && !i.types[i.broadcast->operand].bitfield.qword
5037 && !i.types[i.broadcast->operand].bitfield.unspecified))
5038 goto bad_broadcast;
5039
5040 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5041 if (i.broadcast->type == BROADCAST_1TO16)
5042 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5043 else if (i.broadcast->type == BROADCAST_1TO8)
5044 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5045 else if (i.broadcast->type == BROADCAST_1TO4)
5046 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5047 else if (i.broadcast->type == BROADCAST_1TO2)
5048 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5049 else
5050 goto bad_broadcast;
5051
5052 if ((broadcasted_opnd_size == 256
5053 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5054 || (broadcasted_opnd_size == 512
5055 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5056 {
5057 bad_broadcast:
5058 i.error = unsupported_broadcast;
5059 return 1;
5060 }
5061 }
5062 /* If broadcast is supported in this instruction, we need to check if
5063 operand of one-element size isn't specified without broadcast. */
5064 else if (t->opcode_modifier.broadcast && i.mem_operands)
5065 {
5066 /* Find memory operand. */
5067 for (op = 0; op < i.operands; op++)
5068 if (operand_type_check (i.types[op], anymem))
5069 break;
5070 gas_assert (op < i.operands);
5071 /* Check size of the memory operand. */
5072 if ((t->opcode_modifier.vecesize == 0
5073 && i.types[op].bitfield.dword)
5074 || (t->opcode_modifier.vecesize == 1
5075 && i.types[op].bitfield.qword))
5076 {
5077 i.error = broadcast_needed;
5078 return 1;
5079 }
5080 }
5081
5082 /* Check if requested masking is supported. */
5083 if (i.mask
5084 && (!t->opcode_modifier.masking
5085 || (i.mask->zeroing
5086 && t->opcode_modifier.masking == MERGING_MASKING)))
5087 {
5088 i.error = unsupported_masking;
5089 return 1;
5090 }
5091
5092 /* Check if masking is applied to dest operand. */
5093 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5094 {
5095 i.error = mask_not_on_destination;
5096 return 1;
5097 }
5098
5099 /* Check RC/SAE. */
5100 if (i.rounding)
5101 {
5102 if ((i.rounding->type != saeonly
5103 && !t->opcode_modifier.staticrounding)
5104 || (i.rounding->type == saeonly
5105 && (t->opcode_modifier.staticrounding
5106 || !t->opcode_modifier.sae)))
5107 {
5108 i.error = unsupported_rc_sae;
5109 return 1;
5110 }
5111 /* If the instruction has several immediate operands and one of
5112 them is rounding, the rounding operand should be the last
5113 immediate operand. */
5114 if (i.imm_operands > 1
5115 && i.rounding->operand != (int) (i.imm_operands - 1))
5116 {
5117 i.error = rc_sae_operand_not_last_imm;
5118 return 1;
5119 }
5120 }
5121
5122 /* Check vector Disp8 operand. */
5123 if (t->opcode_modifier.disp8memshift
5124 && i.disp_encoding != disp_encoding_32bit)
5125 {
5126 if (i.broadcast)
5127 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5128 else
5129 i.memshift = t->opcode_modifier.disp8memshift;
5130
5131 for (op = 0; op < i.operands; op++)
5132 if (operand_type_check (i.types[op], disp)
5133 && i.op[op].disps->X_op == O_constant)
5134 {
5135 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5136 {
5137 i.types[op].bitfield.disp8 = 1;
5138 return 0;
5139 }
5140 i.types[op].bitfield.disp8 = 0;
5141 }
5142 }
5143
5144 i.memshift = 0;
5145
5146 return 0;
5147 }
5148
5149 /* Check if operands are valid for the instruction. Update VEX
5150 operand types. */
5151
5152 static int
5153 VEX_check_operands (const insn_template *t)
5154 {
5155 if (i.vec_encoding == vex_encoding_evex)
5156 {
5157 /* This instruction must be encoded with EVEX prefix. */
5158 if (!t->opcode_modifier.evex)
5159 {
5160 i.error = unsupported;
5161 return 1;
5162 }
5163 return 0;
5164 }
5165
5166 if (!t->opcode_modifier.vex)
5167 {
5168 /* This instruction template doesn't have VEX prefix. */
5169 if (i.vec_encoding != vex_encoding_default)
5170 {
5171 i.error = unsupported;
5172 return 1;
5173 }
5174 return 0;
5175 }
5176
5177 /* Only check VEX_Imm4, which must be the first operand. */
5178 if (t->operand_types[0].bitfield.vec_imm4)
5179 {
5180 if (i.op[0].imms->X_op != O_constant
5181 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5182 {
5183 i.error = bad_imm4;
5184 return 1;
5185 }
5186
5187 /* Turn off Imm8 so that update_imm won't complain. */
5188 i.types[0] = vec_imm4;
5189 }
5190
5191 return 0;
5192 }
5193
5194 static const insn_template *
5195 match_template (char mnem_suffix)
5196 {
5197 /* Points to template once we've found it. */
5198 const insn_template *t;
5199 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5200 i386_operand_type overlap4;
5201 unsigned int found_reverse_match;
5202 i386_opcode_modifier suffix_check, mnemsuf_check;
5203 i386_operand_type operand_types [MAX_OPERANDS];
5204 int addr_prefix_disp;
5205 unsigned int j;
5206 unsigned int found_cpu_match;
5207 unsigned int check_register;
5208 enum i386_error specific_error = 0;
5209
5210 #if MAX_OPERANDS != 5
5211 # error "MAX_OPERANDS must be 5."
5212 #endif
5213
5214 found_reverse_match = 0;
5215 addr_prefix_disp = -1;
5216
5217 memset (&suffix_check, 0, sizeof (suffix_check));
5218 if (i.suffix == BYTE_MNEM_SUFFIX)
5219 suffix_check.no_bsuf = 1;
5220 else if (i.suffix == WORD_MNEM_SUFFIX)
5221 suffix_check.no_wsuf = 1;
5222 else if (i.suffix == SHORT_MNEM_SUFFIX)
5223 suffix_check.no_ssuf = 1;
5224 else if (i.suffix == LONG_MNEM_SUFFIX)
5225 suffix_check.no_lsuf = 1;
5226 else if (i.suffix == QWORD_MNEM_SUFFIX)
5227 suffix_check.no_qsuf = 1;
5228 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5229 suffix_check.no_ldsuf = 1;
5230
5231 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5232 if (intel_syntax)
5233 {
5234 switch (mnem_suffix)
5235 {
5236 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5237 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5238 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5239 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5240 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5241 }
5242 }
5243
5244 /* Must have right number of operands. */
5245 i.error = number_of_operands_mismatch;
5246
5247 for (t = current_templates->start; t < current_templates->end; t++)
5248 {
5249 addr_prefix_disp = -1;
5250
5251 if (i.operands != t->operands)
5252 continue;
5253
5254 /* Check processor support. */
5255 i.error = unsupported;
5256 found_cpu_match = (cpu_flags_match (t)
5257 == CPU_FLAGS_PERFECT_MATCH);
5258 if (!found_cpu_match)
5259 continue;
5260
5261 /* Check old gcc support. */
5262 i.error = old_gcc_only;
5263 if (!old_gcc && t->opcode_modifier.oldgcc)
5264 continue;
5265
5266 /* Check AT&T mnemonic. */
5267 i.error = unsupported_with_intel_mnemonic;
5268 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5269 continue;
5270
5271 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5272 i.error = unsupported_syntax;
5273 if ((intel_syntax && t->opcode_modifier.attsyntax)
5274 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5275 || (intel64 && t->opcode_modifier.amd64)
5276 || (!intel64 && t->opcode_modifier.intel64))
5277 continue;
5278
5279 /* Check the suffix, except for some instructions in intel mode. */
5280 i.error = invalid_instruction_suffix;
5281 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5282 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5283 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5284 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5285 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5286 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5287 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5288 continue;
5289 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5290 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5291 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5292 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5293 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5294 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5295 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5296 continue;
5297
5298 if (!operand_size_match (t))
5299 continue;
5300
5301 for (j = 0; j < MAX_OPERANDS; j++)
5302 operand_types[j] = t->operand_types[j];
5303
5304 /* In general, don't allow 64-bit operands in 32-bit mode. */
5305 if (i.suffix == QWORD_MNEM_SUFFIX
5306 && flag_code != CODE_64BIT
5307 && (intel_syntax
5308 ? (!t->opcode_modifier.ignoresize
5309 && !intel_float_operand (t->name))
5310 : intel_float_operand (t->name) != 2)
5311 && ((!operand_types[0].bitfield.regmmx
5312 && !operand_types[0].bitfield.regsimd)
5313 || (!operand_types[t->operands > 1].bitfield.regmmx
5314 && !operand_types[t->operands > 1].bitfield.regsimd))
5315 && (t->base_opcode != 0x0fc7
5316 || t->extension_opcode != 1 /* cmpxchg8b */))
5317 continue;
5318
5319 /* In general, don't allow 32-bit operands on pre-386. */
5320 else if (i.suffix == LONG_MNEM_SUFFIX
5321 && !cpu_arch_flags.bitfield.cpui386
5322 && (intel_syntax
5323 ? (!t->opcode_modifier.ignoresize
5324 && !intel_float_operand (t->name))
5325 : intel_float_operand (t->name) != 2)
5326 && ((!operand_types[0].bitfield.regmmx
5327 && !operand_types[0].bitfield.regsimd)
5328 || (!operand_types[t->operands > 1].bitfield.regmmx
5329 && !operand_types[t->operands > 1].bitfield.regsimd)))
5330 continue;
5331
5332 /* Do not verify operands when there are none. */
5333 else
5334 {
5335 if (!t->operands)
5336 /* We've found a match; break out of loop. */
5337 break;
5338 }
5339
5340 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5341 into Disp32/Disp16/Disp32 operand. */
5342 if (i.prefix[ADDR_PREFIX] != 0)
5343 {
5344 /* There should be only one Disp operand. */
5345 switch (flag_code)
5346 {
5347 case CODE_16BIT:
5348 for (j = 0; j < MAX_OPERANDS; j++)
5349 {
5350 if (operand_types[j].bitfield.disp16)
5351 {
5352 addr_prefix_disp = j;
5353 operand_types[j].bitfield.disp32 = 1;
5354 operand_types[j].bitfield.disp16 = 0;
5355 break;
5356 }
5357 }
5358 break;
5359 case CODE_32BIT:
5360 for (j = 0; j < MAX_OPERANDS; j++)
5361 {
5362 if (operand_types[j].bitfield.disp32)
5363 {
5364 addr_prefix_disp = j;
5365 operand_types[j].bitfield.disp32 = 0;
5366 operand_types[j].bitfield.disp16 = 1;
5367 break;
5368 }
5369 }
5370 break;
5371 case CODE_64BIT:
5372 for (j = 0; j < MAX_OPERANDS; j++)
5373 {
5374 if (operand_types[j].bitfield.disp64)
5375 {
5376 addr_prefix_disp = j;
5377 operand_types[j].bitfield.disp64 = 0;
5378 operand_types[j].bitfield.disp32 = 1;
5379 break;
5380 }
5381 }
5382 break;
5383 }
5384 }
5385
5386 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5387 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5388 continue;
5389
5390 /* We check register size if needed. */
5391 check_register = t->opcode_modifier.checkregsize;
5392 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5393 switch (t->operands)
5394 {
5395 case 1:
5396 if (!operand_type_match (overlap0, i.types[0]))
5397 continue;
5398 break;
5399 case 2:
5400 /* xchg %eax, %eax is a special case. It is an alias for nop
5401 only in 32bit mode and we can use opcode 0x90. In 64bit
5402 mode, we can't use 0x90 for xchg %eax, %eax since it should
5403 zero-extend %eax to %rax. */
5404 if (flag_code == CODE_64BIT
5405 && t->base_opcode == 0x90
5406 && operand_type_equal (&i.types [0], &acc32)
5407 && operand_type_equal (&i.types [1], &acc32))
5408 continue;
5409 /* If we want store form, we reverse direction of operands. */
5410 if (i.dir_encoding == dir_encoding_store
5411 && t->opcode_modifier.d)
5412 goto check_reverse;
5413 /* Fall through. */
5414
5415 case 3:
5416 /* If we want store form, we skip the current load. */
5417 if (i.dir_encoding == dir_encoding_store
5418 && i.mem_operands == 0
5419 && t->opcode_modifier.load)
5420 continue;
5421 /* Fall through. */
5422 case 4:
5423 case 5:
5424 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5425 if (!operand_type_match (overlap0, i.types[0])
5426 || !operand_type_match (overlap1, i.types[1])
5427 || (check_register
5428 && !operand_type_register_match (i.types[0],
5429 operand_types[0],
5430 i.types[1],
5431 operand_types[1])))
5432 {
5433 /* Check if other direction is valid ... */
5434 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5435 continue;
5436
5437 check_reverse:
5438 /* Try reversing direction of operands. */
5439 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5440 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5441 if (!operand_type_match (overlap0, i.types[0])
5442 || !operand_type_match (overlap1, i.types[1])
5443 || (check_register
5444 && !operand_type_register_match (i.types[0],
5445 operand_types[1],
5446 i.types[1],
5447 operand_types[0])))
5448 {
5449 /* Does not match either direction. */
5450 continue;
5451 }
5452 /* found_reverse_match holds which of D or FloatDR
5453 we've found. */
5454 if (t->opcode_modifier.d)
5455 found_reverse_match = Opcode_D;
5456 else if (t->opcode_modifier.floatd)
5457 found_reverse_match = Opcode_FloatD;
5458 else
5459 found_reverse_match = 0;
5460 if (t->opcode_modifier.floatr)
5461 found_reverse_match |= Opcode_FloatR;
5462 }
5463 else
5464 {
5465 /* Found a forward 2 operand match here. */
5466 switch (t->operands)
5467 {
5468 case 5:
5469 overlap4 = operand_type_and (i.types[4],
5470 operand_types[4]);
5471 /* Fall through. */
5472 case 4:
5473 overlap3 = operand_type_and (i.types[3],
5474 operand_types[3]);
5475 /* Fall through. */
5476 case 3:
5477 overlap2 = operand_type_and (i.types[2],
5478 operand_types[2]);
5479 break;
5480 }
5481
5482 switch (t->operands)
5483 {
5484 case 5:
5485 if (!operand_type_match (overlap4, i.types[4])
5486 || !operand_type_register_match (i.types[3],
5487 operand_types[3],
5488 i.types[4],
5489 operand_types[4]))
5490 continue;
5491 /* Fall through. */
5492 case 4:
5493 if (!operand_type_match (overlap3, i.types[3])
5494 || (check_register
5495 && !operand_type_register_match (i.types[2],
5496 operand_types[2],
5497 i.types[3],
5498 operand_types[3])))
5499 continue;
5500 /* Fall through. */
5501 case 3:
5502 /* Here we make use of the fact that there are no
5503 reverse match 3 operand instructions, and all 3
5504 operand instructions only need to be checked for
5505 register consistency between operands 2 and 3. */
5506 if (!operand_type_match (overlap2, i.types[2])
5507 || (check_register
5508 && !operand_type_register_match (i.types[1],
5509 operand_types[1],
5510 i.types[2],
5511 operand_types[2])))
5512 continue;
5513 break;
5514 }
5515 }
5516 /* Found either forward/reverse 2, 3 or 4 operand match here:
5517 slip through to break. */
5518 }
5519 if (!found_cpu_match)
5520 {
5521 found_reverse_match = 0;
5522 continue;
5523 }
5524
5525 /* Check if vector and VEX operands are valid. */
5526 if (check_VecOperands (t) || VEX_check_operands (t))
5527 {
5528 specific_error = i.error;
5529 continue;
5530 }
5531
5532 /* We've found a match; break out of loop. */
5533 break;
5534 }
5535
5536 if (t == current_templates->end)
5537 {
5538 /* We found no match. */
5539 const char *err_msg;
5540 switch (specific_error ? specific_error : i.error)
5541 {
5542 default:
5543 abort ();
5544 case operand_size_mismatch:
5545 err_msg = _("operand size mismatch");
5546 break;
5547 case operand_type_mismatch:
5548 err_msg = _("operand type mismatch");
5549 break;
5550 case register_type_mismatch:
5551 err_msg = _("register type mismatch");
5552 break;
5553 case number_of_operands_mismatch:
5554 err_msg = _("number of operands mismatch");
5555 break;
5556 case invalid_instruction_suffix:
5557 err_msg = _("invalid instruction suffix");
5558 break;
5559 case bad_imm4:
5560 err_msg = _("constant doesn't fit in 4 bits");
5561 break;
5562 case old_gcc_only:
5563 err_msg = _("only supported with old gcc");
5564 break;
5565 case unsupported_with_intel_mnemonic:
5566 err_msg = _("unsupported with Intel mnemonic");
5567 break;
5568 case unsupported_syntax:
5569 err_msg = _("unsupported syntax");
5570 break;
5571 case unsupported:
5572 as_bad (_("unsupported instruction `%s'"),
5573 current_templates->start->name);
5574 return NULL;
5575 case invalid_vsib_address:
5576 err_msg = _("invalid VSIB address");
5577 break;
5578 case invalid_vector_register_set:
5579 err_msg = _("mask, index, and destination registers must be distinct");
5580 break;
5581 case unsupported_vector_index_register:
5582 err_msg = _("unsupported vector index register");
5583 break;
5584 case unsupported_broadcast:
5585 err_msg = _("unsupported broadcast");
5586 break;
5587 case broadcast_not_on_src_operand:
5588 err_msg = _("broadcast not on source memory operand");
5589 break;
5590 case broadcast_needed:
5591 err_msg = _("broadcast is needed for operand of such type");
5592 break;
5593 case unsupported_masking:
5594 err_msg = _("unsupported masking");
5595 break;
5596 case mask_not_on_destination:
5597 err_msg = _("mask not on destination operand");
5598 break;
5599 case no_default_mask:
5600 err_msg = _("default mask isn't allowed");
5601 break;
5602 case unsupported_rc_sae:
5603 err_msg = _("unsupported static rounding/sae");
5604 break;
5605 case rc_sae_operand_not_last_imm:
5606 if (intel_syntax)
5607 err_msg = _("RC/SAE operand must precede immediate operands");
5608 else
5609 err_msg = _("RC/SAE operand must follow immediate operands");
5610 break;
5611 case invalid_register_operand:
5612 err_msg = _("invalid register operand");
5613 break;
5614 }
5615 as_bad (_("%s for `%s'"), err_msg,
5616 current_templates->start->name);
5617 return NULL;
5618 }
5619
5620 if (!quiet_warnings)
5621 {
5622 if (!intel_syntax
5623 && (i.types[0].bitfield.jumpabsolute
5624 != operand_types[0].bitfield.jumpabsolute))
5625 {
5626 as_warn (_("indirect %s without `*'"), t->name);
5627 }
5628
5629 if (t->opcode_modifier.isprefix
5630 && t->opcode_modifier.ignoresize)
5631 {
5632 /* Warn them that a data or address size prefix doesn't
5633 affect assembly of the next line of code. */
5634 as_warn (_("stand-alone `%s' prefix"), t->name);
5635 }
5636 }
5637
5638 /* Copy the template we found. */
5639 i.tm = *t;
5640
5641 if (addr_prefix_disp != -1)
5642 i.tm.operand_types[addr_prefix_disp]
5643 = operand_types[addr_prefix_disp];
5644
5645 if (found_reverse_match)
5646 {
5647 /* If we found a reverse match we must alter the opcode
5648 direction bit. found_reverse_match holds bits to change
5649 (different for int & float insns). */
5650
5651 i.tm.base_opcode ^= found_reverse_match;
5652
5653 i.tm.operand_types[0] = operand_types[1];
5654 i.tm.operand_types[1] = operand_types[0];
5655 }
5656
5657 return t;
5658 }
5659
5660 static int
5661 check_string (void)
5662 {
5663 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5664 if (i.tm.operand_types[mem_op].bitfield.esseg)
5665 {
5666 if (i.seg[0] != NULL && i.seg[0] != &es)
5667 {
5668 as_bad (_("`%s' operand %d must use `%ses' segment"),
5669 i.tm.name,
5670 mem_op + 1,
5671 register_prefix);
5672 return 0;
5673 }
5674 /* There's only ever one segment override allowed per instruction.
5675 This instruction possibly has a legal segment override on the
5676 second operand, so copy the segment to where non-string
5677 instructions store it, allowing common code. */
5678 i.seg[0] = i.seg[1];
5679 }
5680 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5681 {
5682 if (i.seg[1] != NULL && i.seg[1] != &es)
5683 {
5684 as_bad (_("`%s' operand %d must use `%ses' segment"),
5685 i.tm.name,
5686 mem_op + 2,
5687 register_prefix);
5688 return 0;
5689 }
5690 }
5691 return 1;
5692 }
5693
5694 static int
5695 process_suffix (void)
5696 {
5697 /* If matched instruction specifies an explicit instruction mnemonic
5698 suffix, use it. */
5699 if (i.tm.opcode_modifier.size16)
5700 i.suffix = WORD_MNEM_SUFFIX;
5701 else if (i.tm.opcode_modifier.size32)
5702 i.suffix = LONG_MNEM_SUFFIX;
5703 else if (i.tm.opcode_modifier.size64)
5704 i.suffix = QWORD_MNEM_SUFFIX;
5705 else if (i.reg_operands)
5706 {
5707 /* If there's no instruction mnemonic suffix we try to invent one
5708 based on register operands. */
5709 if (!i.suffix)
5710 {
5711 /* We take i.suffix from the last register operand specified,
5712 Destination register type is more significant than source
5713 register type. crc32 in SSE4.2 prefers source register
5714 type. */
5715 if (i.tm.base_opcode == 0xf20f38f1)
5716 {
5717 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5718 i.suffix = WORD_MNEM_SUFFIX;
5719 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5720 i.suffix = LONG_MNEM_SUFFIX;
5721 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5722 i.suffix = QWORD_MNEM_SUFFIX;
5723 }
5724 else if (i.tm.base_opcode == 0xf20f38f0)
5725 {
5726 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5727 i.suffix = BYTE_MNEM_SUFFIX;
5728 }
5729
5730 if (!i.suffix)
5731 {
5732 int op;
5733
5734 if (i.tm.base_opcode == 0xf20f38f1
5735 || i.tm.base_opcode == 0xf20f38f0)
5736 {
5737 /* We have to know the operand size for crc32. */
5738 as_bad (_("ambiguous memory operand size for `%s`"),
5739 i.tm.name);
5740 return 0;
5741 }
5742
5743 for (op = i.operands; --op >= 0;)
5744 if (!i.tm.operand_types[op].bitfield.inoutportreg
5745 && !i.tm.operand_types[op].bitfield.shiftcount)
5746 {
5747 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5748 {
5749 i.suffix = BYTE_MNEM_SUFFIX;
5750 break;
5751 }
5752 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5753 {
5754 i.suffix = WORD_MNEM_SUFFIX;
5755 break;
5756 }
5757 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5758 {
5759 i.suffix = LONG_MNEM_SUFFIX;
5760 break;
5761 }
5762 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5763 {
5764 i.suffix = QWORD_MNEM_SUFFIX;
5765 break;
5766 }
5767 }
5768 }
5769 }
5770 else if (i.suffix == BYTE_MNEM_SUFFIX)
5771 {
5772 if (intel_syntax
5773 && i.tm.opcode_modifier.ignoresize
5774 && i.tm.opcode_modifier.no_bsuf)
5775 i.suffix = 0;
5776 else if (!check_byte_reg ())
5777 return 0;
5778 }
5779 else if (i.suffix == LONG_MNEM_SUFFIX)
5780 {
5781 if (intel_syntax
5782 && i.tm.opcode_modifier.ignoresize
5783 && i.tm.opcode_modifier.no_lsuf)
5784 i.suffix = 0;
5785 else if (!check_long_reg ())
5786 return 0;
5787 }
5788 else if (i.suffix == QWORD_MNEM_SUFFIX)
5789 {
5790 if (intel_syntax
5791 && i.tm.opcode_modifier.ignoresize
5792 && i.tm.opcode_modifier.no_qsuf)
5793 i.suffix = 0;
5794 else if (!check_qword_reg ())
5795 return 0;
5796 }
5797 else if (i.suffix == WORD_MNEM_SUFFIX)
5798 {
5799 if (intel_syntax
5800 && i.tm.opcode_modifier.ignoresize
5801 && i.tm.opcode_modifier.no_wsuf)
5802 i.suffix = 0;
5803 else if (!check_word_reg ())
5804 return 0;
5805 }
5806 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5807 || i.suffix == YMMWORD_MNEM_SUFFIX
5808 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5809 {
5810 /* Skip if the instruction has x/y/z suffix. match_template
5811 should check if it is a valid suffix. */
5812 }
5813 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5814 /* Do nothing if the instruction is going to ignore the prefix. */
5815 ;
5816 else
5817 abort ();
5818 }
5819 else if (i.tm.opcode_modifier.defaultsize
5820 && !i.suffix
5821 /* exclude fldenv/frstor/fsave/fstenv */
5822 && i.tm.opcode_modifier.no_ssuf)
5823 {
5824 i.suffix = stackop_size;
5825 }
5826 else if (intel_syntax
5827 && !i.suffix
5828 && (i.tm.operand_types[0].bitfield.jumpabsolute
5829 || i.tm.opcode_modifier.jumpbyte
5830 || i.tm.opcode_modifier.jumpintersegment
5831 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5832 && i.tm.extension_opcode <= 3)))
5833 {
5834 switch (flag_code)
5835 {
5836 case CODE_64BIT:
5837 if (!i.tm.opcode_modifier.no_qsuf)
5838 {
5839 i.suffix = QWORD_MNEM_SUFFIX;
5840 break;
5841 }
5842 /* Fall through. */
5843 case CODE_32BIT:
5844 if (!i.tm.opcode_modifier.no_lsuf)
5845 i.suffix = LONG_MNEM_SUFFIX;
5846 break;
5847 case CODE_16BIT:
5848 if (!i.tm.opcode_modifier.no_wsuf)
5849 i.suffix = WORD_MNEM_SUFFIX;
5850 break;
5851 }
5852 }
5853
5854 if (!i.suffix)
5855 {
5856 if (!intel_syntax)
5857 {
5858 if (i.tm.opcode_modifier.w)
5859 {
5860 as_bad (_("no instruction mnemonic suffix given and "
5861 "no register operands; can't size instruction"));
5862 return 0;
5863 }
5864 }
5865 else
5866 {
5867 unsigned int suffixes;
5868
5869 suffixes = !i.tm.opcode_modifier.no_bsuf;
5870 if (!i.tm.opcode_modifier.no_wsuf)
5871 suffixes |= 1 << 1;
5872 if (!i.tm.opcode_modifier.no_lsuf)
5873 suffixes |= 1 << 2;
5874 if (!i.tm.opcode_modifier.no_ldsuf)
5875 suffixes |= 1 << 3;
5876 if (!i.tm.opcode_modifier.no_ssuf)
5877 suffixes |= 1 << 4;
5878 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5879 suffixes |= 1 << 5;
5880
5881 /* There are more than suffix matches. */
5882 if (i.tm.opcode_modifier.w
5883 || ((suffixes & (suffixes - 1))
5884 && !i.tm.opcode_modifier.defaultsize
5885 && !i.tm.opcode_modifier.ignoresize))
5886 {
5887 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5888 return 0;
5889 }
5890 }
5891 }
5892
5893 /* Change the opcode based on the operand size given by i.suffix;
5894 We don't need to change things for byte insns. */
5895
5896 if (i.suffix
5897 && i.suffix != BYTE_MNEM_SUFFIX
5898 && i.suffix != XMMWORD_MNEM_SUFFIX
5899 && i.suffix != YMMWORD_MNEM_SUFFIX
5900 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5901 {
5902 /* It's not a byte, select word/dword operation. */
5903 if (i.tm.opcode_modifier.w)
5904 {
5905 if (i.tm.opcode_modifier.shortform)
5906 i.tm.base_opcode |= 8;
5907 else
5908 i.tm.base_opcode |= 1;
5909 }
5910
5911 /* Now select between word & dword operations via the operand
5912 size prefix, except for instructions that will ignore this
5913 prefix anyway. */
5914 if (i.tm.opcode_modifier.addrprefixop0)
5915 {
5916 /* The address size override prefix changes the size of the
5917 first operand. */
5918 if ((flag_code == CODE_32BIT
5919 && i.op->regs[0].reg_type.bitfield.word)
5920 || (flag_code != CODE_32BIT
5921 && i.op->regs[0].reg_type.bitfield.dword))
5922 if (!add_prefix (ADDR_PREFIX_OPCODE))
5923 return 0;
5924 }
5925 else if (i.suffix != QWORD_MNEM_SUFFIX
5926 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5927 && !i.tm.opcode_modifier.ignoresize
5928 && !i.tm.opcode_modifier.floatmf
5929 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5930 || (flag_code == CODE_64BIT
5931 && i.tm.opcode_modifier.jumpbyte)))
5932 {
5933 unsigned int prefix = DATA_PREFIX_OPCODE;
5934
5935 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5936 prefix = ADDR_PREFIX_OPCODE;
5937
5938 if (!add_prefix (prefix))
5939 return 0;
5940 }
5941
5942 /* Set mode64 for an operand. */
5943 if (i.suffix == QWORD_MNEM_SUFFIX
5944 && flag_code == CODE_64BIT
5945 && !i.tm.opcode_modifier.norex64)
5946 {
5947 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5948 need rex64. cmpxchg8b is also a special case. */
5949 if (! (i.operands == 2
5950 && i.tm.base_opcode == 0x90
5951 && i.tm.extension_opcode == None
5952 && operand_type_equal (&i.types [0], &acc64)
5953 && operand_type_equal (&i.types [1], &acc64))
5954 && ! (i.operands == 1
5955 && i.tm.base_opcode == 0xfc7
5956 && i.tm.extension_opcode == 1
5957 && !operand_type_check (i.types [0], reg)
5958 && operand_type_check (i.types [0], anymem)))
5959 i.rex |= REX_W;
5960 }
5961
5962 /* Size floating point instruction. */
5963 if (i.suffix == LONG_MNEM_SUFFIX)
5964 if (i.tm.opcode_modifier.floatmf)
5965 i.tm.base_opcode ^= 4;
5966 }
5967
5968 return 1;
5969 }
5970
5971 static int
5972 check_byte_reg (void)
5973 {
5974 int op;
5975
5976 for (op = i.operands; --op >= 0;)
5977 {
5978 /* Skip non-register operands. */
5979 if (!i.types[op].bitfield.reg)
5980 continue;
5981
5982 /* If this is an eight bit register, it's OK. If it's the 16 or
5983 32 bit version of an eight bit register, we will just use the
5984 low portion, and that's OK too. */
5985 if (i.types[op].bitfield.byte)
5986 continue;
5987
5988 /* I/O port address operands are OK too. */
5989 if (i.tm.operand_types[op].bitfield.inoutportreg)
5990 continue;
5991
5992 /* crc32 doesn't generate this warning. */
5993 if (i.tm.base_opcode == 0xf20f38f0)
5994 continue;
5995
5996 if ((i.types[op].bitfield.word
5997 || i.types[op].bitfield.dword
5998 || i.types[op].bitfield.qword)
5999 && i.op[op].regs->reg_num < 4
6000 /* Prohibit these changes in 64bit mode, since the lowering
6001 would be more complicated. */
6002 && flag_code != CODE_64BIT)
6003 {
6004 #if REGISTER_WARNINGS
6005 if (!quiet_warnings)
6006 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6007 register_prefix,
6008 (i.op[op].regs + (i.types[op].bitfield.word
6009 ? REGNAM_AL - REGNAM_AX
6010 : REGNAM_AL - REGNAM_EAX))->reg_name,
6011 register_prefix,
6012 i.op[op].regs->reg_name,
6013 i.suffix);
6014 #endif
6015 continue;
6016 }
6017 /* Any other register is bad. */
6018 if (i.types[op].bitfield.reg
6019 || i.types[op].bitfield.regmmx
6020 || i.types[op].bitfield.regsimd
6021 || i.types[op].bitfield.sreg2
6022 || i.types[op].bitfield.sreg3
6023 || i.types[op].bitfield.control
6024 || i.types[op].bitfield.debug
6025 || i.types[op].bitfield.test)
6026 {
6027 as_bad (_("`%s%s' not allowed with `%s%c'"),
6028 register_prefix,
6029 i.op[op].regs->reg_name,
6030 i.tm.name,
6031 i.suffix);
6032 return 0;
6033 }
6034 }
6035 return 1;
6036 }
6037
6038 static int
6039 check_long_reg (void)
6040 {
6041 int op;
6042
6043 for (op = i.operands; --op >= 0;)
6044 /* Skip non-register operands. */
6045 if (!i.types[op].bitfield.reg)
6046 continue;
6047 /* Reject eight bit registers, except where the template requires
6048 them. (eg. movzb) */
6049 else if (i.types[op].bitfield.byte
6050 && (i.tm.operand_types[op].bitfield.reg
6051 || i.tm.operand_types[op].bitfield.acc)
6052 && (i.tm.operand_types[op].bitfield.word
6053 || i.tm.operand_types[op].bitfield.dword))
6054 {
6055 as_bad (_("`%s%s' not allowed with `%s%c'"),
6056 register_prefix,
6057 i.op[op].regs->reg_name,
6058 i.tm.name,
6059 i.suffix);
6060 return 0;
6061 }
6062 /* Warn if the e prefix on a general reg is missing. */
6063 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6064 && i.types[op].bitfield.word
6065 && (i.tm.operand_types[op].bitfield.reg
6066 || i.tm.operand_types[op].bitfield.acc)
6067 && i.tm.operand_types[op].bitfield.dword)
6068 {
6069 /* Prohibit these changes in the 64bit mode, since the
6070 lowering is more complicated. */
6071 if (flag_code == CODE_64BIT)
6072 {
6073 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6074 register_prefix, i.op[op].regs->reg_name,
6075 i.suffix);
6076 return 0;
6077 }
6078 #if REGISTER_WARNINGS
6079 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6080 register_prefix,
6081 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6082 register_prefix, i.op[op].regs->reg_name, i.suffix);
6083 #endif
6084 }
6085 /* Warn if the r prefix on a general reg is present. */
6086 else if (i.types[op].bitfield.qword
6087 && (i.tm.operand_types[op].bitfield.reg
6088 || i.tm.operand_types[op].bitfield.acc)
6089 && i.tm.operand_types[op].bitfield.dword)
6090 {
6091 if (intel_syntax
6092 && i.tm.opcode_modifier.toqword
6093 && !i.types[0].bitfield.regsimd)
6094 {
6095 /* Convert to QWORD. We want REX byte. */
6096 i.suffix = QWORD_MNEM_SUFFIX;
6097 }
6098 else
6099 {
6100 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6101 register_prefix, i.op[op].regs->reg_name,
6102 i.suffix);
6103 return 0;
6104 }
6105 }
6106 return 1;
6107 }
6108
6109 static int
6110 check_qword_reg (void)
6111 {
6112 int op;
6113
6114 for (op = i.operands; --op >= 0; )
6115 /* Skip non-register operands. */
6116 if (!i.types[op].bitfield.reg)
6117 continue;
6118 /* Reject eight bit registers, except where the template requires
6119 them. (eg. movzb) */
6120 else if (i.types[op].bitfield.byte
6121 && (i.tm.operand_types[op].bitfield.reg
6122 || i.tm.operand_types[op].bitfield.acc)
6123 && (i.tm.operand_types[op].bitfield.word
6124 || i.tm.operand_types[op].bitfield.dword))
6125 {
6126 as_bad (_("`%s%s' not allowed with `%s%c'"),
6127 register_prefix,
6128 i.op[op].regs->reg_name,
6129 i.tm.name,
6130 i.suffix);
6131 return 0;
6132 }
6133 /* Warn if the r prefix on a general reg is missing. */
6134 else if ((i.types[op].bitfield.word
6135 || i.types[op].bitfield.dword)
6136 && (i.tm.operand_types[op].bitfield.reg
6137 || i.tm.operand_types[op].bitfield.acc)
6138 && i.tm.operand_types[op].bitfield.qword)
6139 {
6140 /* Prohibit these changes in the 64bit mode, since the
6141 lowering is more complicated. */
6142 if (intel_syntax
6143 && i.tm.opcode_modifier.todword
6144 && !i.types[0].bitfield.regsimd)
6145 {
6146 /* Convert to DWORD. We don't want REX byte. */
6147 i.suffix = LONG_MNEM_SUFFIX;
6148 }
6149 else
6150 {
6151 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6152 register_prefix, i.op[op].regs->reg_name,
6153 i.suffix);
6154 return 0;
6155 }
6156 }
6157 return 1;
6158 }
6159
6160 static int
6161 check_word_reg (void)
6162 {
6163 int op;
6164 for (op = i.operands; --op >= 0;)
6165 /* Skip non-register operands. */
6166 if (!i.types[op].bitfield.reg)
6167 continue;
6168 /* Reject eight bit registers, except where the template requires
6169 them. (eg. movzb) */
6170 else if (i.types[op].bitfield.byte
6171 && (i.tm.operand_types[op].bitfield.reg
6172 || i.tm.operand_types[op].bitfield.acc)
6173 && (i.tm.operand_types[op].bitfield.word
6174 || i.tm.operand_types[op].bitfield.dword))
6175 {
6176 as_bad (_("`%s%s' not allowed with `%s%c'"),
6177 register_prefix,
6178 i.op[op].regs->reg_name,
6179 i.tm.name,
6180 i.suffix);
6181 return 0;
6182 }
6183 /* Warn if the e or r prefix on a general reg is present. */
6184 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6185 && (i.types[op].bitfield.dword
6186 || i.types[op].bitfield.qword)
6187 && (i.tm.operand_types[op].bitfield.reg
6188 || i.tm.operand_types[op].bitfield.acc)
6189 && i.tm.operand_types[op].bitfield.word)
6190 {
6191 /* Prohibit these changes in the 64bit mode, since the
6192 lowering is more complicated. */
6193 if (flag_code == CODE_64BIT)
6194 {
6195 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6196 register_prefix, i.op[op].regs->reg_name,
6197 i.suffix);
6198 return 0;
6199 }
6200 #if REGISTER_WARNINGS
6201 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6202 register_prefix,
6203 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6204 register_prefix, i.op[op].regs->reg_name, i.suffix);
6205 #endif
6206 }
6207 return 1;
6208 }
6209
6210 static int
6211 update_imm (unsigned int j)
6212 {
6213 i386_operand_type overlap = i.types[j];
6214 if ((overlap.bitfield.imm8
6215 || overlap.bitfield.imm8s
6216 || overlap.bitfield.imm16
6217 || overlap.bitfield.imm32
6218 || overlap.bitfield.imm32s
6219 || overlap.bitfield.imm64)
6220 && !operand_type_equal (&overlap, &imm8)
6221 && !operand_type_equal (&overlap, &imm8s)
6222 && !operand_type_equal (&overlap, &imm16)
6223 && !operand_type_equal (&overlap, &imm32)
6224 && !operand_type_equal (&overlap, &imm32s)
6225 && !operand_type_equal (&overlap, &imm64))
6226 {
6227 if (i.suffix)
6228 {
6229 i386_operand_type temp;
6230
6231 operand_type_set (&temp, 0);
6232 if (i.suffix == BYTE_MNEM_SUFFIX)
6233 {
6234 temp.bitfield.imm8 = overlap.bitfield.imm8;
6235 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6236 }
6237 else if (i.suffix == WORD_MNEM_SUFFIX)
6238 temp.bitfield.imm16 = overlap.bitfield.imm16;
6239 else if (i.suffix == QWORD_MNEM_SUFFIX)
6240 {
6241 temp.bitfield.imm64 = overlap.bitfield.imm64;
6242 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6243 }
6244 else
6245 temp.bitfield.imm32 = overlap.bitfield.imm32;
6246 overlap = temp;
6247 }
6248 else if (operand_type_equal (&overlap, &imm16_32_32s)
6249 || operand_type_equal (&overlap, &imm16_32)
6250 || operand_type_equal (&overlap, &imm16_32s))
6251 {
6252 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6253 overlap = imm16;
6254 else
6255 overlap = imm32s;
6256 }
6257 if (!operand_type_equal (&overlap, &imm8)
6258 && !operand_type_equal (&overlap, &imm8s)
6259 && !operand_type_equal (&overlap, &imm16)
6260 && !operand_type_equal (&overlap, &imm32)
6261 && !operand_type_equal (&overlap, &imm32s)
6262 && !operand_type_equal (&overlap, &imm64))
6263 {
6264 as_bad (_("no instruction mnemonic suffix given; "
6265 "can't determine immediate size"));
6266 return 0;
6267 }
6268 }
6269 i.types[j] = overlap;
6270
6271 return 1;
6272 }
6273
6274 static int
6275 finalize_imm (void)
6276 {
6277 unsigned int j, n;
6278
6279 /* Update the first 2 immediate operands. */
6280 n = i.operands > 2 ? 2 : i.operands;
6281 if (n)
6282 {
6283 for (j = 0; j < n; j++)
6284 if (update_imm (j) == 0)
6285 return 0;
6286
6287 /* The 3rd operand can't be immediate operand. */
6288 gas_assert (operand_type_check (i.types[2], imm) == 0);
6289 }
6290
6291 return 1;
6292 }
6293
6294 static int
6295 process_operands (void)
6296 {
6297 /* Default segment register this instruction will use for memory
6298 accesses. 0 means unknown. This is only for optimizing out
6299 unnecessary segment overrides. */
6300 const seg_entry *default_seg = 0;
6301
6302 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6303 {
6304 unsigned int dupl = i.operands;
6305 unsigned int dest = dupl - 1;
6306 unsigned int j;
6307
6308 /* The destination must be an xmm register. */
6309 gas_assert (i.reg_operands
6310 && MAX_OPERANDS > dupl
6311 && operand_type_equal (&i.types[dest], &regxmm));
6312
6313 if (i.tm.operand_types[0].bitfield.acc
6314 && i.tm.operand_types[0].bitfield.xmmword)
6315 {
6316 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6317 {
6318 /* Keep xmm0 for instructions with VEX prefix and 3
6319 sources. */
6320 i.tm.operand_types[0].bitfield.acc = 0;
6321 i.tm.operand_types[0].bitfield.regsimd = 1;
6322 goto duplicate;
6323 }
6324 else
6325 {
6326 /* We remove the first xmm0 and keep the number of
6327 operands unchanged, which in fact duplicates the
6328 destination. */
6329 for (j = 1; j < i.operands; j++)
6330 {
6331 i.op[j - 1] = i.op[j];
6332 i.types[j - 1] = i.types[j];
6333 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6334 }
6335 }
6336 }
6337 else if (i.tm.opcode_modifier.implicit1stxmm0)
6338 {
6339 gas_assert ((MAX_OPERANDS - 1) > dupl
6340 && (i.tm.opcode_modifier.vexsources
6341 == VEX3SOURCES));
6342
6343 /* Add the implicit xmm0 for instructions with VEX prefix
6344 and 3 sources. */
6345 for (j = i.operands; j > 0; j--)
6346 {
6347 i.op[j] = i.op[j - 1];
6348 i.types[j] = i.types[j - 1];
6349 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6350 }
6351 i.op[0].regs
6352 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6353 i.types[0] = regxmm;
6354 i.tm.operand_types[0] = regxmm;
6355
6356 i.operands += 2;
6357 i.reg_operands += 2;
6358 i.tm.operands += 2;
6359
6360 dupl++;
6361 dest++;
6362 i.op[dupl] = i.op[dest];
6363 i.types[dupl] = i.types[dest];
6364 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6365 }
6366 else
6367 {
6368 duplicate:
6369 i.operands++;
6370 i.reg_operands++;
6371 i.tm.operands++;
6372
6373 i.op[dupl] = i.op[dest];
6374 i.types[dupl] = i.types[dest];
6375 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6376 }
6377
6378 if (i.tm.opcode_modifier.immext)
6379 process_immext ();
6380 }
6381 else if (i.tm.operand_types[0].bitfield.acc
6382 && i.tm.operand_types[0].bitfield.xmmword)
6383 {
6384 unsigned int j;
6385
6386 for (j = 1; j < i.operands; j++)
6387 {
6388 i.op[j - 1] = i.op[j];
6389 i.types[j - 1] = i.types[j];
6390
6391 /* We need to adjust fields in i.tm since they are used by
6392 build_modrm_byte. */
6393 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6394 }
6395
6396 i.operands--;
6397 i.reg_operands--;
6398 i.tm.operands--;
6399 }
6400 else if (i.tm.opcode_modifier.implicitquadgroup)
6401 {
6402 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6403 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6404 unsigned int regnum = register_number (i.op[1].regs);
6405 unsigned int first_reg_in_group = regnum & ~3;
6406 unsigned int last_reg_in_group = first_reg_in_group + 3;
6407 if (regnum != first_reg_in_group) {
6408 as_warn (_("the second source register `%s%s' implicitly denotes"
6409 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6410 register_prefix, i.op[1].regs->reg_name,
6411 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6412 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6413 i.tm.name);
6414 }
6415 }
6416 else if (i.tm.opcode_modifier.regkludge)
6417 {
6418 /* The imul $imm, %reg instruction is converted into
6419 imul $imm, %reg, %reg, and the clr %reg instruction
6420 is converted into xor %reg, %reg. */
6421
6422 unsigned int first_reg_op;
6423
6424 if (operand_type_check (i.types[0], reg))
6425 first_reg_op = 0;
6426 else
6427 first_reg_op = 1;
6428 /* Pretend we saw the extra register operand. */
6429 gas_assert (i.reg_operands == 1
6430 && i.op[first_reg_op + 1].regs == 0);
6431 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6432 i.types[first_reg_op + 1] = i.types[first_reg_op];
6433 i.operands++;
6434 i.reg_operands++;
6435 }
6436
6437 if (i.tm.opcode_modifier.shortform)
6438 {
6439 if (i.types[0].bitfield.sreg2
6440 || i.types[0].bitfield.sreg3)
6441 {
6442 if (i.tm.base_opcode == POP_SEG_SHORT
6443 && i.op[0].regs->reg_num == 1)
6444 {
6445 as_bad (_("you can't `pop %scs'"), register_prefix);
6446 return 0;
6447 }
6448 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6449 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6450 i.rex |= REX_B;
6451 }
6452 else
6453 {
6454 /* The register or float register operand is in operand
6455 0 or 1. */
6456 unsigned int op;
6457
6458 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6459 || operand_type_check (i.types[0], reg))
6460 op = 0;
6461 else
6462 op = 1;
6463 /* Register goes in low 3 bits of opcode. */
6464 i.tm.base_opcode |= i.op[op].regs->reg_num;
6465 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6466 i.rex |= REX_B;
6467 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6468 {
6469 /* Warn about some common errors, but press on regardless.
6470 The first case can be generated by gcc (<= 2.8.1). */
6471 if (i.operands == 2)
6472 {
6473 /* Reversed arguments on faddp, fsubp, etc. */
6474 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6475 register_prefix, i.op[!intel_syntax].regs->reg_name,
6476 register_prefix, i.op[intel_syntax].regs->reg_name);
6477 }
6478 else
6479 {
6480 /* Extraneous `l' suffix on fp insn. */
6481 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6482 register_prefix, i.op[0].regs->reg_name);
6483 }
6484 }
6485 }
6486 }
6487 else if (i.tm.opcode_modifier.modrm)
6488 {
6489 /* The opcode is completed (modulo i.tm.extension_opcode which
6490 must be put into the modrm byte). Now, we make the modrm and
6491 index base bytes based on all the info we've collected. */
6492
6493 default_seg = build_modrm_byte ();
6494 }
6495 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6496 {
6497 default_seg = &ds;
6498 }
6499 else if (i.tm.opcode_modifier.isstring)
6500 {
6501 /* For the string instructions that allow a segment override
6502 on one of their operands, the default segment is ds. */
6503 default_seg = &ds;
6504 }
6505
6506 if (i.tm.base_opcode == 0x8d /* lea */
6507 && i.seg[0]
6508 && !quiet_warnings)
6509 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6510
6511 /* If a segment was explicitly specified, and the specified segment
6512 is not the default, use an opcode prefix to select it. If we
6513 never figured out what the default segment is, then default_seg
6514 will be zero at this point, and the specified segment prefix will
6515 always be used. */
6516 if ((i.seg[0]) && (i.seg[0] != default_seg))
6517 {
6518 if (!add_prefix (i.seg[0]->seg_prefix))
6519 return 0;
6520 }
6521 return 1;
6522 }
6523
6524 static const seg_entry *
6525 build_modrm_byte (void)
6526 {
6527 const seg_entry *default_seg = 0;
6528 unsigned int source, dest;
6529 int vex_3_sources;
6530
6531 /* The first operand of instructions with VEX prefix and 3 sources
6532 must be VEX_Imm4. */
6533 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6534 if (vex_3_sources)
6535 {
6536 unsigned int nds, reg_slot;
6537 expressionS *exp;
6538
6539 if (i.tm.opcode_modifier.veximmext
6540 && i.tm.opcode_modifier.immext)
6541 {
6542 dest = i.operands - 2;
6543 gas_assert (dest == 3);
6544 }
6545 else
6546 dest = i.operands - 1;
6547 nds = dest - 1;
6548
6549 /* There are 2 kinds of instructions:
6550 1. 5 operands: 4 register operands or 3 register operands
6551 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6552 VexW0 or VexW1. The destination must be either XMM, YMM or
6553 ZMM register.
6554 2. 4 operands: 4 register operands or 3 register operands
6555 plus 1 memory operand, VexXDS, and VexImmExt */
6556 gas_assert ((i.reg_operands == 4
6557 || (i.reg_operands == 3 && i.mem_operands == 1))
6558 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6559 && (i.tm.opcode_modifier.veximmext
6560 || (i.imm_operands == 1
6561 && i.types[0].bitfield.vec_imm4
6562 && (i.tm.opcode_modifier.vexw == VEXW0
6563 || i.tm.opcode_modifier.vexw == VEXW1)
6564 && i.tm.operand_types[dest].bitfield.regsimd)));
6565
6566 if (i.imm_operands == 0)
6567 {
6568 /* When there is no immediate operand, generate an 8bit
6569 immediate operand to encode the first operand. */
6570 exp = &im_expressions[i.imm_operands++];
6571 i.op[i.operands].imms = exp;
6572 i.types[i.operands] = imm8;
6573 i.operands++;
6574 /* If VexW1 is set, the first operand is the source and
6575 the second operand is encoded in the immediate operand. */
6576 if (i.tm.opcode_modifier.vexw == VEXW1)
6577 {
6578 source = 0;
6579 reg_slot = 1;
6580 }
6581 else
6582 {
6583 source = 1;
6584 reg_slot = 0;
6585 }
6586
6587 /* FMA swaps REG and NDS. */
6588 if (i.tm.cpu_flags.bitfield.cpufma)
6589 {
6590 unsigned int tmp;
6591 tmp = reg_slot;
6592 reg_slot = nds;
6593 nds = tmp;
6594 }
6595
6596 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6597 exp->X_op = O_constant;
6598 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6599 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6600 }
6601 else
6602 {
6603 unsigned int imm_slot;
6604
6605 if (i.tm.opcode_modifier.vexw == VEXW0)
6606 {
6607 /* If VexW0 is set, the third operand is the source and
6608 the second operand is encoded in the immediate
6609 operand. */
6610 source = 2;
6611 reg_slot = 1;
6612 }
6613 else
6614 {
6615 /* VexW1 is set, the second operand is the source and
6616 the third operand is encoded in the immediate
6617 operand. */
6618 source = 1;
6619 reg_slot = 2;
6620 }
6621
6622 if (i.tm.opcode_modifier.immext)
6623 {
6624 /* When ImmExt is set, the immediate byte is the last
6625 operand. */
6626 imm_slot = i.operands - 1;
6627 source--;
6628 reg_slot--;
6629 }
6630 else
6631 {
6632 imm_slot = 0;
6633
6634 /* Turn on Imm8 so that output_imm will generate it. */
6635 i.types[imm_slot].bitfield.imm8 = 1;
6636 }
6637
6638 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6639 i.op[imm_slot].imms->X_add_number
6640 |= register_number (i.op[reg_slot].regs) << 4;
6641 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6642 }
6643
6644 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6645 i.vex.register_specifier = i.op[nds].regs;
6646 }
6647 else
6648 source = dest = 0;
6649
6650 /* i.reg_operands MUST be the number of real register operands;
6651 implicit registers do not count. If there are 3 register
6652 operands, it must be a instruction with VexNDS. For a
6653 instruction with VexNDD, the destination register is encoded
6654 in VEX prefix. If there are 4 register operands, it must be
6655 a instruction with VEX prefix and 3 sources. */
6656 if (i.mem_operands == 0
6657 && ((i.reg_operands == 2
6658 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6659 || (i.reg_operands == 3
6660 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6661 || (i.reg_operands == 4 && vex_3_sources)))
6662 {
6663 switch (i.operands)
6664 {
6665 case 2:
6666 source = 0;
6667 break;
6668 case 3:
6669 /* When there are 3 operands, one of them may be immediate,
6670 which may be the first or the last operand. Otherwise,
6671 the first operand must be shift count register (cl) or it
6672 is an instruction with VexNDS. */
6673 gas_assert (i.imm_operands == 1
6674 || (i.imm_operands == 0
6675 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6676 || i.types[0].bitfield.shiftcount)));
6677 if (operand_type_check (i.types[0], imm)
6678 || i.types[0].bitfield.shiftcount)
6679 source = 1;
6680 else
6681 source = 0;
6682 break;
6683 case 4:
6684 /* When there are 4 operands, the first two must be 8bit
6685 immediate operands. The source operand will be the 3rd
6686 one.
6687
6688 For instructions with VexNDS, if the first operand
6689 an imm8, the source operand is the 2nd one. If the last
6690 operand is imm8, the source operand is the first one. */
6691 gas_assert ((i.imm_operands == 2
6692 && i.types[0].bitfield.imm8
6693 && i.types[1].bitfield.imm8)
6694 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6695 && i.imm_operands == 1
6696 && (i.types[0].bitfield.imm8
6697 || i.types[i.operands - 1].bitfield.imm8
6698 || i.rounding)));
6699 if (i.imm_operands == 2)
6700 source = 2;
6701 else
6702 {
6703 if (i.types[0].bitfield.imm8)
6704 source = 1;
6705 else
6706 source = 0;
6707 }
6708 break;
6709 case 5:
6710 if (i.tm.opcode_modifier.evex)
6711 {
6712 /* For EVEX instructions, when there are 5 operands, the
6713 first one must be immediate operand. If the second one
6714 is immediate operand, the source operand is the 3th
6715 one. If the last one is immediate operand, the source
6716 operand is the 2nd one. */
6717 gas_assert (i.imm_operands == 2
6718 && i.tm.opcode_modifier.sae
6719 && operand_type_check (i.types[0], imm));
6720 if (operand_type_check (i.types[1], imm))
6721 source = 2;
6722 else if (operand_type_check (i.types[4], imm))
6723 source = 1;
6724 else
6725 abort ();
6726 }
6727 break;
6728 default:
6729 abort ();
6730 }
6731
6732 if (!vex_3_sources)
6733 {
6734 dest = source + 1;
6735
6736 /* RC/SAE operand could be between DEST and SRC. That happens
6737 when one operand is GPR and the other one is XMM/YMM/ZMM
6738 register. */
6739 if (i.rounding && i.rounding->operand == (int) dest)
6740 dest++;
6741
6742 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6743 {
6744 /* For instructions with VexNDS, the register-only source
6745 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6746 register. It is encoded in VEX prefix. We need to
6747 clear RegMem bit before calling operand_type_equal. */
6748
6749 i386_operand_type op;
6750 unsigned int vvvv;
6751
6752 /* Check register-only source operand when two source
6753 operands are swapped. */
6754 if (!i.tm.operand_types[source].bitfield.baseindex
6755 && i.tm.operand_types[dest].bitfield.baseindex)
6756 {
6757 vvvv = source;
6758 source = dest;
6759 }
6760 else
6761 vvvv = dest;
6762
6763 op = i.tm.operand_types[vvvv];
6764 op.bitfield.regmem = 0;
6765 if ((dest + 1) >= i.operands
6766 || ((!op.bitfield.reg
6767 || (!op.bitfield.dword && !op.bitfield.qword))
6768 && !op.bitfield.regsimd
6769 && !operand_type_equal (&op, &regmask)))
6770 abort ();
6771 i.vex.register_specifier = i.op[vvvv].regs;
6772 dest++;
6773 }
6774 }
6775
6776 i.rm.mode = 3;
6777 /* One of the register operands will be encoded in the i.tm.reg
6778 field, the other in the combined i.tm.mode and i.tm.regmem
6779 fields. If no form of this instruction supports a memory
6780 destination operand, then we assume the source operand may
6781 sometimes be a memory operand and so we need to store the
6782 destination in the i.rm.reg field. */
6783 if (!i.tm.operand_types[dest].bitfield.regmem
6784 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6785 {
6786 i.rm.reg = i.op[dest].regs->reg_num;
6787 i.rm.regmem = i.op[source].regs->reg_num;
6788 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6789 i.rex |= REX_R;
6790 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6791 i.vrex |= REX_R;
6792 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6793 i.rex |= REX_B;
6794 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6795 i.vrex |= REX_B;
6796 }
6797 else
6798 {
6799 i.rm.reg = i.op[source].regs->reg_num;
6800 i.rm.regmem = i.op[dest].regs->reg_num;
6801 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6802 i.rex |= REX_B;
6803 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6804 i.vrex |= REX_B;
6805 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6806 i.rex |= REX_R;
6807 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6808 i.vrex |= REX_R;
6809 }
6810 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6811 {
6812 if (!i.types[0].bitfield.control
6813 && !i.types[1].bitfield.control)
6814 abort ();
6815 i.rex &= ~(REX_R | REX_B);
6816 add_prefix (LOCK_PREFIX_OPCODE);
6817 }
6818 }
6819 else
6820 { /* If it's not 2 reg operands... */
6821 unsigned int mem;
6822
6823 if (i.mem_operands)
6824 {
6825 unsigned int fake_zero_displacement = 0;
6826 unsigned int op;
6827
6828 for (op = 0; op < i.operands; op++)
6829 if (operand_type_check (i.types[op], anymem))
6830 break;
6831 gas_assert (op < i.operands);
6832
6833 if (i.tm.opcode_modifier.vecsib)
6834 {
6835 if (i.index_reg->reg_num == RegEiz
6836 || i.index_reg->reg_num == RegRiz)
6837 abort ();
6838
6839 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6840 if (!i.base_reg)
6841 {
6842 i.sib.base = NO_BASE_REGISTER;
6843 i.sib.scale = i.log2_scale_factor;
6844 i.types[op].bitfield.disp8 = 0;
6845 i.types[op].bitfield.disp16 = 0;
6846 i.types[op].bitfield.disp64 = 0;
6847 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6848 {
6849 /* Must be 32 bit */
6850 i.types[op].bitfield.disp32 = 1;
6851 i.types[op].bitfield.disp32s = 0;
6852 }
6853 else
6854 {
6855 i.types[op].bitfield.disp32 = 0;
6856 i.types[op].bitfield.disp32s = 1;
6857 }
6858 }
6859 i.sib.index = i.index_reg->reg_num;
6860 if ((i.index_reg->reg_flags & RegRex) != 0)
6861 i.rex |= REX_X;
6862 if ((i.index_reg->reg_flags & RegVRex) != 0)
6863 i.vrex |= REX_X;
6864 }
6865
6866 default_seg = &ds;
6867
6868 if (i.base_reg == 0)
6869 {
6870 i.rm.mode = 0;
6871 if (!i.disp_operands)
6872 fake_zero_displacement = 1;
6873 if (i.index_reg == 0)
6874 {
6875 gas_assert (!i.tm.opcode_modifier.vecsib);
6876 /* Operand is just <disp> */
6877 if (flag_code == CODE_64BIT)
6878 {
6879 /* 64bit mode overwrites the 32bit absolute
6880 addressing by RIP relative addressing and
6881 absolute addressing is encoded by one of the
6882 redundant SIB forms. */
6883 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6884 i.sib.base = NO_BASE_REGISTER;
6885 i.sib.index = NO_INDEX_REGISTER;
6886 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6887 ? disp32s : disp32);
6888 }
6889 else if ((flag_code == CODE_16BIT)
6890 ^ (i.prefix[ADDR_PREFIX] != 0))
6891 {
6892 i.rm.regmem = NO_BASE_REGISTER_16;
6893 i.types[op] = disp16;
6894 }
6895 else
6896 {
6897 i.rm.regmem = NO_BASE_REGISTER;
6898 i.types[op] = disp32;
6899 }
6900 }
6901 else if (!i.tm.opcode_modifier.vecsib)
6902 {
6903 /* !i.base_reg && i.index_reg */
6904 if (i.index_reg->reg_num == RegEiz
6905 || i.index_reg->reg_num == RegRiz)
6906 i.sib.index = NO_INDEX_REGISTER;
6907 else
6908 i.sib.index = i.index_reg->reg_num;
6909 i.sib.base = NO_BASE_REGISTER;
6910 i.sib.scale = i.log2_scale_factor;
6911 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6912 i.types[op].bitfield.disp8 = 0;
6913 i.types[op].bitfield.disp16 = 0;
6914 i.types[op].bitfield.disp64 = 0;
6915 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6916 {
6917 /* Must be 32 bit */
6918 i.types[op].bitfield.disp32 = 1;
6919 i.types[op].bitfield.disp32s = 0;
6920 }
6921 else
6922 {
6923 i.types[op].bitfield.disp32 = 0;
6924 i.types[op].bitfield.disp32s = 1;
6925 }
6926 if ((i.index_reg->reg_flags & RegRex) != 0)
6927 i.rex |= REX_X;
6928 }
6929 }
6930 /* RIP addressing for 64bit mode. */
6931 else if (i.base_reg->reg_num == RegRip ||
6932 i.base_reg->reg_num == RegEip)
6933 {
6934 gas_assert (!i.tm.opcode_modifier.vecsib);
6935 i.rm.regmem = NO_BASE_REGISTER;
6936 i.types[op].bitfield.disp8 = 0;
6937 i.types[op].bitfield.disp16 = 0;
6938 i.types[op].bitfield.disp32 = 0;
6939 i.types[op].bitfield.disp32s = 1;
6940 i.types[op].bitfield.disp64 = 0;
6941 i.flags[op] |= Operand_PCrel;
6942 if (! i.disp_operands)
6943 fake_zero_displacement = 1;
6944 }
6945 else if (i.base_reg->reg_type.bitfield.word)
6946 {
6947 gas_assert (!i.tm.opcode_modifier.vecsib);
6948 switch (i.base_reg->reg_num)
6949 {
6950 case 3: /* (%bx) */
6951 if (i.index_reg == 0)
6952 i.rm.regmem = 7;
6953 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6954 i.rm.regmem = i.index_reg->reg_num - 6;
6955 break;
6956 case 5: /* (%bp) */
6957 default_seg = &ss;
6958 if (i.index_reg == 0)
6959 {
6960 i.rm.regmem = 6;
6961 if (operand_type_check (i.types[op], disp) == 0)
6962 {
6963 /* fake (%bp) into 0(%bp) */
6964 i.types[op].bitfield.disp8 = 1;
6965 fake_zero_displacement = 1;
6966 }
6967 }
6968 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6969 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6970 break;
6971 default: /* (%si) -> 4 or (%di) -> 5 */
6972 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6973 }
6974 i.rm.mode = mode_from_disp_size (i.types[op]);
6975 }
6976 else /* i.base_reg and 32/64 bit mode */
6977 {
6978 if (flag_code == CODE_64BIT
6979 && operand_type_check (i.types[op], disp))
6980 {
6981 i386_operand_type temp;
6982 operand_type_set (&temp, 0);
6983 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6984 i.types[op] = temp;
6985 if (i.prefix[ADDR_PREFIX] == 0)
6986 i.types[op].bitfield.disp32s = 1;
6987 else
6988 i.types[op].bitfield.disp32 = 1;
6989 }
6990
6991 if (!i.tm.opcode_modifier.vecsib)
6992 i.rm.regmem = i.base_reg->reg_num;
6993 if ((i.base_reg->reg_flags & RegRex) != 0)
6994 i.rex |= REX_B;
6995 i.sib.base = i.base_reg->reg_num;
6996 /* x86-64 ignores REX prefix bit here to avoid decoder
6997 complications. */
6998 if (!(i.base_reg->reg_flags & RegRex)
6999 && (i.base_reg->reg_num == EBP_REG_NUM
7000 || i.base_reg->reg_num == ESP_REG_NUM))
7001 default_seg = &ss;
7002 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7003 {
7004 fake_zero_displacement = 1;
7005 i.types[op].bitfield.disp8 = 1;
7006 }
7007 i.sib.scale = i.log2_scale_factor;
7008 if (i.index_reg == 0)
7009 {
7010 gas_assert (!i.tm.opcode_modifier.vecsib);
7011 /* <disp>(%esp) becomes two byte modrm with no index
7012 register. We've already stored the code for esp
7013 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7014 Any base register besides %esp will not use the
7015 extra modrm byte. */
7016 i.sib.index = NO_INDEX_REGISTER;
7017 }
7018 else if (!i.tm.opcode_modifier.vecsib)
7019 {
7020 if (i.index_reg->reg_num == RegEiz
7021 || i.index_reg->reg_num == RegRiz)
7022 i.sib.index = NO_INDEX_REGISTER;
7023 else
7024 i.sib.index = i.index_reg->reg_num;
7025 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7026 if ((i.index_reg->reg_flags & RegRex) != 0)
7027 i.rex |= REX_X;
7028 }
7029
7030 if (i.disp_operands
7031 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7032 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7033 i.rm.mode = 0;
7034 else
7035 {
7036 if (!fake_zero_displacement
7037 && !i.disp_operands
7038 && i.disp_encoding)
7039 {
7040 fake_zero_displacement = 1;
7041 if (i.disp_encoding == disp_encoding_8bit)
7042 i.types[op].bitfield.disp8 = 1;
7043 else
7044 i.types[op].bitfield.disp32 = 1;
7045 }
7046 i.rm.mode = mode_from_disp_size (i.types[op]);
7047 }
7048 }
7049
7050 if (fake_zero_displacement)
7051 {
7052 /* Fakes a zero displacement assuming that i.types[op]
7053 holds the correct displacement size. */
7054 expressionS *exp;
7055
7056 gas_assert (i.op[op].disps == 0);
7057 exp = &disp_expressions[i.disp_operands++];
7058 i.op[op].disps = exp;
7059 exp->X_op = O_constant;
7060 exp->X_add_number = 0;
7061 exp->X_add_symbol = (symbolS *) 0;
7062 exp->X_op_symbol = (symbolS *) 0;
7063 }
7064
7065 mem = op;
7066 }
7067 else
7068 mem = ~0;
7069
7070 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7071 {
7072 if (operand_type_check (i.types[0], imm))
7073 i.vex.register_specifier = NULL;
7074 else
7075 {
7076 /* VEX.vvvv encodes one of the sources when the first
7077 operand is not an immediate. */
7078 if (i.tm.opcode_modifier.vexw == VEXW0)
7079 i.vex.register_specifier = i.op[0].regs;
7080 else
7081 i.vex.register_specifier = i.op[1].regs;
7082 }
7083
7084 /* Destination is a XMM register encoded in the ModRM.reg
7085 and VEX.R bit. */
7086 i.rm.reg = i.op[2].regs->reg_num;
7087 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7088 i.rex |= REX_R;
7089
7090 /* ModRM.rm and VEX.B encodes the other source. */
7091 if (!i.mem_operands)
7092 {
7093 i.rm.mode = 3;
7094
7095 if (i.tm.opcode_modifier.vexw == VEXW0)
7096 i.rm.regmem = i.op[1].regs->reg_num;
7097 else
7098 i.rm.regmem = i.op[0].regs->reg_num;
7099
7100 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7101 i.rex |= REX_B;
7102 }
7103 }
7104 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7105 {
7106 i.vex.register_specifier = i.op[2].regs;
7107 if (!i.mem_operands)
7108 {
7109 i.rm.mode = 3;
7110 i.rm.regmem = i.op[1].regs->reg_num;
7111 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7112 i.rex |= REX_B;
7113 }
7114 }
7115 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7116 (if any) based on i.tm.extension_opcode. Again, we must be
7117 careful to make sure that segment/control/debug/test/MMX
7118 registers are coded into the i.rm.reg field. */
7119 else if (i.reg_operands)
7120 {
7121 unsigned int op;
7122 unsigned int vex_reg = ~0;
7123
7124 for (op = 0; op < i.operands; op++)
7125 if (i.types[op].bitfield.reg
7126 || i.types[op].bitfield.regmmx
7127 || i.types[op].bitfield.regsimd
7128 || i.types[op].bitfield.regbnd
7129 || i.types[op].bitfield.regmask
7130 || i.types[op].bitfield.sreg2
7131 || i.types[op].bitfield.sreg3
7132 || i.types[op].bitfield.control
7133 || i.types[op].bitfield.debug
7134 || i.types[op].bitfield.test)
7135 break;
7136
7137 if (vex_3_sources)
7138 op = dest;
7139 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7140 {
7141 /* For instructions with VexNDS, the register-only
7142 source operand is encoded in VEX prefix. */
7143 gas_assert (mem != (unsigned int) ~0);
7144
7145 if (op > mem)
7146 {
7147 vex_reg = op++;
7148 gas_assert (op < i.operands);
7149 }
7150 else
7151 {
7152 /* Check register-only source operand when two source
7153 operands are swapped. */
7154 if (!i.tm.operand_types[op].bitfield.baseindex
7155 && i.tm.operand_types[op + 1].bitfield.baseindex)
7156 {
7157 vex_reg = op;
7158 op += 2;
7159 gas_assert (mem == (vex_reg + 1)
7160 && op < i.operands);
7161 }
7162 else
7163 {
7164 vex_reg = op + 1;
7165 gas_assert (vex_reg < i.operands);
7166 }
7167 }
7168 }
7169 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7170 {
7171 /* For instructions with VexNDD, the register destination
7172 is encoded in VEX prefix. */
7173 if (i.mem_operands == 0)
7174 {
7175 /* There is no memory operand. */
7176 gas_assert ((op + 2) == i.operands);
7177 vex_reg = op + 1;
7178 }
7179 else
7180 {
7181 /* There are only 2 operands. */
7182 gas_assert (op < 2 && i.operands == 2);
7183 vex_reg = 1;
7184 }
7185 }
7186 else
7187 gas_assert (op < i.operands);
7188
7189 if (vex_reg != (unsigned int) ~0)
7190 {
7191 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7192
7193 if ((!type->bitfield.reg
7194 || (!type->bitfield.dword && !type->bitfield.qword))
7195 && !type->bitfield.regsimd
7196 && !operand_type_equal (type, &regmask))
7197 abort ();
7198
7199 i.vex.register_specifier = i.op[vex_reg].regs;
7200 }
7201
7202 /* Don't set OP operand twice. */
7203 if (vex_reg != op)
7204 {
7205 /* If there is an extension opcode to put here, the
7206 register number must be put into the regmem field. */
7207 if (i.tm.extension_opcode != None)
7208 {
7209 i.rm.regmem = i.op[op].regs->reg_num;
7210 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7211 i.rex |= REX_B;
7212 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7213 i.vrex |= REX_B;
7214 }
7215 else
7216 {
7217 i.rm.reg = i.op[op].regs->reg_num;
7218 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7219 i.rex |= REX_R;
7220 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7221 i.vrex |= REX_R;
7222 }
7223 }
7224
7225 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7226 must set it to 3 to indicate this is a register operand
7227 in the regmem field. */
7228 if (!i.mem_operands)
7229 i.rm.mode = 3;
7230 }
7231
7232 /* Fill in i.rm.reg field with extension opcode (if any). */
7233 if (i.tm.extension_opcode != None)
7234 i.rm.reg = i.tm.extension_opcode;
7235 }
7236 return default_seg;
7237 }
7238
7239 static void
7240 output_branch (void)
7241 {
7242 char *p;
7243 int size;
7244 int code16;
7245 int prefix;
7246 relax_substateT subtype;
7247 symbolS *sym;
7248 offsetT off;
7249
7250 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7251 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7252
7253 prefix = 0;
7254 if (i.prefix[DATA_PREFIX] != 0)
7255 {
7256 prefix = 1;
7257 i.prefixes -= 1;
7258 code16 ^= CODE16;
7259 }
7260 /* Pentium4 branch hints. */
7261 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7262 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7263 {
7264 prefix++;
7265 i.prefixes--;
7266 }
7267 if (i.prefix[REX_PREFIX] != 0)
7268 {
7269 prefix++;
7270 i.prefixes--;
7271 }
7272
7273 /* BND prefixed jump. */
7274 if (i.prefix[BND_PREFIX] != 0)
7275 {
7276 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7277 i.prefixes -= 1;
7278 }
7279
7280 if (i.prefixes != 0 && !intel_syntax)
7281 as_warn (_("skipping prefixes on this instruction"));
7282
7283 /* It's always a symbol; End frag & setup for relax.
7284 Make sure there is enough room in this frag for the largest
7285 instruction we may generate in md_convert_frag. This is 2
7286 bytes for the opcode and room for the prefix and largest
7287 displacement. */
7288 frag_grow (prefix + 2 + 4);
7289 /* Prefix and 1 opcode byte go in fr_fix. */
7290 p = frag_more (prefix + 1);
7291 if (i.prefix[DATA_PREFIX] != 0)
7292 *p++ = DATA_PREFIX_OPCODE;
7293 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7294 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7295 *p++ = i.prefix[SEG_PREFIX];
7296 if (i.prefix[REX_PREFIX] != 0)
7297 *p++ = i.prefix[REX_PREFIX];
7298 *p = i.tm.base_opcode;
7299
7300 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7301 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7302 else if (cpu_arch_flags.bitfield.cpui386)
7303 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7304 else
7305 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7306 subtype |= code16;
7307
7308 sym = i.op[0].disps->X_add_symbol;
7309 off = i.op[0].disps->X_add_number;
7310
7311 if (i.op[0].disps->X_op != O_constant
7312 && i.op[0].disps->X_op != O_symbol)
7313 {
7314 /* Handle complex expressions. */
7315 sym = make_expr_symbol (i.op[0].disps);
7316 off = 0;
7317 }
7318
7319 /* 1 possible extra opcode + 4 byte displacement go in var part.
7320 Pass reloc in fr_var. */
7321 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7322 }
7323
7324 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7325 /* Return TRUE iff PLT32 relocation should be used for branching to
7326 symbol S. */
7327
7328 static bfd_boolean
7329 need_plt32_p (symbolS *s)
7330 {
7331 /* PLT32 relocation is ELF only. */
7332 if (!IS_ELF)
7333 return FALSE;
7334
7335 /* Since there is no need to prepare for PLT branch on x86-64, we
7336 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7337 be used as a marker for 32-bit PC-relative branches. */
7338 if (!object_64bit)
7339 return FALSE;
7340
7341 /* Weak or undefined symbol need PLT32 relocation. */
7342 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7343 return TRUE;
7344
7345 /* Non-global symbol doesn't need PLT32 relocation. */
7346 if (! S_IS_EXTERNAL (s))
7347 return FALSE;
7348
7349 /* Other global symbols need PLT32 relocation. NB: Symbol with
7350 non-default visibilities are treated as normal global symbol
7351 so that PLT32 relocation can be used as a marker for 32-bit
7352 PC-relative branches. It is useful for linker relaxation. */
7353 return TRUE;
7354 }
7355 #endif
7356
7357 static void
7358 output_jump (void)
7359 {
7360 char *p;
7361 int size;
7362 fixS *fixP;
7363 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7364
7365 if (i.tm.opcode_modifier.jumpbyte)
7366 {
7367 /* This is a loop or jecxz type instruction. */
7368 size = 1;
7369 if (i.prefix[ADDR_PREFIX] != 0)
7370 {
7371 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7372 i.prefixes -= 1;
7373 }
7374 /* Pentium4 branch hints. */
7375 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7376 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7377 {
7378 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7379 i.prefixes--;
7380 }
7381 }
7382 else
7383 {
7384 int code16;
7385
7386 code16 = 0;
7387 if (flag_code == CODE_16BIT)
7388 code16 = CODE16;
7389
7390 if (i.prefix[DATA_PREFIX] != 0)
7391 {
7392 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7393 i.prefixes -= 1;
7394 code16 ^= CODE16;
7395 }
7396
7397 size = 4;
7398 if (code16)
7399 size = 2;
7400 }
7401
7402 if (i.prefix[REX_PREFIX] != 0)
7403 {
7404 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7405 i.prefixes -= 1;
7406 }
7407
7408 /* BND prefixed jump. */
7409 if (i.prefix[BND_PREFIX] != 0)
7410 {
7411 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7412 i.prefixes -= 1;
7413 }
7414
7415 if (i.prefixes != 0 && !intel_syntax)
7416 as_warn (_("skipping prefixes on this instruction"));
7417
7418 p = frag_more (i.tm.opcode_length + size);
7419 switch (i.tm.opcode_length)
7420 {
7421 case 2:
7422 *p++ = i.tm.base_opcode >> 8;
7423 /* Fall through. */
7424 case 1:
7425 *p++ = i.tm.base_opcode;
7426 break;
7427 default:
7428 abort ();
7429 }
7430
7431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7432 if (size == 4
7433 && jump_reloc == NO_RELOC
7434 && need_plt32_p (i.op[0].disps->X_add_symbol))
7435 jump_reloc = BFD_RELOC_X86_64_PLT32;
7436 #endif
7437
7438 jump_reloc = reloc (size, 1, 1, jump_reloc);
7439
7440 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7441 i.op[0].disps, 1, jump_reloc);
7442
7443 /* All jumps handled here are signed, but don't use a signed limit
7444 check for 32 and 16 bit jumps as we want to allow wrap around at
7445 4G and 64k respectively. */
7446 if (size == 1)
7447 fixP->fx_signed = 1;
7448 }
7449
7450 static void
7451 output_interseg_jump (void)
7452 {
7453 char *p;
7454 int size;
7455 int prefix;
7456 int code16;
7457
7458 code16 = 0;
7459 if (flag_code == CODE_16BIT)
7460 code16 = CODE16;
7461
7462 prefix = 0;
7463 if (i.prefix[DATA_PREFIX] != 0)
7464 {
7465 prefix = 1;
7466 i.prefixes -= 1;
7467 code16 ^= CODE16;
7468 }
7469 if (i.prefix[REX_PREFIX] != 0)
7470 {
7471 prefix++;
7472 i.prefixes -= 1;
7473 }
7474
7475 size = 4;
7476 if (code16)
7477 size = 2;
7478
7479 if (i.prefixes != 0 && !intel_syntax)
7480 as_warn (_("skipping prefixes on this instruction"));
7481
7482 /* 1 opcode; 2 segment; offset */
7483 p = frag_more (prefix + 1 + 2 + size);
7484
7485 if (i.prefix[DATA_PREFIX] != 0)
7486 *p++ = DATA_PREFIX_OPCODE;
7487
7488 if (i.prefix[REX_PREFIX] != 0)
7489 *p++ = i.prefix[REX_PREFIX];
7490
7491 *p++ = i.tm.base_opcode;
7492 if (i.op[1].imms->X_op == O_constant)
7493 {
7494 offsetT n = i.op[1].imms->X_add_number;
7495
7496 if (size == 2
7497 && !fits_in_unsigned_word (n)
7498 && !fits_in_signed_word (n))
7499 {
7500 as_bad (_("16-bit jump out of range"));
7501 return;
7502 }
7503 md_number_to_chars (p, n, size);
7504 }
7505 else
7506 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7507 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7508 if (i.op[0].imms->X_op != O_constant)
7509 as_bad (_("can't handle non absolute segment in `%s'"),
7510 i.tm.name);
7511 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7512 }
7513
7514 static void
7515 output_insn (void)
7516 {
7517 fragS *insn_start_frag;
7518 offsetT insn_start_off;
7519
7520 /* Tie dwarf2 debug info to the address at the start of the insn.
7521 We can't do this after the insn has been output as the current
7522 frag may have been closed off. eg. by frag_var. */
7523 dwarf2_emit_insn (0);
7524
7525 insn_start_frag = frag_now;
7526 insn_start_off = frag_now_fix ();
7527
7528 /* Output jumps. */
7529 if (i.tm.opcode_modifier.jump)
7530 output_branch ();
7531 else if (i.tm.opcode_modifier.jumpbyte
7532 || i.tm.opcode_modifier.jumpdword)
7533 output_jump ();
7534 else if (i.tm.opcode_modifier.jumpintersegment)
7535 output_interseg_jump ();
7536 else
7537 {
7538 /* Output normal instructions here. */
7539 char *p;
7540 unsigned char *q;
7541 unsigned int j;
7542 unsigned int prefix;
7543
7544 if (avoid_fence
7545 && i.tm.base_opcode == 0xfae
7546 && i.operands == 1
7547 && i.imm_operands == 1
7548 && (i.op[0].imms->X_add_number == 0xe8
7549 || i.op[0].imms->X_add_number == 0xf0
7550 || i.op[0].imms->X_add_number == 0xf8))
7551 {
7552 /* Encode lfence, mfence, and sfence as
7553 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7554 offsetT val = 0x240483f0ULL;
7555 p = frag_more (5);
7556 md_number_to_chars (p, val, 5);
7557 return;
7558 }
7559
7560 /* Some processors fail on LOCK prefix. This options makes
7561 assembler ignore LOCK prefix and serves as a workaround. */
7562 if (omit_lock_prefix)
7563 {
7564 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7565 return;
7566 i.prefix[LOCK_PREFIX] = 0;
7567 }
7568
7569 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7570 don't need the explicit prefix. */
7571 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7572 {
7573 switch (i.tm.opcode_length)
7574 {
7575 case 3:
7576 if (i.tm.base_opcode & 0xff000000)
7577 {
7578 prefix = (i.tm.base_opcode >> 24) & 0xff;
7579 goto check_prefix;
7580 }
7581 break;
7582 case 2:
7583 if ((i.tm.base_opcode & 0xff0000) != 0)
7584 {
7585 prefix = (i.tm.base_opcode >> 16) & 0xff;
7586 if (i.tm.cpu_flags.bitfield.cpupadlock)
7587 {
7588 check_prefix:
7589 if (prefix != REPE_PREFIX_OPCODE
7590 || (i.prefix[REP_PREFIX]
7591 != REPE_PREFIX_OPCODE))
7592 add_prefix (prefix);
7593 }
7594 else
7595 add_prefix (prefix);
7596 }
7597 break;
7598 case 1:
7599 break;
7600 case 0:
7601 /* Check for pseudo prefixes. */
7602 as_bad_where (insn_start_frag->fr_file,
7603 insn_start_frag->fr_line,
7604 _("pseudo prefix without instruction"));
7605 return;
7606 default:
7607 abort ();
7608 }
7609
7610 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7611 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7612 R_X86_64_GOTTPOFF relocation so that linker can safely
7613 perform IE->LE optimization. */
7614 if (x86_elf_abi == X86_64_X32_ABI
7615 && i.operands == 2
7616 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7617 && i.prefix[REX_PREFIX] == 0)
7618 add_prefix (REX_OPCODE);
7619 #endif
7620
7621 /* The prefix bytes. */
7622 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7623 if (*q)
7624 FRAG_APPEND_1_CHAR (*q);
7625 }
7626 else
7627 {
7628 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7629 if (*q)
7630 switch (j)
7631 {
7632 case REX_PREFIX:
7633 /* REX byte is encoded in VEX prefix. */
7634 break;
7635 case SEG_PREFIX:
7636 case ADDR_PREFIX:
7637 FRAG_APPEND_1_CHAR (*q);
7638 break;
7639 default:
7640 /* There should be no other prefixes for instructions
7641 with VEX prefix. */
7642 abort ();
7643 }
7644
7645 /* For EVEX instructions i.vrex should become 0 after
7646 build_evex_prefix. For VEX instructions upper 16 registers
7647 aren't available, so VREX should be 0. */
7648 if (i.vrex)
7649 abort ();
7650 /* Now the VEX prefix. */
7651 p = frag_more (i.vex.length);
7652 for (j = 0; j < i.vex.length; j++)
7653 p[j] = i.vex.bytes[j];
7654 }
7655
7656 /* Now the opcode; be careful about word order here! */
7657 if (i.tm.opcode_length == 1)
7658 {
7659 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7660 }
7661 else
7662 {
7663 switch (i.tm.opcode_length)
7664 {
7665 case 4:
7666 p = frag_more (4);
7667 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7668 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7669 break;
7670 case 3:
7671 p = frag_more (3);
7672 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7673 break;
7674 case 2:
7675 p = frag_more (2);
7676 break;
7677 default:
7678 abort ();
7679 break;
7680 }
7681
7682 /* Put out high byte first: can't use md_number_to_chars! */
7683 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7684 *p = i.tm.base_opcode & 0xff;
7685 }
7686
7687 /* Now the modrm byte and sib byte (if present). */
7688 if (i.tm.opcode_modifier.modrm)
7689 {
7690 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7691 | i.rm.reg << 3
7692 | i.rm.mode << 6));
7693 /* If i.rm.regmem == ESP (4)
7694 && i.rm.mode != (Register mode)
7695 && not 16 bit
7696 ==> need second modrm byte. */
7697 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7698 && i.rm.mode != 3
7699 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7700 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7701 | i.sib.index << 3
7702 | i.sib.scale << 6));
7703 }
7704
7705 if (i.disp_operands)
7706 output_disp (insn_start_frag, insn_start_off);
7707
7708 if (i.imm_operands)
7709 output_imm (insn_start_frag, insn_start_off);
7710 }
7711
7712 #ifdef DEBUG386
7713 if (flag_debug)
7714 {
7715 pi ("" /*line*/, &i);
7716 }
7717 #endif /* DEBUG386 */
7718 }
7719
7720 /* Return the size of the displacement operand N. */
7721
7722 static int
7723 disp_size (unsigned int n)
7724 {
7725 int size = 4;
7726
7727 if (i.types[n].bitfield.disp64)
7728 size = 8;
7729 else if (i.types[n].bitfield.disp8)
7730 size = 1;
7731 else if (i.types[n].bitfield.disp16)
7732 size = 2;
7733 return size;
7734 }
7735
7736 /* Return the size of the immediate operand N. */
7737
7738 static int
7739 imm_size (unsigned int n)
7740 {
7741 int size = 4;
7742 if (i.types[n].bitfield.imm64)
7743 size = 8;
7744 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7745 size = 1;
7746 else if (i.types[n].bitfield.imm16)
7747 size = 2;
7748 return size;
7749 }
7750
7751 static void
7752 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7753 {
7754 char *p;
7755 unsigned int n;
7756
7757 for (n = 0; n < i.operands; n++)
7758 {
7759 if (operand_type_check (i.types[n], disp))
7760 {
7761 if (i.op[n].disps->X_op == O_constant)
7762 {
7763 int size = disp_size (n);
7764 offsetT val = i.op[n].disps->X_add_number;
7765
7766 val = offset_in_range (val >> i.memshift, size);
7767 p = frag_more (size);
7768 md_number_to_chars (p, val, size);
7769 }
7770 else
7771 {
7772 enum bfd_reloc_code_real reloc_type;
7773 int size = disp_size (n);
7774 int sign = i.types[n].bitfield.disp32s;
7775 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7776 fixS *fixP;
7777
7778 /* We can't have 8 bit displacement here. */
7779 gas_assert (!i.types[n].bitfield.disp8);
7780
7781 /* The PC relative address is computed relative
7782 to the instruction boundary, so in case immediate
7783 fields follows, we need to adjust the value. */
7784 if (pcrel && i.imm_operands)
7785 {
7786 unsigned int n1;
7787 int sz = 0;
7788
7789 for (n1 = 0; n1 < i.operands; n1++)
7790 if (operand_type_check (i.types[n1], imm))
7791 {
7792 /* Only one immediate is allowed for PC
7793 relative address. */
7794 gas_assert (sz == 0);
7795 sz = imm_size (n1);
7796 i.op[n].disps->X_add_number -= sz;
7797 }
7798 /* We should find the immediate. */
7799 gas_assert (sz != 0);
7800 }
7801
7802 p = frag_more (size);
7803 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7804 if (GOT_symbol
7805 && GOT_symbol == i.op[n].disps->X_add_symbol
7806 && (((reloc_type == BFD_RELOC_32
7807 || reloc_type == BFD_RELOC_X86_64_32S
7808 || (reloc_type == BFD_RELOC_64
7809 && object_64bit))
7810 && (i.op[n].disps->X_op == O_symbol
7811 || (i.op[n].disps->X_op == O_add
7812 && ((symbol_get_value_expression
7813 (i.op[n].disps->X_op_symbol)->X_op)
7814 == O_subtract))))
7815 || reloc_type == BFD_RELOC_32_PCREL))
7816 {
7817 offsetT add;
7818
7819 if (insn_start_frag == frag_now)
7820 add = (p - frag_now->fr_literal) - insn_start_off;
7821 else
7822 {
7823 fragS *fr;
7824
7825 add = insn_start_frag->fr_fix - insn_start_off;
7826 for (fr = insn_start_frag->fr_next;
7827 fr && fr != frag_now; fr = fr->fr_next)
7828 add += fr->fr_fix;
7829 add += p - frag_now->fr_literal;
7830 }
7831
7832 if (!object_64bit)
7833 {
7834 reloc_type = BFD_RELOC_386_GOTPC;
7835 i.op[n].imms->X_add_number += add;
7836 }
7837 else if (reloc_type == BFD_RELOC_64)
7838 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7839 else
7840 /* Don't do the adjustment for x86-64, as there
7841 the pcrel addressing is relative to the _next_
7842 insn, and that is taken care of in other code. */
7843 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7844 }
7845 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7846 size, i.op[n].disps, pcrel,
7847 reloc_type);
7848 /* Check for "call/jmp *mem", "mov mem, %reg",
7849 "test %reg, mem" and "binop mem, %reg" where binop
7850 is one of adc, add, and, cmp, or, sbb, sub, xor
7851 instructions. Always generate R_386_GOT32X for
7852 "sym*GOT" operand in 32-bit mode. */
7853 if ((generate_relax_relocations
7854 || (!object_64bit
7855 && i.rm.mode == 0
7856 && i.rm.regmem == 5))
7857 && (i.rm.mode == 2
7858 || (i.rm.mode == 0 && i.rm.regmem == 5))
7859 && ((i.operands == 1
7860 && i.tm.base_opcode == 0xff
7861 && (i.rm.reg == 2 || i.rm.reg == 4))
7862 || (i.operands == 2
7863 && (i.tm.base_opcode == 0x8b
7864 || i.tm.base_opcode == 0x85
7865 || (i.tm.base_opcode & 0xc7) == 0x03))))
7866 {
7867 if (object_64bit)
7868 {
7869 fixP->fx_tcbit = i.rex != 0;
7870 if (i.base_reg
7871 && (i.base_reg->reg_num == RegRip
7872 || i.base_reg->reg_num == RegEip))
7873 fixP->fx_tcbit2 = 1;
7874 }
7875 else
7876 fixP->fx_tcbit2 = 1;
7877 }
7878 }
7879 }
7880 }
7881 }
7882
7883 static void
7884 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7885 {
7886 char *p;
7887 unsigned int n;
7888
7889 for (n = 0; n < i.operands; n++)
7890 {
7891 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7892 if (i.rounding && (int) n == i.rounding->operand)
7893 continue;
7894
7895 if (operand_type_check (i.types[n], imm))
7896 {
7897 if (i.op[n].imms->X_op == O_constant)
7898 {
7899 int size = imm_size (n);
7900 offsetT val;
7901
7902 val = offset_in_range (i.op[n].imms->X_add_number,
7903 size);
7904 p = frag_more (size);
7905 md_number_to_chars (p, val, size);
7906 }
7907 else
7908 {
7909 /* Not absolute_section.
7910 Need a 32-bit fixup (don't support 8bit
7911 non-absolute imms). Try to support other
7912 sizes ... */
7913 enum bfd_reloc_code_real reloc_type;
7914 int size = imm_size (n);
7915 int sign;
7916
7917 if (i.types[n].bitfield.imm32s
7918 && (i.suffix == QWORD_MNEM_SUFFIX
7919 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7920 sign = 1;
7921 else
7922 sign = 0;
7923
7924 p = frag_more (size);
7925 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7926
7927 /* This is tough to explain. We end up with this one if we
7928 * have operands that look like
7929 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7930 * obtain the absolute address of the GOT, and it is strongly
7931 * preferable from a performance point of view to avoid using
7932 * a runtime relocation for this. The actual sequence of
7933 * instructions often look something like:
7934 *
7935 * call .L66
7936 * .L66:
7937 * popl %ebx
7938 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7939 *
7940 * The call and pop essentially return the absolute address
7941 * of the label .L66 and store it in %ebx. The linker itself
7942 * will ultimately change the first operand of the addl so
7943 * that %ebx points to the GOT, but to keep things simple, the
7944 * .o file must have this operand set so that it generates not
7945 * the absolute address of .L66, but the absolute address of
7946 * itself. This allows the linker itself simply treat a GOTPC
7947 * relocation as asking for a pcrel offset to the GOT to be
7948 * added in, and the addend of the relocation is stored in the
7949 * operand field for the instruction itself.
7950 *
7951 * Our job here is to fix the operand so that it would add
7952 * the correct offset so that %ebx would point to itself. The
7953 * thing that is tricky is that .-.L66 will point to the
7954 * beginning of the instruction, so we need to further modify
7955 * the operand so that it will point to itself. There are
7956 * other cases where you have something like:
7957 *
7958 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7959 *
7960 * and here no correction would be required. Internally in
7961 * the assembler we treat operands of this form as not being
7962 * pcrel since the '.' is explicitly mentioned, and I wonder
7963 * whether it would simplify matters to do it this way. Who
7964 * knows. In earlier versions of the PIC patches, the
7965 * pcrel_adjust field was used to store the correction, but
7966 * since the expression is not pcrel, I felt it would be
7967 * confusing to do it this way. */
7968
7969 if ((reloc_type == BFD_RELOC_32
7970 || reloc_type == BFD_RELOC_X86_64_32S
7971 || reloc_type == BFD_RELOC_64)
7972 && GOT_symbol
7973 && GOT_symbol == i.op[n].imms->X_add_symbol
7974 && (i.op[n].imms->X_op == O_symbol
7975 || (i.op[n].imms->X_op == O_add
7976 && ((symbol_get_value_expression
7977 (i.op[n].imms->X_op_symbol)->X_op)
7978 == O_subtract))))
7979 {
7980 offsetT add;
7981
7982 if (insn_start_frag == frag_now)
7983 add = (p - frag_now->fr_literal) - insn_start_off;
7984 else
7985 {
7986 fragS *fr;
7987
7988 add = insn_start_frag->fr_fix - insn_start_off;
7989 for (fr = insn_start_frag->fr_next;
7990 fr && fr != frag_now; fr = fr->fr_next)
7991 add += fr->fr_fix;
7992 add += p - frag_now->fr_literal;
7993 }
7994
7995 if (!object_64bit)
7996 reloc_type = BFD_RELOC_386_GOTPC;
7997 else if (size == 4)
7998 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7999 else if (size == 8)
8000 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8001 i.op[n].imms->X_add_number += add;
8002 }
8003 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8004 i.op[n].imms, 0, reloc_type);
8005 }
8006 }
8007 }
8008 }
8009 \f
8010 /* x86_cons_fix_new is called via the expression parsing code when a
8011 reloc is needed. We use this hook to get the correct .got reloc. */
8012 static int cons_sign = -1;
8013
8014 void
8015 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8016 expressionS *exp, bfd_reloc_code_real_type r)
8017 {
8018 r = reloc (len, 0, cons_sign, r);
8019
8020 #ifdef TE_PE
8021 if (exp->X_op == O_secrel)
8022 {
8023 exp->X_op = O_symbol;
8024 r = BFD_RELOC_32_SECREL;
8025 }
8026 #endif
8027
8028 fix_new_exp (frag, off, len, exp, 0, r);
8029 }
8030
8031 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8032 purpose of the `.dc.a' internal pseudo-op. */
8033
8034 int
8035 x86_address_bytes (void)
8036 {
8037 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8038 return 4;
8039 return stdoutput->arch_info->bits_per_address / 8;
8040 }
8041
8042 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8043 || defined (LEX_AT)
8044 # define lex_got(reloc, adjust, types) NULL
8045 #else
8046 /* Parse operands of the form
8047 <symbol>@GOTOFF+<nnn>
8048 and similar .plt or .got references.
8049
8050 If we find one, set up the correct relocation in RELOC and copy the
8051 input string, minus the `@GOTOFF' into a malloc'd buffer for
8052 parsing by the calling routine. Return this buffer, and if ADJUST
8053 is non-null set it to the length of the string we removed from the
8054 input line. Otherwise return NULL. */
8055 static char *
8056 lex_got (enum bfd_reloc_code_real *rel,
8057 int *adjust,
8058 i386_operand_type *types)
8059 {
8060 /* Some of the relocations depend on the size of what field is to
8061 be relocated. But in our callers i386_immediate and i386_displacement
8062 we don't yet know the operand size (this will be set by insn
8063 matching). Hence we record the word32 relocation here,
8064 and adjust the reloc according to the real size in reloc(). */
8065 static const struct {
8066 const char *str;
8067 int len;
8068 const enum bfd_reloc_code_real rel[2];
8069 const i386_operand_type types64;
8070 } gotrel[] = {
8071 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8072 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8073 BFD_RELOC_SIZE32 },
8074 OPERAND_TYPE_IMM32_64 },
8075 #endif
8076 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8077 BFD_RELOC_X86_64_PLTOFF64 },
8078 OPERAND_TYPE_IMM64 },
8079 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8080 BFD_RELOC_X86_64_PLT32 },
8081 OPERAND_TYPE_IMM32_32S_DISP32 },
8082 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8083 BFD_RELOC_X86_64_GOTPLT64 },
8084 OPERAND_TYPE_IMM64_DISP64 },
8085 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8086 BFD_RELOC_X86_64_GOTOFF64 },
8087 OPERAND_TYPE_IMM64_DISP64 },
8088 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8089 BFD_RELOC_X86_64_GOTPCREL },
8090 OPERAND_TYPE_IMM32_32S_DISP32 },
8091 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8092 BFD_RELOC_X86_64_TLSGD },
8093 OPERAND_TYPE_IMM32_32S_DISP32 },
8094 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8095 _dummy_first_bfd_reloc_code_real },
8096 OPERAND_TYPE_NONE },
8097 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8098 BFD_RELOC_X86_64_TLSLD },
8099 OPERAND_TYPE_IMM32_32S_DISP32 },
8100 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8101 BFD_RELOC_X86_64_GOTTPOFF },
8102 OPERAND_TYPE_IMM32_32S_DISP32 },
8103 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8104 BFD_RELOC_X86_64_TPOFF32 },
8105 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8106 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8107 _dummy_first_bfd_reloc_code_real },
8108 OPERAND_TYPE_NONE },
8109 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8110 BFD_RELOC_X86_64_DTPOFF32 },
8111 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8112 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8113 _dummy_first_bfd_reloc_code_real },
8114 OPERAND_TYPE_NONE },
8115 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8116 _dummy_first_bfd_reloc_code_real },
8117 OPERAND_TYPE_NONE },
8118 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8119 BFD_RELOC_X86_64_GOT32 },
8120 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8121 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8122 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8123 OPERAND_TYPE_IMM32_32S_DISP32 },
8124 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8125 BFD_RELOC_X86_64_TLSDESC_CALL },
8126 OPERAND_TYPE_IMM32_32S_DISP32 },
8127 };
8128 char *cp;
8129 unsigned int j;
8130
8131 #if defined (OBJ_MAYBE_ELF)
8132 if (!IS_ELF)
8133 return NULL;
8134 #endif
8135
8136 for (cp = input_line_pointer; *cp != '@'; cp++)
8137 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8138 return NULL;
8139
8140 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8141 {
8142 int len = gotrel[j].len;
8143 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8144 {
8145 if (gotrel[j].rel[object_64bit] != 0)
8146 {
8147 int first, second;
8148 char *tmpbuf, *past_reloc;
8149
8150 *rel = gotrel[j].rel[object_64bit];
8151
8152 if (types)
8153 {
8154 if (flag_code != CODE_64BIT)
8155 {
8156 types->bitfield.imm32 = 1;
8157 types->bitfield.disp32 = 1;
8158 }
8159 else
8160 *types = gotrel[j].types64;
8161 }
8162
8163 if (j != 0 && GOT_symbol == NULL)
8164 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8165
8166 /* The length of the first part of our input line. */
8167 first = cp - input_line_pointer;
8168
8169 /* The second part goes from after the reloc token until
8170 (and including) an end_of_line char or comma. */
8171 past_reloc = cp + 1 + len;
8172 cp = past_reloc;
8173 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8174 ++cp;
8175 second = cp + 1 - past_reloc;
8176
8177 /* Allocate and copy string. The trailing NUL shouldn't
8178 be necessary, but be safe. */
8179 tmpbuf = XNEWVEC (char, first + second + 2);
8180 memcpy (tmpbuf, input_line_pointer, first);
8181 if (second != 0 && *past_reloc != ' ')
8182 /* Replace the relocation token with ' ', so that
8183 errors like foo@GOTOFF1 will be detected. */
8184 tmpbuf[first++] = ' ';
8185 else
8186 /* Increment length by 1 if the relocation token is
8187 removed. */
8188 len++;
8189 if (adjust)
8190 *adjust = len;
8191 memcpy (tmpbuf + first, past_reloc, second);
8192 tmpbuf[first + second] = '\0';
8193 return tmpbuf;
8194 }
8195
8196 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8197 gotrel[j].str, 1 << (5 + object_64bit));
8198 return NULL;
8199 }
8200 }
8201
8202 /* Might be a symbol version string. Don't as_bad here. */
8203 return NULL;
8204 }
8205 #endif
8206
8207 #ifdef TE_PE
8208 #ifdef lex_got
8209 #undef lex_got
8210 #endif
8211 /* Parse operands of the form
8212 <symbol>@SECREL32+<nnn>
8213
8214 If we find one, set up the correct relocation in RELOC and copy the
8215 input string, minus the `@SECREL32' into a malloc'd buffer for
8216 parsing by the calling routine. Return this buffer, and if ADJUST
8217 is non-null set it to the length of the string we removed from the
8218 input line. Otherwise return NULL.
8219
8220 This function is copied from the ELF version above adjusted for PE targets. */
8221
8222 static char *
8223 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8224 int *adjust ATTRIBUTE_UNUSED,
8225 i386_operand_type *types)
8226 {
8227 static const struct
8228 {
8229 const char *str;
8230 int len;
8231 const enum bfd_reloc_code_real rel[2];
8232 const i386_operand_type types64;
8233 }
8234 gotrel[] =
8235 {
8236 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8237 BFD_RELOC_32_SECREL },
8238 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8239 };
8240
8241 char *cp;
8242 unsigned j;
8243
8244 for (cp = input_line_pointer; *cp != '@'; cp++)
8245 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8246 return NULL;
8247
8248 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8249 {
8250 int len = gotrel[j].len;
8251
8252 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8253 {
8254 if (gotrel[j].rel[object_64bit] != 0)
8255 {
8256 int first, second;
8257 char *tmpbuf, *past_reloc;
8258
8259 *rel = gotrel[j].rel[object_64bit];
8260 if (adjust)
8261 *adjust = len;
8262
8263 if (types)
8264 {
8265 if (flag_code != CODE_64BIT)
8266 {
8267 types->bitfield.imm32 = 1;
8268 types->bitfield.disp32 = 1;
8269 }
8270 else
8271 *types = gotrel[j].types64;
8272 }
8273
8274 /* The length of the first part of our input line. */
8275 first = cp - input_line_pointer;
8276
8277 /* The second part goes from after the reloc token until
8278 (and including) an end_of_line char or comma. */
8279 past_reloc = cp + 1 + len;
8280 cp = past_reloc;
8281 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8282 ++cp;
8283 second = cp + 1 - past_reloc;
8284
8285 /* Allocate and copy string. The trailing NUL shouldn't
8286 be necessary, but be safe. */
8287 tmpbuf = XNEWVEC (char, first + second + 2);
8288 memcpy (tmpbuf, input_line_pointer, first);
8289 if (second != 0 && *past_reloc != ' ')
8290 /* Replace the relocation token with ' ', so that
8291 errors like foo@SECLREL321 will be detected. */
8292 tmpbuf[first++] = ' ';
8293 memcpy (tmpbuf + first, past_reloc, second);
8294 tmpbuf[first + second] = '\0';
8295 return tmpbuf;
8296 }
8297
8298 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8299 gotrel[j].str, 1 << (5 + object_64bit));
8300 return NULL;
8301 }
8302 }
8303
8304 /* Might be a symbol version string. Don't as_bad here. */
8305 return NULL;
8306 }
8307
8308 #endif /* TE_PE */
8309
8310 bfd_reloc_code_real_type
8311 x86_cons (expressionS *exp, int size)
8312 {
8313 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8314
8315 intel_syntax = -intel_syntax;
8316
8317 exp->X_md = 0;
8318 if (size == 4 || (object_64bit && size == 8))
8319 {
8320 /* Handle @GOTOFF and the like in an expression. */
8321 char *save;
8322 char *gotfree_input_line;
8323 int adjust = 0;
8324
8325 save = input_line_pointer;
8326 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8327 if (gotfree_input_line)
8328 input_line_pointer = gotfree_input_line;
8329
8330 expression (exp);
8331
8332 if (gotfree_input_line)
8333 {
8334 /* expression () has merrily parsed up to the end of line,
8335 or a comma - in the wrong buffer. Transfer how far
8336 input_line_pointer has moved to the right buffer. */
8337 input_line_pointer = (save
8338 + (input_line_pointer - gotfree_input_line)
8339 + adjust);
8340 free (gotfree_input_line);
8341 if (exp->X_op == O_constant
8342 || exp->X_op == O_absent
8343 || exp->X_op == O_illegal
8344 || exp->X_op == O_register
8345 || exp->X_op == O_big)
8346 {
8347 char c = *input_line_pointer;
8348 *input_line_pointer = 0;
8349 as_bad (_("missing or invalid expression `%s'"), save);
8350 *input_line_pointer = c;
8351 }
8352 }
8353 }
8354 else
8355 expression (exp);
8356
8357 intel_syntax = -intel_syntax;
8358
8359 if (intel_syntax)
8360 i386_intel_simplify (exp);
8361
8362 return got_reloc;
8363 }
8364
8365 static void
8366 signed_cons (int size)
8367 {
8368 if (flag_code == CODE_64BIT)
8369 cons_sign = 1;
8370 cons (size);
8371 cons_sign = -1;
8372 }
8373
8374 #ifdef TE_PE
8375 static void
8376 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8377 {
8378 expressionS exp;
8379
8380 do
8381 {
8382 expression (&exp);
8383 if (exp.X_op == O_symbol)
8384 exp.X_op = O_secrel;
8385
8386 emit_expr (&exp, 4);
8387 }
8388 while (*input_line_pointer++ == ',');
8389
8390 input_line_pointer--;
8391 demand_empty_rest_of_line ();
8392 }
8393 #endif
8394
8395 /* Handle Vector operations. */
8396
8397 static char *
8398 check_VecOperations (char *op_string, char *op_end)
8399 {
8400 const reg_entry *mask;
8401 const char *saved;
8402 char *end_op;
8403
8404 while (*op_string
8405 && (op_end == NULL || op_string < op_end))
8406 {
8407 saved = op_string;
8408 if (*op_string == '{')
8409 {
8410 op_string++;
8411
8412 /* Check broadcasts. */
8413 if (strncmp (op_string, "1to", 3) == 0)
8414 {
8415 int bcst_type;
8416
8417 if (i.broadcast)
8418 goto duplicated_vec_op;
8419
8420 op_string += 3;
8421 if (*op_string == '8')
8422 bcst_type = BROADCAST_1TO8;
8423 else if (*op_string == '4')
8424 bcst_type = BROADCAST_1TO4;
8425 else if (*op_string == '2')
8426 bcst_type = BROADCAST_1TO2;
8427 else if (*op_string == '1'
8428 && *(op_string+1) == '6')
8429 {
8430 bcst_type = BROADCAST_1TO16;
8431 op_string++;
8432 }
8433 else
8434 {
8435 as_bad (_("Unsupported broadcast: `%s'"), saved);
8436 return NULL;
8437 }
8438 op_string++;
8439
8440 broadcast_op.type = bcst_type;
8441 broadcast_op.operand = this_operand;
8442 i.broadcast = &broadcast_op;
8443 }
8444 /* Check masking operation. */
8445 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8446 {
8447 /* k0 can't be used for write mask. */
8448 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8449 {
8450 as_bad (_("`%s%s' can't be used for write mask"),
8451 register_prefix, mask->reg_name);
8452 return NULL;
8453 }
8454
8455 if (!i.mask)
8456 {
8457 mask_op.mask = mask;
8458 mask_op.zeroing = 0;
8459 mask_op.operand = this_operand;
8460 i.mask = &mask_op;
8461 }
8462 else
8463 {
8464 if (i.mask->mask)
8465 goto duplicated_vec_op;
8466
8467 i.mask->mask = mask;
8468
8469 /* Only "{z}" is allowed here. No need to check
8470 zeroing mask explicitly. */
8471 if (i.mask->operand != this_operand)
8472 {
8473 as_bad (_("invalid write mask `%s'"), saved);
8474 return NULL;
8475 }
8476 }
8477
8478 op_string = end_op;
8479 }
8480 /* Check zeroing-flag for masking operation. */
8481 else if (*op_string == 'z')
8482 {
8483 if (!i.mask)
8484 {
8485 mask_op.mask = NULL;
8486 mask_op.zeroing = 1;
8487 mask_op.operand = this_operand;
8488 i.mask = &mask_op;
8489 }
8490 else
8491 {
8492 if (i.mask->zeroing)
8493 {
8494 duplicated_vec_op:
8495 as_bad (_("duplicated `%s'"), saved);
8496 return NULL;
8497 }
8498
8499 i.mask->zeroing = 1;
8500
8501 /* Only "{%k}" is allowed here. No need to check mask
8502 register explicitly. */
8503 if (i.mask->operand != this_operand)
8504 {
8505 as_bad (_("invalid zeroing-masking `%s'"),
8506 saved);
8507 return NULL;
8508 }
8509 }
8510
8511 op_string++;
8512 }
8513 else
8514 goto unknown_vec_op;
8515
8516 if (*op_string != '}')
8517 {
8518 as_bad (_("missing `}' in `%s'"), saved);
8519 return NULL;
8520 }
8521 op_string++;
8522 continue;
8523 }
8524 unknown_vec_op:
8525 /* We don't know this one. */
8526 as_bad (_("unknown vector operation: `%s'"), saved);
8527 return NULL;
8528 }
8529
8530 if (i.mask && i.mask->zeroing && !i.mask->mask)
8531 {
8532 as_bad (_("zeroing-masking only allowed with write mask"));
8533 return NULL;
8534 }
8535
8536 return op_string;
8537 }
8538
8539 static int
8540 i386_immediate (char *imm_start)
8541 {
8542 char *save_input_line_pointer;
8543 char *gotfree_input_line;
8544 segT exp_seg = 0;
8545 expressionS *exp;
8546 i386_operand_type types;
8547
8548 operand_type_set (&types, ~0);
8549
8550 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8551 {
8552 as_bad (_("at most %d immediate operands are allowed"),
8553 MAX_IMMEDIATE_OPERANDS);
8554 return 0;
8555 }
8556
8557 exp = &im_expressions[i.imm_operands++];
8558 i.op[this_operand].imms = exp;
8559
8560 if (is_space_char (*imm_start))
8561 ++imm_start;
8562
8563 save_input_line_pointer = input_line_pointer;
8564 input_line_pointer = imm_start;
8565
8566 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8567 if (gotfree_input_line)
8568 input_line_pointer = gotfree_input_line;
8569
8570 exp_seg = expression (exp);
8571
8572 SKIP_WHITESPACE ();
8573
8574 /* Handle vector operations. */
8575 if (*input_line_pointer == '{')
8576 {
8577 input_line_pointer = check_VecOperations (input_line_pointer,
8578 NULL);
8579 if (input_line_pointer == NULL)
8580 return 0;
8581 }
8582
8583 if (*input_line_pointer)
8584 as_bad (_("junk `%s' after expression"), input_line_pointer);
8585
8586 input_line_pointer = save_input_line_pointer;
8587 if (gotfree_input_line)
8588 {
8589 free (gotfree_input_line);
8590
8591 if (exp->X_op == O_constant || exp->X_op == O_register)
8592 exp->X_op = O_illegal;
8593 }
8594
8595 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8596 }
8597
8598 static int
8599 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8600 i386_operand_type types, const char *imm_start)
8601 {
8602 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8603 {
8604 if (imm_start)
8605 as_bad (_("missing or invalid immediate expression `%s'"),
8606 imm_start);
8607 return 0;
8608 }
8609 else if (exp->X_op == O_constant)
8610 {
8611 /* Size it properly later. */
8612 i.types[this_operand].bitfield.imm64 = 1;
8613 /* If not 64bit, sign extend val. */
8614 if (flag_code != CODE_64BIT
8615 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8616 exp->X_add_number
8617 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8618 }
8619 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8620 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8621 && exp_seg != absolute_section
8622 && exp_seg != text_section
8623 && exp_seg != data_section
8624 && exp_seg != bss_section
8625 && exp_seg != undefined_section
8626 && !bfd_is_com_section (exp_seg))
8627 {
8628 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8629 return 0;
8630 }
8631 #endif
8632 else if (!intel_syntax && exp_seg == reg_section)
8633 {
8634 if (imm_start)
8635 as_bad (_("illegal immediate register operand %s"), imm_start);
8636 return 0;
8637 }
8638 else
8639 {
8640 /* This is an address. The size of the address will be
8641 determined later, depending on destination register,
8642 suffix, or the default for the section. */
8643 i.types[this_operand].bitfield.imm8 = 1;
8644 i.types[this_operand].bitfield.imm16 = 1;
8645 i.types[this_operand].bitfield.imm32 = 1;
8646 i.types[this_operand].bitfield.imm32s = 1;
8647 i.types[this_operand].bitfield.imm64 = 1;
8648 i.types[this_operand] = operand_type_and (i.types[this_operand],
8649 types);
8650 }
8651
8652 return 1;
8653 }
8654
8655 static char *
8656 i386_scale (char *scale)
8657 {
8658 offsetT val;
8659 char *save = input_line_pointer;
8660
8661 input_line_pointer = scale;
8662 val = get_absolute_expression ();
8663
8664 switch (val)
8665 {
8666 case 1:
8667 i.log2_scale_factor = 0;
8668 break;
8669 case 2:
8670 i.log2_scale_factor = 1;
8671 break;
8672 case 4:
8673 i.log2_scale_factor = 2;
8674 break;
8675 case 8:
8676 i.log2_scale_factor = 3;
8677 break;
8678 default:
8679 {
8680 char sep = *input_line_pointer;
8681
8682 *input_line_pointer = '\0';
8683 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8684 scale);
8685 *input_line_pointer = sep;
8686 input_line_pointer = save;
8687 return NULL;
8688 }
8689 }
8690 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8691 {
8692 as_warn (_("scale factor of %d without an index register"),
8693 1 << i.log2_scale_factor);
8694 i.log2_scale_factor = 0;
8695 }
8696 scale = input_line_pointer;
8697 input_line_pointer = save;
8698 return scale;
8699 }
8700
8701 static int
8702 i386_displacement (char *disp_start, char *disp_end)
8703 {
8704 expressionS *exp;
8705 segT exp_seg = 0;
8706 char *save_input_line_pointer;
8707 char *gotfree_input_line;
8708 int override;
8709 i386_operand_type bigdisp, types = anydisp;
8710 int ret;
8711
8712 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8713 {
8714 as_bad (_("at most %d displacement operands are allowed"),
8715 MAX_MEMORY_OPERANDS);
8716 return 0;
8717 }
8718
8719 operand_type_set (&bigdisp, 0);
8720 if ((i.types[this_operand].bitfield.jumpabsolute)
8721 || (!current_templates->start->opcode_modifier.jump
8722 && !current_templates->start->opcode_modifier.jumpdword))
8723 {
8724 bigdisp.bitfield.disp32 = 1;
8725 override = (i.prefix[ADDR_PREFIX] != 0);
8726 if (flag_code == CODE_64BIT)
8727 {
8728 if (!override)
8729 {
8730 bigdisp.bitfield.disp32s = 1;
8731 bigdisp.bitfield.disp64 = 1;
8732 }
8733 }
8734 else if ((flag_code == CODE_16BIT) ^ override)
8735 {
8736 bigdisp.bitfield.disp32 = 0;
8737 bigdisp.bitfield.disp16 = 1;
8738 }
8739 }
8740 else
8741 {
8742 /* For PC-relative branches, the width of the displacement
8743 is dependent upon data size, not address size. */
8744 override = (i.prefix[DATA_PREFIX] != 0);
8745 if (flag_code == CODE_64BIT)
8746 {
8747 if (override || i.suffix == WORD_MNEM_SUFFIX)
8748 bigdisp.bitfield.disp16 = 1;
8749 else
8750 {
8751 bigdisp.bitfield.disp32 = 1;
8752 bigdisp.bitfield.disp32s = 1;
8753 }
8754 }
8755 else
8756 {
8757 if (!override)
8758 override = (i.suffix == (flag_code != CODE_16BIT
8759 ? WORD_MNEM_SUFFIX
8760 : LONG_MNEM_SUFFIX));
8761 bigdisp.bitfield.disp32 = 1;
8762 if ((flag_code == CODE_16BIT) ^ override)
8763 {
8764 bigdisp.bitfield.disp32 = 0;
8765 bigdisp.bitfield.disp16 = 1;
8766 }
8767 }
8768 }
8769 i.types[this_operand] = operand_type_or (i.types[this_operand],
8770 bigdisp);
8771
8772 exp = &disp_expressions[i.disp_operands];
8773 i.op[this_operand].disps = exp;
8774 i.disp_operands++;
8775 save_input_line_pointer = input_line_pointer;
8776 input_line_pointer = disp_start;
8777 END_STRING_AND_SAVE (disp_end);
8778
8779 #ifndef GCC_ASM_O_HACK
8780 #define GCC_ASM_O_HACK 0
8781 #endif
8782 #if GCC_ASM_O_HACK
8783 END_STRING_AND_SAVE (disp_end + 1);
8784 if (i.types[this_operand].bitfield.baseIndex
8785 && displacement_string_end[-1] == '+')
8786 {
8787 /* This hack is to avoid a warning when using the "o"
8788 constraint within gcc asm statements.
8789 For instance:
8790
8791 #define _set_tssldt_desc(n,addr,limit,type) \
8792 __asm__ __volatile__ ( \
8793 "movw %w2,%0\n\t" \
8794 "movw %w1,2+%0\n\t" \
8795 "rorl $16,%1\n\t" \
8796 "movb %b1,4+%0\n\t" \
8797 "movb %4,5+%0\n\t" \
8798 "movb $0,6+%0\n\t" \
8799 "movb %h1,7+%0\n\t" \
8800 "rorl $16,%1" \
8801 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8802
8803 This works great except that the output assembler ends
8804 up looking a bit weird if it turns out that there is
8805 no offset. You end up producing code that looks like:
8806
8807 #APP
8808 movw $235,(%eax)
8809 movw %dx,2+(%eax)
8810 rorl $16,%edx
8811 movb %dl,4+(%eax)
8812 movb $137,5+(%eax)
8813 movb $0,6+(%eax)
8814 movb %dh,7+(%eax)
8815 rorl $16,%edx
8816 #NO_APP
8817
8818 So here we provide the missing zero. */
8819
8820 *displacement_string_end = '0';
8821 }
8822 #endif
8823 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8824 if (gotfree_input_line)
8825 input_line_pointer = gotfree_input_line;
8826
8827 exp_seg = expression (exp);
8828
8829 SKIP_WHITESPACE ();
8830 if (*input_line_pointer)
8831 as_bad (_("junk `%s' after expression"), input_line_pointer);
8832 #if GCC_ASM_O_HACK
8833 RESTORE_END_STRING (disp_end + 1);
8834 #endif
8835 input_line_pointer = save_input_line_pointer;
8836 if (gotfree_input_line)
8837 {
8838 free (gotfree_input_line);
8839
8840 if (exp->X_op == O_constant || exp->X_op == O_register)
8841 exp->X_op = O_illegal;
8842 }
8843
8844 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8845
8846 RESTORE_END_STRING (disp_end);
8847
8848 return ret;
8849 }
8850
8851 static int
8852 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8853 i386_operand_type types, const char *disp_start)
8854 {
8855 i386_operand_type bigdisp;
8856 int ret = 1;
8857
8858 /* We do this to make sure that the section symbol is in
8859 the symbol table. We will ultimately change the relocation
8860 to be relative to the beginning of the section. */
8861 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8862 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8863 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8864 {
8865 if (exp->X_op != O_symbol)
8866 goto inv_disp;
8867
8868 if (S_IS_LOCAL (exp->X_add_symbol)
8869 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8870 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8871 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8872 exp->X_op = O_subtract;
8873 exp->X_op_symbol = GOT_symbol;
8874 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8875 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8876 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8877 i.reloc[this_operand] = BFD_RELOC_64;
8878 else
8879 i.reloc[this_operand] = BFD_RELOC_32;
8880 }
8881
8882 else if (exp->X_op == O_absent
8883 || exp->X_op == O_illegal
8884 || exp->X_op == O_big)
8885 {
8886 inv_disp:
8887 as_bad (_("missing or invalid displacement expression `%s'"),
8888 disp_start);
8889 ret = 0;
8890 }
8891
8892 else if (flag_code == CODE_64BIT
8893 && !i.prefix[ADDR_PREFIX]
8894 && exp->X_op == O_constant)
8895 {
8896 /* Since displacement is signed extended to 64bit, don't allow
8897 disp32 and turn off disp32s if they are out of range. */
8898 i.types[this_operand].bitfield.disp32 = 0;
8899 if (!fits_in_signed_long (exp->X_add_number))
8900 {
8901 i.types[this_operand].bitfield.disp32s = 0;
8902 if (i.types[this_operand].bitfield.baseindex)
8903 {
8904 as_bad (_("0x%lx out range of signed 32bit displacement"),
8905 (long) exp->X_add_number);
8906 ret = 0;
8907 }
8908 }
8909 }
8910
8911 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8912 else if (exp->X_op != O_constant
8913 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8914 && exp_seg != absolute_section
8915 && exp_seg != text_section
8916 && exp_seg != data_section
8917 && exp_seg != bss_section
8918 && exp_seg != undefined_section
8919 && !bfd_is_com_section (exp_seg))
8920 {
8921 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8922 ret = 0;
8923 }
8924 #endif
8925
8926 /* Check if this is a displacement only operand. */
8927 bigdisp = i.types[this_operand];
8928 bigdisp.bitfield.disp8 = 0;
8929 bigdisp.bitfield.disp16 = 0;
8930 bigdisp.bitfield.disp32 = 0;
8931 bigdisp.bitfield.disp32s = 0;
8932 bigdisp.bitfield.disp64 = 0;
8933 if (operand_type_all_zero (&bigdisp))
8934 i.types[this_operand] = operand_type_and (i.types[this_operand],
8935 types);
8936
8937 return ret;
8938 }
8939
8940 /* Return the active addressing mode, taking address override and
8941 registers forming the address into consideration. Update the
8942 address override prefix if necessary. */
8943
8944 static enum flag_code
8945 i386_addressing_mode (void)
8946 {
8947 enum flag_code addr_mode;
8948
8949 if (i.prefix[ADDR_PREFIX])
8950 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8951 else
8952 {
8953 addr_mode = flag_code;
8954
8955 #if INFER_ADDR_PREFIX
8956 if (i.mem_operands == 0)
8957 {
8958 /* Infer address prefix from the first memory operand. */
8959 const reg_entry *addr_reg = i.base_reg;
8960
8961 if (addr_reg == NULL)
8962 addr_reg = i.index_reg;
8963
8964 if (addr_reg)
8965 {
8966 if (addr_reg->reg_num == RegEip
8967 || addr_reg->reg_num == RegEiz
8968 || addr_reg->reg_type.bitfield.dword)
8969 addr_mode = CODE_32BIT;
8970 else if (flag_code != CODE_64BIT
8971 && addr_reg->reg_type.bitfield.word)
8972 addr_mode = CODE_16BIT;
8973
8974 if (addr_mode != flag_code)
8975 {
8976 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8977 i.prefixes += 1;
8978 /* Change the size of any displacement too. At most one
8979 of Disp16 or Disp32 is set.
8980 FIXME. There doesn't seem to be any real need for
8981 separate Disp16 and Disp32 flags. The same goes for
8982 Imm16 and Imm32. Removing them would probably clean
8983 up the code quite a lot. */
8984 if (flag_code != CODE_64BIT
8985 && (i.types[this_operand].bitfield.disp16
8986 || i.types[this_operand].bitfield.disp32))
8987 i.types[this_operand]
8988 = operand_type_xor (i.types[this_operand], disp16_32);
8989 }
8990 }
8991 }
8992 #endif
8993 }
8994
8995 return addr_mode;
8996 }
8997
8998 /* Make sure the memory operand we've been dealt is valid.
8999 Return 1 on success, 0 on a failure. */
9000
9001 static int
9002 i386_index_check (const char *operand_string)
9003 {
9004 const char *kind = "base/index";
9005 enum flag_code addr_mode = i386_addressing_mode ();
9006
9007 if (current_templates->start->opcode_modifier.isstring
9008 && !current_templates->start->opcode_modifier.immext
9009 && (current_templates->end[-1].opcode_modifier.isstring
9010 || i.mem_operands))
9011 {
9012 /* Memory operands of string insns are special in that they only allow
9013 a single register (rDI, rSI, or rBX) as their memory address. */
9014 const reg_entry *expected_reg;
9015 static const char *di_si[][2] =
9016 {
9017 { "esi", "edi" },
9018 { "si", "di" },
9019 { "rsi", "rdi" }
9020 };
9021 static const char *bx[] = { "ebx", "bx", "rbx" };
9022
9023 kind = "string address";
9024
9025 if (current_templates->start->opcode_modifier.repprefixok)
9026 {
9027 i386_operand_type type = current_templates->end[-1].operand_types[0];
9028
9029 if (!type.bitfield.baseindex
9030 || ((!i.mem_operands != !intel_syntax)
9031 && current_templates->end[-1].operand_types[1]
9032 .bitfield.baseindex))
9033 type = current_templates->end[-1].operand_types[1];
9034 expected_reg = hash_find (reg_hash,
9035 di_si[addr_mode][type.bitfield.esseg]);
9036
9037 }
9038 else
9039 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9040
9041 if (i.base_reg != expected_reg
9042 || i.index_reg
9043 || operand_type_check (i.types[this_operand], disp))
9044 {
9045 /* The second memory operand must have the same size as
9046 the first one. */
9047 if (i.mem_operands
9048 && i.base_reg
9049 && !((addr_mode == CODE_64BIT
9050 && i.base_reg->reg_type.bitfield.qword)
9051 || (addr_mode == CODE_32BIT
9052 ? i.base_reg->reg_type.bitfield.dword
9053 : i.base_reg->reg_type.bitfield.word)))
9054 goto bad_address;
9055
9056 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9057 operand_string,
9058 intel_syntax ? '[' : '(',
9059 register_prefix,
9060 expected_reg->reg_name,
9061 intel_syntax ? ']' : ')');
9062 return 1;
9063 }
9064 else
9065 return 1;
9066
9067 bad_address:
9068 as_bad (_("`%s' is not a valid %s expression"),
9069 operand_string, kind);
9070 return 0;
9071 }
9072 else
9073 {
9074 if (addr_mode != CODE_16BIT)
9075 {
9076 /* 32-bit/64-bit checks. */
9077 if ((i.base_reg
9078 && (addr_mode == CODE_64BIT
9079 ? !i.base_reg->reg_type.bitfield.qword
9080 : !i.base_reg->reg_type.bitfield.dword)
9081 && (i.index_reg
9082 || (i.base_reg->reg_num
9083 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9084 || (i.index_reg
9085 && !i.index_reg->reg_type.bitfield.xmmword
9086 && !i.index_reg->reg_type.bitfield.ymmword
9087 && !i.index_reg->reg_type.bitfield.zmmword
9088 && ((addr_mode == CODE_64BIT
9089 ? !(i.index_reg->reg_type.bitfield.qword
9090 || i.index_reg->reg_num == RegRiz)
9091 : !(i.index_reg->reg_type.bitfield.dword
9092 || i.index_reg->reg_num == RegEiz))
9093 || !i.index_reg->reg_type.bitfield.baseindex)))
9094 goto bad_address;
9095
9096 /* bndmk, bndldx, and bndstx have special restrictions. */
9097 if (current_templates->start->base_opcode == 0xf30f1b
9098 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9099 {
9100 /* They cannot use RIP-relative addressing. */
9101 if (i.base_reg && i.base_reg->reg_num == RegRip)
9102 {
9103 as_bad (_("`%s' cannot be used here"), operand_string);
9104 return 0;
9105 }
9106
9107 /* bndldx and bndstx ignore their scale factor. */
9108 if (current_templates->start->base_opcode != 0xf30f1b
9109 && i.log2_scale_factor)
9110 as_warn (_("register scaling is being ignored here"));
9111 }
9112 }
9113 else
9114 {
9115 /* 16-bit checks. */
9116 if ((i.base_reg
9117 && (!i.base_reg->reg_type.bitfield.word
9118 || !i.base_reg->reg_type.bitfield.baseindex))
9119 || (i.index_reg
9120 && (!i.index_reg->reg_type.bitfield.word
9121 || !i.index_reg->reg_type.bitfield.baseindex
9122 || !(i.base_reg
9123 && i.base_reg->reg_num < 6
9124 && i.index_reg->reg_num >= 6
9125 && i.log2_scale_factor == 0))))
9126 goto bad_address;
9127 }
9128 }
9129 return 1;
9130 }
9131
9132 /* Handle vector immediates. */
9133
9134 static int
9135 RC_SAE_immediate (const char *imm_start)
9136 {
9137 unsigned int match_found, j;
9138 const char *pstr = imm_start;
9139 expressionS *exp;
9140
9141 if (*pstr != '{')
9142 return 0;
9143
9144 pstr++;
9145 match_found = 0;
9146 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9147 {
9148 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9149 {
9150 if (!i.rounding)
9151 {
9152 rc_op.type = RC_NamesTable[j].type;
9153 rc_op.operand = this_operand;
9154 i.rounding = &rc_op;
9155 }
9156 else
9157 {
9158 as_bad (_("duplicated `%s'"), imm_start);
9159 return 0;
9160 }
9161 pstr += RC_NamesTable[j].len;
9162 match_found = 1;
9163 break;
9164 }
9165 }
9166 if (!match_found)
9167 return 0;
9168
9169 if (*pstr++ != '}')
9170 {
9171 as_bad (_("Missing '}': '%s'"), imm_start);
9172 return 0;
9173 }
9174 /* RC/SAE immediate string should contain nothing more. */;
9175 if (*pstr != 0)
9176 {
9177 as_bad (_("Junk after '}': '%s'"), imm_start);
9178 return 0;
9179 }
9180
9181 exp = &im_expressions[i.imm_operands++];
9182 i.op[this_operand].imms = exp;
9183
9184 exp->X_op = O_constant;
9185 exp->X_add_number = 0;
9186 exp->X_add_symbol = (symbolS *) 0;
9187 exp->X_op_symbol = (symbolS *) 0;
9188
9189 i.types[this_operand].bitfield.imm8 = 1;
9190 return 1;
9191 }
9192
9193 /* Only string instructions can have a second memory operand, so
9194 reduce current_templates to just those if it contains any. */
9195 static int
9196 maybe_adjust_templates (void)
9197 {
9198 const insn_template *t;
9199
9200 gas_assert (i.mem_operands == 1);
9201
9202 for (t = current_templates->start; t < current_templates->end; ++t)
9203 if (t->opcode_modifier.isstring)
9204 break;
9205
9206 if (t < current_templates->end)
9207 {
9208 static templates aux_templates;
9209 bfd_boolean recheck;
9210
9211 aux_templates.start = t;
9212 for (; t < current_templates->end; ++t)
9213 if (!t->opcode_modifier.isstring)
9214 break;
9215 aux_templates.end = t;
9216
9217 /* Determine whether to re-check the first memory operand. */
9218 recheck = (aux_templates.start != current_templates->start
9219 || t != current_templates->end);
9220
9221 current_templates = &aux_templates;
9222
9223 if (recheck)
9224 {
9225 i.mem_operands = 0;
9226 if (i.memop1_string != NULL
9227 && i386_index_check (i.memop1_string) == 0)
9228 return 0;
9229 i.mem_operands = 1;
9230 }
9231 }
9232
9233 return 1;
9234 }
9235
9236 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9237 on error. */
9238
9239 static int
9240 i386_att_operand (char *operand_string)
9241 {
9242 const reg_entry *r;
9243 char *end_op;
9244 char *op_string = operand_string;
9245
9246 if (is_space_char (*op_string))
9247 ++op_string;
9248
9249 /* We check for an absolute prefix (differentiating,
9250 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9251 if (*op_string == ABSOLUTE_PREFIX)
9252 {
9253 ++op_string;
9254 if (is_space_char (*op_string))
9255 ++op_string;
9256 i.types[this_operand].bitfield.jumpabsolute = 1;
9257 }
9258
9259 /* Check if operand is a register. */
9260 if ((r = parse_register (op_string, &end_op)) != NULL)
9261 {
9262 i386_operand_type temp;
9263
9264 /* Check for a segment override by searching for ':' after a
9265 segment register. */
9266 op_string = end_op;
9267 if (is_space_char (*op_string))
9268 ++op_string;
9269 if (*op_string == ':'
9270 && (r->reg_type.bitfield.sreg2
9271 || r->reg_type.bitfield.sreg3))
9272 {
9273 switch (r->reg_num)
9274 {
9275 case 0:
9276 i.seg[i.mem_operands] = &es;
9277 break;
9278 case 1:
9279 i.seg[i.mem_operands] = &cs;
9280 break;
9281 case 2:
9282 i.seg[i.mem_operands] = &ss;
9283 break;
9284 case 3:
9285 i.seg[i.mem_operands] = &ds;
9286 break;
9287 case 4:
9288 i.seg[i.mem_operands] = &fs;
9289 break;
9290 case 5:
9291 i.seg[i.mem_operands] = &gs;
9292 break;
9293 }
9294
9295 /* Skip the ':' and whitespace. */
9296 ++op_string;
9297 if (is_space_char (*op_string))
9298 ++op_string;
9299
9300 if (!is_digit_char (*op_string)
9301 && !is_identifier_char (*op_string)
9302 && *op_string != '('
9303 && *op_string != ABSOLUTE_PREFIX)
9304 {
9305 as_bad (_("bad memory operand `%s'"), op_string);
9306 return 0;
9307 }
9308 /* Handle case of %es:*foo. */
9309 if (*op_string == ABSOLUTE_PREFIX)
9310 {
9311 ++op_string;
9312 if (is_space_char (*op_string))
9313 ++op_string;
9314 i.types[this_operand].bitfield.jumpabsolute = 1;
9315 }
9316 goto do_memory_reference;
9317 }
9318
9319 /* Handle vector operations. */
9320 if (*op_string == '{')
9321 {
9322 op_string = check_VecOperations (op_string, NULL);
9323 if (op_string == NULL)
9324 return 0;
9325 }
9326
9327 if (*op_string)
9328 {
9329 as_bad (_("junk `%s' after register"), op_string);
9330 return 0;
9331 }
9332 temp = r->reg_type;
9333 temp.bitfield.baseindex = 0;
9334 i.types[this_operand] = operand_type_or (i.types[this_operand],
9335 temp);
9336 i.types[this_operand].bitfield.unspecified = 0;
9337 i.op[this_operand].regs = r;
9338 i.reg_operands++;
9339 }
9340 else if (*op_string == REGISTER_PREFIX)
9341 {
9342 as_bad (_("bad register name `%s'"), op_string);
9343 return 0;
9344 }
9345 else if (*op_string == IMMEDIATE_PREFIX)
9346 {
9347 ++op_string;
9348 if (i.types[this_operand].bitfield.jumpabsolute)
9349 {
9350 as_bad (_("immediate operand illegal with absolute jump"));
9351 return 0;
9352 }
9353 if (!i386_immediate (op_string))
9354 return 0;
9355 }
9356 else if (RC_SAE_immediate (operand_string))
9357 {
9358 /* If it is a RC or SAE immediate, do nothing. */
9359 ;
9360 }
9361 else if (is_digit_char (*op_string)
9362 || is_identifier_char (*op_string)
9363 || *op_string == '"'
9364 || *op_string == '(')
9365 {
9366 /* This is a memory reference of some sort. */
9367 char *base_string;
9368
9369 /* Start and end of displacement string expression (if found). */
9370 char *displacement_string_start;
9371 char *displacement_string_end;
9372 char *vop_start;
9373
9374 do_memory_reference:
9375 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9376 return 0;
9377 if ((i.mem_operands == 1
9378 && !current_templates->start->opcode_modifier.isstring)
9379 || i.mem_operands == 2)
9380 {
9381 as_bad (_("too many memory references for `%s'"),
9382 current_templates->start->name);
9383 return 0;
9384 }
9385
9386 /* Check for base index form. We detect the base index form by
9387 looking for an ')' at the end of the operand, searching
9388 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9389 after the '('. */
9390 base_string = op_string + strlen (op_string);
9391
9392 /* Handle vector operations. */
9393 vop_start = strchr (op_string, '{');
9394 if (vop_start && vop_start < base_string)
9395 {
9396 if (check_VecOperations (vop_start, base_string) == NULL)
9397 return 0;
9398 base_string = vop_start;
9399 }
9400
9401 --base_string;
9402 if (is_space_char (*base_string))
9403 --base_string;
9404
9405 /* If we only have a displacement, set-up for it to be parsed later. */
9406 displacement_string_start = op_string;
9407 displacement_string_end = base_string + 1;
9408
9409 if (*base_string == ')')
9410 {
9411 char *temp_string;
9412 unsigned int parens_balanced = 1;
9413 /* We've already checked that the number of left & right ()'s are
9414 equal, so this loop will not be infinite. */
9415 do
9416 {
9417 base_string--;
9418 if (*base_string == ')')
9419 parens_balanced++;
9420 if (*base_string == '(')
9421 parens_balanced--;
9422 }
9423 while (parens_balanced);
9424
9425 temp_string = base_string;
9426
9427 /* Skip past '(' and whitespace. */
9428 ++base_string;
9429 if (is_space_char (*base_string))
9430 ++base_string;
9431
9432 if (*base_string == ','
9433 || ((i.base_reg = parse_register (base_string, &end_op))
9434 != NULL))
9435 {
9436 displacement_string_end = temp_string;
9437
9438 i.types[this_operand].bitfield.baseindex = 1;
9439
9440 if (i.base_reg)
9441 {
9442 base_string = end_op;
9443 if (is_space_char (*base_string))
9444 ++base_string;
9445 }
9446
9447 /* There may be an index reg or scale factor here. */
9448 if (*base_string == ',')
9449 {
9450 ++base_string;
9451 if (is_space_char (*base_string))
9452 ++base_string;
9453
9454 if ((i.index_reg = parse_register (base_string, &end_op))
9455 != NULL)
9456 {
9457 base_string = end_op;
9458 if (is_space_char (*base_string))
9459 ++base_string;
9460 if (*base_string == ',')
9461 {
9462 ++base_string;
9463 if (is_space_char (*base_string))
9464 ++base_string;
9465 }
9466 else if (*base_string != ')')
9467 {
9468 as_bad (_("expecting `,' or `)' "
9469 "after index register in `%s'"),
9470 operand_string);
9471 return 0;
9472 }
9473 }
9474 else if (*base_string == REGISTER_PREFIX)
9475 {
9476 end_op = strchr (base_string, ',');
9477 if (end_op)
9478 *end_op = '\0';
9479 as_bad (_("bad register name `%s'"), base_string);
9480 return 0;
9481 }
9482
9483 /* Check for scale factor. */
9484 if (*base_string != ')')
9485 {
9486 char *end_scale = i386_scale (base_string);
9487
9488 if (!end_scale)
9489 return 0;
9490
9491 base_string = end_scale;
9492 if (is_space_char (*base_string))
9493 ++base_string;
9494 if (*base_string != ')')
9495 {
9496 as_bad (_("expecting `)' "
9497 "after scale factor in `%s'"),
9498 operand_string);
9499 return 0;
9500 }
9501 }
9502 else if (!i.index_reg)
9503 {
9504 as_bad (_("expecting index register or scale factor "
9505 "after `,'; got '%c'"),
9506 *base_string);
9507 return 0;
9508 }
9509 }
9510 else if (*base_string != ')')
9511 {
9512 as_bad (_("expecting `,' or `)' "
9513 "after base register in `%s'"),
9514 operand_string);
9515 return 0;
9516 }
9517 }
9518 else if (*base_string == REGISTER_PREFIX)
9519 {
9520 end_op = strchr (base_string, ',');
9521 if (end_op)
9522 *end_op = '\0';
9523 as_bad (_("bad register name `%s'"), base_string);
9524 return 0;
9525 }
9526 }
9527
9528 /* If there's an expression beginning the operand, parse it,
9529 assuming displacement_string_start and
9530 displacement_string_end are meaningful. */
9531 if (displacement_string_start != displacement_string_end)
9532 {
9533 if (!i386_displacement (displacement_string_start,
9534 displacement_string_end))
9535 return 0;
9536 }
9537
9538 /* Special case for (%dx) while doing input/output op. */
9539 if (i.base_reg
9540 && operand_type_equal (&i.base_reg->reg_type,
9541 &reg16_inoutportreg)
9542 && i.index_reg == 0
9543 && i.log2_scale_factor == 0
9544 && i.seg[i.mem_operands] == 0
9545 && !operand_type_check (i.types[this_operand], disp))
9546 {
9547 i.types[this_operand] = inoutportreg;
9548 return 1;
9549 }
9550
9551 if (i386_index_check (operand_string) == 0)
9552 return 0;
9553 i.types[this_operand].bitfield.mem = 1;
9554 if (i.mem_operands == 0)
9555 i.memop1_string = xstrdup (operand_string);
9556 i.mem_operands++;
9557 }
9558 else
9559 {
9560 /* It's not a memory operand; argh! */
9561 as_bad (_("invalid char %s beginning operand %d `%s'"),
9562 output_invalid (*op_string),
9563 this_operand + 1,
9564 op_string);
9565 return 0;
9566 }
9567 return 1; /* Normal return. */
9568 }
9569 \f
9570 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9571 that an rs_machine_dependent frag may reach. */
9572
9573 unsigned int
9574 i386_frag_max_var (fragS *frag)
9575 {
9576 /* The only relaxable frags are for jumps.
9577 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9578 gas_assert (frag->fr_type == rs_machine_dependent);
9579 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9580 }
9581
9582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9583 static int
9584 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9585 {
9586 /* STT_GNU_IFUNC symbol must go through PLT. */
9587 if ((symbol_get_bfdsym (fr_symbol)->flags
9588 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9589 return 0;
9590
9591 if (!S_IS_EXTERNAL (fr_symbol))
9592 /* Symbol may be weak or local. */
9593 return !S_IS_WEAK (fr_symbol);
9594
9595 /* Global symbols with non-default visibility can't be preempted. */
9596 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9597 return 1;
9598
9599 if (fr_var != NO_RELOC)
9600 switch ((enum bfd_reloc_code_real) fr_var)
9601 {
9602 case BFD_RELOC_386_PLT32:
9603 case BFD_RELOC_X86_64_PLT32:
9604 /* Symbol with PLT relocation may be preempted. */
9605 return 0;
9606 default:
9607 abort ();
9608 }
9609
9610 /* Global symbols with default visibility in a shared library may be
9611 preempted by another definition. */
9612 return !shared;
9613 }
9614 #endif
9615
9616 /* md_estimate_size_before_relax()
9617
9618 Called just before relax() for rs_machine_dependent frags. The x86
9619 assembler uses these frags to handle variable size jump
9620 instructions.
9621
9622 Any symbol that is now undefined will not become defined.
9623 Return the correct fr_subtype in the frag.
9624 Return the initial "guess for variable size of frag" to caller.
9625 The guess is actually the growth beyond the fixed part. Whatever
9626 we do to grow the fixed or variable part contributes to our
9627 returned value. */
9628
9629 int
9630 md_estimate_size_before_relax (fragS *fragP, segT segment)
9631 {
9632 /* We've already got fragP->fr_subtype right; all we have to do is
9633 check for un-relaxable symbols. On an ELF system, we can't relax
9634 an externally visible symbol, because it may be overridden by a
9635 shared library. */
9636 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9637 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9638 || (IS_ELF
9639 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9640 fragP->fr_var))
9641 #endif
9642 #if defined (OBJ_COFF) && defined (TE_PE)
9643 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9644 && S_IS_WEAK (fragP->fr_symbol))
9645 #endif
9646 )
9647 {
9648 /* Symbol is undefined in this segment, or we need to keep a
9649 reloc so that weak symbols can be overridden. */
9650 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9651 enum bfd_reloc_code_real reloc_type;
9652 unsigned char *opcode;
9653 int old_fr_fix;
9654
9655 if (fragP->fr_var != NO_RELOC)
9656 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9657 else if (size == 2)
9658 reloc_type = BFD_RELOC_16_PCREL;
9659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9660 else if (need_plt32_p (fragP->fr_symbol))
9661 reloc_type = BFD_RELOC_X86_64_PLT32;
9662 #endif
9663 else
9664 reloc_type = BFD_RELOC_32_PCREL;
9665
9666 old_fr_fix = fragP->fr_fix;
9667 opcode = (unsigned char *) fragP->fr_opcode;
9668
9669 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9670 {
9671 case UNCOND_JUMP:
9672 /* Make jmp (0xeb) a (d)word displacement jump. */
9673 opcode[0] = 0xe9;
9674 fragP->fr_fix += size;
9675 fix_new (fragP, old_fr_fix, size,
9676 fragP->fr_symbol,
9677 fragP->fr_offset, 1,
9678 reloc_type);
9679 break;
9680
9681 case COND_JUMP86:
9682 if (size == 2
9683 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9684 {
9685 /* Negate the condition, and branch past an
9686 unconditional jump. */
9687 opcode[0] ^= 1;
9688 opcode[1] = 3;
9689 /* Insert an unconditional jump. */
9690 opcode[2] = 0xe9;
9691 /* We added two extra opcode bytes, and have a two byte
9692 offset. */
9693 fragP->fr_fix += 2 + 2;
9694 fix_new (fragP, old_fr_fix + 2, 2,
9695 fragP->fr_symbol,
9696 fragP->fr_offset, 1,
9697 reloc_type);
9698 break;
9699 }
9700 /* Fall through. */
9701
9702 case COND_JUMP:
9703 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9704 {
9705 fixS *fixP;
9706
9707 fragP->fr_fix += 1;
9708 fixP = fix_new (fragP, old_fr_fix, 1,
9709 fragP->fr_symbol,
9710 fragP->fr_offset, 1,
9711 BFD_RELOC_8_PCREL);
9712 fixP->fx_signed = 1;
9713 break;
9714 }
9715
9716 /* This changes the byte-displacement jump 0x7N
9717 to the (d)word-displacement jump 0x0f,0x8N. */
9718 opcode[1] = opcode[0] + 0x10;
9719 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9720 /* We've added an opcode byte. */
9721 fragP->fr_fix += 1 + size;
9722 fix_new (fragP, old_fr_fix + 1, size,
9723 fragP->fr_symbol,
9724 fragP->fr_offset, 1,
9725 reloc_type);
9726 break;
9727
9728 default:
9729 BAD_CASE (fragP->fr_subtype);
9730 break;
9731 }
9732 frag_wane (fragP);
9733 return fragP->fr_fix - old_fr_fix;
9734 }
9735
9736 /* Guess size depending on current relax state. Initially the relax
9737 state will correspond to a short jump and we return 1, because
9738 the variable part of the frag (the branch offset) is one byte
9739 long. However, we can relax a section more than once and in that
9740 case we must either set fr_subtype back to the unrelaxed state,
9741 or return the value for the appropriate branch. */
9742 return md_relax_table[fragP->fr_subtype].rlx_length;
9743 }
9744
9745 /* Called after relax() is finished.
9746
9747 In: Address of frag.
9748 fr_type == rs_machine_dependent.
9749 fr_subtype is what the address relaxed to.
9750
9751 Out: Any fixSs and constants are set up.
9752 Caller will turn frag into a ".space 0". */
9753
9754 void
9755 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9756 fragS *fragP)
9757 {
9758 unsigned char *opcode;
9759 unsigned char *where_to_put_displacement = NULL;
9760 offsetT target_address;
9761 offsetT opcode_address;
9762 unsigned int extension = 0;
9763 offsetT displacement_from_opcode_start;
9764
9765 opcode = (unsigned char *) fragP->fr_opcode;
9766
9767 /* Address we want to reach in file space. */
9768 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9769
9770 /* Address opcode resides at in file space. */
9771 opcode_address = fragP->fr_address + fragP->fr_fix;
9772
9773 /* Displacement from opcode start to fill into instruction. */
9774 displacement_from_opcode_start = target_address - opcode_address;
9775
9776 if ((fragP->fr_subtype & BIG) == 0)
9777 {
9778 /* Don't have to change opcode. */
9779 extension = 1; /* 1 opcode + 1 displacement */
9780 where_to_put_displacement = &opcode[1];
9781 }
9782 else
9783 {
9784 if (no_cond_jump_promotion
9785 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9786 as_warn_where (fragP->fr_file, fragP->fr_line,
9787 _("long jump required"));
9788
9789 switch (fragP->fr_subtype)
9790 {
9791 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9792 extension = 4; /* 1 opcode + 4 displacement */
9793 opcode[0] = 0xe9;
9794 where_to_put_displacement = &opcode[1];
9795 break;
9796
9797 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9798 extension = 2; /* 1 opcode + 2 displacement */
9799 opcode[0] = 0xe9;
9800 where_to_put_displacement = &opcode[1];
9801 break;
9802
9803 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9804 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9805 extension = 5; /* 2 opcode + 4 displacement */
9806 opcode[1] = opcode[0] + 0x10;
9807 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9808 where_to_put_displacement = &opcode[2];
9809 break;
9810
9811 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9812 extension = 3; /* 2 opcode + 2 displacement */
9813 opcode[1] = opcode[0] + 0x10;
9814 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9815 where_to_put_displacement = &opcode[2];
9816 break;
9817
9818 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9819 extension = 4;
9820 opcode[0] ^= 1;
9821 opcode[1] = 3;
9822 opcode[2] = 0xe9;
9823 where_to_put_displacement = &opcode[3];
9824 break;
9825
9826 default:
9827 BAD_CASE (fragP->fr_subtype);
9828 break;
9829 }
9830 }
9831
9832 /* If size if less then four we are sure that the operand fits,
9833 but if it's 4, then it could be that the displacement is larger
9834 then -/+ 2GB. */
9835 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9836 && object_64bit
9837 && ((addressT) (displacement_from_opcode_start - extension
9838 + ((addressT) 1 << 31))
9839 > (((addressT) 2 << 31) - 1)))
9840 {
9841 as_bad_where (fragP->fr_file, fragP->fr_line,
9842 _("jump target out of range"));
9843 /* Make us emit 0. */
9844 displacement_from_opcode_start = extension;
9845 }
9846 /* Now put displacement after opcode. */
9847 md_number_to_chars ((char *) where_to_put_displacement,
9848 (valueT) (displacement_from_opcode_start - extension),
9849 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9850 fragP->fr_fix += extension;
9851 }
9852 \f
9853 /* Apply a fixup (fixP) to segment data, once it has been determined
9854 by our caller that we have all the info we need to fix it up.
9855
9856 Parameter valP is the pointer to the value of the bits.
9857
9858 On the 386, immediates, displacements, and data pointers are all in
9859 the same (little-endian) format, so we don't need to care about which
9860 we are handling. */
9861
9862 void
9863 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9864 {
9865 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9866 valueT value = *valP;
9867
9868 #if !defined (TE_Mach)
9869 if (fixP->fx_pcrel)
9870 {
9871 switch (fixP->fx_r_type)
9872 {
9873 default:
9874 break;
9875
9876 case BFD_RELOC_64:
9877 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9878 break;
9879 case BFD_RELOC_32:
9880 case BFD_RELOC_X86_64_32S:
9881 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9882 break;
9883 case BFD_RELOC_16:
9884 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9885 break;
9886 case BFD_RELOC_8:
9887 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9888 break;
9889 }
9890 }
9891
9892 if (fixP->fx_addsy != NULL
9893 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9894 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9895 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9896 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9897 && !use_rela_relocations)
9898 {
9899 /* This is a hack. There should be a better way to handle this.
9900 This covers for the fact that bfd_install_relocation will
9901 subtract the current location (for partial_inplace, PC relative
9902 relocations); see more below. */
9903 #ifndef OBJ_AOUT
9904 if (IS_ELF
9905 #ifdef TE_PE
9906 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9907 #endif
9908 )
9909 value += fixP->fx_where + fixP->fx_frag->fr_address;
9910 #endif
9911 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9912 if (IS_ELF)
9913 {
9914 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9915
9916 if ((sym_seg == seg
9917 || (symbol_section_p (fixP->fx_addsy)
9918 && sym_seg != absolute_section))
9919 && !generic_force_reloc (fixP))
9920 {
9921 /* Yes, we add the values in twice. This is because
9922 bfd_install_relocation subtracts them out again. I think
9923 bfd_install_relocation is broken, but I don't dare change
9924 it. FIXME. */
9925 value += fixP->fx_where + fixP->fx_frag->fr_address;
9926 }
9927 }
9928 #endif
9929 #if defined (OBJ_COFF) && defined (TE_PE)
9930 /* For some reason, the PE format does not store a
9931 section address offset for a PC relative symbol. */
9932 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9933 || S_IS_WEAK (fixP->fx_addsy))
9934 value += md_pcrel_from (fixP);
9935 #endif
9936 }
9937 #if defined (OBJ_COFF) && defined (TE_PE)
9938 if (fixP->fx_addsy != NULL
9939 && S_IS_WEAK (fixP->fx_addsy)
9940 /* PR 16858: Do not modify weak function references. */
9941 && ! fixP->fx_pcrel)
9942 {
9943 #if !defined (TE_PEP)
9944 /* For x86 PE weak function symbols are neither PC-relative
9945 nor do they set S_IS_FUNCTION. So the only reliable way
9946 to detect them is to check the flags of their containing
9947 section. */
9948 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9949 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9950 ;
9951 else
9952 #endif
9953 value -= S_GET_VALUE (fixP->fx_addsy);
9954 }
9955 #endif
9956
9957 /* Fix a few things - the dynamic linker expects certain values here,
9958 and we must not disappoint it. */
9959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9960 if (IS_ELF && fixP->fx_addsy)
9961 switch (fixP->fx_r_type)
9962 {
9963 case BFD_RELOC_386_PLT32:
9964 case BFD_RELOC_X86_64_PLT32:
9965 /* Make the jump instruction point to the address of the operand. At
9966 runtime we merely add the offset to the actual PLT entry. */
9967 value = -4;
9968 break;
9969
9970 case BFD_RELOC_386_TLS_GD:
9971 case BFD_RELOC_386_TLS_LDM:
9972 case BFD_RELOC_386_TLS_IE_32:
9973 case BFD_RELOC_386_TLS_IE:
9974 case BFD_RELOC_386_TLS_GOTIE:
9975 case BFD_RELOC_386_TLS_GOTDESC:
9976 case BFD_RELOC_X86_64_TLSGD:
9977 case BFD_RELOC_X86_64_TLSLD:
9978 case BFD_RELOC_X86_64_GOTTPOFF:
9979 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9980 value = 0; /* Fully resolved at runtime. No addend. */
9981 /* Fallthrough */
9982 case BFD_RELOC_386_TLS_LE:
9983 case BFD_RELOC_386_TLS_LDO_32:
9984 case BFD_RELOC_386_TLS_LE_32:
9985 case BFD_RELOC_X86_64_DTPOFF32:
9986 case BFD_RELOC_X86_64_DTPOFF64:
9987 case BFD_RELOC_X86_64_TPOFF32:
9988 case BFD_RELOC_X86_64_TPOFF64:
9989 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9990 break;
9991
9992 case BFD_RELOC_386_TLS_DESC_CALL:
9993 case BFD_RELOC_X86_64_TLSDESC_CALL:
9994 value = 0; /* Fully resolved at runtime. No addend. */
9995 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9996 fixP->fx_done = 0;
9997 return;
9998
9999 case BFD_RELOC_VTABLE_INHERIT:
10000 case BFD_RELOC_VTABLE_ENTRY:
10001 fixP->fx_done = 0;
10002 return;
10003
10004 default:
10005 break;
10006 }
10007 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10008 *valP = value;
10009 #endif /* !defined (TE_Mach) */
10010
10011 /* Are we finished with this relocation now? */
10012 if (fixP->fx_addsy == NULL)
10013 fixP->fx_done = 1;
10014 #if defined (OBJ_COFF) && defined (TE_PE)
10015 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10016 {
10017 fixP->fx_done = 0;
10018 /* Remember value for tc_gen_reloc. */
10019 fixP->fx_addnumber = value;
10020 /* Clear out the frag for now. */
10021 value = 0;
10022 }
10023 #endif
10024 else if (use_rela_relocations)
10025 {
10026 fixP->fx_no_overflow = 1;
10027 /* Remember value for tc_gen_reloc. */
10028 fixP->fx_addnumber = value;
10029 value = 0;
10030 }
10031
10032 md_number_to_chars (p, value, fixP->fx_size);
10033 }
10034 \f
10035 const char *
10036 md_atof (int type, char *litP, int *sizeP)
10037 {
10038 /* This outputs the LITTLENUMs in REVERSE order;
10039 in accord with the bigendian 386. */
10040 return ieee_md_atof (type, litP, sizeP, FALSE);
10041 }
10042 \f
10043 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10044
10045 static char *
10046 output_invalid (int c)
10047 {
10048 if (ISPRINT (c))
10049 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10050 "'%c'", c);
10051 else
10052 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10053 "(0x%x)", (unsigned char) c);
10054 return output_invalid_buf;
10055 }
10056
10057 /* REG_STRING starts *before* REGISTER_PREFIX. */
10058
10059 static const reg_entry *
10060 parse_real_register (char *reg_string, char **end_op)
10061 {
10062 char *s = reg_string;
10063 char *p;
10064 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10065 const reg_entry *r;
10066
10067 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10068 if (*s == REGISTER_PREFIX)
10069 ++s;
10070
10071 if (is_space_char (*s))
10072 ++s;
10073
10074 p = reg_name_given;
10075 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10076 {
10077 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10078 return (const reg_entry *) NULL;
10079 s++;
10080 }
10081
10082 /* For naked regs, make sure that we are not dealing with an identifier.
10083 This prevents confusing an identifier like `eax_var' with register
10084 `eax'. */
10085 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10086 return (const reg_entry *) NULL;
10087
10088 *end_op = s;
10089
10090 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10091
10092 /* Handle floating point regs, allowing spaces in the (i) part. */
10093 if (r == i386_regtab /* %st is first entry of table */)
10094 {
10095 if (is_space_char (*s))
10096 ++s;
10097 if (*s == '(')
10098 {
10099 ++s;
10100 if (is_space_char (*s))
10101 ++s;
10102 if (*s >= '0' && *s <= '7')
10103 {
10104 int fpr = *s - '0';
10105 ++s;
10106 if (is_space_char (*s))
10107 ++s;
10108 if (*s == ')')
10109 {
10110 *end_op = s + 1;
10111 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10112 know (r);
10113 return r + fpr;
10114 }
10115 }
10116 /* We have "%st(" then garbage. */
10117 return (const reg_entry *) NULL;
10118 }
10119 }
10120
10121 if (r == NULL || allow_pseudo_reg)
10122 return r;
10123
10124 if (operand_type_all_zero (&r->reg_type))
10125 return (const reg_entry *) NULL;
10126
10127 if ((r->reg_type.bitfield.dword
10128 || r->reg_type.bitfield.sreg3
10129 || r->reg_type.bitfield.control
10130 || r->reg_type.bitfield.debug
10131 || r->reg_type.bitfield.test)
10132 && !cpu_arch_flags.bitfield.cpui386)
10133 return (const reg_entry *) NULL;
10134
10135 if (r->reg_type.bitfield.tbyte
10136 && !cpu_arch_flags.bitfield.cpu8087
10137 && !cpu_arch_flags.bitfield.cpu287
10138 && !cpu_arch_flags.bitfield.cpu387)
10139 return (const reg_entry *) NULL;
10140
10141 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10142 return (const reg_entry *) NULL;
10143
10144 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10145 return (const reg_entry *) NULL;
10146
10147 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10148 return (const reg_entry *) NULL;
10149
10150 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10151 return (const reg_entry *) NULL;
10152
10153 if (r->reg_type.bitfield.regmask
10154 && !cpu_arch_flags.bitfield.cpuregmask)
10155 return (const reg_entry *) NULL;
10156
10157 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10158 if (!allow_index_reg
10159 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10160 return (const reg_entry *) NULL;
10161
10162 /* Upper 16 vector register is only available with VREX in 64bit
10163 mode. */
10164 if ((r->reg_flags & RegVRex))
10165 {
10166 if (i.vec_encoding == vex_encoding_default)
10167 i.vec_encoding = vex_encoding_evex;
10168
10169 if (!cpu_arch_flags.bitfield.cpuvrex
10170 || i.vec_encoding != vex_encoding_evex
10171 || flag_code != CODE_64BIT)
10172 return (const reg_entry *) NULL;
10173 }
10174
10175 if (((r->reg_flags & (RegRex64 | RegRex))
10176 || r->reg_type.bitfield.qword)
10177 && (!cpu_arch_flags.bitfield.cpulm
10178 || !operand_type_equal (&r->reg_type, &control))
10179 && flag_code != CODE_64BIT)
10180 return (const reg_entry *) NULL;
10181
10182 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10183 return (const reg_entry *) NULL;
10184
10185 return r;
10186 }
10187
10188 /* REG_STRING starts *before* REGISTER_PREFIX. */
10189
10190 static const reg_entry *
10191 parse_register (char *reg_string, char **end_op)
10192 {
10193 const reg_entry *r;
10194
10195 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10196 r = parse_real_register (reg_string, end_op);
10197 else
10198 r = NULL;
10199 if (!r)
10200 {
10201 char *save = input_line_pointer;
10202 char c;
10203 symbolS *symbolP;
10204
10205 input_line_pointer = reg_string;
10206 c = get_symbol_name (&reg_string);
10207 symbolP = symbol_find (reg_string);
10208 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10209 {
10210 const expressionS *e = symbol_get_value_expression (symbolP);
10211
10212 know (e->X_op == O_register);
10213 know (e->X_add_number >= 0
10214 && (valueT) e->X_add_number < i386_regtab_size);
10215 r = i386_regtab + e->X_add_number;
10216 if ((r->reg_flags & RegVRex))
10217 i.vec_encoding = vex_encoding_evex;
10218 *end_op = input_line_pointer;
10219 }
10220 *input_line_pointer = c;
10221 input_line_pointer = save;
10222 }
10223 return r;
10224 }
10225
10226 int
10227 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10228 {
10229 const reg_entry *r;
10230 char *end = input_line_pointer;
10231
10232 *end = *nextcharP;
10233 r = parse_register (name, &input_line_pointer);
10234 if (r && end <= input_line_pointer)
10235 {
10236 *nextcharP = *input_line_pointer;
10237 *input_line_pointer = 0;
10238 e->X_op = O_register;
10239 e->X_add_number = r - i386_regtab;
10240 return 1;
10241 }
10242 input_line_pointer = end;
10243 *end = 0;
10244 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10245 }
10246
10247 void
10248 md_operand (expressionS *e)
10249 {
10250 char *end;
10251 const reg_entry *r;
10252
10253 switch (*input_line_pointer)
10254 {
10255 case REGISTER_PREFIX:
10256 r = parse_real_register (input_line_pointer, &end);
10257 if (r)
10258 {
10259 e->X_op = O_register;
10260 e->X_add_number = r - i386_regtab;
10261 input_line_pointer = end;
10262 }
10263 break;
10264
10265 case '[':
10266 gas_assert (intel_syntax);
10267 end = input_line_pointer++;
10268 expression (e);
10269 if (*input_line_pointer == ']')
10270 {
10271 ++input_line_pointer;
10272 e->X_op_symbol = make_expr_symbol (e);
10273 e->X_add_symbol = NULL;
10274 e->X_add_number = 0;
10275 e->X_op = O_index;
10276 }
10277 else
10278 {
10279 e->X_op = O_absent;
10280 input_line_pointer = end;
10281 }
10282 break;
10283 }
10284 }
10285
10286 \f
10287 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10288 const char *md_shortopts = "kVQ:sqnO::";
10289 #else
10290 const char *md_shortopts = "qnO::";
10291 #endif
10292
10293 #define OPTION_32 (OPTION_MD_BASE + 0)
10294 #define OPTION_64 (OPTION_MD_BASE + 1)
10295 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10296 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10297 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10298 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10299 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10300 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10301 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10302 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10303 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10304 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10305 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10306 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10307 #define OPTION_X32 (OPTION_MD_BASE + 14)
10308 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10309 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10310 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10311 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10312 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10313 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10314 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10315 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10316 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10317 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10318 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10319
10320 struct option md_longopts[] =
10321 {
10322 {"32", no_argument, NULL, OPTION_32},
10323 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10324 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10325 {"64", no_argument, NULL, OPTION_64},
10326 #endif
10327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10328 {"x32", no_argument, NULL, OPTION_X32},
10329 {"mshared", no_argument, NULL, OPTION_MSHARED},
10330 #endif
10331 {"divide", no_argument, NULL, OPTION_DIVIDE},
10332 {"march", required_argument, NULL, OPTION_MARCH},
10333 {"mtune", required_argument, NULL, OPTION_MTUNE},
10334 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10335 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10336 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10337 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10338 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10339 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10340 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10341 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10342 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10343 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10344 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10345 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10346 # if defined (TE_PE) || defined (TE_PEP)
10347 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10348 #endif
10349 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10350 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10351 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10352 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10353 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10354 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10355 {NULL, no_argument, NULL, 0}
10356 };
10357 size_t md_longopts_size = sizeof (md_longopts);
10358
10359 int
10360 md_parse_option (int c, const char *arg)
10361 {
10362 unsigned int j;
10363 char *arch, *next, *saved;
10364
10365 switch (c)
10366 {
10367 case 'n':
10368 optimize_align_code = 0;
10369 break;
10370
10371 case 'q':
10372 quiet_warnings = 1;
10373 break;
10374
10375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10376 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10377 should be emitted or not. FIXME: Not implemented. */
10378 case 'Q':
10379 break;
10380
10381 /* -V: SVR4 argument to print version ID. */
10382 case 'V':
10383 print_version_id ();
10384 break;
10385
10386 /* -k: Ignore for FreeBSD compatibility. */
10387 case 'k':
10388 break;
10389
10390 case 's':
10391 /* -s: On i386 Solaris, this tells the native assembler to use
10392 .stab instead of .stab.excl. We always use .stab anyhow. */
10393 break;
10394
10395 case OPTION_MSHARED:
10396 shared = 1;
10397 break;
10398 #endif
10399 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10400 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10401 case OPTION_64:
10402 {
10403 const char **list, **l;
10404
10405 list = bfd_target_list ();
10406 for (l = list; *l != NULL; l++)
10407 if (CONST_STRNEQ (*l, "elf64-x86-64")
10408 || strcmp (*l, "coff-x86-64") == 0
10409 || strcmp (*l, "pe-x86-64") == 0
10410 || strcmp (*l, "pei-x86-64") == 0
10411 || strcmp (*l, "mach-o-x86-64") == 0)
10412 {
10413 default_arch = "x86_64";
10414 break;
10415 }
10416 if (*l == NULL)
10417 as_fatal (_("no compiled in support for x86_64"));
10418 free (list);
10419 }
10420 break;
10421 #endif
10422
10423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10424 case OPTION_X32:
10425 if (IS_ELF)
10426 {
10427 const char **list, **l;
10428
10429 list = bfd_target_list ();
10430 for (l = list; *l != NULL; l++)
10431 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10432 {
10433 default_arch = "x86_64:32";
10434 break;
10435 }
10436 if (*l == NULL)
10437 as_fatal (_("no compiled in support for 32bit x86_64"));
10438 free (list);
10439 }
10440 else
10441 as_fatal (_("32bit x86_64 is only supported for ELF"));
10442 break;
10443 #endif
10444
10445 case OPTION_32:
10446 default_arch = "i386";
10447 break;
10448
10449 case OPTION_DIVIDE:
10450 #ifdef SVR4_COMMENT_CHARS
10451 {
10452 char *n, *t;
10453 const char *s;
10454
10455 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10456 t = n;
10457 for (s = i386_comment_chars; *s != '\0'; s++)
10458 if (*s != '/')
10459 *t++ = *s;
10460 *t = '\0';
10461 i386_comment_chars = n;
10462 }
10463 #endif
10464 break;
10465
10466 case OPTION_MARCH:
10467 saved = xstrdup (arg);
10468 arch = saved;
10469 /* Allow -march=+nosse. */
10470 if (*arch == '+')
10471 arch++;
10472 do
10473 {
10474 if (*arch == '.')
10475 as_fatal (_("invalid -march= option: `%s'"), arg);
10476 next = strchr (arch, '+');
10477 if (next)
10478 *next++ = '\0';
10479 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10480 {
10481 if (strcmp (arch, cpu_arch [j].name) == 0)
10482 {
10483 /* Processor. */
10484 if (! cpu_arch[j].flags.bitfield.cpui386)
10485 continue;
10486
10487 cpu_arch_name = cpu_arch[j].name;
10488 cpu_sub_arch_name = NULL;
10489 cpu_arch_flags = cpu_arch[j].flags;
10490 cpu_arch_isa = cpu_arch[j].type;
10491 cpu_arch_isa_flags = cpu_arch[j].flags;
10492 if (!cpu_arch_tune_set)
10493 {
10494 cpu_arch_tune = cpu_arch_isa;
10495 cpu_arch_tune_flags = cpu_arch_isa_flags;
10496 }
10497 break;
10498 }
10499 else if (*cpu_arch [j].name == '.'
10500 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10501 {
10502 /* ISA extension. */
10503 i386_cpu_flags flags;
10504
10505 flags = cpu_flags_or (cpu_arch_flags,
10506 cpu_arch[j].flags);
10507
10508 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10509 {
10510 if (cpu_sub_arch_name)
10511 {
10512 char *name = cpu_sub_arch_name;
10513 cpu_sub_arch_name = concat (name,
10514 cpu_arch[j].name,
10515 (const char *) NULL);
10516 free (name);
10517 }
10518 else
10519 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10520 cpu_arch_flags = flags;
10521 cpu_arch_isa_flags = flags;
10522 }
10523 break;
10524 }
10525 }
10526
10527 if (j >= ARRAY_SIZE (cpu_arch))
10528 {
10529 /* Disable an ISA extension. */
10530 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10531 if (strcmp (arch, cpu_noarch [j].name) == 0)
10532 {
10533 i386_cpu_flags flags;
10534
10535 flags = cpu_flags_and_not (cpu_arch_flags,
10536 cpu_noarch[j].flags);
10537 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10538 {
10539 if (cpu_sub_arch_name)
10540 {
10541 char *name = cpu_sub_arch_name;
10542 cpu_sub_arch_name = concat (arch,
10543 (const char *) NULL);
10544 free (name);
10545 }
10546 else
10547 cpu_sub_arch_name = xstrdup (arch);
10548 cpu_arch_flags = flags;
10549 cpu_arch_isa_flags = flags;
10550 }
10551 break;
10552 }
10553
10554 if (j >= ARRAY_SIZE (cpu_noarch))
10555 j = ARRAY_SIZE (cpu_arch);
10556 }
10557
10558 if (j >= ARRAY_SIZE (cpu_arch))
10559 as_fatal (_("invalid -march= option: `%s'"), arg);
10560
10561 arch = next;
10562 }
10563 while (next != NULL);
10564 free (saved);
10565 break;
10566
10567 case OPTION_MTUNE:
10568 if (*arg == '.')
10569 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10570 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10571 {
10572 if (strcmp (arg, cpu_arch [j].name) == 0)
10573 {
10574 cpu_arch_tune_set = 1;
10575 cpu_arch_tune = cpu_arch [j].type;
10576 cpu_arch_tune_flags = cpu_arch[j].flags;
10577 break;
10578 }
10579 }
10580 if (j >= ARRAY_SIZE (cpu_arch))
10581 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10582 break;
10583
10584 case OPTION_MMNEMONIC:
10585 if (strcasecmp (arg, "att") == 0)
10586 intel_mnemonic = 0;
10587 else if (strcasecmp (arg, "intel") == 0)
10588 intel_mnemonic = 1;
10589 else
10590 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10591 break;
10592
10593 case OPTION_MSYNTAX:
10594 if (strcasecmp (arg, "att") == 0)
10595 intel_syntax = 0;
10596 else if (strcasecmp (arg, "intel") == 0)
10597 intel_syntax = 1;
10598 else
10599 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10600 break;
10601
10602 case OPTION_MINDEX_REG:
10603 allow_index_reg = 1;
10604 break;
10605
10606 case OPTION_MNAKED_REG:
10607 allow_naked_reg = 1;
10608 break;
10609
10610 case OPTION_MOLD_GCC:
10611 old_gcc = 1;
10612 break;
10613
10614 case OPTION_MSSE2AVX:
10615 sse2avx = 1;
10616 break;
10617
10618 case OPTION_MSSE_CHECK:
10619 if (strcasecmp (arg, "error") == 0)
10620 sse_check = check_error;
10621 else if (strcasecmp (arg, "warning") == 0)
10622 sse_check = check_warning;
10623 else if (strcasecmp (arg, "none") == 0)
10624 sse_check = check_none;
10625 else
10626 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10627 break;
10628
10629 case OPTION_MOPERAND_CHECK:
10630 if (strcasecmp (arg, "error") == 0)
10631 operand_check = check_error;
10632 else if (strcasecmp (arg, "warning") == 0)
10633 operand_check = check_warning;
10634 else if (strcasecmp (arg, "none") == 0)
10635 operand_check = check_none;
10636 else
10637 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10638 break;
10639
10640 case OPTION_MAVXSCALAR:
10641 if (strcasecmp (arg, "128") == 0)
10642 avxscalar = vex128;
10643 else if (strcasecmp (arg, "256") == 0)
10644 avxscalar = vex256;
10645 else
10646 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10647 break;
10648
10649 case OPTION_MADD_BND_PREFIX:
10650 add_bnd_prefix = 1;
10651 break;
10652
10653 case OPTION_MEVEXLIG:
10654 if (strcmp (arg, "128") == 0)
10655 evexlig = evexl128;
10656 else if (strcmp (arg, "256") == 0)
10657 evexlig = evexl256;
10658 else if (strcmp (arg, "512") == 0)
10659 evexlig = evexl512;
10660 else
10661 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10662 break;
10663
10664 case OPTION_MEVEXRCIG:
10665 if (strcmp (arg, "rne") == 0)
10666 evexrcig = rne;
10667 else if (strcmp (arg, "rd") == 0)
10668 evexrcig = rd;
10669 else if (strcmp (arg, "ru") == 0)
10670 evexrcig = ru;
10671 else if (strcmp (arg, "rz") == 0)
10672 evexrcig = rz;
10673 else
10674 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10675 break;
10676
10677 case OPTION_MEVEXWIG:
10678 if (strcmp (arg, "0") == 0)
10679 evexwig = evexw0;
10680 else if (strcmp (arg, "1") == 0)
10681 evexwig = evexw1;
10682 else
10683 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10684 break;
10685
10686 # if defined (TE_PE) || defined (TE_PEP)
10687 case OPTION_MBIG_OBJ:
10688 use_big_obj = 1;
10689 break;
10690 #endif
10691
10692 case OPTION_MOMIT_LOCK_PREFIX:
10693 if (strcasecmp (arg, "yes") == 0)
10694 omit_lock_prefix = 1;
10695 else if (strcasecmp (arg, "no") == 0)
10696 omit_lock_prefix = 0;
10697 else
10698 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10699 break;
10700
10701 case OPTION_MFENCE_AS_LOCK_ADD:
10702 if (strcasecmp (arg, "yes") == 0)
10703 avoid_fence = 1;
10704 else if (strcasecmp (arg, "no") == 0)
10705 avoid_fence = 0;
10706 else
10707 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10708 break;
10709
10710 case OPTION_MRELAX_RELOCATIONS:
10711 if (strcasecmp (arg, "yes") == 0)
10712 generate_relax_relocations = 1;
10713 else if (strcasecmp (arg, "no") == 0)
10714 generate_relax_relocations = 0;
10715 else
10716 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10717 break;
10718
10719 case OPTION_MAMD64:
10720 intel64 = 0;
10721 break;
10722
10723 case OPTION_MINTEL64:
10724 intel64 = 1;
10725 break;
10726
10727 case 'O':
10728 if (arg == NULL)
10729 {
10730 optimize = 1;
10731 /* Turn off -Os. */
10732 optimize_for_space = 0;
10733 }
10734 else if (*arg == 's')
10735 {
10736 optimize_for_space = 1;
10737 /* Turn on all encoding optimizations. */
10738 optimize = -1;
10739 }
10740 else
10741 {
10742 optimize = atoi (arg);
10743 /* Turn off -Os. */
10744 optimize_for_space = 0;
10745 }
10746 break;
10747
10748 default:
10749 return 0;
10750 }
10751 return 1;
10752 }
10753
10754 #define MESSAGE_TEMPLATE \
10755 " "
10756
10757 static char *
10758 output_message (FILE *stream, char *p, char *message, char *start,
10759 int *left_p, const char *name, int len)
10760 {
10761 int size = sizeof (MESSAGE_TEMPLATE);
10762 int left = *left_p;
10763
10764 /* Reserve 2 spaces for ", " or ",\0" */
10765 left -= len + 2;
10766
10767 /* Check if there is any room. */
10768 if (left >= 0)
10769 {
10770 if (p != start)
10771 {
10772 *p++ = ',';
10773 *p++ = ' ';
10774 }
10775 p = mempcpy (p, name, len);
10776 }
10777 else
10778 {
10779 /* Output the current message now and start a new one. */
10780 *p++ = ',';
10781 *p = '\0';
10782 fprintf (stream, "%s\n", message);
10783 p = start;
10784 left = size - (start - message) - len - 2;
10785
10786 gas_assert (left >= 0);
10787
10788 p = mempcpy (p, name, len);
10789 }
10790
10791 *left_p = left;
10792 return p;
10793 }
10794
10795 static void
10796 show_arch (FILE *stream, int ext, int check)
10797 {
10798 static char message[] = MESSAGE_TEMPLATE;
10799 char *start = message + 27;
10800 char *p;
10801 int size = sizeof (MESSAGE_TEMPLATE);
10802 int left;
10803 const char *name;
10804 int len;
10805 unsigned int j;
10806
10807 p = start;
10808 left = size - (start - message);
10809 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10810 {
10811 /* Should it be skipped? */
10812 if (cpu_arch [j].skip)
10813 continue;
10814
10815 name = cpu_arch [j].name;
10816 len = cpu_arch [j].len;
10817 if (*name == '.')
10818 {
10819 /* It is an extension. Skip if we aren't asked to show it. */
10820 if (ext)
10821 {
10822 name++;
10823 len--;
10824 }
10825 else
10826 continue;
10827 }
10828 else if (ext)
10829 {
10830 /* It is an processor. Skip if we show only extension. */
10831 continue;
10832 }
10833 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10834 {
10835 /* It is an impossible processor - skip. */
10836 continue;
10837 }
10838
10839 p = output_message (stream, p, message, start, &left, name, len);
10840 }
10841
10842 /* Display disabled extensions. */
10843 if (ext)
10844 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10845 {
10846 name = cpu_noarch [j].name;
10847 len = cpu_noarch [j].len;
10848 p = output_message (stream, p, message, start, &left, name,
10849 len);
10850 }
10851
10852 *p = '\0';
10853 fprintf (stream, "%s\n", message);
10854 }
10855
10856 void
10857 md_show_usage (FILE *stream)
10858 {
10859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10860 fprintf (stream, _("\
10861 -Q ignored\n\
10862 -V print assembler version number\n\
10863 -k ignored\n"));
10864 #endif
10865 fprintf (stream, _("\
10866 -n Do not optimize code alignment\n\
10867 -q quieten some warnings\n"));
10868 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10869 fprintf (stream, _("\
10870 -s ignored\n"));
10871 #endif
10872 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10873 || defined (TE_PE) || defined (TE_PEP))
10874 fprintf (stream, _("\
10875 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10876 #endif
10877 #ifdef SVR4_COMMENT_CHARS
10878 fprintf (stream, _("\
10879 --divide do not treat `/' as a comment character\n"));
10880 #else
10881 fprintf (stream, _("\
10882 --divide ignored\n"));
10883 #endif
10884 fprintf (stream, _("\
10885 -march=CPU[,+EXTENSION...]\n\
10886 generate code for CPU and EXTENSION, CPU is one of:\n"));
10887 show_arch (stream, 0, 1);
10888 fprintf (stream, _("\
10889 EXTENSION is combination of:\n"));
10890 show_arch (stream, 1, 0);
10891 fprintf (stream, _("\
10892 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10893 show_arch (stream, 0, 0);
10894 fprintf (stream, _("\
10895 -msse2avx encode SSE instructions with VEX prefix\n"));
10896 fprintf (stream, _("\
10897 -msse-check=[none|error|warning]\n\
10898 check SSE instructions\n"));
10899 fprintf (stream, _("\
10900 -moperand-check=[none|error|warning]\n\
10901 check operand combinations for validity\n"));
10902 fprintf (stream, _("\
10903 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10904 length\n"));
10905 fprintf (stream, _("\
10906 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10907 length\n"));
10908 fprintf (stream, _("\
10909 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10910 for EVEX.W bit ignored instructions\n"));
10911 fprintf (stream, _("\
10912 -mevexrcig=[rne|rd|ru|rz]\n\
10913 encode EVEX instructions with specific EVEX.RC value\n\
10914 for SAE-only ignored instructions\n"));
10915 fprintf (stream, _("\
10916 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10917 fprintf (stream, _("\
10918 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10919 fprintf (stream, _("\
10920 -mindex-reg support pseudo index registers\n"));
10921 fprintf (stream, _("\
10922 -mnaked-reg don't require `%%' prefix for registers\n"));
10923 fprintf (stream, _("\
10924 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10925 fprintf (stream, _("\
10926 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10927 fprintf (stream, _("\
10928 -mshared disable branch optimization for shared code\n"));
10929 # if defined (TE_PE) || defined (TE_PEP)
10930 fprintf (stream, _("\
10931 -mbig-obj generate big object files\n"));
10932 #endif
10933 fprintf (stream, _("\
10934 -momit-lock-prefix=[no|yes]\n\
10935 strip all lock prefixes\n"));
10936 fprintf (stream, _("\
10937 -mfence-as-lock-add=[no|yes]\n\
10938 encode lfence, mfence and sfence as\n\
10939 lock addl $0x0, (%%{re}sp)\n"));
10940 fprintf (stream, _("\
10941 -mrelax-relocations=[no|yes]\n\
10942 generate relax relocations\n"));
10943 fprintf (stream, _("\
10944 -mamd64 accept only AMD64 ISA\n"));
10945 fprintf (stream, _("\
10946 -mintel64 accept only Intel64 ISA\n"));
10947 }
10948
10949 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10950 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10951 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10952
10953 /* Pick the target format to use. */
10954
10955 const char *
10956 i386_target_format (void)
10957 {
10958 if (!strncmp (default_arch, "x86_64", 6))
10959 {
10960 update_code_flag (CODE_64BIT, 1);
10961 if (default_arch[6] == '\0')
10962 x86_elf_abi = X86_64_ABI;
10963 else
10964 x86_elf_abi = X86_64_X32_ABI;
10965 }
10966 else if (!strcmp (default_arch, "i386"))
10967 update_code_flag (CODE_32BIT, 1);
10968 else if (!strcmp (default_arch, "iamcu"))
10969 {
10970 update_code_flag (CODE_32BIT, 1);
10971 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10972 {
10973 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10974 cpu_arch_name = "iamcu";
10975 cpu_sub_arch_name = NULL;
10976 cpu_arch_flags = iamcu_flags;
10977 cpu_arch_isa = PROCESSOR_IAMCU;
10978 cpu_arch_isa_flags = iamcu_flags;
10979 if (!cpu_arch_tune_set)
10980 {
10981 cpu_arch_tune = cpu_arch_isa;
10982 cpu_arch_tune_flags = cpu_arch_isa_flags;
10983 }
10984 }
10985 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10986 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10987 cpu_arch_name);
10988 }
10989 else
10990 as_fatal (_("unknown architecture"));
10991
10992 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10993 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10994 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10995 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10996
10997 switch (OUTPUT_FLAVOR)
10998 {
10999 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11000 case bfd_target_aout_flavour:
11001 return AOUT_TARGET_FORMAT;
11002 #endif
11003 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11004 # if defined (TE_PE) || defined (TE_PEP)
11005 case bfd_target_coff_flavour:
11006 if (flag_code == CODE_64BIT)
11007 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11008 else
11009 return "pe-i386";
11010 # elif defined (TE_GO32)
11011 case bfd_target_coff_flavour:
11012 return "coff-go32";
11013 # else
11014 case bfd_target_coff_flavour:
11015 return "coff-i386";
11016 # endif
11017 #endif
11018 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11019 case bfd_target_elf_flavour:
11020 {
11021 const char *format;
11022
11023 switch (x86_elf_abi)
11024 {
11025 default:
11026 format = ELF_TARGET_FORMAT;
11027 break;
11028 case X86_64_ABI:
11029 use_rela_relocations = 1;
11030 object_64bit = 1;
11031 format = ELF_TARGET_FORMAT64;
11032 break;
11033 case X86_64_X32_ABI:
11034 use_rela_relocations = 1;
11035 object_64bit = 1;
11036 disallow_64bit_reloc = 1;
11037 format = ELF_TARGET_FORMAT32;
11038 break;
11039 }
11040 if (cpu_arch_isa == PROCESSOR_L1OM)
11041 {
11042 if (x86_elf_abi != X86_64_ABI)
11043 as_fatal (_("Intel L1OM is 64bit only"));
11044 return ELF_TARGET_L1OM_FORMAT;
11045 }
11046 else if (cpu_arch_isa == PROCESSOR_K1OM)
11047 {
11048 if (x86_elf_abi != X86_64_ABI)
11049 as_fatal (_("Intel K1OM is 64bit only"));
11050 return ELF_TARGET_K1OM_FORMAT;
11051 }
11052 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11053 {
11054 if (x86_elf_abi != I386_ABI)
11055 as_fatal (_("Intel MCU is 32bit only"));
11056 return ELF_TARGET_IAMCU_FORMAT;
11057 }
11058 else
11059 return format;
11060 }
11061 #endif
11062 #if defined (OBJ_MACH_O)
11063 case bfd_target_mach_o_flavour:
11064 if (flag_code == CODE_64BIT)
11065 {
11066 use_rela_relocations = 1;
11067 object_64bit = 1;
11068 return "mach-o-x86-64";
11069 }
11070 else
11071 return "mach-o-i386";
11072 #endif
11073 default:
11074 abort ();
11075 return NULL;
11076 }
11077 }
11078
11079 #endif /* OBJ_MAYBE_ more than one */
11080 \f
11081 symbolS *
11082 md_undefined_symbol (char *name)
11083 {
11084 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11085 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11086 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11087 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11088 {
11089 if (!GOT_symbol)
11090 {
11091 if (symbol_find (name))
11092 as_bad (_("GOT already in symbol table"));
11093 GOT_symbol = symbol_new (name, undefined_section,
11094 (valueT) 0, &zero_address_frag);
11095 };
11096 return GOT_symbol;
11097 }
11098 return 0;
11099 }
11100
11101 /* Round up a section size to the appropriate boundary. */
11102
11103 valueT
11104 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11105 {
11106 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11107 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11108 {
11109 /* For a.out, force the section size to be aligned. If we don't do
11110 this, BFD will align it for us, but it will not write out the
11111 final bytes of the section. This may be a bug in BFD, but it is
11112 easier to fix it here since that is how the other a.out targets
11113 work. */
11114 int align;
11115
11116 align = bfd_get_section_alignment (stdoutput, segment);
11117 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11118 }
11119 #endif
11120
11121 return size;
11122 }
11123
11124 /* On the i386, PC-relative offsets are relative to the start of the
11125 next instruction. That is, the address of the offset, plus its
11126 size, since the offset is always the last part of the insn. */
11127
11128 long
11129 md_pcrel_from (fixS *fixP)
11130 {
11131 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11132 }
11133
11134 #ifndef I386COFF
11135
11136 static void
11137 s_bss (int ignore ATTRIBUTE_UNUSED)
11138 {
11139 int temp;
11140
11141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11142 if (IS_ELF)
11143 obj_elf_section_change_hook ();
11144 #endif
11145 temp = get_absolute_expression ();
11146 subseg_set (bss_section, (subsegT) temp);
11147 demand_empty_rest_of_line ();
11148 }
11149
11150 #endif
11151
11152 void
11153 i386_validate_fix (fixS *fixp)
11154 {
11155 if (fixp->fx_subsy)
11156 {
11157 if (fixp->fx_subsy == GOT_symbol)
11158 {
11159 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11160 {
11161 if (!object_64bit)
11162 abort ();
11163 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11164 if (fixp->fx_tcbit2)
11165 fixp->fx_r_type = (fixp->fx_tcbit
11166 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11167 : BFD_RELOC_X86_64_GOTPCRELX);
11168 else
11169 #endif
11170 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11171 }
11172 else
11173 {
11174 if (!object_64bit)
11175 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11176 else
11177 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11178 }
11179 fixp->fx_subsy = 0;
11180 }
11181 }
11182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11183 else if (!object_64bit)
11184 {
11185 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11186 && fixp->fx_tcbit2)
11187 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11188 }
11189 #endif
11190 }
11191
11192 arelent *
11193 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11194 {
11195 arelent *rel;
11196 bfd_reloc_code_real_type code;
11197
11198 switch (fixp->fx_r_type)
11199 {
11200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11201 case BFD_RELOC_SIZE32:
11202 case BFD_RELOC_SIZE64:
11203 if (S_IS_DEFINED (fixp->fx_addsy)
11204 && !S_IS_EXTERNAL (fixp->fx_addsy))
11205 {
11206 /* Resolve size relocation against local symbol to size of
11207 the symbol plus addend. */
11208 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11209 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11210 && !fits_in_unsigned_long (value))
11211 as_bad_where (fixp->fx_file, fixp->fx_line,
11212 _("symbol size computation overflow"));
11213 fixp->fx_addsy = NULL;
11214 fixp->fx_subsy = NULL;
11215 md_apply_fix (fixp, (valueT *) &value, NULL);
11216 return NULL;
11217 }
11218 #endif
11219 /* Fall through. */
11220
11221 case BFD_RELOC_X86_64_PLT32:
11222 case BFD_RELOC_X86_64_GOT32:
11223 case BFD_RELOC_X86_64_GOTPCREL:
11224 case BFD_RELOC_X86_64_GOTPCRELX:
11225 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11226 case BFD_RELOC_386_PLT32:
11227 case BFD_RELOC_386_GOT32:
11228 case BFD_RELOC_386_GOT32X:
11229 case BFD_RELOC_386_GOTOFF:
11230 case BFD_RELOC_386_GOTPC:
11231 case BFD_RELOC_386_TLS_GD:
11232 case BFD_RELOC_386_TLS_LDM:
11233 case BFD_RELOC_386_TLS_LDO_32:
11234 case BFD_RELOC_386_TLS_IE_32:
11235 case BFD_RELOC_386_TLS_IE:
11236 case BFD_RELOC_386_TLS_GOTIE:
11237 case BFD_RELOC_386_TLS_LE_32:
11238 case BFD_RELOC_386_TLS_LE:
11239 case BFD_RELOC_386_TLS_GOTDESC:
11240 case BFD_RELOC_386_TLS_DESC_CALL:
11241 case BFD_RELOC_X86_64_TLSGD:
11242 case BFD_RELOC_X86_64_TLSLD:
11243 case BFD_RELOC_X86_64_DTPOFF32:
11244 case BFD_RELOC_X86_64_DTPOFF64:
11245 case BFD_RELOC_X86_64_GOTTPOFF:
11246 case BFD_RELOC_X86_64_TPOFF32:
11247 case BFD_RELOC_X86_64_TPOFF64:
11248 case BFD_RELOC_X86_64_GOTOFF64:
11249 case BFD_RELOC_X86_64_GOTPC32:
11250 case BFD_RELOC_X86_64_GOT64:
11251 case BFD_RELOC_X86_64_GOTPCREL64:
11252 case BFD_RELOC_X86_64_GOTPC64:
11253 case BFD_RELOC_X86_64_GOTPLT64:
11254 case BFD_RELOC_X86_64_PLTOFF64:
11255 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11256 case BFD_RELOC_X86_64_TLSDESC_CALL:
11257 case BFD_RELOC_RVA:
11258 case BFD_RELOC_VTABLE_ENTRY:
11259 case BFD_RELOC_VTABLE_INHERIT:
11260 #ifdef TE_PE
11261 case BFD_RELOC_32_SECREL:
11262 #endif
11263 code = fixp->fx_r_type;
11264 break;
11265 case BFD_RELOC_X86_64_32S:
11266 if (!fixp->fx_pcrel)
11267 {
11268 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11269 code = fixp->fx_r_type;
11270 break;
11271 }
11272 /* Fall through. */
11273 default:
11274 if (fixp->fx_pcrel)
11275 {
11276 switch (fixp->fx_size)
11277 {
11278 default:
11279 as_bad_where (fixp->fx_file, fixp->fx_line,
11280 _("can not do %d byte pc-relative relocation"),
11281 fixp->fx_size);
11282 code = BFD_RELOC_32_PCREL;
11283 break;
11284 case 1: code = BFD_RELOC_8_PCREL; break;
11285 case 2: code = BFD_RELOC_16_PCREL; break;
11286 case 4: code = BFD_RELOC_32_PCREL; break;
11287 #ifdef BFD64
11288 case 8: code = BFD_RELOC_64_PCREL; break;
11289 #endif
11290 }
11291 }
11292 else
11293 {
11294 switch (fixp->fx_size)
11295 {
11296 default:
11297 as_bad_where (fixp->fx_file, fixp->fx_line,
11298 _("can not do %d byte relocation"),
11299 fixp->fx_size);
11300 code = BFD_RELOC_32;
11301 break;
11302 case 1: code = BFD_RELOC_8; break;
11303 case 2: code = BFD_RELOC_16; break;
11304 case 4: code = BFD_RELOC_32; break;
11305 #ifdef BFD64
11306 case 8: code = BFD_RELOC_64; break;
11307 #endif
11308 }
11309 }
11310 break;
11311 }
11312
11313 if ((code == BFD_RELOC_32
11314 || code == BFD_RELOC_32_PCREL
11315 || code == BFD_RELOC_X86_64_32S)
11316 && GOT_symbol
11317 && fixp->fx_addsy == GOT_symbol)
11318 {
11319 if (!object_64bit)
11320 code = BFD_RELOC_386_GOTPC;
11321 else
11322 code = BFD_RELOC_X86_64_GOTPC32;
11323 }
11324 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11325 && GOT_symbol
11326 && fixp->fx_addsy == GOT_symbol)
11327 {
11328 code = BFD_RELOC_X86_64_GOTPC64;
11329 }
11330
11331 rel = XNEW (arelent);
11332 rel->sym_ptr_ptr = XNEW (asymbol *);
11333 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11334
11335 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11336
11337 if (!use_rela_relocations)
11338 {
11339 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11340 vtable entry to be used in the relocation's section offset. */
11341 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11342 rel->address = fixp->fx_offset;
11343 #if defined (OBJ_COFF) && defined (TE_PE)
11344 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11345 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11346 else
11347 #endif
11348 rel->addend = 0;
11349 }
11350 /* Use the rela in 64bit mode. */
11351 else
11352 {
11353 if (disallow_64bit_reloc)
11354 switch (code)
11355 {
11356 case BFD_RELOC_X86_64_DTPOFF64:
11357 case BFD_RELOC_X86_64_TPOFF64:
11358 case BFD_RELOC_64_PCREL:
11359 case BFD_RELOC_X86_64_GOTOFF64:
11360 case BFD_RELOC_X86_64_GOT64:
11361 case BFD_RELOC_X86_64_GOTPCREL64:
11362 case BFD_RELOC_X86_64_GOTPC64:
11363 case BFD_RELOC_X86_64_GOTPLT64:
11364 case BFD_RELOC_X86_64_PLTOFF64:
11365 as_bad_where (fixp->fx_file, fixp->fx_line,
11366 _("cannot represent relocation type %s in x32 mode"),
11367 bfd_get_reloc_code_name (code));
11368 break;
11369 default:
11370 break;
11371 }
11372
11373 if (!fixp->fx_pcrel)
11374 rel->addend = fixp->fx_offset;
11375 else
11376 switch (code)
11377 {
11378 case BFD_RELOC_X86_64_PLT32:
11379 case BFD_RELOC_X86_64_GOT32:
11380 case BFD_RELOC_X86_64_GOTPCREL:
11381 case BFD_RELOC_X86_64_GOTPCRELX:
11382 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11383 case BFD_RELOC_X86_64_TLSGD:
11384 case BFD_RELOC_X86_64_TLSLD:
11385 case BFD_RELOC_X86_64_GOTTPOFF:
11386 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11387 case BFD_RELOC_X86_64_TLSDESC_CALL:
11388 rel->addend = fixp->fx_offset - fixp->fx_size;
11389 break;
11390 default:
11391 rel->addend = (section->vma
11392 - fixp->fx_size
11393 + fixp->fx_addnumber
11394 + md_pcrel_from (fixp));
11395 break;
11396 }
11397 }
11398
11399 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11400 if (rel->howto == NULL)
11401 {
11402 as_bad_where (fixp->fx_file, fixp->fx_line,
11403 _("cannot represent relocation type %s"),
11404 bfd_get_reloc_code_name (code));
11405 /* Set howto to a garbage value so that we can keep going. */
11406 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11407 gas_assert (rel->howto != NULL);
11408 }
11409
11410 return rel;
11411 }
11412
11413 #include "tc-i386-intel.c"
11414
11415 void
11416 tc_x86_parse_to_dw2regnum (expressionS *exp)
11417 {
11418 int saved_naked_reg;
11419 char saved_register_dot;
11420
11421 saved_naked_reg = allow_naked_reg;
11422 allow_naked_reg = 1;
11423 saved_register_dot = register_chars['.'];
11424 register_chars['.'] = '.';
11425 allow_pseudo_reg = 1;
11426 expression_and_evaluate (exp);
11427 allow_pseudo_reg = 0;
11428 register_chars['.'] = saved_register_dot;
11429 allow_naked_reg = saved_naked_reg;
11430
11431 if (exp->X_op == O_register && exp->X_add_number >= 0)
11432 {
11433 if ((addressT) exp->X_add_number < i386_regtab_size)
11434 {
11435 exp->X_op = O_constant;
11436 exp->X_add_number = i386_regtab[exp->X_add_number]
11437 .dw2_regnum[flag_code >> 1];
11438 }
11439 else
11440 exp->X_op = O_illegal;
11441 }
11442 }
11443
11444 void
11445 tc_x86_frame_initial_instructions (void)
11446 {
11447 static unsigned int sp_regno[2];
11448
11449 if (!sp_regno[flag_code >> 1])
11450 {
11451 char *saved_input = input_line_pointer;
11452 char sp[][4] = {"esp", "rsp"};
11453 expressionS exp;
11454
11455 input_line_pointer = sp[flag_code >> 1];
11456 tc_x86_parse_to_dw2regnum (&exp);
11457 gas_assert (exp.X_op == O_constant);
11458 sp_regno[flag_code >> 1] = exp.X_add_number;
11459 input_line_pointer = saved_input;
11460 }
11461
11462 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11463 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11464 }
11465
11466 int
11467 x86_dwarf2_addr_size (void)
11468 {
11469 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11470 if (x86_elf_abi == X86_64_X32_ABI)
11471 return 4;
11472 #endif
11473 return bfd_arch_bits_per_address (stdoutput) / 8;
11474 }
11475
11476 int
11477 i386_elf_section_type (const char *str, size_t len)
11478 {
11479 if (flag_code == CODE_64BIT
11480 && len == sizeof ("unwind") - 1
11481 && strncmp (str, "unwind", 6) == 0)
11482 return SHT_X86_64_UNWIND;
11483
11484 return -1;
11485 }
11486
11487 #ifdef TE_SOLARIS
11488 void
11489 i386_solaris_fix_up_eh_frame (segT sec)
11490 {
11491 if (flag_code == CODE_64BIT)
11492 elf_section_type (sec) = SHT_X86_64_UNWIND;
11493 }
11494 #endif
11495
11496 #ifdef TE_PE
11497 void
11498 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11499 {
11500 expressionS exp;
11501
11502 exp.X_op = O_secrel;
11503 exp.X_add_symbol = symbol;
11504 exp.X_add_number = 0;
11505 emit_expr (&exp, size);
11506 }
11507 #endif
11508
11509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11510 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11511
11512 bfd_vma
11513 x86_64_section_letter (int letter, const char **ptr_msg)
11514 {
11515 if (flag_code == CODE_64BIT)
11516 {
11517 if (letter == 'l')
11518 return SHF_X86_64_LARGE;
11519
11520 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11521 }
11522 else
11523 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11524 return -1;
11525 }
11526
11527 bfd_vma
11528 x86_64_section_word (char *str, size_t len)
11529 {
11530 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11531 return SHF_X86_64_LARGE;
11532
11533 return -1;
11534 }
11535
11536 static void
11537 handle_large_common (int small ATTRIBUTE_UNUSED)
11538 {
11539 if (flag_code != CODE_64BIT)
11540 {
11541 s_comm_internal (0, elf_common_parse);
11542 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11543 }
11544 else
11545 {
11546 static segT lbss_section;
11547 asection *saved_com_section_ptr = elf_com_section_ptr;
11548 asection *saved_bss_section = bss_section;
11549
11550 if (lbss_section == NULL)
11551 {
11552 flagword applicable;
11553 segT seg = now_seg;
11554 subsegT subseg = now_subseg;
11555
11556 /* The .lbss section is for local .largecomm symbols. */
11557 lbss_section = subseg_new (".lbss", 0);
11558 applicable = bfd_applicable_section_flags (stdoutput);
11559 bfd_set_section_flags (stdoutput, lbss_section,
11560 applicable & SEC_ALLOC);
11561 seg_info (lbss_section)->bss = 1;
11562
11563 subseg_set (seg, subseg);
11564 }
11565
11566 elf_com_section_ptr = &_bfd_elf_large_com_section;
11567 bss_section = lbss_section;
11568
11569 s_comm_internal (0, elf_common_parse);
11570
11571 elf_com_section_ptr = saved_com_section_ptr;
11572 bss_section = saved_bss_section;
11573 }
11574 }
11575 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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