1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static void signed_cons
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void swap_imm_operands
PARAMS ((void));
93 static void optimize_imm
PARAMS ((void));
94 static void optimize_disp
PARAMS ((void));
95 static int match_template
PARAMS ((void));
96 static int check_string
PARAMS ((void));
97 static int process_suffix
PARAMS ((void));
98 static int check_byte_reg
PARAMS ((void));
99 static int check_long_reg
PARAMS ((void));
100 static int check_qword_reg
PARAMS ((void));
101 static int check_word_reg
PARAMS ((void));
102 static int finalize_imm
PARAMS ((void));
103 static int process_operands
PARAMS ((void));
104 static const seg_entry
*build_modrm_byte
PARAMS ((void));
105 static void output_insn
PARAMS ((void));
106 static void output_branch
PARAMS ((void));
107 static void output_jump
PARAMS ((void));
108 static void output_interseg_jump
PARAMS ((void));
109 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
111 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
112 offsetT insn_start_off
));
114 static void s_bss
PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
120 static const char *default_arch
= DEFAULT_ARCH
;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry
*regs
;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands
;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types
[MAX_OPERANDS
];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op
[MAX_OPERANDS
];
157 /* Flags for operands. */
158 unsigned int flags
[MAX_OPERANDS
];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry
*base_reg
;
167 const reg_entry
*index_reg
;
168 unsigned int log2_scale_factor
;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry
*seg
[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes
;
177 unsigned char prefix
[MAX_PREFIXES
];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn
;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars
[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars
= "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars
= "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars
[] = "#/";
229 const char line_separator_chars
[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS
[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS
[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars
[256];
242 static char register_chars
[256];
243 static char operand_chars
[256];
244 static char identifier_chars
[256];
245 static char digit_chars
[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack
[32];
263 static char *save_stack_p
;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates
*current_templates
;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions
[2], im_expressions
[2];
278 /* Current operand we are working on. */
279 static int this_operand
;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code
;
291 static unsigned int object_64bit
;
292 static int use_rela_relocations
= 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names
[] =
302 /* 1 for intel syntax,
304 static int intel_syntax
= 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg
= 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size
= '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code
= 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings
= 0;
321 static const char *cpu_arch_name
= NULL
;
322 static const char *cpu_sub_arch_name
= NULL
;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
327 /* If we have selected a cpu we are generating instructions for. */
328 static int cpu_arch_tune_set
= 0;
330 /* Cpu we are generating instructions for. */
331 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
333 /* CPU feature flags of cpu we are generating instructions for. */
334 static unsigned int cpu_arch_tune_flags
= 0;
336 /* CPU instruction set architecture used. */
337 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
339 /* CPU feature flags of instruction set architecture used. */
340 static unsigned int cpu_arch_isa_flags
= 0;
342 /* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344 static unsigned int no_cond_jump_promotion
= 0;
346 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
347 static symbolS
*GOT_symbol
;
349 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
350 unsigned int x86_dwarf2_return_column
;
352 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353 int x86_cie_data_alignment
;
355 /* Interface to relax_segment.
356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
361 #define UNCOND_JUMP 0
363 #define COND_JUMP86 2
368 #define SMALL16 (SMALL | CODE16)
370 #define BIG16 (BIG | CODE16)
374 #define INLINE __inline__
380 #define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382 #define TYPE_FROM_RELAX_STATE(s) \
384 #define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
387 /* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
395 const relax_typeS md_relax_table
[] =
398 1) most positive reach of this state,
399 2) most negative reach of this state,
400 3) how many bytes this mode will have in the variable part of the frag
401 4) which index into the table to try if we can't fit into this one. */
403 /* UNCOND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 3 bytes to frag:
420 1 extra opcode byte, 2 displacement bytes. */
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
434 static const arch_entry cpu_arch
[] =
436 {"generic32", PROCESSOR_GENERIC32
,
437 Cpu186
|Cpu286
|Cpu386
},
438 {"generic64", PROCESSOR_GENERIC64
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
440 |CpuMMX2
|CpuSSE
|CpuSSE2
},
441 {"i8086", PROCESSOR_UNKNOWN
,
443 {"i186", PROCESSOR_UNKNOWN
,
445 {"i286", PROCESSOR_UNKNOWN
,
447 {"i386", PROCESSOR_GENERIC32
,
448 Cpu186
|Cpu286
|Cpu386
},
449 {"i486", PROCESSOR_I486
,
450 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
451 {"i586", PROCESSOR_PENTIUM
,
452 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
453 {"i686", PROCESSOR_PENTIUMPRO
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
455 {"pentium", PROCESSOR_PENTIUM
,
456 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
458 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
459 {"pentiumii", PROCESSOR_PENTIUMPRO
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
462 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
463 {"pentium4", PROCESSOR_PENTIUM4
,
464 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
465 |CpuMMX2
|CpuSSE
|CpuSSE2
},
466 {"prescott", PROCESSOR_NOCONA
,
467 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
468 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
469 {"nocona", PROCESSOR_NOCONA
,
470 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
471 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
472 {"yonah", PROCESSOR_YONAH
,
473 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
474 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
475 {"merom", PROCESSOR_MEROM
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
477 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuMNI
},
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
480 {"k6_2", PROCESSOR_K6
,
481 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
482 {"athlon", PROCESSOR_ATHLON
,
483 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
484 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
485 {"sledgehammer", PROCESSOR_K8
,
486 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
487 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
488 {"opteron", PROCESSOR_K8
,
489 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
490 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
492 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
493 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
494 {"amdfam10", PROCESSOR_AMDFAM10
,
495 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
496 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
498 {".mmx", PROCESSOR_UNKNOWN
,
500 {".sse", PROCESSOR_UNKNOWN
,
501 CpuMMX
|CpuMMX2
|CpuSSE
},
502 {".sse2", PROCESSOR_UNKNOWN
,
503 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
504 {".sse3", PROCESSOR_UNKNOWN
,
505 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
506 {".3dnow", PROCESSOR_UNKNOWN
,
508 {".3dnowa", PROCESSOR_UNKNOWN
,
509 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
510 {".padlock", PROCESSOR_UNKNOWN
,
512 {".pacifica", PROCESSOR_UNKNOWN
,
514 {".svme", PROCESSOR_UNKNOWN
,
516 {".sse4a", PROCESSOR_UNKNOWN
,
517 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
518 {".abm", PROCESSOR_UNKNOWN
,
522 const pseudo_typeS md_pseudo_table
[] =
524 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
525 {"align", s_align_bytes
, 0},
527 {"align", s_align_ptwo
, 0},
529 {"arch", set_cpu_arch
, 0},
533 {"ffloat", float_cons
, 'f'},
534 {"dfloat", float_cons
, 'd'},
535 {"tfloat", float_cons
, 'x'},
537 {"slong", signed_cons
, 4},
538 {"noopt", s_ignore
, 0},
539 {"optim", s_ignore
, 0},
540 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
541 {"code16", set_code_flag
, CODE_16BIT
},
542 {"code32", set_code_flag
, CODE_32BIT
},
543 {"code64", set_code_flag
, CODE_64BIT
},
544 {"intel_syntax", set_intel_syntax
, 1},
545 {"att_syntax", set_intel_syntax
, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common
, 0},
549 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
550 {"loc", dwarf2_directive_loc
, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
554 {"secrel32", pe_directive_secrel
, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer
;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control
*op_hash
;
565 /* Hash table for register lookup. */
566 static struct hash_control
*reg_hash
;
569 i386_align_code (fragP
, count
)
573 /* Various efficient no-op patterns for aligning code labels.
574 Note: Don't try to assemble the instructions in the comments.
575 0L and 0w are not legal. */
576 static const char f32_1
[] =
578 static const char f32_2
[] =
579 {0x66,0x90}; /* xchg %ax,%ax */
580 static const char f32_3
[] =
581 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
582 static const char f32_4
[] =
583 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
584 static const char f32_5
[] =
586 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
587 static const char f32_6
[] =
588 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
589 static const char f32_7
[] =
590 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
591 static const char f32_8
[] =
593 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
594 static const char f32_9
[] =
595 {0x89,0xf6, /* movl %esi,%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_10
[] =
598 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_11
[] =
601 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_12
[] =
604 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
605 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
606 static const char f32_13
[] =
607 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_14
[] =
610 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_15
[] =
613 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
614 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
615 static const char f16_3
[] =
616 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
617 static const char f16_4
[] =
618 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
619 static const char f16_5
[] =
621 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
622 static const char f16_6
[] =
623 {0x89,0xf6, /* mov %si,%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char f16_7
[] =
626 {0x8d,0x74,0x00, /* lea 0(%si),%si */
627 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
628 static const char f16_8
[] =
629 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
630 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
631 static const char *const f32_patt
[] = {
632 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
633 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
635 static const char *const f16_patt
[] = {
636 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
637 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
640 static const char alt_3
[] =
642 /* nopl 0(%[re]ax) */
643 static const char alt_4
[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5
[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6
[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7
[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8
[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9
[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10
[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11
[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12
[] =
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13
[] =
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14
[] =
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15
[] =
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11
[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12
[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
720 static const char alt_short_13
[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
725 static const char alt_short_14
[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15
[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt
[] = {
734 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
735 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
736 alt_short_14
, alt_short_15
738 static const char *const alt_long_patt
[] = {
739 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
740 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
741 alt_long_14
, alt_long_15
744 if (count
<= 0 || count
> 15)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
751 f32_patt will be used.
752 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
753 3. For PROCESSOR_MEROM, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
764 if (flag_code
== CODE_16BIT
)
766 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
767 f16_patt
[count
- 1], count
);
769 /* Adjust jump offset. */
770 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
772 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
775 int nnops
= (count
+ 3) / 4;
776 int len
= count
/ nnops
;
777 int remains
= count
- nnops
* len
;
780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
782 for (i
= 0; i
< remains
; i
++)
784 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
785 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
788 for (; i
< nnops
; i
++)
790 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
791 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
797 const char *const *patt
= NULL
;
799 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune
)
804 case PROCESSOR_UNKNOWN
:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
808 patt
= alt_short_patt
;
812 case PROCESSOR_MEROM
:
813 patt
= alt_long_patt
;
815 case PROCESSOR_PENTIUMPRO
:
816 case PROCESSOR_PENTIUM4
:
817 case PROCESSOR_NOCONA
:
818 case PROCESSOR_YONAH
:
820 case PROCESSOR_ATHLON
:
822 case PROCESSOR_GENERIC64
:
823 case PROCESSOR_AMDFAM10
:
824 patt
= alt_short_patt
;
827 case PROCESSOR_PENTIUM
:
828 case PROCESSOR_GENERIC32
:
835 switch (cpu_arch_tune
)
837 case PROCESSOR_UNKNOWN
:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
844 case PROCESSOR_PENTIUM
:
845 case PROCESSOR_PENTIUMPRO
:
846 case PROCESSOR_PENTIUM4
:
847 case PROCESSOR_NOCONA
:
848 case PROCESSOR_YONAH
:
850 case PROCESSOR_ATHLON
:
852 case PROCESSOR_AMDFAM10
:
853 case PROCESSOR_GENERIC32
:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
856 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
857 patt
= alt_short_patt
;
861 case PROCESSOR_MEROM
:
862 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
863 patt
= alt_long_patt
;
867 case PROCESSOR_GENERIC64
:
868 patt
= alt_short_patt
;
873 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
874 patt
[count
- 1], count
);
876 fragP
->fr_var
= count
;
879 static INLINE
unsigned int
880 mode_from_disp_size (t
)
883 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
887 fits_in_signed_byte (num
)
890 return (num
>= -128) && (num
<= 127);
894 fits_in_unsigned_byte (num
)
897 return (num
& 0xff) == num
;
901 fits_in_unsigned_word (num
)
904 return (num
& 0xffff) == num
;
908 fits_in_signed_word (num
)
911 return (-32768 <= num
) && (num
<= 32767);
914 fits_in_signed_long (num
)
915 offsetT num ATTRIBUTE_UNUSED
;
920 return (!(((offsetT
) -1 << 31) & num
)
921 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
923 } /* fits_in_signed_long() */
925 fits_in_unsigned_long (num
)
926 offsetT num ATTRIBUTE_UNUSED
;
931 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
933 } /* fits_in_unsigned_long() */
936 smallest_imm_type (num
)
939 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
941 /* This code is disabled on the 486 because all the Imm1 forms
942 in the opcode table are slower on the i486. They're the
943 versions with the implicitly specified single-position
944 displacement, which has another syntax if you really want to
947 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
949 return (fits_in_signed_byte (num
)
950 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
951 : fits_in_unsigned_byte (num
)
952 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
953 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
954 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
955 : fits_in_signed_long (num
)
956 ? (Imm32
| Imm32S
| Imm64
)
957 : fits_in_unsigned_long (num
)
963 offset_in_range (val
, size
)
971 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
972 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
973 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
975 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
980 /* If BFD64, sign extend val. */
981 if (!use_rela_relocations
)
982 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
983 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
985 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
987 char buf1
[40], buf2
[40];
989 sprint_value (buf1
, val
);
990 sprint_value (buf2
, val
& mask
);
991 as_warn (_("%s shortened to %s"), buf1
, buf2
);
996 /* Returns 0 if attempting to add a prefix where one from the same
997 class already exists, 1 if non rep/repne added, 2 if rep/repne
1001 unsigned int prefix
;
1006 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1007 && flag_code
== CODE_64BIT
)
1009 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
1010 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
1011 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
1022 case CS_PREFIX_OPCODE
:
1023 case DS_PREFIX_OPCODE
:
1024 case ES_PREFIX_OPCODE
:
1025 case FS_PREFIX_OPCODE
:
1026 case GS_PREFIX_OPCODE
:
1027 case SS_PREFIX_OPCODE
:
1031 case REPNE_PREFIX_OPCODE
:
1032 case REPE_PREFIX_OPCODE
:
1035 case LOCK_PREFIX_OPCODE
:
1043 case ADDR_PREFIX_OPCODE
:
1047 case DATA_PREFIX_OPCODE
:
1051 if (i
.prefix
[q
] != 0)
1059 i
.prefix
[q
] |= prefix
;
1062 as_bad (_("same type of prefix used twice"));
1068 set_code_flag (value
)
1072 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1073 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1074 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1076 as_bad (_("64bit mode not supported on this CPU."));
1078 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1080 as_bad (_("32bit mode not supported on this CPU."));
1082 stackop_size
= '\0';
1086 set_16bit_gcc_code_flag (new_code_flag
)
1089 flag_code
= new_code_flag
;
1090 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1091 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1092 stackop_size
= LONG_MNEM_SUFFIX
;
1096 set_intel_syntax (syntax_flag
)
1099 /* Find out if register prefixing is specified. */
1100 int ask_naked_reg
= 0;
1103 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1105 char *string
= input_line_pointer
;
1106 int e
= get_symbol_end ();
1108 if (strcmp (string
, "prefix") == 0)
1110 else if (strcmp (string
, "noprefix") == 0)
1113 as_bad (_("bad argument to syntax directive."));
1114 *input_line_pointer
= e
;
1116 demand_empty_rest_of_line ();
1118 intel_syntax
= syntax_flag
;
1120 if (ask_naked_reg
== 0)
1121 allow_naked_reg
= (intel_syntax
1122 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1124 allow_naked_reg
= (ask_naked_reg
< 0);
1126 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1127 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1131 set_cpu_arch (dummy
)
1132 int dummy ATTRIBUTE_UNUSED
;
1136 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1138 char *string
= input_line_pointer
;
1139 int e
= get_symbol_end ();
1142 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1144 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1148 cpu_arch_name
= cpu_arch
[i
].name
;
1149 cpu_sub_arch_name
= NULL
;
1150 cpu_arch_flags
= (cpu_arch
[i
].flags
1151 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
1152 cpu_arch_isa
= cpu_arch
[i
].type
;
1153 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1154 if (!cpu_arch_tune_set
)
1156 cpu_arch_tune
= cpu_arch_isa
;
1157 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1161 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1163 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1164 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1166 *input_line_pointer
= e
;
1167 demand_empty_rest_of_line ();
1171 if (i
>= ARRAY_SIZE (cpu_arch
))
1172 as_bad (_("no such architecture: `%s'"), string
);
1174 *input_line_pointer
= e
;
1177 as_bad (_("missing cpu architecture"));
1179 no_cond_jump_promotion
= 0;
1180 if (*input_line_pointer
== ','
1181 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1183 char *string
= ++input_line_pointer
;
1184 int e
= get_symbol_end ();
1186 if (strcmp (string
, "nojumps") == 0)
1187 no_cond_jump_promotion
= 1;
1188 else if (strcmp (string
, "jumps") == 0)
1191 as_bad (_("no such architecture modifier: `%s'"), string
);
1193 *input_line_pointer
= e
;
1196 demand_empty_rest_of_line ();
1202 if (!strcmp (default_arch
, "x86_64"))
1203 return bfd_mach_x86_64
;
1204 else if (!strcmp (default_arch
, "i386"))
1205 return bfd_mach_i386_i386
;
1207 as_fatal (_("Unknown architecture"));
1213 const char *hash_err
;
1215 /* Initialize op_hash hash table. */
1216 op_hash
= hash_new ();
1219 const template *optab
;
1220 templates
*core_optab
;
1222 /* Setup for loop. */
1224 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1225 core_optab
->start
= optab
;
1230 if (optab
->name
== NULL
1231 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1233 /* different name --> ship out current template list;
1234 add to hash table; & begin anew. */
1235 core_optab
->end
= optab
;
1236 hash_err
= hash_insert (op_hash
,
1241 as_fatal (_("Internal Error: Can't hash %s: %s"),
1245 if (optab
->name
== NULL
)
1247 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1248 core_optab
->start
= optab
;
1253 /* Initialize reg_hash hash table. */
1254 reg_hash
= hash_new ();
1256 const reg_entry
*regtab
;
1258 for (regtab
= i386_regtab
;
1259 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
1262 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1264 as_fatal (_("Internal Error: Can't hash %s: %s"),
1270 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1275 for (c
= 0; c
< 256; c
++)
1280 mnemonic_chars
[c
] = c
;
1281 register_chars
[c
] = c
;
1282 operand_chars
[c
] = c
;
1284 else if (ISLOWER (c
))
1286 mnemonic_chars
[c
] = c
;
1287 register_chars
[c
] = c
;
1288 operand_chars
[c
] = c
;
1290 else if (ISUPPER (c
))
1292 mnemonic_chars
[c
] = TOLOWER (c
);
1293 register_chars
[c
] = mnemonic_chars
[c
];
1294 operand_chars
[c
] = c
;
1297 if (ISALPHA (c
) || ISDIGIT (c
))
1298 identifier_chars
[c
] = c
;
1301 identifier_chars
[c
] = c
;
1302 operand_chars
[c
] = c
;
1307 identifier_chars
['@'] = '@';
1310 identifier_chars
['?'] = '?';
1311 operand_chars
['?'] = '?';
1313 digit_chars
['-'] = '-';
1314 mnemonic_chars
['-'] = '-';
1315 identifier_chars
['_'] = '_';
1316 identifier_chars
['.'] = '.';
1318 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1319 operand_chars
[(unsigned char) *p
] = *p
;
1322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1325 record_alignment (text_section
, 2);
1326 record_alignment (data_section
, 2);
1327 record_alignment (bss_section
, 2);
1331 if (flag_code
== CODE_64BIT
)
1333 x86_dwarf2_return_column
= 16;
1334 x86_cie_data_alignment
= -8;
1338 x86_dwarf2_return_column
= 8;
1339 x86_cie_data_alignment
= -4;
1344 i386_print_statistics (file
)
1347 hash_print_statistics (file
, "i386 opcode", op_hash
);
1348 hash_print_statistics (file
, "i386 register", reg_hash
);
1353 /* Debugging routines for md_assemble. */
1354 static void pi
PARAMS ((char *, i386_insn
*));
1355 static void pte
PARAMS ((template *));
1356 static void pt
PARAMS ((unsigned int));
1357 static void pe
PARAMS ((expressionS
*));
1358 static void ps
PARAMS ((symbolS
*));
1367 fprintf (stdout
, "%s: template ", line
);
1369 fprintf (stdout
, " address: base %s index %s scale %x\n",
1370 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1371 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1372 x
->log2_scale_factor
);
1373 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1374 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1375 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1376 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1377 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1378 (x
->rex
& REX_MODE64
) != 0,
1379 (x
->rex
& REX_EXTX
) != 0,
1380 (x
->rex
& REX_EXTY
) != 0,
1381 (x
->rex
& REX_EXTZ
) != 0);
1382 for (i
= 0; i
< x
->operands
; i
++)
1384 fprintf (stdout
, " #%d: ", i
+ 1);
1386 fprintf (stdout
, "\n");
1388 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1389 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1390 if (x
->types
[i
] & Imm
)
1392 if (x
->types
[i
] & Disp
)
1393 pe (x
->op
[i
].disps
);
1402 fprintf (stdout
, " %d operands ", t
->operands
);
1403 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1404 if (t
->extension_opcode
!= None
)
1405 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1406 if (t
->opcode_modifier
& D
)
1407 fprintf (stdout
, "D");
1408 if (t
->opcode_modifier
& W
)
1409 fprintf (stdout
, "W");
1410 fprintf (stdout
, "\n");
1411 for (i
= 0; i
< t
->operands
; i
++)
1413 fprintf (stdout
, " #%d type ", i
+ 1);
1414 pt (t
->operand_types
[i
]);
1415 fprintf (stdout
, "\n");
1423 fprintf (stdout
, " operation %d\n", e
->X_op
);
1424 fprintf (stdout
, " add_number %ld (%lx)\n",
1425 (long) e
->X_add_number
, (long) e
->X_add_number
);
1426 if (e
->X_add_symbol
)
1428 fprintf (stdout
, " add_symbol ");
1429 ps (e
->X_add_symbol
);
1430 fprintf (stdout
, "\n");
1434 fprintf (stdout
, " op_symbol ");
1435 ps (e
->X_op_symbol
);
1436 fprintf (stdout
, "\n");
1444 fprintf (stdout
, "%s type %s%s",
1446 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1447 segment_name (S_GET_SEGMENT (s
)));
1450 static struct type_name
1455 const type_names
[] =
1468 { BaseIndex
, "BaseIndex" },
1472 { Disp32S
, "d32s" },
1474 { InOutPortReg
, "InOutPortReg" },
1475 { ShiftCount
, "ShiftCount" },
1476 { Control
, "control reg" },
1477 { Test
, "test reg" },
1478 { Debug
, "debug reg" },
1479 { FloatReg
, "FReg" },
1480 { FloatAcc
, "FAcc" },
1484 { JumpAbsolute
, "Jump Absolute" },
1495 const struct type_name
*ty
;
1497 for (ty
= type_names
; ty
->mask
; ty
++)
1499 fprintf (stdout
, "%s, ", ty
->tname
);
1503 #endif /* DEBUG386 */
1505 static bfd_reloc_code_real_type
1506 reloc (unsigned int size
,
1509 bfd_reloc_code_real_type other
)
1511 if (other
!= NO_RELOC
)
1513 reloc_howto_type
*reloc
;
1518 case BFD_RELOC_X86_64_GOT32
:
1519 return BFD_RELOC_X86_64_GOT64
;
1521 case BFD_RELOC_X86_64_PLTOFF64
:
1522 return BFD_RELOC_X86_64_PLTOFF64
;
1524 case BFD_RELOC_X86_64_GOTPC32
:
1525 other
= BFD_RELOC_X86_64_GOTPC64
;
1527 case BFD_RELOC_X86_64_GOTPCREL
:
1528 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1530 case BFD_RELOC_X86_64_TPOFF32
:
1531 other
= BFD_RELOC_X86_64_TPOFF64
;
1533 case BFD_RELOC_X86_64_DTPOFF32
:
1534 other
= BFD_RELOC_X86_64_DTPOFF64
;
1540 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1541 if (size
== 4 && flag_code
!= CODE_64BIT
)
1544 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1546 as_bad (_("unknown relocation (%u)"), other
);
1547 else if (size
!= bfd_get_reloc_size (reloc
))
1548 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1549 bfd_get_reloc_size (reloc
),
1551 else if (pcrel
&& !reloc
->pc_relative
)
1552 as_bad (_("non-pc-relative relocation for pc-relative field"));
1553 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1555 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1557 as_bad (_("relocated field and relocation type differ in signedness"));
1566 as_bad (_("there are no unsigned pc-relative relocations"));
1569 case 1: return BFD_RELOC_8_PCREL
;
1570 case 2: return BFD_RELOC_16_PCREL
;
1571 case 4: return BFD_RELOC_32_PCREL
;
1572 case 8: return BFD_RELOC_64_PCREL
;
1574 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1581 case 4: return BFD_RELOC_X86_64_32S
;
1586 case 1: return BFD_RELOC_8
;
1587 case 2: return BFD_RELOC_16
;
1588 case 4: return BFD_RELOC_32
;
1589 case 8: return BFD_RELOC_64
;
1591 as_bad (_("cannot do %s %u byte relocation"),
1592 sign
> 0 ? "signed" : "unsigned", size
);
1596 return BFD_RELOC_NONE
;
1599 /* Here we decide which fixups can be adjusted to make them relative to
1600 the beginning of the section instead of the symbol. Basically we need
1601 to make sure that the dynamic relocations are done correctly, so in
1602 some cases we force the original symbol to be used. */
1605 tc_i386_fix_adjustable (fixP
)
1606 fixS
*fixP ATTRIBUTE_UNUSED
;
1608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1612 /* Don't adjust pc-relative references to merge sections in 64-bit
1614 if (use_rela_relocations
1615 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1619 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1620 and changed later by validate_fix. */
1621 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1622 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1625 /* adjust_reloc_syms doesn't know about the GOT. */
1626 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1627 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1628 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1629 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1630 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1631 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1632 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1633 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1634 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1635 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1636 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1637 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1638 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1639 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1640 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1641 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1642 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1643 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1644 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1645 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1646 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1647 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1648 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1649 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1650 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1651 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1652 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1653 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1659 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1662 intel_float_operand (mnemonic
)
1663 const char *mnemonic
;
1665 /* Note that the value returned is meaningful only for opcodes with (memory)
1666 operands, hence the code here is free to improperly handle opcodes that
1667 have no operands (for better performance and smaller code). */
1669 if (mnemonic
[0] != 'f')
1670 return 0; /* non-math */
1672 switch (mnemonic
[1])
1674 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1675 the fs segment override prefix not currently handled because no
1676 call path can make opcodes without operands get here */
1678 return 2 /* integer op */;
1680 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1681 return 3; /* fldcw/fldenv */
1684 if (mnemonic
[2] != 'o' /* fnop */)
1685 return 3; /* non-waiting control op */
1688 if (mnemonic
[2] == 's')
1689 return 3; /* frstor/frstpm */
1692 if (mnemonic
[2] == 'a')
1693 return 3; /* fsave */
1694 if (mnemonic
[2] == 't')
1696 switch (mnemonic
[3])
1698 case 'c': /* fstcw */
1699 case 'd': /* fstdw */
1700 case 'e': /* fstenv */
1701 case 's': /* fsts[gw] */
1707 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1708 return 0; /* fxsave/fxrstor are not really math ops */
1715 /* This is the guts of the machine-dependent assembler. LINE points to a
1716 machine dependent instruction. This function is supposed to emit
1717 the frags/bytes it assembles to. */
1724 char mnemonic
[MAX_MNEM_SIZE
];
1726 /* Initialize globals. */
1727 memset (&i
, '\0', sizeof (i
));
1728 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1729 i
.reloc
[j
] = NO_RELOC
;
1730 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1731 memset (im_expressions
, '\0', sizeof (im_expressions
));
1732 save_stack_p
= save_stack
;
1734 /* First parse an instruction mnemonic & call i386_operand for the operands.
1735 We assume that the scrubber has arranged it so that line[0] is the valid
1736 start of a (possibly prefixed) mnemonic. */
1738 line
= parse_insn (line
, mnemonic
);
1742 line
= parse_operands (line
, mnemonic
);
1746 /* The order of the immediates should be reversed
1747 for 2 immediates extrq and insertq instructions */
1748 if ((i
.imm_operands
== 2) &&
1749 ((strcmp (mnemonic
, "extrq") == 0)
1750 || (strcmp (mnemonic
, "insertq") == 0)))
1752 swap_imm_operands ();
1753 /* "extrq" and insertq" are the only two instructions whose operands
1754 have to be reversed even though they have two immediate operands.
1760 /* Now we've parsed the mnemonic into a set of templates, and have the
1761 operands at hand. */
1763 /* All intel opcodes have reversed operands except for "bound" and
1764 "enter". We also don't reverse intersegment "jmp" and "call"
1765 instructions with 2 immediate operands so that the immediate segment
1766 precedes the offset, as it does when in AT&T mode. */
1767 if (intel_syntax
&& i
.operands
> 1
1768 && (strcmp (mnemonic
, "bound") != 0)
1769 && (strcmp (mnemonic
, "invlpga") != 0)
1770 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1776 /* Don't optimize displacement for movabs since it only takes 64bit
1779 && (flag_code
!= CODE_64BIT
1780 || strcmp (mnemonic
, "movabs") != 0))
1783 /* Next, we find a template that matches the given insn,
1784 making sure the overlap of the given operands types is consistent
1785 with the template operand types. */
1787 if (!match_template ())
1792 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1794 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1795 i
.tm
.base_opcode
^= FloatR
;
1797 /* Zap movzx and movsx suffix. The suffix may have been set from
1798 "word ptr" or "byte ptr" on the source operand, but we'll use
1799 the suffix later to choose the destination register. */
1800 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1802 if (i
.reg_operands
< 2
1804 && (~i
.tm
.opcode_modifier
1811 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1817 if (i
.tm
.opcode_modifier
& FWait
)
1818 if (!add_prefix (FWAIT_OPCODE
))
1821 /* Check string instruction segment overrides. */
1822 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1824 if (!check_string ())
1828 if (!process_suffix ())
1831 /* Make still unresolved immediate matches conform to size of immediate
1832 given in i.suffix. */
1833 if (!finalize_imm ())
1836 if (i
.types
[0] & Imm1
)
1837 i
.imm_operands
= 0; /* kludge for shift insns. */
1838 if (i
.types
[0] & ImplicitRegister
)
1840 if (i
.types
[1] & ImplicitRegister
)
1842 if (i
.types
[2] & ImplicitRegister
)
1845 if (i
.tm
.opcode_modifier
& ImmExt
)
1849 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1851 /* These Intel Prescott New Instructions have the fixed
1852 operands with an opcode suffix which is coded in the same
1853 place as an 8-bit immediate field would be. Here we check
1854 those operands and remove them afterwards. */
1857 for (x
= 0; x
< i
.operands
; x
++)
1858 if (i
.op
[x
].regs
->reg_num
!= x
)
1859 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1860 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1864 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1865 opcode suffix which is coded in the same place as an 8-bit
1866 immediate field would be. Here we fake an 8-bit immediate
1867 operand from the opcode suffix stored in tm.extension_opcode. */
1869 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1871 exp
= &im_expressions
[i
.imm_operands
++];
1872 i
.op
[i
.operands
].imms
= exp
;
1873 i
.types
[i
.operands
++] = Imm8
;
1874 exp
->X_op
= O_constant
;
1875 exp
->X_add_number
= i
.tm
.extension_opcode
;
1876 i
.tm
.extension_opcode
= None
;
1879 /* For insns with operands there are more diddles to do to the opcode. */
1882 if (!process_operands ())
1885 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1887 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1888 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1891 /* Handle conversion of 'int $3' --> special int3 insn. */
1892 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1894 i
.tm
.base_opcode
= INT3_OPCODE
;
1898 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1899 && i
.op
[0].disps
->X_op
== O_constant
)
1901 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1902 the absolute address given by the constant. Since ix86 jumps and
1903 calls are pc relative, we need to generate a reloc. */
1904 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1905 i
.op
[0].disps
->X_op
= O_symbol
;
1908 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1909 i
.rex
|= REX_MODE64
;
1911 /* For 8 bit registers we need an empty rex prefix. Also if the
1912 instruction already has a prefix, we need to convert old
1913 registers to new ones. */
1915 if (((i
.types
[0] & Reg8
) != 0
1916 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1917 || ((i
.types
[1] & Reg8
) != 0
1918 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1919 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1924 i
.rex
|= REX_OPCODE
;
1925 for (x
= 0; x
< 2; x
++)
1927 /* Look for 8 bit operand that uses old registers. */
1928 if ((i
.types
[x
] & Reg8
) != 0
1929 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1931 /* In case it is "hi" register, give up. */
1932 if (i
.op
[x
].regs
->reg_num
> 3)
1933 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1934 i
.op
[x
].regs
->reg_name
);
1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1940 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1946 add_prefix (REX_OPCODE
| i
.rex
);
1948 /* We are ready to output the insn. */
1953 parse_insn (line
, mnemonic
)
1958 char *token_start
= l
;
1963 /* Non-zero if we found a prefix only acceptable with string insns. */
1964 const char *expecting_string_instruction
= NULL
;
1969 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1972 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1974 as_bad (_("no such instruction: `%s'"), token_start
);
1979 if (!is_space_char (*l
)
1980 && *l
!= END_OF_INSN
1982 || (*l
!= PREFIX_SEPARATOR
1985 as_bad (_("invalid character %s in mnemonic"),
1986 output_invalid (*l
));
1989 if (token_start
== l
)
1991 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1992 as_bad (_("expecting prefix; got nothing"));
1994 as_bad (_("expecting mnemonic; got nothing"));
1998 /* Look up instruction (or prefix) via hash table. */
1999 current_templates
= hash_find (op_hash
, mnemonic
);
2001 if (*l
!= END_OF_INSN
2002 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2003 && current_templates
2004 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
2006 if (current_templates
->start
->cpu_flags
2007 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
2009 as_bad ((flag_code
!= CODE_64BIT
2010 ? _("`%s' is only supported in 64-bit mode")
2011 : _("`%s' is not supported in 64-bit mode")),
2012 current_templates
->start
->name
);
2015 /* If we are in 16-bit mode, do not allow addr16 or data16.
2016 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2017 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
2018 && flag_code
!= CODE_64BIT
2019 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
2020 ^ (flag_code
== CODE_16BIT
)))
2022 as_bad (_("redundant %s prefix"),
2023 current_templates
->start
->name
);
2026 /* Add prefix, checking for repeated prefixes. */
2027 switch (add_prefix (current_templates
->start
->base_opcode
))
2032 expecting_string_instruction
= current_templates
->start
->name
;
2035 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2042 if (!current_templates
)
2044 /* See if we can get a match by trimming off a suffix. */
2047 case WORD_MNEM_SUFFIX
:
2048 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2049 i
.suffix
= SHORT_MNEM_SUFFIX
;
2051 case BYTE_MNEM_SUFFIX
:
2052 case QWORD_MNEM_SUFFIX
:
2053 i
.suffix
= mnem_p
[-1];
2055 current_templates
= hash_find (op_hash
, mnemonic
);
2057 case SHORT_MNEM_SUFFIX
:
2058 case LONG_MNEM_SUFFIX
:
2061 i
.suffix
= mnem_p
[-1];
2063 current_templates
= hash_find (op_hash
, mnemonic
);
2071 if (intel_float_operand (mnemonic
) == 1)
2072 i
.suffix
= SHORT_MNEM_SUFFIX
;
2074 i
.suffix
= LONG_MNEM_SUFFIX
;
2076 current_templates
= hash_find (op_hash
, mnemonic
);
2080 if (!current_templates
)
2082 as_bad (_("no such instruction: `%s'"), token_start
);
2087 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2089 /* Check for a branch hint. We allow ",pt" and ",pn" for
2090 predict taken and predict not taken respectively.
2091 I'm not sure that branch hints actually do anything on loop
2092 and jcxz insns (JumpByte) for current Pentium4 chips. They
2093 may work in the future and it doesn't hurt to accept them
2095 if (l
[0] == ',' && l
[1] == 'p')
2099 if (!add_prefix (DS_PREFIX_OPCODE
))
2103 else if (l
[2] == 'n')
2105 if (!add_prefix (CS_PREFIX_OPCODE
))
2111 /* Any other comma loses. */
2114 as_bad (_("invalid character %s in mnemonic"),
2115 output_invalid (*l
));
2119 /* Check if instruction is supported on specified architecture. */
2121 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2123 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2124 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2126 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2129 if (!(supported
& 2))
2131 as_bad (flag_code
== CODE_64BIT
2132 ? _("`%s' is not supported in 64-bit mode")
2133 : _("`%s' is only supported in 64-bit mode"),
2134 current_templates
->start
->name
);
2137 if (!(supported
& 1))
2139 as_warn (_("`%s' is not supported on `%s%s'"),
2140 current_templates
->start
->name
,
2142 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2144 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2146 as_warn (_("use .code16 to ensure correct addressing mode"));
2149 /* Check for rep/repne without a string instruction. */
2150 if (expecting_string_instruction
)
2152 static templates override
;
2154 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2155 if (t
->opcode_modifier
& IsString
)
2157 if (t
>= current_templates
->end
)
2159 as_bad (_("expecting string instruction after `%s'"),
2160 expecting_string_instruction
);
2163 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2164 if (!(t
->opcode_modifier
& IsString
))
2167 current_templates
= &override
;
2174 parse_operands (l
, mnemonic
)
2176 const char *mnemonic
;
2180 /* 1 if operand is pending after ','. */
2181 unsigned int expecting_operand
= 0;
2183 /* Non-zero if operand parens not balanced. */
2184 unsigned int paren_not_balanced
;
2186 while (*l
!= END_OF_INSN
)
2188 /* Skip optional white space before operand. */
2189 if (is_space_char (*l
))
2191 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2193 as_bad (_("invalid character %s before operand %d"),
2194 output_invalid (*l
),
2198 token_start
= l
; /* after white space */
2199 paren_not_balanced
= 0;
2200 while (paren_not_balanced
|| *l
!= ',')
2202 if (*l
== END_OF_INSN
)
2204 if (paren_not_balanced
)
2207 as_bad (_("unbalanced parenthesis in operand %d."),
2210 as_bad (_("unbalanced brackets in operand %d."),
2215 break; /* we are done */
2217 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2219 as_bad (_("invalid character %s in operand %d"),
2220 output_invalid (*l
),
2227 ++paren_not_balanced
;
2229 --paren_not_balanced
;
2234 ++paren_not_balanced
;
2236 --paren_not_balanced
;
2240 if (l
!= token_start
)
2241 { /* Yes, we've read in another operand. */
2242 unsigned int operand_ok
;
2243 this_operand
= i
.operands
++;
2244 if (i
.operands
> MAX_OPERANDS
)
2246 as_bad (_("spurious operands; (%d operands/instruction max)"),
2250 /* Now parse operand adding info to 'i' as we go along. */
2251 END_STRING_AND_SAVE (l
);
2255 i386_intel_operand (token_start
,
2256 intel_float_operand (mnemonic
));
2258 operand_ok
= i386_operand (token_start
);
2260 RESTORE_END_STRING (l
);
2266 if (expecting_operand
)
2268 expecting_operand_after_comma
:
2269 as_bad (_("expecting operand after ','; got nothing"));
2274 as_bad (_("expecting operand before ','; got nothing"));
2279 /* Now *l must be either ',' or END_OF_INSN. */
2282 if (*++l
== END_OF_INSN
)
2284 /* Just skip it, if it's \n complain. */
2285 goto expecting_operand_after_comma
;
2287 expecting_operand
= 1;
2294 swap_imm_operands ()
2296 union i386_op temp_op
;
2297 unsigned int temp_type
;
2298 enum bfd_reloc_code_real temp_reloc
;
2302 temp_type
= i
.types
[xchg2
];
2303 i
.types
[xchg2
] = i
.types
[xchg1
];
2304 i
.types
[xchg1
] = temp_type
;
2305 temp_op
= i
.op
[xchg2
];
2306 i
.op
[xchg2
] = i
.op
[xchg1
];
2307 i
.op
[xchg1
] = temp_op
;
2308 temp_reloc
= i
.reloc
[xchg2
];
2309 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2310 i
.reloc
[xchg1
] = temp_reloc
;
2317 union i386_op temp_op
;
2318 unsigned int temp_type
;
2319 enum bfd_reloc_code_real temp_reloc
;
2323 if (i
.operands
== 4)
2324 /* There will be two exchanges in a 4 operand instruction.
2325 First exchange is the done inside this block.(1st and 4rth operand)
2326 The next exchange is done outside this block.(2nd and 3rd operand) */
2330 temp_type
= i
.types
[xchg2
];
2331 i
.types
[xchg2
] = i
.types
[xchg1
];
2332 i
.types
[xchg1
] = temp_type
;
2333 temp_op
= i
.op
[xchg2
];
2334 i
.op
[xchg2
] = i
.op
[xchg1
];
2335 i
.op
[xchg1
] = temp_op
;
2336 temp_reloc
= i
.reloc
[xchg2
];
2337 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2338 i
.reloc
[xchg1
] = temp_reloc
;
2343 if (i
.operands
== 2)
2348 else if (i
.operands
== 3)
2353 temp_type
= i
.types
[xchg2
];
2354 i
.types
[xchg2
] = i
.types
[xchg1
];
2355 i
.types
[xchg1
] = temp_type
;
2356 temp_op
= i
.op
[xchg2
];
2357 i
.op
[xchg2
] = i
.op
[xchg1
];
2358 i
.op
[xchg1
] = temp_op
;
2359 temp_reloc
= i
.reloc
[xchg2
];
2360 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2361 i
.reloc
[xchg1
] = temp_reloc
;
2363 if (i
.mem_operands
== 2)
2365 const seg_entry
*temp_seg
;
2366 temp_seg
= i
.seg
[0];
2367 i
.seg
[0] = i
.seg
[1];
2368 i
.seg
[1] = temp_seg
;
2372 /* Try to ensure constant immediates are represented in the smallest
2377 char guess_suffix
= 0;
2381 guess_suffix
= i
.suffix
;
2382 else if (i
.reg_operands
)
2384 /* Figure out a suffix from the last register operand specified.
2385 We can't do this properly yet, ie. excluding InOutPortReg,
2386 but the following works for instructions with immediates.
2387 In any case, we can't set i.suffix yet. */
2388 for (op
= i
.operands
; --op
>= 0;)
2389 if (i
.types
[op
] & Reg
)
2391 if (i
.types
[op
] & Reg8
)
2392 guess_suffix
= BYTE_MNEM_SUFFIX
;
2393 else if (i
.types
[op
] & Reg16
)
2394 guess_suffix
= WORD_MNEM_SUFFIX
;
2395 else if (i
.types
[op
] & Reg32
)
2396 guess_suffix
= LONG_MNEM_SUFFIX
;
2397 else if (i
.types
[op
] & Reg64
)
2398 guess_suffix
= QWORD_MNEM_SUFFIX
;
2402 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2403 guess_suffix
= WORD_MNEM_SUFFIX
;
2405 for (op
= i
.operands
; --op
>= 0;)
2406 if (i
.types
[op
] & Imm
)
2408 switch (i
.op
[op
].imms
->X_op
)
2411 /* If a suffix is given, this operand may be shortened. */
2412 switch (guess_suffix
)
2414 case LONG_MNEM_SUFFIX
:
2415 i
.types
[op
] |= Imm32
| Imm64
;
2417 case WORD_MNEM_SUFFIX
:
2418 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2420 case BYTE_MNEM_SUFFIX
:
2421 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2425 /* If this operand is at most 16 bits, convert it
2426 to a signed 16 bit number before trying to see
2427 whether it will fit in an even smaller size.
2428 This allows a 16-bit operand such as $0xffe0 to
2429 be recognised as within Imm8S range. */
2430 if ((i
.types
[op
] & Imm16
)
2431 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2433 i
.op
[op
].imms
->X_add_number
=
2434 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2436 if ((i
.types
[op
] & Imm32
)
2437 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2440 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2441 ^ ((offsetT
) 1 << 31))
2442 - ((offsetT
) 1 << 31));
2444 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2446 /* We must avoid matching of Imm32 templates when 64bit
2447 only immediate is available. */
2448 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2449 i
.types
[op
] &= ~Imm32
;
2456 /* Symbols and expressions. */
2458 /* Convert symbolic operand to proper sizes for matching, but don't
2459 prevent matching a set of insns that only supports sizes other
2460 than those matching the insn suffix. */
2462 unsigned int mask
, allowed
= 0;
2465 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2466 allowed
|= t
->operand_types
[op
];
2467 switch (guess_suffix
)
2469 case QWORD_MNEM_SUFFIX
:
2470 mask
= Imm64
| Imm32S
;
2472 case LONG_MNEM_SUFFIX
:
2475 case WORD_MNEM_SUFFIX
:
2478 case BYTE_MNEM_SUFFIX
:
2486 i
.types
[op
] &= mask
;
2493 /* Try to use the smallest displacement type too. */
2499 for (op
= i
.operands
; --op
>= 0;)
2500 if (i
.types
[op
] & Disp
)
2502 if (i
.op
[op
].disps
->X_op
== O_constant
)
2504 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2506 if ((i
.types
[op
] & Disp16
)
2507 && (disp
& ~(offsetT
) 0xffff) == 0)
2509 /* If this operand is at most 16 bits, convert
2510 to a signed 16 bit number and don't use 64bit
2512 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2513 i
.types
[op
] &= ~Disp64
;
2515 if ((i
.types
[op
] & Disp32
)
2516 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2518 /* If this operand is at most 32 bits, convert
2519 to a signed 32 bit number and don't use 64bit
2521 disp
&= (((offsetT
) 2 << 31) - 1);
2522 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2523 i
.types
[op
] &= ~Disp64
;
2525 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2527 i
.types
[op
] &= ~Disp
;
2531 else if (flag_code
== CODE_64BIT
)
2533 if (fits_in_signed_long (disp
))
2535 i
.types
[op
] &= ~Disp64
;
2536 i
.types
[op
] |= Disp32S
;
2538 if (fits_in_unsigned_long (disp
))
2539 i
.types
[op
] |= Disp32
;
2541 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2542 && fits_in_signed_byte (disp
))
2543 i
.types
[op
] |= Disp8
;
2545 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2546 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2548 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2549 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2550 i
.types
[op
] &= ~Disp
;
2553 /* We only support 64bit displacement on constants. */
2554 i
.types
[op
] &= ~Disp64
;
2561 /* Points to template once we've found it. */
2563 unsigned int overlap0
, overlap1
, overlap2
;
2564 unsigned int found_reverse_match
;
2567 #define MATCH(overlap, given, template) \
2568 ((overlap & ~JumpAbsolute) \
2569 && (((given) & (BaseIndex | JumpAbsolute)) \
2570 == ((overlap) & (BaseIndex | JumpAbsolute))))
2572 /* If given types r0 and r1 are registers they must be of the same type
2573 unless the expected operand type register overlap is null.
2574 Note that Acc in a template matches every size of reg. */
2575 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2576 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2577 || ((g0) & Reg) == ((g1) & Reg) \
2578 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2583 found_reverse_match
= 0;
2584 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2586 : (i
.suffix
== WORD_MNEM_SUFFIX
2588 : (i
.suffix
== SHORT_MNEM_SUFFIX
2590 : (i
.suffix
== LONG_MNEM_SUFFIX
2592 : (i
.suffix
== QWORD_MNEM_SUFFIX
2594 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2595 ? No_xSuf
: 0))))));
2597 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2599 /* Must have right number of operands. */
2600 if (i
.operands
!= t
->operands
)
2603 /* Check the suffix, except for some instructions in intel mode. */
2604 if ((t
->opcode_modifier
& suffix_check
)
2606 && (t
->opcode_modifier
& IgnoreSize
)))
2609 /* In general, don't allow 64-bit operands in 32-bit mode. */
2610 if (i
.suffix
== QWORD_MNEM_SUFFIX
2611 && flag_code
!= CODE_64BIT
2613 ? (!(t
->opcode_modifier
& IgnoreSize
)
2614 && !intel_float_operand (t
->name
))
2615 : intel_float_operand (t
->name
) != 2)
2616 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2617 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2618 && (t
->base_opcode
!= 0x0fc7
2619 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2622 /* Do not verify operands when there are none. */
2623 else if (!t
->operands
)
2625 if (t
->cpu_flags
& ~cpu_arch_flags
)
2627 /* We've found a match; break out of loop. */
2631 overlap0
= i
.types
[0] & t
->operand_types
[0];
2632 switch (t
->operands
)
2635 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2640 overlap1
= i
.types
[1] & t
->operand_types
[1];
2641 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2642 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2643 /* monitor in SSE3 is a very special case. The first
2644 register and the second register may have different
2646 || !((t
->base_opcode
== 0x0f01
2647 && t
->extension_opcode
== 0xc8)
2648 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2649 t
->operand_types
[0],
2650 overlap1
, i
.types
[1],
2651 t
->operand_types
[1])))
2653 /* Check if other direction is valid ... */
2654 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2657 /* Try reversing direction of operands. */
2658 overlap0
= i
.types
[0] & t
->operand_types
[1];
2659 overlap1
= i
.types
[1] & t
->operand_types
[0];
2660 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2661 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2662 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2663 t
->operand_types
[1],
2664 overlap1
, i
.types
[1],
2665 t
->operand_types
[0]))
2667 /* Does not match either direction. */
2670 /* found_reverse_match holds which of D or FloatDR
2672 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2674 /* Found a forward 2 operand match here. */
2675 else if (t
->operands
== 3)
2677 /* Here we make use of the fact that there are no
2678 reverse match 3 operand instructions, and all 3
2679 operand instructions only need to be checked for
2680 register consistency between operands 2 and 3. */
2681 overlap2
= i
.types
[2] & t
->operand_types
[2];
2682 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2683 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2684 t
->operand_types
[1],
2685 overlap2
, i
.types
[2],
2686 t
->operand_types
[2]))
2690 /* Found either forward/reverse 2 or 3 operand match here:
2691 slip through to break. */
2693 if (t
->cpu_flags
& ~cpu_arch_flags
)
2695 found_reverse_match
= 0;
2698 /* We've found a match; break out of loop. */
2702 if (t
== current_templates
->end
)
2704 /* We found no match. */
2705 as_bad (_("suffix or operands invalid for `%s'"),
2706 current_templates
->start
->name
);
2710 if (!quiet_warnings
)
2713 && ((i
.types
[0] & JumpAbsolute
)
2714 != (t
->operand_types
[0] & JumpAbsolute
)))
2716 as_warn (_("indirect %s without `*'"), t
->name
);
2719 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2720 == (IsPrefix
| IgnoreSize
))
2722 /* Warn them that a data or address size prefix doesn't
2723 affect assembly of the next line of code. */
2724 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2728 /* Copy the template we found. */
2730 if (found_reverse_match
)
2732 /* If we found a reverse match we must alter the opcode
2733 direction bit. found_reverse_match holds bits to change
2734 (different for int & float insns). */
2736 i
.tm
.base_opcode
^= found_reverse_match
;
2738 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2739 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2748 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2749 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2751 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2753 as_bad (_("`%s' operand %d must use `%%es' segment"),
2758 /* There's only ever one segment override allowed per instruction.
2759 This instruction possibly has a legal segment override on the
2760 second operand, so copy the segment to where non-string
2761 instructions store it, allowing common code. */
2762 i
.seg
[0] = i
.seg
[1];
2764 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2766 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2768 as_bad (_("`%s' operand %d must use `%%es' segment"),
2778 process_suffix (void)
2780 /* If matched instruction specifies an explicit instruction mnemonic
2782 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2784 if (i
.tm
.opcode_modifier
& Size16
)
2785 i
.suffix
= WORD_MNEM_SUFFIX
;
2786 else if (i
.tm
.opcode_modifier
& Size64
)
2787 i
.suffix
= QWORD_MNEM_SUFFIX
;
2789 i
.suffix
= LONG_MNEM_SUFFIX
;
2791 else if (i
.reg_operands
)
2793 /* If there's no instruction mnemonic suffix we try to invent one
2794 based on register operands. */
2797 /* We take i.suffix from the last register operand specified,
2798 Destination register type is more significant than source
2802 for (op
= i
.operands
; --op
>= 0;)
2803 if ((i
.types
[op
] & Reg
)
2804 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2806 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2807 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2808 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2813 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2815 if (!check_byte_reg ())
2818 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2820 if (!check_long_reg ())
2823 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2825 if (!check_qword_reg ())
2828 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2830 if (!check_word_reg ())
2833 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2834 /* Do nothing if the instruction is going to ignore the prefix. */
2839 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2841 /* exclude fldenv/frstor/fsave/fstenv */
2842 && (i
.tm
.opcode_modifier
& No_sSuf
))
2844 i
.suffix
= stackop_size
;
2846 else if (intel_syntax
2848 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2849 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2850 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2851 && i
.tm
.extension_opcode
<= 3)))
2856 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2858 i
.suffix
= QWORD_MNEM_SUFFIX
;
2862 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2863 i
.suffix
= LONG_MNEM_SUFFIX
;
2866 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2867 i
.suffix
= WORD_MNEM_SUFFIX
;
2876 if (i
.tm
.opcode_modifier
& W
)
2878 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2884 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2892 if ((i
.tm
.opcode_modifier
& W
)
2893 || ((suffixes
& (suffixes
- 1))
2894 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2896 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2902 /* Change the opcode based on the operand size given by i.suffix;
2903 We don't need to change things for byte insns. */
2905 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2907 /* It's not a byte, select word/dword operation. */
2908 if (i
.tm
.opcode_modifier
& W
)
2910 if (i
.tm
.opcode_modifier
& ShortForm
)
2911 i
.tm
.base_opcode
|= 8;
2913 i
.tm
.base_opcode
|= 1;
2916 /* Now select between word & dword operations via the operand
2917 size prefix, except for instructions that will ignore this
2919 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2921 /* monitor in SSE3 is a very special case. The default size
2922 of AX is the size of mode. The address size override
2923 prefix will change the size of AX. */
2924 if (i
.op
->regs
[0].reg_type
&
2925 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2926 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2929 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2930 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2931 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2932 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2933 || (flag_code
== CODE_64BIT
2934 && (i
.tm
.opcode_modifier
& JumpByte
))))
2936 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2938 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2939 prefix
= ADDR_PREFIX_OPCODE
;
2941 if (!add_prefix (prefix
))
2945 /* Set mode64 for an operand. */
2946 if (i
.suffix
== QWORD_MNEM_SUFFIX
2947 && flag_code
== CODE_64BIT
2948 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2950 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2953 || i
.types
[0] != (Acc
| Reg64
)
2954 || i
.types
[1] != (Acc
| Reg64
)
2955 || strcmp (i
.tm
.name
, "xchg") != 0)
2956 i
.rex
|= REX_MODE64
;
2959 /* Size floating point instruction. */
2960 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2961 if (i
.tm
.opcode_modifier
& FloatMF
)
2962 i
.tm
.base_opcode
^= 4;
2969 check_byte_reg (void)
2973 for (op
= i
.operands
; --op
>= 0;)
2975 /* If this is an eight bit register, it's OK. If it's the 16 or
2976 32 bit version of an eight bit register, we will just use the
2977 low portion, and that's OK too. */
2978 if (i
.types
[op
] & Reg8
)
2981 /* movzx and movsx should not generate this warning. */
2983 && (i
.tm
.base_opcode
== 0xfb7
2984 || i
.tm
.base_opcode
== 0xfb6
2985 || i
.tm
.base_opcode
== 0x63
2986 || i
.tm
.base_opcode
== 0xfbe
2987 || i
.tm
.base_opcode
== 0xfbf))
2990 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2992 /* Prohibit these changes in the 64bit mode, since the
2993 lowering is more complicated. */
2994 if (flag_code
== CODE_64BIT
2995 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2997 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2998 i
.op
[op
].regs
->reg_name
,
3002 #if REGISTER_WARNINGS
3004 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3005 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3006 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3007 ? REGNAM_AL
- REGNAM_AX
3008 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3009 i
.op
[op
].regs
->reg_name
,
3014 /* Any other register is bad. */
3015 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3017 | Control
| Debug
| Test
3018 | FloatReg
| FloatAcc
))
3020 as_bad (_("`%%%s' not allowed with `%s%c'"),
3021 i
.op
[op
].regs
->reg_name
,
3035 for (op
= i
.operands
; --op
>= 0;)
3036 /* Reject eight bit registers, except where the template requires
3037 them. (eg. movzb) */
3038 if ((i
.types
[op
] & Reg8
) != 0
3039 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3041 as_bad (_("`%%%s' not allowed with `%s%c'"),
3042 i
.op
[op
].regs
->reg_name
,
3047 /* Warn if the e prefix on a general reg is missing. */
3048 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3049 && (i
.types
[op
] & Reg16
) != 0
3050 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3052 /* Prohibit these changes in the 64bit mode, since the
3053 lowering is more complicated. */
3054 if (flag_code
== CODE_64BIT
)
3056 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3057 i
.op
[op
].regs
->reg_name
,
3061 #if REGISTER_WARNINGS
3063 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3064 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3065 i
.op
[op
].regs
->reg_name
,
3069 /* Warn if the r prefix on a general reg is missing. */
3070 else if ((i
.types
[op
] & Reg64
) != 0
3071 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3073 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3074 i
.op
[op
].regs
->reg_name
,
3086 for (op
= i
.operands
; --op
>= 0; )
3087 /* Reject eight bit registers, except where the template requires
3088 them. (eg. movzb) */
3089 if ((i
.types
[op
] & Reg8
) != 0
3090 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3092 as_bad (_("`%%%s' not allowed with `%s%c'"),
3093 i
.op
[op
].regs
->reg_name
,
3098 /* Warn if the e prefix on a general reg is missing. */
3099 else if (((i
.types
[op
] & Reg16
) != 0
3100 || (i
.types
[op
] & Reg32
) != 0)
3101 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3103 /* Prohibit these changes in the 64bit mode, since the
3104 lowering is more complicated. */
3105 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3106 i
.op
[op
].regs
->reg_name
,
3117 for (op
= i
.operands
; --op
>= 0;)
3118 /* Reject eight bit registers, except where the template requires
3119 them. (eg. movzb) */
3120 if ((i
.types
[op
] & Reg8
) != 0
3121 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3123 as_bad (_("`%%%s' not allowed with `%s%c'"),
3124 i
.op
[op
].regs
->reg_name
,
3129 /* Warn if the e prefix on a general reg is present. */
3130 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3131 && (i
.types
[op
] & Reg32
) != 0
3132 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3134 /* Prohibit these changes in the 64bit mode, since the
3135 lowering is more complicated. */
3136 if (flag_code
== CODE_64BIT
)
3138 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3139 i
.op
[op
].regs
->reg_name
,
3144 #if REGISTER_WARNINGS
3145 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3146 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3147 i
.op
[op
].regs
->reg_name
,
3157 unsigned int overlap0
, overlap1
, overlap2
;
3159 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3160 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3161 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3162 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3163 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3167 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3169 : (i
.suffix
== WORD_MNEM_SUFFIX
3171 : (i
.suffix
== QWORD_MNEM_SUFFIX
3175 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3176 || overlap0
== (Imm16
| Imm32
)
3177 || overlap0
== (Imm16
| Imm32S
))
3179 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3182 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3183 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3184 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3186 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3190 i
.types
[0] = overlap0
;
3192 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3193 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3194 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3195 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3196 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3200 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3202 : (i
.suffix
== WORD_MNEM_SUFFIX
3204 : (i
.suffix
== QWORD_MNEM_SUFFIX
3208 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3209 || overlap1
== (Imm16
| Imm32
)
3210 || overlap1
== (Imm16
| Imm32S
))
3212 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3215 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3216 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3217 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3219 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
3223 i
.types
[1] = overlap1
;
3225 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3226 assert ((overlap2
& Imm
) == 0);
3227 i
.types
[2] = overlap2
;
3235 /* Default segment register this instruction will use for memory
3236 accesses. 0 means unknown. This is only for optimizing out
3237 unnecessary segment overrides. */
3238 const seg_entry
*default_seg
= 0;
3240 /* The imul $imm, %reg instruction is converted into
3241 imul $imm, %reg, %reg, and the clr %reg instruction
3242 is converted into xor %reg, %reg. */
3243 if (i
.tm
.opcode_modifier
& regKludge
)
3245 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3246 /* Pretend we saw the extra register operand. */
3247 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
3248 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3249 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3253 if (i
.tm
.opcode_modifier
& ShortForm
)
3255 /* The register or float register operand is in operand 0 or 1. */
3256 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3257 /* Register goes in low 3 bits of opcode. */
3258 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3259 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3261 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3263 /* Warn about some common errors, but press on regardless.
3264 The first case can be generated by gcc (<= 2.8.1). */
3265 if (i
.operands
== 2)
3267 /* Reversed arguments on faddp, fsubp, etc. */
3268 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3269 i
.op
[1].regs
->reg_name
,
3270 i
.op
[0].regs
->reg_name
);
3274 /* Extraneous `l' suffix on fp insn. */
3275 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3276 i
.op
[0].regs
->reg_name
);
3280 else if (i
.tm
.opcode_modifier
& Modrm
)
3282 /* The opcode is completed (modulo i.tm.extension_opcode which
3283 must be put into the modrm byte). Now, we make the modrm and
3284 index base bytes based on all the info we've collected. */
3286 default_seg
= build_modrm_byte ();
3288 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
3290 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3291 && i
.op
[0].regs
->reg_num
== 1)
3293 as_bad (_("you can't `pop %%cs'"));
3296 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3297 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3300 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
3304 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3306 /* For the string instructions that allow a segment override
3307 on one of their operands, the default segment is ds. */
3311 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3312 || (i
.tm
.cpu_flags
& CpuSVME
))
3313 && i
.seg
[0] && !quiet_warnings
)
3314 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3316 /* If a segment was explicitly specified, and the specified segment
3317 is not the default, use an opcode prefix to select it. If we
3318 never figured out what the default segment is, then default_seg
3319 will be zero at this point, and the specified segment prefix will
3321 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3323 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3329 static const seg_entry
*
3332 const seg_entry
*default_seg
= 0;
3334 /* i.reg_operands MUST be the number of real register operands;
3335 implicit registers do not count. */
3336 if (i
.reg_operands
== 2)
3338 unsigned int source
, dest
;
3339 source
= ((i
.types
[0]
3340 & (Reg
| RegMMX
| RegXMM
3342 | Control
| Debug
| Test
))
3345 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3346 bytes and hence source operand will be in the next byte after the immediates */
3347 if ((i
.operands
== 4)&&(i
.imm_operands
=2)) source
++;
3351 /* One of the register operands will be encoded in the i.tm.reg
3352 field, the other in the combined i.tm.mode and i.tm.regmem
3353 fields. If no form of this instruction supports a memory
3354 destination operand, then we assume the source operand may
3355 sometimes be a memory operand and so we need to store the
3356 destination in the i.rm.reg field. */
3357 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3359 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3360 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3361 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3363 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3368 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3369 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3370 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3372 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3375 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3377 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3379 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3380 add_prefix (LOCK_PREFIX_OPCODE
);
3384 { /* If it's not 2 reg operands... */
3387 unsigned int fake_zero_displacement
= 0;
3388 unsigned int op
= ((i
.types
[0] & AnyMem
)
3390 : (i
.types
[1] & AnyMem
) ? 1 : 2);
3394 if (i
.base_reg
== 0)
3397 if (!i
.disp_operands
)
3398 fake_zero_displacement
= 1;
3399 if (i
.index_reg
== 0)
3401 /* Operand is just <disp> */
3402 if (flag_code
== CODE_64BIT
)
3404 /* 64bit mode overwrites the 32bit absolute
3405 addressing by RIP relative addressing and
3406 absolute addressing is encoded by one of the
3407 redundant SIB forms. */
3408 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3409 i
.sib
.base
= NO_BASE_REGISTER
;
3410 i
.sib
.index
= NO_INDEX_REGISTER
;
3411 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3413 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3415 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3416 i
.types
[op
] = Disp16
;
3420 i
.rm
.regmem
= NO_BASE_REGISTER
;
3421 i
.types
[op
] = Disp32
;
3424 else /* !i.base_reg && i.index_reg */
3426 i
.sib
.index
= i
.index_reg
->reg_num
;
3427 i
.sib
.base
= NO_BASE_REGISTER
;
3428 i
.sib
.scale
= i
.log2_scale_factor
;
3429 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3430 i
.types
[op
] &= ~Disp
;
3431 if (flag_code
!= CODE_64BIT
)
3432 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3434 i
.types
[op
] |= Disp32S
;
3435 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3439 /* RIP addressing for 64bit mode. */
3440 else if (i
.base_reg
->reg_type
== BaseIndex
)
3442 i
.rm
.regmem
= NO_BASE_REGISTER
;
3443 i
.types
[op
] &= ~ Disp
;
3444 i
.types
[op
] |= Disp32S
;
3445 i
.flags
[op
] = Operand_PCrel
;
3446 if (! i
.disp_operands
)
3447 fake_zero_displacement
= 1;
3449 else if (i
.base_reg
->reg_type
& Reg16
)
3451 switch (i
.base_reg
->reg_num
)
3454 if (i
.index_reg
== 0)
3456 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3457 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3461 if (i
.index_reg
== 0)
3464 if ((i
.types
[op
] & Disp
) == 0)
3466 /* fake (%bp) into 0(%bp) */
3467 i
.types
[op
] |= Disp8
;
3468 fake_zero_displacement
= 1;
3471 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3472 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3474 default: /* (%si) -> 4 or (%di) -> 5 */
3475 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3477 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3479 else /* i.base_reg and 32/64 bit mode */
3481 if (flag_code
== CODE_64BIT
3482 && (i
.types
[op
] & Disp
))
3483 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3485 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3486 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3488 i
.sib
.base
= i
.base_reg
->reg_num
;
3489 /* x86-64 ignores REX prefix bit here to avoid decoder
3491 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3494 if (i
.disp_operands
== 0)
3496 fake_zero_displacement
= 1;
3497 i
.types
[op
] |= Disp8
;
3500 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3504 i
.sib
.scale
= i
.log2_scale_factor
;
3505 if (i
.index_reg
== 0)
3507 /* <disp>(%esp) becomes two byte modrm with no index
3508 register. We've already stored the code for esp
3509 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3510 Any base register besides %esp will not use the
3511 extra modrm byte. */
3512 i
.sib
.index
= NO_INDEX_REGISTER
;
3513 #if !SCALE1_WHEN_NO_INDEX
3514 /* Another case where we force the second modrm byte. */
3515 if (i
.log2_scale_factor
)
3516 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3521 i
.sib
.index
= i
.index_reg
->reg_num
;
3522 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3523 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3528 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3529 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3532 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3535 if (fake_zero_displacement
)
3537 /* Fakes a zero displacement assuming that i.types[op]
3538 holds the correct displacement size. */
3541 assert (i
.op
[op
].disps
== 0);
3542 exp
= &disp_expressions
[i
.disp_operands
++];
3543 i
.op
[op
].disps
= exp
;
3544 exp
->X_op
= O_constant
;
3545 exp
->X_add_number
= 0;
3546 exp
->X_add_symbol
= (symbolS
*) 0;
3547 exp
->X_op_symbol
= (symbolS
*) 0;
3551 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3552 (if any) based on i.tm.extension_opcode. Again, we must be
3553 careful to make sure that segment/control/debug/test/MMX
3554 registers are coded into the i.rm.reg field. */
3559 & (Reg
| RegMMX
| RegXMM
3561 | Control
| Debug
| Test
))
3564 & (Reg
| RegMMX
| RegXMM
3566 | Control
| Debug
| Test
))
3569 /* If there is an extension opcode to put here, the register
3570 number must be put into the regmem field. */
3571 if (i
.tm
.extension_opcode
!= None
)
3573 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3574 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3579 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3580 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3584 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3585 must set it to 3 to indicate this is a register operand
3586 in the regmem field. */
3587 if (!i
.mem_operands
)
3591 /* Fill in i.rm.reg field with extension opcode (if any). */
3592 if (i
.tm
.extension_opcode
!= None
)
3593 i
.rm
.reg
= i
.tm
.extension_opcode
;
3604 relax_substateT subtype
;
3609 if (flag_code
== CODE_16BIT
)
3613 if (i
.prefix
[DATA_PREFIX
] != 0)
3619 /* Pentium4 branch hints. */
3620 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3621 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3626 if (i
.prefix
[REX_PREFIX
] != 0)
3632 if (i
.prefixes
!= 0 && !intel_syntax
)
3633 as_warn (_("skipping prefixes on this instruction"));
3635 /* It's always a symbol; End frag & setup for relax.
3636 Make sure there is enough room in this frag for the largest
3637 instruction we may generate in md_convert_frag. This is 2
3638 bytes for the opcode and room for the prefix and largest
3640 frag_grow (prefix
+ 2 + 4);
3641 /* Prefix and 1 opcode byte go in fr_fix. */
3642 p
= frag_more (prefix
+ 1);
3643 if (i
.prefix
[DATA_PREFIX
] != 0)
3644 *p
++ = DATA_PREFIX_OPCODE
;
3645 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3646 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3647 *p
++ = i
.prefix
[SEG_PREFIX
];
3648 if (i
.prefix
[REX_PREFIX
] != 0)
3649 *p
++ = i
.prefix
[REX_PREFIX
];
3650 *p
= i
.tm
.base_opcode
;
3652 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3653 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3654 else if ((cpu_arch_flags
& Cpu386
) != 0)
3655 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3657 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3660 sym
= i
.op
[0].disps
->X_add_symbol
;
3661 off
= i
.op
[0].disps
->X_add_number
;
3663 if (i
.op
[0].disps
->X_op
!= O_constant
3664 && i
.op
[0].disps
->X_op
!= O_symbol
)
3666 /* Handle complex expressions. */
3667 sym
= make_expr_symbol (i
.op
[0].disps
);
3671 /* 1 possible extra opcode + 4 byte displacement go in var part.
3672 Pass reloc in fr_var. */
3673 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3683 if (i
.tm
.opcode_modifier
& JumpByte
)
3685 /* This is a loop or jecxz type instruction. */
3687 if (i
.prefix
[ADDR_PREFIX
] != 0)
3689 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3692 /* Pentium4 branch hints. */
3693 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3694 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3696 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3705 if (flag_code
== CODE_16BIT
)
3708 if (i
.prefix
[DATA_PREFIX
] != 0)
3710 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3720 if (i
.prefix
[REX_PREFIX
] != 0)
3722 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3726 if (i
.prefixes
!= 0 && !intel_syntax
)
3727 as_warn (_("skipping prefixes on this instruction"));
3729 p
= frag_more (1 + size
);
3730 *p
++ = i
.tm
.base_opcode
;
3732 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3733 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3735 /* All jumps handled here are signed, but don't use a signed limit
3736 check for 32 and 16 bit jumps as we want to allow wrap around at
3737 4G and 64k respectively. */
3739 fixP
->fx_signed
= 1;
3743 output_interseg_jump ()
3751 if (flag_code
== CODE_16BIT
)
3755 if (i
.prefix
[DATA_PREFIX
] != 0)
3761 if (i
.prefix
[REX_PREFIX
] != 0)
3771 if (i
.prefixes
!= 0 && !intel_syntax
)
3772 as_warn (_("skipping prefixes on this instruction"));
3774 /* 1 opcode; 2 segment; offset */
3775 p
= frag_more (prefix
+ 1 + 2 + size
);
3777 if (i
.prefix
[DATA_PREFIX
] != 0)
3778 *p
++ = DATA_PREFIX_OPCODE
;
3780 if (i
.prefix
[REX_PREFIX
] != 0)
3781 *p
++ = i
.prefix
[REX_PREFIX
];
3783 *p
++ = i
.tm
.base_opcode
;
3784 if (i
.op
[1].imms
->X_op
== O_constant
)
3786 offsetT n
= i
.op
[1].imms
->X_add_number
;
3789 && !fits_in_unsigned_word (n
)
3790 && !fits_in_signed_word (n
))
3792 as_bad (_("16-bit jump out of range"));
3795 md_number_to_chars (p
, n
, size
);
3798 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3799 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3800 if (i
.op
[0].imms
->X_op
!= O_constant
)
3801 as_bad (_("can't handle non absolute segment in `%s'"),
3803 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3809 fragS
*insn_start_frag
;
3810 offsetT insn_start_off
;
3812 /* Tie dwarf2 debug info to the address at the start of the insn.
3813 We can't do this after the insn has been output as the current
3814 frag may have been closed off. eg. by frag_var. */
3815 dwarf2_emit_insn (0);
3817 insn_start_frag
= frag_now
;
3818 insn_start_off
= frag_now_fix ();
3821 if (i
.tm
.opcode_modifier
& Jump
)
3823 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3825 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3826 output_interseg_jump ();
3829 /* Output normal instructions here. */
3832 unsigned int prefix
;
3834 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3835 Instructions have 3 bytes. We may use one more higher byte
3836 to specify a prefix the instruction requires. */
3837 if ((i
.tm
.cpu_flags
& CpuMNI
) != 0)
3839 if (i
.tm
.base_opcode
& 0xff000000)
3841 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3845 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3847 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3848 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3851 if (prefix
!= REPE_PREFIX_OPCODE
3852 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3853 add_prefix (prefix
);
3856 add_prefix (prefix
);
3859 /* The prefix bytes. */
3861 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3867 md_number_to_chars (p
, (valueT
) *q
, 1);
3871 /* Now the opcode; be careful about word order here! */
3872 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3874 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3878 if ((i
.tm
.cpu_flags
& CpuMNI
) != 0)
3881 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3886 /* Put out high byte first: can't use md_number_to_chars! */
3887 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3888 *p
= i
.tm
.base_opcode
& 0xff;
3891 /* Now the modrm byte and sib byte (if present). */
3892 if (i
.tm
.opcode_modifier
& Modrm
)
3895 md_number_to_chars (p
,
3896 (valueT
) (i
.rm
.regmem
<< 0
3900 /* If i.rm.regmem == ESP (4)
3901 && i.rm.mode != (Register mode)
3903 ==> need second modrm byte. */
3904 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3906 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3909 md_number_to_chars (p
,
3910 (valueT
) (i
.sib
.base
<< 0
3912 | i
.sib
.scale
<< 6),
3917 if (i
.disp_operands
)
3918 output_disp (insn_start_frag
, insn_start_off
);
3921 output_imm (insn_start_frag
, insn_start_off
);
3927 pi ("" /*line*/, &i
);
3929 #endif /* DEBUG386 */
3933 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
3938 for (n
= 0; n
< i
.operands
; n
++)
3940 if (i
.types
[n
] & Disp
)
3942 if (i
.op
[n
].disps
->X_op
== O_constant
)
3948 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3951 if (i
.types
[n
] & Disp8
)
3953 if (i
.types
[n
] & Disp64
)
3956 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3958 p
= frag_more (size
);
3959 md_number_to_chars (p
, val
, size
);
3963 enum bfd_reloc_code_real reloc_type
;
3966 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3968 /* The PC relative address is computed relative
3969 to the instruction boundary, so in case immediate
3970 fields follows, we need to adjust the value. */
3971 if (pcrel
&& i
.imm_operands
)
3976 for (n1
= 0; n1
< i
.operands
; n1
++)
3977 if (i
.types
[n1
] & Imm
)
3979 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3982 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3984 if (i
.types
[n1
] & Imm64
)
3989 /* We should find the immediate. */
3990 if (n1
== i
.operands
)
3992 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3995 if (i
.types
[n
] & Disp32S
)
3998 if (i
.types
[n
] & (Disp16
| Disp64
))
4001 if (i
.types
[n
] & Disp64
)
4005 p
= frag_more (size
);
4006 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4008 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4009 && (((reloc_type
== BFD_RELOC_32
4010 || reloc_type
== BFD_RELOC_X86_64_32S
4011 || (reloc_type
== BFD_RELOC_64
4013 && (i
.op
[n
].disps
->X_op
== O_symbol
4014 || (i
.op
[n
].disps
->X_op
== O_add
4015 && ((symbol_get_value_expression
4016 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4018 || reloc_type
== BFD_RELOC_32_PCREL
))
4022 if (insn_start_frag
== frag_now
)
4023 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4028 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4029 for (fr
= insn_start_frag
->fr_next
;
4030 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4032 add
+= p
- frag_now
->fr_literal
;
4037 reloc_type
= BFD_RELOC_386_GOTPC
;
4038 i
.op
[n
].imms
->X_add_number
+= add
;
4040 else if (reloc_type
== BFD_RELOC_64
)
4041 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4043 /* Don't do the adjustment for x86-64, as there
4044 the pcrel addressing is relative to the _next_
4045 insn, and that is taken care of in other code. */
4046 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4048 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4049 i
.op
[n
].disps
, pcrel
, reloc_type
);
4056 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4061 for (n
= 0; n
< i
.operands
; n
++)
4063 if (i
.types
[n
] & Imm
)
4065 if (i
.op
[n
].imms
->X_op
== O_constant
)
4071 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4074 if (i
.types
[n
] & (Imm8
| Imm8S
))
4076 else if (i
.types
[n
] & Imm64
)
4079 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4081 p
= frag_more (size
);
4082 md_number_to_chars (p
, val
, size
);
4086 /* Not absolute_section.
4087 Need a 32-bit fixup (don't support 8bit
4088 non-absolute imms). Try to support other
4090 enum bfd_reloc_code_real reloc_type
;
4094 if ((i
.types
[n
] & (Imm32S
))
4095 && (i
.suffix
== QWORD_MNEM_SUFFIX
4096 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4098 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4101 if (i
.types
[n
] & (Imm8
| Imm8S
))
4103 if (i
.types
[n
] & Imm64
)
4107 p
= frag_more (size
);
4108 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4110 /* This is tough to explain. We end up with this one if we
4111 * have operands that look like
4112 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4113 * obtain the absolute address of the GOT, and it is strongly
4114 * preferable from a performance point of view to avoid using
4115 * a runtime relocation for this. The actual sequence of
4116 * instructions often look something like:
4121 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4123 * The call and pop essentially return the absolute address
4124 * of the label .L66 and store it in %ebx. The linker itself
4125 * will ultimately change the first operand of the addl so
4126 * that %ebx points to the GOT, but to keep things simple, the
4127 * .o file must have this operand set so that it generates not
4128 * the absolute address of .L66, but the absolute address of
4129 * itself. This allows the linker itself simply treat a GOTPC
4130 * relocation as asking for a pcrel offset to the GOT to be
4131 * added in, and the addend of the relocation is stored in the
4132 * operand field for the instruction itself.
4134 * Our job here is to fix the operand so that it would add
4135 * the correct offset so that %ebx would point to itself. The
4136 * thing that is tricky is that .-.L66 will point to the
4137 * beginning of the instruction, so we need to further modify
4138 * the operand so that it will point to itself. There are
4139 * other cases where you have something like:
4141 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4143 * and here no correction would be required. Internally in
4144 * the assembler we treat operands of this form as not being
4145 * pcrel since the '.' is explicitly mentioned, and I wonder
4146 * whether it would simplify matters to do it this way. Who
4147 * knows. In earlier versions of the PIC patches, the
4148 * pcrel_adjust field was used to store the correction, but
4149 * since the expression is not pcrel, I felt it would be
4150 * confusing to do it this way. */
4152 if ((reloc_type
== BFD_RELOC_32
4153 || reloc_type
== BFD_RELOC_X86_64_32S
4154 || reloc_type
== BFD_RELOC_64
)
4156 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4157 && (i
.op
[n
].imms
->X_op
== O_symbol
4158 || (i
.op
[n
].imms
->X_op
== O_add
4159 && ((symbol_get_value_expression
4160 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4165 if (insn_start_frag
== frag_now
)
4166 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4171 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4172 for (fr
= insn_start_frag
->fr_next
;
4173 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4175 add
+= p
- frag_now
->fr_literal
;
4179 reloc_type
= BFD_RELOC_386_GOTPC
;
4181 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4183 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4184 i
.op
[n
].imms
->X_add_number
+= add
;
4186 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4187 i
.op
[n
].imms
, 0, reloc_type
);
4193 /* x86_cons_fix_new is called via the expression parsing code when a
4194 reloc is needed. We use this hook to get the correct .got reloc. */
4195 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4196 static int cons_sign
= -1;
4199 x86_cons_fix_new (fragS
*frag
,
4204 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4206 got_reloc
= NO_RELOC
;
4209 if (exp
->X_op
== O_secrel
)
4211 exp
->X_op
= O_symbol
;
4212 r
= BFD_RELOC_32_SECREL
;
4216 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4219 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4220 # define lex_got(reloc, adjust, types) NULL
4222 /* Parse operands of the form
4223 <symbol>@GOTOFF+<nnn>
4224 and similar .plt or .got references.
4226 If we find one, set up the correct relocation in RELOC and copy the
4227 input string, minus the `@GOTOFF' into a malloc'd buffer for
4228 parsing by the calling routine. Return this buffer, and if ADJUST
4229 is non-null set it to the length of the string we removed from the
4230 input line. Otherwise return NULL. */
4232 lex_got (enum bfd_reloc_code_real
*reloc
,
4234 unsigned int *types
)
4236 /* Some of the relocations depend on the size of what field is to
4237 be relocated. But in our callers i386_immediate and i386_displacement
4238 we don't yet know the operand size (this will be set by insn
4239 matching). Hence we record the word32 relocation here,
4240 and adjust the reloc according to the real size in reloc(). */
4241 static const struct {
4243 const enum bfd_reloc_code_real rel
[2];
4244 const unsigned int types64
;
4246 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64
}, Imm64
},
4247 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
4248 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64
}, Imm64
|Disp64
},
4249 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
4250 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
4251 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
4252 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
4253 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
4254 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
4255 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4256 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
4257 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4258 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
4259 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
4260 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
|Imm64
},
4261 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
, BFD_RELOC_X86_64_GOTPC32_TLSDESC
}, Imm32
|Imm32S
|Disp32
},
4262 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
, BFD_RELOC_X86_64_TLSDESC_CALL
}, Imm32
|Imm32S
|Disp32
}
4270 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4271 if (is_end_of_line
[(unsigned char) *cp
])
4274 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4278 len
= strlen (gotrel
[j
].str
);
4279 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4281 if (gotrel
[j
].rel
[object_64bit
] != 0)
4284 char *tmpbuf
, *past_reloc
;
4286 *reloc
= gotrel
[j
].rel
[object_64bit
];
4292 if (flag_code
!= CODE_64BIT
)
4293 *types
= Imm32
|Disp32
;
4295 *types
= gotrel
[j
].types64
;
4298 if (GOT_symbol
== NULL
)
4299 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4301 /* Replace the relocation token with ' ', so that
4302 errors like foo@GOTOFF1 will be detected. */
4304 /* The length of the first part of our input line. */
4305 first
= cp
- input_line_pointer
;
4307 /* The second part goes from after the reloc token until
4308 (and including) an end_of_line char. Don't use strlen
4309 here as the end_of_line char may not be a NUL. */
4310 past_reloc
= cp
+ 1 + len
;
4311 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4313 second
= cp
- past_reloc
;
4315 /* Allocate and copy string. The trailing NUL shouldn't
4316 be necessary, but be safe. */
4317 tmpbuf
= xmalloc (first
+ second
+ 2);
4318 memcpy (tmpbuf
, input_line_pointer
, first
);
4319 tmpbuf
[first
] = ' ';
4320 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4321 tmpbuf
[first
+ second
+ 1] = '\0';
4325 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4326 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4331 /* Might be a symbol version string. Don't as_bad here. */
4336 x86_cons (exp
, size
)
4340 if (size
== 4 || (object_64bit
&& size
== 8))
4342 /* Handle @GOTOFF and the like in an expression. */
4344 char *gotfree_input_line
;
4347 save
= input_line_pointer
;
4348 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4349 if (gotfree_input_line
)
4350 input_line_pointer
= gotfree_input_line
;
4354 if (gotfree_input_line
)
4356 /* expression () has merrily parsed up to the end of line,
4357 or a comma - in the wrong buffer. Transfer how far
4358 input_line_pointer has moved to the right buffer. */
4359 input_line_pointer
= (save
4360 + (input_line_pointer
- gotfree_input_line
)
4362 free (gotfree_input_line
);
4370 static void signed_cons (int size
)
4372 if (flag_code
== CODE_64BIT
)
4380 pe_directive_secrel (dummy
)
4381 int dummy ATTRIBUTE_UNUSED
;
4388 if (exp
.X_op
== O_symbol
)
4389 exp
.X_op
= O_secrel
;
4391 emit_expr (&exp
, 4);
4393 while (*input_line_pointer
++ == ',');
4395 input_line_pointer
--;
4396 demand_empty_rest_of_line ();
4400 static int i386_immediate
PARAMS ((char *));
4403 i386_immediate (imm_start
)
4406 char *save_input_line_pointer
;
4407 char *gotfree_input_line
;
4410 unsigned int types
= ~0U;
4412 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4414 as_bad (_("only 1 or 2 immediate operands are allowed"));
4418 exp
= &im_expressions
[i
.imm_operands
++];
4419 i
.op
[this_operand
].imms
= exp
;
4421 if (is_space_char (*imm_start
))
4424 save_input_line_pointer
= input_line_pointer
;
4425 input_line_pointer
= imm_start
;
4427 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4428 if (gotfree_input_line
)
4429 input_line_pointer
= gotfree_input_line
;
4431 exp_seg
= expression (exp
);
4434 if (*input_line_pointer
)
4435 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4437 input_line_pointer
= save_input_line_pointer
;
4438 if (gotfree_input_line
)
4439 free (gotfree_input_line
);
4441 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4443 /* Missing or bad expr becomes absolute 0. */
4444 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4446 exp
->X_op
= O_constant
;
4447 exp
->X_add_number
= 0;
4448 exp
->X_add_symbol
= (symbolS
*) 0;
4449 exp
->X_op_symbol
= (symbolS
*) 0;
4451 else if (exp
->X_op
== O_constant
)
4453 /* Size it properly later. */
4454 i
.types
[this_operand
] |= Imm64
;
4455 /* If BFD64, sign extend val. */
4456 if (!use_rela_relocations
)
4457 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4458 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4460 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4461 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4462 && exp_seg
!= absolute_section
4463 && exp_seg
!= text_section
4464 && exp_seg
!= data_section
4465 && exp_seg
!= bss_section
4466 && exp_seg
!= undefined_section
4467 && !bfd_is_com_section (exp_seg
))
4469 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4473 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4475 as_bad (_("illegal immediate register operand %s"), imm_start
);
4480 /* This is an address. The size of the address will be
4481 determined later, depending on destination register,
4482 suffix, or the default for the section. */
4483 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4484 i
.types
[this_operand
] &= types
;
4490 static char *i386_scale
PARAMS ((char *));
4497 char *save
= input_line_pointer
;
4499 input_line_pointer
= scale
;
4500 val
= get_absolute_expression ();
4505 i
.log2_scale_factor
= 0;
4508 i
.log2_scale_factor
= 1;
4511 i
.log2_scale_factor
= 2;
4514 i
.log2_scale_factor
= 3;
4518 char sep
= *input_line_pointer
;
4520 *input_line_pointer
= '\0';
4521 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4523 *input_line_pointer
= sep
;
4524 input_line_pointer
= save
;
4528 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4530 as_warn (_("scale factor of %d without an index register"),
4531 1 << i
.log2_scale_factor
);
4532 #if SCALE1_WHEN_NO_INDEX
4533 i
.log2_scale_factor
= 0;
4536 scale
= input_line_pointer
;
4537 input_line_pointer
= save
;
4541 static int i386_displacement
PARAMS ((char *, char *));
4544 i386_displacement (disp_start
, disp_end
)
4550 char *save_input_line_pointer
;
4551 char *gotfree_input_line
;
4552 int bigdisp
, override
;
4553 unsigned int types
= Disp
;
4555 if ((i
.types
[this_operand
] & JumpAbsolute
)
4556 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4559 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4563 /* For PC-relative branches, the width of the displacement
4564 is dependent upon data size, not address size. */
4566 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4568 if (flag_code
== CODE_64BIT
)
4571 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4573 : Disp32S
| Disp32
);
4575 bigdisp
= Disp64
| Disp32S
| Disp32
;
4582 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4584 : LONG_MNEM_SUFFIX
));
4587 if ((flag_code
== CODE_16BIT
) ^ override
)
4590 i
.types
[this_operand
] |= bigdisp
;
4592 exp
= &disp_expressions
[i
.disp_operands
];
4593 i
.op
[this_operand
].disps
= exp
;
4595 save_input_line_pointer
= input_line_pointer
;
4596 input_line_pointer
= disp_start
;
4597 END_STRING_AND_SAVE (disp_end
);
4599 #ifndef GCC_ASM_O_HACK
4600 #define GCC_ASM_O_HACK 0
4603 END_STRING_AND_SAVE (disp_end
+ 1);
4604 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4605 && displacement_string_end
[-1] == '+')
4607 /* This hack is to avoid a warning when using the "o"
4608 constraint within gcc asm statements.
4611 #define _set_tssldt_desc(n,addr,limit,type) \
4612 __asm__ __volatile__ ( \
4614 "movw %w1,2+%0\n\t" \
4616 "movb %b1,4+%0\n\t" \
4617 "movb %4,5+%0\n\t" \
4618 "movb $0,6+%0\n\t" \
4619 "movb %h1,7+%0\n\t" \
4621 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4623 This works great except that the output assembler ends
4624 up looking a bit weird if it turns out that there is
4625 no offset. You end up producing code that looks like:
4638 So here we provide the missing zero. */
4640 *displacement_string_end
= '0';
4643 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4644 if (gotfree_input_line
)
4645 input_line_pointer
= gotfree_input_line
;
4647 exp_seg
= expression (exp
);
4650 if (*input_line_pointer
)
4651 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4653 RESTORE_END_STRING (disp_end
+ 1);
4655 RESTORE_END_STRING (disp_end
);
4656 input_line_pointer
= save_input_line_pointer
;
4657 if (gotfree_input_line
)
4658 free (gotfree_input_line
);
4660 /* We do this to make sure that the section symbol is in
4661 the symbol table. We will ultimately change the relocation
4662 to be relative to the beginning of the section. */
4663 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4664 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4665 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4667 if (exp
->X_op
!= O_symbol
)
4669 as_bad (_("bad expression used with @%s"),
4670 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4676 if (S_IS_LOCAL (exp
->X_add_symbol
)
4677 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4678 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4679 exp
->X_op
= O_subtract
;
4680 exp
->X_op_symbol
= GOT_symbol
;
4681 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4682 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4683 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4684 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4686 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4689 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4691 /* Missing or bad expr becomes absolute 0. */
4692 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4694 exp
->X_op
= O_constant
;
4695 exp
->X_add_number
= 0;
4696 exp
->X_add_symbol
= (symbolS
*) 0;
4697 exp
->X_op_symbol
= (symbolS
*) 0;
4700 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4701 if (exp
->X_op
!= O_constant
4702 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4703 && exp_seg
!= absolute_section
4704 && exp_seg
!= text_section
4705 && exp_seg
!= data_section
4706 && exp_seg
!= bss_section
4707 && exp_seg
!= undefined_section
4708 && !bfd_is_com_section (exp_seg
))
4710 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4715 if (!(i
.types
[this_operand
] & ~Disp
))
4716 i
.types
[this_operand
] &= types
;
4721 static int i386_index_check
PARAMS ((const char *));
4723 /* Make sure the memory operand we've been dealt is valid.
4724 Return 1 on success, 0 on a failure. */
4727 i386_index_check (operand_string
)
4728 const char *operand_string
;
4731 #if INFER_ADDR_PREFIX
4737 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4738 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4740 /* Memory operands of SVME insns are special in that they only allow
4741 rAX as their memory address and ignore any segment override. */
4744 /* SKINIT is even more restrictive: it always requires EAX. */
4745 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4747 else if (flag_code
== CODE_64BIT
)
4748 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4750 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4754 || !(i
.base_reg
->reg_type
& Acc
)
4755 || !(i
.base_reg
->reg_type
& RegXX
)
4757 || (i
.types
[0] & Disp
))
4760 else if (flag_code
== CODE_64BIT
)
4762 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4765 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4766 && (i
.base_reg
->reg_type
!= BaseIndex
4769 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4770 != (RegXX
| BaseIndex
))))
4775 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4779 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4780 != (Reg16
| BaseIndex
)))
4782 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4783 != (Reg16
| BaseIndex
))
4785 && i
.base_reg
->reg_num
< 6
4786 && i
.index_reg
->reg_num
>= 6
4787 && i
.log2_scale_factor
== 0))))
4794 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4796 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4797 != (Reg32
| BaseIndex
))))
4803 #if INFER_ADDR_PREFIX
4804 if (i
.prefix
[ADDR_PREFIX
] == 0)
4806 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4808 /* Change the size of any displacement too. At most one of
4809 Disp16 or Disp32 is set.
4810 FIXME. There doesn't seem to be any real need for separate
4811 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4812 Removing them would probably clean up the code quite a lot. */
4813 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4814 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4819 as_bad (_("`%s' is not a valid base/index expression"),
4823 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4825 flag_code_names
[flag_code
]);
4830 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4834 i386_operand (operand_string
)
4835 char *operand_string
;
4839 char *op_string
= operand_string
;
4841 if (is_space_char (*op_string
))
4844 /* We check for an absolute prefix (differentiating,
4845 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4846 if (*op_string
== ABSOLUTE_PREFIX
)
4849 if (is_space_char (*op_string
))
4851 i
.types
[this_operand
] |= JumpAbsolute
;
4854 /* Check if operand is a register. */
4855 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4857 /* Check for a segment override by searching for ':' after a
4858 segment register. */
4860 if (is_space_char (*op_string
))
4862 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4867 i
.seg
[i
.mem_operands
] = &es
;
4870 i
.seg
[i
.mem_operands
] = &cs
;
4873 i
.seg
[i
.mem_operands
] = &ss
;
4876 i
.seg
[i
.mem_operands
] = &ds
;
4879 i
.seg
[i
.mem_operands
] = &fs
;
4882 i
.seg
[i
.mem_operands
] = &gs
;
4886 /* Skip the ':' and whitespace. */
4888 if (is_space_char (*op_string
))
4891 if (!is_digit_char (*op_string
)
4892 && !is_identifier_char (*op_string
)
4893 && *op_string
!= '('
4894 && *op_string
!= ABSOLUTE_PREFIX
)
4896 as_bad (_("bad memory operand `%s'"), op_string
);
4899 /* Handle case of %es:*foo. */
4900 if (*op_string
== ABSOLUTE_PREFIX
)
4903 if (is_space_char (*op_string
))
4905 i
.types
[this_operand
] |= JumpAbsolute
;
4907 goto do_memory_reference
;
4911 as_bad (_("junk `%s' after register"), op_string
);
4914 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4915 i
.op
[this_operand
].regs
= r
;
4918 else if (*op_string
== REGISTER_PREFIX
)
4920 as_bad (_("bad register name `%s'"), op_string
);
4923 else if (*op_string
== IMMEDIATE_PREFIX
)
4926 if (i
.types
[this_operand
] & JumpAbsolute
)
4928 as_bad (_("immediate operand illegal with absolute jump"));
4931 if (!i386_immediate (op_string
))
4934 else if (is_digit_char (*op_string
)
4935 || is_identifier_char (*op_string
)
4936 || *op_string
== '(')
4938 /* This is a memory reference of some sort. */
4941 /* Start and end of displacement string expression (if found). */
4942 char *displacement_string_start
;
4943 char *displacement_string_end
;
4945 do_memory_reference
:
4946 if ((i
.mem_operands
== 1
4947 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4948 || i
.mem_operands
== 2)
4950 as_bad (_("too many memory references for `%s'"),
4951 current_templates
->start
->name
);
4955 /* Check for base index form. We detect the base index form by
4956 looking for an ')' at the end of the operand, searching
4957 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4959 base_string
= op_string
+ strlen (op_string
);
4962 if (is_space_char (*base_string
))
4965 /* If we only have a displacement, set-up for it to be parsed later. */
4966 displacement_string_start
= op_string
;
4967 displacement_string_end
= base_string
+ 1;
4969 if (*base_string
== ')')
4972 unsigned int parens_balanced
= 1;
4973 /* We've already checked that the number of left & right ()'s are
4974 equal, so this loop will not be infinite. */
4978 if (*base_string
== ')')
4980 if (*base_string
== '(')
4983 while (parens_balanced
);
4985 temp_string
= base_string
;
4987 /* Skip past '(' and whitespace. */
4989 if (is_space_char (*base_string
))
4992 if (*base_string
== ','
4993 || ((i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4995 displacement_string_end
= temp_string
;
4997 i
.types
[this_operand
] |= BaseIndex
;
5001 base_string
= end_op
;
5002 if (is_space_char (*base_string
))
5006 /* There may be an index reg or scale factor here. */
5007 if (*base_string
== ',')
5010 if (is_space_char (*base_string
))
5013 if ((i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
5015 base_string
= end_op
;
5016 if (is_space_char (*base_string
))
5018 if (*base_string
== ',')
5021 if (is_space_char (*base_string
))
5024 else if (*base_string
!= ')')
5026 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5031 else if (*base_string
== REGISTER_PREFIX
)
5033 as_bad (_("bad register name `%s'"), base_string
);
5037 /* Check for scale factor. */
5038 if (*base_string
!= ')')
5040 char *end_scale
= i386_scale (base_string
);
5045 base_string
= end_scale
;
5046 if (is_space_char (*base_string
))
5048 if (*base_string
!= ')')
5050 as_bad (_("expecting `)' after scale factor in `%s'"),
5055 else if (!i
.index_reg
)
5057 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5062 else if (*base_string
!= ')')
5064 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5069 else if (*base_string
== REGISTER_PREFIX
)
5071 as_bad (_("bad register name `%s'"), base_string
);
5076 /* If there's an expression beginning the operand, parse it,
5077 assuming displacement_string_start and
5078 displacement_string_end are meaningful. */
5079 if (displacement_string_start
!= displacement_string_end
)
5081 if (!i386_displacement (displacement_string_start
,
5082 displacement_string_end
))
5086 /* Special case for (%dx) while doing input/output op. */
5088 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5090 && i
.log2_scale_factor
== 0
5091 && i
.seg
[i
.mem_operands
] == 0
5092 && (i
.types
[this_operand
] & Disp
) == 0)
5094 i
.types
[this_operand
] = InOutPortReg
;
5098 if (i386_index_check (operand_string
) == 0)
5104 /* It's not a memory operand; argh! */
5105 as_bad (_("invalid char %s beginning operand %d `%s'"),
5106 output_invalid (*op_string
),
5111 return 1; /* Normal return. */
5114 /* md_estimate_size_before_relax()
5116 Called just before relax() for rs_machine_dependent frags. The x86
5117 assembler uses these frags to handle variable size jump
5120 Any symbol that is now undefined will not become defined.
5121 Return the correct fr_subtype in the frag.
5122 Return the initial "guess for variable size of frag" to caller.
5123 The guess is actually the growth beyond the fixed part. Whatever
5124 we do to grow the fixed or variable part contributes to our
5128 md_estimate_size_before_relax (fragP
, segment
)
5132 /* We've already got fragP->fr_subtype right; all we have to do is
5133 check for un-relaxable symbols. On an ELF system, we can't relax
5134 an externally visible symbol, because it may be overridden by a
5136 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5139 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5140 || S_IS_WEAK (fragP
->fr_symbol
)))
5144 /* Symbol is undefined in this segment, or we need to keep a
5145 reloc so that weak symbols can be overridden. */
5146 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5147 enum bfd_reloc_code_real reloc_type
;
5148 unsigned char *opcode
;
5151 if (fragP
->fr_var
!= NO_RELOC
)
5152 reloc_type
= fragP
->fr_var
;
5154 reloc_type
= BFD_RELOC_16_PCREL
;
5156 reloc_type
= BFD_RELOC_32_PCREL
;
5158 old_fr_fix
= fragP
->fr_fix
;
5159 opcode
= (unsigned char *) fragP
->fr_opcode
;
5161 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5164 /* Make jmp (0xeb) a (d)word displacement jump. */
5166 fragP
->fr_fix
+= size
;
5167 fix_new (fragP
, old_fr_fix
, size
,
5169 fragP
->fr_offset
, 1,
5175 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5177 /* Negate the condition, and branch past an
5178 unconditional jump. */
5181 /* Insert an unconditional jump. */
5183 /* We added two extra opcode bytes, and have a two byte
5185 fragP
->fr_fix
+= 2 + 2;
5186 fix_new (fragP
, old_fr_fix
+ 2, 2,
5188 fragP
->fr_offset
, 1,
5195 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5200 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5202 fragP
->fr_offset
, 1,
5204 fixP
->fx_signed
= 1;
5208 /* This changes the byte-displacement jump 0x7N
5209 to the (d)word-displacement jump 0x0f,0x8N. */
5210 opcode
[1] = opcode
[0] + 0x10;
5211 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5212 /* We've added an opcode byte. */
5213 fragP
->fr_fix
+= 1 + size
;
5214 fix_new (fragP
, old_fr_fix
+ 1, size
,
5216 fragP
->fr_offset
, 1,
5221 BAD_CASE (fragP
->fr_subtype
);
5225 return fragP
->fr_fix
- old_fr_fix
;
5228 /* Guess size depending on current relax state. Initially the relax
5229 state will correspond to a short jump and we return 1, because
5230 the variable part of the frag (the branch offset) is one byte
5231 long. However, we can relax a section more than once and in that
5232 case we must either set fr_subtype back to the unrelaxed state,
5233 or return the value for the appropriate branch. */
5234 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5237 /* Called after relax() is finished.
5239 In: Address of frag.
5240 fr_type == rs_machine_dependent.
5241 fr_subtype is what the address relaxed to.
5243 Out: Any fixSs and constants are set up.
5244 Caller will turn frag into a ".space 0". */
5247 md_convert_frag (abfd
, sec
, fragP
)
5248 bfd
*abfd ATTRIBUTE_UNUSED
;
5249 segT sec ATTRIBUTE_UNUSED
;
5252 unsigned char *opcode
;
5253 unsigned char *where_to_put_displacement
= NULL
;
5254 offsetT target_address
;
5255 offsetT opcode_address
;
5256 unsigned int extension
= 0;
5257 offsetT displacement_from_opcode_start
;
5259 opcode
= (unsigned char *) fragP
->fr_opcode
;
5261 /* Address we want to reach in file space. */
5262 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5264 /* Address opcode resides at in file space. */
5265 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5267 /* Displacement from opcode start to fill into instruction. */
5268 displacement_from_opcode_start
= target_address
- opcode_address
;
5270 if ((fragP
->fr_subtype
& BIG
) == 0)
5272 /* Don't have to change opcode. */
5273 extension
= 1; /* 1 opcode + 1 displacement */
5274 where_to_put_displacement
= &opcode
[1];
5278 if (no_cond_jump_promotion
5279 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5280 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
5282 switch (fragP
->fr_subtype
)
5284 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5285 extension
= 4; /* 1 opcode + 4 displacement */
5287 where_to_put_displacement
= &opcode
[1];
5290 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5291 extension
= 2; /* 1 opcode + 2 displacement */
5293 where_to_put_displacement
= &opcode
[1];
5296 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5297 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5298 extension
= 5; /* 2 opcode + 4 displacement */
5299 opcode
[1] = opcode
[0] + 0x10;
5300 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5301 where_to_put_displacement
= &opcode
[2];
5304 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5305 extension
= 3; /* 2 opcode + 2 displacement */
5306 opcode
[1] = opcode
[0] + 0x10;
5307 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5308 where_to_put_displacement
= &opcode
[2];
5311 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5316 where_to_put_displacement
= &opcode
[3];
5320 BAD_CASE (fragP
->fr_subtype
);
5325 /* If size if less then four we are sure that the operand fits,
5326 but if it's 4, then it could be that the displacement is larger
5328 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5330 && ((addressT
) (displacement_from_opcode_start
- extension
5331 + ((addressT
) 1 << 31))
5332 > (((addressT
) 2 << 31) - 1)))
5334 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5335 _("jump target out of range"));
5336 /* Make us emit 0. */
5337 displacement_from_opcode_start
= extension
;
5339 /* Now put displacement after opcode. */
5340 md_number_to_chars ((char *) where_to_put_displacement
,
5341 (valueT
) (displacement_from_opcode_start
- extension
),
5342 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5343 fragP
->fr_fix
+= extension
;
5346 /* Size of byte displacement jmp. */
5347 int md_short_jump_size
= 2;
5349 /* Size of dword displacement jmp. */
5350 int md_long_jump_size
= 5;
5353 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5355 addressT from_addr
, to_addr
;
5356 fragS
*frag ATTRIBUTE_UNUSED
;
5357 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5361 offset
= to_addr
- (from_addr
+ 2);
5362 /* Opcode for byte-disp jump. */
5363 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5364 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5368 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5370 addressT from_addr
, to_addr
;
5371 fragS
*frag ATTRIBUTE_UNUSED
;
5372 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5376 offset
= to_addr
- (from_addr
+ 5);
5377 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5378 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5381 /* Apply a fixup (fixS) to segment data, once it has been determined
5382 by our caller that we have all the info we need to fix it up.
5384 On the 386, immediates, displacements, and data pointers are all in
5385 the same (little-endian) format, so we don't need to care about which
5389 md_apply_fix (fixP
, valP
, seg
)
5390 /* The fix we're to put in. */
5392 /* Pointer to the value of the bits. */
5394 /* Segment fix is from. */
5395 segT seg ATTRIBUTE_UNUSED
;
5397 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5398 valueT value
= *valP
;
5400 #if !defined (TE_Mach)
5403 switch (fixP
->fx_r_type
)
5409 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5412 case BFD_RELOC_X86_64_32S
:
5413 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5416 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5419 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5424 if (fixP
->fx_addsy
!= NULL
5425 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5426 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5427 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5428 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5429 && !use_rela_relocations
)
5431 /* This is a hack. There should be a better way to handle this.
5432 This covers for the fact that bfd_install_relocation will
5433 subtract the current location (for partial_inplace, PC relative
5434 relocations); see more below. */
5438 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5441 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5446 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5449 || (symbol_section_p (fixP
->fx_addsy
)
5450 && sym_seg
!= absolute_section
))
5451 && !generic_force_reloc (fixP
))
5453 /* Yes, we add the values in twice. This is because
5454 bfd_install_relocation subtracts them out again. I think
5455 bfd_install_relocation is broken, but I don't dare change
5457 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5461 #if defined (OBJ_COFF) && defined (TE_PE)
5462 /* For some reason, the PE format does not store a
5463 section address offset for a PC relative symbol. */
5464 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5465 || S_IS_WEAK (fixP
->fx_addsy
))
5466 value
+= md_pcrel_from (fixP
);
5470 /* Fix a few things - the dynamic linker expects certain values here,
5471 and we must not disappoint it. */
5472 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5473 if (IS_ELF
&& fixP
->fx_addsy
)
5474 switch (fixP
->fx_r_type
)
5476 case BFD_RELOC_386_PLT32
:
5477 case BFD_RELOC_X86_64_PLT32
:
5478 /* Make the jump instruction point to the address of the operand. At
5479 runtime we merely add the offset to the actual PLT entry. */
5483 case BFD_RELOC_386_TLS_GD
:
5484 case BFD_RELOC_386_TLS_LDM
:
5485 case BFD_RELOC_386_TLS_IE_32
:
5486 case BFD_RELOC_386_TLS_IE
:
5487 case BFD_RELOC_386_TLS_GOTIE
:
5488 case BFD_RELOC_386_TLS_GOTDESC
:
5489 case BFD_RELOC_X86_64_TLSGD
:
5490 case BFD_RELOC_X86_64_TLSLD
:
5491 case BFD_RELOC_X86_64_GOTTPOFF
:
5492 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5493 value
= 0; /* Fully resolved at runtime. No addend. */
5495 case BFD_RELOC_386_TLS_LE
:
5496 case BFD_RELOC_386_TLS_LDO_32
:
5497 case BFD_RELOC_386_TLS_LE_32
:
5498 case BFD_RELOC_X86_64_DTPOFF32
:
5499 case BFD_RELOC_X86_64_DTPOFF64
:
5500 case BFD_RELOC_X86_64_TPOFF32
:
5501 case BFD_RELOC_X86_64_TPOFF64
:
5502 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5505 case BFD_RELOC_386_TLS_DESC_CALL
:
5506 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5507 value
= 0; /* Fully resolved at runtime. No addend. */
5508 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5512 case BFD_RELOC_386_GOT32
:
5513 case BFD_RELOC_X86_64_GOT32
:
5514 value
= 0; /* Fully resolved at runtime. No addend. */
5517 case BFD_RELOC_VTABLE_INHERIT
:
5518 case BFD_RELOC_VTABLE_ENTRY
:
5525 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5527 #endif /* !defined (TE_Mach) */
5529 /* Are we finished with this relocation now? */
5530 if (fixP
->fx_addsy
== NULL
)
5532 else if (use_rela_relocations
)
5534 fixP
->fx_no_overflow
= 1;
5535 /* Remember value for tc_gen_reloc. */
5536 fixP
->fx_addnumber
= value
;
5540 md_number_to_chars (p
, value
, fixP
->fx_size
);
5543 #define MAX_LITTLENUMS 6
5545 /* Turn the string pointed to by litP into a floating point constant
5546 of type TYPE, and emit the appropriate bytes. The number of
5547 LITTLENUMS emitted is stored in *SIZEP. An error message is
5548 returned, or NULL on OK. */
5551 md_atof (type
, litP
, sizeP
)
5557 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5558 LITTLENUM_TYPE
*wordP
;
5580 return _("Bad call to md_atof ()");
5582 t
= atof_ieee (input_line_pointer
, type
, words
);
5584 input_line_pointer
= t
;
5586 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5587 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5588 the bigendian 386. */
5589 for (wordP
= words
+ prec
- 1; prec
--;)
5591 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5592 litP
+= sizeof (LITTLENUM_TYPE
);
5597 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5604 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5607 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5608 "(0x%x)", (unsigned char) c
);
5609 return output_invalid_buf
;
5612 /* REG_STRING starts *before* REGISTER_PREFIX. */
5614 static const reg_entry
*
5615 parse_real_register (char *reg_string
, char **end_op
)
5617 char *s
= reg_string
;
5619 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5622 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5623 if (*s
== REGISTER_PREFIX
)
5626 if (is_space_char (*s
))
5630 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5632 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5633 return (const reg_entry
*) NULL
;
5637 /* For naked regs, make sure that we are not dealing with an identifier.
5638 This prevents confusing an identifier like `eax_var' with register
5640 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5641 return (const reg_entry
*) NULL
;
5645 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5647 /* Handle floating point regs, allowing spaces in the (i) part. */
5648 if (r
== i386_regtab
/* %st is first entry of table */)
5650 if (is_space_char (*s
))
5655 if (is_space_char (*s
))
5657 if (*s
>= '0' && *s
<= '7')
5659 r
= &i386_float_regtab
[*s
- '0'];
5661 if (is_space_char (*s
))
5669 /* We have "%st(" then garbage. */
5670 return (const reg_entry
*) NULL
;
5675 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5676 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5677 && flag_code
!= CODE_64BIT
)
5678 return (const reg_entry
*) NULL
;
5683 /* REG_STRING starts *before* REGISTER_PREFIX. */
5685 static const reg_entry
*
5686 parse_register (char *reg_string
, char **end_op
)
5690 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5691 r
= parse_real_register (reg_string
, end_op
);
5696 char *save
= input_line_pointer
;
5700 input_line_pointer
= reg_string
;
5701 c
= get_symbol_end ();
5702 symbolP
= symbol_find (reg_string
);
5703 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5705 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5707 know (e
->X_op
== O_register
);
5708 know (e
->X_add_number
>= 0 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5709 r
= i386_regtab
+ e
->X_add_number
;
5710 *end_op
= input_line_pointer
;
5712 *input_line_pointer
= c
;
5713 input_line_pointer
= save
;
5719 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5722 char *end
= input_line_pointer
;
5725 r
= parse_register (name
, &input_line_pointer
);
5726 if (r
&& end
<= input_line_pointer
)
5728 *nextcharP
= *input_line_pointer
;
5729 *input_line_pointer
= 0;
5730 e
->X_op
= O_register
;
5731 e
->X_add_number
= r
- i386_regtab
;
5734 input_line_pointer
= end
;
5740 md_operand (expressionS
*e
)
5742 if (*input_line_pointer
== REGISTER_PREFIX
)
5745 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5749 e
->X_op
= O_register
;
5750 e
->X_add_number
= r
- i386_regtab
;
5751 input_line_pointer
= end
;
5757 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5758 const char *md_shortopts
= "kVQ:sqn";
5760 const char *md_shortopts
= "qn";
5763 #define OPTION_32 (OPTION_MD_BASE + 0)
5764 #define OPTION_64 (OPTION_MD_BASE + 1)
5765 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5766 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5767 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5769 struct option md_longopts
[] =
5771 {"32", no_argument
, NULL
, OPTION_32
},
5772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5773 {"64", no_argument
, NULL
, OPTION_64
},
5775 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5776 {"march", required_argument
, NULL
, OPTION_MARCH
},
5777 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5778 {NULL
, no_argument
, NULL
, 0}
5780 size_t md_longopts_size
= sizeof (md_longopts
);
5783 md_parse_option (int c
, char *arg
)
5790 optimize_align_code
= 0;
5797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5798 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5799 should be emitted or not. FIXME: Not implemented. */
5803 /* -V: SVR4 argument to print version ID. */
5805 print_version_id ();
5808 /* -k: Ignore for FreeBSD compatibility. */
5813 /* -s: On i386 Solaris, this tells the native assembler to use
5814 .stab instead of .stab.excl. We always use .stab anyhow. */
5817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5820 const char **list
, **l
;
5822 list
= bfd_target_list ();
5823 for (l
= list
; *l
!= NULL
; l
++)
5824 if ( strncmp (*l
, "elf64-x86-64", 12) == 0
5825 || strcmp (*l
, "coff-x86-64") == 0
5826 || strcmp (*l
, "pe-x86-64") == 0
5827 || strcmp (*l
, "pei-x86-64") == 0)
5829 default_arch
= "x86_64";
5833 as_fatal (_("No compiled in support for x86_64"));
5840 default_arch
= "i386";
5844 #ifdef SVR4_COMMENT_CHARS
5849 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5851 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5855 i386_comment_chars
= n
;
5862 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5863 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5865 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5867 cpu_arch_isa
= cpu_arch
[i
].type
;
5868 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
5869 if (!cpu_arch_tune_set
)
5871 cpu_arch_tune
= cpu_arch_isa
;
5872 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
5877 if (i
>= ARRAY_SIZE (cpu_arch
))
5878 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5883 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5884 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5886 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5888 cpu_arch_tune_set
= 1;
5889 cpu_arch_tune
= cpu_arch
[i
].type
;
5890 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
5894 if (i
>= ARRAY_SIZE (cpu_arch
))
5895 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5905 md_show_usage (stream
)
5908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5909 fprintf (stream
, _("\
5911 -V print assembler version number\n\
5914 fprintf (stream
, _("\
5915 -n Do not optimize code alignment\n\
5916 -q quieten some warnings\n"));
5917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5918 fprintf (stream
, _("\
5921 #ifdef SVR4_COMMENT_CHARS
5922 fprintf (stream
, _("\
5923 --divide do not treat `/' as a comment character\n"));
5925 fprintf (stream
, _("\
5926 --divide ignored\n"));
5928 fprintf (stream
, _("\
5929 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5930 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5931 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5937 x86_64_target_format (void)
5939 if (strcmp (default_arch
, "x86_64") == 0)
5941 set_code_flag (CODE_64BIT
);
5942 return COFF_TARGET_FORMAT
;
5944 else if (strcmp (default_arch
, "i386") == 0)
5946 set_code_flag (CODE_32BIT
);
5950 as_fatal (_("Unknown architecture"));
5955 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5956 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5958 /* Pick the target format to use. */
5961 i386_target_format ()
5963 if (!strcmp (default_arch
, "x86_64"))
5965 set_code_flag (CODE_64BIT
);
5966 if (cpu_arch_isa_flags
== 0)
5967 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
5968 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
5970 if (cpu_arch_tune_flags
== 0)
5971 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
5972 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
5975 else if (!strcmp (default_arch
, "i386"))
5977 set_code_flag (CODE_32BIT
);
5978 if (cpu_arch_isa_flags
== 0)
5979 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
5980 if (cpu_arch_tune_flags
== 0)
5981 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
5984 as_fatal (_("Unknown architecture"));
5985 switch (OUTPUT_FLAVOR
)
5987 #ifdef OBJ_MAYBE_AOUT
5988 case bfd_target_aout_flavour
:
5989 return AOUT_TARGET_FORMAT
;
5991 #ifdef OBJ_MAYBE_COFF
5992 case bfd_target_coff_flavour
:
5995 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5996 case bfd_target_elf_flavour
:
5998 if (flag_code
== CODE_64BIT
)
6001 use_rela_relocations
= 1;
6003 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6012 #endif /* OBJ_MAYBE_ more than one */
6014 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6015 void i386_elf_emit_arch_note ()
6017 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6020 asection
*seg
= now_seg
;
6021 subsegT subseg
= now_subseg
;
6022 Elf_Internal_Note i_note
;
6023 Elf_External_Note e_note
;
6024 asection
*note_secp
;
6027 /* Create the .note section. */
6028 note_secp
= subseg_new (".note", 0);
6029 bfd_set_section_flags (stdoutput
,
6031 SEC_HAS_CONTENTS
| SEC_READONLY
);
6033 /* Process the arch string. */
6034 len
= strlen (cpu_arch_name
);
6036 i_note
.namesz
= len
+ 1;
6038 i_note
.type
= NT_ARCH
;
6039 p
= frag_more (sizeof (e_note
.namesz
));
6040 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6041 p
= frag_more (sizeof (e_note
.descsz
));
6042 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6043 p
= frag_more (sizeof (e_note
.type
));
6044 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6045 p
= frag_more (len
+ 1);
6046 strcpy (p
, cpu_arch_name
);
6048 frag_align (2, 0, 0);
6050 subseg_set (seg
, subseg
);
6056 md_undefined_symbol (name
)
6059 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6060 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6061 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6062 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6066 if (symbol_find (name
))
6067 as_bad (_("GOT already in symbol table"));
6068 GOT_symbol
= symbol_new (name
, undefined_section
,
6069 (valueT
) 0, &zero_address_frag
);
6076 /* Round up a section size to the appropriate boundary. */
6079 md_section_align (segment
, size
)
6080 segT segment ATTRIBUTE_UNUSED
;
6083 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6084 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6086 /* For a.out, force the section size to be aligned. If we don't do
6087 this, BFD will align it for us, but it will not write out the
6088 final bytes of the section. This may be a bug in BFD, but it is
6089 easier to fix it here since that is how the other a.out targets
6093 align
= bfd_get_section_alignment (stdoutput
, segment
);
6094 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6101 /* On the i386, PC-relative offsets are relative to the start of the
6102 next instruction. That is, the address of the offset, plus its
6103 size, since the offset is always the last part of the insn. */
6106 md_pcrel_from (fixP
)
6109 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6116 int ignore ATTRIBUTE_UNUSED
;
6120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6122 obj_elf_section_change_hook ();
6124 temp
= get_absolute_expression ();
6125 subseg_set (bss_section
, (subsegT
) temp
);
6126 demand_empty_rest_of_line ();
6132 i386_validate_fix (fixp
)
6135 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6137 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6141 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6146 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6148 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6155 tc_gen_reloc (section
, fixp
)
6156 asection
*section ATTRIBUTE_UNUSED
;
6160 bfd_reloc_code_real_type code
;
6162 switch (fixp
->fx_r_type
)
6164 case BFD_RELOC_X86_64_PLT32
:
6165 case BFD_RELOC_X86_64_GOT32
:
6166 case BFD_RELOC_X86_64_GOTPCREL
:
6167 case BFD_RELOC_386_PLT32
:
6168 case BFD_RELOC_386_GOT32
:
6169 case BFD_RELOC_386_GOTOFF
:
6170 case BFD_RELOC_386_GOTPC
:
6171 case BFD_RELOC_386_TLS_GD
:
6172 case BFD_RELOC_386_TLS_LDM
:
6173 case BFD_RELOC_386_TLS_LDO_32
:
6174 case BFD_RELOC_386_TLS_IE_32
:
6175 case BFD_RELOC_386_TLS_IE
:
6176 case BFD_RELOC_386_TLS_GOTIE
:
6177 case BFD_RELOC_386_TLS_LE_32
:
6178 case BFD_RELOC_386_TLS_LE
:
6179 case BFD_RELOC_386_TLS_GOTDESC
:
6180 case BFD_RELOC_386_TLS_DESC_CALL
:
6181 case BFD_RELOC_X86_64_TLSGD
:
6182 case BFD_RELOC_X86_64_TLSLD
:
6183 case BFD_RELOC_X86_64_DTPOFF32
:
6184 case BFD_RELOC_X86_64_DTPOFF64
:
6185 case BFD_RELOC_X86_64_GOTTPOFF
:
6186 case BFD_RELOC_X86_64_TPOFF32
:
6187 case BFD_RELOC_X86_64_TPOFF64
:
6188 case BFD_RELOC_X86_64_GOTOFF64
:
6189 case BFD_RELOC_X86_64_GOTPC32
:
6190 case BFD_RELOC_X86_64_GOT64
:
6191 case BFD_RELOC_X86_64_GOTPCREL64
:
6192 case BFD_RELOC_X86_64_GOTPC64
:
6193 case BFD_RELOC_X86_64_GOTPLT64
:
6194 case BFD_RELOC_X86_64_PLTOFF64
:
6195 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6196 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6198 case BFD_RELOC_VTABLE_ENTRY
:
6199 case BFD_RELOC_VTABLE_INHERIT
:
6201 case BFD_RELOC_32_SECREL
:
6203 code
= fixp
->fx_r_type
;
6205 case BFD_RELOC_X86_64_32S
:
6206 if (!fixp
->fx_pcrel
)
6208 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6209 code
= fixp
->fx_r_type
;
6215 switch (fixp
->fx_size
)
6218 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6219 _("can not do %d byte pc-relative relocation"),
6221 code
= BFD_RELOC_32_PCREL
;
6223 case 1: code
= BFD_RELOC_8_PCREL
; break;
6224 case 2: code
= BFD_RELOC_16_PCREL
; break;
6225 case 4: code
= BFD_RELOC_32_PCREL
; break;
6227 case 8: code
= BFD_RELOC_64_PCREL
; break;
6233 switch (fixp
->fx_size
)
6236 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6237 _("can not do %d byte relocation"),
6239 code
= BFD_RELOC_32
;
6241 case 1: code
= BFD_RELOC_8
; break;
6242 case 2: code
= BFD_RELOC_16
; break;
6243 case 4: code
= BFD_RELOC_32
; break;
6245 case 8: code
= BFD_RELOC_64
; break;
6252 if ((code
== BFD_RELOC_32
6253 || code
== BFD_RELOC_32_PCREL
6254 || code
== BFD_RELOC_X86_64_32S
)
6256 && fixp
->fx_addsy
== GOT_symbol
)
6259 code
= BFD_RELOC_386_GOTPC
;
6261 code
= BFD_RELOC_X86_64_GOTPC32
;
6263 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6265 && fixp
->fx_addsy
== GOT_symbol
)
6267 code
= BFD_RELOC_X86_64_GOTPC64
;
6270 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6271 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6272 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6274 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6276 if (!use_rela_relocations
)
6278 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6279 vtable entry to be used in the relocation's section offset. */
6280 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6281 rel
->address
= fixp
->fx_offset
;
6285 /* Use the rela in 64bit mode. */
6288 if (!fixp
->fx_pcrel
)
6289 rel
->addend
= fixp
->fx_offset
;
6293 case BFD_RELOC_X86_64_PLT32
:
6294 case BFD_RELOC_X86_64_GOT32
:
6295 case BFD_RELOC_X86_64_GOTPCREL
:
6296 case BFD_RELOC_X86_64_TLSGD
:
6297 case BFD_RELOC_X86_64_TLSLD
:
6298 case BFD_RELOC_X86_64_GOTTPOFF
:
6299 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6300 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6301 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6304 rel
->addend
= (section
->vma
6306 + fixp
->fx_addnumber
6307 + md_pcrel_from (fixp
));
6312 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6313 if (rel
->howto
== NULL
)
6315 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6316 _("cannot represent relocation type %s"),
6317 bfd_get_reloc_code_name (code
));
6318 /* Set howto to a garbage value so that we can keep going. */
6319 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6320 assert (rel
->howto
!= NULL
);
6327 /* Parse operands using Intel syntax. This implements a recursive descent
6328 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6331 FIXME: We do not recognize the full operand grammar defined in the MASM
6332 documentation. In particular, all the structure/union and
6333 high-level macro operands are missing.
6335 Uppercase words are terminals, lower case words are non-terminals.
6336 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6337 bars '|' denote choices. Most grammar productions are implemented in
6338 functions called 'intel_<production>'.
6340 Initial production is 'expr'.
6346 binOp & | AND | \| | OR | ^ | XOR
6348 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6350 constant digits [[ radixOverride ]]
6352 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6390 => expr expr cmpOp e04
6393 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6394 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6396 hexdigit a | b | c | d | e | f
6397 | A | B | C | D | E | F
6403 mulOp * | / | % | MOD | << | SHL | >> | SHR
6407 register specialRegister
6411 segmentRegister CS | DS | ES | FS | GS | SS
6413 specialRegister CR0 | CR2 | CR3 | CR4
6414 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6415 | TR3 | TR4 | TR5 | TR6 | TR7
6417 We simplify the grammar in obvious places (e.g., register parsing is
6418 done by calling parse_register) and eliminate immediate left recursion
6419 to implement a recursive-descent parser.
6423 expr' cmpOp e04 expr'
6474 /* Parsing structure for the intel syntax parser. Used to implement the
6475 semantic actions for the operand grammar. */
6476 struct intel_parser_s
6478 char *op_string
; /* The string being parsed. */
6479 int got_a_float
; /* Whether the operand is a float. */
6480 int op_modifier
; /* Operand modifier. */
6481 int is_mem
; /* 1 if operand is memory reference. */
6482 int in_offset
; /* >=1 if parsing operand of offset. */
6483 int in_bracket
; /* >=1 if parsing operand in brackets. */
6484 const reg_entry
*reg
; /* Last register reference found. */
6485 char *disp
; /* Displacement string being built. */
6486 char *next_operand
; /* Resume point when splitting operands. */
6489 static struct intel_parser_s intel_parser
;
6491 /* Token structure for parsing intel syntax. */
6494 int code
; /* Token code. */
6495 const reg_entry
*reg
; /* Register entry for register tokens. */
6496 char *str
; /* String representation. */
6499 static struct intel_token cur_token
, prev_token
;
6501 /* Token codes for the intel parser. Since T_SHORT is already used
6502 by COFF, undefine it first to prevent a warning. */
6521 /* Prototypes for intel parser functions. */
6522 static int intel_match_token
PARAMS ((int code
));
6523 static void intel_get_token
PARAMS ((void));
6524 static void intel_putback_token
PARAMS ((void));
6525 static int intel_expr
PARAMS ((void));
6526 static int intel_e04
PARAMS ((void));
6527 static int intel_e05
PARAMS ((void));
6528 static int intel_e06
PARAMS ((void));
6529 static int intel_e09
PARAMS ((void));
6530 static int intel_bracket_expr
PARAMS ((void));
6531 static int intel_e10
PARAMS ((void));
6532 static int intel_e11
PARAMS ((void));
6535 i386_intel_operand (operand_string
, got_a_float
)
6536 char *operand_string
;
6542 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6543 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6547 /* Initialize token holders. */
6548 cur_token
.code
= prev_token
.code
= T_NIL
;
6549 cur_token
.reg
= prev_token
.reg
= NULL
;
6550 cur_token
.str
= prev_token
.str
= NULL
;
6552 /* Initialize parser structure. */
6553 intel_parser
.got_a_float
= got_a_float
;
6554 intel_parser
.op_modifier
= 0;
6555 intel_parser
.is_mem
= 0;
6556 intel_parser
.in_offset
= 0;
6557 intel_parser
.in_bracket
= 0;
6558 intel_parser
.reg
= NULL
;
6559 intel_parser
.disp
[0] = '\0';
6560 intel_parser
.next_operand
= NULL
;
6562 /* Read the first token and start the parser. */
6564 ret
= intel_expr ();
6569 if (cur_token
.code
!= T_NIL
)
6571 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6572 current_templates
->start
->name
, cur_token
.str
);
6575 /* If we found a memory reference, hand it over to i386_displacement
6576 to fill in the rest of the operand fields. */
6577 else if (intel_parser
.is_mem
)
6579 if ((i
.mem_operands
== 1
6580 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6581 || i
.mem_operands
== 2)
6583 as_bad (_("too many memory references for '%s'"),
6584 current_templates
->start
->name
);
6589 char *s
= intel_parser
.disp
;
6592 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6593 /* See the comments in intel_bracket_expr. */
6594 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6596 /* Add the displacement expression. */
6598 ret
= i386_displacement (s
, s
+ strlen (s
));
6601 /* Swap base and index in 16-bit memory operands like
6602 [si+bx]. Since i386_index_check is also used in AT&T
6603 mode we have to do that here. */
6606 && (i
.base_reg
->reg_type
& Reg16
)
6607 && (i
.index_reg
->reg_type
& Reg16
)
6608 && i
.base_reg
->reg_num
>= 6
6609 && i
.index_reg
->reg_num
< 6)
6611 const reg_entry
*base
= i
.index_reg
;
6613 i
.index_reg
= i
.base_reg
;
6616 ret
= i386_index_check (operand_string
);
6621 /* Constant and OFFSET expressions are handled by i386_immediate. */
6622 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6623 || intel_parser
.reg
== NULL
)
6624 ret
= i386_immediate (intel_parser
.disp
);
6626 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6628 if (!ret
|| !intel_parser
.next_operand
)
6630 intel_parser
.op_string
= intel_parser
.next_operand
;
6631 this_operand
= i
.operands
++;
6635 free (intel_parser
.disp
);
6640 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6644 expr' cmpOp e04 expr'
6649 /* XXX Implement the comparison operators. */
6650 return intel_e04 ();
6667 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6668 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6670 if (cur_token
.code
== '+')
6672 else if (cur_token
.code
== '-')
6673 nregs
= NUM_ADDRESS_REGS
;
6677 strcat (intel_parser
.disp
, cur_token
.str
);
6678 intel_match_token (cur_token
.code
);
6689 int nregs
= ~NUM_ADDRESS_REGS
;
6696 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6700 str
[0] = cur_token
.code
;
6702 strcat (intel_parser
.disp
, str
);
6707 intel_match_token (cur_token
.code
);
6712 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6713 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6724 int nregs
= ~NUM_ADDRESS_REGS
;
6731 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6735 str
[0] = cur_token
.code
;
6737 strcat (intel_parser
.disp
, str
);
6739 else if (cur_token
.code
== T_SHL
)
6740 strcat (intel_parser
.disp
, "<<");
6741 else if (cur_token
.code
== T_SHR
)
6742 strcat (intel_parser
.disp
, ">>");
6746 intel_match_token (cur_token
.code
);
6751 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6752 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6770 int nregs
= ~NUM_ADDRESS_REGS
;
6775 /* Don't consume constants here. */
6776 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6778 /* Need to look one token ahead - if the next token
6779 is a constant, the current token is its sign. */
6782 intel_match_token (cur_token
.code
);
6783 next_code
= cur_token
.code
;
6784 intel_putback_token ();
6785 if (next_code
== T_CONST
)
6789 /* e09 OFFSET e09 */
6790 if (cur_token
.code
== T_OFFSET
)
6793 ++intel_parser
.in_offset
;
6797 else if (cur_token
.code
== T_SHORT
)
6798 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6801 else if (cur_token
.code
== '+')
6802 strcat (intel_parser
.disp
, "+");
6807 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6813 str
[0] = cur_token
.code
;
6815 strcat (intel_parser
.disp
, str
);
6822 intel_match_token (cur_token
.code
);
6830 /* e09' PTR e10 e09' */
6831 if (cur_token
.code
== T_PTR
)
6835 if (prev_token
.code
== T_BYTE
)
6836 suffix
= BYTE_MNEM_SUFFIX
;
6838 else if (prev_token
.code
== T_WORD
)
6840 if (current_templates
->start
->name
[0] == 'l'
6841 && current_templates
->start
->name
[2] == 's'
6842 && current_templates
->start
->name
[3] == 0)
6843 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6844 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6845 suffix
= SHORT_MNEM_SUFFIX
;
6847 suffix
= WORD_MNEM_SUFFIX
;
6850 else if (prev_token
.code
== T_DWORD
)
6852 if (current_templates
->start
->name
[0] == 'l'
6853 && current_templates
->start
->name
[2] == 's'
6854 && current_templates
->start
->name
[3] == 0)
6855 suffix
= WORD_MNEM_SUFFIX
;
6856 else if (flag_code
== CODE_16BIT
6857 && (current_templates
->start
->opcode_modifier
6858 & (Jump
| JumpDword
)))
6859 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6860 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6861 suffix
= SHORT_MNEM_SUFFIX
;
6863 suffix
= LONG_MNEM_SUFFIX
;
6866 else if (prev_token
.code
== T_FWORD
)
6868 if (current_templates
->start
->name
[0] == 'l'
6869 && current_templates
->start
->name
[2] == 's'
6870 && current_templates
->start
->name
[3] == 0)
6871 suffix
= LONG_MNEM_SUFFIX
;
6872 else if (!intel_parser
.got_a_float
)
6874 if (flag_code
== CODE_16BIT
)
6875 add_prefix (DATA_PREFIX_OPCODE
);
6876 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6879 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6882 else if (prev_token
.code
== T_QWORD
)
6884 if (intel_parser
.got_a_float
== 1) /* "f..." */
6885 suffix
= LONG_MNEM_SUFFIX
;
6887 suffix
= QWORD_MNEM_SUFFIX
;
6890 else if (prev_token
.code
== T_TBYTE
)
6892 if (intel_parser
.got_a_float
== 1)
6893 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6895 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6898 else if (prev_token
.code
== T_XMMWORD
)
6900 /* XXX ignored for now, but accepted since gcc uses it */
6906 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6910 /* Operands for jump/call using 'ptr' notation denote absolute
6912 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6913 i
.types
[this_operand
] |= JumpAbsolute
;
6915 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6919 else if (i
.suffix
!= suffix
)
6921 as_bad (_("Conflicting operand modifiers"));
6927 /* e09' : e10 e09' */
6928 else if (cur_token
.code
== ':')
6930 if (prev_token
.code
!= T_REG
)
6932 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6933 segment/group identifier (which we don't have), using comma
6934 as the operand separator there is even less consistent, since
6935 there all branches only have a single operand. */
6936 if (this_operand
!= 0
6937 || intel_parser
.in_offset
6938 || intel_parser
.in_bracket
6939 || (!(current_templates
->start
->opcode_modifier
6940 & (Jump
|JumpDword
|JumpInterSegment
))
6941 && !(current_templates
->start
->operand_types
[0]
6943 return intel_match_token (T_NIL
);
6944 /* Remember the start of the 2nd operand and terminate 1st
6946 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6947 another expression), but it gets at least the simplest case
6948 (a plain number or symbol on the left side) right. */
6949 intel_parser
.next_operand
= intel_parser
.op_string
;
6950 *--intel_parser
.op_string
= '\0';
6951 return intel_match_token (':');
6959 intel_match_token (cur_token
.code
);
6965 --intel_parser
.in_offset
;
6968 if (NUM_ADDRESS_REGS
> nregs
)
6970 as_bad (_("Invalid operand to `OFFSET'"));
6973 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6976 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6977 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6982 intel_bracket_expr ()
6984 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6985 const char *start
= intel_parser
.op_string
;
6988 if (i
.op
[this_operand
].regs
)
6989 return intel_match_token (T_NIL
);
6991 intel_match_token ('[');
6993 /* Mark as a memory operand only if it's not already known to be an
6994 offset expression. If it's an offset expression, we need to keep
6996 if (!intel_parser
.in_offset
)
6998 ++intel_parser
.in_bracket
;
7000 /* Operands for jump/call inside brackets denote absolute addresses. */
7001 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7002 i
.types
[this_operand
] |= JumpAbsolute
;
7004 /* Unfortunately gas always diverged from MASM in a respect that can't
7005 be easily fixed without risking to break code sequences likely to be
7006 encountered (the testsuite even check for this): MASM doesn't consider
7007 an expression inside brackets unconditionally as a memory reference.
7008 When that is e.g. a constant, an offset expression, or the sum of the
7009 two, this is still taken as a constant load. gas, however, always
7010 treated these as memory references. As a compromise, we'll try to make
7011 offset expressions inside brackets work the MASM way (since that's
7012 less likely to be found in real world code), but make constants alone
7013 continue to work the traditional gas way. In either case, issue a
7015 intel_parser
.op_modifier
&= ~was_offset
;
7018 strcat (intel_parser
.disp
, "[");
7020 /* Add a '+' to the displacement string if necessary. */
7021 if (*intel_parser
.disp
!= '\0'
7022 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7023 strcat (intel_parser
.disp
, "+");
7026 && (len
= intel_parser
.op_string
- start
- 1,
7027 intel_match_token (']')))
7029 /* Preserve brackets when the operand is an offset expression. */
7030 if (intel_parser
.in_offset
)
7031 strcat (intel_parser
.disp
, "]");
7034 --intel_parser
.in_bracket
;
7035 if (i
.base_reg
|| i
.index_reg
)
7036 intel_parser
.is_mem
= 1;
7037 if (!intel_parser
.is_mem
)
7039 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7040 /* Defer the warning until all of the operand was parsed. */
7041 intel_parser
.is_mem
= -1;
7042 else if (!quiet_warnings
)
7043 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
7046 intel_parser
.op_modifier
|= was_offset
;
7063 while (cur_token
.code
== '[')
7065 if (!intel_bracket_expr ())
7090 switch (cur_token
.code
)
7094 intel_match_token ('(');
7095 strcat (intel_parser
.disp
, "(");
7097 if (intel_expr () && intel_match_token (')'))
7099 strcat (intel_parser
.disp
, ")");
7106 return intel_bracket_expr ();
7111 strcat (intel_parser
.disp
, cur_token
.str
);
7112 intel_match_token (cur_token
.code
);
7114 /* Mark as a memory operand only if it's not already known to be an
7115 offset expression. */
7116 if (!intel_parser
.in_offset
)
7117 intel_parser
.is_mem
= 1;
7124 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7126 intel_match_token (T_REG
);
7128 /* Check for segment change. */
7129 if (cur_token
.code
== ':')
7131 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7133 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
7136 else if (i
.seg
[i
.mem_operands
])
7137 as_warn (_("Extra segment override ignored"));
7140 if (!intel_parser
.in_offset
)
7141 intel_parser
.is_mem
= 1;
7142 switch (reg
->reg_num
)
7145 i
.seg
[i
.mem_operands
] = &es
;
7148 i
.seg
[i
.mem_operands
] = &cs
;
7151 i
.seg
[i
.mem_operands
] = &ss
;
7154 i
.seg
[i
.mem_operands
] = &ds
;
7157 i
.seg
[i
.mem_operands
] = &fs
;
7160 i
.seg
[i
.mem_operands
] = &gs
;
7166 /* Not a segment register. Check for register scaling. */
7167 else if (cur_token
.code
== '*')
7169 if (!intel_parser
.in_bracket
)
7171 as_bad (_("Register scaling only allowed in memory operands"));
7175 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7176 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7177 else if (i
.index_reg
)
7178 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7180 /* What follows must be a valid scale. */
7181 intel_match_token ('*');
7183 i
.types
[this_operand
] |= BaseIndex
;
7185 /* Set the scale after setting the register (otherwise,
7186 i386_scale will complain) */
7187 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7189 char *str
, sign
= cur_token
.code
;
7190 intel_match_token (cur_token
.code
);
7191 if (cur_token
.code
!= T_CONST
)
7193 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7197 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7198 strcpy (str
+ 1, cur_token
.str
);
7200 if (!i386_scale (str
))
7204 else if (!i386_scale (cur_token
.str
))
7206 intel_match_token (cur_token
.code
);
7209 /* No scaling. If this is a memory operand, the register is either a
7210 base register (first occurrence) or an index register (second
7212 else if (intel_parser
.in_bracket
)
7217 else if (!i
.index_reg
)
7221 as_bad (_("Too many register references in memory operand"));
7225 i
.types
[this_operand
] |= BaseIndex
;
7228 /* It's neither base nor index. */
7229 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7231 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7232 i
.op
[this_operand
].regs
= reg
;
7237 as_bad (_("Invalid use of register"));
7241 /* Since registers are not part of the displacement string (except
7242 when we're parsing offset operands), we may need to remove any
7243 preceding '+' from the displacement string. */
7244 if (*intel_parser
.disp
!= '\0'
7245 && !intel_parser
.in_offset
)
7247 char *s
= intel_parser
.disp
;
7248 s
+= strlen (s
) - 1;
7271 intel_match_token (cur_token
.code
);
7273 if (cur_token
.code
== T_PTR
)
7276 /* It must have been an identifier. */
7277 intel_putback_token ();
7278 cur_token
.code
= T_ID
;
7284 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7288 /* The identifier represents a memory reference only if it's not
7289 preceded by an offset modifier and if it's not an equate. */
7290 symbolP
= symbol_find(cur_token
.str
);
7291 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7292 intel_parser
.is_mem
= 1;
7300 char *save_str
, sign
= 0;
7302 /* Allow constants that start with `+' or `-'. */
7303 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7305 sign
= cur_token
.code
;
7306 intel_match_token (cur_token
.code
);
7307 if (cur_token
.code
!= T_CONST
)
7309 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7315 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7316 strcpy (save_str
+ !!sign
, cur_token
.str
);
7320 /* Get the next token to check for register scaling. */
7321 intel_match_token (cur_token
.code
);
7323 /* Check if this constant is a scaling factor for an index register. */
7324 if (cur_token
.code
== '*')
7326 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7328 const reg_entry
*reg
= cur_token
.reg
;
7330 if (!intel_parser
.in_bracket
)
7332 as_bad (_("Register scaling only allowed in memory operands"));
7336 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
7337 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7338 else if (i
.index_reg
)
7339 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7341 /* The constant is followed by `* reg', so it must be
7344 i
.types
[this_operand
] |= BaseIndex
;
7346 /* Set the scale after setting the register (otherwise,
7347 i386_scale will complain) */
7348 if (!i386_scale (save_str
))
7350 intel_match_token (T_REG
);
7352 /* Since registers are not part of the displacement
7353 string, we may need to remove any preceding '+' from
7354 the displacement string. */
7355 if (*intel_parser
.disp
!= '\0')
7357 char *s
= intel_parser
.disp
;
7358 s
+= strlen (s
) - 1;
7368 /* The constant was not used for register scaling. Since we have
7369 already consumed the token following `*' we now need to put it
7370 back in the stream. */
7371 intel_putback_token ();
7374 /* Add the constant to the displacement string. */
7375 strcat (intel_parser
.disp
, save_str
);
7382 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7386 /* Match the given token against cur_token. If they match, read the next
7387 token from the operand string. */
7389 intel_match_token (code
)
7392 if (cur_token
.code
== code
)
7399 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7404 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7409 const reg_entry
*reg
;
7410 struct intel_token new_token
;
7412 new_token
.code
= T_NIL
;
7413 new_token
.reg
= NULL
;
7414 new_token
.str
= NULL
;
7416 /* Free the memory allocated to the previous token and move
7417 cur_token to prev_token. */
7419 free (prev_token
.str
);
7421 prev_token
= cur_token
;
7423 /* Skip whitespace. */
7424 while (is_space_char (*intel_parser
.op_string
))
7425 intel_parser
.op_string
++;
7427 /* Return an empty token if we find nothing else on the line. */
7428 if (*intel_parser
.op_string
== '\0')
7430 cur_token
= new_token
;
7434 /* The new token cannot be larger than the remainder of the operand
7436 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7437 new_token
.str
[0] = '\0';
7439 if (strchr ("0123456789", *intel_parser
.op_string
))
7441 char *p
= new_token
.str
;
7442 char *q
= intel_parser
.op_string
;
7443 new_token
.code
= T_CONST
;
7445 /* Allow any kind of identifier char to encompass floating point and
7446 hexadecimal numbers. */
7447 while (is_identifier_char (*q
))
7451 /* Recognize special symbol names [0-9][bf]. */
7452 if (strlen (intel_parser
.op_string
) == 2
7453 && (intel_parser
.op_string
[1] == 'b'
7454 || intel_parser
.op_string
[1] == 'f'))
7455 new_token
.code
= T_ID
;
7458 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7460 size_t len
= end_op
- intel_parser
.op_string
;
7462 new_token
.code
= T_REG
;
7463 new_token
.reg
= reg
;
7465 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7466 new_token
.str
[len
] = '\0';
7469 else if (is_identifier_char (*intel_parser
.op_string
))
7471 char *p
= new_token
.str
;
7472 char *q
= intel_parser
.op_string
;
7474 /* A '.' or '$' followed by an identifier char is an identifier.
7475 Otherwise, it's operator '.' followed by an expression. */
7476 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7478 new_token
.code
= '.';
7479 new_token
.str
[0] = '.';
7480 new_token
.str
[1] = '\0';
7484 while (is_identifier_char (*q
) || *q
== '@')
7488 if (strcasecmp (new_token
.str
, "NOT") == 0)
7489 new_token
.code
= '~';
7491 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7492 new_token
.code
= '%';
7494 else if (strcasecmp (new_token
.str
, "AND") == 0)
7495 new_token
.code
= '&';
7497 else if (strcasecmp (new_token
.str
, "OR") == 0)
7498 new_token
.code
= '|';
7500 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7501 new_token
.code
= '^';
7503 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7504 new_token
.code
= T_SHL
;
7506 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7507 new_token
.code
= T_SHR
;
7509 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7510 new_token
.code
= T_BYTE
;
7512 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7513 new_token
.code
= T_WORD
;
7515 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7516 new_token
.code
= T_DWORD
;
7518 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7519 new_token
.code
= T_FWORD
;
7521 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7522 new_token
.code
= T_QWORD
;
7524 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7525 /* XXX remove (gcc still uses it) */
7526 || strcasecmp (new_token
.str
, "XWORD") == 0)
7527 new_token
.code
= T_TBYTE
;
7529 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7530 || strcasecmp (new_token
.str
, "OWORD") == 0)
7531 new_token
.code
= T_XMMWORD
;
7533 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7534 new_token
.code
= T_PTR
;
7536 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7537 new_token
.code
= T_SHORT
;
7539 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7541 new_token
.code
= T_OFFSET
;
7543 /* ??? This is not mentioned in the MASM grammar but gcc
7544 makes use of it with -mintel-syntax. OFFSET may be
7545 followed by FLAT: */
7546 if (strncasecmp (q
, " FLAT:", 6) == 0)
7547 strcat (new_token
.str
, " FLAT:");
7550 /* ??? This is not mentioned in the MASM grammar. */
7551 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7553 new_token
.code
= T_OFFSET
;
7555 strcat (new_token
.str
, ":");
7557 as_bad (_("`:' expected"));
7561 new_token
.code
= T_ID
;
7565 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7567 new_token
.code
= *intel_parser
.op_string
;
7568 new_token
.str
[0] = *intel_parser
.op_string
;
7569 new_token
.str
[1] = '\0';
7572 else if (strchr ("<>", *intel_parser
.op_string
)
7573 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7575 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7576 new_token
.str
[0] = *intel_parser
.op_string
;
7577 new_token
.str
[1] = *intel_parser
.op_string
;
7578 new_token
.str
[2] = '\0';
7582 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7584 intel_parser
.op_string
+= strlen (new_token
.str
);
7585 cur_token
= new_token
;
7588 /* Put cur_token back into the token stream and make cur_token point to
7591 intel_putback_token ()
7593 if (cur_token
.code
!= T_NIL
)
7595 intel_parser
.op_string
-= strlen (cur_token
.str
);
7596 free (cur_token
.str
);
7598 cur_token
= prev_token
;
7600 /* Forget prev_token. */
7601 prev_token
.code
= T_NIL
;
7602 prev_token
.reg
= NULL
;
7603 prev_token
.str
= NULL
;
7607 tc_x86_regname_to_dw2regnum (char *regname
)
7609 unsigned int regnum
;
7610 unsigned int regnames_count
;
7611 static const char *const regnames_32
[] =
7613 "eax", "ecx", "edx", "ebx",
7614 "esp", "ebp", "esi", "edi",
7615 "eip", "eflags", NULL
,
7616 "st0", "st1", "st2", "st3",
7617 "st4", "st5", "st6", "st7",
7619 "xmm0", "xmm1", "xmm2", "xmm3",
7620 "xmm4", "xmm5", "xmm6", "xmm7",
7621 "mm0", "mm1", "mm2", "mm3",
7622 "mm4", "mm5", "mm6", "mm7",
7623 "fcw", "fsw", "mxcsr",
7624 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7627 static const char *const regnames_64
[] =
7629 "rax", "rdx", "rcx", "rbx",
7630 "rsi", "rdi", "rbp", "rsp",
7631 "r8", "r9", "r10", "r11",
7632 "r12", "r13", "r14", "r15",
7634 "xmm0", "xmm1", "xmm2", "xmm3",
7635 "xmm4", "xmm5", "xmm6", "xmm7",
7636 "xmm8", "xmm9", "xmm10", "xmm11",
7637 "xmm12", "xmm13", "xmm14", "xmm15",
7638 "st0", "st1", "st2", "st3",
7639 "st4", "st5", "st6", "st7",
7640 "mm0", "mm1", "mm2", "mm3",
7641 "mm4", "mm5", "mm6", "mm7",
7643 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7644 "fs.base", "gs.base", NULL
, NULL
,
7646 "mxcsr", "fcw", "fsw"
7648 const char *const *regnames
;
7650 if (flag_code
== CODE_64BIT
)
7652 regnames
= regnames_64
;
7653 regnames_count
= ARRAY_SIZE (regnames_64
);
7657 regnames
= regnames_32
;
7658 regnames_count
= ARRAY_SIZE (regnames_32
);
7661 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7662 if (regnames
[regnum
] != NULL
7663 && strcmp (regname
, regnames
[regnum
]) == 0)
7670 tc_x86_frame_initial_instructions (void)
7672 static unsigned int sp_regno
;
7675 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7678 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7679 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7683 i386_elf_section_type (const char *str
, size_t len
)
7685 if (flag_code
== CODE_64BIT
7686 && len
== sizeof ("unwind") - 1
7687 && strncmp (str
, "unwind", 6) == 0)
7688 return SHT_X86_64_UNWIND
;
7695 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7699 expr
.X_op
= O_secrel
;
7700 expr
.X_add_symbol
= symbol
;
7701 expr
.X_add_number
= 0;
7702 emit_expr (&expr
, size
);
7706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7707 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7710 x86_64_section_letter (int letter
, char **ptr_msg
)
7712 if (flag_code
== CODE_64BIT
)
7715 return SHF_X86_64_LARGE
;
7717 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7720 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7725 x86_64_section_word (char *str
, size_t len
)
7727 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7728 return SHF_X86_64_LARGE
;
7734 handle_large_common (int small ATTRIBUTE_UNUSED
)
7736 if (flag_code
!= CODE_64BIT
)
7738 s_comm_internal (0, elf_common_parse
);
7739 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7743 static segT lbss_section
;
7744 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7745 asection
*saved_bss_section
= bss_section
;
7747 if (lbss_section
== NULL
)
7749 flagword applicable
;
7751 subsegT subseg
= now_subseg
;
7753 /* The .lbss section is for local .largecomm symbols. */
7754 lbss_section
= subseg_new (".lbss", 0);
7755 applicable
= bfd_applicable_section_flags (stdoutput
);
7756 bfd_set_section_flags (stdoutput
, lbss_section
,
7757 applicable
& SEC_ALLOC
);
7758 seg_info (lbss_section
)->bss
= 1;
7760 subseg_set (seg
, subseg
);
7763 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7764 bss_section
= lbss_section
;
7766 s_comm_internal (0, elf_common_parse
);
7768 elf_com_section_ptr
= saved_com_section_ptr
;
7769 bss_section
= saved_bss_section
;
7772 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */