1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands
;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types
[MAX_OPERANDS
];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op
[MAX_OPERANDS
];
311 /* Flags for operands. */
312 unsigned int flags
[MAX_OPERANDS
];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry
*base_reg
;
321 const reg_entry
*index_reg
;
322 unsigned int log2_scale_factor
;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry
*seg
[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes
;
334 unsigned char prefix
[MAX_PREFIXES
];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation
*mask
;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation
*rounding
;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation
*broadcast
;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift
;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default
= 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default
= 0,
372 /* How to encode vector instructions. */
375 vex_encoding_default
= 0,
382 const char *rep_prefix
;
385 const char *hle_prefix
;
387 /* Have BND prefix. */
388 const char *bnd_prefix
;
390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix
;
394 enum i386_error error
;
397 typedef struct _i386_insn i386_insn
;
399 /* Link RC type with corresponding string, that'll be looked for in
408 static const struct RC_name RC_NamesTable
[] =
410 { rne
, STRING_COMMA_LEN ("rn-sae") },
411 { rd
, STRING_COMMA_LEN ("rd-sae") },
412 { ru
, STRING_COMMA_LEN ("ru-sae") },
413 { rz
, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly
, STRING_COMMA_LEN ("sae") },
417 /* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
419 const char extra_symbol_chars
[] = "*%-([{}"
428 #if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
430 && !defined (TE_GNU) \
431 && !defined (TE_LINUX) \
432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars
= "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
445 const char *i386_comment_chars
= "#";
446 #define PREFIX_SEPARATOR '/'
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars
[] = "#/";
459 const char line_separator_chars
[] = ";";
461 /* Chars that can be used to separate mant from exp in floating point
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant
468 const char FLT_CHARS
[] = "fFdDxX";
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars
[256];
472 static char register_chars
[256];
473 static char operand_chars
[256];
474 static char identifier_chars
[256];
475 static char digit_chars
[256];
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack
[32];
493 static char *save_stack_p
;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
499 /* The instruction we're assembling. */
502 /* Possible templates for current insn. */
503 static const templates
*current_templates
;
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
507 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
509 /* Current operand we are working on. */
510 static int this_operand
= -1;
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
520 static enum flag_code flag_code
;
521 static unsigned int object_64bit
;
522 static unsigned int disallow_64bit_reloc
;
523 static int use_rela_relocations
= 0;
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529 /* The ELF ABI to use. */
537 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj
= 0;
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared
= 0;
550 /* 1 for intel syntax,
552 static int intel_syntax
= 0;
554 /* 1 for Intel64 ISA,
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic
= !SYSV386_COMPAT
;
562 /* 1 if support old (<= 2.8.1) versions of gcc. */
563 static int old_gcc
= OLDGCC_COMPAT
;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg
= 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg
= 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix
= 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg
= 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix
= 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence
= 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
592 static enum check_kind
598 sse_check
, operand_check
= check_warning
;
600 /* Register prefix used for error message. */
601 static const char *register_prefix
= "%";
603 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606 static char stackop_size
= '\0';
608 /* Non-zero to optimize code alignment. */
609 int optimize_align_code
= 1;
611 /* Non-zero to quieten some warnings. */
612 static int quiet_warnings
= 0;
615 static const char *cpu_arch_name
= NULL
;
616 static char *cpu_sub_arch_name
= NULL
;
618 /* CPU feature flags. */
619 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
621 /* If we have selected a cpu we are generating instructions for. */
622 static int cpu_arch_tune_set
= 0;
624 /* Cpu we are generating instructions for. */
625 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
627 /* CPU feature flags of cpu we are generating instructions for. */
628 static i386_cpu_flags cpu_arch_tune_flags
;
630 /* CPU instruction set architecture used. */
631 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
633 /* CPU feature flags of instruction set architecture used. */
634 i386_cpu_flags cpu_arch_isa_flags
;
636 /* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638 static unsigned int no_cond_jump_promotion
= 0;
640 /* Encode SSE instructions with VEX prefix. */
641 static unsigned int sse2avx
;
643 /* Encode scalar AVX instructions with specific vector length. */
650 /* Encode scalar EVEX LIG instructions with specific vector length. */
658 /* Encode EVEX WIG instructions with specific evex.w. */
665 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
666 static enum rc_type evexrcig
= rne
;
668 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
669 static symbolS
*GOT_symbol
;
671 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
672 unsigned int x86_dwarf2_return_column
;
674 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675 int x86_cie_data_alignment
;
677 /* Interface to relax_segment.
678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
683 #define UNCOND_JUMP 0
685 #define COND_JUMP86 2
690 #define SMALL16 (SMALL | CODE16)
692 #define BIG16 (BIG | CODE16)
696 #define INLINE __inline__
702 #define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704 #define TYPE_FROM_RELAX_STATE(s) \
706 #define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
709 /* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
717 const relax_typeS md_relax_table
[] =
720 1) most positive reach of this state,
721 2) most negative reach of this state,
722 3) how many bytes this mode will have in the variable part of the frag
723 4) which index into the table to try if we can't fit into this one. */
725 /* UNCOND_JUMP states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
741 /* word conditionals add 3 bytes to frag:
742 1 extra opcode byte, 2 displacement bytes. */
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
756 static const arch_entry cpu_arch
[] =
758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
761 CPU_GENERIC32_FLAGS
, 0 },
762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
763 CPU_GENERIC64_FLAGS
, 0 },
764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
781 CPU_PENTIUMPRO_FLAGS
, 0 },
782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
791 CPU_NOCONA_FLAGS
, 0 },
792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
797 CPU_CORE2_FLAGS
, 1 },
798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
799 CPU_CORE2_FLAGS
, 0 },
800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
801 CPU_COREI7_FLAGS
, 0 },
802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
807 CPU_IAMCU_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
813 CPU_ATHLON_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
821 CPU_AMDFAM10_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
823 CPU_BDVER1_FLAGS
, 0 },
824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
825 CPU_BDVER2_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
827 CPU_BDVER3_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
829 CPU_BDVER4_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
831 CPU_ZNVER1_FLAGS
, 0 },
832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
833 CPU_BTVER1_FLAGS
, 0 },
834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
835 CPU_BTVER2_FLAGS
, 0 },
836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
853 CPU_SSSE3_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
855 CPU_SSE4_1_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
857 CPU_SSE4_2_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
859 CPU_SSE4_2_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
865 CPU_AVX512F_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
867 CPU_AVX512CD_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
869 CPU_AVX512ER_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
871 CPU_AVX512PF_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
873 CPU_AVX512DQ_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
875 CPU_AVX512BW_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
877 CPU_AVX512VL_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
881 CPU_VMFUNC_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
885 CPU_XSAVE_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
887 CPU_XSAVEOPT_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
889 CPU_XSAVEC_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
891 CPU_XSAVES_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
895 CPU_PCLMUL_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
897 CPU_PCLMUL_FLAGS
, 1 },
898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
899 CPU_FSGSBASE_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
901 CPU_RDRND_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
915 CPU_MOVBE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
921 CPU_LZCNT_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
927 CPU_INVPCID_FLAGS
, 0 },
928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
929 CPU_CLFLUSH_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
933 CPU_SYSCALL_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
935 CPU_RDTSCP_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
937 CPU_3DNOW_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
939 CPU_3DNOWA_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
941 CPU_PADLOCK_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
947 CPU_SSE4A_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
957 CPU_RDSEED_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
959 CPU_PRFCHW_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
967 CPU_CLFLUSHOPT_FLAGS
, 0 },
968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
969 CPU_PREFETCHWT1_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
975 CPU_AVX512IFMA_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
977 CPU_AVX512VBMI_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
979 CPU_AVX512_4FMAPS_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
981 CPU_AVX512_4VNNIW_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
983 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
985 CPU_AVX512_VBMI2_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
987 CPU_AVX512_VNNI_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
989 CPU_AVX512_BITALG_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
991 CPU_CLZERO_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
993 CPU_MWAITX_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
995 CPU_OSPKE_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
997 CPU_RDPID_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
999 CPU_PTWRITE_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
1002 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1003 CPU_GFNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1005 CPU_VAES_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1007 CPU_VPCLMULQDQ_FLAGS
, 0 },
1010 static const noarch_entry cpu_noarch
[] =
1012 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1013 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1014 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1015 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1016 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1017 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1018 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1019 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1020 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1021 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1022 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1023 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1024 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1027 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1028 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1029 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1030 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1031 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1032 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1033 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1034 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1035 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1036 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1037 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1038 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1039 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1040 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1044 /* Like s_lcomm_internal in gas/read.c but the alignment string
1045 is allowed to be optional. */
1048 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1055 && *input_line_pointer
== ',')
1057 align
= parse_align (needs_align
- 1);
1059 if (align
== (addressT
) -1)
1074 bss_alloc (symbolP
, size
, align
);
1079 pe_lcomm (int needs_align
)
1081 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1085 const pseudo_typeS md_pseudo_table
[] =
1087 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1088 {"align", s_align_bytes
, 0},
1090 {"align", s_align_ptwo
, 0},
1092 {"arch", set_cpu_arch
, 0},
1096 {"lcomm", pe_lcomm
, 1},
1098 {"ffloat", float_cons
, 'f'},
1099 {"dfloat", float_cons
, 'd'},
1100 {"tfloat", float_cons
, 'x'},
1102 {"slong", signed_cons
, 4},
1103 {"noopt", s_ignore
, 0},
1104 {"optim", s_ignore
, 0},
1105 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1106 {"code16", set_code_flag
, CODE_16BIT
},
1107 {"code32", set_code_flag
, CODE_32BIT
},
1109 {"code64", set_code_flag
, CODE_64BIT
},
1111 {"intel_syntax", set_intel_syntax
, 1},
1112 {"att_syntax", set_intel_syntax
, 0},
1113 {"intel_mnemonic", set_intel_mnemonic
, 1},
1114 {"att_mnemonic", set_intel_mnemonic
, 0},
1115 {"allow_index_reg", set_allow_index_reg
, 1},
1116 {"disallow_index_reg", set_allow_index_reg
, 0},
1117 {"sse_check", set_check
, 0},
1118 {"operand_check", set_check
, 1},
1119 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1120 {"largecomm", handle_large_common
, 0},
1122 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1123 {"loc", dwarf2_directive_loc
, 0},
1124 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1127 {"secrel32", pe_directive_secrel
, 0},
1132 /* For interface with expression (). */
1133 extern char *input_line_pointer
;
1135 /* Hash table for instruction mnemonic lookup. */
1136 static struct hash_control
*op_hash
;
1138 /* Hash table for register lookup. */
1139 static struct hash_control
*reg_hash
;
1142 i386_align_code (fragS
*fragP
, int count
)
1144 /* Various efficient no-op patterns for aligning code labels.
1145 Note: Don't try to assemble the instructions in the comments.
1146 0L and 0w are not legal. */
1147 static const unsigned char f32_1
[] =
1149 static const unsigned char f32_2
[] =
1150 {0x66,0x90}; /* xchg %ax,%ax */
1151 static const unsigned char f32_3
[] =
1152 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1153 static const unsigned char f32_4
[] =
1154 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1155 static const unsigned char f32_5
[] =
1157 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1158 static const unsigned char f32_6
[] =
1159 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1160 static const unsigned char f32_7
[] =
1161 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1162 static const unsigned char f32_8
[] =
1164 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1165 static const unsigned char f32_9
[] =
1166 {0x89,0xf6, /* movl %esi,%esi */
1167 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1168 static const unsigned char f32_10
[] =
1169 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1171 static const unsigned char f32_11
[] =
1172 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1174 static const unsigned char f32_12
[] =
1175 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1176 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1177 static const unsigned char f32_13
[] =
1178 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1179 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1180 static const unsigned char f32_14
[] =
1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1182 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1183 static const unsigned char f16_3
[] =
1184 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1185 static const unsigned char f16_4
[] =
1186 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1187 static const unsigned char f16_5
[] =
1189 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1190 static const unsigned char f16_6
[] =
1191 {0x89,0xf6, /* mov %si,%si */
1192 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1193 static const unsigned char f16_7
[] =
1194 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1195 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1196 static const unsigned char f16_8
[] =
1197 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1198 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1199 static const unsigned char jump_31
[] =
1200 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1204 static const unsigned char *const f32_patt
[] = {
1205 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1206 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1208 static const unsigned char *const f16_patt
[] = {
1209 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1211 /* nopl (%[re]ax) */
1212 static const unsigned char alt_3
[] =
1214 /* nopl 0(%[re]ax) */
1215 static const unsigned char alt_4
[] =
1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_5
[] =
1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
1221 static const unsigned char alt_6
[] =
1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
1224 static const unsigned char alt_7
[] =
1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_8
[] =
1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_9
[] =
1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1233 static const unsigned char alt_10
[] =
1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 static const unsigned char *const alt_patt
[] = {
1236 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1240 /* Only align for at least a positive non-zero boundary. */
1241 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1244 /* We need to decide which NOP sequence to use for 32bit and
1245 64bit. When -mtune= is used:
1247 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1248 PROCESSOR_GENERIC32, f32_patt will be used.
1249 2. For the rest, alt_patt will be used.
1251 When -mtune= isn't used, alt_patt will be used if
1252 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1255 When -march= or .arch is used, we can't use anything beyond
1256 cpu_arch_isa_flags. */
1258 if (flag_code
== CODE_16BIT
)
1262 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1264 /* Adjust jump offset. */
1265 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1268 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1269 f16_patt
[count
- 1], count
);
1273 const unsigned char *const *patt
= NULL
;
1275 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1277 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1278 switch (cpu_arch_tune
)
1280 case PROCESSOR_UNKNOWN
:
1281 /* We use cpu_arch_isa_flags to check if we SHOULD
1282 optimize with nops. */
1283 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1288 case PROCESSOR_PENTIUM4
:
1289 case PROCESSOR_NOCONA
:
1290 case PROCESSOR_CORE
:
1291 case PROCESSOR_CORE2
:
1292 case PROCESSOR_COREI7
:
1293 case PROCESSOR_L1OM
:
1294 case PROCESSOR_K1OM
:
1295 case PROCESSOR_GENERIC64
:
1297 case PROCESSOR_ATHLON
:
1299 case PROCESSOR_AMDFAM10
:
1301 case PROCESSOR_ZNVER
:
1305 case PROCESSOR_I386
:
1306 case PROCESSOR_I486
:
1307 case PROCESSOR_PENTIUM
:
1308 case PROCESSOR_PENTIUMPRO
:
1309 case PROCESSOR_IAMCU
:
1310 case PROCESSOR_GENERIC32
:
1317 switch (fragP
->tc_frag_data
.tune
)
1319 case PROCESSOR_UNKNOWN
:
1320 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1321 PROCESSOR_UNKNOWN. */
1325 case PROCESSOR_I386
:
1326 case PROCESSOR_I486
:
1327 case PROCESSOR_PENTIUM
:
1328 case PROCESSOR_IAMCU
:
1330 case PROCESSOR_ATHLON
:
1332 case PROCESSOR_AMDFAM10
:
1334 case PROCESSOR_ZNVER
:
1336 case PROCESSOR_GENERIC32
:
1337 /* We use cpu_arch_isa_flags to check if we CAN optimize
1339 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1344 case PROCESSOR_PENTIUMPRO
:
1345 case PROCESSOR_PENTIUM4
:
1346 case PROCESSOR_NOCONA
:
1347 case PROCESSOR_CORE
:
1348 case PROCESSOR_CORE2
:
1349 case PROCESSOR_COREI7
:
1350 case PROCESSOR_L1OM
:
1351 case PROCESSOR_K1OM
:
1352 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1357 case PROCESSOR_GENERIC64
:
1363 if (patt
== f32_patt
)
1365 /* If the padding is less than 15 bytes, we use the normal
1366 ones. Otherwise, we use a jump instruction and adjust
1370 /* For 64bit, the limit is 3 bytes. */
1371 if (flag_code
== CODE_64BIT
1372 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1377 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1378 patt
[count
- 1], count
);
1381 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1383 /* Adjust jump offset. */
1384 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1389 /* Maximum length of an instruction is 10 byte. If the
1390 padding is greater than 10 bytes and we don't use jump,
1391 we have to break it into smaller pieces. */
1392 int padding
= count
;
1393 while (padding
> 10)
1396 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1401 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1402 patt
[padding
- 1], padding
);
1405 fragP
->fr_var
= count
;
1409 operand_type_all_zero (const union i386_operand_type
*x
)
1411 switch (ARRAY_SIZE(x
->array
))
1422 return !x
->array
[0];
1429 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1431 switch (ARRAY_SIZE(x
->array
))
1449 operand_type_equal (const union i386_operand_type
*x
,
1450 const union i386_operand_type
*y
)
1452 switch (ARRAY_SIZE(x
->array
))
1455 if (x
->array
[2] != y
->array
[2])
1459 if (x
->array
[1] != y
->array
[1])
1463 return x
->array
[0] == y
->array
[0];
1471 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1473 switch (ARRAY_SIZE(x
->array
))
1488 return !x
->array
[0];
1495 cpu_flags_equal (const union i386_cpu_flags
*x
,
1496 const union i386_cpu_flags
*y
)
1498 switch (ARRAY_SIZE(x
->array
))
1501 if (x
->array
[3] != y
->array
[3])
1505 if (x
->array
[2] != y
->array
[2])
1509 if (x
->array
[1] != y
->array
[1])
1513 return x
->array
[0] == y
->array
[0];
1521 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1523 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1524 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1527 static INLINE i386_cpu_flags
1528 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1530 switch (ARRAY_SIZE (x
.array
))
1533 x
.array
[3] &= y
.array
[3];
1536 x
.array
[2] &= y
.array
[2];
1539 x
.array
[1] &= y
.array
[1];
1542 x
.array
[0] &= y
.array
[0];
1550 static INLINE i386_cpu_flags
1551 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1553 switch (ARRAY_SIZE (x
.array
))
1556 x
.array
[3] |= y
.array
[3];
1559 x
.array
[2] |= y
.array
[2];
1562 x
.array
[1] |= y
.array
[1];
1565 x
.array
[0] |= y
.array
[0];
1573 static INLINE i386_cpu_flags
1574 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1576 switch (ARRAY_SIZE (x
.array
))
1579 x
.array
[3] &= ~y
.array
[3];
1582 x
.array
[2] &= ~y
.array
[2];
1585 x
.array
[1] &= ~y
.array
[1];
1588 x
.array
[0] &= ~y
.array
[0];
1596 #define CPU_FLAGS_ARCH_MATCH 0x1
1597 #define CPU_FLAGS_64BIT_MATCH 0x2
1598 #define CPU_FLAGS_AES_MATCH 0x4
1599 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1600 #define CPU_FLAGS_AVX_MATCH 0x10
1602 #define CPU_FLAGS_32BIT_MATCH \
1603 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1604 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1605 #define CPU_FLAGS_PERFECT_MATCH \
1606 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1608 /* Return CPU flags match bits. */
1611 cpu_flags_match (const insn_template
*t
)
1613 i386_cpu_flags x
= t
->cpu_flags
;
1614 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1616 x
.bitfield
.cpu64
= 0;
1617 x
.bitfield
.cpuno64
= 0;
1619 if (cpu_flags_all_zero (&x
))
1621 /* This instruction is available on all archs. */
1622 match
|= CPU_FLAGS_32BIT_MATCH
;
1626 /* This instruction is available only on some archs. */
1627 i386_cpu_flags cpu
= cpu_arch_flags
;
1629 cpu
= cpu_flags_and (x
, cpu
);
1630 if (!cpu_flags_all_zero (&cpu
))
1632 if (x
.bitfield
.cpuavx
)
1634 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1635 if (cpu
.bitfield
.cpuavx
)
1637 /* Check SSE2AVX. */
1638 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1640 match
|= (CPU_FLAGS_ARCH_MATCH
1641 | CPU_FLAGS_AVX_MATCH
);
1643 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1644 match
|= CPU_FLAGS_AES_MATCH
;
1646 if (!x
.bitfield
.cpupclmul
1647 || cpu
.bitfield
.cpupclmul
)
1648 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1652 match
|= CPU_FLAGS_ARCH_MATCH
;
1654 else if (x
.bitfield
.cpuavx512vl
)
1656 /* Match AVX512VL. */
1657 if (cpu
.bitfield
.cpuavx512vl
)
1659 /* Need another match. */
1660 cpu
.bitfield
.cpuavx512vl
= 0;
1661 if (!cpu_flags_all_zero (&cpu
))
1662 match
|= CPU_FLAGS_32BIT_MATCH
;
1664 match
|= CPU_FLAGS_ARCH_MATCH
;
1667 match
|= CPU_FLAGS_ARCH_MATCH
;
1670 match
|= CPU_FLAGS_32BIT_MATCH
;
1676 static INLINE i386_operand_type
1677 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1679 switch (ARRAY_SIZE (x
.array
))
1682 x
.array
[2] &= y
.array
[2];
1685 x
.array
[1] &= y
.array
[1];
1688 x
.array
[0] &= y
.array
[0];
1696 static INLINE i386_operand_type
1697 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1699 switch (ARRAY_SIZE (x
.array
))
1702 x
.array
[2] |= y
.array
[2];
1705 x
.array
[1] |= y
.array
[1];
1708 x
.array
[0] |= y
.array
[0];
1716 static INLINE i386_operand_type
1717 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1719 switch (ARRAY_SIZE (x
.array
))
1722 x
.array
[2] ^= y
.array
[2];
1725 x
.array
[1] ^= y
.array
[1];
1728 x
.array
[0] ^= y
.array
[0];
1736 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1737 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1738 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1739 static const i386_operand_type inoutportreg
1740 = OPERAND_TYPE_INOUTPORTREG
;
1741 static const i386_operand_type reg16_inoutportreg
1742 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1743 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1744 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1745 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1746 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1747 static const i386_operand_type anydisp
1748 = OPERAND_TYPE_ANYDISP
;
1749 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1750 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1751 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1752 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1753 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1754 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1755 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1756 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1757 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1758 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1759 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1760 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1761 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1762 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1773 operand_type_check (i386_operand_type t
, enum operand_type c
)
1778 return (t
.bitfield
.reg8
1781 || t
.bitfield
.reg64
);
1784 return (t
.bitfield
.imm8
1788 || t
.bitfield
.imm32s
1789 || t
.bitfield
.imm64
);
1792 return (t
.bitfield
.disp8
1793 || t
.bitfield
.disp16
1794 || t
.bitfield
.disp32
1795 || t
.bitfield
.disp32s
1796 || t
.bitfield
.disp64
);
1799 return (t
.bitfield
.disp8
1800 || t
.bitfield
.disp16
1801 || t
.bitfield
.disp32
1802 || t
.bitfield
.disp32s
1803 || t
.bitfield
.disp64
1804 || t
.bitfield
.baseindex
);
1813 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1814 operand J for instruction template T. */
1817 match_reg_size (const insn_template
*t
, unsigned int j
)
1819 return !((i
.types
[j
].bitfield
.byte
1820 && !t
->operand_types
[j
].bitfield
.byte
)
1821 || (i
.types
[j
].bitfield
.word
1822 && !t
->operand_types
[j
].bitfield
.word
)
1823 || (i
.types
[j
].bitfield
.dword
1824 && !t
->operand_types
[j
].bitfield
.dword
)
1825 || (i
.types
[j
].bitfield
.qword
1826 && !t
->operand_types
[j
].bitfield
.qword
));
1829 /* Return 1 if there is no conflict in any size on operand J for
1830 instruction template T. */
1833 match_mem_size (const insn_template
*t
, unsigned int j
)
1835 return (match_reg_size (t
, j
)
1836 && !((i
.types
[j
].bitfield
.unspecified
1838 && !t
->operand_types
[j
].bitfield
.unspecified
)
1839 || (i
.types
[j
].bitfield
.fword
1840 && !t
->operand_types
[j
].bitfield
.fword
)
1841 || (i
.types
[j
].bitfield
.tbyte
1842 && !t
->operand_types
[j
].bitfield
.tbyte
)
1843 || (i
.types
[j
].bitfield
.xmmword
1844 && !t
->operand_types
[j
].bitfield
.xmmword
)
1845 || (i
.types
[j
].bitfield
.ymmword
1846 && !t
->operand_types
[j
].bitfield
.ymmword
)
1847 || (i
.types
[j
].bitfield
.zmmword
1848 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1851 /* Return 1 if there is no size conflict on any operands for
1852 instruction template T. */
1855 operand_size_match (const insn_template
*t
)
1860 /* Don't check jump instructions. */
1861 if (t
->opcode_modifier
.jump
1862 || t
->opcode_modifier
.jumpbyte
1863 || t
->opcode_modifier
.jumpdword
1864 || t
->opcode_modifier
.jumpintersegment
)
1867 /* Check memory and accumulator operand size. */
1868 for (j
= 0; j
< i
.operands
; j
++)
1870 if (t
->operand_types
[j
].bitfield
.anysize
)
1873 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1879 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1888 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1891 i
.error
= operand_size_mismatch
;
1895 /* Check reverse. */
1896 gas_assert (i
.operands
== 2);
1899 for (j
= 0; j
< 2; j
++)
1901 if (t
->operand_types
[j
].bitfield
.acc
1902 && !match_reg_size (t
, j
? 0 : 1))
1905 if (i
.types
[j
].bitfield
.mem
1906 && !match_mem_size (t
, j
? 0 : 1))
1914 operand_type_match (i386_operand_type overlap
,
1915 i386_operand_type given
)
1917 i386_operand_type temp
= overlap
;
1919 temp
.bitfield
.jumpabsolute
= 0;
1920 temp
.bitfield
.unspecified
= 0;
1921 temp
.bitfield
.byte
= 0;
1922 temp
.bitfield
.word
= 0;
1923 temp
.bitfield
.dword
= 0;
1924 temp
.bitfield
.fword
= 0;
1925 temp
.bitfield
.qword
= 0;
1926 temp
.bitfield
.tbyte
= 0;
1927 temp
.bitfield
.xmmword
= 0;
1928 temp
.bitfield
.ymmword
= 0;
1929 temp
.bitfield
.zmmword
= 0;
1930 if (operand_type_all_zero (&temp
))
1933 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1934 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1938 i
.error
= operand_type_mismatch
;
1942 /* If given types g0 and g1 are registers they must be of the same type
1943 unless the expected operand type register overlap is null.
1944 Note that Acc in a template matches every size of reg. */
1947 operand_type_register_match (i386_operand_type m0
,
1948 i386_operand_type g0
,
1949 i386_operand_type t0
,
1950 i386_operand_type m1
,
1951 i386_operand_type g1
,
1952 i386_operand_type t1
)
1954 if (!operand_type_check (g0
, reg
))
1957 if (!operand_type_check (g1
, reg
))
1960 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1961 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1962 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1963 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1966 if (m0
.bitfield
.acc
)
1968 t0
.bitfield
.reg8
= 1;
1969 t0
.bitfield
.reg16
= 1;
1970 t0
.bitfield
.reg32
= 1;
1971 t0
.bitfield
.reg64
= 1;
1974 if (m1
.bitfield
.acc
)
1976 t1
.bitfield
.reg8
= 1;
1977 t1
.bitfield
.reg16
= 1;
1978 t1
.bitfield
.reg32
= 1;
1979 t1
.bitfield
.reg64
= 1;
1982 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1983 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1984 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1985 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1988 i
.error
= register_type_mismatch
;
1993 static INLINE
unsigned int
1994 register_number (const reg_entry
*r
)
1996 unsigned int nr
= r
->reg_num
;
1998 if (r
->reg_flags
& RegRex
)
2001 if (r
->reg_flags
& RegVRex
)
2007 static INLINE
unsigned int
2008 mode_from_disp_size (i386_operand_type t
)
2010 if (t
.bitfield
.disp8
)
2012 else if (t
.bitfield
.disp16
2013 || t
.bitfield
.disp32
2014 || t
.bitfield
.disp32s
)
2021 fits_in_signed_byte (addressT num
)
2023 return num
+ 0x80 <= 0xff;
2027 fits_in_unsigned_byte (addressT num
)
2033 fits_in_unsigned_word (addressT num
)
2035 return num
<= 0xffff;
2039 fits_in_signed_word (addressT num
)
2041 return num
+ 0x8000 <= 0xffff;
2045 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2050 return num
+ 0x80000000 <= 0xffffffff;
2052 } /* fits_in_signed_long() */
2055 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2060 return num
<= 0xffffffff;
2062 } /* fits_in_unsigned_long() */
2065 fits_in_disp8 (offsetT num
)
2067 int shift
= i
.memshift
;
2073 mask
= (1 << shift
) - 1;
2075 /* Return 0 if NUM isn't properly aligned. */
2079 /* Check if NUM will fit in 8bit after shift. */
2080 return fits_in_signed_byte (num
>> shift
);
2084 fits_in_imm4 (offsetT num
)
2086 return (num
& 0xf) == num
;
2089 static i386_operand_type
2090 smallest_imm_type (offsetT num
)
2092 i386_operand_type t
;
2094 operand_type_set (&t
, 0);
2095 t
.bitfield
.imm64
= 1;
2097 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2099 /* This code is disabled on the 486 because all the Imm1 forms
2100 in the opcode table are slower on the i486. They're the
2101 versions with the implicitly specified single-position
2102 displacement, which has another syntax if you really want to
2104 t
.bitfield
.imm1
= 1;
2105 t
.bitfield
.imm8
= 1;
2106 t
.bitfield
.imm8s
= 1;
2107 t
.bitfield
.imm16
= 1;
2108 t
.bitfield
.imm32
= 1;
2109 t
.bitfield
.imm32s
= 1;
2111 else if (fits_in_signed_byte (num
))
2113 t
.bitfield
.imm8
= 1;
2114 t
.bitfield
.imm8s
= 1;
2115 t
.bitfield
.imm16
= 1;
2116 t
.bitfield
.imm32
= 1;
2117 t
.bitfield
.imm32s
= 1;
2119 else if (fits_in_unsigned_byte (num
))
2121 t
.bitfield
.imm8
= 1;
2122 t
.bitfield
.imm16
= 1;
2123 t
.bitfield
.imm32
= 1;
2124 t
.bitfield
.imm32s
= 1;
2126 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2128 t
.bitfield
.imm16
= 1;
2129 t
.bitfield
.imm32
= 1;
2130 t
.bitfield
.imm32s
= 1;
2132 else if (fits_in_signed_long (num
))
2134 t
.bitfield
.imm32
= 1;
2135 t
.bitfield
.imm32s
= 1;
2137 else if (fits_in_unsigned_long (num
))
2138 t
.bitfield
.imm32
= 1;
2144 offset_in_range (offsetT val
, int size
)
2150 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2151 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2152 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2154 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2160 /* If BFD64, sign extend val for 32bit address mode. */
2161 if (flag_code
!= CODE_64BIT
2162 || i
.prefix
[ADDR_PREFIX
])
2163 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2164 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2167 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2169 char buf1
[40], buf2
[40];
2171 sprint_value (buf1
, val
);
2172 sprint_value (buf2
, val
& mask
);
2173 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2188 a. PREFIX_EXIST if attempting to add a prefix where one from the
2189 same class already exists.
2190 b. PREFIX_LOCK if lock prefix is added.
2191 c. PREFIX_REP if rep/repne prefix is added.
2192 d. PREFIX_DS if ds prefix is added.
2193 e. PREFIX_OTHER if other prefix is added.
2196 static enum PREFIX_GROUP
2197 add_prefix (unsigned int prefix
)
2199 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2202 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2203 && flag_code
== CODE_64BIT
)
2205 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2206 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2207 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2218 case DS_PREFIX_OPCODE
:
2221 case CS_PREFIX_OPCODE
:
2222 case ES_PREFIX_OPCODE
:
2223 case FS_PREFIX_OPCODE
:
2224 case GS_PREFIX_OPCODE
:
2225 case SS_PREFIX_OPCODE
:
2229 case REPNE_PREFIX_OPCODE
:
2230 case REPE_PREFIX_OPCODE
:
2235 case LOCK_PREFIX_OPCODE
:
2244 case ADDR_PREFIX_OPCODE
:
2248 case DATA_PREFIX_OPCODE
:
2252 if (i
.prefix
[q
] != 0)
2260 i
.prefix
[q
] |= prefix
;
2263 as_bad (_("same type of prefix used twice"));
2269 update_code_flag (int value
, int check
)
2271 PRINTF_LIKE ((*as_error
));
2273 flag_code
= (enum flag_code
) value
;
2274 if (flag_code
== CODE_64BIT
)
2276 cpu_arch_flags
.bitfield
.cpu64
= 1;
2277 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2281 cpu_arch_flags
.bitfield
.cpu64
= 0;
2282 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2284 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2287 as_error
= as_fatal
;
2290 (*as_error
) (_("64bit mode not supported on `%s'."),
2291 cpu_arch_name
? cpu_arch_name
: default_arch
);
2293 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2296 as_error
= as_fatal
;
2299 (*as_error
) (_("32bit mode not supported on `%s'."),
2300 cpu_arch_name
? cpu_arch_name
: default_arch
);
2302 stackop_size
= '\0';
2306 set_code_flag (int value
)
2308 update_code_flag (value
, 0);
2312 set_16bit_gcc_code_flag (int new_code_flag
)
2314 flag_code
= (enum flag_code
) new_code_flag
;
2315 if (flag_code
!= CODE_16BIT
)
2317 cpu_arch_flags
.bitfield
.cpu64
= 0;
2318 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2319 stackop_size
= LONG_MNEM_SUFFIX
;
2323 set_intel_syntax (int syntax_flag
)
2325 /* Find out if register prefixing is specified. */
2326 int ask_naked_reg
= 0;
2329 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2332 int e
= get_symbol_name (&string
);
2334 if (strcmp (string
, "prefix") == 0)
2336 else if (strcmp (string
, "noprefix") == 0)
2339 as_bad (_("bad argument to syntax directive."));
2340 (void) restore_line_pointer (e
);
2342 demand_empty_rest_of_line ();
2344 intel_syntax
= syntax_flag
;
2346 if (ask_naked_reg
== 0)
2347 allow_naked_reg
= (intel_syntax
2348 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2350 allow_naked_reg
= (ask_naked_reg
< 0);
2352 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2354 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2355 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2356 register_prefix
= allow_naked_reg
? "" : "%";
2360 set_intel_mnemonic (int mnemonic_flag
)
2362 intel_mnemonic
= mnemonic_flag
;
2366 set_allow_index_reg (int flag
)
2368 allow_index_reg
= flag
;
2372 set_check (int what
)
2374 enum check_kind
*kind
;
2379 kind
= &operand_check
;
2390 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2393 int e
= get_symbol_name (&string
);
2395 if (strcmp (string
, "none") == 0)
2397 else if (strcmp (string
, "warning") == 0)
2398 *kind
= check_warning
;
2399 else if (strcmp (string
, "error") == 0)
2400 *kind
= check_error
;
2402 as_bad (_("bad argument to %s_check directive."), str
);
2403 (void) restore_line_pointer (e
);
2406 as_bad (_("missing argument for %s_check directive"), str
);
2408 demand_empty_rest_of_line ();
2412 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2413 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2415 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2416 static const char *arch
;
2418 /* Intel LIOM is only supported on ELF. */
2424 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2425 use default_arch. */
2426 arch
= cpu_arch_name
;
2428 arch
= default_arch
;
2431 /* If we are targeting Intel MCU, we must enable it. */
2432 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2433 || new_flag
.bitfield
.cpuiamcu
)
2436 /* If we are targeting Intel L1OM, we must enable it. */
2437 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2438 || new_flag
.bitfield
.cpul1om
)
2441 /* If we are targeting Intel K1OM, we must enable it. */
2442 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2443 || new_flag
.bitfield
.cpuk1om
)
2446 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2451 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2455 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2458 int e
= get_symbol_name (&string
);
2460 i386_cpu_flags flags
;
2462 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2464 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2466 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2470 cpu_arch_name
= cpu_arch
[j
].name
;
2471 cpu_sub_arch_name
= NULL
;
2472 cpu_arch_flags
= cpu_arch
[j
].flags
;
2473 if (flag_code
== CODE_64BIT
)
2475 cpu_arch_flags
.bitfield
.cpu64
= 1;
2476 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2480 cpu_arch_flags
.bitfield
.cpu64
= 0;
2481 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2483 cpu_arch_isa
= cpu_arch
[j
].type
;
2484 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2485 if (!cpu_arch_tune_set
)
2487 cpu_arch_tune
= cpu_arch_isa
;
2488 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2493 flags
= cpu_flags_or (cpu_arch_flags
,
2496 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2498 if (cpu_sub_arch_name
)
2500 char *name
= cpu_sub_arch_name
;
2501 cpu_sub_arch_name
= concat (name
,
2503 (const char *) NULL
);
2507 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2508 cpu_arch_flags
= flags
;
2509 cpu_arch_isa_flags
= flags
;
2511 (void) restore_line_pointer (e
);
2512 demand_empty_rest_of_line ();
2517 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2519 /* Disable an ISA extension. */
2520 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2521 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2523 flags
= cpu_flags_and_not (cpu_arch_flags
,
2524 cpu_noarch
[j
].flags
);
2525 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2527 if (cpu_sub_arch_name
)
2529 char *name
= cpu_sub_arch_name
;
2530 cpu_sub_arch_name
= concat (name
, string
,
2531 (const char *) NULL
);
2535 cpu_sub_arch_name
= xstrdup (string
);
2536 cpu_arch_flags
= flags
;
2537 cpu_arch_isa_flags
= flags
;
2539 (void) restore_line_pointer (e
);
2540 demand_empty_rest_of_line ();
2544 j
= ARRAY_SIZE (cpu_arch
);
2547 if (j
>= ARRAY_SIZE (cpu_arch
))
2548 as_bad (_("no such architecture: `%s'"), string
);
2550 *input_line_pointer
= e
;
2553 as_bad (_("missing cpu architecture"));
2555 no_cond_jump_promotion
= 0;
2556 if (*input_line_pointer
== ','
2557 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2562 ++input_line_pointer
;
2563 e
= get_symbol_name (&string
);
2565 if (strcmp (string
, "nojumps") == 0)
2566 no_cond_jump_promotion
= 1;
2567 else if (strcmp (string
, "jumps") == 0)
2570 as_bad (_("no such architecture modifier: `%s'"), string
);
2572 (void) restore_line_pointer (e
);
2575 demand_empty_rest_of_line ();
2578 enum bfd_architecture
2581 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2583 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2584 || flag_code
!= CODE_64BIT
)
2585 as_fatal (_("Intel L1OM is 64bit ELF only"));
2586 return bfd_arch_l1om
;
2588 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2590 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2591 || flag_code
!= CODE_64BIT
)
2592 as_fatal (_("Intel K1OM is 64bit ELF only"));
2593 return bfd_arch_k1om
;
2595 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2597 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2598 || flag_code
== CODE_64BIT
)
2599 as_fatal (_("Intel MCU is 32bit ELF only"));
2600 return bfd_arch_iamcu
;
2603 return bfd_arch_i386
;
2609 if (!strncmp (default_arch
, "x86_64", 6))
2611 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2613 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2614 || default_arch
[6] != '\0')
2615 as_fatal (_("Intel L1OM is 64bit ELF only"));
2616 return bfd_mach_l1om
;
2618 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2620 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2621 || default_arch
[6] != '\0')
2622 as_fatal (_("Intel K1OM is 64bit ELF only"));
2623 return bfd_mach_k1om
;
2625 else if (default_arch
[6] == '\0')
2626 return bfd_mach_x86_64
;
2628 return bfd_mach_x64_32
;
2630 else if (!strcmp (default_arch
, "i386")
2631 || !strcmp (default_arch
, "iamcu"))
2633 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2635 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2636 as_fatal (_("Intel MCU is 32bit ELF only"));
2637 return bfd_mach_i386_iamcu
;
2640 return bfd_mach_i386_i386
;
2643 as_fatal (_("unknown architecture"));
2649 const char *hash_err
;
2651 /* Support pseudo prefixes like {disp32}. */
2652 lex_type
['{'] = LEX_BEGIN_NAME
;
2654 /* Initialize op_hash hash table. */
2655 op_hash
= hash_new ();
2658 const insn_template
*optab
;
2659 templates
*core_optab
;
2661 /* Setup for loop. */
2663 core_optab
= XNEW (templates
);
2664 core_optab
->start
= optab
;
2669 if (optab
->name
== NULL
2670 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2672 /* different name --> ship out current template list;
2673 add to hash table; & begin anew. */
2674 core_optab
->end
= optab
;
2675 hash_err
= hash_insert (op_hash
,
2677 (void *) core_optab
);
2680 as_fatal (_("can't hash %s: %s"),
2684 if (optab
->name
== NULL
)
2686 core_optab
= XNEW (templates
);
2687 core_optab
->start
= optab
;
2692 /* Initialize reg_hash hash table. */
2693 reg_hash
= hash_new ();
2695 const reg_entry
*regtab
;
2696 unsigned int regtab_size
= i386_regtab_size
;
2698 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2700 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2702 as_fatal (_("can't hash %s: %s"),
2708 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2713 for (c
= 0; c
< 256; c
++)
2718 mnemonic_chars
[c
] = c
;
2719 register_chars
[c
] = c
;
2720 operand_chars
[c
] = c
;
2722 else if (ISLOWER (c
))
2724 mnemonic_chars
[c
] = c
;
2725 register_chars
[c
] = c
;
2726 operand_chars
[c
] = c
;
2728 else if (ISUPPER (c
))
2730 mnemonic_chars
[c
] = TOLOWER (c
);
2731 register_chars
[c
] = mnemonic_chars
[c
];
2732 operand_chars
[c
] = c
;
2734 else if (c
== '{' || c
== '}')
2736 mnemonic_chars
[c
] = c
;
2737 operand_chars
[c
] = c
;
2740 if (ISALPHA (c
) || ISDIGIT (c
))
2741 identifier_chars
[c
] = c
;
2744 identifier_chars
[c
] = c
;
2745 operand_chars
[c
] = c
;
2750 identifier_chars
['@'] = '@';
2753 identifier_chars
['?'] = '?';
2754 operand_chars
['?'] = '?';
2756 digit_chars
['-'] = '-';
2757 mnemonic_chars
['_'] = '_';
2758 mnemonic_chars
['-'] = '-';
2759 mnemonic_chars
['.'] = '.';
2760 identifier_chars
['_'] = '_';
2761 identifier_chars
['.'] = '.';
2763 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2764 operand_chars
[(unsigned char) *p
] = *p
;
2767 if (flag_code
== CODE_64BIT
)
2769 #if defined (OBJ_COFF) && defined (TE_PE)
2770 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2773 x86_dwarf2_return_column
= 16;
2775 x86_cie_data_alignment
= -8;
2779 x86_dwarf2_return_column
= 8;
2780 x86_cie_data_alignment
= -4;
2785 i386_print_statistics (FILE *file
)
2787 hash_print_statistics (file
, "i386 opcode", op_hash
);
2788 hash_print_statistics (file
, "i386 register", reg_hash
);
2793 /* Debugging routines for md_assemble. */
2794 static void pte (insn_template
*);
2795 static void pt (i386_operand_type
);
2796 static void pe (expressionS
*);
2797 static void ps (symbolS
*);
2800 pi (char *line
, i386_insn
*x
)
2804 fprintf (stdout
, "%s: template ", line
);
2806 fprintf (stdout
, " address: base %s index %s scale %x\n",
2807 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2808 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2809 x
->log2_scale_factor
);
2810 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2811 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2812 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2813 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2814 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2815 (x
->rex
& REX_W
) != 0,
2816 (x
->rex
& REX_R
) != 0,
2817 (x
->rex
& REX_X
) != 0,
2818 (x
->rex
& REX_B
) != 0);
2819 for (j
= 0; j
< x
->operands
; j
++)
2821 fprintf (stdout
, " #%d: ", j
+ 1);
2823 fprintf (stdout
, "\n");
2824 if (x
->types
[j
].bitfield
.reg8
2825 || x
->types
[j
].bitfield
.reg16
2826 || x
->types
[j
].bitfield
.reg32
2827 || x
->types
[j
].bitfield
.reg64
2828 || x
->types
[j
].bitfield
.regmmx
2829 || x
->types
[j
].bitfield
.regxmm
2830 || x
->types
[j
].bitfield
.regymm
2831 || x
->types
[j
].bitfield
.regzmm
2832 || x
->types
[j
].bitfield
.sreg2
2833 || x
->types
[j
].bitfield
.sreg3
2834 || x
->types
[j
].bitfield
.control
2835 || x
->types
[j
].bitfield
.debug
2836 || x
->types
[j
].bitfield
.test
)
2837 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2838 if (operand_type_check (x
->types
[j
], imm
))
2840 if (operand_type_check (x
->types
[j
], disp
))
2841 pe (x
->op
[j
].disps
);
2846 pte (insn_template
*t
)
2849 fprintf (stdout
, " %d operands ", t
->operands
);
2850 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2851 if (t
->extension_opcode
!= None
)
2852 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2853 if (t
->opcode_modifier
.d
)
2854 fprintf (stdout
, "D");
2855 if (t
->opcode_modifier
.w
)
2856 fprintf (stdout
, "W");
2857 fprintf (stdout
, "\n");
2858 for (j
= 0; j
< t
->operands
; j
++)
2860 fprintf (stdout
, " #%d type ", j
+ 1);
2861 pt (t
->operand_types
[j
]);
2862 fprintf (stdout
, "\n");
2869 fprintf (stdout
, " operation %d\n", e
->X_op
);
2870 fprintf (stdout
, " add_number %ld (%lx)\n",
2871 (long) e
->X_add_number
, (long) e
->X_add_number
);
2872 if (e
->X_add_symbol
)
2874 fprintf (stdout
, " add_symbol ");
2875 ps (e
->X_add_symbol
);
2876 fprintf (stdout
, "\n");
2880 fprintf (stdout
, " op_symbol ");
2881 ps (e
->X_op_symbol
);
2882 fprintf (stdout
, "\n");
2889 fprintf (stdout
, "%s type %s%s",
2891 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2892 segment_name (S_GET_SEGMENT (s
)));
2895 static struct type_name
2897 i386_operand_type mask
;
2900 const type_names
[] =
2902 { OPERAND_TYPE_REG8
, "r8" },
2903 { OPERAND_TYPE_REG16
, "r16" },
2904 { OPERAND_TYPE_REG32
, "r32" },
2905 { OPERAND_TYPE_REG64
, "r64" },
2906 { OPERAND_TYPE_IMM8
, "i8" },
2907 { OPERAND_TYPE_IMM8
, "i8s" },
2908 { OPERAND_TYPE_IMM16
, "i16" },
2909 { OPERAND_TYPE_IMM32
, "i32" },
2910 { OPERAND_TYPE_IMM32S
, "i32s" },
2911 { OPERAND_TYPE_IMM64
, "i64" },
2912 { OPERAND_TYPE_IMM1
, "i1" },
2913 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2914 { OPERAND_TYPE_DISP8
, "d8" },
2915 { OPERAND_TYPE_DISP16
, "d16" },
2916 { OPERAND_TYPE_DISP32
, "d32" },
2917 { OPERAND_TYPE_DISP32S
, "d32s" },
2918 { OPERAND_TYPE_DISP64
, "d64" },
2919 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2920 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2921 { OPERAND_TYPE_CONTROL
, "control reg" },
2922 { OPERAND_TYPE_TEST
, "test reg" },
2923 { OPERAND_TYPE_DEBUG
, "debug reg" },
2924 { OPERAND_TYPE_FLOATREG
, "FReg" },
2925 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2926 { OPERAND_TYPE_SREG2
, "SReg2" },
2927 { OPERAND_TYPE_SREG3
, "SReg3" },
2928 { OPERAND_TYPE_ACC
, "Acc" },
2929 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2930 { OPERAND_TYPE_REGMMX
, "rMMX" },
2931 { OPERAND_TYPE_REGXMM
, "rXMM" },
2932 { OPERAND_TYPE_REGYMM
, "rYMM" },
2933 { OPERAND_TYPE_REGZMM
, "rZMM" },
2934 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2935 { OPERAND_TYPE_ESSEG
, "es" },
2939 pt (i386_operand_type t
)
2942 i386_operand_type a
;
2944 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2946 a
= operand_type_and (t
, type_names
[j
].mask
);
2947 if (!operand_type_all_zero (&a
))
2948 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2953 #endif /* DEBUG386 */
2955 static bfd_reloc_code_real_type
2956 reloc (unsigned int size
,
2959 bfd_reloc_code_real_type other
)
2961 if (other
!= NO_RELOC
)
2963 reloc_howto_type
*rel
;
2968 case BFD_RELOC_X86_64_GOT32
:
2969 return BFD_RELOC_X86_64_GOT64
;
2971 case BFD_RELOC_X86_64_GOTPLT64
:
2972 return BFD_RELOC_X86_64_GOTPLT64
;
2974 case BFD_RELOC_X86_64_PLTOFF64
:
2975 return BFD_RELOC_X86_64_PLTOFF64
;
2977 case BFD_RELOC_X86_64_GOTPC32
:
2978 other
= BFD_RELOC_X86_64_GOTPC64
;
2980 case BFD_RELOC_X86_64_GOTPCREL
:
2981 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2983 case BFD_RELOC_X86_64_TPOFF32
:
2984 other
= BFD_RELOC_X86_64_TPOFF64
;
2986 case BFD_RELOC_X86_64_DTPOFF32
:
2987 other
= BFD_RELOC_X86_64_DTPOFF64
;
2993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2994 if (other
== BFD_RELOC_SIZE32
)
2997 other
= BFD_RELOC_SIZE64
;
3000 as_bad (_("there are no pc-relative size relocations"));
3006 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3007 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3010 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3012 as_bad (_("unknown relocation (%u)"), other
);
3013 else if (size
!= bfd_get_reloc_size (rel
))
3014 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3015 bfd_get_reloc_size (rel
),
3017 else if (pcrel
&& !rel
->pc_relative
)
3018 as_bad (_("non-pc-relative relocation for pc-relative field"));
3019 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3021 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3023 as_bad (_("relocated field and relocation type differ in signedness"));
3032 as_bad (_("there are no unsigned pc-relative relocations"));
3035 case 1: return BFD_RELOC_8_PCREL
;
3036 case 2: return BFD_RELOC_16_PCREL
;
3037 case 4: return BFD_RELOC_32_PCREL
;
3038 case 8: return BFD_RELOC_64_PCREL
;
3040 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3047 case 4: return BFD_RELOC_X86_64_32S
;
3052 case 1: return BFD_RELOC_8
;
3053 case 2: return BFD_RELOC_16
;
3054 case 4: return BFD_RELOC_32
;
3055 case 8: return BFD_RELOC_64
;
3057 as_bad (_("cannot do %s %u byte relocation"),
3058 sign
> 0 ? "signed" : "unsigned", size
);
3064 /* Here we decide which fixups can be adjusted to make them relative to
3065 the beginning of the section instead of the symbol. Basically we need
3066 to make sure that the dynamic relocations are done correctly, so in
3067 some cases we force the original symbol to be used. */
3070 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3076 /* Don't adjust pc-relative references to merge sections in 64-bit
3078 if (use_rela_relocations
3079 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3083 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3084 and changed later by validate_fix. */
3085 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3086 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3089 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3090 for size relocations. */
3091 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3092 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3093 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3094 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3095 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3096 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3097 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3098 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3099 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3100 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3101 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3102 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3103 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3104 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3105 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3106 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3107 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3108 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3109 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3110 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3111 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3112 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3113 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3114 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3115 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3116 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3117 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3118 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3119 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3120 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3121 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3122 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3123 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3130 intel_float_operand (const char *mnemonic
)
3132 /* Note that the value returned is meaningful only for opcodes with (memory)
3133 operands, hence the code here is free to improperly handle opcodes that
3134 have no operands (for better performance and smaller code). */
3136 if (mnemonic
[0] != 'f')
3137 return 0; /* non-math */
3139 switch (mnemonic
[1])
3141 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3142 the fs segment override prefix not currently handled because no
3143 call path can make opcodes without operands get here */
3145 return 2 /* integer op */;
3147 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3148 return 3; /* fldcw/fldenv */
3151 if (mnemonic
[2] != 'o' /* fnop */)
3152 return 3; /* non-waiting control op */
3155 if (mnemonic
[2] == 's')
3156 return 3; /* frstor/frstpm */
3159 if (mnemonic
[2] == 'a')
3160 return 3; /* fsave */
3161 if (mnemonic
[2] == 't')
3163 switch (mnemonic
[3])
3165 case 'c': /* fstcw */
3166 case 'd': /* fstdw */
3167 case 'e': /* fstenv */
3168 case 's': /* fsts[gw] */
3174 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3175 return 0; /* fxsave/fxrstor are not really math ops */
3182 /* Build the VEX prefix. */
3185 build_vex_prefix (const insn_template
*t
)
3187 unsigned int register_specifier
;
3188 unsigned int implied_prefix
;
3189 unsigned int vector_length
;
3191 /* Check register specifier. */
3192 if (i
.vex
.register_specifier
)
3194 register_specifier
=
3195 ~register_number (i
.vex
.register_specifier
) & 0xf;
3196 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3199 register_specifier
= 0xf;
3201 /* Use 2-byte VEX prefix by swapping destination and source
3203 if (i
.vec_encoding
!= vex_encoding_vex3
3204 && i
.dir_encoding
== dir_encoding_default
3205 && i
.operands
== i
.reg_operands
3206 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3207 && i
.tm
.opcode_modifier
.load
3210 unsigned int xchg
= i
.operands
- 1;
3211 union i386_op temp_op
;
3212 i386_operand_type temp_type
;
3214 temp_type
= i
.types
[xchg
];
3215 i
.types
[xchg
] = i
.types
[0];
3216 i
.types
[0] = temp_type
;
3217 temp_op
= i
.op
[xchg
];
3218 i
.op
[xchg
] = i
.op
[0];
3221 gas_assert (i
.rm
.mode
== 3);
3225 i
.rm
.regmem
= i
.rm
.reg
;
3228 /* Use the next insn. */
3232 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3233 vector_length
= avxscalar
;
3235 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3237 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3242 case DATA_PREFIX_OPCODE
:
3245 case REPE_PREFIX_OPCODE
:
3248 case REPNE_PREFIX_OPCODE
:
3255 /* Use 2-byte VEX prefix if possible. */
3256 if (i
.vec_encoding
!= vex_encoding_vex3
3257 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3258 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3259 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3261 /* 2-byte VEX prefix. */
3265 i
.vex
.bytes
[0] = 0xc5;
3267 /* Check the REX.R bit. */
3268 r
= (i
.rex
& REX_R
) ? 0 : 1;
3269 i
.vex
.bytes
[1] = (r
<< 7
3270 | register_specifier
<< 3
3271 | vector_length
<< 2
3276 /* 3-byte VEX prefix. */
3281 switch (i
.tm
.opcode_modifier
.vexopcode
)
3285 i
.vex
.bytes
[0] = 0xc4;
3289 i
.vex
.bytes
[0] = 0xc4;
3293 i
.vex
.bytes
[0] = 0xc4;
3297 i
.vex
.bytes
[0] = 0x8f;
3301 i
.vex
.bytes
[0] = 0x8f;
3305 i
.vex
.bytes
[0] = 0x8f;
3311 /* The high 3 bits of the second VEX byte are 1's compliment
3312 of RXB bits from REX. */
3313 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3315 /* Check the REX.W bit. */
3316 w
= (i
.rex
& REX_W
) ? 1 : 0;
3317 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3320 i
.vex
.bytes
[2] = (w
<< 7
3321 | register_specifier
<< 3
3322 | vector_length
<< 2
3327 /* Build the EVEX prefix. */
3330 build_evex_prefix (void)
3332 unsigned int register_specifier
;
3333 unsigned int implied_prefix
;
3335 rex_byte vrex_used
= 0;
3337 /* Check register specifier. */
3338 if (i
.vex
.register_specifier
)
3340 gas_assert ((i
.vrex
& REX_X
) == 0);
3342 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3343 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3344 register_specifier
+= 8;
3345 /* The upper 16 registers are encoded in the fourth byte of the
3347 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3348 i
.vex
.bytes
[3] = 0x8;
3349 register_specifier
= ~register_specifier
& 0xf;
3353 register_specifier
= 0xf;
3355 /* Encode upper 16 vector index register in the fourth byte of
3357 if (!(i
.vrex
& REX_X
))
3358 i
.vex
.bytes
[3] = 0x8;
3363 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3368 case DATA_PREFIX_OPCODE
:
3371 case REPE_PREFIX_OPCODE
:
3374 case REPNE_PREFIX_OPCODE
:
3381 /* 4 byte EVEX prefix. */
3383 i
.vex
.bytes
[0] = 0x62;
3386 switch (i
.tm
.opcode_modifier
.vexopcode
)
3402 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3404 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3406 /* The fifth bit of the second EVEX byte is 1's compliment of the
3407 REX_R bit in VREX. */
3408 if (!(i
.vrex
& REX_R
))
3409 i
.vex
.bytes
[1] |= 0x10;
3413 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3415 /* When all operands are registers, the REX_X bit in REX is not
3416 used. We reuse it to encode the upper 16 registers, which is
3417 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3418 as 1's compliment. */
3419 if ((i
.vrex
& REX_B
))
3422 i
.vex
.bytes
[1] &= ~0x40;
3426 /* EVEX instructions shouldn't need the REX prefix. */
3427 i
.vrex
&= ~vrex_used
;
3428 gas_assert (i
.vrex
== 0);
3430 /* Check the REX.W bit. */
3431 w
= (i
.rex
& REX_W
) ? 1 : 0;
3432 if (i
.tm
.opcode_modifier
.vexw
)
3434 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3437 /* If w is not set it means we are dealing with WIG instruction. */
3440 if (evexwig
== evexw1
)
3444 /* Encode the U bit. */
3445 implied_prefix
|= 0x4;
3447 /* The third byte of the EVEX prefix. */
3448 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3450 /* The fourth byte of the EVEX prefix. */
3451 /* The zeroing-masking bit. */
3452 if (i
.mask
&& i
.mask
->zeroing
)
3453 i
.vex
.bytes
[3] |= 0x80;
3455 /* Don't always set the broadcast bit if there is no RC. */
3458 /* Encode the vector length. */
3459 unsigned int vec_length
;
3461 switch (i
.tm
.opcode_modifier
.evex
)
3463 case EVEXLIG
: /* LL' is ignored */
3464 vec_length
= evexlig
<< 5;
3467 vec_length
= 0 << 5;
3470 vec_length
= 1 << 5;
3473 vec_length
= 2 << 5;
3479 i
.vex
.bytes
[3] |= vec_length
;
3480 /* Encode the broadcast bit. */
3482 i
.vex
.bytes
[3] |= 0x10;
3486 if (i
.rounding
->type
!= saeonly
)
3487 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3489 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3492 if (i
.mask
&& i
.mask
->mask
)
3493 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3497 process_immext (void)
3501 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3504 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3505 with an opcode suffix which is coded in the same place as an
3506 8-bit immediate field would be.
3507 Here we check those operands and remove them afterwards. */
3510 for (x
= 0; x
< i
.operands
; x
++)
3511 if (register_number (i
.op
[x
].regs
) != x
)
3512 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3513 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3519 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3521 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3522 suffix which is coded in the same place as an 8-bit immediate
3524 Here we check those operands and remove them afterwards. */
3527 if (i
.operands
!= 3)
3530 for (x
= 0; x
< 2; x
++)
3531 if (register_number (i
.op
[x
].regs
) != x
)
3532 goto bad_register_operand
;
3534 /* Check for third operand for mwaitx/monitorx insn. */
3535 if (register_number (i
.op
[x
].regs
)
3536 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3538 bad_register_operand
:
3539 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3540 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3547 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3548 which is coded in the same place as an 8-bit immediate field
3549 would be. Here we fake an 8-bit immediate operand from the
3550 opcode suffix stored in tm.extension_opcode.
3552 AVX instructions also use this encoding, for some of
3553 3 argument instructions. */
3555 gas_assert (i
.imm_operands
<= 1
3557 || ((i
.tm
.opcode_modifier
.vex
3558 || i
.tm
.opcode_modifier
.evex
)
3559 && i
.operands
<= 4)));
3561 exp
= &im_expressions
[i
.imm_operands
++];
3562 i
.op
[i
.operands
].imms
= exp
;
3563 i
.types
[i
.operands
] = imm8
;
3565 exp
->X_op
= O_constant
;
3566 exp
->X_add_number
= i
.tm
.extension_opcode
;
3567 i
.tm
.extension_opcode
= None
;
3574 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3579 as_bad (_("invalid instruction `%s' after `%s'"),
3580 i
.tm
.name
, i
.hle_prefix
);
3583 if (i
.prefix
[LOCK_PREFIX
])
3585 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3589 case HLEPrefixRelease
:
3590 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3592 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3596 if (i
.mem_operands
== 0
3597 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3599 as_bad (_("memory destination needed for instruction `%s'"
3600 " after `xrelease'"), i
.tm
.name
);
3607 /* This is the guts of the machine-dependent assembler. LINE points to a
3608 machine dependent instruction. This function is supposed to emit
3609 the frags/bytes it assembles to. */
3612 md_assemble (char *line
)
3615 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3616 const insn_template
*t
;
3618 /* Initialize globals. */
3619 memset (&i
, '\0', sizeof (i
));
3620 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3621 i
.reloc
[j
] = NO_RELOC
;
3622 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3623 memset (im_expressions
, '\0', sizeof (im_expressions
));
3624 save_stack_p
= save_stack
;
3626 /* First parse an instruction mnemonic & call i386_operand for the operands.
3627 We assume that the scrubber has arranged it so that line[0] is the valid
3628 start of a (possibly prefixed) mnemonic. */
3630 line
= parse_insn (line
, mnemonic
);
3633 mnem_suffix
= i
.suffix
;
3635 line
= parse_operands (line
, mnemonic
);
3637 xfree (i
.memop1_string
);
3638 i
.memop1_string
= NULL
;
3642 /* Now we've parsed the mnemonic into a set of templates, and have the
3643 operands at hand. */
3645 /* All intel opcodes have reversed operands except for "bound" and
3646 "enter". We also don't reverse intersegment "jmp" and "call"
3647 instructions with 2 immediate operands so that the immediate segment
3648 precedes the offset, as it does when in AT&T mode. */
3651 && (strcmp (mnemonic
, "bound") != 0)
3652 && (strcmp (mnemonic
, "invlpga") != 0)
3653 && !(operand_type_check (i
.types
[0], imm
)
3654 && operand_type_check (i
.types
[1], imm
)))
3657 /* The order of the immediates should be reversed
3658 for 2 immediates extrq and insertq instructions */
3659 if (i
.imm_operands
== 2
3660 && (strcmp (mnemonic
, "extrq") == 0
3661 || strcmp (mnemonic
, "insertq") == 0))
3662 swap_2_operands (0, 1);
3667 /* Don't optimize displacement for movabs since it only takes 64bit
3670 && i
.disp_encoding
!= disp_encoding_32bit
3671 && (flag_code
!= CODE_64BIT
3672 || strcmp (mnemonic
, "movabs") != 0))
3675 /* Next, we find a template that matches the given insn,
3676 making sure the overlap of the given operands types is consistent
3677 with the template operand types. */
3679 if (!(t
= match_template (mnem_suffix
)))
3682 if (sse_check
!= check_none
3683 && !i
.tm
.opcode_modifier
.noavx
3684 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3685 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3686 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3687 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3688 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3689 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3691 (sse_check
== check_warning
3693 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3696 /* Zap movzx and movsx suffix. The suffix has been set from
3697 "word ptr" or "byte ptr" on the source operand in Intel syntax
3698 or extracted from mnemonic in AT&T syntax. But we'll use
3699 the destination register to choose the suffix for encoding. */
3700 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3702 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3703 there is no suffix, the default will be byte extension. */
3704 if (i
.reg_operands
!= 2
3707 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3712 if (i
.tm
.opcode_modifier
.fwait
)
3713 if (!add_prefix (FWAIT_OPCODE
))
3716 /* Check if REP prefix is OK. */
3717 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3719 as_bad (_("invalid instruction `%s' after `%s'"),
3720 i
.tm
.name
, i
.rep_prefix
);
3724 /* Check for lock without a lockable instruction. Destination operand
3725 must be memory unless it is xchg (0x86). */
3726 if (i
.prefix
[LOCK_PREFIX
]
3727 && (!i
.tm
.opcode_modifier
.islockable
3728 || i
.mem_operands
== 0
3729 || (i
.tm
.base_opcode
!= 0x86
3730 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3732 as_bad (_("expecting lockable instruction after `lock'"));
3736 /* Check if HLE prefix is OK. */
3737 if (i
.hle_prefix
&& !check_hle ())
3740 /* Check BND prefix. */
3741 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3742 as_bad (_("expecting valid branch instruction after `bnd'"));
3744 /* Check NOTRACK prefix. */
3745 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
3746 as_bad (_("expecting indirect branch instruction after `notrack'"));
3748 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3750 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3751 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3752 else if (flag_code
!= CODE_16BIT
3753 ? i
.prefix
[ADDR_PREFIX
]
3754 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3755 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3758 /* Insert BND prefix. */
3760 && i
.tm
.opcode_modifier
.bndprefixok
3761 && !i
.prefix
[BND_PREFIX
])
3762 add_prefix (BND_PREFIX_OPCODE
);
3764 /* Check string instruction segment overrides. */
3765 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3767 if (!check_string ())
3769 i
.disp_operands
= 0;
3772 if (!process_suffix ())
3775 /* Update operand types. */
3776 for (j
= 0; j
< i
.operands
; j
++)
3777 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3779 /* Make still unresolved immediate matches conform to size of immediate
3780 given in i.suffix. */
3781 if (!finalize_imm ())
3784 if (i
.types
[0].bitfield
.imm1
)
3785 i
.imm_operands
= 0; /* kludge for shift insns. */
3787 /* We only need to check those implicit registers for instructions
3788 with 3 operands or less. */
3789 if (i
.operands
<= 3)
3790 for (j
= 0; j
< i
.operands
; j
++)
3791 if (i
.types
[j
].bitfield
.inoutportreg
3792 || i
.types
[j
].bitfield
.shiftcount
3793 || i
.types
[j
].bitfield
.acc
3794 || i
.types
[j
].bitfield
.floatacc
)
3797 /* ImmExt should be processed after SSE2AVX. */
3798 if (!i
.tm
.opcode_modifier
.sse2avx
3799 && i
.tm
.opcode_modifier
.immext
)
3802 /* For insns with operands there are more diddles to do to the opcode. */
3805 if (!process_operands ())
3808 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3810 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3811 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3814 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3816 if (flag_code
== CODE_16BIT
)
3818 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3823 if (i
.tm
.opcode_modifier
.vex
)
3824 build_vex_prefix (t
);
3826 build_evex_prefix ();
3829 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3830 instructions may define INT_OPCODE as well, so avoid this corner
3831 case for those instructions that use MODRM. */
3832 if (i
.tm
.base_opcode
== INT_OPCODE
3833 && !i
.tm
.opcode_modifier
.modrm
3834 && i
.op
[0].imms
->X_add_number
== 3)
3836 i
.tm
.base_opcode
= INT3_OPCODE
;
3840 if ((i
.tm
.opcode_modifier
.jump
3841 || i
.tm
.opcode_modifier
.jumpbyte
3842 || i
.tm
.opcode_modifier
.jumpdword
)
3843 && i
.op
[0].disps
->X_op
== O_constant
)
3845 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3846 the absolute address given by the constant. Since ix86 jumps and
3847 calls are pc relative, we need to generate a reloc. */
3848 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3849 i
.op
[0].disps
->X_op
= O_symbol
;
3852 if (i
.tm
.opcode_modifier
.rex64
)
3855 /* For 8 bit registers we need an empty rex prefix. Also if the
3856 instruction already has a prefix, we need to convert old
3857 registers to new ones. */
3859 if ((i
.types
[0].bitfield
.reg8
3860 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3861 || (i
.types
[1].bitfield
.reg8
3862 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3863 || ((i
.types
[0].bitfield
.reg8
3864 || i
.types
[1].bitfield
.reg8
)
3869 i
.rex
|= REX_OPCODE
;
3870 for (x
= 0; x
< 2; x
++)
3872 /* Look for 8 bit operand that uses old registers. */
3873 if (i
.types
[x
].bitfield
.reg8
3874 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3876 /* In case it is "hi" register, give up. */
3877 if (i
.op
[x
].regs
->reg_num
> 3)
3878 as_bad (_("can't encode register '%s%s' in an "
3879 "instruction requiring REX prefix."),
3880 register_prefix
, i
.op
[x
].regs
->reg_name
);
3882 /* Otherwise it is equivalent to the extended register.
3883 Since the encoding doesn't change this is merely
3884 cosmetic cleanup for debug output. */
3886 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3892 add_prefix (REX_OPCODE
| i
.rex
);
3894 /* We are ready to output the insn. */
3899 parse_insn (char *line
, char *mnemonic
)
3902 char *token_start
= l
;
3905 const insn_template
*t
;
3911 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3916 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3918 as_bad (_("no such instruction: `%s'"), token_start
);
3923 if (!is_space_char (*l
)
3924 && *l
!= END_OF_INSN
3926 || (*l
!= PREFIX_SEPARATOR
3929 as_bad (_("invalid character %s in mnemonic"),
3930 output_invalid (*l
));
3933 if (token_start
== l
)
3935 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3936 as_bad (_("expecting prefix; got nothing"));
3938 as_bad (_("expecting mnemonic; got nothing"));
3942 /* Look up instruction (or prefix) via hash table. */
3943 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3945 if (*l
!= END_OF_INSN
3946 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3947 && current_templates
3948 && current_templates
->start
->opcode_modifier
.isprefix
)
3950 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3952 as_bad ((flag_code
!= CODE_64BIT
3953 ? _("`%s' is only supported in 64-bit mode")
3954 : _("`%s' is not supported in 64-bit mode")),
3955 current_templates
->start
->name
);
3958 /* If we are in 16-bit mode, do not allow addr16 or data16.
3959 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3960 if ((current_templates
->start
->opcode_modifier
.size16
3961 || current_templates
->start
->opcode_modifier
.size32
)
3962 && flag_code
!= CODE_64BIT
3963 && (current_templates
->start
->opcode_modifier
.size32
3964 ^ (flag_code
== CODE_16BIT
)))
3966 as_bad (_("redundant %s prefix"),
3967 current_templates
->start
->name
);
3970 if (current_templates
->start
->opcode_length
== 0)
3972 /* Handle pseudo prefixes. */
3973 switch (current_templates
->start
->base_opcode
)
3977 i
.disp_encoding
= disp_encoding_8bit
;
3981 i
.disp_encoding
= disp_encoding_32bit
;
3985 i
.dir_encoding
= dir_encoding_load
;
3989 i
.dir_encoding
= dir_encoding_store
;
3993 i
.vec_encoding
= vex_encoding_vex2
;
3997 i
.vec_encoding
= vex_encoding_vex3
;
4001 i
.vec_encoding
= vex_encoding_evex
;
4009 /* Add prefix, checking for repeated prefixes. */
4010 switch (add_prefix (current_templates
->start
->base_opcode
))
4015 if (current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
4016 i
.notrack_prefix
= current_templates
->start
->name
;
4019 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4020 i
.hle_prefix
= current_templates
->start
->name
;
4021 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4022 i
.bnd_prefix
= current_templates
->start
->name
;
4024 i
.rep_prefix
= current_templates
->start
->name
;
4030 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4037 if (!current_templates
)
4039 /* Check if we should swap operand or force 32bit displacement in
4041 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4042 i
.dir_encoding
= dir_encoding_store
;
4043 else if (mnem_p
- 3 == dot_p
4046 i
.disp_encoding
= disp_encoding_8bit
;
4047 else if (mnem_p
- 4 == dot_p
4051 i
.disp_encoding
= disp_encoding_32bit
;
4056 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4059 if (!current_templates
)
4062 /* See if we can get a match by trimming off a suffix. */
4065 case WORD_MNEM_SUFFIX
:
4066 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4067 i
.suffix
= SHORT_MNEM_SUFFIX
;
4070 case BYTE_MNEM_SUFFIX
:
4071 case QWORD_MNEM_SUFFIX
:
4072 i
.suffix
= mnem_p
[-1];
4074 current_templates
= (const templates
*) hash_find (op_hash
,
4077 case SHORT_MNEM_SUFFIX
:
4078 case LONG_MNEM_SUFFIX
:
4081 i
.suffix
= mnem_p
[-1];
4083 current_templates
= (const templates
*) hash_find (op_hash
,
4092 if (intel_float_operand (mnemonic
) == 1)
4093 i
.suffix
= SHORT_MNEM_SUFFIX
;
4095 i
.suffix
= LONG_MNEM_SUFFIX
;
4097 current_templates
= (const templates
*) hash_find (op_hash
,
4102 if (!current_templates
)
4104 as_bad (_("no such instruction: `%s'"), token_start
);
4109 if (current_templates
->start
->opcode_modifier
.jump
4110 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4112 /* Check for a branch hint. We allow ",pt" and ",pn" for
4113 predict taken and predict not taken respectively.
4114 I'm not sure that branch hints actually do anything on loop
4115 and jcxz insns (JumpByte) for current Pentium4 chips. They
4116 may work in the future and it doesn't hurt to accept them
4118 if (l
[0] == ',' && l
[1] == 'p')
4122 if (!add_prefix (DS_PREFIX_OPCODE
))
4126 else if (l
[2] == 'n')
4128 if (!add_prefix (CS_PREFIX_OPCODE
))
4134 /* Any other comma loses. */
4137 as_bad (_("invalid character %s in mnemonic"),
4138 output_invalid (*l
));
4142 /* Check if instruction is supported on specified architecture. */
4144 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4146 supported
|= cpu_flags_match (t
);
4147 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4151 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4153 as_bad (flag_code
== CODE_64BIT
4154 ? _("`%s' is not supported in 64-bit mode")
4155 : _("`%s' is only supported in 64-bit mode"),
4156 current_templates
->start
->name
);
4159 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4161 as_bad (_("`%s' is not supported on `%s%s'"),
4162 current_templates
->start
->name
,
4163 cpu_arch_name
? cpu_arch_name
: default_arch
,
4164 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4169 if (!cpu_arch_flags
.bitfield
.cpui386
4170 && (flag_code
!= CODE_16BIT
))
4172 as_warn (_("use .code16 to ensure correct addressing mode"));
4179 parse_operands (char *l
, const char *mnemonic
)
4183 /* 1 if operand is pending after ','. */
4184 unsigned int expecting_operand
= 0;
4186 /* Non-zero if operand parens not balanced. */
4187 unsigned int paren_not_balanced
;
4189 while (*l
!= END_OF_INSN
)
4191 /* Skip optional white space before operand. */
4192 if (is_space_char (*l
))
4194 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4196 as_bad (_("invalid character %s before operand %d"),
4197 output_invalid (*l
),
4201 token_start
= l
; /* After white space. */
4202 paren_not_balanced
= 0;
4203 while (paren_not_balanced
|| *l
!= ',')
4205 if (*l
== END_OF_INSN
)
4207 if (paren_not_balanced
)
4210 as_bad (_("unbalanced parenthesis in operand %d."),
4213 as_bad (_("unbalanced brackets in operand %d."),
4218 break; /* we are done */
4220 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4222 as_bad (_("invalid character %s in operand %d"),
4223 output_invalid (*l
),
4230 ++paren_not_balanced
;
4232 --paren_not_balanced
;
4237 ++paren_not_balanced
;
4239 --paren_not_balanced
;
4243 if (l
!= token_start
)
4244 { /* Yes, we've read in another operand. */
4245 unsigned int operand_ok
;
4246 this_operand
= i
.operands
++;
4247 if (i
.operands
> MAX_OPERANDS
)
4249 as_bad (_("spurious operands; (%d operands/instruction max)"),
4253 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4254 /* Now parse operand adding info to 'i' as we go along. */
4255 END_STRING_AND_SAVE (l
);
4259 i386_intel_operand (token_start
,
4260 intel_float_operand (mnemonic
));
4262 operand_ok
= i386_att_operand (token_start
);
4264 RESTORE_END_STRING (l
);
4270 if (expecting_operand
)
4272 expecting_operand_after_comma
:
4273 as_bad (_("expecting operand after ','; got nothing"));
4278 as_bad (_("expecting operand before ','; got nothing"));
4283 /* Now *l must be either ',' or END_OF_INSN. */
4286 if (*++l
== END_OF_INSN
)
4288 /* Just skip it, if it's \n complain. */
4289 goto expecting_operand_after_comma
;
4291 expecting_operand
= 1;
4298 swap_2_operands (int xchg1
, int xchg2
)
4300 union i386_op temp_op
;
4301 i386_operand_type temp_type
;
4302 enum bfd_reloc_code_real temp_reloc
;
4304 temp_type
= i
.types
[xchg2
];
4305 i
.types
[xchg2
] = i
.types
[xchg1
];
4306 i
.types
[xchg1
] = temp_type
;
4307 temp_op
= i
.op
[xchg2
];
4308 i
.op
[xchg2
] = i
.op
[xchg1
];
4309 i
.op
[xchg1
] = temp_op
;
4310 temp_reloc
= i
.reloc
[xchg2
];
4311 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4312 i
.reloc
[xchg1
] = temp_reloc
;
4316 if (i
.mask
->operand
== xchg1
)
4317 i
.mask
->operand
= xchg2
;
4318 else if (i
.mask
->operand
== xchg2
)
4319 i
.mask
->operand
= xchg1
;
4323 if (i
.broadcast
->operand
== xchg1
)
4324 i
.broadcast
->operand
= xchg2
;
4325 else if (i
.broadcast
->operand
== xchg2
)
4326 i
.broadcast
->operand
= xchg1
;
4330 if (i
.rounding
->operand
== xchg1
)
4331 i
.rounding
->operand
= xchg2
;
4332 else if (i
.rounding
->operand
== xchg2
)
4333 i
.rounding
->operand
= xchg1
;
4338 swap_operands (void)
4344 swap_2_operands (1, i
.operands
- 2);
4348 swap_2_operands (0, i
.operands
- 1);
4354 if (i
.mem_operands
== 2)
4356 const seg_entry
*temp_seg
;
4357 temp_seg
= i
.seg
[0];
4358 i
.seg
[0] = i
.seg
[1];
4359 i
.seg
[1] = temp_seg
;
4363 /* Try to ensure constant immediates are represented in the smallest
4368 char guess_suffix
= 0;
4372 guess_suffix
= i
.suffix
;
4373 else if (i
.reg_operands
)
4375 /* Figure out a suffix from the last register operand specified.
4376 We can't do this properly yet, ie. excluding InOutPortReg,
4377 but the following works for instructions with immediates.
4378 In any case, we can't set i.suffix yet. */
4379 for (op
= i
.operands
; --op
>= 0;)
4380 if (i
.types
[op
].bitfield
.reg8
)
4382 guess_suffix
= BYTE_MNEM_SUFFIX
;
4385 else if (i
.types
[op
].bitfield
.reg16
)
4387 guess_suffix
= WORD_MNEM_SUFFIX
;
4390 else if (i
.types
[op
].bitfield
.reg32
)
4392 guess_suffix
= LONG_MNEM_SUFFIX
;
4395 else if (i
.types
[op
].bitfield
.reg64
)
4397 guess_suffix
= QWORD_MNEM_SUFFIX
;
4401 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4402 guess_suffix
= WORD_MNEM_SUFFIX
;
4404 for (op
= i
.operands
; --op
>= 0;)
4405 if (operand_type_check (i
.types
[op
], imm
))
4407 switch (i
.op
[op
].imms
->X_op
)
4410 /* If a suffix is given, this operand may be shortened. */
4411 switch (guess_suffix
)
4413 case LONG_MNEM_SUFFIX
:
4414 i
.types
[op
].bitfield
.imm32
= 1;
4415 i
.types
[op
].bitfield
.imm64
= 1;
4417 case WORD_MNEM_SUFFIX
:
4418 i
.types
[op
].bitfield
.imm16
= 1;
4419 i
.types
[op
].bitfield
.imm32
= 1;
4420 i
.types
[op
].bitfield
.imm32s
= 1;
4421 i
.types
[op
].bitfield
.imm64
= 1;
4423 case BYTE_MNEM_SUFFIX
:
4424 i
.types
[op
].bitfield
.imm8
= 1;
4425 i
.types
[op
].bitfield
.imm8s
= 1;
4426 i
.types
[op
].bitfield
.imm16
= 1;
4427 i
.types
[op
].bitfield
.imm32
= 1;
4428 i
.types
[op
].bitfield
.imm32s
= 1;
4429 i
.types
[op
].bitfield
.imm64
= 1;
4433 /* If this operand is at most 16 bits, convert it
4434 to a signed 16 bit number before trying to see
4435 whether it will fit in an even smaller size.
4436 This allows a 16-bit operand such as $0xffe0 to
4437 be recognised as within Imm8S range. */
4438 if ((i
.types
[op
].bitfield
.imm16
)
4439 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4441 i
.op
[op
].imms
->X_add_number
=
4442 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4445 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4446 if ((i
.types
[op
].bitfield
.imm32
)
4447 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4450 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4451 ^ ((offsetT
) 1 << 31))
4452 - ((offsetT
) 1 << 31));
4456 = operand_type_or (i
.types
[op
],
4457 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4459 /* We must avoid matching of Imm32 templates when 64bit
4460 only immediate is available. */
4461 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4462 i
.types
[op
].bitfield
.imm32
= 0;
4469 /* Symbols and expressions. */
4471 /* Convert symbolic operand to proper sizes for matching, but don't
4472 prevent matching a set of insns that only supports sizes other
4473 than those matching the insn suffix. */
4475 i386_operand_type mask
, allowed
;
4476 const insn_template
*t
;
4478 operand_type_set (&mask
, 0);
4479 operand_type_set (&allowed
, 0);
4481 for (t
= current_templates
->start
;
4482 t
< current_templates
->end
;
4484 allowed
= operand_type_or (allowed
,
4485 t
->operand_types
[op
]);
4486 switch (guess_suffix
)
4488 case QWORD_MNEM_SUFFIX
:
4489 mask
.bitfield
.imm64
= 1;
4490 mask
.bitfield
.imm32s
= 1;
4492 case LONG_MNEM_SUFFIX
:
4493 mask
.bitfield
.imm32
= 1;
4495 case WORD_MNEM_SUFFIX
:
4496 mask
.bitfield
.imm16
= 1;
4498 case BYTE_MNEM_SUFFIX
:
4499 mask
.bitfield
.imm8
= 1;
4504 allowed
= operand_type_and (mask
, allowed
);
4505 if (!operand_type_all_zero (&allowed
))
4506 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4513 /* Try to use the smallest displacement type too. */
4515 optimize_disp (void)
4519 for (op
= i
.operands
; --op
>= 0;)
4520 if (operand_type_check (i
.types
[op
], disp
))
4522 if (i
.op
[op
].disps
->X_op
== O_constant
)
4524 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4526 if (i
.types
[op
].bitfield
.disp16
4527 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4529 /* If this operand is at most 16 bits, convert
4530 to a signed 16 bit number and don't use 64bit
4532 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4533 i
.types
[op
].bitfield
.disp64
= 0;
4536 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4537 if (i
.types
[op
].bitfield
.disp32
4538 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4540 /* If this operand is at most 32 bits, convert
4541 to a signed 32 bit number and don't use 64bit
4543 op_disp
&= (((offsetT
) 2 << 31) - 1);
4544 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4545 i
.types
[op
].bitfield
.disp64
= 0;
4548 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4550 i
.types
[op
].bitfield
.disp8
= 0;
4551 i
.types
[op
].bitfield
.disp16
= 0;
4552 i
.types
[op
].bitfield
.disp32
= 0;
4553 i
.types
[op
].bitfield
.disp32s
= 0;
4554 i
.types
[op
].bitfield
.disp64
= 0;
4558 else if (flag_code
== CODE_64BIT
)
4560 if (fits_in_signed_long (op_disp
))
4562 i
.types
[op
].bitfield
.disp64
= 0;
4563 i
.types
[op
].bitfield
.disp32s
= 1;
4565 if (i
.prefix
[ADDR_PREFIX
]
4566 && fits_in_unsigned_long (op_disp
))
4567 i
.types
[op
].bitfield
.disp32
= 1;
4569 if ((i
.types
[op
].bitfield
.disp32
4570 || i
.types
[op
].bitfield
.disp32s
4571 || i
.types
[op
].bitfield
.disp16
)
4572 && fits_in_disp8 (op_disp
))
4573 i
.types
[op
].bitfield
.disp8
= 1;
4575 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4576 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4578 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4579 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4580 i
.types
[op
].bitfield
.disp8
= 0;
4581 i
.types
[op
].bitfield
.disp16
= 0;
4582 i
.types
[op
].bitfield
.disp32
= 0;
4583 i
.types
[op
].bitfield
.disp32s
= 0;
4584 i
.types
[op
].bitfield
.disp64
= 0;
4587 /* We only support 64bit displacement on constants. */
4588 i
.types
[op
].bitfield
.disp64
= 0;
4592 /* Check if operands are valid for the instruction. */
4595 check_VecOperands (const insn_template
*t
)
4599 /* Without VSIB byte, we can't have a vector register for index. */
4600 if (!t
->opcode_modifier
.vecsib
4602 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4603 || i
.index_reg
->reg_type
.bitfield
.regymm
4604 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4606 i
.error
= unsupported_vector_index_register
;
4610 /* Check if default mask is allowed. */
4611 if (t
->opcode_modifier
.nodefmask
4612 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4614 i
.error
= no_default_mask
;
4618 /* For VSIB byte, we need a vector register for index, and all vector
4619 registers must be distinct. */
4620 if (t
->opcode_modifier
.vecsib
)
4623 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4624 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4625 || (t
->opcode_modifier
.vecsib
== VecSIB256
4626 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4627 || (t
->opcode_modifier
.vecsib
== VecSIB512
4628 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4630 i
.error
= invalid_vsib_address
;
4634 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4635 if (i
.reg_operands
== 2 && !i
.mask
)
4637 gas_assert (i
.types
[0].bitfield
.regxmm
4638 || i
.types
[0].bitfield
.regymm
);
4639 gas_assert (i
.types
[2].bitfield
.regxmm
4640 || i
.types
[2].bitfield
.regymm
);
4641 if (operand_check
== check_none
)
4643 if (register_number (i
.op
[0].regs
)
4644 != register_number (i
.index_reg
)
4645 && register_number (i
.op
[2].regs
)
4646 != register_number (i
.index_reg
)
4647 && register_number (i
.op
[0].regs
)
4648 != register_number (i
.op
[2].regs
))
4650 if (operand_check
== check_error
)
4652 i
.error
= invalid_vector_register_set
;
4655 as_warn (_("mask, index, and destination registers should be distinct"));
4657 else if (i
.reg_operands
== 1 && i
.mask
)
4659 if ((i
.types
[1].bitfield
.regxmm
4660 || i
.types
[1].bitfield
.regymm
4661 || i
.types
[1].bitfield
.regzmm
)
4662 && (register_number (i
.op
[1].regs
)
4663 == register_number (i
.index_reg
)))
4665 if (operand_check
== check_error
)
4667 i
.error
= invalid_vector_register_set
;
4670 if (operand_check
!= check_none
)
4671 as_warn (_("index and destination registers should be distinct"));
4676 /* Check if broadcast is supported by the instruction and is applied
4677 to the memory operand. */
4680 int broadcasted_opnd_size
;
4682 /* Check if specified broadcast is supported in this instruction,
4683 and it's applied to memory operand of DWORD or QWORD type,
4684 depending on VecESize. */
4685 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4686 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4687 || (t
->opcode_modifier
.vecesize
== 0
4688 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4689 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4690 || (t
->opcode_modifier
.vecesize
== 1
4691 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4692 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4695 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4696 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4697 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4698 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4699 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4700 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4701 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4702 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4703 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4707 if ((broadcasted_opnd_size
== 256
4708 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4709 || (broadcasted_opnd_size
== 512
4710 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4713 i
.error
= unsupported_broadcast
;
4717 /* If broadcast is supported in this instruction, we need to check if
4718 operand of one-element size isn't specified without broadcast. */
4719 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4721 /* Find memory operand. */
4722 for (op
= 0; op
< i
.operands
; op
++)
4723 if (operand_type_check (i
.types
[op
], anymem
))
4725 gas_assert (op
< i
.operands
);
4726 /* Check size of the memory operand. */
4727 if ((t
->opcode_modifier
.vecesize
== 0
4728 && i
.types
[op
].bitfield
.dword
)
4729 || (t
->opcode_modifier
.vecesize
== 1
4730 && i
.types
[op
].bitfield
.qword
))
4732 i
.error
= broadcast_needed
;
4737 /* Check if requested masking is supported. */
4739 && (!t
->opcode_modifier
.masking
4741 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4743 i
.error
= unsupported_masking
;
4747 /* Check if masking is applied to dest operand. */
4748 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4750 i
.error
= mask_not_on_destination
;
4757 if ((i
.rounding
->type
!= saeonly
4758 && !t
->opcode_modifier
.staticrounding
)
4759 || (i
.rounding
->type
== saeonly
4760 && (t
->opcode_modifier
.staticrounding
4761 || !t
->opcode_modifier
.sae
)))
4763 i
.error
= unsupported_rc_sae
;
4766 /* If the instruction has several immediate operands and one of
4767 them is rounding, the rounding operand should be the last
4768 immediate operand. */
4769 if (i
.imm_operands
> 1
4770 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4772 i
.error
= rc_sae_operand_not_last_imm
;
4777 /* Check vector Disp8 operand. */
4778 if (t
->opcode_modifier
.disp8memshift
4779 && i
.disp_encoding
!= disp_encoding_32bit
)
4782 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4784 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4786 for (op
= 0; op
< i
.operands
; op
++)
4787 if (operand_type_check (i
.types
[op
], disp
)
4788 && i
.op
[op
].disps
->X_op
== O_constant
)
4790 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
4792 i
.types
[op
].bitfield
.disp8
= 1;
4795 i
.types
[op
].bitfield
.disp8
= 0;
4804 /* Check if operands are valid for the instruction. Update VEX
4808 VEX_check_operands (const insn_template
*t
)
4810 if (i
.vec_encoding
== vex_encoding_evex
)
4812 /* This instruction must be encoded with EVEX prefix. */
4813 if (!t
->opcode_modifier
.evex
)
4815 i
.error
= unsupported
;
4821 if (!t
->opcode_modifier
.vex
)
4823 /* This instruction template doesn't have VEX prefix. */
4824 if (i
.vec_encoding
!= vex_encoding_default
)
4826 i
.error
= unsupported
;
4832 /* Only check VEX_Imm4, which must be the first operand. */
4833 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4835 if (i
.op
[0].imms
->X_op
!= O_constant
4836 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4842 /* Turn off Imm8 so that update_imm won't complain. */
4843 i
.types
[0] = vec_imm4
;
4849 static const insn_template
*
4850 match_template (char mnem_suffix
)
4852 /* Points to template once we've found it. */
4853 const insn_template
*t
;
4854 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4855 i386_operand_type overlap4
;
4856 unsigned int found_reverse_match
;
4857 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4858 i386_operand_type operand_types
[MAX_OPERANDS
];
4859 int addr_prefix_disp
;
4861 unsigned int found_cpu_match
;
4862 unsigned int check_register
;
4863 enum i386_error specific_error
= 0;
4865 #if MAX_OPERANDS != 5
4866 # error "MAX_OPERANDS must be 5."
4869 found_reverse_match
= 0;
4870 addr_prefix_disp
= -1;
4872 memset (&suffix_check
, 0, sizeof (suffix_check
));
4873 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4874 suffix_check
.no_bsuf
= 1;
4875 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4876 suffix_check
.no_wsuf
= 1;
4877 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4878 suffix_check
.no_ssuf
= 1;
4879 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4880 suffix_check
.no_lsuf
= 1;
4881 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4882 suffix_check
.no_qsuf
= 1;
4883 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4884 suffix_check
.no_ldsuf
= 1;
4886 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4889 switch (mnem_suffix
)
4891 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4892 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4893 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4894 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4895 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4899 /* Must have right number of operands. */
4900 i
.error
= number_of_operands_mismatch
;
4902 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4904 addr_prefix_disp
= -1;
4906 if (i
.operands
!= t
->operands
)
4909 /* Check processor support. */
4910 i
.error
= unsupported
;
4911 found_cpu_match
= (cpu_flags_match (t
)
4912 == CPU_FLAGS_PERFECT_MATCH
);
4913 if (!found_cpu_match
)
4916 /* Check old gcc support. */
4917 i
.error
= old_gcc_only
;
4918 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4921 /* Check AT&T mnemonic. */
4922 i
.error
= unsupported_with_intel_mnemonic
;
4923 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4926 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4927 i
.error
= unsupported_syntax
;
4928 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4929 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4930 || (intel64
&& t
->opcode_modifier
.amd64
)
4931 || (!intel64
&& t
->opcode_modifier
.intel64
))
4934 /* Check the suffix, except for some instructions in intel mode. */
4935 i
.error
= invalid_instruction_suffix
;
4936 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4937 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4938 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4939 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4940 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4941 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4942 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4944 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4945 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4946 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4947 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4948 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4949 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4950 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4953 if (!operand_size_match (t
))
4956 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4957 operand_types
[j
] = t
->operand_types
[j
];
4959 /* In general, don't allow 64-bit operands in 32-bit mode. */
4960 if (i
.suffix
== QWORD_MNEM_SUFFIX
4961 && flag_code
!= CODE_64BIT
4963 ? (!t
->opcode_modifier
.ignoresize
4964 && !intel_float_operand (t
->name
))
4965 : intel_float_operand (t
->name
) != 2)
4966 && ((!operand_types
[0].bitfield
.regmmx
4967 && !operand_types
[0].bitfield
.regxmm
4968 && !operand_types
[0].bitfield
.regymm
4969 && !operand_types
[0].bitfield
.regzmm
)
4970 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4971 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4972 && operand_types
[t
->operands
> 1].bitfield
.regymm
4973 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4974 && (t
->base_opcode
!= 0x0fc7
4975 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4978 /* In general, don't allow 32-bit operands on pre-386. */
4979 else if (i
.suffix
== LONG_MNEM_SUFFIX
4980 && !cpu_arch_flags
.bitfield
.cpui386
4982 ? (!t
->opcode_modifier
.ignoresize
4983 && !intel_float_operand (t
->name
))
4984 : intel_float_operand (t
->name
) != 2)
4985 && ((!operand_types
[0].bitfield
.regmmx
4986 && !operand_types
[0].bitfield
.regxmm
)
4987 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4988 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4991 /* Do not verify operands when there are none. */
4995 /* We've found a match; break out of loop. */
4999 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5000 into Disp32/Disp16/Disp32 operand. */
5001 if (i
.prefix
[ADDR_PREFIX
] != 0)
5003 /* There should be only one Disp operand. */
5007 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5009 if (operand_types
[j
].bitfield
.disp16
)
5011 addr_prefix_disp
= j
;
5012 operand_types
[j
].bitfield
.disp32
= 1;
5013 operand_types
[j
].bitfield
.disp16
= 0;
5019 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5021 if (operand_types
[j
].bitfield
.disp32
)
5023 addr_prefix_disp
= j
;
5024 operand_types
[j
].bitfield
.disp32
= 0;
5025 operand_types
[j
].bitfield
.disp16
= 1;
5031 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5033 if (operand_types
[j
].bitfield
.disp64
)
5035 addr_prefix_disp
= j
;
5036 operand_types
[j
].bitfield
.disp64
= 0;
5037 operand_types
[j
].bitfield
.disp32
= 1;
5045 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5046 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5049 /* We check register size if needed. */
5050 check_register
= t
->opcode_modifier
.checkregsize
;
5051 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5052 switch (t
->operands
)
5055 if (!operand_type_match (overlap0
, i
.types
[0]))
5059 /* xchg %eax, %eax is a special case. It is an alias for nop
5060 only in 32bit mode and we can use opcode 0x90. In 64bit
5061 mode, we can't use 0x90 for xchg %eax, %eax since it should
5062 zero-extend %eax to %rax. */
5063 if (flag_code
== CODE_64BIT
5064 && t
->base_opcode
== 0x90
5065 && operand_type_equal (&i
.types
[0], &acc32
)
5066 && operand_type_equal (&i
.types
[1], &acc32
))
5068 /* If we want store form, we reverse direction of operands. */
5069 if (i
.dir_encoding
== dir_encoding_store
5070 && t
->opcode_modifier
.d
)
5075 /* If we want store form, we skip the current load. */
5076 if (i
.dir_encoding
== dir_encoding_store
5077 && i
.mem_operands
== 0
5078 && t
->opcode_modifier
.load
)
5083 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5084 if (!operand_type_match (overlap0
, i
.types
[0])
5085 || !operand_type_match (overlap1
, i
.types
[1])
5087 && !operand_type_register_match (overlap0
, i
.types
[0],
5089 overlap1
, i
.types
[1],
5092 /* Check if other direction is valid ... */
5093 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5097 /* Try reversing direction of operands. */
5098 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5099 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5100 if (!operand_type_match (overlap0
, i
.types
[0])
5101 || !operand_type_match (overlap1
, i
.types
[1])
5103 && !operand_type_register_match (overlap0
,
5110 /* Does not match either direction. */
5113 /* found_reverse_match holds which of D or FloatDR
5115 if (t
->opcode_modifier
.d
)
5116 found_reverse_match
= Opcode_D
;
5117 else if (t
->opcode_modifier
.floatd
)
5118 found_reverse_match
= Opcode_FloatD
;
5120 found_reverse_match
= 0;
5121 if (t
->opcode_modifier
.floatr
)
5122 found_reverse_match
|= Opcode_FloatR
;
5126 /* Found a forward 2 operand match here. */
5127 switch (t
->operands
)
5130 overlap4
= operand_type_and (i
.types
[4],
5134 overlap3
= operand_type_and (i
.types
[3],
5138 overlap2
= operand_type_and (i
.types
[2],
5143 switch (t
->operands
)
5146 if (!operand_type_match (overlap4
, i
.types
[4])
5147 || !operand_type_register_match (overlap3
,
5156 if (!operand_type_match (overlap3
, i
.types
[3])
5158 && !operand_type_register_match (overlap2
,
5167 /* Here we make use of the fact that there are no
5168 reverse match 3 operand instructions, and all 3
5169 operand instructions only need to be checked for
5170 register consistency between operands 2 and 3. */
5171 if (!operand_type_match (overlap2
, i
.types
[2])
5173 && !operand_type_register_match (overlap1
,
5183 /* Found either forward/reverse 2, 3 or 4 operand match here:
5184 slip through to break. */
5186 if (!found_cpu_match
)
5188 found_reverse_match
= 0;
5192 /* Check if vector and VEX operands are valid. */
5193 if (check_VecOperands (t
) || VEX_check_operands (t
))
5195 specific_error
= i
.error
;
5199 /* We've found a match; break out of loop. */
5203 if (t
== current_templates
->end
)
5205 /* We found no match. */
5206 const char *err_msg
;
5207 switch (specific_error
? specific_error
: i
.error
)
5211 case operand_size_mismatch
:
5212 err_msg
= _("operand size mismatch");
5214 case operand_type_mismatch
:
5215 err_msg
= _("operand type mismatch");
5217 case register_type_mismatch
:
5218 err_msg
= _("register type mismatch");
5220 case number_of_operands_mismatch
:
5221 err_msg
= _("number of operands mismatch");
5223 case invalid_instruction_suffix
:
5224 err_msg
= _("invalid instruction suffix");
5227 err_msg
= _("constant doesn't fit in 4 bits");
5230 err_msg
= _("only supported with old gcc");
5232 case unsupported_with_intel_mnemonic
:
5233 err_msg
= _("unsupported with Intel mnemonic");
5235 case unsupported_syntax
:
5236 err_msg
= _("unsupported syntax");
5239 as_bad (_("unsupported instruction `%s'"),
5240 current_templates
->start
->name
);
5242 case invalid_vsib_address
:
5243 err_msg
= _("invalid VSIB address");
5245 case invalid_vector_register_set
:
5246 err_msg
= _("mask, index, and destination registers must be distinct");
5248 case unsupported_vector_index_register
:
5249 err_msg
= _("unsupported vector index register");
5251 case unsupported_broadcast
:
5252 err_msg
= _("unsupported broadcast");
5254 case broadcast_not_on_src_operand
:
5255 err_msg
= _("broadcast not on source memory operand");
5257 case broadcast_needed
:
5258 err_msg
= _("broadcast is needed for operand of such type");
5260 case unsupported_masking
:
5261 err_msg
= _("unsupported masking");
5263 case mask_not_on_destination
:
5264 err_msg
= _("mask not on destination operand");
5266 case no_default_mask
:
5267 err_msg
= _("default mask isn't allowed");
5269 case unsupported_rc_sae
:
5270 err_msg
= _("unsupported static rounding/sae");
5272 case rc_sae_operand_not_last_imm
:
5274 err_msg
= _("RC/SAE operand must precede immediate operands");
5276 err_msg
= _("RC/SAE operand must follow immediate operands");
5278 case invalid_register_operand
:
5279 err_msg
= _("invalid register operand");
5282 as_bad (_("%s for `%s'"), err_msg
,
5283 current_templates
->start
->name
);
5287 if (!quiet_warnings
)
5290 && (i
.types
[0].bitfield
.jumpabsolute
5291 != operand_types
[0].bitfield
.jumpabsolute
))
5293 as_warn (_("indirect %s without `*'"), t
->name
);
5296 if (t
->opcode_modifier
.isprefix
5297 && t
->opcode_modifier
.ignoresize
)
5299 /* Warn them that a data or address size prefix doesn't
5300 affect assembly of the next line of code. */
5301 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5305 /* Copy the template we found. */
5308 if (addr_prefix_disp
!= -1)
5309 i
.tm
.operand_types
[addr_prefix_disp
]
5310 = operand_types
[addr_prefix_disp
];
5312 if (found_reverse_match
)
5314 /* If we found a reverse match we must alter the opcode
5315 direction bit. found_reverse_match holds bits to change
5316 (different for int & float insns). */
5318 i
.tm
.base_opcode
^= found_reverse_match
;
5320 i
.tm
.operand_types
[0] = operand_types
[1];
5321 i
.tm
.operand_types
[1] = operand_types
[0];
5330 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5331 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5333 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5335 as_bad (_("`%s' operand %d must use `%ses' segment"),
5341 /* There's only ever one segment override allowed per instruction.
5342 This instruction possibly has a legal segment override on the
5343 second operand, so copy the segment to where non-string
5344 instructions store it, allowing common code. */
5345 i
.seg
[0] = i
.seg
[1];
5347 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5349 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5351 as_bad (_("`%s' operand %d must use `%ses' segment"),
5362 process_suffix (void)
5364 /* If matched instruction specifies an explicit instruction mnemonic
5366 if (i
.tm
.opcode_modifier
.size16
)
5367 i
.suffix
= WORD_MNEM_SUFFIX
;
5368 else if (i
.tm
.opcode_modifier
.size32
)
5369 i
.suffix
= LONG_MNEM_SUFFIX
;
5370 else if (i
.tm
.opcode_modifier
.size64
)
5371 i
.suffix
= QWORD_MNEM_SUFFIX
;
5372 else if (i
.reg_operands
)
5374 /* If there's no instruction mnemonic suffix we try to invent one
5375 based on register operands. */
5378 /* We take i.suffix from the last register operand specified,
5379 Destination register type is more significant than source
5380 register type. crc32 in SSE4.2 prefers source register
5382 if (i
.tm
.base_opcode
== 0xf20f38f1)
5384 if (i
.types
[0].bitfield
.reg16
)
5385 i
.suffix
= WORD_MNEM_SUFFIX
;
5386 else if (i
.types
[0].bitfield
.reg32
)
5387 i
.suffix
= LONG_MNEM_SUFFIX
;
5388 else if (i
.types
[0].bitfield
.reg64
)
5389 i
.suffix
= QWORD_MNEM_SUFFIX
;
5391 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5393 if (i
.types
[0].bitfield
.reg8
)
5394 i
.suffix
= BYTE_MNEM_SUFFIX
;
5401 if (i
.tm
.base_opcode
== 0xf20f38f1
5402 || i
.tm
.base_opcode
== 0xf20f38f0)
5404 /* We have to know the operand size for crc32. */
5405 as_bad (_("ambiguous memory operand size for `%s`"),
5410 for (op
= i
.operands
; --op
>= 0;)
5411 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5412 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5414 if (i
.types
[op
].bitfield
.reg8
)
5416 i
.suffix
= BYTE_MNEM_SUFFIX
;
5419 else if (i
.types
[op
].bitfield
.reg16
)
5421 i
.suffix
= WORD_MNEM_SUFFIX
;
5424 else if (i
.types
[op
].bitfield
.reg32
)
5426 i
.suffix
= LONG_MNEM_SUFFIX
;
5429 else if (i
.types
[op
].bitfield
.reg64
)
5431 i
.suffix
= QWORD_MNEM_SUFFIX
;
5437 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5440 && i
.tm
.opcode_modifier
.ignoresize
5441 && i
.tm
.opcode_modifier
.no_bsuf
)
5443 else if (!check_byte_reg ())
5446 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5449 && i
.tm
.opcode_modifier
.ignoresize
5450 && i
.tm
.opcode_modifier
.no_lsuf
)
5452 else if (!check_long_reg ())
5455 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5458 && i
.tm
.opcode_modifier
.ignoresize
5459 && i
.tm
.opcode_modifier
.no_qsuf
)
5461 else if (!check_qword_reg ())
5464 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5467 && i
.tm
.opcode_modifier
.ignoresize
5468 && i
.tm
.opcode_modifier
.no_wsuf
)
5470 else if (!check_word_reg ())
5473 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5474 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5475 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5477 /* Skip if the instruction has x/y/z suffix. match_template
5478 should check if it is a valid suffix. */
5480 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5481 /* Do nothing if the instruction is going to ignore the prefix. */
5486 else if (i
.tm
.opcode_modifier
.defaultsize
5488 /* exclude fldenv/frstor/fsave/fstenv */
5489 && i
.tm
.opcode_modifier
.no_ssuf
)
5491 i
.suffix
= stackop_size
;
5493 else if (intel_syntax
5495 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5496 || i
.tm
.opcode_modifier
.jumpbyte
5497 || i
.tm
.opcode_modifier
.jumpintersegment
5498 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5499 && i
.tm
.extension_opcode
<= 3)))
5504 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5506 i
.suffix
= QWORD_MNEM_SUFFIX
;
5511 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5512 i
.suffix
= LONG_MNEM_SUFFIX
;
5515 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5516 i
.suffix
= WORD_MNEM_SUFFIX
;
5525 if (i
.tm
.opcode_modifier
.w
)
5527 as_bad (_("no instruction mnemonic suffix given and "
5528 "no register operands; can't size instruction"));
5534 unsigned int suffixes
;
5536 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5537 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5539 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5541 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5543 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5545 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5548 /* There are more than suffix matches. */
5549 if (i
.tm
.opcode_modifier
.w
5550 || ((suffixes
& (suffixes
- 1))
5551 && !i
.tm
.opcode_modifier
.defaultsize
5552 && !i
.tm
.opcode_modifier
.ignoresize
))
5554 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5560 /* Change the opcode based on the operand size given by i.suffix;
5561 We don't need to change things for byte insns. */
5564 && i
.suffix
!= BYTE_MNEM_SUFFIX
5565 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5566 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5567 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5569 /* It's not a byte, select word/dword operation. */
5570 if (i
.tm
.opcode_modifier
.w
)
5572 if (i
.tm
.opcode_modifier
.shortform
)
5573 i
.tm
.base_opcode
|= 8;
5575 i
.tm
.base_opcode
|= 1;
5578 /* Now select between word & dword operations via the operand
5579 size prefix, except for instructions that will ignore this
5581 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5583 /* The address size override prefix changes the size of the
5585 if ((flag_code
== CODE_32BIT
5586 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5587 || (flag_code
!= CODE_32BIT
5588 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5589 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5592 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5593 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5594 && !i
.tm
.opcode_modifier
.ignoresize
5595 && !i
.tm
.opcode_modifier
.floatmf
5596 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5597 || (flag_code
== CODE_64BIT
5598 && i
.tm
.opcode_modifier
.jumpbyte
)))
5600 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5602 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5603 prefix
= ADDR_PREFIX_OPCODE
;
5605 if (!add_prefix (prefix
))
5609 /* Set mode64 for an operand. */
5610 if (i
.suffix
== QWORD_MNEM_SUFFIX
5611 && flag_code
== CODE_64BIT
5612 && !i
.tm
.opcode_modifier
.norex64
)
5614 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5615 need rex64. cmpxchg8b is also a special case. */
5616 if (! (i
.operands
== 2
5617 && i
.tm
.base_opcode
== 0x90
5618 && i
.tm
.extension_opcode
== None
5619 && operand_type_equal (&i
.types
[0], &acc64
)
5620 && operand_type_equal (&i
.types
[1], &acc64
))
5621 && ! (i
.operands
== 1
5622 && i
.tm
.base_opcode
== 0xfc7
5623 && i
.tm
.extension_opcode
== 1
5624 && !operand_type_check (i
.types
[0], reg
)
5625 && operand_type_check (i
.types
[0], anymem
)))
5629 /* Size floating point instruction. */
5630 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5631 if (i
.tm
.opcode_modifier
.floatmf
)
5632 i
.tm
.base_opcode
^= 4;
5639 check_byte_reg (void)
5643 for (op
= i
.operands
; --op
>= 0;)
5645 /* If this is an eight bit register, it's OK. If it's the 16 or
5646 32 bit version of an eight bit register, we will just use the
5647 low portion, and that's OK too. */
5648 if (i
.types
[op
].bitfield
.reg8
)
5651 /* I/O port address operands are OK too. */
5652 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5655 /* crc32 doesn't generate this warning. */
5656 if (i
.tm
.base_opcode
== 0xf20f38f0)
5659 if ((i
.types
[op
].bitfield
.reg16
5660 || i
.types
[op
].bitfield
.reg32
5661 || i
.types
[op
].bitfield
.reg64
)
5662 && i
.op
[op
].regs
->reg_num
< 4
5663 /* Prohibit these changes in 64bit mode, since the lowering
5664 would be more complicated. */
5665 && flag_code
!= CODE_64BIT
)
5667 #if REGISTER_WARNINGS
5668 if (!quiet_warnings
)
5669 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5671 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5672 ? REGNAM_AL
- REGNAM_AX
5673 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5675 i
.op
[op
].regs
->reg_name
,
5680 /* Any other register is bad. */
5681 if (i
.types
[op
].bitfield
.reg16
5682 || i
.types
[op
].bitfield
.reg32
5683 || i
.types
[op
].bitfield
.reg64
5684 || i
.types
[op
].bitfield
.regmmx
5685 || i
.types
[op
].bitfield
.regxmm
5686 || i
.types
[op
].bitfield
.regymm
5687 || i
.types
[op
].bitfield
.regzmm
5688 || i
.types
[op
].bitfield
.sreg2
5689 || i
.types
[op
].bitfield
.sreg3
5690 || i
.types
[op
].bitfield
.control
5691 || i
.types
[op
].bitfield
.debug
5692 || i
.types
[op
].bitfield
.test
5693 || i
.types
[op
].bitfield
.floatreg
5694 || i
.types
[op
].bitfield
.floatacc
)
5696 as_bad (_("`%s%s' not allowed with `%s%c'"),
5698 i
.op
[op
].regs
->reg_name
,
5708 check_long_reg (void)
5712 for (op
= i
.operands
; --op
>= 0;)
5713 /* Reject eight bit registers, except where the template requires
5714 them. (eg. movzb) */
5715 if (i
.types
[op
].bitfield
.reg8
5716 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5717 || i
.tm
.operand_types
[op
].bitfield
.reg32
5718 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5720 as_bad (_("`%s%s' not allowed with `%s%c'"),
5722 i
.op
[op
].regs
->reg_name
,
5727 /* Warn if the e prefix on a general reg is missing. */
5728 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5729 && i
.types
[op
].bitfield
.reg16
5730 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5731 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5733 /* Prohibit these changes in the 64bit mode, since the
5734 lowering is more complicated. */
5735 if (flag_code
== CODE_64BIT
)
5737 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5738 register_prefix
, i
.op
[op
].regs
->reg_name
,
5742 #if REGISTER_WARNINGS
5743 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5745 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5746 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5749 /* Warn if the r prefix on a general reg is present. */
5750 else if (i
.types
[op
].bitfield
.reg64
5751 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5752 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5755 && i
.tm
.opcode_modifier
.toqword
5756 && !i
.types
[0].bitfield
.regxmm
)
5758 /* Convert to QWORD. We want REX byte. */
5759 i
.suffix
= QWORD_MNEM_SUFFIX
;
5763 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5764 register_prefix
, i
.op
[op
].regs
->reg_name
,
5773 check_qword_reg (void)
5777 for (op
= i
.operands
; --op
>= 0; )
5778 /* Reject eight bit registers, except where the template requires
5779 them. (eg. movzb) */
5780 if (i
.types
[op
].bitfield
.reg8
5781 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5782 || i
.tm
.operand_types
[op
].bitfield
.reg32
5783 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5785 as_bad (_("`%s%s' not allowed with `%s%c'"),
5787 i
.op
[op
].regs
->reg_name
,
5792 /* Warn if the r prefix on a general reg is missing. */
5793 else if ((i
.types
[op
].bitfield
.reg16
5794 || i
.types
[op
].bitfield
.reg32
)
5795 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5796 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5798 /* Prohibit these changes in the 64bit mode, since the
5799 lowering is more complicated. */
5801 && i
.tm
.opcode_modifier
.todword
5802 && !i
.types
[0].bitfield
.regxmm
)
5804 /* Convert to DWORD. We don't want REX byte. */
5805 i
.suffix
= LONG_MNEM_SUFFIX
;
5809 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5810 register_prefix
, i
.op
[op
].regs
->reg_name
,
5819 check_word_reg (void)
5822 for (op
= i
.operands
; --op
>= 0;)
5823 /* Reject eight bit registers, except where the template requires
5824 them. (eg. movzb) */
5825 if (i
.types
[op
].bitfield
.reg8
5826 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5827 || i
.tm
.operand_types
[op
].bitfield
.reg32
5828 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5830 as_bad (_("`%s%s' not allowed with `%s%c'"),
5832 i
.op
[op
].regs
->reg_name
,
5837 /* Warn if the e or r prefix on a general reg is present. */
5838 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5839 && (i
.types
[op
].bitfield
.reg32
5840 || i
.types
[op
].bitfield
.reg64
)
5841 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5842 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5844 /* Prohibit these changes in the 64bit mode, since the
5845 lowering is more complicated. */
5846 if (flag_code
== CODE_64BIT
)
5848 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5849 register_prefix
, i
.op
[op
].regs
->reg_name
,
5853 #if REGISTER_WARNINGS
5854 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5856 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5857 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5864 update_imm (unsigned int j
)
5866 i386_operand_type overlap
= i
.types
[j
];
5867 if ((overlap
.bitfield
.imm8
5868 || overlap
.bitfield
.imm8s
5869 || overlap
.bitfield
.imm16
5870 || overlap
.bitfield
.imm32
5871 || overlap
.bitfield
.imm32s
5872 || overlap
.bitfield
.imm64
)
5873 && !operand_type_equal (&overlap
, &imm8
)
5874 && !operand_type_equal (&overlap
, &imm8s
)
5875 && !operand_type_equal (&overlap
, &imm16
)
5876 && !operand_type_equal (&overlap
, &imm32
)
5877 && !operand_type_equal (&overlap
, &imm32s
)
5878 && !operand_type_equal (&overlap
, &imm64
))
5882 i386_operand_type temp
;
5884 operand_type_set (&temp
, 0);
5885 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5887 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5888 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5890 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5891 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5892 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5894 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5895 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5898 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5901 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5902 || operand_type_equal (&overlap
, &imm16_32
)
5903 || operand_type_equal (&overlap
, &imm16_32s
))
5905 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5910 if (!operand_type_equal (&overlap
, &imm8
)
5911 && !operand_type_equal (&overlap
, &imm8s
)
5912 && !operand_type_equal (&overlap
, &imm16
)
5913 && !operand_type_equal (&overlap
, &imm32
)
5914 && !operand_type_equal (&overlap
, &imm32s
)
5915 && !operand_type_equal (&overlap
, &imm64
))
5917 as_bad (_("no instruction mnemonic suffix given; "
5918 "can't determine immediate size"));
5922 i
.types
[j
] = overlap
;
5932 /* Update the first 2 immediate operands. */
5933 n
= i
.operands
> 2 ? 2 : i
.operands
;
5936 for (j
= 0; j
< n
; j
++)
5937 if (update_imm (j
) == 0)
5940 /* The 3rd operand can't be immediate operand. */
5941 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5948 bad_implicit_operand (int xmm
)
5950 const char *ireg
= xmm
? "xmm0" : "ymm0";
5953 as_bad (_("the last operand of `%s' must be `%s%s'"),
5954 i
.tm
.name
, register_prefix
, ireg
);
5956 as_bad (_("the first operand of `%s' must be `%s%s'"),
5957 i
.tm
.name
, register_prefix
, ireg
);
5962 process_operands (void)
5964 /* Default segment register this instruction will use for memory
5965 accesses. 0 means unknown. This is only for optimizing out
5966 unnecessary segment overrides. */
5967 const seg_entry
*default_seg
= 0;
5969 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5971 unsigned int dupl
= i
.operands
;
5972 unsigned int dest
= dupl
- 1;
5975 /* The destination must be an xmm register. */
5976 gas_assert (i
.reg_operands
5977 && MAX_OPERANDS
> dupl
5978 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5980 if (i
.tm
.opcode_modifier
.firstxmm0
)
5982 /* The first operand is implicit and must be xmm0. */
5983 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5984 if (register_number (i
.op
[0].regs
) != 0)
5985 return bad_implicit_operand (1);
5987 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5989 /* Keep xmm0 for instructions with VEX prefix and 3
5995 /* We remove the first xmm0 and keep the number of
5996 operands unchanged, which in fact duplicates the
5998 for (j
= 1; j
< i
.operands
; j
++)
6000 i
.op
[j
- 1] = i
.op
[j
];
6001 i
.types
[j
- 1] = i
.types
[j
];
6002 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6006 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6008 gas_assert ((MAX_OPERANDS
- 1) > dupl
6009 && (i
.tm
.opcode_modifier
.vexsources
6012 /* Add the implicit xmm0 for instructions with VEX prefix
6014 for (j
= i
.operands
; j
> 0; j
--)
6016 i
.op
[j
] = i
.op
[j
- 1];
6017 i
.types
[j
] = i
.types
[j
- 1];
6018 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6021 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6022 i
.types
[0] = regxmm
;
6023 i
.tm
.operand_types
[0] = regxmm
;
6026 i
.reg_operands
+= 2;
6031 i
.op
[dupl
] = i
.op
[dest
];
6032 i
.types
[dupl
] = i
.types
[dest
];
6033 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6042 i
.op
[dupl
] = i
.op
[dest
];
6043 i
.types
[dupl
] = i
.types
[dest
];
6044 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6047 if (i
.tm
.opcode_modifier
.immext
)
6050 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6054 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6055 gas_assert (i
.reg_operands
6056 && (operand_type_equal (&i
.types
[0], ®xmm
)
6057 || operand_type_equal (&i
.types
[0], ®ymm
)
6058 || operand_type_equal (&i
.types
[0], ®zmm
)));
6059 if (register_number (i
.op
[0].regs
) != 0)
6060 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6062 for (j
= 1; j
< i
.operands
; j
++)
6064 i
.op
[j
- 1] = i
.op
[j
];
6065 i
.types
[j
- 1] = i
.types
[j
];
6067 /* We need to adjust fields in i.tm since they are used by
6068 build_modrm_byte. */
6069 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6076 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6078 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6079 gas_assert (i
.operands
>= 2
6080 && (operand_type_equal (&i
.types
[1], ®xmm
)
6081 || operand_type_equal (&i
.types
[1], ®ymm
)
6082 || operand_type_equal (&i
.types
[1], ®zmm
)));
6083 unsigned int regnum
= register_number (i
.op
[1].regs
);
6084 unsigned int first_reg_in_group
= regnum
& ~3;
6085 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6086 if (regnum
!= first_reg_in_group
) {
6087 as_warn (_("the second source register `%s%s' implicitly denotes"
6088 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6089 register_prefix
, i
.op
[1].regs
->reg_name
,
6090 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6091 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6095 else if (i
.tm
.opcode_modifier
.regkludge
)
6097 /* The imul $imm, %reg instruction is converted into
6098 imul $imm, %reg, %reg, and the clr %reg instruction
6099 is converted into xor %reg, %reg. */
6101 unsigned int first_reg_op
;
6103 if (operand_type_check (i
.types
[0], reg
))
6107 /* Pretend we saw the extra register operand. */
6108 gas_assert (i
.reg_operands
== 1
6109 && i
.op
[first_reg_op
+ 1].regs
== 0);
6110 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6111 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6116 if (i
.tm
.opcode_modifier
.shortform
)
6118 if (i
.types
[0].bitfield
.sreg2
6119 || i
.types
[0].bitfield
.sreg3
)
6121 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6122 && i
.op
[0].regs
->reg_num
== 1)
6124 as_bad (_("you can't `pop %scs'"), register_prefix
);
6127 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6128 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6133 /* The register or float register operand is in operand
6137 if (i
.types
[0].bitfield
.floatreg
6138 || operand_type_check (i
.types
[0], reg
))
6142 /* Register goes in low 3 bits of opcode. */
6143 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6144 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6146 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6148 /* Warn about some common errors, but press on regardless.
6149 The first case can be generated by gcc (<= 2.8.1). */
6150 if (i
.operands
== 2)
6152 /* Reversed arguments on faddp, fsubp, etc. */
6153 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6154 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6155 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6159 /* Extraneous `l' suffix on fp insn. */
6160 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6161 register_prefix
, i
.op
[0].regs
->reg_name
);
6166 else if (i
.tm
.opcode_modifier
.modrm
)
6168 /* The opcode is completed (modulo i.tm.extension_opcode which
6169 must be put into the modrm byte). Now, we make the modrm and
6170 index base bytes based on all the info we've collected. */
6172 default_seg
= build_modrm_byte ();
6174 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6178 else if (i
.tm
.opcode_modifier
.isstring
)
6180 /* For the string instructions that allow a segment override
6181 on one of their operands, the default segment is ds. */
6185 if (i
.tm
.base_opcode
== 0x8d /* lea */
6188 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6190 /* If a segment was explicitly specified, and the specified segment
6191 is not the default, use an opcode prefix to select it. If we
6192 never figured out what the default segment is, then default_seg
6193 will be zero at this point, and the specified segment prefix will
6195 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6197 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6203 static const seg_entry
*
6204 build_modrm_byte (void)
6206 const seg_entry
*default_seg
= 0;
6207 unsigned int source
, dest
;
6210 /* The first operand of instructions with VEX prefix and 3 sources
6211 must be VEX_Imm4. */
6212 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6215 unsigned int nds
, reg_slot
;
6218 if (i
.tm
.opcode_modifier
.veximmext
6219 && i
.tm
.opcode_modifier
.immext
)
6221 dest
= i
.operands
- 2;
6222 gas_assert (dest
== 3);
6225 dest
= i
.operands
- 1;
6228 /* There are 2 kinds of instructions:
6229 1. 5 operands: 4 register operands or 3 register operands
6230 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6231 VexW0 or VexW1. The destination must be either XMM, YMM or
6233 2. 4 operands: 4 register operands or 3 register operands
6234 plus 1 memory operand, VexXDS, and VexImmExt */
6235 gas_assert ((i
.reg_operands
== 4
6236 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6237 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6238 && (i
.tm
.opcode_modifier
.veximmext
6239 || (i
.imm_operands
== 1
6240 && i
.types
[0].bitfield
.vec_imm4
6241 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6242 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6243 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6244 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6245 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6247 if (i
.imm_operands
== 0)
6249 /* When there is no immediate operand, generate an 8bit
6250 immediate operand to encode the first operand. */
6251 exp
= &im_expressions
[i
.imm_operands
++];
6252 i
.op
[i
.operands
].imms
= exp
;
6253 i
.types
[i
.operands
] = imm8
;
6255 /* If VexW1 is set, the first operand is the source and
6256 the second operand is encoded in the immediate operand. */
6257 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6268 /* FMA swaps REG and NDS. */
6269 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6277 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6279 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6281 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6283 exp
->X_op
= O_constant
;
6284 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6285 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6289 unsigned int imm_slot
;
6291 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6293 /* If VexW0 is set, the third operand is the source and
6294 the second operand is encoded in the immediate
6301 /* VexW1 is set, the second operand is the source and
6302 the third operand is encoded in the immediate
6308 if (i
.tm
.opcode_modifier
.immext
)
6310 /* When ImmExt is set, the immediate byte is the last
6312 imm_slot
= i
.operands
- 1;
6320 /* Turn on Imm8 so that output_imm will generate it. */
6321 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6324 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6326 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6328 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6330 i
.op
[imm_slot
].imms
->X_add_number
6331 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6332 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6335 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6336 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6338 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6340 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6345 /* i.reg_operands MUST be the number of real register operands;
6346 implicit registers do not count. If there are 3 register
6347 operands, it must be a instruction with VexNDS. For a
6348 instruction with VexNDD, the destination register is encoded
6349 in VEX prefix. If there are 4 register operands, it must be
6350 a instruction with VEX prefix and 3 sources. */
6351 if (i
.mem_operands
== 0
6352 && ((i
.reg_operands
== 2
6353 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6354 || (i
.reg_operands
== 3
6355 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6356 || (i
.reg_operands
== 4 && vex_3_sources
)))
6364 /* When there are 3 operands, one of them may be immediate,
6365 which may be the first or the last operand. Otherwise,
6366 the first operand must be shift count register (cl) or it
6367 is an instruction with VexNDS. */
6368 gas_assert (i
.imm_operands
== 1
6369 || (i
.imm_operands
== 0
6370 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6371 || i
.types
[0].bitfield
.shiftcount
)));
6372 if (operand_type_check (i
.types
[0], imm
)
6373 || i
.types
[0].bitfield
.shiftcount
)
6379 /* When there are 4 operands, the first two must be 8bit
6380 immediate operands. The source operand will be the 3rd
6383 For instructions with VexNDS, if the first operand
6384 an imm8, the source operand is the 2nd one. If the last
6385 operand is imm8, the source operand is the first one. */
6386 gas_assert ((i
.imm_operands
== 2
6387 && i
.types
[0].bitfield
.imm8
6388 && i
.types
[1].bitfield
.imm8
)
6389 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6390 && i
.imm_operands
== 1
6391 && (i
.types
[0].bitfield
.imm8
6392 || i
.types
[i
.operands
- 1].bitfield
.imm8
6394 if (i
.imm_operands
== 2)
6398 if (i
.types
[0].bitfield
.imm8
)
6405 if (i
.tm
.opcode_modifier
.evex
)
6407 /* For EVEX instructions, when there are 5 operands, the
6408 first one must be immediate operand. If the second one
6409 is immediate operand, the source operand is the 3th
6410 one. If the last one is immediate operand, the source
6411 operand is the 2nd one. */
6412 gas_assert (i
.imm_operands
== 2
6413 && i
.tm
.opcode_modifier
.sae
6414 && operand_type_check (i
.types
[0], imm
));
6415 if (operand_type_check (i
.types
[1], imm
))
6417 else if (operand_type_check (i
.types
[4], imm
))
6431 /* RC/SAE operand could be between DEST and SRC. That happens
6432 when one operand is GPR and the other one is XMM/YMM/ZMM
6434 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6437 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6439 /* For instructions with VexNDS, the register-only source
6440 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6441 register. It is encoded in VEX prefix. We need to
6442 clear RegMem bit before calling operand_type_equal. */
6444 i386_operand_type op
;
6447 /* Check register-only source operand when two source
6448 operands are swapped. */
6449 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6450 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6458 op
= i
.tm
.operand_types
[vvvv
];
6459 op
.bitfield
.regmem
= 0;
6460 if ((dest
+ 1) >= i
.operands
6461 || (!op
.bitfield
.reg32
6462 && !op
.bitfield
.reg64
6463 && !operand_type_equal (&op
, ®xmm
)
6464 && !operand_type_equal (&op
, ®ymm
)
6465 && !operand_type_equal (&op
, ®zmm
)
6466 && !operand_type_equal (&op
, ®mask
)))
6468 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6474 /* One of the register operands will be encoded in the i.tm.reg
6475 field, the other in the combined i.tm.mode and i.tm.regmem
6476 fields. If no form of this instruction supports a memory
6477 destination operand, then we assume the source operand may
6478 sometimes be a memory operand and so we need to store the
6479 destination in the i.rm.reg field. */
6480 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6481 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6483 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6484 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6485 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6487 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6489 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6491 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6496 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6497 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6498 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6500 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6502 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6504 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6507 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6509 if (!i
.types
[0].bitfield
.control
6510 && !i
.types
[1].bitfield
.control
)
6512 i
.rex
&= ~(REX_R
| REX_B
);
6513 add_prefix (LOCK_PREFIX_OPCODE
);
6517 { /* If it's not 2 reg operands... */
6522 unsigned int fake_zero_displacement
= 0;
6525 for (op
= 0; op
< i
.operands
; op
++)
6526 if (operand_type_check (i
.types
[op
], anymem
))
6528 gas_assert (op
< i
.operands
);
6530 if (i
.tm
.opcode_modifier
.vecsib
)
6532 if (i
.index_reg
->reg_num
== RegEiz
6533 || i
.index_reg
->reg_num
== RegRiz
)
6536 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6539 i
.sib
.base
= NO_BASE_REGISTER
;
6540 i
.sib
.scale
= i
.log2_scale_factor
;
6541 i
.types
[op
].bitfield
.disp8
= 0;
6542 i
.types
[op
].bitfield
.disp16
= 0;
6543 i
.types
[op
].bitfield
.disp64
= 0;
6544 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6546 /* Must be 32 bit */
6547 i
.types
[op
].bitfield
.disp32
= 1;
6548 i
.types
[op
].bitfield
.disp32s
= 0;
6552 i
.types
[op
].bitfield
.disp32
= 0;
6553 i
.types
[op
].bitfield
.disp32s
= 1;
6556 i
.sib
.index
= i
.index_reg
->reg_num
;
6557 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6559 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6565 if (i
.base_reg
== 0)
6568 if (!i
.disp_operands
)
6569 fake_zero_displacement
= 1;
6570 if (i
.index_reg
== 0)
6572 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6573 /* Operand is just <disp> */
6574 if (flag_code
== CODE_64BIT
)
6576 /* 64bit mode overwrites the 32bit absolute
6577 addressing by RIP relative addressing and
6578 absolute addressing is encoded by one of the
6579 redundant SIB forms. */
6580 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6581 i
.sib
.base
= NO_BASE_REGISTER
;
6582 i
.sib
.index
= NO_INDEX_REGISTER
;
6583 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6584 ? disp32s
: disp32
);
6586 else if ((flag_code
== CODE_16BIT
)
6587 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6589 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6590 i
.types
[op
] = disp16
;
6594 i
.rm
.regmem
= NO_BASE_REGISTER
;
6595 i
.types
[op
] = disp32
;
6598 else if (!i
.tm
.opcode_modifier
.vecsib
)
6600 /* !i.base_reg && i.index_reg */
6601 if (i
.index_reg
->reg_num
== RegEiz
6602 || i
.index_reg
->reg_num
== RegRiz
)
6603 i
.sib
.index
= NO_INDEX_REGISTER
;
6605 i
.sib
.index
= i
.index_reg
->reg_num
;
6606 i
.sib
.base
= NO_BASE_REGISTER
;
6607 i
.sib
.scale
= i
.log2_scale_factor
;
6608 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6609 i
.types
[op
].bitfield
.disp8
= 0;
6610 i
.types
[op
].bitfield
.disp16
= 0;
6611 i
.types
[op
].bitfield
.disp64
= 0;
6612 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6614 /* Must be 32 bit */
6615 i
.types
[op
].bitfield
.disp32
= 1;
6616 i
.types
[op
].bitfield
.disp32s
= 0;
6620 i
.types
[op
].bitfield
.disp32
= 0;
6621 i
.types
[op
].bitfield
.disp32s
= 1;
6623 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6627 /* RIP addressing for 64bit mode. */
6628 else if (i
.base_reg
->reg_num
== RegRip
||
6629 i
.base_reg
->reg_num
== RegEip
)
6631 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6632 i
.rm
.regmem
= NO_BASE_REGISTER
;
6633 i
.types
[op
].bitfield
.disp8
= 0;
6634 i
.types
[op
].bitfield
.disp16
= 0;
6635 i
.types
[op
].bitfield
.disp32
= 0;
6636 i
.types
[op
].bitfield
.disp32s
= 1;
6637 i
.types
[op
].bitfield
.disp64
= 0;
6638 i
.flags
[op
] |= Operand_PCrel
;
6639 if (! i
.disp_operands
)
6640 fake_zero_displacement
= 1;
6642 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6644 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6645 switch (i
.base_reg
->reg_num
)
6648 if (i
.index_reg
== 0)
6650 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6651 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6655 if (i
.index_reg
== 0)
6658 if (operand_type_check (i
.types
[op
], disp
) == 0)
6660 /* fake (%bp) into 0(%bp) */
6661 i
.types
[op
].bitfield
.disp8
= 1;
6662 fake_zero_displacement
= 1;
6665 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6666 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6668 default: /* (%si) -> 4 or (%di) -> 5 */
6669 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6671 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6673 else /* i.base_reg and 32/64 bit mode */
6675 if (flag_code
== CODE_64BIT
6676 && operand_type_check (i
.types
[op
], disp
))
6678 i386_operand_type temp
;
6679 operand_type_set (&temp
, 0);
6680 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6682 if (i
.prefix
[ADDR_PREFIX
] == 0)
6683 i
.types
[op
].bitfield
.disp32s
= 1;
6685 i
.types
[op
].bitfield
.disp32
= 1;
6688 if (!i
.tm
.opcode_modifier
.vecsib
)
6689 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6690 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6692 i
.sib
.base
= i
.base_reg
->reg_num
;
6693 /* x86-64 ignores REX prefix bit here to avoid decoder
6695 if (!(i
.base_reg
->reg_flags
& RegRex
)
6696 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6697 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6699 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6701 fake_zero_displacement
= 1;
6702 i
.types
[op
].bitfield
.disp8
= 1;
6704 i
.sib
.scale
= i
.log2_scale_factor
;
6705 if (i
.index_reg
== 0)
6707 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6708 /* <disp>(%esp) becomes two byte modrm with no index
6709 register. We've already stored the code for esp
6710 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6711 Any base register besides %esp will not use the
6712 extra modrm byte. */
6713 i
.sib
.index
= NO_INDEX_REGISTER
;
6715 else if (!i
.tm
.opcode_modifier
.vecsib
)
6717 if (i
.index_reg
->reg_num
== RegEiz
6718 || i
.index_reg
->reg_num
== RegRiz
)
6719 i
.sib
.index
= NO_INDEX_REGISTER
;
6721 i
.sib
.index
= i
.index_reg
->reg_num
;
6722 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6723 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6728 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6729 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6733 if (!fake_zero_displacement
6737 fake_zero_displacement
= 1;
6738 if (i
.disp_encoding
== disp_encoding_8bit
)
6739 i
.types
[op
].bitfield
.disp8
= 1;
6741 i
.types
[op
].bitfield
.disp32
= 1;
6743 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6747 if (fake_zero_displacement
)
6749 /* Fakes a zero displacement assuming that i.types[op]
6750 holds the correct displacement size. */
6753 gas_assert (i
.op
[op
].disps
== 0);
6754 exp
= &disp_expressions
[i
.disp_operands
++];
6755 i
.op
[op
].disps
= exp
;
6756 exp
->X_op
= O_constant
;
6757 exp
->X_add_number
= 0;
6758 exp
->X_add_symbol
= (symbolS
*) 0;
6759 exp
->X_op_symbol
= (symbolS
*) 0;
6767 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6769 if (operand_type_check (i
.types
[0], imm
))
6770 i
.vex
.register_specifier
= NULL
;
6773 /* VEX.vvvv encodes one of the sources when the first
6774 operand is not an immediate. */
6775 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6776 i
.vex
.register_specifier
= i
.op
[0].regs
;
6778 i
.vex
.register_specifier
= i
.op
[1].regs
;
6781 /* Destination is a XMM register encoded in the ModRM.reg
6783 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6784 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6787 /* ModRM.rm and VEX.B encodes the other source. */
6788 if (!i
.mem_operands
)
6792 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6793 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6795 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6797 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6801 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6803 i
.vex
.register_specifier
= i
.op
[2].regs
;
6804 if (!i
.mem_operands
)
6807 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6808 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6812 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6813 (if any) based on i.tm.extension_opcode. Again, we must be
6814 careful to make sure that segment/control/debug/test/MMX
6815 registers are coded into the i.rm.reg field. */
6816 else if (i
.reg_operands
)
6819 unsigned int vex_reg
= ~0;
6821 for (op
= 0; op
< i
.operands
; op
++)
6822 if (i
.types
[op
].bitfield
.reg8
6823 || i
.types
[op
].bitfield
.reg16
6824 || i
.types
[op
].bitfield
.reg32
6825 || i
.types
[op
].bitfield
.reg64
6826 || i
.types
[op
].bitfield
.regmmx
6827 || i
.types
[op
].bitfield
.regxmm
6828 || i
.types
[op
].bitfield
.regymm
6829 || i
.types
[op
].bitfield
.regbnd
6830 || i
.types
[op
].bitfield
.regzmm
6831 || i
.types
[op
].bitfield
.regmask
6832 || i
.types
[op
].bitfield
.sreg2
6833 || i
.types
[op
].bitfield
.sreg3
6834 || i
.types
[op
].bitfield
.control
6835 || i
.types
[op
].bitfield
.debug
6836 || i
.types
[op
].bitfield
.test
)
6841 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6843 /* For instructions with VexNDS, the register-only
6844 source operand is encoded in VEX prefix. */
6845 gas_assert (mem
!= (unsigned int) ~0);
6850 gas_assert (op
< i
.operands
);
6854 /* Check register-only source operand when two source
6855 operands are swapped. */
6856 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6857 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6861 gas_assert (mem
== (vex_reg
+ 1)
6862 && op
< i
.operands
);
6867 gas_assert (vex_reg
< i
.operands
);
6871 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6873 /* For instructions with VexNDD, the register destination
6874 is encoded in VEX prefix. */
6875 if (i
.mem_operands
== 0)
6877 /* There is no memory operand. */
6878 gas_assert ((op
+ 2) == i
.operands
);
6883 /* There are only 2 operands. */
6884 gas_assert (op
< 2 && i
.operands
== 2);
6889 gas_assert (op
< i
.operands
);
6891 if (vex_reg
!= (unsigned int) ~0)
6893 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6895 if (type
->bitfield
.reg32
!= 1
6896 && type
->bitfield
.reg64
!= 1
6897 && !operand_type_equal (type
, ®xmm
)
6898 && !operand_type_equal (type
, ®ymm
)
6899 && !operand_type_equal (type
, ®zmm
)
6900 && !operand_type_equal (type
, ®mask
))
6903 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6906 /* Don't set OP operand twice. */
6909 /* If there is an extension opcode to put here, the
6910 register number must be put into the regmem field. */
6911 if (i
.tm
.extension_opcode
!= None
)
6913 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6914 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6916 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6921 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6922 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6924 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6929 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6930 must set it to 3 to indicate this is a register operand
6931 in the regmem field. */
6932 if (!i
.mem_operands
)
6936 /* Fill in i.rm.reg field with extension opcode (if any). */
6937 if (i
.tm
.extension_opcode
!= None
)
6938 i
.rm
.reg
= i
.tm
.extension_opcode
;
6944 output_branch (void)
6950 relax_substateT subtype
;
6954 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6955 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6958 if (i
.prefix
[DATA_PREFIX
] != 0)
6964 /* Pentium4 branch hints. */
6965 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6966 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6971 if (i
.prefix
[REX_PREFIX
] != 0)
6977 /* BND prefixed jump. */
6978 if (i
.prefix
[BND_PREFIX
] != 0)
6980 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6984 if (i
.prefixes
!= 0 && !intel_syntax
)
6985 as_warn (_("skipping prefixes on this instruction"));
6987 /* It's always a symbol; End frag & setup for relax.
6988 Make sure there is enough room in this frag for the largest
6989 instruction we may generate in md_convert_frag. This is 2
6990 bytes for the opcode and room for the prefix and largest
6992 frag_grow (prefix
+ 2 + 4);
6993 /* Prefix and 1 opcode byte go in fr_fix. */
6994 p
= frag_more (prefix
+ 1);
6995 if (i
.prefix
[DATA_PREFIX
] != 0)
6996 *p
++ = DATA_PREFIX_OPCODE
;
6997 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6998 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6999 *p
++ = i
.prefix
[SEG_PREFIX
];
7000 if (i
.prefix
[REX_PREFIX
] != 0)
7001 *p
++ = i
.prefix
[REX_PREFIX
];
7002 *p
= i
.tm
.base_opcode
;
7004 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7005 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7006 else if (cpu_arch_flags
.bitfield
.cpui386
)
7007 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7009 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7012 sym
= i
.op
[0].disps
->X_add_symbol
;
7013 off
= i
.op
[0].disps
->X_add_number
;
7015 if (i
.op
[0].disps
->X_op
!= O_constant
7016 && i
.op
[0].disps
->X_op
!= O_symbol
)
7018 /* Handle complex expressions. */
7019 sym
= make_expr_symbol (i
.op
[0].disps
);
7023 /* 1 possible extra opcode + 4 byte displacement go in var part.
7024 Pass reloc in fr_var. */
7025 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7035 if (i
.tm
.opcode_modifier
.jumpbyte
)
7037 /* This is a loop or jecxz type instruction. */
7039 if (i
.prefix
[ADDR_PREFIX
] != 0)
7041 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7044 /* Pentium4 branch hints. */
7045 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7046 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7048 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7057 if (flag_code
== CODE_16BIT
)
7060 if (i
.prefix
[DATA_PREFIX
] != 0)
7062 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7072 if (i
.prefix
[REX_PREFIX
] != 0)
7074 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7078 /* BND prefixed jump. */
7079 if (i
.prefix
[BND_PREFIX
] != 0)
7081 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7085 if (i
.prefixes
!= 0 && !intel_syntax
)
7086 as_warn (_("skipping prefixes on this instruction"));
7088 p
= frag_more (i
.tm
.opcode_length
+ size
);
7089 switch (i
.tm
.opcode_length
)
7092 *p
++ = i
.tm
.base_opcode
>> 8;
7095 *p
++ = i
.tm
.base_opcode
;
7101 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7102 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7104 /* All jumps handled here are signed, but don't use a signed limit
7105 check for 32 and 16 bit jumps as we want to allow wrap around at
7106 4G and 64k respectively. */
7108 fixP
->fx_signed
= 1;
7112 output_interseg_jump (void)
7120 if (flag_code
== CODE_16BIT
)
7124 if (i
.prefix
[DATA_PREFIX
] != 0)
7130 if (i
.prefix
[REX_PREFIX
] != 0)
7140 if (i
.prefixes
!= 0 && !intel_syntax
)
7141 as_warn (_("skipping prefixes on this instruction"));
7143 /* 1 opcode; 2 segment; offset */
7144 p
= frag_more (prefix
+ 1 + 2 + size
);
7146 if (i
.prefix
[DATA_PREFIX
] != 0)
7147 *p
++ = DATA_PREFIX_OPCODE
;
7149 if (i
.prefix
[REX_PREFIX
] != 0)
7150 *p
++ = i
.prefix
[REX_PREFIX
];
7152 *p
++ = i
.tm
.base_opcode
;
7153 if (i
.op
[1].imms
->X_op
== O_constant
)
7155 offsetT n
= i
.op
[1].imms
->X_add_number
;
7158 && !fits_in_unsigned_word (n
)
7159 && !fits_in_signed_word (n
))
7161 as_bad (_("16-bit jump out of range"));
7164 md_number_to_chars (p
, n
, size
);
7167 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7168 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7169 if (i
.op
[0].imms
->X_op
!= O_constant
)
7170 as_bad (_("can't handle non absolute segment in `%s'"),
7172 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7178 fragS
*insn_start_frag
;
7179 offsetT insn_start_off
;
7181 /* Tie dwarf2 debug info to the address at the start of the insn.
7182 We can't do this after the insn has been output as the current
7183 frag may have been closed off. eg. by frag_var. */
7184 dwarf2_emit_insn (0);
7186 insn_start_frag
= frag_now
;
7187 insn_start_off
= frag_now_fix ();
7190 if (i
.tm
.opcode_modifier
.jump
)
7192 else if (i
.tm
.opcode_modifier
.jumpbyte
7193 || i
.tm
.opcode_modifier
.jumpdword
)
7195 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7196 output_interseg_jump ();
7199 /* Output normal instructions here. */
7203 unsigned int prefix
;
7206 && i
.tm
.base_opcode
== 0xfae
7208 && i
.imm_operands
== 1
7209 && (i
.op
[0].imms
->X_add_number
== 0xe8
7210 || i
.op
[0].imms
->X_add_number
== 0xf0
7211 || i
.op
[0].imms
->X_add_number
== 0xf8))
7213 /* Encode lfence, mfence, and sfence as
7214 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7215 offsetT val
= 0x240483f0ULL
;
7217 md_number_to_chars (p
, val
, 5);
7221 /* Some processors fail on LOCK prefix. This options makes
7222 assembler ignore LOCK prefix and serves as a workaround. */
7223 if (omit_lock_prefix
)
7225 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7227 i
.prefix
[LOCK_PREFIX
] = 0;
7230 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7231 don't need the explicit prefix. */
7232 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7234 switch (i
.tm
.opcode_length
)
7237 if (i
.tm
.base_opcode
& 0xff000000)
7239 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7244 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7246 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7247 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7250 if (prefix
!= REPE_PREFIX_OPCODE
7251 || (i
.prefix
[REP_PREFIX
]
7252 != REPE_PREFIX_OPCODE
))
7253 add_prefix (prefix
);
7256 add_prefix (prefix
);
7265 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7266 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7267 R_X86_64_GOTTPOFF relocation so that linker can safely
7268 perform IE->LE optimization. */
7269 if (x86_elf_abi
== X86_64_X32_ABI
7271 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7272 && i
.prefix
[REX_PREFIX
] == 0)
7273 add_prefix (REX_OPCODE
);
7276 /* The prefix bytes. */
7277 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7279 FRAG_APPEND_1_CHAR (*q
);
7283 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7288 /* REX byte is encoded in VEX prefix. */
7292 FRAG_APPEND_1_CHAR (*q
);
7295 /* There should be no other prefixes for instructions
7300 /* For EVEX instructions i.vrex should become 0 after
7301 build_evex_prefix. For VEX instructions upper 16 registers
7302 aren't available, so VREX should be 0. */
7305 /* Now the VEX prefix. */
7306 p
= frag_more (i
.vex
.length
);
7307 for (j
= 0; j
< i
.vex
.length
; j
++)
7308 p
[j
] = i
.vex
.bytes
[j
];
7311 /* Now the opcode; be careful about word order here! */
7312 if (i
.tm
.opcode_length
== 1)
7314 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7318 switch (i
.tm
.opcode_length
)
7322 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7323 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7327 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7337 /* Put out high byte first: can't use md_number_to_chars! */
7338 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7339 *p
= i
.tm
.base_opcode
& 0xff;
7342 /* Now the modrm byte and sib byte (if present). */
7343 if (i
.tm
.opcode_modifier
.modrm
)
7345 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7348 /* If i.rm.regmem == ESP (4)
7349 && i.rm.mode != (Register mode)
7351 ==> need second modrm byte. */
7352 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7354 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7355 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7357 | i
.sib
.scale
<< 6));
7360 if (i
.disp_operands
)
7361 output_disp (insn_start_frag
, insn_start_off
);
7364 output_imm (insn_start_frag
, insn_start_off
);
7370 pi ("" /*line*/, &i
);
7372 #endif /* DEBUG386 */
7375 /* Return the size of the displacement operand N. */
7378 disp_size (unsigned int n
)
7382 if (i
.types
[n
].bitfield
.disp64
)
7384 else if (i
.types
[n
].bitfield
.disp8
)
7386 else if (i
.types
[n
].bitfield
.disp16
)
7391 /* Return the size of the immediate operand N. */
7394 imm_size (unsigned int n
)
7397 if (i
.types
[n
].bitfield
.imm64
)
7399 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7401 else if (i
.types
[n
].bitfield
.imm16
)
7407 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7412 for (n
= 0; n
< i
.operands
; n
++)
7414 if (operand_type_check (i
.types
[n
], disp
))
7416 if (i
.op
[n
].disps
->X_op
== O_constant
)
7418 int size
= disp_size (n
);
7419 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7421 val
= offset_in_range (val
>> i
.memshift
, size
);
7422 p
= frag_more (size
);
7423 md_number_to_chars (p
, val
, size
);
7427 enum bfd_reloc_code_real reloc_type
;
7428 int size
= disp_size (n
);
7429 int sign
= i
.types
[n
].bitfield
.disp32s
;
7430 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7433 /* We can't have 8 bit displacement here. */
7434 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7436 /* The PC relative address is computed relative
7437 to the instruction boundary, so in case immediate
7438 fields follows, we need to adjust the value. */
7439 if (pcrel
&& i
.imm_operands
)
7444 for (n1
= 0; n1
< i
.operands
; n1
++)
7445 if (operand_type_check (i
.types
[n1
], imm
))
7447 /* Only one immediate is allowed for PC
7448 relative address. */
7449 gas_assert (sz
== 0);
7451 i
.op
[n
].disps
->X_add_number
-= sz
;
7453 /* We should find the immediate. */
7454 gas_assert (sz
!= 0);
7457 p
= frag_more (size
);
7458 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7460 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7461 && (((reloc_type
== BFD_RELOC_32
7462 || reloc_type
== BFD_RELOC_X86_64_32S
7463 || (reloc_type
== BFD_RELOC_64
7465 && (i
.op
[n
].disps
->X_op
== O_symbol
7466 || (i
.op
[n
].disps
->X_op
== O_add
7467 && ((symbol_get_value_expression
7468 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7470 || reloc_type
== BFD_RELOC_32_PCREL
))
7474 if (insn_start_frag
== frag_now
)
7475 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7480 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7481 for (fr
= insn_start_frag
->fr_next
;
7482 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7484 add
+= p
- frag_now
->fr_literal
;
7489 reloc_type
= BFD_RELOC_386_GOTPC
;
7490 i
.op
[n
].imms
->X_add_number
+= add
;
7492 else if (reloc_type
== BFD_RELOC_64
)
7493 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7495 /* Don't do the adjustment for x86-64, as there
7496 the pcrel addressing is relative to the _next_
7497 insn, and that is taken care of in other code. */
7498 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7500 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7501 size
, i
.op
[n
].disps
, pcrel
,
7503 /* Check for "call/jmp *mem", "mov mem, %reg",
7504 "test %reg, mem" and "binop mem, %reg" where binop
7505 is one of adc, add, and, cmp, or, sbb, sub, xor
7506 instructions. Always generate R_386_GOT32X for
7507 "sym*GOT" operand in 32-bit mode. */
7508 if ((generate_relax_relocations
7511 && i
.rm
.regmem
== 5))
7513 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7514 && ((i
.operands
== 1
7515 && i
.tm
.base_opcode
== 0xff
7516 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7518 && (i
.tm
.base_opcode
== 0x8b
7519 || i
.tm
.base_opcode
== 0x85
7520 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7524 fixP
->fx_tcbit
= i
.rex
!= 0;
7526 && (i
.base_reg
->reg_num
== RegRip
7527 || i
.base_reg
->reg_num
== RegEip
))
7528 fixP
->fx_tcbit2
= 1;
7531 fixP
->fx_tcbit2
= 1;
7539 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7544 for (n
= 0; n
< i
.operands
; n
++)
7546 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7547 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7550 if (operand_type_check (i
.types
[n
], imm
))
7552 if (i
.op
[n
].imms
->X_op
== O_constant
)
7554 int size
= imm_size (n
);
7557 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7559 p
= frag_more (size
);
7560 md_number_to_chars (p
, val
, size
);
7564 /* Not absolute_section.
7565 Need a 32-bit fixup (don't support 8bit
7566 non-absolute imms). Try to support other
7568 enum bfd_reloc_code_real reloc_type
;
7569 int size
= imm_size (n
);
7572 if (i
.types
[n
].bitfield
.imm32s
7573 && (i
.suffix
== QWORD_MNEM_SUFFIX
7574 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7579 p
= frag_more (size
);
7580 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7582 /* This is tough to explain. We end up with this one if we
7583 * have operands that look like
7584 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7585 * obtain the absolute address of the GOT, and it is strongly
7586 * preferable from a performance point of view to avoid using
7587 * a runtime relocation for this. The actual sequence of
7588 * instructions often look something like:
7593 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7595 * The call and pop essentially return the absolute address
7596 * of the label .L66 and store it in %ebx. The linker itself
7597 * will ultimately change the first operand of the addl so
7598 * that %ebx points to the GOT, but to keep things simple, the
7599 * .o file must have this operand set so that it generates not
7600 * the absolute address of .L66, but the absolute address of
7601 * itself. This allows the linker itself simply treat a GOTPC
7602 * relocation as asking for a pcrel offset to the GOT to be
7603 * added in, and the addend of the relocation is stored in the
7604 * operand field for the instruction itself.
7606 * Our job here is to fix the operand so that it would add
7607 * the correct offset so that %ebx would point to itself. The
7608 * thing that is tricky is that .-.L66 will point to the
7609 * beginning of the instruction, so we need to further modify
7610 * the operand so that it will point to itself. There are
7611 * other cases where you have something like:
7613 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7615 * and here no correction would be required. Internally in
7616 * the assembler we treat operands of this form as not being
7617 * pcrel since the '.' is explicitly mentioned, and I wonder
7618 * whether it would simplify matters to do it this way. Who
7619 * knows. In earlier versions of the PIC patches, the
7620 * pcrel_adjust field was used to store the correction, but
7621 * since the expression is not pcrel, I felt it would be
7622 * confusing to do it this way. */
7624 if ((reloc_type
== BFD_RELOC_32
7625 || reloc_type
== BFD_RELOC_X86_64_32S
7626 || reloc_type
== BFD_RELOC_64
)
7628 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7629 && (i
.op
[n
].imms
->X_op
== O_symbol
7630 || (i
.op
[n
].imms
->X_op
== O_add
7631 && ((symbol_get_value_expression
7632 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7637 if (insn_start_frag
== frag_now
)
7638 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7643 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7644 for (fr
= insn_start_frag
->fr_next
;
7645 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7647 add
+= p
- frag_now
->fr_literal
;
7651 reloc_type
= BFD_RELOC_386_GOTPC
;
7653 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7655 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7656 i
.op
[n
].imms
->X_add_number
+= add
;
7658 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7659 i
.op
[n
].imms
, 0, reloc_type
);
7665 /* x86_cons_fix_new is called via the expression parsing code when a
7666 reloc is needed. We use this hook to get the correct .got reloc. */
7667 static int cons_sign
= -1;
7670 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7671 expressionS
*exp
, bfd_reloc_code_real_type r
)
7673 r
= reloc (len
, 0, cons_sign
, r
);
7676 if (exp
->X_op
== O_secrel
)
7678 exp
->X_op
= O_symbol
;
7679 r
= BFD_RELOC_32_SECREL
;
7683 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7686 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7687 purpose of the `.dc.a' internal pseudo-op. */
7690 x86_address_bytes (void)
7692 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7694 return stdoutput
->arch_info
->bits_per_address
/ 8;
7697 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7699 # define lex_got(reloc, adjust, types) NULL
7701 /* Parse operands of the form
7702 <symbol>@GOTOFF+<nnn>
7703 and similar .plt or .got references.
7705 If we find one, set up the correct relocation in RELOC and copy the
7706 input string, minus the `@GOTOFF' into a malloc'd buffer for
7707 parsing by the calling routine. Return this buffer, and if ADJUST
7708 is non-null set it to the length of the string we removed from the
7709 input line. Otherwise return NULL. */
7711 lex_got (enum bfd_reloc_code_real
*rel
,
7713 i386_operand_type
*types
)
7715 /* Some of the relocations depend on the size of what field is to
7716 be relocated. But in our callers i386_immediate and i386_displacement
7717 we don't yet know the operand size (this will be set by insn
7718 matching). Hence we record the word32 relocation here,
7719 and adjust the reloc according to the real size in reloc(). */
7720 static const struct {
7723 const enum bfd_reloc_code_real rel
[2];
7724 const i386_operand_type types64
;
7726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7727 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7729 OPERAND_TYPE_IMM32_64
},
7731 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7732 BFD_RELOC_X86_64_PLTOFF64
},
7733 OPERAND_TYPE_IMM64
},
7734 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7735 BFD_RELOC_X86_64_PLT32
},
7736 OPERAND_TYPE_IMM32_32S_DISP32
},
7737 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7738 BFD_RELOC_X86_64_GOTPLT64
},
7739 OPERAND_TYPE_IMM64_DISP64
},
7740 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7741 BFD_RELOC_X86_64_GOTOFF64
},
7742 OPERAND_TYPE_IMM64_DISP64
},
7743 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7744 BFD_RELOC_X86_64_GOTPCREL
},
7745 OPERAND_TYPE_IMM32_32S_DISP32
},
7746 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7747 BFD_RELOC_X86_64_TLSGD
},
7748 OPERAND_TYPE_IMM32_32S_DISP32
},
7749 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7750 _dummy_first_bfd_reloc_code_real
},
7751 OPERAND_TYPE_NONE
},
7752 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7753 BFD_RELOC_X86_64_TLSLD
},
7754 OPERAND_TYPE_IMM32_32S_DISP32
},
7755 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7756 BFD_RELOC_X86_64_GOTTPOFF
},
7757 OPERAND_TYPE_IMM32_32S_DISP32
},
7758 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7759 BFD_RELOC_X86_64_TPOFF32
},
7760 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7761 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7762 _dummy_first_bfd_reloc_code_real
},
7763 OPERAND_TYPE_NONE
},
7764 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7765 BFD_RELOC_X86_64_DTPOFF32
},
7766 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7767 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7768 _dummy_first_bfd_reloc_code_real
},
7769 OPERAND_TYPE_NONE
},
7770 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7771 _dummy_first_bfd_reloc_code_real
},
7772 OPERAND_TYPE_NONE
},
7773 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7774 BFD_RELOC_X86_64_GOT32
},
7775 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7776 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7777 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7778 OPERAND_TYPE_IMM32_32S_DISP32
},
7779 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7780 BFD_RELOC_X86_64_TLSDESC_CALL
},
7781 OPERAND_TYPE_IMM32_32S_DISP32
},
7786 #if defined (OBJ_MAYBE_ELF)
7791 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7792 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7795 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7797 int len
= gotrel
[j
].len
;
7798 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7800 if (gotrel
[j
].rel
[object_64bit
] != 0)
7803 char *tmpbuf
, *past_reloc
;
7805 *rel
= gotrel
[j
].rel
[object_64bit
];
7809 if (flag_code
!= CODE_64BIT
)
7811 types
->bitfield
.imm32
= 1;
7812 types
->bitfield
.disp32
= 1;
7815 *types
= gotrel
[j
].types64
;
7818 if (j
!= 0 && GOT_symbol
== NULL
)
7819 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7821 /* The length of the first part of our input line. */
7822 first
= cp
- input_line_pointer
;
7824 /* The second part goes from after the reloc token until
7825 (and including) an end_of_line char or comma. */
7826 past_reloc
= cp
+ 1 + len
;
7828 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7830 second
= cp
+ 1 - past_reloc
;
7832 /* Allocate and copy string. The trailing NUL shouldn't
7833 be necessary, but be safe. */
7834 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7835 memcpy (tmpbuf
, input_line_pointer
, first
);
7836 if (second
!= 0 && *past_reloc
!= ' ')
7837 /* Replace the relocation token with ' ', so that
7838 errors like foo@GOTOFF1 will be detected. */
7839 tmpbuf
[first
++] = ' ';
7841 /* Increment length by 1 if the relocation token is
7846 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7847 tmpbuf
[first
+ second
] = '\0';
7851 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7852 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7857 /* Might be a symbol version string. Don't as_bad here. */
7866 /* Parse operands of the form
7867 <symbol>@SECREL32+<nnn>
7869 If we find one, set up the correct relocation in RELOC and copy the
7870 input string, minus the `@SECREL32' into a malloc'd buffer for
7871 parsing by the calling routine. Return this buffer, and if ADJUST
7872 is non-null set it to the length of the string we removed from the
7873 input line. Otherwise return NULL.
7875 This function is copied from the ELF version above adjusted for PE targets. */
7878 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7879 int *adjust ATTRIBUTE_UNUSED
,
7880 i386_operand_type
*types
)
7886 const enum bfd_reloc_code_real rel
[2];
7887 const i386_operand_type types64
;
7891 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7892 BFD_RELOC_32_SECREL
},
7893 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7899 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7900 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7903 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7905 int len
= gotrel
[j
].len
;
7907 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7909 if (gotrel
[j
].rel
[object_64bit
] != 0)
7912 char *tmpbuf
, *past_reloc
;
7914 *rel
= gotrel
[j
].rel
[object_64bit
];
7920 if (flag_code
!= CODE_64BIT
)
7922 types
->bitfield
.imm32
= 1;
7923 types
->bitfield
.disp32
= 1;
7926 *types
= gotrel
[j
].types64
;
7929 /* The length of the first part of our input line. */
7930 first
= cp
- input_line_pointer
;
7932 /* The second part goes from after the reloc token until
7933 (and including) an end_of_line char or comma. */
7934 past_reloc
= cp
+ 1 + len
;
7936 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7938 second
= cp
+ 1 - past_reloc
;
7940 /* Allocate and copy string. The trailing NUL shouldn't
7941 be necessary, but be safe. */
7942 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7943 memcpy (tmpbuf
, input_line_pointer
, first
);
7944 if (second
!= 0 && *past_reloc
!= ' ')
7945 /* Replace the relocation token with ' ', so that
7946 errors like foo@SECLREL321 will be detected. */
7947 tmpbuf
[first
++] = ' ';
7948 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7949 tmpbuf
[first
+ second
] = '\0';
7953 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7954 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7959 /* Might be a symbol version string. Don't as_bad here. */
7965 bfd_reloc_code_real_type
7966 x86_cons (expressionS
*exp
, int size
)
7968 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7970 intel_syntax
= -intel_syntax
;
7973 if (size
== 4 || (object_64bit
&& size
== 8))
7975 /* Handle @GOTOFF and the like in an expression. */
7977 char *gotfree_input_line
;
7980 save
= input_line_pointer
;
7981 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7982 if (gotfree_input_line
)
7983 input_line_pointer
= gotfree_input_line
;
7987 if (gotfree_input_line
)
7989 /* expression () has merrily parsed up to the end of line,
7990 or a comma - in the wrong buffer. Transfer how far
7991 input_line_pointer has moved to the right buffer. */
7992 input_line_pointer
= (save
7993 + (input_line_pointer
- gotfree_input_line
)
7995 free (gotfree_input_line
);
7996 if (exp
->X_op
== O_constant
7997 || exp
->X_op
== O_absent
7998 || exp
->X_op
== O_illegal
7999 || exp
->X_op
== O_register
8000 || exp
->X_op
== O_big
)
8002 char c
= *input_line_pointer
;
8003 *input_line_pointer
= 0;
8004 as_bad (_("missing or invalid expression `%s'"), save
);
8005 *input_line_pointer
= c
;
8012 intel_syntax
= -intel_syntax
;
8015 i386_intel_simplify (exp
);
8021 signed_cons (int size
)
8023 if (flag_code
== CODE_64BIT
)
8031 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8038 if (exp
.X_op
== O_symbol
)
8039 exp
.X_op
= O_secrel
;
8041 emit_expr (&exp
, 4);
8043 while (*input_line_pointer
++ == ',');
8045 input_line_pointer
--;
8046 demand_empty_rest_of_line ();
8050 /* Handle Vector operations. */
8053 check_VecOperations (char *op_string
, char *op_end
)
8055 const reg_entry
*mask
;
8060 && (op_end
== NULL
|| op_string
< op_end
))
8063 if (*op_string
== '{')
8067 /* Check broadcasts. */
8068 if (strncmp (op_string
, "1to", 3) == 0)
8073 goto duplicated_vec_op
;
8076 if (*op_string
== '8')
8077 bcst_type
= BROADCAST_1TO8
;
8078 else if (*op_string
== '4')
8079 bcst_type
= BROADCAST_1TO4
;
8080 else if (*op_string
== '2')
8081 bcst_type
= BROADCAST_1TO2
;
8082 else if (*op_string
== '1'
8083 && *(op_string
+1) == '6')
8085 bcst_type
= BROADCAST_1TO16
;
8090 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8095 broadcast_op
.type
= bcst_type
;
8096 broadcast_op
.operand
= this_operand
;
8097 i
.broadcast
= &broadcast_op
;
8099 /* Check masking operation. */
8100 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8102 /* k0 can't be used for write mask. */
8103 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8105 as_bad (_("`%s%s' can't be used for write mask"),
8106 register_prefix
, mask
->reg_name
);
8112 mask_op
.mask
= mask
;
8113 mask_op
.zeroing
= 0;
8114 mask_op
.operand
= this_operand
;
8120 goto duplicated_vec_op
;
8122 i
.mask
->mask
= mask
;
8124 /* Only "{z}" is allowed here. No need to check
8125 zeroing mask explicitly. */
8126 if (i
.mask
->operand
!= this_operand
)
8128 as_bad (_("invalid write mask `%s'"), saved
);
8135 /* Check zeroing-flag for masking operation. */
8136 else if (*op_string
== 'z')
8140 mask_op
.mask
= NULL
;
8141 mask_op
.zeroing
= 1;
8142 mask_op
.operand
= this_operand
;
8147 if (i
.mask
->zeroing
)
8150 as_bad (_("duplicated `%s'"), saved
);
8154 i
.mask
->zeroing
= 1;
8156 /* Only "{%k}" is allowed here. No need to check mask
8157 register explicitly. */
8158 if (i
.mask
->operand
!= this_operand
)
8160 as_bad (_("invalid zeroing-masking `%s'"),
8169 goto unknown_vec_op
;
8171 if (*op_string
!= '}')
8173 as_bad (_("missing `}' in `%s'"), saved
);
8180 /* We don't know this one. */
8181 as_bad (_("unknown vector operation: `%s'"), saved
);
8185 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8187 as_bad (_("zeroing-masking only allowed with write mask"));
8195 i386_immediate (char *imm_start
)
8197 char *save_input_line_pointer
;
8198 char *gotfree_input_line
;
8201 i386_operand_type types
;
8203 operand_type_set (&types
, ~0);
8205 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8207 as_bad (_("at most %d immediate operands are allowed"),
8208 MAX_IMMEDIATE_OPERANDS
);
8212 exp
= &im_expressions
[i
.imm_operands
++];
8213 i
.op
[this_operand
].imms
= exp
;
8215 if (is_space_char (*imm_start
))
8218 save_input_line_pointer
= input_line_pointer
;
8219 input_line_pointer
= imm_start
;
8221 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8222 if (gotfree_input_line
)
8223 input_line_pointer
= gotfree_input_line
;
8225 exp_seg
= expression (exp
);
8229 /* Handle vector operations. */
8230 if (*input_line_pointer
== '{')
8232 input_line_pointer
= check_VecOperations (input_line_pointer
,
8234 if (input_line_pointer
== NULL
)
8238 if (*input_line_pointer
)
8239 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8241 input_line_pointer
= save_input_line_pointer
;
8242 if (gotfree_input_line
)
8244 free (gotfree_input_line
);
8246 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8247 exp
->X_op
= O_illegal
;
8250 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8254 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8255 i386_operand_type types
, const char *imm_start
)
8257 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8260 as_bad (_("missing or invalid immediate expression `%s'"),
8264 else if (exp
->X_op
== O_constant
)
8266 /* Size it properly later. */
8267 i
.types
[this_operand
].bitfield
.imm64
= 1;
8268 /* If not 64bit, sign extend val. */
8269 if (flag_code
!= CODE_64BIT
8270 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8272 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8274 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8275 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8276 && exp_seg
!= absolute_section
8277 && exp_seg
!= text_section
8278 && exp_seg
!= data_section
8279 && exp_seg
!= bss_section
8280 && exp_seg
!= undefined_section
8281 && !bfd_is_com_section (exp_seg
))
8283 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8287 else if (!intel_syntax
&& exp_seg
== reg_section
)
8290 as_bad (_("illegal immediate register operand %s"), imm_start
);
8295 /* This is an address. The size of the address will be
8296 determined later, depending on destination register,
8297 suffix, or the default for the section. */
8298 i
.types
[this_operand
].bitfield
.imm8
= 1;
8299 i
.types
[this_operand
].bitfield
.imm16
= 1;
8300 i
.types
[this_operand
].bitfield
.imm32
= 1;
8301 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8302 i
.types
[this_operand
].bitfield
.imm64
= 1;
8303 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8311 i386_scale (char *scale
)
8314 char *save
= input_line_pointer
;
8316 input_line_pointer
= scale
;
8317 val
= get_absolute_expression ();
8322 i
.log2_scale_factor
= 0;
8325 i
.log2_scale_factor
= 1;
8328 i
.log2_scale_factor
= 2;
8331 i
.log2_scale_factor
= 3;
8335 char sep
= *input_line_pointer
;
8337 *input_line_pointer
= '\0';
8338 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8340 *input_line_pointer
= sep
;
8341 input_line_pointer
= save
;
8345 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8347 as_warn (_("scale factor of %d without an index register"),
8348 1 << i
.log2_scale_factor
);
8349 i
.log2_scale_factor
= 0;
8351 scale
= input_line_pointer
;
8352 input_line_pointer
= save
;
8357 i386_displacement (char *disp_start
, char *disp_end
)
8361 char *save_input_line_pointer
;
8362 char *gotfree_input_line
;
8364 i386_operand_type bigdisp
, types
= anydisp
;
8367 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8369 as_bad (_("at most %d displacement operands are allowed"),
8370 MAX_MEMORY_OPERANDS
);
8374 operand_type_set (&bigdisp
, 0);
8375 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8376 || (!current_templates
->start
->opcode_modifier
.jump
8377 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8379 bigdisp
.bitfield
.disp32
= 1;
8380 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8381 if (flag_code
== CODE_64BIT
)
8385 bigdisp
.bitfield
.disp32s
= 1;
8386 bigdisp
.bitfield
.disp64
= 1;
8389 else if ((flag_code
== CODE_16BIT
) ^ override
)
8391 bigdisp
.bitfield
.disp32
= 0;
8392 bigdisp
.bitfield
.disp16
= 1;
8397 /* For PC-relative branches, the width of the displacement
8398 is dependent upon data size, not address size. */
8399 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8400 if (flag_code
== CODE_64BIT
)
8402 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8403 bigdisp
.bitfield
.disp16
= 1;
8406 bigdisp
.bitfield
.disp32
= 1;
8407 bigdisp
.bitfield
.disp32s
= 1;
8413 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8415 : LONG_MNEM_SUFFIX
));
8416 bigdisp
.bitfield
.disp32
= 1;
8417 if ((flag_code
== CODE_16BIT
) ^ override
)
8419 bigdisp
.bitfield
.disp32
= 0;
8420 bigdisp
.bitfield
.disp16
= 1;
8424 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8427 exp
= &disp_expressions
[i
.disp_operands
];
8428 i
.op
[this_operand
].disps
= exp
;
8430 save_input_line_pointer
= input_line_pointer
;
8431 input_line_pointer
= disp_start
;
8432 END_STRING_AND_SAVE (disp_end
);
8434 #ifndef GCC_ASM_O_HACK
8435 #define GCC_ASM_O_HACK 0
8438 END_STRING_AND_SAVE (disp_end
+ 1);
8439 if (i
.types
[this_operand
].bitfield
.baseIndex
8440 && displacement_string_end
[-1] == '+')
8442 /* This hack is to avoid a warning when using the "o"
8443 constraint within gcc asm statements.
8446 #define _set_tssldt_desc(n,addr,limit,type) \
8447 __asm__ __volatile__ ( \
8449 "movw %w1,2+%0\n\t" \
8451 "movb %b1,4+%0\n\t" \
8452 "movb %4,5+%0\n\t" \
8453 "movb $0,6+%0\n\t" \
8454 "movb %h1,7+%0\n\t" \
8456 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8458 This works great except that the output assembler ends
8459 up looking a bit weird if it turns out that there is
8460 no offset. You end up producing code that looks like:
8473 So here we provide the missing zero. */
8475 *displacement_string_end
= '0';
8478 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8479 if (gotfree_input_line
)
8480 input_line_pointer
= gotfree_input_line
;
8482 exp_seg
= expression (exp
);
8485 if (*input_line_pointer
)
8486 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8488 RESTORE_END_STRING (disp_end
+ 1);
8490 input_line_pointer
= save_input_line_pointer
;
8491 if (gotfree_input_line
)
8493 free (gotfree_input_line
);
8495 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8496 exp
->X_op
= O_illegal
;
8499 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8501 RESTORE_END_STRING (disp_end
);
8507 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8508 i386_operand_type types
, const char *disp_start
)
8510 i386_operand_type bigdisp
;
8513 /* We do this to make sure that the section symbol is in
8514 the symbol table. We will ultimately change the relocation
8515 to be relative to the beginning of the section. */
8516 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8517 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8518 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8520 if (exp
->X_op
!= O_symbol
)
8523 if (S_IS_LOCAL (exp
->X_add_symbol
)
8524 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8525 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8526 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8527 exp
->X_op
= O_subtract
;
8528 exp
->X_op_symbol
= GOT_symbol
;
8529 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8530 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8531 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8532 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8534 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8537 else if (exp
->X_op
== O_absent
8538 || exp
->X_op
== O_illegal
8539 || exp
->X_op
== O_big
)
8542 as_bad (_("missing or invalid displacement expression `%s'"),
8547 else if (flag_code
== CODE_64BIT
8548 && !i
.prefix
[ADDR_PREFIX
]
8549 && exp
->X_op
== O_constant
)
8551 /* Since displacement is signed extended to 64bit, don't allow
8552 disp32 and turn off disp32s if they are out of range. */
8553 i
.types
[this_operand
].bitfield
.disp32
= 0;
8554 if (!fits_in_signed_long (exp
->X_add_number
))
8556 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8557 if (i
.types
[this_operand
].bitfield
.baseindex
)
8559 as_bad (_("0x%lx out range of signed 32bit displacement"),
8560 (long) exp
->X_add_number
);
8566 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8567 else if (exp
->X_op
!= O_constant
8568 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8569 && exp_seg
!= absolute_section
8570 && exp_seg
!= text_section
8571 && exp_seg
!= data_section
8572 && exp_seg
!= bss_section
8573 && exp_seg
!= undefined_section
8574 && !bfd_is_com_section (exp_seg
))
8576 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8581 /* Check if this is a displacement only operand. */
8582 bigdisp
= i
.types
[this_operand
];
8583 bigdisp
.bitfield
.disp8
= 0;
8584 bigdisp
.bitfield
.disp16
= 0;
8585 bigdisp
.bitfield
.disp32
= 0;
8586 bigdisp
.bitfield
.disp32s
= 0;
8587 bigdisp
.bitfield
.disp64
= 0;
8588 if (operand_type_all_zero (&bigdisp
))
8589 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8595 /* Return the active addressing mode, taking address override and
8596 registers forming the address into consideration. Update the
8597 address override prefix if necessary. */
8599 static enum flag_code
8600 i386_addressing_mode (void)
8602 enum flag_code addr_mode
;
8604 if (i
.prefix
[ADDR_PREFIX
])
8605 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8608 addr_mode
= flag_code
;
8610 #if INFER_ADDR_PREFIX
8611 if (i
.mem_operands
== 0)
8613 /* Infer address prefix from the first memory operand. */
8614 const reg_entry
*addr_reg
= i
.base_reg
;
8616 if (addr_reg
== NULL
)
8617 addr_reg
= i
.index_reg
;
8621 if (addr_reg
->reg_num
== RegEip
8622 || addr_reg
->reg_num
== RegEiz
8623 || addr_reg
->reg_type
.bitfield
.reg32
)
8624 addr_mode
= CODE_32BIT
;
8625 else if (flag_code
!= CODE_64BIT
8626 && addr_reg
->reg_type
.bitfield
.reg16
)
8627 addr_mode
= CODE_16BIT
;
8629 if (addr_mode
!= flag_code
)
8631 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8633 /* Change the size of any displacement too. At most one
8634 of Disp16 or Disp32 is set.
8635 FIXME. There doesn't seem to be any real need for
8636 separate Disp16 and Disp32 flags. The same goes for
8637 Imm16 and Imm32. Removing them would probably clean
8638 up the code quite a lot. */
8639 if (flag_code
!= CODE_64BIT
8640 && (i
.types
[this_operand
].bitfield
.disp16
8641 || i
.types
[this_operand
].bitfield
.disp32
))
8642 i
.types
[this_operand
]
8643 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8653 /* Make sure the memory operand we've been dealt is valid.
8654 Return 1 on success, 0 on a failure. */
8657 i386_index_check (const char *operand_string
)
8659 const char *kind
= "base/index";
8660 enum flag_code addr_mode
= i386_addressing_mode ();
8662 if (current_templates
->start
->opcode_modifier
.isstring
8663 && !current_templates
->start
->opcode_modifier
.immext
8664 && (current_templates
->end
[-1].opcode_modifier
.isstring
8667 /* Memory operands of string insns are special in that they only allow
8668 a single register (rDI, rSI, or rBX) as their memory address. */
8669 const reg_entry
*expected_reg
;
8670 static const char *di_si
[][2] =
8676 static const char *bx
[] = { "ebx", "bx", "rbx" };
8678 kind
= "string address";
8680 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8682 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8684 if (!type
.bitfield
.baseindex
8685 || ((!i
.mem_operands
!= !intel_syntax
)
8686 && current_templates
->end
[-1].operand_types
[1]
8687 .bitfield
.baseindex
))
8688 type
= current_templates
->end
[-1].operand_types
[1];
8689 expected_reg
= hash_find (reg_hash
,
8690 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8694 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8696 if (i
.base_reg
!= expected_reg
8698 || operand_type_check (i
.types
[this_operand
], disp
))
8700 /* The second memory operand must have the same size as
8704 && !((addr_mode
== CODE_64BIT
8705 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8706 || (addr_mode
== CODE_32BIT
8707 ? i
.base_reg
->reg_type
.bitfield
.reg32
8708 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8711 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8713 intel_syntax
? '[' : '(',
8715 expected_reg
->reg_name
,
8716 intel_syntax
? ']' : ')');
8723 as_bad (_("`%s' is not a valid %s expression"),
8724 operand_string
, kind
);
8729 if (addr_mode
!= CODE_16BIT
)
8731 /* 32-bit/64-bit checks. */
8733 && (addr_mode
== CODE_64BIT
8734 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8735 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8737 || (i
.base_reg
->reg_num
8738 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8740 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8741 && !i
.index_reg
->reg_type
.bitfield
.regymm
8742 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8743 && ((addr_mode
== CODE_64BIT
8744 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8745 || i
.index_reg
->reg_num
== RegRiz
)
8746 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8747 || i
.index_reg
->reg_num
== RegEiz
))
8748 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8751 /* bndmk, bndldx, and bndstx have special restrictions. */
8752 if (current_templates
->start
->base_opcode
== 0xf30f1b
8753 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8755 /* They cannot use RIP-relative addressing. */
8756 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8758 as_bad (_("`%s' cannot be used here"), operand_string
);
8762 /* bndldx and bndstx ignore their scale factor. */
8763 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8764 && i
.log2_scale_factor
)
8765 as_warn (_("register scaling is being ignored here"));
8770 /* 16-bit checks. */
8772 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8773 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8775 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8776 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8778 && i
.base_reg
->reg_num
< 6
8779 && i
.index_reg
->reg_num
>= 6
8780 && i
.log2_scale_factor
== 0))))
8787 /* Handle vector immediates. */
8790 RC_SAE_immediate (const char *imm_start
)
8792 unsigned int match_found
, j
;
8793 const char *pstr
= imm_start
;
8801 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8803 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8807 rc_op
.type
= RC_NamesTable
[j
].type
;
8808 rc_op
.operand
= this_operand
;
8809 i
.rounding
= &rc_op
;
8813 as_bad (_("duplicated `%s'"), imm_start
);
8816 pstr
+= RC_NamesTable
[j
].len
;
8826 as_bad (_("Missing '}': '%s'"), imm_start
);
8829 /* RC/SAE immediate string should contain nothing more. */;
8832 as_bad (_("Junk after '}': '%s'"), imm_start
);
8836 exp
= &im_expressions
[i
.imm_operands
++];
8837 i
.op
[this_operand
].imms
= exp
;
8839 exp
->X_op
= O_constant
;
8840 exp
->X_add_number
= 0;
8841 exp
->X_add_symbol
= (symbolS
*) 0;
8842 exp
->X_op_symbol
= (symbolS
*) 0;
8844 i
.types
[this_operand
].bitfield
.imm8
= 1;
8848 /* Only string instructions can have a second memory operand, so
8849 reduce current_templates to just those if it contains any. */
8851 maybe_adjust_templates (void)
8853 const insn_template
*t
;
8855 gas_assert (i
.mem_operands
== 1);
8857 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8858 if (t
->opcode_modifier
.isstring
)
8861 if (t
< current_templates
->end
)
8863 static templates aux_templates
;
8864 bfd_boolean recheck
;
8866 aux_templates
.start
= t
;
8867 for (; t
< current_templates
->end
; ++t
)
8868 if (!t
->opcode_modifier
.isstring
)
8870 aux_templates
.end
= t
;
8872 /* Determine whether to re-check the first memory operand. */
8873 recheck
= (aux_templates
.start
!= current_templates
->start
8874 || t
!= current_templates
->end
);
8876 current_templates
= &aux_templates
;
8881 if (i
.memop1_string
!= NULL
8882 && i386_index_check (i
.memop1_string
) == 0)
8891 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8895 i386_att_operand (char *operand_string
)
8899 char *op_string
= operand_string
;
8901 if (is_space_char (*op_string
))
8904 /* We check for an absolute prefix (differentiating,
8905 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8906 if (*op_string
== ABSOLUTE_PREFIX
)
8909 if (is_space_char (*op_string
))
8911 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8914 /* Check if operand is a register. */
8915 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8917 i386_operand_type temp
;
8919 /* Check for a segment override by searching for ':' after a
8920 segment register. */
8922 if (is_space_char (*op_string
))
8924 if (*op_string
== ':'
8925 && (r
->reg_type
.bitfield
.sreg2
8926 || r
->reg_type
.bitfield
.sreg3
))
8931 i
.seg
[i
.mem_operands
] = &es
;
8934 i
.seg
[i
.mem_operands
] = &cs
;
8937 i
.seg
[i
.mem_operands
] = &ss
;
8940 i
.seg
[i
.mem_operands
] = &ds
;
8943 i
.seg
[i
.mem_operands
] = &fs
;
8946 i
.seg
[i
.mem_operands
] = &gs
;
8950 /* Skip the ':' and whitespace. */
8952 if (is_space_char (*op_string
))
8955 if (!is_digit_char (*op_string
)
8956 && !is_identifier_char (*op_string
)
8957 && *op_string
!= '('
8958 && *op_string
!= ABSOLUTE_PREFIX
)
8960 as_bad (_("bad memory operand `%s'"), op_string
);
8963 /* Handle case of %es:*foo. */
8964 if (*op_string
== ABSOLUTE_PREFIX
)
8967 if (is_space_char (*op_string
))
8969 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8971 goto do_memory_reference
;
8974 /* Handle vector operations. */
8975 if (*op_string
== '{')
8977 op_string
= check_VecOperations (op_string
, NULL
);
8978 if (op_string
== NULL
)
8984 as_bad (_("junk `%s' after register"), op_string
);
8988 temp
.bitfield
.baseindex
= 0;
8989 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8991 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8992 i
.op
[this_operand
].regs
= r
;
8995 else if (*op_string
== REGISTER_PREFIX
)
8997 as_bad (_("bad register name `%s'"), op_string
);
9000 else if (*op_string
== IMMEDIATE_PREFIX
)
9003 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9005 as_bad (_("immediate operand illegal with absolute jump"));
9008 if (!i386_immediate (op_string
))
9011 else if (RC_SAE_immediate (operand_string
))
9013 /* If it is a RC or SAE immediate, do nothing. */
9016 else if (is_digit_char (*op_string
)
9017 || is_identifier_char (*op_string
)
9018 || *op_string
== '"'
9019 || *op_string
== '(')
9021 /* This is a memory reference of some sort. */
9024 /* Start and end of displacement string expression (if found). */
9025 char *displacement_string_start
;
9026 char *displacement_string_end
;
9029 do_memory_reference
:
9030 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9032 if ((i
.mem_operands
== 1
9033 && !current_templates
->start
->opcode_modifier
.isstring
)
9034 || i
.mem_operands
== 2)
9036 as_bad (_("too many memory references for `%s'"),
9037 current_templates
->start
->name
);
9041 /* Check for base index form. We detect the base index form by
9042 looking for an ')' at the end of the operand, searching
9043 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9045 base_string
= op_string
+ strlen (op_string
);
9047 /* Handle vector operations. */
9048 vop_start
= strchr (op_string
, '{');
9049 if (vop_start
&& vop_start
< base_string
)
9051 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9053 base_string
= vop_start
;
9057 if (is_space_char (*base_string
))
9060 /* If we only have a displacement, set-up for it to be parsed later. */
9061 displacement_string_start
= op_string
;
9062 displacement_string_end
= base_string
+ 1;
9064 if (*base_string
== ')')
9067 unsigned int parens_balanced
= 1;
9068 /* We've already checked that the number of left & right ()'s are
9069 equal, so this loop will not be infinite. */
9073 if (*base_string
== ')')
9075 if (*base_string
== '(')
9078 while (parens_balanced
);
9080 temp_string
= base_string
;
9082 /* Skip past '(' and whitespace. */
9084 if (is_space_char (*base_string
))
9087 if (*base_string
== ','
9088 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9091 displacement_string_end
= temp_string
;
9093 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9097 base_string
= end_op
;
9098 if (is_space_char (*base_string
))
9102 /* There may be an index reg or scale factor here. */
9103 if (*base_string
== ',')
9106 if (is_space_char (*base_string
))
9109 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9112 base_string
= end_op
;
9113 if (is_space_char (*base_string
))
9115 if (*base_string
== ',')
9118 if (is_space_char (*base_string
))
9121 else if (*base_string
!= ')')
9123 as_bad (_("expecting `,' or `)' "
9124 "after index register in `%s'"),
9129 else if (*base_string
== REGISTER_PREFIX
)
9131 end_op
= strchr (base_string
, ',');
9134 as_bad (_("bad register name `%s'"), base_string
);
9138 /* Check for scale factor. */
9139 if (*base_string
!= ')')
9141 char *end_scale
= i386_scale (base_string
);
9146 base_string
= end_scale
;
9147 if (is_space_char (*base_string
))
9149 if (*base_string
!= ')')
9151 as_bad (_("expecting `)' "
9152 "after scale factor in `%s'"),
9157 else if (!i
.index_reg
)
9159 as_bad (_("expecting index register or scale factor "
9160 "after `,'; got '%c'"),
9165 else if (*base_string
!= ')')
9167 as_bad (_("expecting `,' or `)' "
9168 "after base register in `%s'"),
9173 else if (*base_string
== REGISTER_PREFIX
)
9175 end_op
= strchr (base_string
, ',');
9178 as_bad (_("bad register name `%s'"), base_string
);
9183 /* If there's an expression beginning the operand, parse it,
9184 assuming displacement_string_start and
9185 displacement_string_end are meaningful. */
9186 if (displacement_string_start
!= displacement_string_end
)
9188 if (!i386_displacement (displacement_string_start
,
9189 displacement_string_end
))
9193 /* Special case for (%dx) while doing input/output op. */
9195 && operand_type_equal (&i
.base_reg
->reg_type
,
9196 ®16_inoutportreg
)
9198 && i
.log2_scale_factor
== 0
9199 && i
.seg
[i
.mem_operands
] == 0
9200 && !operand_type_check (i
.types
[this_operand
], disp
))
9202 i
.types
[this_operand
] = inoutportreg
;
9206 if (i386_index_check (operand_string
) == 0)
9208 i
.types
[this_operand
].bitfield
.mem
= 1;
9209 if (i
.mem_operands
== 0)
9210 i
.memop1_string
= xstrdup (operand_string
);
9215 /* It's not a memory operand; argh! */
9216 as_bad (_("invalid char %s beginning operand %d `%s'"),
9217 output_invalid (*op_string
),
9222 return 1; /* Normal return. */
9225 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9226 that an rs_machine_dependent frag may reach. */
9229 i386_frag_max_var (fragS
*frag
)
9231 /* The only relaxable frags are for jumps.
9232 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9233 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9234 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9239 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9241 /* STT_GNU_IFUNC symbol must go through PLT. */
9242 if ((symbol_get_bfdsym (fr_symbol
)->flags
9243 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9246 if (!S_IS_EXTERNAL (fr_symbol
))
9247 /* Symbol may be weak or local. */
9248 return !S_IS_WEAK (fr_symbol
);
9250 /* Global symbols with non-default visibility can't be preempted. */
9251 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9254 if (fr_var
!= NO_RELOC
)
9255 switch ((enum bfd_reloc_code_real
) fr_var
)
9257 case BFD_RELOC_386_PLT32
:
9258 case BFD_RELOC_X86_64_PLT32
:
9259 /* Symbol with PLT relocation may be preempted. */
9265 /* Global symbols with default visibility in a shared library may be
9266 preempted by another definition. */
9271 /* md_estimate_size_before_relax()
9273 Called just before relax() for rs_machine_dependent frags. The x86
9274 assembler uses these frags to handle variable size jump
9277 Any symbol that is now undefined will not become defined.
9278 Return the correct fr_subtype in the frag.
9279 Return the initial "guess for variable size of frag" to caller.
9280 The guess is actually the growth beyond the fixed part. Whatever
9281 we do to grow the fixed or variable part contributes to our
9285 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9287 /* We've already got fragP->fr_subtype right; all we have to do is
9288 check for un-relaxable symbols. On an ELF system, we can't relax
9289 an externally visible symbol, because it may be overridden by a
9291 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9292 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9294 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9297 #if defined (OBJ_COFF) && defined (TE_PE)
9298 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9299 && S_IS_WEAK (fragP
->fr_symbol
))
9303 /* Symbol is undefined in this segment, or we need to keep a
9304 reloc so that weak symbols can be overridden. */
9305 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9306 enum bfd_reloc_code_real reloc_type
;
9307 unsigned char *opcode
;
9310 if (fragP
->fr_var
!= NO_RELOC
)
9311 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9313 reloc_type
= BFD_RELOC_16_PCREL
;
9315 reloc_type
= BFD_RELOC_32_PCREL
;
9317 old_fr_fix
= fragP
->fr_fix
;
9318 opcode
= (unsigned char *) fragP
->fr_opcode
;
9320 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9323 /* Make jmp (0xeb) a (d)word displacement jump. */
9325 fragP
->fr_fix
+= size
;
9326 fix_new (fragP
, old_fr_fix
, size
,
9328 fragP
->fr_offset
, 1,
9334 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9336 /* Negate the condition, and branch past an
9337 unconditional jump. */
9340 /* Insert an unconditional jump. */
9342 /* We added two extra opcode bytes, and have a two byte
9344 fragP
->fr_fix
+= 2 + 2;
9345 fix_new (fragP
, old_fr_fix
+ 2, 2,
9347 fragP
->fr_offset
, 1,
9354 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9359 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9361 fragP
->fr_offset
, 1,
9363 fixP
->fx_signed
= 1;
9367 /* This changes the byte-displacement jump 0x7N
9368 to the (d)word-displacement jump 0x0f,0x8N. */
9369 opcode
[1] = opcode
[0] + 0x10;
9370 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9371 /* We've added an opcode byte. */
9372 fragP
->fr_fix
+= 1 + size
;
9373 fix_new (fragP
, old_fr_fix
+ 1, size
,
9375 fragP
->fr_offset
, 1,
9380 BAD_CASE (fragP
->fr_subtype
);
9384 return fragP
->fr_fix
- old_fr_fix
;
9387 /* Guess size depending on current relax state. Initially the relax
9388 state will correspond to a short jump and we return 1, because
9389 the variable part of the frag (the branch offset) is one byte
9390 long. However, we can relax a section more than once and in that
9391 case we must either set fr_subtype back to the unrelaxed state,
9392 or return the value for the appropriate branch. */
9393 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9396 /* Called after relax() is finished.
9398 In: Address of frag.
9399 fr_type == rs_machine_dependent.
9400 fr_subtype is what the address relaxed to.
9402 Out: Any fixSs and constants are set up.
9403 Caller will turn frag into a ".space 0". */
9406 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9409 unsigned char *opcode
;
9410 unsigned char *where_to_put_displacement
= NULL
;
9411 offsetT target_address
;
9412 offsetT opcode_address
;
9413 unsigned int extension
= 0;
9414 offsetT displacement_from_opcode_start
;
9416 opcode
= (unsigned char *) fragP
->fr_opcode
;
9418 /* Address we want to reach in file space. */
9419 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9421 /* Address opcode resides at in file space. */
9422 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9424 /* Displacement from opcode start to fill into instruction. */
9425 displacement_from_opcode_start
= target_address
- opcode_address
;
9427 if ((fragP
->fr_subtype
& BIG
) == 0)
9429 /* Don't have to change opcode. */
9430 extension
= 1; /* 1 opcode + 1 displacement */
9431 where_to_put_displacement
= &opcode
[1];
9435 if (no_cond_jump_promotion
9436 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9437 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9438 _("long jump required"));
9440 switch (fragP
->fr_subtype
)
9442 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9443 extension
= 4; /* 1 opcode + 4 displacement */
9445 where_to_put_displacement
= &opcode
[1];
9448 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9449 extension
= 2; /* 1 opcode + 2 displacement */
9451 where_to_put_displacement
= &opcode
[1];
9454 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9455 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9456 extension
= 5; /* 2 opcode + 4 displacement */
9457 opcode
[1] = opcode
[0] + 0x10;
9458 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9459 where_to_put_displacement
= &opcode
[2];
9462 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9463 extension
= 3; /* 2 opcode + 2 displacement */
9464 opcode
[1] = opcode
[0] + 0x10;
9465 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9466 where_to_put_displacement
= &opcode
[2];
9469 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9474 where_to_put_displacement
= &opcode
[3];
9478 BAD_CASE (fragP
->fr_subtype
);
9483 /* If size if less then four we are sure that the operand fits,
9484 but if it's 4, then it could be that the displacement is larger
9486 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9488 && ((addressT
) (displacement_from_opcode_start
- extension
9489 + ((addressT
) 1 << 31))
9490 > (((addressT
) 2 << 31) - 1)))
9492 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9493 _("jump target out of range"));
9494 /* Make us emit 0. */
9495 displacement_from_opcode_start
= extension
;
9497 /* Now put displacement after opcode. */
9498 md_number_to_chars ((char *) where_to_put_displacement
,
9499 (valueT
) (displacement_from_opcode_start
- extension
),
9500 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9501 fragP
->fr_fix
+= extension
;
9504 /* Apply a fixup (fixP) to segment data, once it has been determined
9505 by our caller that we have all the info we need to fix it up.
9507 Parameter valP is the pointer to the value of the bits.
9509 On the 386, immediates, displacements, and data pointers are all in
9510 the same (little-endian) format, so we don't need to care about which
9514 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9516 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9517 valueT value
= *valP
;
9519 #if !defined (TE_Mach)
9522 switch (fixP
->fx_r_type
)
9528 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9531 case BFD_RELOC_X86_64_32S
:
9532 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9535 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9538 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9543 if (fixP
->fx_addsy
!= NULL
9544 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9545 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9546 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9547 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9548 && !use_rela_relocations
)
9550 /* This is a hack. There should be a better way to handle this.
9551 This covers for the fact that bfd_install_relocation will
9552 subtract the current location (for partial_inplace, PC relative
9553 relocations); see more below. */
9557 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9560 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9565 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9568 || (symbol_section_p (fixP
->fx_addsy
)
9569 && sym_seg
!= absolute_section
))
9570 && !generic_force_reloc (fixP
))
9572 /* Yes, we add the values in twice. This is because
9573 bfd_install_relocation subtracts them out again. I think
9574 bfd_install_relocation is broken, but I don't dare change
9576 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9580 #if defined (OBJ_COFF) && defined (TE_PE)
9581 /* For some reason, the PE format does not store a
9582 section address offset for a PC relative symbol. */
9583 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9584 || S_IS_WEAK (fixP
->fx_addsy
))
9585 value
+= md_pcrel_from (fixP
);
9588 #if defined (OBJ_COFF) && defined (TE_PE)
9589 if (fixP
->fx_addsy
!= NULL
9590 && S_IS_WEAK (fixP
->fx_addsy
)
9591 /* PR 16858: Do not modify weak function references. */
9592 && ! fixP
->fx_pcrel
)
9594 #if !defined (TE_PEP)
9595 /* For x86 PE weak function symbols are neither PC-relative
9596 nor do they set S_IS_FUNCTION. So the only reliable way
9597 to detect them is to check the flags of their containing
9599 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9600 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9604 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9608 /* Fix a few things - the dynamic linker expects certain values here,
9609 and we must not disappoint it. */
9610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9611 if (IS_ELF
&& fixP
->fx_addsy
)
9612 switch (fixP
->fx_r_type
)
9614 case BFD_RELOC_386_PLT32
:
9615 case BFD_RELOC_X86_64_PLT32
:
9616 /* Make the jump instruction point to the address of the operand. At
9617 runtime we merely add the offset to the actual PLT entry. */
9621 case BFD_RELOC_386_TLS_GD
:
9622 case BFD_RELOC_386_TLS_LDM
:
9623 case BFD_RELOC_386_TLS_IE_32
:
9624 case BFD_RELOC_386_TLS_IE
:
9625 case BFD_RELOC_386_TLS_GOTIE
:
9626 case BFD_RELOC_386_TLS_GOTDESC
:
9627 case BFD_RELOC_X86_64_TLSGD
:
9628 case BFD_RELOC_X86_64_TLSLD
:
9629 case BFD_RELOC_X86_64_GOTTPOFF
:
9630 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9631 value
= 0; /* Fully resolved at runtime. No addend. */
9633 case BFD_RELOC_386_TLS_LE
:
9634 case BFD_RELOC_386_TLS_LDO_32
:
9635 case BFD_RELOC_386_TLS_LE_32
:
9636 case BFD_RELOC_X86_64_DTPOFF32
:
9637 case BFD_RELOC_X86_64_DTPOFF64
:
9638 case BFD_RELOC_X86_64_TPOFF32
:
9639 case BFD_RELOC_X86_64_TPOFF64
:
9640 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9643 case BFD_RELOC_386_TLS_DESC_CALL
:
9644 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9645 value
= 0; /* Fully resolved at runtime. No addend. */
9646 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9650 case BFD_RELOC_VTABLE_INHERIT
:
9651 case BFD_RELOC_VTABLE_ENTRY
:
9658 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9660 #endif /* !defined (TE_Mach) */
9662 /* Are we finished with this relocation now? */
9663 if (fixP
->fx_addsy
== NULL
)
9665 #if defined (OBJ_COFF) && defined (TE_PE)
9666 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9669 /* Remember value for tc_gen_reloc. */
9670 fixP
->fx_addnumber
= value
;
9671 /* Clear out the frag for now. */
9675 else if (use_rela_relocations
)
9677 fixP
->fx_no_overflow
= 1;
9678 /* Remember value for tc_gen_reloc. */
9679 fixP
->fx_addnumber
= value
;
9683 md_number_to_chars (p
, value
, fixP
->fx_size
);
9687 md_atof (int type
, char *litP
, int *sizeP
)
9689 /* This outputs the LITTLENUMs in REVERSE order;
9690 in accord with the bigendian 386. */
9691 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9694 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9697 output_invalid (int c
)
9700 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9703 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9704 "(0x%x)", (unsigned char) c
);
9705 return output_invalid_buf
;
9708 /* REG_STRING starts *before* REGISTER_PREFIX. */
9710 static const reg_entry
*
9711 parse_real_register (char *reg_string
, char **end_op
)
9713 char *s
= reg_string
;
9715 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9718 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9719 if (*s
== REGISTER_PREFIX
)
9722 if (is_space_char (*s
))
9726 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9728 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9729 return (const reg_entry
*) NULL
;
9733 /* For naked regs, make sure that we are not dealing with an identifier.
9734 This prevents confusing an identifier like `eax_var' with register
9736 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9737 return (const reg_entry
*) NULL
;
9741 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9743 /* Handle floating point regs, allowing spaces in the (i) part. */
9744 if (r
== i386_regtab
/* %st is first entry of table */)
9746 if (is_space_char (*s
))
9751 if (is_space_char (*s
))
9753 if (*s
>= '0' && *s
<= '7')
9757 if (is_space_char (*s
))
9762 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9767 /* We have "%st(" then garbage. */
9768 return (const reg_entry
*) NULL
;
9772 if (r
== NULL
|| allow_pseudo_reg
)
9775 if (operand_type_all_zero (&r
->reg_type
))
9776 return (const reg_entry
*) NULL
;
9778 if ((r
->reg_type
.bitfield
.reg32
9779 || r
->reg_type
.bitfield
.sreg3
9780 || r
->reg_type
.bitfield
.control
9781 || r
->reg_type
.bitfield
.debug
9782 || r
->reg_type
.bitfield
.test
)
9783 && !cpu_arch_flags
.bitfield
.cpui386
)
9784 return (const reg_entry
*) NULL
;
9786 if (r
->reg_type
.bitfield
.floatreg
9787 && !cpu_arch_flags
.bitfield
.cpu8087
9788 && !cpu_arch_flags
.bitfield
.cpu287
9789 && !cpu_arch_flags
.bitfield
.cpu387
)
9790 return (const reg_entry
*) NULL
;
9792 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9793 return (const reg_entry
*) NULL
;
9795 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9796 return (const reg_entry
*) NULL
;
9798 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9799 return (const reg_entry
*) NULL
;
9801 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9802 return (const reg_entry
*) NULL
;
9804 if (r
->reg_type
.bitfield
.regmask
9805 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9806 return (const reg_entry
*) NULL
;
9808 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9809 if (!allow_index_reg
9810 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9811 return (const reg_entry
*) NULL
;
9813 /* Upper 16 vector register is only available with VREX in 64bit
9815 if ((r
->reg_flags
& RegVRex
))
9817 if (i
.vec_encoding
== vex_encoding_default
)
9818 i
.vec_encoding
= vex_encoding_evex
;
9820 if (!cpu_arch_flags
.bitfield
.cpuvrex
9821 || i
.vec_encoding
!= vex_encoding_evex
9822 || flag_code
!= CODE_64BIT
)
9823 return (const reg_entry
*) NULL
;
9826 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9827 || r
->reg_type
.bitfield
.reg64
)
9828 && (!cpu_arch_flags
.bitfield
.cpulm
9829 || !operand_type_equal (&r
->reg_type
, &control
))
9830 && flag_code
!= CODE_64BIT
)
9831 return (const reg_entry
*) NULL
;
9833 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9834 return (const reg_entry
*) NULL
;
9839 /* REG_STRING starts *before* REGISTER_PREFIX. */
9841 static const reg_entry
*
9842 parse_register (char *reg_string
, char **end_op
)
9846 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9847 r
= parse_real_register (reg_string
, end_op
);
9852 char *save
= input_line_pointer
;
9856 input_line_pointer
= reg_string
;
9857 c
= get_symbol_name (®_string
);
9858 symbolP
= symbol_find (reg_string
);
9859 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9861 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9863 know (e
->X_op
== O_register
);
9864 know (e
->X_add_number
>= 0
9865 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9866 r
= i386_regtab
+ e
->X_add_number
;
9867 if ((r
->reg_flags
& RegVRex
))
9868 i
.vec_encoding
= vex_encoding_evex
;
9869 *end_op
= input_line_pointer
;
9871 *input_line_pointer
= c
;
9872 input_line_pointer
= save
;
9878 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9881 char *end
= input_line_pointer
;
9884 r
= parse_register (name
, &input_line_pointer
);
9885 if (r
&& end
<= input_line_pointer
)
9887 *nextcharP
= *input_line_pointer
;
9888 *input_line_pointer
= 0;
9889 e
->X_op
= O_register
;
9890 e
->X_add_number
= r
- i386_regtab
;
9893 input_line_pointer
= end
;
9895 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9899 md_operand (expressionS
*e
)
9904 switch (*input_line_pointer
)
9906 case REGISTER_PREFIX
:
9907 r
= parse_real_register (input_line_pointer
, &end
);
9910 e
->X_op
= O_register
;
9911 e
->X_add_number
= r
- i386_regtab
;
9912 input_line_pointer
= end
;
9917 gas_assert (intel_syntax
);
9918 end
= input_line_pointer
++;
9920 if (*input_line_pointer
== ']')
9922 ++input_line_pointer
;
9923 e
->X_op_symbol
= make_expr_symbol (e
);
9924 e
->X_add_symbol
= NULL
;
9925 e
->X_add_number
= 0;
9931 input_line_pointer
= end
;
9938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9939 const char *md_shortopts
= "kVQ:sqn";
9941 const char *md_shortopts
= "qn";
9944 #define OPTION_32 (OPTION_MD_BASE + 0)
9945 #define OPTION_64 (OPTION_MD_BASE + 1)
9946 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9947 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9948 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9949 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9950 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9951 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9952 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9953 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9954 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9955 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9956 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9957 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9958 #define OPTION_X32 (OPTION_MD_BASE + 14)
9959 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9960 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9961 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9962 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9963 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9964 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9965 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9966 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9967 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9968 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9969 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9971 struct option md_longopts
[] =
9973 {"32", no_argument
, NULL
, OPTION_32
},
9974 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9975 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9976 {"64", no_argument
, NULL
, OPTION_64
},
9978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9979 {"x32", no_argument
, NULL
, OPTION_X32
},
9980 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9982 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9983 {"march", required_argument
, NULL
, OPTION_MARCH
},
9984 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9985 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9986 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9987 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9988 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9989 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9990 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9991 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9992 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9993 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9994 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9995 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9996 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9997 # if defined (TE_PE) || defined (TE_PEP)
9998 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10000 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10001 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10002 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10003 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10004 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10005 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10006 {NULL
, no_argument
, NULL
, 0}
10008 size_t md_longopts_size
= sizeof (md_longopts
);
10011 md_parse_option (int c
, const char *arg
)
10014 char *arch
, *next
, *saved
;
10019 optimize_align_code
= 0;
10023 quiet_warnings
= 1;
10026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10027 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10028 should be emitted or not. FIXME: Not implemented. */
10032 /* -V: SVR4 argument to print version ID. */
10034 print_version_id ();
10037 /* -k: Ignore for FreeBSD compatibility. */
10042 /* -s: On i386 Solaris, this tells the native assembler to use
10043 .stab instead of .stab.excl. We always use .stab anyhow. */
10046 case OPTION_MSHARED
:
10050 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10051 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10054 const char **list
, **l
;
10056 list
= bfd_target_list ();
10057 for (l
= list
; *l
!= NULL
; l
++)
10058 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10059 || strcmp (*l
, "coff-x86-64") == 0
10060 || strcmp (*l
, "pe-x86-64") == 0
10061 || strcmp (*l
, "pei-x86-64") == 0
10062 || strcmp (*l
, "mach-o-x86-64") == 0)
10064 default_arch
= "x86_64";
10068 as_fatal (_("no compiled in support for x86_64"));
10074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078 const char **list
, **l
;
10080 list
= bfd_target_list ();
10081 for (l
= list
; *l
!= NULL
; l
++)
10082 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10084 default_arch
= "x86_64:32";
10088 as_fatal (_("no compiled in support for 32bit x86_64"));
10092 as_fatal (_("32bit x86_64 is only supported for ELF"));
10097 default_arch
= "i386";
10100 case OPTION_DIVIDE
:
10101 #ifdef SVR4_COMMENT_CHARS
10106 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10108 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10112 i386_comment_chars
= n
;
10118 saved
= xstrdup (arg
);
10120 /* Allow -march=+nosse. */
10126 as_fatal (_("invalid -march= option: `%s'"), arg
);
10127 next
= strchr (arch
, '+');
10130 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10132 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10135 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10138 cpu_arch_name
= cpu_arch
[j
].name
;
10139 cpu_sub_arch_name
= NULL
;
10140 cpu_arch_flags
= cpu_arch
[j
].flags
;
10141 cpu_arch_isa
= cpu_arch
[j
].type
;
10142 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10143 if (!cpu_arch_tune_set
)
10145 cpu_arch_tune
= cpu_arch_isa
;
10146 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10150 else if (*cpu_arch
[j
].name
== '.'
10151 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10153 /* ISA extension. */
10154 i386_cpu_flags flags
;
10156 flags
= cpu_flags_or (cpu_arch_flags
,
10157 cpu_arch
[j
].flags
);
10159 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10161 if (cpu_sub_arch_name
)
10163 char *name
= cpu_sub_arch_name
;
10164 cpu_sub_arch_name
= concat (name
,
10166 (const char *) NULL
);
10170 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10171 cpu_arch_flags
= flags
;
10172 cpu_arch_isa_flags
= flags
;
10178 if (j
>= ARRAY_SIZE (cpu_arch
))
10180 /* Disable an ISA extension. */
10181 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10182 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10184 i386_cpu_flags flags
;
10186 flags
= cpu_flags_and_not (cpu_arch_flags
,
10187 cpu_noarch
[j
].flags
);
10188 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10190 if (cpu_sub_arch_name
)
10192 char *name
= cpu_sub_arch_name
;
10193 cpu_sub_arch_name
= concat (arch
,
10194 (const char *) NULL
);
10198 cpu_sub_arch_name
= xstrdup (arch
);
10199 cpu_arch_flags
= flags
;
10200 cpu_arch_isa_flags
= flags
;
10205 if (j
>= ARRAY_SIZE (cpu_noarch
))
10206 j
= ARRAY_SIZE (cpu_arch
);
10209 if (j
>= ARRAY_SIZE (cpu_arch
))
10210 as_fatal (_("invalid -march= option: `%s'"), arg
);
10214 while (next
!= NULL
);
10220 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10221 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10223 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10225 cpu_arch_tune_set
= 1;
10226 cpu_arch_tune
= cpu_arch
[j
].type
;
10227 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10231 if (j
>= ARRAY_SIZE (cpu_arch
))
10232 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10235 case OPTION_MMNEMONIC
:
10236 if (strcasecmp (arg
, "att") == 0)
10237 intel_mnemonic
= 0;
10238 else if (strcasecmp (arg
, "intel") == 0)
10239 intel_mnemonic
= 1;
10241 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10244 case OPTION_MSYNTAX
:
10245 if (strcasecmp (arg
, "att") == 0)
10247 else if (strcasecmp (arg
, "intel") == 0)
10250 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10253 case OPTION_MINDEX_REG
:
10254 allow_index_reg
= 1;
10257 case OPTION_MNAKED_REG
:
10258 allow_naked_reg
= 1;
10261 case OPTION_MOLD_GCC
:
10265 case OPTION_MSSE2AVX
:
10269 case OPTION_MSSE_CHECK
:
10270 if (strcasecmp (arg
, "error") == 0)
10271 sse_check
= check_error
;
10272 else if (strcasecmp (arg
, "warning") == 0)
10273 sse_check
= check_warning
;
10274 else if (strcasecmp (arg
, "none") == 0)
10275 sse_check
= check_none
;
10277 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10280 case OPTION_MOPERAND_CHECK
:
10281 if (strcasecmp (arg
, "error") == 0)
10282 operand_check
= check_error
;
10283 else if (strcasecmp (arg
, "warning") == 0)
10284 operand_check
= check_warning
;
10285 else if (strcasecmp (arg
, "none") == 0)
10286 operand_check
= check_none
;
10288 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10291 case OPTION_MAVXSCALAR
:
10292 if (strcasecmp (arg
, "128") == 0)
10293 avxscalar
= vex128
;
10294 else if (strcasecmp (arg
, "256") == 0)
10295 avxscalar
= vex256
;
10297 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10300 case OPTION_MADD_BND_PREFIX
:
10301 add_bnd_prefix
= 1;
10304 case OPTION_MEVEXLIG
:
10305 if (strcmp (arg
, "128") == 0)
10306 evexlig
= evexl128
;
10307 else if (strcmp (arg
, "256") == 0)
10308 evexlig
= evexl256
;
10309 else if (strcmp (arg
, "512") == 0)
10310 evexlig
= evexl512
;
10312 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10315 case OPTION_MEVEXRCIG
:
10316 if (strcmp (arg
, "rne") == 0)
10318 else if (strcmp (arg
, "rd") == 0)
10320 else if (strcmp (arg
, "ru") == 0)
10322 else if (strcmp (arg
, "rz") == 0)
10325 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10328 case OPTION_MEVEXWIG
:
10329 if (strcmp (arg
, "0") == 0)
10331 else if (strcmp (arg
, "1") == 0)
10334 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10337 # if defined (TE_PE) || defined (TE_PEP)
10338 case OPTION_MBIG_OBJ
:
10343 case OPTION_MOMIT_LOCK_PREFIX
:
10344 if (strcasecmp (arg
, "yes") == 0)
10345 omit_lock_prefix
= 1;
10346 else if (strcasecmp (arg
, "no") == 0)
10347 omit_lock_prefix
= 0;
10349 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10352 case OPTION_MFENCE_AS_LOCK_ADD
:
10353 if (strcasecmp (arg
, "yes") == 0)
10355 else if (strcasecmp (arg
, "no") == 0)
10358 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10361 case OPTION_MRELAX_RELOCATIONS
:
10362 if (strcasecmp (arg
, "yes") == 0)
10363 generate_relax_relocations
= 1;
10364 else if (strcasecmp (arg
, "no") == 0)
10365 generate_relax_relocations
= 0;
10367 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10370 case OPTION_MAMD64
:
10374 case OPTION_MINTEL64
:
10384 #define MESSAGE_TEMPLATE \
10388 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10389 int *left_p
, const char *name
, int len
)
10391 int size
= sizeof (MESSAGE_TEMPLATE
);
10392 int left
= *left_p
;
10394 /* Reserve 2 spaces for ", " or ",\0" */
10397 /* Check if there is any room. */
10405 p
= mempcpy (p
, name
, len
);
10409 /* Output the current message now and start a new one. */
10412 fprintf (stream
, "%s\n", message
);
10414 left
= size
- (start
- message
) - len
- 2;
10416 gas_assert (left
>= 0);
10418 p
= mempcpy (p
, name
, len
);
10426 show_arch (FILE *stream
, int ext
, int check
)
10428 static char message
[] = MESSAGE_TEMPLATE
;
10429 char *start
= message
+ 27;
10431 int size
= sizeof (MESSAGE_TEMPLATE
);
10438 left
= size
- (start
- message
);
10439 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10441 /* Should it be skipped? */
10442 if (cpu_arch
[j
].skip
)
10445 name
= cpu_arch
[j
].name
;
10446 len
= cpu_arch
[j
].len
;
10449 /* It is an extension. Skip if we aren't asked to show it. */
10460 /* It is an processor. Skip if we show only extension. */
10463 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10465 /* It is an impossible processor - skip. */
10469 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10472 /* Display disabled extensions. */
10474 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10476 name
= cpu_noarch
[j
].name
;
10477 len
= cpu_noarch
[j
].len
;
10478 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10483 fprintf (stream
, "%s\n", message
);
10487 md_show_usage (FILE *stream
)
10489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10490 fprintf (stream
, _("\
10492 -V print assembler version number\n\
10495 fprintf (stream
, _("\
10496 -n Do not optimize code alignment\n\
10497 -q quieten some warnings\n"));
10498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10499 fprintf (stream
, _("\
10502 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10503 || defined (TE_PE) || defined (TE_PEP))
10504 fprintf (stream
, _("\
10505 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10507 #ifdef SVR4_COMMENT_CHARS
10508 fprintf (stream
, _("\
10509 --divide do not treat `/' as a comment character\n"));
10511 fprintf (stream
, _("\
10512 --divide ignored\n"));
10514 fprintf (stream
, _("\
10515 -march=CPU[,+EXTENSION...]\n\
10516 generate code for CPU and EXTENSION, CPU is one of:\n"));
10517 show_arch (stream
, 0, 1);
10518 fprintf (stream
, _("\
10519 EXTENSION is combination of:\n"));
10520 show_arch (stream
, 1, 0);
10521 fprintf (stream
, _("\
10522 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10523 show_arch (stream
, 0, 0);
10524 fprintf (stream
, _("\
10525 -msse2avx encode SSE instructions with VEX prefix\n"));
10526 fprintf (stream
, _("\
10527 -msse-check=[none|error|warning]\n\
10528 check SSE instructions\n"));
10529 fprintf (stream
, _("\
10530 -moperand-check=[none|error|warning]\n\
10531 check operand combinations for validity\n"));
10532 fprintf (stream
, _("\
10533 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10535 fprintf (stream
, _("\
10536 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10538 fprintf (stream
, _("\
10539 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10540 for EVEX.W bit ignored instructions\n"));
10541 fprintf (stream
, _("\
10542 -mevexrcig=[rne|rd|ru|rz]\n\
10543 encode EVEX instructions with specific EVEX.RC value\n\
10544 for SAE-only ignored instructions\n"));
10545 fprintf (stream
, _("\
10546 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10547 fprintf (stream
, _("\
10548 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10549 fprintf (stream
, _("\
10550 -mindex-reg support pseudo index registers\n"));
10551 fprintf (stream
, _("\
10552 -mnaked-reg don't require `%%' prefix for registers\n"));
10553 fprintf (stream
, _("\
10554 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10555 fprintf (stream
, _("\
10556 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10557 fprintf (stream
, _("\
10558 -mshared disable branch optimization for shared code\n"));
10559 # if defined (TE_PE) || defined (TE_PEP)
10560 fprintf (stream
, _("\
10561 -mbig-obj generate big object files\n"));
10563 fprintf (stream
, _("\
10564 -momit-lock-prefix=[no|yes]\n\
10565 strip all lock prefixes\n"));
10566 fprintf (stream
, _("\
10567 -mfence-as-lock-add=[no|yes]\n\
10568 encode lfence, mfence and sfence as\n\
10569 lock addl $0x0, (%%{re}sp)\n"));
10570 fprintf (stream
, _("\
10571 -mrelax-relocations=[no|yes]\n\
10572 generate relax relocations\n"));
10573 fprintf (stream
, _("\
10574 -mamd64 accept only AMD64 ISA\n"));
10575 fprintf (stream
, _("\
10576 -mintel64 accept only Intel64 ISA\n"));
10579 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10580 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10581 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10583 /* Pick the target format to use. */
10586 i386_target_format (void)
10588 if (!strncmp (default_arch
, "x86_64", 6))
10590 update_code_flag (CODE_64BIT
, 1);
10591 if (default_arch
[6] == '\0')
10592 x86_elf_abi
= X86_64_ABI
;
10594 x86_elf_abi
= X86_64_X32_ABI
;
10596 else if (!strcmp (default_arch
, "i386"))
10597 update_code_flag (CODE_32BIT
, 1);
10598 else if (!strcmp (default_arch
, "iamcu"))
10600 update_code_flag (CODE_32BIT
, 1);
10601 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10603 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10604 cpu_arch_name
= "iamcu";
10605 cpu_sub_arch_name
= NULL
;
10606 cpu_arch_flags
= iamcu_flags
;
10607 cpu_arch_isa
= PROCESSOR_IAMCU
;
10608 cpu_arch_isa_flags
= iamcu_flags
;
10609 if (!cpu_arch_tune_set
)
10611 cpu_arch_tune
= cpu_arch_isa
;
10612 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10615 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10616 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10620 as_fatal (_("unknown architecture"));
10622 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10623 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10624 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10625 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10627 switch (OUTPUT_FLAVOR
)
10629 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10630 case bfd_target_aout_flavour
:
10631 return AOUT_TARGET_FORMAT
;
10633 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10634 # if defined (TE_PE) || defined (TE_PEP)
10635 case bfd_target_coff_flavour
:
10636 if (flag_code
== CODE_64BIT
)
10637 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10640 # elif defined (TE_GO32)
10641 case bfd_target_coff_flavour
:
10642 return "coff-go32";
10644 case bfd_target_coff_flavour
:
10645 return "coff-i386";
10648 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10649 case bfd_target_elf_flavour
:
10651 const char *format
;
10653 switch (x86_elf_abi
)
10656 format
= ELF_TARGET_FORMAT
;
10659 use_rela_relocations
= 1;
10661 format
= ELF_TARGET_FORMAT64
;
10663 case X86_64_X32_ABI
:
10664 use_rela_relocations
= 1;
10666 disallow_64bit_reloc
= 1;
10667 format
= ELF_TARGET_FORMAT32
;
10670 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10672 if (x86_elf_abi
!= X86_64_ABI
)
10673 as_fatal (_("Intel L1OM is 64bit only"));
10674 return ELF_TARGET_L1OM_FORMAT
;
10676 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10678 if (x86_elf_abi
!= X86_64_ABI
)
10679 as_fatal (_("Intel K1OM is 64bit only"));
10680 return ELF_TARGET_K1OM_FORMAT
;
10682 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10684 if (x86_elf_abi
!= I386_ABI
)
10685 as_fatal (_("Intel MCU is 32bit only"));
10686 return ELF_TARGET_IAMCU_FORMAT
;
10692 #if defined (OBJ_MACH_O)
10693 case bfd_target_mach_o_flavour
:
10694 if (flag_code
== CODE_64BIT
)
10696 use_rela_relocations
= 1;
10698 return "mach-o-x86-64";
10701 return "mach-o-i386";
10709 #endif /* OBJ_MAYBE_ more than one */
10712 md_undefined_symbol (char *name
)
10714 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10715 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10716 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10717 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10721 if (symbol_find (name
))
10722 as_bad (_("GOT already in symbol table"));
10723 GOT_symbol
= symbol_new (name
, undefined_section
,
10724 (valueT
) 0, &zero_address_frag
);
10731 /* Round up a section size to the appropriate boundary. */
10734 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10736 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10737 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10739 /* For a.out, force the section size to be aligned. If we don't do
10740 this, BFD will align it for us, but it will not write out the
10741 final bytes of the section. This may be a bug in BFD, but it is
10742 easier to fix it here since that is how the other a.out targets
10746 align
= bfd_get_section_alignment (stdoutput
, segment
);
10747 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10754 /* On the i386, PC-relative offsets are relative to the start of the
10755 next instruction. That is, the address of the offset, plus its
10756 size, since the offset is always the last part of the insn. */
10759 md_pcrel_from (fixS
*fixP
)
10761 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10767 s_bss (int ignore ATTRIBUTE_UNUSED
)
10771 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10773 obj_elf_section_change_hook ();
10775 temp
= get_absolute_expression ();
10776 subseg_set (bss_section
, (subsegT
) temp
);
10777 demand_empty_rest_of_line ();
10783 i386_validate_fix (fixS
*fixp
)
10785 if (fixp
->fx_subsy
)
10787 if (fixp
->fx_subsy
== GOT_symbol
)
10789 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10793 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10794 if (fixp
->fx_tcbit2
)
10795 fixp
->fx_r_type
= (fixp
->fx_tcbit
10796 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10797 : BFD_RELOC_X86_64_GOTPCRELX
);
10800 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10805 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10807 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10809 fixp
->fx_subsy
= 0;
10812 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10813 else if (!object_64bit
)
10815 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10816 && fixp
->fx_tcbit2
)
10817 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10823 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10826 bfd_reloc_code_real_type code
;
10828 switch (fixp
->fx_r_type
)
10830 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10831 case BFD_RELOC_SIZE32
:
10832 case BFD_RELOC_SIZE64
:
10833 if (S_IS_DEFINED (fixp
->fx_addsy
)
10834 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10836 /* Resolve size relocation against local symbol to size of
10837 the symbol plus addend. */
10838 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10839 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10840 && !fits_in_unsigned_long (value
))
10841 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10842 _("symbol size computation overflow"));
10843 fixp
->fx_addsy
= NULL
;
10844 fixp
->fx_subsy
= NULL
;
10845 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10849 /* Fall through. */
10851 case BFD_RELOC_X86_64_PLT32
:
10852 case BFD_RELOC_X86_64_GOT32
:
10853 case BFD_RELOC_X86_64_GOTPCREL
:
10854 case BFD_RELOC_X86_64_GOTPCRELX
:
10855 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10856 case BFD_RELOC_386_PLT32
:
10857 case BFD_RELOC_386_GOT32
:
10858 case BFD_RELOC_386_GOT32X
:
10859 case BFD_RELOC_386_GOTOFF
:
10860 case BFD_RELOC_386_GOTPC
:
10861 case BFD_RELOC_386_TLS_GD
:
10862 case BFD_RELOC_386_TLS_LDM
:
10863 case BFD_RELOC_386_TLS_LDO_32
:
10864 case BFD_RELOC_386_TLS_IE_32
:
10865 case BFD_RELOC_386_TLS_IE
:
10866 case BFD_RELOC_386_TLS_GOTIE
:
10867 case BFD_RELOC_386_TLS_LE_32
:
10868 case BFD_RELOC_386_TLS_LE
:
10869 case BFD_RELOC_386_TLS_GOTDESC
:
10870 case BFD_RELOC_386_TLS_DESC_CALL
:
10871 case BFD_RELOC_X86_64_TLSGD
:
10872 case BFD_RELOC_X86_64_TLSLD
:
10873 case BFD_RELOC_X86_64_DTPOFF32
:
10874 case BFD_RELOC_X86_64_DTPOFF64
:
10875 case BFD_RELOC_X86_64_GOTTPOFF
:
10876 case BFD_RELOC_X86_64_TPOFF32
:
10877 case BFD_RELOC_X86_64_TPOFF64
:
10878 case BFD_RELOC_X86_64_GOTOFF64
:
10879 case BFD_RELOC_X86_64_GOTPC32
:
10880 case BFD_RELOC_X86_64_GOT64
:
10881 case BFD_RELOC_X86_64_GOTPCREL64
:
10882 case BFD_RELOC_X86_64_GOTPC64
:
10883 case BFD_RELOC_X86_64_GOTPLT64
:
10884 case BFD_RELOC_X86_64_PLTOFF64
:
10885 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10886 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10887 case BFD_RELOC_RVA
:
10888 case BFD_RELOC_VTABLE_ENTRY
:
10889 case BFD_RELOC_VTABLE_INHERIT
:
10891 case BFD_RELOC_32_SECREL
:
10893 code
= fixp
->fx_r_type
;
10895 case BFD_RELOC_X86_64_32S
:
10896 if (!fixp
->fx_pcrel
)
10898 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10899 code
= fixp
->fx_r_type
;
10902 /* Fall through. */
10904 if (fixp
->fx_pcrel
)
10906 switch (fixp
->fx_size
)
10909 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10910 _("can not do %d byte pc-relative relocation"),
10912 code
= BFD_RELOC_32_PCREL
;
10914 case 1: code
= BFD_RELOC_8_PCREL
; break;
10915 case 2: code
= BFD_RELOC_16_PCREL
; break;
10916 case 4: code
= BFD_RELOC_32_PCREL
; break;
10918 case 8: code
= BFD_RELOC_64_PCREL
; break;
10924 switch (fixp
->fx_size
)
10927 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10928 _("can not do %d byte relocation"),
10930 code
= BFD_RELOC_32
;
10932 case 1: code
= BFD_RELOC_8
; break;
10933 case 2: code
= BFD_RELOC_16
; break;
10934 case 4: code
= BFD_RELOC_32
; break;
10936 case 8: code
= BFD_RELOC_64
; break;
10943 if ((code
== BFD_RELOC_32
10944 || code
== BFD_RELOC_32_PCREL
10945 || code
== BFD_RELOC_X86_64_32S
)
10947 && fixp
->fx_addsy
== GOT_symbol
)
10950 code
= BFD_RELOC_386_GOTPC
;
10952 code
= BFD_RELOC_X86_64_GOTPC32
;
10954 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10956 && fixp
->fx_addsy
== GOT_symbol
)
10958 code
= BFD_RELOC_X86_64_GOTPC64
;
10961 rel
= XNEW (arelent
);
10962 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10963 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10965 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10967 if (!use_rela_relocations
)
10969 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10970 vtable entry to be used in the relocation's section offset. */
10971 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10972 rel
->address
= fixp
->fx_offset
;
10973 #if defined (OBJ_COFF) && defined (TE_PE)
10974 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10975 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10980 /* Use the rela in 64bit mode. */
10983 if (disallow_64bit_reloc
)
10986 case BFD_RELOC_X86_64_DTPOFF64
:
10987 case BFD_RELOC_X86_64_TPOFF64
:
10988 case BFD_RELOC_64_PCREL
:
10989 case BFD_RELOC_X86_64_GOTOFF64
:
10990 case BFD_RELOC_X86_64_GOT64
:
10991 case BFD_RELOC_X86_64_GOTPCREL64
:
10992 case BFD_RELOC_X86_64_GOTPC64
:
10993 case BFD_RELOC_X86_64_GOTPLT64
:
10994 case BFD_RELOC_X86_64_PLTOFF64
:
10995 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10996 _("cannot represent relocation type %s in x32 mode"),
10997 bfd_get_reloc_code_name (code
));
11003 if (!fixp
->fx_pcrel
)
11004 rel
->addend
= fixp
->fx_offset
;
11008 case BFD_RELOC_X86_64_PLT32
:
11009 case BFD_RELOC_X86_64_GOT32
:
11010 case BFD_RELOC_X86_64_GOTPCREL
:
11011 case BFD_RELOC_X86_64_GOTPCRELX
:
11012 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11013 case BFD_RELOC_X86_64_TLSGD
:
11014 case BFD_RELOC_X86_64_TLSLD
:
11015 case BFD_RELOC_X86_64_GOTTPOFF
:
11016 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11017 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11018 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11021 rel
->addend
= (section
->vma
11023 + fixp
->fx_addnumber
11024 + md_pcrel_from (fixp
));
11029 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11030 if (rel
->howto
== NULL
)
11032 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11033 _("cannot represent relocation type %s"),
11034 bfd_get_reloc_code_name (code
));
11035 /* Set howto to a garbage value so that we can keep going. */
11036 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11037 gas_assert (rel
->howto
!= NULL
);
11043 #include "tc-i386-intel.c"
11046 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11048 int saved_naked_reg
;
11049 char saved_register_dot
;
11051 saved_naked_reg
= allow_naked_reg
;
11052 allow_naked_reg
= 1;
11053 saved_register_dot
= register_chars
['.'];
11054 register_chars
['.'] = '.';
11055 allow_pseudo_reg
= 1;
11056 expression_and_evaluate (exp
);
11057 allow_pseudo_reg
= 0;
11058 register_chars
['.'] = saved_register_dot
;
11059 allow_naked_reg
= saved_naked_reg
;
11061 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11063 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11065 exp
->X_op
= O_constant
;
11066 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11067 .dw2_regnum
[flag_code
>> 1];
11070 exp
->X_op
= O_illegal
;
11075 tc_x86_frame_initial_instructions (void)
11077 static unsigned int sp_regno
[2];
11079 if (!sp_regno
[flag_code
>> 1])
11081 char *saved_input
= input_line_pointer
;
11082 char sp
[][4] = {"esp", "rsp"};
11085 input_line_pointer
= sp
[flag_code
>> 1];
11086 tc_x86_parse_to_dw2regnum (&exp
);
11087 gas_assert (exp
.X_op
== O_constant
);
11088 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11089 input_line_pointer
= saved_input
;
11092 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11093 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11097 x86_dwarf2_addr_size (void)
11099 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11100 if (x86_elf_abi
== X86_64_X32_ABI
)
11103 return bfd_arch_bits_per_address (stdoutput
) / 8;
11107 i386_elf_section_type (const char *str
, size_t len
)
11109 if (flag_code
== CODE_64BIT
11110 && len
== sizeof ("unwind") - 1
11111 && strncmp (str
, "unwind", 6) == 0)
11112 return SHT_X86_64_UNWIND
;
11119 i386_solaris_fix_up_eh_frame (segT sec
)
11121 if (flag_code
== CODE_64BIT
)
11122 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11128 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11132 exp
.X_op
= O_secrel
;
11133 exp
.X_add_symbol
= symbol
;
11134 exp
.X_add_number
= 0;
11135 emit_expr (&exp
, size
);
11139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11140 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11143 x86_64_section_letter (int letter
, const char **ptr_msg
)
11145 if (flag_code
== CODE_64BIT
)
11148 return SHF_X86_64_LARGE
;
11150 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11153 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11158 x86_64_section_word (char *str
, size_t len
)
11160 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11161 return SHF_X86_64_LARGE
;
11167 handle_large_common (int small ATTRIBUTE_UNUSED
)
11169 if (flag_code
!= CODE_64BIT
)
11171 s_comm_internal (0, elf_common_parse
);
11172 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11176 static segT lbss_section
;
11177 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11178 asection
*saved_bss_section
= bss_section
;
11180 if (lbss_section
== NULL
)
11182 flagword applicable
;
11183 segT seg
= now_seg
;
11184 subsegT subseg
= now_subseg
;
11186 /* The .lbss section is for local .largecomm symbols. */
11187 lbss_section
= subseg_new (".lbss", 0);
11188 applicable
= bfd_applicable_section_flags (stdoutput
);
11189 bfd_set_section_flags (stdoutput
, lbss_section
,
11190 applicable
& SEC_ALLOC
);
11191 seg_info (lbss_section
)->bss
= 1;
11193 subseg_set (seg
, subseg
);
11196 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11197 bss_section
= lbss_section
;
11199 s_comm_internal (0, elf_common_parse
);
11201 elf_com_section_ptr
= saved_com_section_ptr
;
11202 bss_section
= saved_bss_section
;
11205 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */