1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
70 #define BND_PREFIX REP_PREFIX
72 #define REX_PREFIX 6 /* must come last. */
73 #define MAX_PREFIXES 7 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 #define ZMMWORD_MNEM_SUFFIX 'z'
90 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94 #define END_OF_INSN '\0'
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
105 const insn_template
*start
;
106 const insn_template
*end
;
110 /* 386 operand encoding bytes: see 386 book for details of this. */
113 unsigned int regmem
; /* codes register or memory operand */
114 unsigned int reg
; /* codes register operand (or extended opcode) */
115 unsigned int mode
; /* how to interpret regmem & reg */
119 /* x86-64 extension prefix. */
120 typedef int rex_byte
;
122 /* 386 opcode byte to code indirect addressing. */
131 /* x86 arch names, types and features */
134 const char *name
; /* arch name */
135 unsigned int len
; /* arch string length */
136 enum processor_type type
; /* arch type */
137 i386_cpu_flags flags
; /* cpu feature flags */
138 unsigned int skip
; /* show_arch should skip this. */
139 unsigned int negated
; /* turn off indicated flags. */
143 static void update_code_flag (int, int);
144 static void set_code_flag (int);
145 static void set_16bit_gcc_code_flag (int);
146 static void set_intel_syntax (int);
147 static void set_intel_mnemonic (int);
148 static void set_allow_index_reg (int);
149 static void set_check (int);
150 static void set_cpu_arch (int);
152 static void pe_directive_secrel (int);
154 static void signed_cons (int);
155 static char *output_invalid (int c
);
156 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
158 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
160 static int i386_att_operand (char *);
161 static int i386_intel_operand (char *, int);
162 static int i386_intel_simplify (expressionS
*);
163 static int i386_intel_parse_name (const char *, expressionS
*);
164 static const reg_entry
*parse_register (char *, char **);
165 static char *parse_insn (char *, char *);
166 static char *parse_operands (char *, const char *);
167 static void swap_operands (void);
168 static void swap_2_operands (int, int);
169 static void optimize_imm (void);
170 static void optimize_disp (void);
171 static const insn_template
*match_template (void);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const seg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
191 static const char *default_arch
= DEFAULT_ARCH
;
193 /* This struct describes rounding control and SAE in the instruction. */
207 static struct RC_Operation rc_op
;
209 /* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212 struct Mask_Operation
214 const reg_entry
*mask
;
215 unsigned int zeroing
;
216 /* The operand where this operation is associated. */
220 static struct Mask_Operation mask_op
;
222 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
224 struct Broadcast_Operation
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 /* Index of broadcasted operand. */
233 static struct Broadcast_Operation broadcast_op
;
238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes
[4];
241 /* Destination or source register specifier. */
242 const reg_entry
*register_specifier
;
245 /* 'md_assemble ()' gathers together information and puts it into a
252 const reg_entry
*regs
;
257 operand_size_mismatch
,
258 operand_type_mismatch
,
259 register_type_mismatch
,
260 number_of_operands_mismatch
,
261 invalid_instruction_suffix
,
264 unsupported_with_intel_mnemonic
,
267 invalid_vsib_address
,
268 invalid_vector_register_set
,
269 unsupported_vector_index_register
,
270 unsupported_broadcast
,
271 broadcast_not_on_src_operand
,
274 mask_not_on_destination
,
277 rc_sae_operand_not_last_imm
,
278 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes
;
327 unsigned char prefix
[MAX_PREFIXES
];
329 /* RM and SIB are the modrm byte and the sib byte where the
330 addressing modes of this insn are encoded. */
337 /* Masking attributes. */
338 struct Mask_Operation
*mask
;
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation
*rounding
;
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation
*broadcast
;
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift
;
349 /* Swap operand in encoding. */
350 unsigned int swap_operand
;
352 /* Prefer 8bit or 32bit displacement in encoding. */
355 disp_encoding_default
= 0,
361 const char *rep_prefix
;
364 const char *hle_prefix
;
366 /* Have BND prefix. */
367 const char *bnd_prefix
;
369 /* Need VREX to support upper 16 registers. */
373 enum i386_error error
;
376 typedef struct _i386_insn i386_insn
;
378 /* Link RC type with corresponding string, that'll be looked for in
387 static const struct RC_name RC_NamesTable
[] =
389 { rne
, STRING_COMMA_LEN ("rn-sae") },
390 { rd
, STRING_COMMA_LEN ("rd-sae") },
391 { ru
, STRING_COMMA_LEN ("ru-sae") },
392 { rz
, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly
, STRING_COMMA_LEN ("sae") },
396 /* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
398 const char extra_symbol_chars
[] = "*%-([{"
407 #if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
409 && !defined (TE_GNU) \
410 && !defined (TE_LINUX) \
411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
413 && !defined (TE_FreeBSD) \
414 && !defined (TE_DragonFly) \
415 && !defined (TE_NetBSD)))
416 /* This array holds the chars that always start a comment. If the
417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419 const char *i386_comment_chars
= "#/";
420 #define SVR4_COMMENT_CHARS 1
421 #define PREFIX_SEPARATOR '\\'
424 const char *i386_comment_chars
= "#";
425 #define PREFIX_SEPARATOR '/'
428 /* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
432 first line of the input file. This is because the compiler outputs
433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
435 '/' isn't otherwise defined. */
436 const char line_comment_chars
[] = "#/";
438 const char line_separator_chars
[] = ";";
440 /* Chars that can be used to separate mant from exp in floating point
442 const char EXP_CHARS
[] = "eE";
444 /* Chars that mean this number is a floating point constant
447 const char FLT_CHARS
[] = "fFdDxX";
449 /* Tables for lexical analysis. */
450 static char mnemonic_chars
[256];
451 static char register_chars
[256];
452 static char operand_chars
[256];
453 static char identifier_chars
[256];
454 static char digit_chars
[256];
456 /* Lexical macros. */
457 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458 #define is_operand_char(x) (operand_chars[(unsigned char) x])
459 #define is_register_char(x) (register_chars[(unsigned char) x])
460 #define is_space_char(x) ((x) == ' ')
461 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462 #define is_digit_char(x) (digit_chars[(unsigned char) x])
464 /* All non-digit non-letter characters that may occur in an operand. */
465 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
467 /* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
470 assembler instruction). */
471 static char save_stack
[32];
472 static char *save_stack_p
;
473 #define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475 #define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
478 /* The instruction we're assembling. */
481 /* Possible templates for current insn. */
482 static const templates
*current_templates
;
484 /* Per instruction expressionS buffers: max displacements & immediates. */
485 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
486 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
488 /* Current operand we are working on. */
489 static int this_operand
= -1;
491 /* We support four different modes. FLAG_CODE variable is used to distinguish
499 static enum flag_code flag_code
;
500 static unsigned int object_64bit
;
501 static unsigned int disallow_64bit_reloc
;
502 static int use_rela_relocations
= 0;
504 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
508 /* The ELF ABI to use. */
516 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
519 /* 1 for intel syntax,
521 static int intel_syntax
= 0;
523 /* 1 for intel mnemonic,
524 0 if att mnemonic. */
525 static int intel_mnemonic
= !SYSV386_COMPAT
;
527 /* 1 if support old (<= 2.8.1) versions of gcc. */
528 static int old_gcc
= OLDGCC_COMPAT
;
530 /* 1 if pseudo registers are permitted. */
531 static int allow_pseudo_reg
= 0;
533 /* 1 if register prefix % not required. */
534 static int allow_naked_reg
= 0;
536 /* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
539 static int add_bnd_prefix
= 0;
541 /* 1 if pseudo index register, eiz/riz, is allowed . */
542 static int allow_index_reg
= 0;
544 static enum check_kind
550 sse_check
, operand_check
= check_warning
;
552 /* Register prefix used for error message. */
553 static const char *register_prefix
= "%";
555 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558 static char stackop_size
= '\0';
560 /* Non-zero to optimize code alignment. */
561 int optimize_align_code
= 1;
563 /* Non-zero to quieten some warnings. */
564 static int quiet_warnings
= 0;
567 static const char *cpu_arch_name
= NULL
;
568 static char *cpu_sub_arch_name
= NULL
;
570 /* CPU feature flags. */
571 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
573 /* If we have selected a cpu we are generating instructions for. */
574 static int cpu_arch_tune_set
= 0;
576 /* Cpu we are generating instructions for. */
577 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
579 /* CPU feature flags of cpu we are generating instructions for. */
580 static i386_cpu_flags cpu_arch_tune_flags
;
582 /* CPU instruction set architecture used. */
583 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of instruction set architecture used. */
586 i386_cpu_flags cpu_arch_isa_flags
;
588 /* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590 static unsigned int no_cond_jump_promotion
= 0;
592 /* Encode SSE instructions with VEX prefix. */
593 static unsigned int sse2avx
;
595 /* Encode scalar AVX instructions with specific vector length. */
602 /* Encode scalar EVEX LIG instructions with specific vector length. */
610 /* Encode EVEX WIG instructions with specific evex.w. */
617 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
618 static symbolS
*GOT_symbol
;
620 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
621 unsigned int x86_dwarf2_return_column
;
623 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624 int x86_cie_data_alignment
;
626 /* Interface to relax_segment.
627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
632 #define UNCOND_JUMP 0
634 #define COND_JUMP86 2
639 #define SMALL16 (SMALL | CODE16)
641 #define BIG16 (BIG | CODE16)
645 #define INLINE __inline__
651 #define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653 #define TYPE_FROM_RELAX_STATE(s) \
655 #define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
658 /* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
666 const relax_typeS md_relax_table
[] =
669 1) most positive reach of this state,
670 2) most negative reach of this state,
671 3) how many bytes this mode will have in the variable part of the frag
672 4) which index into the table to try if we can't fit into this one. */
674 /* UNCOND_JUMP states. */
675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
690 /* word conditionals add 3 bytes to frag:
691 1 extra opcode byte, 2 displacement bytes. */
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
705 static const arch_entry cpu_arch
[] =
707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
710 CPU_GENERIC32_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
712 CPU_GENERIC64_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
714 CPU_NONE_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
716 CPU_I186_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
718 CPU_I286_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
720 CPU_I386_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
722 CPU_I486_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
724 CPU_I586_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
726 CPU_I686_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
728 CPU_I586_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
730 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
732 CPU_P2_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
734 CPU_P3_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
736 CPU_P4_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
738 CPU_CORE_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
740 CPU_NOCONA_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
742 CPU_CORE_FLAGS
, 1, 0 },
743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
746 CPU_CORE2_FLAGS
, 1, 0 },
747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
750 CPU_COREI7_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
752 CPU_L1OM_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
754 CPU_K1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
756 CPU_K6_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
758 CPU_K6_2_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
760 CPU_ATHLON_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
762 CPU_K8_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
768 CPU_AMDFAM10_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
770 CPU_BDVER1_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
772 CPU_BDVER2_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
774 CPU_BDVER3_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
776 CPU_BDVER4_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
778 CPU_BTVER1_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
780 CPU_BTVER2_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
782 CPU_8087_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
784 CPU_287_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
786 CPU_387_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
788 CPU_ANY87_FLAGS
, 0, 1 },
789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
790 CPU_MMX_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
792 CPU_3DNOWA_FLAGS
, 0, 1 },
793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
794 CPU_SSE_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
796 CPU_SSE2_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
798 CPU_SSE3_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
800 CPU_SSSE3_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
802 CPU_SSE4_1_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
806 CPU_SSE4_2_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
808 CPU_ANY_SSE_FLAGS
, 0, 1 },
809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
810 CPU_AVX_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
812 CPU_AVX2_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
814 CPU_AVX512F_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512CD_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512ER_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512PF_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
822 CPU_ANY_AVX_FLAGS
, 0, 1 },
823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
824 CPU_VMX_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
826 CPU_VMFUNC_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
828 CPU_SMX_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
830 CPU_XSAVE_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
832 CPU_XSAVEOPT_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
834 CPU_AES_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
836 CPU_PCLMUL_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
838 CPU_PCLMUL_FLAGS
, 1, 0 },
839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
840 CPU_FSGSBASE_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
842 CPU_RDRND_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
844 CPU_F16C_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
846 CPU_BMI2_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
848 CPU_FMA_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
850 CPU_FMA4_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
852 CPU_XOP_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
854 CPU_LWP_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
856 CPU_MOVBE_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
858 CPU_CX16_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
860 CPU_EPT_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
862 CPU_LZCNT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
864 CPU_HLE_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
866 CPU_RTM_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
868 CPU_INVPCID_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
870 CPU_CLFLUSH_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
872 CPU_NOP_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
874 CPU_SYSCALL_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
876 CPU_RDTSCP_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
878 CPU_3DNOW_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
880 CPU_3DNOWA_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
882 CPU_PADLOCK_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
884 CPU_SVME_FLAGS
, 1, 0 },
885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
886 CPU_SVME_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
888 CPU_SSE4A_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
890 CPU_ABM_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
892 CPU_BMI_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
894 CPU_TBM_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
896 CPU_ADX_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
898 CPU_RDSEED_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
900 CPU_PRFCHW_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
902 CPU_SMAP_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
904 CPU_MPX_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
906 CPU_SHA_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
908 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
910 CPU_XSAVEC_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
912 CPU_XSAVES_FLAGS
, 0, 0 },
916 /* Like s_lcomm_internal in gas/read.c but the alignment string
917 is allowed to be optional. */
920 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
927 && *input_line_pointer
== ',')
929 align
= parse_align (needs_align
- 1);
931 if (align
== (addressT
) -1)
946 bss_alloc (symbolP
, size
, align
);
951 pe_lcomm (int needs_align
)
953 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
957 const pseudo_typeS md_pseudo_table
[] =
959 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
960 {"align", s_align_bytes
, 0},
962 {"align", s_align_ptwo
, 0},
964 {"arch", set_cpu_arch
, 0},
968 {"lcomm", pe_lcomm
, 1},
970 {"ffloat", float_cons
, 'f'},
971 {"dfloat", float_cons
, 'd'},
972 {"tfloat", float_cons
, 'x'},
974 {"slong", signed_cons
, 4},
975 {"noopt", s_ignore
, 0},
976 {"optim", s_ignore
, 0},
977 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
978 {"code16", set_code_flag
, CODE_16BIT
},
979 {"code32", set_code_flag
, CODE_32BIT
},
980 {"code64", set_code_flag
, CODE_64BIT
},
981 {"intel_syntax", set_intel_syntax
, 1},
982 {"att_syntax", set_intel_syntax
, 0},
983 {"intel_mnemonic", set_intel_mnemonic
, 1},
984 {"att_mnemonic", set_intel_mnemonic
, 0},
985 {"allow_index_reg", set_allow_index_reg
, 1},
986 {"disallow_index_reg", set_allow_index_reg
, 0},
987 {"sse_check", set_check
, 0},
988 {"operand_check", set_check
, 1},
989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
990 {"largecomm", handle_large_common
, 0},
992 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
993 {"loc", dwarf2_directive_loc
, 0},
994 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
997 {"secrel32", pe_directive_secrel
, 0},
1002 /* For interface with expression (). */
1003 extern char *input_line_pointer
;
1005 /* Hash table for instruction mnemonic lookup. */
1006 static struct hash_control
*op_hash
;
1008 /* Hash table for register lookup. */
1009 static struct hash_control
*reg_hash
;
1012 i386_align_code (fragS
*fragP
, int count
)
1014 /* Various efficient no-op patterns for aligning code labels.
1015 Note: Don't try to assemble the instructions in the comments.
1016 0L and 0w are not legal. */
1017 static const char f32_1
[] =
1019 static const char f32_2
[] =
1020 {0x66,0x90}; /* xchg %ax,%ax */
1021 static const char f32_3
[] =
1022 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1023 static const char f32_4
[] =
1024 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1025 static const char f32_5
[] =
1027 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1028 static const char f32_6
[] =
1029 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1030 static const char f32_7
[] =
1031 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1032 static const char f32_8
[] =
1034 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1035 static const char f32_9
[] =
1036 {0x89,0xf6, /* movl %esi,%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_10
[] =
1039 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1040 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1041 static const char f32_11
[] =
1042 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_12
[] =
1045 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1046 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1047 static const char f32_13
[] =
1048 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_14
[] =
1051 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1052 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1053 static const char f16_3
[] =
1054 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1055 static const char f16_4
[] =
1056 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1057 static const char f16_5
[] =
1059 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1060 static const char f16_6
[] =
1061 {0x89,0xf6, /* mov %si,%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1063 static const char f16_7
[] =
1064 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1065 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1066 static const char f16_8
[] =
1067 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1068 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1069 static const char jump_31
[] =
1070 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1071 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1072 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1073 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1074 static const char *const f32_patt
[] = {
1075 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1076 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1078 static const char *const f16_patt
[] = {
1079 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1081 /* nopl (%[re]ax) */
1082 static const char alt_3
[] =
1084 /* nopl 0(%[re]ax) */
1085 static const char alt_4
[] =
1086 {0x0f,0x1f,0x40,0x00};
1087 /* nopl 0(%[re]ax,%[re]ax,1) */
1088 static const char alt_5
[] =
1089 {0x0f,0x1f,0x44,0x00,0x00};
1090 /* nopw 0(%[re]ax,%[re]ax,1) */
1091 static const char alt_6
[] =
1092 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1093 /* nopl 0L(%[re]ax) */
1094 static const char alt_7
[] =
1095 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1096 /* nopl 0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_8
[] =
1098 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1099 /* nopw 0L(%[re]ax,%[re]ax,1) */
1100 static const char alt_9
[] =
1101 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1102 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1103 static const char alt_10
[] =
1104 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_11
[] =
1109 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_12
[] =
1116 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1120 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1121 static const char alt_long_13
[] =
1125 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1130 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1131 static const char alt_long_14
[] =
1136 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_long_15
[] =
1149 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1150 /* nopl 0(%[re]ax,%[re]ax,1)
1151 nopw 0(%[re]ax,%[re]ax,1) */
1152 static const char alt_short_11
[] =
1153 {0x0f,0x1f,0x44,0x00,0x00,
1154 0x66,0x0f,0x1f,0x44,0x00,0x00};
1155 /* nopw 0(%[re]ax,%[re]ax,1)
1156 nopw 0(%[re]ax,%[re]ax,1) */
1157 static const char alt_short_12
[] =
1158 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1159 0x66,0x0f,0x1f,0x44,0x00,0x00};
1160 /* nopw 0(%[re]ax,%[re]ax,1)
1162 static const char alt_short_13
[] =
1163 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1164 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1167 static const char alt_short_14
[] =
1168 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1169 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1171 nopl 0L(%[re]ax,%[re]ax,1) */
1172 static const char alt_short_15
[] =
1173 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1174 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1175 static const char *const alt_short_patt
[] = {
1176 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1177 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1178 alt_short_14
, alt_short_15
1180 static const char *const alt_long_patt
[] = {
1181 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1182 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1183 alt_long_14
, alt_long_15
1186 /* Only align for at least a positive non-zero boundary. */
1187 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1190 /* We need to decide which NOP sequence to use for 32bit and
1191 64bit. When -mtune= is used:
1193 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1194 PROCESSOR_GENERIC32, f32_patt will be used.
1195 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1196 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1197 PROCESSOR_GENERIC64, alt_long_patt will be used.
1198 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1199 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1202 When -mtune= isn't used, alt_long_patt will be used if
1203 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1206 When -march= or .arch is used, we can't use anything beyond
1207 cpu_arch_isa_flags. */
1209 if (flag_code
== CODE_16BIT
)
1213 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1215 /* Adjust jump offset. */
1216 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1219 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1220 f16_patt
[count
- 1], count
);
1224 const char *const *patt
= NULL
;
1226 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1228 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1229 switch (cpu_arch_tune
)
1231 case PROCESSOR_UNKNOWN
:
1232 /* We use cpu_arch_isa_flags to check if we SHOULD
1233 optimize with nops. */
1234 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1235 patt
= alt_long_patt
;
1239 case PROCESSOR_PENTIUM4
:
1240 case PROCESSOR_NOCONA
:
1241 case PROCESSOR_CORE
:
1242 case PROCESSOR_CORE2
:
1243 case PROCESSOR_COREI7
:
1244 case PROCESSOR_L1OM
:
1245 case PROCESSOR_K1OM
:
1246 case PROCESSOR_GENERIC64
:
1247 patt
= alt_long_patt
;
1250 case PROCESSOR_ATHLON
:
1252 case PROCESSOR_AMDFAM10
:
1255 patt
= alt_short_patt
;
1257 case PROCESSOR_I386
:
1258 case PROCESSOR_I486
:
1259 case PROCESSOR_PENTIUM
:
1260 case PROCESSOR_PENTIUMPRO
:
1261 case PROCESSOR_GENERIC32
:
1268 switch (fragP
->tc_frag_data
.tune
)
1270 case PROCESSOR_UNKNOWN
:
1271 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1272 PROCESSOR_UNKNOWN. */
1276 case PROCESSOR_I386
:
1277 case PROCESSOR_I486
:
1278 case PROCESSOR_PENTIUM
:
1280 case PROCESSOR_ATHLON
:
1282 case PROCESSOR_AMDFAM10
:
1285 case PROCESSOR_GENERIC32
:
1286 /* We use cpu_arch_isa_flags to check if we CAN optimize
1288 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1289 patt
= alt_short_patt
;
1293 case PROCESSOR_PENTIUMPRO
:
1294 case PROCESSOR_PENTIUM4
:
1295 case PROCESSOR_NOCONA
:
1296 case PROCESSOR_CORE
:
1297 case PROCESSOR_CORE2
:
1298 case PROCESSOR_COREI7
:
1299 case PROCESSOR_L1OM
:
1300 case PROCESSOR_K1OM
:
1301 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1302 patt
= alt_long_patt
;
1306 case PROCESSOR_GENERIC64
:
1307 patt
= alt_long_patt
;
1312 if (patt
== f32_patt
)
1314 /* If the padding is less than 15 bytes, we use the normal
1315 ones. Otherwise, we use a jump instruction and adjust
1319 /* For 64bit, the limit is 3 bytes. */
1320 if (flag_code
== CODE_64BIT
1321 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1326 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1327 patt
[count
- 1], count
);
1330 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1332 /* Adjust jump offset. */
1333 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1338 /* Maximum length of an instruction is 15 byte. If the
1339 padding is greater than 15 bytes and we don't use jump,
1340 we have to break it into smaller pieces. */
1341 int padding
= count
;
1342 while (padding
> 15)
1345 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1350 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1351 patt
[padding
- 1], padding
);
1354 fragP
->fr_var
= count
;
1358 operand_type_all_zero (const union i386_operand_type
*x
)
1360 switch (ARRAY_SIZE(x
->array
))
1369 return !x
->array
[0];
1376 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1378 switch (ARRAY_SIZE(x
->array
))
1393 operand_type_equal (const union i386_operand_type
*x
,
1394 const union i386_operand_type
*y
)
1396 switch (ARRAY_SIZE(x
->array
))
1399 if (x
->array
[2] != y
->array
[2])
1402 if (x
->array
[1] != y
->array
[1])
1405 return x
->array
[0] == y
->array
[0];
1413 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1415 switch (ARRAY_SIZE(x
->array
))
1424 return !x
->array
[0];
1431 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1433 switch (ARRAY_SIZE(x
->array
))
1448 cpu_flags_equal (const union i386_cpu_flags
*x
,
1449 const union i386_cpu_flags
*y
)
1451 switch (ARRAY_SIZE(x
->array
))
1454 if (x
->array
[2] != y
->array
[2])
1457 if (x
->array
[1] != y
->array
[1])
1460 return x
->array
[0] == y
->array
[0];
1468 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1470 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1471 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1474 static INLINE i386_cpu_flags
1475 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1477 switch (ARRAY_SIZE (x
.array
))
1480 x
.array
[2] &= y
.array
[2];
1482 x
.array
[1] &= y
.array
[1];
1484 x
.array
[0] &= y
.array
[0];
1492 static INLINE i386_cpu_flags
1493 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1495 switch (ARRAY_SIZE (x
.array
))
1498 x
.array
[2] |= y
.array
[2];
1500 x
.array
[1] |= y
.array
[1];
1502 x
.array
[0] |= y
.array
[0];
1510 static INLINE i386_cpu_flags
1511 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1513 switch (ARRAY_SIZE (x
.array
))
1516 x
.array
[2] &= ~y
.array
[2];
1518 x
.array
[1] &= ~y
.array
[1];
1520 x
.array
[0] &= ~y
.array
[0];
1528 #define CPU_FLAGS_ARCH_MATCH 0x1
1529 #define CPU_FLAGS_64BIT_MATCH 0x2
1530 #define CPU_FLAGS_AES_MATCH 0x4
1531 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1532 #define CPU_FLAGS_AVX_MATCH 0x10
1534 #define CPU_FLAGS_32BIT_MATCH \
1535 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1536 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1537 #define CPU_FLAGS_PERFECT_MATCH \
1538 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1540 /* Return CPU flags match bits. */
1543 cpu_flags_match (const insn_template
*t
)
1545 i386_cpu_flags x
= t
->cpu_flags
;
1546 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1548 x
.bitfield
.cpu64
= 0;
1549 x
.bitfield
.cpuno64
= 0;
1551 if (cpu_flags_all_zero (&x
))
1553 /* This instruction is available on all archs. */
1554 match
|= CPU_FLAGS_32BIT_MATCH
;
1558 /* This instruction is available only on some archs. */
1559 i386_cpu_flags cpu
= cpu_arch_flags
;
1561 cpu
.bitfield
.cpu64
= 0;
1562 cpu
.bitfield
.cpuno64
= 0;
1563 cpu
= cpu_flags_and (x
, cpu
);
1564 if (!cpu_flags_all_zero (&cpu
))
1566 if (x
.bitfield
.cpuavx
)
1568 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1569 if (cpu
.bitfield
.cpuavx
)
1571 /* Check SSE2AVX. */
1572 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1574 match
|= (CPU_FLAGS_ARCH_MATCH
1575 | CPU_FLAGS_AVX_MATCH
);
1577 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1578 match
|= CPU_FLAGS_AES_MATCH
;
1580 if (!x
.bitfield
.cpupclmul
1581 || cpu
.bitfield
.cpupclmul
)
1582 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1586 match
|= CPU_FLAGS_ARCH_MATCH
;
1589 match
|= CPU_FLAGS_32BIT_MATCH
;
1595 static INLINE i386_operand_type
1596 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1598 switch (ARRAY_SIZE (x
.array
))
1601 x
.array
[2] &= y
.array
[2];
1603 x
.array
[1] &= y
.array
[1];
1605 x
.array
[0] &= y
.array
[0];
1613 static INLINE i386_operand_type
1614 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1616 switch (ARRAY_SIZE (x
.array
))
1619 x
.array
[2] |= y
.array
[2];
1621 x
.array
[1] |= y
.array
[1];
1623 x
.array
[0] |= y
.array
[0];
1631 static INLINE i386_operand_type
1632 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1634 switch (ARRAY_SIZE (x
.array
))
1637 x
.array
[2] ^= y
.array
[2];
1639 x
.array
[1] ^= y
.array
[1];
1641 x
.array
[0] ^= y
.array
[0];
1649 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1650 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1651 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1652 static const i386_operand_type inoutportreg
1653 = OPERAND_TYPE_INOUTPORTREG
;
1654 static const i386_operand_type reg16_inoutportreg
1655 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1656 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1657 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1658 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1659 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1660 static const i386_operand_type anydisp
1661 = OPERAND_TYPE_ANYDISP
;
1662 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1663 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1664 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1665 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1666 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1667 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1668 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1669 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1670 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1671 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1672 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1673 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1674 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1675 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1686 operand_type_check (i386_operand_type t
, enum operand_type c
)
1691 return (t
.bitfield
.reg8
1694 || t
.bitfield
.reg64
);
1697 return (t
.bitfield
.imm8
1701 || t
.bitfield
.imm32s
1702 || t
.bitfield
.imm64
);
1705 return (t
.bitfield
.disp8
1706 || t
.bitfield
.disp16
1707 || t
.bitfield
.disp32
1708 || t
.bitfield
.disp32s
1709 || t
.bitfield
.disp64
);
1712 return (t
.bitfield
.disp8
1713 || t
.bitfield
.disp16
1714 || t
.bitfield
.disp32
1715 || t
.bitfield
.disp32s
1716 || t
.bitfield
.disp64
1717 || t
.bitfield
.baseindex
);
1726 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1727 operand J for instruction template T. */
1730 match_reg_size (const insn_template
*t
, unsigned int j
)
1732 return !((i
.types
[j
].bitfield
.byte
1733 && !t
->operand_types
[j
].bitfield
.byte
)
1734 || (i
.types
[j
].bitfield
.word
1735 && !t
->operand_types
[j
].bitfield
.word
)
1736 || (i
.types
[j
].bitfield
.dword
1737 && !t
->operand_types
[j
].bitfield
.dword
)
1738 || (i
.types
[j
].bitfield
.qword
1739 && !t
->operand_types
[j
].bitfield
.qword
));
1742 /* Return 1 if there is no conflict in any size on operand J for
1743 instruction template T. */
1746 match_mem_size (const insn_template
*t
, unsigned int j
)
1748 return (match_reg_size (t
, j
)
1749 && !((i
.types
[j
].bitfield
.unspecified
1750 && !t
->operand_types
[j
].bitfield
.unspecified
)
1751 || (i
.types
[j
].bitfield
.fword
1752 && !t
->operand_types
[j
].bitfield
.fword
)
1753 || (i
.types
[j
].bitfield
.tbyte
1754 && !t
->operand_types
[j
].bitfield
.tbyte
)
1755 || (i
.types
[j
].bitfield
.xmmword
1756 && !t
->operand_types
[j
].bitfield
.xmmword
)
1757 || (i
.types
[j
].bitfield
.ymmword
1758 && !t
->operand_types
[j
].bitfield
.ymmword
)
1759 || (i
.types
[j
].bitfield
.zmmword
1760 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1763 /* Return 1 if there is no size conflict on any operands for
1764 instruction template T. */
1767 operand_size_match (const insn_template
*t
)
1772 /* Don't check jump instructions. */
1773 if (t
->opcode_modifier
.jump
1774 || t
->opcode_modifier
.jumpbyte
1775 || t
->opcode_modifier
.jumpdword
1776 || t
->opcode_modifier
.jumpintersegment
)
1779 /* Check memory and accumulator operand size. */
1780 for (j
= 0; j
< i
.operands
; j
++)
1782 if (t
->operand_types
[j
].bitfield
.anysize
)
1785 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1791 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1800 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1803 i
.error
= operand_size_mismatch
;
1807 /* Check reverse. */
1808 gas_assert (i
.operands
== 2);
1811 for (j
= 0; j
< 2; j
++)
1813 if (t
->operand_types
[j
].bitfield
.acc
1814 && !match_reg_size (t
, j
? 0 : 1))
1817 if (i
.types
[j
].bitfield
.mem
1818 && !match_mem_size (t
, j
? 0 : 1))
1826 operand_type_match (i386_operand_type overlap
,
1827 i386_operand_type given
)
1829 i386_operand_type temp
= overlap
;
1831 temp
.bitfield
.jumpabsolute
= 0;
1832 temp
.bitfield
.unspecified
= 0;
1833 temp
.bitfield
.byte
= 0;
1834 temp
.bitfield
.word
= 0;
1835 temp
.bitfield
.dword
= 0;
1836 temp
.bitfield
.fword
= 0;
1837 temp
.bitfield
.qword
= 0;
1838 temp
.bitfield
.tbyte
= 0;
1839 temp
.bitfield
.xmmword
= 0;
1840 temp
.bitfield
.ymmword
= 0;
1841 temp
.bitfield
.zmmword
= 0;
1842 if (operand_type_all_zero (&temp
))
1845 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1846 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1850 i
.error
= operand_type_mismatch
;
1854 /* If given types g0 and g1 are registers they must be of the same type
1855 unless the expected operand type register overlap is null.
1856 Note that Acc in a template matches every size of reg. */
1859 operand_type_register_match (i386_operand_type m0
,
1860 i386_operand_type g0
,
1861 i386_operand_type t0
,
1862 i386_operand_type m1
,
1863 i386_operand_type g1
,
1864 i386_operand_type t1
)
1866 if (!operand_type_check (g0
, reg
))
1869 if (!operand_type_check (g1
, reg
))
1872 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1873 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1874 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1875 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1878 if (m0
.bitfield
.acc
)
1880 t0
.bitfield
.reg8
= 1;
1881 t0
.bitfield
.reg16
= 1;
1882 t0
.bitfield
.reg32
= 1;
1883 t0
.bitfield
.reg64
= 1;
1886 if (m1
.bitfield
.acc
)
1888 t1
.bitfield
.reg8
= 1;
1889 t1
.bitfield
.reg16
= 1;
1890 t1
.bitfield
.reg32
= 1;
1891 t1
.bitfield
.reg64
= 1;
1894 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1895 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1896 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1897 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1900 i
.error
= register_type_mismatch
;
1905 static INLINE
unsigned int
1906 register_number (const reg_entry
*r
)
1908 unsigned int nr
= r
->reg_num
;
1910 if (r
->reg_flags
& RegRex
)
1916 static INLINE
unsigned int
1917 mode_from_disp_size (i386_operand_type t
)
1919 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1921 else if (t
.bitfield
.disp16
1922 || t
.bitfield
.disp32
1923 || t
.bitfield
.disp32s
)
1930 fits_in_signed_byte (offsetT num
)
1932 return (num
>= -128) && (num
<= 127);
1936 fits_in_unsigned_byte (offsetT num
)
1938 return (num
& 0xff) == num
;
1942 fits_in_unsigned_word (offsetT num
)
1944 return (num
& 0xffff) == num
;
1948 fits_in_signed_word (offsetT num
)
1950 return (-32768 <= num
) && (num
<= 32767);
1954 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1959 return (!(((offsetT
) -1 << 31) & num
)
1960 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1962 } /* fits_in_signed_long() */
1965 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1970 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1972 } /* fits_in_unsigned_long() */
1975 fits_in_vec_disp8 (offsetT num
)
1977 int shift
= i
.memshift
;
1983 mask
= (1 << shift
) - 1;
1985 /* Return 0 if NUM isn't properly aligned. */
1989 /* Check if NUM will fit in 8bit after shift. */
1990 return fits_in_signed_byte (num
>> shift
);
1994 fits_in_imm4 (offsetT num
)
1996 return (num
& 0xf) == num
;
1999 static i386_operand_type
2000 smallest_imm_type (offsetT num
)
2002 i386_operand_type t
;
2004 operand_type_set (&t
, 0);
2005 t
.bitfield
.imm64
= 1;
2007 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2009 /* This code is disabled on the 486 because all the Imm1 forms
2010 in the opcode table are slower on the i486. They're the
2011 versions with the implicitly specified single-position
2012 displacement, which has another syntax if you really want to
2014 t
.bitfield
.imm1
= 1;
2015 t
.bitfield
.imm8
= 1;
2016 t
.bitfield
.imm8s
= 1;
2017 t
.bitfield
.imm16
= 1;
2018 t
.bitfield
.imm32
= 1;
2019 t
.bitfield
.imm32s
= 1;
2021 else if (fits_in_signed_byte (num
))
2023 t
.bitfield
.imm8
= 1;
2024 t
.bitfield
.imm8s
= 1;
2025 t
.bitfield
.imm16
= 1;
2026 t
.bitfield
.imm32
= 1;
2027 t
.bitfield
.imm32s
= 1;
2029 else if (fits_in_unsigned_byte (num
))
2031 t
.bitfield
.imm8
= 1;
2032 t
.bitfield
.imm16
= 1;
2033 t
.bitfield
.imm32
= 1;
2034 t
.bitfield
.imm32s
= 1;
2036 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2038 t
.bitfield
.imm16
= 1;
2039 t
.bitfield
.imm32
= 1;
2040 t
.bitfield
.imm32s
= 1;
2042 else if (fits_in_signed_long (num
))
2044 t
.bitfield
.imm32
= 1;
2045 t
.bitfield
.imm32s
= 1;
2047 else if (fits_in_unsigned_long (num
))
2048 t
.bitfield
.imm32
= 1;
2054 offset_in_range (offsetT val
, int size
)
2060 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2061 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2062 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2064 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2070 /* If BFD64, sign extend val for 32bit address mode. */
2071 if (flag_code
!= CODE_64BIT
2072 || i
.prefix
[ADDR_PREFIX
])
2073 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2074 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2077 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2079 char buf1
[40], buf2
[40];
2081 sprint_value (buf1
, val
);
2082 sprint_value (buf2
, val
& mask
);
2083 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2097 a. PREFIX_EXIST if attempting to add a prefix where one from the
2098 same class already exists.
2099 b. PREFIX_LOCK if lock prefix is added.
2100 c. PREFIX_REP if rep/repne prefix is added.
2101 d. PREFIX_OTHER if other prefix is added.
2104 static enum PREFIX_GROUP
2105 add_prefix (unsigned int prefix
)
2107 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2110 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2111 && flag_code
== CODE_64BIT
)
2113 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2114 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2115 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2126 case CS_PREFIX_OPCODE
:
2127 case DS_PREFIX_OPCODE
:
2128 case ES_PREFIX_OPCODE
:
2129 case FS_PREFIX_OPCODE
:
2130 case GS_PREFIX_OPCODE
:
2131 case SS_PREFIX_OPCODE
:
2135 case REPNE_PREFIX_OPCODE
:
2136 case REPE_PREFIX_OPCODE
:
2141 case LOCK_PREFIX_OPCODE
:
2150 case ADDR_PREFIX_OPCODE
:
2154 case DATA_PREFIX_OPCODE
:
2158 if (i
.prefix
[q
] != 0)
2166 i
.prefix
[q
] |= prefix
;
2169 as_bad (_("same type of prefix used twice"));
2175 update_code_flag (int value
, int check
)
2177 PRINTF_LIKE ((*as_error
));
2179 flag_code
= (enum flag_code
) value
;
2180 if (flag_code
== CODE_64BIT
)
2182 cpu_arch_flags
.bitfield
.cpu64
= 1;
2183 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2187 cpu_arch_flags
.bitfield
.cpu64
= 0;
2188 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2190 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2193 as_error
= as_fatal
;
2196 (*as_error
) (_("64bit mode not supported on `%s'."),
2197 cpu_arch_name
? cpu_arch_name
: default_arch
);
2199 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2202 as_error
= as_fatal
;
2205 (*as_error
) (_("32bit mode not supported on `%s'."),
2206 cpu_arch_name
? cpu_arch_name
: default_arch
);
2208 stackop_size
= '\0';
2212 set_code_flag (int value
)
2214 update_code_flag (value
, 0);
2218 set_16bit_gcc_code_flag (int new_code_flag
)
2220 flag_code
= (enum flag_code
) new_code_flag
;
2221 if (flag_code
!= CODE_16BIT
)
2223 cpu_arch_flags
.bitfield
.cpu64
= 0;
2224 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2225 stackop_size
= LONG_MNEM_SUFFIX
;
2229 set_intel_syntax (int syntax_flag
)
2231 /* Find out if register prefixing is specified. */
2232 int ask_naked_reg
= 0;
2235 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2237 char *string
= input_line_pointer
;
2238 int e
= get_symbol_end ();
2240 if (strcmp (string
, "prefix") == 0)
2242 else if (strcmp (string
, "noprefix") == 0)
2245 as_bad (_("bad argument to syntax directive."));
2246 *input_line_pointer
= e
;
2248 demand_empty_rest_of_line ();
2250 intel_syntax
= syntax_flag
;
2252 if (ask_naked_reg
== 0)
2253 allow_naked_reg
= (intel_syntax
2254 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2256 allow_naked_reg
= (ask_naked_reg
< 0);
2258 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2260 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2261 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2262 register_prefix
= allow_naked_reg
? "" : "%";
2266 set_intel_mnemonic (int mnemonic_flag
)
2268 intel_mnemonic
= mnemonic_flag
;
2272 set_allow_index_reg (int flag
)
2274 allow_index_reg
= flag
;
2278 set_check (int what
)
2280 enum check_kind
*kind
;
2285 kind
= &operand_check
;
2296 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2298 char *string
= input_line_pointer
;
2299 int e
= get_symbol_end ();
2301 if (strcmp (string
, "none") == 0)
2303 else if (strcmp (string
, "warning") == 0)
2304 *kind
= check_warning
;
2305 else if (strcmp (string
, "error") == 0)
2306 *kind
= check_error
;
2308 as_bad (_("bad argument to %s_check directive."), str
);
2309 *input_line_pointer
= e
;
2312 as_bad (_("missing argument for %s_check directive"), str
);
2314 demand_empty_rest_of_line ();
2318 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2319 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2321 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2322 static const char *arch
;
2324 /* Intel LIOM is only supported on ELF. */
2330 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2331 use default_arch. */
2332 arch
= cpu_arch_name
;
2334 arch
= default_arch
;
2337 /* If we are targeting Intel L1OM, we must enable it. */
2338 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2339 || new_flag
.bitfield
.cpul1om
)
2342 /* If we are targeting Intel K1OM, we must enable it. */
2343 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2344 || new_flag
.bitfield
.cpuk1om
)
2347 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2352 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2356 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2358 char *string
= input_line_pointer
;
2359 int e
= get_symbol_end ();
2361 i386_cpu_flags flags
;
2363 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2365 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2367 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2371 cpu_arch_name
= cpu_arch
[j
].name
;
2372 cpu_sub_arch_name
= NULL
;
2373 cpu_arch_flags
= cpu_arch
[j
].flags
;
2374 if (flag_code
== CODE_64BIT
)
2376 cpu_arch_flags
.bitfield
.cpu64
= 1;
2377 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2381 cpu_arch_flags
.bitfield
.cpu64
= 0;
2382 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2384 cpu_arch_isa
= cpu_arch
[j
].type
;
2385 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2386 if (!cpu_arch_tune_set
)
2388 cpu_arch_tune
= cpu_arch_isa
;
2389 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2394 if (!cpu_arch
[j
].negated
)
2395 flags
= cpu_flags_or (cpu_arch_flags
,
2398 flags
= cpu_flags_and_not (cpu_arch_flags
,
2400 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2402 if (cpu_sub_arch_name
)
2404 char *name
= cpu_sub_arch_name
;
2405 cpu_sub_arch_name
= concat (name
,
2407 (const char *) NULL
);
2411 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2412 cpu_arch_flags
= flags
;
2413 cpu_arch_isa_flags
= flags
;
2415 *input_line_pointer
= e
;
2416 demand_empty_rest_of_line ();
2420 if (j
>= ARRAY_SIZE (cpu_arch
))
2421 as_bad (_("no such architecture: `%s'"), string
);
2423 *input_line_pointer
= e
;
2426 as_bad (_("missing cpu architecture"));
2428 no_cond_jump_promotion
= 0;
2429 if (*input_line_pointer
== ','
2430 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2432 char *string
= ++input_line_pointer
;
2433 int e
= get_symbol_end ();
2435 if (strcmp (string
, "nojumps") == 0)
2436 no_cond_jump_promotion
= 1;
2437 else if (strcmp (string
, "jumps") == 0)
2440 as_bad (_("no such architecture modifier: `%s'"), string
);
2442 *input_line_pointer
= e
;
2445 demand_empty_rest_of_line ();
2448 enum bfd_architecture
2451 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2453 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2454 || flag_code
!= CODE_64BIT
)
2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_arch_l1om
;
2458 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2460 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2461 || flag_code
!= CODE_64BIT
)
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_arch_k1om
;
2466 return bfd_arch_i386
;
2472 if (!strncmp (default_arch
, "x86_64", 6))
2474 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2476 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2477 || default_arch
[6] != '\0')
2478 as_fatal (_("Intel L1OM is 64bit ELF only"));
2479 return bfd_mach_l1om
;
2481 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2483 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2484 || default_arch
[6] != '\0')
2485 as_fatal (_("Intel K1OM is 64bit ELF only"));
2486 return bfd_mach_k1om
;
2488 else if (default_arch
[6] == '\0')
2489 return bfd_mach_x86_64
;
2491 return bfd_mach_x64_32
;
2493 else if (!strcmp (default_arch
, "i386"))
2494 return bfd_mach_i386_i386
;
2496 as_fatal (_("unknown architecture"));
2502 const char *hash_err
;
2504 /* Initialize op_hash hash table. */
2505 op_hash
= hash_new ();
2508 const insn_template
*optab
;
2509 templates
*core_optab
;
2511 /* Setup for loop. */
2513 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2514 core_optab
->start
= optab
;
2519 if (optab
->name
== NULL
2520 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2522 /* different name --> ship out current template list;
2523 add to hash table; & begin anew. */
2524 core_optab
->end
= optab
;
2525 hash_err
= hash_insert (op_hash
,
2527 (void *) core_optab
);
2530 as_fatal (_("can't hash %s: %s"),
2534 if (optab
->name
== NULL
)
2536 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2537 core_optab
->start
= optab
;
2542 /* Initialize reg_hash hash table. */
2543 reg_hash
= hash_new ();
2545 const reg_entry
*regtab
;
2546 unsigned int regtab_size
= i386_regtab_size
;
2548 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2550 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2552 as_fatal (_("can't hash %s: %s"),
2558 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2563 for (c
= 0; c
< 256; c
++)
2568 mnemonic_chars
[c
] = c
;
2569 register_chars
[c
] = c
;
2570 operand_chars
[c
] = c
;
2572 else if (ISLOWER (c
))
2574 mnemonic_chars
[c
] = c
;
2575 register_chars
[c
] = c
;
2576 operand_chars
[c
] = c
;
2578 else if (ISUPPER (c
))
2580 mnemonic_chars
[c
] = TOLOWER (c
);
2581 register_chars
[c
] = mnemonic_chars
[c
];
2582 operand_chars
[c
] = c
;
2584 else if (c
== '{' || c
== '}')
2585 operand_chars
[c
] = c
;
2587 if (ISALPHA (c
) || ISDIGIT (c
))
2588 identifier_chars
[c
] = c
;
2591 identifier_chars
[c
] = c
;
2592 operand_chars
[c
] = c
;
2597 identifier_chars
['@'] = '@';
2600 identifier_chars
['?'] = '?';
2601 operand_chars
['?'] = '?';
2603 digit_chars
['-'] = '-';
2604 mnemonic_chars
['_'] = '_';
2605 mnemonic_chars
['-'] = '-';
2606 mnemonic_chars
['.'] = '.';
2607 identifier_chars
['_'] = '_';
2608 identifier_chars
['.'] = '.';
2610 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2611 operand_chars
[(unsigned char) *p
] = *p
;
2614 if (flag_code
== CODE_64BIT
)
2616 #if defined (OBJ_COFF) && defined (TE_PE)
2617 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2620 x86_dwarf2_return_column
= 16;
2622 x86_cie_data_alignment
= -8;
2626 x86_dwarf2_return_column
= 8;
2627 x86_cie_data_alignment
= -4;
2632 i386_print_statistics (FILE *file
)
2634 hash_print_statistics (file
, "i386 opcode", op_hash
);
2635 hash_print_statistics (file
, "i386 register", reg_hash
);
2640 /* Debugging routines for md_assemble. */
2641 static void pte (insn_template
*);
2642 static void pt (i386_operand_type
);
2643 static void pe (expressionS
*);
2644 static void ps (symbolS
*);
2647 pi (char *line
, i386_insn
*x
)
2651 fprintf (stdout
, "%s: template ", line
);
2653 fprintf (stdout
, " address: base %s index %s scale %x\n",
2654 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2655 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2656 x
->log2_scale_factor
);
2657 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2658 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2659 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2660 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2661 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2662 (x
->rex
& REX_W
) != 0,
2663 (x
->rex
& REX_R
) != 0,
2664 (x
->rex
& REX_X
) != 0,
2665 (x
->rex
& REX_B
) != 0);
2666 for (j
= 0; j
< x
->operands
; j
++)
2668 fprintf (stdout
, " #%d: ", j
+ 1);
2670 fprintf (stdout
, "\n");
2671 if (x
->types
[j
].bitfield
.reg8
2672 || x
->types
[j
].bitfield
.reg16
2673 || x
->types
[j
].bitfield
.reg32
2674 || x
->types
[j
].bitfield
.reg64
2675 || x
->types
[j
].bitfield
.regmmx
2676 || x
->types
[j
].bitfield
.regxmm
2677 || x
->types
[j
].bitfield
.regymm
2678 || x
->types
[j
].bitfield
.regzmm
2679 || x
->types
[j
].bitfield
.sreg2
2680 || x
->types
[j
].bitfield
.sreg3
2681 || x
->types
[j
].bitfield
.control
2682 || x
->types
[j
].bitfield
.debug
2683 || x
->types
[j
].bitfield
.test
)
2684 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2685 if (operand_type_check (x
->types
[j
], imm
))
2687 if (operand_type_check (x
->types
[j
], disp
))
2688 pe (x
->op
[j
].disps
);
2693 pte (insn_template
*t
)
2696 fprintf (stdout
, " %d operands ", t
->operands
);
2697 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2698 if (t
->extension_opcode
!= None
)
2699 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2700 if (t
->opcode_modifier
.d
)
2701 fprintf (stdout
, "D");
2702 if (t
->opcode_modifier
.w
)
2703 fprintf (stdout
, "W");
2704 fprintf (stdout
, "\n");
2705 for (j
= 0; j
< t
->operands
; j
++)
2707 fprintf (stdout
, " #%d type ", j
+ 1);
2708 pt (t
->operand_types
[j
]);
2709 fprintf (stdout
, "\n");
2716 fprintf (stdout
, " operation %d\n", e
->X_op
);
2717 fprintf (stdout
, " add_number %ld (%lx)\n",
2718 (long) e
->X_add_number
, (long) e
->X_add_number
);
2719 if (e
->X_add_symbol
)
2721 fprintf (stdout
, " add_symbol ");
2722 ps (e
->X_add_symbol
);
2723 fprintf (stdout
, "\n");
2727 fprintf (stdout
, " op_symbol ");
2728 ps (e
->X_op_symbol
);
2729 fprintf (stdout
, "\n");
2736 fprintf (stdout
, "%s type %s%s",
2738 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2739 segment_name (S_GET_SEGMENT (s
)));
2742 static struct type_name
2744 i386_operand_type mask
;
2747 const type_names
[] =
2749 { OPERAND_TYPE_REG8
, "r8" },
2750 { OPERAND_TYPE_REG16
, "r16" },
2751 { OPERAND_TYPE_REG32
, "r32" },
2752 { OPERAND_TYPE_REG64
, "r64" },
2753 { OPERAND_TYPE_IMM8
, "i8" },
2754 { OPERAND_TYPE_IMM8
, "i8s" },
2755 { OPERAND_TYPE_IMM16
, "i16" },
2756 { OPERAND_TYPE_IMM32
, "i32" },
2757 { OPERAND_TYPE_IMM32S
, "i32s" },
2758 { OPERAND_TYPE_IMM64
, "i64" },
2759 { OPERAND_TYPE_IMM1
, "i1" },
2760 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2761 { OPERAND_TYPE_DISP8
, "d8" },
2762 { OPERAND_TYPE_DISP16
, "d16" },
2763 { OPERAND_TYPE_DISP32
, "d32" },
2764 { OPERAND_TYPE_DISP32S
, "d32s" },
2765 { OPERAND_TYPE_DISP64
, "d64" },
2766 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2767 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2768 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2769 { OPERAND_TYPE_CONTROL
, "control reg" },
2770 { OPERAND_TYPE_TEST
, "test reg" },
2771 { OPERAND_TYPE_DEBUG
, "debug reg" },
2772 { OPERAND_TYPE_FLOATREG
, "FReg" },
2773 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2774 { OPERAND_TYPE_SREG2
, "SReg2" },
2775 { OPERAND_TYPE_SREG3
, "SReg3" },
2776 { OPERAND_TYPE_ACC
, "Acc" },
2777 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2778 { OPERAND_TYPE_REGMMX
, "rMMX" },
2779 { OPERAND_TYPE_REGXMM
, "rXMM" },
2780 { OPERAND_TYPE_REGYMM
, "rYMM" },
2781 { OPERAND_TYPE_REGZMM
, "rZMM" },
2782 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2783 { OPERAND_TYPE_ESSEG
, "es" },
2787 pt (i386_operand_type t
)
2790 i386_operand_type a
;
2792 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2794 a
= operand_type_and (t
, type_names
[j
].mask
);
2795 if (!operand_type_all_zero (&a
))
2796 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2801 #endif /* DEBUG386 */
2803 static bfd_reloc_code_real_type
2804 reloc (unsigned int size
,
2808 bfd_reloc_code_real_type other
)
2810 if (other
!= NO_RELOC
)
2812 reloc_howto_type
*rel
;
2817 case BFD_RELOC_X86_64_GOT32
:
2818 return BFD_RELOC_X86_64_GOT64
;
2820 case BFD_RELOC_X86_64_PLTOFF64
:
2821 return BFD_RELOC_X86_64_PLTOFF64
;
2823 case BFD_RELOC_X86_64_GOTPC32
:
2824 other
= BFD_RELOC_X86_64_GOTPC64
;
2826 case BFD_RELOC_X86_64_GOTPCREL
:
2827 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2829 case BFD_RELOC_X86_64_TPOFF32
:
2830 other
= BFD_RELOC_X86_64_TPOFF64
;
2832 case BFD_RELOC_X86_64_DTPOFF32
:
2833 other
= BFD_RELOC_X86_64_DTPOFF64
;
2839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2840 if (other
== BFD_RELOC_SIZE32
)
2843 return BFD_RELOC_SIZE64
;
2845 as_bad (_("there are no pc-relative size relocations"));
2849 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2850 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2853 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2855 as_bad (_("unknown relocation (%u)"), other
);
2856 else if (size
!= bfd_get_reloc_size (rel
))
2857 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2858 bfd_get_reloc_size (rel
),
2860 else if (pcrel
&& !rel
->pc_relative
)
2861 as_bad (_("non-pc-relative relocation for pc-relative field"));
2862 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2864 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2866 as_bad (_("relocated field and relocation type differ in signedness"));
2875 as_bad (_("there are no unsigned pc-relative relocations"));
2878 case 1: return BFD_RELOC_8_PCREL
;
2879 case 2: return BFD_RELOC_16_PCREL
;
2880 case 4: return (bnd_prefix
&& object_64bit
2881 ? BFD_RELOC_X86_64_PC32_BND
2882 : BFD_RELOC_32_PCREL
);
2883 case 8: return BFD_RELOC_64_PCREL
;
2885 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2892 case 4: return BFD_RELOC_X86_64_32S
;
2897 case 1: return BFD_RELOC_8
;
2898 case 2: return BFD_RELOC_16
;
2899 case 4: return BFD_RELOC_32
;
2900 case 8: return BFD_RELOC_64
;
2902 as_bad (_("cannot do %s %u byte relocation"),
2903 sign
> 0 ? "signed" : "unsigned", size
);
2909 /* Here we decide which fixups can be adjusted to make them relative to
2910 the beginning of the section instead of the symbol. Basically we need
2911 to make sure that the dynamic relocations are done correctly, so in
2912 some cases we force the original symbol to be used. */
2915 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2921 /* Don't adjust pc-relative references to merge sections in 64-bit
2923 if (use_rela_relocations
2924 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2928 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2929 and changed later by validate_fix. */
2930 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2931 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2934 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2935 for size relocations. */
2936 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2937 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2938 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2939 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2940 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2944 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2945 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2946 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2947 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2948 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2949 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2950 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2963 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2964 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2965 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2972 intel_float_operand (const char *mnemonic
)
2974 /* Note that the value returned is meaningful only for opcodes with (memory)
2975 operands, hence the code here is free to improperly handle opcodes that
2976 have no operands (for better performance and smaller code). */
2978 if (mnemonic
[0] != 'f')
2979 return 0; /* non-math */
2981 switch (mnemonic
[1])
2983 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2984 the fs segment override prefix not currently handled because no
2985 call path can make opcodes without operands get here */
2987 return 2 /* integer op */;
2989 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2990 return 3; /* fldcw/fldenv */
2993 if (mnemonic
[2] != 'o' /* fnop */)
2994 return 3; /* non-waiting control op */
2997 if (mnemonic
[2] == 's')
2998 return 3; /* frstor/frstpm */
3001 if (mnemonic
[2] == 'a')
3002 return 3; /* fsave */
3003 if (mnemonic
[2] == 't')
3005 switch (mnemonic
[3])
3007 case 'c': /* fstcw */
3008 case 'd': /* fstdw */
3009 case 'e': /* fstenv */
3010 case 's': /* fsts[gw] */
3016 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3017 return 0; /* fxsave/fxrstor are not really math ops */
3024 /* Build the VEX prefix. */
3027 build_vex_prefix (const insn_template
*t
)
3029 unsigned int register_specifier
;
3030 unsigned int implied_prefix
;
3031 unsigned int vector_length
;
3033 /* Check register specifier. */
3034 if (i
.vex
.register_specifier
)
3036 register_specifier
=
3037 ~register_number (i
.vex
.register_specifier
) & 0xf;
3038 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3041 register_specifier
= 0xf;
3043 /* Use 2-byte VEX prefix by swappping destination and source
3046 && i
.operands
== i
.reg_operands
3047 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3048 && i
.tm
.opcode_modifier
.s
3051 unsigned int xchg
= i
.operands
- 1;
3052 union i386_op temp_op
;
3053 i386_operand_type temp_type
;
3055 temp_type
= i
.types
[xchg
];
3056 i
.types
[xchg
] = i
.types
[0];
3057 i
.types
[0] = temp_type
;
3058 temp_op
= i
.op
[xchg
];
3059 i
.op
[xchg
] = i
.op
[0];
3062 gas_assert (i
.rm
.mode
== 3);
3066 i
.rm
.regmem
= i
.rm
.reg
;
3069 /* Use the next insn. */
3073 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3074 vector_length
= avxscalar
;
3076 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3078 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3083 case DATA_PREFIX_OPCODE
:
3086 case REPE_PREFIX_OPCODE
:
3089 case REPNE_PREFIX_OPCODE
:
3096 /* Use 2-byte VEX prefix if possible. */
3097 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3098 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3099 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3101 /* 2-byte VEX prefix. */
3105 i
.vex
.bytes
[0] = 0xc5;
3107 /* Check the REX.R bit. */
3108 r
= (i
.rex
& REX_R
) ? 0 : 1;
3109 i
.vex
.bytes
[1] = (r
<< 7
3110 | register_specifier
<< 3
3111 | vector_length
<< 2
3116 /* 3-byte VEX prefix. */
3121 switch (i
.tm
.opcode_modifier
.vexopcode
)
3125 i
.vex
.bytes
[0] = 0xc4;
3129 i
.vex
.bytes
[0] = 0xc4;
3133 i
.vex
.bytes
[0] = 0xc4;
3137 i
.vex
.bytes
[0] = 0x8f;
3141 i
.vex
.bytes
[0] = 0x8f;
3145 i
.vex
.bytes
[0] = 0x8f;
3151 /* The high 3 bits of the second VEX byte are 1's compliment
3152 of RXB bits from REX. */
3153 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3155 /* Check the REX.W bit. */
3156 w
= (i
.rex
& REX_W
) ? 1 : 0;
3157 if (i
.tm
.opcode_modifier
.vexw
)
3162 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3166 i
.vex
.bytes
[2] = (w
<< 7
3167 | register_specifier
<< 3
3168 | vector_length
<< 2
3173 /* Build the EVEX prefix. */
3176 build_evex_prefix (void)
3178 unsigned int register_specifier
;
3179 unsigned int implied_prefix
;
3181 rex_byte vrex_used
= 0;
3183 /* Check register specifier. */
3184 if (i
.vex
.register_specifier
)
3186 gas_assert ((i
.vrex
& REX_X
) == 0);
3188 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3189 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3190 register_specifier
+= 8;
3191 /* The upper 16 registers are encoded in the fourth byte of the
3193 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3194 i
.vex
.bytes
[3] = 0x8;
3195 register_specifier
= ~register_specifier
& 0xf;
3199 register_specifier
= 0xf;
3201 /* Encode upper 16 vector index register in the fourth byte of
3203 if (!(i
.vrex
& REX_X
))
3204 i
.vex
.bytes
[3] = 0x8;
3209 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3214 case DATA_PREFIX_OPCODE
:
3217 case REPE_PREFIX_OPCODE
:
3220 case REPNE_PREFIX_OPCODE
:
3227 /* 4 byte EVEX prefix. */
3229 i
.vex
.bytes
[0] = 0x62;
3232 switch (i
.tm
.opcode_modifier
.vexopcode
)
3248 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3250 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3252 /* The fifth bit of the second EVEX byte is 1's compliment of the
3253 REX_R bit in VREX. */
3254 if (!(i
.vrex
& REX_R
))
3255 i
.vex
.bytes
[1] |= 0x10;
3259 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3261 /* When all operands are registers, the REX_X bit in REX is not
3262 used. We reuse it to encode the upper 16 registers, which is
3263 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3264 as 1's compliment. */
3265 if ((i
.vrex
& REX_B
))
3268 i
.vex
.bytes
[1] &= ~0x40;
3272 /* EVEX instructions shouldn't need the REX prefix. */
3273 i
.vrex
&= ~vrex_used
;
3274 gas_assert (i
.vrex
== 0);
3276 /* Check the REX.W bit. */
3277 w
= (i
.rex
& REX_W
) ? 1 : 0;
3278 if (i
.tm
.opcode_modifier
.vexw
)
3280 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3283 /* If w is not set it means we are dealing with WIG instruction. */
3286 if (evexwig
== evexw1
)
3290 /* Encode the U bit. */
3291 implied_prefix
|= 0x4;
3293 /* The third byte of the EVEX prefix. */
3294 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3296 /* The fourth byte of the EVEX prefix. */
3297 /* The zeroing-masking bit. */
3298 if (i
.mask
&& i
.mask
->zeroing
)
3299 i
.vex
.bytes
[3] |= 0x80;
3301 /* Don't always set the broadcast bit if there is no RC. */
3304 /* Encode the vector length. */
3305 unsigned int vec_length
;
3307 switch (i
.tm
.opcode_modifier
.evex
)
3309 case EVEXLIG
: /* LL' is ignored */
3310 vec_length
= evexlig
<< 5;
3313 vec_length
= 0 << 5;
3316 vec_length
= 1 << 5;
3319 vec_length
= 2 << 5;
3325 i
.vex
.bytes
[3] |= vec_length
;
3326 /* Encode the broadcast bit. */
3328 i
.vex
.bytes
[3] |= 0x10;
3332 if (i
.rounding
->type
!= saeonly
)
3333 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3335 i
.vex
.bytes
[3] |= 0x10;
3338 if (i
.mask
&& i
.mask
->mask
)
3339 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3343 process_immext (void)
3347 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3350 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3351 with an opcode suffix which is coded in the same place as an
3352 8-bit immediate field would be.
3353 Here we check those operands and remove them afterwards. */
3356 for (x
= 0; x
< i
.operands
; x
++)
3357 if (register_number (i
.op
[x
].regs
) != x
)
3358 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3359 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3365 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3366 which is coded in the same place as an 8-bit immediate field
3367 would be. Here we fake an 8-bit immediate operand from the
3368 opcode suffix stored in tm.extension_opcode.
3370 AVX instructions also use this encoding, for some of
3371 3 argument instructions. */
3373 gas_assert (i
.imm_operands
<= 1
3375 || ((i
.tm
.opcode_modifier
.vex
3376 || i
.tm
.opcode_modifier
.evex
)
3377 && i
.operands
<= 4)));
3379 exp
= &im_expressions
[i
.imm_operands
++];
3380 i
.op
[i
.operands
].imms
= exp
;
3381 i
.types
[i
.operands
] = imm8
;
3383 exp
->X_op
= O_constant
;
3384 exp
->X_add_number
= i
.tm
.extension_opcode
;
3385 i
.tm
.extension_opcode
= None
;
3392 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3397 as_bad (_("invalid instruction `%s' after `%s'"),
3398 i
.tm
.name
, i
.hle_prefix
);
3401 if (i
.prefix
[LOCK_PREFIX
])
3403 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3407 case HLEPrefixRelease
:
3408 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3410 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3414 if (i
.mem_operands
== 0
3415 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3417 as_bad (_("memory destination needed for instruction `%s'"
3418 " after `xrelease'"), i
.tm
.name
);
3425 /* This is the guts of the machine-dependent assembler. LINE points to a
3426 machine dependent instruction. This function is supposed to emit
3427 the frags/bytes it assembles to. */
3430 md_assemble (char *line
)
3433 char mnemonic
[MAX_MNEM_SIZE
];
3434 const insn_template
*t
;
3436 /* Initialize globals. */
3437 memset (&i
, '\0', sizeof (i
));
3438 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3439 i
.reloc
[j
] = NO_RELOC
;
3440 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3441 memset (im_expressions
, '\0', sizeof (im_expressions
));
3442 save_stack_p
= save_stack
;
3444 /* First parse an instruction mnemonic & call i386_operand for the operands.
3445 We assume that the scrubber has arranged it so that line[0] is the valid
3446 start of a (possibly prefixed) mnemonic. */
3448 line
= parse_insn (line
, mnemonic
);
3452 line
= parse_operands (line
, mnemonic
);
3457 /* Now we've parsed the mnemonic into a set of templates, and have the
3458 operands at hand. */
3460 /* All intel opcodes have reversed operands except for "bound" and
3461 "enter". We also don't reverse intersegment "jmp" and "call"
3462 instructions with 2 immediate operands so that the immediate segment
3463 precedes the offset, as it does when in AT&T mode. */
3466 && (strcmp (mnemonic
, "bound") != 0)
3467 && (strcmp (mnemonic
, "invlpga") != 0)
3468 && !(operand_type_check (i
.types
[0], imm
)
3469 && operand_type_check (i
.types
[1], imm
)))
3472 /* The order of the immediates should be reversed
3473 for 2 immediates extrq and insertq instructions */
3474 if (i
.imm_operands
== 2
3475 && (strcmp (mnemonic
, "extrq") == 0
3476 || strcmp (mnemonic
, "insertq") == 0))
3477 swap_2_operands (0, 1);
3482 /* Don't optimize displacement for movabs since it only takes 64bit
3485 && i
.disp_encoding
!= disp_encoding_32bit
3486 && (flag_code
!= CODE_64BIT
3487 || strcmp (mnemonic
, "movabs") != 0))
3490 /* Next, we find a template that matches the given insn,
3491 making sure the overlap of the given operands types is consistent
3492 with the template operand types. */
3494 if (!(t
= match_template ()))
3497 if (sse_check
!= check_none
3498 && !i
.tm
.opcode_modifier
.noavx
3499 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3500 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3501 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3502 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3503 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3504 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3506 (sse_check
== check_warning
3508 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3511 /* Zap movzx and movsx suffix. The suffix has been set from
3512 "word ptr" or "byte ptr" on the source operand in Intel syntax
3513 or extracted from mnemonic in AT&T syntax. But we'll use
3514 the destination register to choose the suffix for encoding. */
3515 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3517 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3518 there is no suffix, the default will be byte extension. */
3519 if (i
.reg_operands
!= 2
3522 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3527 if (i
.tm
.opcode_modifier
.fwait
)
3528 if (!add_prefix (FWAIT_OPCODE
))
3531 /* Check if REP prefix is OK. */
3532 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3534 as_bad (_("invalid instruction `%s' after `%s'"),
3535 i
.tm
.name
, i
.rep_prefix
);
3539 /* Check for lock without a lockable instruction. Destination operand
3540 must be memory unless it is xchg (0x86). */
3541 if (i
.prefix
[LOCK_PREFIX
]
3542 && (!i
.tm
.opcode_modifier
.islockable
3543 || i
.mem_operands
== 0
3544 || (i
.tm
.base_opcode
!= 0x86
3545 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3547 as_bad (_("expecting lockable instruction after `lock'"));
3551 /* Check if HLE prefix is OK. */
3552 if (i
.hle_prefix
&& !check_hle ())
3555 /* Check BND prefix. */
3556 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3557 as_bad (_("expecting valid branch instruction after `bnd'"));
3559 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3560 && flag_code
== CODE_64BIT
3561 && i
.prefix
[ADDR_PREFIX
])
3562 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3564 /* Insert BND prefix. */
3566 && i
.tm
.opcode_modifier
.bndprefixok
3567 && !i
.prefix
[BND_PREFIX
])
3568 add_prefix (BND_PREFIX_OPCODE
);
3570 /* Check string instruction segment overrides. */
3571 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3573 if (!check_string ())
3575 i
.disp_operands
= 0;
3578 if (!process_suffix ())
3581 /* Update operand types. */
3582 for (j
= 0; j
< i
.operands
; j
++)
3583 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3585 /* Make still unresolved immediate matches conform to size of immediate
3586 given in i.suffix. */
3587 if (!finalize_imm ())
3590 if (i
.types
[0].bitfield
.imm1
)
3591 i
.imm_operands
= 0; /* kludge for shift insns. */
3593 /* We only need to check those implicit registers for instructions
3594 with 3 operands or less. */
3595 if (i
.operands
<= 3)
3596 for (j
= 0; j
< i
.operands
; j
++)
3597 if (i
.types
[j
].bitfield
.inoutportreg
3598 || i
.types
[j
].bitfield
.shiftcount
3599 || i
.types
[j
].bitfield
.acc
3600 || i
.types
[j
].bitfield
.floatacc
)
3603 /* ImmExt should be processed after SSE2AVX. */
3604 if (!i
.tm
.opcode_modifier
.sse2avx
3605 && i
.tm
.opcode_modifier
.immext
)
3608 /* For insns with operands there are more diddles to do to the opcode. */
3611 if (!process_operands ())
3614 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3616 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3617 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3620 if (i
.tm
.opcode_modifier
.vex
)
3621 build_vex_prefix (t
);
3623 if (i
.tm
.opcode_modifier
.evex
)
3624 build_evex_prefix ();
3626 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3627 instructions may define INT_OPCODE as well, so avoid this corner
3628 case for those instructions that use MODRM. */
3629 if (i
.tm
.base_opcode
== INT_OPCODE
3630 && !i
.tm
.opcode_modifier
.modrm
3631 && i
.op
[0].imms
->X_add_number
== 3)
3633 i
.tm
.base_opcode
= INT3_OPCODE
;
3637 if ((i
.tm
.opcode_modifier
.jump
3638 || i
.tm
.opcode_modifier
.jumpbyte
3639 || i
.tm
.opcode_modifier
.jumpdword
)
3640 && i
.op
[0].disps
->X_op
== O_constant
)
3642 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3643 the absolute address given by the constant. Since ix86 jumps and
3644 calls are pc relative, we need to generate a reloc. */
3645 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3646 i
.op
[0].disps
->X_op
= O_symbol
;
3649 if (i
.tm
.opcode_modifier
.rex64
)
3652 /* For 8 bit registers we need an empty rex prefix. Also if the
3653 instruction already has a prefix, we need to convert old
3654 registers to new ones. */
3656 if ((i
.types
[0].bitfield
.reg8
3657 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3658 || (i
.types
[1].bitfield
.reg8
3659 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3660 || ((i
.types
[0].bitfield
.reg8
3661 || i
.types
[1].bitfield
.reg8
)
3666 i
.rex
|= REX_OPCODE
;
3667 for (x
= 0; x
< 2; x
++)
3669 /* Look for 8 bit operand that uses old registers. */
3670 if (i
.types
[x
].bitfield
.reg8
3671 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3673 /* In case it is "hi" register, give up. */
3674 if (i
.op
[x
].regs
->reg_num
> 3)
3675 as_bad (_("can't encode register '%s%s' in an "
3676 "instruction requiring REX prefix."),
3677 register_prefix
, i
.op
[x
].regs
->reg_name
);
3679 /* Otherwise it is equivalent to the extended register.
3680 Since the encoding doesn't change this is merely
3681 cosmetic cleanup for debug output. */
3683 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3689 add_prefix (REX_OPCODE
| i
.rex
);
3691 /* We are ready to output the insn. */
3696 parse_insn (char *line
, char *mnemonic
)
3699 char *token_start
= l
;
3702 const insn_template
*t
;
3708 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3713 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3715 as_bad (_("no such instruction: `%s'"), token_start
);
3720 if (!is_space_char (*l
)
3721 && *l
!= END_OF_INSN
3723 || (*l
!= PREFIX_SEPARATOR
3726 as_bad (_("invalid character %s in mnemonic"),
3727 output_invalid (*l
));
3730 if (token_start
== l
)
3732 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3733 as_bad (_("expecting prefix; got nothing"));
3735 as_bad (_("expecting mnemonic; got nothing"));
3739 /* Look up instruction (or prefix) via hash table. */
3740 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3742 if (*l
!= END_OF_INSN
3743 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3744 && current_templates
3745 && current_templates
->start
->opcode_modifier
.isprefix
)
3747 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3749 as_bad ((flag_code
!= CODE_64BIT
3750 ? _("`%s' is only supported in 64-bit mode")
3751 : _("`%s' is not supported in 64-bit mode")),
3752 current_templates
->start
->name
);
3755 /* If we are in 16-bit mode, do not allow addr16 or data16.
3756 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3757 if ((current_templates
->start
->opcode_modifier
.size16
3758 || current_templates
->start
->opcode_modifier
.size32
)
3759 && flag_code
!= CODE_64BIT
3760 && (current_templates
->start
->opcode_modifier
.size32
3761 ^ (flag_code
== CODE_16BIT
)))
3763 as_bad (_("redundant %s prefix"),
3764 current_templates
->start
->name
);
3767 /* Add prefix, checking for repeated prefixes. */
3768 switch (add_prefix (current_templates
->start
->base_opcode
))
3773 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3774 i
.hle_prefix
= current_templates
->start
->name
;
3775 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3776 i
.bnd_prefix
= current_templates
->start
->name
;
3778 i
.rep_prefix
= current_templates
->start
->name
;
3783 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3790 if (!current_templates
)
3792 /* Check if we should swap operand or force 32bit displacement in
3794 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3796 else if (mnem_p
- 3 == dot_p
3799 i
.disp_encoding
= disp_encoding_8bit
;
3800 else if (mnem_p
- 4 == dot_p
3804 i
.disp_encoding
= disp_encoding_32bit
;
3809 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3812 if (!current_templates
)
3815 /* See if we can get a match by trimming off a suffix. */
3818 case WORD_MNEM_SUFFIX
:
3819 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3820 i
.suffix
= SHORT_MNEM_SUFFIX
;
3822 case BYTE_MNEM_SUFFIX
:
3823 case QWORD_MNEM_SUFFIX
:
3824 i
.suffix
= mnem_p
[-1];
3826 current_templates
= (const templates
*) hash_find (op_hash
,
3829 case SHORT_MNEM_SUFFIX
:
3830 case LONG_MNEM_SUFFIX
:
3833 i
.suffix
= mnem_p
[-1];
3835 current_templates
= (const templates
*) hash_find (op_hash
,
3844 if (intel_float_operand (mnemonic
) == 1)
3845 i
.suffix
= SHORT_MNEM_SUFFIX
;
3847 i
.suffix
= LONG_MNEM_SUFFIX
;
3849 current_templates
= (const templates
*) hash_find (op_hash
,
3854 if (!current_templates
)
3856 as_bad (_("no such instruction: `%s'"), token_start
);
3861 if (current_templates
->start
->opcode_modifier
.jump
3862 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3864 /* Check for a branch hint. We allow ",pt" and ",pn" for
3865 predict taken and predict not taken respectively.
3866 I'm not sure that branch hints actually do anything on loop
3867 and jcxz insns (JumpByte) for current Pentium4 chips. They
3868 may work in the future and it doesn't hurt to accept them
3870 if (l
[0] == ',' && l
[1] == 'p')
3874 if (!add_prefix (DS_PREFIX_OPCODE
))
3878 else if (l
[2] == 'n')
3880 if (!add_prefix (CS_PREFIX_OPCODE
))
3886 /* Any other comma loses. */
3889 as_bad (_("invalid character %s in mnemonic"),
3890 output_invalid (*l
));
3894 /* Check if instruction is supported on specified architecture. */
3896 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3898 supported
|= cpu_flags_match (t
);
3899 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3903 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3905 as_bad (flag_code
== CODE_64BIT
3906 ? _("`%s' is not supported in 64-bit mode")
3907 : _("`%s' is only supported in 64-bit mode"),
3908 current_templates
->start
->name
);
3911 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3913 as_bad (_("`%s' is not supported on `%s%s'"),
3914 current_templates
->start
->name
,
3915 cpu_arch_name
? cpu_arch_name
: default_arch
,
3916 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3921 if (!cpu_arch_flags
.bitfield
.cpui386
3922 && (flag_code
!= CODE_16BIT
))
3924 as_warn (_("use .code16 to ensure correct addressing mode"));
3931 parse_operands (char *l
, const char *mnemonic
)
3935 /* 1 if operand is pending after ','. */
3936 unsigned int expecting_operand
= 0;
3938 /* Non-zero if operand parens not balanced. */
3939 unsigned int paren_not_balanced
;
3941 while (*l
!= END_OF_INSN
)
3943 /* Skip optional white space before operand. */
3944 if (is_space_char (*l
))
3946 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3948 as_bad (_("invalid character %s before operand %d"),
3949 output_invalid (*l
),
3953 token_start
= l
; /* after white space */
3954 paren_not_balanced
= 0;
3955 while (paren_not_balanced
|| *l
!= ',')
3957 if (*l
== END_OF_INSN
)
3959 if (paren_not_balanced
)
3962 as_bad (_("unbalanced parenthesis in operand %d."),
3965 as_bad (_("unbalanced brackets in operand %d."),
3970 break; /* we are done */
3972 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3974 as_bad (_("invalid character %s in operand %d"),
3975 output_invalid (*l
),
3982 ++paren_not_balanced
;
3984 --paren_not_balanced
;
3989 ++paren_not_balanced
;
3991 --paren_not_balanced
;
3995 if (l
!= token_start
)
3996 { /* Yes, we've read in another operand. */
3997 unsigned int operand_ok
;
3998 this_operand
= i
.operands
++;
3999 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4000 if (i
.operands
> MAX_OPERANDS
)
4002 as_bad (_("spurious operands; (%d operands/instruction max)"),
4006 /* Now parse operand adding info to 'i' as we go along. */
4007 END_STRING_AND_SAVE (l
);
4011 i386_intel_operand (token_start
,
4012 intel_float_operand (mnemonic
));
4014 operand_ok
= i386_att_operand (token_start
);
4016 RESTORE_END_STRING (l
);
4022 if (expecting_operand
)
4024 expecting_operand_after_comma
:
4025 as_bad (_("expecting operand after ','; got nothing"));
4030 as_bad (_("expecting operand before ','; got nothing"));
4035 /* Now *l must be either ',' or END_OF_INSN. */
4038 if (*++l
== END_OF_INSN
)
4040 /* Just skip it, if it's \n complain. */
4041 goto expecting_operand_after_comma
;
4043 expecting_operand
= 1;
4050 swap_2_operands (int xchg1
, int xchg2
)
4052 union i386_op temp_op
;
4053 i386_operand_type temp_type
;
4054 enum bfd_reloc_code_real temp_reloc
;
4056 temp_type
= i
.types
[xchg2
];
4057 i
.types
[xchg2
] = i
.types
[xchg1
];
4058 i
.types
[xchg1
] = temp_type
;
4059 temp_op
= i
.op
[xchg2
];
4060 i
.op
[xchg2
] = i
.op
[xchg1
];
4061 i
.op
[xchg1
] = temp_op
;
4062 temp_reloc
= i
.reloc
[xchg2
];
4063 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4064 i
.reloc
[xchg1
] = temp_reloc
;
4068 if (i
.mask
->operand
== xchg1
)
4069 i
.mask
->operand
= xchg2
;
4070 else if (i
.mask
->operand
== xchg2
)
4071 i
.mask
->operand
= xchg1
;
4075 if (i
.broadcast
->operand
== xchg1
)
4076 i
.broadcast
->operand
= xchg2
;
4077 else if (i
.broadcast
->operand
== xchg2
)
4078 i
.broadcast
->operand
= xchg1
;
4082 if (i
.rounding
->operand
== xchg1
)
4083 i
.rounding
->operand
= xchg2
;
4084 else if (i
.rounding
->operand
== xchg2
)
4085 i
.rounding
->operand
= xchg1
;
4090 swap_operands (void)
4096 swap_2_operands (1, i
.operands
- 2);
4099 swap_2_operands (0, i
.operands
- 1);
4105 if (i
.mem_operands
== 2)
4107 const seg_entry
*temp_seg
;
4108 temp_seg
= i
.seg
[0];
4109 i
.seg
[0] = i
.seg
[1];
4110 i
.seg
[1] = temp_seg
;
4114 /* Try to ensure constant immediates are represented in the smallest
4119 char guess_suffix
= 0;
4123 guess_suffix
= i
.suffix
;
4124 else if (i
.reg_operands
)
4126 /* Figure out a suffix from the last register operand specified.
4127 We can't do this properly yet, ie. excluding InOutPortReg,
4128 but the following works for instructions with immediates.
4129 In any case, we can't set i.suffix yet. */
4130 for (op
= i
.operands
; --op
>= 0;)
4131 if (i
.types
[op
].bitfield
.reg8
)
4133 guess_suffix
= BYTE_MNEM_SUFFIX
;
4136 else if (i
.types
[op
].bitfield
.reg16
)
4138 guess_suffix
= WORD_MNEM_SUFFIX
;
4141 else if (i
.types
[op
].bitfield
.reg32
)
4143 guess_suffix
= LONG_MNEM_SUFFIX
;
4146 else if (i
.types
[op
].bitfield
.reg64
)
4148 guess_suffix
= QWORD_MNEM_SUFFIX
;
4152 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4153 guess_suffix
= WORD_MNEM_SUFFIX
;
4155 for (op
= i
.operands
; --op
>= 0;)
4156 if (operand_type_check (i
.types
[op
], imm
))
4158 switch (i
.op
[op
].imms
->X_op
)
4161 /* If a suffix is given, this operand may be shortened. */
4162 switch (guess_suffix
)
4164 case LONG_MNEM_SUFFIX
:
4165 i
.types
[op
].bitfield
.imm32
= 1;
4166 i
.types
[op
].bitfield
.imm64
= 1;
4168 case WORD_MNEM_SUFFIX
:
4169 i
.types
[op
].bitfield
.imm16
= 1;
4170 i
.types
[op
].bitfield
.imm32
= 1;
4171 i
.types
[op
].bitfield
.imm32s
= 1;
4172 i
.types
[op
].bitfield
.imm64
= 1;
4174 case BYTE_MNEM_SUFFIX
:
4175 i
.types
[op
].bitfield
.imm8
= 1;
4176 i
.types
[op
].bitfield
.imm8s
= 1;
4177 i
.types
[op
].bitfield
.imm16
= 1;
4178 i
.types
[op
].bitfield
.imm32
= 1;
4179 i
.types
[op
].bitfield
.imm32s
= 1;
4180 i
.types
[op
].bitfield
.imm64
= 1;
4184 /* If this operand is at most 16 bits, convert it
4185 to a signed 16 bit number before trying to see
4186 whether it will fit in an even smaller size.
4187 This allows a 16-bit operand such as $0xffe0 to
4188 be recognised as within Imm8S range. */
4189 if ((i
.types
[op
].bitfield
.imm16
)
4190 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4192 i
.op
[op
].imms
->X_add_number
=
4193 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4195 if ((i
.types
[op
].bitfield
.imm32
)
4196 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4199 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4200 ^ ((offsetT
) 1 << 31))
4201 - ((offsetT
) 1 << 31));
4204 = operand_type_or (i
.types
[op
],
4205 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4207 /* We must avoid matching of Imm32 templates when 64bit
4208 only immediate is available. */
4209 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4210 i
.types
[op
].bitfield
.imm32
= 0;
4217 /* Symbols and expressions. */
4219 /* Convert symbolic operand to proper sizes for matching, but don't
4220 prevent matching a set of insns that only supports sizes other
4221 than those matching the insn suffix. */
4223 i386_operand_type mask
, allowed
;
4224 const insn_template
*t
;
4226 operand_type_set (&mask
, 0);
4227 operand_type_set (&allowed
, 0);
4229 for (t
= current_templates
->start
;
4230 t
< current_templates
->end
;
4232 allowed
= operand_type_or (allowed
,
4233 t
->operand_types
[op
]);
4234 switch (guess_suffix
)
4236 case QWORD_MNEM_SUFFIX
:
4237 mask
.bitfield
.imm64
= 1;
4238 mask
.bitfield
.imm32s
= 1;
4240 case LONG_MNEM_SUFFIX
:
4241 mask
.bitfield
.imm32
= 1;
4243 case WORD_MNEM_SUFFIX
:
4244 mask
.bitfield
.imm16
= 1;
4246 case BYTE_MNEM_SUFFIX
:
4247 mask
.bitfield
.imm8
= 1;
4252 allowed
= operand_type_and (mask
, allowed
);
4253 if (!operand_type_all_zero (&allowed
))
4254 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4261 /* Try to use the smallest displacement type too. */
4263 optimize_disp (void)
4267 for (op
= i
.operands
; --op
>= 0;)
4268 if (operand_type_check (i
.types
[op
], disp
))
4270 if (i
.op
[op
].disps
->X_op
== O_constant
)
4272 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4274 if (i
.types
[op
].bitfield
.disp16
4275 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4277 /* If this operand is at most 16 bits, convert
4278 to a signed 16 bit number and don't use 64bit
4280 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4281 i
.types
[op
].bitfield
.disp64
= 0;
4283 if (i
.types
[op
].bitfield
.disp32
4284 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4286 /* If this operand is at most 32 bits, convert
4287 to a signed 32 bit number and don't use 64bit
4289 op_disp
&= (((offsetT
) 2 << 31) - 1);
4290 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4291 i
.types
[op
].bitfield
.disp64
= 0;
4293 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4295 i
.types
[op
].bitfield
.disp8
= 0;
4296 i
.types
[op
].bitfield
.disp16
= 0;
4297 i
.types
[op
].bitfield
.disp32
= 0;
4298 i
.types
[op
].bitfield
.disp32s
= 0;
4299 i
.types
[op
].bitfield
.disp64
= 0;
4303 else if (flag_code
== CODE_64BIT
)
4305 if (fits_in_signed_long (op_disp
))
4307 i
.types
[op
].bitfield
.disp64
= 0;
4308 i
.types
[op
].bitfield
.disp32s
= 1;
4310 if (i
.prefix
[ADDR_PREFIX
]
4311 && fits_in_unsigned_long (op_disp
))
4312 i
.types
[op
].bitfield
.disp32
= 1;
4314 if ((i
.types
[op
].bitfield
.disp32
4315 || i
.types
[op
].bitfield
.disp32s
4316 || i
.types
[op
].bitfield
.disp16
)
4317 && fits_in_signed_byte (op_disp
))
4318 i
.types
[op
].bitfield
.disp8
= 1;
4320 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4321 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4323 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4324 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4325 i
.types
[op
].bitfield
.disp8
= 0;
4326 i
.types
[op
].bitfield
.disp16
= 0;
4327 i
.types
[op
].bitfield
.disp32
= 0;
4328 i
.types
[op
].bitfield
.disp32s
= 0;
4329 i
.types
[op
].bitfield
.disp64
= 0;
4332 /* We only support 64bit displacement on constants. */
4333 i
.types
[op
].bitfield
.disp64
= 0;
4337 /* Check if operands are valid for the instruction. */
4340 check_VecOperands (const insn_template
*t
)
4344 /* Without VSIB byte, we can't have a vector register for index. */
4345 if (!t
->opcode_modifier
.vecsib
4347 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4348 || i
.index_reg
->reg_type
.bitfield
.regymm
4349 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4351 i
.error
= unsupported_vector_index_register
;
4355 /* Check if default mask is allowed. */
4356 if (t
->opcode_modifier
.nodefmask
4357 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4359 i
.error
= no_default_mask
;
4363 /* For VSIB byte, we need a vector register for index, and all vector
4364 registers must be distinct. */
4365 if (t
->opcode_modifier
.vecsib
)
4368 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4369 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4370 || (t
->opcode_modifier
.vecsib
== VecSIB256
4371 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4372 || (t
->opcode_modifier
.vecsib
== VecSIB512
4373 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4375 i
.error
= invalid_vsib_address
;
4379 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4380 if (i
.reg_operands
== 2 && !i
.mask
)
4382 gas_assert (i
.types
[0].bitfield
.regxmm
4383 || i
.types
[0].bitfield
.regymm
);
4384 gas_assert (i
.types
[2].bitfield
.regxmm
4385 || i
.types
[2].bitfield
.regymm
);
4386 if (operand_check
== check_none
)
4388 if (register_number (i
.op
[0].regs
)
4389 != register_number (i
.index_reg
)
4390 && register_number (i
.op
[2].regs
)
4391 != register_number (i
.index_reg
)
4392 && register_number (i
.op
[0].regs
)
4393 != register_number (i
.op
[2].regs
))
4395 if (operand_check
== check_error
)
4397 i
.error
= invalid_vector_register_set
;
4400 as_warn (_("mask, index, and destination registers should be distinct"));
4402 else if (i
.reg_operands
== 1 && i
.mask
)
4404 if ((i
.types
[1].bitfield
.regymm
4405 || i
.types
[1].bitfield
.regzmm
)
4406 && (register_number (i
.op
[1].regs
)
4407 == register_number (i
.index_reg
)))
4409 if (operand_check
== check_error
)
4411 i
.error
= invalid_vector_register_set
;
4414 if (operand_check
!= check_none
)
4415 as_warn (_("index and destination registers should be distinct"));
4420 /* Check if broadcast is supported by the instruction and is applied
4421 to the memory operand. */
4424 int broadcasted_opnd_size
;
4426 /* Check if specified broadcast is supported in this instruction,
4427 and it's applied to memory operand of DWORD or QWORD type,
4428 depending on VecESize. */
4429 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4430 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4431 || (t
->opcode_modifier
.vecesize
== 0
4432 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4433 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4434 || (t
->opcode_modifier
.vecesize
== 1
4435 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4436 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4439 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4440 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4441 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4442 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4443 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4447 if ((broadcasted_opnd_size
== 256
4448 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4449 || (broadcasted_opnd_size
== 512
4450 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4453 i
.error
= unsupported_broadcast
;
4457 /* If broadcast is supported in this instruction, we need to check if
4458 operand of one-element size isn't specified without broadcast. */
4459 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4461 /* Find memory operand. */
4462 for (op
= 0; op
< i
.operands
; op
++)
4463 if (operand_type_check (i
.types
[op
], anymem
))
4465 gas_assert (op
< i
.operands
);
4466 /* Check size of the memory operand. */
4467 if ((t
->opcode_modifier
.vecesize
== 0
4468 && i
.types
[op
].bitfield
.dword
)
4469 || (t
->opcode_modifier
.vecesize
== 1
4470 && i
.types
[op
].bitfield
.qword
))
4472 i
.error
= broadcast_needed
;
4477 /* Check if requested masking is supported. */
4479 && (!t
->opcode_modifier
.masking
4481 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4483 i
.error
= unsupported_masking
;
4487 /* Check if masking is applied to dest operand. */
4488 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4490 i
.error
= mask_not_on_destination
;
4497 if ((i
.rounding
->type
!= saeonly
4498 && !t
->opcode_modifier
.staticrounding
)
4499 || (i
.rounding
->type
== saeonly
4500 && (t
->opcode_modifier
.staticrounding
4501 || !t
->opcode_modifier
.sae
)))
4503 i
.error
= unsupported_rc_sae
;
4506 /* If the instruction has several immediate operands and one of
4507 them is rounding, the rounding operand should be the last
4508 immediate operand. */
4509 if (i
.imm_operands
> 1
4510 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4512 i
.error
= rc_sae_operand_not_last_imm
;
4517 /* Check vector Disp8 operand. */
4518 if (t
->opcode_modifier
.disp8memshift
)
4521 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4523 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4525 for (op
= 0; op
< i
.operands
; op
++)
4526 if (operand_type_check (i
.types
[op
], disp
)
4527 && i
.op
[op
].disps
->X_op
== O_constant
)
4529 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4530 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4531 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4534 i
.types
[op
].bitfield
.vec_disp8
= 1;
4537 /* Vector insn can only have Vec_Disp8/Disp32 in
4538 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4540 i
.types
[op
].bitfield
.disp8
= 0;
4541 if (flag_code
!= CODE_16BIT
)
4542 i
.types
[op
].bitfield
.disp16
= 0;
4545 else if (flag_code
!= CODE_16BIT
)
4547 /* One form of this instruction supports vector Disp8.
4548 Try vector Disp8 if we need to use Disp32. */
4549 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4551 i
.error
= try_vector_disp8
;
4563 /* Check if operands are valid for the instruction. Update VEX
4567 VEX_check_operands (const insn_template
*t
)
4569 /* VREX is only valid with EVEX prefix. */
4570 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4572 i
.error
= invalid_register_operand
;
4576 if (!t
->opcode_modifier
.vex
)
4579 /* Only check VEX_Imm4, which must be the first operand. */
4580 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4582 if (i
.op
[0].imms
->X_op
!= O_constant
4583 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4589 /* Turn off Imm8 so that update_imm won't complain. */
4590 i
.types
[0] = vec_imm4
;
4596 static const insn_template
*
4597 match_template (void)
4599 /* Points to template once we've found it. */
4600 const insn_template
*t
;
4601 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4602 i386_operand_type overlap4
;
4603 unsigned int found_reverse_match
;
4604 i386_opcode_modifier suffix_check
;
4605 i386_operand_type operand_types
[MAX_OPERANDS
];
4606 int addr_prefix_disp
;
4608 unsigned int found_cpu_match
;
4609 unsigned int check_register
;
4610 enum i386_error specific_error
= 0;
4612 #if MAX_OPERANDS != 5
4613 # error "MAX_OPERANDS must be 5."
4616 found_reverse_match
= 0;
4617 addr_prefix_disp
= -1;
4619 memset (&suffix_check
, 0, sizeof (suffix_check
));
4620 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4621 suffix_check
.no_bsuf
= 1;
4622 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4623 suffix_check
.no_wsuf
= 1;
4624 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4625 suffix_check
.no_ssuf
= 1;
4626 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4627 suffix_check
.no_lsuf
= 1;
4628 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4629 suffix_check
.no_qsuf
= 1;
4630 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4631 suffix_check
.no_ldsuf
= 1;
4633 /* Must have right number of operands. */
4634 i
.error
= number_of_operands_mismatch
;
4636 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4638 addr_prefix_disp
= -1;
4640 if (i
.operands
!= t
->operands
)
4643 /* Check processor support. */
4644 i
.error
= unsupported
;
4645 found_cpu_match
= (cpu_flags_match (t
)
4646 == CPU_FLAGS_PERFECT_MATCH
);
4647 if (!found_cpu_match
)
4650 /* Check old gcc support. */
4651 i
.error
= old_gcc_only
;
4652 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4655 /* Check AT&T mnemonic. */
4656 i
.error
= unsupported_with_intel_mnemonic
;
4657 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4660 /* Check AT&T/Intel syntax. */
4661 i
.error
= unsupported_syntax
;
4662 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4663 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4666 /* Check the suffix, except for some instructions in intel mode. */
4667 i
.error
= invalid_instruction_suffix
;
4668 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4669 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4670 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4671 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4672 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4673 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4674 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4677 if (!operand_size_match (t
))
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 operand_types
[j
] = t
->operand_types
[j
];
4683 /* In general, don't allow 64-bit operands in 32-bit mode. */
4684 if (i
.suffix
== QWORD_MNEM_SUFFIX
4685 && flag_code
!= CODE_64BIT
4687 ? (!t
->opcode_modifier
.ignoresize
4688 && !intel_float_operand (t
->name
))
4689 : intel_float_operand (t
->name
) != 2)
4690 && ((!operand_types
[0].bitfield
.regmmx
4691 && !operand_types
[0].bitfield
.regxmm
4692 && !operand_types
[0].bitfield
.regymm
4693 && !operand_types
[0].bitfield
.regzmm
)
4694 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4695 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4696 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4697 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4698 && (t
->base_opcode
!= 0x0fc7
4699 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4702 /* In general, don't allow 32-bit operands on pre-386. */
4703 else if (i
.suffix
== LONG_MNEM_SUFFIX
4704 && !cpu_arch_flags
.bitfield
.cpui386
4706 ? (!t
->opcode_modifier
.ignoresize
4707 && !intel_float_operand (t
->name
))
4708 : intel_float_operand (t
->name
) != 2)
4709 && ((!operand_types
[0].bitfield
.regmmx
4710 && !operand_types
[0].bitfield
.regxmm
)
4711 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4712 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4715 /* Do not verify operands when there are none. */
4719 /* We've found a match; break out of loop. */
4723 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4724 into Disp32/Disp16/Disp32 operand. */
4725 if (i
.prefix
[ADDR_PREFIX
] != 0)
4727 /* There should be only one Disp operand. */
4731 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4733 if (operand_types
[j
].bitfield
.disp16
)
4735 addr_prefix_disp
= j
;
4736 operand_types
[j
].bitfield
.disp32
= 1;
4737 operand_types
[j
].bitfield
.disp16
= 0;
4743 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4745 if (operand_types
[j
].bitfield
.disp32
)
4747 addr_prefix_disp
= j
;
4748 operand_types
[j
].bitfield
.disp32
= 0;
4749 operand_types
[j
].bitfield
.disp16
= 1;
4755 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4757 if (operand_types
[j
].bitfield
.disp64
)
4759 addr_prefix_disp
= j
;
4760 operand_types
[j
].bitfield
.disp64
= 0;
4761 operand_types
[j
].bitfield
.disp32
= 1;
4769 /* We check register size if needed. */
4770 check_register
= t
->opcode_modifier
.checkregsize
;
4771 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4772 switch (t
->operands
)
4775 if (!operand_type_match (overlap0
, i
.types
[0]))
4779 /* xchg %eax, %eax is a special case. It is an aliase for nop
4780 only in 32bit mode and we can use opcode 0x90. In 64bit
4781 mode, we can't use 0x90 for xchg %eax, %eax since it should
4782 zero-extend %eax to %rax. */
4783 if (flag_code
== CODE_64BIT
4784 && t
->base_opcode
== 0x90
4785 && operand_type_equal (&i
.types
[0], &acc32
)
4786 && operand_type_equal (&i
.types
[1], &acc32
))
4790 /* If we swap operand in encoding, we either match
4791 the next one or reverse direction of operands. */
4792 if (t
->opcode_modifier
.s
)
4794 else if (t
->opcode_modifier
.d
)
4799 /* If we swap operand in encoding, we match the next one. */
4800 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4804 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4805 if (!operand_type_match (overlap0
, i
.types
[0])
4806 || !operand_type_match (overlap1
, i
.types
[1])
4808 && !operand_type_register_match (overlap0
, i
.types
[0],
4810 overlap1
, i
.types
[1],
4813 /* Check if other direction is valid ... */
4814 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4818 /* Try reversing direction of operands. */
4819 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4820 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4821 if (!operand_type_match (overlap0
, i
.types
[0])
4822 || !operand_type_match (overlap1
, i
.types
[1])
4824 && !operand_type_register_match (overlap0
,
4831 /* Does not match either direction. */
4834 /* found_reverse_match holds which of D or FloatDR
4836 if (t
->opcode_modifier
.d
)
4837 found_reverse_match
= Opcode_D
;
4838 else if (t
->opcode_modifier
.floatd
)
4839 found_reverse_match
= Opcode_FloatD
;
4841 found_reverse_match
= 0;
4842 if (t
->opcode_modifier
.floatr
)
4843 found_reverse_match
|= Opcode_FloatR
;
4847 /* Found a forward 2 operand match here. */
4848 switch (t
->operands
)
4851 overlap4
= operand_type_and (i
.types
[4],
4854 overlap3
= operand_type_and (i
.types
[3],
4857 overlap2
= operand_type_and (i
.types
[2],
4862 switch (t
->operands
)
4865 if (!operand_type_match (overlap4
, i
.types
[4])
4866 || !operand_type_register_match (overlap3
,
4874 if (!operand_type_match (overlap3
, i
.types
[3])
4876 && !operand_type_register_match (overlap2
,
4884 /* Here we make use of the fact that there are no
4885 reverse match 3 operand instructions, and all 3
4886 operand instructions only need to be checked for
4887 register consistency between operands 2 and 3. */
4888 if (!operand_type_match (overlap2
, i
.types
[2])
4890 && !operand_type_register_match (overlap1
,
4900 /* Found either forward/reverse 2, 3 or 4 operand match here:
4901 slip through to break. */
4903 if (!found_cpu_match
)
4905 found_reverse_match
= 0;
4909 /* Check if vector and VEX operands are valid. */
4910 if (check_VecOperands (t
) || VEX_check_operands (t
))
4912 specific_error
= i
.error
;
4916 /* We've found a match; break out of loop. */
4920 if (t
== current_templates
->end
)
4922 /* We found no match. */
4923 const char *err_msg
;
4924 switch (specific_error
? specific_error
: i
.error
)
4928 case operand_size_mismatch
:
4929 err_msg
= _("operand size mismatch");
4931 case operand_type_mismatch
:
4932 err_msg
= _("operand type mismatch");
4934 case register_type_mismatch
:
4935 err_msg
= _("register type mismatch");
4937 case number_of_operands_mismatch
:
4938 err_msg
= _("number of operands mismatch");
4940 case invalid_instruction_suffix
:
4941 err_msg
= _("invalid instruction suffix");
4944 err_msg
= _("constant doesn't fit in 4 bits");
4947 err_msg
= _("only supported with old gcc");
4949 case unsupported_with_intel_mnemonic
:
4950 err_msg
= _("unsupported with Intel mnemonic");
4952 case unsupported_syntax
:
4953 err_msg
= _("unsupported syntax");
4956 as_bad (_("unsupported instruction `%s'"),
4957 current_templates
->start
->name
);
4959 case invalid_vsib_address
:
4960 err_msg
= _("invalid VSIB address");
4962 case invalid_vector_register_set
:
4963 err_msg
= _("mask, index, and destination registers must be distinct");
4965 case unsupported_vector_index_register
:
4966 err_msg
= _("unsupported vector index register");
4968 case unsupported_broadcast
:
4969 err_msg
= _("unsupported broadcast");
4971 case broadcast_not_on_src_operand
:
4972 err_msg
= _("broadcast not on source memory operand");
4974 case broadcast_needed
:
4975 err_msg
= _("broadcast is needed for operand of such type");
4977 case unsupported_masking
:
4978 err_msg
= _("unsupported masking");
4980 case mask_not_on_destination
:
4981 err_msg
= _("mask not on destination operand");
4983 case no_default_mask
:
4984 err_msg
= _("default mask isn't allowed");
4986 case unsupported_rc_sae
:
4987 err_msg
= _("unsupported static rounding/sae");
4989 case rc_sae_operand_not_last_imm
:
4991 err_msg
= _("RC/SAE operand must precede immediate operands");
4993 err_msg
= _("RC/SAE operand must follow immediate operands");
4995 case invalid_register_operand
:
4996 err_msg
= _("invalid register operand");
4999 as_bad (_("%s for `%s'"), err_msg
,
5000 current_templates
->start
->name
);
5004 if (!quiet_warnings
)
5007 && (i
.types
[0].bitfield
.jumpabsolute
5008 != operand_types
[0].bitfield
.jumpabsolute
))
5010 as_warn (_("indirect %s without `*'"), t
->name
);
5013 if (t
->opcode_modifier
.isprefix
5014 && t
->opcode_modifier
.ignoresize
)
5016 /* Warn them that a data or address size prefix doesn't
5017 affect assembly of the next line of code. */
5018 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5022 /* Copy the template we found. */
5025 if (addr_prefix_disp
!= -1)
5026 i
.tm
.operand_types
[addr_prefix_disp
]
5027 = operand_types
[addr_prefix_disp
];
5029 if (found_reverse_match
)
5031 /* If we found a reverse match we must alter the opcode
5032 direction bit. found_reverse_match holds bits to change
5033 (different for int & float insns). */
5035 i
.tm
.base_opcode
^= found_reverse_match
;
5037 i
.tm
.operand_types
[0] = operand_types
[1];
5038 i
.tm
.operand_types
[1] = operand_types
[0];
5047 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5048 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5050 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5052 as_bad (_("`%s' operand %d must use `%ses' segment"),
5058 /* There's only ever one segment override allowed per instruction.
5059 This instruction possibly has a legal segment override on the
5060 second operand, so copy the segment to where non-string
5061 instructions store it, allowing common code. */
5062 i
.seg
[0] = i
.seg
[1];
5064 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5066 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5068 as_bad (_("`%s' operand %d must use `%ses' segment"),
5079 process_suffix (void)
5081 /* If matched instruction specifies an explicit instruction mnemonic
5083 if (i
.tm
.opcode_modifier
.size16
)
5084 i
.suffix
= WORD_MNEM_SUFFIX
;
5085 else if (i
.tm
.opcode_modifier
.size32
)
5086 i
.suffix
= LONG_MNEM_SUFFIX
;
5087 else if (i
.tm
.opcode_modifier
.size64
)
5088 i
.suffix
= QWORD_MNEM_SUFFIX
;
5089 else if (i
.reg_operands
)
5091 /* If there's no instruction mnemonic suffix we try to invent one
5092 based on register operands. */
5095 /* We take i.suffix from the last register operand specified,
5096 Destination register type is more significant than source
5097 register type. crc32 in SSE4.2 prefers source register
5099 if (i
.tm
.base_opcode
== 0xf20f38f1)
5101 if (i
.types
[0].bitfield
.reg16
)
5102 i
.suffix
= WORD_MNEM_SUFFIX
;
5103 else if (i
.types
[0].bitfield
.reg32
)
5104 i
.suffix
= LONG_MNEM_SUFFIX
;
5105 else if (i
.types
[0].bitfield
.reg64
)
5106 i
.suffix
= QWORD_MNEM_SUFFIX
;
5108 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5110 if (i
.types
[0].bitfield
.reg8
)
5111 i
.suffix
= BYTE_MNEM_SUFFIX
;
5118 if (i
.tm
.base_opcode
== 0xf20f38f1
5119 || i
.tm
.base_opcode
== 0xf20f38f0)
5121 /* We have to know the operand size for crc32. */
5122 as_bad (_("ambiguous memory operand size for `%s`"),
5127 for (op
= i
.operands
; --op
>= 0;)
5128 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5130 if (i
.types
[op
].bitfield
.reg8
)
5132 i
.suffix
= BYTE_MNEM_SUFFIX
;
5135 else if (i
.types
[op
].bitfield
.reg16
)
5137 i
.suffix
= WORD_MNEM_SUFFIX
;
5140 else if (i
.types
[op
].bitfield
.reg32
)
5142 i
.suffix
= LONG_MNEM_SUFFIX
;
5145 else if (i
.types
[op
].bitfield
.reg64
)
5147 i
.suffix
= QWORD_MNEM_SUFFIX
;
5153 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5156 && i
.tm
.opcode_modifier
.ignoresize
5157 && i
.tm
.opcode_modifier
.no_bsuf
)
5159 else if (!check_byte_reg ())
5162 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5165 && i
.tm
.opcode_modifier
.ignoresize
5166 && i
.tm
.opcode_modifier
.no_lsuf
)
5168 else if (!check_long_reg ())
5171 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5174 && i
.tm
.opcode_modifier
.ignoresize
5175 && i
.tm
.opcode_modifier
.no_qsuf
)
5177 else if (!check_qword_reg ())
5180 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5183 && i
.tm
.opcode_modifier
.ignoresize
5184 && i
.tm
.opcode_modifier
.no_wsuf
)
5186 else if (!check_word_reg ())
5189 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5190 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5191 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5193 /* Skip if the instruction has x/y/z suffix. match_template
5194 should check if it is a valid suffix. */
5196 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5197 /* Do nothing if the instruction is going to ignore the prefix. */
5202 else if (i
.tm
.opcode_modifier
.defaultsize
5204 /* exclude fldenv/frstor/fsave/fstenv */
5205 && i
.tm
.opcode_modifier
.no_ssuf
)
5207 i
.suffix
= stackop_size
;
5209 else if (intel_syntax
5211 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5212 || i
.tm
.opcode_modifier
.jumpbyte
5213 || i
.tm
.opcode_modifier
.jumpintersegment
5214 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5215 && i
.tm
.extension_opcode
<= 3)))
5220 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5222 i
.suffix
= QWORD_MNEM_SUFFIX
;
5226 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5227 i
.suffix
= LONG_MNEM_SUFFIX
;
5230 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5231 i
.suffix
= WORD_MNEM_SUFFIX
;
5240 if (i
.tm
.opcode_modifier
.w
)
5242 as_bad (_("no instruction mnemonic suffix given and "
5243 "no register operands; can't size instruction"));
5249 unsigned int suffixes
;
5251 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5252 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5254 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5256 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5258 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5260 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5263 /* There are more than suffix matches. */
5264 if (i
.tm
.opcode_modifier
.w
5265 || ((suffixes
& (suffixes
- 1))
5266 && !i
.tm
.opcode_modifier
.defaultsize
5267 && !i
.tm
.opcode_modifier
.ignoresize
))
5269 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5275 /* Change the opcode based on the operand size given by i.suffix;
5276 We don't need to change things for byte insns. */
5279 && i
.suffix
!= BYTE_MNEM_SUFFIX
5280 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5281 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5282 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5284 /* It's not a byte, select word/dword operation. */
5285 if (i
.tm
.opcode_modifier
.w
)
5287 if (i
.tm
.opcode_modifier
.shortform
)
5288 i
.tm
.base_opcode
|= 8;
5290 i
.tm
.base_opcode
|= 1;
5293 /* Now select between word & dword operations via the operand
5294 size prefix, except for instructions that will ignore this
5296 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5298 /* The address size override prefix changes the size of the
5300 if ((flag_code
== CODE_32BIT
5301 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5302 || (flag_code
!= CODE_32BIT
5303 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5304 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5307 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5308 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5309 && !i
.tm
.opcode_modifier
.ignoresize
5310 && !i
.tm
.opcode_modifier
.floatmf
5311 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5312 || (flag_code
== CODE_64BIT
5313 && i
.tm
.opcode_modifier
.jumpbyte
)))
5315 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5317 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5318 prefix
= ADDR_PREFIX_OPCODE
;
5320 if (!add_prefix (prefix
))
5324 /* Set mode64 for an operand. */
5325 if (i
.suffix
== QWORD_MNEM_SUFFIX
5326 && flag_code
== CODE_64BIT
5327 && !i
.tm
.opcode_modifier
.norex64
)
5329 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5330 need rex64. cmpxchg8b is also a special case. */
5331 if (! (i
.operands
== 2
5332 && i
.tm
.base_opcode
== 0x90
5333 && i
.tm
.extension_opcode
== None
5334 && operand_type_equal (&i
.types
[0], &acc64
)
5335 && operand_type_equal (&i
.types
[1], &acc64
))
5336 && ! (i
.operands
== 1
5337 && i
.tm
.base_opcode
== 0xfc7
5338 && i
.tm
.extension_opcode
== 1
5339 && !operand_type_check (i
.types
[0], reg
)
5340 && operand_type_check (i
.types
[0], anymem
)))
5344 /* Size floating point instruction. */
5345 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5346 if (i
.tm
.opcode_modifier
.floatmf
)
5347 i
.tm
.base_opcode
^= 4;
5354 check_byte_reg (void)
5358 for (op
= i
.operands
; --op
>= 0;)
5360 /* If this is an eight bit register, it's OK. If it's the 16 or
5361 32 bit version of an eight bit register, we will just use the
5362 low portion, and that's OK too. */
5363 if (i
.types
[op
].bitfield
.reg8
)
5366 /* I/O port address operands are OK too. */
5367 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5370 /* crc32 doesn't generate this warning. */
5371 if (i
.tm
.base_opcode
== 0xf20f38f0)
5374 if ((i
.types
[op
].bitfield
.reg16
5375 || i
.types
[op
].bitfield
.reg32
5376 || i
.types
[op
].bitfield
.reg64
)
5377 && i
.op
[op
].regs
->reg_num
< 4
5378 /* Prohibit these changes in 64bit mode, since the lowering
5379 would be more complicated. */
5380 && flag_code
!= CODE_64BIT
)
5382 #if REGISTER_WARNINGS
5383 if (!quiet_warnings
)
5384 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5386 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5387 ? REGNAM_AL
- REGNAM_AX
5388 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5390 i
.op
[op
].regs
->reg_name
,
5395 /* Any other register is bad. */
5396 if (i
.types
[op
].bitfield
.reg16
5397 || i
.types
[op
].bitfield
.reg32
5398 || i
.types
[op
].bitfield
.reg64
5399 || i
.types
[op
].bitfield
.regmmx
5400 || i
.types
[op
].bitfield
.regxmm
5401 || i
.types
[op
].bitfield
.regymm
5402 || i
.types
[op
].bitfield
.regzmm
5403 || i
.types
[op
].bitfield
.sreg2
5404 || i
.types
[op
].bitfield
.sreg3
5405 || i
.types
[op
].bitfield
.control
5406 || i
.types
[op
].bitfield
.debug
5407 || i
.types
[op
].bitfield
.test
5408 || i
.types
[op
].bitfield
.floatreg
5409 || i
.types
[op
].bitfield
.floatacc
)
5411 as_bad (_("`%s%s' not allowed with `%s%c'"),
5413 i
.op
[op
].regs
->reg_name
,
5423 check_long_reg (void)
5427 for (op
= i
.operands
; --op
>= 0;)
5428 /* Reject eight bit registers, except where the template requires
5429 them. (eg. movzb) */
5430 if (i
.types
[op
].bitfield
.reg8
5431 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5432 || i
.tm
.operand_types
[op
].bitfield
.reg32
5433 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5435 as_bad (_("`%s%s' not allowed with `%s%c'"),
5437 i
.op
[op
].regs
->reg_name
,
5442 /* Warn if the e prefix on a general reg is missing. */
5443 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5444 && i
.types
[op
].bitfield
.reg16
5445 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5446 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5448 /* Prohibit these changes in the 64bit mode, since the
5449 lowering is more complicated. */
5450 if (flag_code
== CODE_64BIT
)
5452 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5453 register_prefix
, i
.op
[op
].regs
->reg_name
,
5457 #if REGISTER_WARNINGS
5458 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5460 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5461 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5464 /* Warn if the r prefix on a general reg is present. */
5465 else if (i
.types
[op
].bitfield
.reg64
5466 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5467 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5470 && i
.tm
.opcode_modifier
.toqword
5471 && !i
.types
[0].bitfield
.regxmm
)
5473 /* Convert to QWORD. We want REX byte. */
5474 i
.suffix
= QWORD_MNEM_SUFFIX
;
5478 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5479 register_prefix
, i
.op
[op
].regs
->reg_name
,
5488 check_qword_reg (void)
5492 for (op
= i
.operands
; --op
>= 0; )
5493 /* Reject eight bit registers, except where the template requires
5494 them. (eg. movzb) */
5495 if (i
.types
[op
].bitfield
.reg8
5496 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5497 || i
.tm
.operand_types
[op
].bitfield
.reg32
5498 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5500 as_bad (_("`%s%s' not allowed with `%s%c'"),
5502 i
.op
[op
].regs
->reg_name
,
5507 /* Warn if the r prefix on a general reg is missing. */
5508 else if ((i
.types
[op
].bitfield
.reg16
5509 || i
.types
[op
].bitfield
.reg32
)
5510 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5511 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5513 /* Prohibit these changes in the 64bit mode, since the
5514 lowering is more complicated. */
5516 && i
.tm
.opcode_modifier
.todword
5517 && !i
.types
[0].bitfield
.regxmm
)
5519 /* Convert to DWORD. We don't want REX byte. */
5520 i
.suffix
= LONG_MNEM_SUFFIX
;
5524 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5525 register_prefix
, i
.op
[op
].regs
->reg_name
,
5534 check_word_reg (void)
5537 for (op
= i
.operands
; --op
>= 0;)
5538 /* Reject eight bit registers, except where the template requires
5539 them. (eg. movzb) */
5540 if (i
.types
[op
].bitfield
.reg8
5541 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5542 || i
.tm
.operand_types
[op
].bitfield
.reg32
5543 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5545 as_bad (_("`%s%s' not allowed with `%s%c'"),
5547 i
.op
[op
].regs
->reg_name
,
5552 /* Warn if the e or r prefix on a general reg is present. */
5553 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5554 && (i
.types
[op
].bitfield
.reg32
5555 || i
.types
[op
].bitfield
.reg64
)
5556 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5557 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5559 /* Prohibit these changes in the 64bit mode, since the
5560 lowering is more complicated. */
5561 if (flag_code
== CODE_64BIT
)
5563 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5564 register_prefix
, i
.op
[op
].regs
->reg_name
,
5568 #if REGISTER_WARNINGS
5569 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5571 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5572 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5579 update_imm (unsigned int j
)
5581 i386_operand_type overlap
= i
.types
[j
];
5582 if ((overlap
.bitfield
.imm8
5583 || overlap
.bitfield
.imm8s
5584 || overlap
.bitfield
.imm16
5585 || overlap
.bitfield
.imm32
5586 || overlap
.bitfield
.imm32s
5587 || overlap
.bitfield
.imm64
)
5588 && !operand_type_equal (&overlap
, &imm8
)
5589 && !operand_type_equal (&overlap
, &imm8s
)
5590 && !operand_type_equal (&overlap
, &imm16
)
5591 && !operand_type_equal (&overlap
, &imm32
)
5592 && !operand_type_equal (&overlap
, &imm32s
)
5593 && !operand_type_equal (&overlap
, &imm64
))
5597 i386_operand_type temp
;
5599 operand_type_set (&temp
, 0);
5600 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5602 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5603 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5605 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5606 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5607 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5609 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5610 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5613 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5616 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5617 || operand_type_equal (&overlap
, &imm16_32
)
5618 || operand_type_equal (&overlap
, &imm16_32s
))
5620 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5625 if (!operand_type_equal (&overlap
, &imm8
)
5626 && !operand_type_equal (&overlap
, &imm8s
)
5627 && !operand_type_equal (&overlap
, &imm16
)
5628 && !operand_type_equal (&overlap
, &imm32
)
5629 && !operand_type_equal (&overlap
, &imm32s
)
5630 && !operand_type_equal (&overlap
, &imm64
))
5632 as_bad (_("no instruction mnemonic suffix given; "
5633 "can't determine immediate size"));
5637 i
.types
[j
] = overlap
;
5647 /* Update the first 2 immediate operands. */
5648 n
= i
.operands
> 2 ? 2 : i
.operands
;
5651 for (j
= 0; j
< n
; j
++)
5652 if (update_imm (j
) == 0)
5655 /* The 3rd operand can't be immediate operand. */
5656 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5663 bad_implicit_operand (int xmm
)
5665 const char *ireg
= xmm
? "xmm0" : "ymm0";
5668 as_bad (_("the last operand of `%s' must be `%s%s'"),
5669 i
.tm
.name
, register_prefix
, ireg
);
5671 as_bad (_("the first operand of `%s' must be `%s%s'"),
5672 i
.tm
.name
, register_prefix
, ireg
);
5677 process_operands (void)
5679 /* Default segment register this instruction will use for memory
5680 accesses. 0 means unknown. This is only for optimizing out
5681 unnecessary segment overrides. */
5682 const seg_entry
*default_seg
= 0;
5684 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5686 unsigned int dupl
= i
.operands
;
5687 unsigned int dest
= dupl
- 1;
5690 /* The destination must be an xmm register. */
5691 gas_assert (i
.reg_operands
5692 && MAX_OPERANDS
> dupl
5693 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5695 if (i
.tm
.opcode_modifier
.firstxmm0
)
5697 /* The first operand is implicit and must be xmm0. */
5698 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5699 if (register_number (i
.op
[0].regs
) != 0)
5700 return bad_implicit_operand (1);
5702 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5704 /* Keep xmm0 for instructions with VEX prefix and 3
5710 /* We remove the first xmm0 and keep the number of
5711 operands unchanged, which in fact duplicates the
5713 for (j
= 1; j
< i
.operands
; j
++)
5715 i
.op
[j
- 1] = i
.op
[j
];
5716 i
.types
[j
- 1] = i
.types
[j
];
5717 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5721 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5723 gas_assert ((MAX_OPERANDS
- 1) > dupl
5724 && (i
.tm
.opcode_modifier
.vexsources
5727 /* Add the implicit xmm0 for instructions with VEX prefix
5729 for (j
= i
.operands
; j
> 0; j
--)
5731 i
.op
[j
] = i
.op
[j
- 1];
5732 i
.types
[j
] = i
.types
[j
- 1];
5733 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5736 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5737 i
.types
[0] = regxmm
;
5738 i
.tm
.operand_types
[0] = regxmm
;
5741 i
.reg_operands
+= 2;
5746 i
.op
[dupl
] = i
.op
[dest
];
5747 i
.types
[dupl
] = i
.types
[dest
];
5748 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5757 i
.op
[dupl
] = i
.op
[dest
];
5758 i
.types
[dupl
] = i
.types
[dest
];
5759 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5762 if (i
.tm
.opcode_modifier
.immext
)
5765 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5769 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5770 gas_assert (i
.reg_operands
5771 && (operand_type_equal (&i
.types
[0], ®xmm
)
5772 || operand_type_equal (&i
.types
[0], ®ymm
)
5773 || operand_type_equal (&i
.types
[0], ®zmm
)));
5774 if (register_number (i
.op
[0].regs
) != 0)
5775 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5777 for (j
= 1; j
< i
.operands
; j
++)
5779 i
.op
[j
- 1] = i
.op
[j
];
5780 i
.types
[j
- 1] = i
.types
[j
];
5782 /* We need to adjust fields in i.tm since they are used by
5783 build_modrm_byte. */
5784 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5791 else if (i
.tm
.opcode_modifier
.regkludge
)
5793 /* The imul $imm, %reg instruction is converted into
5794 imul $imm, %reg, %reg, and the clr %reg instruction
5795 is converted into xor %reg, %reg. */
5797 unsigned int first_reg_op
;
5799 if (operand_type_check (i
.types
[0], reg
))
5803 /* Pretend we saw the extra register operand. */
5804 gas_assert (i
.reg_operands
== 1
5805 && i
.op
[first_reg_op
+ 1].regs
== 0);
5806 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5807 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5812 if (i
.tm
.opcode_modifier
.shortform
)
5814 if (i
.types
[0].bitfield
.sreg2
5815 || i
.types
[0].bitfield
.sreg3
)
5817 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5818 && i
.op
[0].regs
->reg_num
== 1)
5820 as_bad (_("you can't `pop %scs'"), register_prefix
);
5823 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5824 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5829 /* The register or float register operand is in operand
5833 if (i
.types
[0].bitfield
.floatreg
5834 || operand_type_check (i
.types
[0], reg
))
5838 /* Register goes in low 3 bits of opcode. */
5839 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5840 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5842 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5844 /* Warn about some common errors, but press on regardless.
5845 The first case can be generated by gcc (<= 2.8.1). */
5846 if (i
.operands
== 2)
5848 /* Reversed arguments on faddp, fsubp, etc. */
5849 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5850 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5851 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5855 /* Extraneous `l' suffix on fp insn. */
5856 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5857 register_prefix
, i
.op
[0].regs
->reg_name
);
5862 else if (i
.tm
.opcode_modifier
.modrm
)
5864 /* The opcode is completed (modulo i.tm.extension_opcode which
5865 must be put into the modrm byte). Now, we make the modrm and
5866 index base bytes based on all the info we've collected. */
5868 default_seg
= build_modrm_byte ();
5870 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5874 else if (i
.tm
.opcode_modifier
.isstring
)
5876 /* For the string instructions that allow a segment override
5877 on one of their operands, the default segment is ds. */
5881 if (i
.tm
.base_opcode
== 0x8d /* lea */
5884 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5886 /* If a segment was explicitly specified, and the specified segment
5887 is not the default, use an opcode prefix to select it. If we
5888 never figured out what the default segment is, then default_seg
5889 will be zero at this point, and the specified segment prefix will
5891 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5893 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5899 static const seg_entry
*
5900 build_modrm_byte (void)
5902 const seg_entry
*default_seg
= 0;
5903 unsigned int source
, dest
;
5906 /* The first operand of instructions with VEX prefix and 3 sources
5907 must be VEX_Imm4. */
5908 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5911 unsigned int nds
, reg_slot
;
5914 if (i
.tm
.opcode_modifier
.veximmext
5915 && i
.tm
.opcode_modifier
.immext
)
5917 dest
= i
.operands
- 2;
5918 gas_assert (dest
== 3);
5921 dest
= i
.operands
- 1;
5924 /* There are 2 kinds of instructions:
5925 1. 5 operands: 4 register operands or 3 register operands
5926 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5927 VexW0 or VexW1. The destination must be either XMM, YMM or
5929 2. 4 operands: 4 register operands or 3 register operands
5930 plus 1 memory operand, VexXDS, and VexImmExt */
5931 gas_assert ((i
.reg_operands
== 4
5932 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5933 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5934 && (i
.tm
.opcode_modifier
.veximmext
5935 || (i
.imm_operands
== 1
5936 && i
.types
[0].bitfield
.vec_imm4
5937 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5938 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5939 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5940 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5941 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5943 if (i
.imm_operands
== 0)
5945 /* When there is no immediate operand, generate an 8bit
5946 immediate operand to encode the first operand. */
5947 exp
= &im_expressions
[i
.imm_operands
++];
5948 i
.op
[i
.operands
].imms
= exp
;
5949 i
.types
[i
.operands
] = imm8
;
5951 /* If VexW1 is set, the first operand is the source and
5952 the second operand is encoded in the immediate operand. */
5953 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5964 /* FMA swaps REG and NDS. */
5965 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5973 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5975 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5977 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5979 exp
->X_op
= O_constant
;
5980 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5981 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5985 unsigned int imm_slot
;
5987 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5989 /* If VexW0 is set, the third operand is the source and
5990 the second operand is encoded in the immediate
5997 /* VexW1 is set, the second operand is the source and
5998 the third operand is encoded in the immediate
6004 if (i
.tm
.opcode_modifier
.immext
)
6006 /* When ImmExt is set, the immdiate byte is the last
6008 imm_slot
= i
.operands
- 1;
6016 /* Turn on Imm8 so that output_imm will generate it. */
6017 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6020 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6022 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6024 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6026 i
.op
[imm_slot
].imms
->X_add_number
6027 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6028 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6031 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6032 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6034 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6036 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6041 /* i.reg_operands MUST be the number of real register operands;
6042 implicit registers do not count. If there are 3 register
6043 operands, it must be a instruction with VexNDS. For a
6044 instruction with VexNDD, the destination register is encoded
6045 in VEX prefix. If there are 4 register operands, it must be
6046 a instruction with VEX prefix and 3 sources. */
6047 if (i
.mem_operands
== 0
6048 && ((i
.reg_operands
== 2
6049 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6050 || (i
.reg_operands
== 3
6051 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6052 || (i
.reg_operands
== 4 && vex_3_sources
)))
6060 /* When there are 3 operands, one of them may be immediate,
6061 which may be the first or the last operand. Otherwise,
6062 the first operand must be shift count register (cl) or it
6063 is an instruction with VexNDS. */
6064 gas_assert (i
.imm_operands
== 1
6065 || (i
.imm_operands
== 0
6066 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6067 || i
.types
[0].bitfield
.shiftcount
)));
6068 if (operand_type_check (i
.types
[0], imm
)
6069 || i
.types
[0].bitfield
.shiftcount
)
6075 /* When there are 4 operands, the first two must be 8bit
6076 immediate operands. The source operand will be the 3rd
6079 For instructions with VexNDS, if the first operand
6080 an imm8, the source operand is the 2nd one. If the last
6081 operand is imm8, the source operand is the first one. */
6082 gas_assert ((i
.imm_operands
== 2
6083 && i
.types
[0].bitfield
.imm8
6084 && i
.types
[1].bitfield
.imm8
)
6085 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6086 && i
.imm_operands
== 1
6087 && (i
.types
[0].bitfield
.imm8
6088 || i
.types
[i
.operands
- 1].bitfield
.imm8
6090 if (i
.imm_operands
== 2)
6094 if (i
.types
[0].bitfield
.imm8
)
6101 if (i
.tm
.opcode_modifier
.evex
)
6103 /* For EVEX instructions, when there are 5 operands, the
6104 first one must be immediate operand. If the second one
6105 is immediate operand, the source operand is the 3th
6106 one. If the last one is immediate operand, the source
6107 operand is the 2nd one. */
6108 gas_assert (i
.imm_operands
== 2
6109 && i
.tm
.opcode_modifier
.sae
6110 && operand_type_check (i
.types
[0], imm
));
6111 if (operand_type_check (i
.types
[1], imm
))
6113 else if (operand_type_check (i
.types
[4], imm
))
6127 /* RC/SAE operand could be between DEST and SRC. That happens
6128 when one operand is GPR and the other one is XMM/YMM/ZMM
6130 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6133 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6135 /* For instructions with VexNDS, the register-only source
6136 operand must be 32/64bit integer, XMM, YMM or ZMM
6137 register. It is encoded in VEX prefix. We need to
6138 clear RegMem bit before calling operand_type_equal. */
6140 i386_operand_type op
;
6143 /* Check register-only source operand when two source
6144 operands are swapped. */
6145 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6146 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6154 op
= i
.tm
.operand_types
[vvvv
];
6155 op
.bitfield
.regmem
= 0;
6156 if ((dest
+ 1) >= i
.operands
6157 || (op
.bitfield
.reg32
!= 1
6158 && !op
.bitfield
.reg64
!= 1
6159 && !operand_type_equal (&op
, ®xmm
)
6160 && !operand_type_equal (&op
, ®ymm
)
6161 && !operand_type_equal (&op
, ®zmm
)
6162 && !operand_type_equal (&op
, ®mask
)))
6164 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6170 /* One of the register operands will be encoded in the i.tm.reg
6171 field, the other in the combined i.tm.mode and i.tm.regmem
6172 fields. If no form of this instruction supports a memory
6173 destination operand, then we assume the source operand may
6174 sometimes be a memory operand and so we need to store the
6175 destination in the i.rm.reg field. */
6176 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6177 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6179 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6180 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6181 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6183 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6185 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6187 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6192 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6193 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6194 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6196 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6198 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6200 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6203 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6205 if (!i
.types
[0].bitfield
.control
6206 && !i
.types
[1].bitfield
.control
)
6208 i
.rex
&= ~(REX_R
| REX_B
);
6209 add_prefix (LOCK_PREFIX_OPCODE
);
6213 { /* If it's not 2 reg operands... */
6218 unsigned int fake_zero_displacement
= 0;
6221 for (op
= 0; op
< i
.operands
; op
++)
6222 if (operand_type_check (i
.types
[op
], anymem
))
6224 gas_assert (op
< i
.operands
);
6226 if (i
.tm
.opcode_modifier
.vecsib
)
6228 if (i
.index_reg
->reg_num
== RegEiz
6229 || i
.index_reg
->reg_num
== RegRiz
)
6232 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6235 i
.sib
.base
= NO_BASE_REGISTER
;
6236 i
.sib
.scale
= i
.log2_scale_factor
;
6237 /* No Vec_Disp8 if there is no base. */
6238 i
.types
[op
].bitfield
.vec_disp8
= 0;
6239 i
.types
[op
].bitfield
.disp8
= 0;
6240 i
.types
[op
].bitfield
.disp16
= 0;
6241 i
.types
[op
].bitfield
.disp64
= 0;
6242 if (flag_code
!= CODE_64BIT
)
6244 /* Must be 32 bit */
6245 i
.types
[op
].bitfield
.disp32
= 1;
6246 i
.types
[op
].bitfield
.disp32s
= 0;
6250 i
.types
[op
].bitfield
.disp32
= 0;
6251 i
.types
[op
].bitfield
.disp32s
= 1;
6254 i
.sib
.index
= i
.index_reg
->reg_num
;
6255 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6257 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6263 if (i
.base_reg
== 0)
6266 if (!i
.disp_operands
)
6268 fake_zero_displacement
= 1;
6269 /* Instructions with VSIB byte need 32bit displacement
6270 if there is no base register. */
6271 if (i
.tm
.opcode_modifier
.vecsib
)
6272 i
.types
[op
].bitfield
.disp32
= 1;
6274 if (i
.index_reg
== 0)
6276 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6277 /* Operand is just <disp> */
6278 if (flag_code
== CODE_64BIT
)
6280 /* 64bit mode overwrites the 32bit absolute
6281 addressing by RIP relative addressing and
6282 absolute addressing is encoded by one of the
6283 redundant SIB forms. */
6284 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6285 i
.sib
.base
= NO_BASE_REGISTER
;
6286 i
.sib
.index
= NO_INDEX_REGISTER
;
6287 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6288 ? disp32s
: disp32
);
6290 else if ((flag_code
== CODE_16BIT
)
6291 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6293 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6294 i
.types
[op
] = disp16
;
6298 i
.rm
.regmem
= NO_BASE_REGISTER
;
6299 i
.types
[op
] = disp32
;
6302 else if (!i
.tm
.opcode_modifier
.vecsib
)
6304 /* !i.base_reg && i.index_reg */
6305 if (i
.index_reg
->reg_num
== RegEiz
6306 || i
.index_reg
->reg_num
== RegRiz
)
6307 i
.sib
.index
= NO_INDEX_REGISTER
;
6309 i
.sib
.index
= i
.index_reg
->reg_num
;
6310 i
.sib
.base
= NO_BASE_REGISTER
;
6311 i
.sib
.scale
= i
.log2_scale_factor
;
6312 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6313 /* No Vec_Disp8 if there is no base. */
6314 i
.types
[op
].bitfield
.vec_disp8
= 0;
6315 i
.types
[op
].bitfield
.disp8
= 0;
6316 i
.types
[op
].bitfield
.disp16
= 0;
6317 i
.types
[op
].bitfield
.disp64
= 0;
6318 if (flag_code
!= CODE_64BIT
)
6320 /* Must be 32 bit */
6321 i
.types
[op
].bitfield
.disp32
= 1;
6322 i
.types
[op
].bitfield
.disp32s
= 0;
6326 i
.types
[op
].bitfield
.disp32
= 0;
6327 i
.types
[op
].bitfield
.disp32s
= 1;
6329 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6333 /* RIP addressing for 64bit mode. */
6334 else if (i
.base_reg
->reg_num
== RegRip
||
6335 i
.base_reg
->reg_num
== RegEip
)
6337 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6338 i
.rm
.regmem
= NO_BASE_REGISTER
;
6339 i
.types
[op
].bitfield
.disp8
= 0;
6340 i
.types
[op
].bitfield
.disp16
= 0;
6341 i
.types
[op
].bitfield
.disp32
= 0;
6342 i
.types
[op
].bitfield
.disp32s
= 1;
6343 i
.types
[op
].bitfield
.disp64
= 0;
6344 i
.types
[op
].bitfield
.vec_disp8
= 0;
6345 i
.flags
[op
] |= Operand_PCrel
;
6346 if (! i
.disp_operands
)
6347 fake_zero_displacement
= 1;
6349 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6351 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6352 switch (i
.base_reg
->reg_num
)
6355 if (i
.index_reg
== 0)
6357 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6358 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6362 if (i
.index_reg
== 0)
6365 if (operand_type_check (i
.types
[op
], disp
) == 0)
6367 /* fake (%bp) into 0(%bp) */
6368 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6369 i
.types
[op
].bitfield
.vec_disp8
= 1;
6371 i
.types
[op
].bitfield
.disp8
= 1;
6372 fake_zero_displacement
= 1;
6375 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6376 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6378 default: /* (%si) -> 4 or (%di) -> 5 */
6379 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6381 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6383 else /* i.base_reg and 32/64 bit mode */
6385 if (flag_code
== CODE_64BIT
6386 && operand_type_check (i
.types
[op
], disp
))
6388 i386_operand_type temp
;
6389 operand_type_set (&temp
, 0);
6390 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6391 temp
.bitfield
.vec_disp8
6392 = i
.types
[op
].bitfield
.vec_disp8
;
6394 if (i
.prefix
[ADDR_PREFIX
] == 0)
6395 i
.types
[op
].bitfield
.disp32s
= 1;
6397 i
.types
[op
].bitfield
.disp32
= 1;
6400 if (!i
.tm
.opcode_modifier
.vecsib
)
6401 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6402 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6404 i
.sib
.base
= i
.base_reg
->reg_num
;
6405 /* x86-64 ignores REX prefix bit here to avoid decoder
6407 if (!(i
.base_reg
->reg_flags
& RegRex
)
6408 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6409 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6411 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6413 fake_zero_displacement
= 1;
6414 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6415 i
.types
[op
].bitfield
.vec_disp8
= 1;
6417 i
.types
[op
].bitfield
.disp8
= 1;
6419 i
.sib
.scale
= i
.log2_scale_factor
;
6420 if (i
.index_reg
== 0)
6422 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6423 /* <disp>(%esp) becomes two byte modrm with no index
6424 register. We've already stored the code for esp
6425 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6426 Any base register besides %esp will not use the
6427 extra modrm byte. */
6428 i
.sib
.index
= NO_INDEX_REGISTER
;
6430 else if (!i
.tm
.opcode_modifier
.vecsib
)
6432 if (i
.index_reg
->reg_num
== RegEiz
6433 || i
.index_reg
->reg_num
== RegRiz
)
6434 i
.sib
.index
= NO_INDEX_REGISTER
;
6436 i
.sib
.index
= i
.index_reg
->reg_num
;
6437 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6438 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6443 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6444 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6448 if (!fake_zero_displacement
6452 fake_zero_displacement
= 1;
6453 if (i
.disp_encoding
== disp_encoding_8bit
)
6454 i
.types
[op
].bitfield
.disp8
= 1;
6456 i
.types
[op
].bitfield
.disp32
= 1;
6458 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6462 if (fake_zero_displacement
)
6464 /* Fakes a zero displacement assuming that i.types[op]
6465 holds the correct displacement size. */
6468 gas_assert (i
.op
[op
].disps
== 0);
6469 exp
= &disp_expressions
[i
.disp_operands
++];
6470 i
.op
[op
].disps
= exp
;
6471 exp
->X_op
= O_constant
;
6472 exp
->X_add_number
= 0;
6473 exp
->X_add_symbol
= (symbolS
*) 0;
6474 exp
->X_op_symbol
= (symbolS
*) 0;
6482 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6484 if (operand_type_check (i
.types
[0], imm
))
6485 i
.vex
.register_specifier
= NULL
;
6488 /* VEX.vvvv encodes one of the sources when the first
6489 operand is not an immediate. */
6490 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6491 i
.vex
.register_specifier
= i
.op
[0].regs
;
6493 i
.vex
.register_specifier
= i
.op
[1].regs
;
6496 /* Destination is a XMM register encoded in the ModRM.reg
6498 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6499 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6502 /* ModRM.rm and VEX.B encodes the other source. */
6503 if (!i
.mem_operands
)
6507 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6508 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6510 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6512 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6516 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6518 i
.vex
.register_specifier
= i
.op
[2].regs
;
6519 if (!i
.mem_operands
)
6522 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6523 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6527 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6528 (if any) based on i.tm.extension_opcode. Again, we must be
6529 careful to make sure that segment/control/debug/test/MMX
6530 registers are coded into the i.rm.reg field. */
6531 else if (i
.reg_operands
)
6534 unsigned int vex_reg
= ~0;
6536 for (op
= 0; op
< i
.operands
; op
++)
6537 if (i
.types
[op
].bitfield
.reg8
6538 || i
.types
[op
].bitfield
.reg16
6539 || i
.types
[op
].bitfield
.reg32
6540 || i
.types
[op
].bitfield
.reg64
6541 || i
.types
[op
].bitfield
.regmmx
6542 || i
.types
[op
].bitfield
.regxmm
6543 || i
.types
[op
].bitfield
.regymm
6544 || i
.types
[op
].bitfield
.regbnd
6545 || i
.types
[op
].bitfield
.regzmm
6546 || i
.types
[op
].bitfield
.regmask
6547 || i
.types
[op
].bitfield
.sreg2
6548 || i
.types
[op
].bitfield
.sreg3
6549 || i
.types
[op
].bitfield
.control
6550 || i
.types
[op
].bitfield
.debug
6551 || i
.types
[op
].bitfield
.test
)
6556 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6558 /* For instructions with VexNDS, the register-only
6559 source operand is encoded in VEX prefix. */
6560 gas_assert (mem
!= (unsigned int) ~0);
6565 gas_assert (op
< i
.operands
);
6569 /* Check register-only source operand when two source
6570 operands are swapped. */
6571 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6572 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6576 gas_assert (mem
== (vex_reg
+ 1)
6577 && op
< i
.operands
);
6582 gas_assert (vex_reg
< i
.operands
);
6586 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6588 /* For instructions with VexNDD, the register destination
6589 is encoded in VEX prefix. */
6590 if (i
.mem_operands
== 0)
6592 /* There is no memory operand. */
6593 gas_assert ((op
+ 2) == i
.operands
);
6598 /* There are only 2 operands. */
6599 gas_assert (op
< 2 && i
.operands
== 2);
6604 gas_assert (op
< i
.operands
);
6606 if (vex_reg
!= (unsigned int) ~0)
6608 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6610 if (type
->bitfield
.reg32
!= 1
6611 && type
->bitfield
.reg64
!= 1
6612 && !operand_type_equal (type
, ®xmm
)
6613 && !operand_type_equal (type
, ®ymm
)
6614 && !operand_type_equal (type
, ®zmm
)
6615 && !operand_type_equal (type
, ®mask
))
6618 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6621 /* Don't set OP operand twice. */
6624 /* If there is an extension opcode to put here, the
6625 register number must be put into the regmem field. */
6626 if (i
.tm
.extension_opcode
!= None
)
6628 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6629 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6631 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6636 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6637 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6639 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6644 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6645 must set it to 3 to indicate this is a register operand
6646 in the regmem field. */
6647 if (!i
.mem_operands
)
6651 /* Fill in i.rm.reg field with extension opcode (if any). */
6652 if (i
.tm
.extension_opcode
!= None
)
6653 i
.rm
.reg
= i
.tm
.extension_opcode
;
6659 output_branch (void)
6665 relax_substateT subtype
;
6669 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6670 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6673 if (i
.prefix
[DATA_PREFIX
] != 0)
6679 /* Pentium4 branch hints. */
6680 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6681 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6686 if (i
.prefix
[REX_PREFIX
] != 0)
6692 /* BND prefixed jump. */
6693 if (i
.prefix
[BND_PREFIX
] != 0)
6695 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6699 if (i
.prefixes
!= 0 && !intel_syntax
)
6700 as_warn (_("skipping prefixes on this instruction"));
6702 /* It's always a symbol; End frag & setup for relax.
6703 Make sure there is enough room in this frag for the largest
6704 instruction we may generate in md_convert_frag. This is 2
6705 bytes for the opcode and room for the prefix and largest
6707 frag_grow (prefix
+ 2 + 4);
6708 /* Prefix and 1 opcode byte go in fr_fix. */
6709 p
= frag_more (prefix
+ 1);
6710 if (i
.prefix
[DATA_PREFIX
] != 0)
6711 *p
++ = DATA_PREFIX_OPCODE
;
6712 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6713 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6714 *p
++ = i
.prefix
[SEG_PREFIX
];
6715 if (i
.prefix
[REX_PREFIX
] != 0)
6716 *p
++ = i
.prefix
[REX_PREFIX
];
6717 *p
= i
.tm
.base_opcode
;
6719 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6720 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6721 else if (cpu_arch_flags
.bitfield
.cpui386
)
6722 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6724 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6727 sym
= i
.op
[0].disps
->X_add_symbol
;
6728 off
= i
.op
[0].disps
->X_add_number
;
6730 if (i
.op
[0].disps
->X_op
!= O_constant
6731 && i
.op
[0].disps
->X_op
!= O_symbol
)
6733 /* Handle complex expressions. */
6734 sym
= make_expr_symbol (i
.op
[0].disps
);
6738 /* 1 possible extra opcode + 4 byte displacement go in var part.
6739 Pass reloc in fr_var. */
6740 frag_var (rs_machine_dependent
, 5,
6742 || i
.reloc
[0] != NO_RELOC
6743 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6745 : BFD_RELOC_X86_64_PC32_BND
),
6746 subtype
, sym
, off
, p
);
6756 if (i
.tm
.opcode_modifier
.jumpbyte
)
6758 /* This is a loop or jecxz type instruction. */
6760 if (i
.prefix
[ADDR_PREFIX
] != 0)
6762 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6765 /* Pentium4 branch hints. */
6766 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6767 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6769 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6778 if (flag_code
== CODE_16BIT
)
6781 if (i
.prefix
[DATA_PREFIX
] != 0)
6783 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6793 if (i
.prefix
[REX_PREFIX
] != 0)
6795 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6799 /* BND prefixed jump. */
6800 if (i
.prefix
[BND_PREFIX
] != 0)
6802 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6806 if (i
.prefixes
!= 0 && !intel_syntax
)
6807 as_warn (_("skipping prefixes on this instruction"));
6809 p
= frag_more (i
.tm
.opcode_length
+ size
);
6810 switch (i
.tm
.opcode_length
)
6813 *p
++ = i
.tm
.base_opcode
>> 8;
6815 *p
++ = i
.tm
.base_opcode
;
6821 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6822 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6823 (i
.bnd_prefix
!= NULL
6827 /* All jumps handled here are signed, but don't use a signed limit
6828 check for 32 and 16 bit jumps as we want to allow wrap around at
6829 4G and 64k respectively. */
6831 fixP
->fx_signed
= 1;
6835 output_interseg_jump (void)
6843 if (flag_code
== CODE_16BIT
)
6847 if (i
.prefix
[DATA_PREFIX
] != 0)
6853 if (i
.prefix
[REX_PREFIX
] != 0)
6863 if (i
.prefixes
!= 0 && !intel_syntax
)
6864 as_warn (_("skipping prefixes on this instruction"));
6866 /* 1 opcode; 2 segment; offset */
6867 p
= frag_more (prefix
+ 1 + 2 + size
);
6869 if (i
.prefix
[DATA_PREFIX
] != 0)
6870 *p
++ = DATA_PREFIX_OPCODE
;
6872 if (i
.prefix
[REX_PREFIX
] != 0)
6873 *p
++ = i
.prefix
[REX_PREFIX
];
6875 *p
++ = i
.tm
.base_opcode
;
6876 if (i
.op
[1].imms
->X_op
== O_constant
)
6878 offsetT n
= i
.op
[1].imms
->X_add_number
;
6881 && !fits_in_unsigned_word (n
)
6882 && !fits_in_signed_word (n
))
6884 as_bad (_("16-bit jump out of range"));
6887 md_number_to_chars (p
, n
, size
);
6890 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6891 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6892 if (i
.op
[0].imms
->X_op
!= O_constant
)
6893 as_bad (_("can't handle non absolute segment in `%s'"),
6895 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6901 fragS
*insn_start_frag
;
6902 offsetT insn_start_off
;
6904 /* Tie dwarf2 debug info to the address at the start of the insn.
6905 We can't do this after the insn has been output as the current
6906 frag may have been closed off. eg. by frag_var. */
6907 dwarf2_emit_insn (0);
6909 insn_start_frag
= frag_now
;
6910 insn_start_off
= frag_now_fix ();
6913 if (i
.tm
.opcode_modifier
.jump
)
6915 else if (i
.tm
.opcode_modifier
.jumpbyte
6916 || i
.tm
.opcode_modifier
.jumpdword
)
6918 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6919 output_interseg_jump ();
6922 /* Output normal instructions here. */
6926 unsigned int prefix
;
6928 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6929 don't need the explicit prefix. */
6930 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6932 switch (i
.tm
.opcode_length
)
6935 if (i
.tm
.base_opcode
& 0xff000000)
6937 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6942 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6944 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6945 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6948 if (prefix
!= REPE_PREFIX_OPCODE
6949 || (i
.prefix
[REP_PREFIX
]
6950 != REPE_PREFIX_OPCODE
))
6951 add_prefix (prefix
);
6954 add_prefix (prefix
);
6963 /* The prefix bytes. */
6964 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6966 FRAG_APPEND_1_CHAR (*q
);
6970 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6975 /* REX byte is encoded in VEX prefix. */
6979 FRAG_APPEND_1_CHAR (*q
);
6982 /* There should be no other prefixes for instructions
6987 /* For EVEX instructions i.vrex should become 0 after
6988 build_evex_prefix. For VEX instructions upper 16 registers
6989 aren't available, so VREX should be 0. */
6992 /* Now the VEX prefix. */
6993 p
= frag_more (i
.vex
.length
);
6994 for (j
= 0; j
< i
.vex
.length
; j
++)
6995 p
[j
] = i
.vex
.bytes
[j
];
6998 /* Now the opcode; be careful about word order here! */
6999 if (i
.tm
.opcode_length
== 1)
7001 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7005 switch (i
.tm
.opcode_length
)
7009 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7010 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7014 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7024 /* Put out high byte first: can't use md_number_to_chars! */
7025 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7026 *p
= i
.tm
.base_opcode
& 0xff;
7029 /* Now the modrm byte and sib byte (if present). */
7030 if (i
.tm
.opcode_modifier
.modrm
)
7032 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7035 /* If i.rm.regmem == ESP (4)
7036 && i.rm.mode != (Register mode)
7038 ==> need second modrm byte. */
7039 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7041 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7042 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7044 | i
.sib
.scale
<< 6));
7047 if (i
.disp_operands
)
7048 output_disp (insn_start_frag
, insn_start_off
);
7051 output_imm (insn_start_frag
, insn_start_off
);
7057 pi ("" /*line*/, &i
);
7059 #endif /* DEBUG386 */
7062 /* Return the size of the displacement operand N. */
7065 disp_size (unsigned int n
)
7069 /* Vec_Disp8 has to be 8bit. */
7070 if (i
.types
[n
].bitfield
.vec_disp8
)
7072 else if (i
.types
[n
].bitfield
.disp64
)
7074 else if (i
.types
[n
].bitfield
.disp8
)
7076 else if (i
.types
[n
].bitfield
.disp16
)
7081 /* Return the size of the immediate operand N. */
7084 imm_size (unsigned int n
)
7087 if (i
.types
[n
].bitfield
.imm64
)
7089 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7091 else if (i
.types
[n
].bitfield
.imm16
)
7097 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7102 for (n
= 0; n
< i
.operands
; n
++)
7104 if (i
.types
[n
].bitfield
.vec_disp8
7105 || operand_type_check (i
.types
[n
], disp
))
7107 if (i
.op
[n
].disps
->X_op
== O_constant
)
7109 int size
= disp_size (n
);
7110 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7112 if (i
.types
[n
].bitfield
.vec_disp8
)
7114 val
= offset_in_range (val
, size
);
7115 p
= frag_more (size
);
7116 md_number_to_chars (p
, val
, size
);
7120 enum bfd_reloc_code_real reloc_type
;
7121 int size
= disp_size (n
);
7122 int sign
= i
.types
[n
].bitfield
.disp32s
;
7123 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7125 /* We can't have 8 bit displacement here. */
7126 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7128 /* The PC relative address is computed relative
7129 to the instruction boundary, so in case immediate
7130 fields follows, we need to adjust the value. */
7131 if (pcrel
&& i
.imm_operands
)
7136 for (n1
= 0; n1
< i
.operands
; n1
++)
7137 if (operand_type_check (i
.types
[n1
], imm
))
7139 /* Only one immediate is allowed for PC
7140 relative address. */
7141 gas_assert (sz
== 0);
7143 i
.op
[n
].disps
->X_add_number
-= sz
;
7145 /* We should find the immediate. */
7146 gas_assert (sz
!= 0);
7149 p
= frag_more (size
);
7150 reloc_type
= reloc (size
, pcrel
, sign
,
7151 (i
.bnd_prefix
!= NULL
7155 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7156 && (((reloc_type
== BFD_RELOC_32
7157 || reloc_type
== BFD_RELOC_X86_64_32S
7158 || (reloc_type
== BFD_RELOC_64
7160 && (i
.op
[n
].disps
->X_op
== O_symbol
7161 || (i
.op
[n
].disps
->X_op
== O_add
7162 && ((symbol_get_value_expression
7163 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7165 || reloc_type
== BFD_RELOC_32_PCREL
))
7169 if (insn_start_frag
== frag_now
)
7170 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7175 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7176 for (fr
= insn_start_frag
->fr_next
;
7177 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7179 add
+= p
- frag_now
->fr_literal
;
7184 reloc_type
= BFD_RELOC_386_GOTPC
;
7185 i
.op
[n
].imms
->X_add_number
+= add
;
7187 else if (reloc_type
== BFD_RELOC_64
)
7188 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7190 /* Don't do the adjustment for x86-64, as there
7191 the pcrel addressing is relative to the _next_
7192 insn, and that is taken care of in other code. */
7193 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7195 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7196 i
.op
[n
].disps
, pcrel
, reloc_type
);
7203 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7208 for (n
= 0; n
< i
.operands
; n
++)
7210 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7211 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7214 if (operand_type_check (i
.types
[n
], imm
))
7216 if (i
.op
[n
].imms
->X_op
== O_constant
)
7218 int size
= imm_size (n
);
7221 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7223 p
= frag_more (size
);
7224 md_number_to_chars (p
, val
, size
);
7228 /* Not absolute_section.
7229 Need a 32-bit fixup (don't support 8bit
7230 non-absolute imms). Try to support other
7232 enum bfd_reloc_code_real reloc_type
;
7233 int size
= imm_size (n
);
7236 if (i
.types
[n
].bitfield
.imm32s
7237 && (i
.suffix
== QWORD_MNEM_SUFFIX
7238 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7243 p
= frag_more (size
);
7244 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7246 /* This is tough to explain. We end up with this one if we
7247 * have operands that look like
7248 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7249 * obtain the absolute address of the GOT, and it is strongly
7250 * preferable from a performance point of view to avoid using
7251 * a runtime relocation for this. The actual sequence of
7252 * instructions often look something like:
7257 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7259 * The call and pop essentially return the absolute address
7260 * of the label .L66 and store it in %ebx. The linker itself
7261 * will ultimately change the first operand of the addl so
7262 * that %ebx points to the GOT, but to keep things simple, the
7263 * .o file must have this operand set so that it generates not
7264 * the absolute address of .L66, but the absolute address of
7265 * itself. This allows the linker itself simply treat a GOTPC
7266 * relocation as asking for a pcrel offset to the GOT to be
7267 * added in, and the addend of the relocation is stored in the
7268 * operand field for the instruction itself.
7270 * Our job here is to fix the operand so that it would add
7271 * the correct offset so that %ebx would point to itself. The
7272 * thing that is tricky is that .-.L66 will point to the
7273 * beginning of the instruction, so we need to further modify
7274 * the operand so that it will point to itself. There are
7275 * other cases where you have something like:
7277 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7279 * and here no correction would be required. Internally in
7280 * the assembler we treat operands of this form as not being
7281 * pcrel since the '.' is explicitly mentioned, and I wonder
7282 * whether it would simplify matters to do it this way. Who
7283 * knows. In earlier versions of the PIC patches, the
7284 * pcrel_adjust field was used to store the correction, but
7285 * since the expression is not pcrel, I felt it would be
7286 * confusing to do it this way. */
7288 if ((reloc_type
== BFD_RELOC_32
7289 || reloc_type
== BFD_RELOC_X86_64_32S
7290 || reloc_type
== BFD_RELOC_64
)
7292 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7293 && (i
.op
[n
].imms
->X_op
== O_symbol
7294 || (i
.op
[n
].imms
->X_op
== O_add
7295 && ((symbol_get_value_expression
7296 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7301 if (insn_start_frag
== frag_now
)
7302 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7307 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7308 for (fr
= insn_start_frag
->fr_next
;
7309 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7311 add
+= p
- frag_now
->fr_literal
;
7315 reloc_type
= BFD_RELOC_386_GOTPC
;
7317 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7319 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7320 i
.op
[n
].imms
->X_add_number
+= add
;
7322 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7323 i
.op
[n
].imms
, 0, reloc_type
);
7329 /* x86_cons_fix_new is called via the expression parsing code when a
7330 reloc is needed. We use this hook to get the correct .got reloc. */
7331 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
7332 static int cons_sign
= -1;
7335 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7338 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, 0, got_reloc
);
7340 got_reloc
= NO_RELOC
;
7343 if (exp
->X_op
== O_secrel
)
7345 exp
->X_op
= O_symbol
;
7346 r
= BFD_RELOC_32_SECREL
;
7350 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7353 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7354 purpose of the `.dc.a' internal pseudo-op. */
7357 x86_address_bytes (void)
7359 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7361 return stdoutput
->arch_info
->bits_per_address
/ 8;
7364 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7366 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7368 /* Parse operands of the form
7369 <symbol>@GOTOFF+<nnn>
7370 and similar .plt or .got references.
7372 If we find one, set up the correct relocation in RELOC and copy the
7373 input string, minus the `@GOTOFF' into a malloc'd buffer for
7374 parsing by the calling routine. Return this buffer, and if ADJUST
7375 is non-null set it to the length of the string we removed from the
7376 input line. Otherwise return NULL. */
7378 lex_got (enum bfd_reloc_code_real
*rel
,
7380 i386_operand_type
*types
,
7383 /* Some of the relocations depend on the size of what field is to
7384 be relocated. But in our callers i386_immediate and i386_displacement
7385 we don't yet know the operand size (this will be set by insn
7386 matching). Hence we record the word32 relocation here,
7387 and adjust the reloc according to the real size in reloc(). */
7388 static const struct {
7391 const enum bfd_reloc_code_real rel
[2];
7392 const i386_operand_type types64
;
7394 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7395 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7397 OPERAND_TYPE_IMM32_64
},
7399 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7400 BFD_RELOC_X86_64_PLTOFF64
},
7401 OPERAND_TYPE_IMM64
},
7402 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7403 BFD_RELOC_X86_64_PLT32
},
7404 OPERAND_TYPE_IMM32_32S_DISP32
},
7405 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7406 BFD_RELOC_X86_64_GOTPLT64
},
7407 OPERAND_TYPE_IMM64_DISP64
},
7408 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7409 BFD_RELOC_X86_64_GOTOFF64
},
7410 OPERAND_TYPE_IMM64_DISP64
},
7411 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7412 BFD_RELOC_X86_64_GOTPCREL
},
7413 OPERAND_TYPE_IMM32_32S_DISP32
},
7414 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7415 BFD_RELOC_X86_64_TLSGD
},
7416 OPERAND_TYPE_IMM32_32S_DISP32
},
7417 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7418 _dummy_first_bfd_reloc_code_real
},
7419 OPERAND_TYPE_NONE
},
7420 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7421 BFD_RELOC_X86_64_TLSLD
},
7422 OPERAND_TYPE_IMM32_32S_DISP32
},
7423 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7424 BFD_RELOC_X86_64_GOTTPOFF
},
7425 OPERAND_TYPE_IMM32_32S_DISP32
},
7426 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7427 BFD_RELOC_X86_64_TPOFF32
},
7428 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7429 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7430 _dummy_first_bfd_reloc_code_real
},
7431 OPERAND_TYPE_NONE
},
7432 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7433 BFD_RELOC_X86_64_DTPOFF32
},
7434 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7435 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7436 _dummy_first_bfd_reloc_code_real
},
7437 OPERAND_TYPE_NONE
},
7438 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7439 _dummy_first_bfd_reloc_code_real
},
7440 OPERAND_TYPE_NONE
},
7441 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7442 BFD_RELOC_X86_64_GOT32
},
7443 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7444 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7445 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7446 OPERAND_TYPE_IMM32_32S_DISP32
},
7447 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7448 BFD_RELOC_X86_64_TLSDESC_CALL
},
7449 OPERAND_TYPE_IMM32_32S_DISP32
},
7454 #if defined (OBJ_MAYBE_ELF)
7459 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7460 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7463 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7465 int len
= gotrel
[j
].len
;
7466 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7468 if (gotrel
[j
].rel
[object_64bit
] != 0)
7471 char *tmpbuf
, *past_reloc
;
7473 *rel
= gotrel
[j
].rel
[object_64bit
];
7477 if (flag_code
!= CODE_64BIT
)
7479 types
->bitfield
.imm32
= 1;
7480 types
->bitfield
.disp32
= 1;
7483 *types
= gotrel
[j
].types64
;
7486 if (j
!= 0 && GOT_symbol
== NULL
)
7487 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7489 /* The length of the first part of our input line. */
7490 first
= cp
- input_line_pointer
;
7492 /* The second part goes from after the reloc token until
7493 (and including) an end_of_line char or comma. */
7494 past_reloc
= cp
+ 1 + len
;
7496 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7498 second
= cp
+ 1 - past_reloc
;
7500 /* Allocate and copy string. The trailing NUL shouldn't
7501 be necessary, but be safe. */
7502 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7503 memcpy (tmpbuf
, input_line_pointer
, first
);
7504 if (second
!= 0 && *past_reloc
!= ' ')
7505 /* Replace the relocation token with ' ', so that
7506 errors like foo@GOTOFF1 will be detected. */
7507 tmpbuf
[first
++] = ' ';
7509 /* Increment length by 1 if the relocation token is
7514 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7515 tmpbuf
[first
+ second
] = '\0';
7516 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7517 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7521 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7522 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7527 /* Might be a symbol version string. Don't as_bad here. */
7536 /* Parse operands of the form
7537 <symbol>@SECREL32+<nnn>
7539 If we find one, set up the correct relocation in RELOC and copy the
7540 input string, minus the `@SECREL32' into a malloc'd buffer for
7541 parsing by the calling routine. Return this buffer, and if ADJUST
7542 is non-null set it to the length of the string we removed from the
7543 input line. Otherwise return NULL.
7545 This function is copied from the ELF version above adjusted for PE targets. */
7548 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7549 int *adjust ATTRIBUTE_UNUSED
,
7550 i386_operand_type
*types
,
7551 int bnd_prefix ATTRIBUTE_UNUSED
)
7557 const enum bfd_reloc_code_real rel
[2];
7558 const i386_operand_type types64
;
7562 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7563 BFD_RELOC_32_SECREL
},
7564 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7570 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7571 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7574 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7576 int len
= gotrel
[j
].len
;
7578 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7580 if (gotrel
[j
].rel
[object_64bit
] != 0)
7583 char *tmpbuf
, *past_reloc
;
7585 *rel
= gotrel
[j
].rel
[object_64bit
];
7591 if (flag_code
!= CODE_64BIT
)
7593 types
->bitfield
.imm32
= 1;
7594 types
->bitfield
.disp32
= 1;
7597 *types
= gotrel
[j
].types64
;
7600 /* The length of the first part of our input line. */
7601 first
= cp
- input_line_pointer
;
7603 /* The second part goes from after the reloc token until
7604 (and including) an end_of_line char or comma. */
7605 past_reloc
= cp
+ 1 + len
;
7607 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7609 second
= cp
+ 1 - past_reloc
;
7611 /* Allocate and copy string. The trailing NUL shouldn't
7612 be necessary, but be safe. */
7613 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7614 memcpy (tmpbuf
, input_line_pointer
, first
);
7615 if (second
!= 0 && *past_reloc
!= ' ')
7616 /* Replace the relocation token with ' ', so that
7617 errors like foo@SECLREL321 will be detected. */
7618 tmpbuf
[first
++] = ' ';
7619 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7620 tmpbuf
[first
+ second
] = '\0';
7624 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7625 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7630 /* Might be a symbol version string. Don't as_bad here. */
7637 x86_cons (expressionS
*exp
, int size
)
7639 intel_syntax
= -intel_syntax
;
7642 if (size
== 4 || (object_64bit
&& size
== 8))
7644 /* Handle @GOTOFF and the like in an expression. */
7646 char *gotfree_input_line
;
7649 save
= input_line_pointer
;
7650 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7651 if (gotfree_input_line
)
7652 input_line_pointer
= gotfree_input_line
;
7656 if (gotfree_input_line
)
7658 /* expression () has merrily parsed up to the end of line,
7659 or a comma - in the wrong buffer. Transfer how far
7660 input_line_pointer has moved to the right buffer. */
7661 input_line_pointer
= (save
7662 + (input_line_pointer
- gotfree_input_line
)
7664 free (gotfree_input_line
);
7665 if (exp
->X_op
== O_constant
7666 || exp
->X_op
== O_absent
7667 || exp
->X_op
== O_illegal
7668 || exp
->X_op
== O_register
7669 || exp
->X_op
== O_big
)
7671 char c
= *input_line_pointer
;
7672 *input_line_pointer
= 0;
7673 as_bad (_("missing or invalid expression `%s'"), save
);
7674 *input_line_pointer
= c
;
7681 intel_syntax
= -intel_syntax
;
7684 i386_intel_simplify (exp
);
7688 signed_cons (int size
)
7690 if (flag_code
== CODE_64BIT
)
7698 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7705 if (exp
.X_op
== O_symbol
)
7706 exp
.X_op
= O_secrel
;
7708 emit_expr (&exp
, 4);
7710 while (*input_line_pointer
++ == ',');
7712 input_line_pointer
--;
7713 demand_empty_rest_of_line ();
7717 /* Handle Vector operations. */
7720 check_VecOperations (char *op_string
, char *op_end
)
7722 const reg_entry
*mask
;
7727 && (op_end
== NULL
|| op_string
< op_end
))
7730 if (*op_string
== '{')
7734 /* Check broadcasts. */
7735 if (strncmp (op_string
, "1to", 3) == 0)
7740 goto duplicated_vec_op
;
7743 if (*op_string
== '8')
7744 bcst_type
= BROADCAST_1TO8
;
7745 else if (*op_string
== '1'
7746 && *(op_string
+1) == '6')
7748 bcst_type
= BROADCAST_1TO16
;
7753 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7758 broadcast_op
.type
= bcst_type
;
7759 broadcast_op
.operand
= this_operand
;
7760 i
.broadcast
= &broadcast_op
;
7762 /* Check masking operation. */
7763 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7765 /* k0 can't be used for write mask. */
7766 if (mask
->reg_num
== 0)
7768 as_bad (_("`%s' can't be used for write mask"),
7775 mask_op
.mask
= mask
;
7776 mask_op
.zeroing
= 0;
7777 mask_op
.operand
= this_operand
;
7783 goto duplicated_vec_op
;
7785 i
.mask
->mask
= mask
;
7787 /* Only "{z}" is allowed here. No need to check
7788 zeroing mask explicitly. */
7789 if (i
.mask
->operand
!= this_operand
)
7791 as_bad (_("invalid write mask `%s'"), saved
);
7798 /* Check zeroing-flag for masking operation. */
7799 else if (*op_string
== 'z')
7803 mask_op
.mask
= NULL
;
7804 mask_op
.zeroing
= 1;
7805 mask_op
.operand
= this_operand
;
7810 if (i
.mask
->zeroing
)
7813 as_bad (_("duplicated `%s'"), saved
);
7817 i
.mask
->zeroing
= 1;
7819 /* Only "{%k}" is allowed here. No need to check mask
7820 register explicitly. */
7821 if (i
.mask
->operand
!= this_operand
)
7823 as_bad (_("invalid zeroing-masking `%s'"),
7832 goto unknown_vec_op
;
7834 if (*op_string
!= '}')
7836 as_bad (_("missing `}' in `%s'"), saved
);
7843 /* We don't know this one. */
7844 as_bad (_("unknown vector operation: `%s'"), saved
);
7852 i386_immediate (char *imm_start
)
7854 char *save_input_line_pointer
;
7855 char *gotfree_input_line
;
7858 i386_operand_type types
;
7860 operand_type_set (&types
, ~0);
7862 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7864 as_bad (_("at most %d immediate operands are allowed"),
7865 MAX_IMMEDIATE_OPERANDS
);
7869 exp
= &im_expressions
[i
.imm_operands
++];
7870 i
.op
[this_operand
].imms
= exp
;
7872 if (is_space_char (*imm_start
))
7875 save_input_line_pointer
= input_line_pointer
;
7876 input_line_pointer
= imm_start
;
7878 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7879 (i
.bnd_prefix
!= NULL
7880 || add_bnd_prefix
));
7881 if (gotfree_input_line
)
7882 input_line_pointer
= gotfree_input_line
;
7884 exp_seg
= expression (exp
);
7888 /* Handle vector operations. */
7889 if (*input_line_pointer
== '{')
7891 input_line_pointer
= check_VecOperations (input_line_pointer
,
7893 if (input_line_pointer
== NULL
)
7897 if (*input_line_pointer
)
7898 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7900 input_line_pointer
= save_input_line_pointer
;
7901 if (gotfree_input_line
)
7903 free (gotfree_input_line
);
7905 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7906 exp
->X_op
= O_illegal
;
7909 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7913 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7914 i386_operand_type types
, const char *imm_start
)
7916 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7919 as_bad (_("missing or invalid immediate expression `%s'"),
7923 else if (exp
->X_op
== O_constant
)
7925 /* Size it properly later. */
7926 i
.types
[this_operand
].bitfield
.imm64
= 1;
7927 /* If not 64bit, sign extend val. */
7928 if (flag_code
!= CODE_64BIT
7929 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7931 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7933 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7934 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7935 && exp_seg
!= absolute_section
7936 && exp_seg
!= text_section
7937 && exp_seg
!= data_section
7938 && exp_seg
!= bss_section
7939 && exp_seg
!= undefined_section
7940 && !bfd_is_com_section (exp_seg
))
7942 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7946 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7949 as_bad (_("illegal immediate register operand %s"), imm_start
);
7954 /* This is an address. The size of the address will be
7955 determined later, depending on destination register,
7956 suffix, or the default for the section. */
7957 i
.types
[this_operand
].bitfield
.imm8
= 1;
7958 i
.types
[this_operand
].bitfield
.imm16
= 1;
7959 i
.types
[this_operand
].bitfield
.imm32
= 1;
7960 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7961 i
.types
[this_operand
].bitfield
.imm64
= 1;
7962 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7970 i386_scale (char *scale
)
7973 char *save
= input_line_pointer
;
7975 input_line_pointer
= scale
;
7976 val
= get_absolute_expression ();
7981 i
.log2_scale_factor
= 0;
7984 i
.log2_scale_factor
= 1;
7987 i
.log2_scale_factor
= 2;
7990 i
.log2_scale_factor
= 3;
7994 char sep
= *input_line_pointer
;
7996 *input_line_pointer
= '\0';
7997 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7999 *input_line_pointer
= sep
;
8000 input_line_pointer
= save
;
8004 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8006 as_warn (_("scale factor of %d without an index register"),
8007 1 << i
.log2_scale_factor
);
8008 i
.log2_scale_factor
= 0;
8010 scale
= input_line_pointer
;
8011 input_line_pointer
= save
;
8016 i386_displacement (char *disp_start
, char *disp_end
)
8020 char *save_input_line_pointer
;
8021 char *gotfree_input_line
;
8023 i386_operand_type bigdisp
, types
= anydisp
;
8026 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8028 as_bad (_("at most %d displacement operands are allowed"),
8029 MAX_MEMORY_OPERANDS
);
8033 operand_type_set (&bigdisp
, 0);
8034 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8035 || (!current_templates
->start
->opcode_modifier
.jump
8036 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8038 bigdisp
.bitfield
.disp32
= 1;
8039 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8040 if (flag_code
== CODE_64BIT
)
8044 bigdisp
.bitfield
.disp32s
= 1;
8045 bigdisp
.bitfield
.disp64
= 1;
8048 else if ((flag_code
== CODE_16BIT
) ^ override
)
8050 bigdisp
.bitfield
.disp32
= 0;
8051 bigdisp
.bitfield
.disp16
= 1;
8056 /* For PC-relative branches, the width of the displacement
8057 is dependent upon data size, not address size. */
8058 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8059 if (flag_code
== CODE_64BIT
)
8061 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8062 bigdisp
.bitfield
.disp16
= 1;
8065 bigdisp
.bitfield
.disp32
= 1;
8066 bigdisp
.bitfield
.disp32s
= 1;
8072 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8074 : LONG_MNEM_SUFFIX
));
8075 bigdisp
.bitfield
.disp32
= 1;
8076 if ((flag_code
== CODE_16BIT
) ^ override
)
8078 bigdisp
.bitfield
.disp32
= 0;
8079 bigdisp
.bitfield
.disp16
= 1;
8083 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8086 exp
= &disp_expressions
[i
.disp_operands
];
8087 i
.op
[this_operand
].disps
= exp
;
8089 save_input_line_pointer
= input_line_pointer
;
8090 input_line_pointer
= disp_start
;
8091 END_STRING_AND_SAVE (disp_end
);
8093 #ifndef GCC_ASM_O_HACK
8094 #define GCC_ASM_O_HACK 0
8097 END_STRING_AND_SAVE (disp_end
+ 1);
8098 if (i
.types
[this_operand
].bitfield
.baseIndex
8099 && displacement_string_end
[-1] == '+')
8101 /* This hack is to avoid a warning when using the "o"
8102 constraint within gcc asm statements.
8105 #define _set_tssldt_desc(n,addr,limit,type) \
8106 __asm__ __volatile__ ( \
8108 "movw %w1,2+%0\n\t" \
8110 "movb %b1,4+%0\n\t" \
8111 "movb %4,5+%0\n\t" \
8112 "movb $0,6+%0\n\t" \
8113 "movb %h1,7+%0\n\t" \
8115 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8117 This works great except that the output assembler ends
8118 up looking a bit weird if it turns out that there is
8119 no offset. You end up producing code that looks like:
8132 So here we provide the missing zero. */
8134 *displacement_string_end
= '0';
8137 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8138 (i
.bnd_prefix
!= NULL
8139 || add_bnd_prefix
));
8140 if (gotfree_input_line
)
8141 input_line_pointer
= gotfree_input_line
;
8143 exp_seg
= expression (exp
);
8146 if (*input_line_pointer
)
8147 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8149 RESTORE_END_STRING (disp_end
+ 1);
8151 input_line_pointer
= save_input_line_pointer
;
8152 if (gotfree_input_line
)
8154 free (gotfree_input_line
);
8156 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8157 exp
->X_op
= O_illegal
;
8160 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8162 RESTORE_END_STRING (disp_end
);
8168 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8169 i386_operand_type types
, const char *disp_start
)
8171 i386_operand_type bigdisp
;
8174 /* We do this to make sure that the section symbol is in
8175 the symbol table. We will ultimately change the relocation
8176 to be relative to the beginning of the section. */
8177 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8178 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8179 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8181 if (exp
->X_op
!= O_symbol
)
8184 if (S_IS_LOCAL (exp
->X_add_symbol
)
8185 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8186 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8187 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8188 exp
->X_op
= O_subtract
;
8189 exp
->X_op_symbol
= GOT_symbol
;
8190 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8191 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8192 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8193 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8195 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8198 else if (exp
->X_op
== O_absent
8199 || exp
->X_op
== O_illegal
8200 || exp
->X_op
== O_big
)
8203 as_bad (_("missing or invalid displacement expression `%s'"),
8208 else if (flag_code
== CODE_64BIT
8209 && !i
.prefix
[ADDR_PREFIX
]
8210 && exp
->X_op
== O_constant
)
8212 /* Since displacement is signed extended to 64bit, don't allow
8213 disp32 and turn off disp32s if they are out of range. */
8214 i
.types
[this_operand
].bitfield
.disp32
= 0;
8215 if (!fits_in_signed_long (exp
->X_add_number
))
8217 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8218 if (i
.types
[this_operand
].bitfield
.baseindex
)
8220 as_bad (_("0x%lx out range of signed 32bit displacement"),
8221 (long) exp
->X_add_number
);
8227 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8228 else if (exp
->X_op
!= O_constant
8229 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8230 && exp_seg
!= absolute_section
8231 && exp_seg
!= text_section
8232 && exp_seg
!= data_section
8233 && exp_seg
!= bss_section
8234 && exp_seg
!= undefined_section
8235 && !bfd_is_com_section (exp_seg
))
8237 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8242 /* Check if this is a displacement only operand. */
8243 bigdisp
= i
.types
[this_operand
];
8244 bigdisp
.bitfield
.disp8
= 0;
8245 bigdisp
.bitfield
.disp16
= 0;
8246 bigdisp
.bitfield
.disp32
= 0;
8247 bigdisp
.bitfield
.disp32s
= 0;
8248 bigdisp
.bitfield
.disp64
= 0;
8249 if (operand_type_all_zero (&bigdisp
))
8250 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8256 /* Make sure the memory operand we've been dealt is valid.
8257 Return 1 on success, 0 on a failure. */
8260 i386_index_check (const char *operand_string
)
8262 const char *kind
= "base/index";
8263 enum flag_code addr_mode
;
8265 if (i
.prefix
[ADDR_PREFIX
])
8266 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8269 addr_mode
= flag_code
;
8271 #if INFER_ADDR_PREFIX
8272 if (i
.mem_operands
== 0)
8274 /* Infer address prefix from the first memory operand. */
8275 const reg_entry
*addr_reg
= i
.base_reg
;
8277 if (addr_reg
== NULL
)
8278 addr_reg
= i
.index_reg
;
8282 if (addr_reg
->reg_num
== RegEip
8283 || addr_reg
->reg_num
== RegEiz
8284 || addr_reg
->reg_type
.bitfield
.reg32
)
8285 addr_mode
= CODE_32BIT
;
8286 else if (flag_code
!= CODE_64BIT
8287 && addr_reg
->reg_type
.bitfield
.reg16
)
8288 addr_mode
= CODE_16BIT
;
8290 if (addr_mode
!= flag_code
)
8292 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8294 /* Change the size of any displacement too. At most one
8295 of Disp16 or Disp32 is set.
8296 FIXME. There doesn't seem to be any real need for
8297 separate Disp16 and Disp32 flags. The same goes for
8298 Imm16 and Imm32. Removing them would probably clean
8299 up the code quite a lot. */
8300 if (flag_code
!= CODE_64BIT
8301 && (i
.types
[this_operand
].bitfield
.disp16
8302 || i
.types
[this_operand
].bitfield
.disp32
))
8303 i
.types
[this_operand
]
8304 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8311 if (current_templates
->start
->opcode_modifier
.isstring
8312 && !current_templates
->start
->opcode_modifier
.immext
8313 && (current_templates
->end
[-1].opcode_modifier
.isstring
8316 /* Memory operands of string insns are special in that they only allow
8317 a single register (rDI, rSI, or rBX) as their memory address. */
8318 const reg_entry
*expected_reg
;
8319 static const char *di_si
[][2] =
8325 static const char *bx
[] = { "ebx", "bx", "rbx" };
8327 kind
= "string address";
8329 if (current_templates
->start
->opcode_modifier
.w
)
8331 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8333 if (!type
.bitfield
.baseindex
8334 || ((!i
.mem_operands
!= !intel_syntax
)
8335 && current_templates
->end
[-1].operand_types
[1]
8336 .bitfield
.baseindex
))
8337 type
= current_templates
->end
[-1].operand_types
[1];
8338 expected_reg
= hash_find (reg_hash
,
8339 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8343 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8345 if (i
.base_reg
!= expected_reg
8347 || operand_type_check (i
.types
[this_operand
], disp
))
8349 /* The second memory operand must have the same size as
8353 && !((addr_mode
== CODE_64BIT
8354 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8355 || (addr_mode
== CODE_32BIT
8356 ? i
.base_reg
->reg_type
.bitfield
.reg32
8357 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8360 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8362 intel_syntax
? '[' : '(',
8364 expected_reg
->reg_name
,
8365 intel_syntax
? ']' : ')');
8372 as_bad (_("`%s' is not a valid %s expression"),
8373 operand_string
, kind
);
8378 if (addr_mode
!= CODE_16BIT
)
8380 /* 32-bit/64-bit checks. */
8382 && (addr_mode
== CODE_64BIT
8383 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8384 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8386 || (i
.base_reg
->reg_num
8387 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8389 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8390 && !i
.index_reg
->reg_type
.bitfield
.regymm
8391 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8392 && ((addr_mode
== CODE_64BIT
8393 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8394 || i
.index_reg
->reg_num
== RegRiz
)
8395 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8396 || i
.index_reg
->reg_num
== RegEiz
))
8397 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8402 /* 16-bit checks. */
8404 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8405 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8407 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8408 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8410 && i
.base_reg
->reg_num
< 6
8411 && i
.index_reg
->reg_num
>= 6
8412 && i
.log2_scale_factor
== 0))))
8419 /* Handle vector immediates. */
8422 RC_SAE_immediate (const char *imm_start
)
8424 unsigned int match_found
, j
;
8425 const char *pstr
= imm_start
;
8433 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8435 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8439 rc_op
.type
= RC_NamesTable
[j
].type
;
8440 rc_op
.operand
= this_operand
;
8441 i
.rounding
= &rc_op
;
8445 as_bad (_("duplicated `%s'"), imm_start
);
8448 pstr
+= RC_NamesTable
[j
].len
;
8458 as_bad (_("Missing '}': '%s'"), imm_start
);
8461 /* RC/SAE immediate string should contain nothing more. */;
8464 as_bad (_("Junk after '}': '%s'"), imm_start
);
8468 exp
= &im_expressions
[i
.imm_operands
++];
8469 i
.op
[this_operand
].imms
= exp
;
8471 exp
->X_op
= O_constant
;
8472 exp
->X_add_number
= 0;
8473 exp
->X_add_symbol
= (symbolS
*) 0;
8474 exp
->X_op_symbol
= (symbolS
*) 0;
8476 i
.types
[this_operand
].bitfield
.imm8
= 1;
8480 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8484 i386_att_operand (char *operand_string
)
8488 char *op_string
= operand_string
;
8490 if (is_space_char (*op_string
))
8493 /* We check for an absolute prefix (differentiating,
8494 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8495 if (*op_string
== ABSOLUTE_PREFIX
)
8498 if (is_space_char (*op_string
))
8500 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8503 /* Check if operand is a register. */
8504 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8506 i386_operand_type temp
;
8508 /* Check for a segment override by searching for ':' after a
8509 segment register. */
8511 if (is_space_char (*op_string
))
8513 if (*op_string
== ':'
8514 && (r
->reg_type
.bitfield
.sreg2
8515 || r
->reg_type
.bitfield
.sreg3
))
8520 i
.seg
[i
.mem_operands
] = &es
;
8523 i
.seg
[i
.mem_operands
] = &cs
;
8526 i
.seg
[i
.mem_operands
] = &ss
;
8529 i
.seg
[i
.mem_operands
] = &ds
;
8532 i
.seg
[i
.mem_operands
] = &fs
;
8535 i
.seg
[i
.mem_operands
] = &gs
;
8539 /* Skip the ':' and whitespace. */
8541 if (is_space_char (*op_string
))
8544 if (!is_digit_char (*op_string
)
8545 && !is_identifier_char (*op_string
)
8546 && *op_string
!= '('
8547 && *op_string
!= ABSOLUTE_PREFIX
)
8549 as_bad (_("bad memory operand `%s'"), op_string
);
8552 /* Handle case of %es:*foo. */
8553 if (*op_string
== ABSOLUTE_PREFIX
)
8556 if (is_space_char (*op_string
))
8558 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8560 goto do_memory_reference
;
8563 /* Handle vector operations. */
8564 if (*op_string
== '{')
8566 op_string
= check_VecOperations (op_string
, NULL
);
8567 if (op_string
== NULL
)
8573 as_bad (_("junk `%s' after register"), op_string
);
8577 temp
.bitfield
.baseindex
= 0;
8578 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8580 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8581 i
.op
[this_operand
].regs
= r
;
8584 else if (*op_string
== REGISTER_PREFIX
)
8586 as_bad (_("bad register name `%s'"), op_string
);
8589 else if (*op_string
== IMMEDIATE_PREFIX
)
8592 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8594 as_bad (_("immediate operand illegal with absolute jump"));
8597 if (!i386_immediate (op_string
))
8600 else if (RC_SAE_immediate (operand_string
))
8602 /* If it is a RC or SAE immediate, do nothing. */
8605 else if (is_digit_char (*op_string
)
8606 || is_identifier_char (*op_string
)
8607 || *op_string
== '(')
8609 /* This is a memory reference of some sort. */
8612 /* Start and end of displacement string expression (if found). */
8613 char *displacement_string_start
;
8614 char *displacement_string_end
;
8617 do_memory_reference
:
8618 if ((i
.mem_operands
== 1
8619 && !current_templates
->start
->opcode_modifier
.isstring
)
8620 || i
.mem_operands
== 2)
8622 as_bad (_("too many memory references for `%s'"),
8623 current_templates
->start
->name
);
8627 /* Check for base index form. We detect the base index form by
8628 looking for an ')' at the end of the operand, searching
8629 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8631 base_string
= op_string
+ strlen (op_string
);
8633 /* Handle vector operations. */
8634 vop_start
= strchr (op_string
, '{');
8635 if (vop_start
&& vop_start
< base_string
)
8637 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8639 base_string
= vop_start
;
8643 if (is_space_char (*base_string
))
8646 /* If we only have a displacement, set-up for it to be parsed later. */
8647 displacement_string_start
= op_string
;
8648 displacement_string_end
= base_string
+ 1;
8650 if (*base_string
== ')')
8653 unsigned int parens_balanced
= 1;
8654 /* We've already checked that the number of left & right ()'s are
8655 equal, so this loop will not be infinite. */
8659 if (*base_string
== ')')
8661 if (*base_string
== '(')
8664 while (parens_balanced
);
8666 temp_string
= base_string
;
8668 /* Skip past '(' and whitespace. */
8670 if (is_space_char (*base_string
))
8673 if (*base_string
== ','
8674 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8677 displacement_string_end
= temp_string
;
8679 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8683 base_string
= end_op
;
8684 if (is_space_char (*base_string
))
8688 /* There may be an index reg or scale factor here. */
8689 if (*base_string
== ',')
8692 if (is_space_char (*base_string
))
8695 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8698 base_string
= end_op
;
8699 if (is_space_char (*base_string
))
8701 if (*base_string
== ',')
8704 if (is_space_char (*base_string
))
8707 else if (*base_string
!= ')')
8709 as_bad (_("expecting `,' or `)' "
8710 "after index register in `%s'"),
8715 else if (*base_string
== REGISTER_PREFIX
)
8717 end_op
= strchr (base_string
, ',');
8720 as_bad (_("bad register name `%s'"), base_string
);
8724 /* Check for scale factor. */
8725 if (*base_string
!= ')')
8727 char *end_scale
= i386_scale (base_string
);
8732 base_string
= end_scale
;
8733 if (is_space_char (*base_string
))
8735 if (*base_string
!= ')')
8737 as_bad (_("expecting `)' "
8738 "after scale factor in `%s'"),
8743 else if (!i
.index_reg
)
8745 as_bad (_("expecting index register or scale factor "
8746 "after `,'; got '%c'"),
8751 else if (*base_string
!= ')')
8753 as_bad (_("expecting `,' or `)' "
8754 "after base register in `%s'"),
8759 else if (*base_string
== REGISTER_PREFIX
)
8761 end_op
= strchr (base_string
, ',');
8764 as_bad (_("bad register name `%s'"), base_string
);
8769 /* If there's an expression beginning the operand, parse it,
8770 assuming displacement_string_start and
8771 displacement_string_end are meaningful. */
8772 if (displacement_string_start
!= displacement_string_end
)
8774 if (!i386_displacement (displacement_string_start
,
8775 displacement_string_end
))
8779 /* Special case for (%dx) while doing input/output op. */
8781 && operand_type_equal (&i
.base_reg
->reg_type
,
8782 ®16_inoutportreg
)
8784 && i
.log2_scale_factor
== 0
8785 && i
.seg
[i
.mem_operands
] == 0
8786 && !operand_type_check (i
.types
[this_operand
], disp
))
8788 i
.types
[this_operand
] = inoutportreg
;
8792 if (i386_index_check (operand_string
) == 0)
8794 i
.types
[this_operand
].bitfield
.mem
= 1;
8799 /* It's not a memory operand; argh! */
8800 as_bad (_("invalid char %s beginning operand %d `%s'"),
8801 output_invalid (*op_string
),
8806 return 1; /* Normal return. */
8809 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8810 that an rs_machine_dependent frag may reach. */
8813 i386_frag_max_var (fragS
*frag
)
8815 /* The only relaxable frags are for jumps.
8816 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8817 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8818 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8821 /* md_estimate_size_before_relax()
8823 Called just before relax() for rs_machine_dependent frags. The x86
8824 assembler uses these frags to handle variable size jump
8827 Any symbol that is now undefined will not become defined.
8828 Return the correct fr_subtype in the frag.
8829 Return the initial "guess for variable size of frag" to caller.
8830 The guess is actually the growth beyond the fixed part. Whatever
8831 we do to grow the fixed or variable part contributes to our
8835 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8837 /* We've already got fragP->fr_subtype right; all we have to do is
8838 check for un-relaxable symbols. On an ELF system, we can't relax
8839 an externally visible symbol, because it may be overridden by a
8841 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8844 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8845 || S_IS_WEAK (fragP
->fr_symbol
)
8846 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8847 & BSF_GNU_INDIRECT_FUNCTION
))))
8849 #if defined (OBJ_COFF) && defined (TE_PE)
8850 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8851 && S_IS_WEAK (fragP
->fr_symbol
))
8855 /* Symbol is undefined in this segment, or we need to keep a
8856 reloc so that weak symbols can be overridden. */
8857 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8858 enum bfd_reloc_code_real reloc_type
;
8859 unsigned char *opcode
;
8862 if (fragP
->fr_var
!= NO_RELOC
)
8863 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8865 reloc_type
= BFD_RELOC_16_PCREL
;
8867 reloc_type
= BFD_RELOC_32_PCREL
;
8869 old_fr_fix
= fragP
->fr_fix
;
8870 opcode
= (unsigned char *) fragP
->fr_opcode
;
8872 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8875 /* Make jmp (0xeb) a (d)word displacement jump. */
8877 fragP
->fr_fix
+= size
;
8878 fix_new (fragP
, old_fr_fix
, size
,
8880 fragP
->fr_offset
, 1,
8886 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8888 /* Negate the condition, and branch past an
8889 unconditional jump. */
8892 /* Insert an unconditional jump. */
8894 /* We added two extra opcode bytes, and have a two byte
8896 fragP
->fr_fix
+= 2 + 2;
8897 fix_new (fragP
, old_fr_fix
+ 2, 2,
8899 fragP
->fr_offset
, 1,
8906 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8911 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8913 fragP
->fr_offset
, 1,
8915 fixP
->fx_signed
= 1;
8919 /* This changes the byte-displacement jump 0x7N
8920 to the (d)word-displacement jump 0x0f,0x8N. */
8921 opcode
[1] = opcode
[0] + 0x10;
8922 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8923 /* We've added an opcode byte. */
8924 fragP
->fr_fix
+= 1 + size
;
8925 fix_new (fragP
, old_fr_fix
+ 1, size
,
8927 fragP
->fr_offset
, 1,
8932 BAD_CASE (fragP
->fr_subtype
);
8936 return fragP
->fr_fix
- old_fr_fix
;
8939 /* Guess size depending on current relax state. Initially the relax
8940 state will correspond to a short jump and we return 1, because
8941 the variable part of the frag (the branch offset) is one byte
8942 long. However, we can relax a section more than once and in that
8943 case we must either set fr_subtype back to the unrelaxed state,
8944 or return the value for the appropriate branch. */
8945 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8948 /* Called after relax() is finished.
8950 In: Address of frag.
8951 fr_type == rs_machine_dependent.
8952 fr_subtype is what the address relaxed to.
8954 Out: Any fixSs and constants are set up.
8955 Caller will turn frag into a ".space 0". */
8958 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8961 unsigned char *opcode
;
8962 unsigned char *where_to_put_displacement
= NULL
;
8963 offsetT target_address
;
8964 offsetT opcode_address
;
8965 unsigned int extension
= 0;
8966 offsetT displacement_from_opcode_start
;
8968 opcode
= (unsigned char *) fragP
->fr_opcode
;
8970 /* Address we want to reach in file space. */
8971 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8973 /* Address opcode resides at in file space. */
8974 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8976 /* Displacement from opcode start to fill into instruction. */
8977 displacement_from_opcode_start
= target_address
- opcode_address
;
8979 if ((fragP
->fr_subtype
& BIG
) == 0)
8981 /* Don't have to change opcode. */
8982 extension
= 1; /* 1 opcode + 1 displacement */
8983 where_to_put_displacement
= &opcode
[1];
8987 if (no_cond_jump_promotion
8988 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8989 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8990 _("long jump required"));
8992 switch (fragP
->fr_subtype
)
8994 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8995 extension
= 4; /* 1 opcode + 4 displacement */
8997 where_to_put_displacement
= &opcode
[1];
9000 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9001 extension
= 2; /* 1 opcode + 2 displacement */
9003 where_to_put_displacement
= &opcode
[1];
9006 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9007 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9008 extension
= 5; /* 2 opcode + 4 displacement */
9009 opcode
[1] = opcode
[0] + 0x10;
9010 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9011 where_to_put_displacement
= &opcode
[2];
9014 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9015 extension
= 3; /* 2 opcode + 2 displacement */
9016 opcode
[1] = opcode
[0] + 0x10;
9017 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9018 where_to_put_displacement
= &opcode
[2];
9021 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9026 where_to_put_displacement
= &opcode
[3];
9030 BAD_CASE (fragP
->fr_subtype
);
9035 /* If size if less then four we are sure that the operand fits,
9036 but if it's 4, then it could be that the displacement is larger
9038 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9040 && ((addressT
) (displacement_from_opcode_start
- extension
9041 + ((addressT
) 1 << 31))
9042 > (((addressT
) 2 << 31) - 1)))
9044 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9045 _("jump target out of range"));
9046 /* Make us emit 0. */
9047 displacement_from_opcode_start
= extension
;
9049 /* Now put displacement after opcode. */
9050 md_number_to_chars ((char *) where_to_put_displacement
,
9051 (valueT
) (displacement_from_opcode_start
- extension
),
9052 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9053 fragP
->fr_fix
+= extension
;
9056 /* Apply a fixup (fixP) to segment data, once it has been determined
9057 by our caller that we have all the info we need to fix it up.
9059 Parameter valP is the pointer to the value of the bits.
9061 On the 386, immediates, displacements, and data pointers are all in
9062 the same (little-endian) format, so we don't need to care about which
9066 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9068 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9069 valueT value
= *valP
;
9071 #if !defined (TE_Mach)
9074 switch (fixP
->fx_r_type
)
9080 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9083 case BFD_RELOC_X86_64_32S
:
9084 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9087 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9090 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9095 if (fixP
->fx_addsy
!= NULL
9096 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9097 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9098 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9099 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9100 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9101 && !use_rela_relocations
)
9103 /* This is a hack. There should be a better way to handle this.
9104 This covers for the fact that bfd_install_relocation will
9105 subtract the current location (for partial_inplace, PC relative
9106 relocations); see more below. */
9110 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9113 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9118 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9121 || (symbol_section_p (fixP
->fx_addsy
)
9122 && sym_seg
!= absolute_section
))
9123 && !generic_force_reloc (fixP
))
9125 /* Yes, we add the values in twice. This is because
9126 bfd_install_relocation subtracts them out again. I think
9127 bfd_install_relocation is broken, but I don't dare change
9129 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9133 #if defined (OBJ_COFF) && defined (TE_PE)
9134 /* For some reason, the PE format does not store a
9135 section address offset for a PC relative symbol. */
9136 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9137 || S_IS_WEAK (fixP
->fx_addsy
))
9138 value
+= md_pcrel_from (fixP
);
9141 #if defined (OBJ_COFF) && defined (TE_PE)
9142 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9144 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9148 /* Fix a few things - the dynamic linker expects certain values here,
9149 and we must not disappoint it. */
9150 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9151 if (IS_ELF
&& fixP
->fx_addsy
)
9152 switch (fixP
->fx_r_type
)
9154 case BFD_RELOC_386_PLT32
:
9155 case BFD_RELOC_X86_64_PLT32
:
9156 case BFD_RELOC_X86_64_PLT32_BND
:
9157 /* Make the jump instruction point to the address of the operand. At
9158 runtime we merely add the offset to the actual PLT entry. */
9162 case BFD_RELOC_386_TLS_GD
:
9163 case BFD_RELOC_386_TLS_LDM
:
9164 case BFD_RELOC_386_TLS_IE_32
:
9165 case BFD_RELOC_386_TLS_IE
:
9166 case BFD_RELOC_386_TLS_GOTIE
:
9167 case BFD_RELOC_386_TLS_GOTDESC
:
9168 case BFD_RELOC_X86_64_TLSGD
:
9169 case BFD_RELOC_X86_64_TLSLD
:
9170 case BFD_RELOC_X86_64_GOTTPOFF
:
9171 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9172 value
= 0; /* Fully resolved at runtime. No addend. */
9174 case BFD_RELOC_386_TLS_LE
:
9175 case BFD_RELOC_386_TLS_LDO_32
:
9176 case BFD_RELOC_386_TLS_LE_32
:
9177 case BFD_RELOC_X86_64_DTPOFF32
:
9178 case BFD_RELOC_X86_64_DTPOFF64
:
9179 case BFD_RELOC_X86_64_TPOFF32
:
9180 case BFD_RELOC_X86_64_TPOFF64
:
9181 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9184 case BFD_RELOC_386_TLS_DESC_CALL
:
9185 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9186 value
= 0; /* Fully resolved at runtime. No addend. */
9187 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9191 case BFD_RELOC_386_GOT32
:
9192 case BFD_RELOC_X86_64_GOT32
:
9193 value
= 0; /* Fully resolved at runtime. No addend. */
9196 case BFD_RELOC_VTABLE_INHERIT
:
9197 case BFD_RELOC_VTABLE_ENTRY
:
9204 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9206 #endif /* !defined (TE_Mach) */
9208 /* Are we finished with this relocation now? */
9209 if (fixP
->fx_addsy
== NULL
)
9211 #if defined (OBJ_COFF) && defined (TE_PE)
9212 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9215 /* Remember value for tc_gen_reloc. */
9216 fixP
->fx_addnumber
= value
;
9217 /* Clear out the frag for now. */
9221 else if (use_rela_relocations
)
9223 fixP
->fx_no_overflow
= 1;
9224 /* Remember value for tc_gen_reloc. */
9225 fixP
->fx_addnumber
= value
;
9229 md_number_to_chars (p
, value
, fixP
->fx_size
);
9233 md_atof (int type
, char *litP
, int *sizeP
)
9235 /* This outputs the LITTLENUMs in REVERSE order;
9236 in accord with the bigendian 386. */
9237 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9240 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9243 output_invalid (int c
)
9246 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9249 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9250 "(0x%x)", (unsigned char) c
);
9251 return output_invalid_buf
;
9254 /* REG_STRING starts *before* REGISTER_PREFIX. */
9256 static const reg_entry
*
9257 parse_real_register (char *reg_string
, char **end_op
)
9259 char *s
= reg_string
;
9261 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9264 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9265 if (*s
== REGISTER_PREFIX
)
9268 if (is_space_char (*s
))
9272 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9274 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9275 return (const reg_entry
*) NULL
;
9279 /* For naked regs, make sure that we are not dealing with an identifier.
9280 This prevents confusing an identifier like `eax_var' with register
9282 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9283 return (const reg_entry
*) NULL
;
9287 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9289 /* Handle floating point regs, allowing spaces in the (i) part. */
9290 if (r
== i386_regtab
/* %st is first entry of table */)
9292 if (is_space_char (*s
))
9297 if (is_space_char (*s
))
9299 if (*s
>= '0' && *s
<= '7')
9303 if (is_space_char (*s
))
9308 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9313 /* We have "%st(" then garbage. */
9314 return (const reg_entry
*) NULL
;
9318 if (r
== NULL
|| allow_pseudo_reg
)
9321 if (operand_type_all_zero (&r
->reg_type
))
9322 return (const reg_entry
*) NULL
;
9324 if ((r
->reg_type
.bitfield
.reg32
9325 || r
->reg_type
.bitfield
.sreg3
9326 || r
->reg_type
.bitfield
.control
9327 || r
->reg_type
.bitfield
.debug
9328 || r
->reg_type
.bitfield
.test
)
9329 && !cpu_arch_flags
.bitfield
.cpui386
)
9330 return (const reg_entry
*) NULL
;
9332 if (r
->reg_type
.bitfield
.floatreg
9333 && !cpu_arch_flags
.bitfield
.cpu8087
9334 && !cpu_arch_flags
.bitfield
.cpu287
9335 && !cpu_arch_flags
.bitfield
.cpu387
)
9336 return (const reg_entry
*) NULL
;
9338 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9339 return (const reg_entry
*) NULL
;
9341 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9342 return (const reg_entry
*) NULL
;
9344 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9345 return (const reg_entry
*) NULL
;
9347 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9348 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9349 return (const reg_entry
*) NULL
;
9351 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9352 if (!allow_index_reg
9353 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9354 return (const reg_entry
*) NULL
;
9356 /* Upper 16 vector register is only available with VREX in 64bit
9358 if ((r
->reg_flags
& RegVRex
))
9360 if (!cpu_arch_flags
.bitfield
.cpuvrex
9361 || flag_code
!= CODE_64BIT
)
9362 return (const reg_entry
*) NULL
;
9367 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9368 || r
->reg_type
.bitfield
.reg64
)
9369 && (!cpu_arch_flags
.bitfield
.cpulm
9370 || !operand_type_equal (&r
->reg_type
, &control
))
9371 && flag_code
!= CODE_64BIT
)
9372 return (const reg_entry
*) NULL
;
9374 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9375 return (const reg_entry
*) NULL
;
9380 /* REG_STRING starts *before* REGISTER_PREFIX. */
9382 static const reg_entry
*
9383 parse_register (char *reg_string
, char **end_op
)
9387 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9388 r
= parse_real_register (reg_string
, end_op
);
9393 char *save
= input_line_pointer
;
9397 input_line_pointer
= reg_string
;
9398 c
= get_symbol_end ();
9399 symbolP
= symbol_find (reg_string
);
9400 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9402 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9404 know (e
->X_op
== O_register
);
9405 know (e
->X_add_number
>= 0
9406 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9407 r
= i386_regtab
+ e
->X_add_number
;
9408 *end_op
= input_line_pointer
;
9410 *input_line_pointer
= c
;
9411 input_line_pointer
= save
;
9417 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9420 char *end
= input_line_pointer
;
9423 r
= parse_register (name
, &input_line_pointer
);
9424 if (r
&& end
<= input_line_pointer
)
9426 *nextcharP
= *input_line_pointer
;
9427 *input_line_pointer
= 0;
9428 e
->X_op
= O_register
;
9429 e
->X_add_number
= r
- i386_regtab
;
9432 input_line_pointer
= end
;
9434 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9438 md_operand (expressionS
*e
)
9443 switch (*input_line_pointer
)
9445 case REGISTER_PREFIX
:
9446 r
= parse_real_register (input_line_pointer
, &end
);
9449 e
->X_op
= O_register
;
9450 e
->X_add_number
= r
- i386_regtab
;
9451 input_line_pointer
= end
;
9456 gas_assert (intel_syntax
);
9457 end
= input_line_pointer
++;
9459 if (*input_line_pointer
== ']')
9461 ++input_line_pointer
;
9462 e
->X_op_symbol
= make_expr_symbol (e
);
9463 e
->X_add_symbol
= NULL
;
9464 e
->X_add_number
= 0;
9470 input_line_pointer
= end
;
9477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9478 const char *md_shortopts
= "kVQ:sqn";
9480 const char *md_shortopts
= "qn";
9483 #define OPTION_32 (OPTION_MD_BASE + 0)
9484 #define OPTION_64 (OPTION_MD_BASE + 1)
9485 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9486 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9487 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9488 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9489 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9490 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9491 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9492 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9493 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9494 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9495 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9496 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9497 #define OPTION_X32 (OPTION_MD_BASE + 14)
9498 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9499 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9500 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9502 struct option md_longopts
[] =
9504 {"32", no_argument
, NULL
, OPTION_32
},
9505 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9507 {"64", no_argument
, NULL
, OPTION_64
},
9509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9510 {"x32", no_argument
, NULL
, OPTION_X32
},
9512 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9513 {"march", required_argument
, NULL
, OPTION_MARCH
},
9514 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9515 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9516 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9517 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9518 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9519 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9520 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9521 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9522 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9523 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9524 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9525 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9526 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9527 {NULL
, no_argument
, NULL
, 0}
9529 size_t md_longopts_size
= sizeof (md_longopts
);
9532 md_parse_option (int c
, char *arg
)
9540 optimize_align_code
= 0;
9547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9548 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9549 should be emitted or not. FIXME: Not implemented. */
9553 /* -V: SVR4 argument to print version ID. */
9555 print_version_id ();
9558 /* -k: Ignore for FreeBSD compatibility. */
9563 /* -s: On i386 Solaris, this tells the native assembler to use
9564 .stab instead of .stab.excl. We always use .stab anyhow. */
9567 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9571 const char **list
, **l
;
9573 list
= bfd_target_list ();
9574 for (l
= list
; *l
!= NULL
; l
++)
9575 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9576 || strcmp (*l
, "coff-x86-64") == 0
9577 || strcmp (*l
, "pe-x86-64") == 0
9578 || strcmp (*l
, "pei-x86-64") == 0
9579 || strcmp (*l
, "mach-o-x86-64") == 0)
9581 default_arch
= "x86_64";
9585 as_fatal (_("no compiled in support for x86_64"));
9591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9595 const char **list
, **l
;
9597 list
= bfd_target_list ();
9598 for (l
= list
; *l
!= NULL
; l
++)
9599 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9601 default_arch
= "x86_64:32";
9605 as_fatal (_("no compiled in support for 32bit x86_64"));
9609 as_fatal (_("32bit x86_64 is only supported for ELF"));
9614 default_arch
= "i386";
9618 #ifdef SVR4_COMMENT_CHARS
9623 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9625 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9629 i386_comment_chars
= n
;
9635 arch
= xstrdup (arg
);
9639 as_fatal (_("invalid -march= option: `%s'"), arg
);
9640 next
= strchr (arch
, '+');
9643 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9645 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9648 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9651 cpu_arch_name
= cpu_arch
[j
].name
;
9652 cpu_sub_arch_name
= NULL
;
9653 cpu_arch_flags
= cpu_arch
[j
].flags
;
9654 cpu_arch_isa
= cpu_arch
[j
].type
;
9655 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9656 if (!cpu_arch_tune_set
)
9658 cpu_arch_tune
= cpu_arch_isa
;
9659 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9663 else if (*cpu_arch
[j
].name
== '.'
9664 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9666 /* ISA entension. */
9667 i386_cpu_flags flags
;
9669 if (!cpu_arch
[j
].negated
)
9670 flags
= cpu_flags_or (cpu_arch_flags
,
9673 flags
= cpu_flags_and_not (cpu_arch_flags
,
9675 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9677 if (cpu_sub_arch_name
)
9679 char *name
= cpu_sub_arch_name
;
9680 cpu_sub_arch_name
= concat (name
,
9682 (const char *) NULL
);
9686 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9687 cpu_arch_flags
= flags
;
9688 cpu_arch_isa_flags
= flags
;
9694 if (j
>= ARRAY_SIZE (cpu_arch
))
9695 as_fatal (_("invalid -march= option: `%s'"), arg
);
9699 while (next
!= NULL
);
9704 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9705 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9707 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9709 cpu_arch_tune_set
= 1;
9710 cpu_arch_tune
= cpu_arch
[j
].type
;
9711 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9715 if (j
>= ARRAY_SIZE (cpu_arch
))
9716 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9719 case OPTION_MMNEMONIC
:
9720 if (strcasecmp (arg
, "att") == 0)
9722 else if (strcasecmp (arg
, "intel") == 0)
9725 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9728 case OPTION_MSYNTAX
:
9729 if (strcasecmp (arg
, "att") == 0)
9731 else if (strcasecmp (arg
, "intel") == 0)
9734 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9737 case OPTION_MINDEX_REG
:
9738 allow_index_reg
= 1;
9741 case OPTION_MNAKED_REG
:
9742 allow_naked_reg
= 1;
9745 case OPTION_MOLD_GCC
:
9749 case OPTION_MSSE2AVX
:
9753 case OPTION_MSSE_CHECK
:
9754 if (strcasecmp (arg
, "error") == 0)
9755 sse_check
= check_error
;
9756 else if (strcasecmp (arg
, "warning") == 0)
9757 sse_check
= check_warning
;
9758 else if (strcasecmp (arg
, "none") == 0)
9759 sse_check
= check_none
;
9761 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9764 case OPTION_MOPERAND_CHECK
:
9765 if (strcasecmp (arg
, "error") == 0)
9766 operand_check
= check_error
;
9767 else if (strcasecmp (arg
, "warning") == 0)
9768 operand_check
= check_warning
;
9769 else if (strcasecmp (arg
, "none") == 0)
9770 operand_check
= check_none
;
9772 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9775 case OPTION_MAVXSCALAR
:
9776 if (strcasecmp (arg
, "128") == 0)
9778 else if (strcasecmp (arg
, "256") == 0)
9781 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9784 case OPTION_MADD_BND_PREFIX
:
9788 case OPTION_MEVEXLIG
:
9789 if (strcmp (arg
, "128") == 0)
9791 else if (strcmp (arg
, "256") == 0)
9793 else if (strcmp (arg
, "512") == 0)
9796 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9799 case OPTION_MEVEXWIG
:
9800 if (strcmp (arg
, "0") == 0)
9802 else if (strcmp (arg
, "1") == 0)
9805 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9814 #define MESSAGE_TEMPLATE \
9818 show_arch (FILE *stream
, int ext
, int check
)
9820 static char message
[] = MESSAGE_TEMPLATE
;
9821 char *start
= message
+ 27;
9823 int size
= sizeof (MESSAGE_TEMPLATE
);
9830 left
= size
- (start
- message
);
9831 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9833 /* Should it be skipped? */
9834 if (cpu_arch
[j
].skip
)
9837 name
= cpu_arch
[j
].name
;
9838 len
= cpu_arch
[j
].len
;
9841 /* It is an extension. Skip if we aren't asked to show it. */
9852 /* It is an processor. Skip if we show only extension. */
9855 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9857 /* It is an impossible processor - skip. */
9861 /* Reserve 2 spaces for ", " or ",\0" */
9864 /* Check if there is any room. */
9872 p
= mempcpy (p
, name
, len
);
9876 /* Output the current message now and start a new one. */
9879 fprintf (stream
, "%s\n", message
);
9881 left
= size
- (start
- message
) - len
- 2;
9883 gas_assert (left
>= 0);
9885 p
= mempcpy (p
, name
, len
);
9890 fprintf (stream
, "%s\n", message
);
9894 md_show_usage (FILE *stream
)
9896 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9897 fprintf (stream
, _("\
9899 -V print assembler version number\n\
9902 fprintf (stream
, _("\
9903 -n Do not optimize code alignment\n\
9904 -q quieten some warnings\n"));
9905 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9906 fprintf (stream
, _("\
9909 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9910 || defined (TE_PE) || defined (TE_PEP))
9911 fprintf (stream
, _("\
9912 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9914 #ifdef SVR4_COMMENT_CHARS
9915 fprintf (stream
, _("\
9916 --divide do not treat `/' as a comment character\n"));
9918 fprintf (stream
, _("\
9919 --divide ignored\n"));
9921 fprintf (stream
, _("\
9922 -march=CPU[,+EXTENSION...]\n\
9923 generate code for CPU and EXTENSION, CPU is one of:\n"));
9924 show_arch (stream
, 0, 1);
9925 fprintf (stream
, _("\
9926 EXTENSION is combination of:\n"));
9927 show_arch (stream
, 1, 0);
9928 fprintf (stream
, _("\
9929 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9930 show_arch (stream
, 0, 0);
9931 fprintf (stream
, _("\
9932 -msse2avx encode SSE instructions with VEX prefix\n"));
9933 fprintf (stream
, _("\
9934 -msse-check=[none|error|warning]\n\
9935 check SSE instructions\n"));
9936 fprintf (stream
, _("\
9937 -moperand-check=[none|error|warning]\n\
9938 check operand combinations for validity\n"));
9939 fprintf (stream
, _("\
9940 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9942 fprintf (stream
, _("\
9943 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9945 fprintf (stream
, _("\
9946 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9947 for EVEX.W bit ignored instructions\n"));
9948 fprintf (stream
, _("\
9949 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9950 fprintf (stream
, _("\
9951 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9952 fprintf (stream
, _("\
9953 -mindex-reg support pseudo index registers\n"));
9954 fprintf (stream
, _("\
9955 -mnaked-reg don't require `%%' prefix for registers\n"));
9956 fprintf (stream
, _("\
9957 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9958 fprintf (stream
, _("\
9959 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9962 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9963 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9964 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9966 /* Pick the target format to use. */
9969 i386_target_format (void)
9971 if (!strncmp (default_arch
, "x86_64", 6))
9973 update_code_flag (CODE_64BIT
, 1);
9974 if (default_arch
[6] == '\0')
9975 x86_elf_abi
= X86_64_ABI
;
9977 x86_elf_abi
= X86_64_X32_ABI
;
9979 else if (!strcmp (default_arch
, "i386"))
9980 update_code_flag (CODE_32BIT
, 1);
9982 as_fatal (_("unknown architecture"));
9984 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9985 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9986 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9987 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9989 switch (OUTPUT_FLAVOR
)
9991 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9992 case bfd_target_aout_flavour
:
9993 return AOUT_TARGET_FORMAT
;
9995 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9996 # if defined (TE_PE) || defined (TE_PEP)
9997 case bfd_target_coff_flavour
:
9998 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9999 # elif defined (TE_GO32)
10000 case bfd_target_coff_flavour
:
10001 return "coff-go32";
10003 case bfd_target_coff_flavour
:
10004 return "coff-i386";
10007 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10008 case bfd_target_elf_flavour
:
10010 const char *format
;
10012 switch (x86_elf_abi
)
10015 format
= ELF_TARGET_FORMAT
;
10018 use_rela_relocations
= 1;
10020 format
= ELF_TARGET_FORMAT64
;
10022 case X86_64_X32_ABI
:
10023 use_rela_relocations
= 1;
10025 disallow_64bit_reloc
= 1;
10026 format
= ELF_TARGET_FORMAT32
;
10029 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10031 if (x86_elf_abi
!= X86_64_ABI
)
10032 as_fatal (_("Intel L1OM is 64bit only"));
10033 return ELF_TARGET_L1OM_FORMAT
;
10035 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10037 if (x86_elf_abi
!= X86_64_ABI
)
10038 as_fatal (_("Intel K1OM is 64bit only"));
10039 return ELF_TARGET_K1OM_FORMAT
;
10045 #if defined (OBJ_MACH_O)
10046 case bfd_target_mach_o_flavour
:
10047 if (flag_code
== CODE_64BIT
)
10049 use_rela_relocations
= 1;
10051 return "mach-o-x86-64";
10054 return "mach-o-i386";
10062 #endif /* OBJ_MAYBE_ more than one */
10064 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10066 i386_elf_emit_arch_note (void)
10068 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10071 asection
*seg
= now_seg
;
10072 subsegT subseg
= now_subseg
;
10073 Elf_Internal_Note i_note
;
10074 Elf_External_Note e_note
;
10075 asection
*note_secp
;
10078 /* Create the .note section. */
10079 note_secp
= subseg_new (".note", 0);
10080 bfd_set_section_flags (stdoutput
,
10082 SEC_HAS_CONTENTS
| SEC_READONLY
);
10084 /* Process the arch string. */
10085 len
= strlen (cpu_arch_name
);
10087 i_note
.namesz
= len
+ 1;
10089 i_note
.type
= NT_ARCH
;
10090 p
= frag_more (sizeof (e_note
.namesz
));
10091 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10092 p
= frag_more (sizeof (e_note
.descsz
));
10093 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10094 p
= frag_more (sizeof (e_note
.type
));
10095 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10096 p
= frag_more (len
+ 1);
10097 strcpy (p
, cpu_arch_name
);
10099 frag_align (2, 0, 0);
10101 subseg_set (seg
, subseg
);
10107 md_undefined_symbol (char *name
)
10109 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10110 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10111 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10112 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10116 if (symbol_find (name
))
10117 as_bad (_("GOT already in symbol table"));
10118 GOT_symbol
= symbol_new (name
, undefined_section
,
10119 (valueT
) 0, &zero_address_frag
);
10126 /* Round up a section size to the appropriate boundary. */
10129 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10131 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10132 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10134 /* For a.out, force the section size to be aligned. If we don't do
10135 this, BFD will align it for us, but it will not write out the
10136 final bytes of the section. This may be a bug in BFD, but it is
10137 easier to fix it here since that is how the other a.out targets
10141 align
= bfd_get_section_alignment (stdoutput
, segment
);
10142 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10149 /* On the i386, PC-relative offsets are relative to the start of the
10150 next instruction. That is, the address of the offset, plus its
10151 size, since the offset is always the last part of the insn. */
10154 md_pcrel_from (fixS
*fixP
)
10156 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10162 s_bss (int ignore ATTRIBUTE_UNUSED
)
10166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10168 obj_elf_section_change_hook ();
10170 temp
= get_absolute_expression ();
10171 subseg_set (bss_section
, (subsegT
) temp
);
10172 demand_empty_rest_of_line ();
10178 i386_validate_fix (fixS
*fixp
)
10180 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10182 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10186 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10191 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10193 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10195 fixp
->fx_subsy
= 0;
10200 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10203 bfd_reloc_code_real_type code
;
10205 switch (fixp
->fx_r_type
)
10207 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10208 case BFD_RELOC_SIZE32
:
10209 case BFD_RELOC_SIZE64
:
10210 if (S_IS_DEFINED (fixp
->fx_addsy
)
10211 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10213 /* Resolve size relocation against local symbol to size of
10214 the symbol plus addend. */
10215 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10216 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10217 && !fits_in_unsigned_long (value
))
10218 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10219 _("symbol size computation overflow"));
10220 fixp
->fx_addsy
= NULL
;
10221 fixp
->fx_subsy
= NULL
;
10222 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10227 case BFD_RELOC_X86_64_PLT32
:
10228 case BFD_RELOC_X86_64_PLT32_BND
:
10229 case BFD_RELOC_X86_64_GOT32
:
10230 case BFD_RELOC_X86_64_GOTPCREL
:
10231 case BFD_RELOC_386_PLT32
:
10232 case BFD_RELOC_386_GOT32
:
10233 case BFD_RELOC_386_GOTOFF
:
10234 case BFD_RELOC_386_GOTPC
:
10235 case BFD_RELOC_386_TLS_GD
:
10236 case BFD_RELOC_386_TLS_LDM
:
10237 case BFD_RELOC_386_TLS_LDO_32
:
10238 case BFD_RELOC_386_TLS_IE_32
:
10239 case BFD_RELOC_386_TLS_IE
:
10240 case BFD_RELOC_386_TLS_GOTIE
:
10241 case BFD_RELOC_386_TLS_LE_32
:
10242 case BFD_RELOC_386_TLS_LE
:
10243 case BFD_RELOC_386_TLS_GOTDESC
:
10244 case BFD_RELOC_386_TLS_DESC_CALL
:
10245 case BFD_RELOC_X86_64_TLSGD
:
10246 case BFD_RELOC_X86_64_TLSLD
:
10247 case BFD_RELOC_X86_64_DTPOFF32
:
10248 case BFD_RELOC_X86_64_DTPOFF64
:
10249 case BFD_RELOC_X86_64_GOTTPOFF
:
10250 case BFD_RELOC_X86_64_TPOFF32
:
10251 case BFD_RELOC_X86_64_TPOFF64
:
10252 case BFD_RELOC_X86_64_GOTOFF64
:
10253 case BFD_RELOC_X86_64_GOTPC32
:
10254 case BFD_RELOC_X86_64_GOT64
:
10255 case BFD_RELOC_X86_64_GOTPCREL64
:
10256 case BFD_RELOC_X86_64_GOTPC64
:
10257 case BFD_RELOC_X86_64_GOTPLT64
:
10258 case BFD_RELOC_X86_64_PLTOFF64
:
10259 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10260 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10261 case BFD_RELOC_RVA
:
10262 case BFD_RELOC_VTABLE_ENTRY
:
10263 case BFD_RELOC_VTABLE_INHERIT
:
10265 case BFD_RELOC_32_SECREL
:
10267 code
= fixp
->fx_r_type
;
10269 case BFD_RELOC_X86_64_32S
:
10270 if (!fixp
->fx_pcrel
)
10272 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10273 code
= fixp
->fx_r_type
;
10277 if (fixp
->fx_pcrel
)
10279 switch (fixp
->fx_size
)
10282 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10283 _("can not do %d byte pc-relative relocation"),
10285 code
= BFD_RELOC_32_PCREL
;
10287 case 1: code
= BFD_RELOC_8_PCREL
; break;
10288 case 2: code
= BFD_RELOC_16_PCREL
; break;
10290 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10291 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10294 case 8: code
= BFD_RELOC_64_PCREL
; break;
10300 switch (fixp
->fx_size
)
10303 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10304 _("can not do %d byte relocation"),
10306 code
= BFD_RELOC_32
;
10308 case 1: code
= BFD_RELOC_8
; break;
10309 case 2: code
= BFD_RELOC_16
; break;
10310 case 4: code
= BFD_RELOC_32
; break;
10312 case 8: code
= BFD_RELOC_64
; break;
10319 if ((code
== BFD_RELOC_32
10320 || code
== BFD_RELOC_32_PCREL
10321 || code
== BFD_RELOC_X86_64_32S
)
10323 && fixp
->fx_addsy
== GOT_symbol
)
10326 code
= BFD_RELOC_386_GOTPC
;
10328 code
= BFD_RELOC_X86_64_GOTPC32
;
10330 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10332 && fixp
->fx_addsy
== GOT_symbol
)
10334 code
= BFD_RELOC_X86_64_GOTPC64
;
10337 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10338 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10339 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10341 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10343 if (!use_rela_relocations
)
10345 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10346 vtable entry to be used in the relocation's section offset. */
10347 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10348 rel
->address
= fixp
->fx_offset
;
10349 #if defined (OBJ_COFF) && defined (TE_PE)
10350 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10351 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10356 /* Use the rela in 64bit mode. */
10359 if (disallow_64bit_reloc
)
10362 case BFD_RELOC_X86_64_DTPOFF64
:
10363 case BFD_RELOC_X86_64_TPOFF64
:
10364 case BFD_RELOC_64_PCREL
:
10365 case BFD_RELOC_X86_64_GOTOFF64
:
10366 case BFD_RELOC_X86_64_GOT64
:
10367 case BFD_RELOC_X86_64_GOTPCREL64
:
10368 case BFD_RELOC_X86_64_GOTPC64
:
10369 case BFD_RELOC_X86_64_GOTPLT64
:
10370 case BFD_RELOC_X86_64_PLTOFF64
:
10371 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10372 _("cannot represent relocation type %s in x32 mode"),
10373 bfd_get_reloc_code_name (code
));
10379 if (!fixp
->fx_pcrel
)
10380 rel
->addend
= fixp
->fx_offset
;
10384 case BFD_RELOC_X86_64_PLT32
:
10385 case BFD_RELOC_X86_64_PLT32_BND
:
10386 case BFD_RELOC_X86_64_GOT32
:
10387 case BFD_RELOC_X86_64_GOTPCREL
:
10388 case BFD_RELOC_X86_64_TLSGD
:
10389 case BFD_RELOC_X86_64_TLSLD
:
10390 case BFD_RELOC_X86_64_GOTTPOFF
:
10391 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10392 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10393 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10396 rel
->addend
= (section
->vma
10398 + fixp
->fx_addnumber
10399 + md_pcrel_from (fixp
));
10404 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10405 if (rel
->howto
== NULL
)
10407 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10408 _("cannot represent relocation type %s"),
10409 bfd_get_reloc_code_name (code
));
10410 /* Set howto to a garbage value so that we can keep going. */
10411 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10412 gas_assert (rel
->howto
!= NULL
);
10418 #include "tc-i386-intel.c"
10421 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10423 int saved_naked_reg
;
10424 char saved_register_dot
;
10426 saved_naked_reg
= allow_naked_reg
;
10427 allow_naked_reg
= 1;
10428 saved_register_dot
= register_chars
['.'];
10429 register_chars
['.'] = '.';
10430 allow_pseudo_reg
= 1;
10431 expression_and_evaluate (exp
);
10432 allow_pseudo_reg
= 0;
10433 register_chars
['.'] = saved_register_dot
;
10434 allow_naked_reg
= saved_naked_reg
;
10436 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10438 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10440 exp
->X_op
= O_constant
;
10441 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10442 .dw2_regnum
[flag_code
>> 1];
10445 exp
->X_op
= O_illegal
;
10450 tc_x86_frame_initial_instructions (void)
10452 static unsigned int sp_regno
[2];
10454 if (!sp_regno
[flag_code
>> 1])
10456 char *saved_input
= input_line_pointer
;
10457 char sp
[][4] = {"esp", "rsp"};
10460 input_line_pointer
= sp
[flag_code
>> 1];
10461 tc_x86_parse_to_dw2regnum (&exp
);
10462 gas_assert (exp
.X_op
== O_constant
);
10463 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10464 input_line_pointer
= saved_input
;
10467 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10468 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10472 x86_dwarf2_addr_size (void)
10474 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10475 if (x86_elf_abi
== X86_64_X32_ABI
)
10478 return bfd_arch_bits_per_address (stdoutput
) / 8;
10482 i386_elf_section_type (const char *str
, size_t len
)
10484 if (flag_code
== CODE_64BIT
10485 && len
== sizeof ("unwind") - 1
10486 && strncmp (str
, "unwind", 6) == 0)
10487 return SHT_X86_64_UNWIND
;
10494 i386_solaris_fix_up_eh_frame (segT sec
)
10496 if (flag_code
== CODE_64BIT
)
10497 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10503 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10507 exp
.X_op
= O_secrel
;
10508 exp
.X_add_symbol
= symbol
;
10509 exp
.X_add_number
= 0;
10510 emit_expr (&exp
, size
);
10514 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10515 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10518 x86_64_section_letter (int letter
, char **ptr_msg
)
10520 if (flag_code
== CODE_64BIT
)
10523 return SHF_X86_64_LARGE
;
10525 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10528 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10533 x86_64_section_word (char *str
, size_t len
)
10535 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10536 return SHF_X86_64_LARGE
;
10542 handle_large_common (int small ATTRIBUTE_UNUSED
)
10544 if (flag_code
!= CODE_64BIT
)
10546 s_comm_internal (0, elf_common_parse
);
10547 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10551 static segT lbss_section
;
10552 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10553 asection
*saved_bss_section
= bss_section
;
10555 if (lbss_section
== NULL
)
10557 flagword applicable
;
10558 segT seg
= now_seg
;
10559 subsegT subseg
= now_subseg
;
10561 /* The .lbss section is for local .largecomm symbols. */
10562 lbss_section
= subseg_new (".lbss", 0);
10563 applicable
= bfd_applicable_section_flags (stdoutput
);
10564 bfd_set_section_flags (stdoutput
, lbss_section
,
10565 applicable
& SEC_ALLOC
);
10566 seg_info (lbss_section
)->bss
= 1;
10568 subseg_set (seg
, subseg
);
10571 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10572 bss_section
= lbss_section
;
10574 s_comm_internal (0, elf_common_parse
);
10576 elf_com_section_ptr
= saved_com_section_ptr
;
10577 bss_section
= saved_bss_section
;
10580 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */