1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
63 #define INLINE __inline__
69 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
70 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
73 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
75 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
76 static int smallest_imm_type
PARAMS ((offsetT
));
77 static offsetT offset_in_range
PARAMS ((offsetT
, int));
78 static int add_prefix
PARAMS ((unsigned int));
79 static void set_code_flag
PARAMS ((int));
80 static void set_16bit_gcc_code_flag
PARAMS ((int));
81 static void set_intel_syntax
PARAMS ((int));
82 static void set_cpu_arch
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((void));
108 static void output_disp
PARAMS ((void));
110 static void s_bss
PARAMS ((int));
113 static const char *default_arch
= DEFAULT_ARCH
;
115 /* 'md_assemble ()' gathers together information and puts it into a
122 const reg_entry
*regs
;
127 /* TM holds the template for the insn were currently assembling. */
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
134 /* OPERANDS gives the number of given operands. */
135 unsigned int operands
;
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
140 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
142 /* TYPES [i] is the type (see above #defines) which tells us how to
143 use OP[i] for the corresponding operand. */
144 unsigned int types
[MAX_OPERANDS
];
146 /* Displacement expression, immediate expression, or register for each
148 union i386_op op
[MAX_OPERANDS
];
150 /* Flags for operands. */
151 unsigned int flags
[MAX_OPERANDS
];
152 #define Operand_PCrel 1
154 /* Relocation type for operand */
155 RELOC_ENUM reloc
[MAX_OPERANDS
];
157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry
*base_reg
;
160 const reg_entry
*index_reg
;
161 unsigned int log2_scale_factor
;
163 /* SEG gives the seg_entries of this insn. They are zero unless
164 explicit segment overrides are given. */
165 const seg_entry
*seg
[2];
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes
;
170 unsigned char prefix
[MAX_PREFIXES
];
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
180 typedef struct _i386_insn i386_insn
;
182 /* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
185 const char extra_symbol_chars
[] = "*%-(@[";
187 const char extra_symbol_chars
[] = "*%-([";
190 #if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
195 /* This array holds the chars that always start a comment. If the
196 pre-processor is disabled, these aren't very useful. */
197 const char comment_chars
[] = "#/";
198 #define PREFIX_SEPARATOR '\\'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars
[] = "";
211 /* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213 const char comment_chars
[] = "#";
214 #define PREFIX_SEPARATOR '/'
216 const char line_comment_chars
[] = "/";
219 const char line_separator_chars
[] = ";";
221 /* Chars that can be used to separate mant from exp in floating point
223 const char EXP_CHARS
[] = "eE";
225 /* Chars that mean this number is a floating point constant
228 const char FLT_CHARS
[] = "fFdDxX";
230 /* Tables for lexical analysis. */
231 static char mnemonic_chars
[256];
232 static char register_chars
[256];
233 static char operand_chars
[256];
234 static char identifier_chars
[256];
235 static char digit_chars
[256];
237 /* Lexical macros. */
238 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239 #define is_operand_char(x) (operand_chars[(unsigned char) x])
240 #define is_register_char(x) (register_chars[(unsigned char) x])
241 #define is_space_char(x) ((x) == ' ')
242 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243 #define is_digit_char(x) (digit_chars[(unsigned char) x])
245 /* All non-digit non-letter charcters that may occur in an operand. */
246 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
248 /* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
251 assembler instruction). */
252 static char save_stack
[32];
253 static char *save_stack_p
;
254 #define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256 #define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
259 /* The instruction we're assembling. */
262 /* Possible templates for current insn. */
263 static const templates
*current_templates
;
265 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
266 static expressionS disp_expressions
[2], im_expressions
[2];
268 /* Current operand we are working on. */
269 static int this_operand
;
271 /* We support four different modes. FLAG_CODE variable is used to distinguish
278 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
280 static enum flag_code flag_code
;
281 static int use_rela_relocations
= 0;
283 /* The names used to print error messages. */
284 static const char *flag_code_names
[] =
291 /* 1 for intel syntax,
293 static int intel_syntax
= 0;
295 /* 1 if register prefix % not required. */
296 static int allow_naked_reg
= 0;
298 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301 static char stackop_size
= '\0';
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings
= 0;
307 static const char *cpu_arch_name
= NULL
;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
312 /* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314 static unsigned int no_cond_jump_promotion
= 0;
316 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319 /* Interface to relax_segment.
320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
325 #define UNCOND_JUMP 0
327 #define COND_JUMP86 2
332 #define SMALL16 (SMALL | CODE16)
334 #define BIG16 (BIG | CODE16)
338 #define INLINE __inline__
344 #define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346 #define TYPE_FROM_RELAX_STATE(s) \
348 #define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
351 /* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
359 const relax_typeS md_relax_table
[] =
362 1) most positive reach of this state,
363 2) most negative reach of this state,
364 3) how many bytes this mode will have in the variable part of the frag
365 4) which index into the table to try if we can't fit into this one. */
367 /* UNCOND_JUMP states. */
368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
383 /* word conditionals add 3 bytes to frag:
384 1 extra opcode byte, 2 displacement bytes. */
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
398 static const arch_entry cpu_arch
[] = {
400 {"i186", Cpu086
|Cpu186
},
401 {"i286", Cpu086
|Cpu186
|Cpu286
},
402 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
403 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
404 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
405 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
406 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
407 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
408 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
409 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
410 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
411 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
415 const pseudo_typeS md_pseudo_table
[] =
417 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes
, 0},
420 {"align", s_align_ptwo
, 0},
422 {"arch", set_cpu_arch
, 0},
426 {"ffloat", float_cons
, 'f'},
427 {"dfloat", float_cons
, 'd'},
428 {"tfloat", float_cons
, 'x'},
430 {"noopt", s_ignore
, 0},
431 {"optim", s_ignore
, 0},
432 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
433 {"code16", set_code_flag
, CODE_16BIT
},
434 {"code32", set_code_flag
, CODE_32BIT
},
435 {"code64", set_code_flag
, CODE_64BIT
},
436 {"intel_syntax", set_intel_syntax
, 1},
437 {"att_syntax", set_intel_syntax
, 0},
438 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
439 {"loc", dwarf2_directive_loc
, 0},
443 /* For interface with expression (). */
444 extern char *input_line_pointer
;
446 /* Hash table for instruction mnemonic lookup. */
447 static struct hash_control
*op_hash
;
449 /* Hash table for register lookup. */
450 static struct hash_control
*reg_hash
;
453 i386_align_code (fragP
, count
)
457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
460 static const char f32_1
[] =
462 static const char f32_2
[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3
[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4
[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5
[] =
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6
[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7
[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8
[] =
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9
[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10
[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11
[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12
[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13
[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14
[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15
[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
499 static const char f16_3
[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
501 static const char f16_4
[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5
[] =
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6
[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7
[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8
[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt
[] = {
516 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
517 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
519 static const char *const f16_patt
[] = {
520 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
521 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code
== CODE_64BIT
)
529 if (count
> 0 && count
<= 15)
531 if (flag_code
== CODE_16BIT
)
533 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
534 f16_patt
[count
- 1], count
);
536 /* Adjust jump offset. */
537 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
540 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
541 f32_patt
[count
- 1], count
);
542 fragP
->fr_var
= count
;
546 static INLINE
unsigned int
547 mode_from_disp_size (t
)
550 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
554 fits_in_signed_byte (num
)
557 return (num
>= -128) && (num
<= 127);
561 fits_in_unsigned_byte (num
)
564 return (num
& 0xff) == num
;
568 fits_in_unsigned_word (num
)
571 return (num
& 0xffff) == num
;
575 fits_in_signed_word (num
)
578 return (-32768 <= num
) && (num
<= 32767);
581 fits_in_signed_long (num
)
582 offsetT num ATTRIBUTE_UNUSED
;
587 return (!(((offsetT
) -1 << 31) & num
)
588 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
590 } /* fits_in_signed_long() */
592 fits_in_unsigned_long (num
)
593 offsetT num ATTRIBUTE_UNUSED
;
598 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
600 } /* fits_in_unsigned_long() */
603 smallest_imm_type (num
)
606 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
614 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
616 return (fits_in_signed_byte (num
)
617 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
618 : fits_in_unsigned_byte (num
)
619 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
620 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
621 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
622 : fits_in_signed_long (num
)
623 ? (Imm32
| Imm32S
| Imm64
)
624 : fits_in_unsigned_long (num
)
630 offset_in_range (val
, size
)
638 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
639 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
640 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
642 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
647 /* If BFD64, sign extend val. */
648 if (!use_rela_relocations
)
649 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
650 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
652 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
654 char buf1
[40], buf2
[40];
656 sprint_value (buf1
, val
);
657 sprint_value (buf2
, val
& mask
);
658 as_warn (_("%s shortened to %s"), buf1
, buf2
);
663 /* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
673 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
674 && flag_code
== CODE_64BIT
)
682 case CS_PREFIX_OPCODE
:
683 case DS_PREFIX_OPCODE
:
684 case ES_PREFIX_OPCODE
:
685 case FS_PREFIX_OPCODE
:
686 case GS_PREFIX_OPCODE
:
687 case SS_PREFIX_OPCODE
:
691 case REPNE_PREFIX_OPCODE
:
692 case REPE_PREFIX_OPCODE
:
695 case LOCK_PREFIX_OPCODE
:
703 case ADDR_PREFIX_OPCODE
:
707 case DATA_PREFIX_OPCODE
:
712 if (i
.prefix
[q
] != 0)
714 as_bad (_("same type of prefix used twice"));
719 i
.prefix
[q
] = prefix
;
724 set_code_flag (value
)
728 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
729 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
730 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
732 as_bad (_("64bit mode not supported on this CPU."));
734 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
736 as_bad (_("32bit mode not supported on this CPU."));
742 set_16bit_gcc_code_flag (new_code_flag
)
745 flag_code
= new_code_flag
;
746 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
747 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
752 set_intel_syntax (syntax_flag
)
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg
= 0;
759 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
761 char *string
= input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "prefix") == 0)
766 else if (strcmp (string
, "noprefix") == 0)
769 as_bad (_("bad argument to syntax directive."));
770 *input_line_pointer
= e
;
772 demand_empty_rest_of_line ();
774 intel_syntax
= syntax_flag
;
776 if (ask_naked_reg
== 0)
779 allow_naked_reg
= (intel_syntax
780 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
782 /* Conservative default. */
787 allow_naked_reg
= (ask_naked_reg
< 0);
792 int dummy ATTRIBUTE_UNUSED
;
796 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
798 char *string
= input_line_pointer
;
799 int e
= get_symbol_end ();
802 for (i
= 0; cpu_arch
[i
].name
; i
++)
804 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
806 cpu_arch_name
= cpu_arch
[i
].name
;
807 cpu_arch_flags
= (cpu_arch
[i
].flags
808 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
812 if (!cpu_arch
[i
].name
)
813 as_bad (_("no such architecture: `%s'"), string
);
815 *input_line_pointer
= e
;
818 as_bad (_("missing cpu architecture"));
820 no_cond_jump_promotion
= 0;
821 if (*input_line_pointer
== ','
822 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
824 char *string
= ++input_line_pointer
;
825 int e
= get_symbol_end ();
827 if (strcmp (string
, "nojumps") == 0)
828 no_cond_jump_promotion
= 1;
829 else if (strcmp (string
, "jumps") == 0)
832 as_bad (_("no such architecture modifier: `%s'"), string
);
834 *input_line_pointer
= e
;
837 demand_empty_rest_of_line ();
844 if (!strcmp (default_arch
, "x86_64"))
845 return bfd_mach_x86_64
;
846 else if (!strcmp (default_arch
, "i386"))
847 return bfd_mach_i386_i386
;
849 as_fatal (_("Unknown architecture"));
856 const char *hash_err
;
858 /* Initialize op_hash hash table. */
859 op_hash
= hash_new ();
862 const template *optab
;
863 templates
*core_optab
;
865 /* Setup for loop. */
867 core_optab
= (templates
*) xmalloc (sizeof (templates
));
868 core_optab
->start
= optab
;
873 if (optab
->name
== NULL
874 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
876 /* different name --> ship out current template list;
877 add to hash table; & begin anew. */
878 core_optab
->end
= optab
;
879 hash_err
= hash_insert (op_hash
,
884 as_fatal (_("Internal Error: Can't hash %s: %s"),
888 if (optab
->name
== NULL
)
890 core_optab
= (templates
*) xmalloc (sizeof (templates
));
891 core_optab
->start
= optab
;
896 /* Initialize reg_hash hash table. */
897 reg_hash
= hash_new ();
899 const reg_entry
*regtab
;
901 for (regtab
= i386_regtab
;
902 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
905 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
907 as_fatal (_("Internal Error: Can't hash %s: %s"),
913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
918 for (c
= 0; c
< 256; c
++)
923 mnemonic_chars
[c
] = c
;
924 register_chars
[c
] = c
;
925 operand_chars
[c
] = c
;
927 else if (ISLOWER (c
))
929 mnemonic_chars
[c
] = c
;
930 register_chars
[c
] = c
;
931 operand_chars
[c
] = c
;
933 else if (ISUPPER (c
))
935 mnemonic_chars
[c
] = TOLOWER (c
);
936 register_chars
[c
] = mnemonic_chars
[c
];
937 operand_chars
[c
] = c
;
940 if (ISALPHA (c
) || ISDIGIT (c
))
941 identifier_chars
[c
] = c
;
944 identifier_chars
[c
] = c
;
945 operand_chars
[c
] = c
;
950 identifier_chars
['@'] = '@';
952 digit_chars
['-'] = '-';
953 identifier_chars
['_'] = '_';
954 identifier_chars
['.'] = '.';
956 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
957 operand_chars
[(unsigned char) *p
] = *p
;
960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
963 record_alignment (text_section
, 2);
964 record_alignment (data_section
, 2);
965 record_alignment (bss_section
, 2);
971 i386_print_statistics (file
)
974 hash_print_statistics (file
, "i386 opcode", op_hash
);
975 hash_print_statistics (file
, "i386 register", reg_hash
);
980 /* Debugging routines for md_assemble. */
981 static void pi
PARAMS ((char *, i386_insn
*));
982 static void pte
PARAMS ((template *));
983 static void pt
PARAMS ((unsigned int));
984 static void pe
PARAMS ((expressionS
*));
985 static void ps
PARAMS ((symbolS
*));
994 fprintf (stdout
, "%s: template ", line
);
996 fprintf (stdout
, " address: base %s index %s scale %x\n",
997 x
->base_reg
? x
->base_reg
->reg_name
: "none",
998 x
->index_reg
? x
->index_reg
->reg_name
: "none",
999 x
->log2_scale_factor
);
1000 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1001 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1002 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1003 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1004 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1005 (x
->rex
& REX_MODE64
) != 0,
1006 (x
->rex
& REX_EXTX
) != 0,
1007 (x
->rex
& REX_EXTY
) != 0,
1008 (x
->rex
& REX_EXTZ
) != 0);
1009 for (i
= 0; i
< x
->operands
; i
++)
1011 fprintf (stdout
, " #%d: ", i
+ 1);
1013 fprintf (stdout
, "\n");
1015 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1016 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1017 if (x
->types
[i
] & Imm
)
1019 if (x
->types
[i
] & Disp
)
1020 pe (x
->op
[i
].disps
);
1029 fprintf (stdout
, " %d operands ", t
->operands
);
1030 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1031 if (t
->extension_opcode
!= None
)
1032 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1033 if (t
->opcode_modifier
& D
)
1034 fprintf (stdout
, "D");
1035 if (t
->opcode_modifier
& W
)
1036 fprintf (stdout
, "W");
1037 fprintf (stdout
, "\n");
1038 for (i
= 0; i
< t
->operands
; i
++)
1040 fprintf (stdout
, " #%d type ", i
+ 1);
1041 pt (t
->operand_types
[i
]);
1042 fprintf (stdout
, "\n");
1050 fprintf (stdout
, " operation %d\n", e
->X_op
);
1051 fprintf (stdout
, " add_number %ld (%lx)\n",
1052 (long) e
->X_add_number
, (long) e
->X_add_number
);
1053 if (e
->X_add_symbol
)
1055 fprintf (stdout
, " add_symbol ");
1056 ps (e
->X_add_symbol
);
1057 fprintf (stdout
, "\n");
1061 fprintf (stdout
, " op_symbol ");
1062 ps (e
->X_op_symbol
);
1063 fprintf (stdout
, "\n");
1071 fprintf (stdout
, "%s type %s%s",
1073 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s
)));
1083 static const type_names
[] =
1096 { BaseIndex
, "BaseIndex" },
1100 { Disp32S
, "d32s" },
1102 { InOutPortReg
, "InOutPortReg" },
1103 { ShiftCount
, "ShiftCount" },
1104 { Control
, "control reg" },
1105 { Test
, "test reg" },
1106 { Debug
, "debug reg" },
1107 { FloatReg
, "FReg" },
1108 { FloatAcc
, "FAcc" },
1112 { JumpAbsolute
, "Jump Absolute" },
1123 const struct type_name
*ty
;
1125 for (ty
= type_names
; ty
->mask
; ty
++)
1127 fprintf (stdout
, "%s, ", ty
->tname
);
1131 #endif /* DEBUG386 */
1133 #ifdef BFD_ASSEMBLER
1134 static bfd_reloc_code_real_type reloc
1135 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1137 static bfd_reloc_code_real_type
1138 reloc (size
, pcrel
, sign
, other
)
1142 bfd_reloc_code_real_type other
;
1144 if (other
!= NO_RELOC
)
1150 as_bad (_("There are no unsigned pc-relative relocations"));
1153 case 1: return BFD_RELOC_8_PCREL
;
1154 case 2: return BFD_RELOC_16_PCREL
;
1155 case 4: return BFD_RELOC_32_PCREL
;
1157 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1164 case 4: return BFD_RELOC_X86_64_32S
;
1169 case 1: return BFD_RELOC_8
;
1170 case 2: return BFD_RELOC_16
;
1171 case 4: return BFD_RELOC_32
;
1172 case 8: return BFD_RELOC_64
;
1174 as_bad (_("can not do %s %d byte relocation"),
1175 sign
? "signed" : "unsigned", size
);
1179 return BFD_RELOC_NONE
;
1182 /* Here we decide which fixups can be adjusted to make them relative to
1183 the beginning of the section instead of the symbol. Basically we need
1184 to make sure that the dynamic relocations are done correctly, so in
1185 some cases we force the original symbol to be used. */
1188 tc_i386_fix_adjustable (fixP
)
1191 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1192 /* Prevent all adjustments to global symbols, or else dynamic
1193 linking will not work correctly. */
1194 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1195 || S_IS_WEAK (fixP
->fx_addsy
)
1196 /* Don't adjust pc-relative references to merge sections in 64-bit
1198 || (use_rela_relocations
1199 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1203 /* adjust_reloc_syms doesn't know about the GOT. */
1204 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1205 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1206 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1207 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1208 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1209 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1210 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1211 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1212 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1213 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1214 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1215 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1216 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1217 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1222 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1223 #define BFD_RELOC_8 0
1224 #define BFD_RELOC_16 0
1225 #define BFD_RELOC_32 0
1226 #define BFD_RELOC_8_PCREL 0
1227 #define BFD_RELOC_16_PCREL 0
1228 #define BFD_RELOC_32_PCREL 0
1229 #define BFD_RELOC_386_PLT32 0
1230 #define BFD_RELOC_386_GOT32 0
1231 #define BFD_RELOC_386_GOTOFF 0
1232 #define BFD_RELOC_386_TLS_GD 0
1233 #define BFD_RELOC_386_TLS_LDM 0
1234 #define BFD_RELOC_386_TLS_LDO_32 0
1235 #define BFD_RELOC_386_TLS_IE_32 0
1236 #define BFD_RELOC_386_TLS_LE_32 0
1237 #define BFD_RELOC_386_TLS_LE 0
1238 #define BFD_RELOC_X86_64_PLT32 0
1239 #define BFD_RELOC_X86_64_GOT32 0
1240 #define BFD_RELOC_X86_64_GOTPCREL 0
1243 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1246 intel_float_operand (mnemonic
)
1247 const char *mnemonic
;
1249 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1252 if (mnemonic
[0] == 'f')
1258 /* This is the guts of the machine-dependent assembler. LINE points to a
1259 machine dependent instruction. This function is supposed to emit
1260 the frags/bytes it assembles to. */
1267 char mnemonic
[MAX_MNEM_SIZE
];
1269 /* Initialize globals. */
1270 memset (&i
, '\0', sizeof (i
));
1271 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1272 i
.reloc
[j
] = NO_RELOC
;
1273 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1274 memset (im_expressions
, '\0', sizeof (im_expressions
));
1275 save_stack_p
= save_stack
;
1277 /* First parse an instruction mnemonic & call i386_operand for the operands.
1278 We assume that the scrubber has arranged it so that line[0] is the valid
1279 start of a (possibly prefixed) mnemonic. */
1281 line
= parse_insn (line
, mnemonic
);
1285 line
= parse_operands (line
, mnemonic
);
1289 /* Now we've parsed the mnemonic into a set of templates, and have the
1290 operands at hand. */
1292 /* All intel opcodes have reversed operands except for "bound" and
1293 "enter". We also don't reverse intersegment "jmp" and "call"
1294 instructions with 2 immediate operands so that the immediate segment
1295 precedes the offset, as it does when in AT&T mode. "enter" and the
1296 intersegment "jmp" and "call" instructions are the only ones that
1297 have two immediate operands. */
1298 if (intel_syntax
&& i
.operands
> 1
1299 && (strcmp (mnemonic
, "bound") != 0)
1300 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1306 if (i
.disp_operands
)
1309 /* Next, we find a template that matches the given insn,
1310 making sure the overlap of the given operands types is consistent
1311 with the template operand types. */
1313 if (!match_template ())
1318 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1320 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1321 i
.tm
.base_opcode
^= FloatR
;
1323 /* Zap movzx and movsx suffix. The suffix may have been set from
1324 "word ptr" or "byte ptr" on the source operand, but we'll use
1325 the suffix later to choose the destination register. */
1326 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1330 if (i
.tm
.opcode_modifier
& FWait
)
1331 if (!add_prefix (FWAIT_OPCODE
))
1334 /* Check string instruction segment overrides. */
1335 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1337 if (!check_string ())
1341 if (!process_suffix ())
1344 /* Make still unresolved immediate matches conform to size of immediate
1345 given in i.suffix. */
1346 if (!finalize_imm ())
1349 if (i
.types
[0] & Imm1
)
1350 i
.imm_operands
= 0; /* kludge for shift insns. */
1351 if (i
.types
[0] & ImplicitRegister
)
1353 if (i
.types
[1] & ImplicitRegister
)
1355 if (i
.types
[2] & ImplicitRegister
)
1358 if (i
.tm
.opcode_modifier
& ImmExt
)
1360 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1361 opcode suffix which is coded in the same place as an 8-bit
1362 immediate field would be. Here we fake an 8-bit immediate
1363 operand from the opcode suffix stored in tm.extension_opcode. */
1367 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1369 exp
= &im_expressions
[i
.imm_operands
++];
1370 i
.op
[i
.operands
].imms
= exp
;
1371 i
.types
[i
.operands
++] = Imm8
;
1372 exp
->X_op
= O_constant
;
1373 exp
->X_add_number
= i
.tm
.extension_opcode
;
1374 i
.tm
.extension_opcode
= None
;
1377 /* For insns with operands there are more diddles to do to the opcode. */
1380 if (!process_operands ())
1383 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1385 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1386 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1389 /* Handle conversion of 'int $3' --> special int3 insn. */
1390 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1392 i
.tm
.base_opcode
= INT3_OPCODE
;
1396 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1397 && i
.op
[0].disps
->X_op
== O_constant
)
1399 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1400 the absolute address given by the constant. Since ix86 jumps and
1401 calls are pc relative, we need to generate a reloc. */
1402 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1403 i
.op
[0].disps
->X_op
= O_symbol
;
1406 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1407 i
.rex
|= REX_MODE64
;
1409 /* For 8 bit registers we need an empty rex prefix. Also if the
1410 instruction already has a prefix, we need to convert old
1411 registers to new ones. */
1413 if (((i
.types
[0] & Reg8
) != 0
1414 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1415 || ((i
.types
[1] & Reg8
) != 0
1416 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1417 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1422 i
.rex
|= REX_OPCODE
;
1423 for (x
= 0; x
< 2; x
++)
1425 /* Look for 8 bit operand that uses old registers. */
1426 if ((i
.types
[x
] & Reg8
) != 0
1427 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1429 /* In case it is "hi" register, give up. */
1430 if (i
.op
[x
].regs
->reg_num
> 3)
1431 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1432 i
.op
[x
].regs
->reg_name
);
1434 /* Otherwise it is equivalent to the extended register.
1435 Since the encoding doesn't change this is merely
1436 cosmetic cleanup for debug output. */
1438 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1444 add_prefix (REX_OPCODE
| i
.rex
);
1446 /* We are ready to output the insn. */
1451 parse_insn (line
, mnemonic
)
1456 char *token_start
= l
;
1459 /* Non-zero if we found a prefix only acceptable with string insns. */
1460 const char *expecting_string_instruction
= NULL
;
1465 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1468 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1470 as_bad (_("no such instruction: `%s'"), token_start
);
1475 if (!is_space_char (*l
)
1476 && *l
!= END_OF_INSN
1477 && *l
!= PREFIX_SEPARATOR
1480 as_bad (_("invalid character %s in mnemonic"),
1481 output_invalid (*l
));
1484 if (token_start
== l
)
1486 if (*l
== PREFIX_SEPARATOR
)
1487 as_bad (_("expecting prefix; got nothing"));
1489 as_bad (_("expecting mnemonic; got nothing"));
1493 /* Look up instruction (or prefix) via hash table. */
1494 current_templates
= hash_find (op_hash
, mnemonic
);
1496 if (*l
!= END_OF_INSN
1497 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1498 && current_templates
1499 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1501 /* If we are in 16-bit mode, do not allow addr16 or data16.
1502 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1503 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1504 && flag_code
!= CODE_64BIT
1505 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1506 ^ (flag_code
== CODE_16BIT
)))
1508 as_bad (_("redundant %s prefix"),
1509 current_templates
->start
->name
);
1512 /* Add prefix, checking for repeated prefixes. */
1513 switch (add_prefix (current_templates
->start
->base_opcode
))
1518 expecting_string_instruction
= current_templates
->start
->name
;
1521 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1528 if (!current_templates
)
1530 /* See if we can get a match by trimming off a suffix. */
1533 case WORD_MNEM_SUFFIX
:
1534 case BYTE_MNEM_SUFFIX
:
1535 case QWORD_MNEM_SUFFIX
:
1536 i
.suffix
= mnem_p
[-1];
1538 current_templates
= hash_find (op_hash
, mnemonic
);
1540 case SHORT_MNEM_SUFFIX
:
1541 case LONG_MNEM_SUFFIX
:
1544 i
.suffix
= mnem_p
[-1];
1546 current_templates
= hash_find (op_hash
, mnemonic
);
1554 if (intel_float_operand (mnemonic
))
1555 i
.suffix
= SHORT_MNEM_SUFFIX
;
1557 i
.suffix
= LONG_MNEM_SUFFIX
;
1559 current_templates
= hash_find (op_hash
, mnemonic
);
1563 if (!current_templates
)
1565 as_bad (_("no such instruction: `%s'"), token_start
);
1570 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1572 /* Check for a branch hint. We allow ",pt" and ",pn" for
1573 predict taken and predict not taken respectively.
1574 I'm not sure that branch hints actually do anything on loop
1575 and jcxz insns (JumpByte) for current Pentium4 chips. They
1576 may work in the future and it doesn't hurt to accept them
1578 if (l
[0] == ',' && l
[1] == 'p')
1582 if (!add_prefix (DS_PREFIX_OPCODE
))
1586 else if (l
[2] == 'n')
1588 if (!add_prefix (CS_PREFIX_OPCODE
))
1594 /* Any other comma loses. */
1597 as_bad (_("invalid character %s in mnemonic"),
1598 output_invalid (*l
));
1602 /* Check if instruction is supported on specified architecture. */
1603 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1604 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1606 as_warn (_("`%s' is not supported on `%s'"),
1607 current_templates
->start
->name
, cpu_arch_name
);
1609 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1611 as_warn (_("use .code16 to ensure correct addressing mode"));
1614 /* Check for rep/repne without a string instruction. */
1615 if (expecting_string_instruction
1616 && !(current_templates
->start
->opcode_modifier
& IsString
))
1618 as_bad (_("expecting string instruction after `%s'"),
1619 expecting_string_instruction
);
1627 parse_operands (l
, mnemonic
)
1629 const char *mnemonic
;
1633 /* 1 if operand is pending after ','. */
1634 unsigned int expecting_operand
= 0;
1636 /* Non-zero if operand parens not balanced. */
1637 unsigned int paren_not_balanced
;
1639 while (*l
!= END_OF_INSN
)
1641 /* Skip optional white space before operand. */
1642 if (is_space_char (*l
))
1644 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1646 as_bad (_("invalid character %s before operand %d"),
1647 output_invalid (*l
),
1651 token_start
= l
; /* after white space */
1652 paren_not_balanced
= 0;
1653 while (paren_not_balanced
|| *l
!= ',')
1655 if (*l
== END_OF_INSN
)
1657 if (paren_not_balanced
)
1660 as_bad (_("unbalanced parenthesis in operand %d."),
1663 as_bad (_("unbalanced brackets in operand %d."),
1668 break; /* we are done */
1670 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1672 as_bad (_("invalid character %s in operand %d"),
1673 output_invalid (*l
),
1680 ++paren_not_balanced
;
1682 --paren_not_balanced
;
1687 ++paren_not_balanced
;
1689 --paren_not_balanced
;
1693 if (l
!= token_start
)
1694 { /* Yes, we've read in another operand. */
1695 unsigned int operand_ok
;
1696 this_operand
= i
.operands
++;
1697 if (i
.operands
> MAX_OPERANDS
)
1699 as_bad (_("spurious operands; (%d operands/instruction max)"),
1703 /* Now parse operand adding info to 'i' as we go along. */
1704 END_STRING_AND_SAVE (l
);
1708 i386_intel_operand (token_start
,
1709 intel_float_operand (mnemonic
));
1711 operand_ok
= i386_operand (token_start
);
1713 RESTORE_END_STRING (l
);
1719 if (expecting_operand
)
1721 expecting_operand_after_comma
:
1722 as_bad (_("expecting operand after ','; got nothing"));
1727 as_bad (_("expecting operand before ','; got nothing"));
1732 /* Now *l must be either ',' or END_OF_INSN. */
1735 if (*++l
== END_OF_INSN
)
1737 /* Just skip it, if it's \n complain. */
1738 goto expecting_operand_after_comma
;
1740 expecting_operand
= 1;
1749 union i386_op temp_op
;
1750 unsigned int temp_type
;
1751 RELOC_ENUM temp_reloc
;
1755 if (i
.operands
== 2)
1760 else if (i
.operands
== 3)
1765 temp_type
= i
.types
[xchg2
];
1766 i
.types
[xchg2
] = i
.types
[xchg1
];
1767 i
.types
[xchg1
] = temp_type
;
1768 temp_op
= i
.op
[xchg2
];
1769 i
.op
[xchg2
] = i
.op
[xchg1
];
1770 i
.op
[xchg1
] = temp_op
;
1771 temp_reloc
= i
.reloc
[xchg2
];
1772 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1773 i
.reloc
[xchg1
] = temp_reloc
;
1775 if (i
.mem_operands
== 2)
1777 const seg_entry
*temp_seg
;
1778 temp_seg
= i
.seg
[0];
1779 i
.seg
[0] = i
.seg
[1];
1780 i
.seg
[1] = temp_seg
;
1784 /* Try to ensure constant immediates are represented in the smallest
1789 char guess_suffix
= 0;
1793 guess_suffix
= i
.suffix
;
1794 else if (i
.reg_operands
)
1796 /* Figure out a suffix from the last register operand specified.
1797 We can't do this properly yet, ie. excluding InOutPortReg,
1798 but the following works for instructions with immediates.
1799 In any case, we can't set i.suffix yet. */
1800 for (op
= i
.operands
; --op
>= 0;)
1801 if (i
.types
[op
] & Reg
)
1803 if (i
.types
[op
] & Reg8
)
1804 guess_suffix
= BYTE_MNEM_SUFFIX
;
1805 else if (i
.types
[op
] & Reg16
)
1806 guess_suffix
= WORD_MNEM_SUFFIX
;
1807 else if (i
.types
[op
] & Reg32
)
1808 guess_suffix
= LONG_MNEM_SUFFIX
;
1809 else if (i
.types
[op
] & Reg64
)
1810 guess_suffix
= QWORD_MNEM_SUFFIX
;
1814 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1815 guess_suffix
= WORD_MNEM_SUFFIX
;
1817 for (op
= i
.operands
; --op
>= 0;)
1818 if (i
.types
[op
] & Imm
)
1820 switch (i
.op
[op
].imms
->X_op
)
1823 /* If a suffix is given, this operand may be shortened. */
1824 switch (guess_suffix
)
1826 case LONG_MNEM_SUFFIX
:
1827 i
.types
[op
] |= Imm32
| Imm64
;
1829 case WORD_MNEM_SUFFIX
:
1830 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1832 case BYTE_MNEM_SUFFIX
:
1833 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1837 /* If this operand is at most 16 bits, convert it
1838 to a signed 16 bit number before trying to see
1839 whether it will fit in an even smaller size.
1840 This allows a 16-bit operand such as $0xffe0 to
1841 be recognised as within Imm8S range. */
1842 if ((i
.types
[op
] & Imm16
)
1843 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1845 i
.op
[op
].imms
->X_add_number
=
1846 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1848 if ((i
.types
[op
] & Imm32
)
1849 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1852 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1853 ^ ((offsetT
) 1 << 31))
1854 - ((offsetT
) 1 << 31));
1856 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1858 /* We must avoid matching of Imm32 templates when 64bit
1859 only immediate is available. */
1860 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1861 i
.types
[op
] &= ~Imm32
;
1868 /* Symbols and expressions. */
1870 /* Convert symbolic operand to proper sizes for matching. */
1871 switch (guess_suffix
)
1873 case QWORD_MNEM_SUFFIX
:
1874 i
.types
[op
] = Imm64
| Imm32S
;
1876 case LONG_MNEM_SUFFIX
:
1877 i
.types
[op
] = Imm32
| Imm64
;
1879 case WORD_MNEM_SUFFIX
:
1880 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1883 case BYTE_MNEM_SUFFIX
:
1884 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1893 /* Try to use the smallest displacement type too. */
1899 for (op
= i
.operands
; --op
>= 0;)
1900 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1902 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1904 if (i
.types
[op
] & Disp16
)
1906 /* We know this operand is at most 16 bits, so
1907 convert to a signed 16 bit number before trying
1908 to see whether it will fit in an even smaller
1911 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1913 else if (i
.types
[op
] & Disp32
)
1915 /* We know this operand is at most 32 bits, so convert to a
1916 signed 32 bit number before trying to see whether it will
1917 fit in an even smaller size. */
1918 disp
&= (((offsetT
) 2 << 31) - 1);
1919 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1921 if (flag_code
== CODE_64BIT
)
1923 if (fits_in_signed_long (disp
))
1924 i
.types
[op
] |= Disp32S
;
1925 if (fits_in_unsigned_long (disp
))
1926 i
.types
[op
] |= Disp32
;
1928 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1929 && fits_in_signed_byte (disp
))
1930 i
.types
[op
] |= Disp8
;
1937 /* Points to template once we've found it. */
1939 unsigned int overlap0
, overlap1
, overlap2
;
1940 unsigned int found_reverse_match
;
1943 #define MATCH(overlap, given, template) \
1944 ((overlap & ~JumpAbsolute) \
1945 && (((given) & (BaseIndex | JumpAbsolute)) \
1946 == ((overlap) & (BaseIndex | JumpAbsolute))))
1948 /* If given types r0 and r1 are registers they must be of the same type
1949 unless the expected operand type register overlap is null.
1950 Note that Acc in a template matches every size of reg. */
1951 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1952 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1953 || ((g0) & Reg) == ((g1) & Reg) \
1954 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1959 found_reverse_match
= 0;
1960 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1962 : (i
.suffix
== WORD_MNEM_SUFFIX
1964 : (i
.suffix
== SHORT_MNEM_SUFFIX
1966 : (i
.suffix
== LONG_MNEM_SUFFIX
1968 : (i
.suffix
== QWORD_MNEM_SUFFIX
1970 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1971 ? No_xSuf
: 0))))));
1973 for (t
= current_templates
->start
;
1974 t
< current_templates
->end
;
1977 /* Must have right number of operands. */
1978 if (i
.operands
!= t
->operands
)
1981 /* Check the suffix, except for some instructions in intel mode. */
1982 if ((t
->opcode_modifier
& suffix_check
)
1984 && (t
->opcode_modifier
& IgnoreSize
))
1986 && t
->base_opcode
== 0xd9
1987 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1988 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1991 /* Do not verify operands when there are none. */
1992 else if (!t
->operands
)
1994 if (t
->cpu_flags
& ~cpu_arch_flags
)
1996 /* We've found a match; break out of loop. */
2000 overlap0
= i
.types
[0] & t
->operand_types
[0];
2001 switch (t
->operands
)
2004 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2009 overlap1
= i
.types
[1] & t
->operand_types
[1];
2010 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2011 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2012 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2013 t
->operand_types
[0],
2014 overlap1
, i
.types
[1],
2015 t
->operand_types
[1]))
2017 /* Check if other direction is valid ... */
2018 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2021 /* Try reversing direction of operands. */
2022 overlap0
= i
.types
[0] & t
->operand_types
[1];
2023 overlap1
= i
.types
[1] & t
->operand_types
[0];
2024 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2025 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2026 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2027 t
->operand_types
[1],
2028 overlap1
, i
.types
[1],
2029 t
->operand_types
[0]))
2031 /* Does not match either direction. */
2034 /* found_reverse_match holds which of D or FloatDR
2036 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2038 /* Found a forward 2 operand match here. */
2039 else if (t
->operands
== 3)
2041 /* Here we make use of the fact that there are no
2042 reverse match 3 operand instructions, and all 3
2043 operand instructions only need to be checked for
2044 register consistency between operands 2 and 3. */
2045 overlap2
= i
.types
[2] & t
->operand_types
[2];
2046 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2047 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2048 t
->operand_types
[1],
2049 overlap2
, i
.types
[2],
2050 t
->operand_types
[2]))
2054 /* Found either forward/reverse 2 or 3 operand match here:
2055 slip through to break. */
2057 if (t
->cpu_flags
& ~cpu_arch_flags
)
2059 found_reverse_match
= 0;
2062 /* We've found a match; break out of loop. */
2066 if (t
== current_templates
->end
)
2068 /* We found no match. */
2069 as_bad (_("suffix or operands invalid for `%s'"),
2070 current_templates
->start
->name
);
2074 if (!quiet_warnings
)
2077 && ((i
.types
[0] & JumpAbsolute
)
2078 != (t
->operand_types
[0] & JumpAbsolute
)))
2080 as_warn (_("indirect %s without `*'"), t
->name
);
2083 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2084 == (IsPrefix
| IgnoreSize
))
2086 /* Warn them that a data or address size prefix doesn't
2087 affect assembly of the next line of code. */
2088 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2092 /* Copy the template we found. */
2094 if (found_reverse_match
)
2096 /* If we found a reverse match we must alter the opcode
2097 direction bit. found_reverse_match holds bits to change
2098 (different for int & float insns). */
2100 i
.tm
.base_opcode
^= found_reverse_match
;
2102 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2103 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2112 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2113 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2115 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2117 as_bad (_("`%s' operand %d must use `%%es' segment"),
2122 /* There's only ever one segment override allowed per instruction.
2123 This instruction possibly has a legal segment override on the
2124 second operand, so copy the segment to where non-string
2125 instructions store it, allowing common code. */
2126 i
.seg
[0] = i
.seg
[1];
2128 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2130 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2132 as_bad (_("`%s' operand %d must use `%%es' segment"),
2144 /* If matched instruction specifies an explicit instruction mnemonic
2146 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2148 if (i
.tm
.opcode_modifier
& Size16
)
2149 i
.suffix
= WORD_MNEM_SUFFIX
;
2150 else if (i
.tm
.opcode_modifier
& Size64
)
2151 i
.suffix
= QWORD_MNEM_SUFFIX
;
2153 i
.suffix
= LONG_MNEM_SUFFIX
;
2155 else if (i
.reg_operands
)
2157 /* If there's no instruction mnemonic suffix we try to invent one
2158 based on register operands. */
2161 /* We take i.suffix from the last register operand specified,
2162 Destination register type is more significant than source
2165 for (op
= i
.operands
; --op
>= 0;)
2166 if ((i
.types
[op
] & Reg
)
2167 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2169 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2170 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2171 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2176 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2178 if (!check_byte_reg ())
2181 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2183 if (!check_long_reg ())
2186 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2188 if (!check_qword_reg ())
2191 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2193 if (!check_word_reg ())
2196 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2197 /* Do nothing if the instruction is going to ignore the prefix. */
2202 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2204 i
.suffix
= stackop_size
;
2207 /* Change the opcode based on the operand size given by i.suffix;
2208 We need not change things for byte insns. */
2210 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2212 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2216 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2218 /* It's not a byte, select word/dword operation. */
2219 if (i
.tm
.opcode_modifier
& W
)
2221 if (i
.tm
.opcode_modifier
& ShortForm
)
2222 i
.tm
.base_opcode
|= 8;
2224 i
.tm
.base_opcode
|= 1;
2227 /* Now select between word & dword operations via the operand
2228 size prefix, except for instructions that will ignore this
2230 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2231 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2232 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2234 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2235 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2236 prefix
= ADDR_PREFIX_OPCODE
;
2238 if (!add_prefix (prefix
))
2242 if (i
.suffix
!= QWORD_MNEM_SUFFIX
&& (flag_code
== CODE_64BIT
)
2243 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2244 && (i
.tm
.opcode_modifier
& JumpByte
))
2246 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2250 /* Set mode64 for an operand. */
2251 if (i
.suffix
== QWORD_MNEM_SUFFIX
2252 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2254 i
.rex
|= REX_MODE64
;
2255 if (flag_code
< CODE_64BIT
)
2257 as_bad (_("64bit operations available only in 64bit modes."));
2262 /* Size floating point instruction. */
2263 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2265 if (i
.tm
.opcode_modifier
& FloatMF
)
2266 i
.tm
.base_opcode
^= 4;
2277 for (op
= i
.operands
; --op
>= 0;)
2279 /* If this is an eight bit register, it's OK. If it's the 16 or
2280 32 bit version of an eight bit register, we will just use the
2281 low portion, and that's OK too. */
2282 if (i
.types
[op
] & Reg8
)
2285 /* movzx and movsx should not generate this warning. */
2287 && (i
.tm
.base_opcode
== 0xfb7
2288 || i
.tm
.base_opcode
== 0xfb6
2289 || i
.tm
.base_opcode
== 0x63
2290 || i
.tm
.base_opcode
== 0xfbe
2291 || i
.tm
.base_opcode
== 0xfbf))
2294 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2296 /* Check that the template allows eight bit regs. This
2297 kills insns such as `orb $1,%edx', which maybe should be
2299 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2303 /* Prohibit these changes in the 64bit mode, since the
2304 lowering is more complicated. */
2305 if (flag_code
== CODE_64BIT
2306 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2308 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2309 i
.op
[op
].regs
->reg_name
,
2313 #if REGISTER_WARNINGS
2315 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2316 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2317 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2318 ? REGNAM_AL
- REGNAM_AX
2319 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2320 i
.op
[op
].regs
->reg_name
,
2325 /* Any other register is bad. */
2326 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2328 | Control
| Debug
| Test
2329 | FloatReg
| FloatAcc
))
2331 as_bad (_("`%%%s' not allowed with `%s%c'"),
2332 i
.op
[op
].regs
->reg_name
,
2346 for (op
= i
.operands
; --op
>= 0;)
2347 /* Reject eight bit registers, except where the template requires
2348 them. (eg. movzb) */
2349 if ((i
.types
[op
] & Reg8
) != 0
2350 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2352 as_bad (_("`%%%s' not allowed with `%s%c'"),
2353 i
.op
[op
].regs
->reg_name
,
2358 /* Warn if the e prefix on a general reg is missing. */
2359 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2360 && (i
.types
[op
] & Reg16
) != 0
2361 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2363 /* Prohibit these changes in the 64bit mode, since the
2364 lowering is more complicated. */
2365 if (flag_code
== CODE_64BIT
)
2367 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2368 i
.op
[op
].regs
->reg_name
,
2372 #if REGISTER_WARNINGS
2374 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2375 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2376 i
.op
[op
].regs
->reg_name
,
2380 /* Warn if the r prefix on a general reg is missing. */
2381 else if ((i
.types
[op
] & Reg64
) != 0
2382 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2384 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2385 i
.op
[op
].regs
->reg_name
,
2397 for (op
= i
.operands
; --op
>= 0; )
2398 /* Reject eight bit registers, except where the template requires
2399 them. (eg. movzb) */
2400 if ((i
.types
[op
] & Reg8
) != 0
2401 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2403 as_bad (_("`%%%s' not allowed with `%s%c'"),
2404 i
.op
[op
].regs
->reg_name
,
2409 /* Warn if the e prefix on a general reg is missing. */
2410 else if (((i
.types
[op
] & Reg16
) != 0
2411 || (i
.types
[op
] & Reg32
) != 0)
2412 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2414 /* Prohibit these changes in the 64bit mode, since the
2415 lowering is more complicated. */
2416 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2417 i
.op
[op
].regs
->reg_name
,
2428 for (op
= i
.operands
; --op
>= 0;)
2429 /* Reject eight bit registers, except where the template requires
2430 them. (eg. movzb) */
2431 if ((i
.types
[op
] & Reg8
) != 0
2432 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2434 as_bad (_("`%%%s' not allowed with `%s%c'"),
2435 i
.op
[op
].regs
->reg_name
,
2440 /* Warn if the e prefix on a general reg is present. */
2441 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2442 && (i
.types
[op
] & Reg32
) != 0
2443 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2445 /* Prohibit these changes in the 64bit mode, since the
2446 lowering is more complicated. */
2447 if (flag_code
== CODE_64BIT
)
2449 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2450 i
.op
[op
].regs
->reg_name
,
2455 #if REGISTER_WARNINGS
2456 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2457 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2458 i
.op
[op
].regs
->reg_name
,
2468 unsigned int overlap0
, overlap1
, overlap2
;
2470 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2471 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2472 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2473 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2474 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2478 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2480 : (i
.suffix
== WORD_MNEM_SUFFIX
2482 : (i
.suffix
== QWORD_MNEM_SUFFIX
2486 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2487 || overlap0
== (Imm16
| Imm32
)
2488 || overlap0
== (Imm16
| Imm32S
))
2490 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2493 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2494 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2495 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2497 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2501 i
.types
[0] = overlap0
;
2503 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2504 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2505 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2506 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2507 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2511 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2513 : (i
.suffix
== WORD_MNEM_SUFFIX
2515 : (i
.suffix
== QWORD_MNEM_SUFFIX
2519 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2520 || overlap1
== (Imm16
| Imm32
)
2521 || overlap1
== (Imm16
| Imm32S
))
2523 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2526 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2527 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2528 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2530 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2534 i
.types
[1] = overlap1
;
2536 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2537 assert ((overlap2
& Imm
) == 0);
2538 i
.types
[2] = overlap2
;
2546 /* Default segment register this instruction will use for memory
2547 accesses. 0 means unknown. This is only for optimizing out
2548 unnecessary segment overrides. */
2549 const seg_entry
*default_seg
= 0;
2551 /* The imul $imm, %reg instruction is converted into
2552 imul $imm, %reg, %reg, and the clr %reg instruction
2553 is converted into xor %reg, %reg. */
2554 if (i
.tm
.opcode_modifier
& regKludge
)
2556 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2557 /* Pretend we saw the extra register operand. */
2558 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2559 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2560 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2564 if (i
.tm
.opcode_modifier
& ShortForm
)
2566 /* The register or float register operand is in operand 0 or 1. */
2567 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2568 /* Register goes in low 3 bits of opcode. */
2569 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2570 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2572 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2574 /* Warn about some common errors, but press on regardless.
2575 The first case can be generated by gcc (<= 2.8.1). */
2576 if (i
.operands
== 2)
2578 /* Reversed arguments on faddp, fsubp, etc. */
2579 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2580 i
.op
[1].regs
->reg_name
,
2581 i
.op
[0].regs
->reg_name
);
2585 /* Extraneous `l' suffix on fp insn. */
2586 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2587 i
.op
[0].regs
->reg_name
);
2591 else if (i
.tm
.opcode_modifier
& Modrm
)
2593 /* The opcode is completed (modulo i.tm.extension_opcode which
2594 must be put into the modrm byte).
2595 Now, we make the modrm & index base bytes based on all the
2596 info we've collected. */
2598 default_seg
= build_modrm_byte ();
2600 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2602 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2603 && i
.op
[0].regs
->reg_num
== 1)
2605 as_bad (_("you can't `pop %%cs'"));
2608 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2609 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2612 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2616 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2618 /* For the string instructions that allow a segment override
2619 on one of their operands, the default segment is ds. */
2623 /* If a segment was explicitly specified,
2624 and the specified segment is not the default,
2625 use an opcode prefix to select it.
2626 If we never figured out what the default segment is,
2627 then default_seg will be zero at this point,
2628 and the specified segment prefix will always be used. */
2629 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2631 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2637 static const seg_entry
*
2640 const seg_entry
*default_seg
= 0;
2642 /* i.reg_operands MUST be the number of real register operands;
2643 implicit registers do not count. */
2644 if (i
.reg_operands
== 2)
2646 unsigned int source
, dest
;
2647 source
= ((i
.types
[0]
2648 & (Reg
| RegMMX
| RegXMM
2650 | Control
| Debug
| Test
))
2655 /* One of the register operands will be encoded in the i.tm.reg
2656 field, the other in the combined i.tm.mode and i.tm.regmem
2657 fields. If no form of this instruction supports a memory
2658 destination operand, then we assume the source operand may
2659 sometimes be a memory operand and so we need to store the
2660 destination in the i.rm.reg field. */
2661 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2663 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2664 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2665 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2667 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2672 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2673 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2674 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2676 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2681 { /* If it's not 2 reg operands... */
2684 unsigned int fake_zero_displacement
= 0;
2685 unsigned int op
= ((i
.types
[0] & AnyMem
)
2687 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2691 if (i
.base_reg
== 0)
2694 if (!i
.disp_operands
)
2695 fake_zero_displacement
= 1;
2696 if (i
.index_reg
== 0)
2698 /* Operand is just <disp> */
2699 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2700 && (flag_code
!= CODE_64BIT
))
2702 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2703 i
.types
[op
] &= ~Disp
;
2704 i
.types
[op
] |= Disp16
;
2706 else if (flag_code
!= CODE_64BIT
2707 || (i
.prefix
[ADDR_PREFIX
] != 0))
2709 i
.rm
.regmem
= NO_BASE_REGISTER
;
2710 i
.types
[op
] &= ~Disp
;
2711 i
.types
[op
] |= Disp32
;
2715 /* 64bit mode overwrites the 32bit absolute
2716 addressing by RIP relative addressing and
2717 absolute addressing is encoded by one of the
2718 redundant SIB forms. */
2719 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2720 i
.sib
.base
= NO_BASE_REGISTER
;
2721 i
.sib
.index
= NO_INDEX_REGISTER
;
2722 i
.types
[op
] &= ~Disp
;
2723 i
.types
[op
] |= Disp32S
;
2726 else /* !i.base_reg && i.index_reg */
2728 i
.sib
.index
= i
.index_reg
->reg_num
;
2729 i
.sib
.base
= NO_BASE_REGISTER
;
2730 i
.sib
.scale
= i
.log2_scale_factor
;
2731 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2732 i
.types
[op
] &= ~Disp
;
2733 if (flag_code
!= CODE_64BIT
)
2734 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2736 i
.types
[op
] |= Disp32S
;
2737 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2741 /* RIP addressing for 64bit mode. */
2742 else if (i
.base_reg
->reg_type
== BaseIndex
)
2744 i
.rm
.regmem
= NO_BASE_REGISTER
;
2745 i
.types
[op
] &= ~Disp
;
2746 i
.types
[op
] |= Disp32S
;
2747 i
.flags
[op
] = Operand_PCrel
;
2749 else if (i
.base_reg
->reg_type
& Reg16
)
2751 switch (i
.base_reg
->reg_num
)
2754 if (i
.index_reg
== 0)
2756 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2757 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2761 if (i
.index_reg
== 0)
2764 if ((i
.types
[op
] & Disp
) == 0)
2766 /* fake (%bp) into 0(%bp) */
2767 i
.types
[op
] |= Disp8
;
2768 fake_zero_displacement
= 1;
2771 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2772 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2774 default: /* (%si) -> 4 or (%di) -> 5 */
2775 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2777 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2779 else /* i.base_reg and 32/64 bit mode */
2781 if (flag_code
== CODE_64BIT
2782 && (i
.types
[op
] & Disp
))
2784 if (i
.types
[op
] & Disp8
)
2785 i
.types
[op
] = Disp8
| Disp32S
;
2787 i
.types
[op
] = Disp32S
;
2789 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2790 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2792 i
.sib
.base
= i
.base_reg
->reg_num
;
2793 /* x86-64 ignores REX prefix bit here to avoid decoder
2795 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2798 if (i
.disp_operands
== 0)
2800 fake_zero_displacement
= 1;
2801 i
.types
[op
] |= Disp8
;
2804 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2808 i
.sib
.scale
= i
.log2_scale_factor
;
2809 if (i
.index_reg
== 0)
2811 /* <disp>(%esp) becomes two byte modrm with no index
2812 register. We've already stored the code for esp
2813 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2814 Any base register besides %esp will not use the
2815 extra modrm byte. */
2816 i
.sib
.index
= NO_INDEX_REGISTER
;
2817 #if !SCALE1_WHEN_NO_INDEX
2818 /* Another case where we force the second modrm byte. */
2819 if (i
.log2_scale_factor
)
2820 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2825 i
.sib
.index
= i
.index_reg
->reg_num
;
2826 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2827 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2830 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2833 if (fake_zero_displacement
)
2835 /* Fakes a zero displacement assuming that i.types[op]
2836 holds the correct displacement size. */
2839 assert (i
.op
[op
].disps
== 0);
2840 exp
= &disp_expressions
[i
.disp_operands
++];
2841 i
.op
[op
].disps
= exp
;
2842 exp
->X_op
= O_constant
;
2843 exp
->X_add_number
= 0;
2844 exp
->X_add_symbol
= (symbolS
*) 0;
2845 exp
->X_op_symbol
= (symbolS
*) 0;
2849 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2850 (if any) based on i.tm.extension_opcode. Again, we must be
2851 careful to make sure that segment/control/debug/test/MMX
2852 registers are coded into the i.rm.reg field. */
2857 & (Reg
| RegMMX
| RegXMM
2859 | Control
| Debug
| Test
))
2862 & (Reg
| RegMMX
| RegXMM
2864 | Control
| Debug
| Test
))
2867 /* If there is an extension opcode to put here, the register
2868 number must be put into the regmem field. */
2869 if (i
.tm
.extension_opcode
!= None
)
2871 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2872 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2877 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2878 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2882 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2883 must set it to 3 to indicate this is a register operand
2884 in the regmem field. */
2885 if (!i
.mem_operands
)
2889 /* Fill in i.rm.reg field with extension opcode (if any). */
2890 if (i
.tm
.extension_opcode
!= None
)
2891 i
.rm
.reg
= i
.tm
.extension_opcode
;
2902 relax_substateT subtype
;
2907 if (flag_code
== CODE_16BIT
)
2911 if (i
.prefix
[DATA_PREFIX
] != 0)
2917 /* Pentium4 branch hints. */
2918 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2919 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2924 if (i
.prefix
[REX_PREFIX
] != 0)
2930 if (i
.prefixes
!= 0 && !intel_syntax
)
2931 as_warn (_("skipping prefixes on this instruction"));
2933 /* It's always a symbol; End frag & setup for relax.
2934 Make sure there is enough room in this frag for the largest
2935 instruction we may generate in md_convert_frag. This is 2
2936 bytes for the opcode and room for the prefix and largest
2938 frag_grow (prefix
+ 2 + 4);
2939 /* Prefix and 1 opcode byte go in fr_fix. */
2940 p
= frag_more (prefix
+ 1);
2941 if (i
.prefix
[DATA_PREFIX
] != 0)
2942 *p
++ = DATA_PREFIX_OPCODE
;
2943 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2944 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2945 *p
++ = i
.prefix
[SEG_PREFIX
];
2946 if (i
.prefix
[REX_PREFIX
] != 0)
2947 *p
++ = i
.prefix
[REX_PREFIX
];
2948 *p
= i
.tm
.base_opcode
;
2950 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2951 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2952 else if ((cpu_arch_flags
& Cpu386
) != 0)
2953 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2955 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2958 sym
= i
.op
[0].disps
->X_add_symbol
;
2959 off
= i
.op
[0].disps
->X_add_number
;
2961 if (i
.op
[0].disps
->X_op
!= O_constant
2962 && i
.op
[0].disps
->X_op
!= O_symbol
)
2964 /* Handle complex expressions. */
2965 sym
= make_expr_symbol (i
.op
[0].disps
);
2969 /* 1 possible extra opcode + 4 byte displacement go in var part.
2970 Pass reloc in fr_var. */
2971 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2980 if (i
.tm
.opcode_modifier
& JumpByte
)
2982 /* This is a loop or jecxz type instruction. */
2984 if (i
.prefix
[ADDR_PREFIX
] != 0)
2986 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2989 /* Pentium4 branch hints. */
2990 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2991 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2993 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3002 if (flag_code
== CODE_16BIT
)
3005 if (i
.prefix
[DATA_PREFIX
] != 0)
3007 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3017 if (i
.prefix
[REX_PREFIX
] != 0)
3019 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3023 if (i
.prefixes
!= 0 && !intel_syntax
)
3024 as_warn (_("skipping prefixes on this instruction"));
3026 p
= frag_more (1 + size
);
3027 *p
++ = i
.tm
.base_opcode
;
3029 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3030 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3034 output_interseg_jump ()
3042 if (flag_code
== CODE_16BIT
)
3046 if (i
.prefix
[DATA_PREFIX
] != 0)
3052 if (i
.prefix
[REX_PREFIX
] != 0)
3062 if (i
.prefixes
!= 0 && !intel_syntax
)
3063 as_warn (_("skipping prefixes on this instruction"));
3065 /* 1 opcode; 2 segment; offset */
3066 p
= frag_more (prefix
+ 1 + 2 + size
);
3068 if (i
.prefix
[DATA_PREFIX
] != 0)
3069 *p
++ = DATA_PREFIX_OPCODE
;
3071 if (i
.prefix
[REX_PREFIX
] != 0)
3072 *p
++ = i
.prefix
[REX_PREFIX
];
3074 *p
++ = i
.tm
.base_opcode
;
3075 if (i
.op
[1].imms
->X_op
== O_constant
)
3077 offsetT n
= i
.op
[1].imms
->X_add_number
;
3080 && !fits_in_unsigned_word (n
)
3081 && !fits_in_signed_word (n
))
3083 as_bad (_("16-bit jump out of range"));
3086 md_number_to_chars (p
, n
, size
);
3089 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3090 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3091 if (i
.op
[0].imms
->X_op
!= O_constant
)
3092 as_bad (_("can't handle non absolute segment in `%s'"),
3094 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3100 /* Tie dwarf2 debug info to the address at the start of the insn.
3101 We can't do this after the insn has been output as the current
3102 frag may have been closed off. eg. by frag_var. */
3103 dwarf2_emit_insn (0);
3106 if (i
.tm
.opcode_modifier
& Jump
)
3108 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3110 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3111 output_interseg_jump ();
3114 /* Output normal instructions here. */
3118 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3119 byte for the SSE instructions to specify a prefix they require. */
3120 if (i
.tm
.base_opcode
& 0xff0000)
3121 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3123 /* The prefix bytes. */
3125 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3131 md_number_to_chars (p
, (valueT
) *q
, 1);
3135 /* Now the opcode; be careful about word order here! */
3136 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3138 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3143 /* Put out high byte first: can't use md_number_to_chars! */
3144 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3145 *p
= i
.tm
.base_opcode
& 0xff;
3148 /* Now the modrm byte and sib byte (if present). */
3149 if (i
.tm
.opcode_modifier
& Modrm
)
3152 md_number_to_chars (p
,
3153 (valueT
) (i
.rm
.regmem
<< 0
3157 /* If i.rm.regmem == ESP (4)
3158 && i.rm.mode != (Register mode)
3160 ==> need second modrm byte. */
3161 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3163 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3166 md_number_to_chars (p
,
3167 (valueT
) (i
.sib
.base
<< 0
3169 | i
.sib
.scale
<< 6),
3174 if (i
.disp_operands
)
3186 #endif /* DEBUG386 */
3195 for (n
= 0; n
< i
.operands
; n
++)
3197 if (i
.types
[n
] & Disp
)
3199 if (i
.op
[n
].disps
->X_op
== O_constant
)
3205 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3208 if (i
.types
[n
] & Disp8
)
3210 if (i
.types
[n
] & Disp64
)
3213 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3215 p
= frag_more (size
);
3216 md_number_to_chars (p
, val
, size
);
3222 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3224 /* The PC relative address is computed relative
3225 to the instruction boundary, so in case immediate
3226 fields follows, we need to adjust the value. */
3227 if (pcrel
&& i
.imm_operands
)
3232 for (n1
= 0; n1
< i
.operands
; n1
++)
3233 if (i
.types
[n1
] & Imm
)
3235 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3238 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3240 if (i
.types
[n1
] & Imm64
)
3245 /* We should find the immediate. */
3246 if (n1
== i
.operands
)
3248 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3251 if (i
.types
[n
] & Disp32S
)
3254 if (i
.types
[n
] & (Disp16
| Disp64
))
3257 if (i
.types
[n
] & Disp64
)
3261 p
= frag_more (size
);
3262 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3263 i
.op
[n
].disps
, pcrel
,
3264 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3276 for (n
= 0; n
< i
.operands
; n
++)
3278 if (i
.types
[n
] & Imm
)
3280 if (i
.op
[n
].imms
->X_op
== O_constant
)
3286 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3289 if (i
.types
[n
] & (Imm8
| Imm8S
))
3291 else if (i
.types
[n
] & Imm64
)
3294 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3296 p
= frag_more (size
);
3297 md_number_to_chars (p
, val
, size
);
3301 /* Not absolute_section.
3302 Need a 32-bit fixup (don't support 8bit
3303 non-absolute imms). Try to support other
3305 RELOC_ENUM reloc_type
;
3309 if ((i
.types
[n
] & (Imm32S
))
3310 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3312 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3315 if (i
.types
[n
] & (Imm8
| Imm8S
))
3317 if (i
.types
[n
] & Imm64
)
3321 p
= frag_more (size
);
3322 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3323 #ifdef BFD_ASSEMBLER
3324 if (reloc_type
== BFD_RELOC_32
3326 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3327 && (i
.op
[n
].imms
->X_op
== O_symbol
3328 || (i
.op
[n
].imms
->X_op
== O_add
3329 && ((symbol_get_value_expression
3330 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3333 /* We don't support dynamic linking on x86-64 yet. */
3334 if (flag_code
== CODE_64BIT
)
3336 reloc_type
= BFD_RELOC_386_GOTPC
;
3337 i
.op
[n
].imms
->X_add_number
+= 3;
3340 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3341 i
.op
[n
].imms
, 0, reloc_type
);
3348 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3350 /* Parse operands of the form
3351 <symbol>@GOTOFF+<nnn>
3352 and similar .plt or .got references.
3354 If we find one, set up the correct relocation in RELOC and copy the
3355 input string, minus the `@GOTOFF' into a malloc'd buffer for
3356 parsing by the calling routine. Return this buffer, and if ADJUST
3357 is non-null set it to the length of the string we removed from the
3358 input line. Otherwise return NULL. */
3360 lex_got (reloc
, adjust
)
3364 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3365 static const struct {
3367 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3369 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3370 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3371 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3372 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, 0 } },
3373 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3374 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, 0 } },
3375 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, 0 } },
3376 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3377 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, 0 } },
3378 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3383 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3384 if (is_end_of_line
[(unsigned char) *cp
])
3387 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3391 len
= strlen (gotrel
[j
].str
);
3392 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3394 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3397 char *tmpbuf
, *past_reloc
;
3399 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3403 if (GOT_symbol
== NULL
)
3404 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3406 /* Replace the relocation token with ' ', so that
3407 errors like foo@GOTOFF1 will be detected. */
3409 /* The length of the first part of our input line. */
3410 first
= cp
- input_line_pointer
;
3412 /* The second part goes from after the reloc token until
3413 (and including) an end_of_line char. Don't use strlen
3414 here as the end_of_line char may not be a NUL. */
3415 past_reloc
= cp
+ 1 + len
;
3416 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3418 second
= cp
- past_reloc
;
3420 /* Allocate and copy string. The trailing NUL shouldn't
3421 be necessary, but be safe. */
3422 tmpbuf
= xmalloc (first
+ second
+ 2);
3423 memcpy (tmpbuf
, input_line_pointer
, first
);
3424 tmpbuf
[first
] = ' ';
3425 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3426 tmpbuf
[first
+ second
+ 1] = '\0';
3430 as_bad (_("@%s reloc is not supported in %s bit mode"),
3431 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3436 /* Might be a symbol version string. Don't as_bad here. */
3440 /* x86_cons_fix_new is called via the expression parsing code when a
3441 reloc is needed. We use this hook to get the correct .got reloc. */
3442 static RELOC_ENUM got_reloc
= NO_RELOC
;
3445 x86_cons_fix_new (frag
, off
, len
, exp
)
3451 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3452 got_reloc
= NO_RELOC
;
3453 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3457 x86_cons (exp
, size
)
3463 /* Handle @GOTOFF and the like in an expression. */
3465 char *gotfree_input_line
;
3468 save
= input_line_pointer
;
3469 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3470 if (gotfree_input_line
)
3471 input_line_pointer
= gotfree_input_line
;
3475 if (gotfree_input_line
)
3477 /* expression () has merrily parsed up to the end of line,
3478 or a comma - in the wrong buffer. Transfer how far
3479 input_line_pointer has moved to the right buffer. */
3480 input_line_pointer
= (save
3481 + (input_line_pointer
- gotfree_input_line
)
3483 free (gotfree_input_line
);
3491 static int i386_immediate
PARAMS ((char *));
3494 i386_immediate (imm_start
)
3497 char *save_input_line_pointer
;
3499 char *gotfree_input_line
;
3504 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3506 as_bad (_("only 1 or 2 immediate operands are allowed"));
3510 exp
= &im_expressions
[i
.imm_operands
++];
3511 i
.op
[this_operand
].imms
= exp
;
3513 if (is_space_char (*imm_start
))
3516 save_input_line_pointer
= input_line_pointer
;
3517 input_line_pointer
= imm_start
;
3520 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3521 if (gotfree_input_line
)
3522 input_line_pointer
= gotfree_input_line
;
3525 exp_seg
= expression (exp
);
3528 if (*input_line_pointer
)
3529 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3531 input_line_pointer
= save_input_line_pointer
;
3533 if (gotfree_input_line
)
3534 free (gotfree_input_line
);
3537 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3539 /* Missing or bad expr becomes absolute 0. */
3540 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3542 exp
->X_op
= O_constant
;
3543 exp
->X_add_number
= 0;
3544 exp
->X_add_symbol
= (symbolS
*) 0;
3545 exp
->X_op_symbol
= (symbolS
*) 0;
3547 else if (exp
->X_op
== O_constant
)
3549 /* Size it properly later. */
3550 i
.types
[this_operand
] |= Imm64
;
3551 /* If BFD64, sign extend val. */
3552 if (!use_rela_relocations
)
3553 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3554 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3556 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3558 #ifdef BFD_ASSEMBLER
3559 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3561 && exp_seg
!= text_section
3562 && exp_seg
!= data_section
3563 && exp_seg
!= bss_section
3564 && exp_seg
!= undefined_section
3565 #ifdef BFD_ASSEMBLER
3566 && !bfd_is_com_section (exp_seg
)
3570 #ifdef BFD_ASSEMBLER
3571 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3573 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3580 /* This is an address. The size of the address will be
3581 determined later, depending on destination register,
3582 suffix, or the default for the section. */
3583 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3589 static char *i386_scale
PARAMS ((char *));
3596 char *save
= input_line_pointer
;
3598 input_line_pointer
= scale
;
3599 val
= get_absolute_expression ();
3605 i
.log2_scale_factor
= 0;
3608 i
.log2_scale_factor
= 1;
3611 i
.log2_scale_factor
= 2;
3614 i
.log2_scale_factor
= 3;
3617 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3619 input_line_pointer
= save
;
3622 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3624 as_warn (_("scale factor of %d without an index register"),
3625 1 << i
.log2_scale_factor
);
3626 #if SCALE1_WHEN_NO_INDEX
3627 i
.log2_scale_factor
= 0;
3630 scale
= input_line_pointer
;
3631 input_line_pointer
= save
;
3635 static int i386_displacement
PARAMS ((char *, char *));
3638 i386_displacement (disp_start
, disp_end
)
3644 char *save_input_line_pointer
;
3646 char *gotfree_input_line
;
3648 int bigdisp
= Disp32
;
3650 if (flag_code
== CODE_64BIT
)
3652 if (i
.prefix
[ADDR_PREFIX
] == 0)
3655 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3657 i
.types
[this_operand
] |= bigdisp
;
3659 exp
= &disp_expressions
[i
.disp_operands
];
3660 i
.op
[this_operand
].disps
= exp
;
3662 save_input_line_pointer
= input_line_pointer
;
3663 input_line_pointer
= disp_start
;
3664 END_STRING_AND_SAVE (disp_end
);
3666 #ifndef GCC_ASM_O_HACK
3667 #define GCC_ASM_O_HACK 0
3670 END_STRING_AND_SAVE (disp_end
+ 1);
3671 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3672 && displacement_string_end
[-1] == '+')
3674 /* This hack is to avoid a warning when using the "o"
3675 constraint within gcc asm statements.
3678 #define _set_tssldt_desc(n,addr,limit,type) \
3679 __asm__ __volatile__ ( \
3681 "movw %w1,2+%0\n\t" \
3683 "movb %b1,4+%0\n\t" \
3684 "movb %4,5+%0\n\t" \
3685 "movb $0,6+%0\n\t" \
3686 "movb %h1,7+%0\n\t" \
3688 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3690 This works great except that the output assembler ends
3691 up looking a bit weird if it turns out that there is
3692 no offset. You end up producing code that looks like:
3705 So here we provide the missing zero. */
3707 *displacement_string_end
= '0';
3711 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3712 if (gotfree_input_line
)
3713 input_line_pointer
= gotfree_input_line
;
3716 exp_seg
= expression (exp
);
3719 if (*input_line_pointer
)
3720 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3722 RESTORE_END_STRING (disp_end
+ 1);
3724 RESTORE_END_STRING (disp_end
);
3725 input_line_pointer
= save_input_line_pointer
;
3727 if (gotfree_input_line
)
3728 free (gotfree_input_line
);
3731 #ifdef BFD_ASSEMBLER
3732 /* We do this to make sure that the section symbol is in
3733 the symbol table. We will ultimately change the relocation
3734 to be relative to the beginning of the section. */
3735 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3736 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3738 if (exp
->X_op
!= O_symbol
)
3740 as_bad (_("bad expression used with @%s"),
3741 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3747 if (S_IS_LOCAL (exp
->X_add_symbol
)
3748 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3749 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3750 exp
->X_op
= O_subtract
;
3751 exp
->X_op_symbol
= GOT_symbol
;
3752 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3753 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3755 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3759 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3761 /* Missing or bad expr becomes absolute 0. */
3762 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3764 exp
->X_op
= O_constant
;
3765 exp
->X_add_number
= 0;
3766 exp
->X_add_symbol
= (symbolS
*) 0;
3767 exp
->X_op_symbol
= (symbolS
*) 0;
3770 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3771 if (exp
->X_op
!= O_constant
3772 #ifdef BFD_ASSEMBLER
3773 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3775 && exp_seg
!= text_section
3776 && exp_seg
!= data_section
3777 && exp_seg
!= bss_section
3778 && exp_seg
!= undefined_section
)
3780 #ifdef BFD_ASSEMBLER
3781 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3783 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3788 else if (flag_code
== CODE_64BIT
)
3789 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3793 static int i386_index_check
PARAMS ((const char *));
3795 /* Make sure the memory operand we've been dealt is valid.
3796 Return 1 on success, 0 on a failure. */
3799 i386_index_check (operand_string
)
3800 const char *operand_string
;
3803 #if INFER_ADDR_PREFIX
3809 if (flag_code
== CODE_64BIT
)
3811 if (i
.prefix
[ADDR_PREFIX
] == 0)
3815 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3816 && (i
.base_reg
->reg_type
!= BaseIndex
3819 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3820 != (Reg64
| BaseIndex
))))
3827 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3829 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3830 != (Reg32
| BaseIndex
))))
3836 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3840 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3841 != (Reg16
| BaseIndex
)))
3843 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3844 != (Reg16
| BaseIndex
))
3846 && i
.base_reg
->reg_num
< 6
3847 && i
.index_reg
->reg_num
>= 6
3848 && i
.log2_scale_factor
== 0))))
3855 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3857 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3858 != (Reg32
| BaseIndex
))))
3864 #if INFER_ADDR_PREFIX
3865 if (flag_code
!= CODE_64BIT
3866 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3868 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3870 /* Change the size of any displacement too. At most one of
3871 Disp16 or Disp32 is set.
3872 FIXME. There doesn't seem to be any real need for separate
3873 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3874 Removing them would probably clean up the code quite a lot. */
3875 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3876 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
3881 as_bad (_("`%s' is not a valid base/index expression"),
3885 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3887 flag_code_names
[flag_code
]);
3893 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3897 i386_operand (operand_string
)
3898 char *operand_string
;
3902 char *op_string
= operand_string
;
3904 if (is_space_char (*op_string
))
3907 /* We check for an absolute prefix (differentiating,
3908 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3909 if (*op_string
== ABSOLUTE_PREFIX
)
3912 if (is_space_char (*op_string
))
3914 i
.types
[this_operand
] |= JumpAbsolute
;
3917 /* Check if operand is a register. */
3918 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3919 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3921 /* Check for a segment override by searching for ':' after a
3922 segment register. */
3924 if (is_space_char (*op_string
))
3926 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3931 i
.seg
[i
.mem_operands
] = &es
;
3934 i
.seg
[i
.mem_operands
] = &cs
;
3937 i
.seg
[i
.mem_operands
] = &ss
;
3940 i
.seg
[i
.mem_operands
] = &ds
;
3943 i
.seg
[i
.mem_operands
] = &fs
;
3946 i
.seg
[i
.mem_operands
] = &gs
;
3950 /* Skip the ':' and whitespace. */
3952 if (is_space_char (*op_string
))
3955 if (!is_digit_char (*op_string
)
3956 && !is_identifier_char (*op_string
)
3957 && *op_string
!= '('
3958 && *op_string
!= ABSOLUTE_PREFIX
)
3960 as_bad (_("bad memory operand `%s'"), op_string
);
3963 /* Handle case of %es:*foo. */
3964 if (*op_string
== ABSOLUTE_PREFIX
)
3967 if (is_space_char (*op_string
))
3969 i
.types
[this_operand
] |= JumpAbsolute
;
3971 goto do_memory_reference
;
3975 as_bad (_("junk `%s' after register"), op_string
);
3978 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3979 i
.op
[this_operand
].regs
= r
;
3982 else if (*op_string
== REGISTER_PREFIX
)
3984 as_bad (_("bad register name `%s'"), op_string
);
3987 else if (*op_string
== IMMEDIATE_PREFIX
)
3990 if (i
.types
[this_operand
] & JumpAbsolute
)
3992 as_bad (_("immediate operand illegal with absolute jump"));
3995 if (!i386_immediate (op_string
))
3998 else if (is_digit_char (*op_string
)
3999 || is_identifier_char (*op_string
)
4000 || *op_string
== '(')
4002 /* This is a memory reference of some sort. */
4005 /* Start and end of displacement string expression (if found). */
4006 char *displacement_string_start
;
4007 char *displacement_string_end
;
4009 do_memory_reference
:
4010 if ((i
.mem_operands
== 1
4011 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4012 || i
.mem_operands
== 2)
4014 as_bad (_("too many memory references for `%s'"),
4015 current_templates
->start
->name
);
4019 /* Check for base index form. We detect the base index form by
4020 looking for an ')' at the end of the operand, searching
4021 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4023 base_string
= op_string
+ strlen (op_string
);
4026 if (is_space_char (*base_string
))
4029 /* If we only have a displacement, set-up for it to be parsed later. */
4030 displacement_string_start
= op_string
;
4031 displacement_string_end
= base_string
+ 1;
4033 if (*base_string
== ')')
4036 unsigned int parens_balanced
= 1;
4037 /* We've already checked that the number of left & right ()'s are
4038 equal, so this loop will not be infinite. */
4042 if (*base_string
== ')')
4044 if (*base_string
== '(')
4047 while (parens_balanced
);
4049 temp_string
= base_string
;
4051 /* Skip past '(' and whitespace. */
4053 if (is_space_char (*base_string
))
4056 if (*base_string
== ','
4057 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4058 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4060 displacement_string_end
= temp_string
;
4062 i
.types
[this_operand
] |= BaseIndex
;
4066 base_string
= end_op
;
4067 if (is_space_char (*base_string
))
4071 /* There may be an index reg or scale factor here. */
4072 if (*base_string
== ',')
4075 if (is_space_char (*base_string
))
4078 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4079 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4081 base_string
= end_op
;
4082 if (is_space_char (*base_string
))
4084 if (*base_string
== ',')
4087 if (is_space_char (*base_string
))
4090 else if (*base_string
!= ')')
4092 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4097 else if (*base_string
== REGISTER_PREFIX
)
4099 as_bad (_("bad register name `%s'"), base_string
);
4103 /* Check for scale factor. */
4104 if (*base_string
!= ')')
4106 char *end_scale
= i386_scale (base_string
);
4111 base_string
= end_scale
;
4112 if (is_space_char (*base_string
))
4114 if (*base_string
!= ')')
4116 as_bad (_("expecting `)' after scale factor in `%s'"),
4121 else if (!i
.index_reg
)
4123 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4128 else if (*base_string
!= ')')
4130 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4135 else if (*base_string
== REGISTER_PREFIX
)
4137 as_bad (_("bad register name `%s'"), base_string
);
4142 /* If there's an expression beginning the operand, parse it,
4143 assuming displacement_string_start and
4144 displacement_string_end are meaningful. */
4145 if (displacement_string_start
!= displacement_string_end
)
4147 if (!i386_displacement (displacement_string_start
,
4148 displacement_string_end
))
4152 /* Special case for (%dx) while doing input/output op. */
4154 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4156 && i
.log2_scale_factor
== 0
4157 && i
.seg
[i
.mem_operands
] == 0
4158 && (i
.types
[this_operand
] & Disp
) == 0)
4160 i
.types
[this_operand
] = InOutPortReg
;
4164 if (i386_index_check (operand_string
) == 0)
4170 /* It's not a memory operand; argh! */
4171 as_bad (_("invalid char %s beginning operand %d `%s'"),
4172 output_invalid (*op_string
),
4177 return 1; /* Normal return. */
4180 /* md_estimate_size_before_relax()
4182 Called just before relax() for rs_machine_dependent frags. The x86
4183 assembler uses these frags to handle variable size jump
4186 Any symbol that is now undefined will not become defined.
4187 Return the correct fr_subtype in the frag.
4188 Return the initial "guess for variable size of frag" to caller.
4189 The guess is actually the growth beyond the fixed part. Whatever
4190 we do to grow the fixed or variable part contributes to our
4194 md_estimate_size_before_relax (fragP
, segment
)
4198 /* We've already got fragP->fr_subtype right; all we have to do is
4199 check for un-relaxable symbols. On an ELF system, we can't relax
4200 an externally visible symbol, because it may be overridden by a
4202 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4204 || S_IS_EXTERNAL (fragP
->fr_symbol
)
4205 || S_IS_WEAK (fragP
->fr_symbol
)
4209 /* Symbol is undefined in this segment, or we need to keep a
4210 reloc so that weak symbols can be overridden. */
4211 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4212 RELOC_ENUM reloc_type
;
4213 unsigned char *opcode
;
4216 if (fragP
->fr_var
!= NO_RELOC
)
4217 reloc_type
= fragP
->fr_var
;
4219 reloc_type
= BFD_RELOC_16_PCREL
;
4221 reloc_type
= BFD_RELOC_32_PCREL
;
4223 old_fr_fix
= fragP
->fr_fix
;
4224 opcode
= (unsigned char *) fragP
->fr_opcode
;
4226 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4229 /* Make jmp (0xeb) a (d)word displacement jump. */
4231 fragP
->fr_fix
+= size
;
4232 fix_new (fragP
, old_fr_fix
, size
,
4234 fragP
->fr_offset
, 1,
4240 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4242 /* Negate the condition, and branch past an
4243 unconditional jump. */
4246 /* Insert an unconditional jump. */
4248 /* We added two extra opcode bytes, and have a two byte
4250 fragP
->fr_fix
+= 2 + 2;
4251 fix_new (fragP
, old_fr_fix
+ 2, 2,
4253 fragP
->fr_offset
, 1,
4260 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4263 fix_new (fragP
, old_fr_fix
, 1,
4265 fragP
->fr_offset
, 1,
4270 /* This changes the byte-displacement jump 0x7N
4271 to the (d)word-displacement jump 0x0f,0x8N. */
4272 opcode
[1] = opcode
[0] + 0x10;
4273 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4274 /* We've added an opcode byte. */
4275 fragP
->fr_fix
+= 1 + size
;
4276 fix_new (fragP
, old_fr_fix
+ 1, size
,
4278 fragP
->fr_offset
, 1,
4283 BAD_CASE (fragP
->fr_subtype
);
4287 return fragP
->fr_fix
- old_fr_fix
;
4290 /* Guess size depending on current relax state. Initially the relax
4291 state will correspond to a short jump and we return 1, because
4292 the variable part of the frag (the branch offset) is one byte
4293 long. However, we can relax a section more than once and in that
4294 case we must either set fr_subtype back to the unrelaxed state,
4295 or return the value for the appropriate branch. */
4296 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4299 /* Called after relax() is finished.
4301 In: Address of frag.
4302 fr_type == rs_machine_dependent.
4303 fr_subtype is what the address relaxed to.
4305 Out: Any fixSs and constants are set up.
4306 Caller will turn frag into a ".space 0". */
4308 #ifndef BFD_ASSEMBLER
4310 md_convert_frag (headers
, sec
, fragP
)
4311 object_headers
*headers ATTRIBUTE_UNUSED
;
4312 segT sec ATTRIBUTE_UNUSED
;
4316 md_convert_frag (abfd
, sec
, fragP
)
4317 bfd
*abfd ATTRIBUTE_UNUSED
;
4318 segT sec ATTRIBUTE_UNUSED
;
4322 unsigned char *opcode
;
4323 unsigned char *where_to_put_displacement
= NULL
;
4324 offsetT target_address
;
4325 offsetT opcode_address
;
4326 unsigned int extension
= 0;
4327 offsetT displacement_from_opcode_start
;
4329 opcode
= (unsigned char *) fragP
->fr_opcode
;
4331 /* Address we want to reach in file space. */
4332 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4334 /* Address opcode resides at in file space. */
4335 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4337 /* Displacement from opcode start to fill into instruction. */
4338 displacement_from_opcode_start
= target_address
- opcode_address
;
4340 if ((fragP
->fr_subtype
& BIG
) == 0)
4342 /* Don't have to change opcode. */
4343 extension
= 1; /* 1 opcode + 1 displacement */
4344 where_to_put_displacement
= &opcode
[1];
4348 if (no_cond_jump_promotion
4349 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4350 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4352 switch (fragP
->fr_subtype
)
4354 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4355 extension
= 4; /* 1 opcode + 4 displacement */
4357 where_to_put_displacement
= &opcode
[1];
4360 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4361 extension
= 2; /* 1 opcode + 2 displacement */
4363 where_to_put_displacement
= &opcode
[1];
4366 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4367 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4368 extension
= 5; /* 2 opcode + 4 displacement */
4369 opcode
[1] = opcode
[0] + 0x10;
4370 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4371 where_to_put_displacement
= &opcode
[2];
4374 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4375 extension
= 3; /* 2 opcode + 2 displacement */
4376 opcode
[1] = opcode
[0] + 0x10;
4377 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4378 where_to_put_displacement
= &opcode
[2];
4381 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4386 where_to_put_displacement
= &opcode
[3];
4390 BAD_CASE (fragP
->fr_subtype
);
4395 /* Now put displacement after opcode. */
4396 md_number_to_chars ((char *) where_to_put_displacement
,
4397 (valueT
) (displacement_from_opcode_start
- extension
),
4398 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4399 fragP
->fr_fix
+= extension
;
4402 /* Size of byte displacement jmp. */
4403 int md_short_jump_size
= 2;
4405 /* Size of dword displacement jmp. */
4406 int md_long_jump_size
= 5;
4408 /* Size of relocation record. */
4409 const int md_reloc_size
= 8;
4412 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4414 addressT from_addr
, to_addr
;
4415 fragS
*frag ATTRIBUTE_UNUSED
;
4416 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4420 offset
= to_addr
- (from_addr
+ 2);
4421 /* Opcode for byte-disp jump. */
4422 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4423 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4427 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4429 addressT from_addr
, to_addr
;
4430 fragS
*frag ATTRIBUTE_UNUSED
;
4431 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4435 offset
= to_addr
- (from_addr
+ 5);
4436 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4437 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4440 /* Apply a fixup (fixS) to segment data, once it has been determined
4441 by our caller that we have all the info we need to fix it up.
4443 On the 386, immediates, displacements, and data pointers are all in
4444 the same (little-endian) format, so we don't need to care about which
4448 md_apply_fix3 (fixP
, valP
, seg
)
4449 /* The fix we're to put in. */
4451 /* Pointer to the value of the bits. */
4453 /* Segment fix is from. */
4454 segT seg ATTRIBUTE_UNUSED
;
4456 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4457 valueT value
= *valP
;
4459 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4462 switch (fixP
->fx_r_type
)
4468 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4471 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4474 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4479 /* This is a hack. There should be a better way to handle this.
4480 This covers for the fact that bfd_install_relocation will
4481 subtract the current location (for partial_inplace, PC relative
4482 relocations); see more below. */
4483 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4484 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4485 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4486 && fixP
->fx_addsy
&& !use_rela_relocations
)
4489 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4491 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4494 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4496 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4497 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4499 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4502 || (symbol_section_p (fixP
->fx_addsy
)
4503 && fseg
!= absolute_section
))
4504 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
4505 && !S_IS_WEAK (fixP
->fx_addsy
)
4506 && S_IS_DEFINED (fixP
->fx_addsy
)
4507 && !S_IS_COMMON (fixP
->fx_addsy
))
4509 /* Yes, we add the values in twice. This is because
4510 bfd_perform_relocation subtracts them out again. I think
4511 bfd_perform_relocation is broken, but I don't dare change
4513 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4517 #if defined (OBJ_COFF) && defined (TE_PE)
4518 /* For some reason, the PE format does not store a section
4519 address offset for a PC relative symbol. */
4520 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4521 value
+= md_pcrel_from (fixP
);
4525 /* Fix a few things - the dynamic linker expects certain values here,
4526 and we must not dissappoint it. */
4527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4528 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4530 switch (fixP
->fx_r_type
)
4532 case BFD_RELOC_386_PLT32
:
4533 case BFD_RELOC_X86_64_PLT32
:
4534 /* Make the jump instruction point to the address of the operand. At
4535 runtime we merely add the offset to the actual PLT entry. */
4538 case BFD_RELOC_386_GOTPC
:
4540 /* This is tough to explain. We end up with this one if we have
4541 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4542 * here is to obtain the absolute address of the GOT, and it is strongly
4543 * preferable from a performance point of view to avoid using a runtime
4544 * relocation for this. The actual sequence of instructions often look
4550 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4552 * The call and pop essentially return the absolute address of
4553 * the label .L66 and store it in %ebx. The linker itself will
4554 * ultimately change the first operand of the addl so that %ebx points to
4555 * the GOT, but to keep things simple, the .o file must have this operand
4556 * set so that it generates not the absolute address of .L66, but the
4557 * absolute address of itself. This allows the linker itself simply
4558 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4559 * added in, and the addend of the relocation is stored in the operand
4560 * field for the instruction itself.
4562 * Our job here is to fix the operand so that it would add the correct
4563 * offset so that %ebx would point to itself. The thing that is tricky is
4564 * that .-.L66 will point to the beginning of the instruction, so we need
4565 * to further modify the operand so that it will point to itself.
4566 * There are other cases where you have something like:
4568 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4570 * and here no correction would be required. Internally in the assembler
4571 * we treat operands of this form as not being pcrel since the '.' is
4572 * explicitly mentioned, and I wonder whether it would simplify matters
4573 * to do it this way. Who knows. In earlier versions of the PIC patches,
4574 * the pcrel_adjust field was used to store the correction, but since the
4575 * expression is not pcrel, I felt it would be confusing to do it this
4580 case BFD_RELOC_386_GOT32
:
4581 case BFD_RELOC_386_TLS_GD
:
4582 case BFD_RELOC_386_TLS_LDM
:
4583 case BFD_RELOC_386_TLS_LDO_32
:
4584 case BFD_RELOC_386_TLS_IE_32
:
4585 case BFD_RELOC_386_TLS_LE_32
:
4586 case BFD_RELOC_386_TLS_LE
:
4587 case BFD_RELOC_X86_64_GOT32
:
4588 value
= 0; /* Fully resolved at runtime. No addend. */
4590 case BFD_RELOC_386_GOTOFF
:
4591 case BFD_RELOC_X86_64_GOTPCREL
:
4594 case BFD_RELOC_VTABLE_INHERIT
:
4595 case BFD_RELOC_VTABLE_ENTRY
:
4602 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4604 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4606 /* Are we finished with this relocation now? */
4607 if (fixP
->fx_addsy
== NULL
)
4609 #ifdef BFD_ASSEMBLER
4610 else if (use_rela_relocations
)
4612 fixP
->fx_no_overflow
= 1;
4613 /* Remember value for tc_gen_reloc. */
4614 fixP
->fx_addnumber
= value
;
4618 md_number_to_chars (p
, value
, fixP
->fx_size
);
4621 #define MAX_LITTLENUMS 6
4623 /* Turn the string pointed to by litP into a floating point constant
4624 of type TYPE, and emit the appropriate bytes. The number of
4625 LITTLENUMS emitted is stored in *SIZEP. An error message is
4626 returned, or NULL on OK. */
4629 md_atof (type
, litP
, sizeP
)
4635 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4636 LITTLENUM_TYPE
*wordP
;
4658 return _("Bad call to md_atof ()");
4660 t
= atof_ieee (input_line_pointer
, type
, words
);
4662 input_line_pointer
= t
;
4664 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4665 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4666 the bigendian 386. */
4667 for (wordP
= words
+ prec
- 1; prec
--;)
4669 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4670 litP
+= sizeof (LITTLENUM_TYPE
);
4675 char output_invalid_buf
[8];
4682 sprintf (output_invalid_buf
, "'%c'", c
);
4684 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4685 return output_invalid_buf
;
4688 /* REG_STRING starts *before* REGISTER_PREFIX. */
4690 static const reg_entry
*
4691 parse_register (reg_string
, end_op
)
4695 char *s
= reg_string
;
4697 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4700 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4701 if (*s
== REGISTER_PREFIX
)
4704 if (is_space_char (*s
))
4708 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4710 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4711 return (const reg_entry
*) NULL
;
4715 /* For naked regs, make sure that we are not dealing with an identifier.
4716 This prevents confusing an identifier like `eax_var' with register
4718 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4719 return (const reg_entry
*) NULL
;
4723 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4725 /* Handle floating point regs, allowing spaces in the (i) part. */
4726 if (r
== i386_regtab
/* %st is first entry of table */)
4728 if (is_space_char (*s
))
4733 if (is_space_char (*s
))
4735 if (*s
>= '0' && *s
<= '7')
4737 r
= &i386_float_regtab
[*s
- '0'];
4739 if (is_space_char (*s
))
4747 /* We have "%st(" then garbage. */
4748 return (const reg_entry
*) NULL
;
4753 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4754 && flag_code
!= CODE_64BIT
)
4756 return (const reg_entry
*) NULL
;
4762 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4763 const char *md_shortopts
= "kVQ:sq";
4765 const char *md_shortopts
= "q";
4768 struct option md_longopts
[] = {
4769 #define OPTION_32 (OPTION_MD_BASE + 0)
4770 {"32", no_argument
, NULL
, OPTION_32
},
4771 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4772 #define OPTION_64 (OPTION_MD_BASE + 1)
4773 {"64", no_argument
, NULL
, OPTION_64
},
4775 {NULL
, no_argument
, NULL
, 0}
4777 size_t md_longopts_size
= sizeof (md_longopts
);
4780 md_parse_option (c
, arg
)
4782 char *arg ATTRIBUTE_UNUSED
;
4790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4791 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4792 should be emitted or not. FIXME: Not implemented. */
4796 /* -V: SVR4 argument to print version ID. */
4798 print_version_id ();
4801 /* -k: Ignore for FreeBSD compatibility. */
4806 /* -s: On i386 Solaris, this tells the native assembler to use
4807 .stab instead of .stab.excl. We always use .stab anyhow. */
4812 const char **list
, **l
;
4814 list
= bfd_target_list ();
4815 for (l
= list
; *l
!= NULL
; l
++)
4816 if (strcmp (*l
, "elf64-x86-64") == 0)
4818 default_arch
= "x86_64";
4822 as_fatal (_("No compiled in support for x86_64"));
4829 default_arch
= "i386";
4839 md_show_usage (stream
)
4842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4843 fprintf (stream
, _("\
4845 -V print assembler version number\n\
4847 -q quieten some warnings\n\
4850 fprintf (stream
, _("\
4851 -q quieten some warnings\n"));
4855 #ifdef BFD_ASSEMBLER
4856 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4857 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4859 /* Pick the target format to use. */
4862 i386_target_format ()
4864 if (!strcmp (default_arch
, "x86_64"))
4865 set_code_flag (CODE_64BIT
);
4866 else if (!strcmp (default_arch
, "i386"))
4867 set_code_flag (CODE_32BIT
);
4869 as_fatal (_("Unknown architecture"));
4870 switch (OUTPUT_FLAVOR
)
4872 #ifdef OBJ_MAYBE_AOUT
4873 case bfd_target_aout_flavour
:
4874 return AOUT_TARGET_FORMAT
;
4876 #ifdef OBJ_MAYBE_COFF
4877 case bfd_target_coff_flavour
:
4880 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4881 case bfd_target_elf_flavour
:
4883 if (flag_code
== CODE_64BIT
)
4884 use_rela_relocations
= 1;
4885 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4894 #endif /* OBJ_MAYBE_ more than one */
4896 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4897 void i386_elf_emit_arch_note ()
4899 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4900 && cpu_arch_name
!= NULL
)
4903 asection
*seg
= now_seg
;
4904 subsegT subseg
= now_subseg
;
4905 Elf_Internal_Note i_note
;
4906 Elf_External_Note e_note
;
4907 asection
*note_secp
;
4910 /* Create the .note section. */
4911 note_secp
= subseg_new (".note", 0);
4912 bfd_set_section_flags (stdoutput
,
4914 SEC_HAS_CONTENTS
| SEC_READONLY
);
4916 /* Process the arch string. */
4917 len
= strlen (cpu_arch_name
);
4919 i_note
.namesz
= len
+ 1;
4921 i_note
.type
= NT_ARCH
;
4922 p
= frag_more (sizeof (e_note
.namesz
));
4923 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4924 p
= frag_more (sizeof (e_note
.descsz
));
4925 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
4926 p
= frag_more (sizeof (e_note
.type
));
4927 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
4928 p
= frag_more (len
+ 1);
4929 strcpy (p
, cpu_arch_name
);
4931 frag_align (2, 0, 0);
4933 subseg_set (seg
, subseg
);
4937 #endif /* BFD_ASSEMBLER */
4940 md_undefined_symbol (name
)
4943 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4944 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4945 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4946 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4950 if (symbol_find (name
))
4951 as_bad (_("GOT already in symbol table"));
4952 GOT_symbol
= symbol_new (name
, undefined_section
,
4953 (valueT
) 0, &zero_address_frag
);
4960 /* Round up a section size to the appropriate boundary. */
4963 md_section_align (segment
, size
)
4964 segT segment ATTRIBUTE_UNUSED
;
4967 #ifdef BFD_ASSEMBLER
4968 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4969 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4971 /* For a.out, force the section size to be aligned. If we don't do
4972 this, BFD will align it for us, but it will not write out the
4973 final bytes of the section. This may be a bug in BFD, but it is
4974 easier to fix it here since that is how the other a.out targets
4978 align
= bfd_get_section_alignment (stdoutput
, segment
);
4979 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4987 /* On the i386, PC-relative offsets are relative to the start of the
4988 next instruction. That is, the address of the offset, plus its
4989 size, since the offset is always the last part of the insn. */
4992 md_pcrel_from (fixP
)
4995 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5002 int ignore ATTRIBUTE_UNUSED
;
5006 temp
= get_absolute_expression ();
5007 subseg_set (bss_section
, (subsegT
) temp
);
5008 demand_empty_rest_of_line ();
5013 #ifdef BFD_ASSEMBLER
5016 i386_validate_fix (fixp
)
5019 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5021 /* GOTOFF relocation are nonsense in 64bit mode. */
5022 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5024 if (flag_code
!= CODE_64BIT
)
5026 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5030 if (flag_code
== CODE_64BIT
)
5032 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5039 tc_gen_reloc (section
, fixp
)
5040 asection
*section ATTRIBUTE_UNUSED
;
5044 bfd_reloc_code_real_type code
;
5046 switch (fixp
->fx_r_type
)
5048 case BFD_RELOC_X86_64_PLT32
:
5049 case BFD_RELOC_X86_64_GOT32
:
5050 case BFD_RELOC_X86_64_GOTPCREL
:
5051 case BFD_RELOC_386_PLT32
:
5052 case BFD_RELOC_386_GOT32
:
5053 case BFD_RELOC_386_GOTOFF
:
5054 case BFD_RELOC_386_GOTPC
:
5055 case BFD_RELOC_386_TLS_GD
:
5056 case BFD_RELOC_386_TLS_LDM
:
5057 case BFD_RELOC_386_TLS_LDO_32
:
5058 case BFD_RELOC_386_TLS_IE_32
:
5059 case BFD_RELOC_386_TLS_LE_32
:
5060 case BFD_RELOC_386_TLS_LE
:
5061 case BFD_RELOC_X86_64_32S
:
5063 case BFD_RELOC_VTABLE_ENTRY
:
5064 case BFD_RELOC_VTABLE_INHERIT
:
5065 code
= fixp
->fx_r_type
;
5070 switch (fixp
->fx_size
)
5073 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5074 _("can not do %d byte pc-relative relocation"),
5076 code
= BFD_RELOC_32_PCREL
;
5078 case 1: code
= BFD_RELOC_8_PCREL
; break;
5079 case 2: code
= BFD_RELOC_16_PCREL
; break;
5080 case 4: code
= BFD_RELOC_32_PCREL
; break;
5085 switch (fixp
->fx_size
)
5088 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5089 _("can not do %d byte relocation"),
5091 code
= BFD_RELOC_32
;
5093 case 1: code
= BFD_RELOC_8
; break;
5094 case 2: code
= BFD_RELOC_16
; break;
5095 case 4: code
= BFD_RELOC_32
; break;
5097 case 8: code
= BFD_RELOC_64
; break;
5104 if (code
== BFD_RELOC_32
5106 && fixp
->fx_addsy
== GOT_symbol
)
5108 /* We don't support GOTPC on 64bit targets. */
5109 if (flag_code
== CODE_64BIT
)
5111 code
= BFD_RELOC_386_GOTPC
;
5114 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5115 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5116 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5118 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5119 if (!use_rela_relocations
)
5121 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5122 vtable entry to be used in the relocation's section offset. */
5123 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5124 rel
->address
= fixp
->fx_offset
;
5128 /* Use the rela in 64bit mode. */
5131 if (!fixp
->fx_pcrel
)
5132 rel
->addend
= fixp
->fx_offset
;
5136 case BFD_RELOC_X86_64_PLT32
:
5137 case BFD_RELOC_X86_64_GOT32
:
5138 case BFD_RELOC_X86_64_GOTPCREL
:
5139 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5142 rel
->addend
= (section
->vma
5144 + fixp
->fx_addnumber
5145 + md_pcrel_from (fixp
));
5150 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5151 if (rel
->howto
== NULL
)
5153 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5154 _("cannot represent relocation type %s"),
5155 bfd_get_reloc_code_name (code
));
5156 /* Set howto to a garbage value so that we can keep going. */
5157 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5158 assert (rel
->howto
!= NULL
);
5164 #else /* !BFD_ASSEMBLER */
5166 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5168 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5171 relax_addressT segment_address_in_file
;
5173 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5174 Out: GNU LD relocation length code: 0, 1, or 2. */
5176 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5179 know (fixP
->fx_addsy
!= NULL
);
5181 md_number_to_chars (where
,
5182 (valueT
) (fixP
->fx_frag
->fr_address
5183 + fixP
->fx_where
- segment_address_in_file
),
5186 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5187 ? S_GET_TYPE (fixP
->fx_addsy
)
5188 : fixP
->fx_addsy
->sy_number
);
5190 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5191 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5192 where
[4] = r_symbolnum
& 0x0ff;
5193 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5194 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5195 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5198 #endif /* OBJ_AOUT or OBJ_BOUT. */
5200 #if defined (I386COFF)
5203 tc_coff_fix2rtype (fixP
)
5206 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5209 return (fixP
->fx_pcrel
?
5210 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5211 fixP
->fx_size
== 2 ? R_PCRWORD
:
5213 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5214 fixP
->fx_size
== 2 ? R_RELWORD
:
5219 tc_coff_sizemachdep (frag
)
5223 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5228 #endif /* I386COFF */
5230 #endif /* !BFD_ASSEMBLER */
5232 /* Parse operands using Intel syntax. This implements a recursive descent
5233 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5236 FIXME: We do not recognize the full operand grammar defined in the MASM
5237 documentation. In particular, all the structure/union and
5238 high-level macro operands are missing.
5240 Uppercase words are terminals, lower case words are non-terminals.
5241 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5242 bars '|' denote choices. Most grammar productions are implemented in
5243 functions called 'intel_<production>'.
5245 Initial production is 'expr'.
5251 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5253 constant digits [[ radixOverride ]]
5255 dataType BYTE | WORD | DWORD | QWORD | XWORD
5288 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5289 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5291 hexdigit a | b | c | d | e | f
5292 | A | B | C | D | E | F
5302 register specialRegister
5306 segmentRegister CS | DS | ES | FS | GS | SS
5308 specialRegister CR0 | CR2 | CR3
5309 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5310 | TR3 | TR4 | TR5 | TR6 | TR7
5312 We simplify the grammar in obvious places (e.g., register parsing is
5313 done by calling parse_register) and eliminate immediate left recursion
5314 to implement a recursive-descent parser.
5354 /* Parsing structure for the intel syntax parser. Used to implement the
5355 semantic actions for the operand grammar. */
5356 struct intel_parser_s
5358 char *op_string
; /* The string being parsed. */
5359 int got_a_float
; /* Whether the operand is a float. */
5360 int op_modifier
; /* Operand modifier. */
5361 int is_mem
; /* 1 if operand is memory reference. */
5362 const reg_entry
*reg
; /* Last register reference found. */
5363 char *disp
; /* Displacement string being built. */
5366 static struct intel_parser_s intel_parser
;
5368 /* Token structure for parsing intel syntax. */
5371 int code
; /* Token code. */
5372 const reg_entry
*reg
; /* Register entry for register tokens. */
5373 char *str
; /* String representation. */
5376 static struct intel_token cur_token
, prev_token
;
5378 /* Token codes for the intel parser. Since T_SHORT is already used
5379 by COFF, undefine it first to prevent a warning. */
5394 /* Prototypes for intel parser functions. */
5395 static int intel_match_token
PARAMS ((int code
));
5396 static void intel_get_token
PARAMS ((void));
5397 static void intel_putback_token
PARAMS ((void));
5398 static int intel_expr
PARAMS ((void));
5399 static int intel_e05
PARAMS ((void));
5400 static int intel_e05_1
PARAMS ((void));
5401 static int intel_e06
PARAMS ((void));
5402 static int intel_e06_1
PARAMS ((void));
5403 static int intel_e09
PARAMS ((void));
5404 static int intel_e09_1
PARAMS ((void));
5405 static int intel_e10
PARAMS ((void));
5406 static int intel_e10_1
PARAMS ((void));
5407 static int intel_e11
PARAMS ((void));
5410 i386_intel_operand (operand_string
, got_a_float
)
5411 char *operand_string
;
5417 /* Initialize token holders. */
5418 cur_token
.code
= prev_token
.code
= T_NIL
;
5419 cur_token
.reg
= prev_token
.reg
= NULL
;
5420 cur_token
.str
= prev_token
.str
= NULL
;
5422 /* Initialize parser structure. */
5423 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5426 strcpy (intel_parser
.op_string
, operand_string
);
5427 intel_parser
.got_a_float
= got_a_float
;
5428 intel_parser
.op_modifier
= -1;
5429 intel_parser
.is_mem
= 0;
5430 intel_parser
.reg
= NULL
;
5431 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5432 if (intel_parser
.disp
== NULL
)
5434 intel_parser
.disp
[0] = '\0';
5436 /* Read the first token and start the parser. */
5438 ret
= intel_expr ();
5442 /* If we found a memory reference, hand it over to i386_displacement
5443 to fill in the rest of the operand fields. */
5444 if (intel_parser
.is_mem
)
5446 if ((i
.mem_operands
== 1
5447 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5448 || i
.mem_operands
== 2)
5450 as_bad (_("too many memory references for '%s'"),
5451 current_templates
->start
->name
);
5456 char *s
= intel_parser
.disp
;
5459 /* Add the displacement expression. */
5461 ret
= i386_displacement (s
, s
+ strlen (s
))
5462 && i386_index_check (s
);
5466 /* Constant and OFFSET expressions are handled by i386_immediate. */
5467 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5468 || intel_parser
.reg
== NULL
)
5469 ret
= i386_immediate (intel_parser
.disp
);
5473 free (intel_parser
.disp
);
5483 /* expr SHORT e05 */
5484 if (cur_token
.code
== T_SHORT
)
5486 intel_parser
.op_modifier
= SHORT
;
5487 intel_match_token (T_SHORT
);
5489 return (intel_e05 ());
5494 return intel_e05 ();
5504 return (intel_e06 () && intel_e05_1 ());
5510 /* e05' addOp e06 e05' */
5511 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5513 strcat (intel_parser
.disp
, cur_token
.str
);
5514 intel_match_token (cur_token
.code
);
5516 return (intel_e06 () && intel_e05_1 ());
5531 return (intel_e09 () && intel_e06_1 ());
5537 /* e06' mulOp e09 e06' */
5538 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5540 strcat (intel_parser
.disp
, cur_token
.str
);
5541 intel_match_token (cur_token
.code
);
5543 return (intel_e09 () && intel_e06_1 ());
5551 /* e09 OFFSET e10 e09'
5560 /* e09 OFFSET e10 e09' */
5561 if (cur_token
.code
== T_OFFSET
)
5563 intel_parser
.is_mem
= 0;
5564 intel_parser
.op_modifier
= OFFSET_FLAT
;
5565 intel_match_token (T_OFFSET
);
5567 return (intel_e10 () && intel_e09_1 ());
5572 return (intel_e10 () && intel_e09_1 ());
5578 /* e09' PTR e10 e09' */
5579 if (cur_token
.code
== T_PTR
)
5581 if (prev_token
.code
== T_BYTE
)
5582 i
.suffix
= BYTE_MNEM_SUFFIX
;
5584 else if (prev_token
.code
== T_WORD
)
5586 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5587 i
.suffix
= SHORT_MNEM_SUFFIX
;
5589 i
.suffix
= WORD_MNEM_SUFFIX
;
5592 else if (prev_token
.code
== T_DWORD
)
5594 if (intel_parser
.got_a_float
== 1) /* "f..." */
5595 i
.suffix
= SHORT_MNEM_SUFFIX
;
5597 i
.suffix
= LONG_MNEM_SUFFIX
;
5600 else if (prev_token
.code
== T_QWORD
)
5602 if (intel_parser
.got_a_float
== 1) /* "f..." */
5603 i
.suffix
= LONG_MNEM_SUFFIX
;
5605 i
.suffix
= QWORD_MNEM_SUFFIX
;
5608 else if (prev_token
.code
== T_XWORD
)
5609 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5613 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5617 intel_match_token (T_PTR
);
5619 return (intel_e10 () && intel_e09_1 ());
5622 /* e09 : e10 e09' */
5623 else if (cur_token
.code
== ':')
5625 /* Mark as a memory operand only if it's not already known to be an
5626 offset expression. */
5627 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5628 intel_parser
.is_mem
= 1;
5630 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5645 return (intel_e11 () && intel_e10_1 ());
5651 /* e10' [ expr ] e10' */
5652 if (cur_token
.code
== '[')
5654 intel_match_token ('[');
5656 /* Mark as a memory operand only if it's not already known to be an
5657 offset expression. If it's an offset expression, we need to keep
5659 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5660 intel_parser
.is_mem
= 1;
5662 strcat (intel_parser
.disp
, "[");
5664 /* Add a '+' to the displacement string if necessary. */
5665 if (*intel_parser
.disp
!= '\0'
5666 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5667 strcat (intel_parser
.disp
, "+");
5669 if (intel_expr () && intel_match_token (']'))
5671 /* Preserve brackets when the operand is an offset expression. */
5672 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5673 strcat (intel_parser
.disp
, "]");
5675 return intel_e10_1 ();
5702 if (cur_token
.code
== '(')
5704 intel_match_token ('(');
5705 strcat (intel_parser
.disp
, "(");
5707 if (intel_expr () && intel_match_token (')'))
5709 strcat (intel_parser
.disp
, ")");
5717 else if (cur_token
.code
== '[')
5719 intel_match_token ('[');
5721 /* Mark as a memory operand only if it's not already known to be an
5722 offset expression. If it's an offset expression, we need to keep
5724 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5725 intel_parser
.is_mem
= 1;
5727 strcat (intel_parser
.disp
, "[");
5729 /* Operands for jump/call inside brackets denote absolute addresses. */
5730 if (current_templates
->start
->opcode_modifier
& Jump
5731 || current_templates
->start
->opcode_modifier
& JumpDword
5732 || current_templates
->start
->opcode_modifier
& JumpByte
5733 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5734 i
.types
[this_operand
] |= JumpAbsolute
;
5736 /* Add a '+' to the displacement string if necessary. */
5737 if (*intel_parser
.disp
!= '\0'
5738 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5739 strcat (intel_parser
.disp
, "+");
5741 if (intel_expr () && intel_match_token (']'))
5743 /* Preserve brackets when the operand is an offset expression. */
5744 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5745 strcat (intel_parser
.disp
, "]");
5758 else if (cur_token
.code
== T_BYTE
5759 || cur_token
.code
== T_WORD
5760 || cur_token
.code
== T_DWORD
5761 || cur_token
.code
== T_QWORD
5762 || cur_token
.code
== T_XWORD
)
5764 intel_match_token (cur_token
.code
);
5771 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5773 strcat (intel_parser
.disp
, cur_token
.str
);
5774 intel_match_token (cur_token
.code
);
5776 /* Mark as a memory operand only if it's not already known to be an
5777 offset expression. */
5778 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5779 intel_parser
.is_mem
= 1;
5785 else if (cur_token
.code
== T_REG
)
5787 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5789 intel_match_token (T_REG
);
5791 /* Check for segment change. */
5792 if (cur_token
.code
== ':')
5794 if (reg
->reg_type
& (SReg2
| SReg3
))
5796 switch (reg
->reg_num
)
5799 i
.seg
[i
.mem_operands
] = &es
;
5802 i
.seg
[i
.mem_operands
] = &cs
;
5805 i
.seg
[i
.mem_operands
] = &ss
;
5808 i
.seg
[i
.mem_operands
] = &ds
;
5811 i
.seg
[i
.mem_operands
] = &fs
;
5814 i
.seg
[i
.mem_operands
] = &gs
;
5820 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5825 /* Not a segment register. Check for register scaling. */
5826 else if (cur_token
.code
== '*')
5828 if (!intel_parser
.is_mem
)
5830 as_bad (_("Register scaling only allowed in memory operands."));
5834 /* What follows must be a valid scale. */
5835 if (intel_match_token ('*')
5836 && strchr ("01248", *cur_token
.str
))
5839 i
.types
[this_operand
] |= BaseIndex
;
5841 /* Set the scale after setting the register (otherwise,
5842 i386_scale will complain) */
5843 i386_scale (cur_token
.str
);
5844 intel_match_token (T_CONST
);
5848 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5854 /* No scaling. If this is a memory operand, the register is either a
5855 base register (first occurrence) or an index register (second
5857 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5859 if (i
.base_reg
&& i
.index_reg
)
5861 as_bad (_("Too many register references in memory operand.\n"));
5865 if (i
.base_reg
== NULL
)
5870 i
.types
[this_operand
] |= BaseIndex
;
5873 /* Offset modifier. Add the register to the displacement string to be
5874 parsed as an immediate expression after we're done. */
5875 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5876 strcat (intel_parser
.disp
, reg
->reg_name
);
5878 /* It's neither base nor index nor offset. */
5881 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5882 i
.op
[this_operand
].regs
= reg
;
5886 /* Since registers are not part of the displacement string (except
5887 when we're parsing offset operands), we may need to remove any
5888 preceding '+' from the displacement string. */
5889 if (*intel_parser
.disp
!= '\0'
5890 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5892 char *s
= intel_parser
.disp
;
5893 s
+= strlen (s
) - 1;
5902 else if (cur_token
.code
== T_ID
)
5904 /* Add the identifier to the displacement string. */
5905 strcat (intel_parser
.disp
, cur_token
.str
);
5906 intel_match_token (T_ID
);
5908 /* The identifier represents a memory reference only if it's not
5909 preceded by an offset modifier. */
5910 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5911 intel_parser
.is_mem
= 1;
5917 else if (cur_token
.code
== T_CONST
5918 || cur_token
.code
== '-'
5919 || cur_token
.code
== '+')
5923 /* Allow constants that start with `+' or `-'. */
5924 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5926 strcat (intel_parser
.disp
, cur_token
.str
);
5927 intel_match_token (cur_token
.code
);
5928 if (cur_token
.code
!= T_CONST
)
5930 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5936 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5937 if (save_str
== NULL
)
5939 strcpy (save_str
, cur_token
.str
);
5941 /* Get the next token to check for register scaling. */
5942 intel_match_token (cur_token
.code
);
5944 /* Check if this constant is a scaling factor for an index register. */
5945 if (cur_token
.code
== '*')
5947 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5949 if (!intel_parser
.is_mem
)
5951 as_bad (_("Register scaling only allowed in memory operands."));
5955 /* The constant is followed by `* reg', so it must be
5957 if (strchr ("01248", *save_str
))
5959 i
.index_reg
= cur_token
.reg
;
5960 i
.types
[this_operand
] |= BaseIndex
;
5962 /* Set the scale after setting the register (otherwise,
5963 i386_scale will complain) */
5964 i386_scale (save_str
);
5965 intel_match_token (T_REG
);
5967 /* Since registers are not part of the displacement
5968 string, we may need to remove any preceding '+' from
5969 the displacement string. */
5970 if (*intel_parser
.disp
!= '\0')
5972 char *s
= intel_parser
.disp
;
5973 s
+= strlen (s
) - 1;
5986 /* The constant was not used for register scaling. Since we have
5987 already consumed the token following `*' we now need to put it
5988 back in the stream. */
5990 intel_putback_token ();
5993 /* Add the constant to the displacement string. */
5994 strcat (intel_parser
.disp
, save_str
);
6000 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6004 /* Match the given token against cur_token. If they match, read the next
6005 token from the operand string. */
6007 intel_match_token (code
)
6010 if (cur_token
.code
== code
)
6017 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6022 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6027 const reg_entry
*reg
;
6028 struct intel_token new_token
;
6030 new_token
.code
= T_NIL
;
6031 new_token
.reg
= NULL
;
6032 new_token
.str
= NULL
;
6034 /* Free the memory allocated to the previous token and move
6035 cur_token to prev_token. */
6037 free (prev_token
.str
);
6039 prev_token
= cur_token
;
6041 /* Skip whitespace. */
6042 while (is_space_char (*intel_parser
.op_string
))
6043 intel_parser
.op_string
++;
6045 /* Return an empty token if we find nothing else on the line. */
6046 if (*intel_parser
.op_string
== '\0')
6048 cur_token
= new_token
;
6052 /* The new token cannot be larger than the remainder of the operand
6054 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6055 if (new_token
.str
== NULL
)
6057 new_token
.str
[0] = '\0';
6059 if (strchr ("0123456789", *intel_parser
.op_string
))
6061 char *p
= new_token
.str
;
6062 char *q
= intel_parser
.op_string
;
6063 new_token
.code
= T_CONST
;
6065 /* Allow any kind of identifier char to encompass floating point and
6066 hexadecimal numbers. */
6067 while (is_identifier_char (*q
))
6071 /* Recognize special symbol names [0-9][bf]. */
6072 if (strlen (intel_parser
.op_string
) == 2
6073 && (intel_parser
.op_string
[1] == 'b'
6074 || intel_parser
.op_string
[1] == 'f'))
6075 new_token
.code
= T_ID
;
6078 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6080 new_token
.code
= *intel_parser
.op_string
;
6081 new_token
.str
[0] = *intel_parser
.op_string
;
6082 new_token
.str
[1] = '\0';
6085 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6086 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6088 new_token
.code
= T_REG
;
6089 new_token
.reg
= reg
;
6091 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6093 new_token
.str
[0] = REGISTER_PREFIX
;
6094 new_token
.str
[1] = '\0';
6097 strcat (new_token
.str
, reg
->reg_name
);
6100 else if (is_identifier_char (*intel_parser
.op_string
))
6102 char *p
= new_token
.str
;
6103 char *q
= intel_parser
.op_string
;
6105 /* A '.' or '$' followed by an identifier char is an identifier.
6106 Otherwise, it's operator '.' followed by an expression. */
6107 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6109 new_token
.code
= *q
;
6110 new_token
.str
[0] = *q
;
6111 new_token
.str
[1] = '\0';
6115 while (is_identifier_char (*q
) || *q
== '@')
6119 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6120 new_token
.code
= T_BYTE
;
6122 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6123 new_token
.code
= T_WORD
;
6125 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6126 new_token
.code
= T_DWORD
;
6128 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6129 new_token
.code
= T_QWORD
;
6131 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6132 new_token
.code
= T_XWORD
;
6134 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6135 new_token
.code
= T_PTR
;
6137 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6138 new_token
.code
= T_SHORT
;
6140 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6142 new_token
.code
= T_OFFSET
;
6144 /* ??? This is not mentioned in the MASM grammar but gcc
6145 makes use of it with -mintel-syntax. OFFSET may be
6146 followed by FLAT: */
6147 if (strncasecmp (q
, " FLAT:", 6) == 0)
6148 strcat (new_token
.str
, " FLAT:");
6151 /* ??? This is not mentioned in the MASM grammar. */
6152 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6153 new_token
.code
= T_OFFSET
;
6156 new_token
.code
= T_ID
;
6161 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6163 intel_parser
.op_string
+= strlen (new_token
.str
);
6164 cur_token
= new_token
;
6167 /* Put cur_token back into the token stream and make cur_token point to
6170 intel_putback_token ()
6172 intel_parser
.op_string
-= strlen (cur_token
.str
);
6173 free (cur_token
.str
);
6174 cur_token
= prev_token
;
6176 /* Forget prev_token. */
6177 prev_token
.code
= T_NIL
;
6178 prev_token
.reg
= NULL
;
6179 prev_token
.str
= NULL
;