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Replace CET bit with IBT and SHSTK bits.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 };
285
286 struct _i386_insn
287 {
288 /* TM holds the template for the insn were currently assembling. */
289 insn_template tm;
290
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
293 char suffix;
294
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
300 operands. */
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
306
307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
310
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
314
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
317
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
327
328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
338 modrm_byte rm;
339 rex_byte rex;
340 rex_byte vrex;
341 sib_byte sib;
342 vex_prefix vex;
343
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
363
364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
371
372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
381 /* REP prefix. */
382 const char *rep_prefix;
383
384 /* HLE prefix. */
385 const char *hle_prefix;
386
387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
393 /* Error message. */
394 enum i386_error error;
395 };
396
397 typedef struct _i386_insn i386_insn;
398
399 /* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401 struct RC_name
402 {
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406 };
407
408 static const struct RC_name RC_NamesTable[] =
409 {
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415 };
416
417 /* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
419 const char extra_symbol_chars[] = "*%-([{}"
420 #ifdef LEX_AT
421 "@"
422 #endif
423 #ifdef LEX_QM
424 "?"
425 #endif
426 ;
427
428 #if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
430 && !defined (TE_GNU) \
431 && !defined (TE_LINUX) \
432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars = "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
443
444 #else
445 const char *i386_comment_chars = "#";
446 #define PREFIX_SEPARATOR '/'
447 #endif
448
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars[] = "#/";
458
459 const char line_separator_chars[] = ";";
460
461 /* Chars that can be used to separate mant from exp in floating point
462 nums. */
463 const char EXP_CHARS[] = "eE";
464
465 /* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
468 const char FLT_CHARS[] = "fFdDxX";
469
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars[256];
472 static char register_chars[256];
473 static char operand_chars[256];
474 static char identifier_chars[256];
475 static char digit_chars[256];
476
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
484
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack[32];
493 static char *save_stack_p;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
499 /* The instruction we're assembling. */
500 static i386_insn i;
501
502 /* Possible templates for current insn. */
503 static const templates *current_templates;
504
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
508
509 /* Current operand we are working on. */
510 static int this_operand = -1;
511
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515 enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520 static enum flag_code flag_code;
521 static unsigned int object_64bit;
522 static unsigned int disallow_64bit_reloc;
523 static int use_rela_relocations = 0;
524
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
529 /* The ELF ABI to use. */
530 enum x86_elf_abi
531 {
532 I386_ABI,
533 X86_64_ABI,
534 X86_64_X32_ABI
535 };
536
537 static enum x86_elf_abi x86_elf_abi = I386_ABI;
538 #endif
539
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj = 0;
543 #endif
544
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared = 0;
548 #endif
549
550 /* 1 for intel syntax,
551 0 if att syntax. */
552 static int intel_syntax = 0;
553
554 /* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556 static int intel64;
557
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic = !SYSV386_COMPAT;
561
562 /* 1 if support old (<= 2.8.1) versions of gcc. */
563 static int old_gcc = OLDGCC_COMPAT;
564
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg = 0;
567
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg = 0;
570
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574 static int add_bnd_prefix = 0;
575
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg = 0;
578
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix = 0;
582
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence = 0;
586
587 /* 1 if the assembler should generate relax relocations. */
588
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
592 static enum check_kind
593 {
594 check_none = 0,
595 check_warning,
596 check_error
597 }
598 sse_check, operand_check = check_warning;
599
600 /* Register prefix used for error message. */
601 static const char *register_prefix = "%";
602
603 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606 static char stackop_size = '\0';
607
608 /* Non-zero to optimize code alignment. */
609 int optimize_align_code = 1;
610
611 /* Non-zero to quieten some warnings. */
612 static int quiet_warnings = 0;
613
614 /* CPU name. */
615 static const char *cpu_arch_name = NULL;
616 static char *cpu_sub_arch_name = NULL;
617
618 /* CPU feature flags. */
619 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
621 /* If we have selected a cpu we are generating instructions for. */
622 static int cpu_arch_tune_set = 0;
623
624 /* Cpu we are generating instructions for. */
625 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
626
627 /* CPU feature flags of cpu we are generating instructions for. */
628 static i386_cpu_flags cpu_arch_tune_flags;
629
630 /* CPU instruction set architecture used. */
631 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
632
633 /* CPU feature flags of instruction set architecture used. */
634 i386_cpu_flags cpu_arch_isa_flags;
635
636 /* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638 static unsigned int no_cond_jump_promotion = 0;
639
640 /* Encode SSE instructions with VEX prefix. */
641 static unsigned int sse2avx;
642
643 /* Encode scalar AVX instructions with specific vector length. */
644 static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
650 /* Encode scalar EVEX LIG instructions with specific vector length. */
651 static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658 /* Encode EVEX WIG instructions with specific evex.w. */
659 static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
665 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
666 static enum rc_type evexrcig = rne;
667
668 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
669 static symbolS *GOT_symbol;
670
671 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
672 unsigned int x86_dwarf2_return_column;
673
674 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675 int x86_cie_data_alignment;
676
677 /* Interface to relax_segment.
678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
681
682 /* Types. */
683 #define UNCOND_JUMP 0
684 #define COND_JUMP 1
685 #define COND_JUMP86 2
686
687 /* Sizes. */
688 #define CODE16 1
689 #define SMALL 0
690 #define SMALL16 (SMALL | CODE16)
691 #define BIG 2
692 #define BIG16 (BIG | CODE16)
693
694 #ifndef INLINE
695 #ifdef __GNUC__
696 #define INLINE __inline__
697 #else
698 #define INLINE
699 #endif
700 #endif
701
702 #define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704 #define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706 #define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
708
709 /* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717 const relax_typeS md_relax_table[] =
718 {
719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
722 3) how many bytes this mode will have in the variable part of the frag
723 4) which index into the table to try if we can't fit into this one. */
724
725 /* UNCOND_JUMP states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
730 {0, 0, 4, 0},
731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
733 {0, 0, 2, 0},
734
735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
741 /* word conditionals add 3 bytes to frag:
742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
754 };
755
756 static const arch_entry cpu_arch[] =
757 {
758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
761 CPU_GENERIC32_FLAGS, 0 },
762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
763 CPU_GENERIC64_FLAGS, 0 },
764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
765 CPU_NONE_FLAGS, 0 },
766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
767 CPU_I186_FLAGS, 0 },
768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
769 CPU_I286_FLAGS, 0 },
770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
771 CPU_I386_FLAGS, 0 },
772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
773 CPU_I486_FLAGS, 0 },
774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
775 CPU_I586_FLAGS, 0 },
776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
777 CPU_I686_FLAGS, 0 },
778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
779 CPU_I586_FLAGS, 0 },
780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
781 CPU_PENTIUMPRO_FLAGS, 0 },
782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
783 CPU_P2_FLAGS, 0 },
784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
785 CPU_P3_FLAGS, 0 },
786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
787 CPU_P4_FLAGS, 0 },
788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
789 CPU_CORE_FLAGS, 0 },
790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
791 CPU_NOCONA_FLAGS, 0 },
792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
793 CPU_CORE_FLAGS, 1 },
794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
795 CPU_CORE_FLAGS, 0 },
796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
797 CPU_CORE2_FLAGS, 1 },
798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
799 CPU_CORE2_FLAGS, 0 },
800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
801 CPU_COREI7_FLAGS, 0 },
802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
803 CPU_L1OM_FLAGS, 0 },
804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
805 CPU_K1OM_FLAGS, 0 },
806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
807 CPU_IAMCU_FLAGS, 0 },
808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
809 CPU_K6_FLAGS, 0 },
810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
811 CPU_K6_2_FLAGS, 0 },
812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
813 CPU_ATHLON_FLAGS, 0 },
814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
815 CPU_K8_FLAGS, 1 },
816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
817 CPU_K8_FLAGS, 0 },
818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
819 CPU_K8_FLAGS, 0 },
820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
821 CPU_AMDFAM10_FLAGS, 0 },
822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
823 CPU_BDVER1_FLAGS, 0 },
824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
825 CPU_BDVER2_FLAGS, 0 },
826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
827 CPU_BDVER3_FLAGS, 0 },
828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
829 CPU_BDVER4_FLAGS, 0 },
830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
831 CPU_ZNVER1_FLAGS, 0 },
832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
833 CPU_BTVER1_FLAGS, 0 },
834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
835 CPU_BTVER2_FLAGS, 0 },
836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
837 CPU_8087_FLAGS, 0 },
838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
839 CPU_287_FLAGS, 0 },
840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
841 CPU_387_FLAGS, 0 },
842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
845 CPU_MMX_FLAGS, 0 },
846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
847 CPU_SSE_FLAGS, 0 },
848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
849 CPU_SSE2_FLAGS, 0 },
850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
851 CPU_SSE3_FLAGS, 0 },
852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
853 CPU_SSSE3_FLAGS, 0 },
854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
855 CPU_SSE4_1_FLAGS, 0 },
856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
857 CPU_SSE4_2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
859 CPU_SSE4_2_FLAGS, 0 },
860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
861 CPU_AVX_FLAGS, 0 },
862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
863 CPU_AVX2_FLAGS, 0 },
864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
865 CPU_AVX512F_FLAGS, 0 },
866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
867 CPU_AVX512CD_FLAGS, 0 },
868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
869 CPU_AVX512ER_FLAGS, 0 },
870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
871 CPU_AVX512PF_FLAGS, 0 },
872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
873 CPU_AVX512DQ_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
875 CPU_AVX512BW_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
877 CPU_AVX512VL_FLAGS, 0 },
878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
879 CPU_VMX_FLAGS, 0 },
880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
881 CPU_VMFUNC_FLAGS, 0 },
882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
883 CPU_SMX_FLAGS, 0 },
884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
885 CPU_XSAVE_FLAGS, 0 },
886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
887 CPU_XSAVEOPT_FLAGS, 0 },
888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
889 CPU_XSAVEC_FLAGS, 0 },
890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
891 CPU_XSAVES_FLAGS, 0 },
892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
893 CPU_AES_FLAGS, 0 },
894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
895 CPU_PCLMUL_FLAGS, 0 },
896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
897 CPU_PCLMUL_FLAGS, 1 },
898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
899 CPU_FSGSBASE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
901 CPU_RDRND_FLAGS, 0 },
902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
903 CPU_F16C_FLAGS, 0 },
904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
905 CPU_BMI2_FLAGS, 0 },
906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
907 CPU_FMA_FLAGS, 0 },
908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
909 CPU_FMA4_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
911 CPU_XOP_FLAGS, 0 },
912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
913 CPU_LWP_FLAGS, 0 },
914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
915 CPU_MOVBE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
917 CPU_CX16_FLAGS, 0 },
918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
919 CPU_EPT_FLAGS, 0 },
920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
921 CPU_LZCNT_FLAGS, 0 },
922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
923 CPU_HLE_FLAGS, 0 },
924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
925 CPU_RTM_FLAGS, 0 },
926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
927 CPU_INVPCID_FLAGS, 0 },
928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
929 CPU_CLFLUSH_FLAGS, 0 },
930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
931 CPU_NOP_FLAGS, 0 },
932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
933 CPU_SYSCALL_FLAGS, 0 },
934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
935 CPU_RDTSCP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
937 CPU_3DNOW_FLAGS, 0 },
938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
939 CPU_3DNOWA_FLAGS, 0 },
940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
941 CPU_PADLOCK_FLAGS, 0 },
942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
943 CPU_SVME_FLAGS, 1 },
944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
945 CPU_SVME_FLAGS, 0 },
946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
947 CPU_SSE4A_FLAGS, 0 },
948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
949 CPU_ABM_FLAGS, 0 },
950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
951 CPU_BMI_FLAGS, 0 },
952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
953 CPU_TBM_FLAGS, 0 },
954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
955 CPU_ADX_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
957 CPU_RDSEED_FLAGS, 0 },
958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
959 CPU_PRFCHW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
961 CPU_SMAP_FLAGS, 0 },
962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
963 CPU_MPX_FLAGS, 0 },
964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
965 CPU_SHA_FLAGS, 0 },
966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
967 CPU_CLFLUSHOPT_FLAGS, 0 },
968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
969 CPU_PREFETCHWT1_FLAGS, 0 },
970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
971 CPU_SE1_FLAGS, 0 },
972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
973 CPU_CLWB_FLAGS, 0 },
974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
975 CPU_AVX512IFMA_FLAGS, 0 },
976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
977 CPU_AVX512VBMI_FLAGS, 0 },
978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
991 CPU_CLZERO_FLAGS, 0 },
992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
993 CPU_MWAITX_FLAGS, 0 },
994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
995 CPU_OSPKE_FLAGS, 0 },
996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
997 CPU_RDPID_FLAGS, 0 },
998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1001 CPU_IBT_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1003 CPU_SHSTK_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1005 CPU_GFNI_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1007 CPU_VAES_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1009 CPU_VPCLMULQDQ_FLAGS, 0 },
1010 };
1011
1012 static const noarch_entry cpu_noarch[] =
1013 {
1014 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1015 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1016 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1017 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1018 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1019 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1020 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1021 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1022 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1024 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1025 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1026 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1027 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1036 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1037 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1038 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1039 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1040 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1041 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1042 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1043 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1044 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1045 };
1046
1047 #ifdef I386COFF
1048 /* Like s_lcomm_internal in gas/read.c but the alignment string
1049 is allowed to be optional. */
1050
1051 static symbolS *
1052 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1053 {
1054 addressT align = 0;
1055
1056 SKIP_WHITESPACE ();
1057
1058 if (needs_align
1059 && *input_line_pointer == ',')
1060 {
1061 align = parse_align (needs_align - 1);
1062
1063 if (align == (addressT) -1)
1064 return NULL;
1065 }
1066 else
1067 {
1068 if (size >= 8)
1069 align = 3;
1070 else if (size >= 4)
1071 align = 2;
1072 else if (size >= 2)
1073 align = 1;
1074 else
1075 align = 0;
1076 }
1077
1078 bss_alloc (symbolP, size, align);
1079 return symbolP;
1080 }
1081
1082 static void
1083 pe_lcomm (int needs_align)
1084 {
1085 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1086 }
1087 #endif
1088
1089 const pseudo_typeS md_pseudo_table[] =
1090 {
1091 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1092 {"align", s_align_bytes, 0},
1093 #else
1094 {"align", s_align_ptwo, 0},
1095 #endif
1096 {"arch", set_cpu_arch, 0},
1097 #ifndef I386COFF
1098 {"bss", s_bss, 0},
1099 #else
1100 {"lcomm", pe_lcomm, 1},
1101 #endif
1102 {"ffloat", float_cons, 'f'},
1103 {"dfloat", float_cons, 'd'},
1104 {"tfloat", float_cons, 'x'},
1105 {"value", cons, 2},
1106 {"slong", signed_cons, 4},
1107 {"noopt", s_ignore, 0},
1108 {"optim", s_ignore, 0},
1109 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1110 {"code16", set_code_flag, CODE_16BIT},
1111 {"code32", set_code_flag, CODE_32BIT},
1112 #ifdef BFD64
1113 {"code64", set_code_flag, CODE_64BIT},
1114 #endif
1115 {"intel_syntax", set_intel_syntax, 1},
1116 {"att_syntax", set_intel_syntax, 0},
1117 {"intel_mnemonic", set_intel_mnemonic, 1},
1118 {"att_mnemonic", set_intel_mnemonic, 0},
1119 {"allow_index_reg", set_allow_index_reg, 1},
1120 {"disallow_index_reg", set_allow_index_reg, 0},
1121 {"sse_check", set_check, 0},
1122 {"operand_check", set_check, 1},
1123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1124 {"largecomm", handle_large_common, 0},
1125 #else
1126 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1127 {"loc", dwarf2_directive_loc, 0},
1128 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1129 #endif
1130 #ifdef TE_PE
1131 {"secrel32", pe_directive_secrel, 0},
1132 #endif
1133 {0, 0, 0}
1134 };
1135
1136 /* For interface with expression (). */
1137 extern char *input_line_pointer;
1138
1139 /* Hash table for instruction mnemonic lookup. */
1140 static struct hash_control *op_hash;
1141
1142 /* Hash table for register lookup. */
1143 static struct hash_control *reg_hash;
1144 \f
1145 void
1146 i386_align_code (fragS *fragP, int count)
1147 {
1148 /* Various efficient no-op patterns for aligning code labels.
1149 Note: Don't try to assemble the instructions in the comments.
1150 0L and 0w are not legal. */
1151 static const unsigned char f32_1[] =
1152 {0x90}; /* nop */
1153 static const unsigned char f32_2[] =
1154 {0x66,0x90}; /* xchg %ax,%ax */
1155 static const unsigned char f32_3[] =
1156 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1157 static const unsigned char f32_4[] =
1158 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1159 static const unsigned char f32_5[] =
1160 {0x90, /* nop */
1161 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1162 static const unsigned char f32_6[] =
1163 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1164 static const unsigned char f32_7[] =
1165 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1166 static const unsigned char f32_8[] =
1167 {0x90, /* nop */
1168 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1169 static const unsigned char f32_9[] =
1170 {0x89,0xf6, /* movl %esi,%esi */
1171 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1172 static const unsigned char f32_10[] =
1173 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1174 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1175 static const unsigned char f32_11[] =
1176 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1177 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1178 static const unsigned char f32_12[] =
1179 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1180 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1181 static const unsigned char f32_13[] =
1182 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1183 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1184 static const unsigned char f32_14[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1186 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1187 static const unsigned char f16_3[] =
1188 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1189 static const unsigned char f16_4[] =
1190 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1191 static const unsigned char f16_5[] =
1192 {0x90, /* nop */
1193 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1194 static const unsigned char f16_6[] =
1195 {0x89,0xf6, /* mov %si,%si */
1196 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1197 static const unsigned char f16_7[] =
1198 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1199 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1200 static const unsigned char f16_8[] =
1201 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1202 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1203 static const unsigned char jump_31[] =
1204 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1205 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1206 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1207 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1208 static const unsigned char *const f32_patt[] = {
1209 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1210 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1211 };
1212 static const unsigned char *const f16_patt[] = {
1213 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1214 };
1215 /* nopl (%[re]ax) */
1216 static const unsigned char alt_3[] =
1217 {0x0f,0x1f,0x00};
1218 /* nopl 0(%[re]ax) */
1219 static const unsigned char alt_4[] =
1220 {0x0f,0x1f,0x40,0x00};
1221 /* nopl 0(%[re]ax,%[re]ax,1) */
1222 static const unsigned char alt_5[] =
1223 {0x0f,0x1f,0x44,0x00,0x00};
1224 /* nopw 0(%[re]ax,%[re]ax,1) */
1225 static const unsigned char alt_6[] =
1226 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1227 /* nopl 0L(%[re]ax) */
1228 static const unsigned char alt_7[] =
1229 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1230 /* nopl 0L(%[re]ax,%[re]ax,1) */
1231 static const unsigned char alt_8[] =
1232 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1233 /* nopw 0L(%[re]ax,%[re]ax,1) */
1234 static const unsigned char alt_9[] =
1235 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1236 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1237 static const unsigned char alt_10[] =
1238 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1239 static const unsigned char *const alt_patt[] = {
1240 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1241 alt_9, alt_10
1242 };
1243
1244 /* Only align for at least a positive non-zero boundary. */
1245 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1246 return;
1247
1248 /* We need to decide which NOP sequence to use for 32bit and
1249 64bit. When -mtune= is used:
1250
1251 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1252 PROCESSOR_GENERIC32, f32_patt will be used.
1253 2. For the rest, alt_patt will be used.
1254
1255 When -mtune= isn't used, alt_patt will be used if
1256 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1257 be used.
1258
1259 When -march= or .arch is used, we can't use anything beyond
1260 cpu_arch_isa_flags. */
1261
1262 if (flag_code == CODE_16BIT)
1263 {
1264 if (count > 8)
1265 {
1266 memcpy (fragP->fr_literal + fragP->fr_fix,
1267 jump_31, count);
1268 /* Adjust jump offset. */
1269 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1270 }
1271 else
1272 memcpy (fragP->fr_literal + fragP->fr_fix,
1273 f16_patt[count - 1], count);
1274 }
1275 else
1276 {
1277 const unsigned char *const *patt = NULL;
1278
1279 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1280 {
1281 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1282 switch (cpu_arch_tune)
1283 {
1284 case PROCESSOR_UNKNOWN:
1285 /* We use cpu_arch_isa_flags to check if we SHOULD
1286 optimize with nops. */
1287 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1288 patt = alt_patt;
1289 else
1290 patt = f32_patt;
1291 break;
1292 case PROCESSOR_PENTIUM4:
1293 case PROCESSOR_NOCONA:
1294 case PROCESSOR_CORE:
1295 case PROCESSOR_CORE2:
1296 case PROCESSOR_COREI7:
1297 case PROCESSOR_L1OM:
1298 case PROCESSOR_K1OM:
1299 case PROCESSOR_GENERIC64:
1300 case PROCESSOR_K6:
1301 case PROCESSOR_ATHLON:
1302 case PROCESSOR_K8:
1303 case PROCESSOR_AMDFAM10:
1304 case PROCESSOR_BD:
1305 case PROCESSOR_ZNVER:
1306 case PROCESSOR_BT:
1307 patt = alt_patt;
1308 break;
1309 case PROCESSOR_I386:
1310 case PROCESSOR_I486:
1311 case PROCESSOR_PENTIUM:
1312 case PROCESSOR_PENTIUMPRO:
1313 case PROCESSOR_IAMCU:
1314 case PROCESSOR_GENERIC32:
1315 patt = f32_patt;
1316 break;
1317 }
1318 }
1319 else
1320 {
1321 switch (fragP->tc_frag_data.tune)
1322 {
1323 case PROCESSOR_UNKNOWN:
1324 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1325 PROCESSOR_UNKNOWN. */
1326 abort ();
1327 break;
1328
1329 case PROCESSOR_I386:
1330 case PROCESSOR_I486:
1331 case PROCESSOR_PENTIUM:
1332 case PROCESSOR_IAMCU:
1333 case PROCESSOR_K6:
1334 case PROCESSOR_ATHLON:
1335 case PROCESSOR_K8:
1336 case PROCESSOR_AMDFAM10:
1337 case PROCESSOR_BD:
1338 case PROCESSOR_ZNVER:
1339 case PROCESSOR_BT:
1340 case PROCESSOR_GENERIC32:
1341 /* We use cpu_arch_isa_flags to check if we CAN optimize
1342 with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1344 patt = alt_patt;
1345 else
1346 patt = f32_patt;
1347 break;
1348 case PROCESSOR_PENTIUMPRO:
1349 case PROCESSOR_PENTIUM4:
1350 case PROCESSOR_NOCONA:
1351 case PROCESSOR_CORE:
1352 case PROCESSOR_CORE2:
1353 case PROCESSOR_COREI7:
1354 case PROCESSOR_L1OM:
1355 case PROCESSOR_K1OM:
1356 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1357 patt = alt_patt;
1358 else
1359 patt = f32_patt;
1360 break;
1361 case PROCESSOR_GENERIC64:
1362 patt = alt_patt;
1363 break;
1364 }
1365 }
1366
1367 if (patt == f32_patt)
1368 {
1369 /* If the padding is less than 15 bytes, we use the normal
1370 ones. Otherwise, we use a jump instruction and adjust
1371 its offset. */
1372 int limit;
1373
1374 /* For 64bit, the limit is 3 bytes. */
1375 if (flag_code == CODE_64BIT
1376 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1377 limit = 3;
1378 else
1379 limit = 15;
1380 if (count < limit)
1381 memcpy (fragP->fr_literal + fragP->fr_fix,
1382 patt[count - 1], count);
1383 else
1384 {
1385 memcpy (fragP->fr_literal + fragP->fr_fix,
1386 jump_31, count);
1387 /* Adjust jump offset. */
1388 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1389 }
1390 }
1391 else
1392 {
1393 /* Maximum length of an instruction is 10 byte. If the
1394 padding is greater than 10 bytes and we don't use jump,
1395 we have to break it into smaller pieces. */
1396 int padding = count;
1397 while (padding > 10)
1398 {
1399 padding -= 10;
1400 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1401 patt [9], 10);
1402 }
1403
1404 if (padding)
1405 memcpy (fragP->fr_literal + fragP->fr_fix,
1406 patt [padding - 1], padding);
1407 }
1408 }
1409 fragP->fr_var = count;
1410 }
1411
1412 static INLINE int
1413 operand_type_all_zero (const union i386_operand_type *x)
1414 {
1415 switch (ARRAY_SIZE(x->array))
1416 {
1417 case 3:
1418 if (x->array[2])
1419 return 0;
1420 /* Fall through. */
1421 case 2:
1422 if (x->array[1])
1423 return 0;
1424 /* Fall through. */
1425 case 1:
1426 return !x->array[0];
1427 default:
1428 abort ();
1429 }
1430 }
1431
1432 static INLINE void
1433 operand_type_set (union i386_operand_type *x, unsigned int v)
1434 {
1435 switch (ARRAY_SIZE(x->array))
1436 {
1437 case 3:
1438 x->array[2] = v;
1439 /* Fall through. */
1440 case 2:
1441 x->array[1] = v;
1442 /* Fall through. */
1443 case 1:
1444 x->array[0] = v;
1445 /* Fall through. */
1446 break;
1447 default:
1448 abort ();
1449 }
1450 }
1451
1452 static INLINE int
1453 operand_type_equal (const union i386_operand_type *x,
1454 const union i386_operand_type *y)
1455 {
1456 switch (ARRAY_SIZE(x->array))
1457 {
1458 case 3:
1459 if (x->array[2] != y->array[2])
1460 return 0;
1461 /* Fall through. */
1462 case 2:
1463 if (x->array[1] != y->array[1])
1464 return 0;
1465 /* Fall through. */
1466 case 1:
1467 return x->array[0] == y->array[0];
1468 break;
1469 default:
1470 abort ();
1471 }
1472 }
1473
1474 static INLINE int
1475 cpu_flags_all_zero (const union i386_cpu_flags *x)
1476 {
1477 switch (ARRAY_SIZE(x->array))
1478 {
1479 case 4:
1480 if (x->array[3])
1481 return 0;
1482 /* Fall through. */
1483 case 3:
1484 if (x->array[2])
1485 return 0;
1486 /* Fall through. */
1487 case 2:
1488 if (x->array[1])
1489 return 0;
1490 /* Fall through. */
1491 case 1:
1492 return !x->array[0];
1493 default:
1494 abort ();
1495 }
1496 }
1497
1498 static INLINE int
1499 cpu_flags_equal (const union i386_cpu_flags *x,
1500 const union i386_cpu_flags *y)
1501 {
1502 switch (ARRAY_SIZE(x->array))
1503 {
1504 case 4:
1505 if (x->array[3] != y->array[3])
1506 return 0;
1507 /* Fall through. */
1508 case 3:
1509 if (x->array[2] != y->array[2])
1510 return 0;
1511 /* Fall through. */
1512 case 2:
1513 if (x->array[1] != y->array[1])
1514 return 0;
1515 /* Fall through. */
1516 case 1:
1517 return x->array[0] == y->array[0];
1518 break;
1519 default:
1520 abort ();
1521 }
1522 }
1523
1524 static INLINE int
1525 cpu_flags_check_cpu64 (i386_cpu_flags f)
1526 {
1527 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1528 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1529 }
1530
1531 static INLINE i386_cpu_flags
1532 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1533 {
1534 switch (ARRAY_SIZE (x.array))
1535 {
1536 case 4:
1537 x.array [3] &= y.array [3];
1538 /* Fall through. */
1539 case 3:
1540 x.array [2] &= y.array [2];
1541 /* Fall through. */
1542 case 2:
1543 x.array [1] &= y.array [1];
1544 /* Fall through. */
1545 case 1:
1546 x.array [0] &= y.array [0];
1547 break;
1548 default:
1549 abort ();
1550 }
1551 return x;
1552 }
1553
1554 static INLINE i386_cpu_flags
1555 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1556 {
1557 switch (ARRAY_SIZE (x.array))
1558 {
1559 case 4:
1560 x.array [3] |= y.array [3];
1561 /* Fall through. */
1562 case 3:
1563 x.array [2] |= y.array [2];
1564 /* Fall through. */
1565 case 2:
1566 x.array [1] |= y.array [1];
1567 /* Fall through. */
1568 case 1:
1569 x.array [0] |= y.array [0];
1570 break;
1571 default:
1572 abort ();
1573 }
1574 return x;
1575 }
1576
1577 static INLINE i386_cpu_flags
1578 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1579 {
1580 switch (ARRAY_SIZE (x.array))
1581 {
1582 case 4:
1583 x.array [3] &= ~y.array [3];
1584 /* Fall through. */
1585 case 3:
1586 x.array [2] &= ~y.array [2];
1587 /* Fall through. */
1588 case 2:
1589 x.array [1] &= ~y.array [1];
1590 /* Fall through. */
1591 case 1:
1592 x.array [0] &= ~y.array [0];
1593 break;
1594 default:
1595 abort ();
1596 }
1597 return x;
1598 }
1599
1600 #define CPU_FLAGS_ARCH_MATCH 0x1
1601 #define CPU_FLAGS_64BIT_MATCH 0x2
1602 #define CPU_FLAGS_AES_MATCH 0x4
1603 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1604 #define CPU_FLAGS_AVX_MATCH 0x10
1605
1606 #define CPU_FLAGS_32BIT_MATCH \
1607 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1608 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1609 #define CPU_FLAGS_PERFECT_MATCH \
1610 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1611
1612 /* Return CPU flags match bits. */
1613
1614 static int
1615 cpu_flags_match (const insn_template *t)
1616 {
1617 i386_cpu_flags x = t->cpu_flags;
1618 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1619
1620 x.bitfield.cpu64 = 0;
1621 x.bitfield.cpuno64 = 0;
1622
1623 if (cpu_flags_all_zero (&x))
1624 {
1625 /* This instruction is available on all archs. */
1626 match |= CPU_FLAGS_32BIT_MATCH;
1627 }
1628 else
1629 {
1630 /* This instruction is available only on some archs. */
1631 i386_cpu_flags cpu = cpu_arch_flags;
1632
1633 cpu = cpu_flags_and (x, cpu);
1634 if (!cpu_flags_all_zero (&cpu))
1635 {
1636 if (x.bitfield.cpuavx)
1637 {
1638 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1639 if (cpu.bitfield.cpuavx)
1640 {
1641 /* Check SSE2AVX. */
1642 if (!t->opcode_modifier.sse2avx|| sse2avx)
1643 {
1644 match |= (CPU_FLAGS_ARCH_MATCH
1645 | CPU_FLAGS_AVX_MATCH);
1646 /* Check AES. */
1647 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1648 match |= CPU_FLAGS_AES_MATCH;
1649 /* Check PCLMUL. */
1650 if (!x.bitfield.cpupclmul
1651 || cpu.bitfield.cpupclmul)
1652 match |= CPU_FLAGS_PCLMUL_MATCH;
1653 }
1654 }
1655 else
1656 match |= CPU_FLAGS_ARCH_MATCH;
1657 }
1658 else if (x.bitfield.cpuavx512vl)
1659 {
1660 /* Match AVX512VL. */
1661 if (cpu.bitfield.cpuavx512vl)
1662 {
1663 /* Need another match. */
1664 cpu.bitfield.cpuavx512vl = 0;
1665 if (!cpu_flags_all_zero (&cpu))
1666 match |= CPU_FLAGS_32BIT_MATCH;
1667 else
1668 match |= CPU_FLAGS_ARCH_MATCH;
1669 }
1670 else
1671 match |= CPU_FLAGS_ARCH_MATCH;
1672 }
1673 else
1674 match |= CPU_FLAGS_32BIT_MATCH;
1675 }
1676 }
1677 return match;
1678 }
1679
1680 static INLINE i386_operand_type
1681 operand_type_and (i386_operand_type x, i386_operand_type y)
1682 {
1683 switch (ARRAY_SIZE (x.array))
1684 {
1685 case 3:
1686 x.array [2] &= y.array [2];
1687 /* Fall through. */
1688 case 2:
1689 x.array [1] &= y.array [1];
1690 /* Fall through. */
1691 case 1:
1692 x.array [0] &= y.array [0];
1693 break;
1694 default:
1695 abort ();
1696 }
1697 return x;
1698 }
1699
1700 static INLINE i386_operand_type
1701 operand_type_or (i386_operand_type x, i386_operand_type y)
1702 {
1703 switch (ARRAY_SIZE (x.array))
1704 {
1705 case 3:
1706 x.array [2] |= y.array [2];
1707 /* Fall through. */
1708 case 2:
1709 x.array [1] |= y.array [1];
1710 /* Fall through. */
1711 case 1:
1712 x.array [0] |= y.array [0];
1713 break;
1714 default:
1715 abort ();
1716 }
1717 return x;
1718 }
1719
1720 static INLINE i386_operand_type
1721 operand_type_xor (i386_operand_type x, i386_operand_type y)
1722 {
1723 switch (ARRAY_SIZE (x.array))
1724 {
1725 case 3:
1726 x.array [2] ^= y.array [2];
1727 /* Fall through. */
1728 case 2:
1729 x.array [1] ^= y.array [1];
1730 /* Fall through. */
1731 case 1:
1732 x.array [0] ^= y.array [0];
1733 break;
1734 default:
1735 abort ();
1736 }
1737 return x;
1738 }
1739
1740 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1741 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1742 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1743 static const i386_operand_type inoutportreg
1744 = OPERAND_TYPE_INOUTPORTREG;
1745 static const i386_operand_type reg16_inoutportreg
1746 = OPERAND_TYPE_REG16_INOUTPORTREG;
1747 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1748 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1749 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1750 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1751 static const i386_operand_type anydisp
1752 = OPERAND_TYPE_ANYDISP;
1753 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1754 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1755 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1756 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1757 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1758 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1759 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1760 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1761 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1762 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1763 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1764 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1765
1766 enum operand_type
1767 {
1768 reg,
1769 imm,
1770 disp,
1771 anymem
1772 };
1773
1774 static INLINE int
1775 operand_type_check (i386_operand_type t, enum operand_type c)
1776 {
1777 switch (c)
1778 {
1779 case reg:
1780 return t.bitfield.reg;
1781
1782 case imm:
1783 return (t.bitfield.imm8
1784 || t.bitfield.imm8s
1785 || t.bitfield.imm16
1786 || t.bitfield.imm32
1787 || t.bitfield.imm32s
1788 || t.bitfield.imm64);
1789
1790 case disp:
1791 return (t.bitfield.disp8
1792 || t.bitfield.disp16
1793 || t.bitfield.disp32
1794 || t.bitfield.disp32s
1795 || t.bitfield.disp64);
1796
1797 case anymem:
1798 return (t.bitfield.disp8
1799 || t.bitfield.disp16
1800 || t.bitfield.disp32
1801 || t.bitfield.disp32s
1802 || t.bitfield.disp64
1803 || t.bitfield.baseindex);
1804
1805 default:
1806 abort ();
1807 }
1808
1809 return 0;
1810 }
1811
1812 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1813 operand J for instruction template T. */
1814
1815 static INLINE int
1816 match_reg_size (const insn_template *t, unsigned int j)
1817 {
1818 return !((i.types[j].bitfield.byte
1819 && !t->operand_types[j].bitfield.byte)
1820 || (i.types[j].bitfield.word
1821 && !t->operand_types[j].bitfield.word)
1822 || (i.types[j].bitfield.dword
1823 && !t->operand_types[j].bitfield.dword)
1824 || (i.types[j].bitfield.qword
1825 && !t->operand_types[j].bitfield.qword)
1826 || (i.types[j].bitfield.tbyte
1827 && !t->operand_types[j].bitfield.tbyte));
1828 }
1829
1830 /* Return 1 if there is no conflict in SIMD register on
1831 operand J for instruction template T. */
1832
1833 static INLINE int
1834 match_simd_size (const insn_template *t, unsigned int j)
1835 {
1836 return !((i.types[j].bitfield.xmmword
1837 && !t->operand_types[j].bitfield.xmmword)
1838 || (i.types[j].bitfield.ymmword
1839 && !t->operand_types[j].bitfield.ymmword)
1840 || (i.types[j].bitfield.zmmword
1841 && !t->operand_types[j].bitfield.zmmword));
1842 }
1843
1844 /* Return 1 if there is no conflict in any size on operand J for
1845 instruction template T. */
1846
1847 static INLINE int
1848 match_mem_size (const insn_template *t, unsigned int j)
1849 {
1850 return (match_reg_size (t, j)
1851 && !((i.types[j].bitfield.unspecified
1852 && !i.broadcast
1853 && !t->operand_types[j].bitfield.unspecified)
1854 || (i.types[j].bitfield.fword
1855 && !t->operand_types[j].bitfield.fword)
1856 /* For scalar opcode templates to allow register and memory
1857 operands at the same time, some special casing is needed
1858 here. */
1859 || ((t->operand_types[j].bitfield.regsimd
1860 && !t->opcode_modifier.broadcast
1861 && (t->operand_types[j].bitfield.dword
1862 || t->operand_types[j].bitfield.qword))
1863 ? (i.types[j].bitfield.xmmword
1864 || i.types[j].bitfield.ymmword
1865 || i.types[j].bitfield.zmmword)
1866 : !match_simd_size(t, j))));
1867 }
1868
1869 /* Return 1 if there is no size conflict on any operands for
1870 instruction template T. */
1871
1872 static INLINE int
1873 operand_size_match (const insn_template *t)
1874 {
1875 unsigned int j;
1876 int match = 1;
1877
1878 /* Don't check jump instructions. */
1879 if (t->opcode_modifier.jump
1880 || t->opcode_modifier.jumpbyte
1881 || t->opcode_modifier.jumpdword
1882 || t->opcode_modifier.jumpintersegment)
1883 return match;
1884
1885 /* Check memory and accumulator operand size. */
1886 for (j = 0; j < i.operands; j++)
1887 {
1888 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1889 && t->operand_types[j].bitfield.anysize)
1890 continue;
1891
1892 if (t->operand_types[j].bitfield.reg
1893 && !match_reg_size (t, j))
1894 {
1895 match = 0;
1896 break;
1897 }
1898
1899 if (t->operand_types[j].bitfield.regsimd
1900 && !match_simd_size (t, j))
1901 {
1902 match = 0;
1903 break;
1904 }
1905
1906 if (t->operand_types[j].bitfield.acc
1907 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1908 {
1909 match = 0;
1910 break;
1911 }
1912
1913 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1914 {
1915 match = 0;
1916 break;
1917 }
1918 }
1919
1920 if (match)
1921 return match;
1922 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1923 {
1924 mismatch:
1925 i.error = operand_size_mismatch;
1926 return 0;
1927 }
1928
1929 /* Check reverse. */
1930 gas_assert (i.operands == 2);
1931
1932 match = 1;
1933 for (j = 0; j < 2; j++)
1934 {
1935 if ((t->operand_types[j].bitfield.reg
1936 || t->operand_types[j].bitfield.acc)
1937 && !match_reg_size (t, j ? 0 : 1))
1938 goto mismatch;
1939
1940 if (i.types[j].bitfield.mem
1941 && !match_mem_size (t, j ? 0 : 1))
1942 goto mismatch;
1943 }
1944
1945 return match;
1946 }
1947
1948 static INLINE int
1949 operand_type_match (i386_operand_type overlap,
1950 i386_operand_type given)
1951 {
1952 i386_operand_type temp = overlap;
1953
1954 temp.bitfield.jumpabsolute = 0;
1955 temp.bitfield.unspecified = 0;
1956 temp.bitfield.byte = 0;
1957 temp.bitfield.word = 0;
1958 temp.bitfield.dword = 0;
1959 temp.bitfield.fword = 0;
1960 temp.bitfield.qword = 0;
1961 temp.bitfield.tbyte = 0;
1962 temp.bitfield.xmmword = 0;
1963 temp.bitfield.ymmword = 0;
1964 temp.bitfield.zmmword = 0;
1965 if (operand_type_all_zero (&temp))
1966 goto mismatch;
1967
1968 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1969 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1970 return 1;
1971
1972 mismatch:
1973 i.error = operand_type_mismatch;
1974 return 0;
1975 }
1976
1977 /* If given types g0 and g1 are registers they must be of the same type
1978 unless the expected operand type register overlap is null.
1979 Memory operand size of certain SIMD instructions is also being checked
1980 here. */
1981
1982 static INLINE int
1983 operand_type_register_match (i386_operand_type g0,
1984 i386_operand_type t0,
1985 i386_operand_type g1,
1986 i386_operand_type t1)
1987 {
1988 if (!g0.bitfield.reg
1989 && !g0.bitfield.regsimd
1990 && (!operand_type_check (g0, anymem)
1991 || g0.bitfield.unspecified
1992 || !t0.bitfield.regsimd))
1993 return 1;
1994
1995 if (!g1.bitfield.reg
1996 && !g1.bitfield.regsimd
1997 && (!operand_type_check (g1, anymem)
1998 || g1.bitfield.unspecified
1999 || !t1.bitfield.regsimd))
2000 return 1;
2001
2002 if (g0.bitfield.byte == g1.bitfield.byte
2003 && g0.bitfield.word == g1.bitfield.word
2004 && g0.bitfield.dword == g1.bitfield.dword
2005 && g0.bitfield.qword == g1.bitfield.qword
2006 && g0.bitfield.xmmword == g1.bitfield.xmmword
2007 && g0.bitfield.ymmword == g1.bitfield.ymmword
2008 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2009 return 1;
2010
2011 if (!(t0.bitfield.byte & t1.bitfield.byte)
2012 && !(t0.bitfield.word & t1.bitfield.word)
2013 && !(t0.bitfield.dword & t1.bitfield.dword)
2014 && !(t0.bitfield.qword & t1.bitfield.qword)
2015 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2016 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2017 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2018 return 1;
2019
2020 i.error = register_type_mismatch;
2021
2022 return 0;
2023 }
2024
2025 static INLINE unsigned int
2026 register_number (const reg_entry *r)
2027 {
2028 unsigned int nr = r->reg_num;
2029
2030 if (r->reg_flags & RegRex)
2031 nr += 8;
2032
2033 if (r->reg_flags & RegVRex)
2034 nr += 16;
2035
2036 return nr;
2037 }
2038
2039 static INLINE unsigned int
2040 mode_from_disp_size (i386_operand_type t)
2041 {
2042 if (t.bitfield.disp8)
2043 return 1;
2044 else if (t.bitfield.disp16
2045 || t.bitfield.disp32
2046 || t.bitfield.disp32s)
2047 return 2;
2048 else
2049 return 0;
2050 }
2051
2052 static INLINE int
2053 fits_in_signed_byte (addressT num)
2054 {
2055 return num + 0x80 <= 0xff;
2056 }
2057
2058 static INLINE int
2059 fits_in_unsigned_byte (addressT num)
2060 {
2061 return num <= 0xff;
2062 }
2063
2064 static INLINE int
2065 fits_in_unsigned_word (addressT num)
2066 {
2067 return num <= 0xffff;
2068 }
2069
2070 static INLINE int
2071 fits_in_signed_word (addressT num)
2072 {
2073 return num + 0x8000 <= 0xffff;
2074 }
2075
2076 static INLINE int
2077 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2078 {
2079 #ifndef BFD64
2080 return 1;
2081 #else
2082 return num + 0x80000000 <= 0xffffffff;
2083 #endif
2084 } /* fits_in_signed_long() */
2085
2086 static INLINE int
2087 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2088 {
2089 #ifndef BFD64
2090 return 1;
2091 #else
2092 return num <= 0xffffffff;
2093 #endif
2094 } /* fits_in_unsigned_long() */
2095
2096 static INLINE int
2097 fits_in_disp8 (offsetT num)
2098 {
2099 int shift = i.memshift;
2100 unsigned int mask;
2101
2102 if (shift == -1)
2103 abort ();
2104
2105 mask = (1 << shift) - 1;
2106
2107 /* Return 0 if NUM isn't properly aligned. */
2108 if ((num & mask))
2109 return 0;
2110
2111 /* Check if NUM will fit in 8bit after shift. */
2112 return fits_in_signed_byte (num >> shift);
2113 }
2114
2115 static INLINE int
2116 fits_in_imm4 (offsetT num)
2117 {
2118 return (num & 0xf) == num;
2119 }
2120
2121 static i386_operand_type
2122 smallest_imm_type (offsetT num)
2123 {
2124 i386_operand_type t;
2125
2126 operand_type_set (&t, 0);
2127 t.bitfield.imm64 = 1;
2128
2129 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2130 {
2131 /* This code is disabled on the 486 because all the Imm1 forms
2132 in the opcode table are slower on the i486. They're the
2133 versions with the implicitly specified single-position
2134 displacement, which has another syntax if you really want to
2135 use that form. */
2136 t.bitfield.imm1 = 1;
2137 t.bitfield.imm8 = 1;
2138 t.bitfield.imm8s = 1;
2139 t.bitfield.imm16 = 1;
2140 t.bitfield.imm32 = 1;
2141 t.bitfield.imm32s = 1;
2142 }
2143 else if (fits_in_signed_byte (num))
2144 {
2145 t.bitfield.imm8 = 1;
2146 t.bitfield.imm8s = 1;
2147 t.bitfield.imm16 = 1;
2148 t.bitfield.imm32 = 1;
2149 t.bitfield.imm32s = 1;
2150 }
2151 else if (fits_in_unsigned_byte (num))
2152 {
2153 t.bitfield.imm8 = 1;
2154 t.bitfield.imm16 = 1;
2155 t.bitfield.imm32 = 1;
2156 t.bitfield.imm32s = 1;
2157 }
2158 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2159 {
2160 t.bitfield.imm16 = 1;
2161 t.bitfield.imm32 = 1;
2162 t.bitfield.imm32s = 1;
2163 }
2164 else if (fits_in_signed_long (num))
2165 {
2166 t.bitfield.imm32 = 1;
2167 t.bitfield.imm32s = 1;
2168 }
2169 else if (fits_in_unsigned_long (num))
2170 t.bitfield.imm32 = 1;
2171
2172 return t;
2173 }
2174
2175 static offsetT
2176 offset_in_range (offsetT val, int size)
2177 {
2178 addressT mask;
2179
2180 switch (size)
2181 {
2182 case 1: mask = ((addressT) 1 << 8) - 1; break;
2183 case 2: mask = ((addressT) 1 << 16) - 1; break;
2184 case 4: mask = ((addressT) 2 << 31) - 1; break;
2185 #ifdef BFD64
2186 case 8: mask = ((addressT) 2 << 63) - 1; break;
2187 #endif
2188 default: abort ();
2189 }
2190
2191 #ifdef BFD64
2192 /* If BFD64, sign extend val for 32bit address mode. */
2193 if (flag_code != CODE_64BIT
2194 || i.prefix[ADDR_PREFIX])
2195 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2196 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2197 #endif
2198
2199 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2200 {
2201 char buf1[40], buf2[40];
2202
2203 sprint_value (buf1, val);
2204 sprint_value (buf2, val & mask);
2205 as_warn (_("%s shortened to %s"), buf1, buf2);
2206 }
2207 return val & mask;
2208 }
2209
2210 enum PREFIX_GROUP
2211 {
2212 PREFIX_EXIST = 0,
2213 PREFIX_LOCK,
2214 PREFIX_REP,
2215 PREFIX_DS,
2216 PREFIX_OTHER
2217 };
2218
2219 /* Returns
2220 a. PREFIX_EXIST if attempting to add a prefix where one from the
2221 same class already exists.
2222 b. PREFIX_LOCK if lock prefix is added.
2223 c. PREFIX_REP if rep/repne prefix is added.
2224 d. PREFIX_DS if ds prefix is added.
2225 e. PREFIX_OTHER if other prefix is added.
2226 */
2227
2228 static enum PREFIX_GROUP
2229 add_prefix (unsigned int prefix)
2230 {
2231 enum PREFIX_GROUP ret = PREFIX_OTHER;
2232 unsigned int q;
2233
2234 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2235 && flag_code == CODE_64BIT)
2236 {
2237 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2238 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2239 && (prefix & (REX_R | REX_X | REX_B))))
2240 ret = PREFIX_EXIST;
2241 q = REX_PREFIX;
2242 }
2243 else
2244 {
2245 switch (prefix)
2246 {
2247 default:
2248 abort ();
2249
2250 case DS_PREFIX_OPCODE:
2251 ret = PREFIX_DS;
2252 /* Fall through. */
2253 case CS_PREFIX_OPCODE:
2254 case ES_PREFIX_OPCODE:
2255 case FS_PREFIX_OPCODE:
2256 case GS_PREFIX_OPCODE:
2257 case SS_PREFIX_OPCODE:
2258 q = SEG_PREFIX;
2259 break;
2260
2261 case REPNE_PREFIX_OPCODE:
2262 case REPE_PREFIX_OPCODE:
2263 q = REP_PREFIX;
2264 ret = PREFIX_REP;
2265 break;
2266
2267 case LOCK_PREFIX_OPCODE:
2268 q = LOCK_PREFIX;
2269 ret = PREFIX_LOCK;
2270 break;
2271
2272 case FWAIT_OPCODE:
2273 q = WAIT_PREFIX;
2274 break;
2275
2276 case ADDR_PREFIX_OPCODE:
2277 q = ADDR_PREFIX;
2278 break;
2279
2280 case DATA_PREFIX_OPCODE:
2281 q = DATA_PREFIX;
2282 break;
2283 }
2284 if (i.prefix[q] != 0)
2285 ret = PREFIX_EXIST;
2286 }
2287
2288 if (ret)
2289 {
2290 if (!i.prefix[q])
2291 ++i.prefixes;
2292 i.prefix[q] |= prefix;
2293 }
2294 else
2295 as_bad (_("same type of prefix used twice"));
2296
2297 return ret;
2298 }
2299
2300 static void
2301 update_code_flag (int value, int check)
2302 {
2303 PRINTF_LIKE ((*as_error));
2304
2305 flag_code = (enum flag_code) value;
2306 if (flag_code == CODE_64BIT)
2307 {
2308 cpu_arch_flags.bitfield.cpu64 = 1;
2309 cpu_arch_flags.bitfield.cpuno64 = 0;
2310 }
2311 else
2312 {
2313 cpu_arch_flags.bitfield.cpu64 = 0;
2314 cpu_arch_flags.bitfield.cpuno64 = 1;
2315 }
2316 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2317 {
2318 if (check)
2319 as_error = as_fatal;
2320 else
2321 as_error = as_bad;
2322 (*as_error) (_("64bit mode not supported on `%s'."),
2323 cpu_arch_name ? cpu_arch_name : default_arch);
2324 }
2325 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2326 {
2327 if (check)
2328 as_error = as_fatal;
2329 else
2330 as_error = as_bad;
2331 (*as_error) (_("32bit mode not supported on `%s'."),
2332 cpu_arch_name ? cpu_arch_name : default_arch);
2333 }
2334 stackop_size = '\0';
2335 }
2336
2337 static void
2338 set_code_flag (int value)
2339 {
2340 update_code_flag (value, 0);
2341 }
2342
2343 static void
2344 set_16bit_gcc_code_flag (int new_code_flag)
2345 {
2346 flag_code = (enum flag_code) new_code_flag;
2347 if (flag_code != CODE_16BIT)
2348 abort ();
2349 cpu_arch_flags.bitfield.cpu64 = 0;
2350 cpu_arch_flags.bitfield.cpuno64 = 1;
2351 stackop_size = LONG_MNEM_SUFFIX;
2352 }
2353
2354 static void
2355 set_intel_syntax (int syntax_flag)
2356 {
2357 /* Find out if register prefixing is specified. */
2358 int ask_naked_reg = 0;
2359
2360 SKIP_WHITESPACE ();
2361 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2362 {
2363 char *string;
2364 int e = get_symbol_name (&string);
2365
2366 if (strcmp (string, "prefix") == 0)
2367 ask_naked_reg = 1;
2368 else if (strcmp (string, "noprefix") == 0)
2369 ask_naked_reg = -1;
2370 else
2371 as_bad (_("bad argument to syntax directive."));
2372 (void) restore_line_pointer (e);
2373 }
2374 demand_empty_rest_of_line ();
2375
2376 intel_syntax = syntax_flag;
2377
2378 if (ask_naked_reg == 0)
2379 allow_naked_reg = (intel_syntax
2380 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2381 else
2382 allow_naked_reg = (ask_naked_reg < 0);
2383
2384 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2385
2386 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2387 identifier_chars['$'] = intel_syntax ? '$' : 0;
2388 register_prefix = allow_naked_reg ? "" : "%";
2389 }
2390
2391 static void
2392 set_intel_mnemonic (int mnemonic_flag)
2393 {
2394 intel_mnemonic = mnemonic_flag;
2395 }
2396
2397 static void
2398 set_allow_index_reg (int flag)
2399 {
2400 allow_index_reg = flag;
2401 }
2402
2403 static void
2404 set_check (int what)
2405 {
2406 enum check_kind *kind;
2407 const char *str;
2408
2409 if (what)
2410 {
2411 kind = &operand_check;
2412 str = "operand";
2413 }
2414 else
2415 {
2416 kind = &sse_check;
2417 str = "sse";
2418 }
2419
2420 SKIP_WHITESPACE ();
2421
2422 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2423 {
2424 char *string;
2425 int e = get_symbol_name (&string);
2426
2427 if (strcmp (string, "none") == 0)
2428 *kind = check_none;
2429 else if (strcmp (string, "warning") == 0)
2430 *kind = check_warning;
2431 else if (strcmp (string, "error") == 0)
2432 *kind = check_error;
2433 else
2434 as_bad (_("bad argument to %s_check directive."), str);
2435 (void) restore_line_pointer (e);
2436 }
2437 else
2438 as_bad (_("missing argument for %s_check directive"), str);
2439
2440 demand_empty_rest_of_line ();
2441 }
2442
2443 static void
2444 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2445 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2446 {
2447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2448 static const char *arch;
2449
2450 /* Intel LIOM is only supported on ELF. */
2451 if (!IS_ELF)
2452 return;
2453
2454 if (!arch)
2455 {
2456 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2457 use default_arch. */
2458 arch = cpu_arch_name;
2459 if (!arch)
2460 arch = default_arch;
2461 }
2462
2463 /* If we are targeting Intel MCU, we must enable it. */
2464 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2465 || new_flag.bitfield.cpuiamcu)
2466 return;
2467
2468 /* If we are targeting Intel L1OM, we must enable it. */
2469 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2470 || new_flag.bitfield.cpul1om)
2471 return;
2472
2473 /* If we are targeting Intel K1OM, we must enable it. */
2474 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2475 || new_flag.bitfield.cpuk1om)
2476 return;
2477
2478 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2479 #endif
2480 }
2481
2482 static void
2483 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2484 {
2485 SKIP_WHITESPACE ();
2486
2487 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2488 {
2489 char *string;
2490 int e = get_symbol_name (&string);
2491 unsigned int j;
2492 i386_cpu_flags flags;
2493
2494 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2495 {
2496 if (strcmp (string, cpu_arch[j].name) == 0)
2497 {
2498 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2499
2500 if (*string != '.')
2501 {
2502 cpu_arch_name = cpu_arch[j].name;
2503 cpu_sub_arch_name = NULL;
2504 cpu_arch_flags = cpu_arch[j].flags;
2505 if (flag_code == CODE_64BIT)
2506 {
2507 cpu_arch_flags.bitfield.cpu64 = 1;
2508 cpu_arch_flags.bitfield.cpuno64 = 0;
2509 }
2510 else
2511 {
2512 cpu_arch_flags.bitfield.cpu64 = 0;
2513 cpu_arch_flags.bitfield.cpuno64 = 1;
2514 }
2515 cpu_arch_isa = cpu_arch[j].type;
2516 cpu_arch_isa_flags = cpu_arch[j].flags;
2517 if (!cpu_arch_tune_set)
2518 {
2519 cpu_arch_tune = cpu_arch_isa;
2520 cpu_arch_tune_flags = cpu_arch_isa_flags;
2521 }
2522 break;
2523 }
2524
2525 flags = cpu_flags_or (cpu_arch_flags,
2526 cpu_arch[j].flags);
2527
2528 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2529 {
2530 if (cpu_sub_arch_name)
2531 {
2532 char *name = cpu_sub_arch_name;
2533 cpu_sub_arch_name = concat (name,
2534 cpu_arch[j].name,
2535 (const char *) NULL);
2536 free (name);
2537 }
2538 else
2539 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2540 cpu_arch_flags = flags;
2541 cpu_arch_isa_flags = flags;
2542 }
2543 (void) restore_line_pointer (e);
2544 demand_empty_rest_of_line ();
2545 return;
2546 }
2547 }
2548
2549 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2550 {
2551 /* Disable an ISA extension. */
2552 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2553 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2554 {
2555 flags = cpu_flags_and_not (cpu_arch_flags,
2556 cpu_noarch[j].flags);
2557 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2558 {
2559 if (cpu_sub_arch_name)
2560 {
2561 char *name = cpu_sub_arch_name;
2562 cpu_sub_arch_name = concat (name, string,
2563 (const char *) NULL);
2564 free (name);
2565 }
2566 else
2567 cpu_sub_arch_name = xstrdup (string);
2568 cpu_arch_flags = flags;
2569 cpu_arch_isa_flags = flags;
2570 }
2571 (void) restore_line_pointer (e);
2572 demand_empty_rest_of_line ();
2573 return;
2574 }
2575
2576 j = ARRAY_SIZE (cpu_arch);
2577 }
2578
2579 if (j >= ARRAY_SIZE (cpu_arch))
2580 as_bad (_("no such architecture: `%s'"), string);
2581
2582 *input_line_pointer = e;
2583 }
2584 else
2585 as_bad (_("missing cpu architecture"));
2586
2587 no_cond_jump_promotion = 0;
2588 if (*input_line_pointer == ','
2589 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2590 {
2591 char *string;
2592 char e;
2593
2594 ++input_line_pointer;
2595 e = get_symbol_name (&string);
2596
2597 if (strcmp (string, "nojumps") == 0)
2598 no_cond_jump_promotion = 1;
2599 else if (strcmp (string, "jumps") == 0)
2600 ;
2601 else
2602 as_bad (_("no such architecture modifier: `%s'"), string);
2603
2604 (void) restore_line_pointer (e);
2605 }
2606
2607 demand_empty_rest_of_line ();
2608 }
2609
2610 enum bfd_architecture
2611 i386_arch (void)
2612 {
2613 if (cpu_arch_isa == PROCESSOR_L1OM)
2614 {
2615 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2616 || flag_code != CODE_64BIT)
2617 as_fatal (_("Intel L1OM is 64bit ELF only"));
2618 return bfd_arch_l1om;
2619 }
2620 else if (cpu_arch_isa == PROCESSOR_K1OM)
2621 {
2622 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2623 || flag_code != CODE_64BIT)
2624 as_fatal (_("Intel K1OM is 64bit ELF only"));
2625 return bfd_arch_k1om;
2626 }
2627 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2628 {
2629 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2630 || flag_code == CODE_64BIT)
2631 as_fatal (_("Intel MCU is 32bit ELF only"));
2632 return bfd_arch_iamcu;
2633 }
2634 else
2635 return bfd_arch_i386;
2636 }
2637
2638 unsigned long
2639 i386_mach (void)
2640 {
2641 if (!strncmp (default_arch, "x86_64", 6))
2642 {
2643 if (cpu_arch_isa == PROCESSOR_L1OM)
2644 {
2645 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2646 || default_arch[6] != '\0')
2647 as_fatal (_("Intel L1OM is 64bit ELF only"));
2648 return bfd_mach_l1om;
2649 }
2650 else if (cpu_arch_isa == PROCESSOR_K1OM)
2651 {
2652 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2653 || default_arch[6] != '\0')
2654 as_fatal (_("Intel K1OM is 64bit ELF only"));
2655 return bfd_mach_k1om;
2656 }
2657 else if (default_arch[6] == '\0')
2658 return bfd_mach_x86_64;
2659 else
2660 return bfd_mach_x64_32;
2661 }
2662 else if (!strcmp (default_arch, "i386")
2663 || !strcmp (default_arch, "iamcu"))
2664 {
2665 if (cpu_arch_isa == PROCESSOR_IAMCU)
2666 {
2667 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2668 as_fatal (_("Intel MCU is 32bit ELF only"));
2669 return bfd_mach_i386_iamcu;
2670 }
2671 else
2672 return bfd_mach_i386_i386;
2673 }
2674 else
2675 as_fatal (_("unknown architecture"));
2676 }
2677 \f
2678 void
2679 md_begin (void)
2680 {
2681 const char *hash_err;
2682
2683 /* Support pseudo prefixes like {disp32}. */
2684 lex_type ['{'] = LEX_BEGIN_NAME;
2685
2686 /* Initialize op_hash hash table. */
2687 op_hash = hash_new ();
2688
2689 {
2690 const insn_template *optab;
2691 templates *core_optab;
2692
2693 /* Setup for loop. */
2694 optab = i386_optab;
2695 core_optab = XNEW (templates);
2696 core_optab->start = optab;
2697
2698 while (1)
2699 {
2700 ++optab;
2701 if (optab->name == NULL
2702 || strcmp (optab->name, (optab - 1)->name) != 0)
2703 {
2704 /* different name --> ship out current template list;
2705 add to hash table; & begin anew. */
2706 core_optab->end = optab;
2707 hash_err = hash_insert (op_hash,
2708 (optab - 1)->name,
2709 (void *) core_optab);
2710 if (hash_err)
2711 {
2712 as_fatal (_("can't hash %s: %s"),
2713 (optab - 1)->name,
2714 hash_err);
2715 }
2716 if (optab->name == NULL)
2717 break;
2718 core_optab = XNEW (templates);
2719 core_optab->start = optab;
2720 }
2721 }
2722 }
2723
2724 /* Initialize reg_hash hash table. */
2725 reg_hash = hash_new ();
2726 {
2727 const reg_entry *regtab;
2728 unsigned int regtab_size = i386_regtab_size;
2729
2730 for (regtab = i386_regtab; regtab_size--; regtab++)
2731 {
2732 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2733 if (hash_err)
2734 as_fatal (_("can't hash %s: %s"),
2735 regtab->reg_name,
2736 hash_err);
2737 }
2738 }
2739
2740 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2741 {
2742 int c;
2743 char *p;
2744
2745 for (c = 0; c < 256; c++)
2746 {
2747 if (ISDIGIT (c))
2748 {
2749 digit_chars[c] = c;
2750 mnemonic_chars[c] = c;
2751 register_chars[c] = c;
2752 operand_chars[c] = c;
2753 }
2754 else if (ISLOWER (c))
2755 {
2756 mnemonic_chars[c] = c;
2757 register_chars[c] = c;
2758 operand_chars[c] = c;
2759 }
2760 else if (ISUPPER (c))
2761 {
2762 mnemonic_chars[c] = TOLOWER (c);
2763 register_chars[c] = mnemonic_chars[c];
2764 operand_chars[c] = c;
2765 }
2766 else if (c == '{' || c == '}')
2767 {
2768 mnemonic_chars[c] = c;
2769 operand_chars[c] = c;
2770 }
2771
2772 if (ISALPHA (c) || ISDIGIT (c))
2773 identifier_chars[c] = c;
2774 else if (c >= 128)
2775 {
2776 identifier_chars[c] = c;
2777 operand_chars[c] = c;
2778 }
2779 }
2780
2781 #ifdef LEX_AT
2782 identifier_chars['@'] = '@';
2783 #endif
2784 #ifdef LEX_QM
2785 identifier_chars['?'] = '?';
2786 operand_chars['?'] = '?';
2787 #endif
2788 digit_chars['-'] = '-';
2789 mnemonic_chars['_'] = '_';
2790 mnemonic_chars['-'] = '-';
2791 mnemonic_chars['.'] = '.';
2792 identifier_chars['_'] = '_';
2793 identifier_chars['.'] = '.';
2794
2795 for (p = operand_special_chars; *p != '\0'; p++)
2796 operand_chars[(unsigned char) *p] = *p;
2797 }
2798
2799 if (flag_code == CODE_64BIT)
2800 {
2801 #if defined (OBJ_COFF) && defined (TE_PE)
2802 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2803 ? 32 : 16);
2804 #else
2805 x86_dwarf2_return_column = 16;
2806 #endif
2807 x86_cie_data_alignment = -8;
2808 }
2809 else
2810 {
2811 x86_dwarf2_return_column = 8;
2812 x86_cie_data_alignment = -4;
2813 }
2814 }
2815
2816 void
2817 i386_print_statistics (FILE *file)
2818 {
2819 hash_print_statistics (file, "i386 opcode", op_hash);
2820 hash_print_statistics (file, "i386 register", reg_hash);
2821 }
2822 \f
2823 #ifdef DEBUG386
2824
2825 /* Debugging routines for md_assemble. */
2826 static void pte (insn_template *);
2827 static void pt (i386_operand_type);
2828 static void pe (expressionS *);
2829 static void ps (symbolS *);
2830
2831 static void
2832 pi (char *line, i386_insn *x)
2833 {
2834 unsigned int j;
2835
2836 fprintf (stdout, "%s: template ", line);
2837 pte (&x->tm);
2838 fprintf (stdout, " address: base %s index %s scale %x\n",
2839 x->base_reg ? x->base_reg->reg_name : "none",
2840 x->index_reg ? x->index_reg->reg_name : "none",
2841 x->log2_scale_factor);
2842 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2843 x->rm.mode, x->rm.reg, x->rm.regmem);
2844 fprintf (stdout, " sib: base %x index %x scale %x\n",
2845 x->sib.base, x->sib.index, x->sib.scale);
2846 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2847 (x->rex & REX_W) != 0,
2848 (x->rex & REX_R) != 0,
2849 (x->rex & REX_X) != 0,
2850 (x->rex & REX_B) != 0);
2851 for (j = 0; j < x->operands; j++)
2852 {
2853 fprintf (stdout, " #%d: ", j + 1);
2854 pt (x->types[j]);
2855 fprintf (stdout, "\n");
2856 if (x->types[j].bitfield.reg
2857 || x->types[j].bitfield.regmmx
2858 || x->types[j].bitfield.regsimd
2859 || x->types[j].bitfield.sreg2
2860 || x->types[j].bitfield.sreg3
2861 || x->types[j].bitfield.control
2862 || x->types[j].bitfield.debug
2863 || x->types[j].bitfield.test)
2864 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2865 if (operand_type_check (x->types[j], imm))
2866 pe (x->op[j].imms);
2867 if (operand_type_check (x->types[j], disp))
2868 pe (x->op[j].disps);
2869 }
2870 }
2871
2872 static void
2873 pte (insn_template *t)
2874 {
2875 unsigned int j;
2876 fprintf (stdout, " %d operands ", t->operands);
2877 fprintf (stdout, "opcode %x ", t->base_opcode);
2878 if (t->extension_opcode != None)
2879 fprintf (stdout, "ext %x ", t->extension_opcode);
2880 if (t->opcode_modifier.d)
2881 fprintf (stdout, "D");
2882 if (t->opcode_modifier.w)
2883 fprintf (stdout, "W");
2884 fprintf (stdout, "\n");
2885 for (j = 0; j < t->operands; j++)
2886 {
2887 fprintf (stdout, " #%d type ", j + 1);
2888 pt (t->operand_types[j]);
2889 fprintf (stdout, "\n");
2890 }
2891 }
2892
2893 static void
2894 pe (expressionS *e)
2895 {
2896 fprintf (stdout, " operation %d\n", e->X_op);
2897 fprintf (stdout, " add_number %ld (%lx)\n",
2898 (long) e->X_add_number, (long) e->X_add_number);
2899 if (e->X_add_symbol)
2900 {
2901 fprintf (stdout, " add_symbol ");
2902 ps (e->X_add_symbol);
2903 fprintf (stdout, "\n");
2904 }
2905 if (e->X_op_symbol)
2906 {
2907 fprintf (stdout, " op_symbol ");
2908 ps (e->X_op_symbol);
2909 fprintf (stdout, "\n");
2910 }
2911 }
2912
2913 static void
2914 ps (symbolS *s)
2915 {
2916 fprintf (stdout, "%s type %s%s",
2917 S_GET_NAME (s),
2918 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2919 segment_name (S_GET_SEGMENT (s)));
2920 }
2921
2922 static struct type_name
2923 {
2924 i386_operand_type mask;
2925 const char *name;
2926 }
2927 const type_names[] =
2928 {
2929 { OPERAND_TYPE_REG8, "r8" },
2930 { OPERAND_TYPE_REG16, "r16" },
2931 { OPERAND_TYPE_REG32, "r32" },
2932 { OPERAND_TYPE_REG64, "r64" },
2933 { OPERAND_TYPE_IMM8, "i8" },
2934 { OPERAND_TYPE_IMM8, "i8s" },
2935 { OPERAND_TYPE_IMM16, "i16" },
2936 { OPERAND_TYPE_IMM32, "i32" },
2937 { OPERAND_TYPE_IMM32S, "i32s" },
2938 { OPERAND_TYPE_IMM64, "i64" },
2939 { OPERAND_TYPE_IMM1, "i1" },
2940 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2941 { OPERAND_TYPE_DISP8, "d8" },
2942 { OPERAND_TYPE_DISP16, "d16" },
2943 { OPERAND_TYPE_DISP32, "d32" },
2944 { OPERAND_TYPE_DISP32S, "d32s" },
2945 { OPERAND_TYPE_DISP64, "d64" },
2946 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2947 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2948 { OPERAND_TYPE_CONTROL, "control reg" },
2949 { OPERAND_TYPE_TEST, "test reg" },
2950 { OPERAND_TYPE_DEBUG, "debug reg" },
2951 { OPERAND_TYPE_FLOATREG, "FReg" },
2952 { OPERAND_TYPE_FLOATACC, "FAcc" },
2953 { OPERAND_TYPE_SREG2, "SReg2" },
2954 { OPERAND_TYPE_SREG3, "SReg3" },
2955 { OPERAND_TYPE_ACC, "Acc" },
2956 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2957 { OPERAND_TYPE_REGMMX, "rMMX" },
2958 { OPERAND_TYPE_REGXMM, "rXMM" },
2959 { OPERAND_TYPE_REGYMM, "rYMM" },
2960 { OPERAND_TYPE_REGZMM, "rZMM" },
2961 { OPERAND_TYPE_REGMASK, "Mask reg" },
2962 { OPERAND_TYPE_ESSEG, "es" },
2963 };
2964
2965 static void
2966 pt (i386_operand_type t)
2967 {
2968 unsigned int j;
2969 i386_operand_type a;
2970
2971 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2972 {
2973 a = operand_type_and (t, type_names[j].mask);
2974 if (!operand_type_all_zero (&a))
2975 fprintf (stdout, "%s, ", type_names[j].name);
2976 }
2977 fflush (stdout);
2978 }
2979
2980 #endif /* DEBUG386 */
2981 \f
2982 static bfd_reloc_code_real_type
2983 reloc (unsigned int size,
2984 int pcrel,
2985 int sign,
2986 bfd_reloc_code_real_type other)
2987 {
2988 if (other != NO_RELOC)
2989 {
2990 reloc_howto_type *rel;
2991
2992 if (size == 8)
2993 switch (other)
2994 {
2995 case BFD_RELOC_X86_64_GOT32:
2996 return BFD_RELOC_X86_64_GOT64;
2997 break;
2998 case BFD_RELOC_X86_64_GOTPLT64:
2999 return BFD_RELOC_X86_64_GOTPLT64;
3000 break;
3001 case BFD_RELOC_X86_64_PLTOFF64:
3002 return BFD_RELOC_X86_64_PLTOFF64;
3003 break;
3004 case BFD_RELOC_X86_64_GOTPC32:
3005 other = BFD_RELOC_X86_64_GOTPC64;
3006 break;
3007 case BFD_RELOC_X86_64_GOTPCREL:
3008 other = BFD_RELOC_X86_64_GOTPCREL64;
3009 break;
3010 case BFD_RELOC_X86_64_TPOFF32:
3011 other = BFD_RELOC_X86_64_TPOFF64;
3012 break;
3013 case BFD_RELOC_X86_64_DTPOFF32:
3014 other = BFD_RELOC_X86_64_DTPOFF64;
3015 break;
3016 default:
3017 break;
3018 }
3019
3020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3021 if (other == BFD_RELOC_SIZE32)
3022 {
3023 if (size == 8)
3024 other = BFD_RELOC_SIZE64;
3025 if (pcrel)
3026 {
3027 as_bad (_("there are no pc-relative size relocations"));
3028 return NO_RELOC;
3029 }
3030 }
3031 #endif
3032
3033 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3034 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3035 sign = -1;
3036
3037 rel = bfd_reloc_type_lookup (stdoutput, other);
3038 if (!rel)
3039 as_bad (_("unknown relocation (%u)"), other);
3040 else if (size != bfd_get_reloc_size (rel))
3041 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3042 bfd_get_reloc_size (rel),
3043 size);
3044 else if (pcrel && !rel->pc_relative)
3045 as_bad (_("non-pc-relative relocation for pc-relative field"));
3046 else if ((rel->complain_on_overflow == complain_overflow_signed
3047 && !sign)
3048 || (rel->complain_on_overflow == complain_overflow_unsigned
3049 && sign > 0))
3050 as_bad (_("relocated field and relocation type differ in signedness"));
3051 else
3052 return other;
3053 return NO_RELOC;
3054 }
3055
3056 if (pcrel)
3057 {
3058 if (!sign)
3059 as_bad (_("there are no unsigned pc-relative relocations"));
3060 switch (size)
3061 {
3062 case 1: return BFD_RELOC_8_PCREL;
3063 case 2: return BFD_RELOC_16_PCREL;
3064 case 4: return BFD_RELOC_32_PCREL;
3065 case 8: return BFD_RELOC_64_PCREL;
3066 }
3067 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3068 }
3069 else
3070 {
3071 if (sign > 0)
3072 switch (size)
3073 {
3074 case 4: return BFD_RELOC_X86_64_32S;
3075 }
3076 else
3077 switch (size)
3078 {
3079 case 1: return BFD_RELOC_8;
3080 case 2: return BFD_RELOC_16;
3081 case 4: return BFD_RELOC_32;
3082 case 8: return BFD_RELOC_64;
3083 }
3084 as_bad (_("cannot do %s %u byte relocation"),
3085 sign > 0 ? "signed" : "unsigned", size);
3086 }
3087
3088 return NO_RELOC;
3089 }
3090
3091 /* Here we decide which fixups can be adjusted to make them relative to
3092 the beginning of the section instead of the symbol. Basically we need
3093 to make sure that the dynamic relocations are done correctly, so in
3094 some cases we force the original symbol to be used. */
3095
3096 int
3097 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3098 {
3099 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3100 if (!IS_ELF)
3101 return 1;
3102
3103 /* Don't adjust pc-relative references to merge sections in 64-bit
3104 mode. */
3105 if (use_rela_relocations
3106 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3107 && fixP->fx_pcrel)
3108 return 0;
3109
3110 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3111 and changed later by validate_fix. */
3112 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3113 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3114 return 0;
3115
3116 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3117 for size relocations. */
3118 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3119 || fixP->fx_r_type == BFD_RELOC_SIZE64
3120 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3121 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3122 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3123 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3124 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3125 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3126 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3127 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3128 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3129 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3130 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3131 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3132 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3133 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3134 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3135 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3136 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3137 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3138 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3139 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3140 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3141 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3142 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3143 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3144 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3145 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3146 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3147 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3148 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3149 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3150 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3151 return 0;
3152 #endif
3153 return 1;
3154 }
3155
3156 static int
3157 intel_float_operand (const char *mnemonic)
3158 {
3159 /* Note that the value returned is meaningful only for opcodes with (memory)
3160 operands, hence the code here is free to improperly handle opcodes that
3161 have no operands (for better performance and smaller code). */
3162
3163 if (mnemonic[0] != 'f')
3164 return 0; /* non-math */
3165
3166 switch (mnemonic[1])
3167 {
3168 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3169 the fs segment override prefix not currently handled because no
3170 call path can make opcodes without operands get here */
3171 case 'i':
3172 return 2 /* integer op */;
3173 case 'l':
3174 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3175 return 3; /* fldcw/fldenv */
3176 break;
3177 case 'n':
3178 if (mnemonic[2] != 'o' /* fnop */)
3179 return 3; /* non-waiting control op */
3180 break;
3181 case 'r':
3182 if (mnemonic[2] == 's')
3183 return 3; /* frstor/frstpm */
3184 break;
3185 case 's':
3186 if (mnemonic[2] == 'a')
3187 return 3; /* fsave */
3188 if (mnemonic[2] == 't')
3189 {
3190 switch (mnemonic[3])
3191 {
3192 case 'c': /* fstcw */
3193 case 'd': /* fstdw */
3194 case 'e': /* fstenv */
3195 case 's': /* fsts[gw] */
3196 return 3;
3197 }
3198 }
3199 break;
3200 case 'x':
3201 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3202 return 0; /* fxsave/fxrstor are not really math ops */
3203 break;
3204 }
3205
3206 return 1;
3207 }
3208
3209 /* Build the VEX prefix. */
3210
3211 static void
3212 build_vex_prefix (const insn_template *t)
3213 {
3214 unsigned int register_specifier;
3215 unsigned int implied_prefix;
3216 unsigned int vector_length;
3217
3218 /* Check register specifier. */
3219 if (i.vex.register_specifier)
3220 {
3221 register_specifier =
3222 ~register_number (i.vex.register_specifier) & 0xf;
3223 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3224 }
3225 else
3226 register_specifier = 0xf;
3227
3228 /* Use 2-byte VEX prefix by swapping destination and source
3229 operand. */
3230 if (i.vec_encoding != vex_encoding_vex3
3231 && i.dir_encoding == dir_encoding_default
3232 && i.operands == i.reg_operands
3233 && i.tm.opcode_modifier.vexopcode == VEX0F
3234 && i.tm.opcode_modifier.load
3235 && i.rex == REX_B)
3236 {
3237 unsigned int xchg = i.operands - 1;
3238 union i386_op temp_op;
3239 i386_operand_type temp_type;
3240
3241 temp_type = i.types[xchg];
3242 i.types[xchg] = i.types[0];
3243 i.types[0] = temp_type;
3244 temp_op = i.op[xchg];
3245 i.op[xchg] = i.op[0];
3246 i.op[0] = temp_op;
3247
3248 gas_assert (i.rm.mode == 3);
3249
3250 i.rex = REX_R;
3251 xchg = i.rm.regmem;
3252 i.rm.regmem = i.rm.reg;
3253 i.rm.reg = xchg;
3254
3255 /* Use the next insn. */
3256 i.tm = t[1];
3257 }
3258
3259 if (i.tm.opcode_modifier.vex == VEXScalar)
3260 vector_length = avxscalar;
3261 else if (i.tm.opcode_modifier.vex == VEX256)
3262 vector_length = 1;
3263 else
3264 {
3265 unsigned int op;
3266
3267 vector_length = 0;
3268 for (op = 0; op < t->operands; ++op)
3269 if (t->operand_types[op].bitfield.xmmword
3270 && t->operand_types[op].bitfield.ymmword
3271 && i.types[op].bitfield.ymmword)
3272 {
3273 vector_length = 1;
3274 break;
3275 }
3276 }
3277
3278 switch ((i.tm.base_opcode >> 8) & 0xff)
3279 {
3280 case 0:
3281 implied_prefix = 0;
3282 break;
3283 case DATA_PREFIX_OPCODE:
3284 implied_prefix = 1;
3285 break;
3286 case REPE_PREFIX_OPCODE:
3287 implied_prefix = 2;
3288 break;
3289 case REPNE_PREFIX_OPCODE:
3290 implied_prefix = 3;
3291 break;
3292 default:
3293 abort ();
3294 }
3295
3296 /* Use 2-byte VEX prefix if possible. */
3297 if (i.vec_encoding != vex_encoding_vex3
3298 && i.tm.opcode_modifier.vexopcode == VEX0F
3299 && i.tm.opcode_modifier.vexw != VEXW1
3300 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3301 {
3302 /* 2-byte VEX prefix. */
3303 unsigned int r;
3304
3305 i.vex.length = 2;
3306 i.vex.bytes[0] = 0xc5;
3307
3308 /* Check the REX.R bit. */
3309 r = (i.rex & REX_R) ? 0 : 1;
3310 i.vex.bytes[1] = (r << 7
3311 | register_specifier << 3
3312 | vector_length << 2
3313 | implied_prefix);
3314 }
3315 else
3316 {
3317 /* 3-byte VEX prefix. */
3318 unsigned int m, w;
3319
3320 i.vex.length = 3;
3321
3322 switch (i.tm.opcode_modifier.vexopcode)
3323 {
3324 case VEX0F:
3325 m = 0x1;
3326 i.vex.bytes[0] = 0xc4;
3327 break;
3328 case VEX0F38:
3329 m = 0x2;
3330 i.vex.bytes[0] = 0xc4;
3331 break;
3332 case VEX0F3A:
3333 m = 0x3;
3334 i.vex.bytes[0] = 0xc4;
3335 break;
3336 case XOP08:
3337 m = 0x8;
3338 i.vex.bytes[0] = 0x8f;
3339 break;
3340 case XOP09:
3341 m = 0x9;
3342 i.vex.bytes[0] = 0x8f;
3343 break;
3344 case XOP0A:
3345 m = 0xa;
3346 i.vex.bytes[0] = 0x8f;
3347 break;
3348 default:
3349 abort ();
3350 }
3351
3352 /* The high 3 bits of the second VEX byte are 1's compliment
3353 of RXB bits from REX. */
3354 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3355
3356 /* Check the REX.W bit. */
3357 w = (i.rex & REX_W) ? 1 : 0;
3358 if (i.tm.opcode_modifier.vexw == VEXW1)
3359 w = 1;
3360
3361 i.vex.bytes[2] = (w << 7
3362 | register_specifier << 3
3363 | vector_length << 2
3364 | implied_prefix);
3365 }
3366 }
3367
3368 /* Build the EVEX prefix. */
3369
3370 static void
3371 build_evex_prefix (void)
3372 {
3373 unsigned int register_specifier;
3374 unsigned int implied_prefix;
3375 unsigned int m, w;
3376 rex_byte vrex_used = 0;
3377
3378 /* Check register specifier. */
3379 if (i.vex.register_specifier)
3380 {
3381 gas_assert ((i.vrex & REX_X) == 0);
3382
3383 register_specifier = i.vex.register_specifier->reg_num;
3384 if ((i.vex.register_specifier->reg_flags & RegRex))
3385 register_specifier += 8;
3386 /* The upper 16 registers are encoded in the fourth byte of the
3387 EVEX prefix. */
3388 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3389 i.vex.bytes[3] = 0x8;
3390 register_specifier = ~register_specifier & 0xf;
3391 }
3392 else
3393 {
3394 register_specifier = 0xf;
3395
3396 /* Encode upper 16 vector index register in the fourth byte of
3397 the EVEX prefix. */
3398 if (!(i.vrex & REX_X))
3399 i.vex.bytes[3] = 0x8;
3400 else
3401 vrex_used |= REX_X;
3402 }
3403
3404 switch ((i.tm.base_opcode >> 8) & 0xff)
3405 {
3406 case 0:
3407 implied_prefix = 0;
3408 break;
3409 case DATA_PREFIX_OPCODE:
3410 implied_prefix = 1;
3411 break;
3412 case REPE_PREFIX_OPCODE:
3413 implied_prefix = 2;
3414 break;
3415 case REPNE_PREFIX_OPCODE:
3416 implied_prefix = 3;
3417 break;
3418 default:
3419 abort ();
3420 }
3421
3422 /* 4 byte EVEX prefix. */
3423 i.vex.length = 4;
3424 i.vex.bytes[0] = 0x62;
3425
3426 /* mmmm bits. */
3427 switch (i.tm.opcode_modifier.vexopcode)
3428 {
3429 case VEX0F:
3430 m = 1;
3431 break;
3432 case VEX0F38:
3433 m = 2;
3434 break;
3435 case VEX0F3A:
3436 m = 3;
3437 break;
3438 default:
3439 abort ();
3440 break;
3441 }
3442
3443 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3444 bits from REX. */
3445 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3446
3447 /* The fifth bit of the second EVEX byte is 1's compliment of the
3448 REX_R bit in VREX. */
3449 if (!(i.vrex & REX_R))
3450 i.vex.bytes[1] |= 0x10;
3451 else
3452 vrex_used |= REX_R;
3453
3454 if ((i.reg_operands + i.imm_operands) == i.operands)
3455 {
3456 /* When all operands are registers, the REX_X bit in REX is not
3457 used. We reuse it to encode the upper 16 registers, which is
3458 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3459 as 1's compliment. */
3460 if ((i.vrex & REX_B))
3461 {
3462 vrex_used |= REX_B;
3463 i.vex.bytes[1] &= ~0x40;
3464 }
3465 }
3466
3467 /* EVEX instructions shouldn't need the REX prefix. */
3468 i.vrex &= ~vrex_used;
3469 gas_assert (i.vrex == 0);
3470
3471 /* Check the REX.W bit. */
3472 w = (i.rex & REX_W) ? 1 : 0;
3473 if (i.tm.opcode_modifier.vexw)
3474 {
3475 if (i.tm.opcode_modifier.vexw == VEXW1)
3476 w = 1;
3477 }
3478 /* If w is not set it means we are dealing with WIG instruction. */
3479 else if (!w)
3480 {
3481 if (evexwig == evexw1)
3482 w = 1;
3483 }
3484
3485 /* Encode the U bit. */
3486 implied_prefix |= 0x4;
3487
3488 /* The third byte of the EVEX prefix. */
3489 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3490
3491 /* The fourth byte of the EVEX prefix. */
3492 /* The zeroing-masking bit. */
3493 if (i.mask && i.mask->zeroing)
3494 i.vex.bytes[3] |= 0x80;
3495
3496 /* Don't always set the broadcast bit if there is no RC. */
3497 if (!i.rounding)
3498 {
3499 /* Encode the vector length. */
3500 unsigned int vec_length;
3501
3502 switch (i.tm.opcode_modifier.evex)
3503 {
3504 case EVEXLIG: /* LL' is ignored */
3505 vec_length = evexlig << 5;
3506 break;
3507 case EVEX128:
3508 vec_length = 0 << 5;
3509 break;
3510 case EVEX256:
3511 vec_length = 1 << 5;
3512 break;
3513 case EVEX512:
3514 vec_length = 2 << 5;
3515 break;
3516 default:
3517 abort ();
3518 break;
3519 }
3520 i.vex.bytes[3] |= vec_length;
3521 /* Encode the broadcast bit. */
3522 if (i.broadcast)
3523 i.vex.bytes[3] |= 0x10;
3524 }
3525 else
3526 {
3527 if (i.rounding->type != saeonly)
3528 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3529 else
3530 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3531 }
3532
3533 if (i.mask && i.mask->mask)
3534 i.vex.bytes[3] |= i.mask->mask->reg_num;
3535 }
3536
3537 static void
3538 process_immext (void)
3539 {
3540 expressionS *exp;
3541
3542 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3543 && i.operands > 0)
3544 {
3545 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3546 with an opcode suffix which is coded in the same place as an
3547 8-bit immediate field would be.
3548 Here we check those operands and remove them afterwards. */
3549 unsigned int x;
3550
3551 for (x = 0; x < i.operands; x++)
3552 if (register_number (i.op[x].regs) != x)
3553 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3554 register_prefix, i.op[x].regs->reg_name, x + 1,
3555 i.tm.name);
3556
3557 i.operands = 0;
3558 }
3559
3560 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3561 {
3562 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3563 suffix which is coded in the same place as an 8-bit immediate
3564 field would be.
3565 Here we check those operands and remove them afterwards. */
3566 unsigned int x;
3567
3568 if (i.operands != 3)
3569 abort();
3570
3571 for (x = 0; x < 2; x++)
3572 if (register_number (i.op[x].regs) != x)
3573 goto bad_register_operand;
3574
3575 /* Check for third operand for mwaitx/monitorx insn. */
3576 if (register_number (i.op[x].regs)
3577 != (x + (i.tm.extension_opcode == 0xfb)))
3578 {
3579 bad_register_operand:
3580 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3581 register_prefix, i.op[x].regs->reg_name, x+1,
3582 i.tm.name);
3583 }
3584
3585 i.operands = 0;
3586 }
3587
3588 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3589 which is coded in the same place as an 8-bit immediate field
3590 would be. Here we fake an 8-bit immediate operand from the
3591 opcode suffix stored in tm.extension_opcode.
3592
3593 AVX instructions also use this encoding, for some of
3594 3 argument instructions. */
3595
3596 gas_assert (i.imm_operands <= 1
3597 && (i.operands <= 2
3598 || ((i.tm.opcode_modifier.vex
3599 || i.tm.opcode_modifier.evex)
3600 && i.operands <= 4)));
3601
3602 exp = &im_expressions[i.imm_operands++];
3603 i.op[i.operands].imms = exp;
3604 i.types[i.operands] = imm8;
3605 i.operands++;
3606 exp->X_op = O_constant;
3607 exp->X_add_number = i.tm.extension_opcode;
3608 i.tm.extension_opcode = None;
3609 }
3610
3611
3612 static int
3613 check_hle (void)
3614 {
3615 switch (i.tm.opcode_modifier.hleprefixok)
3616 {
3617 default:
3618 abort ();
3619 case HLEPrefixNone:
3620 as_bad (_("invalid instruction `%s' after `%s'"),
3621 i.tm.name, i.hle_prefix);
3622 return 0;
3623 case HLEPrefixLock:
3624 if (i.prefix[LOCK_PREFIX])
3625 return 1;
3626 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3627 return 0;
3628 case HLEPrefixAny:
3629 return 1;
3630 case HLEPrefixRelease:
3631 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3632 {
3633 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3634 i.tm.name);
3635 return 0;
3636 }
3637 if (i.mem_operands == 0
3638 || !operand_type_check (i.types[i.operands - 1], anymem))
3639 {
3640 as_bad (_("memory destination needed for instruction `%s'"
3641 " after `xrelease'"), i.tm.name);
3642 return 0;
3643 }
3644 return 1;
3645 }
3646 }
3647
3648 /* This is the guts of the machine-dependent assembler. LINE points to a
3649 machine dependent instruction. This function is supposed to emit
3650 the frags/bytes it assembles to. */
3651
3652 void
3653 md_assemble (char *line)
3654 {
3655 unsigned int j;
3656 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3657 const insn_template *t;
3658
3659 /* Initialize globals. */
3660 memset (&i, '\0', sizeof (i));
3661 for (j = 0; j < MAX_OPERANDS; j++)
3662 i.reloc[j] = NO_RELOC;
3663 memset (disp_expressions, '\0', sizeof (disp_expressions));
3664 memset (im_expressions, '\0', sizeof (im_expressions));
3665 save_stack_p = save_stack;
3666
3667 /* First parse an instruction mnemonic & call i386_operand for the operands.
3668 We assume that the scrubber has arranged it so that line[0] is the valid
3669 start of a (possibly prefixed) mnemonic. */
3670
3671 line = parse_insn (line, mnemonic);
3672 if (line == NULL)
3673 return;
3674 mnem_suffix = i.suffix;
3675
3676 line = parse_operands (line, mnemonic);
3677 this_operand = -1;
3678 xfree (i.memop1_string);
3679 i.memop1_string = NULL;
3680 if (line == NULL)
3681 return;
3682
3683 /* Now we've parsed the mnemonic into a set of templates, and have the
3684 operands at hand. */
3685
3686 /* All intel opcodes have reversed operands except for "bound" and
3687 "enter". We also don't reverse intersegment "jmp" and "call"
3688 instructions with 2 immediate operands so that the immediate segment
3689 precedes the offset, as it does when in AT&T mode. */
3690 if (intel_syntax
3691 && i.operands > 1
3692 && (strcmp (mnemonic, "bound") != 0)
3693 && (strcmp (mnemonic, "invlpga") != 0)
3694 && !(operand_type_check (i.types[0], imm)
3695 && operand_type_check (i.types[1], imm)))
3696 swap_operands ();
3697
3698 /* The order of the immediates should be reversed
3699 for 2 immediates extrq and insertq instructions */
3700 if (i.imm_operands == 2
3701 && (strcmp (mnemonic, "extrq") == 0
3702 || strcmp (mnemonic, "insertq") == 0))
3703 swap_2_operands (0, 1);
3704
3705 if (i.imm_operands)
3706 optimize_imm ();
3707
3708 /* Don't optimize displacement for movabs since it only takes 64bit
3709 displacement. */
3710 if (i.disp_operands
3711 && i.disp_encoding != disp_encoding_32bit
3712 && (flag_code != CODE_64BIT
3713 || strcmp (mnemonic, "movabs") != 0))
3714 optimize_disp ();
3715
3716 /* Next, we find a template that matches the given insn,
3717 making sure the overlap of the given operands types is consistent
3718 with the template operand types. */
3719
3720 if (!(t = match_template (mnem_suffix)))
3721 return;
3722
3723 if (sse_check != check_none
3724 && !i.tm.opcode_modifier.noavx
3725 && (i.tm.cpu_flags.bitfield.cpusse
3726 || i.tm.cpu_flags.bitfield.cpusse2
3727 || i.tm.cpu_flags.bitfield.cpusse3
3728 || i.tm.cpu_flags.bitfield.cpussse3
3729 || i.tm.cpu_flags.bitfield.cpusse4_1
3730 || i.tm.cpu_flags.bitfield.cpusse4_2))
3731 {
3732 (sse_check == check_warning
3733 ? as_warn
3734 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3735 }
3736
3737 /* Zap movzx and movsx suffix. The suffix has been set from
3738 "word ptr" or "byte ptr" on the source operand in Intel syntax
3739 or extracted from mnemonic in AT&T syntax. But we'll use
3740 the destination register to choose the suffix for encoding. */
3741 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3742 {
3743 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3744 there is no suffix, the default will be byte extension. */
3745 if (i.reg_operands != 2
3746 && !i.suffix
3747 && intel_syntax)
3748 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3749
3750 i.suffix = 0;
3751 }
3752
3753 if (i.tm.opcode_modifier.fwait)
3754 if (!add_prefix (FWAIT_OPCODE))
3755 return;
3756
3757 /* Check if REP prefix is OK. */
3758 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3759 {
3760 as_bad (_("invalid instruction `%s' after `%s'"),
3761 i.tm.name, i.rep_prefix);
3762 return;
3763 }
3764
3765 /* Check for lock without a lockable instruction. Destination operand
3766 must be memory unless it is xchg (0x86). */
3767 if (i.prefix[LOCK_PREFIX]
3768 && (!i.tm.opcode_modifier.islockable
3769 || i.mem_operands == 0
3770 || (i.tm.base_opcode != 0x86
3771 && !operand_type_check (i.types[i.operands - 1], anymem))))
3772 {
3773 as_bad (_("expecting lockable instruction after `lock'"));
3774 return;
3775 }
3776
3777 /* Check if HLE prefix is OK. */
3778 if (i.hle_prefix && !check_hle ())
3779 return;
3780
3781 /* Check BND prefix. */
3782 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3783 as_bad (_("expecting valid branch instruction after `bnd'"));
3784
3785 /* Check NOTRACK prefix. */
3786 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3787 as_bad (_("expecting indirect branch instruction after `notrack'"));
3788
3789 if (i.tm.cpu_flags.bitfield.cpumpx)
3790 {
3791 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3792 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3793 else if (flag_code != CODE_16BIT
3794 ? i.prefix[ADDR_PREFIX]
3795 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3796 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3797 }
3798
3799 /* Insert BND prefix. */
3800 if (add_bnd_prefix
3801 && i.tm.opcode_modifier.bndprefixok
3802 && !i.prefix[BND_PREFIX])
3803 add_prefix (BND_PREFIX_OPCODE);
3804
3805 /* Check string instruction segment overrides. */
3806 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3807 {
3808 if (!check_string ())
3809 return;
3810 i.disp_operands = 0;
3811 }
3812
3813 if (!process_suffix ())
3814 return;
3815
3816 /* Update operand types. */
3817 for (j = 0; j < i.operands; j++)
3818 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3819
3820 /* Make still unresolved immediate matches conform to size of immediate
3821 given in i.suffix. */
3822 if (!finalize_imm ())
3823 return;
3824
3825 if (i.types[0].bitfield.imm1)
3826 i.imm_operands = 0; /* kludge for shift insns. */
3827
3828 /* We only need to check those implicit registers for instructions
3829 with 3 operands or less. */
3830 if (i.operands <= 3)
3831 for (j = 0; j < i.operands; j++)
3832 if (i.types[j].bitfield.inoutportreg
3833 || i.types[j].bitfield.shiftcount
3834 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
3835 i.reg_operands--;
3836
3837 /* ImmExt should be processed after SSE2AVX. */
3838 if (!i.tm.opcode_modifier.sse2avx
3839 && i.tm.opcode_modifier.immext)
3840 process_immext ();
3841
3842 /* For insns with operands there are more diddles to do to the opcode. */
3843 if (i.operands)
3844 {
3845 if (!process_operands ())
3846 return;
3847 }
3848 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3849 {
3850 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3851 as_warn (_("translating to `%sp'"), i.tm.name);
3852 }
3853
3854 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3855 {
3856 if (flag_code == CODE_16BIT)
3857 {
3858 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3859 i.tm.name);
3860 return;
3861 }
3862
3863 if (i.tm.opcode_modifier.vex)
3864 build_vex_prefix (t);
3865 else
3866 build_evex_prefix ();
3867 }
3868
3869 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3870 instructions may define INT_OPCODE as well, so avoid this corner
3871 case for those instructions that use MODRM. */
3872 if (i.tm.base_opcode == INT_OPCODE
3873 && !i.tm.opcode_modifier.modrm
3874 && i.op[0].imms->X_add_number == 3)
3875 {
3876 i.tm.base_opcode = INT3_OPCODE;
3877 i.imm_operands = 0;
3878 }
3879
3880 if ((i.tm.opcode_modifier.jump
3881 || i.tm.opcode_modifier.jumpbyte
3882 || i.tm.opcode_modifier.jumpdword)
3883 && i.op[0].disps->X_op == O_constant)
3884 {
3885 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3886 the absolute address given by the constant. Since ix86 jumps and
3887 calls are pc relative, we need to generate a reloc. */
3888 i.op[0].disps->X_add_symbol = &abs_symbol;
3889 i.op[0].disps->X_op = O_symbol;
3890 }
3891
3892 if (i.tm.opcode_modifier.rex64)
3893 i.rex |= REX_W;
3894
3895 /* For 8 bit registers we need an empty rex prefix. Also if the
3896 instruction already has a prefix, we need to convert old
3897 registers to new ones. */
3898
3899 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
3900 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3901 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
3902 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3903 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3904 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
3905 && i.rex != 0))
3906 {
3907 int x;
3908
3909 i.rex |= REX_OPCODE;
3910 for (x = 0; x < 2; x++)
3911 {
3912 /* Look for 8 bit operand that uses old registers. */
3913 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
3914 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3915 {
3916 /* In case it is "hi" register, give up. */
3917 if (i.op[x].regs->reg_num > 3)
3918 as_bad (_("can't encode register '%s%s' in an "
3919 "instruction requiring REX prefix."),
3920 register_prefix, i.op[x].regs->reg_name);
3921
3922 /* Otherwise it is equivalent to the extended register.
3923 Since the encoding doesn't change this is merely
3924 cosmetic cleanup for debug output. */
3925
3926 i.op[x].regs = i.op[x].regs + 8;
3927 }
3928 }
3929 }
3930
3931 if (i.rex != 0)
3932 add_prefix (REX_OPCODE | i.rex);
3933
3934 /* We are ready to output the insn. */
3935 output_insn ();
3936 }
3937
3938 static char *
3939 parse_insn (char *line, char *mnemonic)
3940 {
3941 char *l = line;
3942 char *token_start = l;
3943 char *mnem_p;
3944 int supported;
3945 const insn_template *t;
3946 char *dot_p = NULL;
3947
3948 while (1)
3949 {
3950 mnem_p = mnemonic;
3951 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3952 {
3953 if (*mnem_p == '.')
3954 dot_p = mnem_p;
3955 mnem_p++;
3956 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3957 {
3958 as_bad (_("no such instruction: `%s'"), token_start);
3959 return NULL;
3960 }
3961 l++;
3962 }
3963 if (!is_space_char (*l)
3964 && *l != END_OF_INSN
3965 && (intel_syntax
3966 || (*l != PREFIX_SEPARATOR
3967 && *l != ',')))
3968 {
3969 as_bad (_("invalid character %s in mnemonic"),
3970 output_invalid (*l));
3971 return NULL;
3972 }
3973 if (token_start == l)
3974 {
3975 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3976 as_bad (_("expecting prefix; got nothing"));
3977 else
3978 as_bad (_("expecting mnemonic; got nothing"));
3979 return NULL;
3980 }
3981
3982 /* Look up instruction (or prefix) via hash table. */
3983 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3984
3985 if (*l != END_OF_INSN
3986 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3987 && current_templates
3988 && current_templates->start->opcode_modifier.isprefix)
3989 {
3990 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3991 {
3992 as_bad ((flag_code != CODE_64BIT
3993 ? _("`%s' is only supported in 64-bit mode")
3994 : _("`%s' is not supported in 64-bit mode")),
3995 current_templates->start->name);
3996 return NULL;
3997 }
3998 /* If we are in 16-bit mode, do not allow addr16 or data16.
3999 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4000 if ((current_templates->start->opcode_modifier.size16
4001 || current_templates->start->opcode_modifier.size32)
4002 && flag_code != CODE_64BIT
4003 && (current_templates->start->opcode_modifier.size32
4004 ^ (flag_code == CODE_16BIT)))
4005 {
4006 as_bad (_("redundant %s prefix"),
4007 current_templates->start->name);
4008 return NULL;
4009 }
4010 if (current_templates->start->opcode_length == 0)
4011 {
4012 /* Handle pseudo prefixes. */
4013 switch (current_templates->start->base_opcode)
4014 {
4015 case 0x0:
4016 /* {disp8} */
4017 i.disp_encoding = disp_encoding_8bit;
4018 break;
4019 case 0x1:
4020 /* {disp32} */
4021 i.disp_encoding = disp_encoding_32bit;
4022 break;
4023 case 0x2:
4024 /* {load} */
4025 i.dir_encoding = dir_encoding_load;
4026 break;
4027 case 0x3:
4028 /* {store} */
4029 i.dir_encoding = dir_encoding_store;
4030 break;
4031 case 0x4:
4032 /* {vex2} */
4033 i.vec_encoding = vex_encoding_vex2;
4034 break;
4035 case 0x5:
4036 /* {vex3} */
4037 i.vec_encoding = vex_encoding_vex3;
4038 break;
4039 case 0x6:
4040 /* {evex} */
4041 i.vec_encoding = vex_encoding_evex;
4042 break;
4043 default:
4044 abort ();
4045 }
4046 }
4047 else
4048 {
4049 /* Add prefix, checking for repeated prefixes. */
4050 switch (add_prefix (current_templates->start->base_opcode))
4051 {
4052 case PREFIX_EXIST:
4053 return NULL;
4054 case PREFIX_DS:
4055 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4056 i.notrack_prefix = current_templates->start->name;
4057 break;
4058 case PREFIX_REP:
4059 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4060 i.hle_prefix = current_templates->start->name;
4061 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4062 i.bnd_prefix = current_templates->start->name;
4063 else
4064 i.rep_prefix = current_templates->start->name;
4065 break;
4066 default:
4067 break;
4068 }
4069 }
4070 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4071 token_start = ++l;
4072 }
4073 else
4074 break;
4075 }
4076
4077 if (!current_templates)
4078 {
4079 /* Check if we should swap operand or force 32bit displacement in
4080 encoding. */
4081 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4082 i.dir_encoding = dir_encoding_store;
4083 else if (mnem_p - 3 == dot_p
4084 && dot_p[1] == 'd'
4085 && dot_p[2] == '8')
4086 i.disp_encoding = disp_encoding_8bit;
4087 else if (mnem_p - 4 == dot_p
4088 && dot_p[1] == 'd'
4089 && dot_p[2] == '3'
4090 && dot_p[3] == '2')
4091 i.disp_encoding = disp_encoding_32bit;
4092 else
4093 goto check_suffix;
4094 mnem_p = dot_p;
4095 *dot_p = '\0';
4096 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4097 }
4098
4099 if (!current_templates)
4100 {
4101 check_suffix:
4102 /* See if we can get a match by trimming off a suffix. */
4103 switch (mnem_p[-1])
4104 {
4105 case WORD_MNEM_SUFFIX:
4106 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4107 i.suffix = SHORT_MNEM_SUFFIX;
4108 else
4109 /* Fall through. */
4110 case BYTE_MNEM_SUFFIX:
4111 case QWORD_MNEM_SUFFIX:
4112 i.suffix = mnem_p[-1];
4113 mnem_p[-1] = '\0';
4114 current_templates = (const templates *) hash_find (op_hash,
4115 mnemonic);
4116 break;
4117 case SHORT_MNEM_SUFFIX:
4118 case LONG_MNEM_SUFFIX:
4119 if (!intel_syntax)
4120 {
4121 i.suffix = mnem_p[-1];
4122 mnem_p[-1] = '\0';
4123 current_templates = (const templates *) hash_find (op_hash,
4124 mnemonic);
4125 }
4126 break;
4127
4128 /* Intel Syntax. */
4129 case 'd':
4130 if (intel_syntax)
4131 {
4132 if (intel_float_operand (mnemonic) == 1)
4133 i.suffix = SHORT_MNEM_SUFFIX;
4134 else
4135 i.suffix = LONG_MNEM_SUFFIX;
4136 mnem_p[-1] = '\0';
4137 current_templates = (const templates *) hash_find (op_hash,
4138 mnemonic);
4139 }
4140 break;
4141 }
4142 if (!current_templates)
4143 {
4144 as_bad (_("no such instruction: `%s'"), token_start);
4145 return NULL;
4146 }
4147 }
4148
4149 if (current_templates->start->opcode_modifier.jump
4150 || current_templates->start->opcode_modifier.jumpbyte)
4151 {
4152 /* Check for a branch hint. We allow ",pt" and ",pn" for
4153 predict taken and predict not taken respectively.
4154 I'm not sure that branch hints actually do anything on loop
4155 and jcxz insns (JumpByte) for current Pentium4 chips. They
4156 may work in the future and it doesn't hurt to accept them
4157 now. */
4158 if (l[0] == ',' && l[1] == 'p')
4159 {
4160 if (l[2] == 't')
4161 {
4162 if (!add_prefix (DS_PREFIX_OPCODE))
4163 return NULL;
4164 l += 3;
4165 }
4166 else if (l[2] == 'n')
4167 {
4168 if (!add_prefix (CS_PREFIX_OPCODE))
4169 return NULL;
4170 l += 3;
4171 }
4172 }
4173 }
4174 /* Any other comma loses. */
4175 if (*l == ',')
4176 {
4177 as_bad (_("invalid character %s in mnemonic"),
4178 output_invalid (*l));
4179 return NULL;
4180 }
4181
4182 /* Check if instruction is supported on specified architecture. */
4183 supported = 0;
4184 for (t = current_templates->start; t < current_templates->end; ++t)
4185 {
4186 supported |= cpu_flags_match (t);
4187 if (supported == CPU_FLAGS_PERFECT_MATCH)
4188 goto skip;
4189 }
4190
4191 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4192 {
4193 as_bad (flag_code == CODE_64BIT
4194 ? _("`%s' is not supported in 64-bit mode")
4195 : _("`%s' is only supported in 64-bit mode"),
4196 current_templates->start->name);
4197 return NULL;
4198 }
4199 if (supported != CPU_FLAGS_PERFECT_MATCH)
4200 {
4201 as_bad (_("`%s' is not supported on `%s%s'"),
4202 current_templates->start->name,
4203 cpu_arch_name ? cpu_arch_name : default_arch,
4204 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4205 return NULL;
4206 }
4207
4208 skip:
4209 if (!cpu_arch_flags.bitfield.cpui386
4210 && (flag_code != CODE_16BIT))
4211 {
4212 as_warn (_("use .code16 to ensure correct addressing mode"));
4213 }
4214
4215 return l;
4216 }
4217
4218 static char *
4219 parse_operands (char *l, const char *mnemonic)
4220 {
4221 char *token_start;
4222
4223 /* 1 if operand is pending after ','. */
4224 unsigned int expecting_operand = 0;
4225
4226 /* Non-zero if operand parens not balanced. */
4227 unsigned int paren_not_balanced;
4228
4229 while (*l != END_OF_INSN)
4230 {
4231 /* Skip optional white space before operand. */
4232 if (is_space_char (*l))
4233 ++l;
4234 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4235 {
4236 as_bad (_("invalid character %s before operand %d"),
4237 output_invalid (*l),
4238 i.operands + 1);
4239 return NULL;
4240 }
4241 token_start = l; /* After white space. */
4242 paren_not_balanced = 0;
4243 while (paren_not_balanced || *l != ',')
4244 {
4245 if (*l == END_OF_INSN)
4246 {
4247 if (paren_not_balanced)
4248 {
4249 if (!intel_syntax)
4250 as_bad (_("unbalanced parenthesis in operand %d."),
4251 i.operands + 1);
4252 else
4253 as_bad (_("unbalanced brackets in operand %d."),
4254 i.operands + 1);
4255 return NULL;
4256 }
4257 else
4258 break; /* we are done */
4259 }
4260 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4261 {
4262 as_bad (_("invalid character %s in operand %d"),
4263 output_invalid (*l),
4264 i.operands + 1);
4265 return NULL;
4266 }
4267 if (!intel_syntax)
4268 {
4269 if (*l == '(')
4270 ++paren_not_balanced;
4271 if (*l == ')')
4272 --paren_not_balanced;
4273 }
4274 else
4275 {
4276 if (*l == '[')
4277 ++paren_not_balanced;
4278 if (*l == ']')
4279 --paren_not_balanced;
4280 }
4281 l++;
4282 }
4283 if (l != token_start)
4284 { /* Yes, we've read in another operand. */
4285 unsigned int operand_ok;
4286 this_operand = i.operands++;
4287 if (i.operands > MAX_OPERANDS)
4288 {
4289 as_bad (_("spurious operands; (%d operands/instruction max)"),
4290 MAX_OPERANDS);
4291 return NULL;
4292 }
4293 i.types[this_operand].bitfield.unspecified = 1;
4294 /* Now parse operand adding info to 'i' as we go along. */
4295 END_STRING_AND_SAVE (l);
4296
4297 if (intel_syntax)
4298 operand_ok =
4299 i386_intel_operand (token_start,
4300 intel_float_operand (mnemonic));
4301 else
4302 operand_ok = i386_att_operand (token_start);
4303
4304 RESTORE_END_STRING (l);
4305 if (!operand_ok)
4306 return NULL;
4307 }
4308 else
4309 {
4310 if (expecting_operand)
4311 {
4312 expecting_operand_after_comma:
4313 as_bad (_("expecting operand after ','; got nothing"));
4314 return NULL;
4315 }
4316 if (*l == ',')
4317 {
4318 as_bad (_("expecting operand before ','; got nothing"));
4319 return NULL;
4320 }
4321 }
4322
4323 /* Now *l must be either ',' or END_OF_INSN. */
4324 if (*l == ',')
4325 {
4326 if (*++l == END_OF_INSN)
4327 {
4328 /* Just skip it, if it's \n complain. */
4329 goto expecting_operand_after_comma;
4330 }
4331 expecting_operand = 1;
4332 }
4333 }
4334 return l;
4335 }
4336
4337 static void
4338 swap_2_operands (int xchg1, int xchg2)
4339 {
4340 union i386_op temp_op;
4341 i386_operand_type temp_type;
4342 enum bfd_reloc_code_real temp_reloc;
4343
4344 temp_type = i.types[xchg2];
4345 i.types[xchg2] = i.types[xchg1];
4346 i.types[xchg1] = temp_type;
4347 temp_op = i.op[xchg2];
4348 i.op[xchg2] = i.op[xchg1];
4349 i.op[xchg1] = temp_op;
4350 temp_reloc = i.reloc[xchg2];
4351 i.reloc[xchg2] = i.reloc[xchg1];
4352 i.reloc[xchg1] = temp_reloc;
4353
4354 if (i.mask)
4355 {
4356 if (i.mask->operand == xchg1)
4357 i.mask->operand = xchg2;
4358 else if (i.mask->operand == xchg2)
4359 i.mask->operand = xchg1;
4360 }
4361 if (i.broadcast)
4362 {
4363 if (i.broadcast->operand == xchg1)
4364 i.broadcast->operand = xchg2;
4365 else if (i.broadcast->operand == xchg2)
4366 i.broadcast->operand = xchg1;
4367 }
4368 if (i.rounding)
4369 {
4370 if (i.rounding->operand == xchg1)
4371 i.rounding->operand = xchg2;
4372 else if (i.rounding->operand == xchg2)
4373 i.rounding->operand = xchg1;
4374 }
4375 }
4376
4377 static void
4378 swap_operands (void)
4379 {
4380 switch (i.operands)
4381 {
4382 case 5:
4383 case 4:
4384 swap_2_operands (1, i.operands - 2);
4385 /* Fall through. */
4386 case 3:
4387 case 2:
4388 swap_2_operands (0, i.operands - 1);
4389 break;
4390 default:
4391 abort ();
4392 }
4393
4394 if (i.mem_operands == 2)
4395 {
4396 const seg_entry *temp_seg;
4397 temp_seg = i.seg[0];
4398 i.seg[0] = i.seg[1];
4399 i.seg[1] = temp_seg;
4400 }
4401 }
4402
4403 /* Try to ensure constant immediates are represented in the smallest
4404 opcode possible. */
4405 static void
4406 optimize_imm (void)
4407 {
4408 char guess_suffix = 0;
4409 int op;
4410
4411 if (i.suffix)
4412 guess_suffix = i.suffix;
4413 else if (i.reg_operands)
4414 {
4415 /* Figure out a suffix from the last register operand specified.
4416 We can't do this properly yet, ie. excluding InOutPortReg,
4417 but the following works for instructions with immediates.
4418 In any case, we can't set i.suffix yet. */
4419 for (op = i.operands; --op >= 0;)
4420 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4421 {
4422 guess_suffix = BYTE_MNEM_SUFFIX;
4423 break;
4424 }
4425 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4426 {
4427 guess_suffix = WORD_MNEM_SUFFIX;
4428 break;
4429 }
4430 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4431 {
4432 guess_suffix = LONG_MNEM_SUFFIX;
4433 break;
4434 }
4435 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4436 {
4437 guess_suffix = QWORD_MNEM_SUFFIX;
4438 break;
4439 }
4440 }
4441 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4442 guess_suffix = WORD_MNEM_SUFFIX;
4443
4444 for (op = i.operands; --op >= 0;)
4445 if (operand_type_check (i.types[op], imm))
4446 {
4447 switch (i.op[op].imms->X_op)
4448 {
4449 case O_constant:
4450 /* If a suffix is given, this operand may be shortened. */
4451 switch (guess_suffix)
4452 {
4453 case LONG_MNEM_SUFFIX:
4454 i.types[op].bitfield.imm32 = 1;
4455 i.types[op].bitfield.imm64 = 1;
4456 break;
4457 case WORD_MNEM_SUFFIX:
4458 i.types[op].bitfield.imm16 = 1;
4459 i.types[op].bitfield.imm32 = 1;
4460 i.types[op].bitfield.imm32s = 1;
4461 i.types[op].bitfield.imm64 = 1;
4462 break;
4463 case BYTE_MNEM_SUFFIX:
4464 i.types[op].bitfield.imm8 = 1;
4465 i.types[op].bitfield.imm8s = 1;
4466 i.types[op].bitfield.imm16 = 1;
4467 i.types[op].bitfield.imm32 = 1;
4468 i.types[op].bitfield.imm32s = 1;
4469 i.types[op].bitfield.imm64 = 1;
4470 break;
4471 }
4472
4473 /* If this operand is at most 16 bits, convert it
4474 to a signed 16 bit number before trying to see
4475 whether it will fit in an even smaller size.
4476 This allows a 16-bit operand such as $0xffe0 to
4477 be recognised as within Imm8S range. */
4478 if ((i.types[op].bitfield.imm16)
4479 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4480 {
4481 i.op[op].imms->X_add_number =
4482 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4483 }
4484 #ifdef BFD64
4485 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4486 if ((i.types[op].bitfield.imm32)
4487 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4488 == 0))
4489 {
4490 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4491 ^ ((offsetT) 1 << 31))
4492 - ((offsetT) 1 << 31));
4493 }
4494 #endif
4495 i.types[op]
4496 = operand_type_or (i.types[op],
4497 smallest_imm_type (i.op[op].imms->X_add_number));
4498
4499 /* We must avoid matching of Imm32 templates when 64bit
4500 only immediate is available. */
4501 if (guess_suffix == QWORD_MNEM_SUFFIX)
4502 i.types[op].bitfield.imm32 = 0;
4503 break;
4504
4505 case O_absent:
4506 case O_register:
4507 abort ();
4508
4509 /* Symbols and expressions. */
4510 default:
4511 /* Convert symbolic operand to proper sizes for matching, but don't
4512 prevent matching a set of insns that only supports sizes other
4513 than those matching the insn suffix. */
4514 {
4515 i386_operand_type mask, allowed;
4516 const insn_template *t;
4517
4518 operand_type_set (&mask, 0);
4519 operand_type_set (&allowed, 0);
4520
4521 for (t = current_templates->start;
4522 t < current_templates->end;
4523 ++t)
4524 allowed = operand_type_or (allowed,
4525 t->operand_types[op]);
4526 switch (guess_suffix)
4527 {
4528 case QWORD_MNEM_SUFFIX:
4529 mask.bitfield.imm64 = 1;
4530 mask.bitfield.imm32s = 1;
4531 break;
4532 case LONG_MNEM_SUFFIX:
4533 mask.bitfield.imm32 = 1;
4534 break;
4535 case WORD_MNEM_SUFFIX:
4536 mask.bitfield.imm16 = 1;
4537 break;
4538 case BYTE_MNEM_SUFFIX:
4539 mask.bitfield.imm8 = 1;
4540 break;
4541 default:
4542 break;
4543 }
4544 allowed = operand_type_and (mask, allowed);
4545 if (!operand_type_all_zero (&allowed))
4546 i.types[op] = operand_type_and (i.types[op], mask);
4547 }
4548 break;
4549 }
4550 }
4551 }
4552
4553 /* Try to use the smallest displacement type too. */
4554 static void
4555 optimize_disp (void)
4556 {
4557 int op;
4558
4559 for (op = i.operands; --op >= 0;)
4560 if (operand_type_check (i.types[op], disp))
4561 {
4562 if (i.op[op].disps->X_op == O_constant)
4563 {
4564 offsetT op_disp = i.op[op].disps->X_add_number;
4565
4566 if (i.types[op].bitfield.disp16
4567 && (op_disp & ~(offsetT) 0xffff) == 0)
4568 {
4569 /* If this operand is at most 16 bits, convert
4570 to a signed 16 bit number and don't use 64bit
4571 displacement. */
4572 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4573 i.types[op].bitfield.disp64 = 0;
4574 }
4575 #ifdef BFD64
4576 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4577 if (i.types[op].bitfield.disp32
4578 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4579 {
4580 /* If this operand is at most 32 bits, convert
4581 to a signed 32 bit number and don't use 64bit
4582 displacement. */
4583 op_disp &= (((offsetT) 2 << 31) - 1);
4584 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4585 i.types[op].bitfield.disp64 = 0;
4586 }
4587 #endif
4588 if (!op_disp && i.types[op].bitfield.baseindex)
4589 {
4590 i.types[op].bitfield.disp8 = 0;
4591 i.types[op].bitfield.disp16 = 0;
4592 i.types[op].bitfield.disp32 = 0;
4593 i.types[op].bitfield.disp32s = 0;
4594 i.types[op].bitfield.disp64 = 0;
4595 i.op[op].disps = 0;
4596 i.disp_operands--;
4597 }
4598 else if (flag_code == CODE_64BIT)
4599 {
4600 if (fits_in_signed_long (op_disp))
4601 {
4602 i.types[op].bitfield.disp64 = 0;
4603 i.types[op].bitfield.disp32s = 1;
4604 }
4605 if (i.prefix[ADDR_PREFIX]
4606 && fits_in_unsigned_long (op_disp))
4607 i.types[op].bitfield.disp32 = 1;
4608 }
4609 if ((i.types[op].bitfield.disp32
4610 || i.types[op].bitfield.disp32s
4611 || i.types[op].bitfield.disp16)
4612 && fits_in_disp8 (op_disp))
4613 i.types[op].bitfield.disp8 = 1;
4614 }
4615 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4616 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4617 {
4618 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4619 i.op[op].disps, 0, i.reloc[op]);
4620 i.types[op].bitfield.disp8 = 0;
4621 i.types[op].bitfield.disp16 = 0;
4622 i.types[op].bitfield.disp32 = 0;
4623 i.types[op].bitfield.disp32s = 0;
4624 i.types[op].bitfield.disp64 = 0;
4625 }
4626 else
4627 /* We only support 64bit displacement on constants. */
4628 i.types[op].bitfield.disp64 = 0;
4629 }
4630 }
4631
4632 /* Check if operands are valid for the instruction. */
4633
4634 static int
4635 check_VecOperands (const insn_template *t)
4636 {
4637 unsigned int op;
4638
4639 /* Without VSIB byte, we can't have a vector register for index. */
4640 if (!t->opcode_modifier.vecsib
4641 && i.index_reg
4642 && (i.index_reg->reg_type.bitfield.xmmword
4643 || i.index_reg->reg_type.bitfield.ymmword
4644 || i.index_reg->reg_type.bitfield.zmmword))
4645 {
4646 i.error = unsupported_vector_index_register;
4647 return 1;
4648 }
4649
4650 /* Check if default mask is allowed. */
4651 if (t->opcode_modifier.nodefmask
4652 && (!i.mask || i.mask->mask->reg_num == 0))
4653 {
4654 i.error = no_default_mask;
4655 return 1;
4656 }
4657
4658 /* For VSIB byte, we need a vector register for index, and all vector
4659 registers must be distinct. */
4660 if (t->opcode_modifier.vecsib)
4661 {
4662 if (!i.index_reg
4663 || !((t->opcode_modifier.vecsib == VecSIB128
4664 && i.index_reg->reg_type.bitfield.xmmword)
4665 || (t->opcode_modifier.vecsib == VecSIB256
4666 && i.index_reg->reg_type.bitfield.ymmword)
4667 || (t->opcode_modifier.vecsib == VecSIB512
4668 && i.index_reg->reg_type.bitfield.zmmword)))
4669 {
4670 i.error = invalid_vsib_address;
4671 return 1;
4672 }
4673
4674 gas_assert (i.reg_operands == 2 || i.mask);
4675 if (i.reg_operands == 2 && !i.mask)
4676 {
4677 gas_assert (i.types[0].bitfield.regsimd);
4678 gas_assert (i.types[0].bitfield.xmmword
4679 || i.types[0].bitfield.ymmword);
4680 gas_assert (i.types[2].bitfield.regsimd);
4681 gas_assert (i.types[2].bitfield.xmmword
4682 || i.types[2].bitfield.ymmword);
4683 if (operand_check == check_none)
4684 return 0;
4685 if (register_number (i.op[0].regs)
4686 != register_number (i.index_reg)
4687 && register_number (i.op[2].regs)
4688 != register_number (i.index_reg)
4689 && register_number (i.op[0].regs)
4690 != register_number (i.op[2].regs))
4691 return 0;
4692 if (operand_check == check_error)
4693 {
4694 i.error = invalid_vector_register_set;
4695 return 1;
4696 }
4697 as_warn (_("mask, index, and destination registers should be distinct"));
4698 }
4699 else if (i.reg_operands == 1 && i.mask)
4700 {
4701 if (i.types[1].bitfield.regsimd
4702 && (i.types[1].bitfield.xmmword
4703 || i.types[1].bitfield.ymmword
4704 || i.types[1].bitfield.zmmword)
4705 && (register_number (i.op[1].regs)
4706 == register_number (i.index_reg)))
4707 {
4708 if (operand_check == check_error)
4709 {
4710 i.error = invalid_vector_register_set;
4711 return 1;
4712 }
4713 if (operand_check != check_none)
4714 as_warn (_("index and destination registers should be distinct"));
4715 }
4716 }
4717 }
4718
4719 /* Check if broadcast is supported by the instruction and is applied
4720 to the memory operand. */
4721 if (i.broadcast)
4722 {
4723 int broadcasted_opnd_size;
4724
4725 /* Check if specified broadcast is supported in this instruction,
4726 and it's applied to memory operand of DWORD or QWORD type,
4727 depending on VecESize. */
4728 if (i.broadcast->type != t->opcode_modifier.broadcast
4729 || !i.types[i.broadcast->operand].bitfield.mem
4730 || (t->opcode_modifier.vecesize == 0
4731 && !i.types[i.broadcast->operand].bitfield.dword
4732 && !i.types[i.broadcast->operand].bitfield.unspecified)
4733 || (t->opcode_modifier.vecesize == 1
4734 && !i.types[i.broadcast->operand].bitfield.qword
4735 && !i.types[i.broadcast->operand].bitfield.unspecified))
4736 goto bad_broadcast;
4737
4738 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4739 if (i.broadcast->type == BROADCAST_1TO16)
4740 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4741 else if (i.broadcast->type == BROADCAST_1TO8)
4742 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4743 else if (i.broadcast->type == BROADCAST_1TO4)
4744 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4745 else if (i.broadcast->type == BROADCAST_1TO2)
4746 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4747 else
4748 goto bad_broadcast;
4749
4750 if ((broadcasted_opnd_size == 256
4751 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4752 || (broadcasted_opnd_size == 512
4753 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4754 {
4755 bad_broadcast:
4756 i.error = unsupported_broadcast;
4757 return 1;
4758 }
4759 }
4760 /* If broadcast is supported in this instruction, we need to check if
4761 operand of one-element size isn't specified without broadcast. */
4762 else if (t->opcode_modifier.broadcast && i.mem_operands)
4763 {
4764 /* Find memory operand. */
4765 for (op = 0; op < i.operands; op++)
4766 if (operand_type_check (i.types[op], anymem))
4767 break;
4768 gas_assert (op < i.operands);
4769 /* Check size of the memory operand. */
4770 if ((t->opcode_modifier.vecesize == 0
4771 && i.types[op].bitfield.dword)
4772 || (t->opcode_modifier.vecesize == 1
4773 && i.types[op].bitfield.qword))
4774 {
4775 i.error = broadcast_needed;
4776 return 1;
4777 }
4778 }
4779
4780 /* Check if requested masking is supported. */
4781 if (i.mask
4782 && (!t->opcode_modifier.masking
4783 || (i.mask->zeroing
4784 && t->opcode_modifier.masking == MERGING_MASKING)))
4785 {
4786 i.error = unsupported_masking;
4787 return 1;
4788 }
4789
4790 /* Check if masking is applied to dest operand. */
4791 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4792 {
4793 i.error = mask_not_on_destination;
4794 return 1;
4795 }
4796
4797 /* Check RC/SAE. */
4798 if (i.rounding)
4799 {
4800 if ((i.rounding->type != saeonly
4801 && !t->opcode_modifier.staticrounding)
4802 || (i.rounding->type == saeonly
4803 && (t->opcode_modifier.staticrounding
4804 || !t->opcode_modifier.sae)))
4805 {
4806 i.error = unsupported_rc_sae;
4807 return 1;
4808 }
4809 /* If the instruction has several immediate operands and one of
4810 them is rounding, the rounding operand should be the last
4811 immediate operand. */
4812 if (i.imm_operands > 1
4813 && i.rounding->operand != (int) (i.imm_operands - 1))
4814 {
4815 i.error = rc_sae_operand_not_last_imm;
4816 return 1;
4817 }
4818 }
4819
4820 /* Check vector Disp8 operand. */
4821 if (t->opcode_modifier.disp8memshift
4822 && i.disp_encoding != disp_encoding_32bit)
4823 {
4824 if (i.broadcast)
4825 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4826 else
4827 i.memshift = t->opcode_modifier.disp8memshift;
4828
4829 for (op = 0; op < i.operands; op++)
4830 if (operand_type_check (i.types[op], disp)
4831 && i.op[op].disps->X_op == O_constant)
4832 {
4833 if (fits_in_disp8 (i.op[op].disps->X_add_number))
4834 {
4835 i.types[op].bitfield.disp8 = 1;
4836 return 0;
4837 }
4838 i.types[op].bitfield.disp8 = 0;
4839 }
4840 }
4841
4842 i.memshift = 0;
4843
4844 return 0;
4845 }
4846
4847 /* Check if operands are valid for the instruction. Update VEX
4848 operand types. */
4849
4850 static int
4851 VEX_check_operands (const insn_template *t)
4852 {
4853 if (i.vec_encoding == vex_encoding_evex)
4854 {
4855 /* This instruction must be encoded with EVEX prefix. */
4856 if (!t->opcode_modifier.evex)
4857 {
4858 i.error = unsupported;
4859 return 1;
4860 }
4861 return 0;
4862 }
4863
4864 if (!t->opcode_modifier.vex)
4865 {
4866 /* This instruction template doesn't have VEX prefix. */
4867 if (i.vec_encoding != vex_encoding_default)
4868 {
4869 i.error = unsupported;
4870 return 1;
4871 }
4872 return 0;
4873 }
4874
4875 /* Only check VEX_Imm4, which must be the first operand. */
4876 if (t->operand_types[0].bitfield.vec_imm4)
4877 {
4878 if (i.op[0].imms->X_op != O_constant
4879 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4880 {
4881 i.error = bad_imm4;
4882 return 1;
4883 }
4884
4885 /* Turn off Imm8 so that update_imm won't complain. */
4886 i.types[0] = vec_imm4;
4887 }
4888
4889 return 0;
4890 }
4891
4892 static const insn_template *
4893 match_template (char mnem_suffix)
4894 {
4895 /* Points to template once we've found it. */
4896 const insn_template *t;
4897 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4898 i386_operand_type overlap4;
4899 unsigned int found_reverse_match;
4900 i386_opcode_modifier suffix_check, mnemsuf_check;
4901 i386_operand_type operand_types [MAX_OPERANDS];
4902 int addr_prefix_disp;
4903 unsigned int j;
4904 unsigned int found_cpu_match;
4905 unsigned int check_register;
4906 enum i386_error specific_error = 0;
4907
4908 #if MAX_OPERANDS != 5
4909 # error "MAX_OPERANDS must be 5."
4910 #endif
4911
4912 found_reverse_match = 0;
4913 addr_prefix_disp = -1;
4914
4915 memset (&suffix_check, 0, sizeof (suffix_check));
4916 if (i.suffix == BYTE_MNEM_SUFFIX)
4917 suffix_check.no_bsuf = 1;
4918 else if (i.suffix == WORD_MNEM_SUFFIX)
4919 suffix_check.no_wsuf = 1;
4920 else if (i.suffix == SHORT_MNEM_SUFFIX)
4921 suffix_check.no_ssuf = 1;
4922 else if (i.suffix == LONG_MNEM_SUFFIX)
4923 suffix_check.no_lsuf = 1;
4924 else if (i.suffix == QWORD_MNEM_SUFFIX)
4925 suffix_check.no_qsuf = 1;
4926 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4927 suffix_check.no_ldsuf = 1;
4928
4929 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4930 if (intel_syntax)
4931 {
4932 switch (mnem_suffix)
4933 {
4934 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4935 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4936 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4937 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4938 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4939 }
4940 }
4941
4942 /* Must have right number of operands. */
4943 i.error = number_of_operands_mismatch;
4944
4945 for (t = current_templates->start; t < current_templates->end; t++)
4946 {
4947 addr_prefix_disp = -1;
4948
4949 if (i.operands != t->operands)
4950 continue;
4951
4952 /* Check processor support. */
4953 i.error = unsupported;
4954 found_cpu_match = (cpu_flags_match (t)
4955 == CPU_FLAGS_PERFECT_MATCH);
4956 if (!found_cpu_match)
4957 continue;
4958
4959 /* Check old gcc support. */
4960 i.error = old_gcc_only;
4961 if (!old_gcc && t->opcode_modifier.oldgcc)
4962 continue;
4963
4964 /* Check AT&T mnemonic. */
4965 i.error = unsupported_with_intel_mnemonic;
4966 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4967 continue;
4968
4969 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4970 i.error = unsupported_syntax;
4971 if ((intel_syntax && t->opcode_modifier.attsyntax)
4972 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4973 || (intel64 && t->opcode_modifier.amd64)
4974 || (!intel64 && t->opcode_modifier.intel64))
4975 continue;
4976
4977 /* Check the suffix, except for some instructions in intel mode. */
4978 i.error = invalid_instruction_suffix;
4979 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4980 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4981 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4982 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4983 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4984 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4985 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4986 continue;
4987 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4988 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4989 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4990 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4991 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4992 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4993 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4994 continue;
4995
4996 if (!operand_size_match (t))
4997 continue;
4998
4999 for (j = 0; j < MAX_OPERANDS; j++)
5000 operand_types[j] = t->operand_types[j];
5001
5002 /* In general, don't allow 64-bit operands in 32-bit mode. */
5003 if (i.suffix == QWORD_MNEM_SUFFIX
5004 && flag_code != CODE_64BIT
5005 && (intel_syntax
5006 ? (!t->opcode_modifier.ignoresize
5007 && !intel_float_operand (t->name))
5008 : intel_float_operand (t->name) != 2)
5009 && ((!operand_types[0].bitfield.regmmx
5010 && !operand_types[0].bitfield.regsimd)
5011 || (!operand_types[t->operands > 1].bitfield.regmmx
5012 && !operand_types[t->operands > 1].bitfield.regsimd))
5013 && (t->base_opcode != 0x0fc7
5014 || t->extension_opcode != 1 /* cmpxchg8b */))
5015 continue;
5016
5017 /* In general, don't allow 32-bit operands on pre-386. */
5018 else if (i.suffix == LONG_MNEM_SUFFIX
5019 && !cpu_arch_flags.bitfield.cpui386
5020 && (intel_syntax
5021 ? (!t->opcode_modifier.ignoresize
5022 && !intel_float_operand (t->name))
5023 : intel_float_operand (t->name) != 2)
5024 && ((!operand_types[0].bitfield.regmmx
5025 && !operand_types[0].bitfield.regsimd)
5026 || (!operand_types[t->operands > 1].bitfield.regmmx
5027 && !operand_types[t->operands > 1].bitfield.regsimd)))
5028 continue;
5029
5030 /* Do not verify operands when there are none. */
5031 else
5032 {
5033 if (!t->operands)
5034 /* We've found a match; break out of loop. */
5035 break;
5036 }
5037
5038 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5039 into Disp32/Disp16/Disp32 operand. */
5040 if (i.prefix[ADDR_PREFIX] != 0)
5041 {
5042 /* There should be only one Disp operand. */
5043 switch (flag_code)
5044 {
5045 case CODE_16BIT:
5046 for (j = 0; j < MAX_OPERANDS; j++)
5047 {
5048 if (operand_types[j].bitfield.disp16)
5049 {
5050 addr_prefix_disp = j;
5051 operand_types[j].bitfield.disp32 = 1;
5052 operand_types[j].bitfield.disp16 = 0;
5053 break;
5054 }
5055 }
5056 break;
5057 case CODE_32BIT:
5058 for (j = 0; j < MAX_OPERANDS; j++)
5059 {
5060 if (operand_types[j].bitfield.disp32)
5061 {
5062 addr_prefix_disp = j;
5063 operand_types[j].bitfield.disp32 = 0;
5064 operand_types[j].bitfield.disp16 = 1;
5065 break;
5066 }
5067 }
5068 break;
5069 case CODE_64BIT:
5070 for (j = 0; j < MAX_OPERANDS; j++)
5071 {
5072 if (operand_types[j].bitfield.disp64)
5073 {
5074 addr_prefix_disp = j;
5075 operand_types[j].bitfield.disp64 = 0;
5076 operand_types[j].bitfield.disp32 = 1;
5077 break;
5078 }
5079 }
5080 break;
5081 }
5082 }
5083
5084 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5085 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5086 continue;
5087
5088 /* We check register size if needed. */
5089 check_register = t->opcode_modifier.checkregsize;
5090 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5091 switch (t->operands)
5092 {
5093 case 1:
5094 if (!operand_type_match (overlap0, i.types[0]))
5095 continue;
5096 break;
5097 case 2:
5098 /* xchg %eax, %eax is a special case. It is an alias for nop
5099 only in 32bit mode and we can use opcode 0x90. In 64bit
5100 mode, we can't use 0x90 for xchg %eax, %eax since it should
5101 zero-extend %eax to %rax. */
5102 if (flag_code == CODE_64BIT
5103 && t->base_opcode == 0x90
5104 && operand_type_equal (&i.types [0], &acc32)
5105 && operand_type_equal (&i.types [1], &acc32))
5106 continue;
5107 /* If we want store form, we reverse direction of operands. */
5108 if (i.dir_encoding == dir_encoding_store
5109 && t->opcode_modifier.d)
5110 goto check_reverse;
5111 /* Fall through. */
5112
5113 case 3:
5114 /* If we want store form, we skip the current load. */
5115 if (i.dir_encoding == dir_encoding_store
5116 && i.mem_operands == 0
5117 && t->opcode_modifier.load)
5118 continue;
5119 /* Fall through. */
5120 case 4:
5121 case 5:
5122 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5123 if (!operand_type_match (overlap0, i.types[0])
5124 || !operand_type_match (overlap1, i.types[1])
5125 || (check_register
5126 && !operand_type_register_match (i.types[0],
5127 operand_types[0],
5128 i.types[1],
5129 operand_types[1])))
5130 {
5131 /* Check if other direction is valid ... */
5132 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5133 continue;
5134
5135 check_reverse:
5136 /* Try reversing direction of operands. */
5137 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5138 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5139 if (!operand_type_match (overlap0, i.types[0])
5140 || !operand_type_match (overlap1, i.types[1])
5141 || (check_register
5142 && !operand_type_register_match (i.types[0],
5143 operand_types[1],
5144 i.types[1],
5145 operand_types[0])))
5146 {
5147 /* Does not match either direction. */
5148 continue;
5149 }
5150 /* found_reverse_match holds which of D or FloatDR
5151 we've found. */
5152 if (t->opcode_modifier.d)
5153 found_reverse_match = Opcode_D;
5154 else if (t->opcode_modifier.floatd)
5155 found_reverse_match = Opcode_FloatD;
5156 else
5157 found_reverse_match = 0;
5158 if (t->opcode_modifier.floatr)
5159 found_reverse_match |= Opcode_FloatR;
5160 }
5161 else
5162 {
5163 /* Found a forward 2 operand match here. */
5164 switch (t->operands)
5165 {
5166 case 5:
5167 overlap4 = operand_type_and (i.types[4],
5168 operand_types[4]);
5169 /* Fall through. */
5170 case 4:
5171 overlap3 = operand_type_and (i.types[3],
5172 operand_types[3]);
5173 /* Fall through. */
5174 case 3:
5175 overlap2 = operand_type_and (i.types[2],
5176 operand_types[2]);
5177 break;
5178 }
5179
5180 switch (t->operands)
5181 {
5182 case 5:
5183 if (!operand_type_match (overlap4, i.types[4])
5184 || !operand_type_register_match (i.types[3],
5185 operand_types[3],
5186 i.types[4],
5187 operand_types[4]))
5188 continue;
5189 /* Fall through. */
5190 case 4:
5191 if (!operand_type_match (overlap3, i.types[3])
5192 || (check_register
5193 && !operand_type_register_match (i.types[2],
5194 operand_types[2],
5195 i.types[3],
5196 operand_types[3])))
5197 continue;
5198 /* Fall through. */
5199 case 3:
5200 /* Here we make use of the fact that there are no
5201 reverse match 3 operand instructions, and all 3
5202 operand instructions only need to be checked for
5203 register consistency between operands 2 and 3. */
5204 if (!operand_type_match (overlap2, i.types[2])
5205 || (check_register
5206 && !operand_type_register_match (i.types[1],
5207 operand_types[1],
5208 i.types[2],
5209 operand_types[2])))
5210 continue;
5211 break;
5212 }
5213 }
5214 /* Found either forward/reverse 2, 3 or 4 operand match here:
5215 slip through to break. */
5216 }
5217 if (!found_cpu_match)
5218 {
5219 found_reverse_match = 0;
5220 continue;
5221 }
5222
5223 /* Check if vector and VEX operands are valid. */
5224 if (check_VecOperands (t) || VEX_check_operands (t))
5225 {
5226 specific_error = i.error;
5227 continue;
5228 }
5229
5230 /* We've found a match; break out of loop. */
5231 break;
5232 }
5233
5234 if (t == current_templates->end)
5235 {
5236 /* We found no match. */
5237 const char *err_msg;
5238 switch (specific_error ? specific_error : i.error)
5239 {
5240 default:
5241 abort ();
5242 case operand_size_mismatch:
5243 err_msg = _("operand size mismatch");
5244 break;
5245 case operand_type_mismatch:
5246 err_msg = _("operand type mismatch");
5247 break;
5248 case register_type_mismatch:
5249 err_msg = _("register type mismatch");
5250 break;
5251 case number_of_operands_mismatch:
5252 err_msg = _("number of operands mismatch");
5253 break;
5254 case invalid_instruction_suffix:
5255 err_msg = _("invalid instruction suffix");
5256 break;
5257 case bad_imm4:
5258 err_msg = _("constant doesn't fit in 4 bits");
5259 break;
5260 case old_gcc_only:
5261 err_msg = _("only supported with old gcc");
5262 break;
5263 case unsupported_with_intel_mnemonic:
5264 err_msg = _("unsupported with Intel mnemonic");
5265 break;
5266 case unsupported_syntax:
5267 err_msg = _("unsupported syntax");
5268 break;
5269 case unsupported:
5270 as_bad (_("unsupported instruction `%s'"),
5271 current_templates->start->name);
5272 return NULL;
5273 case invalid_vsib_address:
5274 err_msg = _("invalid VSIB address");
5275 break;
5276 case invalid_vector_register_set:
5277 err_msg = _("mask, index, and destination registers must be distinct");
5278 break;
5279 case unsupported_vector_index_register:
5280 err_msg = _("unsupported vector index register");
5281 break;
5282 case unsupported_broadcast:
5283 err_msg = _("unsupported broadcast");
5284 break;
5285 case broadcast_not_on_src_operand:
5286 err_msg = _("broadcast not on source memory operand");
5287 break;
5288 case broadcast_needed:
5289 err_msg = _("broadcast is needed for operand of such type");
5290 break;
5291 case unsupported_masking:
5292 err_msg = _("unsupported masking");
5293 break;
5294 case mask_not_on_destination:
5295 err_msg = _("mask not on destination operand");
5296 break;
5297 case no_default_mask:
5298 err_msg = _("default mask isn't allowed");
5299 break;
5300 case unsupported_rc_sae:
5301 err_msg = _("unsupported static rounding/sae");
5302 break;
5303 case rc_sae_operand_not_last_imm:
5304 if (intel_syntax)
5305 err_msg = _("RC/SAE operand must precede immediate operands");
5306 else
5307 err_msg = _("RC/SAE operand must follow immediate operands");
5308 break;
5309 case invalid_register_operand:
5310 err_msg = _("invalid register operand");
5311 break;
5312 }
5313 as_bad (_("%s for `%s'"), err_msg,
5314 current_templates->start->name);
5315 return NULL;
5316 }
5317
5318 if (!quiet_warnings)
5319 {
5320 if (!intel_syntax
5321 && (i.types[0].bitfield.jumpabsolute
5322 != operand_types[0].bitfield.jumpabsolute))
5323 {
5324 as_warn (_("indirect %s without `*'"), t->name);
5325 }
5326
5327 if (t->opcode_modifier.isprefix
5328 && t->opcode_modifier.ignoresize)
5329 {
5330 /* Warn them that a data or address size prefix doesn't
5331 affect assembly of the next line of code. */
5332 as_warn (_("stand-alone `%s' prefix"), t->name);
5333 }
5334 }
5335
5336 /* Copy the template we found. */
5337 i.tm = *t;
5338
5339 if (addr_prefix_disp != -1)
5340 i.tm.operand_types[addr_prefix_disp]
5341 = operand_types[addr_prefix_disp];
5342
5343 if (found_reverse_match)
5344 {
5345 /* If we found a reverse match we must alter the opcode
5346 direction bit. found_reverse_match holds bits to change
5347 (different for int & float insns). */
5348
5349 i.tm.base_opcode ^= found_reverse_match;
5350
5351 i.tm.operand_types[0] = operand_types[1];
5352 i.tm.operand_types[1] = operand_types[0];
5353 }
5354
5355 return t;
5356 }
5357
5358 static int
5359 check_string (void)
5360 {
5361 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5362 if (i.tm.operand_types[mem_op].bitfield.esseg)
5363 {
5364 if (i.seg[0] != NULL && i.seg[0] != &es)
5365 {
5366 as_bad (_("`%s' operand %d must use `%ses' segment"),
5367 i.tm.name,
5368 mem_op + 1,
5369 register_prefix);
5370 return 0;
5371 }
5372 /* There's only ever one segment override allowed per instruction.
5373 This instruction possibly has a legal segment override on the
5374 second operand, so copy the segment to where non-string
5375 instructions store it, allowing common code. */
5376 i.seg[0] = i.seg[1];
5377 }
5378 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5379 {
5380 if (i.seg[1] != NULL && i.seg[1] != &es)
5381 {
5382 as_bad (_("`%s' operand %d must use `%ses' segment"),
5383 i.tm.name,
5384 mem_op + 2,
5385 register_prefix);
5386 return 0;
5387 }
5388 }
5389 return 1;
5390 }
5391
5392 static int
5393 process_suffix (void)
5394 {
5395 /* If matched instruction specifies an explicit instruction mnemonic
5396 suffix, use it. */
5397 if (i.tm.opcode_modifier.size16)
5398 i.suffix = WORD_MNEM_SUFFIX;
5399 else if (i.tm.opcode_modifier.size32)
5400 i.suffix = LONG_MNEM_SUFFIX;
5401 else if (i.tm.opcode_modifier.size64)
5402 i.suffix = QWORD_MNEM_SUFFIX;
5403 else if (i.reg_operands)
5404 {
5405 /* If there's no instruction mnemonic suffix we try to invent one
5406 based on register operands. */
5407 if (!i.suffix)
5408 {
5409 /* We take i.suffix from the last register operand specified,
5410 Destination register type is more significant than source
5411 register type. crc32 in SSE4.2 prefers source register
5412 type. */
5413 if (i.tm.base_opcode == 0xf20f38f1)
5414 {
5415 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5416 i.suffix = WORD_MNEM_SUFFIX;
5417 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5418 i.suffix = LONG_MNEM_SUFFIX;
5419 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5420 i.suffix = QWORD_MNEM_SUFFIX;
5421 }
5422 else if (i.tm.base_opcode == 0xf20f38f0)
5423 {
5424 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5425 i.suffix = BYTE_MNEM_SUFFIX;
5426 }
5427
5428 if (!i.suffix)
5429 {
5430 int op;
5431
5432 if (i.tm.base_opcode == 0xf20f38f1
5433 || i.tm.base_opcode == 0xf20f38f0)
5434 {
5435 /* We have to know the operand size for crc32. */
5436 as_bad (_("ambiguous memory operand size for `%s`"),
5437 i.tm.name);
5438 return 0;
5439 }
5440
5441 for (op = i.operands; --op >= 0;)
5442 if (!i.tm.operand_types[op].bitfield.inoutportreg
5443 && !i.tm.operand_types[op].bitfield.shiftcount)
5444 {
5445 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5446 {
5447 i.suffix = BYTE_MNEM_SUFFIX;
5448 break;
5449 }
5450 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5451 {
5452 i.suffix = WORD_MNEM_SUFFIX;
5453 break;
5454 }
5455 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5456 {
5457 i.suffix = LONG_MNEM_SUFFIX;
5458 break;
5459 }
5460 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5461 {
5462 i.suffix = QWORD_MNEM_SUFFIX;
5463 break;
5464 }
5465 }
5466 }
5467 }
5468 else if (i.suffix == BYTE_MNEM_SUFFIX)
5469 {
5470 if (intel_syntax
5471 && i.tm.opcode_modifier.ignoresize
5472 && i.tm.opcode_modifier.no_bsuf)
5473 i.suffix = 0;
5474 else if (!check_byte_reg ())
5475 return 0;
5476 }
5477 else if (i.suffix == LONG_MNEM_SUFFIX)
5478 {
5479 if (intel_syntax
5480 && i.tm.opcode_modifier.ignoresize
5481 && i.tm.opcode_modifier.no_lsuf)
5482 i.suffix = 0;
5483 else if (!check_long_reg ())
5484 return 0;
5485 }
5486 else if (i.suffix == QWORD_MNEM_SUFFIX)
5487 {
5488 if (intel_syntax
5489 && i.tm.opcode_modifier.ignoresize
5490 && i.tm.opcode_modifier.no_qsuf)
5491 i.suffix = 0;
5492 else if (!check_qword_reg ())
5493 return 0;
5494 }
5495 else if (i.suffix == WORD_MNEM_SUFFIX)
5496 {
5497 if (intel_syntax
5498 && i.tm.opcode_modifier.ignoresize
5499 && i.tm.opcode_modifier.no_wsuf)
5500 i.suffix = 0;
5501 else if (!check_word_reg ())
5502 return 0;
5503 }
5504 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5505 || i.suffix == YMMWORD_MNEM_SUFFIX
5506 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5507 {
5508 /* Skip if the instruction has x/y/z suffix. match_template
5509 should check if it is a valid suffix. */
5510 }
5511 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5512 /* Do nothing if the instruction is going to ignore the prefix. */
5513 ;
5514 else
5515 abort ();
5516 }
5517 else if (i.tm.opcode_modifier.defaultsize
5518 && !i.suffix
5519 /* exclude fldenv/frstor/fsave/fstenv */
5520 && i.tm.opcode_modifier.no_ssuf)
5521 {
5522 i.suffix = stackop_size;
5523 }
5524 else if (intel_syntax
5525 && !i.suffix
5526 && (i.tm.operand_types[0].bitfield.jumpabsolute
5527 || i.tm.opcode_modifier.jumpbyte
5528 || i.tm.opcode_modifier.jumpintersegment
5529 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5530 && i.tm.extension_opcode <= 3)))
5531 {
5532 switch (flag_code)
5533 {
5534 case CODE_64BIT:
5535 if (!i.tm.opcode_modifier.no_qsuf)
5536 {
5537 i.suffix = QWORD_MNEM_SUFFIX;
5538 break;
5539 }
5540 /* Fall through. */
5541 case CODE_32BIT:
5542 if (!i.tm.opcode_modifier.no_lsuf)
5543 i.suffix = LONG_MNEM_SUFFIX;
5544 break;
5545 case CODE_16BIT:
5546 if (!i.tm.opcode_modifier.no_wsuf)
5547 i.suffix = WORD_MNEM_SUFFIX;
5548 break;
5549 }
5550 }
5551
5552 if (!i.suffix)
5553 {
5554 if (!intel_syntax)
5555 {
5556 if (i.tm.opcode_modifier.w)
5557 {
5558 as_bad (_("no instruction mnemonic suffix given and "
5559 "no register operands; can't size instruction"));
5560 return 0;
5561 }
5562 }
5563 else
5564 {
5565 unsigned int suffixes;
5566
5567 suffixes = !i.tm.opcode_modifier.no_bsuf;
5568 if (!i.tm.opcode_modifier.no_wsuf)
5569 suffixes |= 1 << 1;
5570 if (!i.tm.opcode_modifier.no_lsuf)
5571 suffixes |= 1 << 2;
5572 if (!i.tm.opcode_modifier.no_ldsuf)
5573 suffixes |= 1 << 3;
5574 if (!i.tm.opcode_modifier.no_ssuf)
5575 suffixes |= 1 << 4;
5576 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5577 suffixes |= 1 << 5;
5578
5579 /* There are more than suffix matches. */
5580 if (i.tm.opcode_modifier.w
5581 || ((suffixes & (suffixes - 1))
5582 && !i.tm.opcode_modifier.defaultsize
5583 && !i.tm.opcode_modifier.ignoresize))
5584 {
5585 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5586 return 0;
5587 }
5588 }
5589 }
5590
5591 /* Change the opcode based on the operand size given by i.suffix;
5592 We don't need to change things for byte insns. */
5593
5594 if (i.suffix
5595 && i.suffix != BYTE_MNEM_SUFFIX
5596 && i.suffix != XMMWORD_MNEM_SUFFIX
5597 && i.suffix != YMMWORD_MNEM_SUFFIX
5598 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5599 {
5600 /* It's not a byte, select word/dword operation. */
5601 if (i.tm.opcode_modifier.w)
5602 {
5603 if (i.tm.opcode_modifier.shortform)
5604 i.tm.base_opcode |= 8;
5605 else
5606 i.tm.base_opcode |= 1;
5607 }
5608
5609 /* Now select between word & dword operations via the operand
5610 size prefix, except for instructions that will ignore this
5611 prefix anyway. */
5612 if (i.tm.opcode_modifier.addrprefixop0)
5613 {
5614 /* The address size override prefix changes the size of the
5615 first operand. */
5616 if ((flag_code == CODE_32BIT
5617 && i.op->regs[0].reg_type.bitfield.word)
5618 || (flag_code != CODE_32BIT
5619 && i.op->regs[0].reg_type.bitfield.dword))
5620 if (!add_prefix (ADDR_PREFIX_OPCODE))
5621 return 0;
5622 }
5623 else if (i.suffix != QWORD_MNEM_SUFFIX
5624 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5625 && !i.tm.opcode_modifier.ignoresize
5626 && !i.tm.opcode_modifier.floatmf
5627 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5628 || (flag_code == CODE_64BIT
5629 && i.tm.opcode_modifier.jumpbyte)))
5630 {
5631 unsigned int prefix = DATA_PREFIX_OPCODE;
5632
5633 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5634 prefix = ADDR_PREFIX_OPCODE;
5635
5636 if (!add_prefix (prefix))
5637 return 0;
5638 }
5639
5640 /* Set mode64 for an operand. */
5641 if (i.suffix == QWORD_MNEM_SUFFIX
5642 && flag_code == CODE_64BIT
5643 && !i.tm.opcode_modifier.norex64)
5644 {
5645 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5646 need rex64. cmpxchg8b is also a special case. */
5647 if (! (i.operands == 2
5648 && i.tm.base_opcode == 0x90
5649 && i.tm.extension_opcode == None
5650 && operand_type_equal (&i.types [0], &acc64)
5651 && operand_type_equal (&i.types [1], &acc64))
5652 && ! (i.operands == 1
5653 && i.tm.base_opcode == 0xfc7
5654 && i.tm.extension_opcode == 1
5655 && !operand_type_check (i.types [0], reg)
5656 && operand_type_check (i.types [0], anymem)))
5657 i.rex |= REX_W;
5658 }
5659
5660 /* Size floating point instruction. */
5661 if (i.suffix == LONG_MNEM_SUFFIX)
5662 if (i.tm.opcode_modifier.floatmf)
5663 i.tm.base_opcode ^= 4;
5664 }
5665
5666 return 1;
5667 }
5668
5669 static int
5670 check_byte_reg (void)
5671 {
5672 int op;
5673
5674 for (op = i.operands; --op >= 0;)
5675 {
5676 /* Skip non-register operands. */
5677 if (!i.types[op].bitfield.reg)
5678 continue;
5679
5680 /* If this is an eight bit register, it's OK. If it's the 16 or
5681 32 bit version of an eight bit register, we will just use the
5682 low portion, and that's OK too. */
5683 if (i.types[op].bitfield.byte)
5684 continue;
5685
5686 /* I/O port address operands are OK too. */
5687 if (i.tm.operand_types[op].bitfield.inoutportreg)
5688 continue;
5689
5690 /* crc32 doesn't generate this warning. */
5691 if (i.tm.base_opcode == 0xf20f38f0)
5692 continue;
5693
5694 if ((i.types[op].bitfield.word
5695 || i.types[op].bitfield.dword
5696 || i.types[op].bitfield.qword)
5697 && i.op[op].regs->reg_num < 4
5698 /* Prohibit these changes in 64bit mode, since the lowering
5699 would be more complicated. */
5700 && flag_code != CODE_64BIT)
5701 {
5702 #if REGISTER_WARNINGS
5703 if (!quiet_warnings)
5704 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5705 register_prefix,
5706 (i.op[op].regs + (i.types[op].bitfield.word
5707 ? REGNAM_AL - REGNAM_AX
5708 : REGNAM_AL - REGNAM_EAX))->reg_name,
5709 register_prefix,
5710 i.op[op].regs->reg_name,
5711 i.suffix);
5712 #endif
5713 continue;
5714 }
5715 /* Any other register is bad. */
5716 if (i.types[op].bitfield.reg
5717 || i.types[op].bitfield.regmmx
5718 || i.types[op].bitfield.regsimd
5719 || i.types[op].bitfield.sreg2
5720 || i.types[op].bitfield.sreg3
5721 || i.types[op].bitfield.control
5722 || i.types[op].bitfield.debug
5723 || i.types[op].bitfield.test)
5724 {
5725 as_bad (_("`%s%s' not allowed with `%s%c'"),
5726 register_prefix,
5727 i.op[op].regs->reg_name,
5728 i.tm.name,
5729 i.suffix);
5730 return 0;
5731 }
5732 }
5733 return 1;
5734 }
5735
5736 static int
5737 check_long_reg (void)
5738 {
5739 int op;
5740
5741 for (op = i.operands; --op >= 0;)
5742 /* Skip non-register operands. */
5743 if (!i.types[op].bitfield.reg)
5744 continue;
5745 /* Reject eight bit registers, except where the template requires
5746 them. (eg. movzb) */
5747 else if (i.types[op].bitfield.byte
5748 && (i.tm.operand_types[op].bitfield.reg
5749 || i.tm.operand_types[op].bitfield.acc)
5750 && (i.tm.operand_types[op].bitfield.word
5751 || i.tm.operand_types[op].bitfield.dword))
5752 {
5753 as_bad (_("`%s%s' not allowed with `%s%c'"),
5754 register_prefix,
5755 i.op[op].regs->reg_name,
5756 i.tm.name,
5757 i.suffix);
5758 return 0;
5759 }
5760 /* Warn if the e prefix on a general reg is missing. */
5761 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5762 && i.types[op].bitfield.word
5763 && (i.tm.operand_types[op].bitfield.reg
5764 || i.tm.operand_types[op].bitfield.acc)
5765 && i.tm.operand_types[op].bitfield.dword)
5766 {
5767 /* Prohibit these changes in the 64bit mode, since the
5768 lowering is more complicated. */
5769 if (flag_code == CODE_64BIT)
5770 {
5771 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5772 register_prefix, i.op[op].regs->reg_name,
5773 i.suffix);
5774 return 0;
5775 }
5776 #if REGISTER_WARNINGS
5777 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5778 register_prefix,
5779 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5780 register_prefix, i.op[op].regs->reg_name, i.suffix);
5781 #endif
5782 }
5783 /* Warn if the r prefix on a general reg is present. */
5784 else if (i.types[op].bitfield.qword
5785 && (i.tm.operand_types[op].bitfield.reg
5786 || i.tm.operand_types[op].bitfield.acc)
5787 && i.tm.operand_types[op].bitfield.dword)
5788 {
5789 if (intel_syntax
5790 && i.tm.opcode_modifier.toqword
5791 && !i.types[0].bitfield.regsimd)
5792 {
5793 /* Convert to QWORD. We want REX byte. */
5794 i.suffix = QWORD_MNEM_SUFFIX;
5795 }
5796 else
5797 {
5798 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5799 register_prefix, i.op[op].regs->reg_name,
5800 i.suffix);
5801 return 0;
5802 }
5803 }
5804 return 1;
5805 }
5806
5807 static int
5808 check_qword_reg (void)
5809 {
5810 int op;
5811
5812 for (op = i.operands; --op >= 0; )
5813 /* Skip non-register operands. */
5814 if (!i.types[op].bitfield.reg)
5815 continue;
5816 /* Reject eight bit registers, except where the template requires
5817 them. (eg. movzb) */
5818 else if (i.types[op].bitfield.byte
5819 && (i.tm.operand_types[op].bitfield.reg
5820 || i.tm.operand_types[op].bitfield.acc)
5821 && (i.tm.operand_types[op].bitfield.word
5822 || i.tm.operand_types[op].bitfield.dword))
5823 {
5824 as_bad (_("`%s%s' not allowed with `%s%c'"),
5825 register_prefix,
5826 i.op[op].regs->reg_name,
5827 i.tm.name,
5828 i.suffix);
5829 return 0;
5830 }
5831 /* Warn if the r prefix on a general reg is missing. */
5832 else if ((i.types[op].bitfield.word
5833 || i.types[op].bitfield.dword)
5834 && (i.tm.operand_types[op].bitfield.reg
5835 || i.tm.operand_types[op].bitfield.acc)
5836 && i.tm.operand_types[op].bitfield.qword)
5837 {
5838 /* Prohibit these changes in the 64bit mode, since the
5839 lowering is more complicated. */
5840 if (intel_syntax
5841 && i.tm.opcode_modifier.todword
5842 && !i.types[0].bitfield.regsimd)
5843 {
5844 /* Convert to DWORD. We don't want REX byte. */
5845 i.suffix = LONG_MNEM_SUFFIX;
5846 }
5847 else
5848 {
5849 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5850 register_prefix, i.op[op].regs->reg_name,
5851 i.suffix);
5852 return 0;
5853 }
5854 }
5855 return 1;
5856 }
5857
5858 static int
5859 check_word_reg (void)
5860 {
5861 int op;
5862 for (op = i.operands; --op >= 0;)
5863 /* Skip non-register operands. */
5864 if (!i.types[op].bitfield.reg)
5865 continue;
5866 /* Reject eight bit registers, except where the template requires
5867 them. (eg. movzb) */
5868 else if (i.types[op].bitfield.byte
5869 && (i.tm.operand_types[op].bitfield.reg
5870 || i.tm.operand_types[op].bitfield.acc)
5871 && (i.tm.operand_types[op].bitfield.word
5872 || i.tm.operand_types[op].bitfield.dword))
5873 {
5874 as_bad (_("`%s%s' not allowed with `%s%c'"),
5875 register_prefix,
5876 i.op[op].regs->reg_name,
5877 i.tm.name,
5878 i.suffix);
5879 return 0;
5880 }
5881 /* Warn if the e or r prefix on a general reg is present. */
5882 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5883 && (i.types[op].bitfield.dword
5884 || i.types[op].bitfield.qword)
5885 && (i.tm.operand_types[op].bitfield.reg
5886 || i.tm.operand_types[op].bitfield.acc)
5887 && i.tm.operand_types[op].bitfield.word)
5888 {
5889 /* Prohibit these changes in the 64bit mode, since the
5890 lowering is more complicated. */
5891 if (flag_code == CODE_64BIT)
5892 {
5893 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5894 register_prefix, i.op[op].regs->reg_name,
5895 i.suffix);
5896 return 0;
5897 }
5898 #if REGISTER_WARNINGS
5899 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5900 register_prefix,
5901 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5902 register_prefix, i.op[op].regs->reg_name, i.suffix);
5903 #endif
5904 }
5905 return 1;
5906 }
5907
5908 static int
5909 update_imm (unsigned int j)
5910 {
5911 i386_operand_type overlap = i.types[j];
5912 if ((overlap.bitfield.imm8
5913 || overlap.bitfield.imm8s
5914 || overlap.bitfield.imm16
5915 || overlap.bitfield.imm32
5916 || overlap.bitfield.imm32s
5917 || overlap.bitfield.imm64)
5918 && !operand_type_equal (&overlap, &imm8)
5919 && !operand_type_equal (&overlap, &imm8s)
5920 && !operand_type_equal (&overlap, &imm16)
5921 && !operand_type_equal (&overlap, &imm32)
5922 && !operand_type_equal (&overlap, &imm32s)
5923 && !operand_type_equal (&overlap, &imm64))
5924 {
5925 if (i.suffix)
5926 {
5927 i386_operand_type temp;
5928
5929 operand_type_set (&temp, 0);
5930 if (i.suffix == BYTE_MNEM_SUFFIX)
5931 {
5932 temp.bitfield.imm8 = overlap.bitfield.imm8;
5933 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5934 }
5935 else if (i.suffix == WORD_MNEM_SUFFIX)
5936 temp.bitfield.imm16 = overlap.bitfield.imm16;
5937 else if (i.suffix == QWORD_MNEM_SUFFIX)
5938 {
5939 temp.bitfield.imm64 = overlap.bitfield.imm64;
5940 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5941 }
5942 else
5943 temp.bitfield.imm32 = overlap.bitfield.imm32;
5944 overlap = temp;
5945 }
5946 else if (operand_type_equal (&overlap, &imm16_32_32s)
5947 || operand_type_equal (&overlap, &imm16_32)
5948 || operand_type_equal (&overlap, &imm16_32s))
5949 {
5950 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5951 overlap = imm16;
5952 else
5953 overlap = imm32s;
5954 }
5955 if (!operand_type_equal (&overlap, &imm8)
5956 && !operand_type_equal (&overlap, &imm8s)
5957 && !operand_type_equal (&overlap, &imm16)
5958 && !operand_type_equal (&overlap, &imm32)
5959 && !operand_type_equal (&overlap, &imm32s)
5960 && !operand_type_equal (&overlap, &imm64))
5961 {
5962 as_bad (_("no instruction mnemonic suffix given; "
5963 "can't determine immediate size"));
5964 return 0;
5965 }
5966 }
5967 i.types[j] = overlap;
5968
5969 return 1;
5970 }
5971
5972 static int
5973 finalize_imm (void)
5974 {
5975 unsigned int j, n;
5976
5977 /* Update the first 2 immediate operands. */
5978 n = i.operands > 2 ? 2 : i.operands;
5979 if (n)
5980 {
5981 for (j = 0; j < n; j++)
5982 if (update_imm (j) == 0)
5983 return 0;
5984
5985 /* The 3rd operand can't be immediate operand. */
5986 gas_assert (operand_type_check (i.types[2], imm) == 0);
5987 }
5988
5989 return 1;
5990 }
5991
5992 static int
5993 process_operands (void)
5994 {
5995 /* Default segment register this instruction will use for memory
5996 accesses. 0 means unknown. This is only for optimizing out
5997 unnecessary segment overrides. */
5998 const seg_entry *default_seg = 0;
5999
6000 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6001 {
6002 unsigned int dupl = i.operands;
6003 unsigned int dest = dupl - 1;
6004 unsigned int j;
6005
6006 /* The destination must be an xmm register. */
6007 gas_assert (i.reg_operands
6008 && MAX_OPERANDS > dupl
6009 && operand_type_equal (&i.types[dest], &regxmm));
6010
6011 if (i.tm.operand_types[0].bitfield.acc
6012 && i.tm.operand_types[0].bitfield.xmmword)
6013 {
6014 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6015 {
6016 /* Keep xmm0 for instructions with VEX prefix and 3
6017 sources. */
6018 i.tm.operand_types[0].bitfield.acc = 0;
6019 i.tm.operand_types[0].bitfield.regsimd = 1;
6020 goto duplicate;
6021 }
6022 else
6023 {
6024 /* We remove the first xmm0 and keep the number of
6025 operands unchanged, which in fact duplicates the
6026 destination. */
6027 for (j = 1; j < i.operands; j++)
6028 {
6029 i.op[j - 1] = i.op[j];
6030 i.types[j - 1] = i.types[j];
6031 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6032 }
6033 }
6034 }
6035 else if (i.tm.opcode_modifier.implicit1stxmm0)
6036 {
6037 gas_assert ((MAX_OPERANDS - 1) > dupl
6038 && (i.tm.opcode_modifier.vexsources
6039 == VEX3SOURCES));
6040
6041 /* Add the implicit xmm0 for instructions with VEX prefix
6042 and 3 sources. */
6043 for (j = i.operands; j > 0; j--)
6044 {
6045 i.op[j] = i.op[j - 1];
6046 i.types[j] = i.types[j - 1];
6047 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6048 }
6049 i.op[0].regs
6050 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6051 i.types[0] = regxmm;
6052 i.tm.operand_types[0] = regxmm;
6053
6054 i.operands += 2;
6055 i.reg_operands += 2;
6056 i.tm.operands += 2;
6057
6058 dupl++;
6059 dest++;
6060 i.op[dupl] = i.op[dest];
6061 i.types[dupl] = i.types[dest];
6062 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6063 }
6064 else
6065 {
6066 duplicate:
6067 i.operands++;
6068 i.reg_operands++;
6069 i.tm.operands++;
6070
6071 i.op[dupl] = i.op[dest];
6072 i.types[dupl] = i.types[dest];
6073 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6074 }
6075
6076 if (i.tm.opcode_modifier.immext)
6077 process_immext ();
6078 }
6079 else if (i.tm.operand_types[0].bitfield.acc
6080 && i.tm.operand_types[0].bitfield.xmmword)
6081 {
6082 unsigned int j;
6083
6084 for (j = 1; j < i.operands; j++)
6085 {
6086 i.op[j - 1] = i.op[j];
6087 i.types[j - 1] = i.types[j];
6088
6089 /* We need to adjust fields in i.tm since they are used by
6090 build_modrm_byte. */
6091 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6092 }
6093
6094 i.operands--;
6095 i.reg_operands--;
6096 i.tm.operands--;
6097 }
6098 else if (i.tm.opcode_modifier.implicitquadgroup)
6099 {
6100 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6101 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6102 unsigned int regnum = register_number (i.op[1].regs);
6103 unsigned int first_reg_in_group = regnum & ~3;
6104 unsigned int last_reg_in_group = first_reg_in_group + 3;
6105 if (regnum != first_reg_in_group) {
6106 as_warn (_("the second source register `%s%s' implicitly denotes"
6107 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6108 register_prefix, i.op[1].regs->reg_name,
6109 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6110 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6111 i.tm.name);
6112 }
6113 }
6114 else if (i.tm.opcode_modifier.regkludge)
6115 {
6116 /* The imul $imm, %reg instruction is converted into
6117 imul $imm, %reg, %reg, and the clr %reg instruction
6118 is converted into xor %reg, %reg. */
6119
6120 unsigned int first_reg_op;
6121
6122 if (operand_type_check (i.types[0], reg))
6123 first_reg_op = 0;
6124 else
6125 first_reg_op = 1;
6126 /* Pretend we saw the extra register operand. */
6127 gas_assert (i.reg_operands == 1
6128 && i.op[first_reg_op + 1].regs == 0);
6129 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6130 i.types[first_reg_op + 1] = i.types[first_reg_op];
6131 i.operands++;
6132 i.reg_operands++;
6133 }
6134
6135 if (i.tm.opcode_modifier.shortform)
6136 {
6137 if (i.types[0].bitfield.sreg2
6138 || i.types[0].bitfield.sreg3)
6139 {
6140 if (i.tm.base_opcode == POP_SEG_SHORT
6141 && i.op[0].regs->reg_num == 1)
6142 {
6143 as_bad (_("you can't `pop %scs'"), register_prefix);
6144 return 0;
6145 }
6146 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6147 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6148 i.rex |= REX_B;
6149 }
6150 else
6151 {
6152 /* The register or float register operand is in operand
6153 0 or 1. */
6154 unsigned int op;
6155
6156 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6157 || operand_type_check (i.types[0], reg))
6158 op = 0;
6159 else
6160 op = 1;
6161 /* Register goes in low 3 bits of opcode. */
6162 i.tm.base_opcode |= i.op[op].regs->reg_num;
6163 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6164 i.rex |= REX_B;
6165 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6166 {
6167 /* Warn about some common errors, but press on regardless.
6168 The first case can be generated by gcc (<= 2.8.1). */
6169 if (i.operands == 2)
6170 {
6171 /* Reversed arguments on faddp, fsubp, etc. */
6172 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6173 register_prefix, i.op[!intel_syntax].regs->reg_name,
6174 register_prefix, i.op[intel_syntax].regs->reg_name);
6175 }
6176 else
6177 {
6178 /* Extraneous `l' suffix on fp insn. */
6179 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6180 register_prefix, i.op[0].regs->reg_name);
6181 }
6182 }
6183 }
6184 }
6185 else if (i.tm.opcode_modifier.modrm)
6186 {
6187 /* The opcode is completed (modulo i.tm.extension_opcode which
6188 must be put into the modrm byte). Now, we make the modrm and
6189 index base bytes based on all the info we've collected. */
6190
6191 default_seg = build_modrm_byte ();
6192 }
6193 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6194 {
6195 default_seg = &ds;
6196 }
6197 else if (i.tm.opcode_modifier.isstring)
6198 {
6199 /* For the string instructions that allow a segment override
6200 on one of their operands, the default segment is ds. */
6201 default_seg = &ds;
6202 }
6203
6204 if (i.tm.base_opcode == 0x8d /* lea */
6205 && i.seg[0]
6206 && !quiet_warnings)
6207 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6208
6209 /* If a segment was explicitly specified, and the specified segment
6210 is not the default, use an opcode prefix to select it. If we
6211 never figured out what the default segment is, then default_seg
6212 will be zero at this point, and the specified segment prefix will
6213 always be used. */
6214 if ((i.seg[0]) && (i.seg[0] != default_seg))
6215 {
6216 if (!add_prefix (i.seg[0]->seg_prefix))
6217 return 0;
6218 }
6219 return 1;
6220 }
6221
6222 static const seg_entry *
6223 build_modrm_byte (void)
6224 {
6225 const seg_entry *default_seg = 0;
6226 unsigned int source, dest;
6227 int vex_3_sources;
6228
6229 /* The first operand of instructions with VEX prefix and 3 sources
6230 must be VEX_Imm4. */
6231 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6232 if (vex_3_sources)
6233 {
6234 unsigned int nds, reg_slot;
6235 expressionS *exp;
6236
6237 if (i.tm.opcode_modifier.veximmext
6238 && i.tm.opcode_modifier.immext)
6239 {
6240 dest = i.operands - 2;
6241 gas_assert (dest == 3);
6242 }
6243 else
6244 dest = i.operands - 1;
6245 nds = dest - 1;
6246
6247 /* There are 2 kinds of instructions:
6248 1. 5 operands: 4 register operands or 3 register operands
6249 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6250 VexW0 or VexW1. The destination must be either XMM, YMM or
6251 ZMM register.
6252 2. 4 operands: 4 register operands or 3 register operands
6253 plus 1 memory operand, VexXDS, and VexImmExt */
6254 gas_assert ((i.reg_operands == 4
6255 || (i.reg_operands == 3 && i.mem_operands == 1))
6256 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6257 && (i.tm.opcode_modifier.veximmext
6258 || (i.imm_operands == 1
6259 && i.types[0].bitfield.vec_imm4
6260 && (i.tm.opcode_modifier.vexw == VEXW0
6261 || i.tm.opcode_modifier.vexw == VEXW1)
6262 && i.tm.operand_types[dest].bitfield.regsimd)));
6263
6264 if (i.imm_operands == 0)
6265 {
6266 /* When there is no immediate operand, generate an 8bit
6267 immediate operand to encode the first operand. */
6268 exp = &im_expressions[i.imm_operands++];
6269 i.op[i.operands].imms = exp;
6270 i.types[i.operands] = imm8;
6271 i.operands++;
6272 /* If VexW1 is set, the first operand is the source and
6273 the second operand is encoded in the immediate operand. */
6274 if (i.tm.opcode_modifier.vexw == VEXW1)
6275 {
6276 source = 0;
6277 reg_slot = 1;
6278 }
6279 else
6280 {
6281 source = 1;
6282 reg_slot = 0;
6283 }
6284
6285 /* FMA swaps REG and NDS. */
6286 if (i.tm.cpu_flags.bitfield.cpufma)
6287 {
6288 unsigned int tmp;
6289 tmp = reg_slot;
6290 reg_slot = nds;
6291 nds = tmp;
6292 }
6293
6294 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6295 exp->X_op = O_constant;
6296 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6297 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6298 }
6299 else
6300 {
6301 unsigned int imm_slot;
6302
6303 if (i.tm.opcode_modifier.vexw == VEXW0)
6304 {
6305 /* If VexW0 is set, the third operand is the source and
6306 the second operand is encoded in the immediate
6307 operand. */
6308 source = 2;
6309 reg_slot = 1;
6310 }
6311 else
6312 {
6313 /* VexW1 is set, the second operand is the source and
6314 the third operand is encoded in the immediate
6315 operand. */
6316 source = 1;
6317 reg_slot = 2;
6318 }
6319
6320 if (i.tm.opcode_modifier.immext)
6321 {
6322 /* When ImmExt is set, the immediate byte is the last
6323 operand. */
6324 imm_slot = i.operands - 1;
6325 source--;
6326 reg_slot--;
6327 }
6328 else
6329 {
6330 imm_slot = 0;
6331
6332 /* Turn on Imm8 so that output_imm will generate it. */
6333 i.types[imm_slot].bitfield.imm8 = 1;
6334 }
6335
6336 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6337 i.op[imm_slot].imms->X_add_number
6338 |= register_number (i.op[reg_slot].regs) << 4;
6339 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6340 }
6341
6342 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6343 i.vex.register_specifier = i.op[nds].regs;
6344 }
6345 else
6346 source = dest = 0;
6347
6348 /* i.reg_operands MUST be the number of real register operands;
6349 implicit registers do not count. If there are 3 register
6350 operands, it must be a instruction with VexNDS. For a
6351 instruction with VexNDD, the destination register is encoded
6352 in VEX prefix. If there are 4 register operands, it must be
6353 a instruction with VEX prefix and 3 sources. */
6354 if (i.mem_operands == 0
6355 && ((i.reg_operands == 2
6356 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6357 || (i.reg_operands == 3
6358 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6359 || (i.reg_operands == 4 && vex_3_sources)))
6360 {
6361 switch (i.operands)
6362 {
6363 case 2:
6364 source = 0;
6365 break;
6366 case 3:
6367 /* When there are 3 operands, one of them may be immediate,
6368 which may be the first or the last operand. Otherwise,
6369 the first operand must be shift count register (cl) or it
6370 is an instruction with VexNDS. */
6371 gas_assert (i.imm_operands == 1
6372 || (i.imm_operands == 0
6373 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6374 || i.types[0].bitfield.shiftcount)));
6375 if (operand_type_check (i.types[0], imm)
6376 || i.types[0].bitfield.shiftcount)
6377 source = 1;
6378 else
6379 source = 0;
6380 break;
6381 case 4:
6382 /* When there are 4 operands, the first two must be 8bit
6383 immediate operands. The source operand will be the 3rd
6384 one.
6385
6386 For instructions with VexNDS, if the first operand
6387 an imm8, the source operand is the 2nd one. If the last
6388 operand is imm8, the source operand is the first one. */
6389 gas_assert ((i.imm_operands == 2
6390 && i.types[0].bitfield.imm8
6391 && i.types[1].bitfield.imm8)
6392 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6393 && i.imm_operands == 1
6394 && (i.types[0].bitfield.imm8
6395 || i.types[i.operands - 1].bitfield.imm8
6396 || i.rounding)));
6397 if (i.imm_operands == 2)
6398 source = 2;
6399 else
6400 {
6401 if (i.types[0].bitfield.imm8)
6402 source = 1;
6403 else
6404 source = 0;
6405 }
6406 break;
6407 case 5:
6408 if (i.tm.opcode_modifier.evex)
6409 {
6410 /* For EVEX instructions, when there are 5 operands, the
6411 first one must be immediate operand. If the second one
6412 is immediate operand, the source operand is the 3th
6413 one. If the last one is immediate operand, the source
6414 operand is the 2nd one. */
6415 gas_assert (i.imm_operands == 2
6416 && i.tm.opcode_modifier.sae
6417 && operand_type_check (i.types[0], imm));
6418 if (operand_type_check (i.types[1], imm))
6419 source = 2;
6420 else if (operand_type_check (i.types[4], imm))
6421 source = 1;
6422 else
6423 abort ();
6424 }
6425 break;
6426 default:
6427 abort ();
6428 }
6429
6430 if (!vex_3_sources)
6431 {
6432 dest = source + 1;
6433
6434 /* RC/SAE operand could be between DEST and SRC. That happens
6435 when one operand is GPR and the other one is XMM/YMM/ZMM
6436 register. */
6437 if (i.rounding && i.rounding->operand == (int) dest)
6438 dest++;
6439
6440 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6441 {
6442 /* For instructions with VexNDS, the register-only source
6443 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6444 register. It is encoded in VEX prefix. We need to
6445 clear RegMem bit before calling operand_type_equal. */
6446
6447 i386_operand_type op;
6448 unsigned int vvvv;
6449
6450 /* Check register-only source operand when two source
6451 operands are swapped. */
6452 if (!i.tm.operand_types[source].bitfield.baseindex
6453 && i.tm.operand_types[dest].bitfield.baseindex)
6454 {
6455 vvvv = source;
6456 source = dest;
6457 }
6458 else
6459 vvvv = dest;
6460
6461 op = i.tm.operand_types[vvvv];
6462 op.bitfield.regmem = 0;
6463 if ((dest + 1) >= i.operands
6464 || ((!op.bitfield.reg
6465 || (!op.bitfield.dword && !op.bitfield.qword))
6466 && !op.bitfield.regsimd
6467 && !operand_type_equal (&op, &regmask)))
6468 abort ();
6469 i.vex.register_specifier = i.op[vvvv].regs;
6470 dest++;
6471 }
6472 }
6473
6474 i.rm.mode = 3;
6475 /* One of the register operands will be encoded in the i.tm.reg
6476 field, the other in the combined i.tm.mode and i.tm.regmem
6477 fields. If no form of this instruction supports a memory
6478 destination operand, then we assume the source operand may
6479 sometimes be a memory operand and so we need to store the
6480 destination in the i.rm.reg field. */
6481 if (!i.tm.operand_types[dest].bitfield.regmem
6482 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6483 {
6484 i.rm.reg = i.op[dest].regs->reg_num;
6485 i.rm.regmem = i.op[source].regs->reg_num;
6486 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6487 i.rex |= REX_R;
6488 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6489 i.vrex |= REX_R;
6490 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6491 i.rex |= REX_B;
6492 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6493 i.vrex |= REX_B;
6494 }
6495 else
6496 {
6497 i.rm.reg = i.op[source].regs->reg_num;
6498 i.rm.regmem = i.op[dest].regs->reg_num;
6499 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6500 i.rex |= REX_B;
6501 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6502 i.vrex |= REX_B;
6503 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6504 i.rex |= REX_R;
6505 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6506 i.vrex |= REX_R;
6507 }
6508 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6509 {
6510 if (!i.types[0].bitfield.control
6511 && !i.types[1].bitfield.control)
6512 abort ();
6513 i.rex &= ~(REX_R | REX_B);
6514 add_prefix (LOCK_PREFIX_OPCODE);
6515 }
6516 }
6517 else
6518 { /* If it's not 2 reg operands... */
6519 unsigned int mem;
6520
6521 if (i.mem_operands)
6522 {
6523 unsigned int fake_zero_displacement = 0;
6524 unsigned int op;
6525
6526 for (op = 0; op < i.operands; op++)
6527 if (operand_type_check (i.types[op], anymem))
6528 break;
6529 gas_assert (op < i.operands);
6530
6531 if (i.tm.opcode_modifier.vecsib)
6532 {
6533 if (i.index_reg->reg_num == RegEiz
6534 || i.index_reg->reg_num == RegRiz)
6535 abort ();
6536
6537 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6538 if (!i.base_reg)
6539 {
6540 i.sib.base = NO_BASE_REGISTER;
6541 i.sib.scale = i.log2_scale_factor;
6542 i.types[op].bitfield.disp8 = 0;
6543 i.types[op].bitfield.disp16 = 0;
6544 i.types[op].bitfield.disp64 = 0;
6545 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6546 {
6547 /* Must be 32 bit */
6548 i.types[op].bitfield.disp32 = 1;
6549 i.types[op].bitfield.disp32s = 0;
6550 }
6551 else
6552 {
6553 i.types[op].bitfield.disp32 = 0;
6554 i.types[op].bitfield.disp32s = 1;
6555 }
6556 }
6557 i.sib.index = i.index_reg->reg_num;
6558 if ((i.index_reg->reg_flags & RegRex) != 0)
6559 i.rex |= REX_X;
6560 if ((i.index_reg->reg_flags & RegVRex) != 0)
6561 i.vrex |= REX_X;
6562 }
6563
6564 default_seg = &ds;
6565
6566 if (i.base_reg == 0)
6567 {
6568 i.rm.mode = 0;
6569 if (!i.disp_operands)
6570 fake_zero_displacement = 1;
6571 if (i.index_reg == 0)
6572 {
6573 gas_assert (!i.tm.opcode_modifier.vecsib);
6574 /* Operand is just <disp> */
6575 if (flag_code == CODE_64BIT)
6576 {
6577 /* 64bit mode overwrites the 32bit absolute
6578 addressing by RIP relative addressing and
6579 absolute addressing is encoded by one of the
6580 redundant SIB forms. */
6581 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6582 i.sib.base = NO_BASE_REGISTER;
6583 i.sib.index = NO_INDEX_REGISTER;
6584 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6585 ? disp32s : disp32);
6586 }
6587 else if ((flag_code == CODE_16BIT)
6588 ^ (i.prefix[ADDR_PREFIX] != 0))
6589 {
6590 i.rm.regmem = NO_BASE_REGISTER_16;
6591 i.types[op] = disp16;
6592 }
6593 else
6594 {
6595 i.rm.regmem = NO_BASE_REGISTER;
6596 i.types[op] = disp32;
6597 }
6598 }
6599 else if (!i.tm.opcode_modifier.vecsib)
6600 {
6601 /* !i.base_reg && i.index_reg */
6602 if (i.index_reg->reg_num == RegEiz
6603 || i.index_reg->reg_num == RegRiz)
6604 i.sib.index = NO_INDEX_REGISTER;
6605 else
6606 i.sib.index = i.index_reg->reg_num;
6607 i.sib.base = NO_BASE_REGISTER;
6608 i.sib.scale = i.log2_scale_factor;
6609 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6610 i.types[op].bitfield.disp8 = 0;
6611 i.types[op].bitfield.disp16 = 0;
6612 i.types[op].bitfield.disp64 = 0;
6613 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6614 {
6615 /* Must be 32 bit */
6616 i.types[op].bitfield.disp32 = 1;
6617 i.types[op].bitfield.disp32s = 0;
6618 }
6619 else
6620 {
6621 i.types[op].bitfield.disp32 = 0;
6622 i.types[op].bitfield.disp32s = 1;
6623 }
6624 if ((i.index_reg->reg_flags & RegRex) != 0)
6625 i.rex |= REX_X;
6626 }
6627 }
6628 /* RIP addressing for 64bit mode. */
6629 else if (i.base_reg->reg_num == RegRip ||
6630 i.base_reg->reg_num == RegEip)
6631 {
6632 gas_assert (!i.tm.opcode_modifier.vecsib);
6633 i.rm.regmem = NO_BASE_REGISTER;
6634 i.types[op].bitfield.disp8 = 0;
6635 i.types[op].bitfield.disp16 = 0;
6636 i.types[op].bitfield.disp32 = 0;
6637 i.types[op].bitfield.disp32s = 1;
6638 i.types[op].bitfield.disp64 = 0;
6639 i.flags[op] |= Operand_PCrel;
6640 if (! i.disp_operands)
6641 fake_zero_displacement = 1;
6642 }
6643 else if (i.base_reg->reg_type.bitfield.word)
6644 {
6645 gas_assert (!i.tm.opcode_modifier.vecsib);
6646 switch (i.base_reg->reg_num)
6647 {
6648 case 3: /* (%bx) */
6649 if (i.index_reg == 0)
6650 i.rm.regmem = 7;
6651 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6652 i.rm.regmem = i.index_reg->reg_num - 6;
6653 break;
6654 case 5: /* (%bp) */
6655 default_seg = &ss;
6656 if (i.index_reg == 0)
6657 {
6658 i.rm.regmem = 6;
6659 if (operand_type_check (i.types[op], disp) == 0)
6660 {
6661 /* fake (%bp) into 0(%bp) */
6662 i.types[op].bitfield.disp8 = 1;
6663 fake_zero_displacement = 1;
6664 }
6665 }
6666 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6667 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6668 break;
6669 default: /* (%si) -> 4 or (%di) -> 5 */
6670 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6671 }
6672 i.rm.mode = mode_from_disp_size (i.types[op]);
6673 }
6674 else /* i.base_reg and 32/64 bit mode */
6675 {
6676 if (flag_code == CODE_64BIT
6677 && operand_type_check (i.types[op], disp))
6678 {
6679 i386_operand_type temp;
6680 operand_type_set (&temp, 0);
6681 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6682 i.types[op] = temp;
6683 if (i.prefix[ADDR_PREFIX] == 0)
6684 i.types[op].bitfield.disp32s = 1;
6685 else
6686 i.types[op].bitfield.disp32 = 1;
6687 }
6688
6689 if (!i.tm.opcode_modifier.vecsib)
6690 i.rm.regmem = i.base_reg->reg_num;
6691 if ((i.base_reg->reg_flags & RegRex) != 0)
6692 i.rex |= REX_B;
6693 i.sib.base = i.base_reg->reg_num;
6694 /* x86-64 ignores REX prefix bit here to avoid decoder
6695 complications. */
6696 if (!(i.base_reg->reg_flags & RegRex)
6697 && (i.base_reg->reg_num == EBP_REG_NUM
6698 || i.base_reg->reg_num == ESP_REG_NUM))
6699 default_seg = &ss;
6700 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6701 {
6702 fake_zero_displacement = 1;
6703 i.types[op].bitfield.disp8 = 1;
6704 }
6705 i.sib.scale = i.log2_scale_factor;
6706 if (i.index_reg == 0)
6707 {
6708 gas_assert (!i.tm.opcode_modifier.vecsib);
6709 /* <disp>(%esp) becomes two byte modrm with no index
6710 register. We've already stored the code for esp
6711 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6712 Any base register besides %esp will not use the
6713 extra modrm byte. */
6714 i.sib.index = NO_INDEX_REGISTER;
6715 }
6716 else if (!i.tm.opcode_modifier.vecsib)
6717 {
6718 if (i.index_reg->reg_num == RegEiz
6719 || i.index_reg->reg_num == RegRiz)
6720 i.sib.index = NO_INDEX_REGISTER;
6721 else
6722 i.sib.index = i.index_reg->reg_num;
6723 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6724 if ((i.index_reg->reg_flags & RegRex) != 0)
6725 i.rex |= REX_X;
6726 }
6727
6728 if (i.disp_operands
6729 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6730 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6731 i.rm.mode = 0;
6732 else
6733 {
6734 if (!fake_zero_displacement
6735 && !i.disp_operands
6736 && i.disp_encoding)
6737 {
6738 fake_zero_displacement = 1;
6739 if (i.disp_encoding == disp_encoding_8bit)
6740 i.types[op].bitfield.disp8 = 1;
6741 else
6742 i.types[op].bitfield.disp32 = 1;
6743 }
6744 i.rm.mode = mode_from_disp_size (i.types[op]);
6745 }
6746 }
6747
6748 if (fake_zero_displacement)
6749 {
6750 /* Fakes a zero displacement assuming that i.types[op]
6751 holds the correct displacement size. */
6752 expressionS *exp;
6753
6754 gas_assert (i.op[op].disps == 0);
6755 exp = &disp_expressions[i.disp_operands++];
6756 i.op[op].disps = exp;
6757 exp->X_op = O_constant;
6758 exp->X_add_number = 0;
6759 exp->X_add_symbol = (symbolS *) 0;
6760 exp->X_op_symbol = (symbolS *) 0;
6761 }
6762
6763 mem = op;
6764 }
6765 else
6766 mem = ~0;
6767
6768 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6769 {
6770 if (operand_type_check (i.types[0], imm))
6771 i.vex.register_specifier = NULL;
6772 else
6773 {
6774 /* VEX.vvvv encodes one of the sources when the first
6775 operand is not an immediate. */
6776 if (i.tm.opcode_modifier.vexw == VEXW0)
6777 i.vex.register_specifier = i.op[0].regs;
6778 else
6779 i.vex.register_specifier = i.op[1].regs;
6780 }
6781
6782 /* Destination is a XMM register encoded in the ModRM.reg
6783 and VEX.R bit. */
6784 i.rm.reg = i.op[2].regs->reg_num;
6785 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6786 i.rex |= REX_R;
6787
6788 /* ModRM.rm and VEX.B encodes the other source. */
6789 if (!i.mem_operands)
6790 {
6791 i.rm.mode = 3;
6792
6793 if (i.tm.opcode_modifier.vexw == VEXW0)
6794 i.rm.regmem = i.op[1].regs->reg_num;
6795 else
6796 i.rm.regmem = i.op[0].regs->reg_num;
6797
6798 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6799 i.rex |= REX_B;
6800 }
6801 }
6802 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6803 {
6804 i.vex.register_specifier = i.op[2].regs;
6805 if (!i.mem_operands)
6806 {
6807 i.rm.mode = 3;
6808 i.rm.regmem = i.op[1].regs->reg_num;
6809 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6810 i.rex |= REX_B;
6811 }
6812 }
6813 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6814 (if any) based on i.tm.extension_opcode. Again, we must be
6815 careful to make sure that segment/control/debug/test/MMX
6816 registers are coded into the i.rm.reg field. */
6817 else if (i.reg_operands)
6818 {
6819 unsigned int op;
6820 unsigned int vex_reg = ~0;
6821
6822 for (op = 0; op < i.operands; op++)
6823 if (i.types[op].bitfield.reg
6824 || i.types[op].bitfield.regmmx
6825 || i.types[op].bitfield.regsimd
6826 || i.types[op].bitfield.regbnd
6827 || i.types[op].bitfield.regmask
6828 || i.types[op].bitfield.sreg2
6829 || i.types[op].bitfield.sreg3
6830 || i.types[op].bitfield.control
6831 || i.types[op].bitfield.debug
6832 || i.types[op].bitfield.test)
6833 break;
6834
6835 if (vex_3_sources)
6836 op = dest;
6837 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6838 {
6839 /* For instructions with VexNDS, the register-only
6840 source operand is encoded in VEX prefix. */
6841 gas_assert (mem != (unsigned int) ~0);
6842
6843 if (op > mem)
6844 {
6845 vex_reg = op++;
6846 gas_assert (op < i.operands);
6847 }
6848 else
6849 {
6850 /* Check register-only source operand when two source
6851 operands are swapped. */
6852 if (!i.tm.operand_types[op].bitfield.baseindex
6853 && i.tm.operand_types[op + 1].bitfield.baseindex)
6854 {
6855 vex_reg = op;
6856 op += 2;
6857 gas_assert (mem == (vex_reg + 1)
6858 && op < i.operands);
6859 }
6860 else
6861 {
6862 vex_reg = op + 1;
6863 gas_assert (vex_reg < i.operands);
6864 }
6865 }
6866 }
6867 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6868 {
6869 /* For instructions with VexNDD, the register destination
6870 is encoded in VEX prefix. */
6871 if (i.mem_operands == 0)
6872 {
6873 /* There is no memory operand. */
6874 gas_assert ((op + 2) == i.operands);
6875 vex_reg = op + 1;
6876 }
6877 else
6878 {
6879 /* There are only 2 operands. */
6880 gas_assert (op < 2 && i.operands == 2);
6881 vex_reg = 1;
6882 }
6883 }
6884 else
6885 gas_assert (op < i.operands);
6886
6887 if (vex_reg != (unsigned int) ~0)
6888 {
6889 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6890
6891 if ((!type->bitfield.reg
6892 || (!type->bitfield.dword && !type->bitfield.qword))
6893 && !type->bitfield.regsimd
6894 && !operand_type_equal (type, &regmask))
6895 abort ();
6896
6897 i.vex.register_specifier = i.op[vex_reg].regs;
6898 }
6899
6900 /* Don't set OP operand twice. */
6901 if (vex_reg != op)
6902 {
6903 /* If there is an extension opcode to put here, the
6904 register number must be put into the regmem field. */
6905 if (i.tm.extension_opcode != None)
6906 {
6907 i.rm.regmem = i.op[op].regs->reg_num;
6908 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6909 i.rex |= REX_B;
6910 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6911 i.vrex |= REX_B;
6912 }
6913 else
6914 {
6915 i.rm.reg = i.op[op].regs->reg_num;
6916 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6917 i.rex |= REX_R;
6918 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6919 i.vrex |= REX_R;
6920 }
6921 }
6922
6923 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6924 must set it to 3 to indicate this is a register operand
6925 in the regmem field. */
6926 if (!i.mem_operands)
6927 i.rm.mode = 3;
6928 }
6929
6930 /* Fill in i.rm.reg field with extension opcode (if any). */
6931 if (i.tm.extension_opcode != None)
6932 i.rm.reg = i.tm.extension_opcode;
6933 }
6934 return default_seg;
6935 }
6936
6937 static void
6938 output_branch (void)
6939 {
6940 char *p;
6941 int size;
6942 int code16;
6943 int prefix;
6944 relax_substateT subtype;
6945 symbolS *sym;
6946 offsetT off;
6947
6948 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6949 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6950
6951 prefix = 0;
6952 if (i.prefix[DATA_PREFIX] != 0)
6953 {
6954 prefix = 1;
6955 i.prefixes -= 1;
6956 code16 ^= CODE16;
6957 }
6958 /* Pentium4 branch hints. */
6959 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6960 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6961 {
6962 prefix++;
6963 i.prefixes--;
6964 }
6965 if (i.prefix[REX_PREFIX] != 0)
6966 {
6967 prefix++;
6968 i.prefixes--;
6969 }
6970
6971 /* BND prefixed jump. */
6972 if (i.prefix[BND_PREFIX] != 0)
6973 {
6974 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6975 i.prefixes -= 1;
6976 }
6977
6978 if (i.prefixes != 0 && !intel_syntax)
6979 as_warn (_("skipping prefixes on this instruction"));
6980
6981 /* It's always a symbol; End frag & setup for relax.
6982 Make sure there is enough room in this frag for the largest
6983 instruction we may generate in md_convert_frag. This is 2
6984 bytes for the opcode and room for the prefix and largest
6985 displacement. */
6986 frag_grow (prefix + 2 + 4);
6987 /* Prefix and 1 opcode byte go in fr_fix. */
6988 p = frag_more (prefix + 1);
6989 if (i.prefix[DATA_PREFIX] != 0)
6990 *p++ = DATA_PREFIX_OPCODE;
6991 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6992 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6993 *p++ = i.prefix[SEG_PREFIX];
6994 if (i.prefix[REX_PREFIX] != 0)
6995 *p++ = i.prefix[REX_PREFIX];
6996 *p = i.tm.base_opcode;
6997
6998 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6999 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7000 else if (cpu_arch_flags.bitfield.cpui386)
7001 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7002 else
7003 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7004 subtype |= code16;
7005
7006 sym = i.op[0].disps->X_add_symbol;
7007 off = i.op[0].disps->X_add_number;
7008
7009 if (i.op[0].disps->X_op != O_constant
7010 && i.op[0].disps->X_op != O_symbol)
7011 {
7012 /* Handle complex expressions. */
7013 sym = make_expr_symbol (i.op[0].disps);
7014 off = 0;
7015 }
7016
7017 /* 1 possible extra opcode + 4 byte displacement go in var part.
7018 Pass reloc in fr_var. */
7019 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7020 }
7021
7022 static void
7023 output_jump (void)
7024 {
7025 char *p;
7026 int size;
7027 fixS *fixP;
7028
7029 if (i.tm.opcode_modifier.jumpbyte)
7030 {
7031 /* This is a loop or jecxz type instruction. */
7032 size = 1;
7033 if (i.prefix[ADDR_PREFIX] != 0)
7034 {
7035 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7036 i.prefixes -= 1;
7037 }
7038 /* Pentium4 branch hints. */
7039 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7040 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7041 {
7042 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7043 i.prefixes--;
7044 }
7045 }
7046 else
7047 {
7048 int code16;
7049
7050 code16 = 0;
7051 if (flag_code == CODE_16BIT)
7052 code16 = CODE16;
7053
7054 if (i.prefix[DATA_PREFIX] != 0)
7055 {
7056 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7057 i.prefixes -= 1;
7058 code16 ^= CODE16;
7059 }
7060
7061 size = 4;
7062 if (code16)
7063 size = 2;
7064 }
7065
7066 if (i.prefix[REX_PREFIX] != 0)
7067 {
7068 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7069 i.prefixes -= 1;
7070 }
7071
7072 /* BND prefixed jump. */
7073 if (i.prefix[BND_PREFIX] != 0)
7074 {
7075 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7076 i.prefixes -= 1;
7077 }
7078
7079 if (i.prefixes != 0 && !intel_syntax)
7080 as_warn (_("skipping prefixes on this instruction"));
7081
7082 p = frag_more (i.tm.opcode_length + size);
7083 switch (i.tm.opcode_length)
7084 {
7085 case 2:
7086 *p++ = i.tm.base_opcode >> 8;
7087 /* Fall through. */
7088 case 1:
7089 *p++ = i.tm.base_opcode;
7090 break;
7091 default:
7092 abort ();
7093 }
7094
7095 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7096 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
7097
7098 /* All jumps handled here are signed, but don't use a signed limit
7099 check for 32 and 16 bit jumps as we want to allow wrap around at
7100 4G and 64k respectively. */
7101 if (size == 1)
7102 fixP->fx_signed = 1;
7103 }
7104
7105 static void
7106 output_interseg_jump (void)
7107 {
7108 char *p;
7109 int size;
7110 int prefix;
7111 int code16;
7112
7113 code16 = 0;
7114 if (flag_code == CODE_16BIT)
7115 code16 = CODE16;
7116
7117 prefix = 0;
7118 if (i.prefix[DATA_PREFIX] != 0)
7119 {
7120 prefix = 1;
7121 i.prefixes -= 1;
7122 code16 ^= CODE16;
7123 }
7124 if (i.prefix[REX_PREFIX] != 0)
7125 {
7126 prefix++;
7127 i.prefixes -= 1;
7128 }
7129
7130 size = 4;
7131 if (code16)
7132 size = 2;
7133
7134 if (i.prefixes != 0 && !intel_syntax)
7135 as_warn (_("skipping prefixes on this instruction"));
7136
7137 /* 1 opcode; 2 segment; offset */
7138 p = frag_more (prefix + 1 + 2 + size);
7139
7140 if (i.prefix[DATA_PREFIX] != 0)
7141 *p++ = DATA_PREFIX_OPCODE;
7142
7143 if (i.prefix[REX_PREFIX] != 0)
7144 *p++ = i.prefix[REX_PREFIX];
7145
7146 *p++ = i.tm.base_opcode;
7147 if (i.op[1].imms->X_op == O_constant)
7148 {
7149 offsetT n = i.op[1].imms->X_add_number;
7150
7151 if (size == 2
7152 && !fits_in_unsigned_word (n)
7153 && !fits_in_signed_word (n))
7154 {
7155 as_bad (_("16-bit jump out of range"));
7156 return;
7157 }
7158 md_number_to_chars (p, n, size);
7159 }
7160 else
7161 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7162 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7163 if (i.op[0].imms->X_op != O_constant)
7164 as_bad (_("can't handle non absolute segment in `%s'"),
7165 i.tm.name);
7166 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7167 }
7168
7169 static void
7170 output_insn (void)
7171 {
7172 fragS *insn_start_frag;
7173 offsetT insn_start_off;
7174
7175 /* Tie dwarf2 debug info to the address at the start of the insn.
7176 We can't do this after the insn has been output as the current
7177 frag may have been closed off. eg. by frag_var. */
7178 dwarf2_emit_insn (0);
7179
7180 insn_start_frag = frag_now;
7181 insn_start_off = frag_now_fix ();
7182
7183 /* Output jumps. */
7184 if (i.tm.opcode_modifier.jump)
7185 output_branch ();
7186 else if (i.tm.opcode_modifier.jumpbyte
7187 || i.tm.opcode_modifier.jumpdword)
7188 output_jump ();
7189 else if (i.tm.opcode_modifier.jumpintersegment)
7190 output_interseg_jump ();
7191 else
7192 {
7193 /* Output normal instructions here. */
7194 char *p;
7195 unsigned char *q;
7196 unsigned int j;
7197 unsigned int prefix;
7198
7199 if (avoid_fence
7200 && i.tm.base_opcode == 0xfae
7201 && i.operands == 1
7202 && i.imm_operands == 1
7203 && (i.op[0].imms->X_add_number == 0xe8
7204 || i.op[0].imms->X_add_number == 0xf0
7205 || i.op[0].imms->X_add_number == 0xf8))
7206 {
7207 /* Encode lfence, mfence, and sfence as
7208 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7209 offsetT val = 0x240483f0ULL;
7210 p = frag_more (5);
7211 md_number_to_chars (p, val, 5);
7212 return;
7213 }
7214
7215 /* Some processors fail on LOCK prefix. This options makes
7216 assembler ignore LOCK prefix and serves as a workaround. */
7217 if (omit_lock_prefix)
7218 {
7219 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7220 return;
7221 i.prefix[LOCK_PREFIX] = 0;
7222 }
7223
7224 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7225 don't need the explicit prefix. */
7226 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7227 {
7228 switch (i.tm.opcode_length)
7229 {
7230 case 3:
7231 if (i.tm.base_opcode & 0xff000000)
7232 {
7233 prefix = (i.tm.base_opcode >> 24) & 0xff;
7234 goto check_prefix;
7235 }
7236 break;
7237 case 2:
7238 if ((i.tm.base_opcode & 0xff0000) != 0)
7239 {
7240 prefix = (i.tm.base_opcode >> 16) & 0xff;
7241 if (i.tm.cpu_flags.bitfield.cpupadlock)
7242 {
7243 check_prefix:
7244 if (prefix != REPE_PREFIX_OPCODE
7245 || (i.prefix[REP_PREFIX]
7246 != REPE_PREFIX_OPCODE))
7247 add_prefix (prefix);
7248 }
7249 else
7250 add_prefix (prefix);
7251 }
7252 break;
7253 case 1:
7254 break;
7255 case 0:
7256 /* Check for pseudo prefixes. */
7257 as_bad_where (insn_start_frag->fr_file,
7258 insn_start_frag->fr_line,
7259 _("pseudo prefix without instruction"));
7260 return;
7261 default:
7262 abort ();
7263 }
7264
7265 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7266 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7267 R_X86_64_GOTTPOFF relocation so that linker can safely
7268 perform IE->LE optimization. */
7269 if (x86_elf_abi == X86_64_X32_ABI
7270 && i.operands == 2
7271 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7272 && i.prefix[REX_PREFIX] == 0)
7273 add_prefix (REX_OPCODE);
7274 #endif
7275
7276 /* The prefix bytes. */
7277 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7278 if (*q)
7279 FRAG_APPEND_1_CHAR (*q);
7280 }
7281 else
7282 {
7283 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7284 if (*q)
7285 switch (j)
7286 {
7287 case REX_PREFIX:
7288 /* REX byte is encoded in VEX prefix. */
7289 break;
7290 case SEG_PREFIX:
7291 case ADDR_PREFIX:
7292 FRAG_APPEND_1_CHAR (*q);
7293 break;
7294 default:
7295 /* There should be no other prefixes for instructions
7296 with VEX prefix. */
7297 abort ();
7298 }
7299
7300 /* For EVEX instructions i.vrex should become 0 after
7301 build_evex_prefix. For VEX instructions upper 16 registers
7302 aren't available, so VREX should be 0. */
7303 if (i.vrex)
7304 abort ();
7305 /* Now the VEX prefix. */
7306 p = frag_more (i.vex.length);
7307 for (j = 0; j < i.vex.length; j++)
7308 p[j] = i.vex.bytes[j];
7309 }
7310
7311 /* Now the opcode; be careful about word order here! */
7312 if (i.tm.opcode_length == 1)
7313 {
7314 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7315 }
7316 else
7317 {
7318 switch (i.tm.opcode_length)
7319 {
7320 case 4:
7321 p = frag_more (4);
7322 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7323 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7324 break;
7325 case 3:
7326 p = frag_more (3);
7327 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7328 break;
7329 case 2:
7330 p = frag_more (2);
7331 break;
7332 default:
7333 abort ();
7334 break;
7335 }
7336
7337 /* Put out high byte first: can't use md_number_to_chars! */
7338 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7339 *p = i.tm.base_opcode & 0xff;
7340 }
7341
7342 /* Now the modrm byte and sib byte (if present). */
7343 if (i.tm.opcode_modifier.modrm)
7344 {
7345 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7346 | i.rm.reg << 3
7347 | i.rm.mode << 6));
7348 /* If i.rm.regmem == ESP (4)
7349 && i.rm.mode != (Register mode)
7350 && not 16 bit
7351 ==> need second modrm byte. */
7352 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7353 && i.rm.mode != 3
7354 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7355 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7356 | i.sib.index << 3
7357 | i.sib.scale << 6));
7358 }
7359
7360 if (i.disp_operands)
7361 output_disp (insn_start_frag, insn_start_off);
7362
7363 if (i.imm_operands)
7364 output_imm (insn_start_frag, insn_start_off);
7365 }
7366
7367 #ifdef DEBUG386
7368 if (flag_debug)
7369 {
7370 pi ("" /*line*/, &i);
7371 }
7372 #endif /* DEBUG386 */
7373 }
7374
7375 /* Return the size of the displacement operand N. */
7376
7377 static int
7378 disp_size (unsigned int n)
7379 {
7380 int size = 4;
7381
7382 if (i.types[n].bitfield.disp64)
7383 size = 8;
7384 else if (i.types[n].bitfield.disp8)
7385 size = 1;
7386 else if (i.types[n].bitfield.disp16)
7387 size = 2;
7388 return size;
7389 }
7390
7391 /* Return the size of the immediate operand N. */
7392
7393 static int
7394 imm_size (unsigned int n)
7395 {
7396 int size = 4;
7397 if (i.types[n].bitfield.imm64)
7398 size = 8;
7399 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7400 size = 1;
7401 else if (i.types[n].bitfield.imm16)
7402 size = 2;
7403 return size;
7404 }
7405
7406 static void
7407 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7408 {
7409 char *p;
7410 unsigned int n;
7411
7412 for (n = 0; n < i.operands; n++)
7413 {
7414 if (operand_type_check (i.types[n], disp))
7415 {
7416 if (i.op[n].disps->X_op == O_constant)
7417 {
7418 int size = disp_size (n);
7419 offsetT val = i.op[n].disps->X_add_number;
7420
7421 val = offset_in_range (val >> i.memshift, size);
7422 p = frag_more (size);
7423 md_number_to_chars (p, val, size);
7424 }
7425 else
7426 {
7427 enum bfd_reloc_code_real reloc_type;
7428 int size = disp_size (n);
7429 int sign = i.types[n].bitfield.disp32s;
7430 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7431 fixS *fixP;
7432
7433 /* We can't have 8 bit displacement here. */
7434 gas_assert (!i.types[n].bitfield.disp8);
7435
7436 /* The PC relative address is computed relative
7437 to the instruction boundary, so in case immediate
7438 fields follows, we need to adjust the value. */
7439 if (pcrel && i.imm_operands)
7440 {
7441 unsigned int n1;
7442 int sz = 0;
7443
7444 for (n1 = 0; n1 < i.operands; n1++)
7445 if (operand_type_check (i.types[n1], imm))
7446 {
7447 /* Only one immediate is allowed for PC
7448 relative address. */
7449 gas_assert (sz == 0);
7450 sz = imm_size (n1);
7451 i.op[n].disps->X_add_number -= sz;
7452 }
7453 /* We should find the immediate. */
7454 gas_assert (sz != 0);
7455 }
7456
7457 p = frag_more (size);
7458 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7459 if (GOT_symbol
7460 && GOT_symbol == i.op[n].disps->X_add_symbol
7461 && (((reloc_type == BFD_RELOC_32
7462 || reloc_type == BFD_RELOC_X86_64_32S
7463 || (reloc_type == BFD_RELOC_64
7464 && object_64bit))
7465 && (i.op[n].disps->X_op == O_symbol
7466 || (i.op[n].disps->X_op == O_add
7467 && ((symbol_get_value_expression
7468 (i.op[n].disps->X_op_symbol)->X_op)
7469 == O_subtract))))
7470 || reloc_type == BFD_RELOC_32_PCREL))
7471 {
7472 offsetT add;
7473
7474 if (insn_start_frag == frag_now)
7475 add = (p - frag_now->fr_literal) - insn_start_off;
7476 else
7477 {
7478 fragS *fr;
7479
7480 add = insn_start_frag->fr_fix - insn_start_off;
7481 for (fr = insn_start_frag->fr_next;
7482 fr && fr != frag_now; fr = fr->fr_next)
7483 add += fr->fr_fix;
7484 add += p - frag_now->fr_literal;
7485 }
7486
7487 if (!object_64bit)
7488 {
7489 reloc_type = BFD_RELOC_386_GOTPC;
7490 i.op[n].imms->X_add_number += add;
7491 }
7492 else if (reloc_type == BFD_RELOC_64)
7493 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7494 else
7495 /* Don't do the adjustment for x86-64, as there
7496 the pcrel addressing is relative to the _next_
7497 insn, and that is taken care of in other code. */
7498 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7499 }
7500 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7501 size, i.op[n].disps, pcrel,
7502 reloc_type);
7503 /* Check for "call/jmp *mem", "mov mem, %reg",
7504 "test %reg, mem" and "binop mem, %reg" where binop
7505 is one of adc, add, and, cmp, or, sbb, sub, xor
7506 instructions. Always generate R_386_GOT32X for
7507 "sym*GOT" operand in 32-bit mode. */
7508 if ((generate_relax_relocations
7509 || (!object_64bit
7510 && i.rm.mode == 0
7511 && i.rm.regmem == 5))
7512 && (i.rm.mode == 2
7513 || (i.rm.mode == 0 && i.rm.regmem == 5))
7514 && ((i.operands == 1
7515 && i.tm.base_opcode == 0xff
7516 && (i.rm.reg == 2 || i.rm.reg == 4))
7517 || (i.operands == 2
7518 && (i.tm.base_opcode == 0x8b
7519 || i.tm.base_opcode == 0x85
7520 || (i.tm.base_opcode & 0xc7) == 0x03))))
7521 {
7522 if (object_64bit)
7523 {
7524 fixP->fx_tcbit = i.rex != 0;
7525 if (i.base_reg
7526 && (i.base_reg->reg_num == RegRip
7527 || i.base_reg->reg_num == RegEip))
7528 fixP->fx_tcbit2 = 1;
7529 }
7530 else
7531 fixP->fx_tcbit2 = 1;
7532 }
7533 }
7534 }
7535 }
7536 }
7537
7538 static void
7539 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7540 {
7541 char *p;
7542 unsigned int n;
7543
7544 for (n = 0; n < i.operands; n++)
7545 {
7546 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7547 if (i.rounding && (int) n == i.rounding->operand)
7548 continue;
7549
7550 if (operand_type_check (i.types[n], imm))
7551 {
7552 if (i.op[n].imms->X_op == O_constant)
7553 {
7554 int size = imm_size (n);
7555 offsetT val;
7556
7557 val = offset_in_range (i.op[n].imms->X_add_number,
7558 size);
7559 p = frag_more (size);
7560 md_number_to_chars (p, val, size);
7561 }
7562 else
7563 {
7564 /* Not absolute_section.
7565 Need a 32-bit fixup (don't support 8bit
7566 non-absolute imms). Try to support other
7567 sizes ... */
7568 enum bfd_reloc_code_real reloc_type;
7569 int size = imm_size (n);
7570 int sign;
7571
7572 if (i.types[n].bitfield.imm32s
7573 && (i.suffix == QWORD_MNEM_SUFFIX
7574 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7575 sign = 1;
7576 else
7577 sign = 0;
7578
7579 p = frag_more (size);
7580 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7581
7582 /* This is tough to explain. We end up with this one if we
7583 * have operands that look like
7584 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7585 * obtain the absolute address of the GOT, and it is strongly
7586 * preferable from a performance point of view to avoid using
7587 * a runtime relocation for this. The actual sequence of
7588 * instructions often look something like:
7589 *
7590 * call .L66
7591 * .L66:
7592 * popl %ebx
7593 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7594 *
7595 * The call and pop essentially return the absolute address
7596 * of the label .L66 and store it in %ebx. The linker itself
7597 * will ultimately change the first operand of the addl so
7598 * that %ebx points to the GOT, but to keep things simple, the
7599 * .o file must have this operand set so that it generates not
7600 * the absolute address of .L66, but the absolute address of
7601 * itself. This allows the linker itself simply treat a GOTPC
7602 * relocation as asking for a pcrel offset to the GOT to be
7603 * added in, and the addend of the relocation is stored in the
7604 * operand field for the instruction itself.
7605 *
7606 * Our job here is to fix the operand so that it would add
7607 * the correct offset so that %ebx would point to itself. The
7608 * thing that is tricky is that .-.L66 will point to the
7609 * beginning of the instruction, so we need to further modify
7610 * the operand so that it will point to itself. There are
7611 * other cases where you have something like:
7612 *
7613 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7614 *
7615 * and here no correction would be required. Internally in
7616 * the assembler we treat operands of this form as not being
7617 * pcrel since the '.' is explicitly mentioned, and I wonder
7618 * whether it would simplify matters to do it this way. Who
7619 * knows. In earlier versions of the PIC patches, the
7620 * pcrel_adjust field was used to store the correction, but
7621 * since the expression is not pcrel, I felt it would be
7622 * confusing to do it this way. */
7623
7624 if ((reloc_type == BFD_RELOC_32
7625 || reloc_type == BFD_RELOC_X86_64_32S
7626 || reloc_type == BFD_RELOC_64)
7627 && GOT_symbol
7628 && GOT_symbol == i.op[n].imms->X_add_symbol
7629 && (i.op[n].imms->X_op == O_symbol
7630 || (i.op[n].imms->X_op == O_add
7631 && ((symbol_get_value_expression
7632 (i.op[n].imms->X_op_symbol)->X_op)
7633 == O_subtract))))
7634 {
7635 offsetT add;
7636
7637 if (insn_start_frag == frag_now)
7638 add = (p - frag_now->fr_literal) - insn_start_off;
7639 else
7640 {
7641 fragS *fr;
7642
7643 add = insn_start_frag->fr_fix - insn_start_off;
7644 for (fr = insn_start_frag->fr_next;
7645 fr && fr != frag_now; fr = fr->fr_next)
7646 add += fr->fr_fix;
7647 add += p - frag_now->fr_literal;
7648 }
7649
7650 if (!object_64bit)
7651 reloc_type = BFD_RELOC_386_GOTPC;
7652 else if (size == 4)
7653 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7654 else if (size == 8)
7655 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7656 i.op[n].imms->X_add_number += add;
7657 }
7658 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7659 i.op[n].imms, 0, reloc_type);
7660 }
7661 }
7662 }
7663 }
7664 \f
7665 /* x86_cons_fix_new is called via the expression parsing code when a
7666 reloc is needed. We use this hook to get the correct .got reloc. */
7667 static int cons_sign = -1;
7668
7669 void
7670 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7671 expressionS *exp, bfd_reloc_code_real_type r)
7672 {
7673 r = reloc (len, 0, cons_sign, r);
7674
7675 #ifdef TE_PE
7676 if (exp->X_op == O_secrel)
7677 {
7678 exp->X_op = O_symbol;
7679 r = BFD_RELOC_32_SECREL;
7680 }
7681 #endif
7682
7683 fix_new_exp (frag, off, len, exp, 0, r);
7684 }
7685
7686 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7687 purpose of the `.dc.a' internal pseudo-op. */
7688
7689 int
7690 x86_address_bytes (void)
7691 {
7692 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7693 return 4;
7694 return stdoutput->arch_info->bits_per_address / 8;
7695 }
7696
7697 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7698 || defined (LEX_AT)
7699 # define lex_got(reloc, adjust, types) NULL
7700 #else
7701 /* Parse operands of the form
7702 <symbol>@GOTOFF+<nnn>
7703 and similar .plt or .got references.
7704
7705 If we find one, set up the correct relocation in RELOC and copy the
7706 input string, minus the `@GOTOFF' into a malloc'd buffer for
7707 parsing by the calling routine. Return this buffer, and if ADJUST
7708 is non-null set it to the length of the string we removed from the
7709 input line. Otherwise return NULL. */
7710 static char *
7711 lex_got (enum bfd_reloc_code_real *rel,
7712 int *adjust,
7713 i386_operand_type *types)
7714 {
7715 /* Some of the relocations depend on the size of what field is to
7716 be relocated. But in our callers i386_immediate and i386_displacement
7717 we don't yet know the operand size (this will be set by insn
7718 matching). Hence we record the word32 relocation here,
7719 and adjust the reloc according to the real size in reloc(). */
7720 static const struct {
7721 const char *str;
7722 int len;
7723 const enum bfd_reloc_code_real rel[2];
7724 const i386_operand_type types64;
7725 } gotrel[] = {
7726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7727 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7728 BFD_RELOC_SIZE32 },
7729 OPERAND_TYPE_IMM32_64 },
7730 #endif
7731 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7732 BFD_RELOC_X86_64_PLTOFF64 },
7733 OPERAND_TYPE_IMM64 },
7734 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7735 BFD_RELOC_X86_64_PLT32 },
7736 OPERAND_TYPE_IMM32_32S_DISP32 },
7737 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7738 BFD_RELOC_X86_64_GOTPLT64 },
7739 OPERAND_TYPE_IMM64_DISP64 },
7740 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7741 BFD_RELOC_X86_64_GOTOFF64 },
7742 OPERAND_TYPE_IMM64_DISP64 },
7743 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7744 BFD_RELOC_X86_64_GOTPCREL },
7745 OPERAND_TYPE_IMM32_32S_DISP32 },
7746 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7747 BFD_RELOC_X86_64_TLSGD },
7748 OPERAND_TYPE_IMM32_32S_DISP32 },
7749 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7750 _dummy_first_bfd_reloc_code_real },
7751 OPERAND_TYPE_NONE },
7752 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7753 BFD_RELOC_X86_64_TLSLD },
7754 OPERAND_TYPE_IMM32_32S_DISP32 },
7755 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7756 BFD_RELOC_X86_64_GOTTPOFF },
7757 OPERAND_TYPE_IMM32_32S_DISP32 },
7758 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7759 BFD_RELOC_X86_64_TPOFF32 },
7760 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7761 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7762 _dummy_first_bfd_reloc_code_real },
7763 OPERAND_TYPE_NONE },
7764 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7765 BFD_RELOC_X86_64_DTPOFF32 },
7766 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7767 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7768 _dummy_first_bfd_reloc_code_real },
7769 OPERAND_TYPE_NONE },
7770 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7771 _dummy_first_bfd_reloc_code_real },
7772 OPERAND_TYPE_NONE },
7773 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7774 BFD_RELOC_X86_64_GOT32 },
7775 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7776 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7777 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7778 OPERAND_TYPE_IMM32_32S_DISP32 },
7779 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7780 BFD_RELOC_X86_64_TLSDESC_CALL },
7781 OPERAND_TYPE_IMM32_32S_DISP32 },
7782 };
7783 char *cp;
7784 unsigned int j;
7785
7786 #if defined (OBJ_MAYBE_ELF)
7787 if (!IS_ELF)
7788 return NULL;
7789 #endif
7790
7791 for (cp = input_line_pointer; *cp != '@'; cp++)
7792 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7793 return NULL;
7794
7795 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7796 {
7797 int len = gotrel[j].len;
7798 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7799 {
7800 if (gotrel[j].rel[object_64bit] != 0)
7801 {
7802 int first, second;
7803 char *tmpbuf, *past_reloc;
7804
7805 *rel = gotrel[j].rel[object_64bit];
7806
7807 if (types)
7808 {
7809 if (flag_code != CODE_64BIT)
7810 {
7811 types->bitfield.imm32 = 1;
7812 types->bitfield.disp32 = 1;
7813 }
7814 else
7815 *types = gotrel[j].types64;
7816 }
7817
7818 if (j != 0 && GOT_symbol == NULL)
7819 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7820
7821 /* The length of the first part of our input line. */
7822 first = cp - input_line_pointer;
7823
7824 /* The second part goes from after the reloc token until
7825 (and including) an end_of_line char or comma. */
7826 past_reloc = cp + 1 + len;
7827 cp = past_reloc;
7828 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7829 ++cp;
7830 second = cp + 1 - past_reloc;
7831
7832 /* Allocate and copy string. The trailing NUL shouldn't
7833 be necessary, but be safe. */
7834 tmpbuf = XNEWVEC (char, first + second + 2);
7835 memcpy (tmpbuf, input_line_pointer, first);
7836 if (second != 0 && *past_reloc != ' ')
7837 /* Replace the relocation token with ' ', so that
7838 errors like foo@GOTOFF1 will be detected. */
7839 tmpbuf[first++] = ' ';
7840 else
7841 /* Increment length by 1 if the relocation token is
7842 removed. */
7843 len++;
7844 if (adjust)
7845 *adjust = len;
7846 memcpy (tmpbuf + first, past_reloc, second);
7847 tmpbuf[first + second] = '\0';
7848 return tmpbuf;
7849 }
7850
7851 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7852 gotrel[j].str, 1 << (5 + object_64bit));
7853 return NULL;
7854 }
7855 }
7856
7857 /* Might be a symbol version string. Don't as_bad here. */
7858 return NULL;
7859 }
7860 #endif
7861
7862 #ifdef TE_PE
7863 #ifdef lex_got
7864 #undef lex_got
7865 #endif
7866 /* Parse operands of the form
7867 <symbol>@SECREL32+<nnn>
7868
7869 If we find one, set up the correct relocation in RELOC and copy the
7870 input string, minus the `@SECREL32' into a malloc'd buffer for
7871 parsing by the calling routine. Return this buffer, and if ADJUST
7872 is non-null set it to the length of the string we removed from the
7873 input line. Otherwise return NULL.
7874
7875 This function is copied from the ELF version above adjusted for PE targets. */
7876
7877 static char *
7878 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7879 int *adjust ATTRIBUTE_UNUSED,
7880 i386_operand_type *types)
7881 {
7882 static const struct
7883 {
7884 const char *str;
7885 int len;
7886 const enum bfd_reloc_code_real rel[2];
7887 const i386_operand_type types64;
7888 }
7889 gotrel[] =
7890 {
7891 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7892 BFD_RELOC_32_SECREL },
7893 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7894 };
7895
7896 char *cp;
7897 unsigned j;
7898
7899 for (cp = input_line_pointer; *cp != '@'; cp++)
7900 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7901 return NULL;
7902
7903 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7904 {
7905 int len = gotrel[j].len;
7906
7907 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7908 {
7909 if (gotrel[j].rel[object_64bit] != 0)
7910 {
7911 int first, second;
7912 char *tmpbuf, *past_reloc;
7913
7914 *rel = gotrel[j].rel[object_64bit];
7915 if (adjust)
7916 *adjust = len;
7917
7918 if (types)
7919 {
7920 if (flag_code != CODE_64BIT)
7921 {
7922 types->bitfield.imm32 = 1;
7923 types->bitfield.disp32 = 1;
7924 }
7925 else
7926 *types = gotrel[j].types64;
7927 }
7928
7929 /* The length of the first part of our input line. */
7930 first = cp - input_line_pointer;
7931
7932 /* The second part goes from after the reloc token until
7933 (and including) an end_of_line char or comma. */
7934 past_reloc = cp + 1 + len;
7935 cp = past_reloc;
7936 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7937 ++cp;
7938 second = cp + 1 - past_reloc;
7939
7940 /* Allocate and copy string. The trailing NUL shouldn't
7941 be necessary, but be safe. */
7942 tmpbuf = XNEWVEC (char, first + second + 2);
7943 memcpy (tmpbuf, input_line_pointer, first);
7944 if (second != 0 && *past_reloc != ' ')
7945 /* Replace the relocation token with ' ', so that
7946 errors like foo@SECLREL321 will be detected. */
7947 tmpbuf[first++] = ' ';
7948 memcpy (tmpbuf + first, past_reloc, second);
7949 tmpbuf[first + second] = '\0';
7950 return tmpbuf;
7951 }
7952
7953 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7954 gotrel[j].str, 1 << (5 + object_64bit));
7955 return NULL;
7956 }
7957 }
7958
7959 /* Might be a symbol version string. Don't as_bad here. */
7960 return NULL;
7961 }
7962
7963 #endif /* TE_PE */
7964
7965 bfd_reloc_code_real_type
7966 x86_cons (expressionS *exp, int size)
7967 {
7968 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7969
7970 intel_syntax = -intel_syntax;
7971
7972 exp->X_md = 0;
7973 if (size == 4 || (object_64bit && size == 8))
7974 {
7975 /* Handle @GOTOFF and the like in an expression. */
7976 char *save;
7977 char *gotfree_input_line;
7978 int adjust = 0;
7979
7980 save = input_line_pointer;
7981 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
7982 if (gotfree_input_line)
7983 input_line_pointer = gotfree_input_line;
7984
7985 expression (exp);
7986
7987 if (gotfree_input_line)
7988 {
7989 /* expression () has merrily parsed up to the end of line,
7990 or a comma - in the wrong buffer. Transfer how far
7991 input_line_pointer has moved to the right buffer. */
7992 input_line_pointer = (save
7993 + (input_line_pointer - gotfree_input_line)
7994 + adjust);
7995 free (gotfree_input_line);
7996 if (exp->X_op == O_constant
7997 || exp->X_op == O_absent
7998 || exp->X_op == O_illegal
7999 || exp->X_op == O_register
8000 || exp->X_op == O_big)
8001 {
8002 char c = *input_line_pointer;
8003 *input_line_pointer = 0;
8004 as_bad (_("missing or invalid expression `%s'"), save);
8005 *input_line_pointer = c;
8006 }
8007 }
8008 }
8009 else
8010 expression (exp);
8011
8012 intel_syntax = -intel_syntax;
8013
8014 if (intel_syntax)
8015 i386_intel_simplify (exp);
8016
8017 return got_reloc;
8018 }
8019
8020 static void
8021 signed_cons (int size)
8022 {
8023 if (flag_code == CODE_64BIT)
8024 cons_sign = 1;
8025 cons (size);
8026 cons_sign = -1;
8027 }
8028
8029 #ifdef TE_PE
8030 static void
8031 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8032 {
8033 expressionS exp;
8034
8035 do
8036 {
8037 expression (&exp);
8038 if (exp.X_op == O_symbol)
8039 exp.X_op = O_secrel;
8040
8041 emit_expr (&exp, 4);
8042 }
8043 while (*input_line_pointer++ == ',');
8044
8045 input_line_pointer--;
8046 demand_empty_rest_of_line ();
8047 }
8048 #endif
8049
8050 /* Handle Vector operations. */
8051
8052 static char *
8053 check_VecOperations (char *op_string, char *op_end)
8054 {
8055 const reg_entry *mask;
8056 const char *saved;
8057 char *end_op;
8058
8059 while (*op_string
8060 && (op_end == NULL || op_string < op_end))
8061 {
8062 saved = op_string;
8063 if (*op_string == '{')
8064 {
8065 op_string++;
8066
8067 /* Check broadcasts. */
8068 if (strncmp (op_string, "1to", 3) == 0)
8069 {
8070 int bcst_type;
8071
8072 if (i.broadcast)
8073 goto duplicated_vec_op;
8074
8075 op_string += 3;
8076 if (*op_string == '8')
8077 bcst_type = BROADCAST_1TO8;
8078 else if (*op_string == '4')
8079 bcst_type = BROADCAST_1TO4;
8080 else if (*op_string == '2')
8081 bcst_type = BROADCAST_1TO2;
8082 else if (*op_string == '1'
8083 && *(op_string+1) == '6')
8084 {
8085 bcst_type = BROADCAST_1TO16;
8086 op_string++;
8087 }
8088 else
8089 {
8090 as_bad (_("Unsupported broadcast: `%s'"), saved);
8091 return NULL;
8092 }
8093 op_string++;
8094
8095 broadcast_op.type = bcst_type;
8096 broadcast_op.operand = this_operand;
8097 i.broadcast = &broadcast_op;
8098 }
8099 /* Check masking operation. */
8100 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8101 {
8102 /* k0 can't be used for write mask. */
8103 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8104 {
8105 as_bad (_("`%s%s' can't be used for write mask"),
8106 register_prefix, mask->reg_name);
8107 return NULL;
8108 }
8109
8110 if (!i.mask)
8111 {
8112 mask_op.mask = mask;
8113 mask_op.zeroing = 0;
8114 mask_op.operand = this_operand;
8115 i.mask = &mask_op;
8116 }
8117 else
8118 {
8119 if (i.mask->mask)
8120 goto duplicated_vec_op;
8121
8122 i.mask->mask = mask;
8123
8124 /* Only "{z}" is allowed here. No need to check
8125 zeroing mask explicitly. */
8126 if (i.mask->operand != this_operand)
8127 {
8128 as_bad (_("invalid write mask `%s'"), saved);
8129 return NULL;
8130 }
8131 }
8132
8133 op_string = end_op;
8134 }
8135 /* Check zeroing-flag for masking operation. */
8136 else if (*op_string == 'z')
8137 {
8138 if (!i.mask)
8139 {
8140 mask_op.mask = NULL;
8141 mask_op.zeroing = 1;
8142 mask_op.operand = this_operand;
8143 i.mask = &mask_op;
8144 }
8145 else
8146 {
8147 if (i.mask->zeroing)
8148 {
8149 duplicated_vec_op:
8150 as_bad (_("duplicated `%s'"), saved);
8151 return NULL;
8152 }
8153
8154 i.mask->zeroing = 1;
8155
8156 /* Only "{%k}" is allowed here. No need to check mask
8157 register explicitly. */
8158 if (i.mask->operand != this_operand)
8159 {
8160 as_bad (_("invalid zeroing-masking `%s'"),
8161 saved);
8162 return NULL;
8163 }
8164 }
8165
8166 op_string++;
8167 }
8168 else
8169 goto unknown_vec_op;
8170
8171 if (*op_string != '}')
8172 {
8173 as_bad (_("missing `}' in `%s'"), saved);
8174 return NULL;
8175 }
8176 op_string++;
8177 continue;
8178 }
8179 unknown_vec_op:
8180 /* We don't know this one. */
8181 as_bad (_("unknown vector operation: `%s'"), saved);
8182 return NULL;
8183 }
8184
8185 if (i.mask && i.mask->zeroing && !i.mask->mask)
8186 {
8187 as_bad (_("zeroing-masking only allowed with write mask"));
8188 return NULL;
8189 }
8190
8191 return op_string;
8192 }
8193
8194 static int
8195 i386_immediate (char *imm_start)
8196 {
8197 char *save_input_line_pointer;
8198 char *gotfree_input_line;
8199 segT exp_seg = 0;
8200 expressionS *exp;
8201 i386_operand_type types;
8202
8203 operand_type_set (&types, ~0);
8204
8205 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8206 {
8207 as_bad (_("at most %d immediate operands are allowed"),
8208 MAX_IMMEDIATE_OPERANDS);
8209 return 0;
8210 }
8211
8212 exp = &im_expressions[i.imm_operands++];
8213 i.op[this_operand].imms = exp;
8214
8215 if (is_space_char (*imm_start))
8216 ++imm_start;
8217
8218 save_input_line_pointer = input_line_pointer;
8219 input_line_pointer = imm_start;
8220
8221 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8222 if (gotfree_input_line)
8223 input_line_pointer = gotfree_input_line;
8224
8225 exp_seg = expression (exp);
8226
8227 SKIP_WHITESPACE ();
8228
8229 /* Handle vector operations. */
8230 if (*input_line_pointer == '{')
8231 {
8232 input_line_pointer = check_VecOperations (input_line_pointer,
8233 NULL);
8234 if (input_line_pointer == NULL)
8235 return 0;
8236 }
8237
8238 if (*input_line_pointer)
8239 as_bad (_("junk `%s' after expression"), input_line_pointer);
8240
8241 input_line_pointer = save_input_line_pointer;
8242 if (gotfree_input_line)
8243 {
8244 free (gotfree_input_line);
8245
8246 if (exp->X_op == O_constant || exp->X_op == O_register)
8247 exp->X_op = O_illegal;
8248 }
8249
8250 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8251 }
8252
8253 static int
8254 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8255 i386_operand_type types, const char *imm_start)
8256 {
8257 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8258 {
8259 if (imm_start)
8260 as_bad (_("missing or invalid immediate expression `%s'"),
8261 imm_start);
8262 return 0;
8263 }
8264 else if (exp->X_op == O_constant)
8265 {
8266 /* Size it properly later. */
8267 i.types[this_operand].bitfield.imm64 = 1;
8268 /* If not 64bit, sign extend val. */
8269 if (flag_code != CODE_64BIT
8270 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8271 exp->X_add_number
8272 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8273 }
8274 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8275 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8276 && exp_seg != absolute_section
8277 && exp_seg != text_section
8278 && exp_seg != data_section
8279 && exp_seg != bss_section
8280 && exp_seg != undefined_section
8281 && !bfd_is_com_section (exp_seg))
8282 {
8283 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8284 return 0;
8285 }
8286 #endif
8287 else if (!intel_syntax && exp_seg == reg_section)
8288 {
8289 if (imm_start)
8290 as_bad (_("illegal immediate register operand %s"), imm_start);
8291 return 0;
8292 }
8293 else
8294 {
8295 /* This is an address. The size of the address will be
8296 determined later, depending on destination register,
8297 suffix, or the default for the section. */
8298 i.types[this_operand].bitfield.imm8 = 1;
8299 i.types[this_operand].bitfield.imm16 = 1;
8300 i.types[this_operand].bitfield.imm32 = 1;
8301 i.types[this_operand].bitfield.imm32s = 1;
8302 i.types[this_operand].bitfield.imm64 = 1;
8303 i.types[this_operand] = operand_type_and (i.types[this_operand],
8304 types);
8305 }
8306
8307 return 1;
8308 }
8309
8310 static char *
8311 i386_scale (char *scale)
8312 {
8313 offsetT val;
8314 char *save = input_line_pointer;
8315
8316 input_line_pointer = scale;
8317 val = get_absolute_expression ();
8318
8319 switch (val)
8320 {
8321 case 1:
8322 i.log2_scale_factor = 0;
8323 break;
8324 case 2:
8325 i.log2_scale_factor = 1;
8326 break;
8327 case 4:
8328 i.log2_scale_factor = 2;
8329 break;
8330 case 8:
8331 i.log2_scale_factor = 3;
8332 break;
8333 default:
8334 {
8335 char sep = *input_line_pointer;
8336
8337 *input_line_pointer = '\0';
8338 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8339 scale);
8340 *input_line_pointer = sep;
8341 input_line_pointer = save;
8342 return NULL;
8343 }
8344 }
8345 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8346 {
8347 as_warn (_("scale factor of %d without an index register"),
8348 1 << i.log2_scale_factor);
8349 i.log2_scale_factor = 0;
8350 }
8351 scale = input_line_pointer;
8352 input_line_pointer = save;
8353 return scale;
8354 }
8355
8356 static int
8357 i386_displacement (char *disp_start, char *disp_end)
8358 {
8359 expressionS *exp;
8360 segT exp_seg = 0;
8361 char *save_input_line_pointer;
8362 char *gotfree_input_line;
8363 int override;
8364 i386_operand_type bigdisp, types = anydisp;
8365 int ret;
8366
8367 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8368 {
8369 as_bad (_("at most %d displacement operands are allowed"),
8370 MAX_MEMORY_OPERANDS);
8371 return 0;
8372 }
8373
8374 operand_type_set (&bigdisp, 0);
8375 if ((i.types[this_operand].bitfield.jumpabsolute)
8376 || (!current_templates->start->opcode_modifier.jump
8377 && !current_templates->start->opcode_modifier.jumpdword))
8378 {
8379 bigdisp.bitfield.disp32 = 1;
8380 override = (i.prefix[ADDR_PREFIX] != 0);
8381 if (flag_code == CODE_64BIT)
8382 {
8383 if (!override)
8384 {
8385 bigdisp.bitfield.disp32s = 1;
8386 bigdisp.bitfield.disp64 = 1;
8387 }
8388 }
8389 else if ((flag_code == CODE_16BIT) ^ override)
8390 {
8391 bigdisp.bitfield.disp32 = 0;
8392 bigdisp.bitfield.disp16 = 1;
8393 }
8394 }
8395 else
8396 {
8397 /* For PC-relative branches, the width of the displacement
8398 is dependent upon data size, not address size. */
8399 override = (i.prefix[DATA_PREFIX] != 0);
8400 if (flag_code == CODE_64BIT)
8401 {
8402 if (override || i.suffix == WORD_MNEM_SUFFIX)
8403 bigdisp.bitfield.disp16 = 1;
8404 else
8405 {
8406 bigdisp.bitfield.disp32 = 1;
8407 bigdisp.bitfield.disp32s = 1;
8408 }
8409 }
8410 else
8411 {
8412 if (!override)
8413 override = (i.suffix == (flag_code != CODE_16BIT
8414 ? WORD_MNEM_SUFFIX
8415 : LONG_MNEM_SUFFIX));
8416 bigdisp.bitfield.disp32 = 1;
8417 if ((flag_code == CODE_16BIT) ^ override)
8418 {
8419 bigdisp.bitfield.disp32 = 0;
8420 bigdisp.bitfield.disp16 = 1;
8421 }
8422 }
8423 }
8424 i.types[this_operand] = operand_type_or (i.types[this_operand],
8425 bigdisp);
8426
8427 exp = &disp_expressions[i.disp_operands];
8428 i.op[this_operand].disps = exp;
8429 i.disp_operands++;
8430 save_input_line_pointer = input_line_pointer;
8431 input_line_pointer = disp_start;
8432 END_STRING_AND_SAVE (disp_end);
8433
8434 #ifndef GCC_ASM_O_HACK
8435 #define GCC_ASM_O_HACK 0
8436 #endif
8437 #if GCC_ASM_O_HACK
8438 END_STRING_AND_SAVE (disp_end + 1);
8439 if (i.types[this_operand].bitfield.baseIndex
8440 && displacement_string_end[-1] == '+')
8441 {
8442 /* This hack is to avoid a warning when using the "o"
8443 constraint within gcc asm statements.
8444 For instance:
8445
8446 #define _set_tssldt_desc(n,addr,limit,type) \
8447 __asm__ __volatile__ ( \
8448 "movw %w2,%0\n\t" \
8449 "movw %w1,2+%0\n\t" \
8450 "rorl $16,%1\n\t" \
8451 "movb %b1,4+%0\n\t" \
8452 "movb %4,5+%0\n\t" \
8453 "movb $0,6+%0\n\t" \
8454 "movb %h1,7+%0\n\t" \
8455 "rorl $16,%1" \
8456 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8457
8458 This works great except that the output assembler ends
8459 up looking a bit weird if it turns out that there is
8460 no offset. You end up producing code that looks like:
8461
8462 #APP
8463 movw $235,(%eax)
8464 movw %dx,2+(%eax)
8465 rorl $16,%edx
8466 movb %dl,4+(%eax)
8467 movb $137,5+(%eax)
8468 movb $0,6+(%eax)
8469 movb %dh,7+(%eax)
8470 rorl $16,%edx
8471 #NO_APP
8472
8473 So here we provide the missing zero. */
8474
8475 *displacement_string_end = '0';
8476 }
8477 #endif
8478 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8479 if (gotfree_input_line)
8480 input_line_pointer = gotfree_input_line;
8481
8482 exp_seg = expression (exp);
8483
8484 SKIP_WHITESPACE ();
8485 if (*input_line_pointer)
8486 as_bad (_("junk `%s' after expression"), input_line_pointer);
8487 #if GCC_ASM_O_HACK
8488 RESTORE_END_STRING (disp_end + 1);
8489 #endif
8490 input_line_pointer = save_input_line_pointer;
8491 if (gotfree_input_line)
8492 {
8493 free (gotfree_input_line);
8494
8495 if (exp->X_op == O_constant || exp->X_op == O_register)
8496 exp->X_op = O_illegal;
8497 }
8498
8499 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8500
8501 RESTORE_END_STRING (disp_end);
8502
8503 return ret;
8504 }
8505
8506 static int
8507 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8508 i386_operand_type types, const char *disp_start)
8509 {
8510 i386_operand_type bigdisp;
8511 int ret = 1;
8512
8513 /* We do this to make sure that the section symbol is in
8514 the symbol table. We will ultimately change the relocation
8515 to be relative to the beginning of the section. */
8516 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8517 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8518 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8519 {
8520 if (exp->X_op != O_symbol)
8521 goto inv_disp;
8522
8523 if (S_IS_LOCAL (exp->X_add_symbol)
8524 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8525 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8526 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8527 exp->X_op = O_subtract;
8528 exp->X_op_symbol = GOT_symbol;
8529 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8530 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8531 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8532 i.reloc[this_operand] = BFD_RELOC_64;
8533 else
8534 i.reloc[this_operand] = BFD_RELOC_32;
8535 }
8536
8537 else if (exp->X_op == O_absent
8538 || exp->X_op == O_illegal
8539 || exp->X_op == O_big)
8540 {
8541 inv_disp:
8542 as_bad (_("missing or invalid displacement expression `%s'"),
8543 disp_start);
8544 ret = 0;
8545 }
8546
8547 else if (flag_code == CODE_64BIT
8548 && !i.prefix[ADDR_PREFIX]
8549 && exp->X_op == O_constant)
8550 {
8551 /* Since displacement is signed extended to 64bit, don't allow
8552 disp32 and turn off disp32s if they are out of range. */
8553 i.types[this_operand].bitfield.disp32 = 0;
8554 if (!fits_in_signed_long (exp->X_add_number))
8555 {
8556 i.types[this_operand].bitfield.disp32s = 0;
8557 if (i.types[this_operand].bitfield.baseindex)
8558 {
8559 as_bad (_("0x%lx out range of signed 32bit displacement"),
8560 (long) exp->X_add_number);
8561 ret = 0;
8562 }
8563 }
8564 }
8565
8566 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8567 else if (exp->X_op != O_constant
8568 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8569 && exp_seg != absolute_section
8570 && exp_seg != text_section
8571 && exp_seg != data_section
8572 && exp_seg != bss_section
8573 && exp_seg != undefined_section
8574 && !bfd_is_com_section (exp_seg))
8575 {
8576 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8577 ret = 0;
8578 }
8579 #endif
8580
8581 /* Check if this is a displacement only operand. */
8582 bigdisp = i.types[this_operand];
8583 bigdisp.bitfield.disp8 = 0;
8584 bigdisp.bitfield.disp16 = 0;
8585 bigdisp.bitfield.disp32 = 0;
8586 bigdisp.bitfield.disp32s = 0;
8587 bigdisp.bitfield.disp64 = 0;
8588 if (operand_type_all_zero (&bigdisp))
8589 i.types[this_operand] = operand_type_and (i.types[this_operand],
8590 types);
8591
8592 return ret;
8593 }
8594
8595 /* Return the active addressing mode, taking address override and
8596 registers forming the address into consideration. Update the
8597 address override prefix if necessary. */
8598
8599 static enum flag_code
8600 i386_addressing_mode (void)
8601 {
8602 enum flag_code addr_mode;
8603
8604 if (i.prefix[ADDR_PREFIX])
8605 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8606 else
8607 {
8608 addr_mode = flag_code;
8609
8610 #if INFER_ADDR_PREFIX
8611 if (i.mem_operands == 0)
8612 {
8613 /* Infer address prefix from the first memory operand. */
8614 const reg_entry *addr_reg = i.base_reg;
8615
8616 if (addr_reg == NULL)
8617 addr_reg = i.index_reg;
8618
8619 if (addr_reg)
8620 {
8621 if (addr_reg->reg_num == RegEip
8622 || addr_reg->reg_num == RegEiz
8623 || addr_reg->reg_type.bitfield.dword)
8624 addr_mode = CODE_32BIT;
8625 else if (flag_code != CODE_64BIT
8626 && addr_reg->reg_type.bitfield.word)
8627 addr_mode = CODE_16BIT;
8628
8629 if (addr_mode != flag_code)
8630 {
8631 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8632 i.prefixes += 1;
8633 /* Change the size of any displacement too. At most one
8634 of Disp16 or Disp32 is set.
8635 FIXME. There doesn't seem to be any real need for
8636 separate Disp16 and Disp32 flags. The same goes for
8637 Imm16 and Imm32. Removing them would probably clean
8638 up the code quite a lot. */
8639 if (flag_code != CODE_64BIT
8640 && (i.types[this_operand].bitfield.disp16
8641 || i.types[this_operand].bitfield.disp32))
8642 i.types[this_operand]
8643 = operand_type_xor (i.types[this_operand], disp16_32);
8644 }
8645 }
8646 }
8647 #endif
8648 }
8649
8650 return addr_mode;
8651 }
8652
8653 /* Make sure the memory operand we've been dealt is valid.
8654 Return 1 on success, 0 on a failure. */
8655
8656 static int
8657 i386_index_check (const char *operand_string)
8658 {
8659 const char *kind = "base/index";
8660 enum flag_code addr_mode = i386_addressing_mode ();
8661
8662 if (current_templates->start->opcode_modifier.isstring
8663 && !current_templates->start->opcode_modifier.immext
8664 && (current_templates->end[-1].opcode_modifier.isstring
8665 || i.mem_operands))
8666 {
8667 /* Memory operands of string insns are special in that they only allow
8668 a single register (rDI, rSI, or rBX) as their memory address. */
8669 const reg_entry *expected_reg;
8670 static const char *di_si[][2] =
8671 {
8672 { "esi", "edi" },
8673 { "si", "di" },
8674 { "rsi", "rdi" }
8675 };
8676 static const char *bx[] = { "ebx", "bx", "rbx" };
8677
8678 kind = "string address";
8679
8680 if (current_templates->start->opcode_modifier.repprefixok)
8681 {
8682 i386_operand_type type = current_templates->end[-1].operand_types[0];
8683
8684 if (!type.bitfield.baseindex
8685 || ((!i.mem_operands != !intel_syntax)
8686 && current_templates->end[-1].operand_types[1]
8687 .bitfield.baseindex))
8688 type = current_templates->end[-1].operand_types[1];
8689 expected_reg = hash_find (reg_hash,
8690 di_si[addr_mode][type.bitfield.esseg]);
8691
8692 }
8693 else
8694 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8695
8696 if (i.base_reg != expected_reg
8697 || i.index_reg
8698 || operand_type_check (i.types[this_operand], disp))
8699 {
8700 /* The second memory operand must have the same size as
8701 the first one. */
8702 if (i.mem_operands
8703 && i.base_reg
8704 && !((addr_mode == CODE_64BIT
8705 && i.base_reg->reg_type.bitfield.qword)
8706 || (addr_mode == CODE_32BIT
8707 ? i.base_reg->reg_type.bitfield.dword
8708 : i.base_reg->reg_type.bitfield.word)))
8709 goto bad_address;
8710
8711 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8712 operand_string,
8713 intel_syntax ? '[' : '(',
8714 register_prefix,
8715 expected_reg->reg_name,
8716 intel_syntax ? ']' : ')');
8717 return 1;
8718 }
8719 else
8720 return 1;
8721
8722 bad_address:
8723 as_bad (_("`%s' is not a valid %s expression"),
8724 operand_string, kind);
8725 return 0;
8726 }
8727 else
8728 {
8729 if (addr_mode != CODE_16BIT)
8730 {
8731 /* 32-bit/64-bit checks. */
8732 if ((i.base_reg
8733 && (addr_mode == CODE_64BIT
8734 ? !i.base_reg->reg_type.bitfield.qword
8735 : !i.base_reg->reg_type.bitfield.dword)
8736 && (i.index_reg
8737 || (i.base_reg->reg_num
8738 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8739 || (i.index_reg
8740 && !i.index_reg->reg_type.bitfield.xmmword
8741 && !i.index_reg->reg_type.bitfield.ymmword
8742 && !i.index_reg->reg_type.bitfield.zmmword
8743 && ((addr_mode == CODE_64BIT
8744 ? !(i.index_reg->reg_type.bitfield.qword
8745 || i.index_reg->reg_num == RegRiz)
8746 : !(i.index_reg->reg_type.bitfield.dword
8747 || i.index_reg->reg_num == RegEiz))
8748 || !i.index_reg->reg_type.bitfield.baseindex)))
8749 goto bad_address;
8750
8751 /* bndmk, bndldx, and bndstx have special restrictions. */
8752 if (current_templates->start->base_opcode == 0xf30f1b
8753 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8754 {
8755 /* They cannot use RIP-relative addressing. */
8756 if (i.base_reg && i.base_reg->reg_num == RegRip)
8757 {
8758 as_bad (_("`%s' cannot be used here"), operand_string);
8759 return 0;
8760 }
8761
8762 /* bndldx and bndstx ignore their scale factor. */
8763 if (current_templates->start->base_opcode != 0xf30f1b
8764 && i.log2_scale_factor)
8765 as_warn (_("register scaling is being ignored here"));
8766 }
8767 }
8768 else
8769 {
8770 /* 16-bit checks. */
8771 if ((i.base_reg
8772 && (!i.base_reg->reg_type.bitfield.word
8773 || !i.base_reg->reg_type.bitfield.baseindex))
8774 || (i.index_reg
8775 && (!i.index_reg->reg_type.bitfield.word
8776 || !i.index_reg->reg_type.bitfield.baseindex
8777 || !(i.base_reg
8778 && i.base_reg->reg_num < 6
8779 && i.index_reg->reg_num >= 6
8780 && i.log2_scale_factor == 0))))
8781 goto bad_address;
8782 }
8783 }
8784 return 1;
8785 }
8786
8787 /* Handle vector immediates. */
8788
8789 static int
8790 RC_SAE_immediate (const char *imm_start)
8791 {
8792 unsigned int match_found, j;
8793 const char *pstr = imm_start;
8794 expressionS *exp;
8795
8796 if (*pstr != '{')
8797 return 0;
8798
8799 pstr++;
8800 match_found = 0;
8801 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8802 {
8803 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8804 {
8805 if (!i.rounding)
8806 {
8807 rc_op.type = RC_NamesTable[j].type;
8808 rc_op.operand = this_operand;
8809 i.rounding = &rc_op;
8810 }
8811 else
8812 {
8813 as_bad (_("duplicated `%s'"), imm_start);
8814 return 0;
8815 }
8816 pstr += RC_NamesTable[j].len;
8817 match_found = 1;
8818 break;
8819 }
8820 }
8821 if (!match_found)
8822 return 0;
8823
8824 if (*pstr++ != '}')
8825 {
8826 as_bad (_("Missing '}': '%s'"), imm_start);
8827 return 0;
8828 }
8829 /* RC/SAE immediate string should contain nothing more. */;
8830 if (*pstr != 0)
8831 {
8832 as_bad (_("Junk after '}': '%s'"), imm_start);
8833 return 0;
8834 }
8835
8836 exp = &im_expressions[i.imm_operands++];
8837 i.op[this_operand].imms = exp;
8838
8839 exp->X_op = O_constant;
8840 exp->X_add_number = 0;
8841 exp->X_add_symbol = (symbolS *) 0;
8842 exp->X_op_symbol = (symbolS *) 0;
8843
8844 i.types[this_operand].bitfield.imm8 = 1;
8845 return 1;
8846 }
8847
8848 /* Only string instructions can have a second memory operand, so
8849 reduce current_templates to just those if it contains any. */
8850 static int
8851 maybe_adjust_templates (void)
8852 {
8853 const insn_template *t;
8854
8855 gas_assert (i.mem_operands == 1);
8856
8857 for (t = current_templates->start; t < current_templates->end; ++t)
8858 if (t->opcode_modifier.isstring)
8859 break;
8860
8861 if (t < current_templates->end)
8862 {
8863 static templates aux_templates;
8864 bfd_boolean recheck;
8865
8866 aux_templates.start = t;
8867 for (; t < current_templates->end; ++t)
8868 if (!t->opcode_modifier.isstring)
8869 break;
8870 aux_templates.end = t;
8871
8872 /* Determine whether to re-check the first memory operand. */
8873 recheck = (aux_templates.start != current_templates->start
8874 || t != current_templates->end);
8875
8876 current_templates = &aux_templates;
8877
8878 if (recheck)
8879 {
8880 i.mem_operands = 0;
8881 if (i.memop1_string != NULL
8882 && i386_index_check (i.memop1_string) == 0)
8883 return 0;
8884 i.mem_operands = 1;
8885 }
8886 }
8887
8888 return 1;
8889 }
8890
8891 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8892 on error. */
8893
8894 static int
8895 i386_att_operand (char *operand_string)
8896 {
8897 const reg_entry *r;
8898 char *end_op;
8899 char *op_string = operand_string;
8900
8901 if (is_space_char (*op_string))
8902 ++op_string;
8903
8904 /* We check for an absolute prefix (differentiating,
8905 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8906 if (*op_string == ABSOLUTE_PREFIX)
8907 {
8908 ++op_string;
8909 if (is_space_char (*op_string))
8910 ++op_string;
8911 i.types[this_operand].bitfield.jumpabsolute = 1;
8912 }
8913
8914 /* Check if operand is a register. */
8915 if ((r = parse_register (op_string, &end_op)) != NULL)
8916 {
8917 i386_operand_type temp;
8918
8919 /* Check for a segment override by searching for ':' after a
8920 segment register. */
8921 op_string = end_op;
8922 if (is_space_char (*op_string))
8923 ++op_string;
8924 if (*op_string == ':'
8925 && (r->reg_type.bitfield.sreg2
8926 || r->reg_type.bitfield.sreg3))
8927 {
8928 switch (r->reg_num)
8929 {
8930 case 0:
8931 i.seg[i.mem_operands] = &es;
8932 break;
8933 case 1:
8934 i.seg[i.mem_operands] = &cs;
8935 break;
8936 case 2:
8937 i.seg[i.mem_operands] = &ss;
8938 break;
8939 case 3:
8940 i.seg[i.mem_operands] = &ds;
8941 break;
8942 case 4:
8943 i.seg[i.mem_operands] = &fs;
8944 break;
8945 case 5:
8946 i.seg[i.mem_operands] = &gs;
8947 break;
8948 }
8949
8950 /* Skip the ':' and whitespace. */
8951 ++op_string;
8952 if (is_space_char (*op_string))
8953 ++op_string;
8954
8955 if (!is_digit_char (*op_string)
8956 && !is_identifier_char (*op_string)
8957 && *op_string != '('
8958 && *op_string != ABSOLUTE_PREFIX)
8959 {
8960 as_bad (_("bad memory operand `%s'"), op_string);
8961 return 0;
8962 }
8963 /* Handle case of %es:*foo. */
8964 if (*op_string == ABSOLUTE_PREFIX)
8965 {
8966 ++op_string;
8967 if (is_space_char (*op_string))
8968 ++op_string;
8969 i.types[this_operand].bitfield.jumpabsolute = 1;
8970 }
8971 goto do_memory_reference;
8972 }
8973
8974 /* Handle vector operations. */
8975 if (*op_string == '{')
8976 {
8977 op_string = check_VecOperations (op_string, NULL);
8978 if (op_string == NULL)
8979 return 0;
8980 }
8981
8982 if (*op_string)
8983 {
8984 as_bad (_("junk `%s' after register"), op_string);
8985 return 0;
8986 }
8987 temp = r->reg_type;
8988 temp.bitfield.baseindex = 0;
8989 i.types[this_operand] = operand_type_or (i.types[this_operand],
8990 temp);
8991 i.types[this_operand].bitfield.unspecified = 0;
8992 i.op[this_operand].regs = r;
8993 i.reg_operands++;
8994 }
8995 else if (*op_string == REGISTER_PREFIX)
8996 {
8997 as_bad (_("bad register name `%s'"), op_string);
8998 return 0;
8999 }
9000 else if (*op_string == IMMEDIATE_PREFIX)
9001 {
9002 ++op_string;
9003 if (i.types[this_operand].bitfield.jumpabsolute)
9004 {
9005 as_bad (_("immediate operand illegal with absolute jump"));
9006 return 0;
9007 }
9008 if (!i386_immediate (op_string))
9009 return 0;
9010 }
9011 else if (RC_SAE_immediate (operand_string))
9012 {
9013 /* If it is a RC or SAE immediate, do nothing. */
9014 ;
9015 }
9016 else if (is_digit_char (*op_string)
9017 || is_identifier_char (*op_string)
9018 || *op_string == '"'
9019 || *op_string == '(')
9020 {
9021 /* This is a memory reference of some sort. */
9022 char *base_string;
9023
9024 /* Start and end of displacement string expression (if found). */
9025 char *displacement_string_start;
9026 char *displacement_string_end;
9027 char *vop_start;
9028
9029 do_memory_reference:
9030 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9031 return 0;
9032 if ((i.mem_operands == 1
9033 && !current_templates->start->opcode_modifier.isstring)
9034 || i.mem_operands == 2)
9035 {
9036 as_bad (_("too many memory references for `%s'"),
9037 current_templates->start->name);
9038 return 0;
9039 }
9040
9041 /* Check for base index form. We detect the base index form by
9042 looking for an ')' at the end of the operand, searching
9043 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9044 after the '('. */
9045 base_string = op_string + strlen (op_string);
9046
9047 /* Handle vector operations. */
9048 vop_start = strchr (op_string, '{');
9049 if (vop_start && vop_start < base_string)
9050 {
9051 if (check_VecOperations (vop_start, base_string) == NULL)
9052 return 0;
9053 base_string = vop_start;
9054 }
9055
9056 --base_string;
9057 if (is_space_char (*base_string))
9058 --base_string;
9059
9060 /* If we only have a displacement, set-up for it to be parsed later. */
9061 displacement_string_start = op_string;
9062 displacement_string_end = base_string + 1;
9063
9064 if (*base_string == ')')
9065 {
9066 char *temp_string;
9067 unsigned int parens_balanced = 1;
9068 /* We've already checked that the number of left & right ()'s are
9069 equal, so this loop will not be infinite. */
9070 do
9071 {
9072 base_string--;
9073 if (*base_string == ')')
9074 parens_balanced++;
9075 if (*base_string == '(')
9076 parens_balanced--;
9077 }
9078 while (parens_balanced);
9079
9080 temp_string = base_string;
9081
9082 /* Skip past '(' and whitespace. */
9083 ++base_string;
9084 if (is_space_char (*base_string))
9085 ++base_string;
9086
9087 if (*base_string == ','
9088 || ((i.base_reg = parse_register (base_string, &end_op))
9089 != NULL))
9090 {
9091 displacement_string_end = temp_string;
9092
9093 i.types[this_operand].bitfield.baseindex = 1;
9094
9095 if (i.base_reg)
9096 {
9097 base_string = end_op;
9098 if (is_space_char (*base_string))
9099 ++base_string;
9100 }
9101
9102 /* There may be an index reg or scale factor here. */
9103 if (*base_string == ',')
9104 {
9105 ++base_string;
9106 if (is_space_char (*base_string))
9107 ++base_string;
9108
9109 if ((i.index_reg = parse_register (base_string, &end_op))
9110 != NULL)
9111 {
9112 base_string = end_op;
9113 if (is_space_char (*base_string))
9114 ++base_string;
9115 if (*base_string == ',')
9116 {
9117 ++base_string;
9118 if (is_space_char (*base_string))
9119 ++base_string;
9120 }
9121 else if (*base_string != ')')
9122 {
9123 as_bad (_("expecting `,' or `)' "
9124 "after index register in `%s'"),
9125 operand_string);
9126 return 0;
9127 }
9128 }
9129 else if (*base_string == REGISTER_PREFIX)
9130 {
9131 end_op = strchr (base_string, ',');
9132 if (end_op)
9133 *end_op = '\0';
9134 as_bad (_("bad register name `%s'"), base_string);
9135 return 0;
9136 }
9137
9138 /* Check for scale factor. */
9139 if (*base_string != ')')
9140 {
9141 char *end_scale = i386_scale (base_string);
9142
9143 if (!end_scale)
9144 return 0;
9145
9146 base_string = end_scale;
9147 if (is_space_char (*base_string))
9148 ++base_string;
9149 if (*base_string != ')')
9150 {
9151 as_bad (_("expecting `)' "
9152 "after scale factor in `%s'"),
9153 operand_string);
9154 return 0;
9155 }
9156 }
9157 else if (!i.index_reg)
9158 {
9159 as_bad (_("expecting index register or scale factor "
9160 "after `,'; got '%c'"),
9161 *base_string);
9162 return 0;
9163 }
9164 }
9165 else if (*base_string != ')')
9166 {
9167 as_bad (_("expecting `,' or `)' "
9168 "after base register in `%s'"),
9169 operand_string);
9170 return 0;
9171 }
9172 }
9173 else if (*base_string == REGISTER_PREFIX)
9174 {
9175 end_op = strchr (base_string, ',');
9176 if (end_op)
9177 *end_op = '\0';
9178 as_bad (_("bad register name `%s'"), base_string);
9179 return 0;
9180 }
9181 }
9182
9183 /* If there's an expression beginning the operand, parse it,
9184 assuming displacement_string_start and
9185 displacement_string_end are meaningful. */
9186 if (displacement_string_start != displacement_string_end)
9187 {
9188 if (!i386_displacement (displacement_string_start,
9189 displacement_string_end))
9190 return 0;
9191 }
9192
9193 /* Special case for (%dx) while doing input/output op. */
9194 if (i.base_reg
9195 && operand_type_equal (&i.base_reg->reg_type,
9196 &reg16_inoutportreg)
9197 && i.index_reg == 0
9198 && i.log2_scale_factor == 0
9199 && i.seg[i.mem_operands] == 0
9200 && !operand_type_check (i.types[this_operand], disp))
9201 {
9202 i.types[this_operand] = inoutportreg;
9203 return 1;
9204 }
9205
9206 if (i386_index_check (operand_string) == 0)
9207 return 0;
9208 i.types[this_operand].bitfield.mem = 1;
9209 if (i.mem_operands == 0)
9210 i.memop1_string = xstrdup (operand_string);
9211 i.mem_operands++;
9212 }
9213 else
9214 {
9215 /* It's not a memory operand; argh! */
9216 as_bad (_("invalid char %s beginning operand %d `%s'"),
9217 output_invalid (*op_string),
9218 this_operand + 1,
9219 op_string);
9220 return 0;
9221 }
9222 return 1; /* Normal return. */
9223 }
9224 \f
9225 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9226 that an rs_machine_dependent frag may reach. */
9227
9228 unsigned int
9229 i386_frag_max_var (fragS *frag)
9230 {
9231 /* The only relaxable frags are for jumps.
9232 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9233 gas_assert (frag->fr_type == rs_machine_dependent);
9234 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9235 }
9236
9237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9238 static int
9239 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9240 {
9241 /* STT_GNU_IFUNC symbol must go through PLT. */
9242 if ((symbol_get_bfdsym (fr_symbol)->flags
9243 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9244 return 0;
9245
9246 if (!S_IS_EXTERNAL (fr_symbol))
9247 /* Symbol may be weak or local. */
9248 return !S_IS_WEAK (fr_symbol);
9249
9250 /* Global symbols with non-default visibility can't be preempted. */
9251 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9252 return 1;
9253
9254 if (fr_var != NO_RELOC)
9255 switch ((enum bfd_reloc_code_real) fr_var)
9256 {
9257 case BFD_RELOC_386_PLT32:
9258 case BFD_RELOC_X86_64_PLT32:
9259 /* Symbol with PLT relocation may be preempted. */
9260 return 0;
9261 default:
9262 abort ();
9263 }
9264
9265 /* Global symbols with default visibility in a shared library may be
9266 preempted by another definition. */
9267 return !shared;
9268 }
9269 #endif
9270
9271 /* md_estimate_size_before_relax()
9272
9273 Called just before relax() for rs_machine_dependent frags. The x86
9274 assembler uses these frags to handle variable size jump
9275 instructions.
9276
9277 Any symbol that is now undefined will not become defined.
9278 Return the correct fr_subtype in the frag.
9279 Return the initial "guess for variable size of frag" to caller.
9280 The guess is actually the growth beyond the fixed part. Whatever
9281 we do to grow the fixed or variable part contributes to our
9282 returned value. */
9283
9284 int
9285 md_estimate_size_before_relax (fragS *fragP, segT segment)
9286 {
9287 /* We've already got fragP->fr_subtype right; all we have to do is
9288 check for un-relaxable symbols. On an ELF system, we can't relax
9289 an externally visible symbol, because it may be overridden by a
9290 shared library. */
9291 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9292 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9293 || (IS_ELF
9294 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9295 fragP->fr_var))
9296 #endif
9297 #if defined (OBJ_COFF) && defined (TE_PE)
9298 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9299 && S_IS_WEAK (fragP->fr_symbol))
9300 #endif
9301 )
9302 {
9303 /* Symbol is undefined in this segment, or we need to keep a
9304 reloc so that weak symbols can be overridden. */
9305 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9306 enum bfd_reloc_code_real reloc_type;
9307 unsigned char *opcode;
9308 int old_fr_fix;
9309
9310 if (fragP->fr_var != NO_RELOC)
9311 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9312 else if (size == 2)
9313 reloc_type = BFD_RELOC_16_PCREL;
9314 else
9315 reloc_type = BFD_RELOC_32_PCREL;
9316
9317 old_fr_fix = fragP->fr_fix;
9318 opcode = (unsigned char *) fragP->fr_opcode;
9319
9320 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9321 {
9322 case UNCOND_JUMP:
9323 /* Make jmp (0xeb) a (d)word displacement jump. */
9324 opcode[0] = 0xe9;
9325 fragP->fr_fix += size;
9326 fix_new (fragP, old_fr_fix, size,
9327 fragP->fr_symbol,
9328 fragP->fr_offset, 1,
9329 reloc_type);
9330 break;
9331
9332 case COND_JUMP86:
9333 if (size == 2
9334 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9335 {
9336 /* Negate the condition, and branch past an
9337 unconditional jump. */
9338 opcode[0] ^= 1;
9339 opcode[1] = 3;
9340 /* Insert an unconditional jump. */
9341 opcode[2] = 0xe9;
9342 /* We added two extra opcode bytes, and have a two byte
9343 offset. */
9344 fragP->fr_fix += 2 + 2;
9345 fix_new (fragP, old_fr_fix + 2, 2,
9346 fragP->fr_symbol,
9347 fragP->fr_offset, 1,
9348 reloc_type);
9349 break;
9350 }
9351 /* Fall through. */
9352
9353 case COND_JUMP:
9354 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9355 {
9356 fixS *fixP;
9357
9358 fragP->fr_fix += 1;
9359 fixP = fix_new (fragP, old_fr_fix, 1,
9360 fragP->fr_symbol,
9361 fragP->fr_offset, 1,
9362 BFD_RELOC_8_PCREL);
9363 fixP->fx_signed = 1;
9364 break;
9365 }
9366
9367 /* This changes the byte-displacement jump 0x7N
9368 to the (d)word-displacement jump 0x0f,0x8N. */
9369 opcode[1] = opcode[0] + 0x10;
9370 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9371 /* We've added an opcode byte. */
9372 fragP->fr_fix += 1 + size;
9373 fix_new (fragP, old_fr_fix + 1, size,
9374 fragP->fr_symbol,
9375 fragP->fr_offset, 1,
9376 reloc_type);
9377 break;
9378
9379 default:
9380 BAD_CASE (fragP->fr_subtype);
9381 break;
9382 }
9383 frag_wane (fragP);
9384 return fragP->fr_fix - old_fr_fix;
9385 }
9386
9387 /* Guess size depending on current relax state. Initially the relax
9388 state will correspond to a short jump and we return 1, because
9389 the variable part of the frag (the branch offset) is one byte
9390 long. However, we can relax a section more than once and in that
9391 case we must either set fr_subtype back to the unrelaxed state,
9392 or return the value for the appropriate branch. */
9393 return md_relax_table[fragP->fr_subtype].rlx_length;
9394 }
9395
9396 /* Called after relax() is finished.
9397
9398 In: Address of frag.
9399 fr_type == rs_machine_dependent.
9400 fr_subtype is what the address relaxed to.
9401
9402 Out: Any fixSs and constants are set up.
9403 Caller will turn frag into a ".space 0". */
9404
9405 void
9406 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9407 fragS *fragP)
9408 {
9409 unsigned char *opcode;
9410 unsigned char *where_to_put_displacement = NULL;
9411 offsetT target_address;
9412 offsetT opcode_address;
9413 unsigned int extension = 0;
9414 offsetT displacement_from_opcode_start;
9415
9416 opcode = (unsigned char *) fragP->fr_opcode;
9417
9418 /* Address we want to reach in file space. */
9419 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9420
9421 /* Address opcode resides at in file space. */
9422 opcode_address = fragP->fr_address + fragP->fr_fix;
9423
9424 /* Displacement from opcode start to fill into instruction. */
9425 displacement_from_opcode_start = target_address - opcode_address;
9426
9427 if ((fragP->fr_subtype & BIG) == 0)
9428 {
9429 /* Don't have to change opcode. */
9430 extension = 1; /* 1 opcode + 1 displacement */
9431 where_to_put_displacement = &opcode[1];
9432 }
9433 else
9434 {
9435 if (no_cond_jump_promotion
9436 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9437 as_warn_where (fragP->fr_file, fragP->fr_line,
9438 _("long jump required"));
9439
9440 switch (fragP->fr_subtype)
9441 {
9442 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9443 extension = 4; /* 1 opcode + 4 displacement */
9444 opcode[0] = 0xe9;
9445 where_to_put_displacement = &opcode[1];
9446 break;
9447
9448 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9449 extension = 2; /* 1 opcode + 2 displacement */
9450 opcode[0] = 0xe9;
9451 where_to_put_displacement = &opcode[1];
9452 break;
9453
9454 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9455 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9456 extension = 5; /* 2 opcode + 4 displacement */
9457 opcode[1] = opcode[0] + 0x10;
9458 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9459 where_to_put_displacement = &opcode[2];
9460 break;
9461
9462 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9463 extension = 3; /* 2 opcode + 2 displacement */
9464 opcode[1] = opcode[0] + 0x10;
9465 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9466 where_to_put_displacement = &opcode[2];
9467 break;
9468
9469 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9470 extension = 4;
9471 opcode[0] ^= 1;
9472 opcode[1] = 3;
9473 opcode[2] = 0xe9;
9474 where_to_put_displacement = &opcode[3];
9475 break;
9476
9477 default:
9478 BAD_CASE (fragP->fr_subtype);
9479 break;
9480 }
9481 }
9482
9483 /* If size if less then four we are sure that the operand fits,
9484 but if it's 4, then it could be that the displacement is larger
9485 then -/+ 2GB. */
9486 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9487 && object_64bit
9488 && ((addressT) (displacement_from_opcode_start - extension
9489 + ((addressT) 1 << 31))
9490 > (((addressT) 2 << 31) - 1)))
9491 {
9492 as_bad_where (fragP->fr_file, fragP->fr_line,
9493 _("jump target out of range"));
9494 /* Make us emit 0. */
9495 displacement_from_opcode_start = extension;
9496 }
9497 /* Now put displacement after opcode. */
9498 md_number_to_chars ((char *) where_to_put_displacement,
9499 (valueT) (displacement_from_opcode_start - extension),
9500 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9501 fragP->fr_fix += extension;
9502 }
9503 \f
9504 /* Apply a fixup (fixP) to segment data, once it has been determined
9505 by our caller that we have all the info we need to fix it up.
9506
9507 Parameter valP is the pointer to the value of the bits.
9508
9509 On the 386, immediates, displacements, and data pointers are all in
9510 the same (little-endian) format, so we don't need to care about which
9511 we are handling. */
9512
9513 void
9514 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9515 {
9516 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9517 valueT value = *valP;
9518
9519 #if !defined (TE_Mach)
9520 if (fixP->fx_pcrel)
9521 {
9522 switch (fixP->fx_r_type)
9523 {
9524 default:
9525 break;
9526
9527 case BFD_RELOC_64:
9528 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9529 break;
9530 case BFD_RELOC_32:
9531 case BFD_RELOC_X86_64_32S:
9532 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9533 break;
9534 case BFD_RELOC_16:
9535 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9536 break;
9537 case BFD_RELOC_8:
9538 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9539 break;
9540 }
9541 }
9542
9543 if (fixP->fx_addsy != NULL
9544 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9545 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9546 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9547 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9548 && !use_rela_relocations)
9549 {
9550 /* This is a hack. There should be a better way to handle this.
9551 This covers for the fact that bfd_install_relocation will
9552 subtract the current location (for partial_inplace, PC relative
9553 relocations); see more below. */
9554 #ifndef OBJ_AOUT
9555 if (IS_ELF
9556 #ifdef TE_PE
9557 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9558 #endif
9559 )
9560 value += fixP->fx_where + fixP->fx_frag->fr_address;
9561 #endif
9562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9563 if (IS_ELF)
9564 {
9565 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9566
9567 if ((sym_seg == seg
9568 || (symbol_section_p (fixP->fx_addsy)
9569 && sym_seg != absolute_section))
9570 && !generic_force_reloc (fixP))
9571 {
9572 /* Yes, we add the values in twice. This is because
9573 bfd_install_relocation subtracts them out again. I think
9574 bfd_install_relocation is broken, but I don't dare change
9575 it. FIXME. */
9576 value += fixP->fx_where + fixP->fx_frag->fr_address;
9577 }
9578 }
9579 #endif
9580 #if defined (OBJ_COFF) && defined (TE_PE)
9581 /* For some reason, the PE format does not store a
9582 section address offset for a PC relative symbol. */
9583 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9584 || S_IS_WEAK (fixP->fx_addsy))
9585 value += md_pcrel_from (fixP);
9586 #endif
9587 }
9588 #if defined (OBJ_COFF) && defined (TE_PE)
9589 if (fixP->fx_addsy != NULL
9590 && S_IS_WEAK (fixP->fx_addsy)
9591 /* PR 16858: Do not modify weak function references. */
9592 && ! fixP->fx_pcrel)
9593 {
9594 #if !defined (TE_PEP)
9595 /* For x86 PE weak function symbols are neither PC-relative
9596 nor do they set S_IS_FUNCTION. So the only reliable way
9597 to detect them is to check the flags of their containing
9598 section. */
9599 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9600 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9601 ;
9602 else
9603 #endif
9604 value -= S_GET_VALUE (fixP->fx_addsy);
9605 }
9606 #endif
9607
9608 /* Fix a few things - the dynamic linker expects certain values here,
9609 and we must not disappoint it. */
9610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9611 if (IS_ELF && fixP->fx_addsy)
9612 switch (fixP->fx_r_type)
9613 {
9614 case BFD_RELOC_386_PLT32:
9615 case BFD_RELOC_X86_64_PLT32:
9616 /* Make the jump instruction point to the address of the operand. At
9617 runtime we merely add the offset to the actual PLT entry. */
9618 value = -4;
9619 break;
9620
9621 case BFD_RELOC_386_TLS_GD:
9622 case BFD_RELOC_386_TLS_LDM:
9623 case BFD_RELOC_386_TLS_IE_32:
9624 case BFD_RELOC_386_TLS_IE:
9625 case BFD_RELOC_386_TLS_GOTIE:
9626 case BFD_RELOC_386_TLS_GOTDESC:
9627 case BFD_RELOC_X86_64_TLSGD:
9628 case BFD_RELOC_X86_64_TLSLD:
9629 case BFD_RELOC_X86_64_GOTTPOFF:
9630 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9631 value = 0; /* Fully resolved at runtime. No addend. */
9632 /* Fallthrough */
9633 case BFD_RELOC_386_TLS_LE:
9634 case BFD_RELOC_386_TLS_LDO_32:
9635 case BFD_RELOC_386_TLS_LE_32:
9636 case BFD_RELOC_X86_64_DTPOFF32:
9637 case BFD_RELOC_X86_64_DTPOFF64:
9638 case BFD_RELOC_X86_64_TPOFF32:
9639 case BFD_RELOC_X86_64_TPOFF64:
9640 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9641 break;
9642
9643 case BFD_RELOC_386_TLS_DESC_CALL:
9644 case BFD_RELOC_X86_64_TLSDESC_CALL:
9645 value = 0; /* Fully resolved at runtime. No addend. */
9646 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9647 fixP->fx_done = 0;
9648 return;
9649
9650 case BFD_RELOC_VTABLE_INHERIT:
9651 case BFD_RELOC_VTABLE_ENTRY:
9652 fixP->fx_done = 0;
9653 return;
9654
9655 default:
9656 break;
9657 }
9658 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9659 *valP = value;
9660 #endif /* !defined (TE_Mach) */
9661
9662 /* Are we finished with this relocation now? */
9663 if (fixP->fx_addsy == NULL)
9664 fixP->fx_done = 1;
9665 #if defined (OBJ_COFF) && defined (TE_PE)
9666 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9667 {
9668 fixP->fx_done = 0;
9669 /* Remember value for tc_gen_reloc. */
9670 fixP->fx_addnumber = value;
9671 /* Clear out the frag for now. */
9672 value = 0;
9673 }
9674 #endif
9675 else if (use_rela_relocations)
9676 {
9677 fixP->fx_no_overflow = 1;
9678 /* Remember value for tc_gen_reloc. */
9679 fixP->fx_addnumber = value;
9680 value = 0;
9681 }
9682
9683 md_number_to_chars (p, value, fixP->fx_size);
9684 }
9685 \f
9686 const char *
9687 md_atof (int type, char *litP, int *sizeP)
9688 {
9689 /* This outputs the LITTLENUMs in REVERSE order;
9690 in accord with the bigendian 386. */
9691 return ieee_md_atof (type, litP, sizeP, FALSE);
9692 }
9693 \f
9694 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9695
9696 static char *
9697 output_invalid (int c)
9698 {
9699 if (ISPRINT (c))
9700 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9701 "'%c'", c);
9702 else
9703 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9704 "(0x%x)", (unsigned char) c);
9705 return output_invalid_buf;
9706 }
9707
9708 /* REG_STRING starts *before* REGISTER_PREFIX. */
9709
9710 static const reg_entry *
9711 parse_real_register (char *reg_string, char **end_op)
9712 {
9713 char *s = reg_string;
9714 char *p;
9715 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9716 const reg_entry *r;
9717
9718 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9719 if (*s == REGISTER_PREFIX)
9720 ++s;
9721
9722 if (is_space_char (*s))
9723 ++s;
9724
9725 p = reg_name_given;
9726 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9727 {
9728 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9729 return (const reg_entry *) NULL;
9730 s++;
9731 }
9732
9733 /* For naked regs, make sure that we are not dealing with an identifier.
9734 This prevents confusing an identifier like `eax_var' with register
9735 `eax'. */
9736 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9737 return (const reg_entry *) NULL;
9738
9739 *end_op = s;
9740
9741 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9742
9743 /* Handle floating point regs, allowing spaces in the (i) part. */
9744 if (r == i386_regtab /* %st is first entry of table */)
9745 {
9746 if (is_space_char (*s))
9747 ++s;
9748 if (*s == '(')
9749 {
9750 ++s;
9751 if (is_space_char (*s))
9752 ++s;
9753 if (*s >= '0' && *s <= '7')
9754 {
9755 int fpr = *s - '0';
9756 ++s;
9757 if (is_space_char (*s))
9758 ++s;
9759 if (*s == ')')
9760 {
9761 *end_op = s + 1;
9762 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9763 know (r);
9764 return r + fpr;
9765 }
9766 }
9767 /* We have "%st(" then garbage. */
9768 return (const reg_entry *) NULL;
9769 }
9770 }
9771
9772 if (r == NULL || allow_pseudo_reg)
9773 return r;
9774
9775 if (operand_type_all_zero (&r->reg_type))
9776 return (const reg_entry *) NULL;
9777
9778 if ((r->reg_type.bitfield.dword
9779 || r->reg_type.bitfield.sreg3
9780 || r->reg_type.bitfield.control
9781 || r->reg_type.bitfield.debug
9782 || r->reg_type.bitfield.test)
9783 && !cpu_arch_flags.bitfield.cpui386)
9784 return (const reg_entry *) NULL;
9785
9786 if (r->reg_type.bitfield.tbyte
9787 && !cpu_arch_flags.bitfield.cpu8087
9788 && !cpu_arch_flags.bitfield.cpu287
9789 && !cpu_arch_flags.bitfield.cpu387)
9790 return (const reg_entry *) NULL;
9791
9792 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9793 return (const reg_entry *) NULL;
9794
9795 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
9796 return (const reg_entry *) NULL;
9797
9798 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
9799 return (const reg_entry *) NULL;
9800
9801 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
9802 return (const reg_entry *) NULL;
9803
9804 if (r->reg_type.bitfield.regmask
9805 && !cpu_arch_flags.bitfield.cpuregmask)
9806 return (const reg_entry *) NULL;
9807
9808 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9809 if (!allow_index_reg
9810 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9811 return (const reg_entry *) NULL;
9812
9813 /* Upper 16 vector register is only available with VREX in 64bit
9814 mode. */
9815 if ((r->reg_flags & RegVRex))
9816 {
9817 if (i.vec_encoding == vex_encoding_default)
9818 i.vec_encoding = vex_encoding_evex;
9819
9820 if (!cpu_arch_flags.bitfield.cpuvrex
9821 || i.vec_encoding != vex_encoding_evex
9822 || flag_code != CODE_64BIT)
9823 return (const reg_entry *) NULL;
9824 }
9825
9826 if (((r->reg_flags & (RegRex64 | RegRex))
9827 || r->reg_type.bitfield.qword)
9828 && (!cpu_arch_flags.bitfield.cpulm
9829 || !operand_type_equal (&r->reg_type, &control))
9830 && flag_code != CODE_64BIT)
9831 return (const reg_entry *) NULL;
9832
9833 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9834 return (const reg_entry *) NULL;
9835
9836 return r;
9837 }
9838
9839 /* REG_STRING starts *before* REGISTER_PREFIX. */
9840
9841 static const reg_entry *
9842 parse_register (char *reg_string, char **end_op)
9843 {
9844 const reg_entry *r;
9845
9846 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9847 r = parse_real_register (reg_string, end_op);
9848 else
9849 r = NULL;
9850 if (!r)
9851 {
9852 char *save = input_line_pointer;
9853 char c;
9854 symbolS *symbolP;
9855
9856 input_line_pointer = reg_string;
9857 c = get_symbol_name (&reg_string);
9858 symbolP = symbol_find (reg_string);
9859 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9860 {
9861 const expressionS *e = symbol_get_value_expression (symbolP);
9862
9863 know (e->X_op == O_register);
9864 know (e->X_add_number >= 0
9865 && (valueT) e->X_add_number < i386_regtab_size);
9866 r = i386_regtab + e->X_add_number;
9867 if ((r->reg_flags & RegVRex))
9868 i.vec_encoding = vex_encoding_evex;
9869 *end_op = input_line_pointer;
9870 }
9871 *input_line_pointer = c;
9872 input_line_pointer = save;
9873 }
9874 return r;
9875 }
9876
9877 int
9878 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9879 {
9880 const reg_entry *r;
9881 char *end = input_line_pointer;
9882
9883 *end = *nextcharP;
9884 r = parse_register (name, &input_line_pointer);
9885 if (r && end <= input_line_pointer)
9886 {
9887 *nextcharP = *input_line_pointer;
9888 *input_line_pointer = 0;
9889 e->X_op = O_register;
9890 e->X_add_number = r - i386_regtab;
9891 return 1;
9892 }
9893 input_line_pointer = end;
9894 *end = 0;
9895 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9896 }
9897
9898 void
9899 md_operand (expressionS *e)
9900 {
9901 char *end;
9902 const reg_entry *r;
9903
9904 switch (*input_line_pointer)
9905 {
9906 case REGISTER_PREFIX:
9907 r = parse_real_register (input_line_pointer, &end);
9908 if (r)
9909 {
9910 e->X_op = O_register;
9911 e->X_add_number = r - i386_regtab;
9912 input_line_pointer = end;
9913 }
9914 break;
9915
9916 case '[':
9917 gas_assert (intel_syntax);
9918 end = input_line_pointer++;
9919 expression (e);
9920 if (*input_line_pointer == ']')
9921 {
9922 ++input_line_pointer;
9923 e->X_op_symbol = make_expr_symbol (e);
9924 e->X_add_symbol = NULL;
9925 e->X_add_number = 0;
9926 e->X_op = O_index;
9927 }
9928 else
9929 {
9930 e->X_op = O_absent;
9931 input_line_pointer = end;
9932 }
9933 break;
9934 }
9935 }
9936
9937 \f
9938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9939 const char *md_shortopts = "kVQ:sqn";
9940 #else
9941 const char *md_shortopts = "qn";
9942 #endif
9943
9944 #define OPTION_32 (OPTION_MD_BASE + 0)
9945 #define OPTION_64 (OPTION_MD_BASE + 1)
9946 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9947 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9948 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9949 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9950 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9951 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9952 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9953 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9954 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9955 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9956 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9957 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9958 #define OPTION_X32 (OPTION_MD_BASE + 14)
9959 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9960 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9961 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9962 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9963 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9964 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9965 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9966 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9967 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9968 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9969 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9970
9971 struct option md_longopts[] =
9972 {
9973 {"32", no_argument, NULL, OPTION_32},
9974 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9975 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9976 {"64", no_argument, NULL, OPTION_64},
9977 #endif
9978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9979 {"x32", no_argument, NULL, OPTION_X32},
9980 {"mshared", no_argument, NULL, OPTION_MSHARED},
9981 #endif
9982 {"divide", no_argument, NULL, OPTION_DIVIDE},
9983 {"march", required_argument, NULL, OPTION_MARCH},
9984 {"mtune", required_argument, NULL, OPTION_MTUNE},
9985 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9986 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9987 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9988 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9989 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9990 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9991 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9992 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9993 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9994 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9995 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9996 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9997 # if defined (TE_PE) || defined (TE_PEP)
9998 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9999 #endif
10000 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10001 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10002 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10003 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10004 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10005 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10006 {NULL, no_argument, NULL, 0}
10007 };
10008 size_t md_longopts_size = sizeof (md_longopts);
10009
10010 int
10011 md_parse_option (int c, const char *arg)
10012 {
10013 unsigned int j;
10014 char *arch, *next, *saved;
10015
10016 switch (c)
10017 {
10018 case 'n':
10019 optimize_align_code = 0;
10020 break;
10021
10022 case 'q':
10023 quiet_warnings = 1;
10024 break;
10025
10026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10027 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10028 should be emitted or not. FIXME: Not implemented. */
10029 case 'Q':
10030 break;
10031
10032 /* -V: SVR4 argument to print version ID. */
10033 case 'V':
10034 print_version_id ();
10035 break;
10036
10037 /* -k: Ignore for FreeBSD compatibility. */
10038 case 'k':
10039 break;
10040
10041 case 's':
10042 /* -s: On i386 Solaris, this tells the native assembler to use
10043 .stab instead of .stab.excl. We always use .stab anyhow. */
10044 break;
10045
10046 case OPTION_MSHARED:
10047 shared = 1;
10048 break;
10049 #endif
10050 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10051 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10052 case OPTION_64:
10053 {
10054 const char **list, **l;
10055
10056 list = bfd_target_list ();
10057 for (l = list; *l != NULL; l++)
10058 if (CONST_STRNEQ (*l, "elf64-x86-64")
10059 || strcmp (*l, "coff-x86-64") == 0
10060 || strcmp (*l, "pe-x86-64") == 0
10061 || strcmp (*l, "pei-x86-64") == 0
10062 || strcmp (*l, "mach-o-x86-64") == 0)
10063 {
10064 default_arch = "x86_64";
10065 break;
10066 }
10067 if (*l == NULL)
10068 as_fatal (_("no compiled in support for x86_64"));
10069 free (list);
10070 }
10071 break;
10072 #endif
10073
10074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10075 case OPTION_X32:
10076 if (IS_ELF)
10077 {
10078 const char **list, **l;
10079
10080 list = bfd_target_list ();
10081 for (l = list; *l != NULL; l++)
10082 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10083 {
10084 default_arch = "x86_64:32";
10085 break;
10086 }
10087 if (*l == NULL)
10088 as_fatal (_("no compiled in support for 32bit x86_64"));
10089 free (list);
10090 }
10091 else
10092 as_fatal (_("32bit x86_64 is only supported for ELF"));
10093 break;
10094 #endif
10095
10096 case OPTION_32:
10097 default_arch = "i386";
10098 break;
10099
10100 case OPTION_DIVIDE:
10101 #ifdef SVR4_COMMENT_CHARS
10102 {
10103 char *n, *t;
10104 const char *s;
10105
10106 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10107 t = n;
10108 for (s = i386_comment_chars; *s != '\0'; s++)
10109 if (*s != '/')
10110 *t++ = *s;
10111 *t = '\0';
10112 i386_comment_chars = n;
10113 }
10114 #endif
10115 break;
10116
10117 case OPTION_MARCH:
10118 saved = xstrdup (arg);
10119 arch = saved;
10120 /* Allow -march=+nosse. */
10121 if (*arch == '+')
10122 arch++;
10123 do
10124 {
10125 if (*arch == '.')
10126 as_fatal (_("invalid -march= option: `%s'"), arg);
10127 next = strchr (arch, '+');
10128 if (next)
10129 *next++ = '\0';
10130 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10131 {
10132 if (strcmp (arch, cpu_arch [j].name) == 0)
10133 {
10134 /* Processor. */
10135 if (! cpu_arch[j].flags.bitfield.cpui386)
10136 continue;
10137
10138 cpu_arch_name = cpu_arch[j].name;
10139 cpu_sub_arch_name = NULL;
10140 cpu_arch_flags = cpu_arch[j].flags;
10141 cpu_arch_isa = cpu_arch[j].type;
10142 cpu_arch_isa_flags = cpu_arch[j].flags;
10143 if (!cpu_arch_tune_set)
10144 {
10145 cpu_arch_tune = cpu_arch_isa;
10146 cpu_arch_tune_flags = cpu_arch_isa_flags;
10147 }
10148 break;
10149 }
10150 else if (*cpu_arch [j].name == '.'
10151 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10152 {
10153 /* ISA extension. */
10154 i386_cpu_flags flags;
10155
10156 flags = cpu_flags_or (cpu_arch_flags,
10157 cpu_arch[j].flags);
10158
10159 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10160 {
10161 if (cpu_sub_arch_name)
10162 {
10163 char *name = cpu_sub_arch_name;
10164 cpu_sub_arch_name = concat (name,
10165 cpu_arch[j].name,
10166 (const char *) NULL);
10167 free (name);
10168 }
10169 else
10170 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10171 cpu_arch_flags = flags;
10172 cpu_arch_isa_flags = flags;
10173 }
10174 break;
10175 }
10176 }
10177
10178 if (j >= ARRAY_SIZE (cpu_arch))
10179 {
10180 /* Disable an ISA extension. */
10181 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10182 if (strcmp (arch, cpu_noarch [j].name) == 0)
10183 {
10184 i386_cpu_flags flags;
10185
10186 flags = cpu_flags_and_not (cpu_arch_flags,
10187 cpu_noarch[j].flags);
10188 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10189 {
10190 if (cpu_sub_arch_name)
10191 {
10192 char *name = cpu_sub_arch_name;
10193 cpu_sub_arch_name = concat (arch,
10194 (const char *) NULL);
10195 free (name);
10196 }
10197 else
10198 cpu_sub_arch_name = xstrdup (arch);
10199 cpu_arch_flags = flags;
10200 cpu_arch_isa_flags = flags;
10201 }
10202 break;
10203 }
10204
10205 if (j >= ARRAY_SIZE (cpu_noarch))
10206 j = ARRAY_SIZE (cpu_arch);
10207 }
10208
10209 if (j >= ARRAY_SIZE (cpu_arch))
10210 as_fatal (_("invalid -march= option: `%s'"), arg);
10211
10212 arch = next;
10213 }
10214 while (next != NULL);
10215 free (saved);
10216 break;
10217
10218 case OPTION_MTUNE:
10219 if (*arg == '.')
10220 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10221 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10222 {
10223 if (strcmp (arg, cpu_arch [j].name) == 0)
10224 {
10225 cpu_arch_tune_set = 1;
10226 cpu_arch_tune = cpu_arch [j].type;
10227 cpu_arch_tune_flags = cpu_arch[j].flags;
10228 break;
10229 }
10230 }
10231 if (j >= ARRAY_SIZE (cpu_arch))
10232 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10233 break;
10234
10235 case OPTION_MMNEMONIC:
10236 if (strcasecmp (arg, "att") == 0)
10237 intel_mnemonic = 0;
10238 else if (strcasecmp (arg, "intel") == 0)
10239 intel_mnemonic = 1;
10240 else
10241 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10242 break;
10243
10244 case OPTION_MSYNTAX:
10245 if (strcasecmp (arg, "att") == 0)
10246 intel_syntax = 0;
10247 else if (strcasecmp (arg, "intel") == 0)
10248 intel_syntax = 1;
10249 else
10250 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10251 break;
10252
10253 case OPTION_MINDEX_REG:
10254 allow_index_reg = 1;
10255 break;
10256
10257 case OPTION_MNAKED_REG:
10258 allow_naked_reg = 1;
10259 break;
10260
10261 case OPTION_MOLD_GCC:
10262 old_gcc = 1;
10263 break;
10264
10265 case OPTION_MSSE2AVX:
10266 sse2avx = 1;
10267 break;
10268
10269 case OPTION_MSSE_CHECK:
10270 if (strcasecmp (arg, "error") == 0)
10271 sse_check = check_error;
10272 else if (strcasecmp (arg, "warning") == 0)
10273 sse_check = check_warning;
10274 else if (strcasecmp (arg, "none") == 0)
10275 sse_check = check_none;
10276 else
10277 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10278 break;
10279
10280 case OPTION_MOPERAND_CHECK:
10281 if (strcasecmp (arg, "error") == 0)
10282 operand_check = check_error;
10283 else if (strcasecmp (arg, "warning") == 0)
10284 operand_check = check_warning;
10285 else if (strcasecmp (arg, "none") == 0)
10286 operand_check = check_none;
10287 else
10288 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10289 break;
10290
10291 case OPTION_MAVXSCALAR:
10292 if (strcasecmp (arg, "128") == 0)
10293 avxscalar = vex128;
10294 else if (strcasecmp (arg, "256") == 0)
10295 avxscalar = vex256;
10296 else
10297 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10298 break;
10299
10300 case OPTION_MADD_BND_PREFIX:
10301 add_bnd_prefix = 1;
10302 break;
10303
10304 case OPTION_MEVEXLIG:
10305 if (strcmp (arg, "128") == 0)
10306 evexlig = evexl128;
10307 else if (strcmp (arg, "256") == 0)
10308 evexlig = evexl256;
10309 else if (strcmp (arg, "512") == 0)
10310 evexlig = evexl512;
10311 else
10312 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10313 break;
10314
10315 case OPTION_MEVEXRCIG:
10316 if (strcmp (arg, "rne") == 0)
10317 evexrcig = rne;
10318 else if (strcmp (arg, "rd") == 0)
10319 evexrcig = rd;
10320 else if (strcmp (arg, "ru") == 0)
10321 evexrcig = ru;
10322 else if (strcmp (arg, "rz") == 0)
10323 evexrcig = rz;
10324 else
10325 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10326 break;
10327
10328 case OPTION_MEVEXWIG:
10329 if (strcmp (arg, "0") == 0)
10330 evexwig = evexw0;
10331 else if (strcmp (arg, "1") == 0)
10332 evexwig = evexw1;
10333 else
10334 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10335 break;
10336
10337 # if defined (TE_PE) || defined (TE_PEP)
10338 case OPTION_MBIG_OBJ:
10339 use_big_obj = 1;
10340 break;
10341 #endif
10342
10343 case OPTION_MOMIT_LOCK_PREFIX:
10344 if (strcasecmp (arg, "yes") == 0)
10345 omit_lock_prefix = 1;
10346 else if (strcasecmp (arg, "no") == 0)
10347 omit_lock_prefix = 0;
10348 else
10349 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10350 break;
10351
10352 case OPTION_MFENCE_AS_LOCK_ADD:
10353 if (strcasecmp (arg, "yes") == 0)
10354 avoid_fence = 1;
10355 else if (strcasecmp (arg, "no") == 0)
10356 avoid_fence = 0;
10357 else
10358 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10359 break;
10360
10361 case OPTION_MRELAX_RELOCATIONS:
10362 if (strcasecmp (arg, "yes") == 0)
10363 generate_relax_relocations = 1;
10364 else if (strcasecmp (arg, "no") == 0)
10365 generate_relax_relocations = 0;
10366 else
10367 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10368 break;
10369
10370 case OPTION_MAMD64:
10371 intel64 = 0;
10372 break;
10373
10374 case OPTION_MINTEL64:
10375 intel64 = 1;
10376 break;
10377
10378 default:
10379 return 0;
10380 }
10381 return 1;
10382 }
10383
10384 #define MESSAGE_TEMPLATE \
10385 " "
10386
10387 static char *
10388 output_message (FILE *stream, char *p, char *message, char *start,
10389 int *left_p, const char *name, int len)
10390 {
10391 int size = sizeof (MESSAGE_TEMPLATE);
10392 int left = *left_p;
10393
10394 /* Reserve 2 spaces for ", " or ",\0" */
10395 left -= len + 2;
10396
10397 /* Check if there is any room. */
10398 if (left >= 0)
10399 {
10400 if (p != start)
10401 {
10402 *p++ = ',';
10403 *p++ = ' ';
10404 }
10405 p = mempcpy (p, name, len);
10406 }
10407 else
10408 {
10409 /* Output the current message now and start a new one. */
10410 *p++ = ',';
10411 *p = '\0';
10412 fprintf (stream, "%s\n", message);
10413 p = start;
10414 left = size - (start - message) - len - 2;
10415
10416 gas_assert (left >= 0);
10417
10418 p = mempcpy (p, name, len);
10419 }
10420
10421 *left_p = left;
10422 return p;
10423 }
10424
10425 static void
10426 show_arch (FILE *stream, int ext, int check)
10427 {
10428 static char message[] = MESSAGE_TEMPLATE;
10429 char *start = message + 27;
10430 char *p;
10431 int size = sizeof (MESSAGE_TEMPLATE);
10432 int left;
10433 const char *name;
10434 int len;
10435 unsigned int j;
10436
10437 p = start;
10438 left = size - (start - message);
10439 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10440 {
10441 /* Should it be skipped? */
10442 if (cpu_arch [j].skip)
10443 continue;
10444
10445 name = cpu_arch [j].name;
10446 len = cpu_arch [j].len;
10447 if (*name == '.')
10448 {
10449 /* It is an extension. Skip if we aren't asked to show it. */
10450 if (ext)
10451 {
10452 name++;
10453 len--;
10454 }
10455 else
10456 continue;
10457 }
10458 else if (ext)
10459 {
10460 /* It is an processor. Skip if we show only extension. */
10461 continue;
10462 }
10463 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10464 {
10465 /* It is an impossible processor - skip. */
10466 continue;
10467 }
10468
10469 p = output_message (stream, p, message, start, &left, name, len);
10470 }
10471
10472 /* Display disabled extensions. */
10473 if (ext)
10474 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10475 {
10476 name = cpu_noarch [j].name;
10477 len = cpu_noarch [j].len;
10478 p = output_message (stream, p, message, start, &left, name,
10479 len);
10480 }
10481
10482 *p = '\0';
10483 fprintf (stream, "%s\n", message);
10484 }
10485
10486 void
10487 md_show_usage (FILE *stream)
10488 {
10489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10490 fprintf (stream, _("\
10491 -Q ignored\n\
10492 -V print assembler version number\n\
10493 -k ignored\n"));
10494 #endif
10495 fprintf (stream, _("\
10496 -n Do not optimize code alignment\n\
10497 -q quieten some warnings\n"));
10498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10499 fprintf (stream, _("\
10500 -s ignored\n"));
10501 #endif
10502 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10503 || defined (TE_PE) || defined (TE_PEP))
10504 fprintf (stream, _("\
10505 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10506 #endif
10507 #ifdef SVR4_COMMENT_CHARS
10508 fprintf (stream, _("\
10509 --divide do not treat `/' as a comment character\n"));
10510 #else
10511 fprintf (stream, _("\
10512 --divide ignored\n"));
10513 #endif
10514 fprintf (stream, _("\
10515 -march=CPU[,+EXTENSION...]\n\
10516 generate code for CPU and EXTENSION, CPU is one of:\n"));
10517 show_arch (stream, 0, 1);
10518 fprintf (stream, _("\
10519 EXTENSION is combination of:\n"));
10520 show_arch (stream, 1, 0);
10521 fprintf (stream, _("\
10522 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10523 show_arch (stream, 0, 0);
10524 fprintf (stream, _("\
10525 -msse2avx encode SSE instructions with VEX prefix\n"));
10526 fprintf (stream, _("\
10527 -msse-check=[none|error|warning]\n\
10528 check SSE instructions\n"));
10529 fprintf (stream, _("\
10530 -moperand-check=[none|error|warning]\n\
10531 check operand combinations for validity\n"));
10532 fprintf (stream, _("\
10533 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10534 length\n"));
10535 fprintf (stream, _("\
10536 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10537 length\n"));
10538 fprintf (stream, _("\
10539 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10540 for EVEX.W bit ignored instructions\n"));
10541 fprintf (stream, _("\
10542 -mevexrcig=[rne|rd|ru|rz]\n\
10543 encode EVEX instructions with specific EVEX.RC value\n\
10544 for SAE-only ignored instructions\n"));
10545 fprintf (stream, _("\
10546 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10547 fprintf (stream, _("\
10548 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10549 fprintf (stream, _("\
10550 -mindex-reg support pseudo index registers\n"));
10551 fprintf (stream, _("\
10552 -mnaked-reg don't require `%%' prefix for registers\n"));
10553 fprintf (stream, _("\
10554 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10555 fprintf (stream, _("\
10556 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10557 fprintf (stream, _("\
10558 -mshared disable branch optimization for shared code\n"));
10559 # if defined (TE_PE) || defined (TE_PEP)
10560 fprintf (stream, _("\
10561 -mbig-obj generate big object files\n"));
10562 #endif
10563 fprintf (stream, _("\
10564 -momit-lock-prefix=[no|yes]\n\
10565 strip all lock prefixes\n"));
10566 fprintf (stream, _("\
10567 -mfence-as-lock-add=[no|yes]\n\
10568 encode lfence, mfence and sfence as\n\
10569 lock addl $0x0, (%%{re}sp)\n"));
10570 fprintf (stream, _("\
10571 -mrelax-relocations=[no|yes]\n\
10572 generate relax relocations\n"));
10573 fprintf (stream, _("\
10574 -mamd64 accept only AMD64 ISA\n"));
10575 fprintf (stream, _("\
10576 -mintel64 accept only Intel64 ISA\n"));
10577 }
10578
10579 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10580 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10581 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10582
10583 /* Pick the target format to use. */
10584
10585 const char *
10586 i386_target_format (void)
10587 {
10588 if (!strncmp (default_arch, "x86_64", 6))
10589 {
10590 update_code_flag (CODE_64BIT, 1);
10591 if (default_arch[6] == '\0')
10592 x86_elf_abi = X86_64_ABI;
10593 else
10594 x86_elf_abi = X86_64_X32_ABI;
10595 }
10596 else if (!strcmp (default_arch, "i386"))
10597 update_code_flag (CODE_32BIT, 1);
10598 else if (!strcmp (default_arch, "iamcu"))
10599 {
10600 update_code_flag (CODE_32BIT, 1);
10601 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10602 {
10603 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10604 cpu_arch_name = "iamcu";
10605 cpu_sub_arch_name = NULL;
10606 cpu_arch_flags = iamcu_flags;
10607 cpu_arch_isa = PROCESSOR_IAMCU;
10608 cpu_arch_isa_flags = iamcu_flags;
10609 if (!cpu_arch_tune_set)
10610 {
10611 cpu_arch_tune = cpu_arch_isa;
10612 cpu_arch_tune_flags = cpu_arch_isa_flags;
10613 }
10614 }
10615 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10616 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10617 cpu_arch_name);
10618 }
10619 else
10620 as_fatal (_("unknown architecture"));
10621
10622 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10623 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10624 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10625 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10626
10627 switch (OUTPUT_FLAVOR)
10628 {
10629 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10630 case bfd_target_aout_flavour:
10631 return AOUT_TARGET_FORMAT;
10632 #endif
10633 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10634 # if defined (TE_PE) || defined (TE_PEP)
10635 case bfd_target_coff_flavour:
10636 if (flag_code == CODE_64BIT)
10637 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10638 else
10639 return "pe-i386";
10640 # elif defined (TE_GO32)
10641 case bfd_target_coff_flavour:
10642 return "coff-go32";
10643 # else
10644 case bfd_target_coff_flavour:
10645 return "coff-i386";
10646 # endif
10647 #endif
10648 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10649 case bfd_target_elf_flavour:
10650 {
10651 const char *format;
10652
10653 switch (x86_elf_abi)
10654 {
10655 default:
10656 format = ELF_TARGET_FORMAT;
10657 break;
10658 case X86_64_ABI:
10659 use_rela_relocations = 1;
10660 object_64bit = 1;
10661 format = ELF_TARGET_FORMAT64;
10662 break;
10663 case X86_64_X32_ABI:
10664 use_rela_relocations = 1;
10665 object_64bit = 1;
10666 disallow_64bit_reloc = 1;
10667 format = ELF_TARGET_FORMAT32;
10668 break;
10669 }
10670 if (cpu_arch_isa == PROCESSOR_L1OM)
10671 {
10672 if (x86_elf_abi != X86_64_ABI)
10673 as_fatal (_("Intel L1OM is 64bit only"));
10674 return ELF_TARGET_L1OM_FORMAT;
10675 }
10676 else if (cpu_arch_isa == PROCESSOR_K1OM)
10677 {
10678 if (x86_elf_abi != X86_64_ABI)
10679 as_fatal (_("Intel K1OM is 64bit only"));
10680 return ELF_TARGET_K1OM_FORMAT;
10681 }
10682 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10683 {
10684 if (x86_elf_abi != I386_ABI)
10685 as_fatal (_("Intel MCU is 32bit only"));
10686 return ELF_TARGET_IAMCU_FORMAT;
10687 }
10688 else
10689 return format;
10690 }
10691 #endif
10692 #if defined (OBJ_MACH_O)
10693 case bfd_target_mach_o_flavour:
10694 if (flag_code == CODE_64BIT)
10695 {
10696 use_rela_relocations = 1;
10697 object_64bit = 1;
10698 return "mach-o-x86-64";
10699 }
10700 else
10701 return "mach-o-i386";
10702 #endif
10703 default:
10704 abort ();
10705 return NULL;
10706 }
10707 }
10708
10709 #endif /* OBJ_MAYBE_ more than one */
10710 \f
10711 symbolS *
10712 md_undefined_symbol (char *name)
10713 {
10714 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10715 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10716 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10717 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10718 {
10719 if (!GOT_symbol)
10720 {
10721 if (symbol_find (name))
10722 as_bad (_("GOT already in symbol table"));
10723 GOT_symbol = symbol_new (name, undefined_section,
10724 (valueT) 0, &zero_address_frag);
10725 };
10726 return GOT_symbol;
10727 }
10728 return 0;
10729 }
10730
10731 /* Round up a section size to the appropriate boundary. */
10732
10733 valueT
10734 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10735 {
10736 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10737 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10738 {
10739 /* For a.out, force the section size to be aligned. If we don't do
10740 this, BFD will align it for us, but it will not write out the
10741 final bytes of the section. This may be a bug in BFD, but it is
10742 easier to fix it here since that is how the other a.out targets
10743 work. */
10744 int align;
10745
10746 align = bfd_get_section_alignment (stdoutput, segment);
10747 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10748 }
10749 #endif
10750
10751 return size;
10752 }
10753
10754 /* On the i386, PC-relative offsets are relative to the start of the
10755 next instruction. That is, the address of the offset, plus its
10756 size, since the offset is always the last part of the insn. */
10757
10758 long
10759 md_pcrel_from (fixS *fixP)
10760 {
10761 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10762 }
10763
10764 #ifndef I386COFF
10765
10766 static void
10767 s_bss (int ignore ATTRIBUTE_UNUSED)
10768 {
10769 int temp;
10770
10771 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10772 if (IS_ELF)
10773 obj_elf_section_change_hook ();
10774 #endif
10775 temp = get_absolute_expression ();
10776 subseg_set (bss_section, (subsegT) temp);
10777 demand_empty_rest_of_line ();
10778 }
10779
10780 #endif
10781
10782 void
10783 i386_validate_fix (fixS *fixp)
10784 {
10785 if (fixp->fx_subsy)
10786 {
10787 if (fixp->fx_subsy == GOT_symbol)
10788 {
10789 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10790 {
10791 if (!object_64bit)
10792 abort ();
10793 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10794 if (fixp->fx_tcbit2)
10795 fixp->fx_r_type = (fixp->fx_tcbit
10796 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10797 : BFD_RELOC_X86_64_GOTPCRELX);
10798 else
10799 #endif
10800 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10801 }
10802 else
10803 {
10804 if (!object_64bit)
10805 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10806 else
10807 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10808 }
10809 fixp->fx_subsy = 0;
10810 }
10811 }
10812 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10813 else if (!object_64bit)
10814 {
10815 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10816 && fixp->fx_tcbit2)
10817 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10818 }
10819 #endif
10820 }
10821
10822 arelent *
10823 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10824 {
10825 arelent *rel;
10826 bfd_reloc_code_real_type code;
10827
10828 switch (fixp->fx_r_type)
10829 {
10830 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10831 case BFD_RELOC_SIZE32:
10832 case BFD_RELOC_SIZE64:
10833 if (S_IS_DEFINED (fixp->fx_addsy)
10834 && !S_IS_EXTERNAL (fixp->fx_addsy))
10835 {
10836 /* Resolve size relocation against local symbol to size of
10837 the symbol plus addend. */
10838 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10839 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10840 && !fits_in_unsigned_long (value))
10841 as_bad_where (fixp->fx_file, fixp->fx_line,
10842 _("symbol size computation overflow"));
10843 fixp->fx_addsy = NULL;
10844 fixp->fx_subsy = NULL;
10845 md_apply_fix (fixp, (valueT *) &value, NULL);
10846 return NULL;
10847 }
10848 #endif
10849 /* Fall through. */
10850
10851 case BFD_RELOC_X86_64_PLT32:
10852 case BFD_RELOC_X86_64_GOT32:
10853 case BFD_RELOC_X86_64_GOTPCREL:
10854 case BFD_RELOC_X86_64_GOTPCRELX:
10855 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10856 case BFD_RELOC_386_PLT32:
10857 case BFD_RELOC_386_GOT32:
10858 case BFD_RELOC_386_GOT32X:
10859 case BFD_RELOC_386_GOTOFF:
10860 case BFD_RELOC_386_GOTPC:
10861 case BFD_RELOC_386_TLS_GD:
10862 case BFD_RELOC_386_TLS_LDM:
10863 case BFD_RELOC_386_TLS_LDO_32:
10864 case BFD_RELOC_386_TLS_IE_32:
10865 case BFD_RELOC_386_TLS_IE:
10866 case BFD_RELOC_386_TLS_GOTIE:
10867 case BFD_RELOC_386_TLS_LE_32:
10868 case BFD_RELOC_386_TLS_LE:
10869 case BFD_RELOC_386_TLS_GOTDESC:
10870 case BFD_RELOC_386_TLS_DESC_CALL:
10871 case BFD_RELOC_X86_64_TLSGD:
10872 case BFD_RELOC_X86_64_TLSLD:
10873 case BFD_RELOC_X86_64_DTPOFF32:
10874 case BFD_RELOC_X86_64_DTPOFF64:
10875 case BFD_RELOC_X86_64_GOTTPOFF:
10876 case BFD_RELOC_X86_64_TPOFF32:
10877 case BFD_RELOC_X86_64_TPOFF64:
10878 case BFD_RELOC_X86_64_GOTOFF64:
10879 case BFD_RELOC_X86_64_GOTPC32:
10880 case BFD_RELOC_X86_64_GOT64:
10881 case BFD_RELOC_X86_64_GOTPCREL64:
10882 case BFD_RELOC_X86_64_GOTPC64:
10883 case BFD_RELOC_X86_64_GOTPLT64:
10884 case BFD_RELOC_X86_64_PLTOFF64:
10885 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10886 case BFD_RELOC_X86_64_TLSDESC_CALL:
10887 case BFD_RELOC_RVA:
10888 case BFD_RELOC_VTABLE_ENTRY:
10889 case BFD_RELOC_VTABLE_INHERIT:
10890 #ifdef TE_PE
10891 case BFD_RELOC_32_SECREL:
10892 #endif
10893 code = fixp->fx_r_type;
10894 break;
10895 case BFD_RELOC_X86_64_32S:
10896 if (!fixp->fx_pcrel)
10897 {
10898 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10899 code = fixp->fx_r_type;
10900 break;
10901 }
10902 /* Fall through. */
10903 default:
10904 if (fixp->fx_pcrel)
10905 {
10906 switch (fixp->fx_size)
10907 {
10908 default:
10909 as_bad_where (fixp->fx_file, fixp->fx_line,
10910 _("can not do %d byte pc-relative relocation"),
10911 fixp->fx_size);
10912 code = BFD_RELOC_32_PCREL;
10913 break;
10914 case 1: code = BFD_RELOC_8_PCREL; break;
10915 case 2: code = BFD_RELOC_16_PCREL; break;
10916 case 4: code = BFD_RELOC_32_PCREL; break;
10917 #ifdef BFD64
10918 case 8: code = BFD_RELOC_64_PCREL; break;
10919 #endif
10920 }
10921 }
10922 else
10923 {
10924 switch (fixp->fx_size)
10925 {
10926 default:
10927 as_bad_where (fixp->fx_file, fixp->fx_line,
10928 _("can not do %d byte relocation"),
10929 fixp->fx_size);
10930 code = BFD_RELOC_32;
10931 break;
10932 case 1: code = BFD_RELOC_8; break;
10933 case 2: code = BFD_RELOC_16; break;
10934 case 4: code = BFD_RELOC_32; break;
10935 #ifdef BFD64
10936 case 8: code = BFD_RELOC_64; break;
10937 #endif
10938 }
10939 }
10940 break;
10941 }
10942
10943 if ((code == BFD_RELOC_32
10944 || code == BFD_RELOC_32_PCREL
10945 || code == BFD_RELOC_X86_64_32S)
10946 && GOT_symbol
10947 && fixp->fx_addsy == GOT_symbol)
10948 {
10949 if (!object_64bit)
10950 code = BFD_RELOC_386_GOTPC;
10951 else
10952 code = BFD_RELOC_X86_64_GOTPC32;
10953 }
10954 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10955 && GOT_symbol
10956 && fixp->fx_addsy == GOT_symbol)
10957 {
10958 code = BFD_RELOC_X86_64_GOTPC64;
10959 }
10960
10961 rel = XNEW (arelent);
10962 rel->sym_ptr_ptr = XNEW (asymbol *);
10963 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10964
10965 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10966
10967 if (!use_rela_relocations)
10968 {
10969 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10970 vtable entry to be used in the relocation's section offset. */
10971 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10972 rel->address = fixp->fx_offset;
10973 #if defined (OBJ_COFF) && defined (TE_PE)
10974 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10975 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10976 else
10977 #endif
10978 rel->addend = 0;
10979 }
10980 /* Use the rela in 64bit mode. */
10981 else
10982 {
10983 if (disallow_64bit_reloc)
10984 switch (code)
10985 {
10986 case BFD_RELOC_X86_64_DTPOFF64:
10987 case BFD_RELOC_X86_64_TPOFF64:
10988 case BFD_RELOC_64_PCREL:
10989 case BFD_RELOC_X86_64_GOTOFF64:
10990 case BFD_RELOC_X86_64_GOT64:
10991 case BFD_RELOC_X86_64_GOTPCREL64:
10992 case BFD_RELOC_X86_64_GOTPC64:
10993 case BFD_RELOC_X86_64_GOTPLT64:
10994 case BFD_RELOC_X86_64_PLTOFF64:
10995 as_bad_where (fixp->fx_file, fixp->fx_line,
10996 _("cannot represent relocation type %s in x32 mode"),
10997 bfd_get_reloc_code_name (code));
10998 break;
10999 default:
11000 break;
11001 }
11002
11003 if (!fixp->fx_pcrel)
11004 rel->addend = fixp->fx_offset;
11005 else
11006 switch (code)
11007 {
11008 case BFD_RELOC_X86_64_PLT32:
11009 case BFD_RELOC_X86_64_GOT32:
11010 case BFD_RELOC_X86_64_GOTPCREL:
11011 case BFD_RELOC_X86_64_GOTPCRELX:
11012 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11013 case BFD_RELOC_X86_64_TLSGD:
11014 case BFD_RELOC_X86_64_TLSLD:
11015 case BFD_RELOC_X86_64_GOTTPOFF:
11016 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11017 case BFD_RELOC_X86_64_TLSDESC_CALL:
11018 rel->addend = fixp->fx_offset - fixp->fx_size;
11019 break;
11020 default:
11021 rel->addend = (section->vma
11022 - fixp->fx_size
11023 + fixp->fx_addnumber
11024 + md_pcrel_from (fixp));
11025 break;
11026 }
11027 }
11028
11029 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11030 if (rel->howto == NULL)
11031 {
11032 as_bad_where (fixp->fx_file, fixp->fx_line,
11033 _("cannot represent relocation type %s"),
11034 bfd_get_reloc_code_name (code));
11035 /* Set howto to a garbage value so that we can keep going. */
11036 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11037 gas_assert (rel->howto != NULL);
11038 }
11039
11040 return rel;
11041 }
11042
11043 #include "tc-i386-intel.c"
11044
11045 void
11046 tc_x86_parse_to_dw2regnum (expressionS *exp)
11047 {
11048 int saved_naked_reg;
11049 char saved_register_dot;
11050
11051 saved_naked_reg = allow_naked_reg;
11052 allow_naked_reg = 1;
11053 saved_register_dot = register_chars['.'];
11054 register_chars['.'] = '.';
11055 allow_pseudo_reg = 1;
11056 expression_and_evaluate (exp);
11057 allow_pseudo_reg = 0;
11058 register_chars['.'] = saved_register_dot;
11059 allow_naked_reg = saved_naked_reg;
11060
11061 if (exp->X_op == O_register && exp->X_add_number >= 0)
11062 {
11063 if ((addressT) exp->X_add_number < i386_regtab_size)
11064 {
11065 exp->X_op = O_constant;
11066 exp->X_add_number = i386_regtab[exp->X_add_number]
11067 .dw2_regnum[flag_code >> 1];
11068 }
11069 else
11070 exp->X_op = O_illegal;
11071 }
11072 }
11073
11074 void
11075 tc_x86_frame_initial_instructions (void)
11076 {
11077 static unsigned int sp_regno[2];
11078
11079 if (!sp_regno[flag_code >> 1])
11080 {
11081 char *saved_input = input_line_pointer;
11082 char sp[][4] = {"esp", "rsp"};
11083 expressionS exp;
11084
11085 input_line_pointer = sp[flag_code >> 1];
11086 tc_x86_parse_to_dw2regnum (&exp);
11087 gas_assert (exp.X_op == O_constant);
11088 sp_regno[flag_code >> 1] = exp.X_add_number;
11089 input_line_pointer = saved_input;
11090 }
11091
11092 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11093 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11094 }
11095
11096 int
11097 x86_dwarf2_addr_size (void)
11098 {
11099 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11100 if (x86_elf_abi == X86_64_X32_ABI)
11101 return 4;
11102 #endif
11103 return bfd_arch_bits_per_address (stdoutput) / 8;
11104 }
11105
11106 int
11107 i386_elf_section_type (const char *str, size_t len)
11108 {
11109 if (flag_code == CODE_64BIT
11110 && len == sizeof ("unwind") - 1
11111 && strncmp (str, "unwind", 6) == 0)
11112 return SHT_X86_64_UNWIND;
11113
11114 return -1;
11115 }
11116
11117 #ifdef TE_SOLARIS
11118 void
11119 i386_solaris_fix_up_eh_frame (segT sec)
11120 {
11121 if (flag_code == CODE_64BIT)
11122 elf_section_type (sec) = SHT_X86_64_UNWIND;
11123 }
11124 #endif
11125
11126 #ifdef TE_PE
11127 void
11128 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11129 {
11130 expressionS exp;
11131
11132 exp.X_op = O_secrel;
11133 exp.X_add_symbol = symbol;
11134 exp.X_add_number = 0;
11135 emit_expr (&exp, size);
11136 }
11137 #endif
11138
11139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11140 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11141
11142 bfd_vma
11143 x86_64_section_letter (int letter, const char **ptr_msg)
11144 {
11145 if (flag_code == CODE_64BIT)
11146 {
11147 if (letter == 'l')
11148 return SHF_X86_64_LARGE;
11149
11150 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11151 }
11152 else
11153 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11154 return -1;
11155 }
11156
11157 bfd_vma
11158 x86_64_section_word (char *str, size_t len)
11159 {
11160 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11161 return SHF_X86_64_LARGE;
11162
11163 return -1;
11164 }
11165
11166 static void
11167 handle_large_common (int small ATTRIBUTE_UNUSED)
11168 {
11169 if (flag_code != CODE_64BIT)
11170 {
11171 s_comm_internal (0, elf_common_parse);
11172 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11173 }
11174 else
11175 {
11176 static segT lbss_section;
11177 asection *saved_com_section_ptr = elf_com_section_ptr;
11178 asection *saved_bss_section = bss_section;
11179
11180 if (lbss_section == NULL)
11181 {
11182 flagword applicable;
11183 segT seg = now_seg;
11184 subsegT subseg = now_subseg;
11185
11186 /* The .lbss section is for local .largecomm symbols. */
11187 lbss_section = subseg_new (".lbss", 0);
11188 applicable = bfd_applicable_section_flags (stdoutput);
11189 bfd_set_section_flags (stdoutput, lbss_section,
11190 applicable & SEC_ALLOC);
11191 seg_info (lbss_section)->bss = 1;
11192
11193 subseg_set (seg, subseg);
11194 }
11195
11196 elf_com_section_ptr = &_bfd_elf_large_com_section;
11197 bss_section = lbss_section;
11198
11199 s_comm_internal (0, elf_common_parse);
11200
11201 elf_com_section_ptr = saved_com_section_ptr;
11202 bss_section = saved_bss_section;
11203 }
11204 }
11205 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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