1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Prefer load or store in encoding. */
360 dir_encoding_default
= 0,
365 /* Prefer 8bit or 32bit displacement in encoding. */
368 disp_encoding_default
= 0,
373 /* How to encode vector instructions. */
376 vex_encoding_default
= 0,
383 const char *rep_prefix
;
386 const char *hle_prefix
;
388 /* Have BND prefix. */
389 const char *bnd_prefix
;
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix
;
395 enum i386_error error
;
398 typedef struct _i386_insn i386_insn
;
400 /* Link RC type with corresponding string, that'll be looked for in
409 static const struct RC_name RC_NamesTable
[] =
411 { rne
, STRING_COMMA_LEN ("rn-sae") },
412 { rd
, STRING_COMMA_LEN ("rd-sae") },
413 { ru
, STRING_COMMA_LEN ("ru-sae") },
414 { rz
, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly
, STRING_COMMA_LEN ("sae") },
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars
[] = "*%-([{}"
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if support old (<= 2.8.1) versions of gcc. */
564 static int old_gcc
= OLDGCC_COMPAT
;
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg
= 0;
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg
= 0;
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
575 static int add_bnd_prefix
= 0;
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg
= 0;
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix
= 0;
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence
= 0;
588 /* 1 if the assembler should generate relax relocations. */
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
593 static enum check_kind
599 sse_check
, operand_check
= check_warning
;
601 /* Register prefix used for error message. */
602 static const char *register_prefix
= "%";
604 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607 static char stackop_size
= '\0';
609 /* Non-zero to optimize code alignment. */
610 int optimize_align_code
= 1;
612 /* Non-zero to quieten some warnings. */
613 static int quiet_warnings
= 0;
616 static const char *cpu_arch_name
= NULL
;
617 static char *cpu_sub_arch_name
= NULL
;
619 /* CPU feature flags. */
620 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
622 /* If we have selected a cpu we are generating instructions for. */
623 static int cpu_arch_tune_set
= 0;
625 /* Cpu we are generating instructions for. */
626 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
628 /* CPU feature flags of cpu we are generating instructions for. */
629 static i386_cpu_flags cpu_arch_tune_flags
;
631 /* CPU instruction set architecture used. */
632 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
634 /* CPU feature flags of instruction set architecture used. */
635 i386_cpu_flags cpu_arch_isa_flags
;
637 /* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639 static unsigned int no_cond_jump_promotion
= 0;
641 /* Encode SSE instructions with VEX prefix. */
642 static unsigned int sse2avx
;
644 /* Encode scalar AVX instructions with specific vector length. */
651 /* Encode scalar EVEX LIG instructions with specific vector length. */
659 /* Encode EVEX WIG instructions with specific evex.w. */
666 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
667 static enum rc_type evexrcig
= rne
;
669 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
670 static symbolS
*GOT_symbol
;
672 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
673 unsigned int x86_dwarf2_return_column
;
675 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676 int x86_cie_data_alignment
;
678 /* Interface to relax_segment.
679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
684 #define UNCOND_JUMP 0
686 #define COND_JUMP86 2
691 #define SMALL16 (SMALL | CODE16)
693 #define BIG16 (BIG | CODE16)
697 #define INLINE __inline__
703 #define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705 #define TYPE_FROM_RELAX_STATE(s) \
707 #define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
710 /* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
718 const relax_typeS md_relax_table
[] =
721 1) most positive reach of this state,
722 2) most negative reach of this state,
723 3) how many bytes this mode will have in the variable part of the frag
724 4) which index into the table to try if we can't fit into this one. */
726 /* UNCOND_JUMP states. */
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
742 /* word conditionals add 3 bytes to frag:
743 1 extra opcode byte, 2 displacement bytes. */
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
757 static const arch_entry cpu_arch
[] =
759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
762 CPU_GENERIC32_FLAGS
, 0 },
763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
764 CPU_GENERIC64_FLAGS
, 0 },
765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
782 CPU_PENTIUMPRO_FLAGS
, 0 },
783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
792 CPU_NOCONA_FLAGS
, 0 },
793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
798 CPU_CORE2_FLAGS
, 1 },
799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
800 CPU_CORE2_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
802 CPU_COREI7_FLAGS
, 0 },
803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
808 CPU_IAMCU_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
814 CPU_ATHLON_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
822 CPU_AMDFAM10_FLAGS
, 0 },
823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
824 CPU_BDVER1_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
826 CPU_BDVER2_FLAGS
, 0 },
827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
828 CPU_BDVER3_FLAGS
, 0 },
829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
830 CPU_BDVER4_FLAGS
, 0 },
831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
832 CPU_ZNVER1_FLAGS
, 0 },
833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
834 CPU_BTVER1_FLAGS
, 0 },
835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
836 CPU_BTVER2_FLAGS
, 0 },
837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
854 CPU_SSSE3_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
856 CPU_SSE4_1_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
858 CPU_SSE4_2_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
860 CPU_SSE4_2_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
866 CPU_AVX512F_FLAGS
, 0 },
867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
868 CPU_AVX512CD_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
870 CPU_AVX512ER_FLAGS
, 0 },
871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
872 CPU_AVX512PF_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
874 CPU_AVX512DQ_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
876 CPU_AVX512BW_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
878 CPU_AVX512VL_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
882 CPU_VMFUNC_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
886 CPU_XSAVE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
888 CPU_XSAVEOPT_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
890 CPU_XSAVEC_FLAGS
, 0 },
891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
892 CPU_XSAVES_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
896 CPU_PCLMUL_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
898 CPU_PCLMUL_FLAGS
, 1 },
899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
900 CPU_FSGSBASE_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
902 CPU_RDRND_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
916 CPU_MOVBE_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
922 CPU_LZCNT_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
928 CPU_INVPCID_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
930 CPU_CLFLUSH_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
934 CPU_SYSCALL_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
936 CPU_RDTSCP_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
938 CPU_3DNOW_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
940 CPU_3DNOWA_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
942 CPU_PADLOCK_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
948 CPU_SSE4A_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
958 CPU_RDSEED_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
960 CPU_PRFCHW_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
968 CPU_CLFLUSHOPT_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
970 CPU_PREFETCHWT1_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
976 CPU_AVX512IFMA_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
978 CPU_AVX512VBMI_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
980 CPU_AVX512_4FMAPS_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
982 CPU_AVX512_4VNNIW_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
984 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
986 CPU_AVX512_VBMI2_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
988 CPU_AVX512_VNNI_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
990 CPU_AVX512_BITALG_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
992 CPU_CLZERO_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
994 CPU_MWAITX_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
996 CPU_OSPKE_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
998 CPU_RDPID_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1000 CPU_PTWRITE_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
1003 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1004 CPU_GFNI_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1006 CPU_VAES_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1008 CPU_VPCLMULQDQ_FLAGS
, 0 },
1011 static const noarch_entry cpu_noarch
[] =
1013 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1014 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1015 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1016 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1017 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1018 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1019 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1020 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1021 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1022 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1023 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1024 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1027 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1028 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1029 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1030 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1031 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1032 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1033 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1034 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1035 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1036 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1037 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1038 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1039 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1040 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1041 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1045 /* Like s_lcomm_internal in gas/read.c but the alignment string
1046 is allowed to be optional. */
1049 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1056 && *input_line_pointer
== ',')
1058 align
= parse_align (needs_align
- 1);
1060 if (align
== (addressT
) -1)
1075 bss_alloc (symbolP
, size
, align
);
1080 pe_lcomm (int needs_align
)
1082 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1086 const pseudo_typeS md_pseudo_table
[] =
1088 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1089 {"align", s_align_bytes
, 0},
1091 {"align", s_align_ptwo
, 0},
1093 {"arch", set_cpu_arch
, 0},
1097 {"lcomm", pe_lcomm
, 1},
1099 {"ffloat", float_cons
, 'f'},
1100 {"dfloat", float_cons
, 'd'},
1101 {"tfloat", float_cons
, 'x'},
1103 {"slong", signed_cons
, 4},
1104 {"noopt", s_ignore
, 0},
1105 {"optim", s_ignore
, 0},
1106 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1107 {"code16", set_code_flag
, CODE_16BIT
},
1108 {"code32", set_code_flag
, CODE_32BIT
},
1109 {"code64", set_code_flag
, CODE_64BIT
},
1110 {"intel_syntax", set_intel_syntax
, 1},
1111 {"att_syntax", set_intel_syntax
, 0},
1112 {"intel_mnemonic", set_intel_mnemonic
, 1},
1113 {"att_mnemonic", set_intel_mnemonic
, 0},
1114 {"allow_index_reg", set_allow_index_reg
, 1},
1115 {"disallow_index_reg", set_allow_index_reg
, 0},
1116 {"sse_check", set_check
, 0},
1117 {"operand_check", set_check
, 1},
1118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1119 {"largecomm", handle_large_common
, 0},
1121 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1122 {"loc", dwarf2_directive_loc
, 0},
1123 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1126 {"secrel32", pe_directive_secrel
, 0},
1131 /* For interface with expression (). */
1132 extern char *input_line_pointer
;
1134 /* Hash table for instruction mnemonic lookup. */
1135 static struct hash_control
*op_hash
;
1137 /* Hash table for register lookup. */
1138 static struct hash_control
*reg_hash
;
1141 i386_align_code (fragS
*fragP
, int count
)
1143 /* Various efficient no-op patterns for aligning code labels.
1144 Note: Don't try to assemble the instructions in the comments.
1145 0L and 0w are not legal. */
1146 static const unsigned char f32_1
[] =
1148 static const unsigned char f32_2
[] =
1149 {0x66,0x90}; /* xchg %ax,%ax */
1150 static const unsigned char f32_3
[] =
1151 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1152 static const unsigned char f32_4
[] =
1153 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1154 static const unsigned char f32_5
[] =
1156 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1157 static const unsigned char f32_6
[] =
1158 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1159 static const unsigned char f32_7
[] =
1160 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1161 static const unsigned char f32_8
[] =
1163 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1164 static const unsigned char f32_9
[] =
1165 {0x89,0xf6, /* movl %esi,%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1167 static const unsigned char f32_10
[] =
1168 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1169 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1170 static const unsigned char f32_11
[] =
1171 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1172 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1173 static const unsigned char f32_12
[] =
1174 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1175 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1176 static const unsigned char f32_13
[] =
1177 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1178 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1179 static const unsigned char f32_14
[] =
1180 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1181 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1182 static const unsigned char f16_3
[] =
1183 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1184 static const unsigned char f16_4
[] =
1185 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1186 static const unsigned char f16_5
[] =
1188 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1189 static const unsigned char f16_6
[] =
1190 {0x89,0xf6, /* mov %si,%si */
1191 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1192 static const unsigned char f16_7
[] =
1193 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1194 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1195 static const unsigned char f16_8
[] =
1196 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1197 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1198 static const unsigned char jump_31
[] =
1199 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1200 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1203 static const unsigned char *const f32_patt
[] = {
1204 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1205 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1207 static const unsigned char *const f16_patt
[] = {
1208 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1210 /* nopl (%[re]ax) */
1211 static const unsigned char alt_3
[] =
1213 /* nopl 0(%[re]ax) */
1214 static const unsigned char alt_4
[] =
1215 {0x0f,0x1f,0x40,0x00};
1216 /* nopl 0(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_5
[] =
1218 {0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopw 0(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_6
[] =
1221 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1222 /* nopl 0L(%[re]ax) */
1223 static const unsigned char alt_7
[] =
1224 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1225 /* nopl 0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_8
[] =
1227 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw 0L(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_9
[] =
1230 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1232 static const unsigned char alt_10
[] =
1233 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1234 static const unsigned char *const alt_patt
[] = {
1235 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1239 /* Only align for at least a positive non-zero boundary. */
1240 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1243 /* We need to decide which NOP sequence to use for 32bit and
1244 64bit. When -mtune= is used:
1246 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1247 PROCESSOR_GENERIC32, f32_patt will be used.
1248 2. For the rest, alt_patt will be used.
1250 When -mtune= isn't used, alt_patt will be used if
1251 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1254 When -march= or .arch is used, we can't use anything beyond
1255 cpu_arch_isa_flags. */
1257 if (flag_code
== CODE_16BIT
)
1261 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1263 /* Adjust jump offset. */
1264 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1267 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1268 f16_patt
[count
- 1], count
);
1272 const unsigned char *const *patt
= NULL
;
1274 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1276 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1277 switch (cpu_arch_tune
)
1279 case PROCESSOR_UNKNOWN
:
1280 /* We use cpu_arch_isa_flags to check if we SHOULD
1281 optimize with nops. */
1282 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1287 case PROCESSOR_PENTIUM4
:
1288 case PROCESSOR_NOCONA
:
1289 case PROCESSOR_CORE
:
1290 case PROCESSOR_CORE2
:
1291 case PROCESSOR_COREI7
:
1292 case PROCESSOR_L1OM
:
1293 case PROCESSOR_K1OM
:
1294 case PROCESSOR_GENERIC64
:
1296 case PROCESSOR_ATHLON
:
1298 case PROCESSOR_AMDFAM10
:
1300 case PROCESSOR_ZNVER
:
1304 case PROCESSOR_I386
:
1305 case PROCESSOR_I486
:
1306 case PROCESSOR_PENTIUM
:
1307 case PROCESSOR_PENTIUMPRO
:
1308 case PROCESSOR_IAMCU
:
1309 case PROCESSOR_GENERIC32
:
1316 switch (fragP
->tc_frag_data
.tune
)
1318 case PROCESSOR_UNKNOWN
:
1319 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1320 PROCESSOR_UNKNOWN. */
1324 case PROCESSOR_I386
:
1325 case PROCESSOR_I486
:
1326 case PROCESSOR_PENTIUM
:
1327 case PROCESSOR_IAMCU
:
1329 case PROCESSOR_ATHLON
:
1331 case PROCESSOR_AMDFAM10
:
1333 case PROCESSOR_ZNVER
:
1335 case PROCESSOR_GENERIC32
:
1336 /* We use cpu_arch_isa_flags to check if we CAN optimize
1338 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1343 case PROCESSOR_PENTIUMPRO
:
1344 case PROCESSOR_PENTIUM4
:
1345 case PROCESSOR_NOCONA
:
1346 case PROCESSOR_CORE
:
1347 case PROCESSOR_CORE2
:
1348 case PROCESSOR_COREI7
:
1349 case PROCESSOR_L1OM
:
1350 case PROCESSOR_K1OM
:
1351 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1356 case PROCESSOR_GENERIC64
:
1362 if (patt
== f32_patt
)
1364 /* If the padding is less than 15 bytes, we use the normal
1365 ones. Otherwise, we use a jump instruction and adjust
1369 /* For 64bit, the limit is 3 bytes. */
1370 if (flag_code
== CODE_64BIT
1371 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1376 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1377 patt
[count
- 1], count
);
1380 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1382 /* Adjust jump offset. */
1383 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1388 /* Maximum length of an instruction is 10 byte. If the
1389 padding is greater than 10 bytes and we don't use jump,
1390 we have to break it into smaller pieces. */
1391 int padding
= count
;
1392 while (padding
> 10)
1395 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1400 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1401 patt
[padding
- 1], padding
);
1404 fragP
->fr_var
= count
;
1408 operand_type_all_zero (const union i386_operand_type
*x
)
1410 switch (ARRAY_SIZE(x
->array
))
1421 return !x
->array
[0];
1428 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1430 switch (ARRAY_SIZE(x
->array
))
1448 operand_type_equal (const union i386_operand_type
*x
,
1449 const union i386_operand_type
*y
)
1451 switch (ARRAY_SIZE(x
->array
))
1454 if (x
->array
[2] != y
->array
[2])
1458 if (x
->array
[1] != y
->array
[1])
1462 return x
->array
[0] == y
->array
[0];
1470 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1472 switch (ARRAY_SIZE(x
->array
))
1487 return !x
->array
[0];
1494 cpu_flags_equal (const union i386_cpu_flags
*x
,
1495 const union i386_cpu_flags
*y
)
1497 switch (ARRAY_SIZE(x
->array
))
1500 if (x
->array
[3] != y
->array
[3])
1504 if (x
->array
[2] != y
->array
[2])
1508 if (x
->array
[1] != y
->array
[1])
1512 return x
->array
[0] == y
->array
[0];
1520 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1522 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1523 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1526 static INLINE i386_cpu_flags
1527 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1529 switch (ARRAY_SIZE (x
.array
))
1532 x
.array
[3] &= y
.array
[3];
1535 x
.array
[2] &= y
.array
[2];
1538 x
.array
[1] &= y
.array
[1];
1541 x
.array
[0] &= y
.array
[0];
1549 static INLINE i386_cpu_flags
1550 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1552 switch (ARRAY_SIZE (x
.array
))
1555 x
.array
[3] |= y
.array
[3];
1558 x
.array
[2] |= y
.array
[2];
1561 x
.array
[1] |= y
.array
[1];
1564 x
.array
[0] |= y
.array
[0];
1572 static INLINE i386_cpu_flags
1573 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1575 switch (ARRAY_SIZE (x
.array
))
1578 x
.array
[3] &= ~y
.array
[3];
1581 x
.array
[2] &= ~y
.array
[2];
1584 x
.array
[1] &= ~y
.array
[1];
1587 x
.array
[0] &= ~y
.array
[0];
1595 #define CPU_FLAGS_ARCH_MATCH 0x1
1596 #define CPU_FLAGS_64BIT_MATCH 0x2
1597 #define CPU_FLAGS_AES_MATCH 0x4
1598 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1599 #define CPU_FLAGS_AVX_MATCH 0x10
1601 #define CPU_FLAGS_32BIT_MATCH \
1602 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1603 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1604 #define CPU_FLAGS_PERFECT_MATCH \
1605 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1607 /* Return CPU flags match bits. */
1610 cpu_flags_match (const insn_template
*t
)
1612 i386_cpu_flags x
= t
->cpu_flags
;
1613 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1615 x
.bitfield
.cpu64
= 0;
1616 x
.bitfield
.cpuno64
= 0;
1618 if (cpu_flags_all_zero (&x
))
1620 /* This instruction is available on all archs. */
1621 match
|= CPU_FLAGS_32BIT_MATCH
;
1625 /* This instruction is available only on some archs. */
1626 i386_cpu_flags cpu
= cpu_arch_flags
;
1628 cpu
= cpu_flags_and (x
, cpu
);
1629 if (!cpu_flags_all_zero (&cpu
))
1631 if (x
.bitfield
.cpuavx
)
1633 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1634 if (cpu
.bitfield
.cpuavx
)
1636 /* Check SSE2AVX. */
1637 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1639 match
|= (CPU_FLAGS_ARCH_MATCH
1640 | CPU_FLAGS_AVX_MATCH
);
1642 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1643 match
|= CPU_FLAGS_AES_MATCH
;
1645 if (!x
.bitfield
.cpupclmul
1646 || cpu
.bitfield
.cpupclmul
)
1647 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1651 match
|= CPU_FLAGS_ARCH_MATCH
;
1653 else if (x
.bitfield
.cpuavx512vl
)
1655 /* Match AVX512VL. */
1656 if (cpu
.bitfield
.cpuavx512vl
)
1658 /* Need another match. */
1659 cpu
.bitfield
.cpuavx512vl
= 0;
1660 if (!cpu_flags_all_zero (&cpu
))
1661 match
|= CPU_FLAGS_32BIT_MATCH
;
1663 match
|= CPU_FLAGS_ARCH_MATCH
;
1666 match
|= CPU_FLAGS_ARCH_MATCH
;
1669 match
|= CPU_FLAGS_32BIT_MATCH
;
1675 static INLINE i386_operand_type
1676 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1678 switch (ARRAY_SIZE (x
.array
))
1681 x
.array
[2] &= y
.array
[2];
1684 x
.array
[1] &= y
.array
[1];
1687 x
.array
[0] &= y
.array
[0];
1695 static INLINE i386_operand_type
1696 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1698 switch (ARRAY_SIZE (x
.array
))
1701 x
.array
[2] |= y
.array
[2];
1704 x
.array
[1] |= y
.array
[1];
1707 x
.array
[0] |= y
.array
[0];
1715 static INLINE i386_operand_type
1716 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1718 switch (ARRAY_SIZE (x
.array
))
1721 x
.array
[2] ^= y
.array
[2];
1724 x
.array
[1] ^= y
.array
[1];
1727 x
.array
[0] ^= y
.array
[0];
1735 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1736 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1737 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1738 static const i386_operand_type inoutportreg
1739 = OPERAND_TYPE_INOUTPORTREG
;
1740 static const i386_operand_type reg16_inoutportreg
1741 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1742 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1743 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1744 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1745 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1746 static const i386_operand_type anydisp
1747 = OPERAND_TYPE_ANYDISP
;
1748 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1749 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1750 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1751 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1752 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1753 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1754 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1755 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1756 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1757 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1758 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1759 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1760 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1761 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1772 operand_type_check (i386_operand_type t
, enum operand_type c
)
1777 return (t
.bitfield
.reg8
1780 || t
.bitfield
.reg64
);
1783 return (t
.bitfield
.imm8
1787 || t
.bitfield
.imm32s
1788 || t
.bitfield
.imm64
);
1791 return (t
.bitfield
.disp8
1792 || t
.bitfield
.disp16
1793 || t
.bitfield
.disp32
1794 || t
.bitfield
.disp32s
1795 || t
.bitfield
.disp64
);
1798 return (t
.bitfield
.disp8
1799 || t
.bitfield
.disp16
1800 || t
.bitfield
.disp32
1801 || t
.bitfield
.disp32s
1802 || t
.bitfield
.disp64
1803 || t
.bitfield
.baseindex
);
1812 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1813 operand J for instruction template T. */
1816 match_reg_size (const insn_template
*t
, unsigned int j
)
1818 return !((i
.types
[j
].bitfield
.byte
1819 && !t
->operand_types
[j
].bitfield
.byte
)
1820 || (i
.types
[j
].bitfield
.word
1821 && !t
->operand_types
[j
].bitfield
.word
)
1822 || (i
.types
[j
].bitfield
.dword
1823 && !t
->operand_types
[j
].bitfield
.dword
)
1824 || (i
.types
[j
].bitfield
.qword
1825 && !t
->operand_types
[j
].bitfield
.qword
));
1828 /* Return 1 if there is no conflict in any size on operand J for
1829 instruction template T. */
1832 match_mem_size (const insn_template
*t
, unsigned int j
)
1834 return (match_reg_size (t
, j
)
1835 && !((i
.types
[j
].bitfield
.unspecified
1837 && !t
->operand_types
[j
].bitfield
.unspecified
)
1838 || (i
.types
[j
].bitfield
.fword
1839 && !t
->operand_types
[j
].bitfield
.fword
)
1840 || (i
.types
[j
].bitfield
.tbyte
1841 && !t
->operand_types
[j
].bitfield
.tbyte
)
1842 || (i
.types
[j
].bitfield
.xmmword
1843 && !t
->operand_types
[j
].bitfield
.xmmword
)
1844 || (i
.types
[j
].bitfield
.ymmword
1845 && !t
->operand_types
[j
].bitfield
.ymmword
)
1846 || (i
.types
[j
].bitfield
.zmmword
1847 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1850 /* Return 1 if there is no size conflict on any operands for
1851 instruction template T. */
1854 operand_size_match (const insn_template
*t
)
1859 /* Don't check jump instructions. */
1860 if (t
->opcode_modifier
.jump
1861 || t
->opcode_modifier
.jumpbyte
1862 || t
->opcode_modifier
.jumpdword
1863 || t
->opcode_modifier
.jumpintersegment
)
1866 /* Check memory and accumulator operand size. */
1867 for (j
= 0; j
< i
.operands
; j
++)
1869 if (t
->operand_types
[j
].bitfield
.anysize
)
1872 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1878 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1887 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1890 i
.error
= operand_size_mismatch
;
1894 /* Check reverse. */
1895 gas_assert (i
.operands
== 2);
1898 for (j
= 0; j
< 2; j
++)
1900 if (t
->operand_types
[j
].bitfield
.acc
1901 && !match_reg_size (t
, j
? 0 : 1))
1904 if (i
.types
[j
].bitfield
.mem
1905 && !match_mem_size (t
, j
? 0 : 1))
1913 operand_type_match (i386_operand_type overlap
,
1914 i386_operand_type given
)
1916 i386_operand_type temp
= overlap
;
1918 temp
.bitfield
.jumpabsolute
= 0;
1919 temp
.bitfield
.unspecified
= 0;
1920 temp
.bitfield
.byte
= 0;
1921 temp
.bitfield
.word
= 0;
1922 temp
.bitfield
.dword
= 0;
1923 temp
.bitfield
.fword
= 0;
1924 temp
.bitfield
.qword
= 0;
1925 temp
.bitfield
.tbyte
= 0;
1926 temp
.bitfield
.xmmword
= 0;
1927 temp
.bitfield
.ymmword
= 0;
1928 temp
.bitfield
.zmmword
= 0;
1929 if (operand_type_all_zero (&temp
))
1932 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1933 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1937 i
.error
= operand_type_mismatch
;
1941 /* If given types g0 and g1 are registers they must be of the same type
1942 unless the expected operand type register overlap is null.
1943 Note that Acc in a template matches every size of reg. */
1946 operand_type_register_match (i386_operand_type m0
,
1947 i386_operand_type g0
,
1948 i386_operand_type t0
,
1949 i386_operand_type m1
,
1950 i386_operand_type g1
,
1951 i386_operand_type t1
)
1953 if (!operand_type_check (g0
, reg
))
1956 if (!operand_type_check (g1
, reg
))
1959 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1960 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1961 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1962 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1965 if (m0
.bitfield
.acc
)
1967 t0
.bitfield
.reg8
= 1;
1968 t0
.bitfield
.reg16
= 1;
1969 t0
.bitfield
.reg32
= 1;
1970 t0
.bitfield
.reg64
= 1;
1973 if (m1
.bitfield
.acc
)
1975 t1
.bitfield
.reg8
= 1;
1976 t1
.bitfield
.reg16
= 1;
1977 t1
.bitfield
.reg32
= 1;
1978 t1
.bitfield
.reg64
= 1;
1981 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1982 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1983 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1984 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1987 i
.error
= register_type_mismatch
;
1992 static INLINE
unsigned int
1993 register_number (const reg_entry
*r
)
1995 unsigned int nr
= r
->reg_num
;
1997 if (r
->reg_flags
& RegRex
)
2000 if (r
->reg_flags
& RegVRex
)
2006 static INLINE
unsigned int
2007 mode_from_disp_size (i386_operand_type t
)
2009 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
2011 else if (t
.bitfield
.disp16
2012 || t
.bitfield
.disp32
2013 || t
.bitfield
.disp32s
)
2020 fits_in_signed_byte (addressT num
)
2022 return num
+ 0x80 <= 0xff;
2026 fits_in_unsigned_byte (addressT num
)
2032 fits_in_unsigned_word (addressT num
)
2034 return num
<= 0xffff;
2038 fits_in_signed_word (addressT num
)
2040 return num
+ 0x8000 <= 0xffff;
2044 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2049 return num
+ 0x80000000 <= 0xffffffff;
2051 } /* fits_in_signed_long() */
2054 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2059 return num
<= 0xffffffff;
2061 } /* fits_in_unsigned_long() */
2064 fits_in_vec_disp8 (offsetT num
)
2066 int shift
= i
.memshift
;
2072 mask
= (1 << shift
) - 1;
2074 /* Return 0 if NUM isn't properly aligned. */
2078 /* Check if NUM will fit in 8bit after shift. */
2079 return fits_in_signed_byte (num
>> shift
);
2083 fits_in_imm4 (offsetT num
)
2085 return (num
& 0xf) == num
;
2088 static i386_operand_type
2089 smallest_imm_type (offsetT num
)
2091 i386_operand_type t
;
2093 operand_type_set (&t
, 0);
2094 t
.bitfield
.imm64
= 1;
2096 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2098 /* This code is disabled on the 486 because all the Imm1 forms
2099 in the opcode table are slower on the i486. They're the
2100 versions with the implicitly specified single-position
2101 displacement, which has another syntax if you really want to
2103 t
.bitfield
.imm1
= 1;
2104 t
.bitfield
.imm8
= 1;
2105 t
.bitfield
.imm8s
= 1;
2106 t
.bitfield
.imm16
= 1;
2107 t
.bitfield
.imm32
= 1;
2108 t
.bitfield
.imm32s
= 1;
2110 else if (fits_in_signed_byte (num
))
2112 t
.bitfield
.imm8
= 1;
2113 t
.bitfield
.imm8s
= 1;
2114 t
.bitfield
.imm16
= 1;
2115 t
.bitfield
.imm32
= 1;
2116 t
.bitfield
.imm32s
= 1;
2118 else if (fits_in_unsigned_byte (num
))
2120 t
.bitfield
.imm8
= 1;
2121 t
.bitfield
.imm16
= 1;
2122 t
.bitfield
.imm32
= 1;
2123 t
.bitfield
.imm32s
= 1;
2125 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2127 t
.bitfield
.imm16
= 1;
2128 t
.bitfield
.imm32
= 1;
2129 t
.bitfield
.imm32s
= 1;
2131 else if (fits_in_signed_long (num
))
2133 t
.bitfield
.imm32
= 1;
2134 t
.bitfield
.imm32s
= 1;
2136 else if (fits_in_unsigned_long (num
))
2137 t
.bitfield
.imm32
= 1;
2143 offset_in_range (offsetT val
, int size
)
2149 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2150 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2151 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2153 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2159 /* If BFD64, sign extend val for 32bit address mode. */
2160 if (flag_code
!= CODE_64BIT
2161 || i
.prefix
[ADDR_PREFIX
])
2162 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2163 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2166 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2168 char buf1
[40], buf2
[40];
2170 sprint_value (buf1
, val
);
2171 sprint_value (buf2
, val
& mask
);
2172 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2187 a. PREFIX_EXIST if attempting to add a prefix where one from the
2188 same class already exists.
2189 b. PREFIX_LOCK if lock prefix is added.
2190 c. PREFIX_REP if rep/repne prefix is added.
2191 d. PREFIX_DS if ds prefix is added.
2192 e. PREFIX_OTHER if other prefix is added.
2195 static enum PREFIX_GROUP
2196 add_prefix (unsigned int prefix
)
2198 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2201 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2202 && flag_code
== CODE_64BIT
)
2204 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2205 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2206 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2217 case DS_PREFIX_OPCODE
:
2220 case CS_PREFIX_OPCODE
:
2221 case ES_PREFIX_OPCODE
:
2222 case FS_PREFIX_OPCODE
:
2223 case GS_PREFIX_OPCODE
:
2224 case SS_PREFIX_OPCODE
:
2228 case REPNE_PREFIX_OPCODE
:
2229 case REPE_PREFIX_OPCODE
:
2234 case LOCK_PREFIX_OPCODE
:
2243 case ADDR_PREFIX_OPCODE
:
2247 case DATA_PREFIX_OPCODE
:
2251 if (i
.prefix
[q
] != 0)
2259 i
.prefix
[q
] |= prefix
;
2262 as_bad (_("same type of prefix used twice"));
2268 update_code_flag (int value
, int check
)
2270 PRINTF_LIKE ((*as_error
));
2272 flag_code
= (enum flag_code
) value
;
2273 if (flag_code
== CODE_64BIT
)
2275 cpu_arch_flags
.bitfield
.cpu64
= 1;
2276 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2280 cpu_arch_flags
.bitfield
.cpu64
= 0;
2281 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2283 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2286 as_error
= as_fatal
;
2289 (*as_error
) (_("64bit mode not supported on `%s'."),
2290 cpu_arch_name
? cpu_arch_name
: default_arch
);
2292 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2295 as_error
= as_fatal
;
2298 (*as_error
) (_("32bit mode not supported on `%s'."),
2299 cpu_arch_name
? cpu_arch_name
: default_arch
);
2301 stackop_size
= '\0';
2305 set_code_flag (int value
)
2307 update_code_flag (value
, 0);
2311 set_16bit_gcc_code_flag (int new_code_flag
)
2313 flag_code
= (enum flag_code
) new_code_flag
;
2314 if (flag_code
!= CODE_16BIT
)
2316 cpu_arch_flags
.bitfield
.cpu64
= 0;
2317 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2318 stackop_size
= LONG_MNEM_SUFFIX
;
2322 set_intel_syntax (int syntax_flag
)
2324 /* Find out if register prefixing is specified. */
2325 int ask_naked_reg
= 0;
2328 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2331 int e
= get_symbol_name (&string
);
2333 if (strcmp (string
, "prefix") == 0)
2335 else if (strcmp (string
, "noprefix") == 0)
2338 as_bad (_("bad argument to syntax directive."));
2339 (void) restore_line_pointer (e
);
2341 demand_empty_rest_of_line ();
2343 intel_syntax
= syntax_flag
;
2345 if (ask_naked_reg
== 0)
2346 allow_naked_reg
= (intel_syntax
2347 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2349 allow_naked_reg
= (ask_naked_reg
< 0);
2351 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2353 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2354 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2355 register_prefix
= allow_naked_reg
? "" : "%";
2359 set_intel_mnemonic (int mnemonic_flag
)
2361 intel_mnemonic
= mnemonic_flag
;
2365 set_allow_index_reg (int flag
)
2367 allow_index_reg
= flag
;
2371 set_check (int what
)
2373 enum check_kind
*kind
;
2378 kind
= &operand_check
;
2389 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2392 int e
= get_symbol_name (&string
);
2394 if (strcmp (string
, "none") == 0)
2396 else if (strcmp (string
, "warning") == 0)
2397 *kind
= check_warning
;
2398 else if (strcmp (string
, "error") == 0)
2399 *kind
= check_error
;
2401 as_bad (_("bad argument to %s_check directive."), str
);
2402 (void) restore_line_pointer (e
);
2405 as_bad (_("missing argument for %s_check directive"), str
);
2407 demand_empty_rest_of_line ();
2411 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2412 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2414 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2415 static const char *arch
;
2417 /* Intel LIOM is only supported on ELF. */
2423 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2424 use default_arch. */
2425 arch
= cpu_arch_name
;
2427 arch
= default_arch
;
2430 /* If we are targeting Intel MCU, we must enable it. */
2431 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2432 || new_flag
.bitfield
.cpuiamcu
)
2435 /* If we are targeting Intel L1OM, we must enable it. */
2436 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2437 || new_flag
.bitfield
.cpul1om
)
2440 /* If we are targeting Intel K1OM, we must enable it. */
2441 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2442 || new_flag
.bitfield
.cpuk1om
)
2445 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2450 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2454 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2457 int e
= get_symbol_name (&string
);
2459 i386_cpu_flags flags
;
2461 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2463 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2465 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2469 cpu_arch_name
= cpu_arch
[j
].name
;
2470 cpu_sub_arch_name
= NULL
;
2471 cpu_arch_flags
= cpu_arch
[j
].flags
;
2472 if (flag_code
== CODE_64BIT
)
2474 cpu_arch_flags
.bitfield
.cpu64
= 1;
2475 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2479 cpu_arch_flags
.bitfield
.cpu64
= 0;
2480 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2482 cpu_arch_isa
= cpu_arch
[j
].type
;
2483 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2484 if (!cpu_arch_tune_set
)
2486 cpu_arch_tune
= cpu_arch_isa
;
2487 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2492 flags
= cpu_flags_or (cpu_arch_flags
,
2495 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2497 if (cpu_sub_arch_name
)
2499 char *name
= cpu_sub_arch_name
;
2500 cpu_sub_arch_name
= concat (name
,
2502 (const char *) NULL
);
2506 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2507 cpu_arch_flags
= flags
;
2508 cpu_arch_isa_flags
= flags
;
2510 (void) restore_line_pointer (e
);
2511 demand_empty_rest_of_line ();
2516 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2518 /* Disable an ISA extension. */
2519 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2520 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2522 flags
= cpu_flags_and_not (cpu_arch_flags
,
2523 cpu_noarch
[j
].flags
);
2524 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2526 if (cpu_sub_arch_name
)
2528 char *name
= cpu_sub_arch_name
;
2529 cpu_sub_arch_name
= concat (name
, string
,
2530 (const char *) NULL
);
2534 cpu_sub_arch_name
= xstrdup (string
);
2535 cpu_arch_flags
= flags
;
2536 cpu_arch_isa_flags
= flags
;
2538 (void) restore_line_pointer (e
);
2539 demand_empty_rest_of_line ();
2543 j
= ARRAY_SIZE (cpu_arch
);
2546 if (j
>= ARRAY_SIZE (cpu_arch
))
2547 as_bad (_("no such architecture: `%s'"), string
);
2549 *input_line_pointer
= e
;
2552 as_bad (_("missing cpu architecture"));
2554 no_cond_jump_promotion
= 0;
2555 if (*input_line_pointer
== ','
2556 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2561 ++input_line_pointer
;
2562 e
= get_symbol_name (&string
);
2564 if (strcmp (string
, "nojumps") == 0)
2565 no_cond_jump_promotion
= 1;
2566 else if (strcmp (string
, "jumps") == 0)
2569 as_bad (_("no such architecture modifier: `%s'"), string
);
2571 (void) restore_line_pointer (e
);
2574 demand_empty_rest_of_line ();
2577 enum bfd_architecture
2580 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2582 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2583 || flag_code
!= CODE_64BIT
)
2584 as_fatal (_("Intel L1OM is 64bit ELF only"));
2585 return bfd_arch_l1om
;
2587 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2589 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2590 || flag_code
!= CODE_64BIT
)
2591 as_fatal (_("Intel K1OM is 64bit ELF only"));
2592 return bfd_arch_k1om
;
2594 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2596 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2597 || flag_code
== CODE_64BIT
)
2598 as_fatal (_("Intel MCU is 32bit ELF only"));
2599 return bfd_arch_iamcu
;
2602 return bfd_arch_i386
;
2608 if (!strncmp (default_arch
, "x86_64", 6))
2610 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2612 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2613 || default_arch
[6] != '\0')
2614 as_fatal (_("Intel L1OM is 64bit ELF only"));
2615 return bfd_mach_l1om
;
2617 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2619 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2620 || default_arch
[6] != '\0')
2621 as_fatal (_("Intel K1OM is 64bit ELF only"));
2622 return bfd_mach_k1om
;
2624 else if (default_arch
[6] == '\0')
2625 return bfd_mach_x86_64
;
2627 return bfd_mach_x64_32
;
2629 else if (!strcmp (default_arch
, "i386")
2630 || !strcmp (default_arch
, "iamcu"))
2632 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2634 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2635 as_fatal (_("Intel MCU is 32bit ELF only"));
2636 return bfd_mach_i386_iamcu
;
2639 return bfd_mach_i386_i386
;
2642 as_fatal (_("unknown architecture"));
2648 const char *hash_err
;
2650 /* Support pseudo prefixes like {disp32}. */
2651 lex_type
['{'] = LEX_BEGIN_NAME
;
2653 /* Initialize op_hash hash table. */
2654 op_hash
= hash_new ();
2657 const insn_template
*optab
;
2658 templates
*core_optab
;
2660 /* Setup for loop. */
2662 core_optab
= XNEW (templates
);
2663 core_optab
->start
= optab
;
2668 if (optab
->name
== NULL
2669 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2671 /* different name --> ship out current template list;
2672 add to hash table; & begin anew. */
2673 core_optab
->end
= optab
;
2674 hash_err
= hash_insert (op_hash
,
2676 (void *) core_optab
);
2679 as_fatal (_("can't hash %s: %s"),
2683 if (optab
->name
== NULL
)
2685 core_optab
= XNEW (templates
);
2686 core_optab
->start
= optab
;
2691 /* Initialize reg_hash hash table. */
2692 reg_hash
= hash_new ();
2694 const reg_entry
*regtab
;
2695 unsigned int regtab_size
= i386_regtab_size
;
2697 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2699 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2701 as_fatal (_("can't hash %s: %s"),
2707 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2712 for (c
= 0; c
< 256; c
++)
2717 mnemonic_chars
[c
] = c
;
2718 register_chars
[c
] = c
;
2719 operand_chars
[c
] = c
;
2721 else if (ISLOWER (c
))
2723 mnemonic_chars
[c
] = c
;
2724 register_chars
[c
] = c
;
2725 operand_chars
[c
] = c
;
2727 else if (ISUPPER (c
))
2729 mnemonic_chars
[c
] = TOLOWER (c
);
2730 register_chars
[c
] = mnemonic_chars
[c
];
2731 operand_chars
[c
] = c
;
2733 else if (c
== '{' || c
== '}')
2735 mnemonic_chars
[c
] = c
;
2736 operand_chars
[c
] = c
;
2739 if (ISALPHA (c
) || ISDIGIT (c
))
2740 identifier_chars
[c
] = c
;
2743 identifier_chars
[c
] = c
;
2744 operand_chars
[c
] = c
;
2749 identifier_chars
['@'] = '@';
2752 identifier_chars
['?'] = '?';
2753 operand_chars
['?'] = '?';
2755 digit_chars
['-'] = '-';
2756 mnemonic_chars
['_'] = '_';
2757 mnemonic_chars
['-'] = '-';
2758 mnemonic_chars
['.'] = '.';
2759 identifier_chars
['_'] = '_';
2760 identifier_chars
['.'] = '.';
2762 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2763 operand_chars
[(unsigned char) *p
] = *p
;
2766 if (flag_code
== CODE_64BIT
)
2768 #if defined (OBJ_COFF) && defined (TE_PE)
2769 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2772 x86_dwarf2_return_column
= 16;
2774 x86_cie_data_alignment
= -8;
2778 x86_dwarf2_return_column
= 8;
2779 x86_cie_data_alignment
= -4;
2784 i386_print_statistics (FILE *file
)
2786 hash_print_statistics (file
, "i386 opcode", op_hash
);
2787 hash_print_statistics (file
, "i386 register", reg_hash
);
2792 /* Debugging routines for md_assemble. */
2793 static void pte (insn_template
*);
2794 static void pt (i386_operand_type
);
2795 static void pe (expressionS
*);
2796 static void ps (symbolS
*);
2799 pi (char *line
, i386_insn
*x
)
2803 fprintf (stdout
, "%s: template ", line
);
2805 fprintf (stdout
, " address: base %s index %s scale %x\n",
2806 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2807 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2808 x
->log2_scale_factor
);
2809 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2810 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2811 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2812 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2813 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2814 (x
->rex
& REX_W
) != 0,
2815 (x
->rex
& REX_R
) != 0,
2816 (x
->rex
& REX_X
) != 0,
2817 (x
->rex
& REX_B
) != 0);
2818 for (j
= 0; j
< x
->operands
; j
++)
2820 fprintf (stdout
, " #%d: ", j
+ 1);
2822 fprintf (stdout
, "\n");
2823 if (x
->types
[j
].bitfield
.reg8
2824 || x
->types
[j
].bitfield
.reg16
2825 || x
->types
[j
].bitfield
.reg32
2826 || x
->types
[j
].bitfield
.reg64
2827 || x
->types
[j
].bitfield
.regmmx
2828 || x
->types
[j
].bitfield
.regxmm
2829 || x
->types
[j
].bitfield
.regymm
2830 || x
->types
[j
].bitfield
.regzmm
2831 || x
->types
[j
].bitfield
.sreg2
2832 || x
->types
[j
].bitfield
.sreg3
2833 || x
->types
[j
].bitfield
.control
2834 || x
->types
[j
].bitfield
.debug
2835 || x
->types
[j
].bitfield
.test
)
2836 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2837 if (operand_type_check (x
->types
[j
], imm
))
2839 if (operand_type_check (x
->types
[j
], disp
))
2840 pe (x
->op
[j
].disps
);
2845 pte (insn_template
*t
)
2848 fprintf (stdout
, " %d operands ", t
->operands
);
2849 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2850 if (t
->extension_opcode
!= None
)
2851 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2852 if (t
->opcode_modifier
.d
)
2853 fprintf (stdout
, "D");
2854 if (t
->opcode_modifier
.w
)
2855 fprintf (stdout
, "W");
2856 fprintf (stdout
, "\n");
2857 for (j
= 0; j
< t
->operands
; j
++)
2859 fprintf (stdout
, " #%d type ", j
+ 1);
2860 pt (t
->operand_types
[j
]);
2861 fprintf (stdout
, "\n");
2868 fprintf (stdout
, " operation %d\n", e
->X_op
);
2869 fprintf (stdout
, " add_number %ld (%lx)\n",
2870 (long) e
->X_add_number
, (long) e
->X_add_number
);
2871 if (e
->X_add_symbol
)
2873 fprintf (stdout
, " add_symbol ");
2874 ps (e
->X_add_symbol
);
2875 fprintf (stdout
, "\n");
2879 fprintf (stdout
, " op_symbol ");
2880 ps (e
->X_op_symbol
);
2881 fprintf (stdout
, "\n");
2888 fprintf (stdout
, "%s type %s%s",
2890 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2891 segment_name (S_GET_SEGMENT (s
)));
2894 static struct type_name
2896 i386_operand_type mask
;
2899 const type_names
[] =
2901 { OPERAND_TYPE_REG8
, "r8" },
2902 { OPERAND_TYPE_REG16
, "r16" },
2903 { OPERAND_TYPE_REG32
, "r32" },
2904 { OPERAND_TYPE_REG64
, "r64" },
2905 { OPERAND_TYPE_IMM8
, "i8" },
2906 { OPERAND_TYPE_IMM8
, "i8s" },
2907 { OPERAND_TYPE_IMM16
, "i16" },
2908 { OPERAND_TYPE_IMM32
, "i32" },
2909 { OPERAND_TYPE_IMM32S
, "i32s" },
2910 { OPERAND_TYPE_IMM64
, "i64" },
2911 { OPERAND_TYPE_IMM1
, "i1" },
2912 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2913 { OPERAND_TYPE_DISP8
, "d8" },
2914 { OPERAND_TYPE_DISP16
, "d16" },
2915 { OPERAND_TYPE_DISP32
, "d32" },
2916 { OPERAND_TYPE_DISP32S
, "d32s" },
2917 { OPERAND_TYPE_DISP64
, "d64" },
2918 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2919 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2920 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2921 { OPERAND_TYPE_CONTROL
, "control reg" },
2922 { OPERAND_TYPE_TEST
, "test reg" },
2923 { OPERAND_TYPE_DEBUG
, "debug reg" },
2924 { OPERAND_TYPE_FLOATREG
, "FReg" },
2925 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2926 { OPERAND_TYPE_SREG2
, "SReg2" },
2927 { OPERAND_TYPE_SREG3
, "SReg3" },
2928 { OPERAND_TYPE_ACC
, "Acc" },
2929 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2930 { OPERAND_TYPE_REGMMX
, "rMMX" },
2931 { OPERAND_TYPE_REGXMM
, "rXMM" },
2932 { OPERAND_TYPE_REGYMM
, "rYMM" },
2933 { OPERAND_TYPE_REGZMM
, "rZMM" },
2934 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2935 { OPERAND_TYPE_ESSEG
, "es" },
2939 pt (i386_operand_type t
)
2942 i386_operand_type a
;
2944 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2946 a
= operand_type_and (t
, type_names
[j
].mask
);
2947 if (!operand_type_all_zero (&a
))
2948 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2953 #endif /* DEBUG386 */
2955 static bfd_reloc_code_real_type
2956 reloc (unsigned int size
,
2959 bfd_reloc_code_real_type other
)
2961 if (other
!= NO_RELOC
)
2963 reloc_howto_type
*rel
;
2968 case BFD_RELOC_X86_64_GOT32
:
2969 return BFD_RELOC_X86_64_GOT64
;
2971 case BFD_RELOC_X86_64_GOTPLT64
:
2972 return BFD_RELOC_X86_64_GOTPLT64
;
2974 case BFD_RELOC_X86_64_PLTOFF64
:
2975 return BFD_RELOC_X86_64_PLTOFF64
;
2977 case BFD_RELOC_X86_64_GOTPC32
:
2978 other
= BFD_RELOC_X86_64_GOTPC64
;
2980 case BFD_RELOC_X86_64_GOTPCREL
:
2981 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2983 case BFD_RELOC_X86_64_TPOFF32
:
2984 other
= BFD_RELOC_X86_64_TPOFF64
;
2986 case BFD_RELOC_X86_64_DTPOFF32
:
2987 other
= BFD_RELOC_X86_64_DTPOFF64
;
2993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2994 if (other
== BFD_RELOC_SIZE32
)
2997 other
= BFD_RELOC_SIZE64
;
3000 as_bad (_("there are no pc-relative size relocations"));
3006 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3007 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3010 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3012 as_bad (_("unknown relocation (%u)"), other
);
3013 else if (size
!= bfd_get_reloc_size (rel
))
3014 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3015 bfd_get_reloc_size (rel
),
3017 else if (pcrel
&& !rel
->pc_relative
)
3018 as_bad (_("non-pc-relative relocation for pc-relative field"));
3019 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3021 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3023 as_bad (_("relocated field and relocation type differ in signedness"));
3032 as_bad (_("there are no unsigned pc-relative relocations"));
3035 case 1: return BFD_RELOC_8_PCREL
;
3036 case 2: return BFD_RELOC_16_PCREL
;
3037 case 4: return BFD_RELOC_32_PCREL
;
3038 case 8: return BFD_RELOC_64_PCREL
;
3040 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3047 case 4: return BFD_RELOC_X86_64_32S
;
3052 case 1: return BFD_RELOC_8
;
3053 case 2: return BFD_RELOC_16
;
3054 case 4: return BFD_RELOC_32
;
3055 case 8: return BFD_RELOC_64
;
3057 as_bad (_("cannot do %s %u byte relocation"),
3058 sign
> 0 ? "signed" : "unsigned", size
);
3064 /* Here we decide which fixups can be adjusted to make them relative to
3065 the beginning of the section instead of the symbol. Basically we need
3066 to make sure that the dynamic relocations are done correctly, so in
3067 some cases we force the original symbol to be used. */
3070 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3076 /* Don't adjust pc-relative references to merge sections in 64-bit
3078 if (use_rela_relocations
3079 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3083 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3084 and changed later by validate_fix. */
3085 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3086 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3089 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3090 for size relocations. */
3091 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3092 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3093 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3094 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3095 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3096 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3097 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3098 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3099 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3100 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3101 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3102 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3103 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3104 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3105 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3106 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3107 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3108 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3109 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3110 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3111 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3112 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3113 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3114 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3115 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3116 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3117 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3118 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3119 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3120 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3121 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3122 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3123 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3130 intel_float_operand (const char *mnemonic
)
3132 /* Note that the value returned is meaningful only for opcodes with (memory)
3133 operands, hence the code here is free to improperly handle opcodes that
3134 have no operands (for better performance and smaller code). */
3136 if (mnemonic
[0] != 'f')
3137 return 0; /* non-math */
3139 switch (mnemonic
[1])
3141 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3142 the fs segment override prefix not currently handled because no
3143 call path can make opcodes without operands get here */
3145 return 2 /* integer op */;
3147 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3148 return 3; /* fldcw/fldenv */
3151 if (mnemonic
[2] != 'o' /* fnop */)
3152 return 3; /* non-waiting control op */
3155 if (mnemonic
[2] == 's')
3156 return 3; /* frstor/frstpm */
3159 if (mnemonic
[2] == 'a')
3160 return 3; /* fsave */
3161 if (mnemonic
[2] == 't')
3163 switch (mnemonic
[3])
3165 case 'c': /* fstcw */
3166 case 'd': /* fstdw */
3167 case 'e': /* fstenv */
3168 case 's': /* fsts[gw] */
3174 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3175 return 0; /* fxsave/fxrstor are not really math ops */
3182 /* Build the VEX prefix. */
3185 build_vex_prefix (const insn_template
*t
)
3187 unsigned int register_specifier
;
3188 unsigned int implied_prefix
;
3189 unsigned int vector_length
;
3191 /* Check register specifier. */
3192 if (i
.vex
.register_specifier
)
3194 register_specifier
=
3195 ~register_number (i
.vex
.register_specifier
) & 0xf;
3196 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3199 register_specifier
= 0xf;
3201 /* Use 2-byte VEX prefix by swapping destination and source
3203 if (i
.vec_encoding
!= vex_encoding_vex3
3204 && i
.dir_encoding
== dir_encoding_default
3205 && i
.operands
== i
.reg_operands
3206 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3207 && i
.tm
.opcode_modifier
.load
3210 unsigned int xchg
= i
.operands
- 1;
3211 union i386_op temp_op
;
3212 i386_operand_type temp_type
;
3214 temp_type
= i
.types
[xchg
];
3215 i
.types
[xchg
] = i
.types
[0];
3216 i
.types
[0] = temp_type
;
3217 temp_op
= i
.op
[xchg
];
3218 i
.op
[xchg
] = i
.op
[0];
3221 gas_assert (i
.rm
.mode
== 3);
3225 i
.rm
.regmem
= i
.rm
.reg
;
3228 /* Use the next insn. */
3232 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3233 vector_length
= avxscalar
;
3235 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3237 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3242 case DATA_PREFIX_OPCODE
:
3245 case REPE_PREFIX_OPCODE
:
3248 case REPNE_PREFIX_OPCODE
:
3255 /* Use 2-byte VEX prefix if possible. */
3256 if (i
.vec_encoding
!= vex_encoding_vex3
3257 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3258 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3259 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3261 /* 2-byte VEX prefix. */
3265 i
.vex
.bytes
[0] = 0xc5;
3267 /* Check the REX.R bit. */
3268 r
= (i
.rex
& REX_R
) ? 0 : 1;
3269 i
.vex
.bytes
[1] = (r
<< 7
3270 | register_specifier
<< 3
3271 | vector_length
<< 2
3276 /* 3-byte VEX prefix. */
3281 switch (i
.tm
.opcode_modifier
.vexopcode
)
3285 i
.vex
.bytes
[0] = 0xc4;
3289 i
.vex
.bytes
[0] = 0xc4;
3293 i
.vex
.bytes
[0] = 0xc4;
3297 i
.vex
.bytes
[0] = 0x8f;
3301 i
.vex
.bytes
[0] = 0x8f;
3305 i
.vex
.bytes
[0] = 0x8f;
3311 /* The high 3 bits of the second VEX byte are 1's compliment
3312 of RXB bits from REX. */
3313 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3315 /* Check the REX.W bit. */
3316 w
= (i
.rex
& REX_W
) ? 1 : 0;
3317 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3320 i
.vex
.bytes
[2] = (w
<< 7
3321 | register_specifier
<< 3
3322 | vector_length
<< 2
3327 /* Build the EVEX prefix. */
3330 build_evex_prefix (void)
3332 unsigned int register_specifier
;
3333 unsigned int implied_prefix
;
3335 rex_byte vrex_used
= 0;
3337 /* Check register specifier. */
3338 if (i
.vex
.register_specifier
)
3340 gas_assert ((i
.vrex
& REX_X
) == 0);
3342 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3343 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3344 register_specifier
+= 8;
3345 /* The upper 16 registers are encoded in the fourth byte of the
3347 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3348 i
.vex
.bytes
[3] = 0x8;
3349 register_specifier
= ~register_specifier
& 0xf;
3353 register_specifier
= 0xf;
3355 /* Encode upper 16 vector index register in the fourth byte of
3357 if (!(i
.vrex
& REX_X
))
3358 i
.vex
.bytes
[3] = 0x8;
3363 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3368 case DATA_PREFIX_OPCODE
:
3371 case REPE_PREFIX_OPCODE
:
3374 case REPNE_PREFIX_OPCODE
:
3381 /* 4 byte EVEX prefix. */
3383 i
.vex
.bytes
[0] = 0x62;
3386 switch (i
.tm
.opcode_modifier
.vexopcode
)
3402 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3404 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3406 /* The fifth bit of the second EVEX byte is 1's compliment of the
3407 REX_R bit in VREX. */
3408 if (!(i
.vrex
& REX_R
))
3409 i
.vex
.bytes
[1] |= 0x10;
3413 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3415 /* When all operands are registers, the REX_X bit in REX is not
3416 used. We reuse it to encode the upper 16 registers, which is
3417 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3418 as 1's compliment. */
3419 if ((i
.vrex
& REX_B
))
3422 i
.vex
.bytes
[1] &= ~0x40;
3426 /* EVEX instructions shouldn't need the REX prefix. */
3427 i
.vrex
&= ~vrex_used
;
3428 gas_assert (i
.vrex
== 0);
3430 /* Check the REX.W bit. */
3431 w
= (i
.rex
& REX_W
) ? 1 : 0;
3432 if (i
.tm
.opcode_modifier
.vexw
)
3434 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3437 /* If w is not set it means we are dealing with WIG instruction. */
3440 if (evexwig
== evexw1
)
3444 /* Encode the U bit. */
3445 implied_prefix
|= 0x4;
3447 /* The third byte of the EVEX prefix. */
3448 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3450 /* The fourth byte of the EVEX prefix. */
3451 /* The zeroing-masking bit. */
3452 if (i
.mask
&& i
.mask
->zeroing
)
3453 i
.vex
.bytes
[3] |= 0x80;
3455 /* Don't always set the broadcast bit if there is no RC. */
3458 /* Encode the vector length. */
3459 unsigned int vec_length
;
3461 switch (i
.tm
.opcode_modifier
.evex
)
3463 case EVEXLIG
: /* LL' is ignored */
3464 vec_length
= evexlig
<< 5;
3467 vec_length
= 0 << 5;
3470 vec_length
= 1 << 5;
3473 vec_length
= 2 << 5;
3479 i
.vex
.bytes
[3] |= vec_length
;
3480 /* Encode the broadcast bit. */
3482 i
.vex
.bytes
[3] |= 0x10;
3486 if (i
.rounding
->type
!= saeonly
)
3487 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3489 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3492 if (i
.mask
&& i
.mask
->mask
)
3493 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3497 process_immext (void)
3501 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3504 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3505 with an opcode suffix which is coded in the same place as an
3506 8-bit immediate field would be.
3507 Here we check those operands and remove them afterwards. */
3510 for (x
= 0; x
< i
.operands
; x
++)
3511 if (register_number (i
.op
[x
].regs
) != x
)
3512 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3513 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3519 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3521 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3522 suffix which is coded in the same place as an 8-bit immediate
3524 Here we check those operands and remove them afterwards. */
3527 if (i
.operands
!= 3)
3530 for (x
= 0; x
< 2; x
++)
3531 if (register_number (i
.op
[x
].regs
) != x
)
3532 goto bad_register_operand
;
3534 /* Check for third operand for mwaitx/monitorx insn. */
3535 if (register_number (i
.op
[x
].regs
)
3536 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3538 bad_register_operand
:
3539 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3540 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3547 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3548 which is coded in the same place as an 8-bit immediate field
3549 would be. Here we fake an 8-bit immediate operand from the
3550 opcode suffix stored in tm.extension_opcode.
3552 AVX instructions also use this encoding, for some of
3553 3 argument instructions. */
3555 gas_assert (i
.imm_operands
<= 1
3557 || ((i
.tm
.opcode_modifier
.vex
3558 || i
.tm
.opcode_modifier
.evex
)
3559 && i
.operands
<= 4)));
3561 exp
= &im_expressions
[i
.imm_operands
++];
3562 i
.op
[i
.operands
].imms
= exp
;
3563 i
.types
[i
.operands
] = imm8
;
3565 exp
->X_op
= O_constant
;
3566 exp
->X_add_number
= i
.tm
.extension_opcode
;
3567 i
.tm
.extension_opcode
= None
;
3574 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3579 as_bad (_("invalid instruction `%s' after `%s'"),
3580 i
.tm
.name
, i
.hle_prefix
);
3583 if (i
.prefix
[LOCK_PREFIX
])
3585 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3589 case HLEPrefixRelease
:
3590 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3592 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3596 if (i
.mem_operands
== 0
3597 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3599 as_bad (_("memory destination needed for instruction `%s'"
3600 " after `xrelease'"), i
.tm
.name
);
3607 /* This is the guts of the machine-dependent assembler. LINE points to a
3608 machine dependent instruction. This function is supposed to emit
3609 the frags/bytes it assembles to. */
3612 md_assemble (char *line
)
3615 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3616 const insn_template
*t
;
3618 /* Initialize globals. */
3619 memset (&i
, '\0', sizeof (i
));
3620 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3621 i
.reloc
[j
] = NO_RELOC
;
3622 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3623 memset (im_expressions
, '\0', sizeof (im_expressions
));
3624 save_stack_p
= save_stack
;
3626 /* First parse an instruction mnemonic & call i386_operand for the operands.
3627 We assume that the scrubber has arranged it so that line[0] is the valid
3628 start of a (possibly prefixed) mnemonic. */
3630 line
= parse_insn (line
, mnemonic
);
3633 mnem_suffix
= i
.suffix
;
3635 line
= parse_operands (line
, mnemonic
);
3637 xfree (i
.memop1_string
);
3638 i
.memop1_string
= NULL
;
3642 /* Now we've parsed the mnemonic into a set of templates, and have the
3643 operands at hand. */
3645 /* All intel opcodes have reversed operands except for "bound" and
3646 "enter". We also don't reverse intersegment "jmp" and "call"
3647 instructions with 2 immediate operands so that the immediate segment
3648 precedes the offset, as it does when in AT&T mode. */
3651 && (strcmp (mnemonic
, "bound") != 0)
3652 && (strcmp (mnemonic
, "invlpga") != 0)
3653 && !(operand_type_check (i
.types
[0], imm
)
3654 && operand_type_check (i
.types
[1], imm
)))
3657 /* The order of the immediates should be reversed
3658 for 2 immediates extrq and insertq instructions */
3659 if (i
.imm_operands
== 2
3660 && (strcmp (mnemonic
, "extrq") == 0
3661 || strcmp (mnemonic
, "insertq") == 0))
3662 swap_2_operands (0, 1);
3667 /* Don't optimize displacement for movabs since it only takes 64bit
3670 && i
.disp_encoding
!= disp_encoding_32bit
3671 && (flag_code
!= CODE_64BIT
3672 || strcmp (mnemonic
, "movabs") != 0))
3675 /* Next, we find a template that matches the given insn,
3676 making sure the overlap of the given operands types is consistent
3677 with the template operand types. */
3679 if (!(t
= match_template (mnem_suffix
)))
3682 if (sse_check
!= check_none
3683 && !i
.tm
.opcode_modifier
.noavx
3684 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3685 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3686 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3687 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3688 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3689 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3691 (sse_check
== check_warning
3693 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3696 /* Zap movzx and movsx suffix. The suffix has been set from
3697 "word ptr" or "byte ptr" on the source operand in Intel syntax
3698 or extracted from mnemonic in AT&T syntax. But we'll use
3699 the destination register to choose the suffix for encoding. */
3700 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3702 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3703 there is no suffix, the default will be byte extension. */
3704 if (i
.reg_operands
!= 2
3707 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3712 if (i
.tm
.opcode_modifier
.fwait
)
3713 if (!add_prefix (FWAIT_OPCODE
))
3716 /* Check if REP prefix is OK. */
3717 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3719 as_bad (_("invalid instruction `%s' after `%s'"),
3720 i
.tm
.name
, i
.rep_prefix
);
3724 /* Check for lock without a lockable instruction. Destination operand
3725 must be memory unless it is xchg (0x86). */
3726 if (i
.prefix
[LOCK_PREFIX
]
3727 && (!i
.tm
.opcode_modifier
.islockable
3728 || i
.mem_operands
== 0
3729 || (i
.tm
.base_opcode
!= 0x86
3730 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3732 as_bad (_("expecting lockable instruction after `lock'"));
3736 /* Check if HLE prefix is OK. */
3737 if (i
.hle_prefix
&& !check_hle ())
3740 /* Check BND prefix. */
3741 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3742 as_bad (_("expecting valid branch instruction after `bnd'"));
3744 /* Check NOTRACK prefix. */
3745 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
3746 as_bad (_("expecting indirect branch instruction after `notrack'"));
3748 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3750 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3751 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3752 else if (flag_code
!= CODE_16BIT
3753 ? i
.prefix
[ADDR_PREFIX
]
3754 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3755 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3758 /* Insert BND prefix. */
3760 && i
.tm
.opcode_modifier
.bndprefixok
3761 && !i
.prefix
[BND_PREFIX
])
3762 add_prefix (BND_PREFIX_OPCODE
);
3764 /* Check string instruction segment overrides. */
3765 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3767 if (!check_string ())
3769 i
.disp_operands
= 0;
3772 if (!process_suffix ())
3775 /* Update operand types. */
3776 for (j
= 0; j
< i
.operands
; j
++)
3777 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3779 /* Make still unresolved immediate matches conform to size of immediate
3780 given in i.suffix. */
3781 if (!finalize_imm ())
3784 if (i
.types
[0].bitfield
.imm1
)
3785 i
.imm_operands
= 0; /* kludge for shift insns. */
3787 /* We only need to check those implicit registers for instructions
3788 with 3 operands or less. */
3789 if (i
.operands
<= 3)
3790 for (j
= 0; j
< i
.operands
; j
++)
3791 if (i
.types
[j
].bitfield
.inoutportreg
3792 || i
.types
[j
].bitfield
.shiftcount
3793 || i
.types
[j
].bitfield
.acc
3794 || i
.types
[j
].bitfield
.floatacc
)
3797 /* ImmExt should be processed after SSE2AVX. */
3798 if (!i
.tm
.opcode_modifier
.sse2avx
3799 && i
.tm
.opcode_modifier
.immext
)
3802 /* For insns with operands there are more diddles to do to the opcode. */
3805 if (!process_operands ())
3808 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3810 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3811 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3814 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3816 if (flag_code
== CODE_16BIT
)
3818 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3823 if (i
.tm
.opcode_modifier
.vex
)
3824 build_vex_prefix (t
);
3826 build_evex_prefix ();
3829 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3830 instructions may define INT_OPCODE as well, so avoid this corner
3831 case for those instructions that use MODRM. */
3832 if (i
.tm
.base_opcode
== INT_OPCODE
3833 && !i
.tm
.opcode_modifier
.modrm
3834 && i
.op
[0].imms
->X_add_number
== 3)
3836 i
.tm
.base_opcode
= INT3_OPCODE
;
3840 if ((i
.tm
.opcode_modifier
.jump
3841 || i
.tm
.opcode_modifier
.jumpbyte
3842 || i
.tm
.opcode_modifier
.jumpdword
)
3843 && i
.op
[0].disps
->X_op
== O_constant
)
3845 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3846 the absolute address given by the constant. Since ix86 jumps and
3847 calls are pc relative, we need to generate a reloc. */
3848 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3849 i
.op
[0].disps
->X_op
= O_symbol
;
3852 if (i
.tm
.opcode_modifier
.rex64
)
3855 /* For 8 bit registers we need an empty rex prefix. Also if the
3856 instruction already has a prefix, we need to convert old
3857 registers to new ones. */
3859 if ((i
.types
[0].bitfield
.reg8
3860 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3861 || (i
.types
[1].bitfield
.reg8
3862 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3863 || ((i
.types
[0].bitfield
.reg8
3864 || i
.types
[1].bitfield
.reg8
)
3869 i
.rex
|= REX_OPCODE
;
3870 for (x
= 0; x
< 2; x
++)
3872 /* Look for 8 bit operand that uses old registers. */
3873 if (i
.types
[x
].bitfield
.reg8
3874 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3876 /* In case it is "hi" register, give up. */
3877 if (i
.op
[x
].regs
->reg_num
> 3)
3878 as_bad (_("can't encode register '%s%s' in an "
3879 "instruction requiring REX prefix."),
3880 register_prefix
, i
.op
[x
].regs
->reg_name
);
3882 /* Otherwise it is equivalent to the extended register.
3883 Since the encoding doesn't change this is merely
3884 cosmetic cleanup for debug output. */
3886 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3892 add_prefix (REX_OPCODE
| i
.rex
);
3894 /* We are ready to output the insn. */
3899 parse_insn (char *line
, char *mnemonic
)
3902 char *token_start
= l
;
3905 const insn_template
*t
;
3911 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3916 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3918 as_bad (_("no such instruction: `%s'"), token_start
);
3923 if (!is_space_char (*l
)
3924 && *l
!= END_OF_INSN
3926 || (*l
!= PREFIX_SEPARATOR
3929 as_bad (_("invalid character %s in mnemonic"),
3930 output_invalid (*l
));
3933 if (token_start
== l
)
3935 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3936 as_bad (_("expecting prefix; got nothing"));
3938 as_bad (_("expecting mnemonic; got nothing"));
3942 /* Look up instruction (or prefix) via hash table. */
3943 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3945 if (*l
!= END_OF_INSN
3946 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3947 && current_templates
3948 && current_templates
->start
->opcode_modifier
.isprefix
)
3950 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3952 as_bad ((flag_code
!= CODE_64BIT
3953 ? _("`%s' is only supported in 64-bit mode")
3954 : _("`%s' is not supported in 64-bit mode")),
3955 current_templates
->start
->name
);
3958 /* If we are in 16-bit mode, do not allow addr16 or data16.
3959 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3960 if ((current_templates
->start
->opcode_modifier
.size16
3961 || current_templates
->start
->opcode_modifier
.size32
)
3962 && flag_code
!= CODE_64BIT
3963 && (current_templates
->start
->opcode_modifier
.size32
3964 ^ (flag_code
== CODE_16BIT
)))
3966 as_bad (_("redundant %s prefix"),
3967 current_templates
->start
->name
);
3970 if (current_templates
->start
->opcode_length
== 0)
3972 /* Handle pseudo prefixes. */
3973 switch (current_templates
->start
->base_opcode
)
3977 i
.disp_encoding
= disp_encoding_8bit
;
3981 i
.disp_encoding
= disp_encoding_32bit
;
3985 i
.dir_encoding
= dir_encoding_load
;
3989 i
.dir_encoding
= dir_encoding_store
;
3993 i
.vec_encoding
= vex_encoding_vex2
;
3997 i
.vec_encoding
= vex_encoding_vex3
;
4001 i
.vec_encoding
= vex_encoding_evex
;
4009 /* Add prefix, checking for repeated prefixes. */
4010 switch (add_prefix (current_templates
->start
->base_opcode
))
4015 if (current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
4016 i
.notrack_prefix
= current_templates
->start
->name
;
4019 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4020 i
.hle_prefix
= current_templates
->start
->name
;
4021 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4022 i
.bnd_prefix
= current_templates
->start
->name
;
4024 i
.rep_prefix
= current_templates
->start
->name
;
4030 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4037 if (!current_templates
)
4039 /* Check if we should swap operand or force 32bit displacement in
4041 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4042 i
.dir_encoding
= dir_encoding_store
;
4043 else if (mnem_p
- 3 == dot_p
4046 i
.disp_encoding
= disp_encoding_8bit
;
4047 else if (mnem_p
- 4 == dot_p
4051 i
.disp_encoding
= disp_encoding_32bit
;
4056 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4059 if (!current_templates
)
4062 /* See if we can get a match by trimming off a suffix. */
4065 case WORD_MNEM_SUFFIX
:
4066 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4067 i
.suffix
= SHORT_MNEM_SUFFIX
;
4070 case BYTE_MNEM_SUFFIX
:
4071 case QWORD_MNEM_SUFFIX
:
4072 i
.suffix
= mnem_p
[-1];
4074 current_templates
= (const templates
*) hash_find (op_hash
,
4077 case SHORT_MNEM_SUFFIX
:
4078 case LONG_MNEM_SUFFIX
:
4081 i
.suffix
= mnem_p
[-1];
4083 current_templates
= (const templates
*) hash_find (op_hash
,
4092 if (intel_float_operand (mnemonic
) == 1)
4093 i
.suffix
= SHORT_MNEM_SUFFIX
;
4095 i
.suffix
= LONG_MNEM_SUFFIX
;
4097 current_templates
= (const templates
*) hash_find (op_hash
,
4102 if (!current_templates
)
4104 as_bad (_("no such instruction: `%s'"), token_start
);
4109 if (current_templates
->start
->opcode_modifier
.jump
4110 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4112 /* Check for a branch hint. We allow ",pt" and ",pn" for
4113 predict taken and predict not taken respectively.
4114 I'm not sure that branch hints actually do anything on loop
4115 and jcxz insns (JumpByte) for current Pentium4 chips. They
4116 may work in the future and it doesn't hurt to accept them
4118 if (l
[0] == ',' && l
[1] == 'p')
4122 if (!add_prefix (DS_PREFIX_OPCODE
))
4126 else if (l
[2] == 'n')
4128 if (!add_prefix (CS_PREFIX_OPCODE
))
4134 /* Any other comma loses. */
4137 as_bad (_("invalid character %s in mnemonic"),
4138 output_invalid (*l
));
4142 /* Check if instruction is supported on specified architecture. */
4144 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4146 supported
|= cpu_flags_match (t
);
4147 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4151 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4153 as_bad (flag_code
== CODE_64BIT
4154 ? _("`%s' is not supported in 64-bit mode")
4155 : _("`%s' is only supported in 64-bit mode"),
4156 current_templates
->start
->name
);
4159 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4161 as_bad (_("`%s' is not supported on `%s%s'"),
4162 current_templates
->start
->name
,
4163 cpu_arch_name
? cpu_arch_name
: default_arch
,
4164 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4169 if (!cpu_arch_flags
.bitfield
.cpui386
4170 && (flag_code
!= CODE_16BIT
))
4172 as_warn (_("use .code16 to ensure correct addressing mode"));
4179 parse_operands (char *l
, const char *mnemonic
)
4183 /* 1 if operand is pending after ','. */
4184 unsigned int expecting_operand
= 0;
4186 /* Non-zero if operand parens not balanced. */
4187 unsigned int paren_not_balanced
;
4189 while (*l
!= END_OF_INSN
)
4191 /* Skip optional white space before operand. */
4192 if (is_space_char (*l
))
4194 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4196 as_bad (_("invalid character %s before operand %d"),
4197 output_invalid (*l
),
4201 token_start
= l
; /* After white space. */
4202 paren_not_balanced
= 0;
4203 while (paren_not_balanced
|| *l
!= ',')
4205 if (*l
== END_OF_INSN
)
4207 if (paren_not_balanced
)
4210 as_bad (_("unbalanced parenthesis in operand %d."),
4213 as_bad (_("unbalanced brackets in operand %d."),
4218 break; /* we are done */
4220 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4222 as_bad (_("invalid character %s in operand %d"),
4223 output_invalid (*l
),
4230 ++paren_not_balanced
;
4232 --paren_not_balanced
;
4237 ++paren_not_balanced
;
4239 --paren_not_balanced
;
4243 if (l
!= token_start
)
4244 { /* Yes, we've read in another operand. */
4245 unsigned int operand_ok
;
4246 this_operand
= i
.operands
++;
4247 if (i
.operands
> MAX_OPERANDS
)
4249 as_bad (_("spurious operands; (%d operands/instruction max)"),
4253 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4254 /* Now parse operand adding info to 'i' as we go along. */
4255 END_STRING_AND_SAVE (l
);
4259 i386_intel_operand (token_start
,
4260 intel_float_operand (mnemonic
));
4262 operand_ok
= i386_att_operand (token_start
);
4264 RESTORE_END_STRING (l
);
4270 if (expecting_operand
)
4272 expecting_operand_after_comma
:
4273 as_bad (_("expecting operand after ','; got nothing"));
4278 as_bad (_("expecting operand before ','; got nothing"));
4283 /* Now *l must be either ',' or END_OF_INSN. */
4286 if (*++l
== END_OF_INSN
)
4288 /* Just skip it, if it's \n complain. */
4289 goto expecting_operand_after_comma
;
4291 expecting_operand
= 1;
4298 swap_2_operands (int xchg1
, int xchg2
)
4300 union i386_op temp_op
;
4301 i386_operand_type temp_type
;
4302 enum bfd_reloc_code_real temp_reloc
;
4304 temp_type
= i
.types
[xchg2
];
4305 i
.types
[xchg2
] = i
.types
[xchg1
];
4306 i
.types
[xchg1
] = temp_type
;
4307 temp_op
= i
.op
[xchg2
];
4308 i
.op
[xchg2
] = i
.op
[xchg1
];
4309 i
.op
[xchg1
] = temp_op
;
4310 temp_reloc
= i
.reloc
[xchg2
];
4311 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4312 i
.reloc
[xchg1
] = temp_reloc
;
4316 if (i
.mask
->operand
== xchg1
)
4317 i
.mask
->operand
= xchg2
;
4318 else if (i
.mask
->operand
== xchg2
)
4319 i
.mask
->operand
= xchg1
;
4323 if (i
.broadcast
->operand
== xchg1
)
4324 i
.broadcast
->operand
= xchg2
;
4325 else if (i
.broadcast
->operand
== xchg2
)
4326 i
.broadcast
->operand
= xchg1
;
4330 if (i
.rounding
->operand
== xchg1
)
4331 i
.rounding
->operand
= xchg2
;
4332 else if (i
.rounding
->operand
== xchg2
)
4333 i
.rounding
->operand
= xchg1
;
4338 swap_operands (void)
4344 swap_2_operands (1, i
.operands
- 2);
4348 swap_2_operands (0, i
.operands
- 1);
4354 if (i
.mem_operands
== 2)
4356 const seg_entry
*temp_seg
;
4357 temp_seg
= i
.seg
[0];
4358 i
.seg
[0] = i
.seg
[1];
4359 i
.seg
[1] = temp_seg
;
4363 /* Try to ensure constant immediates are represented in the smallest
4368 char guess_suffix
= 0;
4372 guess_suffix
= i
.suffix
;
4373 else if (i
.reg_operands
)
4375 /* Figure out a suffix from the last register operand specified.
4376 We can't do this properly yet, ie. excluding InOutPortReg,
4377 but the following works for instructions with immediates.
4378 In any case, we can't set i.suffix yet. */
4379 for (op
= i
.operands
; --op
>= 0;)
4380 if (i
.types
[op
].bitfield
.reg8
)
4382 guess_suffix
= BYTE_MNEM_SUFFIX
;
4385 else if (i
.types
[op
].bitfield
.reg16
)
4387 guess_suffix
= WORD_MNEM_SUFFIX
;
4390 else if (i
.types
[op
].bitfield
.reg32
)
4392 guess_suffix
= LONG_MNEM_SUFFIX
;
4395 else if (i
.types
[op
].bitfield
.reg64
)
4397 guess_suffix
= QWORD_MNEM_SUFFIX
;
4401 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4402 guess_suffix
= WORD_MNEM_SUFFIX
;
4404 for (op
= i
.operands
; --op
>= 0;)
4405 if (operand_type_check (i
.types
[op
], imm
))
4407 switch (i
.op
[op
].imms
->X_op
)
4410 /* If a suffix is given, this operand may be shortened. */
4411 switch (guess_suffix
)
4413 case LONG_MNEM_SUFFIX
:
4414 i
.types
[op
].bitfield
.imm32
= 1;
4415 i
.types
[op
].bitfield
.imm64
= 1;
4417 case WORD_MNEM_SUFFIX
:
4418 i
.types
[op
].bitfield
.imm16
= 1;
4419 i
.types
[op
].bitfield
.imm32
= 1;
4420 i
.types
[op
].bitfield
.imm32s
= 1;
4421 i
.types
[op
].bitfield
.imm64
= 1;
4423 case BYTE_MNEM_SUFFIX
:
4424 i
.types
[op
].bitfield
.imm8
= 1;
4425 i
.types
[op
].bitfield
.imm8s
= 1;
4426 i
.types
[op
].bitfield
.imm16
= 1;
4427 i
.types
[op
].bitfield
.imm32
= 1;
4428 i
.types
[op
].bitfield
.imm32s
= 1;
4429 i
.types
[op
].bitfield
.imm64
= 1;
4433 /* If this operand is at most 16 bits, convert it
4434 to a signed 16 bit number before trying to see
4435 whether it will fit in an even smaller size.
4436 This allows a 16-bit operand such as $0xffe0 to
4437 be recognised as within Imm8S range. */
4438 if ((i
.types
[op
].bitfield
.imm16
)
4439 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4441 i
.op
[op
].imms
->X_add_number
=
4442 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4445 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4446 if ((i
.types
[op
].bitfield
.imm32
)
4447 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4450 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4451 ^ ((offsetT
) 1 << 31))
4452 - ((offsetT
) 1 << 31));
4456 = operand_type_or (i
.types
[op
],
4457 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4459 /* We must avoid matching of Imm32 templates when 64bit
4460 only immediate is available. */
4461 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4462 i
.types
[op
].bitfield
.imm32
= 0;
4469 /* Symbols and expressions. */
4471 /* Convert symbolic operand to proper sizes for matching, but don't
4472 prevent matching a set of insns that only supports sizes other
4473 than those matching the insn suffix. */
4475 i386_operand_type mask
, allowed
;
4476 const insn_template
*t
;
4478 operand_type_set (&mask
, 0);
4479 operand_type_set (&allowed
, 0);
4481 for (t
= current_templates
->start
;
4482 t
< current_templates
->end
;
4484 allowed
= operand_type_or (allowed
,
4485 t
->operand_types
[op
]);
4486 switch (guess_suffix
)
4488 case QWORD_MNEM_SUFFIX
:
4489 mask
.bitfield
.imm64
= 1;
4490 mask
.bitfield
.imm32s
= 1;
4492 case LONG_MNEM_SUFFIX
:
4493 mask
.bitfield
.imm32
= 1;
4495 case WORD_MNEM_SUFFIX
:
4496 mask
.bitfield
.imm16
= 1;
4498 case BYTE_MNEM_SUFFIX
:
4499 mask
.bitfield
.imm8
= 1;
4504 allowed
= operand_type_and (mask
, allowed
);
4505 if (!operand_type_all_zero (&allowed
))
4506 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4513 /* Try to use the smallest displacement type too. */
4515 optimize_disp (void)
4519 for (op
= i
.operands
; --op
>= 0;)
4520 if (operand_type_check (i
.types
[op
], disp
))
4522 if (i
.op
[op
].disps
->X_op
== O_constant
)
4524 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4526 if (i
.types
[op
].bitfield
.disp16
4527 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4529 /* If this operand is at most 16 bits, convert
4530 to a signed 16 bit number and don't use 64bit
4532 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4533 i
.types
[op
].bitfield
.disp64
= 0;
4536 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4537 if (i
.types
[op
].bitfield
.disp32
4538 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4540 /* If this operand is at most 32 bits, convert
4541 to a signed 32 bit number and don't use 64bit
4543 op_disp
&= (((offsetT
) 2 << 31) - 1);
4544 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4545 i
.types
[op
].bitfield
.disp64
= 0;
4548 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4550 i
.types
[op
].bitfield
.disp8
= 0;
4551 i
.types
[op
].bitfield
.disp16
= 0;
4552 i
.types
[op
].bitfield
.disp32
= 0;
4553 i
.types
[op
].bitfield
.disp32s
= 0;
4554 i
.types
[op
].bitfield
.disp64
= 0;
4558 else if (flag_code
== CODE_64BIT
)
4560 if (fits_in_signed_long (op_disp
))
4562 i
.types
[op
].bitfield
.disp64
= 0;
4563 i
.types
[op
].bitfield
.disp32s
= 1;
4565 if (i
.prefix
[ADDR_PREFIX
]
4566 && fits_in_unsigned_long (op_disp
))
4567 i
.types
[op
].bitfield
.disp32
= 1;
4569 if ((i
.types
[op
].bitfield
.disp32
4570 || i
.types
[op
].bitfield
.disp32s
4571 || i
.types
[op
].bitfield
.disp16
)
4572 && fits_in_signed_byte (op_disp
))
4573 i
.types
[op
].bitfield
.disp8
= 1;
4575 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4576 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4578 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4579 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4580 i
.types
[op
].bitfield
.disp8
= 0;
4581 i
.types
[op
].bitfield
.disp16
= 0;
4582 i
.types
[op
].bitfield
.disp32
= 0;
4583 i
.types
[op
].bitfield
.disp32s
= 0;
4584 i
.types
[op
].bitfield
.disp64
= 0;
4587 /* We only support 64bit displacement on constants. */
4588 i
.types
[op
].bitfield
.disp64
= 0;
4592 /* Check if operands are valid for the instruction. */
4595 check_VecOperands (const insn_template
*t
)
4599 /* Without VSIB byte, we can't have a vector register for index. */
4600 if (!t
->opcode_modifier
.vecsib
4602 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4603 || i
.index_reg
->reg_type
.bitfield
.regymm
4604 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4606 i
.error
= unsupported_vector_index_register
;
4610 /* Check if default mask is allowed. */
4611 if (t
->opcode_modifier
.nodefmask
4612 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4614 i
.error
= no_default_mask
;
4618 /* For VSIB byte, we need a vector register for index, and all vector
4619 registers must be distinct. */
4620 if (t
->opcode_modifier
.vecsib
)
4623 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4624 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4625 || (t
->opcode_modifier
.vecsib
== VecSIB256
4626 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4627 || (t
->opcode_modifier
.vecsib
== VecSIB512
4628 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4630 i
.error
= invalid_vsib_address
;
4634 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4635 if (i
.reg_operands
== 2 && !i
.mask
)
4637 gas_assert (i
.types
[0].bitfield
.regxmm
4638 || i
.types
[0].bitfield
.regymm
);
4639 gas_assert (i
.types
[2].bitfield
.regxmm
4640 || i
.types
[2].bitfield
.regymm
);
4641 if (operand_check
== check_none
)
4643 if (register_number (i
.op
[0].regs
)
4644 != register_number (i
.index_reg
)
4645 && register_number (i
.op
[2].regs
)
4646 != register_number (i
.index_reg
)
4647 && register_number (i
.op
[0].regs
)
4648 != register_number (i
.op
[2].regs
))
4650 if (operand_check
== check_error
)
4652 i
.error
= invalid_vector_register_set
;
4655 as_warn (_("mask, index, and destination registers should be distinct"));
4657 else if (i
.reg_operands
== 1 && i
.mask
)
4659 if ((i
.types
[1].bitfield
.regymm
4660 || i
.types
[1].bitfield
.regzmm
)
4661 && (register_number (i
.op
[1].regs
)
4662 == register_number (i
.index_reg
)))
4664 if (operand_check
== check_error
)
4666 i
.error
= invalid_vector_register_set
;
4669 if (operand_check
!= check_none
)
4670 as_warn (_("index and destination registers should be distinct"));
4675 /* Check if broadcast is supported by the instruction and is applied
4676 to the memory operand. */
4679 int broadcasted_opnd_size
;
4681 /* Check if specified broadcast is supported in this instruction,
4682 and it's applied to memory operand of DWORD or QWORD type,
4683 depending on VecESize. */
4684 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4685 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4686 || (t
->opcode_modifier
.vecesize
== 0
4687 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4688 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4689 || (t
->opcode_modifier
.vecesize
== 1
4690 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4691 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4694 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4695 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4696 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4697 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4698 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4699 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4700 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4701 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4702 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4706 if ((broadcasted_opnd_size
== 256
4707 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4708 || (broadcasted_opnd_size
== 512
4709 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4712 i
.error
= unsupported_broadcast
;
4716 /* If broadcast is supported in this instruction, we need to check if
4717 operand of one-element size isn't specified without broadcast. */
4718 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4720 /* Find memory operand. */
4721 for (op
= 0; op
< i
.operands
; op
++)
4722 if (operand_type_check (i
.types
[op
], anymem
))
4724 gas_assert (op
< i
.operands
);
4725 /* Check size of the memory operand. */
4726 if ((t
->opcode_modifier
.vecesize
== 0
4727 && i
.types
[op
].bitfield
.dword
)
4728 || (t
->opcode_modifier
.vecesize
== 1
4729 && i
.types
[op
].bitfield
.qword
))
4731 i
.error
= broadcast_needed
;
4736 /* Check if requested masking is supported. */
4738 && (!t
->opcode_modifier
.masking
4740 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4742 i
.error
= unsupported_masking
;
4746 /* Check if masking is applied to dest operand. */
4747 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4749 i
.error
= mask_not_on_destination
;
4756 if ((i
.rounding
->type
!= saeonly
4757 && !t
->opcode_modifier
.staticrounding
)
4758 || (i
.rounding
->type
== saeonly
4759 && (t
->opcode_modifier
.staticrounding
4760 || !t
->opcode_modifier
.sae
)))
4762 i
.error
= unsupported_rc_sae
;
4765 /* If the instruction has several immediate operands and one of
4766 them is rounding, the rounding operand should be the last
4767 immediate operand. */
4768 if (i
.imm_operands
> 1
4769 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4771 i
.error
= rc_sae_operand_not_last_imm
;
4776 /* Check vector Disp8 operand. */
4777 if (t
->opcode_modifier
.disp8memshift
)
4780 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4782 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4784 for (op
= 0; op
< i
.operands
; op
++)
4785 if (operand_type_check (i
.types
[op
], disp
)
4786 && i
.op
[op
].disps
->X_op
== O_constant
)
4788 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4790 = (i
.disp_encoding
!= disp_encoding_32bit
4791 && fits_in_vec_disp8 (value
));
4792 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4795 i
.types
[op
].bitfield
.vec_disp8
= 1;
4798 /* Vector insn can only have Vec_Disp8/Disp32 in
4799 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4801 i
.types
[op
].bitfield
.disp8
= 0;
4802 if (flag_code
!= CODE_16BIT
)
4803 i
.types
[op
].bitfield
.disp16
= 0;
4806 else if (flag_code
!= CODE_16BIT
)
4808 /* One form of this instruction supports vector Disp8.
4809 Try vector Disp8 if we need to use Disp32. */
4810 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4812 i
.error
= try_vector_disp8
;
4824 /* Check if operands are valid for the instruction. Update VEX
4828 VEX_check_operands (const insn_template
*t
)
4830 if (i
.vec_encoding
== vex_encoding_evex
)
4832 /* This instruction must be encoded with EVEX prefix. */
4833 if (!t
->opcode_modifier
.evex
)
4835 i
.error
= unsupported
;
4841 if (!t
->opcode_modifier
.vex
)
4843 /* This instruction template doesn't have VEX prefix. */
4844 if (i
.vec_encoding
!= vex_encoding_default
)
4846 i
.error
= unsupported
;
4852 /* Only check VEX_Imm4, which must be the first operand. */
4853 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4855 if (i
.op
[0].imms
->X_op
!= O_constant
4856 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4862 /* Turn off Imm8 so that update_imm won't complain. */
4863 i
.types
[0] = vec_imm4
;
4869 static const insn_template
*
4870 match_template (char mnem_suffix
)
4872 /* Points to template once we've found it. */
4873 const insn_template
*t
;
4874 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4875 i386_operand_type overlap4
;
4876 unsigned int found_reverse_match
;
4877 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4878 i386_operand_type operand_types
[MAX_OPERANDS
];
4879 int addr_prefix_disp
;
4881 unsigned int found_cpu_match
;
4882 unsigned int check_register
;
4883 enum i386_error specific_error
= 0;
4885 #if MAX_OPERANDS != 5
4886 # error "MAX_OPERANDS must be 5."
4889 found_reverse_match
= 0;
4890 addr_prefix_disp
= -1;
4892 memset (&suffix_check
, 0, sizeof (suffix_check
));
4893 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4894 suffix_check
.no_bsuf
= 1;
4895 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4896 suffix_check
.no_wsuf
= 1;
4897 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4898 suffix_check
.no_ssuf
= 1;
4899 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4900 suffix_check
.no_lsuf
= 1;
4901 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4902 suffix_check
.no_qsuf
= 1;
4903 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4904 suffix_check
.no_ldsuf
= 1;
4906 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4909 switch (mnem_suffix
)
4911 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4912 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4913 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4914 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4915 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4919 /* Must have right number of operands. */
4920 i
.error
= number_of_operands_mismatch
;
4922 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4924 addr_prefix_disp
= -1;
4926 if (i
.operands
!= t
->operands
)
4929 /* Check processor support. */
4930 i
.error
= unsupported
;
4931 found_cpu_match
= (cpu_flags_match (t
)
4932 == CPU_FLAGS_PERFECT_MATCH
);
4933 if (!found_cpu_match
)
4936 /* Check old gcc support. */
4937 i
.error
= old_gcc_only
;
4938 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4941 /* Check AT&T mnemonic. */
4942 i
.error
= unsupported_with_intel_mnemonic
;
4943 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4946 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4947 i
.error
= unsupported_syntax
;
4948 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4949 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4950 || (intel64
&& t
->opcode_modifier
.amd64
)
4951 || (!intel64
&& t
->opcode_modifier
.intel64
))
4954 /* Check the suffix, except for some instructions in intel mode. */
4955 i
.error
= invalid_instruction_suffix
;
4956 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4957 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4958 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4959 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4960 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4961 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4962 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4964 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4965 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4966 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4967 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4968 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4969 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4970 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4973 if (!operand_size_match (t
))
4976 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4977 operand_types
[j
] = t
->operand_types
[j
];
4979 /* In general, don't allow 64-bit operands in 32-bit mode. */
4980 if (i
.suffix
== QWORD_MNEM_SUFFIX
4981 && flag_code
!= CODE_64BIT
4983 ? (!t
->opcode_modifier
.ignoresize
4984 && !intel_float_operand (t
->name
))
4985 : intel_float_operand (t
->name
) != 2)
4986 && ((!operand_types
[0].bitfield
.regmmx
4987 && !operand_types
[0].bitfield
.regxmm
4988 && !operand_types
[0].bitfield
.regymm
4989 && !operand_types
[0].bitfield
.regzmm
)
4990 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4991 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4992 && operand_types
[t
->operands
> 1].bitfield
.regymm
4993 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4994 && (t
->base_opcode
!= 0x0fc7
4995 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4998 /* In general, don't allow 32-bit operands on pre-386. */
4999 else if (i
.suffix
== LONG_MNEM_SUFFIX
5000 && !cpu_arch_flags
.bitfield
.cpui386
5002 ? (!t
->opcode_modifier
.ignoresize
5003 && !intel_float_operand (t
->name
))
5004 : intel_float_operand (t
->name
) != 2)
5005 && ((!operand_types
[0].bitfield
.regmmx
5006 && !operand_types
[0].bitfield
.regxmm
)
5007 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5008 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
5011 /* Do not verify operands when there are none. */
5015 /* We've found a match; break out of loop. */
5019 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5020 into Disp32/Disp16/Disp32 operand. */
5021 if (i
.prefix
[ADDR_PREFIX
] != 0)
5023 /* There should be only one Disp operand. */
5027 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5029 if (operand_types
[j
].bitfield
.disp16
)
5031 addr_prefix_disp
= j
;
5032 operand_types
[j
].bitfield
.disp32
= 1;
5033 operand_types
[j
].bitfield
.disp16
= 0;
5039 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5041 if (operand_types
[j
].bitfield
.disp32
)
5043 addr_prefix_disp
= j
;
5044 operand_types
[j
].bitfield
.disp32
= 0;
5045 operand_types
[j
].bitfield
.disp16
= 1;
5051 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5053 if (operand_types
[j
].bitfield
.disp64
)
5055 addr_prefix_disp
= j
;
5056 operand_types
[j
].bitfield
.disp64
= 0;
5057 operand_types
[j
].bitfield
.disp32
= 1;
5065 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5066 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5069 /* We check register size if needed. */
5070 check_register
= t
->opcode_modifier
.checkregsize
;
5071 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5072 switch (t
->operands
)
5075 if (!operand_type_match (overlap0
, i
.types
[0]))
5079 /* xchg %eax, %eax is a special case. It is an alias for nop
5080 only in 32bit mode and we can use opcode 0x90. In 64bit
5081 mode, we can't use 0x90 for xchg %eax, %eax since it should
5082 zero-extend %eax to %rax. */
5083 if (flag_code
== CODE_64BIT
5084 && t
->base_opcode
== 0x90
5085 && operand_type_equal (&i
.types
[0], &acc32
)
5086 && operand_type_equal (&i
.types
[1], &acc32
))
5088 /* If we want store form, we reverse direction of operands. */
5089 if (i
.dir_encoding
== dir_encoding_store
5090 && t
->opcode_modifier
.d
)
5095 /* If we want store form, we skip the current load. */
5096 if (i
.dir_encoding
== dir_encoding_store
5097 && i
.mem_operands
== 0
5098 && t
->opcode_modifier
.load
)
5103 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5104 if (!operand_type_match (overlap0
, i
.types
[0])
5105 || !operand_type_match (overlap1
, i
.types
[1])
5107 && !operand_type_register_match (overlap0
, i
.types
[0],
5109 overlap1
, i
.types
[1],
5112 /* Check if other direction is valid ... */
5113 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5117 /* Try reversing direction of operands. */
5118 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5119 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5120 if (!operand_type_match (overlap0
, i
.types
[0])
5121 || !operand_type_match (overlap1
, i
.types
[1])
5123 && !operand_type_register_match (overlap0
,
5130 /* Does not match either direction. */
5133 /* found_reverse_match holds which of D or FloatDR
5135 if (t
->opcode_modifier
.d
)
5136 found_reverse_match
= Opcode_D
;
5137 else if (t
->opcode_modifier
.floatd
)
5138 found_reverse_match
= Opcode_FloatD
;
5140 found_reverse_match
= 0;
5141 if (t
->opcode_modifier
.floatr
)
5142 found_reverse_match
|= Opcode_FloatR
;
5146 /* Found a forward 2 operand match here. */
5147 switch (t
->operands
)
5150 overlap4
= operand_type_and (i
.types
[4],
5154 overlap3
= operand_type_and (i
.types
[3],
5158 overlap2
= operand_type_and (i
.types
[2],
5163 switch (t
->operands
)
5166 if (!operand_type_match (overlap4
, i
.types
[4])
5167 || !operand_type_register_match (overlap3
,
5176 if (!operand_type_match (overlap3
, i
.types
[3])
5178 && !operand_type_register_match (overlap2
,
5187 /* Here we make use of the fact that there are no
5188 reverse match 3 operand instructions, and all 3
5189 operand instructions only need to be checked for
5190 register consistency between operands 2 and 3. */
5191 if (!operand_type_match (overlap2
, i
.types
[2])
5193 && !operand_type_register_match (overlap1
,
5203 /* Found either forward/reverse 2, 3 or 4 operand match here:
5204 slip through to break. */
5206 if (!found_cpu_match
)
5208 found_reverse_match
= 0;
5212 /* Check if vector and VEX operands are valid. */
5213 if (check_VecOperands (t
) || VEX_check_operands (t
))
5215 specific_error
= i
.error
;
5219 /* We've found a match; break out of loop. */
5223 if (t
== current_templates
->end
)
5225 /* We found no match. */
5226 const char *err_msg
;
5227 switch (specific_error
? specific_error
: i
.error
)
5231 case operand_size_mismatch
:
5232 err_msg
= _("operand size mismatch");
5234 case operand_type_mismatch
:
5235 err_msg
= _("operand type mismatch");
5237 case register_type_mismatch
:
5238 err_msg
= _("register type mismatch");
5240 case number_of_operands_mismatch
:
5241 err_msg
= _("number of operands mismatch");
5243 case invalid_instruction_suffix
:
5244 err_msg
= _("invalid instruction suffix");
5247 err_msg
= _("constant doesn't fit in 4 bits");
5250 err_msg
= _("only supported with old gcc");
5252 case unsupported_with_intel_mnemonic
:
5253 err_msg
= _("unsupported with Intel mnemonic");
5255 case unsupported_syntax
:
5256 err_msg
= _("unsupported syntax");
5259 as_bad (_("unsupported instruction `%s'"),
5260 current_templates
->start
->name
);
5262 case invalid_vsib_address
:
5263 err_msg
= _("invalid VSIB address");
5265 case invalid_vector_register_set
:
5266 err_msg
= _("mask, index, and destination registers must be distinct");
5268 case unsupported_vector_index_register
:
5269 err_msg
= _("unsupported vector index register");
5271 case unsupported_broadcast
:
5272 err_msg
= _("unsupported broadcast");
5274 case broadcast_not_on_src_operand
:
5275 err_msg
= _("broadcast not on source memory operand");
5277 case broadcast_needed
:
5278 err_msg
= _("broadcast is needed for operand of such type");
5280 case unsupported_masking
:
5281 err_msg
= _("unsupported masking");
5283 case mask_not_on_destination
:
5284 err_msg
= _("mask not on destination operand");
5286 case no_default_mask
:
5287 err_msg
= _("default mask isn't allowed");
5289 case unsupported_rc_sae
:
5290 err_msg
= _("unsupported static rounding/sae");
5292 case rc_sae_operand_not_last_imm
:
5294 err_msg
= _("RC/SAE operand must precede immediate operands");
5296 err_msg
= _("RC/SAE operand must follow immediate operands");
5298 case invalid_register_operand
:
5299 err_msg
= _("invalid register operand");
5302 as_bad (_("%s for `%s'"), err_msg
,
5303 current_templates
->start
->name
);
5307 if (!quiet_warnings
)
5310 && (i
.types
[0].bitfield
.jumpabsolute
5311 != operand_types
[0].bitfield
.jumpabsolute
))
5313 as_warn (_("indirect %s without `*'"), t
->name
);
5316 if (t
->opcode_modifier
.isprefix
5317 && t
->opcode_modifier
.ignoresize
)
5319 /* Warn them that a data or address size prefix doesn't
5320 affect assembly of the next line of code. */
5321 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5325 /* Copy the template we found. */
5328 if (addr_prefix_disp
!= -1)
5329 i
.tm
.operand_types
[addr_prefix_disp
]
5330 = operand_types
[addr_prefix_disp
];
5332 if (found_reverse_match
)
5334 /* If we found a reverse match we must alter the opcode
5335 direction bit. found_reverse_match holds bits to change
5336 (different for int & float insns). */
5338 i
.tm
.base_opcode
^= found_reverse_match
;
5340 i
.tm
.operand_types
[0] = operand_types
[1];
5341 i
.tm
.operand_types
[1] = operand_types
[0];
5350 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5351 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5353 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5355 as_bad (_("`%s' operand %d must use `%ses' segment"),
5361 /* There's only ever one segment override allowed per instruction.
5362 This instruction possibly has a legal segment override on the
5363 second operand, so copy the segment to where non-string
5364 instructions store it, allowing common code. */
5365 i
.seg
[0] = i
.seg
[1];
5367 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5369 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5371 as_bad (_("`%s' operand %d must use `%ses' segment"),
5382 process_suffix (void)
5384 /* If matched instruction specifies an explicit instruction mnemonic
5386 if (i
.tm
.opcode_modifier
.size16
)
5387 i
.suffix
= WORD_MNEM_SUFFIX
;
5388 else if (i
.tm
.opcode_modifier
.size32
)
5389 i
.suffix
= LONG_MNEM_SUFFIX
;
5390 else if (i
.tm
.opcode_modifier
.size64
)
5391 i
.suffix
= QWORD_MNEM_SUFFIX
;
5392 else if (i
.reg_operands
)
5394 /* If there's no instruction mnemonic suffix we try to invent one
5395 based on register operands. */
5398 /* We take i.suffix from the last register operand specified,
5399 Destination register type is more significant than source
5400 register type. crc32 in SSE4.2 prefers source register
5402 if (i
.tm
.base_opcode
== 0xf20f38f1)
5404 if (i
.types
[0].bitfield
.reg16
)
5405 i
.suffix
= WORD_MNEM_SUFFIX
;
5406 else if (i
.types
[0].bitfield
.reg32
)
5407 i
.suffix
= LONG_MNEM_SUFFIX
;
5408 else if (i
.types
[0].bitfield
.reg64
)
5409 i
.suffix
= QWORD_MNEM_SUFFIX
;
5411 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5413 if (i
.types
[0].bitfield
.reg8
)
5414 i
.suffix
= BYTE_MNEM_SUFFIX
;
5421 if (i
.tm
.base_opcode
== 0xf20f38f1
5422 || i
.tm
.base_opcode
== 0xf20f38f0)
5424 /* We have to know the operand size for crc32. */
5425 as_bad (_("ambiguous memory operand size for `%s`"),
5430 for (op
= i
.operands
; --op
>= 0;)
5431 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5433 if (i
.types
[op
].bitfield
.reg8
)
5435 i
.suffix
= BYTE_MNEM_SUFFIX
;
5438 else if (i
.types
[op
].bitfield
.reg16
)
5440 i
.suffix
= WORD_MNEM_SUFFIX
;
5443 else if (i
.types
[op
].bitfield
.reg32
)
5445 i
.suffix
= LONG_MNEM_SUFFIX
;
5448 else if (i
.types
[op
].bitfield
.reg64
)
5450 i
.suffix
= QWORD_MNEM_SUFFIX
;
5456 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5459 && i
.tm
.opcode_modifier
.ignoresize
5460 && i
.tm
.opcode_modifier
.no_bsuf
)
5462 else if (!check_byte_reg ())
5465 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5468 && i
.tm
.opcode_modifier
.ignoresize
5469 && i
.tm
.opcode_modifier
.no_lsuf
)
5471 else if (!check_long_reg ())
5474 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5477 && i
.tm
.opcode_modifier
.ignoresize
5478 && i
.tm
.opcode_modifier
.no_qsuf
)
5480 else if (!check_qword_reg ())
5483 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5486 && i
.tm
.opcode_modifier
.ignoresize
5487 && i
.tm
.opcode_modifier
.no_wsuf
)
5489 else if (!check_word_reg ())
5492 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5493 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5494 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5496 /* Skip if the instruction has x/y/z suffix. match_template
5497 should check if it is a valid suffix. */
5499 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5500 /* Do nothing if the instruction is going to ignore the prefix. */
5505 else if (i
.tm
.opcode_modifier
.defaultsize
5507 /* exclude fldenv/frstor/fsave/fstenv */
5508 && i
.tm
.opcode_modifier
.no_ssuf
)
5510 i
.suffix
= stackop_size
;
5512 else if (intel_syntax
5514 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5515 || i
.tm
.opcode_modifier
.jumpbyte
5516 || i
.tm
.opcode_modifier
.jumpintersegment
5517 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5518 && i
.tm
.extension_opcode
<= 3)))
5523 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5525 i
.suffix
= QWORD_MNEM_SUFFIX
;
5530 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5531 i
.suffix
= LONG_MNEM_SUFFIX
;
5534 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5535 i
.suffix
= WORD_MNEM_SUFFIX
;
5544 if (i
.tm
.opcode_modifier
.w
)
5546 as_bad (_("no instruction mnemonic suffix given and "
5547 "no register operands; can't size instruction"));
5553 unsigned int suffixes
;
5555 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5556 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5558 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5560 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5562 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5564 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5567 /* There are more than suffix matches. */
5568 if (i
.tm
.opcode_modifier
.w
5569 || ((suffixes
& (suffixes
- 1))
5570 && !i
.tm
.opcode_modifier
.defaultsize
5571 && !i
.tm
.opcode_modifier
.ignoresize
))
5573 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5579 /* Change the opcode based on the operand size given by i.suffix;
5580 We don't need to change things for byte insns. */
5583 && i
.suffix
!= BYTE_MNEM_SUFFIX
5584 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5585 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5586 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5588 /* It's not a byte, select word/dword operation. */
5589 if (i
.tm
.opcode_modifier
.w
)
5591 if (i
.tm
.opcode_modifier
.shortform
)
5592 i
.tm
.base_opcode
|= 8;
5594 i
.tm
.base_opcode
|= 1;
5597 /* Now select between word & dword operations via the operand
5598 size prefix, except for instructions that will ignore this
5600 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5602 /* The address size override prefix changes the size of the
5604 if ((flag_code
== CODE_32BIT
5605 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5606 || (flag_code
!= CODE_32BIT
5607 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5608 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5611 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5612 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5613 && !i
.tm
.opcode_modifier
.ignoresize
5614 && !i
.tm
.opcode_modifier
.floatmf
5615 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5616 || (flag_code
== CODE_64BIT
5617 && i
.tm
.opcode_modifier
.jumpbyte
)))
5619 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5621 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5622 prefix
= ADDR_PREFIX_OPCODE
;
5624 if (!add_prefix (prefix
))
5628 /* Set mode64 for an operand. */
5629 if (i
.suffix
== QWORD_MNEM_SUFFIX
5630 && flag_code
== CODE_64BIT
5631 && !i
.tm
.opcode_modifier
.norex64
)
5633 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5634 need rex64. cmpxchg8b is also a special case. */
5635 if (! (i
.operands
== 2
5636 && i
.tm
.base_opcode
== 0x90
5637 && i
.tm
.extension_opcode
== None
5638 && operand_type_equal (&i
.types
[0], &acc64
)
5639 && operand_type_equal (&i
.types
[1], &acc64
))
5640 && ! (i
.operands
== 1
5641 && i
.tm
.base_opcode
== 0xfc7
5642 && i
.tm
.extension_opcode
== 1
5643 && !operand_type_check (i
.types
[0], reg
)
5644 && operand_type_check (i
.types
[0], anymem
)))
5648 /* Size floating point instruction. */
5649 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5650 if (i
.tm
.opcode_modifier
.floatmf
)
5651 i
.tm
.base_opcode
^= 4;
5658 check_byte_reg (void)
5662 for (op
= i
.operands
; --op
>= 0;)
5664 /* If this is an eight bit register, it's OK. If it's the 16 or
5665 32 bit version of an eight bit register, we will just use the
5666 low portion, and that's OK too. */
5667 if (i
.types
[op
].bitfield
.reg8
)
5670 /* I/O port address operands are OK too. */
5671 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5674 /* crc32 doesn't generate this warning. */
5675 if (i
.tm
.base_opcode
== 0xf20f38f0)
5678 if ((i
.types
[op
].bitfield
.reg16
5679 || i
.types
[op
].bitfield
.reg32
5680 || i
.types
[op
].bitfield
.reg64
)
5681 && i
.op
[op
].regs
->reg_num
< 4
5682 /* Prohibit these changes in 64bit mode, since the lowering
5683 would be more complicated. */
5684 && flag_code
!= CODE_64BIT
)
5686 #if REGISTER_WARNINGS
5687 if (!quiet_warnings
)
5688 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5690 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5691 ? REGNAM_AL
- REGNAM_AX
5692 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5694 i
.op
[op
].regs
->reg_name
,
5699 /* Any other register is bad. */
5700 if (i
.types
[op
].bitfield
.reg16
5701 || i
.types
[op
].bitfield
.reg32
5702 || i
.types
[op
].bitfield
.reg64
5703 || i
.types
[op
].bitfield
.regmmx
5704 || i
.types
[op
].bitfield
.regxmm
5705 || i
.types
[op
].bitfield
.regymm
5706 || i
.types
[op
].bitfield
.regzmm
5707 || i
.types
[op
].bitfield
.sreg2
5708 || i
.types
[op
].bitfield
.sreg3
5709 || i
.types
[op
].bitfield
.control
5710 || i
.types
[op
].bitfield
.debug
5711 || i
.types
[op
].bitfield
.test
5712 || i
.types
[op
].bitfield
.floatreg
5713 || i
.types
[op
].bitfield
.floatacc
)
5715 as_bad (_("`%s%s' not allowed with `%s%c'"),
5717 i
.op
[op
].regs
->reg_name
,
5727 check_long_reg (void)
5731 for (op
= i
.operands
; --op
>= 0;)
5732 /* Reject eight bit registers, except where the template requires
5733 them. (eg. movzb) */
5734 if (i
.types
[op
].bitfield
.reg8
5735 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5736 || i
.tm
.operand_types
[op
].bitfield
.reg32
5737 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5739 as_bad (_("`%s%s' not allowed with `%s%c'"),
5741 i
.op
[op
].regs
->reg_name
,
5746 /* Warn if the e prefix on a general reg is missing. */
5747 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5748 && i
.types
[op
].bitfield
.reg16
5749 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5750 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5752 /* Prohibit these changes in the 64bit mode, since the
5753 lowering is more complicated. */
5754 if (flag_code
== CODE_64BIT
)
5756 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5757 register_prefix
, i
.op
[op
].regs
->reg_name
,
5761 #if REGISTER_WARNINGS
5762 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5764 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5765 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5768 /* Warn if the r prefix on a general reg is present. */
5769 else if (i
.types
[op
].bitfield
.reg64
5770 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5771 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5774 && i
.tm
.opcode_modifier
.toqword
5775 && !i
.types
[0].bitfield
.regxmm
)
5777 /* Convert to QWORD. We want REX byte. */
5778 i
.suffix
= QWORD_MNEM_SUFFIX
;
5782 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5783 register_prefix
, i
.op
[op
].regs
->reg_name
,
5792 check_qword_reg (void)
5796 for (op
= i
.operands
; --op
>= 0; )
5797 /* Reject eight bit registers, except where the template requires
5798 them. (eg. movzb) */
5799 if (i
.types
[op
].bitfield
.reg8
5800 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5801 || i
.tm
.operand_types
[op
].bitfield
.reg32
5802 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5804 as_bad (_("`%s%s' not allowed with `%s%c'"),
5806 i
.op
[op
].regs
->reg_name
,
5811 /* Warn if the r prefix on a general reg is missing. */
5812 else if ((i
.types
[op
].bitfield
.reg16
5813 || i
.types
[op
].bitfield
.reg32
)
5814 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5815 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5817 /* Prohibit these changes in the 64bit mode, since the
5818 lowering is more complicated. */
5820 && i
.tm
.opcode_modifier
.todword
5821 && !i
.types
[0].bitfield
.regxmm
)
5823 /* Convert to DWORD. We don't want REX byte. */
5824 i
.suffix
= LONG_MNEM_SUFFIX
;
5828 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5829 register_prefix
, i
.op
[op
].regs
->reg_name
,
5838 check_word_reg (void)
5841 for (op
= i
.operands
; --op
>= 0;)
5842 /* Reject eight bit registers, except where the template requires
5843 them. (eg. movzb) */
5844 if (i
.types
[op
].bitfield
.reg8
5845 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5846 || i
.tm
.operand_types
[op
].bitfield
.reg32
5847 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5849 as_bad (_("`%s%s' not allowed with `%s%c'"),
5851 i
.op
[op
].regs
->reg_name
,
5856 /* Warn if the e or r prefix on a general reg is present. */
5857 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5858 && (i
.types
[op
].bitfield
.reg32
5859 || i
.types
[op
].bitfield
.reg64
)
5860 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5861 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5863 /* Prohibit these changes in the 64bit mode, since the
5864 lowering is more complicated. */
5865 if (flag_code
== CODE_64BIT
)
5867 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5868 register_prefix
, i
.op
[op
].regs
->reg_name
,
5872 #if REGISTER_WARNINGS
5873 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5875 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5876 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5883 update_imm (unsigned int j
)
5885 i386_operand_type overlap
= i
.types
[j
];
5886 if ((overlap
.bitfield
.imm8
5887 || overlap
.bitfield
.imm8s
5888 || overlap
.bitfield
.imm16
5889 || overlap
.bitfield
.imm32
5890 || overlap
.bitfield
.imm32s
5891 || overlap
.bitfield
.imm64
)
5892 && !operand_type_equal (&overlap
, &imm8
)
5893 && !operand_type_equal (&overlap
, &imm8s
)
5894 && !operand_type_equal (&overlap
, &imm16
)
5895 && !operand_type_equal (&overlap
, &imm32
)
5896 && !operand_type_equal (&overlap
, &imm32s
)
5897 && !operand_type_equal (&overlap
, &imm64
))
5901 i386_operand_type temp
;
5903 operand_type_set (&temp
, 0);
5904 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5906 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5907 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5909 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5910 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5911 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5913 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5914 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5917 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5920 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5921 || operand_type_equal (&overlap
, &imm16_32
)
5922 || operand_type_equal (&overlap
, &imm16_32s
))
5924 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5929 if (!operand_type_equal (&overlap
, &imm8
)
5930 && !operand_type_equal (&overlap
, &imm8s
)
5931 && !operand_type_equal (&overlap
, &imm16
)
5932 && !operand_type_equal (&overlap
, &imm32
)
5933 && !operand_type_equal (&overlap
, &imm32s
)
5934 && !operand_type_equal (&overlap
, &imm64
))
5936 as_bad (_("no instruction mnemonic suffix given; "
5937 "can't determine immediate size"));
5941 i
.types
[j
] = overlap
;
5951 /* Update the first 2 immediate operands. */
5952 n
= i
.operands
> 2 ? 2 : i
.operands
;
5955 for (j
= 0; j
< n
; j
++)
5956 if (update_imm (j
) == 0)
5959 /* The 3rd operand can't be immediate operand. */
5960 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5967 bad_implicit_operand (int xmm
)
5969 const char *ireg
= xmm
? "xmm0" : "ymm0";
5972 as_bad (_("the last operand of `%s' must be `%s%s'"),
5973 i
.tm
.name
, register_prefix
, ireg
);
5975 as_bad (_("the first operand of `%s' must be `%s%s'"),
5976 i
.tm
.name
, register_prefix
, ireg
);
5981 process_operands (void)
5983 /* Default segment register this instruction will use for memory
5984 accesses. 0 means unknown. This is only for optimizing out
5985 unnecessary segment overrides. */
5986 const seg_entry
*default_seg
= 0;
5988 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5990 unsigned int dupl
= i
.operands
;
5991 unsigned int dest
= dupl
- 1;
5994 /* The destination must be an xmm register. */
5995 gas_assert (i
.reg_operands
5996 && MAX_OPERANDS
> dupl
5997 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5999 if (i
.tm
.opcode_modifier
.firstxmm0
)
6001 /* The first operand is implicit and must be xmm0. */
6002 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
6003 if (register_number (i
.op
[0].regs
) != 0)
6004 return bad_implicit_operand (1);
6006 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6008 /* Keep xmm0 for instructions with VEX prefix and 3
6014 /* We remove the first xmm0 and keep the number of
6015 operands unchanged, which in fact duplicates the
6017 for (j
= 1; j
< i
.operands
; j
++)
6019 i
.op
[j
- 1] = i
.op
[j
];
6020 i
.types
[j
- 1] = i
.types
[j
];
6021 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6025 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6027 gas_assert ((MAX_OPERANDS
- 1) > dupl
6028 && (i
.tm
.opcode_modifier
.vexsources
6031 /* Add the implicit xmm0 for instructions with VEX prefix
6033 for (j
= i
.operands
; j
> 0; j
--)
6035 i
.op
[j
] = i
.op
[j
- 1];
6036 i
.types
[j
] = i
.types
[j
- 1];
6037 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6040 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6041 i
.types
[0] = regxmm
;
6042 i
.tm
.operand_types
[0] = regxmm
;
6045 i
.reg_operands
+= 2;
6050 i
.op
[dupl
] = i
.op
[dest
];
6051 i
.types
[dupl
] = i
.types
[dest
];
6052 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6061 i
.op
[dupl
] = i
.op
[dest
];
6062 i
.types
[dupl
] = i
.types
[dest
];
6063 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6066 if (i
.tm
.opcode_modifier
.immext
)
6069 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6073 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6074 gas_assert (i
.reg_operands
6075 && (operand_type_equal (&i
.types
[0], ®xmm
)
6076 || operand_type_equal (&i
.types
[0], ®ymm
)
6077 || operand_type_equal (&i
.types
[0], ®zmm
)));
6078 if (register_number (i
.op
[0].regs
) != 0)
6079 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6081 for (j
= 1; j
< i
.operands
; j
++)
6083 i
.op
[j
- 1] = i
.op
[j
];
6084 i
.types
[j
- 1] = i
.types
[j
];
6086 /* We need to adjust fields in i.tm since they are used by
6087 build_modrm_byte. */
6088 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6095 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6097 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6098 gas_assert (i
.operands
>= 2
6099 && (operand_type_equal (&i
.types
[1], ®xmm
)
6100 || operand_type_equal (&i
.types
[1], ®ymm
)
6101 || operand_type_equal (&i
.types
[1], ®zmm
)));
6102 unsigned int regnum
= register_number (i
.op
[1].regs
);
6103 unsigned int first_reg_in_group
= regnum
& ~3;
6104 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6105 if (regnum
!= first_reg_in_group
) {
6106 as_warn (_("the second source register `%s%s' implicitly denotes"
6107 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6108 register_prefix
, i
.op
[1].regs
->reg_name
,
6109 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6110 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6114 else if (i
.tm
.opcode_modifier
.regkludge
)
6116 /* The imul $imm, %reg instruction is converted into
6117 imul $imm, %reg, %reg, and the clr %reg instruction
6118 is converted into xor %reg, %reg. */
6120 unsigned int first_reg_op
;
6122 if (operand_type_check (i
.types
[0], reg
))
6126 /* Pretend we saw the extra register operand. */
6127 gas_assert (i
.reg_operands
== 1
6128 && i
.op
[first_reg_op
+ 1].regs
== 0);
6129 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6130 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6135 if (i
.tm
.opcode_modifier
.shortform
)
6137 if (i
.types
[0].bitfield
.sreg2
6138 || i
.types
[0].bitfield
.sreg3
)
6140 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6141 && i
.op
[0].regs
->reg_num
== 1)
6143 as_bad (_("you can't `pop %scs'"), register_prefix
);
6146 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6147 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6152 /* The register or float register operand is in operand
6156 if (i
.types
[0].bitfield
.floatreg
6157 || operand_type_check (i
.types
[0], reg
))
6161 /* Register goes in low 3 bits of opcode. */
6162 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6163 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6165 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6167 /* Warn about some common errors, but press on regardless.
6168 The first case can be generated by gcc (<= 2.8.1). */
6169 if (i
.operands
== 2)
6171 /* Reversed arguments on faddp, fsubp, etc. */
6172 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6173 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6174 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6178 /* Extraneous `l' suffix on fp insn. */
6179 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6180 register_prefix
, i
.op
[0].regs
->reg_name
);
6185 else if (i
.tm
.opcode_modifier
.modrm
)
6187 /* The opcode is completed (modulo i.tm.extension_opcode which
6188 must be put into the modrm byte). Now, we make the modrm and
6189 index base bytes based on all the info we've collected. */
6191 default_seg
= build_modrm_byte ();
6193 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6197 else if (i
.tm
.opcode_modifier
.isstring
)
6199 /* For the string instructions that allow a segment override
6200 on one of their operands, the default segment is ds. */
6204 if (i
.tm
.base_opcode
== 0x8d /* lea */
6207 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6209 /* If a segment was explicitly specified, and the specified segment
6210 is not the default, use an opcode prefix to select it. If we
6211 never figured out what the default segment is, then default_seg
6212 will be zero at this point, and the specified segment prefix will
6214 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6216 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6222 static const seg_entry
*
6223 build_modrm_byte (void)
6225 const seg_entry
*default_seg
= 0;
6226 unsigned int source
, dest
;
6229 /* The first operand of instructions with VEX prefix and 3 sources
6230 must be VEX_Imm4. */
6231 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6234 unsigned int nds
, reg_slot
;
6237 if (i
.tm
.opcode_modifier
.veximmext
6238 && i
.tm
.opcode_modifier
.immext
)
6240 dest
= i
.operands
- 2;
6241 gas_assert (dest
== 3);
6244 dest
= i
.operands
- 1;
6247 /* There are 2 kinds of instructions:
6248 1. 5 operands: 4 register operands or 3 register operands
6249 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6250 VexW0 or VexW1. The destination must be either XMM, YMM or
6252 2. 4 operands: 4 register operands or 3 register operands
6253 plus 1 memory operand, VexXDS, and VexImmExt */
6254 gas_assert ((i
.reg_operands
== 4
6255 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6256 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6257 && (i
.tm
.opcode_modifier
.veximmext
6258 || (i
.imm_operands
== 1
6259 && i
.types
[0].bitfield
.vec_imm4
6260 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6261 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6262 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6263 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6264 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6266 if (i
.imm_operands
== 0)
6268 /* When there is no immediate operand, generate an 8bit
6269 immediate operand to encode the first operand. */
6270 exp
= &im_expressions
[i
.imm_operands
++];
6271 i
.op
[i
.operands
].imms
= exp
;
6272 i
.types
[i
.operands
] = imm8
;
6274 /* If VexW1 is set, the first operand is the source and
6275 the second operand is encoded in the immediate operand. */
6276 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6287 /* FMA swaps REG and NDS. */
6288 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6296 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6298 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6300 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6302 exp
->X_op
= O_constant
;
6303 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6304 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6308 unsigned int imm_slot
;
6310 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6312 /* If VexW0 is set, the third operand is the source and
6313 the second operand is encoded in the immediate
6320 /* VexW1 is set, the second operand is the source and
6321 the third operand is encoded in the immediate
6327 if (i
.tm
.opcode_modifier
.immext
)
6329 /* When ImmExt is set, the immediate byte is the last
6331 imm_slot
= i
.operands
- 1;
6339 /* Turn on Imm8 so that output_imm will generate it. */
6340 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6343 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6345 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6347 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6349 i
.op
[imm_slot
].imms
->X_add_number
6350 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6351 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6354 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6355 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6357 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6359 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6364 /* i.reg_operands MUST be the number of real register operands;
6365 implicit registers do not count. If there are 3 register
6366 operands, it must be a instruction with VexNDS. For a
6367 instruction with VexNDD, the destination register is encoded
6368 in VEX prefix. If there are 4 register operands, it must be
6369 a instruction with VEX prefix and 3 sources. */
6370 if (i
.mem_operands
== 0
6371 && ((i
.reg_operands
== 2
6372 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6373 || (i
.reg_operands
== 3
6374 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6375 || (i
.reg_operands
== 4 && vex_3_sources
)))
6383 /* When there are 3 operands, one of them may be immediate,
6384 which may be the first or the last operand. Otherwise,
6385 the first operand must be shift count register (cl) or it
6386 is an instruction with VexNDS. */
6387 gas_assert (i
.imm_operands
== 1
6388 || (i
.imm_operands
== 0
6389 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6390 || i
.types
[0].bitfield
.shiftcount
)));
6391 if (operand_type_check (i
.types
[0], imm
)
6392 || i
.types
[0].bitfield
.shiftcount
)
6398 /* When there are 4 operands, the first two must be 8bit
6399 immediate operands. The source operand will be the 3rd
6402 For instructions with VexNDS, if the first operand
6403 an imm8, the source operand is the 2nd one. If the last
6404 operand is imm8, the source operand is the first one. */
6405 gas_assert ((i
.imm_operands
== 2
6406 && i
.types
[0].bitfield
.imm8
6407 && i
.types
[1].bitfield
.imm8
)
6408 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6409 && i
.imm_operands
== 1
6410 && (i
.types
[0].bitfield
.imm8
6411 || i
.types
[i
.operands
- 1].bitfield
.imm8
6413 if (i
.imm_operands
== 2)
6417 if (i
.types
[0].bitfield
.imm8
)
6424 if (i
.tm
.opcode_modifier
.evex
)
6426 /* For EVEX instructions, when there are 5 operands, the
6427 first one must be immediate operand. If the second one
6428 is immediate operand, the source operand is the 3th
6429 one. If the last one is immediate operand, the source
6430 operand is the 2nd one. */
6431 gas_assert (i
.imm_operands
== 2
6432 && i
.tm
.opcode_modifier
.sae
6433 && operand_type_check (i
.types
[0], imm
));
6434 if (operand_type_check (i
.types
[1], imm
))
6436 else if (operand_type_check (i
.types
[4], imm
))
6450 /* RC/SAE operand could be between DEST and SRC. That happens
6451 when one operand is GPR and the other one is XMM/YMM/ZMM
6453 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6456 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6458 /* For instructions with VexNDS, the register-only source
6459 operand must be 32/64bit integer, XMM, YMM or ZMM
6460 register. It is encoded in VEX prefix. We need to
6461 clear RegMem bit before calling operand_type_equal. */
6463 i386_operand_type op
;
6466 /* Check register-only source operand when two source
6467 operands are swapped. */
6468 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6469 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6477 op
= i
.tm
.operand_types
[vvvv
];
6478 op
.bitfield
.regmem
= 0;
6479 if ((dest
+ 1) >= i
.operands
6480 || (!op
.bitfield
.reg32
6481 && op
.bitfield
.reg64
6482 && !operand_type_equal (&op
, ®xmm
)
6483 && !operand_type_equal (&op
, ®ymm
)
6484 && !operand_type_equal (&op
, ®zmm
)
6485 && !operand_type_equal (&op
, ®mask
)))
6487 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6493 /* One of the register operands will be encoded in the i.tm.reg
6494 field, the other in the combined i.tm.mode and i.tm.regmem
6495 fields. If no form of this instruction supports a memory
6496 destination operand, then we assume the source operand may
6497 sometimes be a memory operand and so we need to store the
6498 destination in the i.rm.reg field. */
6499 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6500 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6502 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6503 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6504 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6506 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6508 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6510 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6515 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6516 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6517 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6519 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6521 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6523 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6526 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6528 if (!i
.types
[0].bitfield
.control
6529 && !i
.types
[1].bitfield
.control
)
6531 i
.rex
&= ~(REX_R
| REX_B
);
6532 add_prefix (LOCK_PREFIX_OPCODE
);
6536 { /* If it's not 2 reg operands... */
6541 unsigned int fake_zero_displacement
= 0;
6544 for (op
= 0; op
< i
.operands
; op
++)
6545 if (operand_type_check (i
.types
[op
], anymem
))
6547 gas_assert (op
< i
.operands
);
6549 if (i
.tm
.opcode_modifier
.vecsib
)
6551 if (i
.index_reg
->reg_num
== RegEiz
6552 || i
.index_reg
->reg_num
== RegRiz
)
6555 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6558 i
.sib
.base
= NO_BASE_REGISTER
;
6559 i
.sib
.scale
= i
.log2_scale_factor
;
6560 /* No Vec_Disp8 if there is no base. */
6561 i
.types
[op
].bitfield
.vec_disp8
= 0;
6562 i
.types
[op
].bitfield
.disp8
= 0;
6563 i
.types
[op
].bitfield
.disp16
= 0;
6564 i
.types
[op
].bitfield
.disp64
= 0;
6565 if (flag_code
!= CODE_64BIT
)
6567 /* Must be 32 bit */
6568 i
.types
[op
].bitfield
.disp32
= 1;
6569 i
.types
[op
].bitfield
.disp32s
= 0;
6573 i
.types
[op
].bitfield
.disp32
= 0;
6574 i
.types
[op
].bitfield
.disp32s
= 1;
6577 i
.sib
.index
= i
.index_reg
->reg_num
;
6578 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6580 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6586 if (i
.base_reg
== 0)
6589 if (!i
.disp_operands
)
6591 fake_zero_displacement
= 1;
6592 /* Instructions with VSIB byte need 32bit displacement
6593 if there is no base register. */
6594 if (i
.tm
.opcode_modifier
.vecsib
)
6595 i
.types
[op
].bitfield
.disp32
= 1;
6597 if (i
.index_reg
== 0)
6599 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6600 /* Operand is just <disp> */
6601 if (flag_code
== CODE_64BIT
)
6603 /* 64bit mode overwrites the 32bit absolute
6604 addressing by RIP relative addressing and
6605 absolute addressing is encoded by one of the
6606 redundant SIB forms. */
6607 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6608 i
.sib
.base
= NO_BASE_REGISTER
;
6609 i
.sib
.index
= NO_INDEX_REGISTER
;
6610 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6611 ? disp32s
: disp32
);
6613 else if ((flag_code
== CODE_16BIT
)
6614 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6616 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6617 i
.types
[op
] = disp16
;
6621 i
.rm
.regmem
= NO_BASE_REGISTER
;
6622 i
.types
[op
] = disp32
;
6625 else if (!i
.tm
.opcode_modifier
.vecsib
)
6627 /* !i.base_reg && i.index_reg */
6628 if (i
.index_reg
->reg_num
== RegEiz
6629 || i
.index_reg
->reg_num
== RegRiz
)
6630 i
.sib
.index
= NO_INDEX_REGISTER
;
6632 i
.sib
.index
= i
.index_reg
->reg_num
;
6633 i
.sib
.base
= NO_BASE_REGISTER
;
6634 i
.sib
.scale
= i
.log2_scale_factor
;
6635 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6636 /* No Vec_Disp8 if there is no base. */
6637 i
.types
[op
].bitfield
.vec_disp8
= 0;
6638 i
.types
[op
].bitfield
.disp8
= 0;
6639 i
.types
[op
].bitfield
.disp16
= 0;
6640 i
.types
[op
].bitfield
.disp64
= 0;
6641 if (flag_code
!= CODE_64BIT
)
6643 /* Must be 32 bit */
6644 i
.types
[op
].bitfield
.disp32
= 1;
6645 i
.types
[op
].bitfield
.disp32s
= 0;
6649 i
.types
[op
].bitfield
.disp32
= 0;
6650 i
.types
[op
].bitfield
.disp32s
= 1;
6652 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6656 /* RIP addressing for 64bit mode. */
6657 else if (i
.base_reg
->reg_num
== RegRip
||
6658 i
.base_reg
->reg_num
== RegEip
)
6660 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6661 i
.rm
.regmem
= NO_BASE_REGISTER
;
6662 i
.types
[op
].bitfield
.disp8
= 0;
6663 i
.types
[op
].bitfield
.disp16
= 0;
6664 i
.types
[op
].bitfield
.disp32
= 0;
6665 i
.types
[op
].bitfield
.disp32s
= 1;
6666 i
.types
[op
].bitfield
.disp64
= 0;
6667 i
.types
[op
].bitfield
.vec_disp8
= 0;
6668 i
.flags
[op
] |= Operand_PCrel
;
6669 if (! i
.disp_operands
)
6670 fake_zero_displacement
= 1;
6672 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6674 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6675 switch (i
.base_reg
->reg_num
)
6678 if (i
.index_reg
== 0)
6680 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6681 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6685 if (i
.index_reg
== 0)
6688 if (operand_type_check (i
.types
[op
], disp
) == 0)
6690 /* fake (%bp) into 0(%bp) */
6691 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6692 i
.types
[op
].bitfield
.vec_disp8
= 1;
6694 i
.types
[op
].bitfield
.disp8
= 1;
6695 fake_zero_displacement
= 1;
6698 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6699 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6701 default: /* (%si) -> 4 or (%di) -> 5 */
6702 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6704 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6706 else /* i.base_reg and 32/64 bit mode */
6708 if (flag_code
== CODE_64BIT
6709 && operand_type_check (i
.types
[op
], disp
))
6711 i386_operand_type temp
;
6712 operand_type_set (&temp
, 0);
6713 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6714 temp
.bitfield
.vec_disp8
6715 = i
.types
[op
].bitfield
.vec_disp8
;
6717 if (i
.prefix
[ADDR_PREFIX
] == 0)
6718 i
.types
[op
].bitfield
.disp32s
= 1;
6720 i
.types
[op
].bitfield
.disp32
= 1;
6723 if (!i
.tm
.opcode_modifier
.vecsib
)
6724 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6725 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6727 i
.sib
.base
= i
.base_reg
->reg_num
;
6728 /* x86-64 ignores REX prefix bit here to avoid decoder
6730 if (!(i
.base_reg
->reg_flags
& RegRex
)
6731 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6732 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6734 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6736 fake_zero_displacement
= 1;
6737 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6738 i
.types
[op
].bitfield
.vec_disp8
= 1;
6740 i
.types
[op
].bitfield
.disp8
= 1;
6742 i
.sib
.scale
= i
.log2_scale_factor
;
6743 if (i
.index_reg
== 0)
6745 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6746 /* <disp>(%esp) becomes two byte modrm with no index
6747 register. We've already stored the code for esp
6748 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6749 Any base register besides %esp will not use the
6750 extra modrm byte. */
6751 i
.sib
.index
= NO_INDEX_REGISTER
;
6753 else if (!i
.tm
.opcode_modifier
.vecsib
)
6755 if (i
.index_reg
->reg_num
== RegEiz
6756 || i
.index_reg
->reg_num
== RegRiz
)
6757 i
.sib
.index
= NO_INDEX_REGISTER
;
6759 i
.sib
.index
= i
.index_reg
->reg_num
;
6760 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6761 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6766 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6767 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6771 if (!fake_zero_displacement
6775 fake_zero_displacement
= 1;
6776 if (i
.disp_encoding
== disp_encoding_8bit
)
6777 i
.types
[op
].bitfield
.disp8
= 1;
6779 i
.types
[op
].bitfield
.disp32
= 1;
6781 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6785 if (fake_zero_displacement
)
6787 /* Fakes a zero displacement assuming that i.types[op]
6788 holds the correct displacement size. */
6791 gas_assert (i
.op
[op
].disps
== 0);
6792 exp
= &disp_expressions
[i
.disp_operands
++];
6793 i
.op
[op
].disps
= exp
;
6794 exp
->X_op
= O_constant
;
6795 exp
->X_add_number
= 0;
6796 exp
->X_add_symbol
= (symbolS
*) 0;
6797 exp
->X_op_symbol
= (symbolS
*) 0;
6805 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6807 if (operand_type_check (i
.types
[0], imm
))
6808 i
.vex
.register_specifier
= NULL
;
6811 /* VEX.vvvv encodes one of the sources when the first
6812 operand is not an immediate. */
6813 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6814 i
.vex
.register_specifier
= i
.op
[0].regs
;
6816 i
.vex
.register_specifier
= i
.op
[1].regs
;
6819 /* Destination is a XMM register encoded in the ModRM.reg
6821 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6822 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6825 /* ModRM.rm and VEX.B encodes the other source. */
6826 if (!i
.mem_operands
)
6830 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6831 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6833 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6835 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6839 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6841 i
.vex
.register_specifier
= i
.op
[2].regs
;
6842 if (!i
.mem_operands
)
6845 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6846 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6850 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6851 (if any) based on i.tm.extension_opcode. Again, we must be
6852 careful to make sure that segment/control/debug/test/MMX
6853 registers are coded into the i.rm.reg field. */
6854 else if (i
.reg_operands
)
6857 unsigned int vex_reg
= ~0;
6859 for (op
= 0; op
< i
.operands
; op
++)
6860 if (i
.types
[op
].bitfield
.reg8
6861 || i
.types
[op
].bitfield
.reg16
6862 || i
.types
[op
].bitfield
.reg32
6863 || i
.types
[op
].bitfield
.reg64
6864 || i
.types
[op
].bitfield
.regmmx
6865 || i
.types
[op
].bitfield
.regxmm
6866 || i
.types
[op
].bitfield
.regymm
6867 || i
.types
[op
].bitfield
.regbnd
6868 || i
.types
[op
].bitfield
.regzmm
6869 || i
.types
[op
].bitfield
.regmask
6870 || i
.types
[op
].bitfield
.sreg2
6871 || i
.types
[op
].bitfield
.sreg3
6872 || i
.types
[op
].bitfield
.control
6873 || i
.types
[op
].bitfield
.debug
6874 || i
.types
[op
].bitfield
.test
)
6879 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6881 /* For instructions with VexNDS, the register-only
6882 source operand is encoded in VEX prefix. */
6883 gas_assert (mem
!= (unsigned int) ~0);
6888 gas_assert (op
< i
.operands
);
6892 /* Check register-only source operand when two source
6893 operands are swapped. */
6894 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6895 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6899 gas_assert (mem
== (vex_reg
+ 1)
6900 && op
< i
.operands
);
6905 gas_assert (vex_reg
< i
.operands
);
6909 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6911 /* For instructions with VexNDD, the register destination
6912 is encoded in VEX prefix. */
6913 if (i
.mem_operands
== 0)
6915 /* There is no memory operand. */
6916 gas_assert ((op
+ 2) == i
.operands
);
6921 /* There are only 2 operands. */
6922 gas_assert (op
< 2 && i
.operands
== 2);
6927 gas_assert (op
< i
.operands
);
6929 if (vex_reg
!= (unsigned int) ~0)
6931 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6933 if (type
->bitfield
.reg32
!= 1
6934 && type
->bitfield
.reg64
!= 1
6935 && !operand_type_equal (type
, ®xmm
)
6936 && !operand_type_equal (type
, ®ymm
)
6937 && !operand_type_equal (type
, ®zmm
)
6938 && !operand_type_equal (type
, ®mask
))
6941 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6944 /* Don't set OP operand twice. */
6947 /* If there is an extension opcode to put here, the
6948 register number must be put into the regmem field. */
6949 if (i
.tm
.extension_opcode
!= None
)
6951 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6952 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6954 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6959 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6960 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6962 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6967 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6968 must set it to 3 to indicate this is a register operand
6969 in the regmem field. */
6970 if (!i
.mem_operands
)
6974 /* Fill in i.rm.reg field with extension opcode (if any). */
6975 if (i
.tm
.extension_opcode
!= None
)
6976 i
.rm
.reg
= i
.tm
.extension_opcode
;
6982 output_branch (void)
6988 relax_substateT subtype
;
6992 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6993 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6996 if (i
.prefix
[DATA_PREFIX
] != 0)
7002 /* Pentium4 branch hints. */
7003 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7004 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7009 if (i
.prefix
[REX_PREFIX
] != 0)
7015 /* BND prefixed jump. */
7016 if (i
.prefix
[BND_PREFIX
] != 0)
7018 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7022 if (i
.prefixes
!= 0 && !intel_syntax
)
7023 as_warn (_("skipping prefixes on this instruction"));
7025 /* It's always a symbol; End frag & setup for relax.
7026 Make sure there is enough room in this frag for the largest
7027 instruction we may generate in md_convert_frag. This is 2
7028 bytes for the opcode and room for the prefix and largest
7030 frag_grow (prefix
+ 2 + 4);
7031 /* Prefix and 1 opcode byte go in fr_fix. */
7032 p
= frag_more (prefix
+ 1);
7033 if (i
.prefix
[DATA_PREFIX
] != 0)
7034 *p
++ = DATA_PREFIX_OPCODE
;
7035 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7036 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7037 *p
++ = i
.prefix
[SEG_PREFIX
];
7038 if (i
.prefix
[REX_PREFIX
] != 0)
7039 *p
++ = i
.prefix
[REX_PREFIX
];
7040 *p
= i
.tm
.base_opcode
;
7042 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7043 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7044 else if (cpu_arch_flags
.bitfield
.cpui386
)
7045 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7047 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7050 sym
= i
.op
[0].disps
->X_add_symbol
;
7051 off
= i
.op
[0].disps
->X_add_number
;
7053 if (i
.op
[0].disps
->X_op
!= O_constant
7054 && i
.op
[0].disps
->X_op
!= O_symbol
)
7056 /* Handle complex expressions. */
7057 sym
= make_expr_symbol (i
.op
[0].disps
);
7061 /* 1 possible extra opcode + 4 byte displacement go in var part.
7062 Pass reloc in fr_var. */
7063 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7073 if (i
.tm
.opcode_modifier
.jumpbyte
)
7075 /* This is a loop or jecxz type instruction. */
7077 if (i
.prefix
[ADDR_PREFIX
] != 0)
7079 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7082 /* Pentium4 branch hints. */
7083 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7084 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7086 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7095 if (flag_code
== CODE_16BIT
)
7098 if (i
.prefix
[DATA_PREFIX
] != 0)
7100 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7110 if (i
.prefix
[REX_PREFIX
] != 0)
7112 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7116 /* BND prefixed jump. */
7117 if (i
.prefix
[BND_PREFIX
] != 0)
7119 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7123 if (i
.prefixes
!= 0 && !intel_syntax
)
7124 as_warn (_("skipping prefixes on this instruction"));
7126 p
= frag_more (i
.tm
.opcode_length
+ size
);
7127 switch (i
.tm
.opcode_length
)
7130 *p
++ = i
.tm
.base_opcode
>> 8;
7133 *p
++ = i
.tm
.base_opcode
;
7139 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7140 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7142 /* All jumps handled here are signed, but don't use a signed limit
7143 check for 32 and 16 bit jumps as we want to allow wrap around at
7144 4G and 64k respectively. */
7146 fixP
->fx_signed
= 1;
7150 output_interseg_jump (void)
7158 if (flag_code
== CODE_16BIT
)
7162 if (i
.prefix
[DATA_PREFIX
] != 0)
7168 if (i
.prefix
[REX_PREFIX
] != 0)
7178 if (i
.prefixes
!= 0 && !intel_syntax
)
7179 as_warn (_("skipping prefixes on this instruction"));
7181 /* 1 opcode; 2 segment; offset */
7182 p
= frag_more (prefix
+ 1 + 2 + size
);
7184 if (i
.prefix
[DATA_PREFIX
] != 0)
7185 *p
++ = DATA_PREFIX_OPCODE
;
7187 if (i
.prefix
[REX_PREFIX
] != 0)
7188 *p
++ = i
.prefix
[REX_PREFIX
];
7190 *p
++ = i
.tm
.base_opcode
;
7191 if (i
.op
[1].imms
->X_op
== O_constant
)
7193 offsetT n
= i
.op
[1].imms
->X_add_number
;
7196 && !fits_in_unsigned_word (n
)
7197 && !fits_in_signed_word (n
))
7199 as_bad (_("16-bit jump out of range"));
7202 md_number_to_chars (p
, n
, size
);
7205 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7206 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7207 if (i
.op
[0].imms
->X_op
!= O_constant
)
7208 as_bad (_("can't handle non absolute segment in `%s'"),
7210 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7216 fragS
*insn_start_frag
;
7217 offsetT insn_start_off
;
7219 /* Tie dwarf2 debug info to the address at the start of the insn.
7220 We can't do this after the insn has been output as the current
7221 frag may have been closed off. eg. by frag_var. */
7222 dwarf2_emit_insn (0);
7224 insn_start_frag
= frag_now
;
7225 insn_start_off
= frag_now_fix ();
7228 if (i
.tm
.opcode_modifier
.jump
)
7230 else if (i
.tm
.opcode_modifier
.jumpbyte
7231 || i
.tm
.opcode_modifier
.jumpdword
)
7233 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7234 output_interseg_jump ();
7237 /* Output normal instructions here. */
7241 unsigned int prefix
;
7244 && i
.tm
.base_opcode
== 0xfae
7246 && i
.imm_operands
== 1
7247 && (i
.op
[0].imms
->X_add_number
== 0xe8
7248 || i
.op
[0].imms
->X_add_number
== 0xf0
7249 || i
.op
[0].imms
->X_add_number
== 0xf8))
7251 /* Encode lfence, mfence, and sfence as
7252 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7253 offsetT val
= 0x240483f0ULL
;
7255 md_number_to_chars (p
, val
, 5);
7259 /* Some processors fail on LOCK prefix. This options makes
7260 assembler ignore LOCK prefix and serves as a workaround. */
7261 if (omit_lock_prefix
)
7263 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7265 i
.prefix
[LOCK_PREFIX
] = 0;
7268 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7269 don't need the explicit prefix. */
7270 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7272 switch (i
.tm
.opcode_length
)
7275 if (i
.tm
.base_opcode
& 0xff000000)
7277 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7282 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7284 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7285 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7288 if (prefix
!= REPE_PREFIX_OPCODE
7289 || (i
.prefix
[REP_PREFIX
]
7290 != REPE_PREFIX_OPCODE
))
7291 add_prefix (prefix
);
7294 add_prefix (prefix
);
7303 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7304 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7305 R_X86_64_GOTTPOFF relocation so that linker can safely
7306 perform IE->LE optimization. */
7307 if (x86_elf_abi
== X86_64_X32_ABI
7309 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7310 && i
.prefix
[REX_PREFIX
] == 0)
7311 add_prefix (REX_OPCODE
);
7314 /* The prefix bytes. */
7315 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7317 FRAG_APPEND_1_CHAR (*q
);
7321 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7326 /* REX byte is encoded in VEX prefix. */
7330 FRAG_APPEND_1_CHAR (*q
);
7333 /* There should be no other prefixes for instructions
7338 /* For EVEX instructions i.vrex should become 0 after
7339 build_evex_prefix. For VEX instructions upper 16 registers
7340 aren't available, so VREX should be 0. */
7343 /* Now the VEX prefix. */
7344 p
= frag_more (i
.vex
.length
);
7345 for (j
= 0; j
< i
.vex
.length
; j
++)
7346 p
[j
] = i
.vex
.bytes
[j
];
7349 /* Now the opcode; be careful about word order here! */
7350 if (i
.tm
.opcode_length
== 1)
7352 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7356 switch (i
.tm
.opcode_length
)
7360 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7361 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7365 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7375 /* Put out high byte first: can't use md_number_to_chars! */
7376 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7377 *p
= i
.tm
.base_opcode
& 0xff;
7380 /* Now the modrm byte and sib byte (if present). */
7381 if (i
.tm
.opcode_modifier
.modrm
)
7383 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7386 /* If i.rm.regmem == ESP (4)
7387 && i.rm.mode != (Register mode)
7389 ==> need second modrm byte. */
7390 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7392 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7393 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7395 | i
.sib
.scale
<< 6));
7398 if (i
.disp_operands
)
7399 output_disp (insn_start_frag
, insn_start_off
);
7402 output_imm (insn_start_frag
, insn_start_off
);
7408 pi ("" /*line*/, &i
);
7410 #endif /* DEBUG386 */
7413 /* Return the size of the displacement operand N. */
7416 disp_size (unsigned int n
)
7420 /* Vec_Disp8 has to be 8bit. */
7421 if (i
.types
[n
].bitfield
.vec_disp8
)
7423 else if (i
.types
[n
].bitfield
.disp64
)
7425 else if (i
.types
[n
].bitfield
.disp8
)
7427 else if (i
.types
[n
].bitfield
.disp16
)
7432 /* Return the size of the immediate operand N. */
7435 imm_size (unsigned int n
)
7438 if (i
.types
[n
].bitfield
.imm64
)
7440 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7442 else if (i
.types
[n
].bitfield
.imm16
)
7448 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7453 for (n
= 0; n
< i
.operands
; n
++)
7455 if (i
.types
[n
].bitfield
.vec_disp8
7456 || operand_type_check (i
.types
[n
], disp
))
7458 if (i
.op
[n
].disps
->X_op
== O_constant
)
7460 int size
= disp_size (n
);
7461 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7463 if (i
.types
[n
].bitfield
.vec_disp8
)
7465 val
= offset_in_range (val
, size
);
7466 p
= frag_more (size
);
7467 md_number_to_chars (p
, val
, size
);
7471 enum bfd_reloc_code_real reloc_type
;
7472 int size
= disp_size (n
);
7473 int sign
= i
.types
[n
].bitfield
.disp32s
;
7474 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7477 /* We can't have 8 bit displacement here. */
7478 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7480 /* The PC relative address is computed relative
7481 to the instruction boundary, so in case immediate
7482 fields follows, we need to adjust the value. */
7483 if (pcrel
&& i
.imm_operands
)
7488 for (n1
= 0; n1
< i
.operands
; n1
++)
7489 if (operand_type_check (i
.types
[n1
], imm
))
7491 /* Only one immediate is allowed for PC
7492 relative address. */
7493 gas_assert (sz
== 0);
7495 i
.op
[n
].disps
->X_add_number
-= sz
;
7497 /* We should find the immediate. */
7498 gas_assert (sz
!= 0);
7501 p
= frag_more (size
);
7502 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7504 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7505 && (((reloc_type
== BFD_RELOC_32
7506 || reloc_type
== BFD_RELOC_X86_64_32S
7507 || (reloc_type
== BFD_RELOC_64
7509 && (i
.op
[n
].disps
->X_op
== O_symbol
7510 || (i
.op
[n
].disps
->X_op
== O_add
7511 && ((symbol_get_value_expression
7512 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7514 || reloc_type
== BFD_RELOC_32_PCREL
))
7518 if (insn_start_frag
== frag_now
)
7519 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7524 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7525 for (fr
= insn_start_frag
->fr_next
;
7526 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7528 add
+= p
- frag_now
->fr_literal
;
7533 reloc_type
= BFD_RELOC_386_GOTPC
;
7534 i
.op
[n
].imms
->X_add_number
+= add
;
7536 else if (reloc_type
== BFD_RELOC_64
)
7537 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7539 /* Don't do the adjustment for x86-64, as there
7540 the pcrel addressing is relative to the _next_
7541 insn, and that is taken care of in other code. */
7542 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7544 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7545 size
, i
.op
[n
].disps
, pcrel
,
7547 /* Check for "call/jmp *mem", "mov mem, %reg",
7548 "test %reg, mem" and "binop mem, %reg" where binop
7549 is one of adc, add, and, cmp, or, sbb, sub, xor
7550 instructions. Always generate R_386_GOT32X for
7551 "sym*GOT" operand in 32-bit mode. */
7552 if ((generate_relax_relocations
7555 && i
.rm
.regmem
== 5))
7557 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7558 && ((i
.operands
== 1
7559 && i
.tm
.base_opcode
== 0xff
7560 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7562 && (i
.tm
.base_opcode
== 0x8b
7563 || i
.tm
.base_opcode
== 0x85
7564 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7568 fixP
->fx_tcbit
= i
.rex
!= 0;
7570 && (i
.base_reg
->reg_num
== RegRip
7571 || i
.base_reg
->reg_num
== RegEip
))
7572 fixP
->fx_tcbit2
= 1;
7575 fixP
->fx_tcbit2
= 1;
7583 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7588 for (n
= 0; n
< i
.operands
; n
++)
7590 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7591 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7594 if (operand_type_check (i
.types
[n
], imm
))
7596 if (i
.op
[n
].imms
->X_op
== O_constant
)
7598 int size
= imm_size (n
);
7601 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7603 p
= frag_more (size
);
7604 md_number_to_chars (p
, val
, size
);
7608 /* Not absolute_section.
7609 Need a 32-bit fixup (don't support 8bit
7610 non-absolute imms). Try to support other
7612 enum bfd_reloc_code_real reloc_type
;
7613 int size
= imm_size (n
);
7616 if (i
.types
[n
].bitfield
.imm32s
7617 && (i
.suffix
== QWORD_MNEM_SUFFIX
7618 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7623 p
= frag_more (size
);
7624 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7626 /* This is tough to explain. We end up with this one if we
7627 * have operands that look like
7628 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7629 * obtain the absolute address of the GOT, and it is strongly
7630 * preferable from a performance point of view to avoid using
7631 * a runtime relocation for this. The actual sequence of
7632 * instructions often look something like:
7637 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7639 * The call and pop essentially return the absolute address
7640 * of the label .L66 and store it in %ebx. The linker itself
7641 * will ultimately change the first operand of the addl so
7642 * that %ebx points to the GOT, but to keep things simple, the
7643 * .o file must have this operand set so that it generates not
7644 * the absolute address of .L66, but the absolute address of
7645 * itself. This allows the linker itself simply treat a GOTPC
7646 * relocation as asking for a pcrel offset to the GOT to be
7647 * added in, and the addend of the relocation is stored in the
7648 * operand field for the instruction itself.
7650 * Our job here is to fix the operand so that it would add
7651 * the correct offset so that %ebx would point to itself. The
7652 * thing that is tricky is that .-.L66 will point to the
7653 * beginning of the instruction, so we need to further modify
7654 * the operand so that it will point to itself. There are
7655 * other cases where you have something like:
7657 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7659 * and here no correction would be required. Internally in
7660 * the assembler we treat operands of this form as not being
7661 * pcrel since the '.' is explicitly mentioned, and I wonder
7662 * whether it would simplify matters to do it this way. Who
7663 * knows. In earlier versions of the PIC patches, the
7664 * pcrel_adjust field was used to store the correction, but
7665 * since the expression is not pcrel, I felt it would be
7666 * confusing to do it this way. */
7668 if ((reloc_type
== BFD_RELOC_32
7669 || reloc_type
== BFD_RELOC_X86_64_32S
7670 || reloc_type
== BFD_RELOC_64
)
7672 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7673 && (i
.op
[n
].imms
->X_op
== O_symbol
7674 || (i
.op
[n
].imms
->X_op
== O_add
7675 && ((symbol_get_value_expression
7676 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7681 if (insn_start_frag
== frag_now
)
7682 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7687 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7688 for (fr
= insn_start_frag
->fr_next
;
7689 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7691 add
+= p
- frag_now
->fr_literal
;
7695 reloc_type
= BFD_RELOC_386_GOTPC
;
7697 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7699 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7700 i
.op
[n
].imms
->X_add_number
+= add
;
7702 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7703 i
.op
[n
].imms
, 0, reloc_type
);
7709 /* x86_cons_fix_new is called via the expression parsing code when a
7710 reloc is needed. We use this hook to get the correct .got reloc. */
7711 static int cons_sign
= -1;
7714 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7715 expressionS
*exp
, bfd_reloc_code_real_type r
)
7717 r
= reloc (len
, 0, cons_sign
, r
);
7720 if (exp
->X_op
== O_secrel
)
7722 exp
->X_op
= O_symbol
;
7723 r
= BFD_RELOC_32_SECREL
;
7727 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7730 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7731 purpose of the `.dc.a' internal pseudo-op. */
7734 x86_address_bytes (void)
7736 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7738 return stdoutput
->arch_info
->bits_per_address
/ 8;
7741 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7743 # define lex_got(reloc, adjust, types) NULL
7745 /* Parse operands of the form
7746 <symbol>@GOTOFF+<nnn>
7747 and similar .plt or .got references.
7749 If we find one, set up the correct relocation in RELOC and copy the
7750 input string, minus the `@GOTOFF' into a malloc'd buffer for
7751 parsing by the calling routine. Return this buffer, and if ADJUST
7752 is non-null set it to the length of the string we removed from the
7753 input line. Otherwise return NULL. */
7755 lex_got (enum bfd_reloc_code_real
*rel
,
7757 i386_operand_type
*types
)
7759 /* Some of the relocations depend on the size of what field is to
7760 be relocated. But in our callers i386_immediate and i386_displacement
7761 we don't yet know the operand size (this will be set by insn
7762 matching). Hence we record the word32 relocation here,
7763 and adjust the reloc according to the real size in reloc(). */
7764 static const struct {
7767 const enum bfd_reloc_code_real rel
[2];
7768 const i386_operand_type types64
;
7770 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7771 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7773 OPERAND_TYPE_IMM32_64
},
7775 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7776 BFD_RELOC_X86_64_PLTOFF64
},
7777 OPERAND_TYPE_IMM64
},
7778 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7779 BFD_RELOC_X86_64_PLT32
},
7780 OPERAND_TYPE_IMM32_32S_DISP32
},
7781 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7782 BFD_RELOC_X86_64_GOTPLT64
},
7783 OPERAND_TYPE_IMM64_DISP64
},
7784 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7785 BFD_RELOC_X86_64_GOTOFF64
},
7786 OPERAND_TYPE_IMM64_DISP64
},
7787 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7788 BFD_RELOC_X86_64_GOTPCREL
},
7789 OPERAND_TYPE_IMM32_32S_DISP32
},
7790 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7791 BFD_RELOC_X86_64_TLSGD
},
7792 OPERAND_TYPE_IMM32_32S_DISP32
},
7793 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7794 _dummy_first_bfd_reloc_code_real
},
7795 OPERAND_TYPE_NONE
},
7796 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7797 BFD_RELOC_X86_64_TLSLD
},
7798 OPERAND_TYPE_IMM32_32S_DISP32
},
7799 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7800 BFD_RELOC_X86_64_GOTTPOFF
},
7801 OPERAND_TYPE_IMM32_32S_DISP32
},
7802 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7803 BFD_RELOC_X86_64_TPOFF32
},
7804 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7805 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7806 _dummy_first_bfd_reloc_code_real
},
7807 OPERAND_TYPE_NONE
},
7808 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7809 BFD_RELOC_X86_64_DTPOFF32
},
7810 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7811 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7812 _dummy_first_bfd_reloc_code_real
},
7813 OPERAND_TYPE_NONE
},
7814 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7815 _dummy_first_bfd_reloc_code_real
},
7816 OPERAND_TYPE_NONE
},
7817 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7818 BFD_RELOC_X86_64_GOT32
},
7819 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7820 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7821 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7822 OPERAND_TYPE_IMM32_32S_DISP32
},
7823 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7824 BFD_RELOC_X86_64_TLSDESC_CALL
},
7825 OPERAND_TYPE_IMM32_32S_DISP32
},
7830 #if defined (OBJ_MAYBE_ELF)
7835 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7836 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7839 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7841 int len
= gotrel
[j
].len
;
7842 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7844 if (gotrel
[j
].rel
[object_64bit
] != 0)
7847 char *tmpbuf
, *past_reloc
;
7849 *rel
= gotrel
[j
].rel
[object_64bit
];
7853 if (flag_code
!= CODE_64BIT
)
7855 types
->bitfield
.imm32
= 1;
7856 types
->bitfield
.disp32
= 1;
7859 *types
= gotrel
[j
].types64
;
7862 if (j
!= 0 && GOT_symbol
== NULL
)
7863 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7865 /* The length of the first part of our input line. */
7866 first
= cp
- input_line_pointer
;
7868 /* The second part goes from after the reloc token until
7869 (and including) an end_of_line char or comma. */
7870 past_reloc
= cp
+ 1 + len
;
7872 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7874 second
= cp
+ 1 - past_reloc
;
7876 /* Allocate and copy string. The trailing NUL shouldn't
7877 be necessary, but be safe. */
7878 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7879 memcpy (tmpbuf
, input_line_pointer
, first
);
7880 if (second
!= 0 && *past_reloc
!= ' ')
7881 /* Replace the relocation token with ' ', so that
7882 errors like foo@GOTOFF1 will be detected. */
7883 tmpbuf
[first
++] = ' ';
7885 /* Increment length by 1 if the relocation token is
7890 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7891 tmpbuf
[first
+ second
] = '\0';
7895 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7896 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7901 /* Might be a symbol version string. Don't as_bad here. */
7910 /* Parse operands of the form
7911 <symbol>@SECREL32+<nnn>
7913 If we find one, set up the correct relocation in RELOC and copy the
7914 input string, minus the `@SECREL32' into a malloc'd buffer for
7915 parsing by the calling routine. Return this buffer, and if ADJUST
7916 is non-null set it to the length of the string we removed from the
7917 input line. Otherwise return NULL.
7919 This function is copied from the ELF version above adjusted for PE targets. */
7922 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7923 int *adjust ATTRIBUTE_UNUSED
,
7924 i386_operand_type
*types
)
7930 const enum bfd_reloc_code_real rel
[2];
7931 const i386_operand_type types64
;
7935 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7936 BFD_RELOC_32_SECREL
},
7937 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7943 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7944 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7947 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7949 int len
= gotrel
[j
].len
;
7951 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7953 if (gotrel
[j
].rel
[object_64bit
] != 0)
7956 char *tmpbuf
, *past_reloc
;
7958 *rel
= gotrel
[j
].rel
[object_64bit
];
7964 if (flag_code
!= CODE_64BIT
)
7966 types
->bitfield
.imm32
= 1;
7967 types
->bitfield
.disp32
= 1;
7970 *types
= gotrel
[j
].types64
;
7973 /* The length of the first part of our input line. */
7974 first
= cp
- input_line_pointer
;
7976 /* The second part goes from after the reloc token until
7977 (and including) an end_of_line char or comma. */
7978 past_reloc
= cp
+ 1 + len
;
7980 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7982 second
= cp
+ 1 - past_reloc
;
7984 /* Allocate and copy string. The trailing NUL shouldn't
7985 be necessary, but be safe. */
7986 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7987 memcpy (tmpbuf
, input_line_pointer
, first
);
7988 if (second
!= 0 && *past_reloc
!= ' ')
7989 /* Replace the relocation token with ' ', so that
7990 errors like foo@SECLREL321 will be detected. */
7991 tmpbuf
[first
++] = ' ';
7992 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7993 tmpbuf
[first
+ second
] = '\0';
7997 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7998 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8003 /* Might be a symbol version string. Don't as_bad here. */
8009 bfd_reloc_code_real_type
8010 x86_cons (expressionS
*exp
, int size
)
8012 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8014 intel_syntax
= -intel_syntax
;
8017 if (size
== 4 || (object_64bit
&& size
== 8))
8019 /* Handle @GOTOFF and the like in an expression. */
8021 char *gotfree_input_line
;
8024 save
= input_line_pointer
;
8025 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8026 if (gotfree_input_line
)
8027 input_line_pointer
= gotfree_input_line
;
8031 if (gotfree_input_line
)
8033 /* expression () has merrily parsed up to the end of line,
8034 or a comma - in the wrong buffer. Transfer how far
8035 input_line_pointer has moved to the right buffer. */
8036 input_line_pointer
= (save
8037 + (input_line_pointer
- gotfree_input_line
)
8039 free (gotfree_input_line
);
8040 if (exp
->X_op
== O_constant
8041 || exp
->X_op
== O_absent
8042 || exp
->X_op
== O_illegal
8043 || exp
->X_op
== O_register
8044 || exp
->X_op
== O_big
)
8046 char c
= *input_line_pointer
;
8047 *input_line_pointer
= 0;
8048 as_bad (_("missing or invalid expression `%s'"), save
);
8049 *input_line_pointer
= c
;
8056 intel_syntax
= -intel_syntax
;
8059 i386_intel_simplify (exp
);
8065 signed_cons (int size
)
8067 if (flag_code
== CODE_64BIT
)
8075 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8082 if (exp
.X_op
== O_symbol
)
8083 exp
.X_op
= O_secrel
;
8085 emit_expr (&exp
, 4);
8087 while (*input_line_pointer
++ == ',');
8089 input_line_pointer
--;
8090 demand_empty_rest_of_line ();
8094 /* Handle Vector operations. */
8097 check_VecOperations (char *op_string
, char *op_end
)
8099 const reg_entry
*mask
;
8104 && (op_end
== NULL
|| op_string
< op_end
))
8107 if (*op_string
== '{')
8111 /* Check broadcasts. */
8112 if (strncmp (op_string
, "1to", 3) == 0)
8117 goto duplicated_vec_op
;
8120 if (*op_string
== '8')
8121 bcst_type
= BROADCAST_1TO8
;
8122 else if (*op_string
== '4')
8123 bcst_type
= BROADCAST_1TO4
;
8124 else if (*op_string
== '2')
8125 bcst_type
= BROADCAST_1TO2
;
8126 else if (*op_string
== '1'
8127 && *(op_string
+1) == '6')
8129 bcst_type
= BROADCAST_1TO16
;
8134 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8139 broadcast_op
.type
= bcst_type
;
8140 broadcast_op
.operand
= this_operand
;
8141 i
.broadcast
= &broadcast_op
;
8143 /* Check masking operation. */
8144 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8146 /* k0 can't be used for write mask. */
8147 if (mask
->reg_num
== 0)
8149 as_bad (_("`%s' can't be used for write mask"),
8156 mask_op
.mask
= mask
;
8157 mask_op
.zeroing
= 0;
8158 mask_op
.operand
= this_operand
;
8164 goto duplicated_vec_op
;
8166 i
.mask
->mask
= mask
;
8168 /* Only "{z}" is allowed here. No need to check
8169 zeroing mask explicitly. */
8170 if (i
.mask
->operand
!= this_operand
)
8172 as_bad (_("invalid write mask `%s'"), saved
);
8179 /* Check zeroing-flag for masking operation. */
8180 else if (*op_string
== 'z')
8184 mask_op
.mask
= NULL
;
8185 mask_op
.zeroing
= 1;
8186 mask_op
.operand
= this_operand
;
8191 if (i
.mask
->zeroing
)
8194 as_bad (_("duplicated `%s'"), saved
);
8198 i
.mask
->zeroing
= 1;
8200 /* Only "{%k}" is allowed here. No need to check mask
8201 register explicitly. */
8202 if (i
.mask
->operand
!= this_operand
)
8204 as_bad (_("invalid zeroing-masking `%s'"),
8213 goto unknown_vec_op
;
8215 if (*op_string
!= '}')
8217 as_bad (_("missing `}' in `%s'"), saved
);
8224 /* We don't know this one. */
8225 as_bad (_("unknown vector operation: `%s'"), saved
);
8233 i386_immediate (char *imm_start
)
8235 char *save_input_line_pointer
;
8236 char *gotfree_input_line
;
8239 i386_operand_type types
;
8241 operand_type_set (&types
, ~0);
8243 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8245 as_bad (_("at most %d immediate operands are allowed"),
8246 MAX_IMMEDIATE_OPERANDS
);
8250 exp
= &im_expressions
[i
.imm_operands
++];
8251 i
.op
[this_operand
].imms
= exp
;
8253 if (is_space_char (*imm_start
))
8256 save_input_line_pointer
= input_line_pointer
;
8257 input_line_pointer
= imm_start
;
8259 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8260 if (gotfree_input_line
)
8261 input_line_pointer
= gotfree_input_line
;
8263 exp_seg
= expression (exp
);
8267 /* Handle vector operations. */
8268 if (*input_line_pointer
== '{')
8270 input_line_pointer
= check_VecOperations (input_line_pointer
,
8272 if (input_line_pointer
== NULL
)
8276 if (*input_line_pointer
)
8277 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8279 input_line_pointer
= save_input_line_pointer
;
8280 if (gotfree_input_line
)
8282 free (gotfree_input_line
);
8284 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8285 exp
->X_op
= O_illegal
;
8288 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8292 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8293 i386_operand_type types
, const char *imm_start
)
8295 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8298 as_bad (_("missing or invalid immediate expression `%s'"),
8302 else if (exp
->X_op
== O_constant
)
8304 /* Size it properly later. */
8305 i
.types
[this_operand
].bitfield
.imm64
= 1;
8306 /* If not 64bit, sign extend val. */
8307 if (flag_code
!= CODE_64BIT
8308 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8310 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8312 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8313 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8314 && exp_seg
!= absolute_section
8315 && exp_seg
!= text_section
8316 && exp_seg
!= data_section
8317 && exp_seg
!= bss_section
8318 && exp_seg
!= undefined_section
8319 && !bfd_is_com_section (exp_seg
))
8321 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8325 else if (!intel_syntax
&& exp_seg
== reg_section
)
8328 as_bad (_("illegal immediate register operand %s"), imm_start
);
8333 /* This is an address. The size of the address will be
8334 determined later, depending on destination register,
8335 suffix, or the default for the section. */
8336 i
.types
[this_operand
].bitfield
.imm8
= 1;
8337 i
.types
[this_operand
].bitfield
.imm16
= 1;
8338 i
.types
[this_operand
].bitfield
.imm32
= 1;
8339 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8340 i
.types
[this_operand
].bitfield
.imm64
= 1;
8341 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8349 i386_scale (char *scale
)
8352 char *save
= input_line_pointer
;
8354 input_line_pointer
= scale
;
8355 val
= get_absolute_expression ();
8360 i
.log2_scale_factor
= 0;
8363 i
.log2_scale_factor
= 1;
8366 i
.log2_scale_factor
= 2;
8369 i
.log2_scale_factor
= 3;
8373 char sep
= *input_line_pointer
;
8375 *input_line_pointer
= '\0';
8376 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8378 *input_line_pointer
= sep
;
8379 input_line_pointer
= save
;
8383 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8385 as_warn (_("scale factor of %d without an index register"),
8386 1 << i
.log2_scale_factor
);
8387 i
.log2_scale_factor
= 0;
8389 scale
= input_line_pointer
;
8390 input_line_pointer
= save
;
8395 i386_displacement (char *disp_start
, char *disp_end
)
8399 char *save_input_line_pointer
;
8400 char *gotfree_input_line
;
8402 i386_operand_type bigdisp
, types
= anydisp
;
8405 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8407 as_bad (_("at most %d displacement operands are allowed"),
8408 MAX_MEMORY_OPERANDS
);
8412 operand_type_set (&bigdisp
, 0);
8413 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8414 || (!current_templates
->start
->opcode_modifier
.jump
8415 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8417 bigdisp
.bitfield
.disp32
= 1;
8418 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8419 if (flag_code
== CODE_64BIT
)
8423 bigdisp
.bitfield
.disp32s
= 1;
8424 bigdisp
.bitfield
.disp64
= 1;
8427 else if ((flag_code
== CODE_16BIT
) ^ override
)
8429 bigdisp
.bitfield
.disp32
= 0;
8430 bigdisp
.bitfield
.disp16
= 1;
8435 /* For PC-relative branches, the width of the displacement
8436 is dependent upon data size, not address size. */
8437 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8438 if (flag_code
== CODE_64BIT
)
8440 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8441 bigdisp
.bitfield
.disp16
= 1;
8444 bigdisp
.bitfield
.disp32
= 1;
8445 bigdisp
.bitfield
.disp32s
= 1;
8451 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8453 : LONG_MNEM_SUFFIX
));
8454 bigdisp
.bitfield
.disp32
= 1;
8455 if ((flag_code
== CODE_16BIT
) ^ override
)
8457 bigdisp
.bitfield
.disp32
= 0;
8458 bigdisp
.bitfield
.disp16
= 1;
8462 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8465 exp
= &disp_expressions
[i
.disp_operands
];
8466 i
.op
[this_operand
].disps
= exp
;
8468 save_input_line_pointer
= input_line_pointer
;
8469 input_line_pointer
= disp_start
;
8470 END_STRING_AND_SAVE (disp_end
);
8472 #ifndef GCC_ASM_O_HACK
8473 #define GCC_ASM_O_HACK 0
8476 END_STRING_AND_SAVE (disp_end
+ 1);
8477 if (i
.types
[this_operand
].bitfield
.baseIndex
8478 && displacement_string_end
[-1] == '+')
8480 /* This hack is to avoid a warning when using the "o"
8481 constraint within gcc asm statements.
8484 #define _set_tssldt_desc(n,addr,limit,type) \
8485 __asm__ __volatile__ ( \
8487 "movw %w1,2+%0\n\t" \
8489 "movb %b1,4+%0\n\t" \
8490 "movb %4,5+%0\n\t" \
8491 "movb $0,6+%0\n\t" \
8492 "movb %h1,7+%0\n\t" \
8494 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8496 This works great except that the output assembler ends
8497 up looking a bit weird if it turns out that there is
8498 no offset. You end up producing code that looks like:
8511 So here we provide the missing zero. */
8513 *displacement_string_end
= '0';
8516 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8517 if (gotfree_input_line
)
8518 input_line_pointer
= gotfree_input_line
;
8520 exp_seg
= expression (exp
);
8523 if (*input_line_pointer
)
8524 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8526 RESTORE_END_STRING (disp_end
+ 1);
8528 input_line_pointer
= save_input_line_pointer
;
8529 if (gotfree_input_line
)
8531 free (gotfree_input_line
);
8533 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8534 exp
->X_op
= O_illegal
;
8537 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8539 RESTORE_END_STRING (disp_end
);
8545 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8546 i386_operand_type types
, const char *disp_start
)
8548 i386_operand_type bigdisp
;
8551 /* We do this to make sure that the section symbol is in
8552 the symbol table. We will ultimately change the relocation
8553 to be relative to the beginning of the section. */
8554 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8555 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8556 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8558 if (exp
->X_op
!= O_symbol
)
8561 if (S_IS_LOCAL (exp
->X_add_symbol
)
8562 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8563 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8564 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8565 exp
->X_op
= O_subtract
;
8566 exp
->X_op_symbol
= GOT_symbol
;
8567 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8568 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8569 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8570 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8572 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8575 else if (exp
->X_op
== O_absent
8576 || exp
->X_op
== O_illegal
8577 || exp
->X_op
== O_big
)
8580 as_bad (_("missing or invalid displacement expression `%s'"),
8585 else if (flag_code
== CODE_64BIT
8586 && !i
.prefix
[ADDR_PREFIX
]
8587 && exp
->X_op
== O_constant
)
8589 /* Since displacement is signed extended to 64bit, don't allow
8590 disp32 and turn off disp32s if they are out of range. */
8591 i
.types
[this_operand
].bitfield
.disp32
= 0;
8592 if (!fits_in_signed_long (exp
->X_add_number
))
8594 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8595 if (i
.types
[this_operand
].bitfield
.baseindex
)
8597 as_bad (_("0x%lx out range of signed 32bit displacement"),
8598 (long) exp
->X_add_number
);
8604 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8605 else if (exp
->X_op
!= O_constant
8606 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8607 && exp_seg
!= absolute_section
8608 && exp_seg
!= text_section
8609 && exp_seg
!= data_section
8610 && exp_seg
!= bss_section
8611 && exp_seg
!= undefined_section
8612 && !bfd_is_com_section (exp_seg
))
8614 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8619 /* Check if this is a displacement only operand. */
8620 bigdisp
= i
.types
[this_operand
];
8621 bigdisp
.bitfield
.disp8
= 0;
8622 bigdisp
.bitfield
.disp16
= 0;
8623 bigdisp
.bitfield
.disp32
= 0;
8624 bigdisp
.bitfield
.disp32s
= 0;
8625 bigdisp
.bitfield
.disp64
= 0;
8626 if (operand_type_all_zero (&bigdisp
))
8627 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8633 /* Make sure the memory operand we've been dealt is valid.
8634 Return 1 on success, 0 on a failure. */
8637 i386_index_check (const char *operand_string
)
8639 const char *kind
= "base/index";
8640 enum flag_code addr_mode
;
8642 if (i
.prefix
[ADDR_PREFIX
])
8643 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8646 addr_mode
= flag_code
;
8648 #if INFER_ADDR_PREFIX
8649 if (i
.mem_operands
== 0)
8651 /* Infer address prefix from the first memory operand. */
8652 const reg_entry
*addr_reg
= i
.base_reg
;
8654 if (addr_reg
== NULL
)
8655 addr_reg
= i
.index_reg
;
8659 if (addr_reg
->reg_num
== RegEip
8660 || addr_reg
->reg_num
== RegEiz
8661 || addr_reg
->reg_type
.bitfield
.reg32
)
8662 addr_mode
= CODE_32BIT
;
8663 else if (flag_code
!= CODE_64BIT
8664 && addr_reg
->reg_type
.bitfield
.reg16
)
8665 addr_mode
= CODE_16BIT
;
8667 if (addr_mode
!= flag_code
)
8669 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8671 /* Change the size of any displacement too. At most one
8672 of Disp16 or Disp32 is set.
8673 FIXME. There doesn't seem to be any real need for
8674 separate Disp16 and Disp32 flags. The same goes for
8675 Imm16 and Imm32. Removing them would probably clean
8676 up the code quite a lot. */
8677 if (flag_code
!= CODE_64BIT
8678 && (i
.types
[this_operand
].bitfield
.disp16
8679 || i
.types
[this_operand
].bitfield
.disp32
))
8680 i
.types
[this_operand
]
8681 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8688 if (current_templates
->start
->opcode_modifier
.isstring
8689 && !current_templates
->start
->opcode_modifier
.immext
8690 && (current_templates
->end
[-1].opcode_modifier
.isstring
8693 /* Memory operands of string insns are special in that they only allow
8694 a single register (rDI, rSI, or rBX) as their memory address. */
8695 const reg_entry
*expected_reg
;
8696 static const char *di_si
[][2] =
8702 static const char *bx
[] = { "ebx", "bx", "rbx" };
8704 kind
= "string address";
8706 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8708 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8710 if (!type
.bitfield
.baseindex
8711 || ((!i
.mem_operands
!= !intel_syntax
)
8712 && current_templates
->end
[-1].operand_types
[1]
8713 .bitfield
.baseindex
))
8714 type
= current_templates
->end
[-1].operand_types
[1];
8715 expected_reg
= hash_find (reg_hash
,
8716 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8720 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8722 if (i
.base_reg
!= expected_reg
8724 || operand_type_check (i
.types
[this_operand
], disp
))
8726 /* The second memory operand must have the same size as
8730 && !((addr_mode
== CODE_64BIT
8731 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8732 || (addr_mode
== CODE_32BIT
8733 ? i
.base_reg
->reg_type
.bitfield
.reg32
8734 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8737 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8739 intel_syntax
? '[' : '(',
8741 expected_reg
->reg_name
,
8742 intel_syntax
? ']' : ')');
8749 as_bad (_("`%s' is not a valid %s expression"),
8750 operand_string
, kind
);
8755 if (addr_mode
!= CODE_16BIT
)
8757 /* 32-bit/64-bit checks. */
8759 && (addr_mode
== CODE_64BIT
8760 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8761 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8763 || (i
.base_reg
->reg_num
8764 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8766 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8767 && !i
.index_reg
->reg_type
.bitfield
.regymm
8768 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8769 && ((addr_mode
== CODE_64BIT
8770 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8771 || i
.index_reg
->reg_num
== RegRiz
)
8772 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8773 || i
.index_reg
->reg_num
== RegEiz
))
8774 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8777 /* bndmk, bndldx, and bndstx have special restrictions. */
8778 if (current_templates
->start
->base_opcode
== 0xf30f1b
8779 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8781 /* They cannot use RIP-relative addressing. */
8782 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8784 as_bad (_("`%s' cannot be used here"), operand_string
);
8788 /* bndldx and bndstx ignore their scale factor. */
8789 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8790 && i
.log2_scale_factor
)
8791 as_warn (_("register scaling is being ignored here"));
8796 /* 16-bit checks. */
8798 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8799 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8801 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8802 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8804 && i
.base_reg
->reg_num
< 6
8805 && i
.index_reg
->reg_num
>= 6
8806 && i
.log2_scale_factor
== 0))))
8813 /* Handle vector immediates. */
8816 RC_SAE_immediate (const char *imm_start
)
8818 unsigned int match_found
, j
;
8819 const char *pstr
= imm_start
;
8827 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8829 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8833 rc_op
.type
= RC_NamesTable
[j
].type
;
8834 rc_op
.operand
= this_operand
;
8835 i
.rounding
= &rc_op
;
8839 as_bad (_("duplicated `%s'"), imm_start
);
8842 pstr
+= RC_NamesTable
[j
].len
;
8852 as_bad (_("Missing '}': '%s'"), imm_start
);
8855 /* RC/SAE immediate string should contain nothing more. */;
8858 as_bad (_("Junk after '}': '%s'"), imm_start
);
8862 exp
= &im_expressions
[i
.imm_operands
++];
8863 i
.op
[this_operand
].imms
= exp
;
8865 exp
->X_op
= O_constant
;
8866 exp
->X_add_number
= 0;
8867 exp
->X_add_symbol
= (symbolS
*) 0;
8868 exp
->X_op_symbol
= (symbolS
*) 0;
8870 i
.types
[this_operand
].bitfield
.imm8
= 1;
8874 /* Only string instructions can have a second memory operand, so
8875 reduce current_templates to just those if it contains any. */
8877 maybe_adjust_templates (void)
8879 const insn_template
*t
;
8881 gas_assert (i
.mem_operands
== 1);
8883 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8884 if (t
->opcode_modifier
.isstring
)
8887 if (t
< current_templates
->end
)
8889 static templates aux_templates
;
8890 bfd_boolean recheck
;
8892 aux_templates
.start
= t
;
8893 for (; t
< current_templates
->end
; ++t
)
8894 if (!t
->opcode_modifier
.isstring
)
8896 aux_templates
.end
= t
;
8898 /* Determine whether to re-check the first memory operand. */
8899 recheck
= (aux_templates
.start
!= current_templates
->start
8900 || t
!= current_templates
->end
);
8902 current_templates
= &aux_templates
;
8907 if (i
.memop1_string
!= NULL
8908 && i386_index_check (i
.memop1_string
) == 0)
8917 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8921 i386_att_operand (char *operand_string
)
8925 char *op_string
= operand_string
;
8927 if (is_space_char (*op_string
))
8930 /* We check for an absolute prefix (differentiating,
8931 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8932 if (*op_string
== ABSOLUTE_PREFIX
)
8935 if (is_space_char (*op_string
))
8937 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8940 /* Check if operand is a register. */
8941 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8943 i386_operand_type temp
;
8945 /* Check for a segment override by searching for ':' after a
8946 segment register. */
8948 if (is_space_char (*op_string
))
8950 if (*op_string
== ':'
8951 && (r
->reg_type
.bitfield
.sreg2
8952 || r
->reg_type
.bitfield
.sreg3
))
8957 i
.seg
[i
.mem_operands
] = &es
;
8960 i
.seg
[i
.mem_operands
] = &cs
;
8963 i
.seg
[i
.mem_operands
] = &ss
;
8966 i
.seg
[i
.mem_operands
] = &ds
;
8969 i
.seg
[i
.mem_operands
] = &fs
;
8972 i
.seg
[i
.mem_operands
] = &gs
;
8976 /* Skip the ':' and whitespace. */
8978 if (is_space_char (*op_string
))
8981 if (!is_digit_char (*op_string
)
8982 && !is_identifier_char (*op_string
)
8983 && *op_string
!= '('
8984 && *op_string
!= ABSOLUTE_PREFIX
)
8986 as_bad (_("bad memory operand `%s'"), op_string
);
8989 /* Handle case of %es:*foo. */
8990 if (*op_string
== ABSOLUTE_PREFIX
)
8993 if (is_space_char (*op_string
))
8995 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8997 goto do_memory_reference
;
9000 /* Handle vector operations. */
9001 if (*op_string
== '{')
9003 op_string
= check_VecOperations (op_string
, NULL
);
9004 if (op_string
== NULL
)
9010 as_bad (_("junk `%s' after register"), op_string
);
9014 temp
.bitfield
.baseindex
= 0;
9015 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9017 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9018 i
.op
[this_operand
].regs
= r
;
9021 else if (*op_string
== REGISTER_PREFIX
)
9023 as_bad (_("bad register name `%s'"), op_string
);
9026 else if (*op_string
== IMMEDIATE_PREFIX
)
9029 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9031 as_bad (_("immediate operand illegal with absolute jump"));
9034 if (!i386_immediate (op_string
))
9037 else if (RC_SAE_immediate (operand_string
))
9039 /* If it is a RC or SAE immediate, do nothing. */
9042 else if (is_digit_char (*op_string
)
9043 || is_identifier_char (*op_string
)
9044 || *op_string
== '"'
9045 || *op_string
== '(')
9047 /* This is a memory reference of some sort. */
9050 /* Start and end of displacement string expression (if found). */
9051 char *displacement_string_start
;
9052 char *displacement_string_end
;
9055 do_memory_reference
:
9056 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9058 if ((i
.mem_operands
== 1
9059 && !current_templates
->start
->opcode_modifier
.isstring
)
9060 || i
.mem_operands
== 2)
9062 as_bad (_("too many memory references for `%s'"),
9063 current_templates
->start
->name
);
9067 /* Check for base index form. We detect the base index form by
9068 looking for an ')' at the end of the operand, searching
9069 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9071 base_string
= op_string
+ strlen (op_string
);
9073 /* Handle vector operations. */
9074 vop_start
= strchr (op_string
, '{');
9075 if (vop_start
&& vop_start
< base_string
)
9077 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9079 base_string
= vop_start
;
9083 if (is_space_char (*base_string
))
9086 /* If we only have a displacement, set-up for it to be parsed later. */
9087 displacement_string_start
= op_string
;
9088 displacement_string_end
= base_string
+ 1;
9090 if (*base_string
== ')')
9093 unsigned int parens_balanced
= 1;
9094 /* We've already checked that the number of left & right ()'s are
9095 equal, so this loop will not be infinite. */
9099 if (*base_string
== ')')
9101 if (*base_string
== '(')
9104 while (parens_balanced
);
9106 temp_string
= base_string
;
9108 /* Skip past '(' and whitespace. */
9110 if (is_space_char (*base_string
))
9113 if (*base_string
== ','
9114 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9117 displacement_string_end
= temp_string
;
9119 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9123 base_string
= end_op
;
9124 if (is_space_char (*base_string
))
9128 /* There may be an index reg or scale factor here. */
9129 if (*base_string
== ',')
9132 if (is_space_char (*base_string
))
9135 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9138 base_string
= end_op
;
9139 if (is_space_char (*base_string
))
9141 if (*base_string
== ',')
9144 if (is_space_char (*base_string
))
9147 else if (*base_string
!= ')')
9149 as_bad (_("expecting `,' or `)' "
9150 "after index register in `%s'"),
9155 else if (*base_string
== REGISTER_PREFIX
)
9157 end_op
= strchr (base_string
, ',');
9160 as_bad (_("bad register name `%s'"), base_string
);
9164 /* Check for scale factor. */
9165 if (*base_string
!= ')')
9167 char *end_scale
= i386_scale (base_string
);
9172 base_string
= end_scale
;
9173 if (is_space_char (*base_string
))
9175 if (*base_string
!= ')')
9177 as_bad (_("expecting `)' "
9178 "after scale factor in `%s'"),
9183 else if (!i
.index_reg
)
9185 as_bad (_("expecting index register or scale factor "
9186 "after `,'; got '%c'"),
9191 else if (*base_string
!= ')')
9193 as_bad (_("expecting `,' or `)' "
9194 "after base register in `%s'"),
9199 else if (*base_string
== REGISTER_PREFIX
)
9201 end_op
= strchr (base_string
, ',');
9204 as_bad (_("bad register name `%s'"), base_string
);
9209 /* If there's an expression beginning the operand, parse it,
9210 assuming displacement_string_start and
9211 displacement_string_end are meaningful. */
9212 if (displacement_string_start
!= displacement_string_end
)
9214 if (!i386_displacement (displacement_string_start
,
9215 displacement_string_end
))
9219 /* Special case for (%dx) while doing input/output op. */
9221 && operand_type_equal (&i
.base_reg
->reg_type
,
9222 ®16_inoutportreg
)
9224 && i
.log2_scale_factor
== 0
9225 && i
.seg
[i
.mem_operands
] == 0
9226 && !operand_type_check (i
.types
[this_operand
], disp
))
9228 i
.types
[this_operand
] = inoutportreg
;
9232 if (i386_index_check (operand_string
) == 0)
9234 i
.types
[this_operand
].bitfield
.mem
= 1;
9235 if (i
.mem_operands
== 0)
9236 i
.memop1_string
= xstrdup (operand_string
);
9241 /* It's not a memory operand; argh! */
9242 as_bad (_("invalid char %s beginning operand %d `%s'"),
9243 output_invalid (*op_string
),
9248 return 1; /* Normal return. */
9251 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9252 that an rs_machine_dependent frag may reach. */
9255 i386_frag_max_var (fragS
*frag
)
9257 /* The only relaxable frags are for jumps.
9258 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9259 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9260 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9263 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9265 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9267 /* STT_GNU_IFUNC symbol must go through PLT. */
9268 if ((symbol_get_bfdsym (fr_symbol
)->flags
9269 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9272 if (!S_IS_EXTERNAL (fr_symbol
))
9273 /* Symbol may be weak or local. */
9274 return !S_IS_WEAK (fr_symbol
);
9276 /* Global symbols with non-default visibility can't be preempted. */
9277 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9280 if (fr_var
!= NO_RELOC
)
9281 switch ((enum bfd_reloc_code_real
) fr_var
)
9283 case BFD_RELOC_386_PLT32
:
9284 case BFD_RELOC_X86_64_PLT32
:
9285 /* Symbol with PLT relocation may be preempted. */
9291 /* Global symbols with default visibility in a shared library may be
9292 preempted by another definition. */
9297 /* md_estimate_size_before_relax()
9299 Called just before relax() for rs_machine_dependent frags. The x86
9300 assembler uses these frags to handle variable size jump
9303 Any symbol that is now undefined will not become defined.
9304 Return the correct fr_subtype in the frag.
9305 Return the initial "guess for variable size of frag" to caller.
9306 The guess is actually the growth beyond the fixed part. Whatever
9307 we do to grow the fixed or variable part contributes to our
9311 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9313 /* We've already got fragP->fr_subtype right; all we have to do is
9314 check for un-relaxable symbols. On an ELF system, we can't relax
9315 an externally visible symbol, because it may be overridden by a
9317 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9320 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9323 #if defined (OBJ_COFF) && defined (TE_PE)
9324 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9325 && S_IS_WEAK (fragP
->fr_symbol
))
9329 /* Symbol is undefined in this segment, or we need to keep a
9330 reloc so that weak symbols can be overridden. */
9331 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9332 enum bfd_reloc_code_real reloc_type
;
9333 unsigned char *opcode
;
9336 if (fragP
->fr_var
!= NO_RELOC
)
9337 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9339 reloc_type
= BFD_RELOC_16_PCREL
;
9341 reloc_type
= BFD_RELOC_32_PCREL
;
9343 old_fr_fix
= fragP
->fr_fix
;
9344 opcode
= (unsigned char *) fragP
->fr_opcode
;
9346 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9349 /* Make jmp (0xeb) a (d)word displacement jump. */
9351 fragP
->fr_fix
+= size
;
9352 fix_new (fragP
, old_fr_fix
, size
,
9354 fragP
->fr_offset
, 1,
9360 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9362 /* Negate the condition, and branch past an
9363 unconditional jump. */
9366 /* Insert an unconditional jump. */
9368 /* We added two extra opcode bytes, and have a two byte
9370 fragP
->fr_fix
+= 2 + 2;
9371 fix_new (fragP
, old_fr_fix
+ 2, 2,
9373 fragP
->fr_offset
, 1,
9380 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9385 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9387 fragP
->fr_offset
, 1,
9389 fixP
->fx_signed
= 1;
9393 /* This changes the byte-displacement jump 0x7N
9394 to the (d)word-displacement jump 0x0f,0x8N. */
9395 opcode
[1] = opcode
[0] + 0x10;
9396 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9397 /* We've added an opcode byte. */
9398 fragP
->fr_fix
+= 1 + size
;
9399 fix_new (fragP
, old_fr_fix
+ 1, size
,
9401 fragP
->fr_offset
, 1,
9406 BAD_CASE (fragP
->fr_subtype
);
9410 return fragP
->fr_fix
- old_fr_fix
;
9413 /* Guess size depending on current relax state. Initially the relax
9414 state will correspond to a short jump and we return 1, because
9415 the variable part of the frag (the branch offset) is one byte
9416 long. However, we can relax a section more than once and in that
9417 case we must either set fr_subtype back to the unrelaxed state,
9418 or return the value for the appropriate branch. */
9419 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9422 /* Called after relax() is finished.
9424 In: Address of frag.
9425 fr_type == rs_machine_dependent.
9426 fr_subtype is what the address relaxed to.
9428 Out: Any fixSs and constants are set up.
9429 Caller will turn frag into a ".space 0". */
9432 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9435 unsigned char *opcode
;
9436 unsigned char *where_to_put_displacement
= NULL
;
9437 offsetT target_address
;
9438 offsetT opcode_address
;
9439 unsigned int extension
= 0;
9440 offsetT displacement_from_opcode_start
;
9442 opcode
= (unsigned char *) fragP
->fr_opcode
;
9444 /* Address we want to reach in file space. */
9445 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9447 /* Address opcode resides at in file space. */
9448 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9450 /* Displacement from opcode start to fill into instruction. */
9451 displacement_from_opcode_start
= target_address
- opcode_address
;
9453 if ((fragP
->fr_subtype
& BIG
) == 0)
9455 /* Don't have to change opcode. */
9456 extension
= 1; /* 1 opcode + 1 displacement */
9457 where_to_put_displacement
= &opcode
[1];
9461 if (no_cond_jump_promotion
9462 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9463 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9464 _("long jump required"));
9466 switch (fragP
->fr_subtype
)
9468 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9469 extension
= 4; /* 1 opcode + 4 displacement */
9471 where_to_put_displacement
= &opcode
[1];
9474 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9475 extension
= 2; /* 1 opcode + 2 displacement */
9477 where_to_put_displacement
= &opcode
[1];
9480 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9481 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9482 extension
= 5; /* 2 opcode + 4 displacement */
9483 opcode
[1] = opcode
[0] + 0x10;
9484 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9485 where_to_put_displacement
= &opcode
[2];
9488 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9489 extension
= 3; /* 2 opcode + 2 displacement */
9490 opcode
[1] = opcode
[0] + 0x10;
9491 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9492 where_to_put_displacement
= &opcode
[2];
9495 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9500 where_to_put_displacement
= &opcode
[3];
9504 BAD_CASE (fragP
->fr_subtype
);
9509 /* If size if less then four we are sure that the operand fits,
9510 but if it's 4, then it could be that the displacement is larger
9512 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9514 && ((addressT
) (displacement_from_opcode_start
- extension
9515 + ((addressT
) 1 << 31))
9516 > (((addressT
) 2 << 31) - 1)))
9518 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9519 _("jump target out of range"));
9520 /* Make us emit 0. */
9521 displacement_from_opcode_start
= extension
;
9523 /* Now put displacement after opcode. */
9524 md_number_to_chars ((char *) where_to_put_displacement
,
9525 (valueT
) (displacement_from_opcode_start
- extension
),
9526 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9527 fragP
->fr_fix
+= extension
;
9530 /* Apply a fixup (fixP) to segment data, once it has been determined
9531 by our caller that we have all the info we need to fix it up.
9533 Parameter valP is the pointer to the value of the bits.
9535 On the 386, immediates, displacements, and data pointers are all in
9536 the same (little-endian) format, so we don't need to care about which
9540 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9542 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9543 valueT value
= *valP
;
9545 #if !defined (TE_Mach)
9548 switch (fixP
->fx_r_type
)
9554 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9557 case BFD_RELOC_X86_64_32S
:
9558 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9561 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9564 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9569 if (fixP
->fx_addsy
!= NULL
9570 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9571 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9572 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9573 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9574 && !use_rela_relocations
)
9576 /* This is a hack. There should be a better way to handle this.
9577 This covers for the fact that bfd_install_relocation will
9578 subtract the current location (for partial_inplace, PC relative
9579 relocations); see more below. */
9583 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9586 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9588 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9591 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9594 || (symbol_section_p (fixP
->fx_addsy
)
9595 && sym_seg
!= absolute_section
))
9596 && !generic_force_reloc (fixP
))
9598 /* Yes, we add the values in twice. This is because
9599 bfd_install_relocation subtracts them out again. I think
9600 bfd_install_relocation is broken, but I don't dare change
9602 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9606 #if defined (OBJ_COFF) && defined (TE_PE)
9607 /* For some reason, the PE format does not store a
9608 section address offset for a PC relative symbol. */
9609 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9610 || S_IS_WEAK (fixP
->fx_addsy
))
9611 value
+= md_pcrel_from (fixP
);
9614 #if defined (OBJ_COFF) && defined (TE_PE)
9615 if (fixP
->fx_addsy
!= NULL
9616 && S_IS_WEAK (fixP
->fx_addsy
)
9617 /* PR 16858: Do not modify weak function references. */
9618 && ! fixP
->fx_pcrel
)
9620 #if !defined (TE_PEP)
9621 /* For x86 PE weak function symbols are neither PC-relative
9622 nor do they set S_IS_FUNCTION. So the only reliable way
9623 to detect them is to check the flags of their containing
9625 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9626 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9630 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9634 /* Fix a few things - the dynamic linker expects certain values here,
9635 and we must not disappoint it. */
9636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9637 if (IS_ELF
&& fixP
->fx_addsy
)
9638 switch (fixP
->fx_r_type
)
9640 case BFD_RELOC_386_PLT32
:
9641 case BFD_RELOC_X86_64_PLT32
:
9642 /* Make the jump instruction point to the address of the operand. At
9643 runtime we merely add the offset to the actual PLT entry. */
9647 case BFD_RELOC_386_TLS_GD
:
9648 case BFD_RELOC_386_TLS_LDM
:
9649 case BFD_RELOC_386_TLS_IE_32
:
9650 case BFD_RELOC_386_TLS_IE
:
9651 case BFD_RELOC_386_TLS_GOTIE
:
9652 case BFD_RELOC_386_TLS_GOTDESC
:
9653 case BFD_RELOC_X86_64_TLSGD
:
9654 case BFD_RELOC_X86_64_TLSLD
:
9655 case BFD_RELOC_X86_64_GOTTPOFF
:
9656 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9657 value
= 0; /* Fully resolved at runtime. No addend. */
9659 case BFD_RELOC_386_TLS_LE
:
9660 case BFD_RELOC_386_TLS_LDO_32
:
9661 case BFD_RELOC_386_TLS_LE_32
:
9662 case BFD_RELOC_X86_64_DTPOFF32
:
9663 case BFD_RELOC_X86_64_DTPOFF64
:
9664 case BFD_RELOC_X86_64_TPOFF32
:
9665 case BFD_RELOC_X86_64_TPOFF64
:
9666 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9669 case BFD_RELOC_386_TLS_DESC_CALL
:
9670 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9671 value
= 0; /* Fully resolved at runtime. No addend. */
9672 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9676 case BFD_RELOC_VTABLE_INHERIT
:
9677 case BFD_RELOC_VTABLE_ENTRY
:
9684 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9686 #endif /* !defined (TE_Mach) */
9688 /* Are we finished with this relocation now? */
9689 if (fixP
->fx_addsy
== NULL
)
9691 #if defined (OBJ_COFF) && defined (TE_PE)
9692 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9695 /* Remember value for tc_gen_reloc. */
9696 fixP
->fx_addnumber
= value
;
9697 /* Clear out the frag for now. */
9701 else if (use_rela_relocations
)
9703 fixP
->fx_no_overflow
= 1;
9704 /* Remember value for tc_gen_reloc. */
9705 fixP
->fx_addnumber
= value
;
9709 md_number_to_chars (p
, value
, fixP
->fx_size
);
9713 md_atof (int type
, char *litP
, int *sizeP
)
9715 /* This outputs the LITTLENUMs in REVERSE order;
9716 in accord with the bigendian 386. */
9717 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9720 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9723 output_invalid (int c
)
9726 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9729 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9730 "(0x%x)", (unsigned char) c
);
9731 return output_invalid_buf
;
9734 /* REG_STRING starts *before* REGISTER_PREFIX. */
9736 static const reg_entry
*
9737 parse_real_register (char *reg_string
, char **end_op
)
9739 char *s
= reg_string
;
9741 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9744 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9745 if (*s
== REGISTER_PREFIX
)
9748 if (is_space_char (*s
))
9752 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9754 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9755 return (const reg_entry
*) NULL
;
9759 /* For naked regs, make sure that we are not dealing with an identifier.
9760 This prevents confusing an identifier like `eax_var' with register
9762 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9763 return (const reg_entry
*) NULL
;
9767 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9769 /* Handle floating point regs, allowing spaces in the (i) part. */
9770 if (r
== i386_regtab
/* %st is first entry of table */)
9772 if (is_space_char (*s
))
9777 if (is_space_char (*s
))
9779 if (*s
>= '0' && *s
<= '7')
9783 if (is_space_char (*s
))
9788 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9793 /* We have "%st(" then garbage. */
9794 return (const reg_entry
*) NULL
;
9798 if (r
== NULL
|| allow_pseudo_reg
)
9801 if (operand_type_all_zero (&r
->reg_type
))
9802 return (const reg_entry
*) NULL
;
9804 if ((r
->reg_type
.bitfield
.reg32
9805 || r
->reg_type
.bitfield
.sreg3
9806 || r
->reg_type
.bitfield
.control
9807 || r
->reg_type
.bitfield
.debug
9808 || r
->reg_type
.bitfield
.test
)
9809 && !cpu_arch_flags
.bitfield
.cpui386
)
9810 return (const reg_entry
*) NULL
;
9812 if (r
->reg_type
.bitfield
.floatreg
9813 && !cpu_arch_flags
.bitfield
.cpu8087
9814 && !cpu_arch_flags
.bitfield
.cpu287
9815 && !cpu_arch_flags
.bitfield
.cpu387
)
9816 return (const reg_entry
*) NULL
;
9818 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9819 return (const reg_entry
*) NULL
;
9821 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9822 return (const reg_entry
*) NULL
;
9824 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9825 return (const reg_entry
*) NULL
;
9827 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9828 return (const reg_entry
*) NULL
;
9830 if (r
->reg_type
.bitfield
.regmask
9831 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9832 return (const reg_entry
*) NULL
;
9834 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9835 if (!allow_index_reg
9836 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9837 return (const reg_entry
*) NULL
;
9839 /* Upper 16 vector register is only available with VREX in 64bit
9841 if ((r
->reg_flags
& RegVRex
))
9843 if (i
.vec_encoding
== vex_encoding_default
)
9844 i
.vec_encoding
= vex_encoding_evex
;
9846 if (!cpu_arch_flags
.bitfield
.cpuvrex
9847 || i
.vec_encoding
!= vex_encoding_evex
9848 || flag_code
!= CODE_64BIT
)
9849 return (const reg_entry
*) NULL
;
9852 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9853 || r
->reg_type
.bitfield
.reg64
)
9854 && (!cpu_arch_flags
.bitfield
.cpulm
9855 || !operand_type_equal (&r
->reg_type
, &control
))
9856 && flag_code
!= CODE_64BIT
)
9857 return (const reg_entry
*) NULL
;
9859 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9860 return (const reg_entry
*) NULL
;
9865 /* REG_STRING starts *before* REGISTER_PREFIX. */
9867 static const reg_entry
*
9868 parse_register (char *reg_string
, char **end_op
)
9872 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9873 r
= parse_real_register (reg_string
, end_op
);
9878 char *save
= input_line_pointer
;
9882 input_line_pointer
= reg_string
;
9883 c
= get_symbol_name (®_string
);
9884 symbolP
= symbol_find (reg_string
);
9885 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9887 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9889 know (e
->X_op
== O_register
);
9890 know (e
->X_add_number
>= 0
9891 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9892 r
= i386_regtab
+ e
->X_add_number
;
9893 if ((r
->reg_flags
& RegVRex
))
9894 i
.vec_encoding
= vex_encoding_evex
;
9895 *end_op
= input_line_pointer
;
9897 *input_line_pointer
= c
;
9898 input_line_pointer
= save
;
9904 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9907 char *end
= input_line_pointer
;
9910 r
= parse_register (name
, &input_line_pointer
);
9911 if (r
&& end
<= input_line_pointer
)
9913 *nextcharP
= *input_line_pointer
;
9914 *input_line_pointer
= 0;
9915 e
->X_op
= O_register
;
9916 e
->X_add_number
= r
- i386_regtab
;
9919 input_line_pointer
= end
;
9921 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9925 md_operand (expressionS
*e
)
9930 switch (*input_line_pointer
)
9932 case REGISTER_PREFIX
:
9933 r
= parse_real_register (input_line_pointer
, &end
);
9936 e
->X_op
= O_register
;
9937 e
->X_add_number
= r
- i386_regtab
;
9938 input_line_pointer
= end
;
9943 gas_assert (intel_syntax
);
9944 end
= input_line_pointer
++;
9946 if (*input_line_pointer
== ']')
9948 ++input_line_pointer
;
9949 e
->X_op_symbol
= make_expr_symbol (e
);
9950 e
->X_add_symbol
= NULL
;
9951 e
->X_add_number
= 0;
9957 input_line_pointer
= end
;
9964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9965 const char *md_shortopts
= "kVQ:sqn";
9967 const char *md_shortopts
= "qn";
9970 #define OPTION_32 (OPTION_MD_BASE + 0)
9971 #define OPTION_64 (OPTION_MD_BASE + 1)
9972 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9973 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9974 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9975 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9976 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9977 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9978 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9979 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9980 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9981 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9982 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9983 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9984 #define OPTION_X32 (OPTION_MD_BASE + 14)
9985 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9986 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9987 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9988 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9989 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9990 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9991 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9992 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9993 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9994 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9995 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9997 struct option md_longopts
[] =
9999 {"32", no_argument
, NULL
, OPTION_32
},
10000 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10001 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10002 {"64", no_argument
, NULL
, OPTION_64
},
10004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10005 {"x32", no_argument
, NULL
, OPTION_X32
},
10006 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10008 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10009 {"march", required_argument
, NULL
, OPTION_MARCH
},
10010 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10011 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10012 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10013 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10014 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10015 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
10016 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10017 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10018 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10019 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10020 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10021 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10022 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10023 # if defined (TE_PE) || defined (TE_PEP)
10024 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10026 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10027 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10028 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10029 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10030 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10031 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10032 {NULL
, no_argument
, NULL
, 0}
10034 size_t md_longopts_size
= sizeof (md_longopts
);
10037 md_parse_option (int c
, const char *arg
)
10040 char *arch
, *next
, *saved
;
10045 optimize_align_code
= 0;
10049 quiet_warnings
= 1;
10052 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10053 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10054 should be emitted or not. FIXME: Not implemented. */
10058 /* -V: SVR4 argument to print version ID. */
10060 print_version_id ();
10063 /* -k: Ignore for FreeBSD compatibility. */
10068 /* -s: On i386 Solaris, this tells the native assembler to use
10069 .stab instead of .stab.excl. We always use .stab anyhow. */
10072 case OPTION_MSHARED
:
10076 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10077 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10080 const char **list
, **l
;
10082 list
= bfd_target_list ();
10083 for (l
= list
; *l
!= NULL
; l
++)
10084 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10085 || strcmp (*l
, "coff-x86-64") == 0
10086 || strcmp (*l
, "pe-x86-64") == 0
10087 || strcmp (*l
, "pei-x86-64") == 0
10088 || strcmp (*l
, "mach-o-x86-64") == 0)
10090 default_arch
= "x86_64";
10094 as_fatal (_("no compiled in support for x86_64"));
10100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10104 const char **list
, **l
;
10106 list
= bfd_target_list ();
10107 for (l
= list
; *l
!= NULL
; l
++)
10108 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10110 default_arch
= "x86_64:32";
10114 as_fatal (_("no compiled in support for 32bit x86_64"));
10118 as_fatal (_("32bit x86_64 is only supported for ELF"));
10123 default_arch
= "i386";
10126 case OPTION_DIVIDE
:
10127 #ifdef SVR4_COMMENT_CHARS
10132 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10134 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10138 i386_comment_chars
= n
;
10144 saved
= xstrdup (arg
);
10146 /* Allow -march=+nosse. */
10152 as_fatal (_("invalid -march= option: `%s'"), arg
);
10153 next
= strchr (arch
, '+');
10156 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10158 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10161 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10164 cpu_arch_name
= cpu_arch
[j
].name
;
10165 cpu_sub_arch_name
= NULL
;
10166 cpu_arch_flags
= cpu_arch
[j
].flags
;
10167 cpu_arch_isa
= cpu_arch
[j
].type
;
10168 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10169 if (!cpu_arch_tune_set
)
10171 cpu_arch_tune
= cpu_arch_isa
;
10172 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10176 else if (*cpu_arch
[j
].name
== '.'
10177 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10179 /* ISA extension. */
10180 i386_cpu_flags flags
;
10182 flags
= cpu_flags_or (cpu_arch_flags
,
10183 cpu_arch
[j
].flags
);
10185 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10187 if (cpu_sub_arch_name
)
10189 char *name
= cpu_sub_arch_name
;
10190 cpu_sub_arch_name
= concat (name
,
10192 (const char *) NULL
);
10196 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10197 cpu_arch_flags
= flags
;
10198 cpu_arch_isa_flags
= flags
;
10204 if (j
>= ARRAY_SIZE (cpu_arch
))
10206 /* Disable an ISA extension. */
10207 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10208 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10210 i386_cpu_flags flags
;
10212 flags
= cpu_flags_and_not (cpu_arch_flags
,
10213 cpu_noarch
[j
].flags
);
10214 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10216 if (cpu_sub_arch_name
)
10218 char *name
= cpu_sub_arch_name
;
10219 cpu_sub_arch_name
= concat (arch
,
10220 (const char *) NULL
);
10224 cpu_sub_arch_name
= xstrdup (arch
);
10225 cpu_arch_flags
= flags
;
10226 cpu_arch_isa_flags
= flags
;
10231 if (j
>= ARRAY_SIZE (cpu_noarch
))
10232 j
= ARRAY_SIZE (cpu_arch
);
10235 if (j
>= ARRAY_SIZE (cpu_arch
))
10236 as_fatal (_("invalid -march= option: `%s'"), arg
);
10240 while (next
!= NULL
);
10246 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10247 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10249 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10251 cpu_arch_tune_set
= 1;
10252 cpu_arch_tune
= cpu_arch
[j
].type
;
10253 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10257 if (j
>= ARRAY_SIZE (cpu_arch
))
10258 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10261 case OPTION_MMNEMONIC
:
10262 if (strcasecmp (arg
, "att") == 0)
10263 intel_mnemonic
= 0;
10264 else if (strcasecmp (arg
, "intel") == 0)
10265 intel_mnemonic
= 1;
10267 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10270 case OPTION_MSYNTAX
:
10271 if (strcasecmp (arg
, "att") == 0)
10273 else if (strcasecmp (arg
, "intel") == 0)
10276 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10279 case OPTION_MINDEX_REG
:
10280 allow_index_reg
= 1;
10283 case OPTION_MNAKED_REG
:
10284 allow_naked_reg
= 1;
10287 case OPTION_MOLD_GCC
:
10291 case OPTION_MSSE2AVX
:
10295 case OPTION_MSSE_CHECK
:
10296 if (strcasecmp (arg
, "error") == 0)
10297 sse_check
= check_error
;
10298 else if (strcasecmp (arg
, "warning") == 0)
10299 sse_check
= check_warning
;
10300 else if (strcasecmp (arg
, "none") == 0)
10301 sse_check
= check_none
;
10303 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10306 case OPTION_MOPERAND_CHECK
:
10307 if (strcasecmp (arg
, "error") == 0)
10308 operand_check
= check_error
;
10309 else if (strcasecmp (arg
, "warning") == 0)
10310 operand_check
= check_warning
;
10311 else if (strcasecmp (arg
, "none") == 0)
10312 operand_check
= check_none
;
10314 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10317 case OPTION_MAVXSCALAR
:
10318 if (strcasecmp (arg
, "128") == 0)
10319 avxscalar
= vex128
;
10320 else if (strcasecmp (arg
, "256") == 0)
10321 avxscalar
= vex256
;
10323 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10326 case OPTION_MADD_BND_PREFIX
:
10327 add_bnd_prefix
= 1;
10330 case OPTION_MEVEXLIG
:
10331 if (strcmp (arg
, "128") == 0)
10332 evexlig
= evexl128
;
10333 else if (strcmp (arg
, "256") == 0)
10334 evexlig
= evexl256
;
10335 else if (strcmp (arg
, "512") == 0)
10336 evexlig
= evexl512
;
10338 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10341 case OPTION_MEVEXRCIG
:
10342 if (strcmp (arg
, "rne") == 0)
10344 else if (strcmp (arg
, "rd") == 0)
10346 else if (strcmp (arg
, "ru") == 0)
10348 else if (strcmp (arg
, "rz") == 0)
10351 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10354 case OPTION_MEVEXWIG
:
10355 if (strcmp (arg
, "0") == 0)
10357 else if (strcmp (arg
, "1") == 0)
10360 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10363 # if defined (TE_PE) || defined (TE_PEP)
10364 case OPTION_MBIG_OBJ
:
10369 case OPTION_MOMIT_LOCK_PREFIX
:
10370 if (strcasecmp (arg
, "yes") == 0)
10371 omit_lock_prefix
= 1;
10372 else if (strcasecmp (arg
, "no") == 0)
10373 omit_lock_prefix
= 0;
10375 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10378 case OPTION_MFENCE_AS_LOCK_ADD
:
10379 if (strcasecmp (arg
, "yes") == 0)
10381 else if (strcasecmp (arg
, "no") == 0)
10384 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10387 case OPTION_MRELAX_RELOCATIONS
:
10388 if (strcasecmp (arg
, "yes") == 0)
10389 generate_relax_relocations
= 1;
10390 else if (strcasecmp (arg
, "no") == 0)
10391 generate_relax_relocations
= 0;
10393 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10396 case OPTION_MAMD64
:
10400 case OPTION_MINTEL64
:
10410 #define MESSAGE_TEMPLATE \
10414 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10415 int *left_p
, const char *name
, int len
)
10417 int size
= sizeof (MESSAGE_TEMPLATE
);
10418 int left
= *left_p
;
10420 /* Reserve 2 spaces for ", " or ",\0" */
10423 /* Check if there is any room. */
10431 p
= mempcpy (p
, name
, len
);
10435 /* Output the current message now and start a new one. */
10438 fprintf (stream
, "%s\n", message
);
10440 left
= size
- (start
- message
) - len
- 2;
10442 gas_assert (left
>= 0);
10444 p
= mempcpy (p
, name
, len
);
10452 show_arch (FILE *stream
, int ext
, int check
)
10454 static char message
[] = MESSAGE_TEMPLATE
;
10455 char *start
= message
+ 27;
10457 int size
= sizeof (MESSAGE_TEMPLATE
);
10464 left
= size
- (start
- message
);
10465 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10467 /* Should it be skipped? */
10468 if (cpu_arch
[j
].skip
)
10471 name
= cpu_arch
[j
].name
;
10472 len
= cpu_arch
[j
].len
;
10475 /* It is an extension. Skip if we aren't asked to show it. */
10486 /* It is an processor. Skip if we show only extension. */
10489 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10491 /* It is an impossible processor - skip. */
10495 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10498 /* Display disabled extensions. */
10500 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10502 name
= cpu_noarch
[j
].name
;
10503 len
= cpu_noarch
[j
].len
;
10504 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10509 fprintf (stream
, "%s\n", message
);
10513 md_show_usage (FILE *stream
)
10515 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10516 fprintf (stream
, _("\
10518 -V print assembler version number\n\
10521 fprintf (stream
, _("\
10522 -n Do not optimize code alignment\n\
10523 -q quieten some warnings\n"));
10524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10525 fprintf (stream
, _("\
10528 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10529 || defined (TE_PE) || defined (TE_PEP))
10530 fprintf (stream
, _("\
10531 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10533 #ifdef SVR4_COMMENT_CHARS
10534 fprintf (stream
, _("\
10535 --divide do not treat `/' as a comment character\n"));
10537 fprintf (stream
, _("\
10538 --divide ignored\n"));
10540 fprintf (stream
, _("\
10541 -march=CPU[,+EXTENSION...]\n\
10542 generate code for CPU and EXTENSION, CPU is one of:\n"));
10543 show_arch (stream
, 0, 1);
10544 fprintf (stream
, _("\
10545 EXTENSION is combination of:\n"));
10546 show_arch (stream
, 1, 0);
10547 fprintf (stream
, _("\
10548 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10549 show_arch (stream
, 0, 0);
10550 fprintf (stream
, _("\
10551 -msse2avx encode SSE instructions with VEX prefix\n"));
10552 fprintf (stream
, _("\
10553 -msse-check=[none|error|warning]\n\
10554 check SSE instructions\n"));
10555 fprintf (stream
, _("\
10556 -moperand-check=[none|error|warning]\n\
10557 check operand combinations for validity\n"));
10558 fprintf (stream
, _("\
10559 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10561 fprintf (stream
, _("\
10562 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10564 fprintf (stream
, _("\
10565 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10566 for EVEX.W bit ignored instructions\n"));
10567 fprintf (stream
, _("\
10568 -mevexrcig=[rne|rd|ru|rz]\n\
10569 encode EVEX instructions with specific EVEX.RC value\n\
10570 for SAE-only ignored instructions\n"));
10571 fprintf (stream
, _("\
10572 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10573 fprintf (stream
, _("\
10574 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10575 fprintf (stream
, _("\
10576 -mindex-reg support pseudo index registers\n"));
10577 fprintf (stream
, _("\
10578 -mnaked-reg don't require `%%' prefix for registers\n"));
10579 fprintf (stream
, _("\
10580 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10581 fprintf (stream
, _("\
10582 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10583 fprintf (stream
, _("\
10584 -mshared disable branch optimization for shared code\n"));
10585 # if defined (TE_PE) || defined (TE_PEP)
10586 fprintf (stream
, _("\
10587 -mbig-obj generate big object files\n"));
10589 fprintf (stream
, _("\
10590 -momit-lock-prefix=[no|yes]\n\
10591 strip all lock prefixes\n"));
10592 fprintf (stream
, _("\
10593 -mfence-as-lock-add=[no|yes]\n\
10594 encode lfence, mfence and sfence as\n\
10595 lock addl $0x0, (%%{re}sp)\n"));
10596 fprintf (stream
, _("\
10597 -mrelax-relocations=[no|yes]\n\
10598 generate relax relocations\n"));
10599 fprintf (stream
, _("\
10600 -mamd64 accept only AMD64 ISA\n"));
10601 fprintf (stream
, _("\
10602 -mintel64 accept only Intel64 ISA\n"));
10605 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10606 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10607 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10609 /* Pick the target format to use. */
10612 i386_target_format (void)
10614 if (!strncmp (default_arch
, "x86_64", 6))
10616 update_code_flag (CODE_64BIT
, 1);
10617 if (default_arch
[6] == '\0')
10618 x86_elf_abi
= X86_64_ABI
;
10620 x86_elf_abi
= X86_64_X32_ABI
;
10622 else if (!strcmp (default_arch
, "i386"))
10623 update_code_flag (CODE_32BIT
, 1);
10624 else if (!strcmp (default_arch
, "iamcu"))
10626 update_code_flag (CODE_32BIT
, 1);
10627 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10629 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10630 cpu_arch_name
= "iamcu";
10631 cpu_sub_arch_name
= NULL
;
10632 cpu_arch_flags
= iamcu_flags
;
10633 cpu_arch_isa
= PROCESSOR_IAMCU
;
10634 cpu_arch_isa_flags
= iamcu_flags
;
10635 if (!cpu_arch_tune_set
)
10637 cpu_arch_tune
= cpu_arch_isa
;
10638 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10641 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10642 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10646 as_fatal (_("unknown architecture"));
10648 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10649 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10650 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10651 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10653 switch (OUTPUT_FLAVOR
)
10655 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10656 case bfd_target_aout_flavour
:
10657 return AOUT_TARGET_FORMAT
;
10659 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10660 # if defined (TE_PE) || defined (TE_PEP)
10661 case bfd_target_coff_flavour
:
10662 if (flag_code
== CODE_64BIT
)
10663 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10666 # elif defined (TE_GO32)
10667 case bfd_target_coff_flavour
:
10668 return "coff-go32";
10670 case bfd_target_coff_flavour
:
10671 return "coff-i386";
10674 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10675 case bfd_target_elf_flavour
:
10677 const char *format
;
10679 switch (x86_elf_abi
)
10682 format
= ELF_TARGET_FORMAT
;
10685 use_rela_relocations
= 1;
10687 format
= ELF_TARGET_FORMAT64
;
10689 case X86_64_X32_ABI
:
10690 use_rela_relocations
= 1;
10692 disallow_64bit_reloc
= 1;
10693 format
= ELF_TARGET_FORMAT32
;
10696 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10698 if (x86_elf_abi
!= X86_64_ABI
)
10699 as_fatal (_("Intel L1OM is 64bit only"));
10700 return ELF_TARGET_L1OM_FORMAT
;
10702 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10704 if (x86_elf_abi
!= X86_64_ABI
)
10705 as_fatal (_("Intel K1OM is 64bit only"));
10706 return ELF_TARGET_K1OM_FORMAT
;
10708 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10710 if (x86_elf_abi
!= I386_ABI
)
10711 as_fatal (_("Intel MCU is 32bit only"));
10712 return ELF_TARGET_IAMCU_FORMAT
;
10718 #if defined (OBJ_MACH_O)
10719 case bfd_target_mach_o_flavour
:
10720 if (flag_code
== CODE_64BIT
)
10722 use_rela_relocations
= 1;
10724 return "mach-o-x86-64";
10727 return "mach-o-i386";
10735 #endif /* OBJ_MAYBE_ more than one */
10738 md_undefined_symbol (char *name
)
10740 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10741 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10742 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10743 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10747 if (symbol_find (name
))
10748 as_bad (_("GOT already in symbol table"));
10749 GOT_symbol
= symbol_new (name
, undefined_section
,
10750 (valueT
) 0, &zero_address_frag
);
10757 /* Round up a section size to the appropriate boundary. */
10760 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10762 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10763 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10765 /* For a.out, force the section size to be aligned. If we don't do
10766 this, BFD will align it for us, but it will not write out the
10767 final bytes of the section. This may be a bug in BFD, but it is
10768 easier to fix it here since that is how the other a.out targets
10772 align
= bfd_get_section_alignment (stdoutput
, segment
);
10773 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10780 /* On the i386, PC-relative offsets are relative to the start of the
10781 next instruction. That is, the address of the offset, plus its
10782 size, since the offset is always the last part of the insn. */
10785 md_pcrel_from (fixS
*fixP
)
10787 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10793 s_bss (int ignore ATTRIBUTE_UNUSED
)
10797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10799 obj_elf_section_change_hook ();
10801 temp
= get_absolute_expression ();
10802 subseg_set (bss_section
, (subsegT
) temp
);
10803 demand_empty_rest_of_line ();
10809 i386_validate_fix (fixS
*fixp
)
10811 if (fixp
->fx_subsy
)
10813 if (fixp
->fx_subsy
== GOT_symbol
)
10815 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10819 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10820 if (fixp
->fx_tcbit2
)
10821 fixp
->fx_r_type
= (fixp
->fx_tcbit
10822 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10823 : BFD_RELOC_X86_64_GOTPCRELX
);
10826 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10831 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10833 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10835 fixp
->fx_subsy
= 0;
10838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10839 else if (!object_64bit
)
10841 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10842 && fixp
->fx_tcbit2
)
10843 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10849 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10852 bfd_reloc_code_real_type code
;
10854 switch (fixp
->fx_r_type
)
10856 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10857 case BFD_RELOC_SIZE32
:
10858 case BFD_RELOC_SIZE64
:
10859 if (S_IS_DEFINED (fixp
->fx_addsy
)
10860 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10862 /* Resolve size relocation against local symbol to size of
10863 the symbol plus addend. */
10864 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10865 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10866 && !fits_in_unsigned_long (value
))
10867 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10868 _("symbol size computation overflow"));
10869 fixp
->fx_addsy
= NULL
;
10870 fixp
->fx_subsy
= NULL
;
10871 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10875 /* Fall through. */
10877 case BFD_RELOC_X86_64_PLT32
:
10878 case BFD_RELOC_X86_64_GOT32
:
10879 case BFD_RELOC_X86_64_GOTPCREL
:
10880 case BFD_RELOC_X86_64_GOTPCRELX
:
10881 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10882 case BFD_RELOC_386_PLT32
:
10883 case BFD_RELOC_386_GOT32
:
10884 case BFD_RELOC_386_GOT32X
:
10885 case BFD_RELOC_386_GOTOFF
:
10886 case BFD_RELOC_386_GOTPC
:
10887 case BFD_RELOC_386_TLS_GD
:
10888 case BFD_RELOC_386_TLS_LDM
:
10889 case BFD_RELOC_386_TLS_LDO_32
:
10890 case BFD_RELOC_386_TLS_IE_32
:
10891 case BFD_RELOC_386_TLS_IE
:
10892 case BFD_RELOC_386_TLS_GOTIE
:
10893 case BFD_RELOC_386_TLS_LE_32
:
10894 case BFD_RELOC_386_TLS_LE
:
10895 case BFD_RELOC_386_TLS_GOTDESC
:
10896 case BFD_RELOC_386_TLS_DESC_CALL
:
10897 case BFD_RELOC_X86_64_TLSGD
:
10898 case BFD_RELOC_X86_64_TLSLD
:
10899 case BFD_RELOC_X86_64_DTPOFF32
:
10900 case BFD_RELOC_X86_64_DTPOFF64
:
10901 case BFD_RELOC_X86_64_GOTTPOFF
:
10902 case BFD_RELOC_X86_64_TPOFF32
:
10903 case BFD_RELOC_X86_64_TPOFF64
:
10904 case BFD_RELOC_X86_64_GOTOFF64
:
10905 case BFD_RELOC_X86_64_GOTPC32
:
10906 case BFD_RELOC_X86_64_GOT64
:
10907 case BFD_RELOC_X86_64_GOTPCREL64
:
10908 case BFD_RELOC_X86_64_GOTPC64
:
10909 case BFD_RELOC_X86_64_GOTPLT64
:
10910 case BFD_RELOC_X86_64_PLTOFF64
:
10911 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10912 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10913 case BFD_RELOC_RVA
:
10914 case BFD_RELOC_VTABLE_ENTRY
:
10915 case BFD_RELOC_VTABLE_INHERIT
:
10917 case BFD_RELOC_32_SECREL
:
10919 code
= fixp
->fx_r_type
;
10921 case BFD_RELOC_X86_64_32S
:
10922 if (!fixp
->fx_pcrel
)
10924 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10925 code
= fixp
->fx_r_type
;
10928 /* Fall through. */
10930 if (fixp
->fx_pcrel
)
10932 switch (fixp
->fx_size
)
10935 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10936 _("can not do %d byte pc-relative relocation"),
10938 code
= BFD_RELOC_32_PCREL
;
10940 case 1: code
= BFD_RELOC_8_PCREL
; break;
10941 case 2: code
= BFD_RELOC_16_PCREL
; break;
10942 case 4: code
= BFD_RELOC_32_PCREL
; break;
10944 case 8: code
= BFD_RELOC_64_PCREL
; break;
10950 switch (fixp
->fx_size
)
10953 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10954 _("can not do %d byte relocation"),
10956 code
= BFD_RELOC_32
;
10958 case 1: code
= BFD_RELOC_8
; break;
10959 case 2: code
= BFD_RELOC_16
; break;
10960 case 4: code
= BFD_RELOC_32
; break;
10962 case 8: code
= BFD_RELOC_64
; break;
10969 if ((code
== BFD_RELOC_32
10970 || code
== BFD_RELOC_32_PCREL
10971 || code
== BFD_RELOC_X86_64_32S
)
10973 && fixp
->fx_addsy
== GOT_symbol
)
10976 code
= BFD_RELOC_386_GOTPC
;
10978 code
= BFD_RELOC_X86_64_GOTPC32
;
10980 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10982 && fixp
->fx_addsy
== GOT_symbol
)
10984 code
= BFD_RELOC_X86_64_GOTPC64
;
10987 rel
= XNEW (arelent
);
10988 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10989 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10991 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10993 if (!use_rela_relocations
)
10995 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10996 vtable entry to be used in the relocation's section offset. */
10997 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10998 rel
->address
= fixp
->fx_offset
;
10999 #if defined (OBJ_COFF) && defined (TE_PE)
11000 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11001 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11006 /* Use the rela in 64bit mode. */
11009 if (disallow_64bit_reloc
)
11012 case BFD_RELOC_X86_64_DTPOFF64
:
11013 case BFD_RELOC_X86_64_TPOFF64
:
11014 case BFD_RELOC_64_PCREL
:
11015 case BFD_RELOC_X86_64_GOTOFF64
:
11016 case BFD_RELOC_X86_64_GOT64
:
11017 case BFD_RELOC_X86_64_GOTPCREL64
:
11018 case BFD_RELOC_X86_64_GOTPC64
:
11019 case BFD_RELOC_X86_64_GOTPLT64
:
11020 case BFD_RELOC_X86_64_PLTOFF64
:
11021 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11022 _("cannot represent relocation type %s in x32 mode"),
11023 bfd_get_reloc_code_name (code
));
11029 if (!fixp
->fx_pcrel
)
11030 rel
->addend
= fixp
->fx_offset
;
11034 case BFD_RELOC_X86_64_PLT32
:
11035 case BFD_RELOC_X86_64_GOT32
:
11036 case BFD_RELOC_X86_64_GOTPCREL
:
11037 case BFD_RELOC_X86_64_GOTPCRELX
:
11038 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11039 case BFD_RELOC_X86_64_TLSGD
:
11040 case BFD_RELOC_X86_64_TLSLD
:
11041 case BFD_RELOC_X86_64_GOTTPOFF
:
11042 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11043 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11044 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11047 rel
->addend
= (section
->vma
11049 + fixp
->fx_addnumber
11050 + md_pcrel_from (fixp
));
11055 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11056 if (rel
->howto
== NULL
)
11058 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11059 _("cannot represent relocation type %s"),
11060 bfd_get_reloc_code_name (code
));
11061 /* Set howto to a garbage value so that we can keep going. */
11062 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11063 gas_assert (rel
->howto
!= NULL
);
11069 #include "tc-i386-intel.c"
11072 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11074 int saved_naked_reg
;
11075 char saved_register_dot
;
11077 saved_naked_reg
= allow_naked_reg
;
11078 allow_naked_reg
= 1;
11079 saved_register_dot
= register_chars
['.'];
11080 register_chars
['.'] = '.';
11081 allow_pseudo_reg
= 1;
11082 expression_and_evaluate (exp
);
11083 allow_pseudo_reg
= 0;
11084 register_chars
['.'] = saved_register_dot
;
11085 allow_naked_reg
= saved_naked_reg
;
11087 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11089 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11091 exp
->X_op
= O_constant
;
11092 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11093 .dw2_regnum
[flag_code
>> 1];
11096 exp
->X_op
= O_illegal
;
11101 tc_x86_frame_initial_instructions (void)
11103 static unsigned int sp_regno
[2];
11105 if (!sp_regno
[flag_code
>> 1])
11107 char *saved_input
= input_line_pointer
;
11108 char sp
[][4] = {"esp", "rsp"};
11111 input_line_pointer
= sp
[flag_code
>> 1];
11112 tc_x86_parse_to_dw2regnum (&exp
);
11113 gas_assert (exp
.X_op
== O_constant
);
11114 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11115 input_line_pointer
= saved_input
;
11118 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11119 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11123 x86_dwarf2_addr_size (void)
11125 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11126 if (x86_elf_abi
== X86_64_X32_ABI
)
11129 return bfd_arch_bits_per_address (stdoutput
) / 8;
11133 i386_elf_section_type (const char *str
, size_t len
)
11135 if (flag_code
== CODE_64BIT
11136 && len
== sizeof ("unwind") - 1
11137 && strncmp (str
, "unwind", 6) == 0)
11138 return SHT_X86_64_UNWIND
;
11145 i386_solaris_fix_up_eh_frame (segT sec
)
11147 if (flag_code
== CODE_64BIT
)
11148 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11154 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11158 exp
.X_op
= O_secrel
;
11159 exp
.X_add_symbol
= symbol
;
11160 exp
.X_add_number
= 0;
11161 emit_expr (&exp
, size
);
11165 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11166 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11169 x86_64_section_letter (int letter
, const char **ptr_msg
)
11171 if (flag_code
== CODE_64BIT
)
11174 return SHF_X86_64_LARGE
;
11176 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11179 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11184 x86_64_section_word (char *str
, size_t len
)
11186 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11187 return SHF_X86_64_LARGE
;
11193 handle_large_common (int small ATTRIBUTE_UNUSED
)
11195 if (flag_code
!= CODE_64BIT
)
11197 s_comm_internal (0, elf_common_parse
);
11198 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11202 static segT lbss_section
;
11203 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11204 asection
*saved_bss_section
= bss_section
;
11206 if (lbss_section
== NULL
)
11208 flagword applicable
;
11209 segT seg
= now_seg
;
11210 subsegT subseg
= now_subseg
;
11212 /* The .lbss section is for local .largecomm symbols. */
11213 lbss_section
= subseg_new (".lbss", 0);
11214 applicable
= bfd_applicable_section_flags (stdoutput
);
11215 bfd_set_section_flags (stdoutput
, lbss_section
,
11216 applicable
& SEC_ALLOC
);
11217 seg_info (lbss_section
)->bss
= 1;
11219 subseg_set (seg
, subseg
);
11222 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11223 bss_section
= lbss_section
;
11225 s_comm_internal (0, elf_common_parse
);
11227 elf_com_section_ptr
= saved_com_section_ptr
;
11228 bss_section
= saved_bss_section
;
11231 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */