gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 #ifdef ANSI_PROTOTYPES
  27 struct fix;
  28 #endif
  29
  30 #define TARGET_BYTES_BIG_ENDIAN 0
  31
  32 #ifdef TE_LYNX
  33 #define TARGET_FORMAT           "coff-i386-lynx"
  34 #endif
  35
  36 #ifdef BFD_ASSEMBLER
  37 /* This is used to determine relocation types in tc-i386.c.  The first
  38    parameter is the current relocation type, the second one is the desired
  39    type.  The idea is that if the original type is already some kind of PIC
  40    relocation, we leave it alone, otherwise we give it the desired type */
  41
  42 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
  43 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
  44
  45 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
  46 /* This arranges for gas/write.c to not apply a relocation if
  47    tc_fix_adjustable() says it is not adjustable.
  48    The "! symbol_used_in_reloc_p" test is there specifically to cover
  49    the case of non-global symbols in linkonce sections.  It's the
  50    generally correct thing to do though;  If a reloc is going to be
  51    emitted against a symbol then we don't want to adjust the fixup by
  52    applying the reloc during assembly.  The reloc will be applied by
  53    the linker during final link.  */
  54 #define TC_FIX_ADJUSTABLE(fixP) \
  55   (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
  56 #endif
  57
  58 /* This expression evaluates to false if the relocation is for a local object
  59    for which we still want to do the relocation at runtime.  True if we
  60    are willing to perform this relocation while building the .o file.
  61    This is only used for pcrel relocations, so GOTOFF does not need to be
  62    checked here.  I am not sure if some of the others are ever used with
  63    pcrel, but it is easier to be safe than sorry.  */
  64
  65 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
  66   ((FIX)->fx_r_type != BFD_RELOC_386_PLT32                      \
  67    && (FIX)->fx_r_type != BFD_RELOC_386_GOT32                   \
  68    && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC                   \
  69    && ((FIX)->fx_addsy == NULL                                  \
  70        || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                    \
  71            && ! S_IS_WEAK ((FIX)->fx_addsy)                     \
  72            && S_IS_DEFINED ((FIX)->fx_addsy)                    \
  73            && ! S_IS_COMMON ((FIX)->fx_addsy))))
  74
  75 #define TARGET_ARCH             bfd_arch_i386
  76 #define TARGET_MACH             (i386_mach ())
  77 extern unsigned long i386_mach PARAMS ((void));
  78
  79 #ifdef TE_FreeBSD
  80 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  81 #endif
  82 #ifdef TE_NetBSD
  83 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  84 #endif
  85 #ifdef TE_386BSD
  86 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  87 #endif
  88 #ifdef TE_LINUX
  89 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  90 #endif
  91 #ifdef TE_Mach
  92 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  93 #endif
  94 #ifdef TE_DYNIX
  95 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  96 #endif
  97 #ifndef AOUT_TARGET_FORMAT
  98 #define AOUT_TARGET_FORMAT      "a.out-i386"
  99 #endif
 100
 101 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
 102      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
 103 extern const char *i386_target_format PARAMS ((void));
 104 #define TARGET_FORMAT i386_target_format ()
 105 #else
 106 #ifdef OBJ_ELF
 107 #define TARGET_FORMAT           "elf32-i386"
 108 #endif
 109 #ifdef OBJ_AOUT
 110 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
 111 #endif
 112 #endif
 113
 114 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
 115 #define md_end i386_elf_emit_arch_note
 116 extern void i386_elf_emit_arch_note PARAMS ((void));
 117 #endif
 118
 119 #else /* ! BFD_ASSEMBLER */
 120
 121 /* COFF STUFF */
 122
 123 #define COFF_MAGIC I386MAGIC
 124 #define BFD_ARCH bfd_arch_i386
 125 #define COFF_FLAGS F_AR32WR
 126 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
 127 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
 128 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
 129 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
 130 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
 131
 132 #ifdef TE_GO32
 133 /* DJGPP now expects some sections to be 2**4 aligned.  */
 134 #define SUB_SEGMENT_ALIGN(SEG)                                          \
 135   ((strcmp (obj_segment_name (SEG), ".text") == 0                       \
 136     || strcmp (obj_segment_name (SEG), ".data") == 0                    \
 137     || strcmp (obj_segment_name (SEG), ".bss") == 0                     \
 138     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0     \
 139     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0     \
 140     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0)    \
 141    ? 4                                                                  \
 142    : 2)
 143 #else
 144 #define SUB_SEGMENT_ALIGN(SEG) 2
 145 #endif
 146
 147 #define TC_RVA_RELOC 7
 148 /* Need this for PIC relocations */
 149 #define NEED_FX_R_TYPE
 150
 151 #ifdef TE_386BSD
 152 /* The BSDI linker apparently rejects objects with a machine type of
 153    M_386 (100).  */
 154 #define AOUT_MACHTYPE 0
 155 #else
 156 #define AOUT_MACHTYPE 100
 157 #endif
 158
 159 #undef REVERSE_SORT_RELOCS
 160
 161 #endif /* ! BFD_ASSEMBLER */
 162
 163 #ifndef LEX_AT
 164 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 165 extern void x86_cons PARAMS ((expressionS *, int));
 166
 167 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 168 extern void x86_cons_fix_new
 169   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 170 #endif
 171
 172 #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
 173 extern int tc_i386_force_relocation PARAMS ((struct fix *));
 174
 175 #ifdef BFD_ASSEMBLER
 176 #define NO_RELOC BFD_RELOC_NONE
 177 #else
 178 #define NO_RELOC 0
 179 #endif
 180 #define tc_coff_symbol_emit_hook(a)     ;       /* not used */
 181
 182 #ifndef BFD_ASSEMBLER
 183 #ifndef OBJ_AOUT
 184 #ifndef TE_PE
 185 #ifndef TE_GO32
 186 /* Local labels starts with .L */
 187 #define LOCAL_LABEL(name) (name[0] == '.' \
 188                  && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
 189 #endif
 190 #endif
 191 #endif
 192 #endif
 193
 194 #define LOCAL_LABELS_FB 1
 195
 196 #define tc_aout_pre_write_hook(x)       {;}     /* not used */
 197 #define tc_crawl_symbol_chain(a)        {;}     /* not used */
 198 #define tc_headers_hook(a)              {;}     /* not used */
 199
 200 extern const char extra_symbol_chars[];
 201 #define tc_symbol_chars extra_symbol_chars
 202
 203 #define MAX_OPERANDS 3          /* max operands per insn */
 204 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 205 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 206
 207 /* Prefixes will be emitted in the order defined below.
 208    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 209    instruction, and so must come before any prefixes.  */
 210 #define WAIT_PREFIX     0
 211 #define LOCKREP_PREFIX  1
 212 #define ADDR_PREFIX     2
 213 #define DATA_PREFIX     3
 214 #define SEG_PREFIX      4
 215 #define REX_PREFIX      5       /* must come last.  */
 216 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 217
 218 /* we define the syntax here (modulo base,index,scale syntax) */
 219 #define REGISTER_PREFIX '%'
 220 #define IMMEDIATE_PREFIX '$'
 221 #define ABSOLUTE_PREFIX '*'
 222
 223 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 224 #define NOP_OPCODE (char) 0x90
 225
 226 /* register numbers */
 227 #define EBP_REG_NUM 5
 228 #define ESP_REG_NUM 4
 229
 230 /* modrm_byte.regmem for twobyte escape */
 231 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 232 /* index_base_byte.index for no index register addressing */
 233 #define NO_INDEX_REGISTER ESP_REG_NUM
 234 /* index_base_byte.base for no base register addressing */
 235 #define NO_BASE_REGISTER EBP_REG_NUM
 236 #define NO_BASE_REGISTER_16 6
 237
 238 /* these are the instruction mnemonic suffixes.  */
 239 #define WORD_MNEM_SUFFIX  'w'
 240 #define BYTE_MNEM_SUFFIX  'b'
 241 #define SHORT_MNEM_SUFFIX 's'
 242 #define LONG_MNEM_SUFFIX  'l'
 243 #define QWORD_MNEM_SUFFIX  'q'
 244 /* Intel Syntax */
 245 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 246
 247 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 248 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 249 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 250
 251 #define END_OF_INSN '\0'
 252
 253 /* Intel Syntax */
 254 /* Values 0-4 map onto scale factor */
 255 #define BYTE_PTR     0
 256 #define WORD_PTR     1
 257 #define DWORD_PTR    2
 258 #define QWORD_PTR    3
 259 #define XWORD_PTR    4
 260 #define SHORT        5
 261 #define OFFSET_FLAT  6
 262 #define FLAT         7
 263 #define NONE_FOUND   8
 264
 265 typedef struct
 266 {
 267   /* instruction name sans width suffix ("mov" for movl insns) */
 268   char *name;
 269
 270   /* how many operands */
 271   unsigned int operands;
 272
 273   /* base_opcode is the fundamental opcode byte without optional
 274      prefix(es).  */
 275   unsigned int base_opcode;
 276
 277   /* extension_opcode is the 3 bit extension for group <n> insns.
 278      This field is also used to store the 8-bit opcode suffix for the
 279      AMD 3DNow! instructions.
 280      If this template has no extension opcode (the usual case) use None */
 281   unsigned int extension_opcode;
 282 #define None 0xffff             /* If no extension_opcode is possible.  */
 283
 284   /* cpu feature flags */
 285   unsigned int cpu_flags;
 286 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 287 #define Cpu186            0x2   /* i186 or better required */
 288 #define Cpu286            0x4   /* i286 or better required */
 289 #define Cpu386            0x8   /* i386 or better required */
 290 #define Cpu486           0x10   /* i486 or better required */
 291 #define Cpu586           0x20   /* i585 or better required */
 292 #define Cpu686           0x40   /* i686 or better required */
 293 #define CpuP4            0x80   /* Pentium4 or better required */
 294 #define CpuK6           0x100   /* AMD K6 or better required*/
 295 #define CpuAthlon       0x200   /* AMD Athlon or better required*/
 296 #define CpuSledgehammer 0x400   /* Sledgehammer or better required */
 297 #define CpuMMX          0x800   /* MMX support required */
 298 #define CpuSSE         0x1000   /* Streaming SIMD extensions required */
 299 #define CpuSSE2        0x2000   /* Streaming SIMD extensions 2 required */
 300 #define Cpu3dnow       0x4000   /* 3dnow! support required */
 301
 302   /* These flags are set by gas depending on the flag_code.  */
 303 #define Cpu64        0x4000000   /* 64bit support required  */
 304 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 305
 306   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 307 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
 308
 309   /* the bits in opcode_modifier are used to generate the final opcode from
 310      the base_opcode.  These bits also are used to detect alternate forms of
 311      the same instruction */
 312   unsigned int opcode_modifier;
 313
 314   /* opcode_modifier bits: */
 315 #define W                  0x1  /* set if operands can be words or dwords
 316                                    encoded the canonical way */
 317 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 318                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 319 #define Modrm              0x4
 320 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 321 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 322 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 323 #define Jump              0x40  /* special case for jump insns.  */
 324 #define JumpDword         0x80  /* call and jump */
 325 #define JumpByte         0x100  /* loop and jecxz */
 326 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 327 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 328 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 329 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 330 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 331 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 332 #define Size64          0x8000  /* needs size prefix if in 16-bit mode */
 333 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 334 #define DefaultSize    0x20000  /* default insn size depends on mode */
 335 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 336 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 337 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 338 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 339 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 340 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 341 #define FWait        0x1000000  /* instruction needs FWAIT */
 342 #define IsString     0x2000000  /* quick test for string instructions */
 343 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 344 #define IsPrefix     0x8000000  /* opcode is a prefix */
 345 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 346 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 347 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 348 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 349
 350   /* operand_types[i] describes the type of operand i.  This is made
 351      by OR'ing together all of the possible type masks.  (e.g.
 352      'operand_types[i] = Reg|Imm' specifies that operand i can be
 353      either a register or an immediate operand.  */
 354   unsigned int operand_types[3];
 355
 356   /* operand_types[i] bits */
 357   /* register */
 358 #define Reg8               0x1  /* 8 bit reg */
 359 #define Reg16              0x2  /* 16 bit reg */
 360 #define Reg32              0x4  /* 32 bit reg */
 361 #define Reg64              0x8  /* 64 bit reg */
 362   /* immediate */
 363 #define Imm8              0x10  /* 8 bit immediate */
 364 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 365 #define Imm16             0x40  /* 16 bit immediate */
 366 #define Imm32             0x80  /* 32 bit immediate */
 367 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 368 #define Imm64            0x200  /* 64 bit immediate */
 369 #define Imm1             0x400  /* 1 bit immediate */
 370   /* memory */
 371 #define BaseIndex        0x800
 372   /* Disp8,16,32 are used in different ways, depending on the
 373      instruction.  For jumps, they specify the size of the PC relative
 374      displacement, for baseindex type instructions, they specify the
 375      size of the offset relative to the base register, and for memory
 376      offset instructions such as `mov 1234,%al' they specify the size of
 377      the offset relative to the segment base.  */
 378 #define Disp8           0x1000  /* 8 bit displacement */
 379 #define Disp16          0x2000  /* 16 bit displacement */
 380 #define Disp32          0x4000  /* 32 bit displacement */
 381 #define Disp32S         0x8000  /* 32 bit signed displacement */
 382 #define Disp64         0x10000  /* 64 bit displacement */
 383   /* specials */
 384 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 385 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 386 #define Control        0x80000  /* Control register */
 387 #define Debug         0x100000  /* Debug register */
 388 #define Test          0x200000  /* Test register */
 389 #define FloatReg      0x400000  /* Float register */
 390 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 391 #define SReg2        0x1000000  /* 2 bit segment register */
 392 #define SReg3        0x2000000  /* 3 bit segment register */
 393 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 394 #define JumpAbsolute 0x8000000
 395 #define RegMMX      0x10000000  /* MMX register */
 396 #define RegXMM      0x20000000  /* XMM registers in PIII */
 397 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 398
 399   /* InvMem is for instructions with a modrm byte that only allow a
 400      general register encoding in the i.tm.mode and i.tm.regmem fields,
 401      eg. control reg moves.  They really ought to support a memory form,
 402      but don't, so we add an InvMem flag to the register operand to
 403      indicate that it should be encoded in the i.tm.regmem field.  */
 404 #define InvMem      0x80000000
 405
 406 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 407 #define WordReg (Reg16|Reg32|Reg64)
 408 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 409 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 410 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 411 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 412 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 413   /* The following aliases are defined because the opcode table
 414      carefully specifies the allowed memory types for each instruction.
 415      At the moment we can only tell a memory reference size by the
 416      instruction suffix, so there's not much point in defining Mem8,
 417      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 418      the suffix directly to check memory operands.  */
 419 #define LLongMem AnyMem         /* 64 bits (or more) */
 420 #define LongMem AnyMem          /* 32 bit memory ref */
 421 #define ShortMem AnyMem         /* 16 bit memory ref */
 422 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 423 #define ByteMem AnyMem          /* 8 bit memory ref */
 424 }
 425 template;
 426
 427 /*
 428   'templates' is for grouping together 'template' structures for opcodes
 429   of the same name.  This is only used for storing the insns in the grand
 430   ole hash table of insns.
 431   The templates themselves start at START and range up to (but not including)
 432   END.
 433   */
 434 typedef struct
 435 {
 436   const template *start;
 437   const template *end;
 438 }
 439 templates;
 440
 441 /* these are for register name --> number & type hash lookup */
 442 typedef struct
 443 {
 444   char *reg_name;
 445   unsigned int reg_type;
 446   unsigned int reg_flags;
 447 #define RegRex      0x1  /* Extended register.  */
 448 #define RegRex64    0x2  /* Extended 8 bit register.  */
 449   unsigned int reg_num;
 450 }
 451 reg_entry;
 452
 453 typedef struct
 454 {
 455   char *seg_name;
 456   unsigned int seg_prefix;
 457 }
 458 seg_entry;
 459
 460 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 461 typedef struct
 462 {
 463   unsigned int regmem;  /* codes register or memory operand */
 464   unsigned int reg;     /* codes register operand (or extended opcode) */
 465   unsigned int mode;    /* how to interpret regmem & reg */
 466 }
 467 modrm_byte;
 468
 469 /* x86-64 extension prefix.  */
 470 typedef int rex_byte;
 471 #define REX_OPCODE      0x40
 472
 473 /* Indicates 64 bit operand size.  */
 474 #define REX_MODE64      8
 475 /* High extension to reg field of modrm byte.  */
 476 #define REX_EXTX        4
 477 /* High extension to SIB index field.  */
 478 #define REX_EXTY        2
 479 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 480 #define REX_EXTZ        1
 481
 482 /* 386 opcode byte to code indirect addressing.  */
 483 typedef struct
 484 {
 485   unsigned base;
 486   unsigned index;
 487   unsigned scale;
 488 }
 489 sib_byte;
 490
 491 /* x86 arch names and features */
 492 typedef struct
 493 {
 494   const char *name;     /* arch name */
 495   unsigned int flags;   /* cpu feature flags */
 496 }
 497 arch_entry;
 498
 499 /* The name of the global offset table generated by the compiler. Allow
 500    this to be overridden if need be.  */
 501 #ifndef GLOBAL_OFFSET_TABLE_NAME
 502 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 503 #endif
 504
 505 #ifdef BFD_ASSEMBLER
 506 void i386_validate_fix PARAMS ((struct fix *));
 507 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
 508 #endif
 509
 510 #endif /* TC_I386 */
 511
 512 #define md_operand(x)
 513
 514 extern const struct relax_type md_relax_table[];
 515 #define TC_GENERIC_RELAX_TABLE md_relax_table
 516
 517 #define md_do_align(n, fill, len, max, around)                          \
 518 if ((n) && !need_pass_2                                                 \
 519     && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))         \
 520     && subseg_text_p (now_seg))                                         \
 521   {                                                                     \
 522     frag_align_code ((n), (max));                                       \
 523     goto around;                                                        \
 524   }
 525
 526 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 527
 528 extern void i386_align_code PARAMS ((fragS *, int));
 529
 530 #define HANDLE_ALIGN(fragP)                                             \
 531 if (fragP->fr_type == rs_align_code)                                    \
 532   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 533                            - fragP->fr_address                          \
 534                            - fragP->fr_fix));
 535
 536 void i386_print_statistics PARAMS ((FILE *));
 537 #define tc_print_statistics i386_print_statistics
 538
 539 #define md_number_to_chars number_to_chars_littleendian
 540
 541 #ifdef SCO_ELF
 542 #define tc_init_after_args() sco_id ()
 543 extern void sco_id PARAMS ((void));
 544 #endif
 545
 546 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */