gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001, 2002, 2003, 2004
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 #ifndef BFD_ASSEMBLER
  27 #error So, do you know what you are doing?
  28 #endif
  29
  30 #ifdef ANSI_PROTOTYPES
  31 struct fix;
  32 #endif
  33
  34 #define TARGET_BYTES_BIG_ENDIAN 0
  35
  36 #define TARGET_ARCH             bfd_arch_i386
  37 #define TARGET_MACH             (i386_mach ())
  38 extern unsigned long i386_mach (void);
  39
  40 #ifdef TE_FreeBSD
  41 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  42 #endif
  43 #ifdef TE_NetBSD
  44 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  45 #endif
  46 #ifdef TE_386BSD
  47 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  48 #endif
  49 #ifdef TE_LINUX
  50 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  51 #endif
  52 #ifdef TE_Mach
  53 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  54 #endif
  55 #ifdef TE_DYNIX
  56 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  57 #endif
  58 #ifndef AOUT_TARGET_FORMAT
  59 #define AOUT_TARGET_FORMAT      "a.out-i386"
  60 #endif
  61
  62 #ifdef TE_FreeBSD
  63 #define ELF_TARGET_FORMAT       "elf32-i386-freebsd"
  64 #elif defined (TE_VXWORKS)
  65 #define ELF_TARGET_FORMAT       "elf32-i386-vxworks"
  66 #endif
  67
  68 #ifndef ELF_TARGET_FORMAT
  69 #define ELF_TARGET_FORMAT       "elf32-i386"
  70 #endif
  71
  72 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  73      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  74 extern const char *i386_target_format PARAMS ((void));
  75 #define TARGET_FORMAT i386_target_format ()
  76 #else
  77 #ifdef OBJ_ELF
  78 #define TARGET_FORMAT           ELF_TARGET_FORMAT
  79 #endif
  80 #ifdef OBJ_AOUT
  81 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
  82 #endif
  83 #endif
  84
  85 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
  86 #define md_end i386_elf_emit_arch_note
  87 extern void i386_elf_emit_arch_note PARAMS ((void));
  88 #endif
  89
  90 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
  91
  92 #define LOCAL_LABELS_FB 1
  93
  94 extern const char extra_symbol_chars[];
  95 #define tc_symbol_chars extra_symbol_chars
  96
  97 #define MAX_OPERANDS 3          /* max operands per insn */
  98 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
  99 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 100
 101 /* Prefixes will be emitted in the order defined below.
 102    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 103    instruction, and so must come before any prefixes.  */
 104 #define WAIT_PREFIX     0
 105 #define LOCKREP_PREFIX  1
 106 #define ADDR_PREFIX     2
 107 #define DATA_PREFIX     3
 108 #define SEG_PREFIX      4
 109 #define REX_PREFIX      5       /* must come last.  */
 110 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 111
 112 /* we define the syntax here (modulo base,index,scale syntax) */
 113 #define REGISTER_PREFIX '%'
 114 #define IMMEDIATE_PREFIX '$'
 115 #define ABSOLUTE_PREFIX '*'
 116
 117 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 118 #define NOP_OPCODE (char) 0x90
 119
 120 /* register numbers */
 121 #define EBP_REG_NUM 5
 122 #define ESP_REG_NUM 4
 123
 124 /* modrm_byte.regmem for twobyte escape */
 125 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 126 /* index_base_byte.index for no index register addressing */
 127 #define NO_INDEX_REGISTER ESP_REG_NUM
 128 /* index_base_byte.base for no base register addressing */
 129 #define NO_BASE_REGISTER EBP_REG_NUM
 130 #define NO_BASE_REGISTER_16 6
 131
 132 /* these are the instruction mnemonic suffixes.  */
 133 #define WORD_MNEM_SUFFIX  'w'
 134 #define BYTE_MNEM_SUFFIX  'b'
 135 #define SHORT_MNEM_SUFFIX 's'
 136 #define LONG_MNEM_SUFFIX  'l'
 137 #define QWORD_MNEM_SUFFIX  'q'
 138 /* Intel Syntax */
 139 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 140
 141 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 142 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 143 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 144
 145 #define END_OF_INSN '\0'
 146
 147 typedef struct
 148 {
 149   /* instruction name sans width suffix ("mov" for movl insns) */
 150   char *name;
 151
 152   /* how many operands */
 153   unsigned int operands;
 154
 155   /* base_opcode is the fundamental opcode byte without optional
 156      prefix(es).  */
 157   unsigned int base_opcode;
 158
 159   /* extension_opcode is the 3 bit extension for group <n> insns.
 160      This field is also used to store the 8-bit opcode suffix for the
 161      AMD 3DNow! instructions.
 162      If this template has no extension opcode (the usual case) use None */
 163   unsigned int extension_opcode;
 164 #define None 0xffff             /* If no extension_opcode is possible.  */
 165
 166   /* cpu feature flags */
 167   unsigned int cpu_flags;
 168 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 169 #define Cpu186            0x2   /* i186 or better required */
 170 #define Cpu286            0x4   /* i286 or better required */
 171 #define Cpu386            0x8   /* i386 or better required */
 172 #define Cpu486           0x10   /* i486 or better required */
 173 #define Cpu586           0x20   /* i585 or better required */
 174 #define Cpu686           0x40   /* i686 or better required */
 175 #define CpuP4            0x80   /* Pentium4 or better required */
 176 #define CpuK6           0x100   /* AMD K6 or better required*/
 177 #define CpuAthlon       0x200   /* AMD Athlon or better required*/
 178 #define CpuSledgehammer 0x400   /* Sledgehammer or better required */
 179 #define CpuMMX          0x800   /* MMX support required */
 180 #define CpuMMX2        0x1000   /* extended MMX support (with SSE or 3DNow!Ext) required */
 181 #define CpuSSE         0x2000   /* Streaming SIMD extensions required */
 182 #define CpuSSE2        0x4000   /* Streaming SIMD extensions 2 required */
 183 #define Cpu3dnow       0x8000   /* 3dnow! support required */
 184 #define Cpu3dnowA     0x10000   /* 3dnow!Extensions support required */
 185 #define CpuSSE3       0x20000   /* Streaming SIMD extensions 3 required */
 186 #define CpuPNI        CpuSSE3   /* Prescott New Instructions required */
 187 #define CpuPadLock    0x40000   /* VIA PadLock required */
 188 #define CpuSVME       0x80000   /* AMD Secure Virtual Machine Ext-s required */
 189
 190   /* These flags are set by gas depending on the flag_code.  */
 191 #define Cpu64        0x4000000   /* 64bit support required  */
 192 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 193
 194   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 195 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
 196         |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI \
 197         |Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
 198
 199   /* the bits in opcode_modifier are used to generate the final opcode from
 200      the base_opcode.  These bits also are used to detect alternate forms of
 201      the same instruction */
 202   unsigned int opcode_modifier;
 203
 204   /* opcode_modifier bits: */
 205 #define W                  0x1  /* set if operands can be words or dwords
 206                                    encoded the canonical way */
 207 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 208                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 209 #define Modrm              0x4
 210 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 211 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 212 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 213 #define Jump              0x40  /* special case for jump insns.  */
 214 #define JumpDword         0x80  /* call and jump */
 215 #define JumpByte         0x100  /* loop and jecxz */
 216 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 217 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 218 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 219 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 220 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 221 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 222 #define Size64          0x8000  /* needs size prefix if in 16-bit mode */
 223 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 224 #define DefaultSize    0x20000  /* default insn size depends on mode */
 225 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 226 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 227 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 228 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 229 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 230 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 231 #define FWait        0x1000000  /* instruction needs FWAIT */
 232 #define IsString     0x2000000  /* quick test for string instructions */
 233 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 234 #define IsPrefix     0x8000000  /* opcode is a prefix */
 235 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 236 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 237 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 238 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 239
 240   /* operand_types[i] describes the type of operand i.  This is made
 241      by OR'ing together all of the possible type masks.  (e.g.
 242      'operand_types[i] = Reg|Imm' specifies that operand i can be
 243      either a register or an immediate operand.  */
 244   unsigned int operand_types[3];
 245
 246   /* operand_types[i] bits */
 247   /* register */
 248 #define Reg8               0x1  /* 8 bit reg */
 249 #define Reg16              0x2  /* 16 bit reg */
 250 #define Reg32              0x4  /* 32 bit reg */
 251 #define Reg64              0x8  /* 64 bit reg */
 252   /* immediate */
 253 #define Imm8              0x10  /* 8 bit immediate */
 254 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 255 #define Imm16             0x40  /* 16 bit immediate */
 256 #define Imm32             0x80  /* 32 bit immediate */
 257 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 258 #define Imm64            0x200  /* 64 bit immediate */
 259 #define Imm1             0x400  /* 1 bit immediate */
 260   /* memory */
 261 #define BaseIndex        0x800
 262   /* Disp8,16,32 are used in different ways, depending on the
 263      instruction.  For jumps, they specify the size of the PC relative
 264      displacement, for baseindex type instructions, they specify the
 265      size of the offset relative to the base register, and for memory
 266      offset instructions such as `mov 1234,%al' they specify the size of
 267      the offset relative to the segment base.  */
 268 #define Disp8           0x1000  /* 8 bit displacement */
 269 #define Disp16          0x2000  /* 16 bit displacement */
 270 #define Disp32          0x4000  /* 32 bit displacement */
 271 #define Disp32S         0x8000  /* 32 bit signed displacement */
 272 #define Disp64         0x10000  /* 64 bit displacement */
 273   /* specials */
 274 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 275 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 276 #define Control        0x80000  /* Control register */
 277 #define Debug         0x100000  /* Debug register */
 278 #define Test          0x200000  /* Test register */
 279 #define FloatReg      0x400000  /* Float register */
 280 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 281 #define SReg2        0x1000000  /* 2 bit segment register */
 282 #define SReg3        0x2000000  /* 3 bit segment register */
 283 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 284 #define JumpAbsolute 0x8000000
 285 #define RegMMX      0x10000000  /* MMX register */
 286 #define RegXMM      0x20000000  /* XMM registers in PIII */
 287 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 288
 289   /* InvMem is for instructions with a modrm byte that only allow a
 290      general register encoding in the i.tm.mode and i.tm.regmem fields,
 291      eg. control reg moves.  They really ought to support a memory form,
 292      but don't, so we add an InvMem flag to the register operand to
 293      indicate that it should be encoded in the i.tm.regmem field.  */
 294 #define InvMem      0x80000000
 295
 296 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 297 #define WordReg (Reg16|Reg32|Reg64)
 298 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 299 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 300 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 301 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 302 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 303   /* The following aliases are defined because the opcode table
 304      carefully specifies the allowed memory types for each instruction.
 305      At the moment we can only tell a memory reference size by the
 306      instruction suffix, so there's not much point in defining Mem8,
 307      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 308      the suffix directly to check memory operands.  */
 309 #define LLongMem AnyMem         /* 64 bits (or more) */
 310 #define LongMem AnyMem          /* 32 bit memory ref */
 311 #define ShortMem AnyMem         /* 16 bit memory ref */
 312 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 313 #define ByteMem AnyMem          /* 8 bit memory ref */
 314 }
 315 template;
 316
 317 /*
 318   'templates' is for grouping together 'template' structures for opcodes
 319   of the same name.  This is only used for storing the insns in the grand
 320   ole hash table of insns.
 321   The templates themselves start at START and range up to (but not including)
 322   END.
 323   */
 324 typedef struct
 325 {
 326   const template *start;
 327   const template *end;
 328 }
 329 templates;
 330
 331 /* these are for register name --> number & type hash lookup */
 332 typedef struct
 333 {
 334   char *reg_name;
 335   unsigned int reg_type;
 336   unsigned int reg_flags;
 337 #define RegRex      0x1  /* Extended register.  */
 338 #define RegRex64    0x2  /* Extended 8 bit register.  */
 339   unsigned int reg_num;
 340 }
 341 reg_entry;
 342
 343 typedef struct
 344 {
 345   char *seg_name;
 346   unsigned int seg_prefix;
 347 }
 348 seg_entry;
 349
 350 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 351 typedef struct
 352 {
 353   unsigned int regmem;  /* codes register or memory operand */
 354   unsigned int reg;     /* codes register operand (or extended opcode) */
 355   unsigned int mode;    /* how to interpret regmem & reg */
 356 }
 357 modrm_byte;
 358
 359 /* x86-64 extension prefix.  */
 360 typedef int rex_byte;
 361 #define REX_OPCODE      0x40
 362
 363 /* Indicates 64 bit operand size.  */
 364 #define REX_MODE64      8
 365 /* High extension to reg field of modrm byte.  */
 366 #define REX_EXTX        4
 367 /* High extension to SIB index field.  */
 368 #define REX_EXTY        2
 369 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 370 #define REX_EXTZ        1
 371
 372 /* 386 opcode byte to code indirect addressing.  */
 373 typedef struct
 374 {
 375   unsigned base;
 376   unsigned index;
 377   unsigned scale;
 378 }
 379 sib_byte;
 380
 381 /* x86 arch names and features */
 382 typedef struct
 383 {
 384   const char *name;     /* arch name */
 385   unsigned int flags;   /* cpu feature flags */
 386 }
 387 arch_entry;
 388
 389 /* The name of the global offset table generated by the compiler. Allow
 390    this to be overridden if need be.  */
 391 #ifndef GLOBAL_OFFSET_TABLE_NAME
 392 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 393 #endif
 394
 395 #ifndef LEX_AT
 396 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 397 extern void x86_cons PARAMS ((expressionS *, int));
 398
 399 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 400 extern void x86_cons_fix_new
 401   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 402 #endif
 403
 404 #ifdef TE_PE
 405 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
 406 extern void x86_pe_cons_fix_new
 407   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 408 #endif
 409
 410 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 411
 412 #define NO_RELOC BFD_RELOC_NONE
 413
 414 void i386_validate_fix PARAMS ((struct fix *));
 415 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 416
 417 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 418 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 419
 420 /* Values passed to md_apply_fix don't include the symbol value.  */
 421 #define MD_APPLY_SYM_VALUE(FIX) 0
 422
 423 /* ELF wants external syms kept, as does PE COFF.  */
 424 #if defined (TE_PE) && defined (STRICT_PE_FORMAT)
 425 #define EXTERN_FORCE_RELOC                              \
 426   (OUTPUT_FLAVOR == bfd_target_elf_flavour              \
 427    || OUTPUT_FLAVOR == bfd_target_coff_flavour)
 428 #else
 429 #define EXTERN_FORCE_RELOC                              \
 430   (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 431 #endif
 432
 433 /* This expression evaluates to true if the relocation is for a local
 434    object for which we still want to do the relocation at runtime.
 435    False if we are willing to perform this relocation while building
 436    the .o file.  GOTOFF does not need to be checked here because it is
 437    not pcrel.  I am not sure if some of the others are ever used with
 438    pcrel, but it is easier to be safe than sorry.  */
 439
 440 #define TC_FORCE_RELOCATION_LOCAL(FIX)                  \
 441   (!(FIX)->fx_pcrel                                     \
 442    || (FIX)->fx_plt                                     \
 443    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32           \
 444    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32           \
 445    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC           \
 446    || TC_FORCE_RELOCATION (FIX))
 447
 448 #define md_operand(x)
 449
 450 extern const struct relax_type md_relax_table[];
 451 #define TC_GENERIC_RELAX_TABLE md_relax_table
 452
 453 extern int optimize_align_code;
 454
 455 #define md_do_align(n, fill, len, max, around)                          \
 456 if ((n)                                                                 \
 457     && !need_pass_2                                                     \
 458     && optimize_align_code                                              \
 459     && (!(fill)                                                         \
 460         || ((char)*(fill) == (char)0x90 && (len) == 1))                 \
 461     && subseg_text_p (now_seg))                                         \
 462   {                                                                     \
 463     frag_align_code ((n), (max));                                       \
 464     goto around;                                                        \
 465   }
 466
 467 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 468
 469 extern void i386_align_code PARAMS ((fragS *, int));
 470
 471 #define HANDLE_ALIGN(fragP)                                             \
 472 if (fragP->fr_type == rs_align_code)                                    \
 473   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 474                            - fragP->fr_address                          \
 475                            - fragP->fr_fix));
 476
 477 void i386_print_statistics PARAMS ((FILE *));
 478 #define tc_print_statistics i386_print_statistics
 479
 480 #define md_number_to_chars number_to_chars_littleendian
 481
 482 #ifdef SCO_ELF
 483 #define tc_init_after_args() sco_id ()
 484 extern void sco_id PARAMS ((void));
 485 #endif
 486
 487 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 488 #define TARGET_USE_CFIPOP 1
 489
 490 extern unsigned int x86_dwarf2_return_column;
 491 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
 492
 493 extern int x86_cie_data_alignment;
 494 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 495
 496 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
 497 extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
 498
 499 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
 500 extern void tc_x86_frame_initial_instructions PARAMS ((void));
 501
 502 #define md_elf_section_type(str,len) i386_elf_section_type (str, len)
 503 extern int i386_elf_section_type PARAMS ((const char *, size_t len));
 504
 505 #ifdef TE_PE
 506
 507 #define O_secrel O_md1
 508
 509 #define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
 510 void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
 511
 512 #endif /* TE_PE */
 513
 514 #endif /* TC_I386 */