gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001, 2002, 2003, 2004, 2005
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 struct fix;
  27
  28 #define TARGET_BYTES_BIG_ENDIAN 0
  29
  30 #define TARGET_ARCH             bfd_arch_i386
  31 #define TARGET_MACH             (i386_mach ())
  32 extern unsigned long i386_mach (void);
  33
  34 #ifdef TE_FreeBSD
  35 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  36 #endif
  37 #ifdef TE_NetBSD
  38 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  39 #endif
  40 #ifdef TE_386BSD
  41 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  42 #endif
  43 #ifdef TE_LINUX
  44 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  45 #endif
  46 #ifdef TE_Mach
  47 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  48 #endif
  49 #ifdef TE_DYNIX
  50 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  51 #endif
  52 #ifndef AOUT_TARGET_FORMAT
  53 #define AOUT_TARGET_FORMAT      "a.out-i386"
  54 #endif
  55
  56 #ifdef TE_FreeBSD
  57 #define ELF_TARGET_FORMAT       "elf32-i386-freebsd"
  58 #elif defined (TE_VXWORKS)
  59 #define ELF_TARGET_FORMAT       "elf32-i386-vxworks"
  60 #endif
  61
  62 #ifndef ELF_TARGET_FORMAT
  63 #define ELF_TARGET_FORMAT       "elf32-i386"
  64 #endif
  65
  66 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  67      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  68 extern const char *i386_target_format PARAMS ((void));
  69 #define TARGET_FORMAT i386_target_format ()
  70 #else
  71 #ifdef OBJ_ELF
  72 #define TARGET_FORMAT           ELF_TARGET_FORMAT
  73 #endif
  74 #ifdef OBJ_AOUT
  75 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
  76 #endif
  77 #endif
  78
  79 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
  80 #define md_end i386_elf_emit_arch_note
  81 extern void i386_elf_emit_arch_note PARAMS ((void));
  82 #endif
  83
  84 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
  85
  86 #define LOCAL_LABELS_FB 1
  87
  88 extern const char extra_symbol_chars[];
  89 #define tc_symbol_chars extra_symbol_chars
  90
  91 #define MAX_OPERANDS 3          /* max operands per insn */
  92 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
  93 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
  94
  95 /* Prefixes will be emitted in the order defined below.
  96    WAIT_PREFIX must be the first prefix since FWAIT is really is an
  97    instruction, and so must come before any prefixes.  */
  98 #define WAIT_PREFIX     0
  99 #define LOCKREP_PREFIX  1
 100 #define ADDR_PREFIX     2
 101 #define DATA_PREFIX     3
 102 #define SEG_PREFIX      4
 103 #define REX_PREFIX      5       /* must come last.  */
 104 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 105
 106 /* we define the syntax here (modulo base,index,scale syntax) */
 107 #define REGISTER_PREFIX '%'
 108 #define IMMEDIATE_PREFIX '$'
 109 #define ABSOLUTE_PREFIX '*'
 110
 111 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 112 #define NOP_OPCODE (char) 0x90
 113
 114 /* register numbers */
 115 #define EBP_REG_NUM 5
 116 #define ESP_REG_NUM 4
 117
 118 /* modrm_byte.regmem for twobyte escape */
 119 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 120 /* index_base_byte.index for no index register addressing */
 121 #define NO_INDEX_REGISTER ESP_REG_NUM
 122 /* index_base_byte.base for no base register addressing */
 123 #define NO_BASE_REGISTER EBP_REG_NUM
 124 #define NO_BASE_REGISTER_16 6
 125
 126 /* these are the instruction mnemonic suffixes.  */
 127 #define WORD_MNEM_SUFFIX  'w'
 128 #define BYTE_MNEM_SUFFIX  'b'
 129 #define SHORT_MNEM_SUFFIX 's'
 130 #define LONG_MNEM_SUFFIX  'l'
 131 #define QWORD_MNEM_SUFFIX  'q'
 132 /* Intel Syntax */
 133 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 134
 135 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 136 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 137 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 138
 139 #define END_OF_INSN '\0'
 140
 141 typedef struct
 142 {
 143   /* instruction name sans width suffix ("mov" for movl insns) */
 144   char *name;
 145
 146   /* how many operands */
 147   unsigned int operands;
 148
 149   /* base_opcode is the fundamental opcode byte without optional
 150      prefix(es).  */
 151   unsigned int base_opcode;
 152
 153   /* extension_opcode is the 3 bit extension for group <n> insns.
 154      This field is also used to store the 8-bit opcode suffix for the
 155      AMD 3DNow! instructions.
 156      If this template has no extension opcode (the usual case) use None */
 157   unsigned int extension_opcode;
 158 #define None 0xffff             /* If no extension_opcode is possible.  */
 159
 160   /* cpu feature flags */
 161   unsigned int cpu_flags;
 162 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 163 #define Cpu186            0x2   /* i186 or better required */
 164 #define Cpu286            0x4   /* i286 or better required */
 165 #define Cpu386            0x8   /* i386 or better required */
 166 #define Cpu486           0x10   /* i486 or better required */
 167 #define Cpu586           0x20   /* i585 or better required */
 168 #define Cpu686           0x40   /* i686 or better required */
 169 #define CpuP4            0x80   /* Pentium4 or better required */
 170 #define CpuK6           0x100   /* AMD K6 or better required*/
 171 #define CpuAthlon       0x200   /* AMD Athlon or better required*/
 172 #define CpuSledgehammer 0x400   /* Sledgehammer or better required */
 173 #define CpuMMX          0x800   /* MMX support required */
 174 #define CpuMMX2        0x1000   /* extended MMX support (with SSE or 3DNow!Ext) required */
 175 #define CpuSSE         0x2000   /* Streaming SIMD extensions required */
 176 #define CpuSSE2        0x4000   /* Streaming SIMD extensions 2 required */
 177 #define Cpu3dnow       0x8000   /* 3dnow! support required */
 178 #define Cpu3dnowA     0x10000   /* 3dnow!Extensions support required */
 179 #define CpuSSE3       0x20000   /* Streaming SIMD extensions 3 required */
 180 #define CpuPNI        CpuSSE3   /* Prescott New Instructions required */
 181 #define CpuPadLock    0x40000   /* VIA PadLock required */
 182 #define CpuSVME       0x80000   /* AMD Secure Virtual Machine Ext-s required */
 183 #define CpuVMX       0x100000   /* VMX Instructions required */
 184
 185   /* These flags are set by gas depending on the flag_code.  */
 186 #define Cpu64        0x4000000   /* 64bit support required  */
 187 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 188
 189   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 190 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
 191         |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
 192         |Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
 193
 194   /* the bits in opcode_modifier are used to generate the final opcode from
 195      the base_opcode.  These bits also are used to detect alternate forms of
 196      the same instruction */
 197   unsigned int opcode_modifier;
 198
 199   /* opcode_modifier bits: */
 200 #define W                  0x1  /* set if operands can be words or dwords
 201                                    encoded the canonical way */
 202 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 203                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 204 #define Modrm              0x4
 205 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 206 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 207 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 208 #define Jump              0x40  /* special case for jump insns.  */
 209 #define JumpDword         0x80  /* call and jump */
 210 #define JumpByte         0x100  /* loop and jecxz */
 211 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 212 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 213 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 214 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 215 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 216 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 217 #define Size64          0x8000  /* needs size prefix if in 16-bit mode */
 218 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 219 #define DefaultSize    0x20000  /* default insn size depends on mode */
 220 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 221 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 222 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 223 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 224 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 225 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 226 #define FWait        0x1000000  /* instruction needs FWAIT */
 227 #define IsString     0x2000000  /* quick test for string instructions */
 228 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 229 #define IsPrefix     0x8000000  /* opcode is a prefix */
 230 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 231 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 232 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 233 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 234
 235   /* operand_types[i] describes the type of operand i.  This is made
 236      by OR'ing together all of the possible type masks.  (e.g.
 237      'operand_types[i] = Reg|Imm' specifies that operand i can be
 238      either a register or an immediate operand.  */
 239   unsigned int operand_types[3];
 240
 241   /* operand_types[i] bits */
 242   /* register */
 243 #define Reg8               0x1  /* 8 bit reg */
 244 #define Reg16              0x2  /* 16 bit reg */
 245 #define Reg32              0x4  /* 32 bit reg */
 246 #define Reg64              0x8  /* 64 bit reg */
 247   /* immediate */
 248 #define Imm8              0x10  /* 8 bit immediate */
 249 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 250 #define Imm16             0x40  /* 16 bit immediate */
 251 #define Imm32             0x80  /* 32 bit immediate */
 252 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 253 #define Imm64            0x200  /* 64 bit immediate */
 254 #define Imm1             0x400  /* 1 bit immediate */
 255   /* memory */
 256 #define BaseIndex        0x800
 257   /* Disp8,16,32 are used in different ways, depending on the
 258      instruction.  For jumps, they specify the size of the PC relative
 259      displacement, for baseindex type instructions, they specify the
 260      size of the offset relative to the base register, and for memory
 261      offset instructions such as `mov 1234,%al' they specify the size of
 262      the offset relative to the segment base.  */
 263 #define Disp8           0x1000  /* 8 bit displacement */
 264 #define Disp16          0x2000  /* 16 bit displacement */
 265 #define Disp32          0x4000  /* 32 bit displacement */
 266 #define Disp32S         0x8000  /* 32 bit signed displacement */
 267 #define Disp64         0x10000  /* 64 bit displacement */
 268   /* specials */
 269 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 270 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 271 #define Control        0x80000  /* Control register */
 272 #define Debug         0x100000  /* Debug register */
 273 #define Test          0x200000  /* Test register */
 274 #define FloatReg      0x400000  /* Float register */
 275 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 276 #define SReg2        0x1000000  /* 2 bit segment register */
 277 #define SReg3        0x2000000  /* 3 bit segment register */
 278 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 279 #define JumpAbsolute 0x8000000
 280 #define RegMMX      0x10000000  /* MMX register */
 281 #define RegXMM      0x20000000  /* XMM registers in PIII */
 282 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 283
 284   /* InvMem is for instructions with a modrm byte that only allow a
 285      general register encoding in the i.tm.mode and i.tm.regmem fields,
 286      eg. control reg moves.  They really ought to support a memory form,
 287      but don't, so we add an InvMem flag to the register operand to
 288      indicate that it should be encoded in the i.tm.regmem field.  */
 289 #define InvMem      0x80000000
 290
 291 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 292 #define WordReg (Reg16|Reg32|Reg64)
 293 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 294 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 295 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 296 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 297 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 298   /* The following aliases are defined because the opcode table
 299      carefully specifies the allowed memory types for each instruction.
 300      At the moment we can only tell a memory reference size by the
 301      instruction suffix, so there's not much point in defining Mem8,
 302      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 303      the suffix directly to check memory operands.  */
 304 #define LLongMem AnyMem         /* 64 bits (or more) */
 305 #define LongMem AnyMem          /* 32 bit memory ref */
 306 #define ShortMem AnyMem         /* 16 bit memory ref */
 307 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 308 #define ByteMem AnyMem          /* 8 bit memory ref */
 309 }
 310 template;
 311
 312 /*
 313   'templates' is for grouping together 'template' structures for opcodes
 314   of the same name.  This is only used for storing the insns in the grand
 315   ole hash table of insns.
 316   The templates themselves start at START and range up to (but not including)
 317   END.
 318   */
 319 typedef struct
 320 {
 321   const template *start;
 322   const template *end;
 323 }
 324 templates;
 325
 326 /* these are for register name --> number & type hash lookup */
 327 typedef struct
 328 {
 329   char *reg_name;
 330   unsigned int reg_type;
 331   unsigned int reg_flags;
 332 #define RegRex      0x1  /* Extended register.  */
 333 #define RegRex64    0x2  /* Extended 8 bit register.  */
 334   unsigned int reg_num;
 335 }
 336 reg_entry;
 337
 338 typedef struct
 339 {
 340   char *seg_name;
 341   unsigned int seg_prefix;
 342 }
 343 seg_entry;
 344
 345 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 346 typedef struct
 347 {
 348   unsigned int regmem;  /* codes register or memory operand */
 349   unsigned int reg;     /* codes register operand (or extended opcode) */
 350   unsigned int mode;    /* how to interpret regmem & reg */
 351 }
 352 modrm_byte;
 353
 354 /* x86-64 extension prefix.  */
 355 typedef int rex_byte;
 356 #define REX_OPCODE      0x40
 357
 358 /* Indicates 64 bit operand size.  */
 359 #define REX_MODE64      8
 360 /* High extension to reg field of modrm byte.  */
 361 #define REX_EXTX        4
 362 /* High extension to SIB index field.  */
 363 #define REX_EXTY        2
 364 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 365 #define REX_EXTZ        1
 366
 367 /* 386 opcode byte to code indirect addressing.  */
 368 typedef struct
 369 {
 370   unsigned base;
 371   unsigned index;
 372   unsigned scale;
 373 }
 374 sib_byte;
 375
 376 /* x86 arch names and features */
 377 typedef struct
 378 {
 379   const char *name;     /* arch name */
 380   unsigned int flags;   /* cpu feature flags */
 381 }
 382 arch_entry;
 383
 384 /* The name of the global offset table generated by the compiler. Allow
 385    this to be overridden if need be.  */
 386 #ifndef GLOBAL_OFFSET_TABLE_NAME
 387 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 388 #endif
 389
 390 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
 391 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 392 extern void x86_cons PARAMS ((expressionS *, int));
 393 #endif
 394
 395 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 396 extern void x86_cons_fix_new
 397   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 398
 399 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 400
 401 #define NO_RELOC BFD_RELOC_NONE
 402
 403 void i386_validate_fix PARAMS ((struct fix *));
 404 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 405
 406 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 407 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 408
 409 /* Values passed to md_apply_fix don't include the symbol value.  */
 410 #define MD_APPLY_SYM_VALUE(FIX) 0
 411
 412 /* ELF wants external syms kept, as does PE COFF.  */
 413 #if defined (TE_PE) && defined (STRICT_PE_FORMAT)
 414 #define EXTERN_FORCE_RELOC                              \
 415   (OUTPUT_FLAVOR == bfd_target_elf_flavour              \
 416    || OUTPUT_FLAVOR == bfd_target_coff_flavour)
 417 #else
 418 #define EXTERN_FORCE_RELOC                              \
 419   (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 420 #endif
 421
 422 /* This expression evaluates to true if the relocation is for a local
 423    object for which we still want to do the relocation at runtime.
 424    False if we are willing to perform this relocation while building
 425    the .o file.  GOTOFF does not need to be checked here because it is
 426    not pcrel.  I am not sure if some of the others are ever used with
 427    pcrel, but it is easier to be safe than sorry.  */
 428
 429 #define TC_FORCE_RELOCATION_LOCAL(FIX)                  \
 430   (!(FIX)->fx_pcrel                                     \
 431    || (FIX)->fx_plt                                     \
 432    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32           \
 433    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32           \
 434    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC           \
 435    || TC_FORCE_RELOCATION (FIX))
 436
 437 extern int i386_parse_name (char *, expressionS *, char *);
 438 #define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
 439
 440 extern const struct relax_type md_relax_table[];
 441 #define TC_GENERIC_RELAX_TABLE md_relax_table
 442
 443 extern int optimize_align_code;
 444
 445 #define md_do_align(n, fill, len, max, around)                          \
 446 if ((n)                                                                 \
 447     && !need_pass_2                                                     \
 448     && optimize_align_code                                              \
 449     && (!(fill)                                                         \
 450         || ((char)*(fill) == (char)0x90 && (len) == 1))                 \
 451     && subseg_text_p (now_seg))                                         \
 452   {                                                                     \
 453     frag_align_code ((n), (max));                                       \
 454     goto around;                                                        \
 455   }
 456
 457 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 458
 459 extern void i386_align_code PARAMS ((fragS *, int));
 460
 461 #define HANDLE_ALIGN(fragP)                                             \
 462 if (fragP->fr_type == rs_align_code)                                    \
 463   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 464                            - fragP->fr_address                          \
 465                            - fragP->fr_fix));
 466
 467 void i386_print_statistics PARAMS ((FILE *));
 468 #define tc_print_statistics i386_print_statistics
 469
 470 #define md_number_to_chars number_to_chars_littleendian
 471
 472 #ifdef SCO_ELF
 473 #define tc_init_after_args() sco_id ()
 474 extern void sco_id PARAMS ((void));
 475 #endif
 476
 477 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 478 #define TARGET_USE_CFIPOP 1
 479
 480 extern unsigned int x86_dwarf2_return_column;
 481 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
 482
 483 extern int x86_cie_data_alignment;
 484 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 485
 486 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
 487 extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
 488
 489 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
 490 extern void tc_x86_frame_initial_instructions PARAMS ((void));
 491
 492 #define md_elf_section_type(str,len) i386_elf_section_type (str, len)
 493 extern int i386_elf_section_type PARAMS ((const char *, size_t len));
 494
 495 /* Support for SHF_X86_64_LARGE */
 496 extern int x86_64_section_word PARAMS ((char *, size_t));
 497 extern int x86_64_section_letter PARAMS ((int letter, char **ptr_msg));
 498 #define md_elf_section_letter(LETTER, PTR_MSG)  x86_64_section_letter (LETTER, PTR_MSG)
 499 #define md_elf_section_word(STR, LEN)           x86_64_section_word (STR, LEN)
 500
 501 #ifdef TE_PE
 502
 503 #define O_secrel O_md1
 504
 505 #define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
 506 void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
 507
 508 #endif /* TE_PE */
 509
 510 #endif /* TC_I386 */