gas/config/tc-i860.c

   1 /* tc-i860.c -- Assembler for the Intel i860 architecture.
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
   3    Free Software Foundation, Inc.
   4
   5    Brought back from the dead and completely reworked
   6    by Jason Eckhardt <jle@cygnus.com>.
   7
   8    This file is part of GAS, the GNU Assembler.
   9
  10    GAS is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2, or (at your option)
  13    any later version.
  14
  15    GAS is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with GAS; see the file COPYING.  If not, write to the Free Software
  22    Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include "as.h"
  27 #include "safe-ctype.h"
  28 #include "subsegs.h"
  29 #include "opcode/i860.h"
  30 #include "elf/i860.h"
  31
  32
  33 /* The opcode hash table.  */
  34 static struct hash_control *op_hash = NULL;
  35
  36 /* These characters always start a comment.  */
  37 const char comment_chars[] = "#!/";
  38
  39 /* These characters start a comment at the beginning of a line.  */
  40 const char line_comment_chars[] = "#/";
  41
  42 const char line_separator_chars[] = ";";
  43
  44 /* Characters that can be used to separate the mantissa from the exponent
  45    in floating point numbers.  */
  46 const char EXP_CHARS[] = "eE";
  47
  48 /* Characters that indicate this number is a floating point constant.
  49    As in 0f12.456 or 0d1.2345e12.  */
  50 const char FLT_CHARS[] = "rRsSfFdDxXpP";
  51
  52 /* Register prefix (depends on syntax).  */
  53 static char reg_prefix;
  54
  55 #define MAX_FIXUPS 2
  56
  57 struct i860_it
  58 {
  59   char *error;
  60   unsigned long opcode;
  61   enum expand_type expand;
  62   struct i860_fi
  63   {
  64     expressionS exp;
  65     bfd_reloc_code_real_type reloc;
  66     int pcrel;
  67     valueT fup;
  68   } fi[MAX_FIXUPS];
  69 } the_insn;
  70
  71 /* The current fixup count.  */
  72 static int fc;
  73
  74 static char *expr_end;
  75
  76 /* Indicates error if a pseudo operation was expanded after a branch.  */
  77 static char last_expand;
  78
  79 /* If true, then warn if any pseudo operations were expanded.  */
  80 static int target_warn_expand = 0;
  81
  82 /* If true, then XP support is enabled.  */
  83 static int target_xp = 0;
  84
  85 /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax).  */
  86 static int target_intel_syntax = 0;
  87
  88
  89 /* Prototypes.  */
  90 static void i860_process_insn (char *);
  91 static void s_dual (int);
  92 static void s_enddual (int);
  93 static void s_atmp (int);
  94 static int i860_get_expression (char *);
  95 static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
  96 #ifdef DEBUG_I860
  97 static void print_insn (struct i860_it *);
  98 #endif
  99
 100 const pseudo_typeS md_pseudo_table[] =
 101 {
 102 #ifdef OBJ_ELF
 103   {"align",   s_align_bytes, 0},
 104 #endif
 105   {"dual",    s_dual,        0},
 106   {"enddual", s_enddual,     0},
 107   {"atmp",    s_atmp,        0},
 108   {NULL,      0,             0},
 109 };
 110
 111 /* Dual-instruction mode handling.  */
 112 enum dual
 113 {
 114   DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT,
 115 };
 116 static enum dual dual_mode = DUAL_OFF;
 117
 118 /* Handle ".dual" directive.  */
 119 static void
 120 s_dual (int ignore ATTRIBUTE_UNUSED)
 121 {
 122   if (target_intel_syntax)
 123     dual_mode = DUAL_ON;
 124   else
 125     as_bad (_("Directive .dual available only with -mintel-syntax option"));
 126 }
 127
 128 /* Handle ".enddual" directive.  */
 129 static void
 130 s_enddual (int ignore ATTRIBUTE_UNUSED)
 131 {
 132   if (target_intel_syntax)
 133     dual_mode = DUAL_OFF;
 134   else
 135     as_bad (_("Directive .enddual available only with -mintel-syntax option"));
 136 }
 137
 138 /* Temporary register used when expanding assembler pseudo operations.  */
 139 static int atmp = 31;
 140
 141 static void
 142 s_atmp (int ignore ATTRIBUTE_UNUSED)
 143 {
 144   int temp;
 145
 146   if (! target_intel_syntax)
 147     {
 148       as_bad (_("Directive .atmp available only with -mintel-syntax option"));
 149       demand_empty_rest_of_line ();
 150       return;
 151     }
 152
 153   if (strncmp (input_line_pointer, "sp", 2) == 0)
 154     {
 155       input_line_pointer += 2;
 156       atmp = 2;
 157     }
 158   else if (strncmp (input_line_pointer, "fp", 2) == 0)
 159     {
 160       input_line_pointer += 2;
 161       atmp = 3;
 162     }
 163   else if (strncmp (input_line_pointer, "r", 1) == 0)
 164     {
 165       input_line_pointer += 1;
 166       temp = get_absolute_expression ();
 167       if (temp >= 0 && temp <= 31)
 168         atmp = temp;
 169       else
 170         as_bad (_("Unknown temporary pseudo register"));
 171     }
 172   else
 173     {
 174       as_bad (_("Unknown temporary pseudo register"));
 175     }
 176   demand_empty_rest_of_line ();
 177 }
 178
 179 /* This function is called once, at assembler startup time.  It should
 180    set up all the tables and data structures that the MD part of the
 181    assembler will need.  */
 182 void
 183 md_begin (void)
 184 {
 185   const char *retval = NULL;
 186   int lose = 0;
 187   unsigned int i = 0;
 188
 189   op_hash = hash_new ();
 190
 191   while (i860_opcodes[i].name != NULL)
 192     {
 193       const char *name = i860_opcodes[i].name;
 194       retval = hash_insert (op_hash, name, (PTR)&i860_opcodes[i]);
 195       if (retval != NULL)
 196         {
 197           fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
 198                    i860_opcodes[i].name, retval);
 199           lose = 1;
 200         }
 201       do
 202         {
 203           if (i860_opcodes[i].match & i860_opcodes[i].lose)
 204             {
 205               fprintf (stderr,
 206                        _("internal error: losing opcode: `%s' \"%s\"\n"),
 207                        i860_opcodes[i].name, i860_opcodes[i].args);
 208               lose = 1;
 209             }
 210           ++i;
 211         }
 212       while (i860_opcodes[i].name != NULL
 213              && strcmp (i860_opcodes[i].name, name) == 0);
 214     }
 215
 216   if (lose)
 217     as_fatal (_("Defective assembler.  No assembly attempted."));
 218
 219   /* Set the register prefix for either Intel or AT&T/SVR4 syntax.  */
 220   reg_prefix = target_intel_syntax ? 0 : '%';
 221 }
 222
 223 /* This is the core of the machine-dependent assembler.  STR points to a
 224    machine dependent instruction.  This function emits the frags/bytes
 225    it assembles to.  */
 226 void
 227 md_assemble (char *str)
 228 {
 229   char *destp;
 230   int num_opcodes = 1;
 231   int i;
 232   struct i860_it pseudo[3];
 233
 234   assert (str);
 235   fc = 0;
 236
 237   /* Assemble the instruction.  */
 238   i860_process_insn (str);
 239
 240   /* Check for expandable flag to produce pseudo-instructions.  This
 241      is an undesirable feature that should be avoided.  */
 242   if (the_insn.expand != 0 && the_insn.expand != XP_ONLY
 243       && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT
 244                             | OP_SEL_GOTOFF | OP_SEL_PLT)))
 245     {
 246       for (i = 0; i < 3; i++)
 247         pseudo[i] = the_insn;
 248
 249       fc = 1;
 250       switch (the_insn.expand)
 251         {
 252
 253         case E_DELAY:
 254           num_opcodes = 1;
 255           break;
 256
 257         case E_MOV:
 258           if (the_insn.fi[0].exp.X_add_symbol == NULL
 259               && the_insn.fi[0].exp.X_op_symbol == NULL
 260               && (the_insn.fi[0].exp.X_add_number < (1 << 15)
 261                   && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
 262             break;
 263
 264           /* Emit "or l%const,r0,ireg_dest".  */
 265           pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000;
 266           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 267
 268           /* Emit "orh h%const,ireg_dest,ireg_dest".  */
 269           pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000
 270                               | ((the_insn.opcode & 0x001f0000) << 5);
 271           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 272
 273           num_opcodes = 2;
 274           break;
 275
 276         case E_ADDR:
 277           if (the_insn.fi[0].exp.X_add_symbol == NULL
 278               && the_insn.fi[0].exp.X_op_symbol == NULL
 279               && (the_insn.fi[0].exp.X_add_number < (1 << 15)
 280                   && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
 281             break;
 282
 283           /* Emit "orh ha%addr_expr,r0,r31".  */
 284           pseudo[0].opcode = 0xec000000 | (atmp << 16);
 285           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA);
 286
 287           /* Emit "l%addr_expr(r31),ireg_dest".  We pick up the fixup
 288              information from the original instruction.   */
 289           pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21);
 290           pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L;
 291
 292           num_opcodes = 2;
 293           break;
 294
 295         case E_U32:
 296           if (the_insn.fi[0].exp.X_add_symbol == NULL
 297               && the_insn.fi[0].exp.X_op_symbol == NULL
 298               && (the_insn.fi[0].exp.X_add_number < (1 << 16)
 299                   && the_insn.fi[0].exp.X_add_number >= 0))
 300             break;
 301
 302           /* Emit "$(opcode)h h%const,ireg_src2,r31".  */
 303           pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000
 304                               | (atmp << 16);
 305           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 306
 307           /* Emit "$(opcode) l%const,r31,ireg_dest".  */
 308           pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000
 309                               | (atmp << 21);
 310           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 311
 312           num_opcodes = 2;
 313           break;
 314
 315         case E_AND:
 316           if (the_insn.fi[0].exp.X_add_symbol == NULL
 317               && the_insn.fi[0].exp.X_op_symbol == NULL
 318               && (the_insn.fi[0].exp.X_add_number < (1 << 16)
 319                   && the_insn.fi[0].exp.X_add_number >= 0))
 320             break;
 321
 322           /* Emit "andnot h%const,ireg_src2,r31".  */
 323           pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000
 324                               | (atmp << 16);
 325           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 326           pseudo[0].fi[0].exp.X_add_number =
 327             -1 - the_insn.fi[0].exp.X_add_number;
 328
 329           /* Emit "andnot l%const,r31,ireg_dest".  */
 330           pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000
 331                               | (atmp << 21);
 332           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 333           pseudo[1].fi[0].exp.X_add_number =
 334             -1 - the_insn.fi[0].exp.X_add_number;
 335
 336           num_opcodes = 2;
 337           break;
 338
 339         case E_S32:
 340           if (the_insn.fi[0].exp.X_add_symbol == NULL
 341               && the_insn.fi[0].exp.X_op_symbol == NULL
 342               && (the_insn.fi[0].exp.X_add_number < (1 << 15)
 343                   && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
 344             break;
 345
 346           /* Emit "orh h%const,r0,r31".  */
 347           pseudo[0].opcode = 0xec000000 | (atmp << 16);
 348           pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
 349
 350           /* Emit "or l%const,r31,r31".  */
 351           pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16);
 352           pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
 353
 354           /* Emit "r31,ireg_src2,ireg_dest".  */
 355           pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11);
 356           pseudo[2].fi[0].fup = OP_IMM_S16;
 357
 358           num_opcodes = 3;
 359           break;
 360
 361         default:
 362           as_fatal (_("failed sanity check."));
 363         }
 364
 365       the_insn = pseudo[0];
 366
 367       /* Warn if an opcode is expanded after a delayed branch.  */
 368       if (num_opcodes > 1 && last_expand == 1)
 369         as_warn (_("Expanded opcode after delayed branch: `%s'"), str);
 370
 371       /* Warn if an opcode is expanded in dual mode.  */
 372       if (num_opcodes > 1 && dual_mode != DUAL_OFF)
 373         as_warn (_("Expanded opcode in dual mode: `%s'"), str);
 374
 375       /* Notify if any expansions happen.  */
 376       if (target_warn_expand && num_opcodes > 1)
 377         as_warn (_("An instruction was expanded (%s)"), str);
 378     }
 379
 380   i = 0;
 381   do
 382     {
 383       int tmp;
 384
 385       /* Output the opcode.  Note that the i860 always reads instructions
 386          as little-endian data.  */
 387       destp = frag_more (4);
 388       number_to_chars_littleendian (destp, the_insn.opcode, 4);
 389
 390       /* Check for expanded opcode after branch or in dual mode.  */
 391       last_expand = the_insn.fi[0].pcrel;
 392
 393       /* Output the symbol-dependent stuff.  Only btne and bte will ever
 394          loop more than once here, since only they (possibly) have more
 395          than one fixup.  */
 396       for (tmp = 0; tmp < fc; tmp++)
 397         {
 398           if (the_insn.fi[tmp].fup != OP_NONE)
 399             {
 400               fixS *fix;
 401               fix = fix_new_exp (frag_now,
 402                                  destp - frag_now->fr_literal,
 403                                  4,
 404                                  &the_insn.fi[tmp].exp,
 405                                  the_insn.fi[tmp].pcrel,
 406                                  the_insn.fi[tmp].reloc);
 407
 408              /* Despite the odd name, this is a scratch field.  We use
 409                 it to encode operand type information.  */
 410              fix->fx_addnumber = the_insn.fi[tmp].fup;
 411            }
 412         }
 413       the_insn = pseudo[++i];
 414     }
 415   while (--num_opcodes > 0);
 416
 417 }
 418
 419 /* Assemble the instruction pointed to by STR.  */
 420 static void
 421 i860_process_insn (char *str)
 422 {
 423   char *s;
 424   const char *args;
 425   char c;
 426   struct i860_opcode *insn;
 427   char *args_start;
 428   unsigned long opcode;
 429   unsigned int mask;
 430   int match = 0;
 431   int comma = 0;
 432
 433 #if 1 /* For compiler warnings.  */
 434   args = 0;
 435   insn = 0;
 436   args_start = 0;
 437   opcode = 0;
 438 #endif
 439
 440   for (s = str; ISLOWER (*s) || *s == '.' || *s == '3'
 441        || *s == '2' || *s == '1'; ++s)
 442     ;
 443
 444   switch (*s)
 445     {
 446     case '\0':
 447       break;
 448
 449     case ',':
 450       comma = 1;
 451
 452       /*FALLTHROUGH*/
 453
 454     case ' ':
 455       *s++ = '\0';
 456       break;
 457
 458     default:
 459       as_fatal (_("Unknown opcode: `%s'"), str);
 460     }
 461
 462   /* Check for dual mode ("d.") opcode prefix.  */
 463   if (strncmp (str, "d.", 2) == 0)
 464     {
 465       if (dual_mode == DUAL_ON)
 466         dual_mode = DUAL_ONDDOT;
 467       else
 468         dual_mode = DUAL_DDOT;
 469       str += 2;
 470     }
 471
 472   if ((insn = (struct i860_opcode *) hash_find (op_hash, str)) == NULL)
 473     {
 474       if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT)
 475         str -= 2;
 476       as_bad (_("Unknown opcode: `%s'"), str);
 477       return;
 478     }
 479
 480   if (comma)
 481     *--s = ',';
 482
 483   args_start = s;
 484   for (;;)
 485     {
 486       int t;
 487       opcode = insn->match;
 488       memset (&the_insn, '\0', sizeof (the_insn));
 489       fc = 0;
 490       for (t = 0; t < MAX_FIXUPS; t++)
 491         {
 492           the_insn.fi[t].reloc = BFD_RELOC_NONE;
 493           the_insn.fi[t].pcrel = 0;
 494           the_insn.fi[t].fup = OP_NONE;
 495         }
 496
 497       /* Build the opcode, checking as we go that the operands match.  */
 498       for (args = insn->args; ; ++args)
 499         {
 500           if (fc > MAX_FIXUPS)
 501             abort ();
 502
 503           switch (*args)
 504             {
 505
 506             /* End of args.  */
 507             case '\0':
 508               if (*s == '\0')
 509                 match = 1;
 510               break;
 511
 512             /* These must match exactly.  */
 513             case '+':
 514             case '(':
 515             case ')':
 516             case ',':
 517             case ' ':
 518               if (*s++ == *args)
 519                 continue;
 520               break;
 521
 522             /* Must be at least one digit.  */
 523             case '#':
 524               if (ISDIGIT (*s++))
 525                 {
 526                   while (ISDIGIT (*s))
 527                     ++s;
 528                   continue;
 529                 }
 530               break;
 531
 532             /* Next operand must be a register.  */
 533             case '1':
 534             case '2':
 535             case 'd':
 536               /* Check for register prefix if necessary.  */
 537               if (reg_prefix && *s != reg_prefix)
 538                 goto error;
 539               else if (reg_prefix)
 540                 s++;
 541
 542               switch (*s)
 543                 {
 544                 /* Frame pointer.  */
 545                 case 'f':
 546                   s++;
 547                   if (*s++ == 'p')
 548                     {
 549                       mask = 0x3;
 550                       break;
 551                     }
 552                   goto error;
 553
 554                 /* Stack pointer.  */
 555                 case 's':
 556                   s++;
 557                   if (*s++ == 'p')
 558                     {
 559                       mask = 0x2;
 560                       break;
 561                     }
 562                   goto error;
 563
 564                 /* Any register r0..r31.  */
 565                 case 'r':
 566                   s++;
 567                   if (!ISDIGIT (c = *s++))
 568                     {
 569                       goto error;
 570                     }
 571                   if (ISDIGIT (*s))
 572                     {
 573                       if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
 574                         goto error;
 575                     }
 576                   else
 577                     c -= '0';
 578                   mask = c;
 579                   break;
 580
 581                 /* Not this opcode.  */
 582                 default:
 583                   goto error;
 584                 }
 585
 586               /* Obtained the register, now place it in the opcode.  */
 587               switch (*args)
 588                 {
 589                 case '1':
 590                   opcode |= mask << 11;
 591                   continue;
 592
 593                 case '2':
 594                   opcode |= mask << 21;
 595                   continue;
 596
 597                 case 'd':
 598                   opcode |= mask << 16;
 599                   continue;
 600
 601                 }
 602               break;
 603
 604             /* Next operand is a floating point register.  */
 605             case 'e':
 606             case 'f':
 607             case 'g':
 608               /* Check for register prefix if necessary.  */
 609               if (reg_prefix && *s != reg_prefix)
 610                 goto error;
 611               else if (reg_prefix)
 612                 s++;
 613
 614               if (*s++ == 'f' && ISDIGIT (*s))
 615                 {
 616                   mask = *s++;
 617                   if (ISDIGIT (*s))
 618                     {
 619                       mask = 10 * (mask - '0') + (*s++ - '0');
 620                       if (mask >= 32)
 621                         {
 622                           break;
 623                         }
 624                     }
 625                   else
 626                     mask -= '0';
 627
 628                   switch (*args)
 629                     {
 630
 631                     case 'e':
 632                       opcode |= mask << 11;
 633                       continue;
 634
 635                     case 'f':
 636                       opcode |= mask << 21;
 637                       continue;
 638
 639                     case 'g':
 640                       opcode |= mask << 16;
 641                       if (dual_mode != DUAL_OFF)
 642                         opcode |= (1 << 9);
 643                       if (dual_mode == DUAL_DDOT)
 644                         dual_mode = DUAL_OFF;
 645                       if (dual_mode == DUAL_ONDDOT)
 646                         dual_mode = DUAL_ON;
 647                       if ((opcode & (1 << 10)) && mask != 0
 648                           && (mask == ((opcode >> 11) & 0x1f)))
 649                         as_warn (_("Pipelined instruction: fsrc1 = fdest"));
 650                       continue;
 651                     }
 652                 }
 653               break;
 654
 655             /* Next operand must be a control register.  */
 656             case 'c':
 657               /* Check for register prefix if necessary.  */
 658               if (reg_prefix && *s != reg_prefix)
 659                 goto error;
 660               else if (reg_prefix)
 661                 s++;
 662
 663               if (strncmp (s, "fir", 3) == 0)
 664                 {
 665                   opcode |= 0x0 << 21;
 666                   s += 3;
 667                   continue;
 668                 }
 669               if (strncmp (s, "psr", 3) == 0)
 670                 {
 671                   opcode |= 0x1 << 21;
 672                   s += 3;
 673                   continue;
 674                 }
 675               if (strncmp (s, "dirbase", 7) == 0)
 676                 {
 677                   opcode |= 0x2 << 21;
 678                   s += 7;
 679                   continue;
 680                 }
 681               if (strncmp (s, "db", 2) == 0)
 682                 {
 683                   opcode |= 0x3 << 21;
 684                   s += 2;
 685                   continue;
 686                 }
 687               if (strncmp (s, "fsr", 3) == 0)
 688                 {
 689                   opcode |= 0x4 << 21;
 690                   s += 3;
 691                   continue;
 692                 }
 693               if (strncmp (s, "epsr", 4) == 0)
 694                 {
 695                   opcode |= 0x5 << 21;
 696                   s += 4;
 697                   continue;
 698                 }
 699               /* The remaining control registers are XP only.  */
 700               if (target_xp && strncmp (s, "bear", 4) == 0)
 701                 {
 702                   opcode |= 0x6 << 21;
 703                   s += 4;
 704                   continue;
 705                 }
 706               if (target_xp && strncmp (s, "ccr", 3) == 0)
 707                 {
 708                   opcode |= 0x7 << 21;
 709                   s += 3;
 710                   continue;
 711                 }
 712               if (target_xp && strncmp (s, "p0", 2) == 0)
 713                 {
 714                   opcode |= 0x8 << 21;
 715                   s += 2;
 716                   continue;
 717                 }
 718               if (target_xp && strncmp (s, "p1", 2) == 0)
 719                 {
 720                   opcode |= 0x9 << 21;
 721                   s += 2;
 722                   continue;
 723                 }
 724               if (target_xp && strncmp (s, "p2", 2) == 0)
 725                 {
 726                   opcode |= 0xa << 21;
 727                   s += 2;
 728                   continue;
 729                 }
 730               if (target_xp && strncmp (s, "p3", 2) == 0)
 731                 {
 732                   opcode |= 0xb << 21;
 733                   s += 2;
 734                   continue;
 735                 }
 736               break;
 737
 738             /* 5-bit immediate in src1.  */
 739             case '5':
 740               if (! i860_get_expression (s))
 741                 {
 742                   s = expr_end;
 743                   the_insn.fi[fc].fup |= OP_IMM_U5;
 744                   fc++;
 745                   continue;
 746                 }
 747               break;
 748
 749             /* 26-bit immediate, relative branch (lbroff).  */
 750             case 'l':
 751               the_insn.fi[fc].pcrel = 1;
 752               the_insn.fi[fc].fup |= OP_IMM_BR26;
 753               goto immediate;
 754
 755             /* 16-bit split immediate, relative branch (sbroff).  */
 756             case 'r':
 757               the_insn.fi[fc].pcrel = 1;
 758               the_insn.fi[fc].fup |= OP_IMM_BR16;
 759               goto immediate;
 760
 761             /* 16-bit split immediate.  */
 762             case 's':
 763               the_insn.fi[fc].fup |= OP_IMM_SPLIT16;
 764               goto immediate;
 765
 766             /* 16-bit split immediate, byte aligned (st.b).  */
 767             case 'S':
 768               the_insn.fi[fc].fup |= OP_IMM_SPLIT16;
 769               goto immediate;
 770
 771             /* 16-bit split immediate, half-word aligned (st.s).  */
 772             case 'T':
 773               the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2);
 774               goto immediate;
 775
 776             /* 16-bit split immediate, word aligned (st.l).  */
 777             case 'U':
 778               the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4);
 779               goto immediate;
 780
 781             /* 16-bit immediate.  */
 782             case 'i':
 783               the_insn.fi[fc].fup |= OP_IMM_S16;
 784               goto immediate;
 785
 786             /* 16-bit immediate, byte aligned (ld.b).  */
 787             case 'I':
 788               the_insn.fi[fc].fup |= OP_IMM_S16;
 789               goto immediate;
 790
 791             /* 16-bit immediate, half-word aligned (ld.s).  */
 792             case 'J':
 793               the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2);
 794               goto immediate;
 795
 796             /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l).  */
 797             case 'K':
 798               if (insn->name[0] == 'l')
 799                 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4);
 800               else
 801                 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4);
 802               goto immediate;
 803
 804             /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d).  */
 805             case 'L':
 806               the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8);
 807               goto immediate;
 808
 809             /* 16-bit immediate, quad-word aligned (fld.q, fst.q).  */
 810             case 'M':
 811               the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16);
 812
 813               /*FALLTHROUGH*/
 814
 815               /* Handle the immediate for either the Intel syntax or
 816                  SVR4 syntax. The Intel syntax is "ha%immediate"
 817                  whereas SVR4 syntax is "[immediate]@ha".  */
 818             immediate:
 819               if (target_intel_syntax == 0)
 820                 {
 821                   /* AT&T/SVR4 syntax.  */
 822                   if (*s == ' ')
 823                     s++;
 824
 825                   /* Note that if i860_get_expression() fails, we will still
 826                      have created U entries in the symbol table for the
 827                      'symbols' in the input string.  Try not to create U
 828                      symbols for registers, etc.  */
 829                   if (! i860_get_expression (s))
 830                     s = expr_end;
 831                   else
 832                     goto error;
 833
 834                   if (strncmp (s, "@ha", 3) == 0)
 835                     {
 836                       the_insn.fi[fc].fup |= OP_SEL_HA;
 837                       s += 3;
 838                     }
 839                   else if (strncmp (s, "@h", 2) == 0)
 840                     {
 841                       the_insn.fi[fc].fup |= OP_SEL_H;
 842                       s += 2;
 843                     }
 844                   else if (strncmp (s, "@l", 2) == 0)
 845                     {
 846                       the_insn.fi[fc].fup |= OP_SEL_L;
 847                       s += 2;
 848                     }
 849                   else if (strncmp (s, "@gotoff", 7) == 0
 850                            || strncmp (s, "@GOTOFF", 7) == 0)
 851                     {
 852                       as_bad (_("Assembler does not yet support PIC"));
 853                       the_insn.fi[fc].fup |= OP_SEL_GOTOFF;
 854                       s += 7;
 855                     }
 856                   else if (strncmp (s, "@got", 4) == 0
 857                            || strncmp (s, "@GOT", 4) == 0)
 858                     {
 859                       as_bad (_("Assembler does not yet support PIC"));
 860                       the_insn.fi[fc].fup |= OP_SEL_GOT;
 861                       s += 4;
 862                     }
 863                   else if (strncmp (s, "@plt", 4) == 0
 864                            || strncmp (s, "@PLT", 4) == 0)
 865                     {
 866                       as_bad (_("Assembler does not yet support PIC"));
 867                       the_insn.fi[fc].fup |= OP_SEL_PLT;
 868                       s += 4;
 869                     }
 870
 871                   the_insn.expand = insn->expand;
 872                   fc++;
 873
 874                   continue;
 875                 }
 876               else
 877                 {
 878                   /* Intel syntax.  */
 879                   if (*s == ' ')
 880                     s++;
 881                   if (strncmp (s, "ha%", 3) == 0)
 882                     {
 883                       the_insn.fi[fc].fup |= OP_SEL_HA;
 884                       s += 3;
 885                     }
 886                   else if (strncmp (s, "h%", 2) == 0)
 887                     {
 888                       the_insn.fi[fc].fup |= OP_SEL_H;
 889                       s += 2;
 890                     }
 891                   else if (strncmp (s, "l%", 2) == 0)
 892                     {
 893                       the_insn.fi[fc].fup |= OP_SEL_L;
 894                       s += 2;
 895                     }
 896                   the_insn.expand = insn->expand;
 897
 898                   /* Note that if i860_get_expression() fails, we will still
 899                      have created U entries in the symbol table for the
 900                      'symbols' in the input string.  Try not to create U
 901                      symbols for registers, etc.  */
 902                   if (! i860_get_expression (s))
 903                     s = expr_end;
 904                   else
 905                     goto error;
 906
 907                   fc++;
 908                   continue;
 909                 }
 910               break;
 911
 912             default:
 913               as_fatal (_("failed sanity check."));
 914             }
 915           break;
 916         }
 917     error:
 918       if (match == 0)
 919         {
 920           /* Args don't match.  */
 921           if (insn[1].name != NULL
 922               && ! strcmp (insn->name, insn[1].name))
 923             {
 924               ++insn;
 925               s = args_start;
 926               continue;
 927             }
 928           else
 929             {
 930               as_bad (_("Illegal operands for %s"), insn->name);
 931               return;
 932             }
 933         }
 934       break;
 935     }
 936
 937   the_insn.opcode = opcode;
 938
 939   /* Only recognize XP instructions when the user has requested it.  */
 940   if (insn->expand == XP_ONLY && ! target_xp)
 941     as_bad (_("Unknown opcode: `%s'"), insn->name);
 942 }
 943
 944 static int
 945 i860_get_expression (char *str)
 946 {
 947   char *save_in;
 948   segT seg;
 949
 950   save_in = input_line_pointer;
 951   input_line_pointer = str;
 952   seg = expression (&the_insn.fi[fc].exp);
 953   if (seg != absolute_section
 954       && seg != undefined_section
 955       && ! SEG_NORMAL (seg))
 956     {
 957       the_insn.error = _("bad segment");
 958       expr_end = input_line_pointer;
 959       input_line_pointer = save_in;
 960       return 1;
 961     }
 962   expr_end = input_line_pointer;
 963   input_line_pointer = save_in;
 964   return 0;
 965 }
 966
 967 /* Turn a string in input_line_pointer into a floating point constant of
 968    type TYPE, and store the appropriate bytes in *LITP.  The number of
 969    LITTLENUMS emitted is stored in *SIZEP.  An error message is returned,
 970    or NULL on OK.  */
 971
 972 /* Equal to MAX_PRECISION in atof-ieee.c.  */
 973 #define MAX_LITTLENUMS 6
 974
 975 char *
 976 md_atof (int type, char *litP, int *sizeP)
 977 {
 978   int prec;
 979   LITTLENUM_TYPE words[MAX_LITTLENUMS];
 980   LITTLENUM_TYPE *wordP;
 981   char *t;
 982
 983   switch (type)
 984     {
 985     case 'f':
 986     case 'F':
 987     case 's':
 988     case 'S':
 989       prec = 2;
 990       break;
 991
 992     case 'd':
 993     case 'D':
 994     case 'r':
 995     case 'R':
 996       prec = 4;
 997       break;
 998
 999     case 'x':
1000     case 'X':
1001       prec = 6;
1002       break;
1003
1004     case 'p':
1005     case 'P':
1006       prec = 6;
1007       break;
1008
1009     default:
1010       *sizeP = 0;
1011       return _("Bad call to MD_ATOF()");
1012     }
1013   t = atof_ieee (input_line_pointer, type, words);
1014   if (t)
1015     input_line_pointer = t;
1016   *sizeP = prec * sizeof (LITTLENUM_TYPE);
1017   for (wordP = words; prec--;)
1018     {
1019       md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
1020       litP += sizeof (LITTLENUM_TYPE);
1021     }
1022   return 0;
1023 }
1024
1025 /* Write out in current endian mode.  */
1026 void
1027 md_number_to_chars (char *buf, valueT val, int n)
1028 {
1029   if (target_big_endian)
1030     number_to_chars_bigendian (buf, val, n);
1031   else
1032     number_to_chars_littleendian (buf, val, n);
1033 }
1034
1035 /* This should never be called for i860.  */
1036 int
1037 md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED,
1038                                segT segtype ATTRIBUTE_UNUSED)
1039 {
1040   as_fatal (_("i860_estimate_size_before_relax\n"));
1041 }
1042
1043 #ifdef DEBUG_I860
1044 static void
1045 print_insn (struct i860_it *insn)
1046 {
1047   if (insn->error)
1048     fprintf (stderr, "ERROR: %s\n", insn->error);
1049
1050   fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode);
1051   fprintf (stderr, "expand = 0x%x\t", insn->expand);
1052   fprintf (stderr, "reloc = %s\t\n",
1053            bfd_get_reloc_code_name (insn->reloc));
1054   fprintf (stderr, "exp =  {\n");
1055   fprintf (stderr, "\t\tX_add_symbol = %s\n",
1056            insn->exp.X_add_symbol ?
1057            (S_GET_NAME (insn->exp.X_add_symbol) ?
1058             S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0");
1059   fprintf (stderr, "\t\tX_op_symbol = %s\n",
1060            insn->exp.X_op_symbol ?
1061            (S_GET_NAME (insn->exp.X_op_symbol) ?
1062             S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0");
1063   fprintf (stderr, "\t\tX_add_number = %lx\n",
1064            insn->exp.X_add_number);
1065   fprintf (stderr, "}\n");
1066 }
1067 #endif /* DEBUG_I860 */
1068
1069 \f
1070 #ifdef OBJ_ELF
1071 const char *md_shortopts = "VQ:";
1072 #else
1073 const char *md_shortopts = "";
1074 #endif
1075
1076 #define OPTION_EB               (OPTION_MD_BASE + 0)
1077 #define OPTION_EL               (OPTION_MD_BASE + 1)
1078 #define OPTION_WARN_EXPAND      (OPTION_MD_BASE + 2)
1079 #define OPTION_XP               (OPTION_MD_BASE + 3)
1080 #define OPTION_INTEL_SYNTAX     (OPTION_MD_BASE + 4)
1081
1082 struct option md_longopts[] = {
1083   { "EB",           no_argument, NULL, OPTION_EB },
1084   { "EL",           no_argument, NULL, OPTION_EL },
1085   { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND },
1086   { "mxp",          no_argument, NULL, OPTION_XP },
1087   { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX },
1088   { NULL,           no_argument, NULL, 0 }
1089 };
1090 size_t md_longopts_size = sizeof (md_longopts);
1091
1092 int
1093 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
1094 {
1095   switch (c)
1096     {
1097     case OPTION_EB:
1098       target_big_endian = 1;
1099       break;
1100
1101     case OPTION_EL:
1102       target_big_endian = 0;
1103       break;
1104
1105     case OPTION_WARN_EXPAND:
1106       target_warn_expand = 1;
1107       break;
1108
1109     case OPTION_XP:
1110       target_xp = 1;
1111       break;
1112
1113     case OPTION_INTEL_SYNTAX:
1114       target_intel_syntax = 1;
1115       break;
1116
1117 #ifdef OBJ_ELF
1118     /* SVR4 argument compatibility (-V): print version ID.  */
1119     case 'V':
1120       print_version_id ();
1121       break;
1122
1123     /* SVR4 argument compatibility (-Qy, -Qn): controls whether
1124        a .comment section should be emitted or not (ignored).  */
1125     case 'Q':
1126       break;
1127 #endif
1128
1129     default:
1130       return 0;
1131     }
1132
1133   return 1;
1134 }
1135
1136 void
1137 md_show_usage (FILE *stream)
1138 {
1139   fprintf (stream, _("\
1140   -EL                     generate code for little endian mode (default)\n\
1141   -EB                     generate code for big endian mode\n\
1142   -mwarn-expand           warn if pseudo operations are expanded\n\
1143   -mxp                    enable i860XP support (disabled by default)\n\
1144   -mintel-syntax          enable Intel syntax (default to AT&T/SVR4)\n"));
1145 #ifdef OBJ_ELF
1146   /* SVR4 compatibility flags.  */
1147   fprintf (stream, _("\
1148   -V                      print assembler version number\n\
1149   -Qy, -Qn                ignored\n"));
1150 #endif
1151 }
1152
1153 \f
1154 /* We have no need to default values of symbols.  */
1155 symbolS *
1156 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1157 {
1158   return 0;
1159 }
1160
1161 /* The i860 denotes auto-increment with '++'.  */
1162 void
1163 md_operand (expressionS *exp)
1164 {
1165   char *s;
1166
1167   for (s = input_line_pointer; *s; s++)
1168     {
1169       if (s[0] == '+' && s[1] == '+')
1170         {
1171           input_line_pointer += 2;
1172           exp->X_op = O_register;
1173           break;
1174         }
1175     }
1176 }
1177
1178 /* Round up a section size to the appropriate boundary.  */
1179 valueT
1180 md_section_align (segT segment ATTRIBUTE_UNUSED,
1181                   valueT size ATTRIBUTE_UNUSED)
1182 {
1183   /* Byte alignment is fine.  */
1184   return size;
1185 }
1186
1187 /* On the i860, a PC-relative offset is relative to the address of the
1188    of the offset plus its size.  */
1189 long
1190 md_pcrel_from (fixS *fixP)
1191 {
1192   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
1193 }
1194
1195 /* Determine the relocation needed for non PC-relative 16-bit immediates.
1196    Also adjust the given immediate as necessary.  Finally, check that
1197    all constraints (such as alignment) are satisfied.   */
1198 static bfd_reloc_code_real_type
1199 obtain_reloc_for_imm16 (fixS *fix, long *val)
1200 {
1201   valueT fup = fix->fx_addnumber;
1202   bfd_reloc_code_real_type reloc;
1203
1204   if (fix->fx_pcrel)
1205     abort ();
1206
1207   /* Check alignment restrictions.  */
1208   if ((fup & OP_ALIGN2) && (*val & 0x1))
1209     as_bad_where (fix->fx_file, fix->fx_line,
1210                   _("This immediate requires 0 MOD 2 alignment"));
1211   else if ((fup & OP_ALIGN4) && (*val & 0x3))
1212     as_bad_where (fix->fx_file, fix->fx_line,
1213                   _("This immediate requires 0 MOD 4 alignment"));
1214   else if ((fup & OP_ALIGN8) && (*val & 0x7))
1215     as_bad_where (fix->fx_file, fix->fx_line,
1216                   _("This immediate requires 0 MOD 8 alignment"));
1217   else if ((fup & OP_ALIGN16) && (*val & 0xf))
1218     as_bad_where (fix->fx_file, fix->fx_line,
1219                   _("This immediate requires 0 MOD 16 alignment"));
1220
1221   if (fup & OP_SEL_HA)
1222     {
1223       *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0);
1224       reloc = BFD_RELOC_860_HIGHADJ;
1225     }
1226   else if (fup & OP_SEL_H)
1227     {
1228       *val >>= 16;
1229       reloc = BFD_RELOC_860_HIGH;
1230     }
1231   else if (fup & OP_SEL_L)
1232     {
1233       int num_encode;
1234       if (fup & OP_IMM_SPLIT16)
1235         {
1236           if (fup & OP_ENCODE1)
1237             {
1238               num_encode = 1;
1239               reloc = BFD_RELOC_860_SPLIT1;
1240             }
1241           else if (fup & OP_ENCODE2)
1242             {
1243               num_encode = 2;
1244               reloc = BFD_RELOC_860_SPLIT2;
1245             }
1246           else
1247             {
1248               num_encode = 0;
1249               reloc = BFD_RELOC_860_SPLIT0;
1250             }
1251         }
1252       else
1253         {
1254           if (fup & OP_ENCODE1)
1255             {
1256               num_encode = 1;
1257               reloc = BFD_RELOC_860_LOW1;
1258             }
1259           else if (fup & OP_ENCODE2)
1260             {
1261               num_encode = 2;
1262               reloc = BFD_RELOC_860_LOW2;
1263             }
1264           else if (fup & OP_ENCODE3)
1265             {
1266               num_encode = 3;
1267               reloc = BFD_RELOC_860_LOW3;
1268             }
1269           else
1270             {
1271               num_encode = 0;
1272               reloc = BFD_RELOC_860_LOW0;
1273             }
1274         }
1275
1276       /* Preserve size encode bits.  */
1277       *val &= ~((1 << num_encode) - 1);
1278     }
1279   else
1280     {
1281       /* No selector.  What reloc do we generate (???)?  */
1282       reloc = BFD_RELOC_32;
1283     }
1284
1285   return reloc;
1286 }
1287
1288 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
1289    has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
1290    we will have to generate a reloc entry.  */
1291
1292 void
1293 md_apply_fix3 (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1294 {
1295   char *buf;
1296   long val = *valP;
1297   unsigned long insn;
1298   valueT fup;
1299
1300   buf = fix->fx_frag->fr_literal + fix->fx_where;
1301
1302   /* Recall that earlier we stored the opcode little-endian.  */
1303   insn = bfd_getl32 (buf);
1304
1305   /* We stored a fix-up in this oddly-named scratch field.  */
1306   fup = fix->fx_addnumber;
1307
1308   /* Determine the necessary relocations as well as inserting an
1309      immediate into the instruction.   */
1310   if (fup & OP_IMM_U5)
1311     {
1312       if (val & ~0x1f)
1313         as_bad_where (fix->fx_file, fix->fx_line,
1314                       _("5-bit immediate too large"));
1315       if (fix->fx_addsy)
1316         as_bad_where (fix->fx_file, fix->fx_line,
1317                       _("5-bit field must be absolute"));
1318
1319       insn |= (val & 0x1f) << 11;
1320       bfd_putl32 (insn, buf);
1321       fix->fx_r_type = BFD_RELOC_NONE;
1322       fix->fx_done = 1;
1323     }
1324   else if (fup & OP_IMM_S16)
1325     {
1326       fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val);
1327
1328       /* Insert the immediate.  */
1329       if (fix->fx_addsy)
1330         fix->fx_done = 0;
1331       else
1332         {
1333           insn |= val & 0xffff;
1334           bfd_putl32 (insn, buf);
1335           fix->fx_r_type = BFD_RELOC_NONE;
1336           fix->fx_done = 1;
1337         }
1338     }
1339   else if (fup & OP_IMM_U16)
1340     abort ();
1341
1342   else if (fup & OP_IMM_SPLIT16)
1343     {
1344       fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val);
1345
1346       /* Insert the immediate.  */
1347       if (fix->fx_addsy)
1348         fix->fx_done = 0;
1349       else
1350         {
1351           insn |= val & 0x7ff;
1352           insn |= (val & 0xf800) << 5;
1353           bfd_putl32 (insn, buf);
1354           fix->fx_r_type = BFD_RELOC_NONE;
1355           fix->fx_done = 1;
1356         }
1357     }
1358   else if (fup & OP_IMM_BR16)
1359     {
1360       if (val & 0x3)
1361         as_bad_where (fix->fx_file, fix->fx_line,
1362                       _("A branch offset requires 0 MOD 4 alignment"));
1363
1364       val = val >> 2;
1365
1366       /* Insert the immediate.  */
1367       if (fix->fx_addsy)
1368         {
1369           fix->fx_done = 0;
1370           fix->fx_r_type = BFD_RELOC_860_PC16;
1371         }
1372       else
1373         {
1374           insn |= (val & 0x7ff);
1375           insn |= ((val & 0xf800) << 5);
1376           bfd_putl32 (insn, buf);
1377           fix->fx_r_type = BFD_RELOC_NONE;
1378           fix->fx_done = 1;
1379         }
1380     }
1381   else if (fup & OP_IMM_BR26)
1382     {
1383       if (val & 0x3)
1384         as_bad_where (fix->fx_file, fix->fx_line,
1385                       _("A branch offset requires 0 MOD 4 alignment"));
1386
1387       val >>= 2;
1388
1389       /* Insert the immediate.  */
1390       if (fix->fx_addsy)
1391         {
1392           fix->fx_r_type = BFD_RELOC_860_PC26;
1393           fix->fx_done = 0;
1394         }
1395       else
1396         {
1397           insn |= (val & 0x3ffffff);
1398           bfd_putl32 (insn, buf);
1399           fix->fx_r_type = BFD_RELOC_NONE;
1400           fix->fx_done = 1;
1401         }
1402     }
1403   else if (fup != OP_NONE)
1404     {
1405       as_bad_where (fix->fx_file, fix->fx_line,
1406                     _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup);
1407       abort ();
1408     }
1409   else
1410     {
1411       /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000"
1412          reach here (???).  */
1413       if (fix->fx_addsy)
1414         {
1415           fix->fx_r_type = BFD_RELOC_32;
1416           fix->fx_done = 0;
1417         }
1418       else
1419         {
1420           insn |= (val & 0xffffffff);
1421           bfd_putl32 (insn, buf);
1422           fix->fx_r_type = BFD_RELOC_NONE;
1423           fix->fx_done = 1;
1424         }
1425     }
1426 }
1427
1428 /* Generate a machine dependent reloc from a fixup.  */
1429 arelent*
1430 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
1431               fixS *fixp)
1432 {
1433   arelent *reloc;
1434
1435   reloc = xmalloc (sizeof (*reloc));
1436   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1437   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1438   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1439   reloc->addend = fixp->fx_offset;
1440   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1441
1442   if (! reloc->howto)
1443     {
1444       as_bad_where (fixp->fx_file, fixp->fx_line,
1445                     "Cannot represent %s relocation in object file",
1446                     bfd_get_reloc_code_name (fixp->fx_r_type));
1447     }
1448   return reloc;
1449 }