1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "m:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct label_fix
*tag_fixups
;
223 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
226 unsigned int src_line
;
227 struct dwarf2_line_info debug_line
;
235 struct dynreg
*next
; /* next dynamic register */
237 unsigned short base
; /* the base register number */
238 unsigned short num_regs
; /* # of registers in this set */
240 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
242 flagword flags
; /* ELF-header flags */
245 unsigned hint
:1; /* is this hint currently valid? */
246 bfd_vma offset
; /* mem.offset offset */
247 bfd_vma base
; /* mem.offset base */
250 int path
; /* number of alt. entry points seen */
251 const char **entry_labels
; /* labels of all alternate paths in
252 the current DV-checking block. */
253 int maxpaths
; /* size currently allocated for
255 /* Support for hardware errata workarounds. */
257 /* Record data about the last three insn groups. */
260 /* B-step workaround.
261 For each predicate register, this is set if the corresponding insn
262 group conditionally sets this register with one of the affected
265 /* B-step workaround.
266 For each general register, this is set if the corresponding insn
267 a) is conditional one one of the predicate registers for which
268 P_REG_SET is 1 in the corresponding entry of the previous group,
269 b) sets this general register with one of the affected
271 int g_reg_set_conditionally
[128];
277 /* application registers: */
283 #define AR_BSPSTORE 18
298 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
299 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
300 {"ar.rsc", 16}, {"ar.bsp", 17},
301 {"ar.bspstore", 18}, {"ar.rnat", 19},
302 {"ar.fcr", 21}, {"ar.eflag", 24},
303 {"ar.csd", 25}, {"ar.ssd", 26},
304 {"ar.cflg", 27}, {"ar.fsr", 28},
305 {"ar.fir", 29}, {"ar.fdr", 30},
306 {"ar.ccv", 32}, {"ar.unat", 36},
307 {"ar.fpsr", 40}, {"ar.itc", 44},
308 {"ar.pfs", 64}, {"ar.lc", 65},
329 /* control registers: */
371 static const struct const_desc
378 /* PSR constant masks: */
381 {"psr.be", ((valueT
) 1) << 1},
382 {"psr.up", ((valueT
) 1) << 2},
383 {"psr.ac", ((valueT
) 1) << 3},
384 {"psr.mfl", ((valueT
) 1) << 4},
385 {"psr.mfh", ((valueT
) 1) << 5},
387 {"psr.ic", ((valueT
) 1) << 13},
388 {"psr.i", ((valueT
) 1) << 14},
389 {"psr.pk", ((valueT
) 1) << 15},
391 {"psr.dt", ((valueT
) 1) << 17},
392 {"psr.dfl", ((valueT
) 1) << 18},
393 {"psr.dfh", ((valueT
) 1) << 19},
394 {"psr.sp", ((valueT
) 1) << 20},
395 {"psr.pp", ((valueT
) 1) << 21},
396 {"psr.di", ((valueT
) 1) << 22},
397 {"psr.si", ((valueT
) 1) << 23},
398 {"psr.db", ((valueT
) 1) << 24},
399 {"psr.lp", ((valueT
) 1) << 25},
400 {"psr.tb", ((valueT
) 1) << 26},
401 {"psr.rt", ((valueT
) 1) << 27},
402 /* 28-31: reserved */
403 /* 32-33: cpl (current privilege level) */
404 {"psr.is", ((valueT
) 1) << 34},
405 {"psr.mc", ((valueT
) 1) << 35},
406 {"psr.it", ((valueT
) 1) << 36},
407 {"psr.id", ((valueT
) 1) << 37},
408 {"psr.da", ((valueT
) 1) << 38},
409 {"psr.dd", ((valueT
) 1) << 39},
410 {"psr.ss", ((valueT
) 1) << 40},
411 /* 41-42: ri (restart instruction) */
412 {"psr.ed", ((valueT
) 1) << 43},
413 {"psr.bn", ((valueT
) 1) << 44},
416 /* indirect register-sets/memory: */
425 { "CPUID", IND_CPUID
},
426 { "cpuid", IND_CPUID
},
438 /* Pseudo functions used to indicate relocation types (these functions
439 start with an at sign (@). */
461 /* reloc pseudo functions (these must come first!): */
462 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
463 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
464 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
465 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
466 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
467 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
468 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
469 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
470 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
472 /* mbtype4 constants: */
473 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
474 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
475 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
476 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
477 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
479 /* fclass constants: */
480 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
481 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
482 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
483 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
484 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
485 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
486 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
487 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
488 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
490 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
492 /* unwind-related constants: */
493 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
494 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
495 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
497 /* unwind-related registers: */
498 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
501 /* 41-bit nop opcodes (one per unit): */
502 static const bfd_vma nop
[IA64_NUM_UNITS
] =
504 0x0000000000LL
, /* NIL => break 0 */
505 0x0008000000LL
, /* I-unit nop */
506 0x0008000000LL
, /* M-unit nop */
507 0x4000000000LL
, /* B-unit nop */
508 0x0008000000LL
, /* F-unit nop */
509 0x0008000000LL
, /* L-"unit" nop */
510 0x0008000000LL
, /* X-unit nop */
513 /* Can't be `const' as it's passed to input routines (which have the
514 habit of setting temporary sentinels. */
515 static char special_section_name
[][20] =
517 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
518 {".IA_64.unwind"}, {".IA_64.unwind_info"}
521 /* The best template for a particular sequence of up to three
523 #define N IA64_NUM_TYPES
524 static unsigned char best_template
[N
][N
][N
];
527 /* Resource dependencies currently in effect */
529 int depind
; /* dependency index */
530 const struct ia64_dependency
*dependency
; /* actual dependency */
531 unsigned specific
:1, /* is this a specific bit/regno? */
532 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
533 int index
; /* specific regno/bit within dependency */
534 int note
; /* optional qualifying note (0 if none) */
538 int insn_srlz
; /* current insn serialization state */
539 int data_srlz
; /* current data serialization state */
540 int qp_regno
; /* qualifying predicate for this usage */
541 char *file
; /* what file marked this dependency */
542 unsigned int line
; /* what line marked this dependency */
543 struct mem_offset mem_offset
; /* optional memory offset hint */
544 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
545 int path
; /* corresponding code entry index */
547 static int regdepslen
= 0;
548 static int regdepstotlen
= 0;
549 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
550 static const char *dv_sem
[] = { "none", "implied", "impliedf",
551 "data", "instr", "specific", "stop", "other" };
552 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
554 /* Current state of PR mutexation */
555 static struct qpmutex
{
558 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
559 static int qp_mutexeslen
= 0;
560 static int qp_mutexestotlen
= 0;
561 static valueT qp_safe_across_calls
= 0;
563 /* Current state of PR implications */
564 static struct qp_imply
{
567 unsigned p2_branched
:1;
569 } *qp_implies
= NULL
;
570 static int qp_implieslen
= 0;
571 static int qp_impliestotlen
= 0;
573 /* Keep track of static GR values so that indirect register usage can
574 sometimes be tracked. */
579 } gr_values
[128] = {{ 1, 0, 0 }};
581 /* These are the routines required to output the various types of
584 /* A slot_number is a frag address plus the slot index (0-2). We use the
585 frag address here so that if there is a section switch in the middle of
586 a function, then instructions emitted to a different section are not
587 counted. Since there may be more than one frag for a function, this
588 means we also need to keep track of which frag this address belongs to
589 so we can compute inter-frag distances. This also nicely solves the
590 problem with nops emitted for align directives, which can't easily be
591 counted, but can easily be derived from frag sizes. */
593 typedef struct unw_rec_list
{
595 unsigned long slot_number
;
597 struct unw_rec_list
*next
;
600 #define SLOT_NUM_NOT_SET (unsigned)-1
604 unsigned long next_slot_number
;
605 fragS
*next_slot_frag
;
607 /* Maintain a list of unwind entries for the current function. */
611 /* Any unwind entires that should be attached to the current slot
612 that an insn is being constructed for. */
613 unw_rec_list
*current_entry
;
615 /* These are used to create the unwind table entry for this function. */
618 symbolS
*info
; /* pointer to unwind info */
619 symbolS
*personality_routine
;
621 /* TRUE if processing unwind directives in a prologue region. */
626 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
628 /* Forward delarations: */
629 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
630 static void set_section
PARAMS ((char *name
));
631 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
632 unsigned int, unsigned int));
633 static void dot_radix
PARAMS ((int));
634 static void dot_special_section
PARAMS ((int));
635 static void dot_proc
PARAMS ((int));
636 static void dot_fframe
PARAMS ((int));
637 static void dot_vframe
PARAMS ((int));
638 static void dot_vframesp
PARAMS ((int));
639 static void dot_vframepsp
PARAMS ((int));
640 static void dot_save
PARAMS ((int));
641 static void dot_restore
PARAMS ((int));
642 static void dot_restorereg
PARAMS ((int));
643 static void dot_restorereg_p
PARAMS ((int));
644 static void dot_handlerdata
PARAMS ((int));
645 static void dot_unwentry
PARAMS ((int));
646 static void dot_altrp
PARAMS ((int));
647 static void dot_savemem
PARAMS ((int));
648 static void dot_saveg
PARAMS ((int));
649 static void dot_savef
PARAMS ((int));
650 static void dot_saveb
PARAMS ((int));
651 static void dot_savegf
PARAMS ((int));
652 static void dot_spill
PARAMS ((int));
653 static void dot_spillreg
PARAMS ((int));
654 static void dot_spillmem
PARAMS ((int));
655 static void dot_spillreg_p
PARAMS ((int));
656 static void dot_spillmem_p
PARAMS ((int));
657 static void dot_label_state
PARAMS ((int));
658 static void dot_copy_state
PARAMS ((int));
659 static void dot_unwabi
PARAMS ((int));
660 static void dot_personality
PARAMS ((int));
661 static void dot_body
PARAMS ((int));
662 static void dot_prologue
PARAMS ((int));
663 static void dot_endp
PARAMS ((int));
664 static void dot_template
PARAMS ((int));
665 static void dot_regstk
PARAMS ((int));
666 static void dot_rot
PARAMS ((int));
667 static void dot_byteorder
PARAMS ((int));
668 static void dot_psr
PARAMS ((int));
669 static void dot_alias
PARAMS ((int));
670 static void dot_ln
PARAMS ((int));
671 static char *parse_section_name
PARAMS ((void));
672 static void dot_xdata
PARAMS ((int));
673 static void stmt_float_cons
PARAMS ((int));
674 static void stmt_cons_ua
PARAMS ((int));
675 static void dot_xfloat_cons
PARAMS ((int));
676 static void dot_xstringer
PARAMS ((int));
677 static void dot_xdata_ua
PARAMS ((int));
678 static void dot_xfloat_cons_ua
PARAMS ((int));
679 static void print_prmask
PARAMS ((valueT mask
));
680 static void dot_pred_rel
PARAMS ((int));
681 static void dot_reg_val
PARAMS ((int));
682 static void dot_dv_mode
PARAMS ((int));
683 static void dot_entry
PARAMS ((int));
684 static void dot_mem_offset
PARAMS ((int));
685 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
686 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
687 static void declare_register_set
PARAMS ((const char *, int, int));
688 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
689 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
690 int index
, expressionS
*e
));
691 static int parse_operand
PARAMS ((expressionS
*e
));
692 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
693 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
694 static void emit_one_bundle
PARAMS ((void));
695 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
696 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
697 bfd_reloc_code_real_type r_type
));
698 static void insn_group_break
PARAMS ((int, int, int));
699 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
700 struct rsrc
*, int depind
, int path
));
701 static void add_qp_mutex
PARAMS((valueT mask
));
702 static void add_qp_imply
PARAMS((int p1
, int p2
));
703 static void clear_qp_branch_flag
PARAMS((valueT mask
));
704 static void clear_qp_mutex
PARAMS((valueT mask
));
705 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
706 static void clear_register_values
PARAMS ((void));
707 static void print_dependency
PARAMS ((const char *action
, int depind
));
708 static void instruction_serialization
PARAMS ((void));
709 static void data_serialization
PARAMS ((void));
710 static void remove_marked_resource
PARAMS ((struct rsrc
*));
711 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
712 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
713 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
714 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
715 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
716 struct ia64_opcode
*, int, struct rsrc
[], int, int));
717 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
718 static void check_dependencies
PARAMS((struct ia64_opcode
*));
719 static void mark_resources
PARAMS((struct ia64_opcode
*));
720 static void update_dependencies
PARAMS((struct ia64_opcode
*));
721 static void note_register_values
PARAMS((struct ia64_opcode
*));
722 static int qp_mutex
PARAMS ((int, int, int));
723 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
724 static void output_vbyte_mem
PARAMS ((int, char *, char *));
725 static void count_output
PARAMS ((int, char *, char *));
726 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
727 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
728 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
729 static void output_P1_format
PARAMS ((vbyte_func
, int));
730 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
731 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
732 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
733 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
734 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
735 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
736 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
737 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
738 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
739 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
740 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
741 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
742 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
743 static char format_ab_reg
PARAMS ((int, int));
744 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
746 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
747 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
749 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
750 static void free_list_records
PARAMS ((unw_rec_list
*));
751 static unw_rec_list
*output_prologue
PARAMS ((void));
752 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
753 static unw_rec_list
*output_body
PARAMS ((void));
754 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
755 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
756 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
757 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
758 static unw_rec_list
*output_rp_when
PARAMS ((void));
759 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
760 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
761 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
762 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
763 static unw_rec_list
*output_pfs_when
PARAMS ((void));
764 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
765 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
767 static unw_rec_list
*output_preds_when
PARAMS ((void));
768 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
769 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
771 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
772 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
773 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
774 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
775 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
776 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
777 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
778 static unw_rec_list
*output_unat_when
PARAMS ((void));
779 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
780 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
781 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
782 static unw_rec_list
*output_lc_when
PARAMS ((void));
783 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
784 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
785 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
786 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
787 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
788 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
789 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
790 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
791 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
792 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
793 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
794 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
795 static unw_rec_list
*output_bsp_when
PARAMS ((void));
796 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
797 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
798 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
799 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
800 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
801 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
802 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
803 static unw_rec_list
*output_rnat_when
PARAMS ((void));
804 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
805 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
806 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
807 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
808 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
809 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
810 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
811 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
812 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
813 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
815 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
817 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
819 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
820 unsigned int, unsigned int));
821 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
822 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
823 static int calc_record_size
PARAMS ((unw_rec_list
*));
824 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
825 static int count_bits
PARAMS ((unsigned long));
826 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
827 unsigned long, fragS
*));
828 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
829 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
830 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
831 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
832 static int generate_unwind_image
PARAMS ((void));
834 /* Determine if application register REGNUM resides in the integer
835 unit (as opposed to the memory unit). */
837 ar_is_in_integer_unit (reg
)
842 return (reg
== 64 /* pfs */
843 || reg
== 65 /* lc */
844 || reg
== 66 /* ec */
845 /* ??? ias accepts and puts these in the integer unit. */
846 || (reg
>= 112 && reg
<= 127));
849 /* Switch to section NAME and create section if necessary. It's
850 rather ugly that we have to manipulate input_line_pointer but I
851 don't see any other way to accomplish the same thing without
852 changing obj-elf.c (which may be the Right Thing, in the end). */
857 char *saved_input_line_pointer
;
859 saved_input_line_pointer
= input_line_pointer
;
860 input_line_pointer
= name
;
862 input_line_pointer
= saved_input_line_pointer
;
865 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
868 ia64_elf_section_flags (flags
, attr
, type
)
870 int attr
, type ATTRIBUTE_UNUSED
;
872 if (attr
& SHF_IA_64_SHORT
)
873 flags
|= SEC_SMALL_DATA
;
878 set_regstack (ins
, locs
, outs
, rots
)
879 unsigned int ins
, locs
, outs
, rots
;
884 sof
= ins
+ locs
+ outs
;
887 as_bad ("Size of frame exceeds maximum of 96 registers");
892 as_warn ("Size of rotating registers exceeds frame size");
895 md
.in
.base
= REG_GR
+ 32;
896 md
.loc
.base
= md
.in
.base
+ ins
;
897 md
.out
.base
= md
.loc
.base
+ locs
;
899 md
.in
.num_regs
= ins
;
900 md
.loc
.num_regs
= locs
;
901 md
.out
.num_regs
= outs
;
902 md
.rot
.num_regs
= rots
;
909 struct label_fix
*lfix
;
911 subsegT saved_subseg
;
914 if (!md
.last_text_seg
)
918 saved_subseg
= now_subseg
;
920 subseg_set (md
.last_text_seg
, 0);
922 while (md
.num_slots_in_use
> 0)
923 emit_one_bundle (); /* force out queued instructions */
925 /* In case there are labels following the last instruction, resolve
927 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
929 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
930 symbol_set_frag (lfix
->sym
, frag_now
);
932 CURR_SLOT
.label_fixups
= 0;
933 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
935 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
936 symbol_set_frag (lfix
->sym
, frag_now
);
938 CURR_SLOT
.tag_fixups
= 0;
940 /* In case there are unwind directives following the last instruction,
941 resolve those now. We only handle body and prologue directives here.
942 Give an error for others. */
943 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
945 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
946 || ptr
->r
.type
== body
)
948 ptr
->slot_number
= (unsigned long) frag_more (0);
949 ptr
->slot_frag
= frag_now
;
952 as_bad (_("Unwind directive not followed by an instruction."));
954 unwind
.current_entry
= NULL
;
956 subseg_set (saved_seg
, saved_subseg
);
958 if (md
.qp
.X_op
== O_register
)
959 as_bad ("qualifying predicate not followed by instruction");
963 ia64_do_align (nbytes
)
966 char *saved_input_line_pointer
= input_line_pointer
;
968 input_line_pointer
= "";
969 s_align_bytes (nbytes
);
970 input_line_pointer
= saved_input_line_pointer
;
974 ia64_cons_align (nbytes
)
979 char *saved_input_line_pointer
= input_line_pointer
;
980 input_line_pointer
= "";
981 s_align_bytes (nbytes
);
982 input_line_pointer
= saved_input_line_pointer
;
986 /* Output COUNT bytes to a memory location. */
987 static unsigned char *vbyte_mem_ptr
= NULL
;
990 output_vbyte_mem (count
, ptr
, comment
)
993 char *comment ATTRIBUTE_UNUSED
;
996 if (vbyte_mem_ptr
== NULL
)
1001 for (x
= 0; x
< count
; x
++)
1002 *(vbyte_mem_ptr
++) = ptr
[x
];
1005 /* Count the number of bytes required for records. */
1006 static int vbyte_count
= 0;
1008 count_output (count
, ptr
, comment
)
1010 char *ptr ATTRIBUTE_UNUSED
;
1011 char *comment ATTRIBUTE_UNUSED
;
1013 vbyte_count
+= count
;
1017 output_R1_format (f
, rtype
, rlen
)
1019 unw_record_type rtype
;
1026 output_R3_format (f
, rtype
, rlen
);
1032 else if (rtype
!= prologue
)
1033 as_bad ("record type is not valid");
1035 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1036 (*f
) (1, &byte
, NULL
);
1040 output_R2_format (f
, mask
, grsave
, rlen
)
1047 mask
= (mask
& 0x0f);
1048 grsave
= (grsave
& 0x7f);
1050 bytes
[0] = (UNW_R2
| (mask
>> 1));
1051 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1052 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1053 (*f
) (count
, bytes
, NULL
);
1057 output_R3_format (f
, rtype
, rlen
)
1059 unw_record_type rtype
;
1066 output_R1_format (f
, rtype
, rlen
);
1072 else if (rtype
!= prologue
)
1073 as_bad ("record type is not valid");
1074 bytes
[0] = (UNW_R3
| r
);
1075 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1076 (*f
) (count
+ 1, bytes
, NULL
);
1080 output_P1_format (f
, brmask
)
1085 byte
= UNW_P1
| (brmask
& 0x1f);
1086 (*f
) (1, &byte
, NULL
);
1090 output_P2_format (f
, brmask
, gr
)
1096 brmask
= (brmask
& 0x1f);
1097 bytes
[0] = UNW_P2
| (brmask
>> 1);
1098 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1099 (*f
) (2, bytes
, NULL
);
1103 output_P3_format (f
, rtype
, reg
)
1105 unw_record_type rtype
;
1150 as_bad ("Invalid record type for P3 format.");
1152 bytes
[0] = (UNW_P3
| (r
>> 1));
1153 bytes
[1] = (((r
& 1) << 7) | reg
);
1154 (*f
) (2, bytes
, NULL
);
1158 output_P4_format (f
, imask
, imask_size
)
1160 unsigned char *imask
;
1161 unsigned long imask_size
;
1164 (*f
) (imask_size
, imask
, NULL
);
1168 output_P5_format (f
, grmask
, frmask
)
1171 unsigned long frmask
;
1174 grmask
= (grmask
& 0x0f);
1177 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1178 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1179 bytes
[3] = (frmask
& 0x000000ff);
1180 (*f
) (4, bytes
, NULL
);
1184 output_P6_format (f
, rtype
, rmask
)
1186 unw_record_type rtype
;
1192 if (rtype
== gr_mem
)
1194 else if (rtype
!= fr_mem
)
1195 as_bad ("Invalid record type for format P6");
1196 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1197 (*f
) (1, &byte
, NULL
);
1201 output_P7_format (f
, rtype
, w1
, w2
)
1203 unw_record_type rtype
;
1210 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1215 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1265 bytes
[0] = (UNW_P7
| r
);
1266 (*f
) (count
, bytes
, NULL
);
1270 output_P8_format (f
, rtype
, t
)
1272 unw_record_type rtype
;
1311 case bspstore_psprel
:
1314 case bspstore_sprel
:
1326 case priunat_when_gr
:
1329 case priunat_psprel
:
1335 case priunat_when_mem
:
1342 count
+= output_leb128 (bytes
+ 2, t
, 0);
1343 (*f
) (count
, bytes
, NULL
);
1347 output_P9_format (f
, grmask
, gr
)
1354 bytes
[1] = (grmask
& 0x0f);
1355 bytes
[2] = (gr
& 0x7f);
1356 (*f
) (3, bytes
, NULL
);
1360 output_P10_format (f
, abi
, context
)
1367 bytes
[1] = (abi
& 0xff);
1368 bytes
[2] = (context
& 0xff);
1369 (*f
) (3, bytes
, NULL
);
1373 output_B1_format (f
, rtype
, label
)
1375 unw_record_type rtype
;
1376 unsigned long label
;
1382 output_B4_format (f
, rtype
, label
);
1385 if (rtype
== copy_state
)
1387 else if (rtype
!= label_state
)
1388 as_bad ("Invalid record type for format B1");
1390 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1391 (*f
) (1, &byte
, NULL
);
1395 output_B2_format (f
, ecount
, t
)
1397 unsigned long ecount
;
1404 output_B3_format (f
, ecount
, t
);
1407 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1408 count
+= output_leb128 (bytes
+ 1, t
, 0);
1409 (*f
) (count
, bytes
, NULL
);
1413 output_B3_format (f
, ecount
, t
)
1415 unsigned long ecount
;
1422 output_B2_format (f
, ecount
, t
);
1426 count
+= output_leb128 (bytes
+ 1, t
, 0);
1427 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1428 (*f
) (count
, bytes
, NULL
);
1432 output_B4_format (f
, rtype
, label
)
1434 unw_record_type rtype
;
1435 unsigned long label
;
1442 output_B1_format (f
, rtype
, label
);
1446 if (rtype
== copy_state
)
1448 else if (rtype
!= label_state
)
1449 as_bad ("Invalid record type for format B1");
1451 bytes
[0] = (UNW_B4
| (r
<< 3));
1452 count
+= output_leb128 (bytes
+ 1, label
, 0);
1453 (*f
) (count
, bytes
, NULL
);
1457 format_ab_reg (ab
, reg
)
1464 ret
= (ab
<< 5) | reg
;
1469 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1471 unw_record_type rtype
;
1481 if (rtype
== spill_sprel
)
1483 else if (rtype
!= spill_psprel
)
1484 as_bad ("Invalid record type for format X1");
1485 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1486 count
+= output_leb128 (bytes
+ 2, t
, 0);
1487 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1488 (*f
) (count
, bytes
, NULL
);
1492 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1501 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1502 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1503 count
+= output_leb128 (bytes
+ 3, t
, 0);
1504 (*f
) (count
, bytes
, NULL
);
1508 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1510 unw_record_type rtype
;
1521 if (rtype
== spill_sprel_p
)
1523 else if (rtype
!= spill_psprel_p
)
1524 as_bad ("Invalid record type for format X3");
1525 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1526 bytes
[2] = format_ab_reg (ab
, reg
);
1527 count
+= output_leb128 (bytes
+ 3, t
, 0);
1528 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1529 (*f
) (count
, bytes
, NULL
);
1533 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1543 bytes
[1] = (qp
& 0x3f);
1544 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1545 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1546 count
+= output_leb128 (bytes
+ 4, t
, 0);
1547 (*f
) (count
, bytes
, NULL
);
1550 /* This function allocates a record list structure, and initializes fields. */
1552 static unw_rec_list
*
1553 alloc_record (unw_record_type t
)
1556 ptr
= xmalloc (sizeof (*ptr
));
1558 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1563 /* This function frees an entire list of record structures. */
1566 free_list_records (unw_rec_list
*first
)
1569 for (ptr
= first
; ptr
!= NULL
;)
1571 unw_rec_list
*tmp
= ptr
;
1573 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1574 && tmp
->r
.record
.r
.mask
.i
)
1575 free (tmp
->r
.record
.r
.mask
.i
);
1582 static unw_rec_list
*
1585 unw_rec_list
*ptr
= alloc_record (prologue
);
1586 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1590 static unw_rec_list
*
1591 output_prologue_gr (saved_mask
, reg
)
1592 unsigned int saved_mask
;
1595 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1596 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1597 ptr
->r
.record
.r
.grmask
= saved_mask
;
1598 ptr
->r
.record
.r
.grsave
= reg
;
1602 static unw_rec_list
*
1605 unw_rec_list
*ptr
= alloc_record (body
);
1609 static unw_rec_list
*
1610 output_mem_stack_f (size
)
1613 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1614 ptr
->r
.record
.p
.size
= size
;
1618 static unw_rec_list
*
1619 output_mem_stack_v ()
1621 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1625 static unw_rec_list
*
1629 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1630 ptr
->r
.record
.p
.gr
= gr
;
1634 static unw_rec_list
*
1635 output_psp_sprel (offset
)
1636 unsigned int offset
;
1638 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1639 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1643 static unw_rec_list
*
1646 unw_rec_list
*ptr
= alloc_record (rp_when
);
1650 static unw_rec_list
*
1654 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1655 ptr
->r
.record
.p
.gr
= gr
;
1659 static unw_rec_list
*
1663 unw_rec_list
*ptr
= alloc_record (rp_br
);
1664 ptr
->r
.record
.p
.br
= br
;
1668 static unw_rec_list
*
1669 output_rp_psprel (offset
)
1670 unsigned int offset
;
1672 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1673 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1677 static unw_rec_list
*
1678 output_rp_sprel (offset
)
1679 unsigned int offset
;
1681 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1682 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1686 static unw_rec_list
*
1689 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1693 static unw_rec_list
*
1697 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1698 ptr
->r
.record
.p
.gr
= gr
;
1702 static unw_rec_list
*
1703 output_pfs_psprel (offset
)
1704 unsigned int offset
;
1706 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1707 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1711 static unw_rec_list
*
1712 output_pfs_sprel (offset
)
1713 unsigned int offset
;
1715 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1716 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1720 static unw_rec_list
*
1721 output_preds_when ()
1723 unw_rec_list
*ptr
= alloc_record (preds_when
);
1727 static unw_rec_list
*
1728 output_preds_gr (gr
)
1731 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1732 ptr
->r
.record
.p
.gr
= gr
;
1736 static unw_rec_list
*
1737 output_preds_psprel (offset
)
1738 unsigned int offset
;
1740 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1741 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1745 static unw_rec_list
*
1746 output_preds_sprel (offset
)
1747 unsigned int offset
;
1749 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1750 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1754 static unw_rec_list
*
1755 output_fr_mem (mask
)
1758 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1759 ptr
->r
.record
.p
.rmask
= mask
;
1763 static unw_rec_list
*
1764 output_frgr_mem (gr_mask
, fr_mask
)
1765 unsigned int gr_mask
;
1766 unsigned int fr_mask
;
1768 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1769 ptr
->r
.record
.p
.grmask
= gr_mask
;
1770 ptr
->r
.record
.p
.frmask
= fr_mask
;
1774 static unw_rec_list
*
1775 output_gr_gr (mask
, reg
)
1779 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1780 ptr
->r
.record
.p
.grmask
= mask
;
1781 ptr
->r
.record
.p
.gr
= reg
;
1785 static unw_rec_list
*
1786 output_gr_mem (mask
)
1789 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1790 ptr
->r
.record
.p
.rmask
= mask
;
1794 static unw_rec_list
*
1795 output_br_mem (unsigned int mask
)
1797 unw_rec_list
*ptr
= alloc_record (br_mem
);
1798 ptr
->r
.record
.p
.brmask
= mask
;
1802 static unw_rec_list
*
1803 output_br_gr (save_mask
, reg
)
1804 unsigned int save_mask
;
1807 unw_rec_list
*ptr
= alloc_record (br_gr
);
1808 ptr
->r
.record
.p
.brmask
= save_mask
;
1809 ptr
->r
.record
.p
.gr
= reg
;
1813 static unw_rec_list
*
1814 output_spill_base (offset
)
1815 unsigned int offset
;
1817 unw_rec_list
*ptr
= alloc_record (spill_base
);
1818 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1822 static unw_rec_list
*
1825 unw_rec_list
*ptr
= alloc_record (unat_when
);
1829 static unw_rec_list
*
1833 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1834 ptr
->r
.record
.p
.gr
= gr
;
1838 static unw_rec_list
*
1839 output_unat_psprel (offset
)
1840 unsigned int offset
;
1842 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1843 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1847 static unw_rec_list
*
1848 output_unat_sprel (offset
)
1849 unsigned int offset
;
1851 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1852 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1856 static unw_rec_list
*
1859 unw_rec_list
*ptr
= alloc_record (lc_when
);
1863 static unw_rec_list
*
1867 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1868 ptr
->r
.record
.p
.gr
= gr
;
1872 static unw_rec_list
*
1873 output_lc_psprel (offset
)
1874 unsigned int offset
;
1876 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1877 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1881 static unw_rec_list
*
1882 output_lc_sprel (offset
)
1883 unsigned int offset
;
1885 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1886 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1890 static unw_rec_list
*
1893 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1897 static unw_rec_list
*
1901 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1902 ptr
->r
.record
.p
.gr
= gr
;
1906 static unw_rec_list
*
1907 output_fpsr_psprel (offset
)
1908 unsigned int offset
;
1910 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1911 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1915 static unw_rec_list
*
1916 output_fpsr_sprel (offset
)
1917 unsigned int offset
;
1919 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1920 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1924 static unw_rec_list
*
1925 output_priunat_when_gr ()
1927 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1931 static unw_rec_list
*
1932 output_priunat_when_mem ()
1934 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1938 static unw_rec_list
*
1939 output_priunat_gr (gr
)
1942 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1943 ptr
->r
.record
.p
.gr
= gr
;
1947 static unw_rec_list
*
1948 output_priunat_psprel (offset
)
1949 unsigned int offset
;
1951 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1952 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1956 static unw_rec_list
*
1957 output_priunat_sprel (offset
)
1958 unsigned int offset
;
1960 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1961 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1965 static unw_rec_list
*
1968 unw_rec_list
*ptr
= alloc_record (bsp_when
);
1972 static unw_rec_list
*
1976 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
1977 ptr
->r
.record
.p
.gr
= gr
;
1981 static unw_rec_list
*
1982 output_bsp_psprel (offset
)
1983 unsigned int offset
;
1985 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
1986 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1990 static unw_rec_list
*
1991 output_bsp_sprel (offset
)
1992 unsigned int offset
;
1994 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
1995 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1999 static unw_rec_list
*
2000 output_bspstore_when ()
2002 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2006 static unw_rec_list
*
2007 output_bspstore_gr (gr
)
2010 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2011 ptr
->r
.record
.p
.gr
= gr
;
2015 static unw_rec_list
*
2016 output_bspstore_psprel (offset
)
2017 unsigned int offset
;
2019 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2020 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2024 static unw_rec_list
*
2025 output_bspstore_sprel (offset
)
2026 unsigned int offset
;
2028 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2029 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2033 static unw_rec_list
*
2036 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2040 static unw_rec_list
*
2044 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2045 ptr
->r
.record
.p
.gr
= gr
;
2049 static unw_rec_list
*
2050 output_rnat_psprel (offset
)
2051 unsigned int offset
;
2053 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2054 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2058 static unw_rec_list
*
2059 output_rnat_sprel (offset
)
2060 unsigned int offset
;
2062 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2063 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2067 static unw_rec_list
*
2068 output_unwabi (abi
, context
)
2070 unsigned long context
;
2072 unw_rec_list
*ptr
= alloc_record (unwabi
);
2073 ptr
->r
.record
.p
.abi
= abi
;
2074 ptr
->r
.record
.p
.context
= context
;
2078 static unw_rec_list
*
2079 output_epilogue (unsigned long ecount
)
2081 unw_rec_list
*ptr
= alloc_record (epilogue
);
2082 ptr
->r
.record
.b
.ecount
= ecount
;
2086 static unw_rec_list
*
2087 output_label_state (unsigned long label
)
2089 unw_rec_list
*ptr
= alloc_record (label_state
);
2090 ptr
->r
.record
.b
.label
= label
;
2094 static unw_rec_list
*
2095 output_copy_state (unsigned long label
)
2097 unw_rec_list
*ptr
= alloc_record (copy_state
);
2098 ptr
->r
.record
.b
.label
= label
;
2102 static unw_rec_list
*
2103 output_spill_psprel (ab
, reg
, offset
)
2106 unsigned int offset
;
2108 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2109 ptr
->r
.record
.x
.ab
= ab
;
2110 ptr
->r
.record
.x
.reg
= reg
;
2111 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2115 static unw_rec_list
*
2116 output_spill_sprel (ab
, reg
, offset
)
2119 unsigned int offset
;
2121 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2122 ptr
->r
.record
.x
.ab
= ab
;
2123 ptr
->r
.record
.x
.reg
= reg
;
2124 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2128 static unw_rec_list
*
2129 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2132 unsigned int offset
;
2133 unsigned int predicate
;
2135 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2136 ptr
->r
.record
.x
.ab
= ab
;
2137 ptr
->r
.record
.x
.reg
= reg
;
2138 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2139 ptr
->r
.record
.x
.qp
= predicate
;
2143 static unw_rec_list
*
2144 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2147 unsigned int offset
;
2148 unsigned int predicate
;
2150 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2151 ptr
->r
.record
.x
.ab
= ab
;
2152 ptr
->r
.record
.x
.reg
= reg
;
2153 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2154 ptr
->r
.record
.x
.qp
= predicate
;
2158 static unw_rec_list
*
2159 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2162 unsigned int targ_reg
;
2165 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2166 ptr
->r
.record
.x
.ab
= ab
;
2167 ptr
->r
.record
.x
.reg
= reg
;
2168 ptr
->r
.record
.x
.treg
= targ_reg
;
2169 ptr
->r
.record
.x
.xy
= xy
;
2173 static unw_rec_list
*
2174 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2177 unsigned int targ_reg
;
2179 unsigned int predicate
;
2181 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2182 ptr
->r
.record
.x
.ab
= ab
;
2183 ptr
->r
.record
.x
.reg
= reg
;
2184 ptr
->r
.record
.x
.treg
= targ_reg
;
2185 ptr
->r
.record
.x
.xy
= xy
;
2186 ptr
->r
.record
.x
.qp
= predicate
;
2190 /* Given a unw_rec_list process the correct format with the
2191 specified function. */
2194 process_one_record (ptr
, f
)
2198 unsigned long fr_mask
, gr_mask
;
2200 switch (ptr
->r
.type
)
2206 /* These are taken care of by prologue/prologue_gr. */
2211 if (ptr
->r
.type
== prologue_gr
)
2212 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2213 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2215 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2217 /* Output descriptor(s) for union of register spills (if any). */
2218 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2219 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2222 if ((fr_mask
& ~0xfUL
) == 0)
2223 output_P6_format (f
, fr_mem
, fr_mask
);
2226 output_P5_format (f
, gr_mask
, fr_mask
);
2231 output_P6_format (f
, gr_mem
, gr_mask
);
2232 if (ptr
->r
.record
.r
.mask
.br_mem
)
2233 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2235 /* output imask descriptor if necessary: */
2236 if (ptr
->r
.record
.r
.mask
.i
)
2237 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2238 ptr
->r
.record
.r
.imask_size
);
2242 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2246 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2247 ptr
->r
.record
.p
.size
);
2260 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2263 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2266 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2274 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2283 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2293 case bspstore_sprel
:
2295 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2298 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2301 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2304 as_bad ("spill_mask record unimplemented.");
2306 case priunat_when_gr
:
2307 case priunat_when_mem
:
2311 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2313 case priunat_psprel
:
2315 case bspstore_psprel
:
2317 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2320 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2323 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2327 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2330 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2331 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2332 ptr
->r
.record
.x
.pspoff
);
2335 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2336 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2337 ptr
->r
.record
.x
.spoff
);
2340 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2341 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2342 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2344 case spill_psprel_p
:
2345 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2346 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2347 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2350 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2351 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2352 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2355 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2356 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2357 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2361 as_bad ("record_type_not_valid");
2366 /* Given a unw_rec_list list, process all the records with
2367 the specified function. */
2369 process_unw_records (list
, f
)
2374 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2375 process_one_record (ptr
, f
);
2378 /* Determine the size of a record list in bytes. */
2380 calc_record_size (list
)
2384 process_unw_records (list
, count_output
);
2388 /* Update IMASK bitmask to reflect the fact that one or more registers
2389 of type TYPE are saved starting at instruction with index T. If N
2390 bits are set in REGMASK, it is assumed that instructions T through
2391 T+N-1 save these registers.
2395 1: instruction saves next fp reg
2396 2: instruction saves next general reg
2397 3: instruction saves next branch reg */
2399 set_imask (region
, regmask
, t
, type
)
2400 unw_rec_list
*region
;
2401 unsigned long regmask
;
2405 unsigned char *imask
;
2406 unsigned long imask_size
;
2410 imask
= region
->r
.record
.r
.mask
.i
;
2411 imask_size
= region
->r
.record
.r
.imask_size
;
2414 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2415 imask
= xmalloc (imask_size
);
2416 memset (imask
, 0, imask_size
);
2418 region
->r
.record
.r
.imask_size
= imask_size
;
2419 region
->r
.record
.r
.mask
.i
= imask
;
2423 pos
= 2 * (3 - t
% 4);
2426 if (i
>= imask_size
)
2428 as_bad ("Ignoring attempt to spill beyond end of region");
2432 imask
[i
] |= (type
& 0x3) << pos
;
2434 regmask
&= (regmask
- 1);
2445 count_bits (unsigned long mask
)
2457 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2458 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2459 containing FIRST_ADDR. */
2462 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2463 unsigned long slot_addr
;
2465 unsigned long first_addr
;
2468 unsigned long index
= 0;
2470 /* First time we are called, the initial address and frag are invalid. */
2471 if (first_addr
== 0)
2474 /* If the two addresses are in different frags, then we need to add in
2475 the remaining size of this frag, and then the entire size of intermediate
2477 while (slot_frag
!= first_frag
)
2479 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2481 /* Add in the full size of the frag converted to instruction slots. */
2482 index
+= 3 * (first_frag
->fr_fix
>> 4);
2483 /* Subtract away the initial part before first_addr. */
2484 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2485 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2487 /* Move to the beginning of the next frag. */
2488 first_frag
= first_frag
->fr_next
;
2489 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2492 /* Add in the used part of the last frag. */
2493 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2494 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2498 /* Given a complete record list, process any records which have
2499 unresolved fields, (ie length counts for a prologue). After
2500 this has been run, all neccessary information should be available
2501 within each record to generate an image. */
2504 fixup_unw_records (list
)
2507 unw_rec_list
*ptr
, *region
= 0;
2508 unsigned long first_addr
= 0, rlen
= 0, t
;
2509 fragS
*first_frag
= 0;
2511 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2513 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2514 as_bad (" Insn slot not set in unwind record.");
2515 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2516 first_addr
, first_frag
);
2517 switch (ptr
->r
.type
)
2524 int size
, dir_len
= 0;
2525 unsigned long last_addr
;
2528 first_addr
= ptr
->slot_number
;
2529 first_frag
= ptr
->slot_frag
;
2530 ptr
->slot_number
= 0;
2531 /* Find either the next body/prologue start, or the end of
2532 the list, and determine the size of the region. */
2533 last_addr
= unwind
.next_slot_number
;
2534 last_frag
= unwind
.next_slot_frag
;
2535 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2536 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2537 || last
->r
.type
== body
)
2539 last_addr
= last
->slot_number
;
2540 last_frag
= last
->slot_frag
;
2543 else if (!last
->next
)
2545 /* In the absence of an explicit .body directive,
2546 the prologue ends after the last instruction
2547 covered by an unwind directive. */
2548 if (ptr
->r
.type
!= body
)
2550 last_addr
= last
->slot_number
;
2551 last_frag
= last
->slot_frag
;
2552 switch (last
->r
.type
)
2555 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2556 + count_bits (last
->r
.record
.p
.grmask
));
2560 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2564 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2567 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2576 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2578 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2583 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2594 case priunat_when_gr
:
2595 case priunat_when_mem
:
2599 ptr
->r
.record
.p
.t
= t
;
2607 case spill_psprel_p
:
2608 ptr
->r
.record
.x
.t
= t
;
2614 as_bad ("frgr_mem record before region record!\n");
2617 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2618 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2619 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2620 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2625 as_bad ("fr_mem record before region record!\n");
2628 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2629 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2634 as_bad ("gr_mem record before region record!\n");
2637 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2638 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2643 as_bad ("br_mem record before region record!\n");
2646 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2647 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2653 as_bad ("gr_gr record before region record!\n");
2656 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2661 as_bad ("br_gr record before region record!\n");
2664 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2673 /* Generate an unwind image from a record list. Returns the number of
2674 bytes in the resulting image. The memory image itselof is returned
2675 in the 'ptr' parameter. */
2677 output_unw_records (list
, ptr
)
2681 int size
, x
, extra
= 0;
2684 fixup_unw_records (list
);
2685 size
= calc_record_size (list
);
2687 /* pad to 8 byte boundry. */
2691 /* Add 8 for the header + 8 more bytes for the personality offset. */
2692 mem
= xmalloc (size
+ extra
+ 16);
2694 vbyte_mem_ptr
= mem
+ 8;
2695 /* Clear the padding area and personality. */
2696 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2697 /* Initialize the header area. */
2698 md_number_to_chars (mem
, (((bfd_vma
) 1 << 48) /* version */
2699 | (unwind
.personality_routine
2700 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2702 | ((size
+ extra
) / 8)), /* length (dwords) */
2705 process_unw_records (list
, output_vbyte_mem
);
2708 return size
+ extra
+ 16;
2712 convert_expr_to_ab_reg (e
, ab
, regp
)
2719 if (e
->X_op
!= O_register
)
2722 reg
= e
->X_add_number
;
2723 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2726 *regp
= reg
- REG_GR
;
2728 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2729 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2732 *regp
= reg
- REG_FR
;
2734 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2737 *regp
= reg
- REG_BR
;
2744 case REG_PR
: *regp
= 0; break;
2745 case REG_PSP
: *regp
= 1; break;
2746 case REG_PRIUNAT
: *regp
= 2; break;
2747 case REG_BR
+ 0: *regp
= 3; break;
2748 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2749 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2750 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2751 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2752 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2753 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2754 case REG_AR
+ AR_LC
: *regp
= 10; break;
2764 convert_expr_to_xy_reg (e
, xy
, regp
)
2771 if (e
->X_op
!= O_register
)
2774 reg
= e
->X_add_number
;
2776 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2779 *regp
= reg
- REG_GR
;
2781 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2784 *regp
= reg
- REG_FR
;
2786 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2789 *regp
= reg
- REG_BR
;
2798 int dummy ATTRIBUTE_UNUSED
;
2803 radix
= *input_line_pointer
++;
2805 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2807 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2808 ignore_rest_of_line ();
2813 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2815 dot_special_section (which
)
2818 set_section ((char *) special_section_name
[which
]);
2822 add_unwind_entry (ptr
)
2826 unwind
.tail
->next
= ptr
;
2831 /* The current entry can in fact be a chain of unwind entries. */
2832 if (unwind
.current_entry
== NULL
)
2833 unwind
.current_entry
= ptr
;
2838 int dummy ATTRIBUTE_UNUSED
;
2844 if (e
.X_op
!= O_constant
)
2845 as_bad ("Operand to .fframe must be a constant");
2847 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2852 int dummy ATTRIBUTE_UNUSED
;
2858 reg
= e
.X_add_number
- REG_GR
;
2859 if (e
.X_op
== O_register
&& reg
< 128)
2861 add_unwind_entry (output_mem_stack_v ());
2862 if (! (unwind
.prologue_mask
& 2))
2863 add_unwind_entry (output_psp_gr (reg
));
2866 as_bad ("First operand to .vframe must be a general register");
2870 dot_vframesp (dummy
)
2871 int dummy ATTRIBUTE_UNUSED
;
2876 if (e
.X_op
== O_constant
)
2878 add_unwind_entry (output_mem_stack_v ());
2879 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2882 as_bad ("First operand to .vframesp must be a general register");
2886 dot_vframepsp (dummy
)
2887 int dummy ATTRIBUTE_UNUSED
;
2892 if (e
.X_op
== O_constant
)
2894 add_unwind_entry (output_mem_stack_v ());
2895 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2898 as_bad ("First operand to .vframepsp must be a general register");
2903 int dummy ATTRIBUTE_UNUSED
;
2909 sep
= parse_operand (&e1
);
2911 as_bad ("No second operand to .save");
2912 sep
= parse_operand (&e2
);
2914 reg1
= e1
.X_add_number
;
2915 reg2
= e2
.X_add_number
- REG_GR
;
2917 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2918 if (e1
.X_op
== O_register
)
2920 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
2924 case REG_AR
+ AR_BSP
:
2925 add_unwind_entry (output_bsp_when ());
2926 add_unwind_entry (output_bsp_gr (reg2
));
2928 case REG_AR
+ AR_BSPSTORE
:
2929 add_unwind_entry (output_bspstore_when ());
2930 add_unwind_entry (output_bspstore_gr (reg2
));
2932 case REG_AR
+ AR_RNAT
:
2933 add_unwind_entry (output_rnat_when ());
2934 add_unwind_entry (output_rnat_gr (reg2
));
2936 case REG_AR
+ AR_UNAT
:
2937 add_unwind_entry (output_unat_when ());
2938 add_unwind_entry (output_unat_gr (reg2
));
2940 case REG_AR
+ AR_FPSR
:
2941 add_unwind_entry (output_fpsr_when ());
2942 add_unwind_entry (output_fpsr_gr (reg2
));
2944 case REG_AR
+ AR_PFS
:
2945 add_unwind_entry (output_pfs_when ());
2946 if (! (unwind
.prologue_mask
& 4))
2947 add_unwind_entry (output_pfs_gr (reg2
));
2949 case REG_AR
+ AR_LC
:
2950 add_unwind_entry (output_lc_when ());
2951 add_unwind_entry (output_lc_gr (reg2
));
2954 add_unwind_entry (output_rp_when ());
2955 if (! (unwind
.prologue_mask
& 8))
2956 add_unwind_entry (output_rp_gr (reg2
));
2959 add_unwind_entry (output_preds_when ());
2960 if (! (unwind
.prologue_mask
& 1))
2961 add_unwind_entry (output_preds_gr (reg2
));
2964 add_unwind_entry (output_priunat_when_gr ());
2965 add_unwind_entry (output_priunat_gr (reg2
));
2968 as_bad ("First operand not a valid register");
2972 as_bad (" Second operand not a valid register");
2975 as_bad ("First operand not a register");
2980 int dummy ATTRIBUTE_UNUSED
;
2983 unsigned long ecount
= 0;
2986 sep
= parse_operand (&e1
);
2987 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
2989 as_bad ("First operand to .restore must be stack pointer (sp)");
2995 parse_operand (&e2
);
2996 if (e1
.X_op
!= O_constant
)
2998 as_bad ("Second operand to .restore must be constant");
3003 add_unwind_entry (output_epilogue (ecount
));
3007 dot_restorereg (dummy
)
3008 int dummy ATTRIBUTE_UNUSED
;
3010 unsigned int ab
, reg
;
3015 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3017 as_bad ("First operand to .restorereg must be a preserved register");
3020 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3024 dot_restorereg_p (dummy
)
3025 int dummy ATTRIBUTE_UNUSED
;
3027 unsigned int qp
, ab
, reg
;
3031 sep
= parse_operand (&e1
);
3034 as_bad ("No second operand to .restorereg.p");
3038 parse_operand (&e2
);
3040 qp
= e1
.X_add_number
- REG_P
;
3041 if (e1
.X_op
!= O_register
|| qp
> 63)
3043 as_bad ("First operand to .restorereg.p must be a predicate");
3047 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3049 as_bad ("Second operand to .restorereg.p must be a preserved register");
3052 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3056 generate_unwind_image ()
3059 unsigned char *unw_rec
;
3061 /* Force out pending instructions, to make sure all unwind records have
3062 a valid slot_number field. */
3063 ia64_flush_insns ();
3065 /* Generate the unwind record. */
3066 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3068 as_bad ("Unwind record is not a multiple of 8 bytes.");
3070 /* If there are unwind records, switch sections, and output the info. */
3073 unsigned char *where
;
3075 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND_INFO
]);
3077 /* Make sure the section has 8 byte alignment. */
3078 record_alignment (now_seg
, 3);
3080 /* Set expression which points to start of unwind descriptor area. */
3081 unwind
.info
= expr_build_dot ();
3083 where
= (unsigned char *) frag_more (size
);
3085 /* Issue a label for this address, and keep track of it to put it
3086 in the unwind section. */
3088 /* Copy the information from the unwind record into this section. The
3089 data is already in the correct byte order. */
3090 memcpy (where
, unw_rec
, size
);
3091 /* Add the personality address to the image. */
3092 if (unwind
.personality_routine
!= 0)
3094 exp
.X_op
= O_symbol
;
3095 exp
.X_add_symbol
= unwind
.personality_routine
;
3096 exp
.X_add_number
= 0;
3097 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3098 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3099 unwind
.personality_routine
= 0;
3101 obj_elf_previous (0);
3104 free_list_records (unwind
.list
);
3105 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3111 dot_handlerdata (dummy
)
3112 int dummy ATTRIBUTE_UNUSED
;
3114 generate_unwind_image ();
3115 demand_empty_rest_of_line ();
3119 dot_unwentry (dummy
)
3120 int dummy ATTRIBUTE_UNUSED
;
3122 demand_empty_rest_of_line ();
3127 int dummy ATTRIBUTE_UNUSED
;
3133 reg
= e
.X_add_number
- REG_BR
;
3134 if (e
.X_op
== O_register
&& reg
< 8)
3135 add_unwind_entry (output_rp_br (reg
));
3137 as_bad ("First operand not a valid branch register");
3141 dot_savemem (psprel
)
3148 sep
= parse_operand (&e1
);
3150 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3151 sep
= parse_operand (&e2
);
3153 reg1
= e1
.X_add_number
;
3154 val
= e2
.X_add_number
;
3156 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3157 if (e1
.X_op
== O_register
)
3159 if (e2
.X_op
== O_constant
)
3163 case REG_AR
+ AR_BSP
:
3164 add_unwind_entry (output_bsp_when ());
3165 add_unwind_entry ((psprel
3167 : output_bsp_sprel
) (val
));
3169 case REG_AR
+ AR_BSPSTORE
:
3170 add_unwind_entry (output_bspstore_when ());
3171 add_unwind_entry ((psprel
3172 ? output_bspstore_psprel
3173 : output_bspstore_sprel
) (val
));
3175 case REG_AR
+ AR_RNAT
:
3176 add_unwind_entry (output_rnat_when ());
3177 add_unwind_entry ((psprel
3178 ? output_rnat_psprel
3179 : output_rnat_sprel
) (val
));
3181 case REG_AR
+ AR_UNAT
:
3182 add_unwind_entry (output_unat_when ());
3183 add_unwind_entry ((psprel
3184 ? output_unat_psprel
3185 : output_unat_sprel
) (val
));
3187 case REG_AR
+ AR_FPSR
:
3188 add_unwind_entry (output_fpsr_when ());
3189 add_unwind_entry ((psprel
3190 ? output_fpsr_psprel
3191 : output_fpsr_sprel
) (val
));
3193 case REG_AR
+ AR_PFS
:
3194 add_unwind_entry (output_pfs_when ());
3195 add_unwind_entry ((psprel
3197 : output_pfs_sprel
) (val
));
3199 case REG_AR
+ AR_LC
:
3200 add_unwind_entry (output_lc_when ());
3201 add_unwind_entry ((psprel
3203 : output_lc_sprel
) (val
));
3206 add_unwind_entry (output_rp_when ());
3207 add_unwind_entry ((psprel
3209 : output_rp_sprel
) (val
));
3212 add_unwind_entry (output_preds_when ());
3213 add_unwind_entry ((psprel
3214 ? output_preds_psprel
3215 : output_preds_sprel
) (val
));
3218 add_unwind_entry (output_priunat_when_mem ());
3219 add_unwind_entry ((psprel
3220 ? output_priunat_psprel
3221 : output_priunat_sprel
) (val
));
3224 as_bad ("First operand not a valid register");
3228 as_bad (" Second operand not a valid constant");
3231 as_bad ("First operand not a register");
3236 int dummy ATTRIBUTE_UNUSED
;
3240 sep
= parse_operand (&e1
);
3242 parse_operand (&e2
);
3244 if (e1
.X_op
!= O_constant
)
3245 as_bad ("First operand to .save.g must be a constant.");
3248 int grmask
= e1
.X_add_number
;
3250 add_unwind_entry (output_gr_mem (grmask
));
3253 int reg
= e2
.X_add_number
- REG_GR
;
3254 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3255 add_unwind_entry (output_gr_gr (grmask
, reg
));
3257 as_bad ("Second operand is an invalid register.");
3264 int dummy ATTRIBUTE_UNUSED
;
3268 sep
= parse_operand (&e1
);
3270 if (e1
.X_op
!= O_constant
)
3271 as_bad ("Operand to .save.f must be a constant.");
3273 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3278 int dummy ATTRIBUTE_UNUSED
;
3285 sep
= parse_operand (&e1
);
3286 if (e1
.X_op
!= O_constant
)
3288 as_bad ("First operand to .save.b must be a constant.");
3291 brmask
= e1
.X_add_number
;
3295 sep
= parse_operand (&e2
);
3296 reg
= e2
.X_add_number
- REG_GR
;
3297 if (e2
.X_op
!= O_register
|| reg
> 127)
3299 as_bad ("Second operand to .save.b must be a general register.");
3302 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3305 add_unwind_entry (output_br_mem (brmask
));
3307 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3308 ignore_rest_of_line ();
3313 int dummy ATTRIBUTE_UNUSED
;
3317 sep
= parse_operand (&e1
);
3319 parse_operand (&e2
);
3321 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3322 as_bad ("Both operands of .save.gf must be constants.");
3325 int grmask
= e1
.X_add_number
;
3326 int frmask
= e2
.X_add_number
;
3327 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3333 int dummy ATTRIBUTE_UNUSED
;
3338 sep
= parse_operand (&e
);
3339 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3340 ignore_rest_of_line ();
3342 if (e
.X_op
!= O_constant
)
3343 as_bad ("Operand to .spill must be a constant");
3345 add_unwind_entry (output_spill_base (e
.X_add_number
));
3349 dot_spillreg (dummy
)
3350 int dummy ATTRIBUTE_UNUSED
;
3352 int sep
, ab
, xy
, reg
, treg
;
3355 sep
= parse_operand (&e1
);
3358 as_bad ("No second operand to .spillreg");
3362 parse_operand (&e2
);
3364 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3366 as_bad ("First operand to .spillreg must be a preserved register");
3370 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3372 as_bad ("Second operand to .spillreg must be a register");
3376 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3380 dot_spillmem (psprel
)
3386 sep
= parse_operand (&e1
);
3389 as_bad ("Second operand missing");
3393 parse_operand (&e2
);
3395 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3397 as_bad ("First operand to .spill%s must be a preserved register",
3398 psprel
? "psp" : "sp");
3402 if (e2
.X_op
!= O_constant
)
3404 as_bad ("Second operand to .spill%s must be a constant",
3405 psprel
? "psp" : "sp");
3410 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3412 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3416 dot_spillreg_p (dummy
)
3417 int dummy ATTRIBUTE_UNUSED
;
3419 int sep
, ab
, xy
, reg
, treg
;
3420 expressionS e1
, e2
, e3
;
3423 sep
= parse_operand (&e1
);
3426 as_bad ("No second and third operand to .spillreg.p");
3430 sep
= parse_operand (&e2
);
3433 as_bad ("No third operand to .spillreg.p");
3437 parse_operand (&e3
);
3439 qp
= e1
.X_add_number
- REG_P
;
3441 if (e1
.X_op
!= O_register
|| qp
> 63)
3443 as_bad ("First operand to .spillreg.p must be a predicate");
3447 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3449 as_bad ("Second operand to .spillreg.p must be a preserved register");
3453 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3455 as_bad ("Third operand to .spillreg.p must be a register");
3459 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3463 dot_spillmem_p (psprel
)
3466 expressionS e1
, e2
, e3
;
3470 sep
= parse_operand (&e1
);
3473 as_bad ("Second operand missing");
3477 parse_operand (&e2
);
3480 as_bad ("Second operand missing");
3484 parse_operand (&e3
);
3486 qp
= e1
.X_add_number
- REG_P
;
3487 if (e1
.X_op
!= O_register
|| qp
> 63)
3489 as_bad ("First operand to .spill%s_p must be a predicate",
3490 psprel
? "psp" : "sp");
3494 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3496 as_bad ("Second operand to .spill%s_p must be a preserved register",
3497 psprel
? "psp" : "sp");
3501 if (e3
.X_op
!= O_constant
)
3503 as_bad ("Third operand to .spill%s_p must be a constant",
3504 psprel
? "psp" : "sp");
3509 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3511 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3515 dot_label_state (dummy
)
3516 int dummy ATTRIBUTE_UNUSED
;
3521 if (e
.X_op
!= O_constant
)
3523 as_bad ("Operand to .label_state must be a constant");
3526 add_unwind_entry (output_label_state (e
.X_add_number
));
3530 dot_copy_state (dummy
)
3531 int dummy ATTRIBUTE_UNUSED
;
3536 if (e
.X_op
!= O_constant
)
3538 as_bad ("Operand to .copy_state must be a constant");
3541 add_unwind_entry (output_copy_state (e
.X_add_number
));
3546 int dummy ATTRIBUTE_UNUSED
;
3551 sep
= parse_operand (&e1
);
3554 as_bad ("Second operand to .unwabi missing");
3557 sep
= parse_operand (&e2
);
3558 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3559 ignore_rest_of_line ();
3561 if (e1
.X_op
!= O_constant
)
3563 as_bad ("First operand to .unwabi must be a constant");
3567 if (e2
.X_op
!= O_constant
)
3569 as_bad ("Second operand to .unwabi must be a constant");
3573 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3577 dot_personality (dummy
)
3578 int dummy ATTRIBUTE_UNUSED
;
3582 name
= input_line_pointer
;
3583 c
= get_symbol_end ();
3584 p
= input_line_pointer
;
3585 unwind
.personality_routine
= symbol_find_or_make (name
);
3588 demand_empty_rest_of_line ();
3593 int dummy ATTRIBUTE_UNUSED
;
3598 unwind
.proc_start
= expr_build_dot ();
3599 /* Parse names of main and alternate entry points and mark them as
3600 function symbols: */
3604 name
= input_line_pointer
;
3605 c
= get_symbol_end ();
3606 p
= input_line_pointer
;
3607 sym
= symbol_find_or_make (name
);
3608 if (unwind
.proc_start
== 0)
3610 unwind
.proc_start
= sym
;
3612 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3615 if (*input_line_pointer
!= ',')
3617 ++input_line_pointer
;
3619 demand_empty_rest_of_line ();
3622 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3623 unwind
.personality_routine
= 0;
3628 int dummy ATTRIBUTE_UNUSED
;
3630 unwind
.prologue
= 0;
3631 unwind
.prologue_mask
= 0;
3633 add_unwind_entry (output_body ());
3634 demand_empty_rest_of_line ();
3638 dot_prologue (dummy
)
3639 int dummy ATTRIBUTE_UNUSED
;
3642 int mask
= 0, grsave
= 0;
3644 if (!is_it_end_of_statement ())
3647 sep
= parse_operand (&e1
);
3649 as_bad ("No second operand to .prologue");
3650 sep
= parse_operand (&e2
);
3651 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3652 ignore_rest_of_line ();
3654 if (e1
.X_op
== O_constant
)
3656 mask
= e1
.X_add_number
;
3658 if (e2
.X_op
== O_constant
)
3659 grsave
= e2
.X_add_number
;
3660 else if (e2
.X_op
== O_register
3661 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3664 as_bad ("Second operand not a constant or general register");
3666 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3669 as_bad ("First operand not a constant");
3672 add_unwind_entry (output_prologue ());
3674 unwind
.prologue
= 1;
3675 unwind
.prologue_mask
= mask
;
3680 int dummy ATTRIBUTE_UNUSED
;
3684 int bytes_per_address
;
3687 subsegT saved_subseg
;
3689 saved_seg
= now_seg
;
3690 saved_subseg
= now_subseg
;
3693 demand_empty_rest_of_line ();
3695 insn_group_break (1, 0, 0);
3697 /* If there was a .handlerdata, we haven't generated an image yet. */
3698 if (unwind
.info
== 0)
3700 generate_unwind_image ();
3703 subseg_set (md
.last_text_seg
, 0);
3704 unwind
.proc_end
= expr_build_dot ();
3706 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND
]);
3708 /* Make sure the section has 8 byte alignment. */
3709 record_alignment (now_seg
, 3);
3711 ptr
= frag_more (24);
3712 where
= frag_now_fix () - 24;
3713 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3715 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3716 e
.X_op
= O_pseudo_fixup
;
3717 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3719 e
.X_add_symbol
= unwind
.proc_start
;
3720 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3722 e
.X_op
= O_pseudo_fixup
;
3723 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3725 e
.X_add_symbol
= unwind
.proc_end
;
3726 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
, bytes_per_address
, &e
);
3728 if (unwind
.info
!= 0)
3730 e
.X_op
= O_pseudo_fixup
;
3731 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3733 e
.X_add_symbol
= unwind
.info
;
3734 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2), bytes_per_address
, &e
);
3737 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0, bytes_per_address
);
3739 subseg_set (saved_seg
, saved_subseg
);
3740 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3744 dot_template (template)
3747 CURR_SLOT
.user_template
= template;
3752 int dummy ATTRIBUTE_UNUSED
;
3754 int ins
, locs
, outs
, rots
;
3756 if (is_it_end_of_statement ())
3757 ins
= locs
= outs
= rots
= 0;
3760 ins
= get_absolute_expression ();
3761 if (*input_line_pointer
++ != ',')
3763 locs
= get_absolute_expression ();
3764 if (*input_line_pointer
++ != ',')
3766 outs
= get_absolute_expression ();
3767 if (*input_line_pointer
++ != ',')
3769 rots
= get_absolute_expression ();
3771 set_regstack (ins
, locs
, outs
, rots
);
3775 as_bad ("Comma expected");
3776 ignore_rest_of_line ();
3783 unsigned num_regs
, num_alloced
= 0;
3784 struct dynreg
**drpp
, *dr
;
3785 int ch
, base_reg
= 0;
3791 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3792 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3793 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3797 /* First, remove existing names from hash table. */
3798 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3800 hash_delete (md
.dynreg_hash
, dr
->name
);
3804 drpp
= &md
.dynreg
[type
];
3807 start
= input_line_pointer
;
3808 ch
= get_symbol_end ();
3809 *input_line_pointer
= ch
;
3810 len
= (input_line_pointer
- start
);
3813 if (*input_line_pointer
!= '[')
3815 as_bad ("Expected '['");
3818 ++input_line_pointer
; /* skip '[' */
3820 num_regs
= get_absolute_expression ();
3822 if (*input_line_pointer
++ != ']')
3824 as_bad ("Expected ']'");
3829 num_alloced
+= num_regs
;
3833 if (num_alloced
> md
.rot
.num_regs
)
3835 as_bad ("Used more than the declared %d rotating registers",
3841 if (num_alloced
> 96)
3843 as_bad ("Used more than the available 96 rotating registers");
3848 if (num_alloced
> 48)
3850 as_bad ("Used more than the available 48 rotating registers");
3859 name
= obstack_alloc (¬es
, len
+ 1);
3860 memcpy (name
, start
, len
);
3865 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
3866 memset (*drpp
, 0, sizeof (*dr
));
3871 dr
->num_regs
= num_regs
;
3872 dr
->base
= base_reg
;
3874 base_reg
+= num_regs
;
3876 if (hash_insert (md
.dynreg_hash
, name
, dr
))
3878 as_bad ("Attempt to redefine register set `%s'", name
);
3882 if (*input_line_pointer
!= ',')
3884 ++input_line_pointer
; /* skip comma */
3887 demand_empty_rest_of_line ();
3891 ignore_rest_of_line ();
3895 dot_byteorder (byteorder
)
3898 target_big_endian
= byteorder
;
3903 int dummy ATTRIBUTE_UNUSED
;
3910 option
= input_line_pointer
;
3911 ch
= get_symbol_end ();
3912 if (strcmp (option
, "lsb") == 0)
3913 md
.flags
&= ~EF_IA_64_BE
;
3914 else if (strcmp (option
, "msb") == 0)
3915 md
.flags
|= EF_IA_64_BE
;
3916 else if (strcmp (option
, "abi32") == 0)
3917 md
.flags
&= ~EF_IA_64_ABI64
;
3918 else if (strcmp (option
, "abi64") == 0)
3919 md
.flags
|= EF_IA_64_ABI64
;
3921 as_bad ("Unknown psr option `%s'", option
);
3922 *input_line_pointer
= ch
;
3925 if (*input_line_pointer
!= ',')
3928 ++input_line_pointer
;
3931 demand_empty_rest_of_line ();
3936 int dummy ATTRIBUTE_UNUSED
;
3938 as_bad (".alias not implemented yet");
3943 int dummy ATTRIBUTE_UNUSED
;
3945 new_logical_line (0, get_absolute_expression ());
3946 demand_empty_rest_of_line ();
3950 parse_section_name ()
3956 if (*input_line_pointer
!= '"')
3958 as_bad ("Missing section name");
3959 ignore_rest_of_line ();
3962 name
= demand_copy_C_string (&len
);
3965 ignore_rest_of_line ();
3969 if (*input_line_pointer
!= ',')
3971 as_bad ("Comma expected after section name");
3972 ignore_rest_of_line ();
3975 ++input_line_pointer
; /* skip comma */
3983 char *name
= parse_section_name ();
3989 obj_elf_previous (0);
3992 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3995 stmt_float_cons (kind
)
4002 case 'd': size
= 8; break;
4003 case 'x': size
= 10; break;
4010 ia64_do_align (size
);
4018 int saved_auto_align
= md
.auto_align
;
4022 md
.auto_align
= saved_auto_align
;
4026 dot_xfloat_cons (kind
)
4029 char *name
= parse_section_name ();
4034 stmt_float_cons (kind
);
4035 obj_elf_previous (0);
4039 dot_xstringer (zero
)
4042 char *name
= parse_section_name ();
4048 obj_elf_previous (0);
4055 int saved_auto_align
= md
.auto_align
;
4056 char *name
= parse_section_name ();
4063 md
.auto_align
= saved_auto_align
;
4064 obj_elf_previous (0);
4068 dot_xfloat_cons_ua (kind
)
4071 int saved_auto_align
= md
.auto_align
;
4072 char *name
= parse_section_name ();
4078 stmt_float_cons (kind
);
4079 md
.auto_align
= saved_auto_align
;
4080 obj_elf_previous (0);
4083 /* .reg.val <regname>,value */
4087 int dummy ATTRIBUTE_UNUSED
;
4092 if (reg
.X_op
!= O_register
)
4094 as_bad (_("Register name expected"));
4095 ignore_rest_of_line ();
4097 else if (*input_line_pointer
++ != ',')
4099 as_bad (_("Comma expected"));
4100 ignore_rest_of_line ();
4104 valueT value
= get_absolute_expression ();
4105 int regno
= reg
.X_add_number
;
4106 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4107 as_warn (_("Register value annotation ignored"));
4110 gr_values
[regno
- REG_GR
].known
= 1;
4111 gr_values
[regno
- REG_GR
].value
= value
;
4112 gr_values
[regno
- REG_GR
].path
= md
.path
;
4115 demand_empty_rest_of_line ();
4118 /* select dv checking mode
4123 A stop is inserted when changing modes
4130 if (md
.manual_bundling
)
4131 as_warn (_("Directive invalid within a bundle"));
4133 if (type
== 'E' || type
== 'A')
4134 md
.mode_explicitly_set
= 0;
4136 md
.mode_explicitly_set
= 1;
4143 if (md
.explicit_mode
)
4144 insn_group_break (1, 0, 0);
4145 md
.explicit_mode
= 0;
4149 if (!md
.explicit_mode
)
4150 insn_group_break (1, 0, 0);
4151 md
.explicit_mode
= 1;
4155 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4156 insn_group_break (1, 0, 0);
4157 md
.explicit_mode
= md
.default_explicit_mode
;
4158 md
.mode_explicitly_set
= 0;
4169 for (regno
= 0; regno
< 64; regno
++)
4171 if (mask
& ((valueT
) 1 << regno
))
4173 fprintf (stderr
, "%s p%d", comma
, regno
);
4180 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4181 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4182 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4183 .pred.safe_across_calls p1 [, p2 [,...]]
4192 int p1
= -1, p2
= -1;
4196 if (*input_line_pointer
!= '"')
4198 as_bad (_("Missing predicate relation type"));
4199 ignore_rest_of_line ();
4205 char *form
= demand_copy_C_string (&len
);
4206 if (strcmp (form
, "mutex") == 0)
4208 else if (strcmp (form
, "clear") == 0)
4210 else if (strcmp (form
, "imply") == 0)
4214 as_bad (_("Unrecognized predicate relation type"));
4215 ignore_rest_of_line ();
4219 if (*input_line_pointer
== ',')
4220 ++input_line_pointer
;
4230 if (toupper (*input_line_pointer
) != 'P'
4231 || (regno
= atoi (++input_line_pointer
)) < 0
4234 as_bad (_("Predicate register expected"));
4235 ignore_rest_of_line ();
4238 while (isdigit (*input_line_pointer
))
4239 ++input_line_pointer
;
4246 as_warn (_("Duplicate predicate register ignored"));
4249 /* See if it's a range. */
4250 if (*input_line_pointer
== '-')
4253 ++input_line_pointer
;
4255 if (toupper (*input_line_pointer
) != 'P'
4256 || (regno
= atoi (++input_line_pointer
)) < 0
4259 as_bad (_("Predicate register expected"));
4260 ignore_rest_of_line ();
4263 while (isdigit (*input_line_pointer
))
4264 ++input_line_pointer
;
4268 as_bad (_("Bad register range"));
4269 ignore_rest_of_line ();
4280 if (*input_line_pointer
!= ',')
4282 ++input_line_pointer
;
4291 clear_qp_mutex (mask
);
4292 clear_qp_implies (mask
, (valueT
) 0);
4295 if (count
!= 2 || p1
== -1 || p2
== -1)
4296 as_bad (_("Predicate source and target required"));
4297 else if (p1
== 0 || p2
== 0)
4298 as_bad (_("Use of p0 is not valid in this context"));
4300 add_qp_imply (p1
, p2
);
4305 as_bad (_("At least two PR arguments expected"));
4310 as_bad (_("Use of p0 is not valid in this context"));
4313 add_qp_mutex (mask
);
4316 /* note that we don't override any existing relations */
4319 as_bad (_("At least one PR argument expected"));
4324 fprintf (stderr
, "Safe across calls: ");
4325 print_prmask (mask
);
4326 fprintf (stderr
, "\n");
4328 qp_safe_across_calls
= mask
;
4331 demand_empty_rest_of_line ();
4334 /* .entry label [, label [, ...]]
4335 Hint to DV code that the given labels are to be considered entry points.
4336 Otherwise, only global labels are considered entry points. */
4340 int dummy ATTRIBUTE_UNUSED
;
4349 name
= input_line_pointer
;
4350 c
= get_symbol_end ();
4351 symbolP
= symbol_find_or_make (name
);
4353 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4355 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4358 *input_line_pointer
= c
;
4360 c
= *input_line_pointer
;
4363 input_line_pointer
++;
4365 if (*input_line_pointer
== '\n')
4371 demand_empty_rest_of_line ();
4374 /* .mem.offset offset, base
4375 "base" is used to distinguish between offsets from a different base. */
4378 dot_mem_offset (dummy
)
4379 int dummy ATTRIBUTE_UNUSED
;
4381 md
.mem_offset
.hint
= 1;
4382 md
.mem_offset
.offset
= get_absolute_expression ();
4383 if (*input_line_pointer
!= ',')
4385 as_bad (_("Comma expected"));
4386 ignore_rest_of_line ();
4389 ++input_line_pointer
;
4390 md
.mem_offset
.base
= get_absolute_expression ();
4391 demand_empty_rest_of_line ();
4394 /* ia64-specific pseudo-ops: */
4395 const pseudo_typeS md_pseudo_table
[] =
4397 { "radix", dot_radix
, 0 },
4398 { "lcomm", s_lcomm_bytes
, 1 },
4399 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4400 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4401 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4402 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4403 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4404 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4405 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4406 { "proc", dot_proc
, 0 },
4407 { "body", dot_body
, 0 },
4408 { "prologue", dot_prologue
, 0 },
4409 { "endp", dot_endp
, 0 },
4410 { "file", dwarf2_directive_file
, 0 },
4411 { "loc", dwarf2_directive_loc
, 0 },
4413 { "fframe", dot_fframe
, 0 },
4414 { "vframe", dot_vframe
, 0 },
4415 { "vframesp", dot_vframesp
, 0 },
4416 { "vframepsp", dot_vframepsp
, 0 },
4417 { "save", dot_save
, 0 },
4418 { "restore", dot_restore
, 0 },
4419 { "restorereg", dot_restorereg
, 0 },
4420 { "restorereg.p", dot_restorereg_p
, 0 },
4421 { "handlerdata", dot_handlerdata
, 0 },
4422 { "unwentry", dot_unwentry
, 0 },
4423 { "altrp", dot_altrp
, 0 },
4424 { "savesp", dot_savemem
, 0 },
4425 { "savepsp", dot_savemem
, 1 },
4426 { "save.g", dot_saveg
, 0 },
4427 { "save.f", dot_savef
, 0 },
4428 { "save.b", dot_saveb
, 0 },
4429 { "save.gf", dot_savegf
, 0 },
4430 { "spill", dot_spill
, 0 },
4431 { "spillreg", dot_spillreg
, 0 },
4432 { "spillsp", dot_spillmem
, 0 },
4433 { "spillpsp", dot_spillmem
, 1 },
4434 { "spillreg.p", dot_spillreg_p
, 0 },
4435 { "spillsp.p", dot_spillmem_p
, 0 },
4436 { "spillpsp.p", dot_spillmem_p
, 1 },
4437 { "label_state", dot_label_state
, 0 },
4438 { "copy_state", dot_copy_state
, 0 },
4439 { "unwabi", dot_unwabi
, 0 },
4440 { "personality", dot_personality
, 0 },
4442 { "estate", dot_estate
, 0 },
4444 { "mii", dot_template
, 0x0 },
4445 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4446 { "mlx", dot_template
, 0x2 },
4447 { "mmi", dot_template
, 0x4 },
4448 { "mfi", dot_template
, 0x6 },
4449 { "mmf", dot_template
, 0x7 },
4450 { "mib", dot_template
, 0x8 },
4451 { "mbb", dot_template
, 0x9 },
4452 { "bbb", dot_template
, 0xb },
4453 { "mmb", dot_template
, 0xc },
4454 { "mfb", dot_template
, 0xe },
4456 { "lb", dot_scope
, 0 },
4457 { "le", dot_scope
, 1 },
4459 { "align", s_align_bytes
, 0 },
4460 { "regstk", dot_regstk
, 0 },
4461 { "rotr", dot_rot
, DYNREG_GR
},
4462 { "rotf", dot_rot
, DYNREG_FR
},
4463 { "rotp", dot_rot
, DYNREG_PR
},
4464 { "lsb", dot_byteorder
, 0 },
4465 { "msb", dot_byteorder
, 1 },
4466 { "psr", dot_psr
, 0 },
4467 { "alias", dot_alias
, 0 },
4468 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4470 { "xdata1", dot_xdata
, 1 },
4471 { "xdata2", dot_xdata
, 2 },
4472 { "xdata4", dot_xdata
, 4 },
4473 { "xdata8", dot_xdata
, 8 },
4474 { "xreal4", dot_xfloat_cons
, 'f' },
4475 { "xreal8", dot_xfloat_cons
, 'd' },
4476 { "xreal10", dot_xfloat_cons
, 'x' },
4477 { "xstring", dot_xstringer
, 0 },
4478 { "xstringz", dot_xstringer
, 1 },
4480 /* unaligned versions: */
4481 { "xdata2.ua", dot_xdata_ua
, 2 },
4482 { "xdata4.ua", dot_xdata_ua
, 4 },
4483 { "xdata8.ua", dot_xdata_ua
, 8 },
4484 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4485 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4486 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4488 /* annotations/DV checking support */
4489 { "entry", dot_entry
, 0 },
4490 { "mem.offset", dot_mem_offset
, 0 },
4491 { "pred.rel", dot_pred_rel
, 0 },
4492 { "pred.rel.clear", dot_pred_rel
, 'c' },
4493 { "pred.rel.imply", dot_pred_rel
, 'i' },
4494 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4495 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4496 { "reg.val", dot_reg_val
, 0 },
4497 { "auto", dot_dv_mode
, 'a' },
4498 { "explicit", dot_dv_mode
, 'e' },
4499 { "default", dot_dv_mode
, 'd' },
4504 static const struct pseudo_opcode
4507 void (*handler
) (int);
4512 /* these are more like pseudo-ops, but don't start with a dot */
4513 { "data1", cons
, 1 },
4514 { "data2", cons
, 2 },
4515 { "data4", cons
, 4 },
4516 { "data8", cons
, 8 },
4517 { "real4", stmt_float_cons
, 'f' },
4518 { "real8", stmt_float_cons
, 'd' },
4519 { "real10", stmt_float_cons
, 'x' },
4520 { "string", stringer
, 0 },
4521 { "stringz", stringer
, 1 },
4523 /* unaligned versions: */
4524 { "data2.ua", stmt_cons_ua
, 2 },
4525 { "data4.ua", stmt_cons_ua
, 4 },
4526 { "data8.ua", stmt_cons_ua
, 8 },
4527 { "real4.ua", float_cons
, 'f' },
4528 { "real8.ua", float_cons
, 'd' },
4529 { "real10.ua", float_cons
, 'x' },
4532 /* Declare a register by creating a symbol for it and entering it in
4533 the symbol table. */
4536 declare_register (name
, regnum
)
4543 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4545 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4547 as_fatal ("Inserting \"%s\" into register table failed: %s",
4554 declare_register_set (prefix
, num_regs
, base_regnum
)
4562 for (i
= 0; i
< num_regs
; ++i
)
4564 sprintf (name
, "%s%u", prefix
, i
);
4565 declare_register (name
, base_regnum
+ i
);
4570 operand_width (opnd
)
4571 enum ia64_opnd opnd
;
4573 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4574 unsigned int bits
= 0;
4578 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4579 bits
+= odesc
->field
[i
].bits
;
4585 operand_match (idesc
, index
, e
)
4586 const struct ia64_opcode
*idesc
;
4590 enum ia64_opnd opnd
= idesc
->operands
[index
];
4591 int bits
, relocatable
= 0;
4592 struct insn_fix
*fix
;
4599 case IA64_OPND_AR_CCV
:
4600 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4604 case IA64_OPND_AR_PFS
:
4605 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4610 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4615 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4620 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4624 case IA64_OPND_PR_ROT
:
4625 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4630 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4634 case IA64_OPND_PSR_L
:
4635 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4639 case IA64_OPND_PSR_UM
:
4640 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4645 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4650 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4655 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4659 /* register operands: */
4662 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4663 && e
->X_add_number
< REG_AR
+ 128)
4669 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4670 && e
->X_add_number
< REG_BR
+ 8)
4675 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4676 && e
->X_add_number
< REG_CR
+ 128)
4684 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4685 && e
->X_add_number
< REG_FR
+ 128)
4691 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4692 && e
->X_add_number
< REG_P
+ 64)
4699 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4700 && e
->X_add_number
< REG_GR
+ 128)
4704 case IA64_OPND_R3_2
:
4705 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4706 && e
->X_add_number
< REG_GR
+ 4)
4710 /* indirect operands: */
4711 case IA64_OPND_CPUID_R3
:
4712 case IA64_OPND_DBR_R3
:
4713 case IA64_OPND_DTR_R3
:
4714 case IA64_OPND_ITR_R3
:
4715 case IA64_OPND_IBR_R3
:
4716 case IA64_OPND_MSR_R3
:
4717 case IA64_OPND_PKR_R3
:
4718 case IA64_OPND_PMC_R3
:
4719 case IA64_OPND_PMD_R3
:
4720 case IA64_OPND_RR_R3
:
4721 if (e
->X_op
== O_index
&& e
->X_op_symbol
4722 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4723 == opnd
- IA64_OPND_CPUID_R3
))
4728 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4732 /* immediate operands: */
4733 case IA64_OPND_CNT2a
:
4734 case IA64_OPND_LEN4
:
4735 case IA64_OPND_LEN6
:
4736 bits
= operand_width (idesc
->operands
[index
]);
4737 if (e
->X_op
== O_constant
4738 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4742 case IA64_OPND_CNT2b
:
4743 if (e
->X_op
== O_constant
4744 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4748 case IA64_OPND_CNT2c
:
4749 val
= e
->X_add_number
;
4750 if (e
->X_op
== O_constant
4751 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4756 /* SOR must be an integer multiple of 8 */
4757 if (e
->X_add_number
& 0x7)
4761 if (e
->X_op
== O_constant
&&
4762 (bfd_vma
) e
->X_add_number
<= 96)
4766 case IA64_OPND_IMMU62
:
4767 if (e
->X_op
== O_constant
)
4769 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4774 /* FIXME -- need 62-bit relocation type */
4775 as_bad (_("62-bit relocation not yet implemented"));
4779 case IA64_OPND_IMMU64
:
4780 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4781 || e
->X_op
== O_subtract
)
4783 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4784 fix
->code
= BFD_RELOC_IA64_IMM64
;
4785 if (e
->X_op
!= O_subtract
)
4787 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4788 if (e
->X_op
== O_pseudo_fixup
)
4792 fix
->opnd
= idesc
->operands
[index
];
4795 ++CURR_SLOT
.num_fixups
;
4798 else if (e
->X_op
== O_constant
)
4802 case IA64_OPND_CCNT5
:
4803 case IA64_OPND_CNT5
:
4804 case IA64_OPND_CNT6
:
4805 case IA64_OPND_CPOS6a
:
4806 case IA64_OPND_CPOS6b
:
4807 case IA64_OPND_CPOS6c
:
4808 case IA64_OPND_IMMU2
:
4809 case IA64_OPND_IMMU7a
:
4810 case IA64_OPND_IMMU7b
:
4811 case IA64_OPND_IMMU21
:
4812 case IA64_OPND_IMMU24
:
4813 case IA64_OPND_MBTYPE4
:
4814 case IA64_OPND_MHTYPE8
:
4815 case IA64_OPND_POS6
:
4816 bits
= operand_width (idesc
->operands
[index
]);
4817 if (e
->X_op
== O_constant
4818 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4822 case IA64_OPND_IMMU9
:
4823 bits
= operand_width (idesc
->operands
[index
]);
4824 if (e
->X_op
== O_constant
4825 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4827 int lobits
= e
->X_add_number
& 0x3;
4828 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4829 e
->X_add_number
|= (bfd_vma
) 0x3;
4834 case IA64_OPND_IMM44
:
4835 /* least 16 bits must be zero */
4836 if ((e
->X_add_number
& 0xffff) != 0)
4837 as_warn (_("lower 16 bits of mask ignored"));
4839 if (e
->X_op
== O_constant
4840 && ((e
->X_add_number
>= 0
4841 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
4842 || (e
->X_add_number
< 0
4843 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4846 if (e
->X_add_number
>= 0
4847 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4849 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
4855 case IA64_OPND_IMM17
:
4856 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4857 if (e
->X_op
== O_constant
4858 && ((e
->X_add_number
>= 0
4859 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
4860 || (e
->X_add_number
< 0
4861 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
4864 if (e
->X_add_number
>= 0
4865 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
4867 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
4873 case IA64_OPND_IMM14
:
4874 case IA64_OPND_IMM22
:
4876 case IA64_OPND_IMM1
:
4877 case IA64_OPND_IMM8
:
4878 case IA64_OPND_IMM8U4
:
4879 case IA64_OPND_IMM8M1
:
4880 case IA64_OPND_IMM8M1U4
:
4881 case IA64_OPND_IMM8M1U8
:
4882 case IA64_OPND_IMM9a
:
4883 case IA64_OPND_IMM9b
:
4884 bits
= operand_width (idesc
->operands
[index
]);
4885 if (relocatable
&& (e
->X_op
== O_symbol
4886 || e
->X_op
== O_subtract
4887 || e
->X_op
== O_pseudo_fixup
))
4889 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4891 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
4892 fix
->code
= BFD_RELOC_IA64_IMM14
;
4894 fix
->code
= BFD_RELOC_IA64_IMM22
;
4896 if (e
->X_op
!= O_subtract
)
4898 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4899 if (e
->X_op
== O_pseudo_fixup
)
4903 fix
->opnd
= idesc
->operands
[index
];
4906 ++CURR_SLOT
.num_fixups
;
4909 else if (e
->X_op
!= O_constant
4910 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
4913 if (opnd
== IA64_OPND_IMM8M1U4
)
4915 /* Zero is not valid for unsigned compares that take an adjusted
4916 constant immediate range. */
4917 if (e
->X_add_number
== 0)
4920 /* Sign-extend 32-bit unsigned numbers, so that the following range
4921 checks will work. */
4922 val
= e
->X_add_number
;
4923 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4924 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4925 val
= ((val
<< 32) >> 32);
4927 /* Check for 0x100000000. This is valid because
4928 0x100000000-1 is the same as ((uint32_t) -1). */
4929 if (val
== ((bfd_signed_vma
) 1 << 32))
4934 else if (opnd
== IA64_OPND_IMM8M1U8
)
4936 /* Zero is not valid for unsigned compares that take an adjusted
4937 constant immediate range. */
4938 if (e
->X_add_number
== 0)
4941 /* Check for 0x10000000000000000. */
4942 if (e
->X_op
== O_big
)
4944 if (generic_bignum
[0] == 0
4945 && generic_bignum
[1] == 0
4946 && generic_bignum
[2] == 0
4947 && generic_bignum
[3] == 0
4948 && generic_bignum
[4] == 1)
4954 val
= e
->X_add_number
- 1;
4956 else if (opnd
== IA64_OPND_IMM8M1
)
4957 val
= e
->X_add_number
- 1;
4958 else if (opnd
== IA64_OPND_IMM8U4
)
4960 /* Sign-extend 32-bit unsigned numbers, so that the following range
4961 checks will work. */
4962 val
= e
->X_add_number
;
4963 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
4964 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
4965 val
= ((val
<< 32) >> 32);
4968 val
= e
->X_add_number
;
4970 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
4971 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
4975 case IA64_OPND_INC3
:
4976 /* +/- 1, 4, 8, 16 */
4977 val
= e
->X_add_number
;
4980 if (e
->X_op
== O_constant
4981 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
4985 case IA64_OPND_TGT25
:
4986 case IA64_OPND_TGT25b
:
4987 case IA64_OPND_TGT25c
:
4988 case IA64_OPND_TGT64
:
4989 if (e
->X_op
== O_symbol
)
4991 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4992 if (opnd
== IA64_OPND_TGT25
)
4993 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
4994 else if (opnd
== IA64_OPND_TGT25b
)
4995 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
4996 else if (opnd
== IA64_OPND_TGT25c
)
4997 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
4998 else if (opnd
== IA64_OPND_TGT64
)
4999 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5003 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5004 fix
->opnd
= idesc
->operands
[index
];
5007 ++CURR_SLOT
.num_fixups
;
5010 case IA64_OPND_TAG13
:
5011 case IA64_OPND_TAG13b
:
5018 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5019 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
5020 fix
->opnd
= idesc
->operands
[index
];
5023 ++CURR_SLOT
.num_fixups
;
5043 memset (e
, 0, sizeof (*e
));
5046 if (*input_line_pointer
!= '}')
5048 sep
= *input_line_pointer
++;
5052 if (!md
.manual_bundling
)
5053 as_warn ("Found '}' when manual bundling is off");
5055 CURR_SLOT
.manual_bundling_off
= 1;
5056 md
.manual_bundling
= 0;
5062 /* Returns the next entry in the opcode table that matches the one in
5063 IDESC, and frees the entry in IDESC. If no matching entry is
5064 found, NULL is returned instead. */
5066 static struct ia64_opcode
*
5067 get_next_opcode (struct ia64_opcode
*idesc
)
5069 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5070 ia64_free_opcode (idesc
);
5074 /* Parse the operands for the opcode and find the opcode variant that
5075 matches the specified operands, or NULL if no match is possible. */
5077 static struct ia64_opcode
*
5078 parse_operands (idesc
)
5079 struct ia64_opcode
*idesc
;
5081 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5083 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5085 char *first_arg
= 0, *end
, *saved_input_pointer
;
5088 assert (strlen (idesc
->name
) <= 128);
5090 strcpy (mnemonic
, idesc
->name
);
5091 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5093 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5094 can't parse the first operand until we have parsed the
5095 remaining operands of the "alloc" instruction. */
5097 first_arg
= input_line_pointer
;
5098 end
= strchr (input_line_pointer
, '=');
5101 as_bad ("Expected separator `='");
5104 input_line_pointer
= end
+ 1;
5109 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5111 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5112 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5117 if (sep
!= '=' && sep
!= ',')
5122 if (num_outputs
> 0)
5123 as_bad ("Duplicate equal sign (=) in instruction");
5125 num_outputs
= i
+ 1;
5130 as_bad ("Illegal operand separator `%c'", sep
);
5134 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5136 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5137 know (strcmp (idesc
->name
, "alloc") == 0);
5138 if (num_operands
== 5 /* first_arg not included in this count! */
5139 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5140 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5141 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5142 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5144 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5145 CURR_SLOT
.opnd
[3].X_add_number
,
5146 CURR_SLOT
.opnd
[4].X_add_number
,
5147 CURR_SLOT
.opnd
[5].X_add_number
);
5149 /* now we can parse the first arg: */
5150 saved_input_pointer
= input_line_pointer
;
5151 input_line_pointer
= first_arg
;
5152 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5154 --num_outputs
; /* force error */
5155 input_line_pointer
= saved_input_pointer
;
5157 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5158 CURR_SLOT
.opnd
[3].X_add_number
5159 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5160 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5164 highest_unmatched_operand
= 0;
5165 expected_operand
= idesc
->operands
[0];
5166 for (; idesc
; idesc
= get_next_opcode (idesc
))
5168 if (num_outputs
!= idesc
->num_outputs
)
5169 continue; /* mismatch in # of outputs */
5171 CURR_SLOT
.num_fixups
= 0;
5172 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5173 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5176 if (i
!= num_operands
)
5178 if (i
> highest_unmatched_operand
)
5180 highest_unmatched_operand
= i
;
5181 expected_operand
= idesc
->operands
[i
];
5186 if (num_operands
< NELEMS (idesc
->operands
)
5187 && idesc
->operands
[num_operands
])
5188 continue; /* mismatch in number of arguments */
5194 if (expected_operand
)
5195 as_bad ("Operand %u of `%s' should be %s",
5196 highest_unmatched_operand
+ 1, mnemonic
,
5197 elf64_ia64_operands
[expected_operand
].desc
);
5199 as_bad ("Operand mismatch");
5205 /* Keep track of state necessary to determine whether a NOP is necessary
5206 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5207 detect a case where additional NOPs may be necessary. */
5209 errata_nop_necessary_p (slot
, insn_unit
)
5211 enum ia64_unit insn_unit
;
5214 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5215 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5216 struct ia64_opcode
*idesc
= slot
->idesc
;
5218 /* Test whether this could be the first insn in a problematic sequence. */
5219 if (insn_unit
== IA64_UNIT_F
)
5221 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5222 if (idesc
->operands
[i
] == IA64_OPND_P1
5223 || idesc
->operands
[i
] == IA64_OPND_P2
)
5225 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5226 /* Ignore invalid operands; they generate errors elsewhere. */
5229 this_group
->p_reg_set
[regno
] = 1;
5233 /* Test whether this could be the second insn in a problematic sequence. */
5234 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5235 && prev_group
->p_reg_set
[slot
->qp_regno
])
5237 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5238 if (idesc
->operands
[i
] == IA64_OPND_R1
5239 || idesc
->operands
[i
] == IA64_OPND_R2
5240 || idesc
->operands
[i
] == IA64_OPND_R3
)
5242 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5243 /* Ignore invalid operands; they generate errors elsewhere. */
5246 if (strncmp (idesc
->name
, "add", 3) != 0
5247 && strncmp (idesc
->name
, "sub", 3) != 0
5248 && strncmp (idesc
->name
, "shladd", 6) != 0
5249 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5250 this_group
->g_reg_set_conditionally
[regno
] = 1;
5254 /* Test whether this could be the third insn in a problematic sequence. */
5255 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5257 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5258 idesc
->operands
[i
] == IA64_OPND_R3
5259 /* For mov indirect. */
5260 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5261 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5262 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5263 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5264 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5265 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5266 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5267 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5269 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5270 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5271 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5272 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5274 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5275 /* Ignore invalid operands; they generate errors elsewhere. */
5278 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5280 if (strcmp (idesc
->name
, "fc") != 0
5281 && strcmp (idesc
->name
, "tak") != 0
5282 && strcmp (idesc
->name
, "thash") != 0
5283 && strcmp (idesc
->name
, "tpa") != 0
5284 && strcmp (idesc
->name
, "ttag") != 0
5285 && strncmp (idesc
->name
, "ptr", 3) != 0
5286 && strncmp (idesc
->name
, "ptc", 3) != 0
5287 && strncmp (idesc
->name
, "probe", 5) != 0)
5290 if (prev_group
->g_reg_set_conditionally
[regno
])
5298 build_insn (slot
, insnp
)
5302 const struct ia64_operand
*odesc
, *o2desc
;
5303 struct ia64_opcode
*idesc
= slot
->idesc
;
5304 bfd_signed_vma insn
, val
;
5308 insn
= idesc
->opcode
| slot
->qp_regno
;
5310 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5312 if (slot
->opnd
[i
].X_op
== O_register
5313 || slot
->opnd
[i
].X_op
== O_constant
5314 || slot
->opnd
[i
].X_op
== O_index
)
5315 val
= slot
->opnd
[i
].X_add_number
;
5316 else if (slot
->opnd
[i
].X_op
== O_big
)
5318 /* This must be the value 0x10000000000000000. */
5319 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5325 switch (idesc
->operands
[i
])
5327 case IA64_OPND_IMMU64
:
5328 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5329 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5330 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5331 | (((val
>> 63) & 0x1) << 36));
5334 case IA64_OPND_IMMU62
:
5335 val
&= 0x3fffffffffffffffULL
;
5336 if (val
!= slot
->opnd
[i
].X_add_number
)
5337 as_warn (_("Value truncated to 62 bits"));
5338 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5339 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5342 case IA64_OPND_TGT64
:
5344 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5345 insn
|= ((((val
>> 59) & 0x1) << 36)
5346 | (((val
>> 0) & 0xfffff) << 13));
5377 case IA64_OPND_R3_2
:
5378 case IA64_OPND_CPUID_R3
:
5379 case IA64_OPND_DBR_R3
:
5380 case IA64_OPND_DTR_R3
:
5381 case IA64_OPND_ITR_R3
:
5382 case IA64_OPND_IBR_R3
:
5384 case IA64_OPND_MSR_R3
:
5385 case IA64_OPND_PKR_R3
:
5386 case IA64_OPND_PMC_R3
:
5387 case IA64_OPND_PMD_R3
:
5388 case IA64_OPND_RR_R3
:
5396 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5397 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5399 as_bad_where (slot
->src_file
, slot
->src_line
,
5400 "Bad operand value: %s", err
);
5401 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5403 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5404 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5406 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5407 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5409 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5410 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5411 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5413 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5414 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5424 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5425 unsigned int manual_bundling
= 0;
5426 enum ia64_unit required_unit
, insn_unit
= 0;
5427 enum ia64_insn_type type
[3], insn_type
;
5428 unsigned int template, orig_template
;
5429 bfd_vma insn
[3] = { -1, -1, -1 };
5430 struct ia64_opcode
*idesc
;
5431 int end_of_insn_group
= 0, user_template
= -1;
5432 int n
, i
, j
, first
, curr
;
5434 bfd_vma t0
= 0, t1
= 0;
5435 struct label_fix
*lfix
;
5436 struct insn_fix
*ifix
;
5441 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5442 know (first
>= 0 & first
< NUM_SLOTS
);
5443 n
= MIN (3, md
.num_slots_in_use
);
5445 /* Determine template: user user_template if specified, best match
5448 if (md
.slot
[first
].user_template
>= 0)
5449 user_template
= template = md
.slot
[first
].user_template
;
5452 /* Auto select appropriate template. */
5453 memset (type
, 0, sizeof (type
));
5455 for (i
= 0; i
< n
; ++i
)
5457 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5459 type
[i
] = md
.slot
[curr
].idesc
->type
;
5460 curr
= (curr
+ 1) % NUM_SLOTS
;
5462 template = best_template
[type
[0]][type
[1]][type
[2]];
5465 /* initialize instructions with appropriate nops: */
5466 for (i
= 0; i
< 3; ++i
)
5467 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5471 /* now fill in slots with as many insns as possible: */
5473 idesc
= md
.slot
[curr
].idesc
;
5474 end_of_insn_group
= 0;
5475 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5477 /* Set the slot number for prologue/body records now as those
5478 refer to the current point, not the point after the
5479 instruction has been issued: */
5480 /* Don't try to delete prologue/body records here, as that will cause
5481 them to also be deleted from the master list of unwind records. */
5482 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5483 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5484 || ptr
->r
.type
== body
)
5486 ptr
->slot_number
= (unsigned long) f
+ i
;
5487 ptr
->slot_frag
= frag_now
;
5490 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5492 if (manual_bundling
&& i
!= 2)
5493 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5494 "`%s' must be last in bundle", idesc
->name
);
5498 if (idesc
->flags
& IA64_OPCODE_LAST
)
5501 unsigned int required_template
;
5503 /* If we need a stop bit after an M slot, our only choice is
5504 template 5 (M;;MI). If we need a stop bit after a B
5505 slot, our only choice is to place it at the end of the
5506 bundle, because the only available templates are MIB,
5507 MBB, BBB, MMB, and MFB. We don't handle anything other
5508 than M and B slots because these are the only kind of
5509 instructions that can have the IA64_OPCODE_LAST bit set. */
5510 required_template
= template;
5511 switch (idesc
->type
)
5515 required_template
= 5;
5523 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5524 "Internal error: don't know how to force %s to end"
5525 "of instruction group", idesc
->name
);
5529 if (manual_bundling
&& i
!= required_slot
)
5530 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5531 "`%s' must be last in instruction group",
5533 if (required_slot
< i
)
5534 /* Can't fit this instruction. */
5538 if (required_template
!= template)
5540 /* If we switch the template, we need to reset the NOPs
5541 after slot i. The slot-types of the instructions ahead
5542 of i never change, so we don't need to worry about
5543 changing NOPs in front of this slot. */
5544 for (j
= i
; j
< 3; ++j
)
5545 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5547 template = required_template
;
5549 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5551 if (manual_bundling_on
)
5552 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5553 "Label must be first in a bundle");
5554 /* This insn must go into the first slot of a bundle. */
5558 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5559 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5561 if (manual_bundling_on
)
5564 manual_bundling
= 1;
5566 break; /* need to start a new bundle */
5569 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5571 /* We need an instruction group boundary in the middle of a
5572 bundle. See if we can switch to an other template with
5573 an appropriate boundary. */
5575 orig_template
= template;
5576 if (i
== 1 && (user_template
== 4
5577 || (user_template
< 0
5578 && (ia64_templ_desc
[template].exec_unit
[0]
5582 end_of_insn_group
= 0;
5584 else if (i
== 2 && (user_template
== 0
5585 || (user_template
< 0
5586 && (ia64_templ_desc
[template].exec_unit
[1]
5588 /* This test makes sure we don't switch the template if
5589 the next instruction is one that needs to be first in
5590 an instruction group. Since all those instructions are
5591 in the M group, there is no way such an instruction can
5592 fit in this bundle even if we switch the template. The
5593 reason we have to check for this is that otherwise we
5594 may end up generating "MI;;I M.." which has the deadly
5595 effect that the second M instruction is no longer the
5596 first in the bundle! --davidm 99/12/16 */
5597 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5600 end_of_insn_group
= 0;
5602 else if (curr
!= first
)
5603 /* can't fit this insn */
5606 if (template != orig_template
)
5607 /* if we switch the template, we need to reset the NOPs
5608 after slot i. The slot-types of the instructions ahead
5609 of i never change, so we don't need to worry about
5610 changing NOPs in front of this slot. */
5611 for (j
= i
; j
< 3; ++j
)
5612 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5614 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5616 /* resolve dynamic opcodes such as "break" and "nop": */
5617 if (idesc
->type
== IA64_TYPE_DYN
)
5619 if ((strcmp (idesc
->name
, "nop") == 0)
5620 || (strcmp (idesc
->name
, "break") == 0))
5621 insn_unit
= required_unit
;
5622 else if (strcmp (idesc
->name
, "chk.s") == 0)
5624 insn_unit
= IA64_UNIT_M
;
5625 if (required_unit
== IA64_UNIT_I
)
5626 insn_unit
= IA64_UNIT_I
;
5629 as_fatal ("emit_one_bundle: unexpected dynamic op");
5631 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5632 ia64_free_opcode (idesc
);
5633 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5635 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5640 insn_type
= idesc
->type
;
5641 insn_unit
= IA64_UNIT_NIL
;
5645 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5646 insn_unit
= required_unit
;
5648 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5649 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5650 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5651 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5652 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5657 if (insn_unit
!= required_unit
)
5659 if (required_unit
== IA64_UNIT_L
5660 && insn_unit
== IA64_UNIT_I
5661 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5663 /* we got ourselves an MLX template but the current
5664 instruction isn't an X-unit, or an I-unit instruction
5665 that can go into the X slot of an MLX template. Duh. */
5666 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5668 as_bad_where (md
.slot
[curr
].src_file
,
5669 md
.slot
[curr
].src_line
,
5670 "`%s' can't go in X slot of "
5671 "MLX template", idesc
->name
);
5672 /* drop this insn so we don't livelock: */
5673 --md
.num_slots_in_use
;
5677 continue; /* try next slot */
5683 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
5684 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5687 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
5688 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5690 build_insn (md
.slot
+ curr
, insn
+ i
);
5692 /* Set slot counts for non prologue/body unwind records. */
5693 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5694 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5695 && ptr
->r
.type
!= body
)
5697 ptr
->slot_number
= (unsigned long) f
+ i
;
5698 ptr
->slot_frag
= frag_now
;
5700 md
.slot
[curr
].unwind_record
= NULL
;
5702 if (required_unit
== IA64_UNIT_L
)
5705 /* skip one slot for long/X-unit instructions */
5708 --md
.num_slots_in_use
;
5710 /* now is a good time to fix up the labels for this insn: */
5711 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5713 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5714 symbol_set_frag (lfix
->sym
, frag_now
);
5716 /* and fix up the tags also. */
5717 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
5719 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
5720 symbol_set_frag (lfix
->sym
, frag_now
);
5723 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5725 ifix
= md
.slot
[curr
].fixup
+ j
;
5726 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
5727 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5728 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5729 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5730 fix
->fx_file
= md
.slot
[curr
].src_file
;
5731 fix
->fx_line
= md
.slot
[curr
].src_line
;
5734 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5736 if (end_of_insn_group
)
5738 md
.group_idx
= (md
.group_idx
+ 1) % 3;
5739 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
5743 ia64_free_opcode (md
.slot
[curr
].idesc
);
5744 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5745 md
.slot
[curr
].user_template
= -1;
5747 if (manual_bundling_off
)
5749 manual_bundling
= 0;
5752 curr
= (curr
+ 1) % NUM_SLOTS
;
5753 idesc
= md
.slot
[curr
].idesc
;
5755 if (manual_bundling
)
5757 if (md
.num_slots_in_use
> 0)
5758 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5759 "`%s' does not fit into %s template",
5760 idesc
->name
, ia64_templ_desc
[template].name
);
5762 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5763 "Missing '}' at end of file");
5765 know (md
.num_slots_in_use
< NUM_SLOTS
);
5767 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5768 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5770 number_to_chars_littleendian (f
+ 0, t0
, 8);
5771 number_to_chars_littleendian (f
+ 8, t1
, 8);
5773 unwind
.next_slot_number
= (unsigned long) f
+ 16;
5774 unwind
.next_slot_frag
= frag_now
;
5778 md_parse_option (c
, arg
)
5784 /* Switches from the Intel assembler. */
5786 if (strcmp (arg
, "ilp64") == 0
5787 || strcmp (arg
, "lp64") == 0
5788 || strcmp (arg
, "p64") == 0)
5790 md
.flags
|= EF_IA_64_ABI64
;
5792 else if (strcmp (arg
, "ilp32") == 0)
5794 md
.flags
&= ~EF_IA_64_ABI64
;
5796 else if (strcmp (arg
, "le") == 0)
5798 md
.flags
&= ~EF_IA_64_BE
;
5800 else if (strcmp (arg
, "be") == 0)
5802 md
.flags
|= EF_IA_64_BE
;
5809 if (strcmp (arg
, "so") == 0)
5811 /* Suppress signon message. */
5813 else if (strcmp (arg
, "pi") == 0)
5815 /* Reject privileged instructions. FIXME */
5817 else if (strcmp (arg
, "us") == 0)
5819 /* Allow union of signed and unsigned range. FIXME */
5821 else if (strcmp (arg
, "close_fcalls") == 0)
5823 /* Do not resolve global function calls. */
5830 /* temp[="prefix"] Insert temporary labels into the object file
5831 symbol table prefixed by "prefix".
5832 Default prefix is ":temp:".
5837 /* indirect=<tgt> Assume unannotated indirect branches behavior
5838 according to <tgt> --
5839 exit: branch out from the current context (default)
5840 labels: all labels in context may be branch targets
5842 if (strncmp (arg
, "indirect=", 9) != 0)
5847 /* -X conflicts with an ignored option, use -x instead */
5849 if (!arg
|| strcmp (arg
, "explicit") == 0)
5851 /* set default mode to explicit */
5852 md
.default_explicit_mode
= 1;
5855 else if (strcmp (arg
, "auto") == 0)
5857 md
.default_explicit_mode
= 0;
5859 else if (strcmp (arg
, "debug") == 0)
5863 else if (strcmp (arg
, "debugx") == 0)
5865 md
.default_explicit_mode
= 1;
5870 as_bad (_("Unrecognized option '-x%s'"), arg
);
5875 /* nops Print nops statistics. */
5878 /* GNU specific switches for gcc. */
5879 case OPTION_MCONSTANT_GP
:
5880 md
.flags
|= EF_IA_64_CONS_GP
;
5883 case OPTION_MAUTO_PIC
:
5884 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
5895 md_show_usage (stream
)
5900 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
5901 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
5902 -x | -xexplicit turn on dependency violation checking (default)\n\
5903 -xauto automagically remove dependency violations\n\
5904 -xdebug debug dependency violation checker\n"),
5908 /* Return true if TYPE fits in TEMPL at SLOT. */
5911 match (int templ
, int type
, int slot
)
5913 enum ia64_unit unit
;
5916 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
5919 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
5921 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
5923 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
5924 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
5925 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
5926 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
5927 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
5928 default: result
= 0; break;
5933 /* Add a bit of extra goodness if a nop of type F or B would fit
5934 in TEMPL at SLOT. */
5937 extra_goodness (int templ
, int slot
)
5939 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
5941 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
5946 /* This function is called once, at assembler startup time. It sets
5947 up all the tables, etc. that the MD part of the assembler will need
5948 that can be determined before arguments are parsed. */
5952 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
5957 md
.explicit_mode
= md
.default_explicit_mode
;
5959 bfd_set_section_alignment (stdoutput
, text_section
, 4);
5961 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
5962 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
5963 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
5964 &zero_address_frag
);
5966 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
5967 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
5968 &zero_address_frag
);
5970 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
5971 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
5972 &zero_address_frag
);
5974 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
5975 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
5976 &zero_address_frag
);
5978 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
5979 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
5980 &zero_address_frag
);
5982 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
5983 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
5984 &zero_address_frag
);
5986 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
5987 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
5988 &zero_address_frag
);
5990 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
5991 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
5992 &zero_address_frag
);
5994 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
5995 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
5996 &zero_address_frag
);
5998 /* Compute the table of best templates. We compute goodness as a
5999 base 4 value, in which each match counts for 3, each F counts
6000 for 2, each B counts for 1. This should maximize the number of
6001 F and B nops in the chosen bundles, which is good because these
6002 pipelines are least likely to be overcommitted. */
6003 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6004 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6005 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6008 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6011 if (match (t
, i
, 0))
6013 if (match (t
, j
, 1))
6015 if (match (t
, k
, 2))
6016 goodness
= 3 + 3 + 3;
6018 goodness
= 3 + 3 + extra_goodness (t
, 2);
6020 else if (match (t
, j
, 2))
6021 goodness
= 3 + 3 + extra_goodness (t
, 1);
6025 goodness
+= extra_goodness (t
, 1);
6026 goodness
+= extra_goodness (t
, 2);
6029 else if (match (t
, i
, 1))
6031 if (match (t
, j
, 2))
6034 goodness
= 3 + extra_goodness (t
, 2);
6036 else if (match (t
, i
, 2))
6037 goodness
= 3 + extra_goodness (t
, 1);
6039 if (goodness
> best
)
6042 best_template
[i
][j
][k
] = t
;
6047 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6048 md
.slot
[i
].user_template
= -1;
6050 md
.pseudo_hash
= hash_new ();
6051 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6053 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6054 (void *) (pseudo_opcode
+ i
));
6056 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6057 pseudo_opcode
[i
].name
, err
);
6060 md
.reg_hash
= hash_new ();
6061 md
.dynreg_hash
= hash_new ();
6062 md
.const_hash
= hash_new ();
6063 md
.entry_hash
= hash_new ();
6065 /* general registers: */
6068 for (i
= 0; i
< total
; ++i
)
6070 sprintf (name
, "r%d", i
- REG_GR
);
6071 md
.regsym
[i
] = declare_register (name
, i
);
6074 /* floating point registers: */
6076 for (; i
< total
; ++i
)
6078 sprintf (name
, "f%d", i
- REG_FR
);
6079 md
.regsym
[i
] = declare_register (name
, i
);
6082 /* application registers: */
6085 for (; i
< total
; ++i
)
6087 sprintf (name
, "ar%d", i
- REG_AR
);
6088 md
.regsym
[i
] = declare_register (name
, i
);
6091 /* control registers: */
6094 for (; i
< total
; ++i
)
6096 sprintf (name
, "cr%d", i
- REG_CR
);
6097 md
.regsym
[i
] = declare_register (name
, i
);
6100 /* predicate registers: */
6102 for (; i
< total
; ++i
)
6104 sprintf (name
, "p%d", i
- REG_P
);
6105 md
.regsym
[i
] = declare_register (name
, i
);
6108 /* branch registers: */
6110 for (; i
< total
; ++i
)
6112 sprintf (name
, "b%d", i
- REG_BR
);
6113 md
.regsym
[i
] = declare_register (name
, i
);
6116 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6117 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6118 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6119 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6120 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6121 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6122 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6124 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6126 regnum
= indirect_reg
[i
].regnum
;
6127 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6130 /* define synonyms for application registers: */
6131 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6132 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6133 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6135 /* define synonyms for control registers: */
6136 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6137 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6138 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6140 declare_register ("gp", REG_GR
+ 1);
6141 declare_register ("sp", REG_GR
+ 12);
6142 declare_register ("rp", REG_BR
+ 0);
6144 /* pseudo-registers used to specify unwind info: */
6145 declare_register ("psp", REG_PSP
);
6147 declare_register_set ("ret", 4, REG_GR
+ 8);
6148 declare_register_set ("farg", 8, REG_FR
+ 8);
6149 declare_register_set ("fret", 8, REG_FR
+ 8);
6151 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6153 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6154 (PTR
) (const_bits
+ i
));
6156 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6160 /* Set the architecture and machine depending on defaults and command line
6162 if (md
.flags
& EF_IA_64_ABI64
)
6163 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6165 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6168 as_warn (_("Could not set architecture and machine"));
6170 md
.mem_offset
.hint
= 0;
6173 md
.entry_labels
= NULL
;
6176 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6177 because that is called after md_parse_option which is where we do the
6178 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6179 default endianness. */
6182 ia64_init (argc
, argv
)
6183 int argc ATTRIBUTE_UNUSED
;
6184 char **argv ATTRIBUTE_UNUSED
;
6186 md
.flags
= EF_IA_64_ABI64
;
6187 if (TARGET_BYTES_BIG_ENDIAN
)
6188 md
.flags
|= EF_IA_64_BE
;
6191 /* Return a string for the target object file format. */
6194 ia64_target_format ()
6196 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6198 if (md
.flags
& EF_IA_64_BE
)
6200 if (md
.flags
& EF_IA_64_ABI64
)
6201 return "elf64-ia64-big";
6203 return "elf32-ia64-big";
6207 if (md
.flags
& EF_IA_64_ABI64
)
6208 return "elf64-ia64-little";
6210 return "elf32-ia64-little";
6214 return "unknown-format";
6218 ia64_end_of_source ()
6220 /* terminate insn group upon reaching end of file: */
6221 insn_group_break (1, 0, 0);
6223 /* emits slots we haven't written yet: */
6224 ia64_flush_insns ();
6226 bfd_set_private_flags (stdoutput
, md
.flags
);
6228 md
.mem_offset
.hint
= 0;
6234 if (md
.qp
.X_op
== O_register
)
6235 as_bad ("qualifying predicate not followed by instruction");
6236 md
.qp
.X_op
= O_absent
;
6238 if (ignore_input ())
6241 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6243 if (md
.detect_dv
&& !md
.explicit_mode
)
6244 as_warn (_("Explicit stops are ignored in auto mode"));
6246 insn_group_break (1, 0, 0);
6250 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6252 static int defining_tag
= 0;
6255 ia64_unrecognized_line (ch
)
6261 expression (&md
.qp
);
6262 if (*input_line_pointer
++ != ')')
6264 as_bad ("Expected ')'");
6267 if (md
.qp
.X_op
!= O_register
)
6269 as_bad ("Qualifying predicate expected");
6272 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6274 as_bad ("Predicate register expected");
6280 if (md
.manual_bundling
)
6281 as_warn ("Found '{' when manual bundling is already turned on");
6283 CURR_SLOT
.manual_bundling_on
= 1;
6284 md
.manual_bundling
= 1;
6286 /* Bundling is only acceptable in explicit mode
6287 or when in default automatic mode. */
6288 if (md
.detect_dv
&& !md
.explicit_mode
)
6290 if (!md
.mode_explicitly_set
6291 && !md
.default_explicit_mode
)
6294 as_warn (_("Found '{' after explicit switch to automatic mode"));
6299 if (!md
.manual_bundling
)
6300 as_warn ("Found '}' when manual bundling is off");
6302 PREV_SLOT
.manual_bundling_off
= 1;
6303 md
.manual_bundling
= 0;
6305 /* switch back to automatic mode, if applicable */
6308 && !md
.mode_explicitly_set
6309 && !md
.default_explicit_mode
)
6312 /* Allow '{' to follow on the same line. We also allow ";;", but that
6313 happens automatically because ';' is an end of line marker. */
6315 if (input_line_pointer
[0] == '{')
6317 input_line_pointer
++;
6318 return ia64_unrecognized_line ('{');
6321 demand_empty_rest_of_line ();
6330 if (md
.qp
.X_op
== O_register
)
6332 as_bad ("Tag must come before qualifying predicate.");
6335 s
= input_line_pointer
;
6336 c
= get_symbol_end ();
6339 /* Put ':' back for error messages' sake. */
6340 *input_line_pointer
++ = ':';
6341 as_bad ("Expected ':'");
6347 /* Put ':' back for error messages' sake. */
6348 *input_line_pointer
++ = ':';
6349 if (*input_line_pointer
++ != ']')
6351 as_bad ("Expected ']'");
6356 as_bad ("Tag name expected");
6366 /* Not a valid line. */
6371 ia64_frob_label (sym
)
6374 struct label_fix
*fix
;
6376 /* Tags need special handling since they are not bundle breaks like
6380 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6382 fix
->next
= CURR_SLOT
.tag_fixups
;
6383 CURR_SLOT
.tag_fixups
= fix
;
6388 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6390 md
.last_text_seg
= now_seg
;
6391 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6393 fix
->next
= CURR_SLOT
.label_fixups
;
6394 CURR_SLOT
.label_fixups
= fix
;
6396 /* Keep track of how many code entry points we've seen. */
6397 if (md
.path
== md
.maxpaths
)
6400 md
.entry_labels
= (const char **)
6401 xrealloc ((void *) md
.entry_labels
,
6402 md
.maxpaths
* sizeof (char *));
6404 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6409 ia64_flush_pending_output ()
6411 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6413 /* ??? This causes many unnecessary stop bits to be emitted.
6414 Unfortunately, it isn't clear if it is safe to remove this. */
6415 insn_group_break (1, 0, 0);
6416 ia64_flush_insns ();
6420 /* Do ia64-specific expression optimization. All that's done here is
6421 to transform index expressions that are either due to the indexing
6422 of rotating registers or due to the indexing of indirect register
6425 ia64_optimize_expr (l
, op
, r
)
6434 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6436 num_regs
= (l
->X_add_number
>> 16);
6437 if ((unsigned) r
->X_add_number
>= num_regs
)
6440 as_bad ("No current frame");
6442 as_bad ("Index out of range 0..%u", num_regs
- 1);
6443 r
->X_add_number
= 0;
6445 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6448 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6450 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6451 || l
->X_add_number
== IND_MEM
)
6453 as_bad ("Indirect register set name expected");
6454 l
->X_add_number
= IND_CPUID
;
6457 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6458 l
->X_add_number
= r
->X_add_number
;
6466 ia64_parse_name (name
, e
)
6470 struct const_desc
*cdesc
;
6471 struct dynreg
*dr
= 0;
6472 unsigned int regnum
;
6476 /* first see if NAME is a known register name: */
6477 sym
= hash_find (md
.reg_hash
, name
);
6480 e
->X_op
= O_register
;
6481 e
->X_add_number
= S_GET_VALUE (sym
);
6485 cdesc
= hash_find (md
.const_hash
, name
);
6488 e
->X_op
= O_constant
;
6489 e
->X_add_number
= cdesc
->value
;
6493 /* check for inN, locN, or outN: */
6497 if (name
[1] == 'n' && isdigit (name
[2]))
6505 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6513 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6526 /* The name is inN, locN, or outN; parse the register number. */
6527 regnum
= strtoul (name
, &end
, 10);
6528 if (end
> name
&& *end
== '\0')
6530 if ((unsigned) regnum
>= dr
->num_regs
)
6533 as_bad ("No current frame");
6535 as_bad ("Register number out of range 0..%u",
6539 e
->X_op
= O_register
;
6540 e
->X_add_number
= dr
->base
+ regnum
;
6545 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6547 /* We've got ourselves the name of a rotating register set.
6548 Store the base register number in the low 16 bits of
6549 X_add_number and the size of the register set in the top 16
6551 e
->X_op
= O_register
;
6552 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6558 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6561 ia64_canonicalize_symbol_name (name
)
6564 size_t len
= strlen (name
);
6565 if (len
> 1 && name
[len
- 1] == '#')
6566 name
[len
- 1] = '\0';
6571 is_conditional_branch (idesc
)
6572 struct ia64_opcode
*idesc
;
6574 return (strncmp (idesc
->name
, "br", 2) == 0
6575 && (strcmp (idesc
->name
, "br") == 0
6576 || strncmp (idesc
->name
, "br.cond", 7) == 0
6577 || strncmp (idesc
->name
, "br.call", 7) == 0
6578 || strncmp (idesc
->name
, "br.ret", 6) == 0
6579 || strcmp (idesc
->name
, "brl") == 0
6580 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6581 || strncmp (idesc
->name
, "brl.call", 7) == 0
6582 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6585 /* Return whether the given opcode is a taken branch. If there's any doubt,
6589 is_taken_branch (idesc
)
6590 struct ia64_opcode
*idesc
;
6592 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6593 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6596 /* Return whether the given opcode is an interruption or rfi. If there's any
6597 doubt, returns zero. */
6600 is_interruption_or_rfi (idesc
)
6601 struct ia64_opcode
*idesc
;
6603 if (strcmp (idesc
->name
, "rfi") == 0)
6608 /* Returns the index of the given dependency in the opcode's list of chks, or
6609 -1 if there is no dependency. */
6612 depends_on (depind
, idesc
)
6614 struct ia64_opcode
*idesc
;
6617 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6618 for (i
= 0; i
< dep
->nchks
; i
++)
6620 if (depind
== DEP (dep
->chks
[i
]))
6626 /* Determine a set of specific resources used for a particular resource
6627 class. Returns the number of specific resources identified For those
6628 cases which are not determinable statically, the resource returned is
6631 Meanings of value in 'NOTE':
6632 1) only read/write when the register number is explicitly encoded in the
6634 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6635 accesses CFM when qualifying predicate is in the rotating region.
6636 3) general register value is used to specify an indirect register; not
6637 determinable statically.
6638 4) only read the given resource when bits 7:0 of the indirect index
6639 register value does not match the register number of the resource; not
6640 determinable statically.
6641 5) all rules are implementation specific.
6642 6) only when both the index specified by the reader and the index specified
6643 by the writer have the same value in bits 63:61; not determinable
6645 7) only access the specified resource when the corresponding mask bit is
6647 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6648 only read when these insns reference FR2-31
6649 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6650 written when these insns write FR32-127
6651 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6653 11) The target predicates are written independently of PR[qp], but source
6654 registers are only read if PR[qp] is true. Since the state of PR[qp]
6655 cannot statically be determined, all source registers are marked used.
6656 12) This insn only reads the specified predicate register when that
6657 register is the PR[qp].
6658 13) This reference to ld-c only applies to teh GR whose value is loaded
6659 with data returned from memory, not the post-incremented address register.
6660 14) The RSE resource includes the implementation-specific RSE internal
6661 state resources. At least one (and possibly more) of these resources are
6662 read by each instruction listed in IC:rse-readers. At least one (and
6663 possibly more) of these resources are written by each insn listed in
6665 15+16) Represents reserved instructions, which the assembler does not
6668 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6669 this code; there are no dependency violations based on memory access.
6672 #define MAX_SPECS 256
6677 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6678 const struct ia64_dependency
*dep
;
6679 struct ia64_opcode
*idesc
;
6680 int type
; /* is this a DV chk or a DV reg? */
6681 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6682 int note
; /* resource note for this insn's usage */
6683 int path
; /* which execution path to examine */
6690 if (dep
->mode
== IA64_DV_WAW
6691 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6692 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6695 /* template for any resources we identify */
6696 tmpl
.dependency
= dep
;
6698 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6699 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6700 tmpl
.link_to_qp_branch
= 1;
6701 tmpl
.mem_offset
.hint
= 0;
6704 tmpl
.cmp_type
= CMP_NONE
;
6707 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6708 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6709 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6711 /* we don't need to track these */
6712 if (dep
->semantics
== IA64_DVS_NONE
)
6715 switch (dep
->specifier
)
6720 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6722 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6723 if (regno
>= 0 && regno
<= 7)
6725 specs
[count
] = tmpl
;
6726 specs
[count
++].index
= regno
;
6732 for (i
= 0; i
< 8; i
++)
6734 specs
[count
] = tmpl
;
6735 specs
[count
++].index
= i
;
6744 case IA64_RS_AR_UNAT
:
6745 /* This is a mov =AR or mov AR= instruction. */
6746 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6748 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6749 if (regno
== AR_UNAT
)
6751 specs
[count
++] = tmpl
;
6756 /* This is a spill/fill, or other instruction that modifies the
6759 /* Unless we can determine the specific bits used, mark the whole
6760 thing; bits 8:3 of the memory address indicate the bit used in
6761 UNAT. The .mem.offset hint may be used to eliminate a small
6762 subset of conflicts. */
6763 specs
[count
] = tmpl
;
6764 if (md
.mem_offset
.hint
)
6767 fprintf (stderr
, " Using hint for spill/fill\n");
6768 /* The index isn't actually used, just set it to something
6769 approximating the bit index. */
6770 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6771 specs
[count
].mem_offset
.hint
= 1;
6772 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6773 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6777 specs
[count
++].specific
= 0;
6785 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6787 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6788 if ((regno
>= 8 && regno
<= 15)
6789 || (regno
>= 20 && regno
<= 23)
6790 || (regno
>= 31 && regno
<= 39)
6791 || (regno
>= 41 && regno
<= 47)
6792 || (regno
>= 67 && regno
<= 111))
6794 specs
[count
] = tmpl
;
6795 specs
[count
++].index
= regno
;
6808 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6810 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6811 if ((regno
>= 48 && regno
<= 63)
6812 || (regno
>= 112 && regno
<= 127))
6814 specs
[count
] = tmpl
;
6815 specs
[count
++].index
= regno
;
6821 for (i
= 48; i
< 64; i
++)
6823 specs
[count
] = tmpl
;
6824 specs
[count
++].index
= i
;
6826 for (i
= 112; i
< 128; i
++)
6828 specs
[count
] = tmpl
;
6829 specs
[count
++].index
= i
;
6847 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6848 if (idesc
->operands
[i
] == IA64_OPND_B1
6849 || idesc
->operands
[i
] == IA64_OPND_B2
)
6851 specs
[count
] = tmpl
;
6852 specs
[count
++].index
=
6853 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6858 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
6859 if (idesc
->operands
[i
] == IA64_OPND_B1
6860 || idesc
->operands
[i
] == IA64_OPND_B2
)
6862 specs
[count
] = tmpl
;
6863 specs
[count
++].index
=
6864 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6870 case IA64_RS_CPUID
: /* four or more registers */
6873 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
6875 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6876 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6879 specs
[count
] = tmpl
;
6880 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6884 specs
[count
] = tmpl
;
6885 specs
[count
++].specific
= 0;
6895 case IA64_RS_DBR
: /* four or more registers */
6898 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
6900 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6901 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6904 specs
[count
] = tmpl
;
6905 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6909 specs
[count
] = tmpl
;
6910 specs
[count
++].specific
= 0;
6914 else if (note
== 0 && !rsrc_write
)
6916 specs
[count
] = tmpl
;
6917 specs
[count
++].specific
= 0;
6925 case IA64_RS_IBR
: /* four or more registers */
6928 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
6930 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6931 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6934 specs
[count
] = tmpl
;
6935 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6939 specs
[count
] = tmpl
;
6940 specs
[count
++].specific
= 0;
6953 /* These are implementation specific. Force all references to
6954 conflict with all other references. */
6955 specs
[count
] = tmpl
;
6956 specs
[count
++].specific
= 0;
6964 case IA64_RS_PKR
: /* 16 or more registers */
6965 if (note
== 3 || note
== 4)
6967 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
6969 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6970 if (regno
>= 0 && regno
< NELEMS (gr_values
)
6975 specs
[count
] = tmpl
;
6976 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6979 for (i
= 0; i
< NELEMS (gr_values
); i
++)
6981 /* Uses all registers *except* the one in R3. */
6982 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
6984 specs
[count
] = tmpl
;
6985 specs
[count
++].index
= i
;
6991 specs
[count
] = tmpl
;
6992 specs
[count
++].specific
= 0;
6999 specs
[count
] = tmpl
;
7000 specs
[count
++].specific
= 0;
7004 case IA64_RS_PMC
: /* four or more registers */
7007 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7008 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7011 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7013 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7014 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7017 specs
[count
] = tmpl
;
7018 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7022 specs
[count
] = tmpl
;
7023 specs
[count
++].specific
= 0;
7033 case IA64_RS_PMD
: /* four or more registers */
7036 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7038 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7039 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7042 specs
[count
] = tmpl
;
7043 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7047 specs
[count
] = tmpl
;
7048 specs
[count
++].specific
= 0;
7058 case IA64_RS_RR
: /* eight registers */
7061 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7063 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7064 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7067 specs
[count
] = tmpl
;
7068 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7072 specs
[count
] = tmpl
;
7073 specs
[count
++].specific
= 0;
7077 else if (note
== 0 && !rsrc_write
)
7079 specs
[count
] = tmpl
;
7080 specs
[count
++].specific
= 0;
7088 case IA64_RS_CR_IRR
:
7091 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7092 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7094 && idesc
->operands
[1] == IA64_OPND_CR3
7097 for (i
= 0; i
< 4; i
++)
7099 specs
[count
] = tmpl
;
7100 specs
[count
++].index
= CR_IRR0
+ i
;
7106 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7107 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7109 && regno
<= CR_IRR3
)
7111 specs
[count
] = tmpl
;
7112 specs
[count
++].index
= regno
;
7121 case IA64_RS_CR_LRR
:
7128 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7129 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7130 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7132 specs
[count
] = tmpl
;
7133 specs
[count
++].index
= regno
;
7141 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7143 specs
[count
] = tmpl
;
7144 specs
[count
++].index
=
7145 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7160 else if (rsrc_write
)
7162 if (dep
->specifier
== IA64_RS_FRb
7163 && idesc
->operands
[0] == IA64_OPND_F1
)
7165 specs
[count
] = tmpl
;
7166 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7171 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7173 if (idesc
->operands
[i
] == IA64_OPND_F2
7174 || idesc
->operands
[i
] == IA64_OPND_F3
7175 || idesc
->operands
[i
] == IA64_OPND_F4
)
7177 specs
[count
] = tmpl
;
7178 specs
[count
++].index
=
7179 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7188 /* This reference applies only to the GR whose value is loaded with
7189 data returned from memory. */
7190 specs
[count
] = tmpl
;
7191 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7197 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7198 if (idesc
->operands
[i
] == IA64_OPND_R1
7199 || idesc
->operands
[i
] == IA64_OPND_R2
7200 || idesc
->operands
[i
] == IA64_OPND_R3
)
7202 specs
[count
] = tmpl
;
7203 specs
[count
++].index
=
7204 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7206 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7207 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7208 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7210 specs
[count
] = tmpl
;
7211 specs
[count
++].index
=
7212 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7217 /* Look for anything that reads a GR. */
7218 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7220 if (idesc
->operands
[i
] == IA64_OPND_MR3
7221 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7222 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7223 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7224 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7225 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7226 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7227 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7228 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7229 || ((i
>= idesc
->num_outputs
)
7230 && (idesc
->operands
[i
] == IA64_OPND_R1
7231 || idesc
->operands
[i
] == IA64_OPND_R2
7232 || idesc
->operands
[i
] == IA64_OPND_R3
7233 /* addl source register. */
7234 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7236 specs
[count
] = tmpl
;
7237 specs
[count
++].index
=
7238 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7249 /* This is the same as IA64_RS_PRr, except that the register range is
7250 from 1 - 15, and there are no rotating register reads/writes here. */
7254 for (i
= 1; i
< 16; i
++)
7256 specs
[count
] = tmpl
;
7257 specs
[count
++].index
= i
;
7263 /* Mark only those registers indicated by the mask. */
7266 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7267 for (i
= 1; i
< 16; i
++)
7268 if (mask
& ((valueT
) 1 << i
))
7270 specs
[count
] = tmpl
;
7271 specs
[count
++].index
= i
;
7279 else if (note
== 11) /* note 11 implies note 1 as well */
7283 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7285 if (idesc
->operands
[i
] == IA64_OPND_P1
7286 || idesc
->operands
[i
] == IA64_OPND_P2
)
7288 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7289 if (regno
>= 1 && regno
< 16)
7291 specs
[count
] = tmpl
;
7292 specs
[count
++].index
= regno
;
7302 else if (note
== 12)
7304 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7306 specs
[count
] = tmpl
;
7307 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7314 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7315 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7316 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7317 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7319 if ((idesc
->operands
[0] == IA64_OPND_P1
7320 || idesc
->operands
[0] == IA64_OPND_P2
)
7321 && p1
>= 1 && p1
< 16)
7323 specs
[count
] = tmpl
;
7324 specs
[count
].cmp_type
=
7325 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7326 specs
[count
++].index
= p1
;
7328 if ((idesc
->operands
[1] == IA64_OPND_P1
7329 || idesc
->operands
[1] == IA64_OPND_P2
)
7330 && p2
>= 1 && p2
< 16)
7332 specs
[count
] = tmpl
;
7333 specs
[count
].cmp_type
=
7334 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7335 specs
[count
++].index
= p2
;
7340 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7342 specs
[count
] = tmpl
;
7343 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7345 if (idesc
->operands
[1] == IA64_OPND_PR
)
7347 for (i
= 1; i
< 16; i
++)
7349 specs
[count
] = tmpl
;
7350 specs
[count
++].index
= i
;
7361 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7362 simplified cases of this. */
7366 for (i
= 16; i
< 63; i
++)
7368 specs
[count
] = tmpl
;
7369 specs
[count
++].index
= i
;
7375 /* Mark only those registers indicated by the mask. */
7377 && idesc
->operands
[0] == IA64_OPND_PR
)
7379 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7380 if (mask
& ((valueT
) 1<<16))
7381 for (i
= 16; i
< 63; i
++)
7383 specs
[count
] = tmpl
;
7384 specs
[count
++].index
= i
;
7388 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7390 for (i
= 16; i
< 63; i
++)
7392 specs
[count
] = tmpl
;
7393 specs
[count
++].index
= i
;
7401 else if (note
== 11) /* note 11 implies note 1 as well */
7405 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7407 if (idesc
->operands
[i
] == IA64_OPND_P1
7408 || idesc
->operands
[i
] == IA64_OPND_P2
)
7410 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7411 if (regno
>= 16 && regno
< 63)
7413 specs
[count
] = tmpl
;
7414 specs
[count
++].index
= regno
;
7424 else if (note
== 12)
7426 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7428 specs
[count
] = tmpl
;
7429 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7436 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7437 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7438 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7439 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7441 if ((idesc
->operands
[0] == IA64_OPND_P1
7442 || idesc
->operands
[0] == IA64_OPND_P2
)
7443 && p1
>= 16 && p1
< 63)
7445 specs
[count
] = tmpl
;
7446 specs
[count
].cmp_type
=
7447 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7448 specs
[count
++].index
= p1
;
7450 if ((idesc
->operands
[1] == IA64_OPND_P1
7451 || idesc
->operands
[1] == IA64_OPND_P2
)
7452 && p2
>= 16 && p2
< 63)
7454 specs
[count
] = tmpl
;
7455 specs
[count
].cmp_type
=
7456 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7457 specs
[count
++].index
= p2
;
7462 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7464 specs
[count
] = tmpl
;
7465 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7467 if (idesc
->operands
[1] == IA64_OPND_PR
)
7469 for (i
= 16; i
< 63; i
++)
7471 specs
[count
] = tmpl
;
7472 specs
[count
++].index
= i
;
7484 /* Verify that the instruction is using the PSR bit indicated in
7488 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7490 if (dep
->regindex
< 6)
7492 specs
[count
++] = tmpl
;
7495 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7497 if (dep
->regindex
< 32
7498 || dep
->regindex
== 35
7499 || dep
->regindex
== 36
7500 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7502 specs
[count
++] = tmpl
;
7505 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7507 if (dep
->regindex
< 32
7508 || dep
->regindex
== 35
7509 || dep
->regindex
== 36
7510 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7512 specs
[count
++] = tmpl
;
7517 /* Several PSR bits have very specific dependencies. */
7518 switch (dep
->regindex
)
7521 specs
[count
++] = tmpl
;
7526 specs
[count
++] = tmpl
;
7530 /* Only certain CR accesses use PSR.ic */
7531 if (idesc
->operands
[0] == IA64_OPND_CR3
7532 || idesc
->operands
[1] == IA64_OPND_CR3
)
7535 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7538 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7553 specs
[count
++] = tmpl
;
7562 specs
[count
++] = tmpl
;
7566 /* Only some AR accesses use cpl */
7567 if (idesc
->operands
[0] == IA64_OPND_AR3
7568 || idesc
->operands
[1] == IA64_OPND_AR3
)
7571 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7574 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7581 && regno
<= AR_K7
))))
7583 specs
[count
++] = tmpl
;
7588 specs
[count
++] = tmpl
;
7598 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7600 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7606 if (mask
& ((valueT
) 1 << dep
->regindex
))
7608 specs
[count
++] = tmpl
;
7613 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7614 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7615 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7616 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7618 if (idesc
->operands
[i
] == IA64_OPND_F1
7619 || idesc
->operands
[i
] == IA64_OPND_F2
7620 || idesc
->operands
[i
] == IA64_OPND_F3
7621 || idesc
->operands
[i
] == IA64_OPND_F4
)
7623 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7624 if (reg
>= min
&& reg
<= max
)
7626 specs
[count
++] = tmpl
;
7633 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7634 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7635 /* mfh is read on writes to FR32-127; mfl is read on writes to
7637 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7639 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7641 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7642 if (reg
>= min
&& reg
<= max
)
7644 specs
[count
++] = tmpl
;
7649 else if (note
== 10)
7651 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7653 if (idesc
->operands
[i
] == IA64_OPND_R1
7654 || idesc
->operands
[i
] == IA64_OPND_R2
7655 || idesc
->operands
[i
] == IA64_OPND_R3
)
7657 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7658 if (regno
>= 16 && regno
<= 31)
7660 specs
[count
++] = tmpl
;
7671 case IA64_RS_AR_FPSR
:
7672 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7674 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7675 if (regno
== AR_FPSR
)
7677 specs
[count
++] = tmpl
;
7682 specs
[count
++] = tmpl
;
7687 /* Handle all AR[REG] resources */
7688 if (note
== 0 || note
== 1)
7690 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7691 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7692 && regno
== dep
->regindex
)
7694 specs
[count
++] = tmpl
;
7696 /* other AR[REG] resources may be affected by AR accesses */
7697 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7700 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7701 switch (dep
->regindex
)
7707 if (regno
== AR_BSPSTORE
)
7709 specs
[count
++] = tmpl
;
7713 (regno
== AR_BSPSTORE
7714 || regno
== AR_RNAT
))
7716 specs
[count
++] = tmpl
;
7721 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7724 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7725 switch (dep
->regindex
)
7730 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7732 specs
[count
++] = tmpl
;
7739 specs
[count
++] = tmpl
;
7749 /* Handle all CR[REG] resources */
7750 if (note
== 0 || note
== 1)
7752 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7754 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7755 if (regno
== dep
->regindex
)
7757 specs
[count
++] = tmpl
;
7759 else if (!rsrc_write
)
7761 /* Reads from CR[IVR] affect other resources. */
7762 if (regno
== CR_IVR
)
7764 if ((dep
->regindex
>= CR_IRR0
7765 && dep
->regindex
<= CR_IRR3
)
7766 || dep
->regindex
== CR_TPR
)
7768 specs
[count
++] = tmpl
;
7775 specs
[count
++] = tmpl
;
7784 case IA64_RS_INSERVICE
:
7785 /* look for write of EOI (67) or read of IVR (65) */
7786 if ((idesc
->operands
[0] == IA64_OPND_CR3
7787 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7788 || (idesc
->operands
[1] == IA64_OPND_CR3
7789 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7791 specs
[count
++] = tmpl
;
7798 specs
[count
++] = tmpl
;
7809 specs
[count
++] = tmpl
;
7813 /* Check if any of the registers accessed are in the rotating region.
7814 mov to/from pr accesses CFM only when qp_regno is in the rotating
7816 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7818 if (idesc
->operands
[i
] == IA64_OPND_R1
7819 || idesc
->operands
[i
] == IA64_OPND_R2
7820 || idesc
->operands
[i
] == IA64_OPND_R3
)
7822 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7823 /* Assumes that md.rot.num_regs is always valid */
7824 if (md
.rot
.num_regs
> 0
7826 && num
< 31 + md
.rot
.num_regs
)
7828 specs
[count
] = tmpl
;
7829 specs
[count
++].specific
= 0;
7832 else if (idesc
->operands
[i
] == IA64_OPND_F1
7833 || idesc
->operands
[i
] == IA64_OPND_F2
7834 || idesc
->operands
[i
] == IA64_OPND_F3
7835 || idesc
->operands
[i
] == IA64_OPND_F4
)
7837 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7840 specs
[count
] = tmpl
;
7841 specs
[count
++].specific
= 0;
7844 else if (idesc
->operands
[i
] == IA64_OPND_P1
7845 || idesc
->operands
[i
] == IA64_OPND_P2
)
7847 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7850 specs
[count
] = tmpl
;
7851 specs
[count
++].specific
= 0;
7855 if (CURR_SLOT
.qp_regno
> 15)
7857 specs
[count
] = tmpl
;
7858 specs
[count
++].specific
= 0;
7863 /* This is the same as IA64_RS_PRr, except simplified to account for
7864 the fact that there is only one register. */
7868 specs
[count
++] = tmpl
;
7873 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
7874 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7875 if (mask
& ((valueT
) 1 << 63))
7876 specs
[count
++] = tmpl
;
7878 else if (note
== 11)
7880 if ((idesc
->operands
[0] == IA64_OPND_P1
7881 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
7882 || (idesc
->operands
[1] == IA64_OPND_P2
7883 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
7885 specs
[count
++] = tmpl
;
7888 else if (note
== 12)
7890 if (CURR_SLOT
.qp_regno
== 63)
7892 specs
[count
++] = tmpl
;
7899 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7900 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7901 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7902 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7905 && (idesc
->operands
[0] == IA64_OPND_P1
7906 || idesc
->operands
[0] == IA64_OPND_P2
))
7908 specs
[count
] = tmpl
;
7909 specs
[count
++].cmp_type
=
7910 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7913 && (idesc
->operands
[1] == IA64_OPND_P1
7914 || idesc
->operands
[1] == IA64_OPND_P2
))
7916 specs
[count
] = tmpl
;
7917 specs
[count
++].cmp_type
=
7918 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7923 if (CURR_SLOT
.qp_regno
== 63)
7925 specs
[count
++] = tmpl
;
7936 /* FIXME we can identify some individual RSE written resources, but RSE
7937 read resources have not yet been completely identified, so for now
7938 treat RSE as a single resource */
7939 if (strncmp (idesc
->name
, "mov", 3) == 0)
7943 if (idesc
->operands
[0] == IA64_OPND_AR3
7944 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
7946 specs
[count
] = tmpl
;
7947 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7952 if (idesc
->operands
[0] == IA64_OPND_AR3
)
7954 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
7955 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
7957 specs
[count
++] = tmpl
;
7960 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7962 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
7963 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
7964 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
7966 specs
[count
++] = tmpl
;
7973 specs
[count
++] = tmpl
;
7978 /* FIXME -- do any of these need to be non-specific? */
7979 specs
[count
++] = tmpl
;
7983 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
7990 /* Clear branch flags on marked resources. This breaks the link between the
7991 QP of the marking instruction and a subsequent branch on the same QP. */
7994 clear_qp_branch_flag (mask
)
7998 for (i
= 0; i
< regdepslen
; i
++)
8000 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8001 if ((bit
& mask
) != 0)
8003 regdeps
[i
].link_to_qp_branch
= 0;
8008 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8010 Any changes to a PR clears the mutex relations which include that PR. */
8013 clear_qp_mutex (mask
)
8019 while (i
< qp_mutexeslen
)
8021 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8025 fprintf (stderr
, " Clearing mutex relation");
8026 print_prmask (qp_mutexes
[i
].prmask
);
8027 fprintf (stderr
, "\n");
8029 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8036 /* Clear implies relations which contain PRs in the given masks.
8037 P1_MASK indicates the source of the implies relation, while P2_MASK
8038 indicates the implied PR. */
8041 clear_qp_implies (p1_mask
, p2_mask
)
8048 while (i
< qp_implieslen
)
8050 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8051 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8054 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8055 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8056 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8063 /* Add the PRs specified to the list of implied relations. */
8066 add_qp_imply (p1
, p2
)
8073 /* p0 is not meaningful here. */
8074 if (p1
== 0 || p2
== 0)
8080 /* If it exists already, ignore it. */
8081 for (i
= 0; i
< qp_implieslen
; i
++)
8083 if (qp_implies
[i
].p1
== p1
8084 && qp_implies
[i
].p2
== p2
8085 && qp_implies
[i
].path
== md
.path
8086 && !qp_implies
[i
].p2_branched
)
8090 if (qp_implieslen
== qp_impliestotlen
)
8092 qp_impliestotlen
+= 20;
8093 qp_implies
= (struct qp_imply
*)
8094 xrealloc ((void *) qp_implies
,
8095 qp_impliestotlen
* sizeof (struct qp_imply
));
8098 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8099 qp_implies
[qp_implieslen
].p1
= p1
;
8100 qp_implies
[qp_implieslen
].p2
= p2
;
8101 qp_implies
[qp_implieslen
].path
= md
.path
;
8102 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8104 /* Add in the implied transitive relations; for everything that p2 implies,
8105 make p1 imply that, too; for everything that implies p1, make it imply p2
8107 for (i
= 0; i
< qp_implieslen
; i
++)
8109 if (qp_implies
[i
].p1
== p2
)
8110 add_qp_imply (p1
, qp_implies
[i
].p2
);
8111 if (qp_implies
[i
].p2
== p1
)
8112 add_qp_imply (qp_implies
[i
].p1
, p2
);
8114 /* Add in mutex relations implied by this implies relation; for each mutex
8115 relation containing p2, duplicate it and replace p2 with p1. */
8116 bit
= (valueT
) 1 << p1
;
8117 mask
= (valueT
) 1 << p2
;
8118 for (i
= 0; i
< qp_mutexeslen
; i
++)
8120 if (qp_mutexes
[i
].prmask
& mask
)
8121 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8125 /* Add the PRs specified in the mask to the mutex list; this means that only
8126 one of the PRs can be true at any time. PR0 should never be included in
8136 if (qp_mutexeslen
== qp_mutexestotlen
)
8138 qp_mutexestotlen
+= 20;
8139 qp_mutexes
= (struct qpmutex
*)
8140 xrealloc ((void *) qp_mutexes
,
8141 qp_mutexestotlen
* sizeof (struct qpmutex
));
8145 fprintf (stderr
, " Registering mutex on");
8146 print_prmask (mask
);
8147 fprintf (stderr
, "\n");
8149 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8150 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8154 clear_register_values ()
8158 fprintf (stderr
, " Clearing register values\n");
8159 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8160 gr_values
[i
].known
= 0;
8163 /* Keep track of register values/changes which affect DV tracking.
8165 optimization note: should add a flag to classes of insns where otherwise we
8166 have to examine a group of strings to identify them. */
8169 note_register_values (idesc
)
8170 struct ia64_opcode
*idesc
;
8172 valueT qp_changemask
= 0;
8175 /* Invalidate values for registers being written to. */
8176 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8178 if (idesc
->operands
[i
] == IA64_OPND_R1
8179 || idesc
->operands
[i
] == IA64_OPND_R2
8180 || idesc
->operands
[i
] == IA64_OPND_R3
)
8182 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8183 if (regno
> 0 && regno
< NELEMS (gr_values
))
8184 gr_values
[regno
].known
= 0;
8186 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8188 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8189 if (regno
> 0 && regno
< 4)
8190 gr_values
[regno
].known
= 0;
8192 else if (idesc
->operands
[i
] == IA64_OPND_P1
8193 || idesc
->operands
[i
] == IA64_OPND_P2
)
8195 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8196 qp_changemask
|= (valueT
) 1 << regno
;
8198 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8200 if (idesc
->operands
[2] & (valueT
) 0x10000)
8201 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8203 qp_changemask
= idesc
->operands
[2];
8206 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8208 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8209 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8211 qp_changemask
= idesc
->operands
[1];
8212 qp_changemask
&= ~(valueT
) 0xFFFF;
8217 /* Always clear qp branch flags on any PR change. */
8218 /* FIXME there may be exceptions for certain compares. */
8219 clear_qp_branch_flag (qp_changemask
);
8221 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8222 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8224 qp_changemask
|= ~(valueT
) 0xFFFF;
8225 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8227 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8228 gr_values
[i
].known
= 0;
8230 clear_qp_mutex (qp_changemask
);
8231 clear_qp_implies (qp_changemask
, qp_changemask
);
8233 /* After a call, all register values are undefined, except those marked
8235 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8236 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8238 /* FIXME keep GR values which are marked as "safe_across_calls" */
8239 clear_register_values ();
8240 clear_qp_mutex (~qp_safe_across_calls
);
8241 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8242 clear_qp_branch_flag (~qp_safe_across_calls
);
8244 else if (is_interruption_or_rfi (idesc
)
8245 || is_taken_branch (idesc
))
8247 clear_register_values ();
8248 clear_qp_mutex (~(valueT
) 0);
8249 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8251 /* Look for mutex and implies relations. */
8252 else if ((idesc
->operands
[0] == IA64_OPND_P1
8253 || idesc
->operands
[0] == IA64_OPND_P2
)
8254 && (idesc
->operands
[1] == IA64_OPND_P1
8255 || idesc
->operands
[1] == IA64_OPND_P2
))
8257 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8258 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8259 valueT p1mask
= (valueT
) 1 << p1
;
8260 valueT p2mask
= (valueT
) 1 << p2
;
8262 /* If one of the PRs is PR0, we can't really do anything. */
8263 if (p1
== 0 || p2
== 0)
8266 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8268 /* In general, clear mutexes and implies which include P1 or P2,
8269 with the following exceptions. */
8270 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8272 add_qp_mutex (p1mask
| p2mask
);
8273 clear_qp_implies (p2mask
, p1mask
);
8275 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8277 add_qp_mutex (p1mask
| p2mask
);
8278 clear_qp_implies (p1mask
, p2mask
);
8280 else if (strstr (idesc
->name
, ".and") != NULL
)
8282 clear_qp_implies (0, p1mask
| p2mask
);
8284 else if (strstr (idesc
->name
, ".or") != NULL
)
8286 clear_qp_mutex (p1mask
| p2mask
);
8287 clear_qp_implies (p1mask
| p2mask
, 0);
8291 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8292 if (strstr (idesc
->name
, ".unc") != NULL
)
8294 add_qp_mutex (p1mask
| p2mask
);
8295 if (CURR_SLOT
.qp_regno
!= 0)
8297 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8298 CURR_SLOT
.qp_regno
);
8299 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8300 CURR_SLOT
.qp_regno
);
8303 else if (CURR_SLOT
.qp_regno
== 0)
8305 add_qp_mutex (p1mask
| p2mask
);
8309 clear_qp_mutex (p1mask
| p2mask
);
8313 /* Look for mov imm insns into GRs. */
8314 else if (idesc
->operands
[0] == IA64_OPND_R1
8315 && (idesc
->operands
[1] == IA64_OPND_IMM22
8316 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8317 && (strcmp (idesc
->name
, "mov") == 0
8318 || strcmp (idesc
->name
, "movl") == 0))
8320 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8321 if (regno
> 0 && regno
< NELEMS (gr_values
))
8323 gr_values
[regno
].known
= 1;
8324 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8325 gr_values
[regno
].path
= md
.path
;
8328 fprintf (stderr
, " Know gr%d = ", regno
);
8329 fprintf_vma (stderr
, gr_values
[regno
].value
);
8330 fputs ("\n", stderr
);
8336 clear_qp_mutex (qp_changemask
);
8337 clear_qp_implies (qp_changemask
, qp_changemask
);
8341 /* Return whether the given predicate registers are currently mutex. */
8344 qp_mutex (p1
, p2
, path
)
8354 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8355 for (i
= 0; i
< qp_mutexeslen
; i
++)
8357 if (qp_mutexes
[i
].path
>= path
8358 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8365 /* Return whether the given resource is in the given insn's list of chks
8366 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8370 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8372 struct ia64_opcode
*idesc
;
8377 struct rsrc specs
[MAX_SPECS
];
8380 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8381 we don't need to check. One exception is note 11, which indicates that
8382 target predicates are written regardless of PR[qp]. */
8383 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8387 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8390 /* UNAT checking is a bit more specific than other resources */
8391 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8392 && specs
[count
].mem_offset
.hint
8393 && rs
->mem_offset
.hint
)
8395 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8397 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8398 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8405 /* Skip apparent PR write conflicts where both writes are an AND or both
8406 writes are an OR. */
8407 if (rs
->dependency
->specifier
== IA64_RS_PR
8408 || rs
->dependency
->specifier
== IA64_RS_PRr
8409 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8411 if (specs
[count
].cmp_type
!= CMP_NONE
8412 && specs
[count
].cmp_type
== rs
->cmp_type
)
8415 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8416 dv_mode
[rs
->dependency
->mode
],
8417 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8418 specs
[count
].index
: 63);
8423 " %s on parallel compare conflict %s vs %s on PR%d\n",
8424 dv_mode
[rs
->dependency
->mode
],
8425 dv_cmp_type
[rs
->cmp_type
],
8426 dv_cmp_type
[specs
[count
].cmp_type
],
8427 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8428 specs
[count
].index
: 63);
8432 /* If either resource is not specific, conservatively assume a conflict
8434 if (!specs
[count
].specific
|| !rs
->specific
)
8436 else if (specs
[count
].index
== rs
->index
)
8441 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8447 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8448 insert a stop to create the break. Update all resource dependencies
8449 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8450 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8451 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8455 insn_group_break (insert_stop
, qp_regno
, save_current
)
8462 if (insert_stop
&& md
.num_slots_in_use
> 0)
8463 PREV_SLOT
.end_of_insn_group
= 1;
8467 fprintf (stderr
, " Insn group break%s",
8468 (insert_stop
? " (w/stop)" : ""));
8470 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8471 fprintf (stderr
, "\n");
8475 while (i
< regdepslen
)
8477 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8480 && regdeps
[i
].qp_regno
!= qp_regno
)
8487 && CURR_SLOT
.src_file
== regdeps
[i
].file
8488 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8494 /* clear dependencies which are automatically cleared by a stop, or
8495 those that have reached the appropriate state of insn serialization */
8496 if (dep
->semantics
== IA64_DVS_IMPLIED
8497 || dep
->semantics
== IA64_DVS_IMPLIEDF
8498 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8500 print_dependency ("Removing", i
);
8501 regdeps
[i
] = regdeps
[--regdepslen
];
8505 if (dep
->semantics
== IA64_DVS_DATA
8506 || dep
->semantics
== IA64_DVS_INSTR
8507 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8509 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8510 regdeps
[i
].insn_srlz
= STATE_STOP
;
8511 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8512 regdeps
[i
].data_srlz
= STATE_STOP
;
8519 /* Add the given resource usage spec to the list of active dependencies. */
8522 mark_resource (idesc
, dep
, spec
, depind
, path
)
8523 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8524 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
8529 if (regdepslen
== regdepstotlen
)
8531 regdepstotlen
+= 20;
8532 regdeps
= (struct rsrc
*)
8533 xrealloc ((void *) regdeps
,
8534 regdepstotlen
* sizeof (struct rsrc
));
8537 regdeps
[regdepslen
] = *spec
;
8538 regdeps
[regdepslen
].depind
= depind
;
8539 regdeps
[regdepslen
].path
= path
;
8540 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8541 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8543 print_dependency ("Adding", regdepslen
);
8549 print_dependency (action
, depind
)
8555 fprintf (stderr
, " %s %s '%s'",
8556 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8557 (regdeps
[depind
].dependency
)->name
);
8558 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8559 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8560 if (regdeps
[depind
].mem_offset
.hint
)
8562 fputs (" ", stderr
);
8563 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
8564 fputs ("+", stderr
);
8565 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
8567 fprintf (stderr
, "\n");
8572 instruction_serialization ()
8576 fprintf (stderr
, " Instruction serialization\n");
8577 for (i
= 0; i
< regdepslen
; i
++)
8578 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8579 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8583 data_serialization ()
8587 fprintf (stderr
, " Data serialization\n");
8588 while (i
< regdepslen
)
8590 if (regdeps
[i
].data_srlz
== STATE_STOP
8591 /* Note: as of 991210, all "other" dependencies are cleared by a
8592 data serialization. This might change with new tables */
8593 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8595 print_dependency ("Removing", i
);
8596 regdeps
[i
] = regdeps
[--regdepslen
];
8603 /* Insert stops and serializations as needed to avoid DVs. */
8606 remove_marked_resource (rs
)
8609 switch (rs
->dependency
->semantics
)
8611 case IA64_DVS_SPECIFIC
:
8613 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8614 /* ...fall through... */
8615 case IA64_DVS_INSTR
:
8617 fprintf (stderr
, "Inserting instr serialization\n");
8618 if (rs
->insn_srlz
< STATE_STOP
)
8619 insn_group_break (1, 0, 0);
8620 if (rs
->insn_srlz
< STATE_SRLZ
)
8622 int oldqp
= CURR_SLOT
.qp_regno
;
8623 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8624 /* Manually jam a srlz.i insn into the stream */
8625 CURR_SLOT
.qp_regno
= 0;
8626 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8627 instruction_serialization ();
8628 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8629 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8631 CURR_SLOT
.qp_regno
= oldqp
;
8632 CURR_SLOT
.idesc
= oldidesc
;
8634 insn_group_break (1, 0, 0);
8636 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8637 "other" types of DV are eliminated
8638 by a data serialization */
8641 fprintf (stderr
, "Inserting data serialization\n");
8642 if (rs
->data_srlz
< STATE_STOP
)
8643 insn_group_break (1, 0, 0);
8645 int oldqp
= CURR_SLOT
.qp_regno
;
8646 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8647 /* Manually jam a srlz.d insn into the stream */
8648 CURR_SLOT
.qp_regno
= 0;
8649 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8650 data_serialization ();
8651 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8652 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8654 CURR_SLOT
.qp_regno
= oldqp
;
8655 CURR_SLOT
.idesc
= oldidesc
;
8658 case IA64_DVS_IMPLIED
:
8659 case IA64_DVS_IMPLIEDF
:
8661 fprintf (stderr
, "Inserting stop\n");
8662 insn_group_break (1, 0, 0);
8669 /* Check the resources used by the given opcode against the current dependency
8672 The check is run once for each execution path encountered. In this case,
8673 a unique execution path is the sequence of instructions following a code
8674 entry point, e.g. the following has three execution paths, one starting
8675 at L0, one at L1, and one at L2.
8684 check_dependencies (idesc
)
8685 struct ia64_opcode
*idesc
;
8687 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8691 /* Note that the number of marked resources may change within the
8692 loop if in auto mode. */
8694 while (i
< regdepslen
)
8696 struct rsrc
*rs
= ®deps
[i
];
8697 const struct ia64_dependency
*dep
= rs
->dependency
;
8702 if (dep
->semantics
== IA64_DVS_NONE
8703 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8709 note
= NOTE (opdeps
->chks
[chkind
]);
8711 /* Check this resource against each execution path seen thus far. */
8712 for (path
= 0; path
<= md
.path
; path
++)
8716 /* If the dependency wasn't on the path being checked, ignore it. */
8717 if (rs
->path
< path
)
8720 /* If the QP for this insn implies a QP which has branched, don't
8721 bother checking. Ed. NOTE: I don't think this check is terribly
8722 useful; what's the point of generating code which will only be
8723 reached if its QP is zero?
8724 This code was specifically inserted to handle the following code,
8725 based on notes from Intel's DV checking code, where p1 implies p2.
8731 if (CURR_SLOT
.qp_regno
!= 0)
8735 for (implies
= 0; implies
< qp_implieslen
; implies
++)
8737 if (qp_implies
[implies
].path
>= path
8738 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8739 && qp_implies
[implies
].p2_branched
)
8749 if ((matchtype
= resources_match (rs
, idesc
, note
,
8750 CURR_SLOT
.qp_regno
, path
)) != 0)
8753 char pathmsg
[256] = "";
8754 char indexmsg
[256] = "";
8755 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8758 sprintf (pathmsg
, " when entry is at label '%s'",
8759 md
.entry_labels
[path
- 1]);
8760 if (rs
->specific
&& rs
->index
!= 0)
8761 sprintf (indexmsg
, ", specific resource number is %d",
8763 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8765 (certain
? "violates" : "may violate"),
8766 dv_mode
[dep
->mode
], dep
->name
,
8767 dv_sem
[dep
->semantics
],
8770 if (md
.explicit_mode
)
8772 as_warn ("%s", msg
);
8774 as_warn (_("Only the first path encountering the conflict "
8776 as_warn_where (rs
->file
, rs
->line
,
8777 _("This is the location of the "
8778 "conflicting usage"));
8779 /* Don't bother checking other paths, to avoid duplicating
8786 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8788 remove_marked_resource (rs
);
8790 /* since the set of dependencies has changed, start over */
8791 /* FIXME -- since we're removing dvs as we go, we
8792 probably don't really need to start over... */
8805 /* Register new dependencies based on the given opcode. */
8808 mark_resources (idesc
)
8809 struct ia64_opcode
*idesc
;
8812 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8813 int add_only_qp_reads
= 0;
8815 /* A conditional branch only uses its resources if it is taken; if it is
8816 taken, we stop following that path. The other branch types effectively
8817 *always* write their resources. If it's not taken, register only QP
8819 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8821 add_only_qp_reads
= 1;
8825 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8827 for (i
= 0; i
< opdeps
->nregs
; i
++)
8829 const struct ia64_dependency
*dep
;
8830 struct rsrc specs
[MAX_SPECS
];
8835 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8836 note
= NOTE (opdeps
->regs
[i
]);
8838 if (add_only_qp_reads
8839 && !(dep
->mode
== IA64_DV_WAR
8840 && (dep
->specifier
== IA64_RS_PR
8841 || dep
->specifier
== IA64_RS_PRr
8842 || dep
->specifier
== IA64_RS_PR63
)))
8845 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8848 if (md
.debug_dv
&& !count
)
8849 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8850 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
8855 mark_resource (idesc
, dep
, &specs
[count
],
8856 DEP (opdeps
->regs
[i
]), md
.path
);
8859 /* The execution path may affect register values, which may in turn
8860 affect which indirect-access resources are accessed. */
8861 switch (dep
->specifier
)
8873 for (path
= 0; path
< md
.path
; path
++)
8875 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
8877 mark_resource (idesc
, dep
, &specs
[count
],
8878 DEP (opdeps
->regs
[i
]), path
);
8885 /* Remove dependencies when they no longer apply. */
8888 update_dependencies (idesc
)
8889 struct ia64_opcode
*idesc
;
8893 if (strcmp (idesc
->name
, "srlz.i") == 0)
8895 instruction_serialization ();
8897 else if (strcmp (idesc
->name
, "srlz.d") == 0)
8899 data_serialization ();
8901 else if (is_interruption_or_rfi (idesc
)
8902 || is_taken_branch (idesc
))
8904 /* Although technically the taken branch doesn't clear dependencies
8905 which require a srlz.[id], we don't follow the branch; the next
8906 instruction is assumed to start with a clean slate. */
8910 else if (is_conditional_branch (idesc
)
8911 && CURR_SLOT
.qp_regno
!= 0)
8913 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
8915 for (i
= 0; i
< qp_implieslen
; i
++)
8917 /* If the conditional branch's predicate is implied by the predicate
8918 in an existing dependency, remove that dependency. */
8919 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
8922 /* Note that this implied predicate takes a branch so that if
8923 a later insn generates a DV but its predicate implies this
8924 one, we can avoid the false DV warning. */
8925 qp_implies
[i
].p2_branched
= 1;
8926 while (depind
< regdepslen
)
8928 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
8930 print_dependency ("Removing", depind
);
8931 regdeps
[depind
] = regdeps
[--regdepslen
];
8938 /* Any marked resources which have this same predicate should be
8939 cleared, provided that the QP hasn't been modified between the
8940 marking instruction and the branch. */
8943 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
8948 while (i
< regdepslen
)
8950 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
8951 && regdeps
[i
].link_to_qp_branch
8952 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
8953 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
8955 /* Treat like a taken branch */
8956 print_dependency ("Removing", i
);
8957 regdeps
[i
] = regdeps
[--regdepslen
];
8966 /* Examine the current instruction for dependency violations. */
8970 struct ia64_opcode
*idesc
;
8974 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
8975 idesc
->name
, CURR_SLOT
.src_line
,
8976 idesc
->dependencies
->nchks
,
8977 idesc
->dependencies
->nregs
);
8980 /* Look through the list of currently marked resources; if the current
8981 instruction has the dependency in its chks list which uses that resource,
8982 check against the specific resources used. */
8983 check_dependencies (idesc
);
8985 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8986 then add them to the list of marked resources. */
8987 mark_resources (idesc
);
8989 /* There are several types of dependency semantics, and each has its own
8990 requirements for being cleared
8992 Instruction serialization (insns separated by interruption, rfi, or
8993 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8995 Data serialization (instruction serialization, or writer + srlz.d +
8996 reader, where writer and srlz.d are in separate groups) clears
8997 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8998 always be the case).
9000 Instruction group break (groups separated by stop, taken branch,
9001 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9003 update_dependencies (idesc
);
9005 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9006 warning. Keep track of as many as possible that are useful. */
9007 note_register_values (idesc
);
9009 /* We don't need or want this anymore. */
9010 md
.mem_offset
.hint
= 0;
9015 /* Translate one line of assembly. Pseudo ops and labels do not show
9021 char *saved_input_line_pointer
, *mnemonic
;
9022 const struct pseudo_opcode
*pdesc
;
9023 struct ia64_opcode
*idesc
;
9024 unsigned char qp_regno
;
9028 saved_input_line_pointer
= input_line_pointer
;
9029 input_line_pointer
= str
;
9031 /* extract the opcode (mnemonic): */
9033 mnemonic
= input_line_pointer
;
9034 ch
= get_symbol_end ();
9035 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9038 *input_line_pointer
= ch
;
9039 (*pdesc
->handler
) (pdesc
->arg
);
9043 /* Find the instruction descriptor matching the arguments. */
9045 idesc
= ia64_find_opcode (mnemonic
);
9046 *input_line_pointer
= ch
;
9049 as_bad ("Unknown opcode `%s'", mnemonic
);
9053 idesc
= parse_operands (idesc
);
9057 /* Handle the dynamic ops we can handle now: */
9058 if (idesc
->type
== IA64_TYPE_DYN
)
9060 if (strcmp (idesc
->name
, "add") == 0)
9062 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9063 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9067 ia64_free_opcode (idesc
);
9068 idesc
= ia64_find_opcode (mnemonic
);
9070 know (!idesc
->next
);
9073 else if (strcmp (idesc
->name
, "mov") == 0)
9075 enum ia64_opnd opnd1
, opnd2
;
9078 opnd1
= idesc
->operands
[0];
9079 opnd2
= idesc
->operands
[1];
9080 if (opnd1
== IA64_OPND_AR3
)
9082 else if (opnd2
== IA64_OPND_AR3
)
9086 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9087 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9091 ia64_free_opcode (idesc
);
9092 idesc
= ia64_find_opcode (mnemonic
);
9093 while (idesc
!= NULL
9094 && (idesc
->operands
[0] != opnd1
9095 || idesc
->operands
[1] != opnd2
))
9096 idesc
= get_next_opcode (idesc
);
9101 if (md
.qp
.X_op
== O_register
)
9103 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9104 md
.qp
.X_op
= O_absent
;
9107 flags
= idesc
->flags
;
9109 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9110 insn_group_break (1, 0, 0);
9112 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9114 as_bad ("`%s' cannot be predicated", idesc
->name
);
9118 /* Build the instruction. */
9119 CURR_SLOT
.qp_regno
= qp_regno
;
9120 CURR_SLOT
.idesc
= idesc
;
9121 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9122 dwarf2_where (&CURR_SLOT
.debug_line
);
9124 /* Add unwind entry, if there is one. */
9125 if (unwind
.current_entry
)
9127 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9128 unwind
.current_entry
= NULL
;
9131 /* Check for dependency violations. */
9135 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9136 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9139 if ((flags
& IA64_OPCODE_LAST
) != 0)
9140 insn_group_break (1, 0, 0);
9142 md
.last_text_seg
= now_seg
;
9145 input_line_pointer
= saved_input_line_pointer
;
9148 /* Called when symbol NAME cannot be found in the symbol table.
9149 Should be used for dynamic valued symbols only. */
9152 md_undefined_symbol (name
)
9153 char *name ATTRIBUTE_UNUSED
;
9158 /* Called for any expression that can not be recognized. When the
9159 function is called, `input_line_pointer' will point to the start of
9166 enum pseudo_type pseudo_type
;
9171 switch (*input_line_pointer
)
9174 /* Find what relocation pseudo-function we're dealing with. */
9176 ch
= *++input_line_pointer
;
9177 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9178 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9180 len
= strlen (pseudo_func
[i
].name
);
9181 if (strncmp (pseudo_func
[i
].name
+ 1,
9182 input_line_pointer
+ 1, len
- 1) == 0
9183 && !is_part_of_name (input_line_pointer
[len
]))
9185 input_line_pointer
+= len
;
9186 pseudo_type
= pseudo_func
[i
].type
;
9190 switch (pseudo_type
)
9192 case PSEUDO_FUNC_RELOC
:
9194 if (*input_line_pointer
!= '(')
9196 as_bad ("Expected '('");
9200 ++input_line_pointer
;
9202 if (*input_line_pointer
++ != ')')
9204 as_bad ("Missing ')'");
9207 if (e
->X_op
!= O_symbol
)
9209 if (e
->X_op
!= O_pseudo_fixup
)
9211 as_bad ("Not a symbolic expression");
9214 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9215 && i
== FUNC_LT_RELATIVE
)
9216 i
= FUNC_LT_FPTR_RELATIVE
;
9219 as_bad ("Illegal combination of relocation functions");
9223 /* Make sure gas doesn't get rid of local symbols that are used
9225 e
->X_op
= O_pseudo_fixup
;
9226 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9229 case PSEUDO_FUNC_CONST
:
9230 e
->X_op
= O_constant
;
9231 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9234 case PSEUDO_FUNC_REG
:
9235 e
->X_op
= O_register
;
9236 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9240 name
= input_line_pointer
- 1;
9242 as_bad ("Unknown pseudo function `%s'", name
);
9248 ++input_line_pointer
;
9250 if (*input_line_pointer
!= ']')
9252 as_bad ("Closing bracket misssing");
9257 if (e
->X_op
!= O_register
)
9258 as_bad ("Register expected as index");
9260 ++input_line_pointer
;
9271 ignore_rest_of_line ();
9274 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9275 a section symbol plus some offset. For relocs involving @fptr(),
9276 directives we don't want such adjustments since we need to have the
9277 original symbol's name in the reloc. */
9279 ia64_fix_adjustable (fix
)
9282 /* Prevent all adjustments to global symbols */
9283 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9286 switch (fix
->fx_r_type
)
9288 case BFD_RELOC_IA64_FPTR64I
:
9289 case BFD_RELOC_IA64_FPTR32MSB
:
9290 case BFD_RELOC_IA64_FPTR32LSB
:
9291 case BFD_RELOC_IA64_FPTR64MSB
:
9292 case BFD_RELOC_IA64_FPTR64LSB
:
9293 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9294 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9304 ia64_force_relocation (fix
)
9307 switch (fix
->fx_r_type
)
9309 case BFD_RELOC_IA64_FPTR64I
:
9310 case BFD_RELOC_IA64_FPTR32MSB
:
9311 case BFD_RELOC_IA64_FPTR32LSB
:
9312 case BFD_RELOC_IA64_FPTR64MSB
:
9313 case BFD_RELOC_IA64_FPTR64LSB
:
9315 case BFD_RELOC_IA64_LTOFF22
:
9316 case BFD_RELOC_IA64_LTOFF64I
:
9317 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9318 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9319 case BFD_RELOC_IA64_PLTOFF22
:
9320 case BFD_RELOC_IA64_PLTOFF64I
:
9321 case BFD_RELOC_IA64_PLTOFF64MSB
:
9322 case BFD_RELOC_IA64_PLTOFF64LSB
:
9331 /* Decide from what point a pc-relative relocation is relative to,
9332 relative to the pc-relative fixup. Er, relatively speaking. */
9334 ia64_pcrel_from_section (fix
, sec
)
9338 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9340 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9346 /* This is called whenever some data item (not an instruction) needs a
9347 fixup. We pick the right reloc code depending on the byteorder
9348 currently in effect. */
9350 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9356 bfd_reloc_code_real_type code
;
9361 /* There are no reloc for 8 and 16 bit quantities, but we allow
9362 them here since they will work fine as long as the expression
9363 is fully defined at the end of the pass over the source file. */
9364 case 1: code
= BFD_RELOC_8
; break;
9365 case 2: code
= BFD_RELOC_16
; break;
9367 if (target_big_endian
)
9368 code
= BFD_RELOC_IA64_DIR32MSB
;
9370 code
= BFD_RELOC_IA64_DIR32LSB
;
9374 if (target_big_endian
)
9375 code
= BFD_RELOC_IA64_DIR64MSB
;
9377 code
= BFD_RELOC_IA64_DIR64LSB
;
9381 as_bad ("Unsupported fixup size %d", nbytes
);
9382 ignore_rest_of_line ();
9385 if (exp
->X_op
== O_pseudo_fixup
)
9388 exp
->X_op
= O_symbol
;
9389 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9391 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9392 /* We need to store the byte order in effect in case we're going
9393 to fix an 8 or 16 bit relocation (for which there no real
9394 relocs available). See md_apply_fix(). */
9395 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9398 /* Return the actual relocation we wish to associate with the pseudo
9399 reloc described by SYM and R_TYPE. SYM should be one of the
9400 symbols in the pseudo_func array, or NULL. */
9402 static bfd_reloc_code_real_type
9403 ia64_gen_real_reloc_type (sym
, r_type
)
9405 bfd_reloc_code_real_type r_type
;
9407 bfd_reloc_code_real_type
new = 0;
9414 switch (S_GET_VALUE (sym
))
9416 case FUNC_FPTR_RELATIVE
:
9419 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9420 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9421 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9422 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9423 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9428 case FUNC_GP_RELATIVE
:
9431 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9432 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9433 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9434 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9435 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9436 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9441 case FUNC_LT_RELATIVE
:
9444 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9445 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9450 case FUNC_PC_RELATIVE
:
9453 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9454 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9455 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9456 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9457 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9458 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9463 case FUNC_PLT_RELATIVE
:
9466 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9467 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9468 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9469 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9474 case FUNC_SEC_RELATIVE
:
9477 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9478 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9479 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9480 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9485 case FUNC_SEG_RELATIVE
:
9488 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9489 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9490 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9491 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9496 case FUNC_LTV_RELATIVE
:
9499 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9500 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9501 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9502 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9507 case FUNC_LT_FPTR_RELATIVE
:
9510 case BFD_RELOC_IA64_IMM22
:
9511 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9512 case BFD_RELOC_IA64_IMM64
:
9513 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9521 /* Hmmmm. Should this ever occur? */
9528 /* Here is where generate the appropriate reloc for pseudo relocation
9531 ia64_validate_fix (fix
)
9534 switch (fix
->fx_r_type
)
9536 case BFD_RELOC_IA64_FPTR64I
:
9537 case BFD_RELOC_IA64_FPTR32MSB
:
9538 case BFD_RELOC_IA64_FPTR64LSB
:
9539 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9540 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9541 if (fix
->fx_offset
!= 0)
9542 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9543 "No addend allowed in @fptr() relocation");
9553 fix_insn (fix
, odesc
, value
)
9555 const struct ia64_operand
*odesc
;
9558 bfd_vma insn
[3], t0
, t1
, control_bits
;
9563 slot
= fix
->fx_where
& 0x3;
9564 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9566 /* Bundles are always in little-endian byte order */
9567 t0
= bfd_getl64 (fixpos
);
9568 t1
= bfd_getl64 (fixpos
+ 8);
9569 control_bits
= t0
& 0x1f;
9570 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9571 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9572 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9575 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9577 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9578 insn
[2] |= (((value
& 0x7f) << 13)
9579 | (((value
>> 7) & 0x1ff) << 27)
9580 | (((value
>> 16) & 0x1f) << 22)
9581 | (((value
>> 21) & 0x1) << 21)
9582 | (((value
>> 63) & 0x1) << 36));
9584 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9586 if (value
& ~0x3fffffffffffffffULL
)
9587 err
= "integer operand out of range";
9588 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9589 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9591 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9594 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9595 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9596 | (((value
>> 0) & 0xfffff) << 13));
9599 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9602 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9604 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9605 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9606 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
9607 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
9610 /* Attempt to simplify or even eliminate a fixup. The return value is
9611 ignored; perhaps it was once meaningful, but now it is historical.
9612 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9614 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9617 md_apply_fix3 (fix
, valuep
, seg
)
9620 segT seg ATTRIBUTE_UNUSED
;
9623 valueT value
= *valuep
;
9626 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9630 switch (fix
->fx_r_type
)
9632 case BFD_RELOC_IA64_DIR32MSB
:
9633 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9637 case BFD_RELOC_IA64_DIR32LSB
:
9638 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9642 case BFD_RELOC_IA64_DIR64MSB
:
9643 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9647 case BFD_RELOC_IA64_DIR64LSB
:
9648 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9658 switch (fix
->fx_r_type
)
9661 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9662 "%s must have a constant value",
9663 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9670 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9671 work. There should be a better way to handle this. */
9673 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9675 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9677 if (fix
->tc_fix_data
.bigendian
)
9678 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9680 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9686 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9693 /* Generate the BFD reloc to be stuck in the object file from the
9694 fixup used internally in the assembler. */
9697 tc_gen_reloc (sec
, fixp
)
9698 asection
*sec ATTRIBUTE_UNUSED
;
9703 reloc
= xmalloc (sizeof (*reloc
));
9704 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9705 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9706 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9707 reloc
->addend
= fixp
->fx_offset
;
9708 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9712 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9713 "Cannot represent %s relocation in object file",
9714 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9719 /* Turn a string in input_line_pointer into a floating point constant
9720 of type TYPE, and store the appropriate bytes in *LIT. The number
9721 of LITTLENUMS emitted is stored in *SIZE. An error message is
9722 returned, or NULL on OK. */
9724 #define MAX_LITTLENUMS 5
9727 md_atof (type
, lit
, size
)
9732 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9733 LITTLENUM_TYPE
*word
;
9763 return "Bad call to MD_ATOF()";
9765 t
= atof_ieee (input_line_pointer
, type
, words
);
9767 input_line_pointer
= t
;
9768 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9770 for (word
= words
+ prec
- 1; prec
--;)
9772 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9773 lit
+= sizeof (LITTLENUM_TYPE
);
9778 /* Round up a section's size to the appropriate boundary. */
9780 md_section_align (seg
, size
)
9784 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9785 valueT mask
= ((valueT
) 1 << align
) - 1;
9787 return (size
+ mask
) & ~mask
;
9790 /* Handle ia64 specific semantics of the align directive. */
9793 ia64_md_do_align (n
, fill
, len
, max
)
9796 int len ATTRIBUTE_UNUSED
;
9799 if (subseg_text_p (now_seg
))
9800 ia64_flush_insns ();
9803 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9804 of an rs_align_code fragment. */
9807 ia64_handle_align (fragp
)
9810 /* Use mfi bundle of nops with no stop bits. */
9811 static const unsigned char be_nop
[]
9812 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9813 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9814 static const unsigned char le_nop
[]
9815 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9816 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9821 if (fragp
->fr_type
!= rs_align_code
)
9824 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
9825 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
9827 /* Make sure we are on a 16-byte boundary, in case someone has been
9828 putting data into a text section. */
9831 int fix
= bytes
& 15;
9835 fragp
->fr_fix
+= fix
;
9838 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);