1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "M:N:x::";
161 struct option md_longopts
[] =
163 { NULL
, no_argument
, NULL
, 0}
166 size_t md_longopts_size
= sizeof (md_longopts
);
170 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
171 struct hash_control
*reg_hash
; /* register name hash table */
172 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
173 struct hash_control
*const_hash
; /* constant hash table */
174 struct hash_control
*entry_hash
; /* code entry hint hash table */
176 symbolS
*regsym
[REG_NUM
];
178 /* If X_op is != O_absent, the registername for the instruction's
179 qualifying predicate. If NULL, p0 is assumed for instructions
180 that are predicatable. */
187 explicit_mode
: 1, /* which mode we're in */
188 default_explicit_mode
: 1, /* which mode is the default */
189 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
192 /* Each bundle consists of up to three instructions. We keep
193 track of four most recent instructions so we can correctly set
194 the end_of_insn_group for the last instruction in a bundle. */
196 int num_slots_in_use
;
200 end_of_insn_group
: 1,
201 manual_bundling_on
: 1,
202 manual_bundling_off
: 1;
203 signed char user_template
; /* user-selected template, if any */
204 unsigned char qp_regno
; /* qualifying predicate */
205 /* This duplicates a good fraction of "struct fix" but we
206 can't use a "struct fix" instead since we can't call
207 fix_new_exp() until we know the address of the instruction. */
211 bfd_reloc_code_real_type code
;
212 enum ia64_opnd opnd
; /* type of operand in need of fix */
213 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
214 expressionS expr
; /* the value to be inserted */
216 fixup
[2]; /* at most two fixups per insn */
217 struct ia64_opcode
*idesc
;
218 struct label_fix
*label_fixups
;
219 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
222 unsigned int src_line
;
223 struct dwarf2_line_info debug_line
;
231 struct dynreg
*next
; /* next dynamic register */
233 unsigned short base
; /* the base register number */
234 unsigned short num_regs
; /* # of registers in this set */
236 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
238 flagword flags
; /* ELF-header flags */
241 unsigned hint
:1; /* is this hint currently valid? */
242 bfd_vma offset
; /* mem.offset offset */
243 bfd_vma base
; /* mem.offset base */
246 int path
; /* number of alt. entry points seen */
247 const char **entry_labels
; /* labels of all alternate paths in
248 the current DV-checking block. */
249 int maxpaths
; /* size currently allocated for
254 /* application registers: */
260 #define AR_BSPSTORE 18
275 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
276 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
277 {"ar.rsc", 16}, {"ar.bsp", 17},
278 {"ar.bspstore", 18}, {"ar.rnat", 19},
279 {"ar.fcr", 21}, {"ar.eflag", 24},
280 {"ar.csd", 25}, {"ar.ssd", 26},
281 {"ar.cflg", 27}, {"ar.fsr", 28},
282 {"ar.fir", 29}, {"ar.fdr", 30},
283 {"ar.ccv", 32}, {"ar.unat", 36},
284 {"ar.fpsr", 40}, {"ar.itc", 44},
285 {"ar.pfs", 64}, {"ar.lc", 65},
306 /* control registers: */
348 static const struct const_desc
355 /* PSR constant masks: */
358 {"psr.be", ((valueT
) 1) << 1},
359 {"psr.up", ((valueT
) 1) << 2},
360 {"psr.ac", ((valueT
) 1) << 3},
361 {"psr.mfl", ((valueT
) 1) << 4},
362 {"psr.mfh", ((valueT
) 1) << 5},
364 {"psr.ic", ((valueT
) 1) << 13},
365 {"psr.i", ((valueT
) 1) << 14},
366 {"psr.pk", ((valueT
) 1) << 15},
368 {"psr.dt", ((valueT
) 1) << 17},
369 {"psr.dfl", ((valueT
) 1) << 18},
370 {"psr.dfh", ((valueT
) 1) << 19},
371 {"psr.sp", ((valueT
) 1) << 20},
372 {"psr.pp", ((valueT
) 1) << 21},
373 {"psr.di", ((valueT
) 1) << 22},
374 {"psr.si", ((valueT
) 1) << 23},
375 {"psr.db", ((valueT
) 1) << 24},
376 {"psr.lp", ((valueT
) 1) << 25},
377 {"psr.tb", ((valueT
) 1) << 26},
378 {"psr.rt", ((valueT
) 1) << 27},
379 /* 28-31: reserved */
380 /* 32-33: cpl (current privilege level) */
381 {"psr.is", ((valueT
) 1) << 34},
382 {"psr.mc", ((valueT
) 1) << 35},
383 {"psr.it", ((valueT
) 1) << 36},
384 {"psr.id", ((valueT
) 1) << 37},
385 {"psr.da", ((valueT
) 1) << 38},
386 {"psr.dd", ((valueT
) 1) << 39},
387 {"psr.ss", ((valueT
) 1) << 40},
388 /* 41-42: ri (restart instruction) */
389 {"psr.ed", ((valueT
) 1) << 43},
390 {"psr.bn", ((valueT
) 1) << 44},
393 /* indirect register-sets/memory: */
402 { "CPUID", IND_CPUID
},
403 { "cpuid", IND_CPUID
},
415 /* Pseudo functions used to indicate relocation types (these functions
416 start with an at sign (@). */
438 /* reloc pseudo functions (these must come first!): */
439 { "fptr", PSEUDO_FUNC_RELOC
},
440 { "gprel", PSEUDO_FUNC_RELOC
},
441 { "ltoff", PSEUDO_FUNC_RELOC
},
442 { "pcrel", PSEUDO_FUNC_RELOC
},
443 { "pltoff", PSEUDO_FUNC_RELOC
},
444 { "secrel", PSEUDO_FUNC_RELOC
},
445 { "segrel", PSEUDO_FUNC_RELOC
},
446 { "ltv", PSEUDO_FUNC_RELOC
},
447 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
449 /* mbtype4 constants: */
450 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
451 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
452 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
453 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
454 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
456 /* fclass constants: */
457 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
458 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
459 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
460 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
461 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
462 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
463 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
464 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
465 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
467 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
469 /* unwind-related constants: */
470 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
471 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
472 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
474 /* unwind-related registers: */
475 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
478 /* 41-bit nop opcodes (one per unit): */
479 static const bfd_vma nop
[IA64_NUM_UNITS
] =
481 0x0000000000LL
, /* NIL => break 0 */
482 0x0008000000LL
, /* I-unit nop */
483 0x0008000000LL
, /* M-unit nop */
484 0x4000000000LL
, /* B-unit nop */
485 0x0008000000LL
, /* F-unit nop */
486 0x0008000000LL
, /* L-"unit" nop */
487 0x0008000000LL
, /* X-unit nop */
490 /* Can't be `const' as it's passed to input routines (which have the
491 habit of setting temporary sentinels. */
492 static char special_section_name
[][20] =
494 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
495 {".IA_64.unwind"}, {".IA_64.unwind_info"}
498 /* The best template for a particular sequence of up to three
500 #define N IA64_NUM_TYPES
501 static unsigned char best_template
[N
][N
][N
];
504 /* Resource dependencies currently in effect */
506 int depind
; /* dependency index */
507 const struct ia64_dependency
*dependency
; /* actual dependency */
508 unsigned specific
:1, /* is this a specific bit/regno? */
509 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
510 int index
; /* specific regno/bit within dependency */
511 int note
; /* optional qualifying note (0 if none) */
515 int insn_srlz
; /* current insn serialization state */
516 int data_srlz
; /* current data serialization state */
517 int qp_regno
; /* qualifying predicate for this usage */
518 char *file
; /* what file marked this dependency */
519 int line
; /* what line marked this dependency */
520 struct mem_offset mem_offset
; /* optional memory offset hint */
521 int path
; /* corresponding code entry index */
523 static int regdepslen
= 0;
524 static int regdepstotlen
= 0;
525 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
526 static const char *dv_sem
[] = { "none", "implied", "impliedf",
527 "data", "instr", "specific", "other" };
529 /* Current state of PR mutexation */
530 static struct qpmutex
{
533 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
534 static int qp_mutexeslen
= 0;
535 static int qp_mutexestotlen
= 0;
536 static valueT qp_safe_across_calls
= 0;
538 /* Current state of PR implications */
539 static struct qp_imply
{
542 unsigned p2_branched
:1;
544 } *qp_implies
= NULL
;
545 static int qp_implieslen
= 0;
546 static int qp_impliestotlen
= 0;
548 /* Keep track of static GR values so that indirect register usage can
549 sometimes be tracked. */
554 } gr_values
[128] = {{ 1, 0 }};
556 /* These are the routines required to output the various types of
559 typedef struct unw_rec_list
{
561 unsigned long slot_number
;
562 struct unw_rec_list
*next
;
565 #define SLOT_NUM_NOT_SET -1
569 unsigned long next_slot_number
;
571 /* Maintain a list of unwind entries for the current function. */
575 /* Any unwind entires that should be attached to the current slot
576 that an insn is being constructed for. */
577 unw_rec_list
*current_entry
;
579 /* These are used to create the unwind table entry for this function. */
582 symbolS
*info
; /* pointer to unwind info */
583 symbolS
*personality_routine
;
585 /* TRUE if processing unwind directives in a prologue region. */
589 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
591 /* Forward delarations: */
592 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
593 static void set_section
PARAMS ((char *name
));
594 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
595 unsigned int, unsigned int));
596 static void dot_radix
PARAMS ((int));
597 static void dot_special_section
PARAMS ((int));
598 static void dot_proc
PARAMS ((int));
599 static void dot_fframe
PARAMS ((int));
600 static void dot_vframe
PARAMS ((int));
601 static void dot_vframesp
PARAMS ((int));
602 static void dot_vframepsp
PARAMS ((int));
603 static void dot_save
PARAMS ((int));
604 static void dot_restore
PARAMS ((int));
605 static void dot_restorereg
PARAMS ((int));
606 static void dot_restorereg_p
PARAMS ((int));
607 static void dot_handlerdata
PARAMS ((int));
608 static void dot_unwentry
PARAMS ((int));
609 static void dot_altrp
PARAMS ((int));
610 static void dot_savemem
PARAMS ((int));
611 static void dot_saveg
PARAMS ((int));
612 static void dot_savef
PARAMS ((int));
613 static void dot_saveb
PARAMS ((int));
614 static void dot_savegf
PARAMS ((int));
615 static void dot_spill
PARAMS ((int));
616 static void dot_spillreg
PARAMS ((int));
617 static void dot_spillmem
PARAMS ((int));
618 static void dot_spillreg_p
PARAMS ((int));
619 static void dot_spillmem_p
PARAMS ((int));
620 static void dot_label_state
PARAMS ((int));
621 static void dot_copy_state
PARAMS ((int));
622 static void dot_unwabi
PARAMS ((int));
623 static void dot_personality
PARAMS ((int));
624 static void dot_body
PARAMS ((int));
625 static void dot_prologue
PARAMS ((int));
626 static void dot_endp
PARAMS ((int));
627 static void dot_template
PARAMS ((int));
628 static void dot_regstk
PARAMS ((int));
629 static void dot_rot
PARAMS ((int));
630 static void dot_byteorder
PARAMS ((int));
631 static void dot_psr
PARAMS ((int));
632 static void dot_alias
PARAMS ((int));
633 static void dot_ln
PARAMS ((int));
634 static char *parse_section_name
PARAMS ((void));
635 static void dot_xdata
PARAMS ((int));
636 static void stmt_float_cons
PARAMS ((int));
637 static void stmt_cons_ua
PARAMS ((int));
638 static void dot_xfloat_cons
PARAMS ((int));
639 static void dot_xstringer
PARAMS ((int));
640 static void dot_xdata_ua
PARAMS ((int));
641 static void dot_xfloat_cons_ua
PARAMS ((int));
642 static void print_prmask
PARAMS ((valueT mask
));
643 static void dot_pred_rel
PARAMS ((int));
644 static void dot_reg_val
PARAMS ((int));
645 static void dot_dv_mode
PARAMS ((int));
646 static void dot_entry
PARAMS ((int));
647 static void dot_mem_offset
PARAMS ((int));
648 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
649 static symbolS
* declare_register
PARAMS ((const char *name
, int regnum
));
650 static void declare_register_set
PARAMS ((const char *, int, int));
651 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
652 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
653 int index
, expressionS
*e
));
654 static int parse_operand
PARAMS ((expressionS
*e
));
655 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
656 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
657 static void emit_one_bundle
PARAMS ((void));
658 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
659 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
660 bfd_reloc_code_real_type r_type
));
661 static void insn_group_break
PARAMS ((int, int, int));
662 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
663 struct rsrc
*, int depind
, int path
));
664 static void add_qp_mutex
PARAMS((valueT mask
));
665 static void add_qp_imply
PARAMS((int p1
, int p2
));
666 static void clear_qp_branch_flag
PARAMS((valueT mask
));
667 static void clear_qp_mutex
PARAMS((valueT mask
));
668 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
669 static void clear_register_values
PARAMS ((void));
670 static void print_dependency
PARAMS ((const char *action
, int depind
));
671 static void instruction_serialization
PARAMS ((void));
672 static void data_serialization
PARAMS ((void));
673 static void remove_marked_resource
PARAMS ((struct rsrc
*));
674 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
675 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
676 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
677 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
678 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
679 struct ia64_opcode
*, int, struct rsrc
[], int, int));
680 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
681 static void check_dependencies
PARAMS((struct ia64_opcode
*));
682 static void mark_resources
PARAMS((struct ia64_opcode
*));
683 static void update_dependencies
PARAMS((struct ia64_opcode
*));
684 static void note_register_values
PARAMS((struct ia64_opcode
*));
685 static int qp_mutex
PARAMS ((int, int, int));
686 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
687 static void output_vbyte_mem
PARAMS ((int, char *, char *));
688 static void count_output
PARAMS ((int, char *, char *));
689 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
690 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
691 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
692 static void output_P1_format
PARAMS ((vbyte_func
, int));
693 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
694 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
695 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
696 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
697 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
698 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
699 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
700 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
701 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
702 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
703 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
704 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
705 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
706 static char format_ab_reg
PARAMS ((int, int));
707 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
709 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
710 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
712 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
713 static void free_list_records
PARAMS ((unw_rec_list
*));
714 static unw_rec_list
*output_prologue
PARAMS ((void));
715 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
716 static unw_rec_list
*output_body
PARAMS ((void));
717 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
718 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
719 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
720 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
721 static unw_rec_list
*output_rp_when
PARAMS ((void));
722 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
723 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
724 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
725 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
726 static unw_rec_list
*output_pfs_when
PARAMS ((void));
727 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
728 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
729 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
730 static unw_rec_list
*output_preds_when
PARAMS ((void));
731 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
732 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
733 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
734 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
735 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
736 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
737 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
738 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
739 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
740 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
741 static unw_rec_list
*output_unat_when
PARAMS ((void));
742 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
743 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
744 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
745 static unw_rec_list
*output_lc_when
PARAMS ((void));
746 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
747 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
748 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
749 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
750 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
751 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
752 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
753 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
754 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
755 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
756 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
757 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
758 static unw_rec_list
*output_bsp_when
PARAMS ((void));
759 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
760 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
761 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
762 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
763 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
764 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
765 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_rnat_when
PARAMS ((void));
767 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
768 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
769 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
771 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
772 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
773 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
774 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
775 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
776 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
778 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
780 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
782 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
783 unsigned int, unsigned int));
784 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
785 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
786 static int calc_record_size
PARAMS ((unw_rec_list
*));
787 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
788 static int count_bits
PARAMS ((unsigned long));
789 static unsigned long slot_index
PARAMS ((unsigned long, unsigned long));
790 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
791 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
792 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
793 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
794 static int generate_unwind_image
PARAMS ((void));
796 /* Determine if application register REGNUM resides in the integer
797 unit (as opposed to the memory unit). */
799 ar_is_in_integer_unit (reg
)
804 return (reg
== 64 /* pfs */
805 || reg
== 65 /* lc */
806 || reg
== 66 /* ec */
807 /* ??? ias accepts and puts these in the integer unit. */
808 || (reg
>= 112 && reg
<= 127));
811 /* Switch to section NAME and create section if necessary. It's
812 rather ugly that we have to manipulate input_line_pointer but I
813 don't see any other way to accomplish the same thing without
814 changing obj-elf.c (which may be the Right Thing, in the end). */
819 char *saved_input_line_pointer
;
821 saved_input_line_pointer
= input_line_pointer
;
822 input_line_pointer
= name
;
824 input_line_pointer
= saved_input_line_pointer
;
827 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
830 ia64_elf_section_flags (flags
, attr
, type
)
834 if (attr
& SHF_IA_64_SHORT
)
835 flags
|= SEC_SMALL_DATA
;
840 set_regstack (ins
, locs
, outs
, rots
)
841 unsigned int ins
, locs
, outs
, rots
;
843 unsigned int sof
; /* size of frame */
845 sof
= ins
+ locs
+ outs
;
848 as_bad ("Size of frame exceeds maximum of 96 registers");
853 as_warn ("Size of rotating registers exceeds frame size");
856 md
.in
.base
= REG_GR
+ 32;
857 md
.loc
.base
= md
.in
.base
+ ins
;
858 md
.out
.base
= md
.loc
.base
+ locs
;
860 md
.in
.num_regs
= ins
;
861 md
.loc
.num_regs
= locs
;
862 md
.out
.num_regs
= outs
;
863 md
.rot
.num_regs
= rots
;
870 struct label_fix
*lfix
;
872 subsegT saved_subseg
;
874 if (!md
.last_text_seg
)
878 saved_subseg
= now_subseg
;
880 subseg_set (md
.last_text_seg
, 0);
882 while (md
.num_slots_in_use
> 0)
883 emit_one_bundle (); /* force out queued instructions */
885 /* In case there are labels following the last instruction, resolve
887 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
889 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
890 symbol_set_frag (lfix
->sym
, frag_now
);
892 CURR_SLOT
.label_fixups
= 0;
894 subseg_set (saved_seg
, saved_subseg
);
898 ia64_do_align (nbytes
)
901 char *saved_input_line_pointer
= input_line_pointer
;
903 input_line_pointer
= "";
904 s_align_bytes (nbytes
);
905 input_line_pointer
= saved_input_line_pointer
;
909 ia64_cons_align (nbytes
)
914 char *saved_input_line_pointer
= input_line_pointer
;
915 input_line_pointer
= "";
916 s_align_bytes (nbytes
);
917 input_line_pointer
= saved_input_line_pointer
;
921 /* Output COUNT bytes to a memory location. */
922 static unsigned char *vbyte_mem_ptr
= NULL
;
925 output_vbyte_mem (count
, ptr
, comment
)
931 if (vbyte_mem_ptr
== NULL
)
936 for (x
= 0; x
< count
; x
++)
937 *(vbyte_mem_ptr
++) = ptr
[x
];
940 /* Count the number of bytes required for records. */
941 static int vbyte_count
= 0;
943 count_output (count
, ptr
, comment
)
948 vbyte_count
+= count
;
952 output_R1_format (f
, rtype
, rlen
)
954 unw_record_type rtype
;
961 output_R3_format (f
, rtype
, rlen
);
967 else if (rtype
!= prologue
)
968 as_bad ("record type is not valid");
970 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
971 (*f
) (1, &byte
, NULL
);
975 output_R2_format (f
, mask
, grsave
, rlen
)
982 mask
= (mask
& 0x0f);
983 grsave
= (grsave
& 0x7f);
985 bytes
[0] = (UNW_R2
| (mask
>> 1));
986 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
987 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
988 (*f
) (count
, bytes
, NULL
);
992 output_R3_format (f
, rtype
, rlen
)
994 unw_record_type rtype
;
1001 output_R1_format (f
, rtype
, rlen
);
1007 else if (rtype
!= prologue
)
1008 as_bad ("record type is not valid");
1009 bytes
[0] = (UNW_R3
| r
);
1010 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1011 (*f
) (count
+ 1, bytes
, NULL
);
1015 output_P1_format (f
, brmask
)
1020 byte
= UNW_P1
| (brmask
& 0x1f);
1021 (*f
) (1, &byte
, NULL
);
1025 output_P2_format (f
, brmask
, gr
)
1031 brmask
= (brmask
& 0x1f);
1032 bytes
[0] = UNW_P2
| (brmask
>> 1);
1033 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1034 (*f
) (2, bytes
, NULL
);
1038 output_P3_format (f
, rtype
, reg
)
1040 unw_record_type rtype
;
1085 as_bad ("Invalid record type for P3 format.");
1087 bytes
[0] = (UNW_P3
| (r
>> 1));
1088 bytes
[1] = (((r
& 1) << 7) | reg
);
1089 (*f
) (2, bytes
, NULL
);
1094 output_P4_format (f
, imask
, imask_size
)
1096 unsigned char *imask
;
1097 unsigned long imask_size
;
1100 (*f
) (imask_size
, imask
, NULL
);
1104 output_P5_format (f
, grmask
, frmask
)
1107 unsigned long frmask
;
1110 grmask
= (grmask
& 0x0f);
1113 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1114 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1115 bytes
[3] = (frmask
& 0x000000ff);
1116 (*f
) (4, bytes
, NULL
);
1120 output_P6_format (f
, rtype
, rmask
)
1122 unw_record_type rtype
;
1128 if (rtype
== gr_mem
)
1130 else if (rtype
!= fr_mem
)
1131 as_bad ("Invalid record type for format P6");
1132 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1133 (*f
) (1, &byte
, NULL
);
1137 output_P7_format (f
, rtype
, w1
, w2
)
1139 unw_record_type rtype
;
1146 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1151 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1201 bytes
[0] = (UNW_P7
| r
);
1202 (*f
) (count
, bytes
, NULL
);
1206 output_P8_format (f
, rtype
, t
)
1208 unw_record_type rtype
;
1247 case bspstore_psprel
:
1250 case bspstore_sprel
:
1262 case priunat_when_gr
:
1265 case priunat_psprel
:
1271 case priunat_when_mem
:
1278 count
+= output_leb128 (bytes
+ 2, t
, 0);
1279 (*f
) (count
, bytes
, NULL
);
1283 output_P9_format (f
, grmask
, gr
)
1290 bytes
[1] = (grmask
& 0x0f);
1291 bytes
[2] = (gr
& 0x7f);
1292 (*f
) (3, bytes
, NULL
);
1296 output_P10_format (f
, abi
, context
)
1303 bytes
[1] = (abi
& 0xff);
1304 bytes
[2] = (context
& 0xff);
1305 (*f
) (3, bytes
, NULL
);
1309 output_B1_format (f
, rtype
, label
)
1311 unw_record_type rtype
;
1312 unsigned long label
;
1318 output_B4_format (f
, rtype
, label
);
1321 if (rtype
== copy_state
)
1323 else if (rtype
!= label_state
)
1324 as_bad ("Invalid record type for format B1");
1326 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1327 (*f
) (1, &byte
, NULL
);
1331 output_B2_format (f
, ecount
, t
)
1333 unsigned long ecount
;
1340 output_B3_format (f
, ecount
, t
);
1343 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1344 count
+= output_leb128 (bytes
+ 1, t
, 0);
1345 (*f
) (count
, bytes
, NULL
);
1349 output_B3_format (f
, ecount
, t
)
1351 unsigned long ecount
;
1358 output_B2_format (f
, ecount
, t
);
1362 count
+= output_leb128 (bytes
+ 1, t
, 0);
1363 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1364 (*f
) (count
, bytes
, NULL
);
1368 output_B4_format (f
, rtype
, label
)
1370 unw_record_type rtype
;
1371 unsigned long label
;
1378 output_B1_format (f
, rtype
, label
);
1382 if (rtype
== copy_state
)
1384 else if (rtype
!= label_state
)
1385 as_bad ("Invalid record type for format B1");
1387 bytes
[0] = (UNW_B4
| (r
<< 3));
1388 count
+= output_leb128 (bytes
+ 1, label
, 0);
1389 (*f
) (count
, bytes
, NULL
);
1393 format_ab_reg (ab
, reg
)
1400 ret
= (ab
<< 5) | reg
;
1405 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1407 unw_record_type rtype
;
1417 if (rtype
== spill_sprel
)
1419 else if (rtype
!= spill_psprel
)
1420 as_bad ("Invalid record type for format X1");
1421 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1422 count
+= output_leb128 (bytes
+ 2, t
, 0);
1423 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1424 (*f
) (count
, bytes
, NULL
);
1428 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1437 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1438 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1439 count
+= output_leb128 (bytes
+ 3, t
, 0);
1440 (*f
) (count
, bytes
, NULL
);
1444 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1446 unw_record_type rtype
;
1457 if (rtype
== spill_sprel_p
)
1459 else if (rtype
!= spill_psprel_p
)
1460 as_bad ("Invalid record type for format X3");
1461 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1462 bytes
[2] = format_ab_reg (ab
, reg
);
1463 count
+= output_leb128 (bytes
+ 3, t
, 0);
1464 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1465 (*f
) (count
, bytes
, NULL
);
1469 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1479 bytes
[1] = (qp
& 0x3f);
1480 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1481 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1482 count
+= output_leb128 (bytes
+ 4, t
, 0);
1483 (*f
) (count
, bytes
, NULL
);
1486 /* This function allocates a record list structure, and initializes fields. */
1487 static unw_rec_list
*
1488 alloc_record (unw_record_type t
)
1491 ptr
= xmalloc (sizeof (*ptr
));
1493 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1498 /* This function frees an entire list of record structures. */
1500 free_list_records (unw_rec_list
*first
)
1503 for (ptr
= first
; ptr
!= NULL
; )
1505 unw_rec_list
*tmp
= ptr
;
1507 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1508 && tmp
->r
.record
.r
.mask
.i
)
1509 free (tmp
->r
.record
.r
.mask
.i
);
1516 static unw_rec_list
*
1519 unw_rec_list
*ptr
= alloc_record (prologue
);
1520 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1524 static unw_rec_list
*
1525 output_prologue_gr (saved_mask
, reg
)
1526 unsigned int saved_mask
;
1529 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1530 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1531 ptr
->r
.record
.r
.grmask
= saved_mask
;
1532 ptr
->r
.record
.r
.grsave
= reg
;
1536 static unw_rec_list
*
1539 unw_rec_list
*ptr
= alloc_record (body
);
1543 static unw_rec_list
*
1544 output_mem_stack_f (size
)
1547 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1548 ptr
->r
.record
.p
.size
= size
;
1552 static unw_rec_list
*
1553 output_mem_stack_v ()
1555 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1559 static unw_rec_list
*
1563 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1564 ptr
->r
.record
.p
.gr
= gr
;
1568 static unw_rec_list
*
1569 output_psp_sprel (offset
)
1570 unsigned int offset
;
1572 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1573 ptr
->r
.record
.p
.spoff
= offset
/4;
1577 static unw_rec_list
*
1580 unw_rec_list
*ptr
= alloc_record (rp_when
);
1584 static unw_rec_list
*
1588 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1589 ptr
->r
.record
.p
.gr
= gr
;
1593 static unw_rec_list
*
1597 unw_rec_list
*ptr
= alloc_record (rp_br
);
1598 ptr
->r
.record
.p
.br
= br
;
1602 static unw_rec_list
*
1603 output_rp_psprel (offset
)
1604 unsigned int offset
;
1606 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1607 ptr
->r
.record
.p
.pspoff
= offset
/4;
1611 static unw_rec_list
*
1612 output_rp_sprel (offset
)
1613 unsigned int offset
;
1615 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1616 ptr
->r
.record
.p
.spoff
= offset
/4;
1620 static unw_rec_list
*
1623 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1627 static unw_rec_list
*
1631 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1632 ptr
->r
.record
.p
.gr
= gr
;
1636 static unw_rec_list
*
1637 output_pfs_psprel (offset
)
1638 unsigned int offset
;
1640 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1641 ptr
->r
.record
.p
.pspoff
= offset
/4;
1645 static unw_rec_list
*
1646 output_pfs_sprel (offset
)
1647 unsigned int offset
;
1649 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1650 ptr
->r
.record
.p
.spoff
= offset
/4;
1654 static unw_rec_list
*
1655 output_preds_when ()
1657 unw_rec_list
*ptr
= alloc_record (preds_when
);
1661 static unw_rec_list
*
1662 output_preds_gr (gr
)
1665 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1666 ptr
->r
.record
.p
.gr
= gr
;
1670 static unw_rec_list
*
1671 output_preds_psprel (offset
)
1672 unsigned int offset
;
1674 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1675 ptr
->r
.record
.p
.pspoff
= offset
/4;
1679 static unw_rec_list
*
1680 output_preds_sprel (offset
)
1681 unsigned int offset
;
1683 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1684 ptr
->r
.record
.p
.spoff
= offset
/4;
1688 static unw_rec_list
*
1689 output_fr_mem (mask
)
1692 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1693 ptr
->r
.record
.p
.rmask
= mask
;
1697 static unw_rec_list
*
1698 output_frgr_mem (gr_mask
, fr_mask
)
1699 unsigned int gr_mask
;
1700 unsigned int fr_mask
;
1702 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1703 ptr
->r
.record
.p
.grmask
= gr_mask
;
1704 ptr
->r
.record
.p
.frmask
= fr_mask
;
1708 static unw_rec_list
*
1709 output_gr_gr (mask
, reg
)
1713 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1714 ptr
->r
.record
.p
.grmask
= mask
;
1715 ptr
->r
.record
.p
.gr
= reg
;
1719 static unw_rec_list
*
1720 output_gr_mem (mask
)
1723 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1724 ptr
->r
.record
.p
.rmask
= mask
;
1728 static unw_rec_list
*
1729 output_br_mem (unsigned int mask
)
1731 unw_rec_list
*ptr
= alloc_record (br_mem
);
1732 ptr
->r
.record
.p
.brmask
= mask
;
1736 static unw_rec_list
*
1737 output_br_gr (save_mask
, reg
)
1738 unsigned int save_mask
;
1741 unw_rec_list
*ptr
= alloc_record (br_gr
);
1742 ptr
->r
.record
.p
.brmask
= save_mask
;
1743 ptr
->r
.record
.p
.gr
= reg
;
1747 static unw_rec_list
*
1748 output_spill_base (offset
)
1749 unsigned int offset
;
1751 unw_rec_list
*ptr
= alloc_record (spill_base
);
1752 ptr
->r
.record
.p
.pspoff
= offset
/4;
1756 static unw_rec_list
*
1759 unw_rec_list
*ptr
= alloc_record (unat_when
);
1763 static unw_rec_list
*
1767 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1768 ptr
->r
.record
.p
.gr
= gr
;
1772 static unw_rec_list
*
1773 output_unat_psprel (offset
)
1774 unsigned int offset
;
1776 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1777 ptr
->r
.record
.p
.pspoff
= offset
/4;
1781 static unw_rec_list
*
1782 output_unat_sprel (offset
)
1783 unsigned int offset
;
1785 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1786 ptr
->r
.record
.p
.spoff
= offset
/4;
1790 static unw_rec_list
*
1793 unw_rec_list
*ptr
= alloc_record (lc_when
);
1797 static unw_rec_list
*
1801 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1802 ptr
->r
.record
.p
.gr
= gr
;
1806 static unw_rec_list
*
1807 output_lc_psprel (offset
)
1808 unsigned int offset
;
1810 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1811 ptr
->r
.record
.p
.pspoff
= offset
/4;
1815 static unw_rec_list
*
1816 output_lc_sprel (offset
)
1817 unsigned int offset
;
1819 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1820 ptr
->r
.record
.p
.spoff
= offset
/4;
1824 static unw_rec_list
*
1827 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1831 static unw_rec_list
*
1835 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1836 ptr
->r
.record
.p
.gr
= gr
;
1840 static unw_rec_list
*
1841 output_fpsr_psprel (offset
)
1842 unsigned int offset
;
1844 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1845 ptr
->r
.record
.p
.pspoff
= offset
/4;
1849 static unw_rec_list
*
1850 output_fpsr_sprel (offset
)
1851 unsigned int offset
;
1853 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1854 ptr
->r
.record
.p
.spoff
= offset
/4;
1858 static unw_rec_list
*
1859 output_priunat_when_gr ()
1861 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1865 static unw_rec_list
*
1866 output_priunat_when_mem ()
1868 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1872 static unw_rec_list
*
1873 output_priunat_gr (gr
)
1876 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1877 ptr
->r
.record
.p
.gr
= gr
;
1881 static unw_rec_list
*
1882 output_priunat_psprel (offset
)
1883 unsigned int offset
;
1885 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1886 ptr
->r
.record
.p
.pspoff
= offset
/4;
1890 static unw_rec_list
*
1891 output_priunat_sprel (offset
)
1892 unsigned int offset
;
1894 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1895 ptr
->r
.record
.p
.spoff
= offset
/4;
1899 static unw_rec_list
*
1902 unw_rec_list
*ptr
= alloc_record (bsp_when
);
1906 static unw_rec_list
*
1910 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
1911 ptr
->r
.record
.p
.gr
= gr
;
1915 static unw_rec_list
*
1916 output_bsp_psprel (offset
)
1917 unsigned int offset
;
1919 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
1920 ptr
->r
.record
.p
.pspoff
= offset
/4;
1924 static unw_rec_list
*
1925 output_bsp_sprel (offset
)
1926 unsigned int offset
;
1928 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
1929 ptr
->r
.record
.p
.spoff
= offset
/4;
1933 static unw_rec_list
*
1934 output_bspstore_when ()
1936 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
1940 static unw_rec_list
*
1941 output_bspstore_gr (gr
)
1944 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
1945 ptr
->r
.record
.p
.gr
= gr
;
1949 static unw_rec_list
*
1950 output_bspstore_psprel (offset
)
1951 unsigned int offset
;
1953 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
1954 ptr
->r
.record
.p
.pspoff
= offset
/4;
1958 static unw_rec_list
*
1959 output_bspstore_sprel (offset
)
1960 unsigned int offset
;
1962 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
1963 ptr
->r
.record
.p
.spoff
= offset
/4;
1967 static unw_rec_list
*
1970 unw_rec_list
*ptr
= alloc_record (rnat_when
);
1974 static unw_rec_list
*
1978 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
1979 ptr
->r
.record
.p
.gr
= gr
;
1983 static unw_rec_list
*
1984 output_rnat_psprel (offset
)
1985 unsigned int offset
;
1987 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
1988 ptr
->r
.record
.p
.pspoff
= offset
/4;
1992 static unw_rec_list
*
1993 output_rnat_sprel (offset
)
1994 unsigned int offset
;
1996 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
1997 ptr
->r
.record
.p
.spoff
= offset
/4;
2001 static unw_rec_list
*
2002 output_unwabi (abi
, context
)
2004 unsigned long context
;
2006 unw_rec_list
*ptr
= alloc_record (unwabi
);
2007 ptr
->r
.record
.p
.abi
= abi
;
2008 ptr
->r
.record
.p
.context
= context
;
2012 static unw_rec_list
*
2013 output_epilogue (unsigned long ecount
)
2015 unw_rec_list
*ptr
= alloc_record (epilogue
);
2016 ptr
->r
.record
.b
.ecount
= ecount
;
2020 static unw_rec_list
*
2021 output_label_state (unsigned long label
)
2023 unw_rec_list
*ptr
= alloc_record (label_state
);
2024 ptr
->r
.record
.b
.label
= label
;
2028 static unw_rec_list
*
2029 output_copy_state (unsigned long label
)
2031 unw_rec_list
*ptr
= alloc_record (copy_state
);
2032 ptr
->r
.record
.b
.label
= label
;
2036 static unw_rec_list
*
2037 output_spill_psprel (ab
, reg
, offset
)
2040 unsigned int offset
;
2042 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2043 ptr
->r
.record
.x
.ab
= ab
;
2044 ptr
->r
.record
.x
.reg
= reg
;
2045 ptr
->r
.record
.x
.pspoff
= offset
/4;
2049 static unw_rec_list
*
2050 output_spill_sprel (ab
, reg
, offset
)
2053 unsigned int offset
;
2055 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2056 ptr
->r
.record
.x
.ab
= ab
;
2057 ptr
->r
.record
.x
.reg
= reg
;
2058 ptr
->r
.record
.x
.spoff
= offset
/4;
2062 static unw_rec_list
*
2063 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2066 unsigned int offset
;
2067 unsigned int predicate
;
2069 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2070 ptr
->r
.record
.x
.ab
= ab
;
2071 ptr
->r
.record
.x
.reg
= reg
;
2072 ptr
->r
.record
.x
.pspoff
= offset
/4;
2073 ptr
->r
.record
.x
.qp
= predicate
;
2077 static unw_rec_list
*
2078 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2081 unsigned int offset
;
2082 unsigned int predicate
;
2084 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2085 ptr
->r
.record
.x
.ab
= ab
;
2086 ptr
->r
.record
.x
.reg
= reg
;
2087 ptr
->r
.record
.x
.spoff
= offset
/4;
2088 ptr
->r
.record
.x
.qp
= predicate
;
2092 static unw_rec_list
*
2093 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2096 unsigned int targ_reg
;
2099 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2100 ptr
->r
.record
.x
.ab
= ab
;
2101 ptr
->r
.record
.x
.reg
= reg
;
2102 ptr
->r
.record
.x
.treg
= targ_reg
;
2103 ptr
->r
.record
.x
.xy
= xy
;
2107 static unw_rec_list
*
2108 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2111 unsigned int targ_reg
;
2113 unsigned int predicate
;
2115 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2116 ptr
->r
.record
.x
.ab
= ab
;
2117 ptr
->r
.record
.x
.reg
= reg
;
2118 ptr
->r
.record
.x
.treg
= targ_reg
;
2119 ptr
->r
.record
.x
.xy
= xy
;
2120 ptr
->r
.record
.x
.qp
= predicate
;
2124 /* Given a unw_rec_list process the correct format with the
2125 specified function. */
2127 process_one_record (ptr
, f
)
2131 unsigned long fr_mask
, gr_mask
;
2133 switch (ptr
->r
.type
)
2139 /* these are taken care of by prologue/prologue_gr */
2144 if (ptr
->r
.type
== prologue_gr
)
2145 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2146 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2148 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2150 /* output descriptor(s) for union of register spills (if any): */
2151 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2152 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2155 if ((fr_mask
& ~0xfUL
) == 0)
2156 output_P6_format (f
, fr_mem
, fr_mask
);
2159 output_P5_format (f
, gr_mask
, fr_mask
);
2164 output_P6_format (f
, gr_mem
, gr_mask
);
2165 if (ptr
->r
.record
.r
.mask
.br_mem
)
2166 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2168 /* output imask descriptor if necessary: */
2169 if (ptr
->r
.record
.r
.mask
.i
)
2170 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2171 ptr
->r
.record
.r
.imask_size
);
2175 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2179 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2180 ptr
->r
.record
.p
.size
);
2193 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2196 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2199 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2207 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2216 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2226 case bspstore_sprel
:
2228 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2231 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2234 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2237 as_bad ("spill_mask record unimplemented.");
2239 case priunat_when_gr
:
2240 case priunat_when_mem
:
2244 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2246 case priunat_psprel
:
2248 case bspstore_psprel
:
2250 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2253 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2256 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2260 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2263 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2264 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2265 ptr
->r
.record
.x
.pspoff
);
2268 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2269 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2270 ptr
->r
.record
.x
.spoff
);
2273 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2274 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2275 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2277 case spill_psprel_p
:
2278 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2279 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2280 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2283 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2284 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2285 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2288 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2289 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2290 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2294 as_bad ("record_type_not_valid");
2299 /* Given a unw_rec_list list, process all the records with
2300 the specified function. */
2302 process_unw_records (list
, f
)
2307 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2308 process_one_record (ptr
, f
);
2311 /* Determine the size of a record list in bytes. */
2313 calc_record_size (list
)
2317 process_unw_records (list
, count_output
);
2321 /* Update IMASK bitmask to reflect the fact that one or more registers
2322 of type TYPE are saved starting at instruction with index T. If N
2323 bits are set in REGMASK, it is assumed that instructions T through
2324 T+N-1 save these registers.
2328 1: instruction saves next fp reg
2329 2: instruction saves next general reg
2330 3: instruction saves next branch reg */
2332 set_imask (region
, regmask
, t
, type
)
2333 unw_rec_list
*region
;
2334 unsigned long regmask
;
2338 unsigned char *imask
;
2339 unsigned long imask_size
;
2343 imask
= region
->r
.record
.r
.mask
.i
;
2344 imask_size
= region
->r
.record
.r
.imask_size
;
2347 imask_size
= (region
->r
.record
.r
.rlen
*2 + 7)/8 + 1;
2348 imask
= xmalloc (imask_size
);
2349 memset (imask
, 0, imask_size
);
2351 region
->r
.record
.r
.imask_size
= imask_size
;
2352 region
->r
.record
.r
.mask
.i
= imask
;
2359 if (i
>= imask_size
)
2361 as_bad ("Ignoring attempt to spill beyond end of region");
2365 imask
[i
] |= (type
& 0x3) << pos
;
2367 regmask
&= (regmask
- 1);
2378 count_bits (unsigned long mask
)
2391 slot_index (unsigned long slot_addr
, unsigned long first_addr
)
2393 return (3*((slot_addr
>> 4) - (first_addr
>> 4))
2394 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2397 /* Given a complete record list, process any records which have
2398 unresolved fields, (ie length counts for a prologue). After
2399 this has been run, all neccessary information should be available
2400 within each record to generate an image. */
2402 fixup_unw_records (list
)
2405 unw_rec_list
*ptr
, *region
= 0;
2406 unsigned long first_addr
= 0, rlen
= 0, t
;
2408 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2410 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2411 as_bad (" Insn slot not set in unwind record.");
2412 t
= slot_index (ptr
->slot_number
, first_addr
);
2413 switch (ptr
->r
.type
)
2420 int size
, dir_len
= 0;
2421 unsigned long last_addr
;
2423 first_addr
= ptr
->slot_number
;
2424 ptr
->slot_number
= 0;
2425 /* Find either the next body/prologue start, or the end of
2426 the list, and determine the size of the region. */
2427 last_addr
= unwind
.next_slot_number
;
2428 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2429 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2430 || last
->r
.type
== body
)
2432 last_addr
= last
->slot_number
;
2435 else if (!last
->next
)
2437 /* In the absence of an explicit .body directive,
2438 the prologue ends after the last instruction
2439 covered by an unwind directive. */
2440 if (ptr
->r
.type
!= body
)
2442 last_addr
= last
->slot_number
;
2443 switch (last
->r
.type
)
2446 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2447 + count_bits (last
->r
.record
.p
.grmask
));
2451 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2455 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2458 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2467 size
= slot_index (last_addr
, first_addr
) + dir_len
;
2468 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2473 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2484 case priunat_when_gr
:
2485 case priunat_when_mem
:
2489 ptr
->r
.record
.p
.t
= t
;
2497 case spill_psprel_p
:
2498 ptr
->r
.record
.x
.t
= t
;
2504 as_bad ("frgr_mem record before region record!\n");
2507 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2508 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2509 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2510 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2515 as_bad ("fr_mem record before region record!\n");
2518 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2519 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2524 as_bad ("gr_mem record before region record!\n");
2527 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2528 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2533 as_bad ("br_mem record before region record!\n");
2536 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2537 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2543 as_bad ("gr_gr record before region record!\n");
2546 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2551 as_bad ("br_gr record before region record!\n");
2554 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2563 /* Generate an unwind image from a record list. Returns the number of
2564 bytes in the resulting image. The memory image itselof is returned
2565 in the 'ptr' parameter. */
2567 output_unw_records (list
, ptr
)
2571 int size
, x
, extra
= 0;
2574 fixup_unw_records (list
);
2575 size
= calc_record_size (list
);
2577 /* pad to 8 byte boundry. */
2581 /* Add 8 for the header + 8 more bytes for the personality offset. */
2582 mem
= xmalloc (size
+ extra
+ 16);
2584 vbyte_mem_ptr
= mem
+ 8;
2585 /* Clear the padding area and personality. */
2586 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2587 /* Initialize the header area. */
2588 md_number_to_chars (mem
, ( ((bfd_vma
) 1 << 48) /* version */
2589 | ((bfd_vma
) 3 << 32) /* U & E handler flags */
2590 | ((size
+ extra
) / 8)), /* length (dwords) */
2593 process_unw_records (list
, output_vbyte_mem
);
2596 return size
+ extra
+ 16;
2600 convert_expr_to_ab_reg (e
, ab
, regp
)
2607 if (e
->X_op
!= O_register
)
2610 reg
= e
->X_add_number
;
2611 if (reg
>= REG_GR
+ 4 && reg
<= REG_GR
+ 7)
2614 *regp
= reg
- REG_GR
;
2616 else if ((reg
>= REG_FR
+ 2 && reg
<= REG_FR
+ 5)
2617 || (reg
>= REG_FR
+ 16 && reg
<= REG_FR
+ 31))
2620 *regp
= reg
- REG_FR
;
2622 else if (reg
>= REG_BR
+ 1 && reg
<= REG_BR
+ 5)
2625 *regp
= reg
- REG_BR
;
2632 case REG_PR
: *regp
= 0; break;
2633 case REG_PSP
: *regp
= 1; break;
2634 case REG_PRIUNAT
: *regp
= 2; break;
2635 case REG_BR
+ 0: *regp
= 3; break;
2636 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2637 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2638 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2639 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2640 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2641 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2642 case REG_AR
+ AR_LC
: *regp
= 10; break;
2652 convert_expr_to_xy_reg (e
, xy
, regp
)
2659 if (e
->X_op
!= O_register
)
2662 reg
= e
->X_add_number
;
2664 if (reg
>= REG_GR
&& reg
<= REG_GR
+ 127)
2667 *regp
= reg
- REG_GR
;
2669 else if (reg
>= REG_FR
&& reg
<= REG_FR
+ 127)
2672 *regp
= reg
- REG_FR
;
2674 else if (reg
>= REG_BR
&& reg
<= REG_BR
+ 7)
2677 *regp
= reg
- REG_BR
;
2691 radix
= *input_line_pointer
++;
2693 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2695 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2696 ignore_rest_of_line ();
2701 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2703 dot_special_section (which
)
2706 set_section ((char *) special_section_name
[which
]);
2710 add_unwind_entry (ptr
)
2714 unwind
.tail
->next
= ptr
;
2719 /* The current entry can in fact be a chain of unwind entries. */
2720 if (unwind
.current_entry
== NULL
)
2721 unwind
.current_entry
= ptr
;
2732 if (e
.X_op
!= O_constant
)
2733 as_bad ("Operand to .fframe must be a constant");
2735 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2746 reg
= e
.X_add_number
- REG_GR
;
2747 if (e
.X_op
== O_register
&& reg
< 128)
2749 add_unwind_entry (output_mem_stack_v ());
2750 add_unwind_entry (output_psp_gr (reg
));
2753 as_bad ("First operand to .vframe must be a general register");
2757 dot_vframesp (dummy
)
2763 if (e
.X_op
== O_constant
)
2765 add_unwind_entry (output_mem_stack_v ());
2766 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2769 as_bad ("First operand to .vframesp must be a general register");
2773 dot_vframepsp (dummy
)
2779 if (e
.X_op
== O_constant
)
2781 add_unwind_entry (output_mem_stack_v ());
2782 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2785 as_bad ("First operand to .vframepsp must be a general register");
2796 sep
= parse_operand (&e1
);
2798 as_bad ("No second operand to .save");
2799 sep
= parse_operand (&e2
);
2801 reg1
= e1
.X_add_number
;
2802 reg2
= e2
.X_add_number
- REG_GR
;
2804 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2805 if (e1
.X_op
== O_register
)
2807 if (e2
.X_op
== O_register
&& reg2
>=0 && reg2
< 128)
2811 case REG_AR
+ AR_BSP
:
2812 add_unwind_entry (output_bsp_when ());
2813 add_unwind_entry (output_bsp_gr (reg2
));
2815 case REG_AR
+ AR_BSPSTORE
:
2816 add_unwind_entry (output_bspstore_when ());
2817 add_unwind_entry (output_bspstore_gr (reg2
));
2819 case REG_AR
+ AR_RNAT
:
2820 add_unwind_entry (output_rnat_when ());
2821 add_unwind_entry (output_rnat_gr (reg2
));
2823 case REG_AR
+AR_UNAT
:
2824 add_unwind_entry (output_unat_when ());
2825 add_unwind_entry (output_unat_gr (reg2
));
2827 case REG_AR
+AR_FPSR
:
2828 add_unwind_entry (output_fpsr_when ());
2829 add_unwind_entry (output_fpsr_gr (reg2
));
2832 add_unwind_entry (output_pfs_when ());
2833 add_unwind_entry (output_pfs_gr (reg2
));
2836 add_unwind_entry (output_lc_when ());
2837 add_unwind_entry (output_lc_gr (reg2
));
2840 add_unwind_entry (output_rp_when ());
2841 add_unwind_entry (output_rp_gr (reg2
));
2844 add_unwind_entry (output_preds_when ());
2845 add_unwind_entry (output_preds_gr (reg2
));
2848 add_unwind_entry (output_priunat_when_gr ());
2849 add_unwind_entry (output_priunat_gr (reg2
));
2852 as_bad ("First operand not a valid register");
2856 as_bad (" Second operand not a valid register");
2859 as_bad ("First operand not a register");
2867 unsigned long ecount
= 0;
2870 sep
= parse_operand (&e1
);
2871 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
2873 as_bad ("First operand to .restore must be stack pointer (sp)");
2879 parse_operand (&e2
);
2880 if (e1
.X_op
!= O_constant
)
2882 as_bad ("Second operand to .restore must be constant");
2887 add_unwind_entry (output_epilogue (ecount
));
2891 dot_restorereg (dummy
)
2894 unsigned int ab
, reg
;
2899 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
2901 as_bad ("First operand to .restorereg must be a preserved register");
2904 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
2908 dot_restorereg_p (dummy
)
2911 unsigned int qp
, ab
, reg
;
2915 sep
= parse_operand (&e1
);
2918 as_bad ("No second operand to .restorereg.p");
2922 parse_operand (&e2
);
2924 qp
= e1
.X_add_number
- REG_P
;
2925 if (e1
.X_op
!= O_register
|| qp
> 63)
2927 as_bad ("First operand to .restorereg.p must be a predicate");
2931 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
2933 as_bad ("Second operand to .restorereg.p must be a preserved register");
2936 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
2940 generate_unwind_image ()
2943 unsigned char *unw_rec
;
2945 /* Force out pending instructions, to make sure all unwind records have
2946 a valid slot_number field. */
2947 ia64_flush_insns ();
2949 /* Generate the unwind record. */
2950 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
2952 as_bad ("Unwind record is not a multiple of 8 bytes.");
2954 /* If there are unwind records, switch sections, and output the info. */
2957 unsigned char *where
;
2959 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND_INFO
]);
2961 /* Set expression which points to start of unwind descriptor area. */
2962 unwind
.info
= expr_build_dot ();
2964 where
= (unsigned char *)frag_more (size
);
2966 /* Issue a label for this address, and keep track of it to put it
2967 in the unwind section. */
2969 /* Copy the information from the unwind record into this section. The
2970 data is already in the correct byte order. */
2971 memcpy (where
, unw_rec
, size
);
2972 /* Add the personality address to the image. */
2973 if (unwind
.personality_routine
!= 0)
2975 exp
.X_op
= O_symbol
;
2976 exp
.X_add_symbol
= unwind
.personality_routine
;
2977 exp
.X_add_number
= 0;
2978 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
2979 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
2980 unwind
.personality_routine
= 0;
2982 obj_elf_previous (0);
2985 free_list_records (unwind
.list
);
2986 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
2992 dot_handlerdata (dummy
)
2995 generate_unwind_image ();
2996 demand_empty_rest_of_line ();
3000 dot_unwentry (dummy
)
3003 demand_empty_rest_of_line ();
3014 reg
= e
.X_add_number
- REG_BR
;
3015 if (e
.X_op
== O_register
&& reg
< 8)
3016 add_unwind_entry (output_rp_br (reg
));
3018 as_bad ("First operand not a valid branch register");
3022 dot_savemem (psprel
)
3029 sep
= parse_operand (&e1
);
3031 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3032 sep
= parse_operand (&e2
);
3034 reg1
= e1
.X_add_number
;
3035 val
= e2
.X_add_number
;
3037 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3038 if (e1
.X_op
== O_register
)
3040 if (e2
.X_op
== O_constant
)
3044 case REG_AR
+ AR_BSP
:
3045 add_unwind_entry (output_bsp_when ());
3046 add_unwind_entry ((psprel
3048 : output_bsp_sprel
) (val
));
3050 case REG_AR
+ AR_BSPSTORE
:
3051 add_unwind_entry (output_bspstore_when ());
3052 add_unwind_entry ((psprel
3053 ? output_bspstore_psprel
3054 : output_bspstore_sprel
) (val
));
3056 case REG_AR
+ AR_RNAT
:
3057 add_unwind_entry (output_rnat_when ());
3058 add_unwind_entry ((psprel
3059 ? output_rnat_psprel
3060 : output_rnat_sprel
) (val
));
3062 case REG_AR
+ AR_UNAT
:
3063 add_unwind_entry (output_unat_when ());
3064 add_unwind_entry ((psprel
3065 ? output_unat_psprel
3066 : output_unat_sprel
) (val
));
3068 case REG_AR
+ AR_FPSR
:
3069 add_unwind_entry (output_fpsr_when ());
3070 add_unwind_entry ((psprel
3071 ? output_fpsr_psprel
3072 : output_fpsr_sprel
) (val
));
3074 case REG_AR
+ AR_PFS
:
3075 add_unwind_entry (output_pfs_when ());
3076 add_unwind_entry ((psprel
3078 : output_pfs_sprel
) (val
));
3080 case REG_AR
+ AR_LC
:
3081 add_unwind_entry (output_lc_when ());
3082 add_unwind_entry ((psprel
3084 : output_lc_sprel
) (val
));
3087 add_unwind_entry (output_rp_when ());
3088 add_unwind_entry ((psprel
3090 : output_rp_sprel
) (val
));
3093 add_unwind_entry (output_preds_when ());
3094 add_unwind_entry ((psprel
3095 ? output_preds_psprel
3096 : output_preds_sprel
) (val
));
3099 add_unwind_entry (output_priunat_when_mem ());
3100 add_unwind_entry ((psprel
3101 ? output_priunat_psprel
3102 : output_priunat_sprel
) (val
));
3105 as_bad ("First operand not a valid register");
3109 as_bad (" Second operand not a valid constant");
3112 as_bad ("First operand not a register");
3121 sep
= parse_operand (&e1
);
3123 parse_operand (&e2
);
3125 if (e1
.X_op
!= O_constant
)
3126 as_bad ("First operand to .save.g must be a constant.");
3129 int grmask
= e1
.X_add_number
;
3131 add_unwind_entry (output_gr_mem (grmask
));
3134 int reg
= e2
.X_add_number
- REG_GR
;
3135 if (e2
.X_op
== O_register
&& reg
>=0 && reg
< 128)
3136 add_unwind_entry (output_gr_gr (grmask
, reg
));
3138 as_bad ("Second operand is an invalid register.");
3149 sep
= parse_operand (&e1
);
3151 if (e1
.X_op
!= O_constant
)
3152 as_bad ("Operand to .save.f must be a constant.");
3154 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3166 sep
= parse_operand (&e1
);
3167 if (e1
.X_op
!= O_constant
)
3169 as_bad ("First operand to .save.b must be a constant.");
3172 brmask
= e1
.X_add_number
;
3176 sep
= parse_operand (&e2
);
3177 reg
= e2
.X_add_number
- REG_GR
;
3178 if (e2
.X_op
!= O_register
|| reg
> 127)
3180 as_bad ("Second operand to .save.b must be a general register.");
3183 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3186 add_unwind_entry (output_br_mem (brmask
));
3188 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3189 ignore_rest_of_line ();
3198 sep
= parse_operand (&e1
);
3200 parse_operand (&e2
);
3202 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3203 as_bad ("Both operands of .save.gf must be constants.");
3206 int grmask
= e1
.X_add_number
;
3207 int frmask
= e2
.X_add_number
;
3208 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3219 sep
= parse_operand (&e
);
3220 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3221 ignore_rest_of_line ();
3223 if (e
.X_op
!= O_constant
)
3224 as_bad ("Operand to .spill must be a constant");
3226 add_unwind_entry (output_spill_base (e
.X_add_number
));
3230 dot_spillreg (dummy
)
3233 int sep
, ab
, xy
, reg
, treg
;
3236 sep
= parse_operand (&e1
);
3239 as_bad ("No second operand to .spillreg");
3243 parse_operand (&e2
);
3245 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3247 as_bad ("First operand to .spillreg must be a preserved register");
3251 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3253 as_bad ("Second operand to .spillreg must be a register");
3257 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3261 dot_spillmem (psprel
)
3267 sep
= parse_operand (&e1
);
3270 as_bad ("Second operand missing");
3274 parse_operand (&e2
);
3276 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3278 as_bad ("First operand to .spill%s must be a preserved register",
3279 psprel
? "psp" : "sp");
3283 if (e2
.X_op
!= O_constant
)
3285 as_bad ("Second operand to .spill%s must be a constant",
3286 psprel
? "psp" : "sp");
3291 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3293 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3297 dot_spillreg_p (dummy
)
3300 int sep
, ab
, xy
, reg
, treg
;
3301 expressionS e1
, e2
, e3
;
3304 sep
= parse_operand (&e1
);
3307 as_bad ("No second and third operand to .spillreg.p");
3311 sep
= parse_operand (&e2
);
3314 as_bad ("No third operand to .spillreg.p");
3318 parse_operand (&e3
);
3320 qp
= e1
.X_add_number
- REG_P
;
3322 if (e1
.X_op
!= O_register
|| qp
> 63)
3324 as_bad ("First operand to .spillreg.p must be a predicate");
3328 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3330 as_bad ("Second operand to .spillreg.p must be a preserved register");
3334 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3336 as_bad ("Third operand to .spillreg.p must be a register");
3340 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3344 dot_spillmem_p (psprel
)
3347 expressionS e1
, e2
, e3
;
3351 sep
= parse_operand (&e1
);
3354 as_bad ("Second operand missing");
3358 parse_operand (&e2
);
3361 as_bad ("Second operand missing");
3365 parse_operand (&e3
);
3367 qp
= e1
.X_add_number
- REG_P
;
3368 if (e1
.X_op
!= O_register
|| qp
> 63)
3370 as_bad ("First operand to .spill%s_p must be a predicate",
3371 psprel
? "psp" : "sp");
3375 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3377 as_bad ("Second operand to .spill%s_p must be a preserved register",
3378 psprel
? "psp" : "sp");
3382 if (e3
.X_op
!= O_constant
)
3384 as_bad ("Third operand to .spill%s_p must be a constant",
3385 psprel
? "psp" : "sp");
3390 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3392 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3396 dot_label_state (dummy
)
3402 if (e
.X_op
!= O_constant
)
3404 as_bad ("Operand to .label_state must be a constant");
3407 add_unwind_entry (output_label_state (e
.X_add_number
));
3411 dot_copy_state (dummy
)
3417 if (e
.X_op
!= O_constant
)
3419 as_bad ("Operand to .copy_state must be a constant");
3422 add_unwind_entry (output_copy_state (e
.X_add_number
));
3432 sep
= parse_operand (&e1
);
3435 as_bad ("Second operand to .unwabi missing");
3438 sep
= parse_operand (&e2
);
3439 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3440 ignore_rest_of_line ();
3442 if (e1
.X_op
!= O_constant
)
3444 as_bad ("First operand to .unwabi must be a constant");
3448 if (e2
.X_op
!= O_constant
)
3450 as_bad ("Second operand to .unwabi must be a constant");
3454 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3458 dot_personality (dummy
)
3463 name
= input_line_pointer
;
3464 c
= get_symbol_end ();
3465 p
= input_line_pointer
;
3466 unwind
.personality_routine
= symbol_find_or_make (name
);
3469 demand_empty_rest_of_line ();
3479 unwind
.proc_start
= expr_build_dot ();
3480 /* Parse names of main and alternate entry points and mark them as
3481 function symbols: */
3485 name
= input_line_pointer
;
3486 c
= get_symbol_end ();
3487 p
= input_line_pointer
;
3488 sym
= symbol_find_or_make (name
);
3489 if (unwind
.proc_start
== 0)
3491 unwind
.proc_start
= sym
;
3493 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3496 if (*input_line_pointer
!= ',')
3498 ++input_line_pointer
;
3500 demand_empty_rest_of_line ();
3503 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3504 unwind
.personality_routine
= 0;
3511 unwind
.prologue
= 0;
3512 add_unwind_entry (output_body ());
3513 demand_empty_rest_of_line ();
3517 dot_prologue (dummy
)
3522 unwind
.prologue
= 1;
3523 if (!is_it_end_of_statement ())
3526 sep
= parse_operand (&e1
);
3528 as_bad ("No second operand to .prologue");
3529 sep
= parse_operand (&e2
);
3530 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3531 ignore_rest_of_line ();
3533 if (e1
.X_op
== O_constant
)
3535 if (e2
.X_op
== O_constant
)
3537 int mask
= e1
.X_add_number
;
3538 int reg
= e2
.X_add_number
;
3539 add_unwind_entry (output_prologue_gr (mask
, reg
));
3542 as_bad ("Second operand not a constant");
3545 as_bad ("First operand not a constant");
3548 add_unwind_entry (output_prologue ());
3559 subsegT saved_subseg
;
3561 saved_seg
= now_seg
;
3562 saved_subseg
= now_subseg
;
3565 demand_empty_rest_of_line ();
3567 insn_group_break (1, 0, 0);
3569 /* If there was a .handlerdata, we haven't generated an image yet. */
3570 if (unwind
.info
== 0)
3572 generate_unwind_image ();
3575 subseg_set (md
.last_text_seg
, 0);
3576 unwind
.proc_end
= expr_build_dot ();
3578 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND
]);
3579 ptr
= frag_more (24);
3580 where
= frag_now_fix () - 24;
3582 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3583 e
.X_op
= O_pseudo_fixup
;
3584 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3586 e
.X_add_symbol
= unwind
.proc_start
;
3587 ia64_cons_fix_new (frag_now
, where
, 8, &e
);
3589 e
.X_op
= O_pseudo_fixup
;
3590 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3592 e
.X_add_symbol
= unwind
.proc_end
;
3593 ia64_cons_fix_new (frag_now
, where
+ 8, 8, &e
);
3595 if (unwind
.info
!= 0)
3597 e
.X_op
= O_pseudo_fixup
;
3598 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3600 e
.X_add_symbol
= unwind
.info
;
3601 ia64_cons_fix_new (frag_now
, where
+ 16, 8, &e
);
3604 md_number_to_chars (ptr
+ 16, 0, 8);
3606 subseg_set (saved_seg
, saved_subseg
);
3607 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3611 dot_template (template)
3614 CURR_SLOT
.user_template
= template;
3621 int ins
, locs
, outs
, rots
;
3623 if (is_it_end_of_statement ())
3624 ins
= locs
= outs
= rots
= 0;
3627 ins
= get_absolute_expression ();
3628 if (*input_line_pointer
++ != ',')
3630 locs
= get_absolute_expression ();
3631 if (*input_line_pointer
++ != ',')
3633 outs
= get_absolute_expression ();
3634 if (*input_line_pointer
++ != ',')
3636 rots
= get_absolute_expression ();
3638 set_regstack (ins
, locs
, outs
, rots
);
3642 as_bad ("Comma expected");
3643 ignore_rest_of_line ();
3650 unsigned num_regs
, num_alloced
= 0;
3651 struct dynreg
**drpp
, *dr
;
3652 int ch
, base_reg
= 0;
3658 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3659 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3660 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3664 /* first, remove existing names from hash table: */
3665 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3667 hash_delete (md
.dynreg_hash
, dr
->name
);
3671 drpp
= &md
.dynreg
[type
];
3674 start
= input_line_pointer
;
3675 ch
= get_symbol_end ();
3676 *input_line_pointer
= ch
;
3677 len
= (input_line_pointer
- start
);
3680 if (*input_line_pointer
!= '[')
3682 as_bad ("Expected '['");
3685 ++input_line_pointer
; /* skip '[' */
3687 num_regs
= get_absolute_expression ();
3689 if (*input_line_pointer
++ != ']')
3691 as_bad ("Expected ']'");
3696 num_alloced
+= num_regs
;
3700 if (num_alloced
> md
.rot
.num_regs
)
3702 as_bad ("Used more than the declared %d rotating registers",
3708 if (num_alloced
> 96)
3710 as_bad ("Used more than the available 96 rotating registers");
3715 if (num_alloced
> 48)
3717 as_bad ("Used more than the available 48 rotating registers");
3726 name
= obstack_alloc (¬es
, len
+ 1);
3727 memcpy (name
, start
, len
);
3732 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
3733 memset (*drpp
, 0, sizeof (*dr
));
3738 dr
->num_regs
= num_regs
;
3739 dr
->base
= base_reg
;
3741 base_reg
+= num_regs
;
3743 if (hash_insert (md
.dynreg_hash
, name
, dr
))
3745 as_bad ("Attempt to redefine register set `%s'", name
);
3749 if (*input_line_pointer
!= ',')
3751 ++input_line_pointer
; /* skip comma */
3754 demand_empty_rest_of_line ();
3758 ignore_rest_of_line ();
3762 dot_byteorder (byteorder
)
3765 target_big_endian
= byteorder
;
3777 option
= input_line_pointer
;
3778 ch
= get_symbol_end ();
3779 if (strcmp (option
, "lsb") == 0)
3780 md
.flags
&= ~EF_IA_64_BE
;
3781 else if (strcmp (option
, "msb") == 0)
3782 md
.flags
|= EF_IA_64_BE
;
3783 else if (strcmp (option
, "abi32") == 0)
3784 md
.flags
&= ~EF_IA_64_ABI64
;
3785 else if (strcmp (option
, "abi64") == 0)
3786 md
.flags
|= EF_IA_64_ABI64
;
3788 as_bad ("Unknown psr option `%s'", option
);
3789 *input_line_pointer
= ch
;
3792 if (*input_line_pointer
!= ',')
3795 ++input_line_pointer
;
3798 demand_empty_rest_of_line ();
3805 as_bad (".alias not implemented yet");
3812 new_logical_line (0, get_absolute_expression ());
3813 demand_empty_rest_of_line ();
3817 parse_section_name ()
3823 if (*input_line_pointer
!= '"')
3825 as_bad ("Missing section name");
3826 ignore_rest_of_line ();
3829 name
= demand_copy_C_string (&len
);
3832 ignore_rest_of_line ();
3836 if (*input_line_pointer
!= ',')
3838 as_bad ("Comma expected after section name");
3839 ignore_rest_of_line ();
3842 ++input_line_pointer
; /* skip comma */
3850 char *name
= parse_section_name ();
3856 obj_elf_previous (0);
3859 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3861 stmt_float_cons (kind
)
3868 case 'd': size
= 8; break;
3869 case 'x': size
= 10; break;
3876 ia64_do_align (size
);
3884 int saved_auto_align
= md
.auto_align
;
3888 md
.auto_align
= saved_auto_align
;
3892 dot_xfloat_cons (kind
)
3895 char *name
= parse_section_name ();
3900 stmt_float_cons (kind
);
3901 obj_elf_previous (0);
3905 dot_xstringer (zero
)
3908 char *name
= parse_section_name ();
3914 obj_elf_previous (0);
3921 int saved_auto_align
= md
.auto_align
;
3922 char *name
= parse_section_name ();
3929 md
.auto_align
= saved_auto_align
;
3930 obj_elf_previous (0);
3934 dot_xfloat_cons_ua (kind
)
3937 int saved_auto_align
= md
.auto_align
;
3938 char *name
= parse_section_name ();
3944 stmt_float_cons (kind
);
3945 md
.auto_align
= saved_auto_align
;
3946 obj_elf_previous (0);
3949 /* .reg.val <regname>,value */
3957 if (reg
.X_op
!= O_register
)
3959 as_bad (_("Register name expected"));
3960 ignore_rest_of_line ();
3962 else if (*input_line_pointer
++ != ',')
3964 as_bad (_("Comma expected"));
3965 ignore_rest_of_line ();
3969 valueT value
= get_absolute_expression ();
3970 int regno
= reg
.X_add_number
;
3971 if (regno
< REG_GR
|| regno
> REG_GR
+128)
3972 as_warn (_("Register value annotation ignored"));
3975 gr_values
[regno
-REG_GR
].known
= 1;
3976 gr_values
[regno
-REG_GR
].value
= value
;
3977 gr_values
[regno
-REG_GR
].path
= md
.path
;
3980 demand_empty_rest_of_line ();
3983 /* select dv checking mode
3988 A stop is inserted when changing modes
3994 if (md
.manual_bundling
)
3995 as_warn (_("Directive invalid within a bundle"));
3997 if (type
== 'E' || type
== 'A')
3998 md
.mode_explicitly_set
= 0;
4000 md
.mode_explicitly_set
= 1;
4007 if (md
.explicit_mode
)
4008 insn_group_break (1, 0, 0);
4009 md
.explicit_mode
= 0;
4013 if (!md
.explicit_mode
)
4014 insn_group_break (1, 0, 0);
4015 md
.explicit_mode
= 1;
4019 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4020 insn_group_break (1, 0, 0);
4021 md
.explicit_mode
= md
.default_explicit_mode
;
4022 md
.mode_explicitly_set
= 0;
4033 for (regno
= 0;regno
< 64;regno
++)
4035 if (mask
& ((valueT
)1<<regno
))
4037 fprintf (stderr
, "%s p%d", comma
, regno
);
4044 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4045 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4046 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4047 .pred.safe_across_calls p1 [, p2 [,...]]
4055 int p1
= -1, p2
= -1;
4059 if (*input_line_pointer
!= '"')
4061 as_bad (_("Missing predicate relation type"));
4062 ignore_rest_of_line ();
4068 char *form
= demand_copy_C_string (&len
);
4069 if (strcmp (form
, "mutex") == 0)
4071 else if (strcmp (form
, "clear") == 0)
4073 else if (strcmp (form
, "imply") == 0)
4077 as_bad (_("Unrecognized predicate relation type"));
4078 ignore_rest_of_line ();
4082 if (*input_line_pointer
== ',')
4083 ++input_line_pointer
;
4093 if (toupper (*input_line_pointer
) != 'P'
4094 || (regno
= atoi (++input_line_pointer
)) < 0
4097 as_bad (_("Predicate register expected"));
4098 ignore_rest_of_line ();
4101 while (isdigit (*input_line_pointer
))
4102 ++input_line_pointer
;
4109 as_warn (_("Duplicate predicate register ignored"));
4110 mask
|= bit
; count
++;
4111 /* see if it's a range */
4112 if (*input_line_pointer
== '-')
4115 ++input_line_pointer
;
4117 if (toupper (*input_line_pointer
) != 'P'
4118 || (regno
= atoi (++input_line_pointer
)) < 0
4121 as_bad (_("Predicate register expected"));
4122 ignore_rest_of_line ();
4125 while (isdigit (*input_line_pointer
))
4126 ++input_line_pointer
;
4130 as_bad (_("Bad register range"));
4131 ignore_rest_of_line ();
4137 mask
|= bit
; count
++;
4141 if (*input_line_pointer
!= ',')
4143 ++input_line_pointer
;
4152 clear_qp_mutex (mask
);
4153 clear_qp_implies (mask
, (valueT
)0);
4156 if (count
!= 2 || p1
== -1 || p2
== -1)
4157 as_bad (_("Predicate source and target required"));
4158 else if (p1
== 0 || p2
== 0)
4159 as_bad (_("Use of p0 is not valid in this context"));
4161 add_qp_imply (p1
, p2
);
4166 as_bad (_("At least two PR arguments expected"));
4171 as_bad (_("Use of p0 is not valid in this context"));
4174 add_qp_mutex (mask
);
4177 /* note that we don't override any existing relations */
4180 as_bad (_("At least one PR argument expected"));
4185 fprintf (stderr
, "Safe across calls: ");
4186 print_prmask (mask
);
4187 fprintf (stderr
, "\n");
4189 qp_safe_across_calls
= mask
;
4192 demand_empty_rest_of_line ();
4195 /* .entry label [, label [, ...]]
4196 Hint to DV code that the given labels are to be considered entry points.
4197 Otherwise, only global labels are considered entry points.
4210 name
= input_line_pointer
;
4211 c
= get_symbol_end ();
4212 symbolP
= symbol_find_or_make (name
);
4214 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4216 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4219 *input_line_pointer
= c
;
4221 c
= *input_line_pointer
;
4224 input_line_pointer
++;
4226 if (*input_line_pointer
== '\n')
4232 demand_empty_rest_of_line ();
4235 /* .mem.offset offset, base
4236 "base" is used to distinguish between offsets from a different base.
4239 dot_mem_offset (dummy
)
4242 md
.mem_offset
.hint
= 1;
4243 md
.mem_offset
.offset
= get_absolute_expression ();
4244 if (*input_line_pointer
!= ',')
4246 as_bad (_("Comma expected"));
4247 ignore_rest_of_line ();
4250 ++input_line_pointer
;
4251 md
.mem_offset
.base
= get_absolute_expression ();
4252 demand_empty_rest_of_line ();
4255 /* ia64-specific pseudo-ops: */
4256 const pseudo_typeS md_pseudo_table
[] =
4258 { "radix", dot_radix
, 0 },
4259 { "lcomm", s_lcomm_bytes
, 1 },
4260 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4261 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4262 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4263 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4264 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4265 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4266 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4267 { "proc", dot_proc
, 0 },
4268 { "body", dot_body
, 0 },
4269 { "prologue", dot_prologue
, 0 },
4270 { "endp", dot_endp
},
4271 { "file", dwarf2_directive_file
},
4272 { "loc", dwarf2_directive_loc
},
4274 { "fframe", dot_fframe
},
4275 { "vframe", dot_vframe
},
4276 { "vframesp", dot_vframesp
},
4277 { "vframepsp", dot_vframepsp
},
4278 { "save", dot_save
},
4279 { "restore", dot_restore
},
4280 { "restorereg", dot_restorereg
},
4281 { "restorereg.p", dot_restorereg_p
},
4282 { "handlerdata", dot_handlerdata
},
4283 { "unwentry", dot_unwentry
},
4284 { "altrp", dot_altrp
},
4285 { "savesp", dot_savemem
, 0 },
4286 { "savepsp", dot_savemem
, 1 },
4287 { "save.g", dot_saveg
},
4288 { "save.f", dot_savef
},
4289 { "save.b", dot_saveb
},
4290 { "save.gf", dot_savegf
},
4291 { "spill", dot_spill
},
4292 { "spillreg", dot_spillreg
},
4293 { "spillsp", dot_spillmem
, 0 },
4294 { "spillpsp", dot_spillmem
, 1 },
4295 { "spillreg.p", dot_spillreg_p
},
4296 { "spillsp.p", dot_spillmem_p
, 0 },
4297 { "spillpsp.p", dot_spillmem_p
, 1 },
4298 { "label_state", dot_label_state
},
4299 { "copy_state", dot_copy_state
},
4300 { "unwabi", dot_unwabi
},
4301 { "personality", dot_personality
},
4303 { "estate", dot_estate
},
4305 { "mii", dot_template
, 0x0 },
4306 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4307 { "mlx", dot_template
, 0x2 },
4308 { "mmi", dot_template
, 0x4 },
4309 { "mfi", dot_template
, 0x6 },
4310 { "mmf", dot_template
, 0x7 },
4311 { "mib", dot_template
, 0x8 },
4312 { "mbb", dot_template
, 0x9 },
4313 { "bbb", dot_template
, 0xb },
4314 { "mmb", dot_template
, 0xc },
4315 { "mfb", dot_template
, 0xe },
4317 { "lb", dot_scope
, 0 },
4318 { "le", dot_scope
, 1 },
4320 { "align", s_align_bytes
, 0 },
4321 { "regstk", dot_regstk
, 0 },
4322 { "rotr", dot_rot
, DYNREG_GR
},
4323 { "rotf", dot_rot
, DYNREG_FR
},
4324 { "rotp", dot_rot
, DYNREG_PR
},
4325 { "lsb", dot_byteorder
, 0 },
4326 { "msb", dot_byteorder
, 1 },
4327 { "psr", dot_psr
, 0 },
4328 { "alias", dot_alias
, 0 },
4329 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4331 { "xdata1", dot_xdata
, 1 },
4332 { "xdata2", dot_xdata
, 2 },
4333 { "xdata4", dot_xdata
, 4 },
4334 { "xdata8", dot_xdata
, 8 },
4335 { "xreal4", dot_xfloat_cons
, 'f' },
4336 { "xreal8", dot_xfloat_cons
, 'd' },
4337 { "xreal10", dot_xfloat_cons
, 'x' },
4338 { "xstring", dot_xstringer
, 0 },
4339 { "xstringz", dot_xstringer
, 1 },
4341 /* unaligned versions: */
4342 { "xdata2.ua", dot_xdata_ua
, 2 },
4343 { "xdata4.ua", dot_xdata_ua
, 4 },
4344 { "xdata8.ua", dot_xdata_ua
, 8 },
4345 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4346 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4347 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4349 /* annotations/DV checking support */
4350 { "entry", dot_entry
, 0 },
4351 { "mem.offset", dot_mem_offset
},
4352 { "pred.rel", dot_pred_rel
, 0 },
4353 { "pred.rel.clear", dot_pred_rel
, 'c' },
4354 { "pred.rel.imply", dot_pred_rel
, 'i' },
4355 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4356 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4357 { "reg.val", dot_reg_val
},
4358 { "auto", dot_dv_mode
, 'a' },
4359 { "explicit", dot_dv_mode
, 'e' },
4360 { "default", dot_dv_mode
, 'd' },
4365 static const struct pseudo_opcode
4368 void (*handler
) (int);
4373 /* these are more like pseudo-ops, but don't start with a dot */
4374 { "data1", cons
, 1 },
4375 { "data2", cons
, 2 },
4376 { "data4", cons
, 4 },
4377 { "data8", cons
, 8 },
4378 { "real4", stmt_float_cons
, 'f' },
4379 { "real8", stmt_float_cons
, 'd' },
4380 { "real10", stmt_float_cons
, 'x' },
4381 { "string", stringer
, 0 },
4382 { "stringz", stringer
, 1 },
4384 /* unaligned versions: */
4385 { "data2.ua", stmt_cons_ua
, 2 },
4386 { "data4.ua", stmt_cons_ua
, 4 },
4387 { "data8.ua", stmt_cons_ua
, 8 },
4388 { "real4.ua", float_cons
, 'f' },
4389 { "real8.ua", float_cons
, 'd' },
4390 { "real10.ua", float_cons
, 'x' },
4393 /* Declare a register by creating a symbol for it and entering it in
4394 the symbol table. */
4396 declare_register (name
, regnum
)
4403 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4405 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4407 as_fatal ("Inserting \"%s\" into register table failed: %s",
4414 declare_register_set (prefix
, num_regs
, base_regnum
)
4422 for (i
= 0; i
< num_regs
; ++i
)
4424 sprintf (name
, "%s%u", prefix
, i
);
4425 declare_register (name
, base_regnum
+ i
);
4430 operand_width (opnd
)
4431 enum ia64_opnd opnd
;
4433 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4434 unsigned int bits
= 0;
4438 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4439 bits
+= odesc
->field
[i
].bits
;
4445 operand_match (idesc
, index
, e
)
4446 const struct ia64_opcode
*idesc
;
4450 enum ia64_opnd opnd
= idesc
->operands
[index
];
4451 int bits
, relocatable
= 0;
4452 struct insn_fix
*fix
;
4459 case IA64_OPND_AR_CCV
:
4460 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4464 case IA64_OPND_AR_PFS
:
4465 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4470 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4475 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4480 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4484 case IA64_OPND_PR_ROT
:
4485 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4490 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4494 case IA64_OPND_PSR_L
:
4495 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4499 case IA64_OPND_PSR_UM
:
4500 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4505 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4510 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4515 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4519 /* register operands: */
4522 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4523 && e
->X_add_number
< REG_AR
+ 128)
4529 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4530 && e
->X_add_number
< REG_BR
+ 8)
4535 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4536 && e
->X_add_number
< REG_CR
+ 128)
4544 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4545 && e
->X_add_number
< REG_FR
+ 128)
4551 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4552 && e
->X_add_number
< REG_P
+ 64)
4559 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4560 && e
->X_add_number
< REG_GR
+ 128)
4564 case IA64_OPND_R3_2
:
4565 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4566 && e
->X_add_number
< REG_GR
+ 4)
4570 /* indirect operands: */
4571 case IA64_OPND_CPUID_R3
:
4572 case IA64_OPND_DBR_R3
:
4573 case IA64_OPND_DTR_R3
:
4574 case IA64_OPND_ITR_R3
:
4575 case IA64_OPND_IBR_R3
:
4576 case IA64_OPND_MSR_R3
:
4577 case IA64_OPND_PKR_R3
:
4578 case IA64_OPND_PMC_R3
:
4579 case IA64_OPND_PMD_R3
:
4580 case IA64_OPND_RR_R3
:
4581 if (e
->X_op
== O_index
&& e
->X_op_symbol
4582 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4583 == opnd
- IA64_OPND_CPUID_R3
))
4588 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4592 /* immediate operands: */
4593 case IA64_OPND_CNT2a
:
4594 case IA64_OPND_LEN4
:
4595 case IA64_OPND_LEN6
:
4596 bits
= operand_width (idesc
->operands
[index
]);
4597 if (e
->X_op
== O_constant
4598 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4602 case IA64_OPND_CNT2b
:
4603 if (e
->X_op
== O_constant
4604 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4608 case IA64_OPND_CNT2c
:
4609 val
= e
->X_add_number
;
4610 if (e
->X_op
== O_constant
4611 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4616 /* SOR must be an integer multiple of 8 */
4617 if (e
->X_add_number
& 0x7)
4621 if (e
->X_op
== O_constant
&&
4622 (bfd_vma
) e
->X_add_number
<= 96)
4626 case IA64_OPND_IMMU62
:
4627 if (e
->X_op
== O_constant
)
4629 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4634 /* FIXME -- need 62-bit relocation type */
4635 as_bad (_("62-bit relocation not yet implemented"));
4639 case IA64_OPND_IMMU64
:
4640 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4641 || e
->X_op
== O_subtract
)
4643 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4644 fix
->code
= BFD_RELOC_IA64_IMM64
;
4645 if (e
->X_op
!= O_subtract
)
4647 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4648 if (e
->X_op
== O_pseudo_fixup
)
4652 fix
->opnd
= idesc
->operands
[index
];
4655 ++CURR_SLOT
.num_fixups
;
4658 else if (e
->X_op
== O_constant
)
4662 case IA64_OPND_CCNT5
:
4663 case IA64_OPND_CNT5
:
4664 case IA64_OPND_CNT6
:
4665 case IA64_OPND_CPOS6a
:
4666 case IA64_OPND_CPOS6b
:
4667 case IA64_OPND_CPOS6c
:
4668 case IA64_OPND_IMMU2
:
4669 case IA64_OPND_IMMU7a
:
4670 case IA64_OPND_IMMU7b
:
4671 case IA64_OPND_IMMU21
:
4672 case IA64_OPND_IMMU24
:
4673 case IA64_OPND_MBTYPE4
:
4674 case IA64_OPND_MHTYPE8
:
4675 case IA64_OPND_POS6
:
4676 bits
= operand_width (idesc
->operands
[index
]);
4677 if (e
->X_op
== O_constant
4678 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4682 case IA64_OPND_IMMU9
:
4683 bits
= operand_width (idesc
->operands
[index
]);
4684 if (e
->X_op
== O_constant
4685 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4687 int lobits
= e
->X_add_number
& 0x3;
4688 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4689 e
->X_add_number
|= (bfd_vma
)0x3;
4694 case IA64_OPND_IMM44
:
4695 /* least 16 bits must be zero */
4696 if ((e
->X_add_number
& 0xffff) != 0)
4697 as_warn (_("lower 16 bits of mask ignored"));
4699 if (e
->X_op
== O_constant
4700 && ((e
->X_add_number
>= 0
4701 && e
->X_add_number
< ((bfd_vma
) 1 << 44))
4702 || (e
->X_add_number
< 0
4703 && -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4706 if (e
->X_add_number
>= 0
4707 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4709 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
4715 case IA64_OPND_IMM17
:
4716 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4717 if (e
->X_op
== O_constant
4718 && ((e
->X_add_number
>= 0
4719 && e
->X_add_number
< ((bfd_vma
) 1 << 17))
4720 || (e
->X_add_number
< 0
4721 && -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
4724 if (e
->X_add_number
>= 0
4725 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
4727 e
->X_add_number
|= ~(((bfd_vma
)1 << 17) - 1);
4733 case IA64_OPND_IMM14
:
4734 case IA64_OPND_IMM22
:
4736 case IA64_OPND_IMM1
:
4737 case IA64_OPND_IMM8
:
4738 case IA64_OPND_IMM8U4
:
4739 case IA64_OPND_IMM8M1
:
4740 case IA64_OPND_IMM8M1U4
:
4741 case IA64_OPND_IMM8M1U8
:
4742 case IA64_OPND_IMM9a
:
4743 case IA64_OPND_IMM9b
:
4744 bits
= operand_width (idesc
->operands
[index
]);
4745 if (relocatable
&& (e
->X_op
== O_symbol
4746 || e
->X_op
== O_subtract
4747 || e
->X_op
== O_pseudo_fixup
))
4749 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4751 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
4752 fix
->code
= BFD_RELOC_IA64_IMM14
;
4754 fix
->code
= BFD_RELOC_IA64_IMM22
;
4756 if (e
->X_op
!= O_subtract
)
4758 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4759 if (e
->X_op
== O_pseudo_fixup
)
4763 fix
->opnd
= idesc
->operands
[index
];
4766 ++CURR_SLOT
.num_fixups
;
4769 else if (e
->X_op
!= O_constant
4770 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
4773 if (opnd
== IA64_OPND_IMM8M1U4
)
4775 /* Zero is not valid for unsigned compares that take an adjusted
4776 constant immediate range. */
4777 if (e
->X_add_number
== 0)
4780 /* Sign-extend 32-bit unsigned numbers, so that the following range
4781 checks will work. */
4782 val
= e
->X_add_number
;
4783 if (((val
& (~(bfd_vma
)0 << 32)) == 0)
4784 && ((val
& ((bfd_vma
)1 << 31)) != 0))
4785 val
= ((val
<< 32) >> 32);
4787 /* Check for 0x100000000. This is valid because
4788 0x100000000-1 is the same as ((uint32_t) -1). */
4789 if (val
== ((bfd_signed_vma
) 1 << 32))
4794 else if (opnd
== IA64_OPND_IMM8M1U8
)
4796 /* Zero is not valid for unsigned compares that take an adjusted
4797 constant immediate range. */
4798 if (e
->X_add_number
== 0)
4801 /* Check for 0x10000000000000000. */
4802 if (e
->X_op
== O_big
)
4804 if (generic_bignum
[0] == 0
4805 && generic_bignum
[1] == 0
4806 && generic_bignum
[2] == 0
4807 && generic_bignum
[3] == 0
4808 && generic_bignum
[4] == 1)
4814 val
= e
->X_add_number
- 1;
4816 else if (opnd
== IA64_OPND_IMM8M1
)
4817 val
= e
->X_add_number
- 1;
4818 else if (opnd
== IA64_OPND_IMM8U4
)
4820 /* Sign-extend 32-bit unsigned numbers, so that the following range
4821 checks will work. */
4822 val
= e
->X_add_number
;
4823 if (((val
& (~(bfd_vma
)0 << 32)) == 0)
4824 && ((val
& ((bfd_vma
)1 << 31)) != 0))
4825 val
= ((val
<< 32) >> 32);
4828 val
= e
->X_add_number
;
4830 if ((val
>= 0 && val
< ((bfd_vma
) 1 << (bits
- 1)))
4831 || (val
< 0 && -val
<= ((bfd_vma
) 1 << (bits
- 1))))
4835 case IA64_OPND_INC3
:
4836 /* +/- 1, 4, 8, 16 */
4837 val
= e
->X_add_number
;
4840 if (e
->X_op
== O_constant
4841 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
4845 case IA64_OPND_TGT25
:
4846 case IA64_OPND_TGT25b
:
4847 case IA64_OPND_TGT25c
:
4848 case IA64_OPND_TGT64
:
4849 if (e
->X_op
== O_symbol
)
4851 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4852 if (opnd
== IA64_OPND_TGT25
)
4853 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
4854 else if (opnd
== IA64_OPND_TGT25b
)
4855 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
4856 else if (opnd
== IA64_OPND_TGT25c
)
4857 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
4858 else if (opnd
== IA64_OPND_TGT64
)
4859 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
4863 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4864 fix
->opnd
= idesc
->operands
[index
];
4867 ++CURR_SLOT
.num_fixups
;
4870 case IA64_OPND_TAG13
:
4871 case IA64_OPND_TAG13b
:
4878 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4879 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
4880 fix
->opnd
= idesc
->operands
[index
];
4883 ++CURR_SLOT
.num_fixups
;
4903 memset (e
, 0, sizeof (*e
));
4906 if (*input_line_pointer
!= '}')
4908 sep
= *input_line_pointer
++;
4912 if (!md
.manual_bundling
)
4913 as_warn ("Found '}' when manual bundling is off");
4915 CURR_SLOT
.manual_bundling_off
= 1;
4916 md
.manual_bundling
= 0;
4922 /* Returns the next entry in the opcode table that matches the one in
4923 IDESC, and frees the entry in IDESC. If no matching entry is
4924 found, NULL is returned instead. */
4926 static struct ia64_opcode
*
4927 get_next_opcode (struct ia64_opcode
*idesc
)
4929 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
4930 ia64_free_opcode (idesc
);
4934 /* Parse the operands for the opcode and find the opcode variant that
4935 matches the specified operands, or NULL if no match is possible. */
4936 static struct ia64_opcode
*
4937 parse_operands (idesc
)
4938 struct ia64_opcode
*idesc
;
4940 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
4942 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
4944 char *first_arg
= 0, *end
, *saved_input_pointer
;
4947 assert (strlen (idesc
->name
) <= 128);
4949 strcpy (mnemonic
, idesc
->name
);
4950 if (idesc
->operands
[2] == IA64_OPND_SOF
)
4952 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4953 can't parse the first operand until we have parsed the
4954 remaining operands of the "alloc" instruction. */
4956 first_arg
= input_line_pointer
;
4957 end
= strchr (input_line_pointer
, '=');
4960 as_bad ("Expected separator `='");
4963 input_line_pointer
= end
+ 1;
4968 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
4970 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
4971 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
4976 if (sep
!= '=' && sep
!= ',')
4981 if (num_outputs
> 0)
4982 as_bad ("Duplicate equal sign (=) in instruction");
4984 num_outputs
= i
+ 1;
4989 as_bad ("Illegal operand separator `%c'", sep
);
4993 if (idesc
->operands
[2] == IA64_OPND_SOF
)
4995 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
4996 know (strcmp (idesc
->name
, "alloc") == 0);
4997 if (num_operands
== 5 /* first_arg not included in this count! */
4998 && CURR_SLOT
.opnd
[2].X_op
== O_constant
4999 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5000 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5001 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5003 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5004 CURR_SLOT
.opnd
[3].X_add_number
,
5005 CURR_SLOT
.opnd
[4].X_add_number
,
5006 CURR_SLOT
.opnd
[5].X_add_number
);
5008 /* now we can parse the first arg: */
5009 saved_input_pointer
= input_line_pointer
;
5010 input_line_pointer
= first_arg
;
5011 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5013 --num_outputs
; /* force error */
5014 input_line_pointer
= saved_input_pointer
;
5016 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5017 CURR_SLOT
.opnd
[3].X_add_number
5018 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5019 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5023 highest_unmatched_operand
= 0;
5024 expected_operand
= idesc
->operands
[0];
5025 for (; idesc
; idesc
= get_next_opcode (idesc
))
5027 if (num_outputs
!= idesc
->num_outputs
)
5028 continue; /* mismatch in # of outputs */
5030 CURR_SLOT
.num_fixups
= 0;
5031 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5032 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5035 if (i
!= num_operands
)
5037 if (i
> highest_unmatched_operand
)
5039 highest_unmatched_operand
= i
;
5040 expected_operand
= idesc
->operands
[i
];
5045 if (num_operands
< NELEMS (idesc
->operands
)
5046 && idesc
->operands
[num_operands
])
5047 continue; /* mismatch in number of arguments */
5053 if (expected_operand
)
5054 as_bad ("Operand %u of `%s' should be %s",
5055 highest_unmatched_operand
+ 1, mnemonic
,
5056 elf64_ia64_operands
[expected_operand
].desc
);
5058 as_bad ("Operand mismatch");
5065 build_insn (slot
, insnp
)
5069 const struct ia64_operand
*odesc
, *o2desc
;
5070 struct ia64_opcode
*idesc
= slot
->idesc
;
5071 bfd_signed_vma insn
, val
;
5075 insn
= idesc
->opcode
| slot
->qp_regno
;
5077 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5079 if (slot
->opnd
[i
].X_op
== O_register
5080 || slot
->opnd
[i
].X_op
== O_constant
5081 || slot
->opnd
[i
].X_op
== O_index
)
5082 val
= slot
->opnd
[i
].X_add_number
;
5083 else if (slot
->opnd
[i
].X_op
== O_big
)
5085 /* This must be the value 0x10000000000000000. */
5086 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5092 switch (idesc
->operands
[i
])
5094 case IA64_OPND_IMMU64
:
5095 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5096 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5097 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5098 | (((val
>> 63) & 0x1) << 36));
5101 case IA64_OPND_IMMU62
:
5102 val
&= 0x3fffffffffffffffULL
;
5103 if (val
!= slot
->opnd
[i
].X_add_number
)
5104 as_warn (_("Value truncated to 62 bits"));
5105 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5106 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5109 case IA64_OPND_TGT64
:
5111 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5112 insn
|= ((((val
>> 59) & 0x1) << 36)
5113 | (((val
>> 0) & 0xfffff) << 13));
5144 case IA64_OPND_R3_2
:
5145 case IA64_OPND_CPUID_R3
:
5146 case IA64_OPND_DBR_R3
:
5147 case IA64_OPND_DTR_R3
:
5148 case IA64_OPND_ITR_R3
:
5149 case IA64_OPND_IBR_R3
:
5151 case IA64_OPND_MSR_R3
:
5152 case IA64_OPND_PKR_R3
:
5153 case IA64_OPND_PMC_R3
:
5154 case IA64_OPND_PMD_R3
:
5155 case IA64_OPND_RR_R3
:
5163 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5164 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5166 as_bad_where (slot
->src_file
, slot
->src_line
,
5167 "Bad operand value: %s", err
);
5168 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5170 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5171 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5173 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5174 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5176 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5177 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5178 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5180 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5181 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5191 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5192 unsigned int manual_bundling
= 0;
5193 enum ia64_unit required_unit
, insn_unit
= 0;
5194 enum ia64_insn_type type
[3], insn_type
;
5195 unsigned int template, orig_template
;
5196 bfd_vma insn
[3] = {-1, -1, -1};
5197 struct ia64_opcode
*idesc
;
5198 int end_of_insn_group
= 0, user_template
= -1;
5199 int n
, i
, j
, first
, curr
;
5200 unw_rec_list
*ptr
, *prev
;
5201 bfd_vma t0
= 0, t1
= 0;
5202 struct label_fix
*lfix
;
5203 struct insn_fix
*ifix
;
5208 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5209 know (first
>= 0 & first
< NUM_SLOTS
);
5210 n
= MIN (3, md
.num_slots_in_use
);
5212 /* Determine template: user user_template if specified, best match
5215 if (md
.slot
[first
].user_template
>= 0)
5216 user_template
= template = md
.slot
[first
].user_template
;
5219 /* auto select appropriate template */
5220 memset (type
, 0, sizeof (type
));
5222 for (i
= 0; i
< n
; ++i
)
5224 type
[i
] = md
.slot
[curr
].idesc
->type
;
5225 curr
= (curr
+ 1) % NUM_SLOTS
;
5227 template = best_template
[type
[0]][type
[1]][type
[2]];
5230 /* initialize instructions with appropriate nops: */
5231 for (i
= 0; i
< 3; ++i
)
5232 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5236 /* now fill in slots with as many insns as possible: */
5238 idesc
= md
.slot
[curr
].idesc
;
5239 end_of_insn_group
= 0;
5240 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5242 /* Set the slot number for prologue/body records now as those
5243 refer to the current point, not the point after the
5244 instruction has been issued: */
5245 /* Don't try to delete prologue/body records here, as that will cause
5246 them to also be deleted from the master list of unwind records. */
5247 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5248 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5249 || ptr
->r
.type
== body
)
5250 ptr
->slot_number
= (unsigned long) f
+ i
;
5252 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5254 if (manual_bundling
&& i
!= 2)
5255 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5256 "`%s' must be last in bundle", idesc
->name
);
5260 if (idesc
->flags
& IA64_OPCODE_LAST
)
5262 int required_slot
, required_template
;
5264 /* If we need a stop bit after an M slot, our only choice is
5265 template 5 (M;;MI). If we need a stop bit after a B
5266 slot, our only choice is to place it at the end of the
5267 bundle, because the only available templates are MIB,
5268 MBB, BBB, MMB, and MFB. We don't handle anything other
5269 than M and B slots because these are the only kind of
5270 instructions that can have the IA64_OPCODE_LAST bit set. */
5271 required_template
= template;
5272 switch (idesc
->type
)
5276 required_template
= 5;
5284 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5285 "Internal error: don't know how to force %s to end"
5286 "of instruction group", idesc
->name
);
5290 if (manual_bundling
&& i
!= required_slot
)
5291 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5292 "`%s' must be last in instruction group",
5294 if (required_slot
< i
)
5295 /* Can't fit this instruction. */
5299 if (required_template
!= template)
5301 /* If we switch the template, we need to reset the NOPs
5302 after slot i. The slot-types of the instructions ahead
5303 of i never change, so we don't need to worry about
5304 changing NOPs in front of this slot. */
5305 for (j
= i
; j
< 3; ++j
)
5306 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5308 template = required_template
;
5310 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5312 if (manual_bundling_on
)
5313 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5314 "Label must be first in a bundle");
5315 /* This insn must go into the first slot of a bundle. */
5319 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5320 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5322 if (manual_bundling_on
)
5325 manual_bundling
= 1;
5327 break; /* need to start a new bundle */
5330 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5332 /* We need an instruction group boundary in the middle of a
5333 bundle. See if we can switch to an other template with
5334 an appropriate boundary. */
5336 orig_template
= template;
5337 if (i
== 1 && (user_template
== 4
5338 || (user_template
< 0
5339 && (ia64_templ_desc
[template].exec_unit
[0]
5343 end_of_insn_group
= 0;
5345 else if (i
== 2 && (user_template
== 0
5346 || (user_template
< 0
5347 && (ia64_templ_desc
[template].exec_unit
[1]
5349 /* This test makes sure we don't switch the template if
5350 the next instruction is one that needs to be first in
5351 an instruction group. Since all those instructions are
5352 in the M group, there is no way such an instruction can
5353 fit in this bundle even if we switch the template. The
5354 reason we have to check for this is that otherwise we
5355 may end up generating "MI;;I M.." which has the deadly
5356 effect that the second M instruction is no longer the
5357 first in the bundle! --davidm 99/12/16 */
5358 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5361 end_of_insn_group
= 0;
5363 else if (curr
!= first
)
5364 /* can't fit this insn */
5367 if (template != orig_template
)
5368 /* if we switch the template, we need to reset the NOPs
5369 after slot i. The slot-types of the instructions ahead
5370 of i never change, so we don't need to worry about
5371 changing NOPs in front of this slot. */
5372 for (j
= i
; j
< 3; ++j
)
5373 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5375 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5377 /* resolve dynamic opcodes such as "break" and "nop": */
5378 if (idesc
->type
== IA64_TYPE_DYN
)
5380 if ((strcmp (idesc
->name
, "nop") == 0)
5381 || (strcmp (idesc
->name
, "break") == 0))
5382 insn_unit
= required_unit
;
5383 else if (strcmp (idesc
->name
, "chk.s") == 0)
5385 insn_unit
= IA64_UNIT_M
;
5386 if (required_unit
== IA64_UNIT_I
)
5387 insn_unit
= IA64_UNIT_I
;
5390 as_fatal ("emit_one_bundle: unexpected dynamic op");
5392 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5393 ia64_free_opcode (idesc
);
5394 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5396 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5401 insn_type
= idesc
->type
;
5402 insn_unit
= IA64_UNIT_NIL
;
5406 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5407 insn_unit
= required_unit
;
5409 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5410 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5411 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5412 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5413 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5418 if (insn_unit
!= required_unit
)
5420 if (required_unit
== IA64_UNIT_L
5421 && insn_unit
== IA64_UNIT_I
5422 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5424 /* we got ourselves an MLX template but the current
5425 instruction isn't an X-unit, or an I-unit instruction
5426 that can go into the X slot of an MLX template. Duh. */
5427 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5429 as_bad_where (md
.slot
[curr
].src_file
,
5430 md
.slot
[curr
].src_line
,
5431 "`%s' can't go in X slot of "
5432 "MLX template", idesc
->name
);
5433 /* drop this insn so we don't livelock: */
5434 --md
.num_slots_in_use
;
5438 continue; /* try next slot */
5441 if (debug_type
== DEBUG_DWARF2
)
5445 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + 1*i
;
5446 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5449 build_insn (md
.slot
+ curr
, insn
+ i
);
5451 /* Set slot counts for non prologue/body unwind records. */
5452 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5453 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5454 && ptr
->r
.type
!= body
)
5455 ptr
->slot_number
= (unsigned long) f
+ i
;
5456 md
.slot
[curr
].unwind_record
= NULL
;
5457 unwind
.next_slot_number
= (unsigned long) f
+ i
+ ((i
== 2)?(0x10-2):1);
5459 if (required_unit
== IA64_UNIT_L
)
5462 /* skip one slot for long/X-unit instructions */
5465 --md
.num_slots_in_use
;
5467 /* now is a good time to fix up the labels for this insn: */
5468 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5470 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5471 symbol_set_frag (lfix
->sym
, frag_now
);
5474 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5476 ifix
= md
.slot
[curr
].fixup
+ j
;
5477 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 4,
5478 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5479 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5480 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5481 fix
->fx_file
= md
.slot
[curr
].src_file
;
5482 fix
->fx_line
= md
.slot
[curr
].src_line
;
5485 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5488 ia64_free_opcode (md
.slot
[curr
].idesc
);
5489 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5490 md
.slot
[curr
].user_template
= -1;
5492 if (manual_bundling_off
)
5494 manual_bundling
= 0;
5497 curr
= (curr
+ 1) % NUM_SLOTS
;
5498 idesc
= md
.slot
[curr
].idesc
;
5500 if (manual_bundling
)
5502 if (md
.num_slots_in_use
> 0)
5503 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5504 "`%s' does not fit into %s template",
5505 idesc
->name
, ia64_templ_desc
[template].name
);
5507 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5508 "Missing '}' at end of file");
5510 know (md
.num_slots_in_use
< NUM_SLOTS
);
5512 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5513 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5515 md_number_to_chars (f
+ 0, t0
, 8);
5516 md_number_to_chars (f
+ 8, t1
, 8);
5520 md_parse_option (c
, arg
)
5524 /* Switches from the Intel assembler. */
5528 if (strcmp (arg
, "ilp64") == 0
5529 || strcmp (arg
, "lp64") == 0
5530 || strcmp (arg
, "p64") == 0)
5532 md
.flags
|= EF_IA_64_ABI64
;
5534 else if (strcmp (arg
, "ilp32") == 0)
5536 md
.flags
&= ~EF_IA_64_ABI64
;
5538 else if (strcmp (arg
, "le") == 0)
5540 md
.flags
&= ~EF_IA_64_BE
;
5542 else if (strcmp (arg
, "be") == 0)
5544 md
.flags
|= EF_IA_64_BE
;
5551 if (strcmp (arg
, "so") == 0)
5553 /* Suppress signon message. */
5555 else if (strcmp (arg
, "pi") == 0)
5557 /* Reject privileged instructions. FIXME */
5559 else if (strcmp (arg
, "us") == 0)
5561 /* Allow union of signed and unsigned range. FIXME */
5563 else if (strcmp (arg
, "close_fcalls") == 0)
5565 /* Do not resolve global function calls. */
5572 /* temp[="prefix"] Insert temporary labels into the object file
5573 symbol table prefixed by "prefix".
5574 Default prefix is ":temp:".
5579 /* ??? Conflicts with gas' listing option. */
5580 /* indirect=<tgt> Assume unannotated indirect branches behavior
5581 according to <tgt> --
5582 exit: branch out from the current context (default)
5583 labels: all labels in context may be branch targets
5588 /* -X conflicts with an ignored option, use -x instead */
5590 if (!arg
|| strcmp (arg
, "explicit") == 0)
5592 /* set default mode to explicit */
5593 md
.default_explicit_mode
= 1;
5596 else if (strcmp (arg
, "auto") == 0)
5598 md
.default_explicit_mode
= 0;
5600 else if (strcmp (arg
, "debug") == 0)
5604 else if (strcmp (arg
, "debugx") == 0)
5606 md
.default_explicit_mode
= 1;
5611 as_bad (_("Unrecognized option '-x%s'"), arg
);
5616 /* nops Print nops statistics. */
5627 md_show_usage (stream
)
5632 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5633 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5634 -x | -xexplicit turn on dependency violation checking (default)\n\
5635 -xauto automagically remove dependency violations\n\
5636 -xdebug debug dependency violation checker\n"),
5641 match (int templ
, int type
, int slot
)
5643 enum ia64_unit unit
;
5646 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
5649 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
5651 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
5653 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
5654 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
5655 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
5656 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
5657 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
5658 default: result
= 0; break;
5663 /* This function is called once, at assembler startup time. It sets
5664 up all the tables, etc. that the MD part of the assembler will need
5665 that can be determined before arguments are parsed. */
5669 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
;
5674 md
.explicit_mode
= md
.default_explicit_mode
;
5676 bfd_set_section_alignment (stdoutput
, text_section
, 4);
5678 target_big_endian
= 0;
5679 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
5680 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
5681 &zero_address_frag
);
5683 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
5684 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
5685 &zero_address_frag
);
5687 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
5688 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
5689 &zero_address_frag
);
5691 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
5692 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
5693 &zero_address_frag
);
5695 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
5696 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
5697 &zero_address_frag
);
5699 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
5700 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
5701 &zero_address_frag
);
5703 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
5704 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
5705 &zero_address_frag
);
5707 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
5708 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
5709 &zero_address_frag
);
5711 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
5712 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
5713 &zero_address_frag
);
5715 /* compute the table of best templates: */
5716 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
5717 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
5718 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
5721 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
5724 if (match (t
, i
, 0))
5726 if (match (t
, j
, 1))
5728 if (match (t
, k
, 2))
5733 else if (match (t
, j
, 2))
5738 else if (match (t
, i
, 1))
5740 if (match (t
, j
, 2))
5745 else if (match (t
, i
, 2))
5748 if (goodness
> best
)
5751 best_template
[i
][j
][k
] = t
;
5756 for (i
= 0; i
< NUM_SLOTS
; ++i
)
5757 md
.slot
[i
].user_template
= -1;
5759 md
.pseudo_hash
= hash_new ();
5760 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
5762 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
5763 (void *) (pseudo_opcode
+ i
));
5765 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5766 pseudo_opcode
[i
].name
, err
);
5769 md
.reg_hash
= hash_new ();
5770 md
.dynreg_hash
= hash_new ();
5771 md
.const_hash
= hash_new ();
5772 md
.entry_hash
= hash_new ();
5774 /* general registers: */
5777 for (i
= 0; i
< total
; ++i
)
5779 sprintf (name
, "r%d", i
- REG_GR
);
5780 md
.regsym
[i
] = declare_register (name
, i
);
5783 /* floating point registers: */
5785 for (; i
< total
; ++i
)
5787 sprintf (name
, "f%d", i
- REG_FR
);
5788 md
.regsym
[i
] = declare_register (name
, i
);
5791 /* application registers: */
5794 for (; i
< total
; ++i
)
5796 sprintf (name
, "ar%d", i
- REG_AR
);
5797 md
.regsym
[i
] = declare_register (name
, i
);
5800 /* control registers: */
5803 for (; i
< total
; ++i
)
5805 sprintf (name
, "cr%d", i
- REG_CR
);
5806 md
.regsym
[i
] = declare_register (name
, i
);
5809 /* predicate registers: */
5811 for (; i
< total
; ++i
)
5813 sprintf (name
, "p%d", i
- REG_P
);
5814 md
.regsym
[i
] = declare_register (name
, i
);
5817 /* branch registers: */
5819 for (; i
< total
; ++i
)
5821 sprintf (name
, "b%d", i
- REG_BR
);
5822 md
.regsym
[i
] = declare_register (name
, i
);
5825 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
5826 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
5827 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
5828 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
5829 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
5830 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
5831 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
5833 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
5835 regnum
= indirect_reg
[i
].regnum
;
5836 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
5839 /* define synonyms for application registers: */
5840 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
5841 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
5842 REG_AR
+ ar
[i
- REG_AR
].regnum
);
5844 /* define synonyms for control registers: */
5845 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
5846 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
5847 REG_CR
+ cr
[i
- REG_CR
].regnum
);
5849 declare_register ("gp", REG_GR
+ 1);
5850 declare_register ("sp", REG_GR
+ 12);
5851 declare_register ("rp", REG_BR
+ 0);
5853 /* pseudo-registers used to specify unwind info: */
5854 declare_register ("psp", REG_PSP
);
5856 declare_register_set ("ret", 4, REG_GR
+ 8);
5857 declare_register_set ("farg", 8, REG_FR
+ 8);
5858 declare_register_set ("fret", 8, REG_FR
+ 8);
5860 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
5862 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
5863 (PTR
) (const_bits
+ i
));
5865 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5869 /* Default to 64-bit mode. */
5870 md
.flags
= EF_IA_64_ABI64
;
5872 md
.mem_offset
.hint
= 0;
5875 md
.entry_labels
= NULL
;
5879 ia64_end_of_source ()
5881 /* terminate insn group upon reaching end of file: */
5882 insn_group_break (1, 0, 0);
5884 /* emits slots we haven't written yet: */
5885 ia64_flush_insns ();
5887 bfd_set_private_flags (stdoutput
, md
.flags
);
5889 if (debug_type
== DEBUG_DWARF2
)
5892 md
.mem_offset
.hint
= 0;
5898 md
.qp
.X_op
= O_absent
;
5900 if (ignore_input ())
5903 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
5905 if (md
.detect_dv
&& !md
.explicit_mode
)
5906 as_warn (_("Explicit stops are ignored in auto mode"));
5908 insn_group_break (1, 0, 0);
5913 ia64_unrecognized_line (ch
)
5919 expression (&md
.qp
);
5920 if (*input_line_pointer
++ != ')')
5922 as_bad ("Expected ')'");
5925 if (md
.qp
.X_op
!= O_register
)
5927 as_bad ("Qualifying predicate expected");
5930 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
5932 as_bad ("Predicate register expected");
5938 if (md
.manual_bundling
)
5939 as_warn ("Found '{' when manual bundling is already turned on");
5941 CURR_SLOT
.manual_bundling_on
= 1;
5942 md
.manual_bundling
= 1;
5944 /* bundling is only acceptable in explicit mode
5945 or when in default automatic mode */
5946 if (md
.detect_dv
&& !md
.explicit_mode
)
5948 if (!md
.mode_explicitly_set
5949 && !md
.default_explicit_mode
)
5952 as_warn (_("Found '{' after explicit switch to automatic mode"));
5957 if (!md
.manual_bundling
)
5958 as_warn ("Found '}' when manual bundling is off");
5960 PREV_SLOT
.manual_bundling_off
= 1;
5961 md
.manual_bundling
= 0;
5963 /* switch back to automatic mode, if applicable */
5966 && !md
.mode_explicitly_set
5967 && !md
.default_explicit_mode
)
5970 /* Allow '{' to follow on the same line. We also allow ";;", but that
5971 happens automatically because ';' is an end of line marker. */
5973 if (input_line_pointer
[0] == '{')
5975 input_line_pointer
++;
5976 return ia64_unrecognized_line ('{');
5979 demand_empty_rest_of_line ();
5985 return 0; /* not a valid line */
5989 ia64_frob_label (sym
)
5992 struct label_fix
*fix
;
5994 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
5996 md
.last_text_seg
= now_seg
;
5997 fix
= obstack_alloc (¬es
, sizeof (*fix
));
5999 fix
->next
= CURR_SLOT
.label_fixups
;
6000 CURR_SLOT
.label_fixups
= fix
;
6002 /* keep track of how many code entry points we've seen */
6003 if (md
.path
== md
.maxpaths
)
6006 md
.entry_labels
= (const char **)
6007 xrealloc ((void *)md
.entry_labels
, md
.maxpaths
* sizeof (char *));
6009 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6014 ia64_flush_pending_output ()
6016 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6018 /* ??? This causes many unnecessary stop bits to be emitted.
6019 Unfortunately, it isn't clear if it is safe to remove this. */
6020 insn_group_break (1, 0, 0);
6021 ia64_flush_insns ();
6025 /* Do ia64-specific expression optimization. All that's done here is
6026 to transform index expressions that are either due to the indexing
6027 of rotating registers or due to the indexing of indirect register
6030 ia64_optimize_expr (l
, op
, r
)
6039 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6041 num_regs
= (l
->X_add_number
>> 16);
6042 if ((unsigned) r
->X_add_number
>= num_regs
)
6045 as_bad ("No current frame");
6047 as_bad ("Index out of range 0..%u", num_regs
- 1);
6048 r
->X_add_number
= 0;
6050 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6053 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6055 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6056 || l
->X_add_number
== IND_MEM
)
6058 as_bad ("Indirect register set name expected");
6059 l
->X_add_number
= IND_CPUID
;
6062 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6063 l
->X_add_number
= r
->X_add_number
;
6071 ia64_parse_name (name
, e
)
6075 struct const_desc
*cdesc
;
6076 struct dynreg
*dr
= 0;
6077 unsigned int regnum
;
6081 /* first see if NAME is a known register name: */
6082 sym
= hash_find (md
.reg_hash
, name
);
6085 e
->X_op
= O_register
;
6086 e
->X_add_number
= S_GET_VALUE (sym
);
6090 cdesc
= hash_find (md
.const_hash
, name
);
6093 e
->X_op
= O_constant
;
6094 e
->X_add_number
= cdesc
->value
;
6098 /* check for inN, locN, or outN: */
6102 if (name
[1] == 'n' && isdigit (name
[2]))
6110 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6118 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6131 /* the name is inN, locN, or outN; parse the register number: */
6132 regnum
= strtoul (name
, &end
, 10);
6133 if (end
> name
&& *end
== '\0')
6135 if ((unsigned) regnum
>= dr
->num_regs
)
6138 as_bad ("No current frame");
6140 as_bad ("Register number out of range 0..%u", dr
->num_regs
-1);
6143 e
->X_op
= O_register
;
6144 e
->X_add_number
= dr
->base
+ regnum
;
6149 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6151 /* We've got ourselves the name of a rotating register set.
6152 Store the base register number in the low 16 bits of
6153 X_add_number and the size of the register set in the top 16
6155 e
->X_op
= O_register
;
6156 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6162 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6165 ia64_canonicalize_symbol_name (name
)
6168 size_t len
= strlen(name
);
6169 if (len
> 1 && name
[len
-1] == '#')
6175 is_conditional_branch (idesc
)
6176 struct ia64_opcode
*idesc
;
6178 return (strncmp (idesc
->name
, "br", 2) == 0
6179 && (strcmp (idesc
->name
, "br") == 0
6180 || strncmp (idesc
->name
, "br.cond", 7) == 0
6181 || strncmp (idesc
->name
, "br.call", 7) == 0
6182 || strncmp (idesc
->name
, "br.ret", 6) == 0
6183 || strcmp (idesc
->name
, "brl") == 0
6184 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6185 || strncmp (idesc
->name
, "brl.call", 7) == 0
6186 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6189 /* Return whether the given opcode is a taken branch. If there's any doubt,
6192 is_taken_branch (idesc
)
6193 struct ia64_opcode
*idesc
;
6195 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6196 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6199 /* Return whether the given opcode is an interruption or rfi. If there's any
6200 doubt, returns zero */
6202 is_interruption_or_rfi (idesc
)
6203 struct ia64_opcode
*idesc
;
6205 if (strcmp (idesc
->name
, "rfi") == 0)
6210 /* Returns the index of the given dependency in the opcode's list of chks, or
6211 -1 if there is no dependency. */
6213 depends_on (depind
, idesc
)
6215 struct ia64_opcode
*idesc
;
6218 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6219 for (i
= 0;i
< dep
->nchks
; i
++)
6221 if (depind
== DEP(dep
->chks
[i
]))
6227 /* Determine a set of specific resources used for a particular resource
6228 class. Returns the number of specific resources identified For those
6229 cases which are not determinable statically, the resource returned is
6232 Meanings of value in 'NOTE':
6233 1) only read/write when the register number is explicitly encoded in the
6235 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6236 accesses CFM when qualifying predicate is in the rotating region.
6237 3) general register value is used to specify an indirect register; not
6238 determinable statically.
6239 4) only read the given resource when bits 7:0 of the indirect index
6240 register value does not match the register number of the resource; not
6241 determinable statically.
6242 5) all rules are implementation specific.
6243 6) only when both the index specified by the reader and the index specified
6244 by the writer have the same value in bits 63:61; not determinable
6246 7) only access the specified resource when the corresponding mask bit is
6248 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6249 only read when these insns reference FR2-31
6250 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6251 written when these insns write FR32-127
6252 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6254 11) The target predicates are written independently of PR[qp], but source
6255 registers are only read if PR[qp] is true. Since the state of PR[qp]
6256 cannot statically be determined, all source registers are marked used.
6257 12) This insn only reads the specified predicate register when that
6258 register is the PR[qp].
6259 13) This reference to ld-c only applies to teh GR whose value is loaded
6260 with data returned from memory, not the post-incremented address register.
6261 14) The RSE resource includes the implementation-specific RSE internal
6262 state resources. At least one (and possibly more) of these resources are
6263 read by each instruction listed in IC:rse-readers. At least one (and
6264 possibly more) of these resources are written by each insn listed in
6266 15+16) Represents reserved instructions, which the assembler does not
6269 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6270 this code; there are no dependency violations based on memory access.
6274 #define MAX_SPECS 256
6279 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6280 const struct ia64_dependency
*dep
;
6281 struct ia64_opcode
*idesc
;
6282 int type
; /* is this a DV chk or a DV reg? */
6283 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6284 int note
; /* resource note for this insn's usage */
6285 int path
; /* which execution path to examine */
6292 if (dep
->mode
== IA64_DV_WAW
6293 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6294 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6297 /* template for any resources we identify */
6298 tmpl
.dependency
= dep
;
6300 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6301 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6302 tmpl
.link_to_qp_branch
= 1;
6303 tmpl
.mem_offset
.hint
= 0;
6308 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6309 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6310 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6312 /* we don't need to track these */
6313 if (dep
->semantics
== IA64_DVS_NONE
)
6316 switch (dep
->specifier
)
6321 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6323 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6324 if (regno
>= 0 && regno
<= 7)
6326 specs
[count
] = tmpl
;
6327 specs
[count
++].index
= regno
;
6335 specs
[count
] = tmpl
;
6336 specs
[count
++].index
= i
;
6345 case IA64_RS_AR_UNAT
:
6346 /* This is a mov =AR or mov AR= instruction. */
6347 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6349 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6350 if (regno
== AR_UNAT
)
6352 specs
[count
++] = tmpl
;
6357 /* This is a spill/fill, or other instruction that modifies the
6360 /* Unless we can determine the specific bits used, mark the whole
6361 thing; bits 8:3 of the memory address indicate the bit used in
6362 UNAT. The .mem.offset hint may be used to eliminate a small
6363 subset of conflicts. */
6364 specs
[count
] = tmpl
;
6365 if (md
.mem_offset
.hint
)
6368 fprintf (stderr
, " Using hint for spill/fill\n");
6369 /* the index isn't actually used, just set it to something
6370 approximating the bit index */
6371 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6372 specs
[count
].mem_offset
.hint
= 1;
6373 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6374 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6378 specs
[count
++].specific
= 0;
6386 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6388 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6389 if ((regno
>= 8 && regno
<= 15)
6390 || (regno
>= 20 && regno
<= 23)
6391 || (regno
>= 31 && regno
<= 39)
6392 || (regno
>= 41 && regno
<= 47)
6393 || (regno
>= 67 && regno
<= 111))
6395 specs
[count
] = tmpl
;
6396 specs
[count
++].index
= regno
;
6409 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6411 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6412 if ((regno
>= 48 && regno
<= 63)
6413 || (regno
>= 112 && regno
<= 127))
6415 specs
[count
] = tmpl
;
6416 specs
[count
++].index
= regno
;
6422 for (i
=48;i
< 64;i
++)
6424 specs
[count
] = tmpl
;
6425 specs
[count
++].index
= i
;
6427 for (i
=112;i
< 128;i
++)
6429 specs
[count
] = tmpl
;
6430 specs
[count
++].index
= i
;
6448 for (i
=0;i
< idesc
->num_outputs
;i
++)
6449 if (idesc
->operands
[i
] == IA64_OPND_B1
6450 || idesc
->operands
[i
] == IA64_OPND_B2
)
6452 specs
[count
] = tmpl
;
6453 specs
[count
++].index
=
6454 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6459 for (i
= idesc
->num_outputs
;i
< NELEMS(idesc
->operands
);i
++)
6460 if (idesc
->operands
[i
] == IA64_OPND_B1
6461 || idesc
->operands
[i
] == IA64_OPND_B2
)
6463 specs
[count
] = tmpl
;
6464 specs
[count
++].index
=
6465 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6471 case IA64_RS_CPUID
: /* four or more registers */
6474 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
6476 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6477 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6480 specs
[count
] = tmpl
;
6481 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6485 specs
[count
] = tmpl
;
6486 specs
[count
++].specific
= 0;
6496 case IA64_RS_DBR
: /* four or more registers */
6499 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
6501 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6502 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6505 specs
[count
] = tmpl
;
6506 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6510 specs
[count
] = tmpl
;
6511 specs
[count
++].specific
= 0;
6515 else if (note
== 0 && !rsrc_write
)
6517 specs
[count
] = tmpl
;
6518 specs
[count
++].specific
= 0;
6526 case IA64_RS_IBR
: /* four or more registers */
6529 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
6531 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6532 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6535 specs
[count
] = tmpl
;
6536 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6540 specs
[count
] = tmpl
;
6541 specs
[count
++].specific
= 0;
6554 /* These are implementation specific. Force all references to
6555 conflict with all other references. */
6556 specs
[count
] = tmpl
;
6557 specs
[count
++].specific
= 0;
6565 case IA64_RS_PKR
: /* 16 or more registers */
6566 if (note
== 3 || note
== 4)
6568 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
6570 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6571 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6576 specs
[count
] = tmpl
;
6577 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6579 else for (i
=0;i
< NELEMS(gr_values
);i
++)
6581 /* uses all registers *except* the one in R3 */
6582 if (i
!= (gr_values
[regno
].value
& 0xFF))
6584 specs
[count
] = tmpl
;
6585 specs
[count
++].index
= i
;
6591 specs
[count
] = tmpl
;
6592 specs
[count
++].specific
= 0;
6599 specs
[count
] = tmpl
;
6600 specs
[count
++].specific
= 0;
6604 case IA64_RS_PMC
: /* four or more registers */
6607 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
6608 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
6611 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
6613 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
6614 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6617 specs
[count
] = tmpl
;
6618 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6622 specs
[count
] = tmpl
;
6623 specs
[count
++].specific
= 0;
6633 case IA64_RS_PMD
: /* four or more registers */
6636 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
6638 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6639 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6642 specs
[count
] = tmpl
;
6643 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6647 specs
[count
] = tmpl
;
6648 specs
[count
++].specific
= 0;
6658 case IA64_RS_RR
: /* eight registers */
6661 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
6663 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6664 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6667 specs
[count
] = tmpl
;
6668 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
6672 specs
[count
] = tmpl
;
6673 specs
[count
++].specific
= 0;
6677 else if (note
== 0 && !rsrc_write
)
6679 specs
[count
] = tmpl
;
6680 specs
[count
++].specific
= 0;
6688 case IA64_RS_CR_IRR
:
6691 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6692 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
6694 && idesc
->operands
[1] == IA64_OPND_CR3
6699 specs
[count
] = tmpl
;
6700 specs
[count
++].index
= CR_IRR0
+ i
;
6706 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6707 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6709 && regno
<= CR_IRR3
)
6711 specs
[count
] = tmpl
;
6712 specs
[count
++].index
= regno
;
6721 case IA64_RS_CR_LRR
:
6728 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6729 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6730 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
6732 specs
[count
] = tmpl
;
6733 specs
[count
++].index
= regno
;
6741 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
6743 specs
[count
] = tmpl
;
6744 specs
[count
++].index
=
6745 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6760 else if (rsrc_write
)
6762 if (dep
->specifier
== IA64_RS_FRb
6763 && idesc
->operands
[0] == IA64_OPND_F1
)
6765 specs
[count
] = tmpl
;
6766 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
6771 for (i
=idesc
->num_outputs
;i
< NELEMS(idesc
->operands
);i
++)
6773 if (idesc
->operands
[i
] == IA64_OPND_F2
6774 || idesc
->operands
[i
] == IA64_OPND_F3
6775 || idesc
->operands
[i
] == IA64_OPND_F4
)
6777 specs
[count
] = tmpl
;
6778 specs
[count
++].index
=
6779 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
6788 /* This reference applies only to the GR whose value is loaded with
6789 data returned from memory */
6790 specs
[count
] = tmpl
;
6791 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
6797 for (i
=0;i
< idesc
->num_outputs
;i
++)
6799 if (idesc
->operands
[i
] == IA64_OPND_R1
6800 || idesc
->operands
[i
] == IA64_OPND_R2
6801 || idesc
->operands
[i
] == IA64_OPND_R3
)
6803 specs
[count
] = tmpl
;
6804 specs
[count
++].index
=
6805 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6811 /* Look for anything that reads a GR */
6812 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
6814 if (idesc
->operands
[i
] == IA64_OPND_MR3
6815 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
6816 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
6817 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
6818 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
6819 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
6820 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
6821 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
6822 || idesc
->operands
[i
] == IA64_OPND_RR_R3
6823 || ((i
>= idesc
->num_outputs
)
6824 && (idesc
->operands
[i
] == IA64_OPND_R1
6825 || idesc
->operands
[i
] == IA64_OPND_R2
6826 || idesc
->operands
[i
] == IA64_OPND_R3
)))
6828 specs
[count
] = tmpl
;
6829 specs
[count
++].index
=
6830 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6844 if (idesc
->operands
[0] == IA64_OPND_PR_ROT
)
6846 for (i
=16;i
< 63;i
++)
6848 specs
[count
] = tmpl
;
6849 specs
[count
++].index
= i
;
6854 for (i
=1;i
< 63;i
++)
6856 specs
[count
] = tmpl
;
6857 specs
[count
++].index
= i
;
6864 /* mark only those registers indicated by the mask */
6866 && idesc
->operands
[0] == IA64_OPND_PR
)
6868 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
6869 if (mask
& ((valueT
)1<<16))
6870 mask
|= ~(valueT
)0xffff;
6871 for (i
=1;i
< 63;i
++)
6873 if (mask
& ((valueT
)1<<i
))
6875 specs
[count
] = tmpl
;
6876 specs
[count
++].index
= i
;
6881 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
6883 for (i
=16;i
< 63;i
++)
6885 specs
[count
] = tmpl
;
6886 specs
[count
++].index
= i
;
6894 else if (note
== 11) /* note 11 implies note 1 as well */
6898 for (i
=0;i
< idesc
->num_outputs
;i
++)
6900 if (idesc
->operands
[i
] == IA64_OPND_P1
6901 || idesc
->operands
[i
] == IA64_OPND_P2
)
6903 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
6906 specs
[count
] = tmpl
;
6907 specs
[count
++].index
= regno
;
6917 else if (note
== 12)
6919 if (CURR_SLOT
.qp_regno
!= 0)
6921 specs
[count
] = tmpl
;
6922 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
6929 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
6930 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
6931 if ((idesc
->operands
[0] == IA64_OPND_P1
6932 || idesc
->operands
[0] == IA64_OPND_P2
)
6933 && p1
!= 0 && p1
!= 63)
6935 specs
[count
] = tmpl
;
6936 specs
[count
++].index
= p1
;
6938 if ((idesc
->operands
[1] == IA64_OPND_P1
6939 || idesc
->operands
[1] == IA64_OPND_P2
)
6940 && p2
!= 0 && p2
!= 63)
6942 specs
[count
] = tmpl
;
6943 specs
[count
++].index
= p2
;
6948 if (CURR_SLOT
.qp_regno
!= 0)
6950 specs
[count
] = tmpl
;
6951 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
6953 if (idesc
->operands
[1] == IA64_OPND_PR
)
6955 for (i
=1;i
< 63;i
++)
6957 specs
[count
] = tmpl
;
6958 specs
[count
++].index
= i
;
6970 /* Verify that the instruction is using the PSR bit indicated in
6974 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
6976 if (dep
->regindex
< 6)
6978 specs
[count
++] = tmpl
;
6981 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
6983 if (dep
->regindex
< 32
6984 || dep
->regindex
== 35
6985 || dep
->regindex
== 36
6986 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
6988 specs
[count
++] = tmpl
;
6991 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
6993 if (dep
->regindex
< 32
6994 || dep
->regindex
== 35
6995 || dep
->regindex
== 36
6996 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
6998 specs
[count
++] = tmpl
;
7003 /* Several PSR bits have very specific dependencies. */
7004 switch (dep
->regindex
)
7007 specs
[count
++] = tmpl
;
7012 specs
[count
++] = tmpl
;
7016 /* Only certain CR accesses use PSR.ic */
7017 if (idesc
->operands
[0] == IA64_OPND_CR3
7018 || idesc
->operands
[1] == IA64_OPND_CR3
)
7021 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7024 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7039 specs
[count
++] = tmpl
;
7048 specs
[count
++] = tmpl
;
7052 /* Only some AR accesses use cpl */
7053 if (idesc
->operands
[0] == IA64_OPND_AR3
7054 || idesc
->operands
[1] == IA64_OPND_AR3
)
7057 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7060 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7067 && regno
<= AR_K7
))))
7069 specs
[count
++] = tmpl
;
7074 specs
[count
++] = tmpl
;
7084 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7086 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7092 if (mask
& ((valueT
)1<<dep
->regindex
))
7094 specs
[count
++] = tmpl
;
7099 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7100 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7101 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7102 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7104 if (idesc
->operands
[i
] == IA64_OPND_F1
7105 || idesc
->operands
[i
] == IA64_OPND_F2
7106 || idesc
->operands
[i
] == IA64_OPND_F3
7107 || idesc
->operands
[i
] == IA64_OPND_F4
)
7109 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7110 if (reg
>= min
&& reg
<= max
)
7112 specs
[count
++] = tmpl
;
7119 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7120 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7121 /* mfh is read on writes to FR32-127; mfl is read on writes to
7123 for (i
=0;i
< idesc
->num_outputs
;i
++)
7125 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7127 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7128 if (reg
>= min
&& reg
<= max
)
7130 specs
[count
++] = tmpl
;
7135 else if (note
== 10)
7137 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7139 if (idesc
->operands
[i
] == IA64_OPND_R1
7140 || idesc
->operands
[i
] == IA64_OPND_R2
7141 || idesc
->operands
[i
] == IA64_OPND_R3
)
7143 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7144 if (regno
>= 16 && regno
<= 31)
7146 specs
[count
++] = tmpl
;
7157 case IA64_RS_AR_FPSR
:
7158 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7160 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7161 if (regno
== AR_FPSR
)
7163 specs
[count
++] = tmpl
;
7168 specs
[count
++] = tmpl
;
7173 /* Handle all AR[REG] resources */
7174 if (note
== 0 || note
== 1)
7176 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7177 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7178 && regno
== dep
->regindex
)
7180 specs
[count
++] = tmpl
;
7182 /* other AR[REG] resources may be affected by AR accesses */
7183 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7186 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7187 switch (dep
->regindex
)
7193 if (regno
== AR_BSPSTORE
)
7195 specs
[count
++] = tmpl
;
7199 (regno
== AR_BSPSTORE
7200 || regno
== AR_RNAT
))
7202 specs
[count
++] = tmpl
;
7207 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7210 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7211 switch (dep
->regindex
)
7216 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7218 specs
[count
++] = tmpl
;
7225 specs
[count
++] = tmpl
;
7235 /* Handle all CR[REG] resources */
7236 if (note
== 0 || note
== 1)
7238 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7240 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7241 if (regno
== dep
->regindex
)
7243 specs
[count
++] = tmpl
;
7245 else if (!rsrc_write
)
7247 /* Reads from CR[IVR] affect other resources. */
7248 if (regno
== CR_IVR
)
7250 if ((dep
->regindex
>= CR_IRR0
7251 && dep
->regindex
<= CR_IRR3
)
7252 || dep
->regindex
== CR_TPR
)
7254 specs
[count
++] = tmpl
;
7261 specs
[count
++] = tmpl
;
7270 case IA64_RS_INSERVICE
:
7271 /* look for write of EOI (67) or read of IVR (65) */
7272 if ((idesc
->operands
[0] == IA64_OPND_CR3
7273 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7274 || (idesc
->operands
[1] == IA64_OPND_CR3
7275 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7277 specs
[count
++] = tmpl
;
7284 specs
[count
++] = tmpl
;
7295 specs
[count
++] = tmpl
;
7299 /* Check if any of the registers accessed are in the rotating region.
7300 mov to/from pr accesses CFM only when qp_regno is in the rotating
7302 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7304 if (idesc
->operands
[i
] == IA64_OPND_R1
7305 || idesc
->operands
[i
] == IA64_OPND_R2
7306 || idesc
->operands
[i
] == IA64_OPND_R3
)
7308 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7309 /* Assumes that md.rot.num_regs is always valid */
7310 if (md
.rot
.num_regs
> 0
7312 && num
< 31 + md
.rot
.num_regs
)
7314 specs
[count
] = tmpl
;
7315 specs
[count
++].specific
= 0;
7318 else if (idesc
->operands
[i
] == IA64_OPND_F1
7319 || idesc
->operands
[i
] == IA64_OPND_F2
7320 || idesc
->operands
[i
] == IA64_OPND_F3
7321 || idesc
->operands
[i
] == IA64_OPND_F4
)
7323 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7326 specs
[count
] = tmpl
;
7327 specs
[count
++].specific
= 0;
7330 else if (idesc
->operands
[i
] == IA64_OPND_P1
7331 || idesc
->operands
[i
] == IA64_OPND_P2
)
7333 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7336 specs
[count
] = tmpl
;
7337 specs
[count
++].specific
= 0;
7341 if (CURR_SLOT
.qp_regno
> 15)
7343 specs
[count
] = tmpl
;
7344 specs
[count
++].specific
= 0;
7352 specs
[count
++] = tmpl
;
7354 else if (note
== 11)
7356 if ((idesc
->operands
[0] == IA64_OPND_P1
7357 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
7358 || (idesc
->operands
[1] == IA64_OPND_P2
7359 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
7361 specs
[count
++] = tmpl
;
7364 else if (note
== 12)
7366 if (CURR_SLOT
.qp_regno
== 63)
7368 specs
[count
++] = tmpl
;
7374 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
7375 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7376 if (mask
& ((valueT
)1<<63))
7378 specs
[count
++] = tmpl
;
7385 for (i
=0;i
< idesc
->num_outputs
;i
++)
7386 if ((idesc
->operands
[i
] == IA64_OPND_P1
7387 || idesc
->operands
[i
] == IA64_OPND_P2
)
7388 && CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
== 63)
7390 specs
[count
++] = tmpl
;
7395 if (CURR_SLOT
.qp_regno
== 63)
7397 specs
[count
++] = tmpl
;
7408 /* FIXME we can identify some individual RSE written resources, but RSE
7409 read resources have not yet been completely identified, so for now
7410 treat RSE as a single resource */
7411 if (strncmp (idesc
->name
, "mov", 3) == 0)
7415 if (idesc
->operands
[0] == IA64_OPND_AR3
7416 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
7418 specs
[count
] = tmpl
;
7419 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7424 if (idesc
->operands
[0] == IA64_OPND_AR3
)
7426 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
7427 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
7429 specs
[count
++] = tmpl
;
7432 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7434 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
7435 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
7436 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
7438 specs
[count
++] = tmpl
;
7445 specs
[count
++] = tmpl
;
7450 /* FIXME -- do any of these need to be non-specific? */
7451 specs
[count
++] = tmpl
;
7455 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
7462 /* Clear branch flags on marked resources. This breaks the link between the
7463 QP of the marking instruction and a subsequent branch on the same QP.
7466 clear_qp_branch_flag (mask
)
7470 for (i
= 0;i
< regdepslen
;i
++)
7472 valueT bit
= ((valueT
)1 << regdeps
[i
].qp_regno
);
7473 if ((bit
& mask
) != 0)
7475 regdeps
[i
].link_to_qp_branch
= 0;
7480 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7482 Any changes to a PR clears the mutex relations which include that PR.
7485 clear_qp_mutex (mask
)
7491 while (i
< qp_mutexeslen
)
7493 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
7497 fprintf (stderr
, " Clearing mutex relation");
7498 print_prmask (qp_mutexes
[i
].prmask
);
7499 fprintf (stderr
, "\n");
7501 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
7508 /* Clear implies relations which contain PRs in the given masks.
7509 P1_MASK indicates the source of the implies relation, while P2_MASK
7510 indicates the implied PR.
7513 clear_qp_implies (p1_mask
, p2_mask
)
7520 while (i
< qp_implieslen
)
7522 if ((((valueT
)1 << qp_implies
[i
].p1
) & p1_mask
) != 0
7523 || (((valueT
)1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
7526 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
7527 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
7528 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
7535 /* add the PRs specified to the list of implied relations */
7537 add_qp_imply (p1
, p2
)
7544 /* p0 is not meaningful here */
7545 if (p1
== 0 || p2
== 0)
7551 /* if it exists already, ignore it */
7552 for (i
=0;i
< qp_implieslen
;i
++)
7554 if (qp_implies
[i
].p1
== p1
7555 && qp_implies
[i
].p2
== p2
7556 && qp_implies
[i
].path
== md
.path
7557 && !qp_implies
[i
].p2_branched
)
7561 if (qp_implieslen
== qp_impliestotlen
)
7563 qp_impliestotlen
+= 20;
7564 qp_implies
= (struct qp_imply
*)
7565 xrealloc ((void *)qp_implies
,
7566 qp_impliestotlen
* sizeof (struct qp_imply
));
7569 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
7570 qp_implies
[qp_implieslen
].p1
= p1
;
7571 qp_implies
[qp_implieslen
].p2
= p2
;
7572 qp_implies
[qp_implieslen
].path
= md
.path
;
7573 qp_implies
[qp_implieslen
++].p2_branched
= 0;
7575 /* Add in the implied transitive relations; for everything that p2 implies,
7576 make p1 imply that, too; for everything that implies p1, make it imply p2
7578 for (i
=0;i
< qp_implieslen
;i
++)
7580 if (qp_implies
[i
].p1
== p2
)
7581 add_qp_imply (p1
, qp_implies
[i
].p2
);
7582 if (qp_implies
[i
].p2
== p1
)
7583 add_qp_imply (qp_implies
[i
].p1
, p2
);
7585 /* Add in mutex relations implied by this implies relation; for each mutex
7586 relation containing p2, duplicate it and replace p2 with p1. */
7587 bit
= (valueT
)1 << p1
;
7588 mask
= (valueT
)1 << p2
;
7589 for (i
=0;i
< qp_mutexeslen
;i
++)
7591 if (qp_mutexes
[i
].prmask
& mask
)
7592 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
7597 /* Add the PRs specified in the mask to the mutex list; this means that only
7598 one of the PRs can be true at any time. PR0 should never be included in
7607 if (qp_mutexeslen
== qp_mutexestotlen
)
7609 qp_mutexestotlen
+= 20;
7610 qp_mutexes
= (struct qpmutex
*)
7611 xrealloc ((void *)qp_mutexes
,
7612 qp_mutexestotlen
* sizeof (struct qpmutex
));
7616 fprintf (stderr
, " Registering mutex on");
7617 print_prmask (mask
);
7618 fprintf (stderr
, "\n");
7620 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
7621 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
7625 clear_register_values ()
7629 fprintf (stderr
, " Clearing register values\n");
7630 for (i
=1;i
< NELEMS(gr_values
);i
++)
7631 gr_values
[i
].known
= 0;
7634 /* Keep track of register values/changes which affect DV tracking.
7636 optimization note: should add a flag to classes of insns where otherwise we
7637 have to examine a group of strings to identify them.
7641 note_register_values (idesc
)
7642 struct ia64_opcode
*idesc
;
7644 valueT qp_changemask
= 0;
7647 /* invalidate values for registers being written to */
7648 for (i
=0;i
< idesc
->num_outputs
;i
++)
7650 if (idesc
->operands
[i
] == IA64_OPND_R1
7651 || idesc
->operands
[i
] == IA64_OPND_R2
7652 || idesc
->operands
[i
] == IA64_OPND_R3
)
7654 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7655 if (regno
> 0 && regno
< NELEMS(gr_values
))
7656 gr_values
[regno
].known
= 0;
7658 else if (idesc
->operands
[i
] == IA64_OPND_P1
7659 || idesc
->operands
[i
] == IA64_OPND_P2
)
7661 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7662 qp_changemask
|= (valueT
)1 << regno
;
7664 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
7666 if (idesc
->operands
[2] & (valueT
)0x10000)
7667 qp_changemask
= ~(valueT
)0x1FFFF | idesc
->operands
[2];
7669 qp_changemask
= idesc
->operands
[2];
7672 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
7674 if (idesc
->operands
[1] & ((valueT
)1 << 43))
7675 qp_changemask
= ~(valueT
)0xFFFFFFFFFFF | idesc
->operands
[1];
7677 qp_changemask
= idesc
->operands
[1];
7678 qp_changemask
&= ~(valueT
)0xFFFF;
7683 /* Always clear qp branch flags on any PR change */
7684 /* FIXME there may be exceptions for certain compares */
7685 clear_qp_branch_flag (qp_changemask
);
7687 /* invalidate rotating registers on insns which affect RRBs in CFM */
7688 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
7690 qp_changemask
|= ~(valueT
)0xFFFF;
7691 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
7693 for (i
=32;i
< 32+md
.rot
.num_regs
;i
++)
7694 gr_values
[i
].known
= 0;
7696 clear_qp_mutex (qp_changemask
);
7697 clear_qp_implies (qp_changemask
, qp_changemask
);
7699 /* after a call, all register values are undefined, except those marked
7701 else if (strncmp (idesc
->name
, "br.call", 6) == 0
7702 || strncmp (idesc
->name
, "brl.call", 7) == 0)
7704 // FIXME keep GR values which are marked as "safe_across_calls"
7705 clear_register_values ();
7706 clear_qp_mutex (~qp_safe_across_calls
);
7707 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
7708 clear_qp_branch_flag (~qp_safe_across_calls
);
7710 else if (is_interruption_or_rfi (idesc
)
7711 || is_taken_branch (idesc
))
7713 clear_register_values ();
7714 clear_qp_mutex (~(valueT
)0);
7715 clear_qp_implies (~(valueT
)0, ~(valueT
)0);
7717 /* Look for mutex and implies relations */
7718 else if ((idesc
->operands
[0] == IA64_OPND_P1
7719 || idesc
->operands
[0] == IA64_OPND_P2
)
7720 && (idesc
->operands
[1] == IA64_OPND_P1
7721 || idesc
->operands
[1] == IA64_OPND_P2
))
7723 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7724 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7725 valueT p1mask
= (valueT
)1 << p1
;
7726 valueT p2mask
= (valueT
)1 << p2
;
7728 /* if one of the PRs is PR0, we can't really do anything */
7729 if (p1
== 0 || p2
== 0)
7732 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
7734 /* In general, clear mutexes and implies which include P1 or P2,
7735 with the following exceptions */
7736 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
7738 add_qp_mutex (p1mask
| p2mask
);
7739 clear_qp_implies (p2mask
, p1mask
);
7741 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
7743 add_qp_mutex (p1mask
| p2mask
);
7744 clear_qp_implies (p1mask
, p2mask
);
7746 else if (strstr (idesc
->name
, ".and") != NULL
)
7748 clear_qp_implies (0, p1mask
| p2mask
);
7750 else if (strstr (idesc
->name
, ".or") != NULL
)
7752 clear_qp_mutex (p1mask
| p2mask
);
7753 clear_qp_implies (p1mask
| p2mask
, 0);
7757 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
7758 if (strstr (idesc
->name
, ".unc") != NULL
)
7760 add_qp_mutex (p1mask
| p2mask
);
7761 if (CURR_SLOT
.qp_regno
!= 0)
7763 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
7764 CURR_SLOT
.qp_regno
);
7765 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
7766 CURR_SLOT
.qp_regno
);
7769 else if (CURR_SLOT
.qp_regno
== 0)
7771 add_qp_mutex (p1mask
| p2mask
);
7775 clear_qp_mutex (p1mask
| p2mask
);
7779 /* Look for mov imm insns into GRs */
7780 else if (idesc
->operands
[0] == IA64_OPND_R1
7781 && (idesc
->operands
[1] == IA64_OPND_IMM22
7782 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
7783 && (strcmp(idesc
->name
, "mov") == 0
7784 || strcmp(idesc
->name
, "movl") == 0))
7786 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7787 if (regno
> 0 && regno
< NELEMS(gr_values
))
7789 gr_values
[regno
].known
= 1;
7790 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
7791 gr_values
[regno
].path
= md
.path
;
7793 fprintf (stderr
, " Know gr%d = 0x%llx\n",
7794 regno
, gr_values
[regno
].value
);
7799 clear_qp_mutex (qp_changemask
);
7800 clear_qp_implies (qp_changemask
, qp_changemask
);
7804 /* Return whether the given predicate registers are currently mutex */
7806 qp_mutex (p1
, p2
, path
)
7816 mask
= ((valueT
)1<<p1
) | (valueT
)1<<p2
;
7817 for (i
=0;i
< qp_mutexeslen
;i
++)
7819 if (qp_mutexes
[i
].path
>= path
7820 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
7827 /* Return whether the given resource is in the given insn's list of chks
7828 Return 1 if the conflict is absolutely determined, 2 if it's a potential
7832 resources_match (rs
, idesc
, note
, qp_regno
, path
)
7834 struct ia64_opcode
*idesc
;
7839 struct rsrc specs
[MAX_SPECS
];
7842 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7843 we don't need to check. One exception is note 11, which indicates that
7844 target predicates are written regardless of PR[qp]. */
7845 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
7849 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
7852 /* UNAT checking is a bit more specific than other resources */
7853 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
7854 && specs
[count
].mem_offset
.hint
7855 && rs
->mem_offset
.hint
)
7857 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
7859 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
7860 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
7867 /* If either resource is not specific, conservatively assume a conflict
7869 if (!specs
[count
].specific
|| !rs
->specific
)
7871 else if (specs
[count
].index
== rs
->index
)
7876 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
7882 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7883 insert a stop to create the break. Update all resource dependencies
7884 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7885 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7886 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
7891 insn_group_break (insert_stop
, qp_regno
, save_current
)
7898 if (insert_stop
&& md
.num_slots_in_use
> 0)
7899 PREV_SLOT
.end_of_insn_group
= 1;
7903 fprintf (stderr
, " Insn group break%s",
7904 (insert_stop
? " (w/stop)" : ""));
7906 fprintf (stderr
, " effective for QP=%d", qp_regno
);
7907 fprintf (stderr
, "\n");
7911 while (i
< regdepslen
)
7913 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
7916 && regdeps
[i
].qp_regno
!= qp_regno
)
7923 && CURR_SLOT
.src_file
== regdeps
[i
].file
7924 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
7930 /* clear dependencies which are automatically cleared by a stop, or
7931 those that have reached the appropriate state of insn serialization */
7932 if (dep
->semantics
== IA64_DVS_IMPLIED
7933 || dep
->semantics
== IA64_DVS_IMPLIEDF
7934 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
7936 print_dependency ("Removing", i
);
7937 regdeps
[i
] = regdeps
[--regdepslen
];
7941 if (dep
->semantics
== IA64_DVS_DATA
7942 || dep
->semantics
== IA64_DVS_INSTR
7943 || dep
->semantics
== IA64_DVS_SPECIFIC
)
7945 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
7946 regdeps
[i
].insn_srlz
= STATE_STOP
;
7947 if (regdeps
[i
].data_srlz
== STATE_NONE
)
7948 regdeps
[i
].data_srlz
= STATE_STOP
;
7955 /* Add the given resource usage spec to the list of active dependencies */
7957 mark_resource (idesc
, dep
, spec
, depind
, path
)
7958 struct ia64_opcode
*idesc
;
7959 const struct ia64_dependency
*dep
;
7964 if (regdepslen
== regdepstotlen
)
7966 regdepstotlen
+= 20;
7967 regdeps
= (struct rsrc
*)
7968 xrealloc ((void *)regdeps
,
7969 regdepstotlen
* sizeof(struct rsrc
));
7972 regdeps
[regdepslen
] = *spec
;
7973 regdeps
[regdepslen
].depind
= depind
;
7974 regdeps
[regdepslen
].path
= path
;
7975 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
7976 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
7978 print_dependency ("Adding", regdepslen
);
7984 print_dependency (action
, depind
)
7990 fprintf (stderr
, " %s %s '%s'",
7991 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
7992 (regdeps
[depind
].dependency
)->name
);
7993 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
7994 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
7995 if (regdeps
[depind
].mem_offset
.hint
)
7996 fprintf (stderr
, " 0x%llx+0x%llx",
7997 regdeps
[depind
].mem_offset
.base
,
7998 regdeps
[depind
].mem_offset
.offset
);
7999 fprintf (stderr
, "\n");
8004 instruction_serialization ()
8008 fprintf (stderr
, " Instruction serialization\n");
8009 for (i
=0;i
< regdepslen
;i
++)
8010 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8011 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8015 data_serialization ()
8019 fprintf (stderr
, " Data serialization\n");
8020 while (i
< regdepslen
)
8022 if (regdeps
[i
].data_srlz
== STATE_STOP
8023 /* Note: as of 991210, all "other" dependencies are cleared by a
8024 data serialization. This might change with new tables */
8025 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8027 print_dependency ("Removing", i
);
8028 regdeps
[i
] = regdeps
[--regdepslen
];
8035 /* Insert stops and serializations as needed to avoid DVs */
8037 remove_marked_resource (rs
)
8040 switch (rs
->dependency
->semantics
)
8042 case IA64_DVS_SPECIFIC
:
8044 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8045 /* ...fall through... */
8046 case IA64_DVS_INSTR
:
8048 fprintf (stderr
, "Inserting instr serialization\n");
8049 if (rs
->insn_srlz
< STATE_STOP
)
8050 insn_group_break (1, 0, 0);
8051 if (rs
->insn_srlz
< STATE_SRLZ
)
8053 int oldqp
= CURR_SLOT
.qp_regno
;
8054 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8055 /* Manually jam a srlz.i insn into the stream */
8056 CURR_SLOT
.qp_regno
= 0;
8057 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8058 instruction_serialization ();
8059 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8060 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8062 CURR_SLOT
.qp_regno
= oldqp
;
8063 CURR_SLOT
.idesc
= oldidesc
;
8065 insn_group_break (1, 0, 0);
8067 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8068 "other" types of DV are eliminated
8069 by a data serialization */
8072 fprintf (stderr
, "Inserting data serialization\n");
8073 if (rs
->data_srlz
< STATE_STOP
)
8074 insn_group_break (1, 0, 0);
8076 int oldqp
= CURR_SLOT
.qp_regno
;
8077 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8078 /* Manually jam a srlz.d insn into the stream */
8079 CURR_SLOT
.qp_regno
= 0;
8080 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8081 data_serialization ();
8082 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8083 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8085 CURR_SLOT
.qp_regno
= oldqp
;
8086 CURR_SLOT
.idesc
= oldidesc
;
8089 case IA64_DVS_IMPLIED
:
8090 case IA64_DVS_IMPLIEDF
:
8092 fprintf (stderr
, "Inserting stop\n");
8093 insn_group_break (1, 0, 0);
8100 /* Check the resources used by the given opcode against the current dependency
8103 The check is run once for each execution path encountered. In this case,
8104 a unique execution path is the sequence of instructions following a code
8105 entry point, e.g. the following has three execution paths, one starting
8106 at L0, one at L1, and one at L2.
8114 check_dependencies (idesc
)
8115 struct ia64_opcode
*idesc
;
8117 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8121 /* Note that the number of marked resources may change within the
8122 loop if in auto mode. */
8124 while (i
< regdepslen
)
8126 struct rsrc
*rs
= ®deps
[i
];
8127 const struct ia64_dependency
*dep
= rs
->dependency
;
8132 if (dep
->semantics
== IA64_DVS_NONE
8133 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8138 note
= NOTE(opdeps
->chks
[chkind
]);
8140 /* Check this resource against each execution path seen thus far */
8141 for (path
=0;path
<= md
.path
;path
++)
8145 /* If the dependency wasn't on the path being checked, ignore it */
8146 if (rs
->path
< path
)
8149 /* If the QP for this insn implies a QP which has branched, don't
8150 bother checking. Ed. NOTE: I don't think this check is terribly
8151 useful; what's the point of generating code which will only be
8152 reached if its QP is zero?
8153 This code was specifically inserted to handle the following code,
8154 based on notes from Intel's DV checking code, where p1 implies p2.
8161 if (CURR_SLOT
.qp_regno
!= 0)
8165 for (implies
=0;implies
< qp_implieslen
;implies
++)
8167 if (qp_implies
[implies
].path
>= path
8168 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8169 && qp_implies
[implies
].p2_branched
)
8179 if ((matchtype
= resources_match (rs
, idesc
, note
,
8180 CURR_SLOT
.qp_regno
, path
)) != 0)
8183 char pathmsg
[256] = "";
8184 char indexmsg
[256] = "";
8185 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8188 sprintf (pathmsg
, " when entry is at label '%s'",
8189 md
.entry_labels
[path
-1]);
8190 if (rs
->specific
&& rs
->index
!= 0)
8191 sprintf (indexmsg
, ", specific resource number is %d",
8193 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8195 (certain
? "violates" : "may violate"),
8196 dv_mode
[dep
->mode
], dep
->name
,
8197 dv_sem
[dep
->semantics
],
8200 if (md
.explicit_mode
)
8202 as_warn ("%s", msg
);
8204 as_warn (_("Only the first path encountering the conflict "
8206 as_warn_where (rs
->file
, rs
->line
,
8207 _("This is the location of the "
8208 "conflicting usage"));
8209 /* Don't bother checking other paths, to avoid duplicating
8216 fprintf(stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8218 remove_marked_resource (rs
);
8220 /* since the set of dependencies has changed, start over */
8221 /* FIXME -- since we're removing dvs as we go, we
8222 probably don't really need to start over... */
8235 /* register new dependencies based on the given opcode */
8237 mark_resources (idesc
)
8238 struct ia64_opcode
*idesc
;
8241 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8242 int add_only_qp_reads
= 0;
8244 /* A conditional branch only uses its resources if it is taken; if it is
8245 taken, we stop following that path. The other branch types effectively
8246 *always* write their resources. If it's not taken, register only QP
8248 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8250 add_only_qp_reads
= 1;
8254 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8256 for (i
=0;i
< opdeps
->nregs
;i
++)
8258 const struct ia64_dependency
*dep
;
8259 struct rsrc specs
[MAX_SPECS
];
8264 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8265 note
= NOTE(opdeps
->regs
[i
]);
8267 if (add_only_qp_reads
8268 && !(dep
->mode
== IA64_DV_WAR
8269 && (dep
->specifier
== IA64_RS_PR
8270 || dep
->specifier
== IA64_RS_PR63
)))
8273 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8276 if (md
.debug_dv
&& !count
)
8277 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8278 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
8283 mark_resource (idesc
, dep
, &specs
[count
],
8284 DEP(opdeps
->regs
[i
]), md
.path
);
8287 /* The execution path may affect register values, which may in turn
8288 affect which indirect-access resources are accessed. */
8289 switch (dep
->specifier
)
8301 for (path
=0;path
< md
.path
;path
++)
8303 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
8305 mark_resource (idesc
, dep
, &specs
[count
],
8306 DEP(opdeps
->regs
[i
]), path
);
8313 /* remove dependencies when they no longer apply */
8315 update_dependencies (idesc
)
8316 struct ia64_opcode
*idesc
;
8320 if (strcmp (idesc
->name
, "srlz.i") == 0)
8322 instruction_serialization ();
8324 else if (strcmp (idesc
->name
, "srlz.d") == 0)
8326 data_serialization ();
8328 else if (is_interruption_or_rfi (idesc
)
8329 || is_taken_branch (idesc
))
8331 /* although technically the taken branch doesn't clear dependencies
8332 which require a srlz.[id], we don't follow the branch; the next
8333 instruction is assumed to start with a clean slate */
8337 else if (is_conditional_branch (idesc
)
8338 && CURR_SLOT
.qp_regno
!= 0)
8340 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
8342 for (i
=0;i
< qp_implieslen
;i
++)
8344 /* if the conditional branch's predicate is implied by the predicate
8345 in an existing dependency, remove that dependency */
8346 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
8349 /* note that this implied predicate takes a branch so that if
8350 a later insn generates a DV but its predicate implies this
8351 one, we can avoid the false DV warning */
8352 qp_implies
[i
].p2_branched
= 1;
8353 while (depind
< regdepslen
)
8355 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
8357 print_dependency ("Removing", depind
);
8358 regdeps
[depind
] = regdeps
[--regdepslen
];
8365 /* Any marked resources which have this same predicate should be
8366 cleared, provided that the QP hasn't been modified between the
8367 marking instruction and the branch.
8371 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
8376 while (i
< regdepslen
)
8378 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
8379 && regdeps
[i
].link_to_qp_branch
8380 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
8381 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
8383 /* Treat like a taken branch */
8384 print_dependency ("Removing", i
);
8385 regdeps
[i
] = regdeps
[--regdepslen
];
8394 /* Examine the current instruction for dependency violations. */
8397 struct ia64_opcode
*idesc
;
8401 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
8402 idesc
->name
, CURR_SLOT
.src_line
,
8403 idesc
->dependencies
->nchks
,
8404 idesc
->dependencies
->nregs
);
8407 /* Look through the list of currently marked resources; if the current
8408 instruction has the dependency in its chks list which uses that resource,
8409 check against the specific resources used.
8411 check_dependencies (idesc
);
8414 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8415 then add them to the list of marked resources.
8417 mark_resources (idesc
);
8419 /* There are several types of dependency semantics, and each has its own
8420 requirements for being cleared
8422 Instruction serialization (insns separated by interruption, rfi, or
8423 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8425 Data serialization (instruction serialization, or writer + srlz.d +
8426 reader, where writer and srlz.d are in separate groups) clears
8427 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8428 always be the case).
8430 Instruction group break (groups separated by stop, taken branch,
8431 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8433 update_dependencies (idesc
);
8435 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8436 warning. Keep track of as many as possible that are useful. */
8437 note_register_values (idesc
);
8439 /* We don't need or want this anymore. */
8440 md
.mem_offset
.hint
= 0;
8445 /* Translate one line of assembly. Pseudo ops and labels do not show
8451 char *saved_input_line_pointer
, *mnemonic
;
8452 const struct pseudo_opcode
*pdesc
;
8453 struct ia64_opcode
*idesc
;
8454 unsigned char qp_regno
;
8458 saved_input_line_pointer
= input_line_pointer
;
8459 input_line_pointer
= str
;
8461 /* extract the opcode (mnemonic): */
8463 mnemonic
= input_line_pointer
;
8464 ch
= get_symbol_end ();
8465 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
8468 *input_line_pointer
= ch
;
8469 (*pdesc
->handler
) (pdesc
->arg
);
8473 /* find the instruction descriptor matching the arguments: */
8475 idesc
= ia64_find_opcode (mnemonic
);
8476 *input_line_pointer
= ch
;
8479 as_bad ("Unknown opcode `%s'", mnemonic
);
8483 idesc
= parse_operands (idesc
);
8487 /* Handle the dynamic ops we can handle now: */
8488 if (idesc
->type
== IA64_TYPE_DYN
)
8490 if (strcmp (idesc
->name
, "add") == 0)
8492 if (CURR_SLOT
.opnd
[2].X_op
== O_register
8493 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
8497 ia64_free_opcode (idesc
);
8498 idesc
= ia64_find_opcode (mnemonic
);
8500 know (!idesc
->next
);
8503 else if (strcmp (idesc
->name
, "mov") == 0)
8505 enum ia64_opnd opnd1
, opnd2
;
8508 opnd1
= idesc
->operands
[0];
8509 opnd2
= idesc
->operands
[1];
8510 if (opnd1
== IA64_OPND_AR3
)
8512 else if (opnd2
== IA64_OPND_AR3
)
8516 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
8517 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
8521 ia64_free_opcode (idesc
);
8522 idesc
= ia64_find_opcode (mnemonic
);
8523 while (idesc
!= NULL
8524 && (idesc
->operands
[0] != opnd1
8525 || idesc
->operands
[1] != opnd2
))
8526 idesc
= get_next_opcode (idesc
);
8531 if (md
.qp
.X_op
== O_register
)
8532 qp_regno
= md
.qp
.X_add_number
- REG_P
;
8534 flags
= idesc
->flags
;
8536 if ((flags
& IA64_OPCODE_FIRST
) != 0)
8537 insn_group_break (1, 0, 0);
8539 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
8541 as_bad ("`%s' cannot be predicated", idesc
->name
);
8545 /* build the instruction: */
8546 CURR_SLOT
.qp_regno
= qp_regno
;
8547 CURR_SLOT
.idesc
= idesc
;
8548 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
8549 if (debug_type
== DEBUG_DWARF2
)
8550 dwarf2_where (&CURR_SLOT
.debug_line
);
8552 /* Add unwind entry, if there is one. */
8553 if (unwind
.current_entry
)
8555 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
8556 unwind
.current_entry
= NULL
;
8559 /* check for dependency violations */
8563 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8564 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8567 if ((flags
& IA64_OPCODE_LAST
) != 0)
8568 insn_group_break (1, 0, 0);
8570 md
.last_text_seg
= now_seg
;
8573 input_line_pointer
= saved_input_line_pointer
;
8576 /* Called when symbol NAME cannot be found in the symbol table.
8577 Should be used for dynamic valued symbols only. */
8579 md_undefined_symbol (name
)
8585 /* Called for any expression that can not be recognized. When the
8586 function is called, `input_line_pointer' will point to the start of
8592 enum pseudo_type pseudo_type
;
8597 switch (*input_line_pointer
)
8600 /* find what relocation pseudo-function we're dealing with: */
8602 ch
= *++input_line_pointer
;
8603 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
8604 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
8606 len
= strlen (pseudo_func
[i
].name
);
8607 if (strncmp (pseudo_func
[i
].name
+ 1,
8608 input_line_pointer
+ 1, len
- 1) == 0
8609 && !is_part_of_name (input_line_pointer
[len
]))
8611 input_line_pointer
+= len
;
8612 pseudo_type
= pseudo_func
[i
].type
;
8616 switch (pseudo_type
)
8618 case PSEUDO_FUNC_RELOC
:
8620 if (*input_line_pointer
!= '(')
8622 as_bad ("Expected '('");
8625 ++input_line_pointer
; /* skip '(' */
8627 if (*input_line_pointer
++ != ')')
8629 as_bad ("Missing ')'");
8632 if (e
->X_op
!= O_symbol
)
8634 if (e
->X_op
!= O_pseudo_fixup
)
8636 as_bad ("Not a symbolic expression");
8639 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
8640 && i
== FUNC_LT_RELATIVE
)
8641 i
= FUNC_LT_FPTR_RELATIVE
;
8644 as_bad ("Illegal combination of relocation functions");
8648 /* make sure gas doesn't get rid of local symbols that are used
8650 e
->X_op
= O_pseudo_fixup
;
8651 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
8654 case PSEUDO_FUNC_CONST
:
8655 e
->X_op
= O_constant
;
8656 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8659 case PSEUDO_FUNC_REG
:
8660 e
->X_op
= O_register
;
8661 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8665 name
= input_line_pointer
- 1;
8667 as_bad ("Unknown pseudo function `%s'", name
);
8673 ++input_line_pointer
;
8675 if (*input_line_pointer
!= ']')
8677 as_bad ("Closing bracket misssing");
8682 if (e
->X_op
!= O_register
)
8683 as_bad ("Register expected as index");
8685 ++input_line_pointer
;
8696 ignore_rest_of_line ();
8699 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8700 a section symbol plus some offset. For relocs involving @fptr(),
8701 directives we don't want such adjustments since we need to have the
8702 original symbol's name in the reloc. */
8704 ia64_fix_adjustable (fix
)
8707 /* Prevent all adjustments to global symbols */
8708 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
8711 switch (fix
->fx_r_type
)
8713 case BFD_RELOC_IA64_FPTR64I
:
8714 case BFD_RELOC_IA64_FPTR32MSB
:
8715 case BFD_RELOC_IA64_FPTR32LSB
:
8716 case BFD_RELOC_IA64_FPTR64MSB
:
8717 case BFD_RELOC_IA64_FPTR64LSB
:
8718 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8719 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8729 ia64_force_relocation (fix
)
8732 switch (fix
->fx_r_type
)
8734 case BFD_RELOC_IA64_FPTR64I
:
8735 case BFD_RELOC_IA64_FPTR32MSB
:
8736 case BFD_RELOC_IA64_FPTR32LSB
:
8737 case BFD_RELOC_IA64_FPTR64MSB
:
8738 case BFD_RELOC_IA64_FPTR64LSB
:
8740 case BFD_RELOC_IA64_LTOFF22
:
8741 case BFD_RELOC_IA64_LTOFF64I
:
8742 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8743 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8744 case BFD_RELOC_IA64_PLTOFF22
:
8745 case BFD_RELOC_IA64_PLTOFF64I
:
8746 case BFD_RELOC_IA64_PLTOFF64MSB
:
8747 case BFD_RELOC_IA64_PLTOFF64LSB
:
8756 /* Decide from what point a pc-relative relocation is relative to,
8757 relative to the pc-relative fixup. Er, relatively speaking. */
8759 ia64_pcrel_from_section (fix
, sec
)
8763 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
8765 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
8771 /* This is called whenever some data item (not an instruction) needs a
8772 fixup. We pick the right reloc code depending on the byteorder
8773 currently in effect. */
8775 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
8781 bfd_reloc_code_real_type code
;
8786 /* There are no reloc for 8 and 16 bit quantities, but we allow
8787 them here since they will work fine as long as the expression
8788 is fully defined at the end of the pass over the source file. */
8789 case 1: code
= BFD_RELOC_8
; break;
8790 case 2: code
= BFD_RELOC_16
; break;
8792 if (target_big_endian
)
8793 code
= BFD_RELOC_IA64_DIR32MSB
;
8795 code
= BFD_RELOC_IA64_DIR32LSB
;
8799 if (target_big_endian
)
8800 code
= BFD_RELOC_IA64_DIR64MSB
;
8802 code
= BFD_RELOC_IA64_DIR64LSB
;
8806 as_bad ("Unsupported fixup size %d", nbytes
);
8807 ignore_rest_of_line ();
8810 if (exp
->X_op
== O_pseudo_fixup
)
8813 exp
->X_op
= O_symbol
;
8814 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
8816 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
8817 /* We need to store the byte order in effect in case we're going
8818 to fix an 8 or 16 bit relocation (for which there no real
8819 relocs available). See md_apply_fix(). */
8820 fix
->tc_fix_data
.bigendian
= target_big_endian
;
8823 /* Return the actual relocation we wish to associate with the pseudo
8824 reloc described by SYM and R_TYPE. SYM should be one of the
8825 symbols in the pseudo_func array, or NULL. */
8827 static bfd_reloc_code_real_type
8828 ia64_gen_real_reloc_type (sym
, r_type
)
8830 bfd_reloc_code_real_type r_type
;
8832 bfd_reloc_code_real_type
new = 0;
8839 switch (S_GET_VALUE (sym
))
8841 case FUNC_FPTR_RELATIVE
:
8844 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
8845 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
8846 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
8847 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
8848 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
8853 case FUNC_GP_RELATIVE
:
8856 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
8857 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
8858 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
8859 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
8860 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
8861 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
8866 case FUNC_LT_RELATIVE
:
8869 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
8870 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
8875 case FUNC_PC_RELATIVE
:
8878 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
8879 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
8880 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
8881 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
8882 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
8883 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
8888 case FUNC_PLT_RELATIVE
:
8891 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
8892 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
8893 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
8894 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
8899 case FUNC_SEC_RELATIVE
:
8902 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
8903 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
8904 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
8905 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
8910 case FUNC_SEG_RELATIVE
:
8913 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
8914 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
8915 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
8916 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
8921 case FUNC_LTV_RELATIVE
:
8924 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
8925 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
8926 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
8927 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
8932 case FUNC_LT_FPTR_RELATIVE
:
8935 case BFD_RELOC_IA64_IMM22
:
8936 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
8937 case BFD_RELOC_IA64_IMM64
:
8938 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
8946 /* Hmmmm. Should this ever occur? */
8953 /* Here is where generate the appropriate reloc for pseudo relocation
8956 ia64_validate_fix (fix
)
8959 switch (fix
->fx_r_type
)
8961 case BFD_RELOC_IA64_FPTR64I
:
8962 case BFD_RELOC_IA64_FPTR32MSB
:
8963 case BFD_RELOC_IA64_FPTR64LSB
:
8964 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8965 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8966 if (fix
->fx_offset
!= 0)
8967 as_bad_where (fix
->fx_file
, fix
->fx_line
,
8968 "No addend allowed in @fptr() relocation");
8978 fix_insn (fix
, odesc
, value
)
8980 const struct ia64_operand
*odesc
;
8983 bfd_vma insn
[3], t0
, t1
, control_bits
;
8988 slot
= fix
->fx_where
& 0x3;
8989 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
8991 /* Bundles are always in little-endian byte order */
8992 t0
= bfd_getl64 (fixpos
);
8993 t1
= bfd_getl64 (fixpos
+ 8);
8994 control_bits
= t0
& 0x1f;
8995 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
8996 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
8997 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9000 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9002 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9003 insn
[2] |= (((value
& 0x7f) << 13)
9004 | (((value
>> 7) & 0x1ff) << 27)
9005 | (((value
>> 16) & 0x1f) << 22)
9006 | (((value
>> 21) & 0x1) << 21)
9007 | (((value
>> 63) & 0x1) << 36));
9009 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9011 if (value
& ~0x3fffffffffffffffULL
)
9012 err
= "integer operand out of range";
9013 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9014 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9016 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9019 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9020 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9021 | (((value
>> 0) & 0xfffff) << 13));
9024 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9027 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9029 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9030 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9031 md_number_to_chars (fixpos
+ 0, t0
, 8);
9032 md_number_to_chars (fixpos
+ 8, t1
, 8);
9035 /* Attempt to simplify or even eliminate a fixup. The return value is
9036 ignored; perhaps it was once meaningful, but now it is historical.
9037 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9039 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9042 md_apply_fix3 (fix
, valuep
, seg
)
9048 valueT value
= *valuep
;
9051 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9055 switch (fix
->fx_r_type
)
9057 case BFD_RELOC_IA64_DIR32MSB
:
9058 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9062 case BFD_RELOC_IA64_DIR32LSB
:
9063 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9067 case BFD_RELOC_IA64_DIR64MSB
:
9068 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9072 case BFD_RELOC_IA64_DIR64LSB
:
9073 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9083 switch (fix
->fx_r_type
)
9086 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9087 "%s must have a constant value",
9088 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9095 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9096 work. There should be a better way to handle this. */
9098 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9100 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9102 if (fix
->tc_fix_data
.bigendian
)
9103 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9105 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9111 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9118 /* Generate the BFD reloc to be stuck in the object file from the
9119 fixup used internally in the assembler. */
9121 tc_gen_reloc (sec
, fixp
)
9127 reloc
= xmalloc (sizeof (*reloc
));
9128 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9129 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9130 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9131 reloc
->addend
= fixp
->fx_offset
;
9132 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9137 "Cannot represent %s relocation in object file",
9138 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9143 /* Turn a string in input_line_pointer into a floating point constant
9144 of type TYPE, and store the appropriate bytes in *LIT. The number
9145 of LITTLENUMS emitted is stored in *SIZE. An error message is
9146 returned, or NULL on OK. */
9148 #define MAX_LITTLENUMS 5
9151 md_atof (type
, lit
, size
)
9156 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9157 LITTLENUM_TYPE
*word
;
9187 return "Bad call to MD_ATOF()";
9189 t
= atof_ieee (input_line_pointer
, type
, words
);
9191 input_line_pointer
= t
;
9192 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9194 for (word
= words
+ prec
- 1; prec
--;)
9196 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9197 lit
+= sizeof (LITTLENUM_TYPE
);
9202 /* Round up a section's size to the appropriate boundary. */
9204 md_section_align (seg
, size
)
9208 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9209 valueT mask
= ((valueT
)1 << align
) - 1;
9211 return (size
+ mask
) & ~mask
;
9214 /* Handle ia64 specific semantics of the align directive. */
9217 ia64_md_do_align (n
, fill
, len
, max
)
9223 /* Fill any pending bundle with nops. */
9224 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
9225 ia64_flush_insns ();
9227 /* When we align code in a text section, emit a bundle of 3 nops instead of
9228 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9229 N is log base 2 of the requested alignment. */
9231 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
9234 /* Use mfi bundle of nops with no stop bits. */
9235 static const unsigned char be_nop
[]
9236 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9237 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9238 static const unsigned char le_nop
[]
9239 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9240 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9242 /* Make sure we are on a 16-byte boundary, in case someone has been
9243 putting data into a text section. */
9244 frag_align (4, 0, 0);
9246 if (target_big_endian
)
9247 frag_align_pattern (n
, be_nop
, 16, max
);
9249 frag_align_pattern (n
, le_nop
, 16, max
);