1 /* tc-iq2000.c -- Assembler for the Sitera IQ2000.
2 Copyright (C) 2003 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "safe-ctype.h"
24 #include "dwarf2dbg.h"
27 #include "opcodes/iq2000-desc.h"
28 #include "opcodes/iq2000-opc.h"
30 #include "elf/common.h"
31 #include "elf/iq2000.h"
36 /* Structure to hold all of the different components describing
37 an individual instruction. */
40 const CGEN_INSN
* insn
;
41 const CGEN_INSN
* orig_insn
;
44 CGEN_INSN_INT buffer
[1];
45 #define INSN_VALUE(buf) (*(buf))
47 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
48 #define INSN_VALUE(buf) (buf)
53 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
54 int indices
[MAX_OPERAND_INSTANCES
];
58 const char comment_chars
[] = "#";
59 const char line_comment_chars
[] = "";
60 const char line_separator_chars
[] = ";";
61 const char EXP_CHARS
[] = "eE";
62 const char FLT_CHARS
[] = "dD";
66 #define DEFAULT_MACHINE bfd_mach_iq2000
67 #define DEFAULT_FLAGS EF_IQ2000_CPU_IQ2000
69 static unsigned long iq2000_mach
= bfd_mach_iq2000
;
70 static int cpu_mach
= (1 << MACH_IQ2000
);
72 /* Flags to set in the elf header */
73 static flagword iq2000_flags
= DEFAULT_FLAGS
;
77 unsigned long reg_mask
;
78 unsigned long reg_offset
;
79 unsigned long fpreg_mask
;
80 unsigned long fpreg_offset
;
81 unsigned long frame_offset
;
82 unsigned long frame_reg
;
86 static procS cur_proc
;
87 static procS
*cur_proc_ptr
;
90 static void s_change_sec
PARAMS ((int));
91 static void s_iq2000_set
PARAMS ((int));
92 static void s_iq2000_mask
PARAMS ((int));
93 static void s_iq2000_frame
PARAMS ((int));
94 static void s_iq2000_ent
PARAMS ((int));
95 static void s_iq2000_end
PARAMS ((int));
96 static int get_number
PARAMS ((void));
97 static symbolS
* get_symbol
PARAMS ((void));
98 static void iq2000_record_hi16
PARAMS((int, fixS
*, segT
));
101 /* The target specific pseudo-ops which we support. */
102 const pseudo_typeS md_pseudo_table
[] =
104 { "align", s_align_bytes
, 0 },
106 { "file", dwarf2_directive_file
, 0 },
107 { "loc", dwarf2_directive_loc
, 0 },
108 { "rdata", s_change_sec
, 'r'},
109 { "sdata", s_change_sec
, 's'},
110 { "set", s_iq2000_set
, 0 },
111 { "ent", s_iq2000_ent
, 0 },
112 { "end", s_iq2000_end
, 0 },
113 { "frame", s_iq2000_frame
, 0 },
114 { "fmask", s_iq2000_mask
, 'F' },
115 { "mask", s_iq2000_mask
, 'R' },
116 { "dword", cons
, 8 },
121 /* Relocations against symbols are done in two
122 parts, with a HI relocation and a LO relocation. Each relocation
123 has only 16 bits of space to store an addend. This means that in
124 order for the linker to handle carries correctly, it must be able
125 to locate both the HI and the LO relocation. This means that the
126 relocations must appear in order in the relocation table.
128 In order to implement this, we keep track of each unmatched HI
129 relocation. We then sort them so that they immediately precede the
130 corresponding LO relocation. */
132 struct iq2000_hi_fixup
134 struct iq2000_hi_fixup
* next
; /* Next HI fixup. */
135 fixS
* fixp
; /* This fixup. */
136 segT seg
; /* The section this fixup is in. */
140 /* The list of unmatched HI relocs. */
141 static struct iq2000_hi_fixup
* iq2000_hi_fixup_list
;
144 /* assembler options */
145 #define OPTION_CPU_2000 (OPTION_MD_BASE)
146 #define OPTION_CPU_10 (OPTION_MD_BASE + 1)
148 struct option md_longopts
[] =
150 { "m2000", no_argument
, NULL
, OPTION_CPU_2000
},
151 { "m10", no_argument
, NULL
, OPTION_CPU_10
},
152 { NULL
, no_argument
, NULL
, 0 },
155 size_t md_longopts_size
= sizeof (md_longopts
);
157 const char * md_shortopts
= "";
159 static void iq2000_add_macro
PARAMS ((const char *, const char *, const char **));
160 static void iq2000_load_macros
PARAMS ((void));
161 static void iq10_load_macros
PARAMS ((void));
163 /* macro hash table, which we will add to. */
164 extern struct hash_control
*macro_hash
;
167 md_parse_option (c
, arg
)
168 int c ATTRIBUTE_UNUSED
;
169 char * arg ATTRIBUTE_UNUSED
;
173 case OPTION_CPU_2000
:
174 iq2000_flags
= (iq2000_flags
& ~EF_IQ2000_CPU_MASK
) | EF_IQ2000_CPU_IQ2000
;
175 iq2000_mach
= bfd_mach_iq2000
;
176 cpu_mach
= (1 << MACH_IQ2000
);
180 iq2000_flags
= (iq2000_flags
& ~EF_IQ2000_CPU_MASK
) | EF_IQ2000_CPU_IQ10
;
181 iq2000_mach
= bfd_mach_iq10
;
182 cpu_mach
= (1 << MACH_IQ10
);
183 /* only the first 3 pseudo ops (word, file, loc) are in IQ10 */
193 md_show_usage (stream
)
196 fprintf (stream
, _("IQ2000 specific command line options:\n"));
197 fprintf (stream
, _("-m2000 <default> IQ2000 processor\n"));
198 fprintf (stream
, _("-m10 IQ10 processor\n"));
205 /* Initialize the `cgen' interface. */
207 /* Set the machine number and endian. */
208 gas_cgen_cpu_desc
= iq2000_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, cpu_mach
,
209 CGEN_CPU_OPEN_ENDIAN
,
212 iq2000_cgen_init_asm (gas_cgen_cpu_desc
);
214 /* This is a callback from cgen to gas to parse operands. */
215 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
217 /* Set the ELF flags if desired. */
219 bfd_set_private_flags (stdoutput
, iq2000_flags
);
221 /* Set the machine type */
222 bfd_default_set_arch_mach (stdoutput
, bfd_arch_iq2000
, iq2000_mach
);
224 if (iq2000_mach
== bfd_mach_iq2000
)
225 iq2000_load_macros ();
231 iq2000_add_macro (name
, semantics
, arguments
)
233 const char *semantics
;
234 const char **arguments
;
240 macro
= (macro_entry
*) xmalloc (sizeof (macro_entry
));
241 sb_new (¯o
->sub
);
242 sb_new (¯o_name
);
244 macro
->formal_count
= 0;
247 sb_add_string (¯o
->sub
, semantics
);
249 if (arguments
!= NULL
)
251 formal_entry
**p
= ¯o
->formals
;
253 macro
->formal_count
= 0;
254 macro
->formal_hash
= hash_new ();
255 while (*arguments
!= NULL
)
257 formal_entry
*formal
;
259 formal
= (formal_entry
*) xmalloc (sizeof (formal_entry
));
261 sb_new (&formal
->name
);
262 sb_new (&formal
->def
);
263 sb_new (&formal
->actual
);
265 /* chlm: Added the following to allow defaulted args. */
266 if (strchr (*arguments
,'='))
268 char * tt_args
= strdup(*arguments
);
269 char * tt_dflt
= strchr(tt_args
,'=');
272 sb_add_string (&formal
->name
, tt_args
);
273 sb_add_string (&formal
->def
, tt_dflt
+ 1);
276 sb_add_string (&formal
->name
, *arguments
);
278 /* Add to macro's hash table. */
279 hash_jam (macro
->formal_hash
, sb_terminate (&formal
->name
), formal
);
281 formal
->index
= macro
->formal_count
;
282 macro
->formal_count
++;
290 sb_add_string (¯o_name
, name
);
291 namestr
= sb_terminate (¯o_name
);
292 hash_jam (macro_hash
, namestr
, (PTR
) macro
);
297 /* Automatically enter conditional branch macros. */
300 const char * mnemonic
;
301 const char ** expansion
;
303 } iq2000_macro_defs_s
;
305 static const char * abs_args
[] = { "rd", "rs", "scratch=%1", NULL
};
306 static const char * abs_expn
= "\n sra \\rd,\\rs,31\n xor \\scratch,\\rd,\\rs\n sub \\rd,\\scratch,\\rd\n";
308 static const char * la_expn
= "\n lui \\reg,%hi(\\label)\n ori \\reg,\\reg,%lo(\\label)\n";
309 static const char * la_args
[] = { "reg", "label", NULL
};
311 static const char * bxx_args
[] = { "rs", "rt", "label", "scratch=%1", NULL
};
312 static const char * bge_expn
= "\n slt \\scratch,\\rs,\\rt\n beq %0,\\scratch,\\label\n";
313 static const char * bgeu_expn
= "\n sltu \\scratch,\\rs,\\rt\n beq %0,\\scratch,\\label\n";
314 static const char * bgt_expn
= "\n slt \\scratch,\\rt,\\rs\n bne %0,\\scratch,\\label\n";
315 static const char * bgtu_expn
= "\n sltu \\scratch,\\rt,\\rs\n bne %0,\\scratch,\\label\n";
316 static const char * ble_expn
= "\n slt \\scratch,\\rt,\\rs\n beq %0,\\scratch,\\label\n";
317 static const char * bleu_expn
= "\n sltu \\scratch,\\rt,\\rs\n beq %0,\\scratch,\\label\n";
318 static const char * blt_expn
= "\n slt \\scratch,\\rs,\\rt\n bne %0,\\scratch,\\label\n";
319 static const char * bltu_expn
= "\n sltu \\scratch,\\rs,\\rt\n bne %0,\\scratch,\\label\n";
321 static const char * sxx_args
[] = { "rd", "rs", "rt", NULL
};
322 static const char * sge_expn
= "\n slt \\rd,\\rs,\\rt\n xori \\rd,\\rd,1\n";
323 static const char * sgeu_expn
= "\n sltu \\rd,\\rs,\\rt\n xori \\rd,\\rd,1\n";
324 static const char * sle_expn
= "\n slt \\rd,\\rt,\\rs\n xori \\rd,\\rd,1\n";
325 static const char * sleu_expn
= "\n sltu \\rd,\\rt,\\rs\n xori \\rd,\\rd,1\n";
326 static const char * sgt_expn
= "\n slt \\rd,\\rt,\\rs\n";
327 static const char * sgtu_expn
= "\n sltu \\rd,\\rt,\\rs\n";
328 static const char * sne_expn
= "\n xor \\rd,\\rt,\\rs\n sltu \\rd,%0,\\rd\n";
329 static const char * seq_expn
= "\n xor \\rd,\\rt,\\rs\n sltu \\rd,%0,\\rd\n xori \\rd,\\rd,1\n";
331 static const char * ai32_args
[] = { "rt", "rs", "imm", NULL
};
332 static const char * andi32_expn
= "\n\
333 .if (\\imm & 0xffff0000 == 0xffff0000)\n\
334 andoi \\rt,\\rs,%lo(\\imm)\n\
335 .elseif (\\imm & 0x0000ffff == 0x0000ffff)\n\
336 andoui \\rt,\\rs,%uhi(\\imm)\n\
337 .elseif (\\imm & 0xffff0000 == 0x00000000)\n\
338 andi \\rt,\\rs,%lo(\\imm)\n\
340 andoui \\rt,\\rs,%uhi(\\imm)\n\
341 andoi \\rt,\\rt,%lo(\\imm)\n\
343 static const char * ori32_expn
= "\n\
344 .if (\\imm & 0xffff == 0)\n\
345 orui \\rt,\\rs,%uhi(\\imm)\n\
346 .elseif (\\imm & 0xffff0000 == 0)\n\
347 ori \\rt,\\rs,%lo(\\imm)\n\
349 orui \\rt,\\rs,%uhi(\\imm)\n\
350 ori \\rt,\\rt,%lo(\\imm)\n\
353 static const char * neg_args
[] = { "rd", "rs", NULL
};
354 static const char * neg_expn
= "\n sub \\rd,%0,\\rs\n";
355 static const char * negu_expn
= "\n subu \\rd,%0,\\rs\n";
357 static const char * li_args
[] = { "rt", "imm", NULL
};
358 static const char * li_expn
= "\n\
359 .if (\\imm & 0xffff0000 == 0x0)\n\
361 .elseif (\\imm & 0xffff0000 == 0xffff0000)\n\
362 addi \\rt,%0,\\imm\n\
363 .elseif (\\imm & 0x0000ffff == 0)
364 lui \\rt,%uhi(\\imm)\n\
366 lui \\rt,%uhi(\\imm)\n\
367 ori \\rt,\\rt,%lo(\\imm)\n\
370 static iq2000_macro_defs_s iq2000_macro_defs
[] = {
371 {"abs", (const char **)&abs_expn
, (const char **)&abs_args
},
372 {"la", (const char **)&la_expn
, (const char **)&la_args
},
373 {"bge", (const char **)&bge_expn
, (const char **)&bxx_args
},
374 {"bgeu", (const char **)&bgeu_expn
, (const char **)&bxx_args
},
375 {"bgt", (const char **)&bgt_expn
, (const char **)&bxx_args
},
376 {"bgtu", (const char **)&bgtu_expn
, (const char **)&bxx_args
},
377 {"ble", (const char **)&ble_expn
, (const char **)&bxx_args
},
378 {"bleu", (const char **)&bleu_expn
, (const char **)&bxx_args
},
379 {"blt", (const char **)&blt_expn
, (const char **)&bxx_args
},
380 {"bltu", (const char **)&bltu_expn
, (const char **)&bxx_args
},
381 {"sge", (const char **)&sge_expn
, (const char **)&sxx_args
},
382 {"sgeu", (const char **)&sgeu_expn
, (const char **)&sxx_args
},
383 {"sle", (const char **)&sle_expn
, (const char **)&sxx_args
},
384 {"sleu", (const char **)&sleu_expn
, (const char **)&sxx_args
},
385 {"sgt", (const char **)&sgt_expn
, (const char **)&sxx_args
},
386 {"sgtu", (const char **)&sgtu_expn
, (const char **)&sxx_args
},
387 {"seq", (const char **)&seq_expn
, (const char **)&sxx_args
},
388 {"sne", (const char **)&sne_expn
, (const char **)&sxx_args
},
389 {"neg", (const char **)&neg_expn
, (const char **)&neg_args
},
390 {"negu", (const char **)&negu_expn
, (const char **)&neg_args
},
391 {"li", (const char **)&li_expn
, (const char **)&li_args
},
392 {"ori32", (const char **)&ori32_expn
, (const char **)&ai32_args
},
393 {"andi32",(const char **)&andi32_expn
,(const char **)&ai32_args
},
397 iq2000_load_macros ()
400 int mcnt
= sizeof (iq2000_macro_defs
) / sizeof (iq2000_macro_defs_s
);
402 for (i
= 0; i
< mcnt
; i
++)
403 iq2000_add_macro (iq2000_macro_defs
[i
].mnemonic
,
404 *iq2000_macro_defs
[i
].expansion
,
405 iq2000_macro_defs
[i
].args
);
411 /* Allow all iq2k macros in iq10, instead of just LA. */
412 iq2000_load_macros ();
414 char *la_sem
= "\n lui \\reg,%hi(\\label)\n ori \\reg,\\reg,%lo(\\label)\n";
416 char *la_arg_1
= "reg";
417 char *la_arg_2
= "label";
418 const char *la_args
[3] = { la_arg_1
, la_arg_2
, NULL
};
420 iq2000_add_macro ("la", la_sem
, la_args
);
429 static long delayed_load_register
= 0;
430 static int last_insn_had_delay_slot
= 0;
431 static int last_insn_has_load_delay
= 0;
432 static int last_insn_unconditional_jump
= 0;
433 static int last_insn_was_ldw
= 0;
438 /* Initialize GAS's cgen interface for a new instruction. */
439 gas_cgen_init_parse ();
441 insn
.insn
= iq2000_cgen_assemble_insn
442 (gas_cgen_cpu_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
446 as_bad ("%s", errmsg
);
450 /* Doesn't really matter what we pass for RELAX_P here. */
451 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
452 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
454 /* We need to generate an error if there's a yielding instruction in the delay
455 slot of a control flow modifying instruction (jump (yes), load (no)) */
456 if ((last_insn_had_delay_slot
&& !last_insn_has_load_delay
) &&
457 CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_YIELD_INSN
))
458 as_bad (_("the yielding instruction %s may not be in a delay slot."),
459 CGEN_INSN_NAME (insn
.insn
));
461 /* Warn about odd numbered base registers for paired-register
462 instructions like LDW. On iq2000, result is always rt. */
463 if (iq2000_mach
== bfd_mach_iq2000
464 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_EVEN_REG_NUM
)
465 && (insn
.fields
.f_rt
% 2))
466 as_bad (_("Register number (R%ld) for double word access must be even."),
469 /* Warn about odd numbered base registers for paired-register
470 instructions like LDW. On iq10, result is always rd. */
471 if (iq2000_mach
== bfd_mach_iq10
472 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_EVEN_REG_NUM
)
473 && (insn
.fields
.f_rd
% 2))
474 as_bad (_("Register number (R%ld) for double word access must be even."),
477 /* Warn about insns that reference the target of a previous load. */
478 /* NOTE: R0 is a special case and is not subject to load delays (except for ldw). */
479 if (delayed_load_register
&& (last_insn_has_load_delay
|| last_insn_was_ldw
))
481 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_RD
) &&
482 insn
.fields
.f_rd
== delayed_load_register
)
483 as_warn (_("operand references R%ld of previous load."),
486 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_RS
) &&
487 insn
.fields
.f_rs
== delayed_load_register
)
488 as_warn (_("operand references R%ld of previous load."),
491 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_RT
) &&
492 insn
.fields
.f_rt
== delayed_load_register
)
493 as_warn (_("operand references R%ld of previous load."),
496 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_R31
) &&
497 delayed_load_register
== 31)
498 as_warn (_("instruction implicitly accesses R31 of previous load."));
501 /* Warn about insns that reference the (target + 1) of a previous ldw */
502 if (last_insn_was_ldw
)
504 if ((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_RD
)
505 && insn
.fields
.f_rd
== delayed_load_register
+ 1)
506 || (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_RS
)
507 && insn
.fields
.f_rs
== delayed_load_register
+ 1)
508 || (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_USES_RT
)
509 && insn
.fields
.f_rt
== delayed_load_register
+ 1))
510 as_warn (_("operand references R%ld of previous load."),
511 delayed_load_register
+ 1);
514 last_insn_had_delay_slot
=
515 CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_DELAY_SLOT
);
517 last_insn_has_load_delay
=
518 CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_LOAD_DELAY
);
520 if (last_insn_unconditional_jump
)
521 last_insn_has_load_delay
= last_insn_unconditional_jump
= 0;
522 else if (! strcmp (CGEN_INSN_MNEMONIC (insn
.insn
), "j")
523 || ! strcmp (CGEN_INSN_MNEMONIC (insn
.insn
), "jal"))
524 last_insn_unconditional_jump
= 1;
526 /* The meaning of EVEN_REG_NUM was overloaded to also imply LDW. Since that's
527 not true for IQ10, let's make the above logic specific to LDW. */
528 last_insn_was_ldw
= ! strcmp ("ldw", CGEN_INSN_NAME (insn
.insn
));
530 /* The assumption here is that the target of a load is always rt.
531 That is true for iq2000 & iq10. */
532 delayed_load_register
= insn
.fields
.f_rt
;
536 md_section_align (segment
, size
)
540 int align
= bfd_get_section_alignment (stdoutput
, segment
);
541 return ((size
+ (1 << align
) - 1) & (-1 << align
));
546 md_undefined_symbol (name
)
547 char * name ATTRIBUTE_UNUSED
;
552 /* Interface to relax_segment. */
554 /* Return an initial guess of the length by which a fragment must grow to
555 hold a branch to reach its destination.
556 Also updates fr_type/fr_subtype as necessary.
558 Called just before doing relaxation.
559 Any symbol that is now undefined will not become defined.
560 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
561 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
562 Although it may not be explicit in the frag, pretend fr_var starts with a
566 md_estimate_size_before_relax (fragP
, segment
)
568 segT segment ATTRIBUTE_UNUSED
;
570 int old_fr_fix
= fragP
->fr_fix
;
572 /* The only thing we have to handle here are symbols outside of the
573 current segment. They may be undefined or in a different segment in
574 which case linker scripts may place them anywhere.
575 However, we can't finish the fragment here and emit the reloc as insn
576 alignment requirements may move the insn about. */
578 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
581 /* *fragP has been relaxed to its final size, and now needs to have
582 the bytes inside it modified to conform to the new size.
584 Called after relaxation is finished.
585 fragP->fr_type == rs_machine_dependent.
586 fragP->fr_subtype is the subtype of what the address relaxed to. */
589 md_convert_frag (abfd
, sec
, fragP
)
590 bfd
* abfd ATTRIBUTE_UNUSED
;
591 segT sec ATTRIBUTE_UNUSED
;
592 fragS
* fragP ATTRIBUTE_UNUSED
;
597 /* Functions concerning relocs. */
600 md_pcrel_from_section (fixP
, sec
)
604 if (fixP
->fx_addsy
!= (symbolS
*) NULL
605 && (! S_IS_DEFINED (fixP
->fx_addsy
)
606 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
608 /* The symbol is undefined (or is defined but not in this section).
609 Let the linker figure it out. */
613 /* return the address of the delay slot */
614 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
617 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
618 Returns BFD_RELOC_NONE if no reloc type can be found.
619 *FIXP may be modified if desired. */
621 bfd_reloc_code_real_type
622 md_cgen_lookup_reloc (insn
, operand
, fixP
)
623 const CGEN_INSN
* insn ATTRIBUTE_UNUSED
;
624 const CGEN_OPERAND
* operand
;
625 fixS
* fixP ATTRIBUTE_UNUSED
;
627 switch (operand
->type
)
629 case IQ2000_OPERAND_OFFSET
:
630 return BFD_RELOC_16_PCREL_S2
;
631 case IQ2000_OPERAND_JMPTARG
:
632 return BFD_RELOC_IQ2000_OFFSET_16
;
633 case IQ2000_OPERAND_JMPTARGQ10
:
634 if (iq2000_mach
== bfd_mach_iq10
)
635 return BFD_RELOC_IQ2000_OFFSET_21
;
636 return BFD_RELOC_NONE
;
637 case IQ2000_OPERAND_HI16
:
638 return BFD_RELOC_HI16
;
639 case IQ2000_OPERAND_LO16
:
640 return BFD_RELOC_LO16
;
642 /* Pacify gcc -Wall. */
643 return BFD_RELOC_NONE
;
646 return BFD_RELOC_NONE
;
649 /* Record a HI16 reloc for later matching with its LO16 cousin. */
652 iq2000_record_hi16 (reloc_type
, fixP
, seg
)
655 segT seg ATTRIBUTE_UNUSED
;
657 struct iq2000_hi_fixup
* hi_fixup
;
659 assert (reloc_type
== BFD_RELOC_HI16
);
661 hi_fixup
= ((struct iq2000_hi_fixup
*)
662 xmalloc (sizeof (struct iq2000_hi_fixup
)));
663 hi_fixup
->fixp
= fixP
;
664 hi_fixup
->seg
= now_seg
;
665 hi_fixup
->next
= iq2000_hi_fixup_list
;
667 iq2000_hi_fixup_list
= hi_fixup
;
670 /* Called while parsing an instruction to create a fixup.
671 We need to check for HI16 relocs and queue them up for later sorting. */
674 iq2000_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
677 const CGEN_INSN
* insn
;
679 const CGEN_OPERAND
* operand
;
683 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
684 operand
, opinfo
, exp
);
686 switch (operand
->type
)
688 case IQ2000_OPERAND_HI16
:
689 /* If low/high was used, it is recorded in `opinfo'. */
690 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_HI16
691 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_LO16
)
692 iq2000_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
694 default : /* avoid -Wall warning */
701 /* Return BFD reloc type from opinfo field in a fixS.
702 It's tricky using fx_r_type in iq2000_frob_file because the values
703 are BFD_RELOC_UNUSED + operand number. */
704 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
706 /* Sort any unmatched HI16 relocs so that they immediately precede
707 the corresponding LO16 reloc. This is called before md_apply_fix3 and
713 struct iq2000_hi_fixup
* l
;
715 for (l
= iq2000_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
717 segment_info_type
* seginfo
;
720 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_HI16
721 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_LO16
);
723 /* Check quickly whether the next fixup happens to be a matching low. */
724 if (l
->fixp
->fx_next
!= NULL
725 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_LO16
726 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
727 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
730 /* Look through the fixups for this segment for a matching
731 `low'. When we find one, move the high just in front of it.
732 We do this in two passes. In the first pass, we try to find
733 a unique `low'. In the second pass, we permit multiple
734 high's relocs for a single `low'. */
735 seginfo
= seg_info (l
->seg
);
736 for (pass
= 0; pass
< 2; pass
++)
742 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
744 /* Check whether this is a `low' fixup which matches l->fixp. */
745 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_LO16
746 && f
->fx_addsy
== l
->fixp
->fx_addsy
747 && f
->fx_offset
== l
->fixp
->fx_offset
750 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_HI16
)
751 || prev
->fx_addsy
!= f
->fx_addsy
752 || prev
->fx_offset
!= f
->fx_offset
))
756 /* Move l->fixp before f. */
757 for (pf
= &seginfo
->fix_root
;
759 pf
= & (* pf
)->fx_next
)
760 assert (* pf
!= NULL
);
762 * pf
= l
->fixp
->fx_next
;
764 l
->fixp
->fx_next
= f
;
766 seginfo
->fix_root
= l
->fixp
;
768 prev
->fx_next
= l
->fixp
;
780 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
781 _("Unmatched high relocation"));
786 /* See whether we need to force a relocation into the output file. */
789 iq2000_force_relocation (fix
)
792 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
793 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
799 /* Handle the .set pseudo-op. */
803 int x ATTRIBUTE_UNUSED
;
805 char *name
= input_line_pointer
, ch
;
806 char *save_ILP
= input_line_pointer
;
808 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
809 input_line_pointer
++;
810 ch
= *input_line_pointer
;
811 *input_line_pointer
= '\0';
813 if (strcmp (name
, "reorder") == 0)
816 else if (strcmp (name
, "noreorder") == 0)
819 else if (strcmp (name
, "at") == 0)
822 else if (strcmp (name
, "noat") == 0)
825 else if (strcmp (name
, "macro") == 0)
828 else if (strcmp (name
, "nomacro") == 0)
831 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
834 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
837 else if (strcmp (name
, "bopt") == 0)
840 else if (strcmp (name
, "nobopt") == 0)
845 /* We'd like to be able to use .set symbol, expn */
846 input_line_pointer
= save_ILP
;
849 /*as_warn (_("Tried to set unrecognized symbol: %s\n"), name);*/
851 *input_line_pointer
= ch
;
852 demand_empty_rest_of_line ();
855 /* Write a value out to the object file, using the appropriate endianness. */
858 md_number_to_chars (buf
, val
, n
)
863 number_to_chars_bigendian (buf
, val
, n
);
870 /* In case of a syntax error, escape back to try next syntax combo. */
871 if (exp
->X_op
== O_absent
)
872 gas_cgen_md_operand (exp
);
875 /* Turn a string in input_line_pointer into a floating point constant
876 of type type, and store the appropriate bytes in *litP. The number
877 of LITTLENUMS emitted is stored in *sizeP . An error message is
878 returned, or NULL on OK. */
880 /* Equal to MAX_PRECISION in atof-ieee.c */
881 #define MAX_LITTLENUMS 6
884 md_atof (type
, litP
, sizeP
)
891 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
911 /* FIXME: Some targets allow other format chars for bigger sizes here. */
915 return _("Bad call to md_atof()");
918 t
= atof_ieee (input_line_pointer
, type
, words
);
920 input_line_pointer
= t
;
921 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
923 for (i
= 0; i
< prec
; i
++)
925 md_number_to_chars (litP
, (valueT
) words
[i
],
926 sizeof (LITTLENUM_TYPE
));
927 litP
+= sizeof (LITTLENUM_TYPE
);
935 iq2000_fix_adjustable (fixP
)
938 bfd_reloc_code_real_type reloc_type
;
940 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
942 const CGEN_INSN
*insn
= NULL
;
943 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
944 const CGEN_OPERAND
*operand
= cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
945 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
948 reloc_type
= fixP
->fx_r_type
;
950 if (fixP
->fx_addsy
== NULL
)
953 /* Prevent all adjustments to global symbols. */
954 if (S_IS_EXTERN (fixP
->fx_addsy
))
957 if (S_IS_WEAK (fixP
->fx_addsy
))
960 /* We need the symbol name for the VTABLE entries. */
961 if ( reloc_type
== BFD_RELOC_VTABLE_INHERIT
962 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)
974 /* The ELF backend needs to know that we are changing sections, so
975 that .previous works correctly. We could do something like check
976 for a obj_section_change_hook macro, but that might be confusing
977 as it would not be appropriate to use it in the section changing
978 functions in read.c, since obj-elf.c intercepts those. FIXME:
979 This should be cleaner, somehow. */
980 obj_elf_section_change_hook ();
983 /* iq2000_emit_delays (false); */
997 /* The .end directive. */
1001 int x ATTRIBUTE_UNUSED
;
1006 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1009 demand_empty_rest_of_line ();
1014 if (1/*iq2000_mach == bfd_mach_iq2000*/)
1016 #ifdef BFD_ASSEMBLER
1017 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
1022 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
1029 as_warn (_(".end not in text section"));
1033 as_warn (_(".end directive without a preceding .ent directive."));
1034 demand_empty_rest_of_line ();
1040 assert (S_GET_NAME (p
));
1041 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
1042 as_warn (_(".end symbol does not match .ent symbol."));
1045 as_warn (_(".end directive missing or unknown symbol"));
1049 cur_proc_ptr
= NULL
;
1052 /* The .aent and .ent directives. */
1062 if (1/*iq2000_mach == bfd_mach_iq2000*/)
1064 symbolP
= get_symbol ();
1065 if (*input_line_pointer
== ',')
1066 input_line_pointer
++;
1068 if (ISDIGIT (*input_line_pointer
) || *input_line_pointer
== '-')
1069 number
= get_number ();
1071 #ifdef BFD_ASSEMBLER
1072 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
1077 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
1084 as_warn (_(".ent or .aent not in text section."));
1086 if (!aent
&& cur_proc_ptr
)
1087 as_warn (_("missing `.end'"));
1091 cur_proc_ptr
= &cur_proc
;
1092 memset (cur_proc_ptr
, '\0', sizeof (procS
));
1094 cur_proc_ptr
->isym
= symbolP
;
1096 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
1102 as_bad (_("unknown pseudo-op: `%s'"), ".ent");
1104 demand_empty_rest_of_line ();
1107 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
1108 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
1109 s_iq2000_frame is used so that we can set the PDR information correctly.
1110 We can't use the ecoff routines because they make reference to the ecoff
1111 symbol table (in the mdebug section). */
1114 s_iq2000_frame (ignore
)
1120 /* The .fmask and .mask directives. If the mdebug section is present
1121 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
1122 embedded targets, s_iq2000_mask is used so that we can set the PDR
1123 information correctly. We can't use the ecoff routines because they
1124 make reference to the ecoff symbol table (in the mdebug section). */
1127 s_iq2000_mask (reg_type
)
1130 s_ignore (reg_type
);
1140 name
= input_line_pointer
;
1141 c
= get_symbol_end ();
1142 p
= (symbolS
*) symbol_find_or_make (name
);
1143 *input_line_pointer
= c
;
1153 if (*input_line_pointer
== '-')
1155 ++input_line_pointer
;
1159 if (! ISDIGIT (*input_line_pointer
))
1160 as_bad (_("Expected simple number."));
1162 if (input_line_pointer
[0] == '0')
1164 if (input_line_pointer
[1] == 'x')
1166 input_line_pointer
+= 2;
1167 while (ISXDIGIT (*input_line_pointer
))
1170 val
|= hex_value (*input_line_pointer
++);
1172 return negative
? -val
: val
;
1176 ++input_line_pointer
;
1178 while (ISDIGIT (*input_line_pointer
))
1181 val
|= *input_line_pointer
++ - '0';
1183 return negative
? -val
: val
;
1187 if (! ISDIGIT (*input_line_pointer
))
1189 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
1190 *input_line_pointer
, *input_line_pointer
);
1191 as_warn (_("Invalid number"));
1195 while (ISDIGIT (*input_line_pointer
))
1198 val
+= *input_line_pointer
++ - '0';
1201 return negative
? -val
: val
;