1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link
*next
;
37 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
39 /* Structure to hold all of the different components describing an individual instruction. */
42 const CGEN_INSN
* insn
;
43 const CGEN_INSN
* orig_insn
;
46 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
48 char buffer
[CGEN_MAX_INSN_SIZE
];
53 fixS
* fixups
[CGEN_MAX_FIXUPS
];
54 int indices
[MAX_OPERAND_INSTANCES
];
55 sym_linkS
*debug_sym_link
;
59 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
60 boundary (i.e. was the first of two 16 bit insns). */
61 static m32r_insn prev_insn
;
63 /* Non-zero if we've seen a relaxable insn since the last 32 bit
65 static int seen_relaxable_p
= 0;
67 /* Non-zero if -relax specified, in which case sufficient relocs are output
68 for the linker to do relaxing.
69 We do simple forms of relaxing internally, but they are always done.
70 This flag does not apply to them. */
71 static int m32r_relax
;
73 /* If non-NULL, pointer to cpu description file to read.
74 This allows runtime additions to the assembler. */
75 static char * m32r_cpu_desc
;
77 /* start-sanitize-m32rx */
78 /* Non-zero if -m32rx has been specified, in which case support for the
79 extended M32RX instruction set should be enabled. */
80 static int enable_m32rx
= 0;
82 /* Non-zero if the programmer should be warned when an explicit parallel
83 instruction might have constraint violations. */
84 static int warn_explicit_parallel_conflicts
= 1;
86 /* Non-zero if insns can be made parallel. */
88 /* end-sanitize-m32rx */
90 /* stuff for .scomm symbols. */
91 static segT sbss_section
;
92 static asection scom_section
;
93 static asymbol scom_symbol
;
95 const char comment_chars
[] = ";";
96 const char line_comment_chars
[] = "#";
97 const char line_separator_chars
[] = "";
98 const char EXP_CHARS
[] = "eE";
99 const char FLT_CHARS
[] = "dD";
101 /* Relocations against symbols are done in two
102 parts, with a HI relocation and a LO relocation. Each relocation
103 has only 16 bits of space to store an addend. This means that in
104 order for the linker to handle carries correctly, it must be able
105 to locate both the HI and the LO relocation. This means that the
106 relocations must appear in order in the relocation table.
108 In order to implement this, we keep track of each unmatched HI
109 relocation. We then sort them so that they immediately precede the
110 corresponding LO relocation. */
114 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
115 fixS
* fixp
; /* This fixup. */
116 segT seg
; /* The section this fixup is in. */
120 /* The list of unmatched HI relocs. */
122 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
125 /* start-sanitize-m32rx */
132 if (stdoutput
!= NULL
)
133 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
134 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
136 /* end-sanitize-m32rx */
138 #define M32R_SHORTOPTS ""
139 /* start-sanitize-m32rx */
140 #undef M32R_SHORTOPTS
141 #define M32R_SHORTOPTS "O"
142 /* end-sanitize-m32rx */
143 const char * md_shortopts
= M32R_SHORTOPTS
;
145 struct option md_longopts
[] =
147 /* start-sanitize-m32rx */
148 #define OPTION_M32RX (OPTION_MD_BASE)
149 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
150 #define OPTION_WARN (OPTION_MD_BASE + 1)
151 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN
},
152 {"Wp", no_argument
, NULL
, OPTION_WARN
},
153 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
154 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN
},
155 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN
},
156 /* end-sanitize-m32rx */
158 #if 0 /* not supported yet */
159 #define OPTION_RELAX (OPTION_MD_BASE + 3)
160 {"relax", no_argument
, NULL
, OPTION_RELAX
},
161 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
162 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
165 {NULL
, no_argument
, NULL
, 0}
167 size_t md_longopts_size
= sizeof (md_longopts
);
170 md_parse_option (c
, arg
)
176 /* start-sanitize-m32rx */
186 warn_explicit_parallel_conflicts
= 1;
190 warn_explicit_parallel_conflicts
= 0;
192 /* end-sanitize-m32rx */
194 #if 0 /* not supported yet */
198 case OPTION_CPU_DESC
:
209 md_show_usage (stream
)
212 /* start-sanitize-m32rx */
213 fprintf (stream
, _("M32R/X specific command line options:\n"));
214 fprintf (stream
, _("\
215 --m32rx support the extended m32rx instruction set\n"));
217 fprintf (stream
, _("\
218 -O try to combine instructions in parallel\n"));
220 fprintf (stream
, _("\
221 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
222 fprintf (stream
, _("\
223 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
224 fprintf (stream
, _("\
225 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
226 fprintf (stream
, _("\
227 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
228 /* end-sanitize-m32rx */
231 fprintf (stream
, _("\
232 --relax create linker relaxable code\n"));
233 fprintf (stream
, _("\
234 --cpu-desc provide runtime cpu description file\n"));
238 static void fill_insn
PARAMS ((int));
239 static void m32r_scomm
PARAMS ((int));
240 static void debug_sym
PARAMS ((int));
241 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
243 /* Set by md_assemble for use by m32r_fill_insn. */
244 static subsegT prev_subseg
;
245 static segT prev_seg
;
247 /* The target specific pseudo-ops which we support. */
248 const pseudo_typeS md_pseudo_table
[] =
251 { "fillinsn", fill_insn
, 0 },
252 { "scomm", m32r_scomm
, 0 },
253 { "debugsym", debug_sym
, 0 },
254 /* start-sanitize-m32rx */
255 { "m32r", allow_m32rx
, 0 },
256 { "m32rx", allow_m32rx
, 1 },
257 /* end-sanitize-m32rx */
261 /* FIXME: Should be machine generated. */
262 #define NOP_INSN 0x7000
263 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
265 /* When we align the .text section, insert the correct NOP pattern.
266 N is the power of 2 alignment. LEN is the length of pattern FILL.
267 MAX is the maximum number of characters to skip when doing the alignment,
268 or 0 if there is no maximum. */
271 m32r_do_align (n
, fill
, len
, max
)
277 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
278 && (now_seg
->flags
& SEC_CODE
) != 0
279 /* Only do this special handling if aligning to at least a
282 /* Only do this special handling if we're allowed to emit at
284 && (max
== 0 || max
> 1))
286 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
289 /* First align to a 2 byte boundary, in case there is an odd .byte. */
290 /* FIXME: How much memory will cause gas to use when assembling a big
291 program? Perhaps we can avoid the frag_align call? */
292 frag_align (1, 0, 0);
294 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
296 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
297 /* If doing larger alignments use a repeating sequence of appropriate
301 static const unsigned char multi_nop_pattern
[] =
302 { 0x70, 0x00, 0xf0, 0x00 };
303 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
313 assemble_nop (opcode
)
316 char * f
= frag_more (2);
317 md_number_to_chars (f
, opcode
, 2);
320 /* If the last instruction was the first of 2 16 bit insns,
321 output a nop to move the PC to a 32 bit boundary.
323 This is done via an alignment specification since branch relaxing
324 may make it unnecessary.
326 Internally, we need to output one of these each time a 32 bit insn is
327 seen after an insn that is relaxable. */
333 (void) m32r_do_align (2, NULL
, 0, 0);
334 prev_insn
.insn
= NULL
;
335 seen_relaxable_p
= 0;
338 /* Record the symbol so that when we output the insn, we can create
339 a symbol that is at the start of the instruction. This is used
340 to emit the label for the start of a breakpoint without causing
341 the assembler to emit a NOP if the previous instruction was a
342 16 bit instruction. */
350 register char *end_name
;
351 register symbolS
*symbolP
;
352 register sym_linkS
*link
;
354 name
= input_line_pointer
;
355 delim
= get_symbol_end ();
356 end_name
= input_line_pointer
;
358 if ((symbolP
= symbol_find (name
)) == NULL
359 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
361 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
364 symbol_table_insert (symbolP
);
365 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
366 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
370 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
371 link
->symbol
= symbolP
;
372 link
->next
= debug_sym_link
;
373 debug_sym_link
= link
;
378 demand_empty_rest_of_line ();
381 /* Second pass to expanding the debug symbols, go through linked
382 list of symbols and reassign the address. */
385 expand_debug_syms (syms
, align
)
389 char *save_input_line
= input_line_pointer
;
390 sym_linkS
*next_syms
;
396 (void) m32r_do_align (align
, NULL
, 0, 0);
397 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
399 symbolS
*symbolP
= syms
->symbol
;
400 next_syms
= syms
->next
;
401 input_line_pointer
= ".\n";
402 pseudo_set (symbolP
);
406 input_line_pointer
= save_input_line
;
409 /* Cover function to fill_insn called after a label and at end of assembly.
411 The result is always 1: we're called in a conditional to see if the
412 current line is a label. */
415 m32r_fill_insn (done
)
418 if (prev_seg
!= NULL
)
421 subsegT subseg
= now_subseg
;
423 subseg_set (prev_seg
, prev_subseg
);
427 subseg_set (seg
, subseg
);
440 /* Initialize the `cgen' interface. */
442 /* This is a callback from cgen to gas to parse operands. */
443 cgen_parse_operand_fn
= cgen_parse_operand
;
445 /* Set the machine number and endian. */
446 CGEN_SYM (init_asm
) (0 /* mach number */,
448 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
450 #if 0 /* not supported yet */
451 /* If a runtime cpu description file was provided, parse it. */
452 if (m32r_cpu_desc
!= NULL
)
456 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
458 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
462 /* Save the current subseg so we can restore it [it's the default one and
463 we don't want the initial section to be .sbss]. */
467 /* The sbss section is for local .scomm symbols. */
468 sbss_section
= subseg_new (".sbss", 0);
470 /* This is copied from perform_an_assembly_pass. */
471 applicable
= bfd_applicable_section_flags (stdoutput
);
472 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
474 #if 0 /* What does this do? [see perform_an_assembly_pass] */
475 seg_info (bss_section
)->bss
= 1;
478 subseg_set (seg
, subseg
);
480 /* We must construct a fake section similar to bfd_com_section
481 but with the name .scommon. */
482 scom_section
= bfd_com_section
;
483 scom_section
.name
= ".scommon";
484 scom_section
.output_section
= & scom_section
;
485 scom_section
.symbol
= & scom_symbol
;
486 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
487 scom_symbol
= * bfd_com_section
.symbol
;
488 scom_symbol
.name
= ".scommon";
489 scom_symbol
.section
= & scom_section
;
491 /* start-sanitize-m32rx */
492 allow_m32rx (enable_m32rx
);
493 /* end-sanitize-m32rx */
496 /* start-sanitize-m32rx */
498 #define OPERAND_IS_COND_BIT(operand, indices, index) \
499 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
500 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
501 && (indices [index] == 0 || indices [index] == 1)))
503 /* Returns true if an output of instruction 'a' is referenced by an operand
504 of instruction 'b'. If 'check_outputs' is true then b's outputs are
505 checked, otherwise its inputs are examined. */
508 first_writes_to_seconds_operands (a
, b
, check_outputs
)
511 const int check_outputs
;
513 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
514 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
517 /* If at least one of the instructions takes no operands, then there is
518 nothing to check. There really are instructions without operands,
520 if (a_operands
== NULL
|| b_ops
== NULL
)
523 /* Scan the operand list of 'a' looking for an output operand. */
525 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
526 a_index
++, a_operands
++)
528 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
531 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
534 The Condition bit 'C' is a shadow of the CBR register (control
535 register 1) and also a shadow of bit 31 of the program status
536 word (control register 0). For now this is handled here, rather
539 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
541 /* Scan operand list of 'b' looking for another reference to the
542 condition bit, which goes in the right direction. */
544 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
545 b_index
++, b_operands
++)
547 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
548 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
549 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
555 /* Scan operand list of 'b' looking for an operand that references
556 the same hardware element, and which goes in the right direction. */
558 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
559 b_index
++, b_operands
++)
561 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
562 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
563 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
564 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
574 /* Returns true if the insn can (potentially) alter the program counter. */
580 #if 0 /* Once PC operands are working.... */
581 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
583 if (a_operands
== NULL
)
586 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
588 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
589 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
595 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
596 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
602 /* Returns NULL if the two 16 bit insns can be executed in parallel,
603 otherwise it returns a pointer to an error message explaining why not. */
606 can_make_parallel (a
, b
)
613 /* Make sure the instructions are the right length. */
614 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
615 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
618 if (first_writes_to_seconds_operands (a
, b
, true))
619 return _("Instructions write to the same destination register.");
621 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
622 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
624 /* Make sure that the instructions use the correct execution pipelines. */
625 if ( a_pipe
== PIPE_NONE
626 || b_pipe
== PIPE_NONE
)
627 return _("Instructions do not use parallel execution pipelines.");
629 /* Leave this test for last, since it is the only test that can
630 go away if the instructions are swapped, and we want to make
631 sure that any other errors are detected before this happens. */
632 if ( a_pipe
== PIPE_S
634 return _("Instructions share the same execution pipeline");
642 make_parallel (buffer
)
643 cgen_insn_t
* buffer
;
645 /* Force the top bit of the second insn to be set. */
649 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
651 value
= bfd_getb16 ((bfd_byte
*) buffer
);
653 bfd_putb16 (value
, (char *) buffer
);
657 value
= bfd_getl16 ((bfd_byte
*) buffer
);
659 bfd_putl16 (value
, (char *) buffer
);
666 make_parallel (buffer
)
669 /* Force the top bit of the second insn to be set. */
671 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
674 #endif /* ! CGEN_INT_INSN */
677 assemble_parallel_insn (str
, str2
)
686 * str2
= 0; /* Seperate the two instructions. */
688 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
689 so that the parallel instruction will start on a 32 bit boundary. */
693 first
.debug_sym_link
= debug_sym_link
;
694 debug_sym_link
= (sym_linkS
*)0;
696 /* Parse the first instruction. */
697 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
698 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
705 /* FIXME: Need standard macro to perform this test. */
706 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
708 as_bad (_("instruction '%s' is for the M32RX only"), str
);
712 /* Check to see if this is an allowable parallel insn. */
713 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
715 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
719 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
720 str3
= str
; /* Save the original string pointer. */
721 str
= str2
+ 2; /* Advanced past the parsed string. */
722 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
724 /* Preserve any fixups that have been generated and reset the list to empty. */
727 /* Get the indices of the operands of the instruction. */
728 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
729 doesn't seem right. Perhaps allow passing fields like we do insn. */
730 /* FIXME: ALIAS insns do not have operands, so we use this function
731 to find the equivalent insn and overwrite the value stored in our
732 structure. We still need the original insn, however, since this
733 may have certain attributes that are not present in the unaliased
734 version (eg relaxability). When aliases behave differently this
735 may have to change. */
736 first
.orig_insn
= first
.insn
;
737 first
.insn
= m32r_cgen_lookup_get_insn_operands (NULL
,
738 bfd_getb16 ((char *) first
.buffer
),
741 if (first
.insn
== NULL
)
742 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
744 second
.debug_sym_link
= NULL
;
746 /* Parse the second instruction. */
747 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
748 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
756 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
758 as_bad (_("instruction '%s' is for the M32RX only"), str
);
762 /* Check to see if this is an allowable parallel insn. */
763 if (CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
765 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
771 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
772 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
774 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
779 /* Get the indices of the operands of the instruction. */
780 second
.orig_insn
= second
.insn
;
781 second
.insn
= m32r_cgen_lookup_get_insn_operands (NULL
,
782 bfd_getb16 ((char *) second
.buffer
),
785 if (second
.insn
== NULL
)
786 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
788 /* We assume that if the first instruction writes to a register that is
789 read by the second instruction it is because the programmer intended
790 this to happen, (after all they have explicitly requested that these
791 two instructions be executed in parallel). Although if the global
792 variable warn_explicit_parallel_conflicts is true then we do generate
793 a warning message. Similarly we assume that parallel branch and jump
794 instructions are deliberate and should not produce errors. */
796 if (warn_explicit_parallel_conflicts
)
798 if (first_writes_to_seconds_operands (& first
, & second
, false))
799 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
801 if (first_writes_to_seconds_operands (& second
, & first
, false))
802 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
805 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
807 /* Get the fixups for the first instruction. */
811 expand_debug_syms (first
.debug_sym_link
, 1);
812 cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
813 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
815 /* Force the top bit of the second insn to be set. */
816 make_parallel (second
.buffer
);
818 /* Get its fixups. */
819 cgen_restore_fixups ();
822 expand_debug_syms (second
.debug_sym_link
, 1);
823 cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
824 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
826 /* Try swapping the instructions to see if they work that way. */
827 else if (can_make_parallel (& second
, & first
) == NULL
)
829 /* Write out the second instruction first. */
830 expand_debug_syms (second
.debug_sym_link
, 1);
831 cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
832 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
834 /* Force the top bit of the first instruction to be set. */
835 make_parallel (first
.buffer
);
837 /* Get the fixups for the first instruction. */
838 cgen_restore_fixups ();
840 /* Write out the first instruction. */
841 expand_debug_syms (first
.debug_sym_link
, 1);
842 cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
843 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
847 as_bad ("'%s': %s", str2
, errmsg
);
851 /* Set these so m32r_fill_insn can use them. */
853 prev_subseg
= now_subseg
;
856 /* end-sanitize-m32rx */
867 /* Initialize GAS's cgen interface for a new instruction. */
868 cgen_asm_init_parse ();
870 /* start-sanitize-m32rx */
871 /* Look for a parallel instruction seperator. */
872 if ((str2
= strstr (str
, "||")) != NULL
)
874 assemble_parallel_insn (str
, str2
);
877 /* end-sanitize-m32rx */
879 insn
.debug_sym_link
= debug_sym_link
;
880 debug_sym_link
= (sym_linkS
*)0;
882 insn
.insn
= CGEN_SYM (assemble_insn
) (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
889 /* start-sanitize-m32rx */
890 if (! enable_m32rx
&& CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
892 as_bad (_("instruction '%s' is for the M32RX only"), str
);
895 /* end-sanitize-m32rx */
897 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
899 /* 32 bit insns must live on 32 bit boundaries. */
900 if (prev_insn
.insn
|| seen_relaxable_p
)
902 /* ??? If calling fill_insn too many times turns us into a memory
903 pig, can we call assemble_nop instead of !seen_relaxable_p? */
907 expand_debug_syms (insn
.debug_sym_link
, 2);
909 /* Doesn't really matter what we pass for RELAX_P here. */
910 cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
911 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
915 int on_32bit_boundary_p
;
916 /* start-sanitize-m32rx */
918 /* end-sanitize-m32rx */
920 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
923 insn
.orig_insn
= insn
.insn
;
924 /* start-sanitize-m32rx */
927 /* Get the indices of the operands of the instruction.
928 FIXME: See assemble_parallel for notes on orig_insn. */
929 insn
.insn
= m32r_cgen_lookup_get_insn_operands (NULL
,
930 bfd_getb16 ((char *) insn
.buffer
),
933 if (insn
.insn
== NULL
)
934 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
936 /* end-sanitize-m32rx */
938 /* Compute whether we're on a 32 bit boundary or not.
939 prev_insn.insn is NULL when we're on a 32 bit boundary. */
940 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
942 /* start-sanitize-m32rx */
943 /* Look to see if this instruction can be combined with the
944 previous instruction to make one, parallel, 32 bit instruction.
945 If the previous instruction (potentially) changed the flow of
946 program control, then it cannot be combined with the current
947 instruction. If the current instruction is relaxable, then it
948 might be replaced with a longer version, so we cannot combine it.
949 Also if the output of the previous instruction is used as an
950 input to the current instruction then it cannot be combined.
951 Otherwise call can_make_parallel() with both orderings of the
952 instructions to see if they can be combined. */
953 if ( ! on_32bit_boundary_p
956 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
957 && ! writes_to_pc (& prev_insn
)
958 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
961 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
962 make_parallel (insn
.buffer
);
963 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
966 /* end-sanitize-m32rx */
968 expand_debug_syms (insn
.debug_sym_link
, 1);
974 /* Ensure each pair of 16 bit insns is in the same frag. */
977 cgen_asm_finish_insn (insn
.orig_insn
, insn
.buffer
,
978 CGEN_FIELDS_BITSIZE (& insn
.fields
),
982 insn
.num_fixups
= fi
.num_fixups
;
983 for (i
= 0; i
< fi
.num_fixups
; ++i
)
984 insn
.fixups
[i
] = fi
.fixups
[i
];
987 /* start-sanitize-m32rx */
992 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
994 /* Swap the two insns */
995 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
996 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
998 make_parallel (insn
.addr
);
1000 /* Swap any relaxable frags recorded for the two insns. */
1001 /* FIXME: Clarify. relaxation precludes parallel insns */
1002 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1003 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1004 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1005 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1007 /* Update the addresses in any fixups.
1008 Note that we don't have to handle the case where each insn is in
1009 a different frag as we ensure they're in the same frag above. */
1010 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1011 prev_insn
.fixups
[i
]->fx_where
+= 2;
1012 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1013 insn
.fixups
[i
]->fx_where
-= 2;
1015 /* end-sanitize-m32rx */
1017 /* Keep track of whether we've seen a pair of 16 bit insns.
1018 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1019 if (on_32bit_boundary_p
)
1022 prev_insn
.insn
= NULL
;
1024 /* If the insn needs the following one to be on a 32 bit boundary
1025 (e.g. subroutine calls), fill this insn's slot. */
1026 if (on_32bit_boundary_p
1027 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1030 /* If this is a relaxable insn (can be replaced with a larger version)
1031 mark the fact so that we can emit an alignment directive for a
1032 following 32 bit insn if we see one. */
1033 if (CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1034 seen_relaxable_p
= 1;
1037 /* Set these so m32r_fill_insn can use them. */
1039 prev_subseg
= now_subseg
;
1042 /* The syntax in the manual says constants begin with '#'.
1043 We just ignore it. */
1046 md_operand (expressionP
)
1047 expressionS
* expressionP
;
1049 if (* input_line_pointer
== '#')
1051 input_line_pointer
++;
1052 expression (expressionP
);
1057 md_section_align (segment
, size
)
1061 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1062 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1066 md_undefined_symbol (name
)
1072 /* .scomm pseudo-op handler.
1074 This is a new pseudo-op to handle putting objects in .scommon.
1075 By doing this the linker won't need to do any work and more importantly
1076 it removes the implicit -G arg necessary to correctly link the object file.
1083 register char * name
;
1087 register symbolS
* symbolP
;
1091 name
= input_line_pointer
;
1092 c
= get_symbol_end ();
1094 /* just after name is now '\0' */
1095 p
= input_line_pointer
;
1098 if (* input_line_pointer
!= ',')
1100 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1101 ignore_rest_of_line ();
1105 input_line_pointer
++; /* skip ',' */
1106 if ((size
= get_absolute_expression ()) < 0)
1108 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1109 ignore_rest_of_line ();
1113 /* The third argument to .scomm is the alignment. */
1114 if (* input_line_pointer
!= ',')
1118 ++ input_line_pointer
;
1119 align
= get_absolute_expression ();
1122 as_warn (_("ignoring bad alignment"));
1126 /* Convert to a power of 2 alignment. */
1129 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1133 as_bad (_("Common alignment not a power of 2"));
1134 ignore_rest_of_line ();
1142 symbolP
= symbol_find_or_make (name
);
1145 if (S_IS_DEFINED (symbolP
))
1147 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1148 S_GET_NAME (symbolP
));
1149 ignore_rest_of_line ();
1153 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1155 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1156 S_GET_NAME (symbolP
),
1157 (long) S_GET_VALUE (symbolP
),
1160 ignore_rest_of_line ();
1166 segT old_sec
= now_seg
;
1167 int old_subsec
= now_subseg
;
1170 record_alignment (sbss_section
, align2
);
1171 subseg_set (sbss_section
, 0);
1174 frag_align (align2
, 0, 0);
1176 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1177 symbolP
->sy_frag
->fr_symbol
= 0;
1179 symbolP
->sy_frag
= frag_now
;
1181 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1184 S_SET_SIZE (symbolP
, size
);
1185 S_SET_SEGMENT (symbolP
, sbss_section
);
1186 S_CLEAR_EXTERNAL (symbolP
);
1187 subseg_set (old_sec
, old_subsec
);
1191 S_SET_VALUE (symbolP
, (valueT
) size
);
1192 S_SET_ALIGN (symbolP
, align2
);
1193 S_SET_EXTERNAL (symbolP
);
1194 S_SET_SEGMENT (symbolP
, & scom_section
);
1197 demand_empty_rest_of_line ();
1200 /* Interface to relax_segment. */
1202 /* FIXME: Build table by hand, get it working, then machine generate. */
1204 const relax_typeS md_relax_table
[] =
1207 1) most positive reach of this state,
1208 2) most negative reach of this state,
1209 3) how many bytes this mode will add to the size of the current frag
1210 4) which index into the table to try if we can't fit into this one. */
1212 /* The first entry must be unused because an `rlx_more' value of zero ends
1216 /* The displacement used by GAS is from the end of the 2 byte insn,
1217 so we subtract 2 from the following. */
1218 /* 16 bit insn, 8 bit disp -> 10 bit range.
1219 This doesn't handle a branch in the right slot at the border:
1220 the "& -4" isn't taken into account. It's not important enough to
1221 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1223 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1224 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1225 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1226 /* Same thing, but with leading nop for alignment. */
1227 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1231 m32r_relax_frag (fragP
, stretch
)
1235 /* Address of branch insn. */
1236 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1239 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1240 if (fragP
->fr_subtype
== 2)
1242 if ((address
& 3) != 0)
1244 fragP
->fr_subtype
= 3;
1248 else if (fragP
->fr_subtype
== 3)
1250 if ((address
& 3) == 0)
1252 fragP
->fr_subtype
= 2;
1258 growth
= relax_frag (fragP
, stretch
);
1260 /* Long jump on odd halfword boundary? */
1261 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1263 fragP
->fr_subtype
= 3;
1271 /* Return an initial guess of the length by which a fragment must grow to
1272 hold a branch to reach its destination.
1273 Also updates fr_type/fr_subtype as necessary.
1275 Called just before doing relaxation.
1276 Any symbol that is now undefined will not become defined.
1277 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1278 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1279 Although it may not be explicit in the frag, pretend fr_var starts with a
1283 md_estimate_size_before_relax (fragP
, segment
)
1287 int old_fr_fix
= fragP
->fr_fix
;
1288 char * opcode
= fragP
->fr_opcode
;
1290 /* The only thing we have to handle here are symbols outside of the
1291 current segment. They may be undefined or in a different segment in
1292 which case linker scripts may place them anywhere.
1293 However, we can't finish the fragment here and emit the reloc as insn
1294 alignment requirements may move the insn about. */
1296 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1298 /* The symbol is undefined in this segment.
1299 Change the relaxation subtype to the max allowable and leave
1300 all further handling to md_convert_frag. */
1301 fragP
->fr_subtype
= 2;
1303 #if 0 /* Can't use this, but leave in for illustration. */
1304 /* Change 16 bit insn to 32 bit insn. */
1307 /* Increase known (fixed) size of fragment. */
1310 /* Create a relocation for it. */
1311 fix_new (fragP
, old_fr_fix
, 4,
1313 fragP
->fr_offset
, 1 /* pcrel */,
1314 /* FIXME: Can't use a real BFD reloc here.
1315 cgen_md_apply_fix3 can't handle it. */
1316 BFD_RELOC_M32R_26_PCREL
);
1318 /* Mark this fragment as finished. */
1322 const CGEN_INSN
* insn
;
1325 /* Update the recorded insn.
1326 Fortunately we don't have to look very far.
1327 FIXME: Change this to record in the instruction the next higher
1328 relaxable insn to use. */
1329 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1331 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1332 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1334 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1340 fragP
->fr_cgen
.insn
= insn
;
1346 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1349 /* *fragP has been relaxed to its final size, and now needs to have
1350 the bytes inside it modified to conform to the new size.
1352 Called after relaxation is finished.
1353 fragP->fr_type == rs_machine_dependent.
1354 fragP->fr_subtype is the subtype of what the address relaxed to. */
1357 md_convert_frag (abfd
, sec
, fragP
)
1363 char * displacement
;
1369 opcode
= fragP
->fr_opcode
;
1371 /* Address opcode resides at in file space. */
1372 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1374 switch (fragP
->fr_subtype
)
1378 displacement
= & opcode
[1];
1383 displacement
= & opcode
[1];
1386 opcode
[2] = opcode
[0] | 0x80;
1387 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1388 opcode_address
+= 2;
1390 displacement
= & opcode
[3];
1396 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1398 /* symbol must be resolved by linker */
1399 if (fragP
->fr_offset
& 3)
1400 as_warn (_("Addend to unresolved symbol not on word boundary."));
1401 addend
= fragP
->fr_offset
>> 2;
1405 /* Address we want to reach in file space. */
1406 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1407 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1408 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1411 /* Create a relocation for symbols that must be resolved by the linker.
1412 Otherwise output the completed insn. */
1414 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1416 assert (fragP
->fr_subtype
!= 1);
1417 assert (fragP
->fr_cgen
.insn
!= 0);
1418 cgen_record_fixup (fragP
,
1419 /* Offset of branch insn in frag. */
1420 fragP
->fr_fix
+ extension
- 4,
1421 fragP
->fr_cgen
.insn
,
1423 /* FIXME: quick hack */
1425 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1427 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1429 fragP
->fr_cgen
.opinfo
,
1430 fragP
->fr_symbol
, fragP
->fr_offset
);
1433 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1435 md_number_to_chars (displacement
, (valueT
) addend
,
1436 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1438 fragP
->fr_fix
+= extension
;
1441 /* Functions concerning relocs. */
1443 /* The location from which a PC relative jump should be calculated,
1444 given a PC relative reloc. */
1447 md_pcrel_from_section (fixP
, sec
)
1451 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1452 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1453 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1455 /* The symbol is undefined (or is defined but not in this section).
1456 Let the linker figure it out. */
1460 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1463 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1464 Returns BFD_RELOC_NONE if no reloc type can be found.
1465 *FIXP may be modified if desired. */
1467 bfd_reloc_code_real_type
1468 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1469 const CGEN_INSN
* insn
;
1470 const CGEN_OPERAND
* operand
;
1473 switch (CGEN_OPERAND_TYPE (operand
))
1475 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1476 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1477 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1478 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1479 case M32R_OPERAND_HI16
:
1480 case M32R_OPERAND_SLO16
:
1481 case M32R_OPERAND_ULO16
:
1482 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1483 if (fixP
->tc_fix_data
.opinfo
!= 0)
1484 return fixP
->tc_fix_data
.opinfo
;
1487 return BFD_RELOC_NONE
;
1490 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1493 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1498 struct m32r_hi_fixup
* hi_fixup
;
1500 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1501 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1503 hi_fixup
= ((struct m32r_hi_fixup
*)
1504 xmalloc (sizeof (struct m32r_hi_fixup
)));
1505 hi_fixup
->fixp
= fixP
;
1506 hi_fixup
->seg
= now_seg
;
1507 hi_fixup
->next
= m32r_hi_fixup_list
;
1509 m32r_hi_fixup_list
= hi_fixup
;
1512 /* Called while parsing an instruction to create a fixup.
1513 We need to check for HI16 relocs and queue them up for later sorting. */
1516 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1519 const CGEN_INSN
* insn
;
1521 const CGEN_OPERAND
* operand
;
1525 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1526 operand
, opinfo
, exp
);
1528 switch (CGEN_OPERAND_TYPE (operand
))
1530 case M32R_OPERAND_HI16
:
1531 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1532 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1533 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1534 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1541 /* Return BFD reloc type from opinfo field in a fixS.
1542 It's tricky using fx_r_type in m32r_frob_file because the values
1543 are BFD_RELOC_UNUSED + operand number. */
1544 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1546 /* Sort any unmatched HI16 relocs so that they immediately precede
1547 the corresponding LO16 reloc. This is called before md_apply_fix and
1553 struct m32r_hi_fixup
* l
;
1555 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1557 segment_info_type
* seginfo
;
1560 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1561 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1563 /* Check quickly whether the next fixup happens to be a matching low. */
1564 if (l
->fixp
->fx_next
!= NULL
1565 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1566 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1567 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1570 /* Look through the fixups for this segment for a matching `low'.
1571 When we find one, move the high/shigh just in front of it. We do
1572 this in two passes. In the first pass, we try to find a
1573 unique `low'. In the second pass, we permit multiple high's
1574 relocs for a single `low'. */
1575 seginfo
= seg_info (l
->seg
);
1576 for (pass
= 0; pass
< 2; pass
++)
1582 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1584 /* Check whether this is a `low' fixup which matches l->fixp. */
1585 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1586 && f
->fx_addsy
== l
->fixp
->fx_addsy
1587 && f
->fx_offset
== l
->fixp
->fx_offset
1590 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1591 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1592 || prev
->fx_addsy
!= f
->fx_addsy
1593 || prev
->fx_offset
!= f
->fx_offset
))
1597 /* Move l->fixp before f. */
1598 for (pf
= &seginfo
->fix_root
;
1600 pf
= & (* pf
)->fx_next
)
1601 assert (* pf
!= NULL
);
1603 * pf
= l
->fixp
->fx_next
;
1605 l
->fixp
->fx_next
= f
;
1607 seginfo
->fix_root
= l
->fixp
;
1609 prev
->fx_next
= l
->fixp
;
1621 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1622 _("Unmatched high/shigh reloc"));
1627 /* See whether we need to force a relocation into the output file.
1628 This is used to force out switch and PC relative relocations when
1632 m32r_force_relocation (fix
)
1638 return (fix
->fx_pcrel
1642 /* Write a value out to the object file, using the appropriate endianness. */
1645 md_number_to_chars (buf
, val
, n
)
1650 if (target_big_endian
)
1651 number_to_chars_bigendian (buf
, val
, n
);
1653 number_to_chars_littleendian (buf
, val
, n
);
1656 /* Turn a string in input_line_pointer into a floating point constant of type
1657 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1658 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1661 /* Equal to MAX_PRECISION in atof-ieee.c */
1662 #define MAX_LITTLENUMS 6
1665 md_atof (type
, litP
, sizeP
)
1672 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1673 LITTLENUM_TYPE
* wordP
;
1675 char * atof_ieee ();
1693 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1697 return _("Bad call to md_atof()");
1700 t
= atof_ieee (input_line_pointer
, type
, words
);
1702 input_line_pointer
= t
;
1703 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1705 if (target_big_endian
)
1707 for (i
= 0; i
< prec
; i
++)
1709 md_number_to_chars (litP
, (valueT
) words
[i
],
1710 sizeof (LITTLENUM_TYPE
));
1711 litP
+= sizeof (LITTLENUM_TYPE
);
1716 for (i
= prec
- 1; i
>= 0; i
--)
1718 md_number_to_chars (litP
, (valueT
) words
[i
],
1719 sizeof (LITTLENUM_TYPE
));
1720 litP
+= sizeof (LITTLENUM_TYPE
);
1728 m32r_elf_section_change_hook ()
1730 /* If we have reached the end of a section and we have just emitted a
1731 16 bit insn, then emit a nop to make sure that the section ends on
1732 a 32 bit boundary. */
1734 if (prev_insn
.insn
|| seen_relaxable_p
)
1735 (void) m32r_fill_insn (0);