1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "opcodes/m32r-desc.h"
28 #include "opcodes/m32r-opc.h"
31 /* Linked list of symbols that are debugging symbols to be defined as the
32 beginning of the current instruction. */
33 typedef struct sym_link
35 struct sym_link
*next
;
39 static sym_linkS
*debug_sym_link
= (sym_linkS
*) 0;
41 /* Structure to hold all of the different components describing
42 an individual instruction. */
45 const CGEN_INSN
*insn
;
46 const CGEN_INSN
*orig_insn
;
49 CGEN_INSN_INT buffer
[1];
50 #define INSN_VALUE(buf) (*(buf))
52 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
53 #define INSN_VALUE(buf) (buf)
58 fixS
*fixups
[GAS_CGEN_MAX_FIXUPS
];
59 int indices
[MAX_OPERAND_INSTANCES
];
60 sym_linkS
*debug_sym_link
;
64 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
65 boundary (i.e. was the first of two 16 bit insns). */
66 static m32r_insn prev_insn
;
68 /* Non-zero if we've seen a relaxable insn since the last 32 bit
70 static int seen_relaxable_p
= 0;
72 /* Non-zero if -relax specified, in which case sufficient relocs are output
73 for the linker to do relaxing.
74 We do simple forms of relaxing internally, but they are always done.
75 This flag does not apply to them. */
76 static int m32r_relax
;
79 /* Not supported yet. */
80 /* If non-NULL, pointer to cpu description file to read.
81 This allows runtime additions to the assembler. */
82 static const char *m32r_cpu_desc
;
85 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
86 Each high/shigh reloc must be paired with it's low cousin in order to
87 properly calculate the addend in a relocatable link (since there is a
88 potential carry from the low to the high/shigh).
89 This option is off by default though for user-written assembler code it
90 might make sense to make the default be on (i.e. have gcc pass a flag
91 to turn it off). This warning must not be on for GCC created code as
92 optimization may delete the low but not the high/shigh (at least we
93 shouldn't assume or require it to). */
94 static int warn_unmatched_high
= 0;
96 /* Non-zero if -m32rx has been specified, in which case support for the
97 extended M32RX instruction set should be enabled. */
98 static int enable_m32rx
= 0;
100 /* Non-zero if -m32rx -hidden has been specified, in which case support for
101 the special M32RX instruction set should be enabled. */
102 static int enable_special
= 0;
104 /* Non-zero if the programmer should be warned when an explicit parallel
105 instruction might have constraint violations. */
106 static int warn_explicit_parallel_conflicts
= 1;
108 /* Non-zero if insns can be made parallel. */
111 /* Stuff for .scomm symbols. */
112 static segT sbss_section
;
113 static asection scom_section
;
114 static asymbol scom_symbol
;
116 const char comment_chars
[] = ";";
117 const char line_comment_chars
[] = "#";
118 const char line_separator_chars
[] = "";
119 const char EXP_CHARS
[] = "eE";
120 const char FLT_CHARS
[] = "dD";
122 /* Relocations against symbols are done in two
123 parts, with a HI relocation and a LO relocation. Each relocation
124 has only 16 bits of space to store an addend. This means that in
125 order for the linker to handle carries correctly, it must be able
126 to locate both the HI and the LO relocation. This means that the
127 relocations must appear in order in the relocation table.
129 In order to implement this, we keep track of each unmatched HI
130 relocation. We then sort them so that they immediately precede the
131 corresponding LO relocation. */
136 struct m32r_hi_fixup
*next
;
141 /* The section this fixup is in. */
145 /* The list of unmatched HI relocs. */
147 static struct m32r_hi_fixup
*m32r_hi_fixup_list
;
155 if (stdoutput
!= NULL
)
156 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
157 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
160 #define M32R_SHORTOPTS "O"
162 const char *md_shortopts
= M32R_SHORTOPTS
;
164 struct option md_longopts
[] =
166 #define OPTION_M32R (OPTION_MD_BASE)
167 #define OPTION_M32RX (OPTION_M32R + 1)
168 #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1)
169 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
170 #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1)
171 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1)
172 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
173 {"m32r", no_argument
, NULL
, OPTION_M32R
},
174 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
175 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
176 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
177 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
178 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
179 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
180 /* Sigh. I guess all warnings must now have both variants. */
181 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
182 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
183 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
184 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
187 /* Not supported yet. */
188 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
189 #define OPTION_CPU_DESC (OPTION_RELAX + 1)
190 {"relax", no_argument
, NULL
, OPTION_RELAX
},
191 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
193 {NULL
, no_argument
, NULL
, 0}
196 size_t md_longopts_size
= sizeof (md_longopts
);
199 md_parse_option (c
, arg
)
217 case OPTION_WARN_PARALLEL
:
218 warn_explicit_parallel_conflicts
= 1;
221 case OPTION_NO_WARN_PARALLEL
:
222 warn_explicit_parallel_conflicts
= 0;
230 /* Pretend that we do not recognise this option. */
231 as_bad (_("Unrecognised option: -hidden"));
236 case OPTION_WARN_UNMATCHED
:
237 warn_unmatched_high
= 1;
240 case OPTION_NO_WARN_UNMATCHED
:
241 warn_unmatched_high
= 0;
245 /* Not supported yet. */
249 case OPTION_CPU_DESC
:
262 md_show_usage (stream
)
265 fprintf (stream
, _(" M32R specific command line options:\n"));
267 fprintf (stream
, _("\
268 -m32r disable support for the m32rx instruction set\n"));
269 fprintf (stream
, _("\
270 -m32rx support the extended m32rx instruction set\n"));
271 fprintf (stream
, _("\
272 -O try to combine instructions in parallel\n"));
274 fprintf (stream
, _("\
275 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
276 fprintf (stream
, _("\
277 violate contraints\n"));
278 fprintf (stream
, _("\
279 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
280 fprintf (stream
, _("\
281 instructions violate contraints\n"));
282 fprintf (stream
, _("\
283 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
284 fprintf (stream
, _("\
285 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
287 fprintf (stream
, _("\
288 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
289 fprintf (stream
, _("\
290 -no-warn-unmatched-high do not warn about missing low relocs\n"));
291 fprintf (stream
, _("\
292 -Wuh synonym for -warn-unmatched-high\n"));
293 fprintf (stream
, _("\
294 -Wnuh synonym for -no-warn-unmatched-high\n"));
297 fprintf (stream
, _("\
298 -relax create linker relaxable code\n"));
299 fprintf (stream
, _("\
300 -cpu-desc provide runtime cpu description file\n"));
304 static void fill_insn
PARAMS ((int));
305 static void m32r_scomm
PARAMS ((int));
306 static void debug_sym
PARAMS ((int));
307 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
309 /* Set by md_assemble for use by m32r_fill_insn. */
310 static subsegT prev_subseg
;
311 static segT prev_seg
;
313 /* The target specific pseudo-ops which we support. */
314 const pseudo_typeS md_pseudo_table
[] =
317 { "fillinsn", fill_insn
, 0 },
318 { "scomm", m32r_scomm
, 0 },
319 { "debugsym", debug_sym
, 0 },
320 /* Not documented as so far there is no need for them.... */
321 { "m32r", allow_m32rx
, 0 },
322 { "m32rx", allow_m32rx
, 1 },
326 /* FIXME: Should be machine generated. */
327 #define NOP_INSN 0x7000
328 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
330 /* When we align the .text section, insert the correct NOP pattern.
331 N is the power of 2 alignment. LEN is the length of pattern FILL.
332 MAX is the maximum number of characters to skip when doing the alignment,
333 or 0 if there is no maximum. */
336 m32r_do_align (n
, fill
, len
, max
)
342 /* Only do this if the fill pattern wasn't specified. */
344 && subseg_text_p (now_seg
)
345 /* Only do this special handling if aligning to at least a
348 /* Only do this special handling if we're allowed to emit at
350 && (max
== 0 || max
> 1))
352 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
355 /* First align to a 2 byte boundary, in case there is an odd .byte. */
356 /* FIXME: How much memory will cause gas to use when assembling a big
357 program? Perhaps we can avoid the frag_align call? */
358 frag_align (1, 0, 0);
360 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
362 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
363 /* If doing larger alignments use a repeating sequence of appropriate
367 static const unsigned char multi_nop_pattern
[] =
368 { 0x70, 0x00, 0xf0, 0x00 };
369 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
373 prev_insn
.insn
= NULL
;
380 /* If the last instruction was the first of 2 16 bit insns,
381 output a nop to move the PC to a 32 bit boundary.
383 This is done via an alignment specification since branch relaxing
384 may make it unnecessary.
386 Internally, we need to output one of these each time a 32 bit insn is
387 seen after an insn that is relaxable. */
393 (void) m32r_do_align (2, NULL
, 0, 0);
394 prev_insn
.insn
= NULL
;
395 seen_relaxable_p
= 0;
398 /* Record the symbol so that when we output the insn, we can create
399 a symbol that is at the start of the instruction. This is used
400 to emit the label for the start of a breakpoint without causing
401 the assembler to emit a NOP if the previous instruction was a
402 16 bit instruction. */
410 register char *end_name
;
411 register symbolS
*symbolP
;
412 register sym_linkS
*link
;
414 name
= input_line_pointer
;
415 delim
= get_symbol_end ();
416 end_name
= input_line_pointer
;
418 if ((symbolP
= symbol_find (name
)) == NULL
419 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
421 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
424 symbol_table_insert (symbolP
);
425 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
426 /* xgettext:c-format */
427 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
431 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
432 link
->symbol
= symbolP
;
433 link
->next
= debug_sym_link
;
434 debug_sym_link
= link
;
435 symbol_get_obj (symbolP
)->local
= 1;
439 demand_empty_rest_of_line ();
442 /* Second pass to expanding the debug symbols, go through linked
443 list of symbols and reassign the address. */
446 expand_debug_syms (syms
, align
)
450 char *save_input_line
= input_line_pointer
;
451 sym_linkS
*next_syms
;
456 (void) m32r_do_align (align
, NULL
, 0, 0);
457 for (; syms
!= (sym_linkS
*) 0; syms
= next_syms
)
459 symbolS
*symbolP
= syms
->symbol
;
460 next_syms
= syms
->next
;
461 input_line_pointer
= ".\n";
462 pseudo_set (symbolP
);
463 free ((char *) syms
);
466 input_line_pointer
= save_input_line
;
469 /* Cover function to fill_insn called after a label and at end of assembly.
470 The result is always 1: we're called in a conditional to see if the
471 current line is a label. */
474 m32r_fill_insn (done
)
477 if (prev_seg
!= NULL
)
480 subsegT subseg
= now_subseg
;
482 subseg_set (prev_seg
, prev_subseg
);
486 subseg_set (seg
, subseg
);
489 if (done
&& debug_sym_link
)
491 expand_debug_syms (debug_sym_link
, 1);
492 debug_sym_link
= (sym_linkS
*) 0;
505 /* Initialize the `cgen' interface. */
507 /* Set the machine number and endian. */
508 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
509 CGEN_CPU_OPEN_ENDIAN
,
512 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
514 /* The operand instance table is used during optimization to determine
515 which insns can be executed in parallel. It is also used to give
516 warnings regarding operand interference in parallel insns. */
517 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
519 /* This is a callback from cgen to gas to parse operands. */
520 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
523 /* Not supported yet. */
524 /* If a runtime cpu description file was provided, parse it. */
525 if (m32r_cpu_desc
!= NULL
)
529 errmsg
= cgen_read_cpu_file (gas_cgen_cpu_desc
, m32r_cpu_desc
);
531 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
535 /* Save the current subseg so we can restore it [it's the default one and
536 we don't want the initial section to be .sbss]. */
540 /* The sbss section is for local .scomm symbols. */
541 sbss_section
= subseg_new (".sbss", 0);
543 /* This is copied from perform_an_assembly_pass. */
544 applicable
= bfd_applicable_section_flags (stdoutput
);
545 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
548 /* What does this do? [see perform_an_assembly_pass] */
549 seg_info (bss_section
)->bss
= 1;
552 subseg_set (seg
, subseg
);
554 /* We must construct a fake section similar to bfd_com_section
555 but with the name .scommon. */
556 scom_section
= bfd_com_section
;
557 scom_section
.name
= ".scommon";
558 scom_section
.output_section
= &scom_section
;
559 scom_section
.symbol
= &scom_symbol
;
560 scom_section
.symbol_ptr_ptr
= &scom_section
.symbol
;
561 scom_symbol
= *bfd_com_section
.symbol
;
562 scom_symbol
.name
= ".scommon";
563 scom_symbol
.section
= &scom_section
;
565 allow_m32rx (enable_m32rx
);
568 #define OPERAND_IS_COND_BIT(operand, indices, index) \
569 ((operand)->hw_type == HW_H_COND \
570 || ((operand)->hw_type == HW_H_PSW) \
571 || ((operand)->hw_type == HW_H_CR \
572 && (indices [index] == 0 || indices [index] == 1)))
574 /* Returns true if an output of instruction 'a' is referenced by an operand
575 of instruction 'b'. If 'check_outputs' is true then b's outputs are
576 checked, otherwise its inputs are examined. */
579 first_writes_to_seconds_operands (a
, b
, check_outputs
)
582 const int check_outputs
;
584 const CGEN_OPINST
*a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
585 const CGEN_OPINST
*b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
588 /* If at least one of the instructions takes no operands, then there is
589 nothing to check. There really are instructions without operands,
591 if (a_operands
== NULL
|| b_ops
== NULL
)
594 /* Scan the operand list of 'a' looking for an output operand. */
596 a_operands
->type
!= CGEN_OPINST_END
;
597 a_index
++, a_operands
++)
599 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
602 const CGEN_OPINST
*b_operands
= b_ops
;
605 The Condition bit 'C' is a shadow of the CBR register (control
606 register 1) and also a shadow of bit 31 of the program status
607 word (control register 0). For now this is handled here, rather
610 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
612 /* Scan operand list of 'b' looking for another reference to the
613 condition bit, which goes in the right direction. */
615 b_operands
->type
!= CGEN_OPINST_END
;
616 b_index
++, b_operands
++)
618 if ((b_operands
->type
621 : CGEN_OPINST_INPUT
))
622 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
628 /* Scan operand list of 'b' looking for an operand that
629 references the same hardware element, and which goes in the
632 b_operands
->type
!= CGEN_OPINST_END
;
633 b_index
++, b_operands
++)
635 if ((b_operands
->type
638 : CGEN_OPINST_INPUT
))
639 && (b_operands
->hw_type
== a_operands
->hw_type
)
640 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
650 /* Returns true if the insn can (potentially) alter the program counter. */
657 /* Once PC operands are working.... */
658 const CGEN_OPINST
*a_operands
== CGEN_INSN_OPERANDS (gas_cgen_cpu_desc
,
661 if (a_operands
== NULL
)
664 while (a_operands
->type
!= CGEN_OPINST_END
)
666 if (a_operands
->operand
!= NULL
667 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc
,
668 a_operands
->operand
) == M32R_OPERAND_PC
)
674 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
675 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
681 /* Return NULL if the two 16 bit insns can be executed in parallel.
682 Otherwise return a pointer to an error message explaining why not. */
685 can_make_parallel (a
, b
)
692 /* Make sure the instructions are the right length. */
693 if (CGEN_FIELDS_BITSIZE (&a
->fields
) != 16
694 || CGEN_FIELDS_BITSIZE (&b
->fields
) != 16)
697 if (first_writes_to_seconds_operands (a
, b
, true))
698 return _("Instructions write to the same destination register.");
700 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
701 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
703 /* Make sure that the instructions use the correct execution pipelines. */
704 if (a_pipe
== PIPE_NONE
705 || b_pipe
== PIPE_NONE
)
706 return _("Instructions do not use parallel execution pipelines.");
708 /* Leave this test for last, since it is the only test that can
709 go away if the instructions are swapped, and we want to make
710 sure that any other errors are detected before this happens. */
713 return _("Instructions share the same execution pipeline");
718 /* Force the top bit of the second 16-bit insn to be set. */
721 make_parallel (buffer
)
722 CGEN_INSN_BYTES_PTR buffer
;
727 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
732 /* Same as make_parallel except buffer contains the bytes in target order. */
735 target_make_parallel (buffer
)
738 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
742 /* Assemble two instructions with an explicit parallel operation (||) or
743 sequential operation (->). */
746 assemble_two_insns (str
, str2
, parallel_p
)
755 char save_str2
= *str2
;
757 /* Seperate the two instructions. */
760 /* Make sure the two insns begin on a 32 bit boundary.
761 This is also done for the serial case (foo -> bar), relaxing doesn't
762 affect insns written like this.
763 Note that we must always do this as we can't assume anything about
764 whether we're currently on a 32 bit boundary or not. Relaxing may
768 first
.debug_sym_link
= debug_sym_link
;
769 debug_sym_link
= (sym_linkS
*) 0;
771 /* Parse the first instruction. */
772 if (! (first
.insn
= m32r_cgen_assemble_insn
773 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
780 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
782 /* xgettext:c-format */
783 as_bad (_("not a 16 bit instruction '%s'"), str
);
786 else if (! enable_special
787 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
789 /* xgettext:c-format */
790 as_bad (_("unknown instruction '%s'"), str
);
793 else if (! enable_m32rx
794 /* FIXME: Need standard macro to perform this test. */
795 && (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
796 == (1 << MACH_M32RX
)))
798 /* xgettext:c-format */
799 as_bad (_("instruction '%s' is for the M32RX only"), str
);
803 /* Check to see if this is an allowable parallel insn. */
805 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
807 /* xgettext:c-format */
808 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
812 /* Restore the original assembly text, just in case it is needed. */
815 /* Save the original string pointer. */
818 /* Advanced past the parsed string. */
821 /* Remember the entire string in case it is needed for error
825 /* Convert the opcode to lower case. */
829 while (isspace (*s2
++))
834 while (isalnum (*s2
))
836 if (isupper ((unsigned char) *s2
))
842 /* Preserve any fixups that have been generated and reset the list
844 gas_cgen_save_fixups ();
846 /* Get the indices of the operands of the instruction. */
847 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
848 doesn't seem right. Perhaps allow passing fields like we do insn. */
849 /* FIXME: ALIAS insns do not have operands, so we use this function
850 to find the equivalent insn and overwrite the value stored in our
851 structure. We still need the original insn, however, since this
852 may have certain attributes that are not present in the unaliased
853 version (eg relaxability). When aliases behave differently this
854 may have to change. */
855 first
.orig_insn
= first
.insn
;
857 CGEN_FIELDS tmp_fields
;
858 first
.insn
= cgen_lookup_get_insn_operands
859 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
860 first
.indices
, &tmp_fields
);
863 if (first
.insn
== NULL
)
864 as_fatal (_("internal error: lookup/get operands failed"));
866 second
.debug_sym_link
= NULL
;
868 /* Parse the second instruction. */
869 if (! (second
.insn
= m32r_cgen_assemble_insn
870 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
877 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
879 /* xgettext:c-format */
880 as_bad (_("not a 16 bit instruction '%s'"), str
);
883 else if (! enable_special
884 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
886 /* xgettext:c-format */
887 as_bad (_("unknown instruction '%s'"), str
);
890 else if (! enable_m32rx
891 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
893 /* xgettext:c-format */
894 as_bad (_("instruction '%s' is for the M32RX only"), str
);
898 /* Check to see if this is an allowable parallel insn. */
900 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
902 /* xgettext:c-format */
903 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
907 if (parallel_p
&& ! enable_m32rx
)
909 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
910 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
912 /* xgettext:c-format */
913 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
918 /* Get the indices of the operands of the instruction. */
919 second
.orig_insn
= second
.insn
;
921 CGEN_FIELDS tmp_fields
;
922 second
.insn
= cgen_lookup_get_insn_operands
923 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
924 second
.indices
, &tmp_fields
);
927 if (second
.insn
== NULL
)
928 as_fatal (_("internal error: lookup/get operands failed"));
930 /* We assume that if the first instruction writes to a register that is
931 read by the second instruction it is because the programmer intended
932 this to happen, (after all they have explicitly requested that these
933 two instructions be executed in parallel). Although if the global
934 variable warn_explicit_parallel_conflicts is true then we do generate
935 a warning message. Similarly we assume that parallel branch and jump
936 instructions are deliberate and should not produce errors. */
938 if (parallel_p
&& warn_explicit_parallel_conflicts
)
940 if (first_writes_to_seconds_operands (&first
, &second
, false))
941 /* xgettext:c-format */
942 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
944 if (first_writes_to_seconds_operands (&second
, &first
, false))
945 /* xgettext:c-format */
946 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
950 || (errmsg
= (char *) can_make_parallel (&first
, &second
)) == NULL
)
952 /* Get the fixups for the first instruction. */
953 gas_cgen_swap_fixups ();
956 expand_debug_syms (first
.debug_sym_link
, 1);
957 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
958 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
960 /* Force the top bit of the second insn to be set. */
962 make_parallel (second
.buffer
);
964 /* Get its fixups. */
965 gas_cgen_restore_fixups ();
968 expand_debug_syms (second
.debug_sym_link
, 1);
969 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
970 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
972 /* Try swapping the instructions to see if they work that way. */
973 else if (can_make_parallel (&second
, &first
) == NULL
)
975 /* Write out the second instruction first. */
976 expand_debug_syms (second
.debug_sym_link
, 1);
977 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
978 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
980 /* Force the top bit of the first instruction to be set. */
981 make_parallel (first
.buffer
);
983 /* Get the fixups for the first instruction. */
984 gas_cgen_restore_fixups ();
986 /* Write out the first instruction. */
987 expand_debug_syms (first
.debug_sym_link
, 1);
988 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
989 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
993 as_bad ("'%s': %s", str2
, errmsg
);
997 /* Set these so m32r_fill_insn can use them. */
999 prev_subseg
= now_subseg
;
1010 /* Initialize GAS's cgen interface for a new instruction. */
1011 gas_cgen_init_parse ();
1013 /* Look for a parallel instruction seperator. */
1014 if ((str2
= strstr (str
, "||")) != NULL
)
1016 assemble_two_insns (str
, str2
, 1);
1020 /* Also look for a sequential instruction seperator. */
1021 if ((str2
= strstr (str
, "->")) != NULL
)
1023 assemble_two_insns (str
, str2
, 0);
1027 insn
.debug_sym_link
= debug_sym_link
;
1028 debug_sym_link
= (sym_linkS
*) 0;
1030 insn
.insn
= m32r_cgen_assemble_insn
1031 (gas_cgen_cpu_desc
, str
, &insn
.fields
, insn
.buffer
, & errmsg
);
1039 if (! enable_special
1040 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1042 /* xgettext:c-format */
1043 as_bad (_("unknown instruction '%s'"), str
);
1046 else if (! enable_m32rx
1047 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1049 /* xgettext:c-format */
1050 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1054 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1056 /* 32 bit insns must live on 32 bit boundaries. */
1057 if (prev_insn
.insn
|| seen_relaxable_p
)
1059 /* ??? If calling fill_insn too many times turns us into a memory
1060 pig, can we call a fn to assemble a nop instead of
1061 !seen_relaxable_p? */
1065 expand_debug_syms (insn
.debug_sym_link
, 2);
1067 /* Doesn't really matter what we pass for RELAX_P here. */
1068 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1069 CGEN_FIELDS_BITSIZE (&insn
.fields
), 1, NULL
);
1073 int on_32bit_boundary_p
;
1076 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1079 insn
.orig_insn
= insn
.insn
;
1081 /* If the previous insn was relaxable, then it may be expanded
1082 to fill the current 16 bit slot. Emit a NOP here to occupy
1083 this slot, so that we can start at optimizing at a 32 bit
1085 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1090 /* Get the indices of the operands of the instruction.
1091 FIXME: See assemble_parallel for notes on orig_insn. */
1093 CGEN_FIELDS tmp_fields
;
1094 insn
.insn
= cgen_lookup_get_insn_operands
1095 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1096 16, insn
.indices
, &tmp_fields
);
1099 if (insn
.insn
== NULL
)
1100 as_fatal (_("internal error: lookup/get operands failed"));
1103 /* Compute whether we're on a 32 bit boundary or not.
1104 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1105 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1107 /* Look to see if this instruction can be combined with the
1108 previous instruction to make one, parallel, 32 bit instruction.
1109 If the previous instruction (potentially) changed the flow of
1110 program control, then it cannot be combined with the current
1111 instruction. If the current instruction is relaxable, then it
1112 might be replaced with a longer version, so we cannot combine it.
1113 Also if the output of the previous instruction is used as an
1114 input to the current instruction then it cannot be combined.
1115 Otherwise call can_make_parallel() with both orderings of the
1116 instructions to see if they can be combined. */
1117 if (! on_32bit_boundary_p
1120 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1121 && ! writes_to_pc (&prev_insn
)
1122 && ! first_writes_to_seconds_operands (&prev_insn
, &insn
, false))
1124 if (can_make_parallel (&prev_insn
, &insn
) == NULL
)
1125 make_parallel (insn
.buffer
);
1126 else if (can_make_parallel (&insn
, &prev_insn
) == NULL
)
1130 expand_debug_syms (insn
.debug_sym_link
, 1);
1136 /* Ensure each pair of 16 bit insns is in the same frag. */
1139 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1140 CGEN_FIELDS_BITSIZE (&insn
.fields
),
1141 1 /* relax_p */, &fi
);
1142 insn
.addr
= fi
.addr
;
1143 insn
.frag
= fi
.frag
;
1144 insn
.num_fixups
= fi
.num_fixups
;
1145 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1146 insn
.fixups
[i
] = fi
.fixups
[i
];
1153 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1155 /* Swap the two insns */
1156 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1157 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1159 target_make_parallel (insn
.addr
);
1161 /* Swap any relaxable frags recorded for the two insns. */
1162 /* FIXME: Clarify. relaxation precludes parallel insns */
1163 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1164 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1165 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1166 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1168 /* Update the addresses in any fixups.
1169 Note that we don't have to handle the case where each insn is in
1170 a different frag as we ensure they're in the same frag above. */
1171 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1172 prev_insn
.fixups
[i
]->fx_where
+= 2;
1173 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1174 insn
.fixups
[i
]->fx_where
-= 2;
1177 /* Keep track of whether we've seen a pair of 16 bit insns.
1178 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1179 if (on_32bit_boundary_p
)
1182 prev_insn
.insn
= NULL
;
1184 /* If the insn needs the following one to be on a 32 bit boundary
1185 (e.g. subroutine calls), fill this insn's slot. */
1186 if (on_32bit_boundary_p
1187 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1190 /* If this is a relaxable insn (can be replaced with a larger version)
1191 mark the fact so that we can emit an alignment directive for a
1192 following 32 bit insn if we see one. */
1193 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1194 seen_relaxable_p
= 1;
1197 /* Set these so m32r_fill_insn can use them. */
1199 prev_subseg
= now_subseg
;
1202 /* The syntax in the manual says constants begin with '#'.
1203 We just ignore it. */
1206 md_operand (expressionP
)
1207 expressionS
*expressionP
;
1209 if (*input_line_pointer
== '#')
1211 input_line_pointer
++;
1212 expression (expressionP
);
1217 md_section_align (segment
, size
)
1221 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1222 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1226 md_undefined_symbol (name
)
1232 /* .scomm pseudo-op handler.
1234 This is a new pseudo-op to handle putting objects in .scommon.
1235 By doing this the linker won't need to do any work,
1236 and more importantly it removes the implicit -G arg necessary to
1237 correctly link the object file. */
1243 register char *name
;
1247 register symbolS
*symbolP
;
1251 name
= input_line_pointer
;
1252 c
= get_symbol_end ();
1254 /* Just after name is now '\0'. */
1255 p
= input_line_pointer
;
1258 if (*input_line_pointer
!= ',')
1260 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1261 ignore_rest_of_line ();
1266 input_line_pointer
++;
1267 if ((size
= get_absolute_expression ()) < 0)
1269 /* xgettext:c-format */
1270 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1271 ignore_rest_of_line ();
1275 /* The third argument to .scomm is the alignment. */
1276 if (*input_line_pointer
!= ',')
1280 ++input_line_pointer
;
1281 align
= get_absolute_expression ();
1284 as_warn (_("ignoring bad alignment"));
1289 /* Convert to a power of 2 alignment. */
1292 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
)
1296 as_bad (_("Common alignment not a power of 2"));
1297 ignore_rest_of_line ();
1305 symbolP
= symbol_find_or_make (name
);
1308 if (S_IS_DEFINED (symbolP
))
1310 /* xgettext:c-format */
1311 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1312 S_GET_NAME (symbolP
));
1313 ignore_rest_of_line ();
1317 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1319 /* xgettext:c-format */
1320 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1321 S_GET_NAME (symbolP
),
1322 (long) S_GET_VALUE (symbolP
),
1325 ignore_rest_of_line ();
1329 if (symbol_get_obj (symbolP
)->local
)
1331 segT old_sec
= now_seg
;
1332 int old_subsec
= now_subseg
;
1335 record_alignment (sbss_section
, align2
);
1336 subseg_set (sbss_section
, 0);
1339 frag_align (align2
, 0, 0);
1341 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1342 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1344 symbol_set_frag (symbolP
, frag_now
);
1346 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1349 S_SET_SIZE (symbolP
, size
);
1350 S_SET_SEGMENT (symbolP
, sbss_section
);
1351 S_CLEAR_EXTERNAL (symbolP
);
1352 subseg_set (old_sec
, old_subsec
);
1356 S_SET_VALUE (symbolP
, (valueT
) size
);
1357 S_SET_ALIGN (symbolP
, align2
);
1358 S_SET_EXTERNAL (symbolP
);
1359 S_SET_SEGMENT (symbolP
, &scom_section
);
1362 demand_empty_rest_of_line ();
1365 /* Interface to relax_segment. */
1367 /* FIXME: Build table by hand, get it working, then machine generate. */
1369 const relax_typeS md_relax_table
[] =
1372 1) most positive reach of this state,
1373 2) most negative reach of this state,
1374 3) how many bytes this mode will add to the size of the current frag
1375 4) which index into the table to try if we can't fit into this one. */
1377 /* The first entry must be unused because an `rlx_more' value of zero ends
1381 /* The displacement used by GAS is from the end of the 2 byte insn,
1382 so we subtract 2 from the following. */
1383 /* 16 bit insn, 8 bit disp -> 10 bit range.
1384 This doesn't handle a branch in the right slot at the border:
1385 the "& -4" isn't taken into account. It's not important enough to
1386 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1388 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1389 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1390 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1391 /* Same thing, but with leading nop for alignment. */
1392 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1396 m32r_relax_frag (fragP
, stretch
)
1400 /* Address of branch insn. */
1401 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1404 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1405 if (fragP
->fr_subtype
== 2)
1407 if ((address
& 3) != 0)
1409 fragP
->fr_subtype
= 3;
1413 else if (fragP
->fr_subtype
== 3)
1415 if ((address
& 3) == 0)
1417 fragP
->fr_subtype
= 2;
1423 growth
= relax_frag (fragP
, stretch
);
1425 /* Long jump on odd halfword boundary? */
1426 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1428 fragP
->fr_subtype
= 3;
1436 /* Return an initial guess of the length by which a fragment must grow to
1437 hold a branch to reach its destination.
1438 Also updates fr_type/fr_subtype as necessary.
1440 Called just before doing relaxation.
1441 Any symbol that is now undefined will not become defined.
1442 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1443 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1444 Although it may not be explicit in the frag, pretend fr_var starts
1448 md_estimate_size_before_relax (fragP
, segment
)
1452 int old_fr_fix
= fragP
->fr_fix
;
1454 /* The only thing we have to handle here are symbols outside of the
1455 current segment. They may be undefined or in a different segment in
1456 which case linker scripts may place them anywhere.
1457 However, we can't finish the fragment here and emit the reloc as insn
1458 alignment requirements may move the insn about. */
1460 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1462 /* The symbol is undefined in this segment.
1463 Change the relaxation subtype to the max allowable and leave
1464 all further handling to md_convert_frag. */
1465 fragP
->fr_subtype
= 2;
1468 /* Can't use this, but leave in for illustration. */
1469 /* Change 16 bit insn to 32 bit insn. */
1470 fragP
->fr_opcode
[0] |= 0x80;
1472 /* Increase known (fixed) size of fragment. */
1475 /* Create a relocation for it. */
1476 fix_new (fragP
, old_fr_fix
, 4,
1478 fragP
->fr_offset
, 1 /* pcrel */,
1479 /* FIXME: Can't use a real BFD reloc here.
1480 gas_cgen_md_apply_fix3 can't handle it. */
1481 BFD_RELOC_M32R_26_PCREL
);
1483 /* Mark this fragment as finished. */
1487 const CGEN_INSN
*insn
;
1490 /* Update the recorded insn.
1491 Fortunately we don't have to look very far.
1492 FIXME: Change this to record in the instruction the next higher
1493 relaxable insn to use. */
1494 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1496 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1497 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1499 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAX
))
1505 fragP
->fr_cgen
.insn
= insn
;
1511 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1514 /* *FRAGP has been relaxed to its final size, and now needs to have
1515 the bytes inside it modified to conform to the new size.
1517 Called after relaxation is finished.
1518 fragP->fr_type == rs_machine_dependent.
1519 fragP->fr_subtype is the subtype of what the address relaxed to. */
1522 md_convert_frag (abfd
, sec
, fragP
)
1534 opcode
= fragP
->fr_opcode
;
1536 /* Address opcode resides at in file space. */
1537 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1539 switch (fragP
->fr_subtype
)
1543 displacement
= &opcode
[1];
1548 displacement
= &opcode
[1];
1551 opcode
[2] = opcode
[0] | 0x80;
1552 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1553 opcode_address
+= 2;
1555 displacement
= &opcode
[3];
1561 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1563 /* Symbol must be resolved by linker. */
1564 if (fragP
->fr_offset
& 3)
1565 as_warn (_("Addend to unresolved symbol not on word boundary."));
1566 addend
= fragP
->fr_offset
>> 2;
1570 /* Address we want to reach in file space. */
1571 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1572 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
1573 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1576 /* Create a relocation for symbols that must be resolved by the linker.
1577 Otherwise output the completed insn. */
1579 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1581 assert (fragP
->fr_subtype
!= 1);
1582 assert (fragP
->fr_cgen
.insn
!= 0);
1583 gas_cgen_record_fixup (fragP
,
1584 /* Offset of branch insn in frag. */
1585 fragP
->fr_fix
+ extension
- 4,
1586 fragP
->fr_cgen
.insn
,
1588 /* FIXME: quick hack. */
1590 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1591 fragP
->fr_cgen
.opindex
),
1593 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1594 M32R_OPERAND_DISP24
),
1596 fragP
->fr_cgen
.opinfo
,
1597 fragP
->fr_symbol
, fragP
->fr_offset
);
1600 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1602 md_number_to_chars (displacement
, (valueT
) addend
,
1603 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1605 fragP
->fr_fix
+= extension
;
1608 /* Functions concerning relocs. */
1610 /* The location from which a PC relative jump should be calculated,
1611 given a PC relative reloc. */
1614 md_pcrel_from_section (fixP
, sec
)
1618 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1619 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1620 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1622 /* The symbol is undefined (or is defined but not in this section).
1623 Let the linker figure it out. */
1627 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1630 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1631 Returns BFD_RELOC_NONE if no reloc type can be found.
1632 *FIXP may be modified if desired. */
1634 bfd_reloc_code_real_type
1635 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1636 const CGEN_INSN
*insn
;
1637 const CGEN_OPERAND
*operand
;
1640 switch (operand
->type
)
1642 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1643 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1644 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1645 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1646 case M32R_OPERAND_HI16
:
1647 case M32R_OPERAND_SLO16
:
1648 case M32R_OPERAND_ULO16
:
1649 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1650 if (fixP
->fx_cgen
.opinfo
!= 0)
1651 return fixP
->fx_cgen
.opinfo
;
1654 /* Avoid -Wall warning. */
1657 return BFD_RELOC_NONE
;
1660 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1663 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1668 struct m32r_hi_fixup
*hi_fixup
;
1670 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1671 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1673 hi_fixup
= ((struct m32r_hi_fixup
*)
1674 xmalloc (sizeof (struct m32r_hi_fixup
)));
1675 hi_fixup
->fixp
= fixP
;
1676 hi_fixup
->seg
= now_seg
;
1677 hi_fixup
->next
= m32r_hi_fixup_list
;
1679 m32r_hi_fixup_list
= hi_fixup
;
1682 /* Called while parsing an instruction to create a fixup.
1683 We need to check for HI16 relocs and queue them up for later sorting. */
1686 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1689 const CGEN_INSN
*insn
;
1691 const CGEN_OPERAND
*operand
;
1695 fixS
*fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1696 operand
, opinfo
, exp
);
1698 switch (operand
->type
)
1700 case M32R_OPERAND_HI16
:
1701 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1702 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1703 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1704 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
1707 /* Avoid -Wall warning */
1714 /* Return BFD reloc type from opinfo field in a fixS.
1715 It's tricky using fx_r_type in m32r_frob_file because the values
1716 are BFD_RELOC_UNUSED + operand number. */
1717 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1719 /* Sort any unmatched HI16 relocs so that they immediately precede
1720 the corresponding LO16 reloc. This is called before md_apply_fix and
1726 struct m32r_hi_fixup
*l
;
1728 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1730 segment_info_type
*seginfo
;
1733 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1734 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1736 /* Check quickly whether the next fixup happens to be a matching low. */
1737 if (l
->fixp
->fx_next
!= NULL
1738 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1739 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1740 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1743 /* Look through the fixups for this segment for a matching `low'.
1744 When we find one, move the high/shigh just in front of it. We do
1745 this in two passes. In the first pass, we try to find a
1746 unique `low'. In the second pass, we permit multiple high's
1747 relocs for a single `low'. */
1748 seginfo
= seg_info (l
->seg
);
1749 for (pass
= 0; pass
< 2; pass
++)
1755 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1757 /* Check whether this is a `low' fixup which matches l->fixp. */
1758 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1759 && f
->fx_addsy
== l
->fixp
->fx_addsy
1760 && f
->fx_offset
== l
->fixp
->fx_offset
1763 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1764 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1765 || prev
->fx_addsy
!= f
->fx_addsy
1766 || prev
->fx_offset
!= f
->fx_offset
))
1770 /* Move l->fixp before f. */
1771 for (pf
= &seginfo
->fix_root
;
1773 pf
= & (*pf
)->fx_next
)
1774 assert (*pf
!= NULL
);
1776 *pf
= l
->fixp
->fx_next
;
1778 l
->fixp
->fx_next
= f
;
1780 seginfo
->fix_root
= l
->fixp
;
1782 prev
->fx_next
= l
->fixp
;
1794 && warn_unmatched_high
)
1795 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1796 _("Unmatched high/shigh reloc"));
1801 /* See whether we need to force a relocation into the output file.
1802 This is used to force out switch and PC relative relocations when
1806 m32r_force_relocation (fix
)
1809 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1810 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1816 return fix
->fx_pcrel
;
1819 /* Write a value out to the object file, using the appropriate endianness. */
1822 md_number_to_chars (buf
, val
, n
)
1827 if (target_big_endian
)
1828 number_to_chars_bigendian (buf
, val
, n
);
1830 number_to_chars_littleendian (buf
, val
, n
);
1833 /* Turn a string in input_line_pointer into a floating point constant
1834 of type TYPE, and store the appropriate bytes in *LITP. The number
1835 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1836 returned, or NULL on OK. */
1838 /* Equal to MAX_PRECISION in atof-ieee.c. */
1839 #define MAX_LITTLENUMS 6
1842 md_atof (type
, litP
, sizeP
)
1849 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1869 /* FIXME: Some targets allow other format chars for bigger sizes
1874 return _("Bad call to md_atof()");
1877 t
= atof_ieee (input_line_pointer
, type
, words
);
1879 input_line_pointer
= t
;
1880 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1882 if (target_big_endian
)
1884 for (i
= 0; i
< prec
; i
++)
1886 md_number_to_chars (litP
, (valueT
) words
[i
],
1887 sizeof (LITTLENUM_TYPE
));
1888 litP
+= sizeof (LITTLENUM_TYPE
);
1893 for (i
= prec
- 1; i
>= 0; i
--)
1895 md_number_to_chars (litP
, (valueT
) words
[i
],
1896 sizeof (LITTLENUM_TYPE
));
1897 litP
+= sizeof (LITTLENUM_TYPE
);
1905 m32r_elf_section_change_hook ()
1907 /* If we have reached the end of a section and we have just emitted a
1908 16 bit insn, then emit a nop to make sure that the section ends on
1909 a 32 bit boundary. */
1911 if (prev_insn
.insn
|| seen_relaxable_p
)
1912 (void) m32r_fill_insn (0);
1915 /* Return true if can adjust the reloc to be relative to its section
1916 (such as .data) instead of relative to some symbol. */
1919 m32r_fix_adjustable (fixP
)
1923 bfd_reloc_code_real_type reloc_type
;
1925 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
1927 const CGEN_INSN
*insn
= NULL
;
1928 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
1929 const CGEN_OPERAND
*operand
=
1930 cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
1931 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
1934 reloc_type
= fixP
->fx_r_type
;
1936 if (fixP
->fx_addsy
== NULL
)
1939 /* Prevent all adjustments to global symbols. */
1940 if (S_IS_EXTERN (fixP
->fx_addsy
))
1942 if (S_IS_WEAK (fixP
->fx_addsy
))
1945 /* We need the symbol name for the VTABLE entries. */
1946 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
1947 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)