1 /* tc-m32r.c -- Assembler for the Renesas M32R.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
27 #include "opcodes/m32r-desc.h"
28 #include "opcodes/m32r-opc.h"
32 /* Linked list of symbols that are debugging symbols to be defined as the
33 beginning of the current instruction. */
34 typedef struct sym_link
36 struct sym_link
*next
;
40 static sym_linkS
*debug_sym_link
= (sym_linkS
*) 0;
42 /* Structure to hold all of the different components describing
43 an individual instruction. */
46 const CGEN_INSN
*insn
;
47 const CGEN_INSN
*orig_insn
;
50 CGEN_INSN_INT buffer
[1];
51 #define INSN_VALUE(buf) (*(buf))
53 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
54 #define INSN_VALUE(buf) (buf)
59 fixS
*fixups
[GAS_CGEN_MAX_FIXUPS
];
60 int indices
[MAX_OPERAND_INSTANCES
];
61 sym_linkS
*debug_sym_link
;
65 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
66 boundary (i.e. was the first of two 16 bit insns). */
67 static m32r_insn prev_insn
;
69 /* Non-zero if we've seen a relaxable insn since the last 32 bit
71 static int seen_relaxable_p
= 0;
73 /* Non-zero if -relax specified, in which case sufficient relocs are output
74 for the linker to do relaxing.
75 We do simple forms of relaxing internally, but they are always done.
76 This flag does not apply to them. */
77 static int m32r_relax
;
80 /* Not supported yet. */
81 /* If non-NULL, pointer to cpu description file to read.
82 This allows runtime additions to the assembler. */
83 static const char *m32r_cpu_desc
;
86 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
87 Each high/shigh reloc must be paired with it's low cousin in order to
88 properly calculate the addend in a relocatable link (since there is a
89 potential carry from the low to the high/shigh).
90 This option is off by default though for user-written assembler code it
91 might make sense to make the default be on (i.e. have gcc pass a flag
92 to turn it off). This warning must not be on for GCC created code as
93 optimization may delete the low but not the high/shigh (at least we
94 shouldn't assume or require it to). */
95 static int warn_unmatched_high
= 0;
97 /* 1 if -m32rx has been specified, in which case support for
98 the extended M32RX instruction set should be enabled.
99 2 if -m32r2 has been specified, in which case support for
100 the extended M32R2 instruction set should be enabled. */
101 static int enable_m32rx
= 0; /* Default to M32R. */
103 /* Non-zero if -m32rx -hidden has been specified, in which case support for
104 the special M32RX instruction set should be enabled. */
105 static int enable_special
= 0;
107 /* Non-zero if -bitinst has been specified, in which case support
108 for extended M32R bit-field instruction set should be enabled. */
109 static int enable_special_m32r
= 0;
111 /* Non-zero if -float has been specified, in which case support for
112 extended M32R floating point instruction set should be enabled. */
113 static int enable_special_float
= 0;
115 /* Non-zero if the programmer should be warned when an explicit parallel
116 instruction might have constraint violations. */
117 static int warn_explicit_parallel_conflicts
= 1;
119 /* Non-zero if the programmer should not receive any messages about
120 parallel instruction with potential or real constraint violations.
121 The ability to suppress these messages is intended only for hardware
122 vendors testing the chip. It superceedes
123 warn_explicit_parallel_conflicts. */
124 static int ignore_parallel_conflicts
= 0;
126 /* Non-zero if insns can be made parallel. */
127 static int use_parallel
= 1;
129 /* Non-zero if optimizations should be performed. */
133 static int m32r_flags
= 0;
135 /* Stuff for .scomm symbols. */
136 static segT sbss_section
;
137 static asection scom_section
;
138 static asymbol scom_symbol
;
140 const char comment_chars
[] = ";";
141 const char line_comment_chars
[] = "#";
142 const char line_separator_chars
[] = "!";
143 const char EXP_CHARS
[] = "eE";
144 const char FLT_CHARS
[] = "dD";
146 /* Relocations against symbols are done in two
147 parts, with a HI relocation and a LO relocation. Each relocation
148 has only 16 bits of space to store an addend. This means that in
149 order for the linker to handle carries correctly, it must be able
150 to locate both the HI and the LO relocation. This means that the
151 relocations must appear in order in the relocation table.
153 In order to implement this, we keep track of each unmatched HI
154 relocation. We then sort them so that they immediately precede the
155 corresponding LO relocation. */
160 struct m32r_hi_fixup
*next
;
165 /* The section this fixup is in. */
169 /* The list of unmatched HI relocs. */
171 static struct m32r_hi_fixup
*m32r_hi_fixup_list
;
174 enum bfd_architecture bfd_mach
;
178 { bfd_mach_m32r
, (1<<MACH_M32R
) },
179 { bfd_mach_m32rx
, (1<<MACH_M32RX
) },
180 { bfd_mach_m32r2
, (1<<MACH_M32R2
) }
183 static void allow_m32rx (int);
190 if (stdoutput
!= NULL
)
191 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_table
[on
].bfd_mach
);
193 if (gas_cgen_cpu_desc
!= NULL
)
194 gas_cgen_cpu_desc
->machs
= mach_table
[on
].mach_flags
;
197 #define M32R_SHORTOPTS "O"
199 const char *md_shortopts
= M32R_SHORTOPTS
;
201 struct option md_longopts
[] =
203 #define OPTION_M32R (OPTION_MD_BASE)
204 #define OPTION_M32RX (OPTION_M32R + 1)
205 #define OPTION_M32R2 (OPTION_M32RX + 1)
206 #define OPTION_BIG (OPTION_M32R2 + 1)
207 #define OPTION_LITTLE (OPTION_BIG + 1)
208 #define OPTION_PARALLEL (OPTION_LITTLE + 1)
209 #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
210 #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
211 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
212 #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
213 #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1)
214 #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1)
215 #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
216 #define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1)
217 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
218 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
219 {"m32r", no_argument
, NULL
, OPTION_M32R
},
220 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
221 {"m32r2", no_argument
, NULL
, OPTION_M32R2
},
222 {"big", no_argument
, NULL
, OPTION_BIG
},
223 {"little", no_argument
, NULL
, OPTION_LITTLE
},
224 {"EB", no_argument
, NULL
, OPTION_BIG
},
225 {"EL", no_argument
, NULL
, OPTION_LITTLE
},
226 {"parallel", no_argument
, NULL
, OPTION_PARALLEL
},
227 {"no-parallel", no_argument
, NULL
, OPTION_NO_PARALLEL
},
228 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
229 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
230 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
231 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
232 {"ignore-parallel-conflicts", no_argument
, NULL
, OPTION_IGNORE_PARALLEL
},
233 {"Ip", no_argument
, NULL
, OPTION_IGNORE_PARALLEL
},
234 {"no-ignore-parallel-conflicts", no_argument
, NULL
, OPTION_NO_IGNORE_PARALLEL
},
235 {"nIp", no_argument
, NULL
, OPTION_NO_IGNORE_PARALLEL
},
236 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
237 {"bitinst", no_argument
, NULL
, OPTION_SPECIAL_M32R
},
238 {"float", no_argument
, NULL
, OPTION_SPECIAL_FLOAT
},
239 /* Sigh. I guess all warnings must now have both variants. */
240 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
241 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
242 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
243 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
246 /* Not supported yet. */
247 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
248 #define OPTION_CPU_DESC (OPTION_RELAX + 1)
249 {"relax", no_argument
, NULL
, OPTION_RELAX
},
250 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
252 {NULL
, no_argument
, NULL
, 0}
255 size_t md_longopts_size
= sizeof (md_longopts
);
257 static void little (int);
258 static int parallel (void);
263 target_big_endian
= ! on
;
266 /* Use parallel execution. */
274 if (use_parallel
== 1)
281 md_parse_option (c
, arg
)
283 char *arg ATTRIBUTE_UNUSED
;
303 enable_special_m32r
= 1;
307 target_big_endian
= 1;
311 target_big_endian
= 0;
314 case OPTION_PARALLEL
:
318 case OPTION_NO_PARALLEL
:
322 case OPTION_WARN_PARALLEL
:
323 warn_explicit_parallel_conflicts
= 1;
326 case OPTION_NO_WARN_PARALLEL
:
327 warn_explicit_parallel_conflicts
= 0;
330 case OPTION_IGNORE_PARALLEL
:
331 ignore_parallel_conflicts
= 1;
334 case OPTION_NO_IGNORE_PARALLEL
:
335 ignore_parallel_conflicts
= 0;
343 /* Pretend that we do not recognise this option. */
344 as_bad (_("Unrecognised option: -hidden"));
349 case OPTION_SPECIAL_M32R
:
350 enable_special_m32r
= 1;
353 case OPTION_SPECIAL_FLOAT
:
354 enable_special_float
= 1;
357 case OPTION_WARN_UNMATCHED
:
358 warn_unmatched_high
= 1;
361 case OPTION_NO_WARN_UNMATCHED
:
362 warn_unmatched_high
= 0;
366 /* Not supported yet. */
370 case OPTION_CPU_DESC
:
383 md_show_usage (stream
)
386 fprintf (stream
, _(" M32R specific command line options:\n"));
388 fprintf (stream
, _("\
389 -m32r disable support for the m32rx instruction set\n"));
390 fprintf (stream
, _("\
391 -m32rx support the extended m32rx instruction set\n"));
392 fprintf (stream
, _("\
393 -m32r2 support the extended m32r2 instruction set\n"));
394 fprintf (stream
, _("\
395 -EL,-little produce little endian code and data\n"));
396 fprintf (stream
, _("\
397 -EB,-big produce big endian code and data\n"));
398 fprintf (stream
, _("\
399 -parallel try to combine instructions in parallel\n"));
400 fprintf (stream
, _("\
401 -no-parallel disable -parallel\n"));
402 fprintf (stream
, _("\
403 -O try to optimize code. Implies -parallel\n"));
405 fprintf (stream
, _("\
406 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
407 fprintf (stream
, _("\
408 might violate contraints\n"));
409 fprintf (stream
, _("\
410 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
411 fprintf (stream
, _("\
412 instructions might violate contraints\n"));
413 fprintf (stream
, _("\
414 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
415 fprintf (stream
, _("\
416 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
417 fprintf (stream
, _("\
418 -ignore-parallel-conflicts do not check parallel instructions\n"));
419 fprintf (stream
, _("\
420 fo contraint violations\n"));
421 fprintf (stream
, _("\
422 -no-ignore-parallel-conflicts check parallel instructions for\n"));
423 fprintf (stream
, _("\
424 contraint violations\n"));
425 fprintf (stream
, _("\
426 -Ip synonym for -ignore-parallel-conflicts\n"));
427 fprintf (stream
, _("\
428 -nIp synonym for -no-ignore-parallel-conflicts\n"));
430 fprintf (stream
, _("\
431 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
432 fprintf (stream
, _("\
433 -no-warn-unmatched-high do not warn about missing low relocs\n"));
434 fprintf (stream
, _("\
435 -Wuh synonym for -warn-unmatched-high\n"));
436 fprintf (stream
, _("\
437 -Wnuh synonym for -no-warn-unmatched-high\n"));
440 fprintf (stream
, _("\
441 -relax create linker relaxable code\n"));
442 fprintf (stream
, _("\
443 -cpu-desc provide runtime cpu description file\n"));
447 static void fill_insn
PARAMS ((int));
448 static void m32r_scomm
PARAMS ((int));
449 static void debug_sym
PARAMS ((int));
450 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
452 /* Set by md_assemble for use by m32r_fill_insn. */
453 static subsegT prev_subseg
;
454 static segT prev_seg
;
456 /* The target specific pseudo-ops which we support. */
457 const pseudo_typeS md_pseudo_table
[] =
460 { "fillinsn", fill_insn
, 0 },
461 { "scomm", m32r_scomm
, 0 },
462 { "debugsym", debug_sym
, 0 },
463 { "m32r", allow_m32rx
, 0 },
464 { "m32rx", allow_m32rx
, 1 },
465 { "m32r2", allow_m32rx
, 2 },
466 { "little", little
, 1 },
467 { "big", little
, 0 },
471 /* FIXME: Should be machine generated. */
472 #define NOP_INSN 0x7000
473 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
475 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
476 of an rs_align_code fragment. */
479 m32r_handle_align (fragp
)
482 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
483 static const unsigned char multi_nop_pattern
[] = { 0x70, 0x00, 0xf0, 0x00 };
488 if (fragp
->fr_type
!= rs_align_code
)
491 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
492 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
504 memcpy (p
, nop_pattern
, 2);
510 memcpy (p
, multi_nop_pattern
, 4);
512 fragp
->fr_fix
+= fix
;
516 /* If the last instruction was the first of 2 16 bit insns,
517 output a nop to move the PC to a 32 bit boundary.
519 This is done via an alignment specification since branch relaxing
520 may make it unnecessary.
522 Internally, we need to output one of these each time a 32 bit insn is
523 seen after an insn that is relaxable. */
527 int ignore ATTRIBUTE_UNUSED
;
529 frag_align_code (2, 0);
530 prev_insn
.insn
= NULL
;
531 seen_relaxable_p
= 0;
534 /* Record the symbol so that when we output the insn, we can create
535 a symbol that is at the start of the instruction. This is used
536 to emit the label for the start of a breakpoint without causing
537 the assembler to emit a NOP if the previous instruction was a
538 16 bit instruction. */
542 int ignore ATTRIBUTE_UNUSED
;
546 register char *end_name
;
547 register symbolS
*symbolP
;
548 register sym_linkS
*link
;
550 name
= input_line_pointer
;
551 delim
= get_symbol_end ();
552 end_name
= input_line_pointer
;
554 if ((symbolP
= symbol_find (name
)) == NULL
555 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
557 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
560 symbol_table_insert (symbolP
);
561 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
562 /* xgettext:c-format */
563 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
567 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
568 link
->symbol
= symbolP
;
569 link
->next
= debug_sym_link
;
570 debug_sym_link
= link
;
571 symbol_get_obj (symbolP
)->local
= 1;
575 demand_empty_rest_of_line ();
578 /* Second pass to expanding the debug symbols, go through linked
579 list of symbols and reassign the address. */
582 expand_debug_syms (syms
, align
)
586 char *save_input_line
= input_line_pointer
;
587 sym_linkS
*next_syms
;
592 (void) frag_align_code (align
, 0);
593 for (; syms
!= (sym_linkS
*) 0; syms
= next_syms
)
595 symbolS
*symbolP
= syms
->symbol
;
596 next_syms
= syms
->next
;
597 input_line_pointer
= ".\n";
598 pseudo_set (symbolP
);
599 free ((char *) syms
);
602 input_line_pointer
= save_input_line
;
606 m32r_flush_pending_output()
610 expand_debug_syms (debug_sym_link
, 1);
611 debug_sym_link
= (sym_linkS
*) 0;
615 /* Cover function to fill_insn called after a label and at end of assembly.
616 The result is always 1: we're called in a conditional to see if the
617 current line is a label. */
620 m32r_fill_insn (done
)
623 if (prev_seg
!= NULL
)
626 subsegT subseg
= now_subseg
;
628 subseg_set (prev_seg
, prev_subseg
);
632 subseg_set (seg
, subseg
);
635 if (done
&& debug_sym_link
)
637 expand_debug_syms (debug_sym_link
, 1);
638 debug_sym_link
= (sym_linkS
*) 0;
644 /* The default target format to use. */
647 m32r_target_format ()
650 if (target_big_endian
)
651 return "elf32-m32r-linux";
653 return "elf32-m32rle-linux";
655 if (target_big_endian
)
658 return "elf32-m32rle";
669 /* Initialize the `cgen' interface. */
671 /* Set the machine number and endian. */
672 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
673 CGEN_CPU_OPEN_ENDIAN
,
675 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
),
677 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
679 /* The operand instance table is used during optimization to determine
680 which insns can be executed in parallel. It is also used to give
681 warnings regarding operand interference in parallel insns. */
682 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
684 /* This is a callback from cgen to gas to parse operands. */
685 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
688 /* Not supported yet. */
689 /* If a runtime cpu description file was provided, parse it. */
690 if (m32r_cpu_desc
!= NULL
)
694 errmsg
= cgen_read_cpu_file (gas_cgen_cpu_desc
, m32r_cpu_desc
);
696 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
700 /* Save the current subseg so we can restore it [it's the default one and
701 we don't want the initial section to be .sbss]. */
705 /* The sbss section is for local .scomm symbols. */
706 sbss_section
= subseg_new (".sbss", 0);
708 /* This is copied from perform_an_assembly_pass. */
709 applicable
= bfd_applicable_section_flags (stdoutput
);
710 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
713 /* What does this do? [see perform_an_assembly_pass] */
714 seg_info (bss_section
)->bss
= 1;
717 subseg_set (seg
, subseg
);
719 /* We must construct a fake section similar to bfd_com_section
720 but with the name .scommon. */
721 scom_section
= bfd_com_section
;
722 scom_section
.name
= ".scommon";
723 scom_section
.output_section
= &scom_section
;
724 scom_section
.symbol
= &scom_symbol
;
725 scom_section
.symbol_ptr_ptr
= &scom_section
.symbol
;
726 scom_symbol
= *bfd_com_section
.symbol
;
727 scom_symbol
.name
= ".scommon";
728 scom_symbol
.section
= &scom_section
;
730 allow_m32rx (enable_m32rx
);
732 gas_cgen_initialize_saved_fixups_array ();
735 #define OPERAND_IS_COND_BIT(operand, indices, index) \
736 ((operand)->hw_type == HW_H_COND \
737 || ((operand)->hw_type == HW_H_PSW) \
738 || ((operand)->hw_type == HW_H_CR \
739 && (indices [index] == 0 || indices [index] == 1)))
741 /* Returns true if an output of instruction 'a' is referenced by an operand
742 of instruction 'b'. If 'check_outputs' is true then b's outputs are
743 checked, otherwise its inputs are examined. */
745 static int first_writes_to_seconds_operands
746 PARAMS ((m32r_insn
*, m32r_insn
*, const int));
749 first_writes_to_seconds_operands (a
, b
, check_outputs
)
752 const int check_outputs
;
754 const CGEN_OPINST
*a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
755 const CGEN_OPINST
*b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
758 if (ignore_parallel_conflicts
)
761 /* If at least one of the instructions takes no operands, then there is
762 nothing to check. There really are instructions without operands,
764 if (a_operands
== NULL
|| b_ops
== NULL
)
767 /* Scan the operand list of 'a' looking for an output operand. */
769 a_operands
->type
!= CGEN_OPINST_END
;
770 a_index
++, a_operands
++)
772 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
775 const CGEN_OPINST
*b_operands
= b_ops
;
778 The Condition bit 'C' is a shadow of the CBR register (control
779 register 1) and also a shadow of bit 31 of the program status
780 word (control register 0). For now this is handled here, rather
783 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
785 /* Scan operand list of 'b' looking for another reference to the
786 condition bit, which goes in the right direction. */
788 b_operands
->type
!= CGEN_OPINST_END
;
789 b_index
++, b_operands
++)
791 if ((b_operands
->type
794 : CGEN_OPINST_INPUT
))
795 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
801 /* Scan operand list of 'b' looking for an operand that
802 references the same hardware element, and which goes in the
805 b_operands
->type
!= CGEN_OPINST_END
;
806 b_index
++, b_operands
++)
808 if ((b_operands
->type
811 : CGEN_OPINST_INPUT
))
812 && (b_operands
->hw_type
== a_operands
->hw_type
)
813 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
823 /* Returns true if the insn can (potentially) alter the program counter. */
825 static int writes_to_pc
PARAMS ((m32r_insn
*));
832 /* Once PC operands are working.... */
833 const CGEN_OPINST
*a_operands
== CGEN_INSN_OPERANDS (gas_cgen_cpu_desc
,
836 if (a_operands
== NULL
)
839 while (a_operands
->type
!= CGEN_OPINST_END
)
841 if (a_operands
->operand
!= NULL
842 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc
,
843 a_operands
->operand
) == M32R_OPERAND_PC
)
849 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
850 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
856 /* Return NULL if the two 16 bit insns can be executed in parallel.
857 Otherwise return a pointer to an error message explaining why not. */
859 static const char *can_make_parallel
PARAMS ((m32r_insn
*, m32r_insn
*));
862 can_make_parallel (a
, b
)
869 /* Make sure the instructions are the right length. */
870 if (CGEN_FIELDS_BITSIZE (&a
->fields
) != 16
871 || CGEN_FIELDS_BITSIZE (&b
->fields
) != 16)
874 if (first_writes_to_seconds_operands (a
, b
, TRUE
))
875 return _("instructions write to the same destination register.");
877 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
878 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
880 /* Make sure that the instructions use the correct execution pipelines. */
881 if (a_pipe
== PIPE_NONE
882 || b_pipe
== PIPE_NONE
)
883 return _("Instructions do not use parallel execution pipelines.");
885 /* Leave this test for last, since it is the only test that can
886 go away if the instructions are swapped, and we want to make
887 sure that any other errors are detected before this happens. */
890 || (b_pipe
== PIPE_O_OS
&& (enable_m32rx
!= 2)))
891 return _("Instructions share the same execution pipeline");
896 /* Force the top bit of the second 16-bit insn to be set. */
898 static void make_parallel
PARAMS ((CGEN_INSN_BYTES_PTR
));
901 make_parallel (buffer
)
902 CGEN_INSN_BYTES_PTR buffer
;
907 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
912 /* Same as make_parallel except buffer contains the bytes in target order. */
914 static void target_make_parallel
PARAMS ((char *));
917 target_make_parallel (buffer
)
920 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
924 /* Assemble two instructions with an explicit parallel operation (||) or
925 sequential operation (->). */
927 static void assemble_two_insns
PARAMS ((char *, char *, int));
930 assemble_two_insns (str
, str2
, parallel_p
)
939 char save_str2
= *str2
;
941 /* Separate the two instructions. */
944 /* Make sure the two insns begin on a 32 bit boundary.
945 This is also done for the serial case (foo -> bar), relaxing doesn't
946 affect insns written like this.
947 Note that we must always do this as we can't assume anything about
948 whether we're currently on a 32 bit boundary or not. Relaxing may
952 first
.debug_sym_link
= debug_sym_link
;
953 debug_sym_link
= (sym_linkS
*) 0;
955 /* Parse the first instruction. */
956 if (! (first
.insn
= m32r_cgen_assemble_insn
957 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
964 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
966 /* xgettext:c-format */
967 as_bad (_("not a 16 bit instruction '%s'"), str
);
971 else if ((enable_m32rx
== 1)
972 /* FIXME: Need standard macro to perform this test. */
973 && ((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
975 && !((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
976 & (1 << MACH_M32RX
)))))
978 /* xgettext:c-format */
979 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
982 else if ((! enable_special
983 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
984 || (! enable_special_m32r
985 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_M32R
)))
987 else if (! enable_special
988 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
991 /* xgettext:c-format */
992 as_bad (_("unknown instruction '%s'"), str
);
995 else if (! enable_m32rx
996 /* FIXME: Need standard macro to perform this test. */
997 && (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
998 == (1 << MACH_M32RX
)))
1000 /* xgettext:c-format */
1001 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1005 /* Check to see if this is an allowable parallel insn. */
1007 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
1009 /* xgettext:c-format */
1010 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
1014 /* Restore the original assembly text, just in case it is needed. */
1017 /* Save the original string pointer. */
1020 /* Advanced past the parsed string. */
1023 /* Remember the entire string in case it is needed for error
1027 /* Convert the opcode to lower case. */
1031 while (ISSPACE (*s2
++))
1036 while (ISALNUM (*s2
))
1038 *s2
= TOLOWER (*s2
);
1043 /* Preserve any fixups that have been generated and reset the list
1045 gas_cgen_save_fixups (0);
1047 /* Get the indices of the operands of the instruction. */
1048 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
1049 doesn't seem right. Perhaps allow passing fields like we do insn. */
1050 /* FIXME: ALIAS insns do not have operands, so we use this function
1051 to find the equivalent insn and overwrite the value stored in our
1052 structure. We still need the original insn, however, since this
1053 may have certain attributes that are not present in the unaliased
1054 version (eg relaxability). When aliases behave differently this
1055 may have to change. */
1056 first
.orig_insn
= first
.insn
;
1058 CGEN_FIELDS tmp_fields
;
1059 first
.insn
= cgen_lookup_get_insn_operands
1060 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
1061 first
.indices
, &tmp_fields
);
1064 if (first
.insn
== NULL
)
1065 as_fatal (_("internal error: lookup/get operands failed"));
1067 second
.debug_sym_link
= NULL
;
1069 /* Parse the second instruction. */
1070 if (! (second
.insn
= m32r_cgen_assemble_insn
1071 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
1078 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
1080 /* xgettext:c-format */
1081 as_bad (_("not a 16 bit instruction '%s'"), str
);
1085 else if ((enable_m32rx
== 1)
1086 /* FIXME: Need standard macro to perform this test. */
1087 && ((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1088 & (1 << MACH_M32R2
))
1089 && !((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1090 & (1 << MACH_M32RX
)))))
1092 /* xgettext:c-format */
1093 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1096 else if ((! enable_special
1097 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1098 || (! enable_special_m32r
1099 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1101 else if (! enable_special
1102 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1105 /* xgettext:c-format */
1106 as_bad (_("unknown instruction '%s'"), str
);
1109 else if (! enable_m32rx
1110 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1112 /* xgettext:c-format */
1113 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1117 /* Check to see if this is an allowable parallel insn. */
1119 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
1121 /* xgettext:c-format */
1122 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
1126 if (parallel_p
&& ! enable_m32rx
)
1128 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
1129 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
1131 /* xgettext:c-format */
1132 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
1137 /* Get the indices of the operands of the instruction. */
1138 second
.orig_insn
= second
.insn
;
1140 CGEN_FIELDS tmp_fields
;
1141 second
.insn
= cgen_lookup_get_insn_operands
1142 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
1143 second
.indices
, &tmp_fields
);
1146 if (second
.insn
== NULL
)
1147 as_fatal (_("internal error: lookup/get operands failed"));
1149 /* We assume that if the first instruction writes to a register that is
1150 read by the second instruction it is because the programmer intended
1151 this to happen, (after all they have explicitly requested that these
1152 two instructions be executed in parallel). Although if the global
1153 variable warn_explicit_parallel_conflicts is true then we do generate
1154 a warning message. Similarly we assume that parallel branch and jump
1155 instructions are deliberate and should not produce errors. */
1157 if (parallel_p
&& warn_explicit_parallel_conflicts
)
1159 if (first_writes_to_seconds_operands (&first
, &second
, FALSE
))
1160 /* xgettext:c-format */
1161 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
1163 if (first_writes_to_seconds_operands (&second
, &first
, FALSE
))
1164 /* xgettext:c-format */
1165 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
1169 || (errmsg
= (char *) can_make_parallel (&first
, &second
)) == NULL
)
1171 /* Get the fixups for the first instruction. */
1172 gas_cgen_swap_fixups (0);
1175 expand_debug_syms (first
.debug_sym_link
, 1);
1176 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
1177 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
1179 /* Force the top bit of the second insn to be set. */
1181 make_parallel (second
.buffer
);
1183 /* Get its fixups. */
1184 gas_cgen_restore_fixups (0);
1187 expand_debug_syms (second
.debug_sym_link
, 1);
1188 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
1189 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
1191 /* Try swapping the instructions to see if they work that way. */
1192 else if (can_make_parallel (&second
, &first
) == NULL
)
1194 /* Write out the second instruction first. */
1195 expand_debug_syms (second
.debug_sym_link
, 1);
1196 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
1197 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
1199 /* Force the top bit of the first instruction to be set. */
1200 make_parallel (first
.buffer
);
1202 /* Get the fixups for the first instruction. */
1203 gas_cgen_restore_fixups (0);
1205 /* Write out the first instruction. */
1206 expand_debug_syms (first
.debug_sym_link
, 1);
1207 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
1208 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
1212 as_bad ("'%s': %s", str2
, errmsg
);
1216 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
)
1217 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1218 m32r_flags
|= E_M32R_HAS_HIDDEN_INST
;
1219 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_M32R
)
1220 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_M32R
))
1221 m32r_flags
|= E_M32R_HAS_BIT_INST
;
1222 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_FLOAT
)
1223 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_FLOAT
))
1224 m32r_flags
|= E_M32R_HAS_FLOAT_INST
;
1226 /* Set these so m32r_fill_insn can use them. */
1228 prev_subseg
= now_subseg
;
1239 /* Initialize GAS's cgen interface for a new instruction. */
1240 gas_cgen_init_parse ();
1242 /* Look for a parallel instruction separator. */
1243 if ((str2
= strstr (str
, "||")) != NULL
)
1245 assemble_two_insns (str
, str2
, 1);
1246 m32r_flags
|= E_M32R_HAS_PARALLEL
;
1250 /* Also look for a sequential instruction separator. */
1251 if ((str2
= strstr (str
, "->")) != NULL
)
1253 assemble_two_insns (str
, str2
, 0);
1257 insn
.debug_sym_link
= debug_sym_link
;
1258 debug_sym_link
= (sym_linkS
*) 0;
1260 insn
.insn
= m32r_cgen_assemble_insn
1261 (gas_cgen_cpu_desc
, str
, &insn
.fields
, insn
.buffer
, & errmsg
);
1270 if ((enable_m32rx
== 1)
1271 /* FIXME: Need standard macro to perform this test. */
1272 && ((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
)
1273 & (1 << MACH_M32R2
))
1274 && !((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
)
1275 & (1 << MACH_M32RX
)))))
1277 /* xgettext:c-format */
1278 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1281 else if ((! enable_special
1282 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1283 || (! enable_special_m32r
1284 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1286 if (! enable_special
1287 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1290 /* xgettext:c-format */
1291 as_bad (_("unknown instruction '%s'"), str
);
1294 else if (! enable_m32rx
1295 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1297 /* xgettext:c-format */
1298 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1302 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1303 m32r_flags
|= E_M32R_HAS_HIDDEN_INST
;
1304 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_M32R
))
1305 m32r_flags
|= E_M32R_HAS_BIT_INST
;
1306 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_FLOAT
))
1307 m32r_flags
|= E_M32R_HAS_FLOAT_INST
;
1309 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1311 /* 32 bit insns must live on 32 bit boundaries. */
1312 if (prev_insn
.insn
|| seen_relaxable_p
)
1314 /* ??? If calling fill_insn too many times turns us into a memory
1315 pig, can we call a fn to assemble a nop instead of
1316 !seen_relaxable_p? */
1320 expand_debug_syms (insn
.debug_sym_link
, 2);
1322 /* Doesn't really matter what we pass for RELAX_P here. */
1323 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1324 CGEN_FIELDS_BITSIZE (&insn
.fields
), 1, NULL
);
1328 int on_32bit_boundary_p
;
1331 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1334 insn
.orig_insn
= insn
.insn
;
1336 /* If the previous insn was relaxable, then it may be expanded
1337 to fill the current 16 bit slot. Emit a NOP here to occupy
1338 this slot, so that we can start at optimizing at a 32 bit
1340 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1345 /* Get the indices of the operands of the instruction.
1346 FIXME: See assemble_parallel for notes on orig_insn. */
1348 CGEN_FIELDS tmp_fields
;
1349 insn
.insn
= cgen_lookup_get_insn_operands
1350 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1351 16, insn
.indices
, &tmp_fields
);
1354 if (insn
.insn
== NULL
)
1355 as_fatal (_("internal error: lookup/get operands failed"));
1358 /* Compute whether we're on a 32 bit boundary or not.
1359 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1360 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1362 /* Look to see if this instruction can be combined with the
1363 previous instruction to make one, parallel, 32 bit instruction.
1364 If the previous instruction (potentially) changed the flow of
1365 program control, then it cannot be combined with the current
1366 instruction. If the current instruction is relaxable, then it
1367 might be replaced with a longer version, so we cannot combine it.
1368 Also if the output of the previous instruction is used as an
1369 input to the current instruction then it cannot be combined.
1370 Otherwise call can_make_parallel() with both orderings of the
1371 instructions to see if they can be combined. */
1372 if (! on_32bit_boundary_p
1374 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1375 && ! writes_to_pc (&prev_insn
)
1376 && ! first_writes_to_seconds_operands (&prev_insn
, &insn
, FALSE
))
1378 if (can_make_parallel (&prev_insn
, &insn
) == NULL
)
1379 make_parallel (insn
.buffer
);
1380 else if (can_make_parallel (&insn
, &prev_insn
) == NULL
)
1384 expand_debug_syms (insn
.debug_sym_link
, 1);
1390 /* Ensure each pair of 16 bit insns is in the same frag. */
1393 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1394 CGEN_FIELDS_BITSIZE (&insn
.fields
),
1395 1 /* relax_p */, &fi
);
1396 insn
.addr
= fi
.addr
;
1397 insn
.frag
= fi
.frag
;
1398 insn
.num_fixups
= fi
.num_fixups
;
1399 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1400 insn
.fixups
[i
] = fi
.fixups
[i
];
1407 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1409 /* Swap the two insns */
1410 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1411 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1413 target_make_parallel (insn
.addr
);
1415 /* Swap any relaxable frags recorded for the two insns. */
1416 /* FIXME: Clarify. relaxation precludes parallel insns */
1417 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1418 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1419 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1420 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1422 /* Update the addresses in any fixups.
1423 Note that we don't have to handle the case where each insn is in
1424 a different frag as we ensure they're in the same frag above. */
1425 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1426 prev_insn
.fixups
[i
]->fx_where
+= 2;
1427 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1428 insn
.fixups
[i
]->fx_where
-= 2;
1431 /* Keep track of whether we've seen a pair of 16 bit insns.
1432 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1433 if (on_32bit_boundary_p
)
1436 prev_insn
.insn
= NULL
;
1438 /* If the insn needs the following one to be on a 32 bit boundary
1439 (e.g. subroutine calls), fill this insn's slot. */
1440 if (on_32bit_boundary_p
1441 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1444 /* If this is a relaxable insn (can be replaced with a larger version)
1445 mark the fact so that we can emit an alignment directive for a
1446 following 32 bit insn if we see one. */
1447 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1448 seen_relaxable_p
= 1;
1451 /* Set these so m32r_fill_insn can use them. */
1453 prev_subseg
= now_subseg
;
1456 /* The syntax in the manual says constants begin with '#'.
1457 We just ignore it. */
1460 md_operand (expressionP
)
1461 expressionS
*expressionP
;
1463 if (*input_line_pointer
== '#')
1465 input_line_pointer
++;
1466 expression (expressionP
);
1471 md_section_align (segment
, size
)
1475 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1476 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1480 md_undefined_symbol (name
)
1481 char *name ATTRIBUTE_UNUSED
;
1486 /* .scomm pseudo-op handler.
1488 This is a new pseudo-op to handle putting objects in .scommon.
1489 By doing this the linker won't need to do any work,
1490 and more importantly it removes the implicit -G arg necessary to
1491 correctly link the object file. */
1495 int ignore ATTRIBUTE_UNUSED
;
1497 register char *name
;
1501 register symbolS
*symbolP
;
1505 name
= input_line_pointer
;
1506 c
= get_symbol_end ();
1508 /* Just after name is now '\0'. */
1509 p
= input_line_pointer
;
1512 if (*input_line_pointer
!= ',')
1514 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1515 ignore_rest_of_line ();
1520 input_line_pointer
++;
1521 if ((size
= get_absolute_expression ()) < 0)
1523 /* xgettext:c-format */
1524 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1525 ignore_rest_of_line ();
1529 /* The third argument to .scomm is the alignment. */
1530 if (*input_line_pointer
!= ',')
1534 ++input_line_pointer
;
1535 align
= get_absolute_expression ();
1538 as_warn (_("ignoring bad alignment"));
1543 /* Convert to a power of 2 alignment. */
1546 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
)
1550 as_bad (_("Common alignment not a power of 2"));
1551 ignore_rest_of_line ();
1559 symbolP
= symbol_find_or_make (name
);
1562 if (S_IS_DEFINED (symbolP
))
1564 /* xgettext:c-format */
1565 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1566 S_GET_NAME (symbolP
));
1567 ignore_rest_of_line ();
1571 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1573 /* xgettext:c-format */
1574 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1575 S_GET_NAME (symbolP
),
1576 (long) S_GET_VALUE (symbolP
),
1579 ignore_rest_of_line ();
1583 if (symbol_get_obj (symbolP
)->local
)
1585 segT old_sec
= now_seg
;
1586 int old_subsec
= now_subseg
;
1589 record_alignment (sbss_section
, align2
);
1590 subseg_set (sbss_section
, 0);
1593 frag_align (align2
, 0, 0);
1595 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1596 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1598 symbol_set_frag (symbolP
, frag_now
);
1600 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1603 S_SET_SIZE (symbolP
, size
);
1604 S_SET_SEGMENT (symbolP
, sbss_section
);
1605 S_CLEAR_EXTERNAL (symbolP
);
1606 subseg_set (old_sec
, old_subsec
);
1610 S_SET_VALUE (symbolP
, (valueT
) size
);
1611 S_SET_ALIGN (symbolP
, align2
);
1612 S_SET_EXTERNAL (symbolP
);
1613 S_SET_SEGMENT (symbolP
, &scom_section
);
1616 demand_empty_rest_of_line ();
1619 /* Interface to relax_segment. */
1621 /* FIXME: Build table by hand, get it working, then machine generate. */
1623 const relax_typeS md_relax_table
[] =
1626 1) most positive reach of this state,
1627 2) most negative reach of this state,
1628 3) how many bytes this mode will add to the size of the current frag
1629 4) which index into the table to try if we can't fit into this one. */
1631 /* The first entry must be unused because an `rlx_more' value of zero ends
1635 /* The displacement used by GAS is from the end of the 2 byte insn,
1636 so we subtract 2 from the following. */
1637 /* 16 bit insn, 8 bit disp -> 10 bit range.
1638 This doesn't handle a branch in the right slot at the border:
1639 the "& -4" isn't taken into account. It's not important enough to
1640 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1642 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1643 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1644 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1645 /* Same thing, but with leading nop for alignment. */
1646 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1650 m32r_relax_frag (segment
, fragP
, stretch
)
1655 /* Address of branch insn. */
1656 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1659 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1660 if (fragP
->fr_subtype
== 2)
1662 if ((address
& 3) != 0)
1664 fragP
->fr_subtype
= 3;
1668 else if (fragP
->fr_subtype
== 3)
1670 if ((address
& 3) == 0)
1672 fragP
->fr_subtype
= 2;
1678 growth
= relax_frag (segment
, fragP
, stretch
);
1680 /* Long jump on odd halfword boundary? */
1681 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1683 fragP
->fr_subtype
= 3;
1691 /* Return an initial guess of the length by which a fragment must grow to
1692 hold a branch to reach its destination.
1693 Also updates fr_type/fr_subtype as necessary.
1695 Called just before doing relaxation.
1696 Any symbol that is now undefined will not become defined.
1697 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1698 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1699 Although it may not be explicit in the frag, pretend fr_var starts
1703 md_estimate_size_before_relax (fragP
, segment
)
1707 /* The only thing we have to handle here are symbols outside of the
1708 current segment. They may be undefined or in a different segment in
1709 which case linker scripts may place them anywhere.
1710 However, we can't finish the fragment here and emit the reloc as insn
1711 alignment requirements may move the insn about. */
1713 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1716 int old_fr_fix
= fragP
->fr_fix
;
1719 /* The symbol is undefined in this segment.
1720 Change the relaxation subtype to the max allowable and leave
1721 all further handling to md_convert_frag. */
1722 fragP
->fr_subtype
= 2;
1725 /* Can't use this, but leave in for illustration. */
1726 /* Change 16 bit insn to 32 bit insn. */
1727 fragP
->fr_opcode
[0] |= 0x80;
1729 /* Increase known (fixed) size of fragment. */
1732 /* Create a relocation for it. */
1733 fix_new (fragP
, old_fr_fix
, 4,
1735 fragP
->fr_offset
, 1 /* pcrel */,
1736 /* FIXME: Can't use a real BFD reloc here.
1737 gas_cgen_md_apply_fix3 can't handle it. */
1738 BFD_RELOC_M32R_26_PCREL
);
1740 /* Mark this fragment as finished. */
1742 return fragP
->fr_fix
- old_fr_fix
;
1745 const CGEN_INSN
*insn
;
1748 /* Update the recorded insn.
1749 Fortunately we don't have to look very far.
1750 FIXME: Change this to record in the instruction the next higher
1751 relaxable insn to use. */
1752 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1754 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1755 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1757 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAXED
))
1763 fragP
->fr_cgen
.insn
= insn
;
1769 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
1772 /* *FRAGP has been relaxed to its final size, and now needs to have
1773 the bytes inside it modified to conform to the new size.
1775 Called after relaxation is finished.
1776 fragP->fr_type == rs_machine_dependent.
1777 fragP->fr_subtype is the subtype of what the address relaxed to. */
1780 md_convert_frag (abfd
, sec
, fragP
)
1781 bfd
*abfd ATTRIBUTE_UNUSED
;
1792 opcode
= fragP
->fr_opcode
;
1794 /* Address opcode resides at in file space. */
1795 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1797 switch (fragP
->fr_subtype
)
1801 displacement
= &opcode
[1];
1806 displacement
= &opcode
[1];
1809 opcode
[2] = opcode
[0] | 0x80;
1810 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1811 opcode_address
+= 2;
1813 displacement
= &opcode
[3];
1819 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1821 /* Symbol must be resolved by linker. */
1822 if (fragP
->fr_offset
& 3)
1823 as_warn (_("Addend to unresolved symbol not on word boundary."));
1824 addend
= fragP
->fr_offset
>> 2;
1828 /* Address we want to reach in file space. */
1829 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1830 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1833 /* Create a relocation for symbols that must be resolved by the linker.
1834 Otherwise output the completed insn. */
1836 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1838 assert (fragP
->fr_subtype
!= 1);
1839 assert (fragP
->fr_cgen
.insn
!= 0);
1840 gas_cgen_record_fixup (fragP
,
1841 /* Offset of branch insn in frag. */
1842 fragP
->fr_fix
+ extension
- 4,
1843 fragP
->fr_cgen
.insn
,
1845 /* FIXME: quick hack. */
1847 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1848 fragP
->fr_cgen
.opindex
),
1850 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1851 M32R_OPERAND_DISP24
),
1853 fragP
->fr_cgen
.opinfo
,
1854 fragP
->fr_symbol
, fragP
->fr_offset
);
1857 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1859 md_number_to_chars (displacement
, (valueT
) addend
,
1860 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1862 fragP
->fr_fix
+= extension
;
1865 /* Functions concerning relocs. */
1867 /* The location from which a PC relative jump should be calculated,
1868 given a PC relative reloc. */
1871 md_pcrel_from_section (fixP
, sec
)
1875 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1876 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1877 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1879 /* The symbol is undefined (or is defined but not in this section).
1880 Let the linker figure it out. */
1884 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1887 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1888 Returns BFD_RELOC_NONE if no reloc type can be found.
1889 *FIXP may be modified if desired. */
1891 bfd_reloc_code_real_type
1892 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1893 const CGEN_INSN
*insn ATTRIBUTE_UNUSED
;
1894 const CGEN_OPERAND
*operand
;
1897 switch (operand
->type
)
1899 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1900 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1901 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1902 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1903 case M32R_OPERAND_HI16
:
1904 case M32R_OPERAND_SLO16
:
1905 case M32R_OPERAND_ULO16
:
1906 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1907 if (fixP
->fx_cgen
.opinfo
!= 0)
1908 return fixP
->fx_cgen
.opinfo
;
1911 /* Avoid -Wall warning. */
1914 return BFD_RELOC_NONE
;
1917 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1919 static void m32r_record_hi16
PARAMS ((int, fixS
*, segT
));
1922 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1925 segT seg ATTRIBUTE_UNUSED
;
1927 struct m32r_hi_fixup
*hi_fixup
;
1929 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1930 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1932 hi_fixup
= ((struct m32r_hi_fixup
*)
1933 xmalloc (sizeof (struct m32r_hi_fixup
)));
1934 hi_fixup
->fixp
= fixP
;
1935 hi_fixup
->seg
= now_seg
;
1936 hi_fixup
->next
= m32r_hi_fixup_list
;
1938 m32r_hi_fixup_list
= hi_fixup
;
1941 /* Called while parsing an instruction to create a fixup.
1942 We need to check for HI16 relocs and queue them up for later sorting. */
1945 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1948 const CGEN_INSN
*insn
;
1950 const CGEN_OPERAND
*operand
;
1954 fixS
*fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1955 operand
, opinfo
, exp
);
1957 switch (operand
->type
)
1959 case M32R_OPERAND_HI16
:
1960 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1961 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1962 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1963 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
1966 /* Avoid -Wall warning */
1973 /* Return BFD reloc type from opinfo field in a fixS.
1974 It's tricky using fx_r_type in m32r_frob_file because the values
1975 are BFD_RELOC_UNUSED + operand number. */
1976 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1978 /* Sort any unmatched HI16 relocs so that they immediately precede
1979 the corresponding LO16 reloc. This is called before md_apply_fix3 and
1985 struct m32r_hi_fixup
*l
;
1987 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1989 segment_info_type
*seginfo
;
1992 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1993 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1995 /* Check quickly whether the next fixup happens to be a matching low. */
1996 if (l
->fixp
->fx_next
!= NULL
1997 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1998 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1999 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
2002 /* Look through the fixups for this segment for a matching `low'.
2003 When we find one, move the high/shigh just in front of it. We do
2004 this in two passes. In the first pass, we try to find a
2005 unique `low'. In the second pass, we permit multiple high's
2006 relocs for a single `low'. */
2007 seginfo
= seg_info (l
->seg
);
2008 for (pass
= 0; pass
< 2; pass
++)
2014 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
2016 /* Check whether this is a `low' fixup which matches l->fixp. */
2017 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
2018 && f
->fx_addsy
== l
->fixp
->fx_addsy
2019 && f
->fx_offset
== l
->fixp
->fx_offset
2022 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
2023 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
2024 || prev
->fx_addsy
!= f
->fx_addsy
2025 || prev
->fx_offset
!= f
->fx_offset
))
2029 /* Move l->fixp before f. */
2030 for (pf
= &seginfo
->fix_root
;
2032 pf
= & (*pf
)->fx_next
)
2033 assert (*pf
!= NULL
);
2035 *pf
= l
->fixp
->fx_next
;
2037 l
->fixp
->fx_next
= f
;
2039 seginfo
->fix_root
= l
->fixp
;
2041 prev
->fx_next
= l
->fixp
;
2053 && warn_unmatched_high
)
2054 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
2055 _("Unmatched high/shigh reloc"));
2060 /* See whether we need to force a relocation into the output file.
2061 This is used to force out switch and PC relative relocations when
2065 m32r_force_relocation (fix
)
2068 if (generic_force_reloc (fix
))
2074 return fix
->fx_pcrel
;
2077 /* Write a value out to the object file, using the appropriate endianness. */
2080 md_number_to_chars (buf
, val
, n
)
2085 if (target_big_endian
)
2086 number_to_chars_bigendian (buf
, val
, n
);
2088 number_to_chars_littleendian (buf
, val
, n
);
2091 /* Turn a string in input_line_pointer into a floating point constant
2092 of type TYPE, and store the appropriate bytes in *LITP. The number
2093 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2094 returned, or NULL on OK. */
2096 /* Equal to MAX_PRECISION in atof-ieee.c. */
2097 #define MAX_LITTLENUMS 6
2100 md_atof (type
, litP
, sizeP
)
2107 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2126 /* FIXME: Some targets allow other format chars for bigger sizes
2131 return _("Bad call to md_atof()");
2134 t
= atof_ieee (input_line_pointer
, type
, words
);
2136 input_line_pointer
= t
;
2137 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2139 if (target_big_endian
)
2141 for (i
= 0; i
< prec
; i
++)
2143 md_number_to_chars (litP
, (valueT
) words
[i
],
2144 sizeof (LITTLENUM_TYPE
));
2145 litP
+= sizeof (LITTLENUM_TYPE
);
2150 for (i
= prec
- 1; i
>= 0; i
--)
2152 md_number_to_chars (litP
, (valueT
) words
[i
],
2153 sizeof (LITTLENUM_TYPE
));
2154 litP
+= sizeof (LITTLENUM_TYPE
);
2162 m32r_elf_section_change_hook ()
2164 /* If we have reached the end of a section and we have just emitted a
2165 16 bit insn, then emit a nop to make sure that the section ends on
2166 a 32 bit boundary. */
2168 if (prev_insn
.insn
|| seen_relaxable_p
)
2169 (void) m32r_fill_insn (0);
2172 /* Return true if can adjust the reloc to be relative to its section
2173 (such as .data) instead of relative to some symbol. */
2176 m32r_fix_adjustable (fixP
)
2179 bfd_reloc_code_real_type reloc_type
;
2181 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
2183 const CGEN_INSN
*insn
= NULL
;
2184 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
2185 const CGEN_OPERAND
*operand
=
2186 cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
2187 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
2190 reloc_type
= fixP
->fx_r_type
;
2192 /* We need the symbol name for the VTABLE entries. */
2193 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
2194 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)
2201 m32r_elf_final_processing ()
2204 m32r_flags
|= E_M32R_HAS_PARALLEL
;
2205 elf_elfheader (stdoutput
)->e_flags
|= m32r_flags
;