1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
28 /* Structure to hold all of the different components describing an individual instruction. */
31 const CGEN_INSN
* insn
;
32 const CGEN_INSN
* orig_insn
;
35 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
37 char buffer
[CGEN_MAX_INSN_SIZE
];
41 int indices
[MAX_OPERAND_INSTANCES
];
45 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
46 boundary (i.e. was the first of two 16 bit insns). */
47 static m32r_insn prev_insn
;
49 /* Non-zero if we've seen a relaxable insn since the last 32 bit
51 static int seen_relaxable_p
= 0;
53 /* Non-zero if -relax specified, in which case sufficient relocs are output
54 for the linker to do relaxing.
55 We do simple forms of relaxing internally, but they are always done.
56 This flag does not apply to them. */
57 static int m32r_relax
;
59 /* If non-NULL, pointer to cpu description file to read.
60 This allows runtime additions to the assembler. */
61 static char * m32r_cpu_desc
;
63 /* start-sanitize-m32rx */
64 /* Non-zero if -m32rx has been specified, in which case support for the
65 extended M32RX instruction set should be enabled. */
66 static int enable_m32rx
= 0;
68 /* Non-zero if the programmer should be warned when an explicit parallel
69 instruction might have constraint violations. */
70 static int warn_explicit_parallel_conflicts
= 1;
72 /* start-sanitize-phase2-m32rx */
73 /* Non-zero if insns can be made parallel. */
75 /* end-sanitize-phase2-m32rx */
76 /* end-sanitize-m32rx */
78 /* stuff for .scomm symbols. */
79 static segT sbss_section
;
80 static asection scom_section
;
81 static asymbol scom_symbol
;
83 const char comment_chars
[] = ";";
84 const char line_comment_chars
[] = "#";
85 const char line_separator_chars
[] = "";
86 const char EXP_CHARS
[] = "eE";
87 const char FLT_CHARS
[] = "dD";
89 /* Relocations against symbols are done in two
90 parts, with a HI relocation and a LO relocation. Each relocation
91 has only 16 bits of space to store an addend. This means that in
92 order for the linker to handle carries correctly, it must be able
93 to locate both the HI and the LO relocation. This means that the
94 relocations must appear in order in the relocation table.
96 In order to implement this, we keep track of each unmatched HI
97 relocation. We then sort them so that they immediately precede the
98 corresponding LO relocation. */
102 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
103 fixS
* fixp
; /* This fixup. */
104 segT seg
; /* The section this fixup is in. */
108 /* The list of unmatched HI relocs. */
110 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
113 /* start-sanitize-m32rx */
120 if (stdoutput
!= NULL
)
121 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
122 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
124 /* end-sanitize-m32rx */
126 #define M32R_SHORTOPTS ""
127 /* start-sanitize-phase2-m32rx */
128 #undef M32R_SHORTOPTS
129 #define M32R_SHORTOPTS "O"
130 /* end-sanitize-phase2-m32rx */
131 const char * md_shortopts
= M32R_SHORTOPTS
;
133 struct option md_longopts
[] =
135 /* start-sanitize-m32rx */
136 #define OPTION_M32RX (OPTION_MD_BASE)
137 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
138 #define OPTION_WARN (OPTION_MD_BASE + 1)
139 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN
},
140 {"Wp", no_argument
, NULL
, OPTION_WARN
},
141 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
142 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN
},
143 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN
},
144 /* end-sanitize-m32rx */
146 #if 0 /* not supported yet */
147 #define OPTION_RELAX (OPTION_MD_BASE + 3)
148 {"relax", no_argument
, NULL
, OPTION_RELAX
},
149 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
150 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
153 {NULL
, no_argument
, NULL
, 0}
155 size_t md_longopts_size
= sizeof (md_longopts
);
158 md_parse_option (c
, arg
)
164 /* start-sanitize-m32rx */
165 /* start-sanitize-phase2-m32rx */
169 /* end-sanitize-phase2-m32rx */
176 warn_explicit_parallel_conflicts
= 1;
180 warn_explicit_parallel_conflicts
= 0;
182 /* end-sanitize-m32rx */
184 #if 0 /* not supported yet */
188 case OPTION_CPU_DESC
:
199 md_show_usage (stream
)
202 /* start-sanitize-m32rx */
203 fprintf (stream
, _("M32R/X specific command line options:\n"));
204 fprintf (stream
, _("\
205 --m32rx support the extended m32rx instruction set\n"));
207 /* start-sanitize-phase2-m32rx */
208 fprintf (stream
, _("\
209 -O try to combine instructions in parallel\n"));
210 /* end-sanitize-phase2-m32rx */
212 fprintf (stream
, _("\
213 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
214 fprintf (stream
, _("\
215 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
216 fprintf (stream
, _("\
217 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
218 fprintf (stream
, _("\
219 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
220 /* end-sanitize-m32rx */
223 fprintf (stream
, _("\
224 --relax create linker relaxable code\n"));
225 fprintf (stream
, _("\
226 --cpu-desc provide runtime cpu description file\n"));
230 static void fill_insn
PARAMS ((int));
231 static void m32r_scomm
PARAMS ((int));
233 /* Set by md_assemble for use by m32r_fill_insn. */
234 static subsegT prev_subseg
;
235 static segT prev_seg
;
237 /* The target specific pseudo-ops which we support. */
238 const pseudo_typeS md_pseudo_table
[] =
241 { "fillinsn", fill_insn
, 0 },
242 { "scomm", m32r_scomm
, 0 },
243 /* start-sanitize-m32rx */
244 { "m32r", allow_m32rx
, 0},
245 { "m32rx", allow_m32rx
, 1},
246 /* end-sanitize-m32rx */
250 /* FIXME: Should be machine generated. */
251 #define NOP_INSN 0x7000
252 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
254 /* When we align the .text section, insert the correct NOP pattern.
255 N is the power of 2 alignment. LEN is the length of pattern FILL.
256 MAX is the maximum number of characters to skip when doing the alignment,
257 or 0 if there is no maximum. */
260 m32r_do_align (n
, fill
, len
, max
)
266 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
267 && (now_seg
->flags
& SEC_CODE
) != 0
268 /* Only do this special handling if aligning to at least a
271 /* Only do this special handling if we're allowed to emit at
273 && (max
== 0 || max
> 1))
275 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
278 /* First align to a 2 byte boundary, in case there is an odd .byte. */
279 /* FIXME: How much memory will cause gas to use when assembling a big
280 program? Perhaps we can avoid the frag_align call? */
281 frag_align (1, 0, 0);
283 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
285 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
286 /* If doing larger alignments use a repeating sequence of appropriate
290 static const unsigned char multi_nop_pattern
[] =
291 { 0x70, 0x00, 0xf0, 0x00 };
292 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
302 assemble_nop (opcode
)
305 char * f
= frag_more (2);
306 md_number_to_chars (f
, opcode
, 2);
309 /* If the last instruction was the first of 2 16 bit insns,
310 output a nop to move the PC to a 32 bit boundary.
312 This is done via an alignment specification since branch relaxing
313 may make it unnecessary.
315 Internally, we need to output one of these each time a 32 bit insn is
316 seen after an insn that is relaxable. */
322 (void) m32r_do_align (2, NULL
, 0, 0);
323 prev_insn
.insn
= NULL
;
324 seen_relaxable_p
= 0;
327 /* Cover function to fill_insn called after a label and at end of assembly.
329 The result is always 1: we're called in a conditional to see if the
330 current line is a label. */
333 m32r_fill_insn (done
)
336 if (prev_seg
!= NULL
)
339 subsegT subseg
= now_subseg
;
341 subseg_set (prev_seg
, prev_subseg
);
345 subseg_set (seg
, subseg
);
358 /* Initialize the `cgen' interface. */
360 /* This is a callback from cgen to gas to parse operands. */
361 cgen_parse_operand_fn
= cgen_parse_operand
;
363 /* Set the machine number and endian. */
364 CGEN_SYM (init_asm
) (0 /* mach number */,
366 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
368 #if 0 /* not supported yet */
369 /* If a runtime cpu description file was provided, parse it. */
370 if (m32r_cpu_desc
!= NULL
)
374 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
376 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
380 /* Save the current subseg so we can restore it [it's the default one and
381 we don't want the initial section to be .sbss]. */
385 /* The sbss section is for local .scomm symbols. */
386 sbss_section
= subseg_new (".sbss", 0);
388 /* This is copied from perform_an_assembly_pass. */
389 applicable
= bfd_applicable_section_flags (stdoutput
);
390 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
392 #if 0 /* What does this do? [see perform_an_assembly_pass] */
393 seg_info (bss_section
)->bss
= 1;
396 subseg_set (seg
, subseg
);
398 /* We must construct a fake section similar to bfd_com_section
399 but with the name .scommon. */
400 scom_section
= bfd_com_section
;
401 scom_section
.name
= ".scommon";
402 scom_section
.output_section
= & scom_section
;
403 scom_section
.symbol
= & scom_symbol
;
404 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
405 scom_symbol
= * bfd_com_section
.symbol
;
406 scom_symbol
.name
= ".scommon";
407 scom_symbol
.section
= & scom_section
;
409 /* start-sanitize-m32rx */
410 allow_m32rx (enable_m32rx
);
411 /* end-sanitize-m32rx */
414 /* start-sanitize-m32rx */
416 #define OPERAND_IS_COND_BIT(operand, indices, index) \
417 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
418 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
419 && (indices [index] == 0 || indices [index] == 1)))
421 /* Returns true if an output of instruction 'a' is referenced by an operand
422 of instruction 'b'. If 'check_outputs' is true then b's outputs are
423 checked, otherwise its inputs are examined. */
426 first_writes_to_seconds_operands (a
, b
, check_outputs
)
429 const int check_outputs
;
431 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
432 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
435 /* If at least one of the instructions takes no operands, then there is
436 nothing to check. There really are instructions without operands,
438 if (a_operands
== NULL
|| b_ops
== NULL
)
441 /* Scan the operand list of 'a' looking for an output operand. */
443 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
444 a_index
++, a_operands
++)
446 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
449 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
452 The Condition bit 'C' is a shadow of the CBR register (control
453 register 1) and also a shadow of bit 31 of the program status
454 word (control register 0). For now this is handled here, rather
457 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
459 /* Scan operand list of 'b' looking for another reference to the
460 condition bit, which goes in the right direction. */
462 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
463 b_index
++, b_operands
++)
465 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
466 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
467 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
473 /* Scan operand list of 'b' looking for an operand that references
474 the same hardware element, and which goes in the right direction. */
476 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
477 b_index
++, b_operands
++)
479 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
480 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
481 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
482 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
492 /* Returns true if the insn can (potentially) alter the program counter. */
498 #if 0 /* Once PC operands are working.... */
499 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
501 if (a_operands
== NULL
)
504 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
506 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
507 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
513 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
514 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
520 /* Returns NULL if the two 16 bit insns can be executed in parallel,
521 otherwise it returns a pointer to an error message explaining why not. */
524 can_make_parallel (a
, b
)
531 /* Make sure the instructions are the right length. */
532 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
533 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
536 if (first_writes_to_seconds_operands (a
, b
, true))
537 return _("Instructions write to the same destination register.");
539 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
540 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
542 /* Make sure that the instructions use the correct execution pipelines. */
543 if ( a_pipe
== PIPE_NONE
544 || b_pipe
== PIPE_NONE
)
545 return _("Instructions do not use parallel execution pipelines.");
547 /* Leave this test for last, since it is the only test that can
548 go away if the instructions are swapped, and we want to make
549 sure that any other errors are detected before this happens. */
550 if ( a_pipe
== PIPE_S
552 return _("Instructions share the same execution pipeline");
560 make_parallel (buffer
)
561 cgen_insn_t
* buffer
;
563 /* Force the top bit of the second insn to be set. */
567 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
569 value
= bfd_getb16 ((bfd_byte
*) buffer
);
571 bfd_putb16 (value
, (char *) buffer
);
575 value
= bfd_getl16 ((bfd_byte
*) buffer
);
577 bfd_putl16 (value
, (char *) buffer
);
584 make_parallel (buffer
)
587 /* Force the top bit of the second insn to be set. */
589 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
592 #endif /* ! CGEN_INT_INSN */
595 assemble_parallel_insn (str
, str2
)
604 * str2
= 0; /* Seperate the two instructions. */
606 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
607 so that the parallel instruction will start on a 32 bit boundary. */
611 /* Parse the first instruction. */
612 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
613 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
620 /* FIXME: Need standard macro to perform this test. */
621 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
623 as_bad (_("instruction '%s' is for the M32RX only"), str
);
627 /* Check to see if this is an allowable parallel insn. */
628 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
630 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
634 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
635 str3
= str
; /* Save the original string pointer. */
636 str
= str2
+ 2; /* Advanced past the parsed string. */
637 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
639 /* Preserve any fixups that have been generated and reset the list to empty. */
642 /* Get the indices of the operands of the instruction. */
643 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
644 doesn't seem right. Perhaps allow passing fields like we do insn. */
645 /* FIXME: ALIAS insns do not have operands, so we use this function
646 to find the equivalent insn and overwrite the value stored in our
647 structure. We still need the original insn, however, since this
648 may have certain attributes that are not present in the unaliased
649 version (eg relaxability). When aliases behave differently this
650 may have to change. */
651 first
.orig_insn
= first
.insn
;
652 first
.insn
= m32r_cgen_lookup_get_insn_operands (NULL
,
653 bfd_getb16 ((char *) first
.buffer
),
656 if (first
.insn
== NULL
)
657 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
659 /* Parse the second instruction. */
660 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
661 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
669 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
671 as_bad (_("instruction '%s' is for the M32RX only"), str
);
675 /* Check to see if this is an allowable parallel insn. */
676 if (CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
678 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
684 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
685 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
687 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
692 /* Get the indices of the operands of the instruction. */
693 second
.orig_insn
= second
.insn
;
694 second
.insn
= m32r_cgen_lookup_get_insn_operands (NULL
,
695 bfd_getb16 ((char *) second
.buffer
),
698 if (second
.insn
== NULL
)
699 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
701 /* We assume that if the first instruction writes to a register that is
702 read by the second instruction it is because the programmer intended
703 this to happen, (after all they have explicitly requested that these
704 two instructions be executed in parallel). Although if the global
705 variable warn_explicit_parallel_conflicts is true then we do generate
706 a warning message. Similarly we assume that parallel branch and jump
707 instructions are deliberate and should not produce errors. */
709 if (warn_explicit_parallel_conflicts
)
711 if (first_writes_to_seconds_operands (& first
, & second
, false))
712 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
714 if (first_writes_to_seconds_operands (& second
, & first
, false))
715 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
718 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
720 /* Get the fixups for the first instruction. */
724 (void) cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
725 CGEN_FIELDS_BITSIZE (& first
.fields
), 0);
727 /* Force the top bit of the second insn to be set. */
728 make_parallel (second
.buffer
);
730 /* Get its fixups. */
731 cgen_restore_fixups ();
734 (void) cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
735 CGEN_FIELDS_BITSIZE (& second
.fields
), 0);
737 /* Try swapping the instructions to see if they work that way. */
738 else if (can_make_parallel (& second
, & first
) == NULL
)
740 /* Write out the second instruction first. */
741 (void) cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
742 CGEN_FIELDS_BITSIZE (& second
.fields
), 0);
744 /* Force the top bit of the first instruction to be set. */
745 make_parallel (first
.buffer
);
747 /* Get the fixups for the first instruction. */
748 cgen_restore_fixups ();
750 /* Write out the first instruction. */
751 (void) cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
752 CGEN_FIELDS_BITSIZE (& first
.fields
), 0);
756 as_bad ("'%s': %s", str2
, errmsg
);
760 /* Set these so m32r_fill_insn can use them. */
762 prev_subseg
= now_subseg
;
765 /* end-sanitize-m32rx */
776 /* Initialize GAS's cgen interface for a new instruction. */
777 cgen_asm_init_parse ();
779 /* start-sanitize-m32rx */
780 /* Look for a parallel instruction seperator. */
781 if ((str2
= strstr (str
, "||")) != NULL
)
783 assemble_parallel_insn (str
, str2
);
786 /* end-sanitize-m32rx */
788 insn
.insn
= CGEN_SYM (assemble_insn
) (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
795 /* start-sanitize-m32rx */
796 if (! enable_m32rx
&& CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
798 as_bad (_("instruction '%s' is for the M32RX only"), str
);
801 /* end-sanitize-m32rx */
803 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
805 /* 32 bit insns must live on 32 bit boundaries. */
806 if (prev_insn
.insn
|| seen_relaxable_p
)
808 /* ??? If calling fill_insn too many times turns us into a memory
809 pig, can we call assemble_nop instead of !seen_relaxable_p? */
813 /* Doesn't really matter what we pass for RELAX_P here. */
814 (void) cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
815 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1);
819 /* start-sanitize-m32rx */
820 /* start-sanitize-phase2-m32rx */
822 /* end-sanitize-phase2-m32rx */
823 /* end-sanitize-m32rx */
825 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
830 /* Get the indices of the operands of the instruction.
831 FIXME: See assemble_parallel for notes on orig_insn. */
832 insn
.orig_insn
= insn
.insn
;
833 insn
.insn
= m32r_cgen_lookup_get_insn_operands (NULL
,
834 bfd_getb16 ((char *) insn
.buffer
),
837 if (insn
.insn
== NULL
)
838 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
841 insn
.orig_insn
= insn
.insn
;
843 /* Keep track of whether we've seen a pair of 16 bit insns.
844 prev_insn.insn is NULL when we're on a 32 bit boundary. */
847 /* start-sanitize-m32rx */
848 /* start-sanitize-phase2-m32rx */
849 /* Look to see if this instruction can be combined with the
850 previous instruction to make one, parallel, 32 bit instruction.
851 If the previous instruction (potentially) changed the flow of
852 program control, then it cannot be combined with the current
853 instruction. If the current instruction is relaxable, then it
854 might be replaced with a longer version, so we cannot combine it.
855 Also if the output of the previous instruction is used as an
856 input to the current instruction then it cannot be combined.
857 Otherwise call can_make_parallel() with both orderings of the
858 instructions to see if they can be combined. */
861 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
862 && ! writes_to_pc (& prev_insn
)
863 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
866 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
867 make_parallel (insn
.buffer
);
868 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
871 /* end-sanitize-phase2-m32rx */
872 /* end-sanitize-m32rx */
874 prev_insn
.insn
= NULL
;
881 /* Record the frag that might be used by this insn. */
882 insn
.frag
= frag_now
;
883 insn
.addr
= cgen_asm_finish_insn (insn
.orig_insn
, insn
.buffer
,
884 CGEN_FIELDS_BITSIZE (& insn
.fields
),
887 /* start-sanitize-m32rx */
888 /* start-sanitize-phase2-m32rx */
893 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
895 /* Swap the two insns */
896 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
897 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
899 make_parallel (insn
.addr
);
901 /* Swap any relaxable frags recorded for the two insns. */
902 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
903 prev_insn
.frag
->fr_opcode
= insn
.addr
;
904 else if (insn
.frag
->fr_opcode
== insn
.addr
)
905 insn
.frag
->fr_opcode
= prev_insn
.addr
;
907 /* end-sanitize-phase2-m32rx */
909 /* Record where this instruction was assembled. */
910 prev_insn
.addr
= insn
.addr
;
911 prev_insn
.frag
= insn
.frag
;
912 /* end-sanitize-m32rx */
914 /* If the insn needs the following one to be on a 32 bit boundary
915 (e.g. subroutine calls), fill this insn's slot. */
916 if (prev_insn
.insn
!= NULL
917 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
920 /* If this is a relaxable insn (can be replaced with a larger version)
921 mark the fact so that we can emit an alignment directive for a
922 following 32 bit insn if we see one. */
923 if (CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
924 seen_relaxable_p
= 1;
927 /* Set these so m32r_fill_insn can use them. */
929 prev_subseg
= now_subseg
;
932 /* The syntax in the manual says constants begin with '#'.
933 We just ignore it. */
936 md_operand (expressionP
)
937 expressionS
* expressionP
;
939 if (* input_line_pointer
== '#')
941 input_line_pointer
++;
942 expression (expressionP
);
947 md_section_align (segment
, size
)
951 int align
= bfd_get_section_alignment (stdoutput
, segment
);
952 return ((size
+ (1 << align
) - 1) & (-1 << align
));
956 md_undefined_symbol (name
)
962 /* .scomm pseudo-op handler.
964 This is a new pseudo-op to handle putting objects in .scommon.
965 By doing this the linker won't need to do any work and more importantly
966 it removes the implicit -G arg necessary to correctly link the object file.
973 register char * name
;
977 register symbolS
* symbolP
;
981 name
= input_line_pointer
;
982 c
= get_symbol_end ();
984 /* just after name is now '\0' */
985 p
= input_line_pointer
;
988 if (* input_line_pointer
!= ',')
990 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
991 ignore_rest_of_line ();
995 input_line_pointer
++; /* skip ',' */
996 if ((size
= get_absolute_expression ()) < 0)
998 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
999 ignore_rest_of_line ();
1003 /* The third argument to .scomm is the alignment. */
1004 if (* input_line_pointer
!= ',')
1008 ++ input_line_pointer
;
1009 align
= get_absolute_expression ();
1012 as_warn (_("ignoring bad alignment"));
1016 /* Convert to a power of 2 alignment. */
1019 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1023 as_bad (_("Common alignment not a power of 2"));
1024 ignore_rest_of_line ();
1032 symbolP
= symbol_find_or_make (name
);
1035 if (S_IS_DEFINED (symbolP
))
1037 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1038 S_GET_NAME (symbolP
));
1039 ignore_rest_of_line ();
1043 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1045 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1046 S_GET_NAME (symbolP
),
1047 (long) S_GET_VALUE (symbolP
),
1050 ignore_rest_of_line ();
1056 segT old_sec
= now_seg
;
1057 int old_subsec
= now_subseg
;
1060 record_alignment (sbss_section
, align2
);
1061 subseg_set (sbss_section
, 0);
1064 frag_align (align2
, 0, 0);
1066 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1067 symbolP
->sy_frag
->fr_symbol
= 0;
1069 symbolP
->sy_frag
= frag_now
;
1071 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1074 S_SET_SIZE (symbolP
, size
);
1075 S_SET_SEGMENT (symbolP
, sbss_section
);
1076 S_CLEAR_EXTERNAL (symbolP
);
1077 subseg_set (old_sec
, old_subsec
);
1081 S_SET_VALUE (symbolP
, (valueT
) size
);
1082 S_SET_ALIGN (symbolP
, align2
);
1083 S_SET_EXTERNAL (symbolP
);
1084 S_SET_SEGMENT (symbolP
, & scom_section
);
1087 demand_empty_rest_of_line ();
1090 /* Interface to relax_segment. */
1092 /* FIXME: Build table by hand, get it working, then machine generate. */
1094 const relax_typeS md_relax_table
[] =
1097 1) most positive reach of this state,
1098 2) most negative reach of this state,
1099 3) how many bytes this mode will add to the size of the current frag
1100 4) which index into the table to try if we can't fit into this one. */
1102 /* The first entry must be unused because an `rlx_more' value of zero ends
1106 /* The displacement used by GAS is from the end of the 2 byte insn,
1107 so we subtract 2 from the following. */
1108 /* 16 bit insn, 8 bit disp -> 10 bit range.
1109 This doesn't handle a branch in the right slot at the border:
1110 the "& -4" isn't taken into account. It's not important enough to
1111 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1113 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1114 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1115 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1116 /* Same thing, but with leading nop for alignment. */
1117 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1121 m32r_relax_frag (fragP
, stretch
)
1125 /* Address of branch insn. */
1126 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1129 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1130 if (fragP
->fr_subtype
== 2)
1132 if ((address
& 3) != 0)
1134 fragP
->fr_subtype
= 3;
1138 else if (fragP
->fr_subtype
== 3)
1140 if ((address
& 3) == 0)
1142 fragP
->fr_subtype
= 2;
1148 growth
= relax_frag (fragP
, stretch
);
1150 /* Long jump on odd halfword boundary? */
1151 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1153 fragP
->fr_subtype
= 3;
1161 /* Return an initial guess of the length by which a fragment must grow to
1162 hold a branch to reach its destination.
1163 Also updates fr_type/fr_subtype as necessary.
1165 Called just before doing relaxation.
1166 Any symbol that is now undefined will not become defined.
1167 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1168 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1169 Although it may not be explicit in the frag, pretend fr_var starts with a
1173 md_estimate_size_before_relax (fragP
, segment
)
1177 int old_fr_fix
= fragP
->fr_fix
;
1178 char * opcode
= fragP
->fr_opcode
;
1180 /* The only thing we have to handle here are symbols outside of the
1181 current segment. They may be undefined or in a different segment in
1182 which case linker scripts may place them anywhere.
1183 However, we can't finish the fragment here and emit the reloc as insn
1184 alignment requirements may move the insn about. */
1186 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1188 /* The symbol is undefined in this segment.
1189 Change the relaxation subtype to the max allowable and leave
1190 all further handling to md_convert_frag. */
1191 fragP
->fr_subtype
= 2;
1193 #if 0 /* Can't use this, but leave in for illustration. */
1194 /* Change 16 bit insn to 32 bit insn. */
1197 /* Increase known (fixed) size of fragment. */
1200 /* Create a relocation for it. */
1201 fix_new (fragP
, old_fr_fix
, 4,
1203 fragP
->fr_offset
, 1 /* pcrel */,
1204 /* FIXME: Can't use a real BFD reloc here.
1205 cgen_md_apply_fix3 can't handle it. */
1206 BFD_RELOC_M32R_26_PCREL
);
1208 /* Mark this fragment as finished. */
1212 const CGEN_INSN
* insn
;
1215 /* Update the recorded insn.
1216 Fortunately we don't have to look very far.
1217 FIXME: Change this to record in the instruction the next higher
1218 relaxable insn to use. */
1219 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1221 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1222 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1224 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1230 fragP
->fr_cgen
.insn
= insn
;
1236 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1239 /* *fragP has been relaxed to its final size, and now needs to have
1240 the bytes inside it modified to conform to the new size.
1242 Called after relaxation is finished.
1243 fragP->fr_type == rs_machine_dependent.
1244 fragP->fr_subtype is the subtype of what the address relaxed to. */
1247 md_convert_frag (abfd
, sec
, fragP
)
1253 char * displacement
;
1259 opcode
= fragP
->fr_opcode
;
1261 /* Address opcode resides at in file space. */
1262 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1264 switch (fragP
->fr_subtype
)
1268 displacement
= & opcode
[1];
1273 displacement
= & opcode
[1];
1276 opcode
[2] = opcode
[0] | 0x80;
1277 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1278 opcode_address
+= 2;
1280 displacement
= & opcode
[3];
1286 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1288 /* symbol must be resolved by linker */
1289 if (fragP
->fr_offset
& 3)
1290 as_warn (_("Addend to unresolved symbol not on word boundary."));
1291 addend
= fragP
->fr_offset
>> 2;
1295 /* Address we want to reach in file space. */
1296 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1297 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1298 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1301 /* Create a relocation for symbols that must be resolved by the linker.
1302 Otherwise output the completed insn. */
1304 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1306 assert (fragP
->fr_subtype
!= 1);
1307 assert (fragP
->fr_cgen
.insn
!= 0);
1308 cgen_record_fixup (fragP
,
1309 /* Offset of branch insn in frag. */
1310 fragP
->fr_fix
+ extension
- 4,
1311 fragP
->fr_cgen
.insn
,
1313 /* FIXME: quick hack */
1315 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1317 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1319 fragP
->fr_cgen
.opinfo
,
1320 fragP
->fr_symbol
, fragP
->fr_offset
);
1323 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1325 md_number_to_chars (displacement
, (valueT
) addend
,
1326 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1328 fragP
->fr_fix
+= extension
;
1331 /* Functions concerning relocs. */
1333 /* The location from which a PC relative jump should be calculated,
1334 given a PC relative reloc. */
1337 md_pcrel_from_section (fixP
, sec
)
1341 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1342 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1343 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1345 /* The symbol is undefined (or is defined but not in this section).
1346 Let the linker figure it out. */
1350 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1353 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1354 Returns BFD_RELOC_NONE if no reloc type can be found.
1355 *FIXP may be modified if desired. */
1357 bfd_reloc_code_real_type
1358 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1359 const CGEN_INSN
* insn
;
1360 const CGEN_OPERAND
* operand
;
1363 switch (CGEN_OPERAND_TYPE (operand
))
1365 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1366 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1367 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1368 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1369 case M32R_OPERAND_HI16
:
1370 case M32R_OPERAND_SLO16
:
1371 case M32R_OPERAND_ULO16
:
1372 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1373 if (fixP
->tc_fix_data
.opinfo
!= 0)
1374 return fixP
->tc_fix_data
.opinfo
;
1377 return BFD_RELOC_NONE
;
1380 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1383 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1388 struct m32r_hi_fixup
* hi_fixup
;
1390 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1391 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1393 hi_fixup
= ((struct m32r_hi_fixup
*)
1394 xmalloc (sizeof (struct m32r_hi_fixup
)));
1395 hi_fixup
->fixp
= fixP
;
1396 hi_fixup
->seg
= now_seg
;
1397 hi_fixup
->next
= m32r_hi_fixup_list
;
1399 m32r_hi_fixup_list
= hi_fixup
;
1402 /* Called while parsing an instruction to create a fixup.
1403 We need to check for HI16 relocs and queue them up for later sorting. */
1406 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1409 const CGEN_INSN
* insn
;
1411 const CGEN_OPERAND
* operand
;
1415 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1416 operand
, opinfo
, exp
);
1418 switch (CGEN_OPERAND_TYPE (operand
))
1420 case M32R_OPERAND_HI16
:
1421 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1422 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1423 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1424 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1431 /* Return BFD reloc type from opinfo field in a fixS.
1432 It's tricky using fx_r_type in m32r_frob_file because the values
1433 are BFD_RELOC_UNUSED + operand number. */
1434 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1436 /* Sort any unmatched HI16 relocs so that they immediately precede
1437 the corresponding LO16 reloc. This is called before md_apply_fix and
1443 struct m32r_hi_fixup
* l
;
1445 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1447 segment_info_type
* seginfo
;
1450 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1451 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1453 /* Check quickly whether the next fixup happens to be a matching low. */
1454 if (l
->fixp
->fx_next
!= NULL
1455 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1456 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1457 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1460 /* Look through the fixups for this segment for a matching `low'.
1461 When we find one, move the high/shigh just in front of it. We do
1462 this in two passes. In the first pass, we try to find a
1463 unique `low'. In the second pass, we permit multiple high's
1464 relocs for a single `low'. */
1465 seginfo
= seg_info (l
->seg
);
1466 for (pass
= 0; pass
< 2; pass
++)
1472 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1474 /* Check whether this is a `low' fixup which matches l->fixp. */
1475 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1476 && f
->fx_addsy
== l
->fixp
->fx_addsy
1477 && f
->fx_offset
== l
->fixp
->fx_offset
1480 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1481 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1482 || prev
->fx_addsy
!= f
->fx_addsy
1483 || prev
->fx_offset
!= f
->fx_offset
))
1487 /* Move l->fixp before f. */
1488 for (pf
= &seginfo
->fix_root
;
1490 pf
= & (* pf
)->fx_next
)
1491 assert (* pf
!= NULL
);
1493 * pf
= l
->fixp
->fx_next
;
1495 l
->fixp
->fx_next
= f
;
1497 seginfo
->fix_root
= l
->fixp
;
1499 prev
->fx_next
= l
->fixp
;
1511 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1512 _("Unmatched high/shigh reloc"));
1517 /* See whether we need to force a relocation into the output file.
1518 This is used to force out switch and PC relative relocations when
1522 m32r_force_relocation (fix
)
1528 return (fix
->fx_pcrel
1532 /* Write a value out to the object file, using the appropriate endianness. */
1535 md_number_to_chars (buf
, val
, n
)
1540 if (target_big_endian
)
1541 number_to_chars_bigendian (buf
, val
, n
);
1543 number_to_chars_littleendian (buf
, val
, n
);
1546 /* Turn a string in input_line_pointer into a floating point constant of type
1547 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1548 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1551 /* Equal to MAX_PRECISION in atof-ieee.c */
1552 #define MAX_LITTLENUMS 6
1555 md_atof (type
, litP
, sizeP
)
1562 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1563 LITTLENUM_TYPE
* wordP
;
1565 char * atof_ieee ();
1583 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1587 return _("Bad call to md_atof()");
1590 t
= atof_ieee (input_line_pointer
, type
, words
);
1592 input_line_pointer
= t
;
1593 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1595 if (target_big_endian
)
1597 for (i
= 0; i
< prec
; i
++)
1599 md_number_to_chars (litP
, (valueT
) words
[i
],
1600 sizeof (LITTLENUM_TYPE
));
1601 litP
+= sizeof (LITTLENUM_TYPE
);
1606 for (i
= prec
- 1; i
>= 0; i
--)
1608 md_number_to_chars (litP
, (valueT
) words
[i
],
1609 sizeof (LITTLENUM_TYPE
));
1610 litP
+= sizeof (LITTLENUM_TYPE
);
1618 m32r_elf_section_change_hook ()
1620 /* If we have reached the end of a section and we have just emitted a
1621 16 bit insn, then emit a nop to make sure that the section ends on
1622 a 32 bit boundary. */
1624 if (prev_insn
.insn
|| seen_relaxable_p
)
1625 (void) m32r_fill_insn (0);