1 /* tc-m32r.c -- Assembler for the Renesas M32R.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
27 #include "opcodes/m32r-desc.h"
28 #include "opcodes/m32r-opc.h"
32 /* Linked list of symbols that are debugging symbols to be defined as the
33 beginning of the current instruction. */
34 typedef struct sym_link
36 struct sym_link
*next
;
40 static sym_linkS
*debug_sym_link
= (sym_linkS
*) 0;
42 /* Structure to hold all of the different components describing
43 an individual instruction. */
46 const CGEN_INSN
*insn
;
47 const CGEN_INSN
*orig_insn
;
50 CGEN_INSN_INT buffer
[1];
51 #define INSN_VALUE(buf) (*(buf))
53 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
54 #define INSN_VALUE(buf) (buf)
59 fixS
*fixups
[GAS_CGEN_MAX_FIXUPS
];
60 int indices
[MAX_OPERAND_INSTANCES
];
61 sym_linkS
*debug_sym_link
;
65 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
66 boundary (i.e. was the first of two 16 bit insns). */
67 static m32r_insn prev_insn
;
69 /* Non-zero if we've seen a relaxable insn since the last 32 bit
71 static int seen_relaxable_p
= 0;
73 /* Non-zero if we are generating PIC code. */
76 /* Non-zero if -relax specified, in which case sufficient relocs are output
77 for the linker to do relaxing.
78 We do simple forms of relaxing internally, but they are always done.
79 This flag does not apply to them. */
80 static int m32r_relax
;
82 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
83 Each high/shigh reloc must be paired with it's low cousin in order to
84 properly calculate the addend in a relocatable link (since there is a
85 potential carry from the low to the high/shigh).
86 This option is off by default though for user-written assembler code it
87 might make sense to make the default be on (i.e. have gcc pass a flag
88 to turn it off). This warning must not be on for GCC created code as
89 optimization may delete the low but not the high/shigh (at least we
90 shouldn't assume or require it to). */
91 static int warn_unmatched_high
= 0;
93 /* 1 if -m32rx has been specified, in which case support for
94 the extended M32RX instruction set should be enabled.
95 2 if -m32r2 has been specified, in which case support for
96 the extended M32R2 instruction set should be enabled. */
97 static int enable_m32rx
= 0; /* Default to M32R. */
99 /* Non-zero if -m32rx -hidden has been specified, in which case support for
100 the special M32RX instruction set should be enabled. */
101 static int enable_special
= 0;
103 /* Non-zero if -bitinst has been specified, in which case support
104 for extended M32R bit-field instruction set should be enabled. */
105 static int enable_special_m32r
= 1;
107 /* Non-zero if -float has been specified, in which case support for
108 extended M32R floating point instruction set should be enabled. */
109 static int enable_special_float
= 0;
111 /* Non-zero if the programmer should be warned when an explicit parallel
112 instruction might have constraint violations. */
113 static int warn_explicit_parallel_conflicts
= 1;
115 /* Non-zero if the programmer should not receive any messages about
116 parallel instruction with potential or real constraint violations.
117 The ability to suppress these messages is intended only for hardware
118 vendors testing the chip. It superceedes
119 warn_explicit_parallel_conflicts. */
120 static int ignore_parallel_conflicts
= 0;
122 /* Non-zero if insns can be made parallel. */
123 static int use_parallel
= 1;
125 /* Non-zero if optimizations should be performed. */
129 static int m32r_flags
= 0;
131 /* Stuff for .scomm symbols. */
132 static segT sbss_section
;
133 static asection scom_section
;
134 static asymbol scom_symbol
;
136 const char comment_chars
[] = ";";
137 const char line_comment_chars
[] = "#";
138 const char line_separator_chars
[] = "!";
139 const char EXP_CHARS
[] = "eE";
140 const char FLT_CHARS
[] = "dD";
142 /* Relocations against symbols are done in two
143 parts, with a HI relocation and a LO relocation. Each relocation
144 has only 16 bits of space to store an addend. This means that in
145 order for the linker to handle carries correctly, it must be able
146 to locate both the HI and the LO relocation. This means that the
147 relocations must appear in order in the relocation table.
149 In order to implement this, we keep track of each unmatched HI
150 relocation. We then sort them so that they immediately precede the
151 corresponding LO relocation. */
156 struct m32r_hi_fixup
*next
;
161 /* The section this fixup is in. */
165 /* The list of unmatched HI relocs. */
167 static struct m32r_hi_fixup
*m32r_hi_fixup_list
;
170 enum bfd_architecture bfd_mach
;
174 { bfd_mach_m32r
, (1<<MACH_M32R
) },
175 { bfd_mach_m32rx
, (1<<MACH_M32RX
) },
176 { bfd_mach_m32r2
, (1<<MACH_M32R2
) }
179 static void allow_m32rx (int);
186 if (stdoutput
!= NULL
)
187 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_table
[on
].bfd_mach
);
189 if (gas_cgen_cpu_desc
!= NULL
)
190 gas_cgen_cpu_desc
->machs
= mach_table
[on
].mach_flags
;
193 #define M32R_SHORTOPTS "O::K:"
195 const char *md_shortopts
= M32R_SHORTOPTS
;
197 struct option md_longopts
[] =
199 #define OPTION_M32R (OPTION_MD_BASE)
200 #define OPTION_M32RX (OPTION_M32R + 1)
201 #define OPTION_M32R2 (OPTION_M32RX + 1)
202 #define OPTION_BIG (OPTION_M32R2 + 1)
203 #define OPTION_LITTLE (OPTION_BIG + 1)
204 #define OPTION_PARALLEL (OPTION_LITTLE + 1)
205 #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
206 #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
207 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
208 #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
209 #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1)
210 #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1)
211 #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
212 #define OPTION_NO_SPECIAL_M32R (OPTION_SPECIAL_M32R + 1)
213 #define OPTION_SPECIAL_FLOAT (OPTION_NO_SPECIAL_M32R + 1)
214 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
215 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
216 {"m32r", no_argument
, NULL
, OPTION_M32R
},
217 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
218 {"m32r2", no_argument
, NULL
, OPTION_M32R2
},
219 {"big", no_argument
, NULL
, OPTION_BIG
},
220 {"little", no_argument
, NULL
, OPTION_LITTLE
},
221 {"EB", no_argument
, NULL
, OPTION_BIG
},
222 {"EL", no_argument
, NULL
, OPTION_LITTLE
},
223 {"parallel", no_argument
, NULL
, OPTION_PARALLEL
},
224 {"no-parallel", no_argument
, NULL
, OPTION_NO_PARALLEL
},
225 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
226 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
227 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
228 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
229 {"ignore-parallel-conflicts", no_argument
, NULL
, OPTION_IGNORE_PARALLEL
},
230 {"Ip", no_argument
, NULL
, OPTION_IGNORE_PARALLEL
},
231 {"no-ignore-parallel-conflicts", no_argument
, NULL
, OPTION_NO_IGNORE_PARALLEL
},
232 {"nIp", no_argument
, NULL
, OPTION_NO_IGNORE_PARALLEL
},
233 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
234 {"bitinst", no_argument
, NULL
, OPTION_SPECIAL_M32R
},
235 {"no-bitinst", no_argument
, NULL
, OPTION_NO_SPECIAL_M32R
},
236 {"float", no_argument
, NULL
, OPTION_SPECIAL_FLOAT
},
237 /* Sigh. I guess all warnings must now have both variants. */
238 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
239 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
240 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
241 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
242 {NULL
, no_argument
, NULL
, 0}
245 size_t md_longopts_size
= sizeof (md_longopts
);
247 static void little (int);
248 static int parallel (void);
253 target_big_endian
= ! on
;
256 /* Use parallel execution. */
264 if (use_parallel
== 1)
271 md_parse_option (c
, arg
)
273 char *arg ATTRIBUTE_UNUSED
;
293 enable_special_m32r
= 1;
297 target_big_endian
= 1;
301 target_big_endian
= 0;
304 case OPTION_PARALLEL
:
308 case OPTION_NO_PARALLEL
:
312 case OPTION_WARN_PARALLEL
:
313 warn_explicit_parallel_conflicts
= 1;
316 case OPTION_NO_WARN_PARALLEL
:
317 warn_explicit_parallel_conflicts
= 0;
320 case OPTION_IGNORE_PARALLEL
:
321 ignore_parallel_conflicts
= 1;
324 case OPTION_NO_IGNORE_PARALLEL
:
325 ignore_parallel_conflicts
= 0;
333 /* Pretend that we do not recognise this option. */
334 as_bad (_("Unrecognised option: -hidden"));
339 case OPTION_SPECIAL_M32R
:
340 enable_special_m32r
= 1;
343 case OPTION_NO_SPECIAL_M32R
:
344 enable_special_m32r
= 0;
347 case OPTION_SPECIAL_FLOAT
:
348 enable_special_float
= 1;
351 case OPTION_WARN_UNMATCHED
:
352 warn_unmatched_high
= 1;
355 case OPTION_NO_WARN_UNMATCHED
:
356 warn_unmatched_high
= 0;
360 if (strcmp (arg
, "PIC") != 0)
361 as_warn (_("Unrecognized option following -K"));
374 md_show_usage (stream
)
377 fprintf (stream
, _(" M32R specific command line options:\n"));
379 fprintf (stream
, _("\
380 -m32r disable support for the m32rx instruction set\n"));
381 fprintf (stream
, _("\
382 -m32rx support the extended m32rx instruction set\n"));
383 fprintf (stream
, _("\
384 -m32r2 support the extended m32r2 instruction set\n"));
385 fprintf (stream
, _("\
386 -EL,-little produce little endian code and data\n"));
387 fprintf (stream
, _("\
388 -EB,-big produce big endian code and data\n"));
389 fprintf (stream
, _("\
390 -parallel try to combine instructions in parallel\n"));
391 fprintf (stream
, _("\
392 -no-parallel disable -parallel\n"));
393 fprintf (stream
, _("\
394 -no-bitinst disallow the M32R2's extended bit-field instructions\n"));
395 fprintf (stream
, _("\
396 -O try to optimize code. Implies -parallel\n"));
398 fprintf (stream
, _("\
399 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
400 fprintf (stream
, _("\
401 might violate contraints\n"));
402 fprintf (stream
, _("\
403 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
404 fprintf (stream
, _("\
405 instructions might violate contraints\n"));
406 fprintf (stream
, _("\
407 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
408 fprintf (stream
, _("\
409 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
410 fprintf (stream
, _("\
411 -ignore-parallel-conflicts do not check parallel instructions\n"));
412 fprintf (stream
, _("\
413 fo contraint violations\n"));
414 fprintf (stream
, _("\
415 -no-ignore-parallel-conflicts check parallel instructions for\n"));
416 fprintf (stream
, _("\
417 contraint violations\n"));
418 fprintf (stream
, _("\
419 -Ip synonym for -ignore-parallel-conflicts\n"));
420 fprintf (stream
, _("\
421 -nIp synonym for -no-ignore-parallel-conflicts\n"));
423 fprintf (stream
, _("\
424 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
425 fprintf (stream
, _("\
426 -no-warn-unmatched-high do not warn about missing low relocs\n"));
427 fprintf (stream
, _("\
428 -Wuh synonym for -warn-unmatched-high\n"));
429 fprintf (stream
, _("\
430 -Wnuh synonym for -no-warn-unmatched-high\n"));
432 fprintf (stream
, _("\
433 -KPIC generate PIC\n"));
436 static void fill_insn
PARAMS ((int));
437 static void m32r_scomm
PARAMS ((int));
438 static void debug_sym
PARAMS ((int));
439 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
441 /* Set by md_assemble for use by m32r_fill_insn. */
442 static subsegT prev_subseg
;
443 static segT prev_seg
;
445 /* The target specific pseudo-ops which we support. */
446 const pseudo_typeS md_pseudo_table
[] =
449 { "fillinsn", fill_insn
, 0 },
450 { "scomm", m32r_scomm
, 0 },
451 { "debugsym", debug_sym
, 0 },
452 { "m32r", allow_m32rx
, 0 },
453 { "m32rx", allow_m32rx
, 1 },
454 { "m32r2", allow_m32rx
, 2 },
455 { "little", little
, 1 },
456 { "big", little
, 0 },
460 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
461 symbolS
* GOT_symbol
;
464 m32r_PIC_related_p (symbolS
*sym
)
471 if (sym
== GOT_symbol
)
474 exp
= symbol_get_value_expression (sym
);
476 return (exp
->X_op
== O_PIC_reloc
477 || exp
->X_md
== BFD_RELOC_M32R_26_PLTREL
478 || m32r_PIC_related_p (exp
->X_add_symbol
)
479 || m32r_PIC_related_p (exp
->X_op_symbol
));
483 m32r_check_fixup (expressionS
*main_exp
, bfd_reloc_code_real_type
*r_type_p
)
485 expressionS
*exp
= main_exp
;
487 if (exp
->X_op
== O_add
&& m32r_PIC_related_p (exp
->X_op_symbol
))
490 if (exp
->X_op
== O_symbol
&& exp
->X_add_symbol
)
492 if (exp
->X_add_symbol
== GOT_symbol
)
494 *r_type_p
= BFD_RELOC_M32R_GOTPC24
;
498 else if (exp
->X_op
== O_add
)
500 exp
= symbol_get_value_expression (exp
->X_add_symbol
);
505 if (exp
->X_op
== O_PIC_reloc
|| exp
->X_md
!= BFD_RELOC_UNUSED
)
507 *r_type_p
= exp
->X_md
;
509 exp
->X_op
= O_symbol
;
512 main_exp
->X_add_symbol
= exp
->X_add_symbol
;
513 main_exp
->X_add_number
+= exp
->X_add_number
;
517 return (m32r_PIC_related_p (exp
->X_add_symbol
)
518 || m32r_PIC_related_p (exp
->X_op_symbol
));
523 /* FIXME: Should be machine generated. */
524 #define NOP_INSN 0x7000
525 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
527 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
528 of an rs_align_code fragment. */
531 m32r_handle_align (fragp
)
534 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
535 static const unsigned char multi_nop_pattern
[] = { 0x70, 0x00, 0xf0, 0x00 };
540 if (fragp
->fr_type
!= rs_align_code
)
543 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
544 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
556 memcpy (p
, nop_pattern
, 2);
562 memcpy (p
, multi_nop_pattern
, 4);
564 fragp
->fr_fix
+= fix
;
568 /* If the last instruction was the first of 2 16 bit insns,
569 output a nop to move the PC to a 32 bit boundary.
571 This is done via an alignment specification since branch relaxing
572 may make it unnecessary.
574 Internally, we need to output one of these each time a 32 bit insn is
575 seen after an insn that is relaxable. */
579 int ignore ATTRIBUTE_UNUSED
;
581 frag_align_code (2, 0);
582 prev_insn
.insn
= NULL
;
583 seen_relaxable_p
= 0;
586 /* Record the symbol so that when we output the insn, we can create
587 a symbol that is at the start of the instruction. This is used
588 to emit the label for the start of a breakpoint without causing
589 the assembler to emit a NOP if the previous instruction was a
590 16 bit instruction. */
594 int ignore ATTRIBUTE_UNUSED
;
598 register char *end_name
;
599 register symbolS
*symbolP
;
600 register sym_linkS
*link
;
602 name
= input_line_pointer
;
603 delim
= get_symbol_end ();
604 end_name
= input_line_pointer
;
606 if ((symbolP
= symbol_find (name
)) == NULL
607 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
609 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
612 symbol_table_insert (symbolP
);
613 if (S_IS_DEFINED (symbolP
) && (S_GET_SEGMENT (symbolP
) != reg_section
614 || S_IS_EXTERNAL (symbolP
)
615 || S_IS_WEAK (symbolP
)))
616 /* xgettext:c-format */
617 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
621 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
622 link
->symbol
= symbolP
;
623 link
->next
= debug_sym_link
;
624 debug_sym_link
= link
;
625 symbol_get_obj (symbolP
)->local
= 1;
629 demand_empty_rest_of_line ();
632 /* Second pass to expanding the debug symbols, go through linked
633 list of symbols and reassign the address. */
636 expand_debug_syms (syms
, align
)
640 char *save_input_line
= input_line_pointer
;
641 sym_linkS
*next_syms
;
646 (void) frag_align_code (align
, 0);
647 for (; syms
!= (sym_linkS
*) 0; syms
= next_syms
)
649 symbolS
*symbolP
= syms
->symbol
;
650 next_syms
= syms
->next
;
651 input_line_pointer
= ".\n";
652 pseudo_set (symbolP
);
653 free ((char *) syms
);
656 input_line_pointer
= save_input_line
;
660 m32r_flush_pending_output()
664 expand_debug_syms (debug_sym_link
, 1);
665 debug_sym_link
= (sym_linkS
*) 0;
669 /* Cover function to fill_insn called after a label and at end of assembly.
670 The result is always 1: we're called in a conditional to see if the
671 current line is a label. */
674 m32r_fill_insn (done
)
677 if (prev_seg
!= NULL
)
680 subsegT subseg
= now_subseg
;
682 subseg_set (prev_seg
, prev_subseg
);
686 subseg_set (seg
, subseg
);
689 if (done
&& debug_sym_link
)
691 expand_debug_syms (debug_sym_link
, 1);
692 debug_sym_link
= (sym_linkS
*) 0;
698 /* The default target format to use. */
701 m32r_target_format ()
704 if (target_big_endian
)
705 return "elf32-m32r-linux";
707 return "elf32-m32rle-linux";
709 if (target_big_endian
)
712 return "elf32-m32rle";
723 /* Initialize the `cgen' interface. */
725 /* Set the machine number and endian. */
726 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
727 CGEN_CPU_OPEN_ENDIAN
,
729 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
),
731 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
733 /* The operand instance table is used during optimization to determine
734 which insns can be executed in parallel. It is also used to give
735 warnings regarding operand interference in parallel insns. */
736 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
738 /* This is a callback from cgen to gas to parse operands. */
739 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
741 /* Save the current subseg so we can restore it [it's the default one and
742 we don't want the initial section to be .sbss]. */
746 /* The sbss section is for local .scomm symbols. */
747 sbss_section
= subseg_new (".sbss", 0);
749 /* This is copied from perform_an_assembly_pass. */
750 applicable
= bfd_applicable_section_flags (stdoutput
);
751 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
753 subseg_set (seg
, subseg
);
755 /* We must construct a fake section similar to bfd_com_section
756 but with the name .scommon. */
757 scom_section
= bfd_com_section
;
758 scom_section
.name
= ".scommon";
759 scom_section
.output_section
= &scom_section
;
760 scom_section
.symbol
= &scom_symbol
;
761 scom_section
.symbol_ptr_ptr
= &scom_section
.symbol
;
762 scom_symbol
= *bfd_com_section
.symbol
;
763 scom_symbol
.name
= ".scommon";
764 scom_symbol
.section
= &scom_section
;
766 allow_m32rx (enable_m32rx
);
768 gas_cgen_initialize_saved_fixups_array ();
771 #define OPERAND_IS_COND_BIT(operand, indices, index) \
772 ((operand)->hw_type == HW_H_COND \
773 || ((operand)->hw_type == HW_H_PSW) \
774 || ((operand)->hw_type == HW_H_CR \
775 && (indices [index] == 0 || indices [index] == 1)))
777 /* Returns true if an output of instruction 'a' is referenced by an operand
778 of instruction 'b'. If 'check_outputs' is true then b's outputs are
779 checked, otherwise its inputs are examined. */
781 static int first_writes_to_seconds_operands
782 PARAMS ((m32r_insn
*, m32r_insn
*, const int));
785 first_writes_to_seconds_operands (a
, b
, check_outputs
)
788 const int check_outputs
;
790 const CGEN_OPINST
*a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
791 const CGEN_OPINST
*b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
794 if (ignore_parallel_conflicts
)
797 /* If at least one of the instructions takes no operands, then there is
798 nothing to check. There really are instructions without operands,
800 if (a_operands
== NULL
|| b_ops
== NULL
)
803 /* Scan the operand list of 'a' looking for an output operand. */
805 a_operands
->type
!= CGEN_OPINST_END
;
806 a_index
++, a_operands
++)
808 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
811 const CGEN_OPINST
*b_operands
= b_ops
;
814 The Condition bit 'C' is a shadow of the CBR register (control
815 register 1) and also a shadow of bit 31 of the program status
816 word (control register 0). For now this is handled here, rather
819 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
821 /* Scan operand list of 'b' looking for another reference to the
822 condition bit, which goes in the right direction. */
824 b_operands
->type
!= CGEN_OPINST_END
;
825 b_index
++, b_operands
++)
827 if ((b_operands
->type
830 : CGEN_OPINST_INPUT
))
831 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
837 /* Scan operand list of 'b' looking for an operand that
838 references the same hardware element, and which goes in the
841 b_operands
->type
!= CGEN_OPINST_END
;
842 b_index
++, b_operands
++)
844 if ((b_operands
->type
847 : CGEN_OPINST_INPUT
))
848 && (b_operands
->hw_type
== a_operands
->hw_type
)
849 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
859 /* Returns true if the insn can (potentially) alter the program counter. */
861 static int writes_to_pc
PARAMS ((m32r_insn
*));
867 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
868 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
873 /* Return NULL if the two 16 bit insns can be executed in parallel.
874 Otherwise return a pointer to an error message explaining why not. */
876 static const char *can_make_parallel
PARAMS ((m32r_insn
*, m32r_insn
*));
879 can_make_parallel (a
, b
)
886 /* Make sure the instructions are the right length. */
887 if (CGEN_FIELDS_BITSIZE (&a
->fields
) != 16
888 || CGEN_FIELDS_BITSIZE (&b
->fields
) != 16)
891 if (first_writes_to_seconds_operands (a
, b
, TRUE
))
892 return _("instructions write to the same destination register.");
894 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
895 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
897 /* Make sure that the instructions use the correct execution pipelines. */
898 if (a_pipe
== PIPE_NONE
899 || b_pipe
== PIPE_NONE
)
900 return _("Instructions do not use parallel execution pipelines.");
902 /* Leave this test for last, since it is the only test that can
903 go away if the instructions are swapped, and we want to make
904 sure that any other errors are detected before this happens. */
907 || (b_pipe
== PIPE_O_OS
&& (enable_m32rx
!= 2)))
908 return _("Instructions share the same execution pipeline");
913 /* Force the top bit of the second 16-bit insn to be set. */
915 static void make_parallel
PARAMS ((CGEN_INSN_BYTES_PTR
));
918 make_parallel (buffer
)
919 CGEN_INSN_BYTES_PTR buffer
;
924 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
929 /* Same as make_parallel except buffer contains the bytes in target order. */
931 static void target_make_parallel
PARAMS ((char *));
934 target_make_parallel (buffer
)
937 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
941 /* Assemble two instructions with an explicit parallel operation (||) or
942 sequential operation (->). */
944 static void assemble_two_insns
PARAMS ((char *, char *, int));
947 assemble_two_insns (str
, str2
, parallel_p
)
956 char save_str2
= *str2
;
958 /* Separate the two instructions. */
961 /* Make sure the two insns begin on a 32 bit boundary.
962 This is also done for the serial case (foo -> bar), relaxing doesn't
963 affect insns written like this.
964 Note that we must always do this as we can't assume anything about
965 whether we're currently on a 32 bit boundary or not. Relaxing may
969 first
.debug_sym_link
= debug_sym_link
;
970 debug_sym_link
= (sym_linkS
*) 0;
972 /* Parse the first instruction. */
973 if (! (first
.insn
= m32r_cgen_assemble_insn
974 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
981 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
983 /* xgettext:c-format */
984 as_bad (_("not a 16 bit instruction '%s'"), str
);
988 else if ((enable_m32rx
== 1)
989 /* FIXME: Need standard macro to perform this test. */
990 && ((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
992 && !((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
993 & (1 << MACH_M32RX
)))))
995 /* xgettext:c-format */
996 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
999 else if ((! enable_special
1000 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
1001 || (! enable_special_m32r
1002 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1004 else if (! enable_special
1005 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
1008 /* xgettext:c-format */
1009 as_bad (_("unknown instruction '%s'"), str
);
1012 else if (! enable_m32rx
1013 /* FIXME: Need standard macro to perform this test. */
1014 && (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1015 == (1 << MACH_M32RX
)))
1017 /* xgettext:c-format */
1018 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1022 /* Check to see if this is an allowable parallel insn. */
1024 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
1026 /* xgettext:c-format */
1027 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
1031 /* Restore the original assembly text, just in case it is needed. */
1034 /* Save the original string pointer. */
1037 /* Advanced past the parsed string. */
1040 /* Remember the entire string in case it is needed for error
1044 /* Convert the opcode to lower case. */
1048 while (ISSPACE (*s2
++))
1053 while (ISALNUM (*s2
))
1055 *s2
= TOLOWER (*s2
);
1060 /* Preserve any fixups that have been generated and reset the list
1062 gas_cgen_save_fixups (0);
1064 /* Get the indices of the operands of the instruction. */
1065 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
1066 doesn't seem right. Perhaps allow passing fields like we do insn. */
1067 /* FIXME: ALIAS insns do not have operands, so we use this function
1068 to find the equivalent insn and overwrite the value stored in our
1069 structure. We still need the original insn, however, since this
1070 may have certain attributes that are not present in the unaliased
1071 version (eg relaxability). When aliases behave differently this
1072 may have to change. */
1073 first
.orig_insn
= first
.insn
;
1075 CGEN_FIELDS tmp_fields
;
1076 first
.insn
= cgen_lookup_get_insn_operands
1077 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
1078 first
.indices
, &tmp_fields
);
1081 if (first
.insn
== NULL
)
1082 as_fatal (_("internal error: lookup/get operands failed"));
1084 second
.debug_sym_link
= NULL
;
1086 /* Parse the second instruction. */
1087 if (! (second
.insn
= m32r_cgen_assemble_insn
1088 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
1095 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
1097 /* xgettext:c-format */
1098 as_bad (_("not a 16 bit instruction '%s'"), str
);
1102 else if ((enable_m32rx
== 1)
1103 /* FIXME: Need standard macro to perform this test. */
1104 && ((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1105 & (1 << MACH_M32R2
))
1106 && !((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1107 & (1 << MACH_M32RX
)))))
1109 /* xgettext:c-format */
1110 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1113 else if ((! enable_special
1114 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1115 || (! enable_special_m32r
1116 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1118 else if (! enable_special
1119 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1122 /* xgettext:c-format */
1123 as_bad (_("unknown instruction '%s'"), str
);
1126 else if (! enable_m32rx
1127 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1129 /* xgettext:c-format */
1130 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1134 /* Check to see if this is an allowable parallel insn. */
1136 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
1138 /* xgettext:c-format */
1139 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
1143 if (parallel_p
&& ! enable_m32rx
)
1145 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
1146 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
1148 /* xgettext:c-format */
1149 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
1154 /* Get the indices of the operands of the instruction. */
1155 second
.orig_insn
= second
.insn
;
1157 CGEN_FIELDS tmp_fields
;
1158 second
.insn
= cgen_lookup_get_insn_operands
1159 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
1160 second
.indices
, &tmp_fields
);
1163 if (second
.insn
== NULL
)
1164 as_fatal (_("internal error: lookup/get operands failed"));
1166 /* We assume that if the first instruction writes to a register that is
1167 read by the second instruction it is because the programmer intended
1168 this to happen, (after all they have explicitly requested that these
1169 two instructions be executed in parallel). Although if the global
1170 variable warn_explicit_parallel_conflicts is true then we do generate
1171 a warning message. Similarly we assume that parallel branch and jump
1172 instructions are deliberate and should not produce errors. */
1174 if (parallel_p
&& warn_explicit_parallel_conflicts
)
1176 if (first_writes_to_seconds_operands (&first
, &second
, FALSE
))
1177 /* xgettext:c-format */
1178 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
1180 if (first_writes_to_seconds_operands (&second
, &first
, FALSE
))
1181 /* xgettext:c-format */
1182 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
1186 || (errmsg
= (char *) can_make_parallel (&first
, &second
)) == NULL
)
1188 /* Get the fixups for the first instruction. */
1189 gas_cgen_swap_fixups (0);
1192 expand_debug_syms (first
.debug_sym_link
, 1);
1193 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
1194 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
1196 /* Force the top bit of the second insn to be set. */
1198 make_parallel (second
.buffer
);
1200 /* Get its fixups. */
1201 gas_cgen_restore_fixups (0);
1204 expand_debug_syms (second
.debug_sym_link
, 1);
1205 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
1206 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
1208 /* Try swapping the instructions to see if they work that way. */
1209 else if (can_make_parallel (&second
, &first
) == NULL
)
1211 /* Write out the second instruction first. */
1212 expand_debug_syms (second
.debug_sym_link
, 1);
1213 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
1214 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
1216 /* Force the top bit of the first instruction to be set. */
1217 make_parallel (first
.buffer
);
1219 /* Get the fixups for the first instruction. */
1220 gas_cgen_restore_fixups (0);
1222 /* Write out the first instruction. */
1223 expand_debug_syms (first
.debug_sym_link
, 1);
1224 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
1225 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
1229 as_bad ("'%s': %s", str2
, errmsg
);
1233 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
)
1234 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1235 m32r_flags
|= E_M32R_HAS_HIDDEN_INST
;
1236 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_M32R
)
1237 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_M32R
))
1238 m32r_flags
|= E_M32R_HAS_BIT_INST
;
1239 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_FLOAT
)
1240 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_FLOAT
))
1241 m32r_flags
|= E_M32R_HAS_FLOAT_INST
;
1243 /* Set these so m32r_fill_insn can use them. */
1245 prev_subseg
= now_subseg
;
1256 /* Initialize GAS's cgen interface for a new instruction. */
1257 gas_cgen_init_parse ();
1259 /* Look for a parallel instruction separator. */
1260 if ((str2
= strstr (str
, "||")) != NULL
)
1262 assemble_two_insns (str
, str2
, 1);
1263 m32r_flags
|= E_M32R_HAS_PARALLEL
;
1267 /* Also look for a sequential instruction separator. */
1268 if ((str2
= strstr (str
, "->")) != NULL
)
1270 assemble_two_insns (str
, str2
, 0);
1274 insn
.debug_sym_link
= debug_sym_link
;
1275 debug_sym_link
= (sym_linkS
*) 0;
1277 insn
.insn
= m32r_cgen_assemble_insn
1278 (gas_cgen_cpu_desc
, str
, &insn
.fields
, insn
.buffer
, & errmsg
);
1287 if ((enable_m32rx
== 1)
1288 /* FIXME: Need standard macro to perform this test. */
1289 && ((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
)
1290 & (1 << MACH_M32R2
))
1291 && !((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
)
1292 & (1 << MACH_M32RX
)))))
1294 /* xgettext:c-format */
1295 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1298 else if ((! enable_special
1299 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1300 || (! enable_special_m32r
1301 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1303 if (! enable_special
1304 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1307 /* xgettext:c-format */
1308 as_bad (_("unknown instruction '%s'"), str
);
1311 else if (! enable_m32rx
1312 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1314 /* xgettext:c-format */
1315 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1319 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1320 m32r_flags
|= E_M32R_HAS_HIDDEN_INST
;
1321 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_M32R
))
1322 m32r_flags
|= E_M32R_HAS_BIT_INST
;
1323 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_FLOAT
))
1324 m32r_flags
|= E_M32R_HAS_FLOAT_INST
;
1326 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1328 /* 32 bit insns must live on 32 bit boundaries. */
1329 if (prev_insn
.insn
|| seen_relaxable_p
)
1331 /* ??? If calling fill_insn too many times turns us into a memory
1332 pig, can we call a fn to assemble a nop instead of
1333 !seen_relaxable_p? */
1337 expand_debug_syms (insn
.debug_sym_link
, 2);
1339 /* Doesn't really matter what we pass for RELAX_P here. */
1340 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1341 CGEN_FIELDS_BITSIZE (&insn
.fields
), 1, NULL
);
1345 int on_32bit_boundary_p
;
1348 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1351 insn
.orig_insn
= insn
.insn
;
1353 /* If the previous insn was relaxable, then it may be expanded
1354 to fill the current 16 bit slot. Emit a NOP here to occupy
1355 this slot, so that we can start at optimizing at a 32 bit
1357 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1362 /* Get the indices of the operands of the instruction.
1363 FIXME: See assemble_parallel for notes on orig_insn. */
1365 CGEN_FIELDS tmp_fields
;
1366 insn
.insn
= cgen_lookup_get_insn_operands
1367 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1368 16, insn
.indices
, &tmp_fields
);
1371 if (insn
.insn
== NULL
)
1372 as_fatal (_("internal error: lookup/get operands failed"));
1375 /* Compute whether we're on a 32 bit boundary or not.
1376 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1377 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1379 /* Change a frag to, if each insn to swap is in a different frag.
1380 It must keep only one instruction in a frag. */
1381 if (parallel() && on_32bit_boundary_p
)
1383 frag_wane (frag_now
);
1387 /* Look to see if this instruction can be combined with the
1388 previous instruction to make one, parallel, 32 bit instruction.
1389 If the previous instruction (potentially) changed the flow of
1390 program control, then it cannot be combined with the current
1391 instruction. If the current instruction is relaxable, then it
1392 might be replaced with a longer version, so we cannot combine it.
1393 Also if the output of the previous instruction is used as an
1394 input to the current instruction then it cannot be combined.
1395 Otherwise call can_make_parallel() with both orderings of the
1396 instructions to see if they can be combined. */
1397 if (! on_32bit_boundary_p
1399 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1400 && ! writes_to_pc (&prev_insn
)
1401 && ! first_writes_to_seconds_operands (&prev_insn
, &insn
, FALSE
))
1403 if (can_make_parallel (&prev_insn
, &insn
) == NULL
)
1404 make_parallel (insn
.buffer
);
1405 else if (can_make_parallel (&insn
, &prev_insn
) == NULL
)
1409 expand_debug_syms (insn
.debug_sym_link
, 1);
1415 /* Ensure each pair of 16 bit insns is in the same frag. */
1418 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1419 CGEN_FIELDS_BITSIZE (&insn
.fields
),
1420 1 /* relax_p */, &fi
);
1421 insn
.addr
= fi
.addr
;
1422 insn
.frag
= fi
.frag
;
1423 insn
.num_fixups
= fi
.num_fixups
;
1424 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1425 insn
.fixups
[i
] = fi
.fixups
[i
];
1432 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1434 /* Swap the two insns */
1435 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1436 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1438 target_make_parallel (insn
.addr
);
1440 /* Swap any relaxable frags recorded for the two insns. */
1441 /* FIXME: Clarify. relaxation precludes parallel insns */
1442 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1443 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1444 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1445 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1447 /* Change a frag to, if each insn is in a different frag.
1448 It must keep only one instruction in a frag. */
1449 if (prev_insn
.frag
!= insn
.frag
)
1451 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1452 prev_insn
.fixups
[i
]->fx_frag
= insn
.frag
;
1453 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1454 insn
.fixups
[i
]->fx_frag
= prev_insn
.frag
;
1458 /* Update the addresses in any fixups.
1459 Note that we don't have to handle the case where each insn is in
1460 a different frag as we ensure they're in the same frag above. */
1461 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1462 prev_insn
.fixups
[i
]->fx_where
+= 2;
1463 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1464 insn
.fixups
[i
]->fx_where
-= 2;
1468 /* Keep track of whether we've seen a pair of 16 bit insns.
1469 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1470 if (on_32bit_boundary_p
)
1473 prev_insn
.insn
= NULL
;
1475 /* If the insn needs the following one to be on a 32 bit boundary
1476 (e.g. subroutine calls), fill this insn's slot. */
1477 if (on_32bit_boundary_p
1478 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1481 /* If this is a relaxable insn (can be replaced with a larger version)
1482 mark the fact so that we can emit an alignment directive for a
1483 following 32 bit insn if we see one. */
1484 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1485 seen_relaxable_p
= 1;
1488 /* Set these so m32r_fill_insn can use them. */
1490 prev_subseg
= now_subseg
;
1493 /* The syntax in the manual says constants begin with '#'.
1494 We just ignore it. */
1497 md_operand (expressionP
)
1498 expressionS
*expressionP
;
1500 if (*input_line_pointer
== '#')
1502 input_line_pointer
++;
1503 expression (expressionP
);
1508 md_section_align (segment
, size
)
1512 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1513 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1517 md_undefined_symbol (name
)
1518 char *name ATTRIBUTE_UNUSED
;
1523 /* .scomm pseudo-op handler.
1525 This is a new pseudo-op to handle putting objects in .scommon.
1526 By doing this the linker won't need to do any work,
1527 and more importantly it removes the implicit -G arg necessary to
1528 correctly link the object file. */
1532 int ignore ATTRIBUTE_UNUSED
;
1534 register char *name
;
1538 register symbolS
*symbolP
;
1542 name
= input_line_pointer
;
1543 c
= get_symbol_end ();
1545 /* Just after name is now '\0'. */
1546 p
= input_line_pointer
;
1549 if (*input_line_pointer
!= ',')
1551 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1552 ignore_rest_of_line ();
1557 input_line_pointer
++;
1558 if ((size
= get_absolute_expression ()) < 0)
1560 /* xgettext:c-format */
1561 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1562 ignore_rest_of_line ();
1566 /* The third argument to .scomm is the alignment. */
1567 if (*input_line_pointer
!= ',')
1571 ++input_line_pointer
;
1572 align
= get_absolute_expression ();
1575 as_warn (_("ignoring bad alignment"));
1580 /* Convert to a power of 2 alignment. */
1583 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
)
1587 as_bad (_("Common alignment not a power of 2"));
1588 ignore_rest_of_line ();
1596 symbolP
= symbol_find_or_make (name
);
1599 if (S_IS_DEFINED (symbolP
))
1601 /* xgettext:c-format */
1602 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1603 S_GET_NAME (symbolP
));
1604 ignore_rest_of_line ();
1608 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1610 /* xgettext:c-format */
1611 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1612 S_GET_NAME (symbolP
),
1613 (long) S_GET_VALUE (symbolP
),
1616 ignore_rest_of_line ();
1620 if (symbol_get_obj (symbolP
)->local
)
1622 segT old_sec
= now_seg
;
1623 int old_subsec
= now_subseg
;
1626 record_alignment (sbss_section
, align2
);
1627 subseg_set (sbss_section
, 0);
1630 frag_align (align2
, 0, 0);
1632 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1633 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1635 symbol_set_frag (symbolP
, frag_now
);
1637 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1640 S_SET_SIZE (symbolP
, size
);
1641 S_SET_SEGMENT (symbolP
, sbss_section
);
1642 S_CLEAR_EXTERNAL (symbolP
);
1643 subseg_set (old_sec
, old_subsec
);
1647 S_SET_VALUE (symbolP
, (valueT
) size
);
1648 S_SET_ALIGN (symbolP
, align2
);
1649 S_SET_EXTERNAL (symbolP
);
1650 S_SET_SEGMENT (symbolP
, &scom_section
);
1653 demand_empty_rest_of_line ();
1656 /* Interface to relax_segment. */
1658 /* FIXME: Build table by hand, get it working, then machine generate. */
1660 const relax_typeS md_relax_table
[] =
1663 1) most positive reach of this state,
1664 2) most negative reach of this state,
1665 3) how many bytes this mode will add to the size of the current frag
1666 4) which index into the table to try if we can't fit into this one. */
1668 /* The first entry must be unused because an `rlx_more' value of zero ends
1672 /* The displacement used by GAS is from the end of the 2 byte insn,
1673 so we subtract 2 from the following. */
1674 /* 16 bit insn, 8 bit disp -> 10 bit range.
1675 This doesn't handle a branch in the right slot at the border:
1676 the "& -4" isn't taken into account. It's not important enough to
1677 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1679 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1680 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1681 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1682 /* Same thing, but with leading nop for alignment. */
1683 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1687 m32r_relax_frag (segment
, fragP
, stretch
)
1692 /* Address of branch insn. */
1693 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1696 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1697 if (fragP
->fr_subtype
== 2)
1699 if ((address
& 3) != 0)
1701 fragP
->fr_subtype
= 3;
1705 else if (fragP
->fr_subtype
== 3)
1707 if ((address
& 3) == 0)
1709 fragP
->fr_subtype
= 2;
1715 growth
= relax_frag (segment
, fragP
, stretch
);
1717 /* Long jump on odd halfword boundary? */
1718 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1720 fragP
->fr_subtype
= 3;
1728 /* Return an initial guess of the length by which a fragment must grow to
1729 hold a branch to reach its destination.
1730 Also updates fr_type/fr_subtype as necessary.
1732 Called just before doing relaxation.
1733 Any symbol that is now undefined will not become defined.
1734 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1735 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1736 Although it may not be explicit in the frag, pretend fr_var starts
1740 md_estimate_size_before_relax (fragP
, segment
)
1744 /* The only thing we have to handle here are symbols outside of the
1745 current segment. They may be undefined or in a different segment in
1746 which case linker scripts may place them anywhere.
1747 However, we can't finish the fragment here and emit the reloc as insn
1748 alignment requirements may move the insn about. */
1750 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
1751 || S_IS_EXTERNAL (fragP
->fr_symbol
)
1752 || S_IS_WEAK (fragP
->fr_symbol
))
1754 /* The symbol is undefined in this segment.
1755 Change the relaxation subtype to the max allowable and leave
1756 all further handling to md_convert_frag. */
1757 fragP
->fr_subtype
= 2;
1760 const CGEN_INSN
*insn
;
1763 /* Update the recorded insn.
1764 Fortunately we don't have to look very far.
1765 FIXME: Change this to record in the instruction the next higher
1766 relaxable insn to use. */
1767 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1769 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1770 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1772 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAXED
))
1778 fragP
->fr_cgen
.insn
= insn
;
1783 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
1786 /* *FRAGP has been relaxed to its final size, and now needs to have
1787 the bytes inside it modified to conform to the new size.
1789 Called after relaxation is finished.
1790 fragP->fr_type == rs_machine_dependent.
1791 fragP->fr_subtype is the subtype of what the address relaxed to. */
1794 md_convert_frag (abfd
, sec
, fragP
)
1795 bfd
*abfd ATTRIBUTE_UNUSED
;
1806 opcode
= fragP
->fr_opcode
;
1808 /* Address opcode resides at in file space. */
1809 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1811 switch (fragP
->fr_subtype
)
1815 displacement
= &opcode
[1];
1820 displacement
= &opcode
[1];
1823 opcode
[2] = opcode
[0] | 0x80;
1824 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1825 opcode_address
+= 2;
1827 displacement
= &opcode
[3];
1833 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
1834 || S_IS_EXTERNAL (fragP
->fr_symbol
)
1835 || S_IS_WEAK (fragP
->fr_symbol
))
1837 /* Symbol must be resolved by linker. */
1838 if (fragP
->fr_offset
& 3)
1839 as_warn (_("Addend to unresolved symbol not on word boundary."));
1840 #ifdef USE_M32R_OLD_RELOC
1841 addend
= fragP
->fr_offset
>> 2; /* Old M32R used USE_REL. */
1848 /* Address we want to reach in file space. */
1849 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1850 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1853 /* Create a relocation for symbols that must be resolved by the linker.
1854 Otherwise output the completed insn. */
1856 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
1857 || S_IS_EXTERNAL (fragP
->fr_symbol
)
1858 || S_IS_WEAK (fragP
->fr_symbol
))
1862 assert (fragP
->fr_subtype
!= 1);
1863 assert (fragP
->fr_cgen
.insn
!= 0);
1865 fixP
= gas_cgen_record_fixup (fragP
,
1866 /* Offset of branch insn in frag. */
1867 fragP
->fr_fix
+ extension
- 4,
1868 fragP
->fr_cgen
.insn
,
1870 /* FIXME: quick hack. */
1871 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1872 M32R_OPERAND_DISP24
),
1873 fragP
->fr_cgen
.opinfo
,
1874 fragP
->fr_symbol
, fragP
->fr_offset
);
1875 if (fragP
->fr_cgen
.opinfo
)
1876 fixP
->fx_r_type
= fragP
->fr_cgen
.opinfo
;
1879 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1881 md_number_to_chars (displacement
, (valueT
) addend
,
1882 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1884 fragP
->fr_fix
+= extension
;
1887 /* Functions concerning relocs. */
1889 /* The location from which a PC relative jump should be calculated,
1890 given a PC relative reloc. */
1893 md_pcrel_from_section (fixP
, sec
)
1897 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1898 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1899 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
1900 || S_IS_EXTERNAL (fixP
->fx_addsy
)
1901 || S_IS_WEAK (fixP
->fx_addsy
)))
1903 if (S_GET_SEGMENT (fixP
->fx_addsy
) != sec
1904 && S_IS_DEFINED (fixP
->fx_addsy
)
1905 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
1906 && ! S_IS_WEAK (fixP
->fx_addsy
))
1907 return fixP
->fx_offset
;
1909 /* The symbol is undefined (or is defined but not in this section).
1910 Let the linker figure it out. */
1914 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1917 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1918 Returns BFD_RELOC_NONE if no reloc type can be found.
1919 *FIXP may be modified if desired. */
1921 bfd_reloc_code_real_type
1922 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1923 const CGEN_INSN
*insn ATTRIBUTE_UNUSED
;
1924 const CGEN_OPERAND
*operand
;
1927 switch (operand
->type
)
1929 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1930 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1931 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1932 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1933 case M32R_OPERAND_HI16
:
1934 case M32R_OPERAND_SLO16
:
1935 case M32R_OPERAND_ULO16
:
1936 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1937 if (fixP
->fx_cgen
.opinfo
!= 0)
1938 return fixP
->fx_cgen
.opinfo
;
1941 /* Avoid -Wall warning. */
1944 return BFD_RELOC_NONE
;
1947 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1949 static void m32r_record_hi16
PARAMS ((int, fixS
*, segT
));
1952 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1955 segT seg ATTRIBUTE_UNUSED
;
1957 struct m32r_hi_fixup
*hi_fixup
;
1959 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1960 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1962 hi_fixup
= ((struct m32r_hi_fixup
*)
1963 xmalloc (sizeof (struct m32r_hi_fixup
)));
1964 hi_fixup
->fixp
= fixP
;
1965 hi_fixup
->seg
= now_seg
;
1966 hi_fixup
->next
= m32r_hi_fixup_list
;
1968 m32r_hi_fixup_list
= hi_fixup
;
1971 /* Called while parsing an instruction to create a fixup.
1972 We need to check for HI16 relocs and queue them up for later sorting. */
1975 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1978 const CGEN_INSN
*insn
;
1980 const CGEN_OPERAND
*operand
;
1985 bfd_reloc_code_real_type r_type
= BFD_RELOC_UNUSED
;
1987 if (m32r_check_fixup (exp
, &r_type
))
1988 as_bad (_("Invalid PIC expression."));
1990 fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1991 operand
, opinfo
, exp
);
1993 switch (operand
->type
)
1995 case M32R_OPERAND_HI16
:
1996 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1997 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1998 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1999 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
2003 /* Avoid -Wall warning. */
2009 case BFD_RELOC_UNUSED
:
2013 case BFD_RELOC_M32R_GOTPC24
:
2014 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
)
2015 r_type
= BFD_RELOC_M32R_GOTPC_HI_SLO
;
2016 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2017 r_type
= BFD_RELOC_M32R_GOTPC_HI_ULO
;
2018 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_LO16
)
2019 r_type
= BFD_RELOC_M32R_GOTPC_LO
;
2021 case BFD_RELOC_M32R_GOT24
:
2022 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
)
2023 r_type
= BFD_RELOC_M32R_GOT16_HI_SLO
;
2024 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2025 r_type
= BFD_RELOC_M32R_GOT16_HI_ULO
;
2026 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_LO16
)
2027 r_type
= BFD_RELOC_M32R_GOT16_LO
;
2029 case BFD_RELOC_M32R_GOTOFF
:
2030 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
)
2031 r_type
= BFD_RELOC_M32R_GOTOFF_HI_SLO
;
2032 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2033 r_type
= BFD_RELOC_M32R_GOTOFF_HI_ULO
;
2034 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_LO16
)
2035 r_type
= BFD_RELOC_M32R_GOTOFF_LO
;
2037 case BFD_RELOC_M32R_26_PLTREL
:
2038 as_bad (_("Invalid PIC expression."));
2042 fixP
->fx_r_type
= r_type
;
2047 /* Return BFD reloc type from opinfo field in a fixS.
2048 It's tricky using fx_r_type in m32r_frob_file because the values
2049 are BFD_RELOC_UNUSED + operand number. */
2050 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
2052 /* Sort any unmatched HI16 relocs so that they immediately precede
2053 the corresponding LO16 reloc. This is called before md_apply_fix3 and
2059 struct m32r_hi_fixup
*l
;
2061 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
2063 segment_info_type
*seginfo
;
2066 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
2067 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
2069 /* Check quickly whether the next fixup happens to be a matching low. */
2070 if (l
->fixp
->fx_next
!= NULL
2071 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
2072 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
2073 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
2076 /* Look through the fixups for this segment for a matching `low'.
2077 When we find one, move the high/shigh just in front of it. We do
2078 this in two passes. In the first pass, we try to find a
2079 unique `low'. In the second pass, we permit multiple high's
2080 relocs for a single `low'. */
2081 seginfo
= seg_info (l
->seg
);
2082 for (pass
= 0; pass
< 2; pass
++)
2088 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
2090 /* Check whether this is a `low' fixup which matches l->fixp. */
2091 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
2092 && f
->fx_addsy
== l
->fixp
->fx_addsy
2093 && f
->fx_offset
== l
->fixp
->fx_offset
2096 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
2097 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
2098 || prev
->fx_addsy
!= f
->fx_addsy
2099 || prev
->fx_offset
!= f
->fx_offset
))
2103 /* Move l->fixp before f. */
2104 for (pf
= &seginfo
->fix_root
;
2106 pf
= & (*pf
)->fx_next
)
2107 assert (*pf
!= NULL
);
2109 *pf
= l
->fixp
->fx_next
;
2111 l
->fixp
->fx_next
= f
;
2113 seginfo
->fix_root
= l
->fixp
;
2115 prev
->fx_next
= l
->fixp
;
2127 && warn_unmatched_high
)
2128 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
2129 _("Unmatched high/shigh reloc"));
2134 /* See whether we need to force a relocation into the output file.
2135 This is used to force out switch and PC relative relocations when
2139 m32r_force_relocation (fix
)
2142 if (generic_force_reloc (fix
))
2148 return fix
->fx_pcrel
;
2151 /* Write a value out to the object file, using the appropriate endianness. */
2154 md_number_to_chars (buf
, val
, n
)
2159 if (target_big_endian
)
2160 number_to_chars_bigendian (buf
, val
, n
);
2162 number_to_chars_littleendian (buf
, val
, n
);
2165 /* Turn a string in input_line_pointer into a floating point constant
2166 of type TYPE, and store the appropriate bytes in *LITP. The number
2167 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2168 returned, or NULL on OK. */
2170 /* Equal to MAX_PRECISION in atof-ieee.c. */
2171 #define MAX_LITTLENUMS 6
2174 md_atof (type
, litP
, sizeP
)
2181 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2200 /* FIXME: Some targets allow other format chars for bigger sizes
2205 return _("Bad call to md_atof()");
2208 t
= atof_ieee (input_line_pointer
, type
, words
);
2210 input_line_pointer
= t
;
2211 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2213 if (target_big_endian
)
2215 for (i
= 0; i
< prec
; i
++)
2217 md_number_to_chars (litP
, (valueT
) words
[i
],
2218 sizeof (LITTLENUM_TYPE
));
2219 litP
+= sizeof (LITTLENUM_TYPE
);
2224 for (i
= prec
- 1; i
>= 0; i
--)
2226 md_number_to_chars (litP
, (valueT
) words
[i
],
2227 sizeof (LITTLENUM_TYPE
));
2228 litP
+= sizeof (LITTLENUM_TYPE
);
2236 m32r_elf_section_change_hook ()
2238 /* If we have reached the end of a section and we have just emitted a
2239 16 bit insn, then emit a nop to make sure that the section ends on
2240 a 32 bit boundary. */
2242 if (prev_insn
.insn
|| seen_relaxable_p
)
2243 (void) m32r_fill_insn (0);
2246 /* Return true if can adjust the reloc to be relative to its section
2247 (such as .data) instead of relative to some symbol. */
2250 m32r_fix_adjustable (fixP
)
2253 bfd_reloc_code_real_type reloc_type
;
2255 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
2257 const CGEN_INSN
*insn
= NULL
;
2258 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
2259 const CGEN_OPERAND
*operand
=
2260 cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
2261 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
2264 reloc_type
= fixP
->fx_r_type
;
2266 if (fixP
->fx_addsy
== NULL
)
2269 /* Prevent all adjustments to global symbols. */
2270 if (S_IS_EXTERN (fixP
->fx_addsy
))
2272 if (S_IS_WEAK (fixP
->fx_addsy
))
2276 && (reloc_type
== BFD_RELOC_M32R_24
2277 || reloc_type
== BFD_RELOC_M32R_26_PCREL
2278 || reloc_type
== BFD_RELOC_M32R_HI16_SLO
2279 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
2280 || reloc_type
== BFD_RELOC_M32R_LO16
))
2283 if (reloc_type
== BFD_RELOC_M32R_GOT24
2284 || reloc_type
== BFD_RELOC_M32R_26_PLTREL
2285 || reloc_type
== BFD_RELOC_M32R_GOTPC_HI_SLO
2286 || reloc_type
== BFD_RELOC_M32R_GOTPC_HI_ULO
2287 || reloc_type
== BFD_RELOC_M32R_GOTPC_LO
2288 || reloc_type
== BFD_RELOC_M32R_GOT16_HI_SLO
2289 || reloc_type
== BFD_RELOC_M32R_GOT16_HI_ULO
2290 || reloc_type
== BFD_RELOC_M32R_GOT16_LO
)
2293 /* We need the symbol name for the VTABLE entries. */
2294 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
2295 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)
2302 m32r_elf_final_processing (void)
2305 m32r_flags
|= E_M32R_HAS_PARALLEL
;
2306 elf_elfheader (stdoutput
)->e_flags
|= m32r_flags
;
2309 /* Translate internal representation of relocation info to BFD target
2313 tc_gen_reloc (section
, fixP
)
2318 bfd_reloc_code_real_type code
;
2320 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2322 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2323 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2324 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2326 code
= fixP
->fx_r_type
;
2330 printf("%s",bfd_get_reloc_code_name(code
));
2334 case BFD_RELOC_M32R_26_PCREL
:
2335 code
= BFD_RELOC_M32R_26_PLTREL
;
2337 case BFD_RELOC_M32R_24
:
2338 if (fixP
->fx_addsy
!= NULL
2339 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2340 code
= BFD_RELOC_M32R_GOTPC24
;
2342 code
= BFD_RELOC_M32R_GOT24
;
2344 case BFD_RELOC_M32R_HI16_ULO
:
2345 if (fixP
->fx_addsy
!= NULL
2346 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2347 code
= BFD_RELOC_M32R_GOTPC_HI_ULO
;
2349 code
= BFD_RELOC_M32R_GOT16_HI_ULO
;
2351 case BFD_RELOC_M32R_HI16_SLO
:
2352 if (fixP
->fx_addsy
!= NULL
2353 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2354 code
= BFD_RELOC_M32R_GOTPC_HI_SLO
;
2356 code
= BFD_RELOC_M32R_GOT16_HI_SLO
;
2358 case BFD_RELOC_M32R_LO16
:
2359 if (fixP
->fx_addsy
!= NULL
2360 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2361 code
= BFD_RELOC_M32R_GOTPC_LO
;
2363 code
= BFD_RELOC_M32R_GOT16_LO
;
2369 printf(" => %s",bfd_get_reloc_code_name(code
));
2373 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2375 printf(" => %s\n",reloc
->howto
->name
);
2377 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
2379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2380 _("internal error: can't export reloc type %d (`%s')"),
2381 fixP
->fx_r_type
, bfd_get_reloc_code_name (code
));
2385 /* Use fx_offset for these cases. */
2386 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
2387 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
)
2388 reloc
->addend
= fixP
->fx_offset
;
2390 && code
!= BFD_RELOC_M32R_26_PLTREL
)
2392 && fixP
->fx_addsy
!= NULL
2393 && (S_GET_SEGMENT(fixP
->fx_addsy
) != section
)
2394 && S_IS_DEFINED (fixP
->fx_addsy
)
2395 && ! S_IS_EXTERNAL(fixP
->fx_addsy
)
2396 && ! S_IS_WEAK(fixP
->fx_addsy
))
2397 /* Already used fx_offset in the opcode field itseld. */
2398 reloc
->addend
= fixP
->fx_offset
;
2400 reloc
->addend
= fixP
->fx_addnumber
;
2405 inline static char *
2406 m32r_end_of_match (char *cont
, char *what
)
2408 int len
= strlen (what
);
2410 if (strncasecmp (cont
, what
, strlen (what
)) == 0
2411 && ! is_part_of_name (cont
[len
]))
2418 m32r_parse_name (char const *name
, expressionS
*exprP
, char *nextcharP
)
2420 char *next
= input_line_pointer
;
2426 exprP
->X_op_symbol
= NULL
;
2427 exprP
->X_md
= BFD_RELOC_UNUSED
;
2429 if (strcmp (name
, GOT_NAME
) == 0)
2432 GOT_symbol
= symbol_find_or_make (name
);
2434 exprP
->X_add_symbol
= GOT_symbol
;
2436 /* If we have an absolute symbol or a
2437 reg, then we know its value now. */
2438 segment
= S_GET_SEGMENT (exprP
->X_add_symbol
);
2439 if (segment
== absolute_section
)
2441 exprP
->X_op
= O_constant
;
2442 exprP
->X_add_number
= S_GET_VALUE (exprP
->X_add_symbol
);
2443 exprP
->X_add_symbol
= NULL
;
2445 else if (segment
== reg_section
)
2447 exprP
->X_op
= O_register
;
2448 exprP
->X_add_number
= S_GET_VALUE (exprP
->X_add_symbol
);
2449 exprP
->X_add_symbol
= NULL
;
2453 exprP
->X_op
= O_symbol
;
2454 exprP
->X_add_number
= 0;
2460 exprP
->X_add_symbol
= symbol_find_or_make (name
);
2462 if (*nextcharP
!= '@')
2464 else if ((next_end
= m32r_end_of_match (next
+ 1, "GOTOFF")))
2466 reloc_type
= BFD_RELOC_M32R_GOTOFF
;
2467 op_type
= O_PIC_reloc
;
2469 else if ((next_end
= m32r_end_of_match (next
+ 1, "GOT")))
2471 reloc_type
= BFD_RELOC_M32R_GOT24
;
2472 op_type
= O_PIC_reloc
;
2474 else if ((next_end
= m32r_end_of_match (next
+ 1, "PLT")))
2476 reloc_type
= BFD_RELOC_M32R_26_PLTREL
;
2477 op_type
= O_PIC_reloc
;
2482 *input_line_pointer
= *nextcharP
;
2483 input_line_pointer
= next_end
;
2484 *nextcharP
= *input_line_pointer
;
2485 *input_line_pointer
= '\0';
2487 exprP
->X_op
= op_type
;
2488 exprP
->X_add_number
= 0;
2489 exprP
->X_md
= reloc_type
;
2495 m32r_cgen_parse_fix_exp(int opinfo
, expressionS
*exp
)
2497 if (exp
->X_op
== O_PIC_reloc
2498 && exp
->X_md
== BFD_RELOC_M32R_26_PLTREL
)
2500 exp
->X_op
= O_symbol
;