1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
29 const char comment_chars
[] = ";!";
30 const char line_comment_chars
[] = "#*";
31 const char line_separator_chars
[] = "";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
36 #define STATE_CONDITIONAL_BRANCH (1)
37 #define STATE_PC_RELATIVE (2)
38 #define STATE_INDEXED_OFFSET (3)
39 #define STATE_XBCC_BRANCH (4)
40 #define STATE_CONDITIONAL_BRANCH_6812 (5)
42 #define STATE_BYTE (0)
43 #define STATE_BITS5 (0)
44 #define STATE_WORD (1)
45 #define STATE_BITS9 (1)
46 #define STATE_LONG (2)
47 #define STATE_BITS16 (2)
48 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
50 /* This macro has no side-effects. */
51 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
52 #define RELAX_STATE(s) ((s) >> 2)
53 #define RELAX_LENGTH(s) ((s) & 3)
55 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
57 /* This table describes how you change sizes for the various types of variable
58 size expressions. This version only supports two kinds. */
61 How far Forward this mode will reach.
62 How far Backward this mode will reach.
63 How many bytes this mode will add to the size of the frag.
64 Which mode to go to if the offset won't fit in this one. */
66 relax_typeS md_relax_table
[] = {
67 {1, 1, 0, 0}, /* First entries aren't used. */
68 {1, 1, 0, 0}, /* For no good reason except. */
69 {1, 1, 0, 0}, /* that the VAX doesn't either. */
73 These insns are translated into b!cc +3 jmp L. */
74 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
79 /* Relax for bsr <L> and bra <L>.
80 These insns are translated into jsr and jmp. */
81 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
86 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
87 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
88 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
92 /* Relax for dbeq/ibeq/tbeq r,<L>:
93 These insns are translated into db!cc +3 jmp L. */
94 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
99 /* Relax for bcc <L> on 68HC12.
100 These insns are translated into lbcc <L>. */
101 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
108 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
109 typedef enum register_id
{
121 typedef struct operand
{
128 struct m68hc11_opcode_def
{
134 struct m68hc11_opcode
*opcode
;
137 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
138 static int m68hc11_nb_opcode_defs
= 0;
140 typedef struct alias
{
145 static alias alias_opcodes
[] = {
152 /* Local functions. */
153 static register_id reg_name_search
PARAMS ((char *));
154 static register_id register_name
PARAMS ((void));
155 static int cmp_opcode
PARAMS ((struct m68hc11_opcode
*,
156 struct m68hc11_opcode
*));
157 static char *print_opcode_format
PARAMS ((struct m68hc11_opcode
*, int));
158 static char *skip_whites
PARAMS ((char *));
159 static int check_range
PARAMS ((long, int));
160 static void print_opcode_list
PARAMS ((void));
161 static void get_default_target
PARAMS ((void));
162 static void print_insn_format
PARAMS ((char *));
163 static int get_operand
PARAMS ((operand
*, int, long));
164 static void fixup8
PARAMS ((expressionS
*, int, int));
165 static void fixup16
PARAMS ((expressionS
*, int, int));
166 static unsigned char convert_branch
PARAMS ((unsigned char));
167 static char *m68hc11_new_insn
PARAMS ((int));
168 static void build_dbranch_insn
PARAMS ((struct m68hc11_opcode
*,
169 operand
*, int, int));
170 static int build_indexed_byte
PARAMS ((operand
*, int, int));
171 static int build_reg_mode
PARAMS ((operand
*, int));
173 static struct m68hc11_opcode
*find
174 PARAMS ((struct m68hc11_opcode_def
*, operand
*, int));
175 static struct m68hc11_opcode
*find_opcode
176 PARAMS ((struct m68hc11_opcode_def
*, operand
*, int *));
177 static void build_jump_insn
178 PARAMS ((struct m68hc11_opcode
*, operand
*, int, int));
179 static void build_insn
180 PARAMS ((struct m68hc11_opcode
*, operand
*, int));
181 static int relaxable_symbol
PARAMS ((symbolS
*));
183 /* Controls whether relative branches can be turned into long branches.
184 When the relative offset is too large, the insn are changed:
192 Setting the flag forbidds this. */
193 static short flag_fixed_branchs
= 0;
195 /* Force to use long jumps (absolute) instead of relative branches. */
196 static short flag_force_long_jumps
= 0;
198 /* Change the direct addressing mode into an absolute addressing mode
199 when the insn does not support direct addressing.
200 For example, "clr *ZD0" is normally not possible and is changed
202 static short flag_strict_direct_addressing
= 1;
204 /* When an opcode has invalid operand, print out the syntax of the opcode
206 static short flag_print_insn_syntax
= 0;
208 /* Dumps the list of instructions with syntax and then exit:
209 1 -> Only dumps the list (sorted by name)
210 2 -> Generate an example (or test) that can be compiled. */
211 static short flag_print_opcodes
= 0;
213 /* Opcode hash table. */
214 static struct hash_control
*m68hc11_hash
;
216 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
217 by 'get_default_target' by looking at default BFD vector. This is overriden
218 with the -m<cpu> option. */
219 static int current_architecture
= 0;
221 /* Default cpu determined by 'get_default_target'. */
222 static const char *default_cpu
;
224 /* Number of opcodes in the sorted table (filtered by current cpu). */
225 static int num_opcodes
;
227 /* The opcodes sorted by name and filtered by current cpu. */
228 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
230 /* These are the machine dependent pseudo-ops. These are included so
231 the assembler can work on the output from the SUN C compiler, which
234 /* This table describes all the machine specific pseudo-ops the assembler
235 has to support. The fields are:
236 pseudo-op name without dot
237 function to call to execute this pseudo-op
238 Integer arg to pass to the function. */
239 const pseudo_typeS md_pseudo_table
[] = {
240 /* The following pseudo-ops are supported for MRI compatibility. */
243 {"fcc", stringer
, 1},
246 /* Dwarf2 support for Gcc. */
247 {"file", dwarf2_directive_file
, 0},
248 {"loc", dwarf2_directive_loc
, 0},
251 {"xrefb", s_ignore
, 0}, /* Same as xref */
256 /* Options and initialization. */
258 CONST
char *md_shortopts
= "Sm:";
260 struct option md_longopts
[] = {
261 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
262 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
264 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
265 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHS
},
267 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
268 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
270 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
271 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
273 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
274 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
276 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
277 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
279 {NULL
, no_argument
, NULL
, 0}
281 size_t md_longopts_size
= sizeof (md_longopts
);
283 /* Get the target cpu for the assembler. This is based on the configure
284 options and on the -m68hc11/-m68hc12 option. If no option is specified,
285 we must get the default. */
287 m68hc11_arch_format ()
289 get_default_target ();
290 if (current_architecture
& cpu6811
)
291 return "elf32-m68hc11";
293 return "elf32-m68hc12";
296 enum bfd_architecture
299 get_default_target ();
300 if (current_architecture
& cpu6811
)
301 return bfd_arch_m68hc11
;
303 return bfd_arch_m68hc12
;
312 /* Listing header selected according to cpu. */
314 m68hc11_listing_header ()
316 if (current_architecture
& cpu6811
)
317 return "M68HC11 GAS ";
319 return "M68HC12 GAS ";
323 md_show_usage (stream
)
326 get_default_target ();
327 fprintf (stream
, _("\
328 Motorola 68HC11/68HC12 options:\n\
329 -m68hc11 | -m68hc12 specify the processor [default %s]\n\
330 --force-long-branchs always turn relative branchs into absolute ones\n\
331 -S,--short-branchs do not turn relative branchs into absolute ones\n\
332 when the offset is out of range\n\
333 --strict-direct-mode do not turn the direct mode into extended mode\n\
334 when the instruction does not support direct mode\n\
335 --print-insn-syntax print the syntax of instruction in case of error\n\
336 --print-opcodes print the list of instructions with syntax\n\
337 --generate-example generate an example of each instruction\n\
338 (used for testing)\n"), default_cpu
);
342 /* Try to identify the default target based on the BFD library. */
344 get_default_target ()
346 const bfd_target
*target
;
349 if (current_architecture
!= 0)
352 default_cpu
= "unknown";
353 target
= bfd_find_target (0, &abfd
);
354 if (target
&& target
->name
)
356 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
358 current_architecture
= cpu6812
;
359 default_cpu
= "m68hc12";
361 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
363 current_architecture
= cpu6811
;
364 default_cpu
= "m68hc11";
368 as_bad (_("Default target `%s' is not supported."), target
->name
);
374 m68hc11_print_statistics (file
)
378 struct m68hc11_opcode_def
*opc
;
380 hash_print_statistics (file
, "opcode table", m68hc11_hash
);
382 opc
= m68hc11_opcode_defs
;
383 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
386 /* Dump the opcode statistics table. */
387 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
388 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
390 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
393 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
398 md_parse_option (c
, arg
)
402 get_default_target ();
405 /* -S means keep external to 2 bit offset rather than 16 bit one. */
406 case OPTION_SHORT_BRANCHS
:
408 flag_fixed_branchs
= 1;
411 case OPTION_FORCE_LONG_BRANCH
:
412 flag_force_long_jumps
= 1;
415 case OPTION_PRINT_INSN_SYNTAX
:
416 flag_print_insn_syntax
= 1;
419 case OPTION_PRINT_OPCODES
:
420 flag_print_opcodes
= 1;
423 case OPTION_STRICT_DIRECT_MODE
:
424 flag_strict_direct_addressing
= 0;
427 case OPTION_GENERATE_EXAMPLE
:
428 flag_print_opcodes
= 2;
432 if (strcasecmp (arg
, "68hc11") == 0)
433 current_architecture
= cpu6811
;
434 else if (strcasecmp (arg
, "68hc12") == 0)
435 current_architecture
= cpu6812
;
437 as_bad (_("Option `%s' is not recognized."), arg
);
448 md_undefined_symbol (name
)
449 char *name ATTRIBUTE_UNUSED
;
454 /* Equal to MAX_PRECISION in atof-ieee.c. */
455 #define MAX_LITTLENUMS 6
457 /* Turn a string in input_line_pointer into a floating point constant
458 of type TYPE, and store the appropriate bytes in *LITP. The number
459 of LITTLENUMS emitted is stored in *SIZEP. An error message is
460 returned, or NULL on OK. */
462 md_atof (type
, litP
, sizeP
)
468 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
469 LITTLENUM_TYPE
*wordP
;
500 return _("Bad call to MD_ATOF()");
502 t
= atof_ieee (input_line_pointer
, type
, words
);
504 input_line_pointer
= t
;
506 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
507 for (wordP
= words
; prec
--;)
509 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
510 litP
+= sizeof (LITTLENUM_TYPE
);
516 md_section_align (seg
, addr
)
520 int align
= bfd_get_section_alignment (stdoutput
, seg
);
521 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
525 cmp_opcode (op1
, op2
)
526 struct m68hc11_opcode
*op1
;
527 struct m68hc11_opcode
*op2
;
529 return strcmp (op1
->name
, op2
->name
);
532 /* Initialize the assembler. Create the opcode hash table
533 (sorted on the names) with the M6811 opcode table
534 (from opcode library). */
538 char *prev_name
= "";
539 struct m68hc11_opcode
*opcodes
;
540 struct m68hc11_opcode_def
*opc
= 0;
543 get_default_target ();
545 m68hc11_hash
= hash_new ();
547 /* Get a writable copy of the opcode table and sort it on the names. */
548 opcodes
= (struct m68hc11_opcode
*) xmalloc (m68hc11_num_opcodes
*
551 m68hc11_sorted_opcodes
= opcodes
;
553 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
555 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
557 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
558 if (opcodes
[num_opcodes
].name
[0] == 'b'
559 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
560 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
563 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
566 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
567 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
569 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
570 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
576 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
), cmp_opcode
);
578 opc
= (struct m68hc11_opcode_def
*)
579 xmalloc (num_opcodes
* sizeof (struct m68hc11_opcode_def
));
580 m68hc11_opcode_defs
= opc
--;
582 /* Insert unique names into hash table. The M6811 instruction set
583 has several identical opcode names that have different opcodes based
584 on the operands. This hash table then provides a quick index to
585 the first opcode with a particular name in the opcode table. */
586 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
590 if (strcmp (prev_name
, opcodes
->name
))
592 prev_name
= (char *) opcodes
->name
;
596 opc
->min_operands
= 100;
597 opc
->max_operands
= 0;
599 opc
->opcode
= opcodes
;
601 hash_insert (m68hc11_hash
, opcodes
->name
, (char *) opc
);
604 opc
->format
|= opcodes
->format
;
606 /* See how many operands this opcode needs. */
608 if (opcodes
->format
& M6811_OP_MASK
)
610 if (opcodes
->format
& M6811_OP_BITMASK
)
612 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
614 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
617 if (expect
< opc
->min_operands
)
618 opc
->min_operands
= expect
;
619 if (expect
> opc
->max_operands
)
620 opc
->max_operands
= expect
;
623 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
625 if (flag_print_opcodes
)
627 print_opcode_list ();
633 m68hc11_init_after_args ()
639 /* Return a string that represents the operand format for the instruction.
640 When example is true, this generates an example of operand. This is used
641 to give an example and also to generate a test. */
643 print_opcode_format (opcode
, example
)
644 struct m68hc11_opcode
*opcode
;
647 static char buf
[128];
648 int format
= opcode
->format
;
653 if (format
& M6811_OP_IMM8
)
656 sprintf (p
, "#%d", rand () & 0x0FF);
658 strcpy (p
, _("#<imm8>"));
662 if (format
& M6811_OP_IMM16
)
665 sprintf (p
, "#%d", rand () & 0x0FFFF);
667 strcpy (p
, _("#<imm16>"));
671 if (format
& M6811_OP_IX
)
674 sprintf (p
, "%d,X", rand () & 0x0FF);
676 strcpy (p
, _("<imm8>,X"));
680 if (format
& M6811_OP_IY
)
683 sprintf (p
, "%d,X", rand () & 0x0FF);
685 strcpy (p
, _("<imm8>,X"));
689 if (format
& M6812_OP_IDX
)
692 sprintf (p
, "%d,X", rand () & 0x0FF);
698 if (format
& M6811_OP_DIRECT
)
701 sprintf (p
, "*Z%d", rand () & 0x0FF);
703 strcpy (p
, _("*<abs8>"));
707 if (format
& M6811_OP_BITMASK
)
713 sprintf (p
, "#$%02x", rand () & 0x0FF);
715 strcpy (p
, _("#<mask>"));
718 if (format
& M6811_OP_JUMP_REL
)
722 if (format
& M6811_OP_IND16
)
725 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
727 strcpy (p
, _("<abs>"));
732 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
736 if (format
& M6811_OP_BITMASK
)
738 sprintf (p
, ".+%d", rand () & 0x7F);
742 sprintf (p
, "L%d", rand () & 0x0FF);
746 strcpy (p
, _("<label>"));
752 /* Prints the list of instructions with the possible operands. */
757 char *prev_name
= "";
758 struct m68hc11_opcode
*opcodes
;
759 int example
= flag_print_opcodes
== 2;
762 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
765 opcodes
= m68hc11_sorted_opcodes
;
767 /* Walk the list sorted on names (by md_begin). We only report
768 one instruction per line, and we collect the different operand
770 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
772 char *fmt
= print_opcode_format (opcodes
, example
);
776 printf ("L%d:\t", i
);
777 printf ("%s %s\n", opcodes
->name
, fmt
);
781 if (strcmp (prev_name
, opcodes
->name
))
786 printf ("%-5.5s ", opcodes
->name
);
787 prev_name
= (char *) opcodes
->name
;
790 printf (" [%s]", fmt
);
796 /* Print the instruction format. This operation is called when some
797 instruction is not correct. Instruction format is printed as an
800 print_insn_format (name
)
803 struct m68hc11_opcode_def
*opc
;
804 struct m68hc11_opcode
*opcode
;
807 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
810 as_bad (_("Instruction `%s' is not recognized."), name
);
813 opcode
= opc
->opcode
;
815 as_bad (_("Instruction formats for `%s':"), name
);
820 fmt
= print_opcode_format (opcode
, 0);
821 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
826 while (strcmp (opcode
->name
, name
) == 0);
829 /* Analysis of 68HC11 and 68HC12 operands. */
831 /* reg_name_search() finds the register number given its name.
832 Returns the register number or REG_NONE on failure. */
834 reg_name_search (name
)
837 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
839 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
841 if (strcasecmp (name
, "a") == 0)
843 if (strcasecmp (name
, "b") == 0)
845 if (strcasecmp (name
, "d") == 0)
847 if (strcasecmp (name
, "sp") == 0)
849 if (strcasecmp (name
, "pc") == 0)
851 if (strcasecmp (name
, "ccr") == 0)
861 while (*p
== ' ' || *p
== '\t')
867 /* Check the string at input_line_pointer
868 to see if it is a valid register name. */
872 register_id reg_number
;
873 char c
, *p
= input_line_pointer
;
875 if (!is_name_beginner (*p
++))
878 while (is_part_of_name (*p
++))
885 /* Look to see if it's in the register table. */
886 reg_number
= reg_name_search (input_line_pointer
);
887 if (reg_number
!= REG_NONE
)
892 input_line_pointer
= p
;
901 /* Parse a string of operands and return an array of expressions.
903 Operand mode[0] mode[1] exp[0] exp[1]
904 #n M6811_OP_IMM16 - O_*
905 *<exp> M6811_OP_DIRECT - O_*
906 .{+-}<exp> M6811_OP_JUMP_REL - O_*
907 <exp> M6811_OP_IND16 - O_*
908 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
909 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
910 n,+r M6812_PRE_INC " "
911 n,r- M6812_POST_DEC " "
912 n,r+ M6812_POST_INC " "
913 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
914 [D,r] M6811_OP_IDX_2 M6812_OP_REG O_register O_register
915 [n,r] M6811_OP_IDX_1 M6812_OP_REG O_constant O_register */
917 get_operand (oper
, which
, opmode
)
922 char *p
= input_line_pointer
;
926 oper
->exp
.X_op
= O_absent
;
927 oper
->reg1
= REG_NONE
;
928 oper
->reg2
= REG_NONE
;
929 mode
= M6811_OP_NONE
;
933 if (*p
== 0 || *p
== '\n' || *p
== '\r')
935 input_line_pointer
= p
;
939 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
941 mode
= M6811_OP_DIRECT
;
946 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
948 as_bad (_("Immediate operand is not allowed for operand %d."),
953 mode
= M6811_OP_IMM16
;
955 if (strncmp (p
, "%hi", 3) == 0)
958 mode
|= M6811_OP_HIGH_ADDR
;
960 else if (strncmp (p
, "%lo", 3) == 0)
963 mode
|= M6811_OP_LOW_ADDR
;
966 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
969 mode
= M6811_OP_JUMP_REL
;
973 if (current_architecture
& cpu6811
)
974 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
977 mode
= M6812_OP_IDX_2
;
980 else if (*p
== ',') /* Special handling of ,x and ,y. */
983 input_line_pointer
= p
;
985 reg
= register_name ();
989 oper
->exp
.X_op
= O_constant
;
990 oper
->exp
.X_add_number
= 0;
991 oper
->mode
= M6812_OP_IDX
;
994 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
997 input_line_pointer
= p
;
999 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_IDX_2
)
1000 reg
= register_name ();
1004 if (reg
!= REG_NONE
)
1006 p
= skip_whites (input_line_pointer
);
1007 if (*p
== ']' && mode
== M6812_OP_IDX_2
)
1010 (_("Missing second register or offset for indexed-indirect mode."));
1015 oper
->mode
= mode
| M6812_OP_REG
;
1018 if (mode
== M6812_OP_IDX_2
)
1020 as_bad (_("Missing second register for indexed-indirect mode."));
1027 input_line_pointer
= p
;
1028 reg
= register_name ();
1029 if (reg
!= REG_NONE
)
1031 p
= skip_whites (input_line_pointer
);
1032 if (mode
== M6812_OP_IDX_2
)
1036 as_bad (_("Missing `]' to close indexed-indirect mode."));
1041 input_line_pointer
= p
;
1049 /* In MRI mode, isolate the operand because we can't distinguish
1050 operands from comments. */
1055 p
= skip_whites (p
);
1056 while (*p
&& *p
!= ' ' && *p
!= '\t')
1065 /* Parse as an expression. */
1066 expression (&oper
->exp
);
1075 expression (&oper
->exp
);
1078 if (oper
->exp
.X_op
== O_illegal
)
1080 as_bad (_("Illegal operand."));
1083 else if (oper
->exp
.X_op
== O_absent
)
1085 as_bad (_("Missing operand."));
1089 p
= input_line_pointer
;
1091 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1092 || mode
== M6812_OP_IDX_2
)
1094 p
= skip_whites (input_line_pointer
);
1098 int possible_mode
= M6811_OP_NONE
;
1099 char *old_input_line
;
1102 /* 68HC12 pre increment or decrement. */
1103 if (mode
== M6811_OP_NONE
)
1107 possible_mode
= M6812_PRE_DEC
;
1112 possible_mode
= M6812_PRE_INC
;
1115 p
= skip_whites (p
);
1117 old_input_line
= input_line_pointer
;
1118 input_line_pointer
= p
;
1119 reg
= register_name ();
1121 /* Backtrack if we have a valid constant expression and
1122 it does not correspond to the offset of the 68HC12 indexed
1123 addressing mode (as in N,x). */
1124 if (reg
== REG_NONE
&& mode
== M6811_OP_NONE
1125 && possible_mode
!= M6811_OP_NONE
)
1127 oper
->mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1128 input_line_pointer
= skip_whites (old_input_line
);
1132 if (possible_mode
!= M6811_OP_NONE
)
1133 mode
= possible_mode
;
1135 if ((current_architecture
& cpu6811
)
1136 && possible_mode
!= M6811_OP_NONE
)
1137 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1139 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1140 && reg
!= REG_X
&& reg
!= REG_Y
1141 && reg
!= REG_PC
&& reg
!= REG_SP
)
1144 input_line_pointer
= p
;
1147 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1148 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1150 as_bad (_("Wrong register in register indirect mode."));
1153 if (mode
== M6812_OP_IDX_2
)
1155 p
= skip_whites (input_line_pointer
);
1158 as_bad (_("Missing `]' to close register indirect operand."));
1161 input_line_pointer
= p
;
1163 if (reg
!= REG_NONE
)
1166 if (mode
== M6811_OP_NONE
)
1168 p
= input_line_pointer
;
1171 mode
= M6812_POST_DEC
;
1173 if (current_architecture
& cpu6811
)
1175 (_("Post-decrement mode is not valid for 68HC11."));
1179 mode
= M6812_POST_INC
;
1181 if (current_architecture
& cpu6811
)
1183 (_("Post-increment mode is not valid for 68HC11."));
1186 mode
= M6812_OP_IDX
;
1188 input_line_pointer
= p
;
1191 mode
|= M6812_OP_IDX
;
1198 if (mode
== M6812_OP_D_IDX_2
)
1200 as_bad (_("Invalid indexed indirect mode."));
1205 /* If the mode is not known until now, this is either a label
1206 or an indirect address. */
1207 if (mode
== M6811_OP_NONE
)
1208 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1210 p
= input_line_pointer
;
1211 while (*p
== ' ' || *p
== '\t')
1213 input_line_pointer
= p
;
1219 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1220 | M6812_POST_INC | M6812_POST_DEC)
1222 /* Checks that the number 'num' fits for a given mode. */
1224 check_range (num
, mode
)
1228 /* Auto increment and decrement are ok for [-8..8] without 0. */
1229 if (mode
& M6812_AUTO_INC_DEC
)
1230 return (num
!= 0 && num
<= 8 && num
>= -8);
1232 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1233 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1234 mode
= M6811_OP_IND16
;
1236 if (mode
& M6812_OP_JUMP_REL16
)
1237 mode
= M6811_OP_IND16
;
1243 case M6811_OP_DIRECT
:
1244 return (num
>= 0 && num
<= 255) ? 1 : 0;
1246 case M6811_OP_BITMASK
:
1248 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1251 case M6811_OP_JUMP_REL
:
1252 return (num
>= -128 && num
<= 127) ? 1 : 0;
1254 case M6811_OP_IND16
:
1255 case M6811_OP_IMM16
:
1256 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1259 case M6812_OP_IBCC_MARKER
:
1260 case M6812_OP_TBCC_MARKER
:
1261 case M6812_OP_DBCC_MARKER
:
1262 return (num
>= -256 && num
<= 255) ? 1 : 0;
1264 case M6812_OP_TRAP_ID
:
1265 return ((num
>= 0x30 && num
<= 0x39)
1266 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1273 /* Gas fixup generation. */
1275 /* Put a 1 byte expression described by 'oper'. If this expression contains
1276 unresolved symbols, generate an 8-bit fixup. */
1278 fixup8 (oper
, mode
, opmode
)
1287 if (oper
->X_op
== O_constant
)
1289 if (mode
& M6812_OP_TRAP_ID
1290 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1292 static char trap_id_warn_once
= 0;
1294 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1295 if (trap_id_warn_once
== 0)
1297 trap_id_warn_once
= 1;
1298 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1302 if (!(mode
& M6812_OP_TRAP_ID
)
1303 && !check_range (oper
->X_add_number
, mode
))
1305 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1307 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1309 else if (oper
->X_op
!= O_register
)
1311 if (mode
& M6812_OP_TRAP_ID
)
1312 as_bad (_("The trap id must be a constant."));
1314 if (mode
== M6811_OP_JUMP_REL
)
1318 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1319 oper
, true, BFD_RELOC_8_PCREL
);
1320 fixp
->fx_pcrel_adjust
= 1;
1324 /* Now create an 8-bit fixup. If there was some %hi or %lo
1325 modifier, generate the reloc accordingly. */
1326 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1328 ((opmode
& M6811_OP_HIGH_ADDR
)
1329 ? BFD_RELOC_M68HC11_HI8
1330 : ((opmode
& M6811_OP_LOW_ADDR
)
1331 ? BFD_RELOC_M68HC11_LO8
: BFD_RELOC_8
)));
1333 number_to_chars_bigendian (f
, 0, 1);
1337 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1341 /* Put a 2 byte expression described by 'oper'. If this expression contains
1342 unresolved symbols, generate a 16-bit fixup. */
1344 fixup16 (oper
, mode
, opmode
)
1347 int opmode ATTRIBUTE_UNUSED
;
1353 if (oper
->X_op
== O_constant
)
1355 if (!check_range (oper
->X_add_number
, mode
))
1357 as_bad (_("Operand out of 16-bit range: `%ld'."),
1358 oper
->X_add_number
);
1360 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1362 else if (oper
->X_op
!= O_register
)
1366 /* Now create a 16-bit fixup. */
1367 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1369 (mode
& M6812_OP_JUMP_REL16
? true : false),
1370 (mode
& M6812_OP_JUMP_REL16
1371 ? BFD_RELOC_16_PCREL
: BFD_RELOC_16
));
1372 number_to_chars_bigendian (f
, 0, 2);
1373 if (mode
& M6812_OP_JUMP_REL16
)
1374 fixp
->fx_pcrel_adjust
= 2;
1378 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1382 /* 68HC11 and 68HC12 code generation. */
1384 /* Translate the short branch/bsr instruction into a long branch. */
1385 static unsigned char
1386 convert_branch (code
)
1389 if (IS_OPCODE (code
, M6812_BSR
))
1391 else if (IS_OPCODE (code
, M6811_BSR
))
1393 else if (IS_OPCODE (code
, M6811_BRA
))
1394 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1396 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1398 /* Keep gcc happy. */
1402 /* Start a new insn that contains at least 'size' bytes. Record the
1403 line information of that insn in the dwarf2 debug sections. */
1405 m68hc11_new_insn (size
)
1410 f
= frag_more (size
);
1412 dwarf2_emit_insn (size
);
1417 /* Builds a jump instruction (bra, bcc, bsr). */
1419 build_jump_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1420 struct m68hc11_opcode
*opcode
;
1429 /* The relative branch convertion is not supported for
1431 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1432 assert (nb_operands
== 1);
1433 assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1435 code
= opcode
->opcode
;
1437 n
= operands
[0].exp
.X_add_number
;
1439 /* Turn into a long branch:
1440 - when force long branch option (and not for jbcc pseudos),
1441 - when jbcc and the constant is out of -128..127 range,
1442 - when branch optimization is allowed and branch out of range. */
1443 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1444 || (operands
[0].exp
.X_op
== O_constant
1445 && (!check_range (n
, opcode
->format
) &&
1446 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1448 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1450 code
= convert_branch (code
);
1452 f
= m68hc11_new_insn (1);
1453 number_to_chars_bigendian (f
, code
, 1);
1455 else if (current_architecture
& cpu6812
)
1457 /* 68HC12: translate the bcc into a lbcc. */
1458 f
= m68hc11_new_insn (2);
1459 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1460 number_to_chars_bigendian (f
+ 1, code
, 1);
1461 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1462 M6812_OP_JUMP_REL16
);
1467 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1468 f
= m68hc11_new_insn (3);
1470 number_to_chars_bigendian (f
, code
, 1);
1471 number_to_chars_bigendian (f
+ 1, 3, 1);
1472 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1474 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1478 /* Branch with a constant that must fit in 8-bits. */
1479 if (operands
[0].exp
.X_op
== O_constant
)
1481 if (!check_range (n
, opcode
->format
))
1483 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1486 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1488 f
= m68hc11_new_insn (4);
1489 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1490 number_to_chars_bigendian (f
+ 1, code
, 1);
1491 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1495 f
= m68hc11_new_insn (2);
1496 number_to_chars_bigendian (f
, code
, 1);
1497 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1500 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1502 f
= m68hc11_new_insn (2);
1503 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1504 number_to_chars_bigendian (f
+ 1, code
, 1);
1505 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1511 /* Branch offset must fit in 8-bits, don't do some relax. */
1512 if (jmp_mode
== 0 && flag_fixed_branchs
)
1514 opcode
= m68hc11_new_insn (1);
1515 number_to_chars_bigendian (opcode
, code
, 1);
1516 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1519 /* bra/bsr made be changed into jmp/jsr. */
1520 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1522 opcode
= m68hc11_new_insn (2);
1523 number_to_chars_bigendian (opcode
, code
, 1);
1524 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1525 frag_var (rs_machine_dependent
, 2, 1,
1526 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1527 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1529 else if (current_architecture
& cpu6812
)
1531 opcode
= m68hc11_new_insn (2);
1532 number_to_chars_bigendian (opcode
, code
, 1);
1533 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1534 frag_var (rs_machine_dependent
, 2, 2,
1535 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1536 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1540 opcode
= m68hc11_new_insn (2);
1541 number_to_chars_bigendian (opcode
, code
, 1);
1542 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1543 frag_var (rs_machine_dependent
, 3, 3,
1544 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1545 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1550 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1552 build_dbranch_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1553 struct m68hc11_opcode
*opcode
;
1562 /* The relative branch convertion is not supported for
1564 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1565 assert (nb_operands
== 2);
1566 assert (operands
[0].reg1
!= REG_NONE
);
1568 code
= opcode
->opcode
& 0x0FF;
1570 f
= m68hc11_new_insn (1);
1571 number_to_chars_bigendian (f
, code
, 1);
1573 n
= operands
[1].exp
.X_add_number
;
1574 code
= operands
[0].reg1
;
1576 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
1577 || operands
[0].reg1
== REG_PC
)
1578 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1580 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
1582 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
1585 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
1588 /* Turn into a long branch:
1589 - when force long branch option (and not for jbcc pseudos),
1590 - when jdbcc and the constant is out of -256..255 range,
1591 - when branch optimization is allowed and branch out of range. */
1592 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1593 || (operands
[1].exp
.X_op
== O_constant
1594 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
1595 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1599 number_to_chars_bigendian (f
, code
, 1);
1600 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
1601 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1605 /* Branch with a constant that must fit in 9-bits. */
1606 if (operands
[1].exp
.X_op
== O_constant
)
1608 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
1610 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1619 number_to_chars_bigendian (f
, code
, 1);
1620 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1625 /* Branch offset must fit in 8-bits, don't do some relax. */
1626 if (jmp_mode
== 0 && flag_fixed_branchs
)
1628 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1634 number_to_chars_bigendian (f
, code
, 1);
1635 number_to_chars_bigendian (f
+ 1, 0, 1);
1636 frag_var (rs_machine_dependent
, 3, 3,
1637 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
1638 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
1643 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1645 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1647 build_indexed_byte (op
, format
, move_insn
)
1649 int format ATTRIBUTE_UNUSED
;
1652 unsigned char byte
= 0;
1657 val
= op
->exp
.X_add_number
;
1659 if (mode
& M6812_AUTO_INC_DEC
)
1662 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
1665 if (op
->exp
.X_op
== O_constant
)
1667 if (!check_range (val
, mode
))
1669 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1672 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
1673 byte
|= (val
- 1) & 0x07;
1675 byte
|= (8 - ((val
) & 7)) | 0x8;
1680 as_fatal (_("Expecting a register."));
1695 as_bad (_("Invalid register for post/pre increment."));
1700 number_to_chars_bigendian (f
, byte
, 1);
1704 if (mode
& M6812_OP_IDX
)
1725 as_bad (_("Invalid register."));
1728 if (op
->exp
.X_op
== O_constant
)
1730 if (!check_range (val
, M6812_OP_IDX
))
1732 as_bad (_("Offset out of 16-bit range: %ld."), val
);
1735 if (move_insn
&& !(val
>= -16 && val
<= 15))
1737 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
1742 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_IDX_2
))
1747 number_to_chars_bigendian (f
, byte
, 1);
1750 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_IDX_2
))
1757 number_to_chars_bigendian (f
, byte
, 1);
1758 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
1764 if (mode
& M6812_OP_IDX_2
)
1770 number_to_chars_bigendian (f
, byte
, 1);
1771 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
1775 if (op
->reg1
!= REG_PC
)
1777 byte
= (byte
<< 3) | 0xe2;
1779 number_to_chars_bigendian (f
, byte
, 1);
1782 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1783 &op
->exp
, false, BFD_RELOC_16
);
1784 number_to_chars_bigendian (f
, 0, 2);
1789 number_to_chars_bigendian (f
, byte
, 1);
1790 frag_var (rs_machine_dependent
, 2, 2,
1791 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
1792 op
->exp
.X_add_symbol
,
1793 op
->exp
.X_add_number
, f
);
1798 if (mode
& M6812_OP_REG
)
1800 if (mode
& M6812_OP_IDX_2
)
1802 if (op
->reg1
!= REG_D
)
1803 as_bad (_("Expecting register D for indexed indirect mode."));
1805 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
1822 as_bad (_("Invalid accumulator register."));
1847 as_bad (_("Invalid indexed register."));
1851 number_to_chars_bigendian (f
, byte
, 1);
1855 as_fatal (_("Addressing mode not implemented yet."));
1859 /* Assemble the 68HC12 register mode byte. */
1861 build_reg_mode (op
, format
)
1868 if (format
& M6812_OP_SEX_MARKER
1869 && op
->reg1
!= REG_A
&& op
->reg1
!= REG_B
&& op
->reg1
!= REG_CCR
)
1870 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
1871 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
1872 as_bad (_("Invalid source register."));
1874 if (format
& M6812_OP_SEX_MARKER
1875 && op
->reg2
!= REG_D
1876 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
1877 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
1878 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
1879 as_bad (_("Invalid destination register."));
1881 byte
= (op
->reg1
<< 4) | (op
->reg2
);
1882 if (format
& M6812_OP_EXG_MARKER
)
1886 number_to_chars_bigendian (f
, byte
, 1);
1890 /* build_insn takes a pointer to the opcode entry in the opcode table,
1891 the array of operand expressions and builds the correspding instruction.
1892 This operation only deals with non relative jumps insn (need special
1895 build_insn (opcode
, operands
, nb_operands
)
1896 struct m68hc11_opcode
*opcode
;
1898 int nb_operands ATTRIBUTE_UNUSED
;
1905 /* Put the page code instruction if there is one. */
1906 format
= opcode
->format
;
1907 if (format
& OP_EXTENDED
)
1911 f
= m68hc11_new_insn (2);
1912 if (format
& M6811_OP_PAGE2
)
1913 page_code
= M6811_OPCODE_PAGE2
;
1914 else if (format
& M6811_OP_PAGE3
)
1915 page_code
= M6811_OPCODE_PAGE3
;
1917 page_code
= M6811_OPCODE_PAGE4
;
1919 number_to_chars_bigendian (f
, page_code
, 1);
1923 f
= m68hc11_new_insn (1);
1925 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
1929 /* The 68HC12 movb and movw instructions are special. We have to handle
1930 them in a special way. */
1931 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
1934 if (format
& M6812_OP_IDX
)
1936 build_indexed_byte (&operands
[0], format
, 1);
1938 format
&= ~M6812_OP_IDX
;
1940 if (format
& M6812_OP_IDX_P2
)
1942 build_indexed_byte (&operands
[1], format
, 1);
1944 format
&= ~M6812_OP_IDX_P2
;
1948 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
1950 fixup8 (&operands
[i
].exp
,
1951 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
1955 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
1957 fixup16 (&operands
[i
].exp
, format
& (M6811_OP_IMM16
| M6811_OP_IND16
),
1961 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
1963 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
1964 as_bad (_("Invalid indexed register, expecting register X."));
1965 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
1966 as_bad (_("Invalid indexed register, expecting register Y."));
1968 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
1972 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
| M6812_OP_D_IDX
))
1974 build_indexed_byte (&operands
[i
], format
, move_insn
);
1977 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
1979 build_reg_mode (&operands
[i
], format
);
1982 if (format
& M6811_OP_BITMASK
)
1984 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
1987 if (format
& M6811_OP_JUMP_REL
)
1989 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
1991 else if (format
& M6812_OP_IND16_P2
)
1993 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
1997 /* Opcode identification and operand analysis. */
1999 /* find() gets a pointer to an entry in the opcode table. It must look at all
2000 opcodes with the same name and use the operands to choose the correct
2001 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2002 static struct m68hc11_opcode
*
2003 find (opc
, operands
, nb_operands
)
2004 struct m68hc11_opcode_def
*opc
;
2009 struct m68hc11_opcode
*opcode
;
2010 struct m68hc11_opcode
*op_indirect
;
2013 opcode
= opc
->opcode
;
2015 /* Now search the opcode table table for one with operands
2016 that matches what we've got. We're only done if the operands matched so
2017 far AND there are no more to check. */
2018 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2020 int poss_indirect
= 0;
2021 long format
= opcode
->format
;
2025 if (opcode
->format
& M6811_OP_MASK
)
2027 if (opcode
->format
& M6811_OP_BITMASK
)
2029 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2031 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2034 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2036 int mode
= operands
[i
].mode
;
2038 if (mode
& M6811_OP_IMM16
)
2041 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2045 if (mode
== M6811_OP_DIRECT
)
2047 if (format
& M6811_OP_DIRECT
)
2050 /* If the operand is a page 0 operand, remember a
2051 possible <abs-16> addressing mode. We mark
2052 this and continue to check other operands. */
2053 if (format
& M6811_OP_IND16
2054 && flag_strict_direct_addressing
&& op_indirect
== 0)
2061 if (mode
& M6811_OP_IND16
)
2063 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2065 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2067 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2070 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2072 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2075 if (mode
& M6812_OP_REG
)
2078 && (format
& M6812_OP_REG
)
2079 && (operands
[i
].reg2
== REG_NONE
))
2082 && (format
& M6812_OP_REG
)
2083 && (format
& M6812_OP_REG_2
)
2084 && (operands
[i
].reg2
!= REG_NONE
))
2087 && (format
& M6812_OP_IDX
)
2088 && (operands
[i
].reg2
!= REG_NONE
))
2091 && (format
& M6812_OP_D_IDX
))
2094 && (format
& M6812_OP_IDX
)
2095 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2098 && (format
& M6812_OP_IDX_P2
))
2102 if (mode
& M6812_OP_IDX
)
2104 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2106 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2109 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2110 && (operands
[i
].reg1
== REG_X
2111 || operands
[i
].reg1
== REG_Y
2112 || operands
[i
].reg1
== REG_SP
2113 || operands
[i
].reg1
== REG_PC
))
2115 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2118 if (mode
& M6812_AUTO_INC_DEC
)
2121 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2124 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2129 match
= i
== nb_operands
;
2131 /* Operands are ok but an operand uses page 0 addressing mode
2132 while the insn supports abs-16 mode. Keep a reference to this
2133 insns in case there is no insn supporting page 0 addressing. */
2134 if (match
&& poss_indirect
)
2136 op_indirect
= opcode
;
2143 /* Page 0 addressing is used but not supported by any insn.
2144 If absolute addresses are supported, we use that insn. */
2145 if (match
== 0 && op_indirect
)
2147 opcode
= op_indirect
;
2159 /* Find the real opcode and its associated operands. We use a progressive
2160 approach here. On entry, 'opc' points to the first opcode in the
2161 table that matches the opcode name in the source line. We try to
2162 isolate an operand, find a possible match in the opcode table.
2163 We isolate another operand if no match were found. The table 'operands'
2164 is filled while operands are recognized.
2166 Returns the opcode pointer that matches the opcode name in the
2167 source line and the associated operands. */
2168 static struct m68hc11_opcode
*
2169 find_opcode (opc
, operands
, nb_operands
)
2170 struct m68hc11_opcode_def
*opc
;
2174 struct m68hc11_opcode
*opcode
;
2177 if (opc
->max_operands
== 0)
2183 for (i
= 0; i
< opc
->max_operands
;)
2187 result
= get_operand (&operands
[i
], i
, opc
->format
);
2191 /* Special case where the bitmask of the bclr/brclr
2192 instructions is not introduced by #.
2193 Example: bclr 3,x $80. */
2194 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2195 && (operands
[i
].mode
& M6811_OP_IND16
))
2197 operands
[i
].mode
= M6811_OP_IMM16
;
2202 if (i
>= opc
->min_operands
)
2204 opcode
= find (opc
, operands
, i
);
2209 if (*input_line_pointer
== ',')
2210 input_line_pointer
++;
2216 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2217 | M6812_OP_DBCC_MARKER \
2218 | M6812_OP_IBCC_MARKER)
2220 /* Gas line assembler entry point. */
2222 /* This is the main entry point for the machine-dependent assembler. str
2223 points to a machine-dependent instruction. This function is supposed to
2224 emit the frags/bytes it assembles to. */
2229 struct m68hc11_opcode_def
*opc
;
2230 struct m68hc11_opcode
*opcode
;
2232 unsigned char *op_start
, *save
;
2233 unsigned char *op_end
;
2236 operand operands
[M6811_MAX_OPERANDS
];
2238 int branch_optimize
= 0;
2241 /* Drop leading whitespace. */
2245 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2246 lower case (the opcode table only has lower case op-codes). */
2247 for (op_start
= op_end
= (unsigned char *) (str
);
2248 *op_end
&& nlen
< 20 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2251 name
[nlen
] = TOLOWER (op_start
[nlen
]);
2258 as_bad (_("No instruction or missing opcode."));
2262 /* Find the opcode definition given its name. */
2263 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
2265 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2266 pseudo insns for relative branch. For these branchs, we always
2267 optimize them (turned into absolute branchs) even if --short-branchs
2269 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
2271 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, &name
[1]);
2273 && (!(opc
->format
& M6811_OP_JUMP_REL
)
2274 || (opc
->format
& M6811_OP_BITMASK
)))
2277 branch_optimize
= 1;
2280 /* The following test should probably be removed. This is not conform
2281 to Motorola assembler specs. */
2282 if (opc
== NULL
&& flag_mri
)
2284 if (*op_end
== ' ' || *op_end
== '\t')
2286 while (*op_end
== ' ' || *op_end
== '\t')
2291 (is_end_of_line
[op_end
[1]]
2292 || op_end
[1] == ' ' || op_end
[1] == '\t'
2293 || !ISALNUM (op_end
[1])))
2294 && (*op_end
== 'a' || *op_end
== 'b'
2295 || *op_end
== 'A' || *op_end
== 'B'
2296 || *op_end
== 'd' || *op_end
== 'D'
2297 || *op_end
== 'x' || *op_end
== 'X'
2298 || *op_end
== 'y' || *op_end
== 'Y'))
2300 name
[nlen
++] = TOLOWER (*op_end
++);
2302 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
,
2308 /* Identify a possible instruction alias. There are some on the
2309 68HC12 to emulate a few 68HC11 instructions. */
2310 if (opc
== NULL
&& (current_architecture
& cpu6812
))
2314 for (i
= 0; i
< m68hc12_num_alias
; i
++)
2315 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
2321 if (opc
== NULL
&& alias_id
< 0)
2323 as_bad (_("Opcode `%s' is not recognized."), name
);
2326 save
= input_line_pointer
;
2327 input_line_pointer
= op_end
;
2332 opcode
= find_opcode (opc
, operands
, &nb_operands
);
2337 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
2339 char *p
= input_line_pointer
;
2341 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
2344 if (*p
!= '\n' && *p
)
2345 as_bad (_("Garbage at end of instruction: `%s'."), p
);
2348 input_line_pointer
= save
;
2352 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
2354 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
2355 if (m68hc12_alias
[alias_id
].size
> 1)
2356 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
2361 /* Opcode is known but does not have valid operands. Print out the
2362 syntax for this opcode. */
2365 if (flag_print_insn_syntax
)
2366 print_insn_format (name
);
2368 as_bad (_("Invalid operand for `%s'"), name
);
2372 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2373 relative and must be in the range -256..255 (9-bits). */
2374 if ((opcode
->format
& M6812_XBCC_MARKER
)
2375 && (opcode
->format
& M6811_OP_JUMP_REL
))
2376 build_dbranch_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2378 /* Relative jumps instructions are taken care of separately. We have to make
2379 sure that the relative branch is within the range -128..127. If it's out
2380 of range, the instructions are changed into absolute instructions.
2381 This is not supported for the brset and brclr instructions. */
2382 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2383 && !(opcode
->format
& M6811_OP_BITMASK
))
2384 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2386 build_insn (opcode
, operands
, nb_operands
);
2389 /* Relocation, relaxation and frag conversions. */
2391 md_pcrel_from_section (fixp
, sec
)
2396 if (fixp
->fx_addsy
!= (symbolS
*) NULL
2397 && (!S_IS_DEFINED (fixp
->fx_addsy
)
2398 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
2401 adjust
= fixp
->fx_pcrel_adjust
;
2402 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
+ adjust
;
2405 /* If while processing a fixup, a reloc really needs to be created
2406 then it is done here. */
2408 tc_gen_reloc (section
, fixp
)
2414 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2415 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2416 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2417 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2418 if (fixp
->fx_r_type
== 0)
2419 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
2421 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2422 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
2424 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2425 _("Relocation %d is not supported by object file format."),
2426 (int) fixp
->fx_r_type
);
2430 if (!fixp
->fx_pcrel
)
2431 reloc
->addend
= fixp
->fx_addnumber
;
2433 reloc
->addend
= (section
->vma
2434 + (fixp
->fx_pcrel_adjust
== 64
2435 ? -1 : fixp
->fx_pcrel_adjust
)
2436 + fixp
->fx_addnumber
2437 + md_pcrel_from_section (fixp
, section
));
2442 md_convert_frag (abfd
, sec
, fragP
)
2443 bfd
*abfd ATTRIBUTE_UNUSED
;
2444 asection
*sec ATTRIBUTE_UNUSED
;
2450 char *buffer_address
= fragP
->fr_literal
;
2452 /* Address in object code of the displacement. */
2453 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
2455 buffer_address
+= fragP
->fr_fix
;
2457 /* The displacement of the address, from current location. */
2458 value
= S_GET_VALUE (fragP
->fr_symbol
);
2459 disp
= (value
+ fragP
->fr_offset
) - object_address
;
2461 switch (fragP
->fr_subtype
)
2463 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
2464 fragP
->fr_opcode
[1] = disp
;
2467 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
2468 /* This relax is only for bsr and bra. */
2469 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2470 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2471 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2473 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
2475 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
2476 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2480 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
2481 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
2482 fragP
->fr_opcode
[1] = disp
;
2485 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
2486 /* Invert branch. */
2487 fragP
->fr_opcode
[0] ^= 1;
2488 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2489 buffer_address
[0] = M6811_JMP
;
2490 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2491 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2495 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
2496 /* Translate branch into a long branch. */
2497 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
2498 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
2500 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2501 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
2502 BFD_RELOC_16_PCREL
);
2503 fixp
->fx_pcrel_adjust
= 2;
2507 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
2508 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 6;
2509 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0c0)
2510 fragP
->fr_opcode
[0] |= disp
& 0x1f;
2512 fragP
->fr_opcode
[0] |= value
& 0x1f;
2515 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
2516 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2517 fragP
->fr_opcode
[0] |= 0xE0;
2518 fix_new (fragP
, fragP
->fr_fix
, 1,
2519 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_8
);
2523 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
2524 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2525 fragP
->fr_opcode
[0] |= 0xe2;
2526 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0fa)
2528 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2529 fragP
->fr_symbol
, fragP
->fr_offset
,
2530 1, BFD_RELOC_16_PCREL
);
2531 fixp
->fx_pcrel_adjust
= 2;
2535 fix_new (fragP
, fragP
->fr_fix
, 2,
2536 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2541 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
2543 fragP
->fr_opcode
[0] |= 0x10;
2545 fragP
->fr_opcode
[1] = disp
& 0x0FF;
2548 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
2549 /* Invert branch. */
2550 fragP
->fr_opcode
[0] ^= 0x20;
2551 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2552 buffer_address
[0] = M6812_JMP
;
2553 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2554 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2563 /* On an ELF system, we can't relax a weak symbol. The weak symbol
2564 can be overridden at final link time by a non weak symbol. We can
2565 relax externally visible symbol because there is no shared library
2566 and such symbol can't be overridden (unless they are weak). */
2568 relaxable_symbol (symbol
)
2571 return ! S_IS_WEAK (symbol
);
2574 /* Force truly undefined symbols to their maximum size, and generally set up
2575 the frag list to be relaxed. */
2577 md_estimate_size_before_relax (fragP
, segment
)
2581 if (RELAX_LENGTH (fragP
->fr_subtype
) == STATE_UNDF
)
2583 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2584 || !relaxable_symbol (fragP
->fr_symbol
))
2586 /* Non-relaxable cases. */
2588 char *buffer_address
;
2590 old_fr_fix
= fragP
->fr_fix
;
2591 buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
2593 switch (RELAX_STATE (fragP
->fr_subtype
))
2595 case STATE_PC_RELATIVE
:
2597 /* This relax is only for bsr and bra. */
2598 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2599 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2600 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2602 if (flag_fixed_branchs
)
2603 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
2604 _("bra or bsr with undefined symbol."));
2606 /* The symbol is undefined or in a separate section.
2607 Turn bra into a jmp and bsr into a jsr. The insn
2608 becomes 3 bytes long (instead of 2). A fixup is
2609 necessary for the unresolved symbol address. */
2610 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
2612 fix_new (fragP
, fragP
->fr_fix
- 1, 2, fragP
->fr_symbol
,
2613 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2617 case STATE_CONDITIONAL_BRANCH
:
2618 assert (current_architecture
& cpu6811
);
2620 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
2621 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
2623 /* Don't use fr_opcode[2] because this may be
2624 in a different frag. */
2625 buffer_address
[0] = M6811_JMP
;
2628 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2629 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2633 case STATE_INDEXED_OFFSET
:
2634 assert (current_architecture
& cpu6812
);
2636 /* Switch the indexed operation to 16-bit mode. */
2637 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
2638 fragP
->fr_opcode
[0] |= 0xe2;
2640 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2641 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2645 case STATE_XBCC_BRANCH
:
2646 assert (current_architecture
& cpu6812
);
2648 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
2649 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
2651 /* Don't use fr_opcode[2] because this may be
2652 in a different frag. */
2653 buffer_address
[0] = M6812_JMP
;
2656 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2657 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2661 case STATE_CONDITIONAL_BRANCH_6812
:
2662 assert (current_architecture
& cpu6812
);
2664 /* Translate into a lbcc branch. */
2665 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
2666 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
2668 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2669 fragP
->fr_offset
, 0, BFD_RELOC_16_PCREL
);
2674 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
2678 /* Return the growth in the fixed part of the frag. */
2679 return fragP
->fr_fix
- old_fr_fix
;
2682 /* Relaxable cases. */
2683 switch (RELAX_STATE (fragP
->fr_subtype
))
2685 case STATE_PC_RELATIVE
:
2686 /* This relax is only for bsr and bra. */
2687 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2688 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2689 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2691 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
2694 case STATE_CONDITIONAL_BRANCH
:
2695 assert (current_architecture
& cpu6811
);
2697 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
2701 case STATE_INDEXED_OFFSET
:
2702 assert (current_architecture
& cpu6812
);
2704 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
2708 case STATE_XBCC_BRANCH
:
2709 assert (current_architecture
& cpu6812
);
2711 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
2714 case STATE_CONDITIONAL_BRANCH_6812
:
2715 assert (current_architecture
& cpu6812
);
2717 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
2723 if (fragP
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
2724 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
2726 /* Return the size of the variable part of the frag. */
2727 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
2731 md_apply_fix (fixp
, valuep
)
2739 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
2744 else if (fixp
->fx_pcrel
)
2750 value
= fixp
->fx_offset
;
2751 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
2753 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
2755 value
-= S_GET_VALUE (fixp
->fx_subsy
);
2759 /* We don't actually support subtracting a symbol. */
2760 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2761 _("Expression too complex."));
2766 op_type
= fixp
->fx_r_type
;
2768 /* Patch the instruction with the resolved operand. Elf relocation
2769 info will also be generated to take care of linker/loader fixups.
2770 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
2771 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
2772 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
2773 because it's either resolved or turned out into non-relative insns (see
2774 relax table, bcc, bra, bsr transformations)
2776 The BFD_RELOC_32 is necessary for the support of --gstabs. */
2777 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
2779 switch (fixp
->fx_r_type
)
2782 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
2786 case BFD_RELOC_16_PCREL
:
2787 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
2788 if (value
< -65537 || value
> 65535)
2789 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2790 _("Value out of 16-bit range."));
2793 case BFD_RELOC_M68HC11_HI8
:
2797 case BFD_RELOC_M68HC11_LO8
:
2800 bfd_putb8 ((bfd_vma
) value
, (unsigned char *) where
);
2802 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
2805 case BFD_RELOC_8_PCREL
:
2807 bfd_putb8 ((bfd_vma
) value
, (unsigned char *) where
);
2809 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
2811 if (value
< -128 || value
> 127)
2812 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2813 _("Value %ld too large for 8-bit PC-relative branch."),
2817 case BFD_RELOC_M68HC11_3B
:
2818 if (value
<= 0 || value
> 8)
2819 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2820 _("Auto increment/decrement offset '%ld' is out of range."),
2827 where
[0] = where
[0] | (value
& 0x07);
2831 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
2832 fixp
->fx_line
, fixp
->fx_r_type
);