1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright (C) 1999, 2000 Free Software Foundation.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
29 struct dwarf2_line_info debug_line
;
31 const char comment_chars
[] = ";!";
32 const char line_comment_chars
[] = "#*";
33 const char line_separator_chars
[] = "";
35 const char EXP_CHARS
[] = "eE";
36 const char FLT_CHARS
[] = "dD";
38 #define STATE_CONDITIONAL_BRANCH (1)
39 #define STATE_PC_RELATIVE (2)
40 #define STATE_INDEXED_OFFSET (3)
41 #define STATE_XBCC_BRANCH (4)
42 #define STATE_CONDITIONAL_BRANCH_6812 (5)
44 #define STATE_BYTE (0)
45 #define STATE_BITS5 (0)
46 #define STATE_WORD (1)
47 #define STATE_BITS9 (1)
48 #define STATE_LONG (2)
49 #define STATE_BITS16 (2)
50 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
52 /* This macro has no side-effects. */
53 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
55 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
57 /* This table describes how you change sizes for the various types of variable
58 size expressions. This version only supports two kinds. */
61 How far Forward this mode will reach:
62 How far Backward this mode will reach:
63 How many bytes this mode will add to the size of the frag
64 Which mode to go to if the offset won't fit in this one */
66 relax_typeS md_relax_table
[] = {
67 {1, 1, 0, 0}, /* First entries aren't used */
68 {1, 1, 0, 0}, /* For no good reason except */
69 {1, 1, 0, 0}, /* that the VAX doesn't either */
73 These insns are translated into b!cc +3 jmp L. */
74 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
79 /* Relax for bsr <L> and bra <L>.
80 These insns are translated into jsr and jmp. */
81 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
86 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
87 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
88 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
92 /* Relax for dbeq/ibeq/tbeq r,<L>:
93 These insns are translated into db!cc +3 jmp L. */
94 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
99 /* Relax for bcc <L> on 68HC12.
100 These insns are translated into lbcc <L>. */
101 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
108 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
109 typedef enum register_id
122 typedef struct operand
130 struct m68hc11_opcode_def
137 struct m68hc11_opcode
*opcode
;
140 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
141 static int m68hc11_nb_opcode_defs
= 0;
150 static alias alias_opcodes
[] = {
157 /* local functions */
158 static register_id reg_name_search
PARAMS ((char *name
));
159 static register_id register_name
PARAMS (());
160 static int check_range
PARAMS ((long num
, int mode
));
162 static void print_opcode_list
PARAMS ((void));
164 static void get_default_target
PARAMS ((void));
165 static void print_insn_format
PARAMS ((char *name
));
166 static int get_operand
PARAMS ((operand
* op
, int first
, long opmode
));
167 static void fixup8
PARAMS ((expressionS
* oper
, int mode
, int opmode
));
168 static void fixup16
PARAMS ((expressionS
* oper
, int mode
, int opmode
));
169 static struct m68hc11_opcode
*find_opcode
171 (struct m68hc11_opcode_def
* opc
, operand operands
[],
173 static void build_jump_insn
175 (struct m68hc11_opcode
* opcode
, operand operands
[], int nb_operands
,
178 static void build_insn
PARAMS ((struct m68hc11_opcode
* opcode
,
179 operand operands
[], int nb_operands
));
181 /* Controls whether relative branches can be turned into long branches.
182 When the relative offset is too large, the insn are changed:
190 Setting the flag forbidds this. */
191 static short flag_fixed_branchs
= 0;
193 /* Force to use long jumps (absolute) instead of relative branches. */
194 static short flag_force_long_jumps
= 0;
196 /* Change the direct addressing mode into an absolute addressing mode
197 when the insn does not support direct addressing.
198 For example, "clr *ZD0" is normally not possible and is changed
200 static short flag_strict_direct_addressing
= 1;
202 /* When an opcode has invalid operand, print out the syntax of the opcode
204 static short flag_print_insn_syntax
= 0;
206 /* Dumps the list of instructions with syntax and then exit:
207 1 -> Only dumps the list (sorted by name)
208 2 -> Generate an example (or test) that can be compiled. */
209 static short flag_print_opcodes
= 0;
211 /* Opcode hash table. */
212 static struct hash_control
*m68hc11_hash
;
214 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
215 by 'get_default_target' by looking at default BFD vector. This is overriden
216 with the -m<cpu> option. */
217 static int current_architecture
= 0;
219 /* Default cpu determined by 'get_default_target'. */
220 static const char *default_cpu
;
222 /* Number of opcodes in the sorted table (filtered by current cpu). */
223 static int num_opcodes
;
225 /* The opcodes sorted by name and filtered by current cpu. */
226 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
228 /* These are the machine dependent pseudo-ops. These are included so
229 the assembler can work on the output from the SUN C compiler, which
232 /* This table describes all the machine specific pseudo-ops the assembler
233 has to support. The fields are:
234 pseudo-op name without dot
235 function to call to execute this pseudo-op
236 Integer arg to pass to the function. */
237 const pseudo_typeS md_pseudo_table
[] = {
238 /* The following pseudo-ops are supported for MRI compatibility. */
241 {"fcc", stringer
, 1},
243 {"file", dwarf2_directive_file
, 0},
244 {"loc", dwarf2_directive_loc
, 0},
250 /* Options and initialization. */
252 CONST
char *md_shortopts
= "Sm:";
254 struct option md_longopts
[] = {
255 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
256 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
258 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
259 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHS
},
261 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
262 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
264 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
265 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
267 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
268 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
270 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
271 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
273 {NULL
, no_argument
, NULL
, 0}
275 size_t md_longopts_size
= sizeof (md_longopts
);
277 /* Get the target cpu for the assembler. This is based on the configure
278 options and on the -m68hc11/-m68hc12 option. If no option is specified,
279 we must get the default. */
281 m68hc11_arch_format ()
283 get_default_target ();
284 if (current_architecture
& cpu6811
)
285 return "elf32-m68hc11";
287 return "elf32-m68hc12";
290 enum bfd_architecture
293 get_default_target ();
294 if (current_architecture
& cpu6811
)
295 return bfd_arch_m68hc11
;
297 return bfd_arch_m68hc12
;
308 md_show_usage (stream
)
311 get_default_target ();
312 fprintf (stream
, _("\
313 Motorola 68HC11/68HC12 options:\n\
314 -m68hc11 | -m68hc12 specify the processor [default %s]\n\
315 --force-long-branchs always turn relative branchs into absolute ones\n\
316 -S,--short-branchs do not turn relative branchs into absolute ones\n\
317 when the offset is out of range\n\
318 --strict-direct-mode do not turn the direct mode into extended mode\n\
319 when the instruction does not support direct mode\n\
320 --print-insn-syntax print the syntax of instruction in case of error\n\
321 --print-opcodes print the list of instructions with syntax\n\
322 --generate-example generate an example of each instruction\n\
323 (used for testing)\n"), default_cpu
);
327 /* Try to identify the default target based on the BFD library. */
329 get_default_target ()
331 const bfd_target
*target
;
334 if (current_architecture
!= 0)
337 default_cpu
= "unknown";
338 target
= bfd_find_target (0, &abfd
);
339 if (target
&& target
->name
)
341 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
343 current_architecture
= cpu6812
;
344 default_cpu
= "m68hc12";
346 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
348 current_architecture
= cpu6811
;
349 default_cpu
= "m68hc11";
353 as_bad (_("Default target `%s' is not supported."), target
->name
);
359 m68hc11_print_statistics (file
)
363 struct m68hc11_opcode_def
*opc
;
365 hash_print_statistics (file
, "opcode table", m68hc11_hash
);
367 opc
= m68hc11_opcode_defs
;
368 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
371 /* Dump the opcode statistics table. */
372 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
373 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
375 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
378 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
383 md_parse_option (c
, arg
)
387 get_default_target ();
390 /* -S means keep external to 2 bits offset rather than 16 bits one. */
391 case OPTION_SHORT_BRANCHS
:
393 flag_fixed_branchs
= 1;
396 case OPTION_FORCE_LONG_BRANCH
:
397 flag_force_long_jumps
= 1;
400 case OPTION_PRINT_INSN_SYNTAX
:
401 flag_print_insn_syntax
= 1;
404 case OPTION_PRINT_OPCODES
:
405 flag_print_opcodes
= 1;
408 case OPTION_STRICT_DIRECT_MODE
:
409 flag_strict_direct_addressing
= 0;
412 case OPTION_GENERATE_EXAMPLE
:
413 flag_print_opcodes
= 2;
417 if (strcasecmp (arg
, "68hc11") == 0)
418 current_architecture
= cpu6811
;
419 else if (strcasecmp (arg
, "68hc12") == 0)
420 current_architecture
= cpu6812
;
422 as_bad (_("Option `%s' is not recognized."), arg
);
433 md_undefined_symbol (name
)
434 char *name ATTRIBUTE_UNUSED
;
439 /* Equal to MAX_PRECISION in atof-ieee.c */
440 #define MAX_LITTLENUMS 6
442 /* Turn a string in input_line_pointer into a floating point constant
443 of type type, and store the appropriate bytes in *litP. The number
444 of LITTLENUMS emitted is stored in *sizeP . An error message is
445 returned, or NULL on OK. */
448 md_atof (type
, litP
, sizeP
)
454 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
455 LITTLENUM_TYPE
*wordP
;
486 return _("Bad call to MD_ATOF()");
488 t
= atof_ieee (input_line_pointer
, type
, words
);
490 input_line_pointer
= t
;
492 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
493 for (wordP
= words
; prec
--;)
495 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
496 litP
+= sizeof (LITTLENUM_TYPE
);
502 md_section_align (seg
, addr
)
506 int align
= bfd_get_section_alignment (stdoutput
, seg
);
507 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
512 cmp_opcode (op1
, op2
)
513 struct m68hc11_opcode
*op1
;
514 struct m68hc11_opcode
*op2
;
516 return strcmp (op1
->name
, op2
->name
);
519 /* Initialize the assembler. Create the opcode hash table
520 (sorted on the names) with the M6811 opcode table
521 (from opcode library). */
525 char *prev_name
= "";
526 struct m68hc11_opcode
*opcodes
;
527 struct m68hc11_opcode_def
*opc
= 0;
530 get_default_target ();
532 m68hc11_hash
= hash_new ();
534 /* Get a writable copy of the opcode table and sort it on the names. */
535 opcodes
= (struct m68hc11_opcode
*) xmalloc (m68hc11_num_opcodes
*
538 m68hc11_sorted_opcodes
= opcodes
;
540 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
542 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
544 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
545 if (opcodes
[num_opcodes
].name
[0] == 'b'
546 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
547 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
550 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
553 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
554 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
556 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
557 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
563 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
), cmp_opcode
);
565 opc
= (struct m68hc11_opcode_def
*)
566 xmalloc (num_opcodes
* sizeof (struct m68hc11_opcode_def
));
567 m68hc11_opcode_defs
= opc
--;
569 /* Insert unique names into hash table. The M6811 instruction set
570 has several identical opcode names that have different opcodes based
571 on the operands. This hash table then provides a quick index to
572 the first opcode with a particular name in the opcode table. */
573 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
577 if (strcmp (prev_name
, opcodes
->name
))
579 prev_name
= (char *) opcodes
->name
;
583 opc
->min_operands
= 100;
584 opc
->max_operands
= 0;
586 opc
->opcode
= opcodes
;
588 hash_insert (m68hc11_hash
, opcodes
->name
, (char *) opc
);
591 opc
->format
|= opcodes
->format
;
593 /* See how many operands this opcode needs. */
595 if (opcodes
->format
& M6811_OP_MASK
)
597 if (opcodes
->format
& M6811_OP_BITMASK
)
599 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
601 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
604 if (expect
< opc
->min_operands
)
605 opc
->min_operands
= expect
;
606 if (expect
> opc
->max_operands
)
607 opc
->max_operands
= expect
;
610 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
612 if (flag_print_opcodes
)
614 print_opcode_list ();
620 m68hc11_init_after_args ()
627 /* Return a string that represents the operand format for the instruction.
628 When example is true, this generates an example of operand. This is used
629 to give an example and also to generate a test. */
631 print_opcode_format (opcode
, example
)
632 struct m68hc11_opcode
*opcode
;
635 static char buf
[128];
636 int format
= opcode
->format
;
641 if (format
& M6811_OP_IMM8
)
644 sprintf (p
, "#%d", rand () & 0x0FF);
646 strcpy (p
, _("#<imm8>"));
650 if (format
& M6811_OP_IMM16
)
653 sprintf (p
, "#%d", rand () & 0x0FFFF);
655 strcpy (p
, _("#<imm16>"));
659 if (format
& M6811_OP_IX
)
662 sprintf (p
, "%d,X", rand () & 0x0FF);
664 strcpy (p
, _("<imm8>,X"));
668 if (format
& M6811_OP_IY
)
671 sprintf (p
, "%d,X", rand () & 0x0FF);
673 strcpy (p
, _("<imm8>,X"));
677 if (format
& M6812_OP_IDX
)
680 sprintf (p
, "%d,X", rand () & 0x0FF);
686 if (format
& M6811_OP_DIRECT
)
689 sprintf (p
, "*Z%d", rand () & 0x0FF);
691 strcpy (p
, _("*<abs8>"));
695 if (format
& M6811_OP_BITMASK
)
701 sprintf (p
, "#$%02x", rand () & 0x0FF);
703 strcpy (p
, _("#<mask>"));
706 if (format
& M6811_OP_JUMP_REL
)
710 if (format
& M6811_OP_IND16
)
713 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
715 strcpy (p
, _("<abs>"));
720 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
724 if (format
& M6811_OP_BITMASK
)
726 sprintf (p
, ".+%d", rand () & 0x7F);
730 sprintf (p
, "L%d", rand () & 0x0FF);
734 strcpy (p
, _("<label>"));
740 /* Prints the list of instructions with the possible operands. */
745 char *prev_name
= "";
746 struct m68hc11_opcode
*opcodes
;
747 int example
= flag_print_opcodes
== 2;
751 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
755 opcodes
= m68hc11_sorted_opcodes
;
757 /* Walk the list sorted on names (by md_begin). We only report
758 one instruction per line, and we collect the different operand
760 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
762 char *fmt
= print_opcode_format (opcodes
, example
);
766 printf ("L%d:\t", i
);
767 printf ("%s %s\n", opcodes
->name
, fmt
);
771 if (strcmp (prev_name
, opcodes
->name
))
776 printf ("%-5.5s ", opcodes
->name
);
777 prev_name
= (char *) opcodes
->name
;
780 printf (" [%s]", fmt
);
787 /* Print the instruction format. This operation is called when some
788 instruction is not correct. Instruction format is printed as an
791 print_insn_format (name
)
794 struct m68hc11_opcode_def
*opc
;
795 struct m68hc11_opcode
*opcode
;
798 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
801 as_bad (_("Instruction `%s' is not recognized."), name
);
804 opcode
= opc
->opcode
;
806 as_bad (_("Instruction formats for `%s':"), name
);
811 fmt
= print_opcode_format (opcode
, 0, 0);
812 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
817 while (strcmp (opcode
->name
, name
) == 0);
821 /* Analysis of 68HC11 and 68HC12 operands. */
823 /* reg_name_search() finds the register number given its name.
824 Returns the register number or REG_NONE on failure. */
826 reg_name_search (name
)
829 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
831 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
833 if (strcasecmp (name
, "a") == 0)
835 if (strcasecmp (name
, "b") == 0)
837 if (strcasecmp (name
, "d") == 0)
839 if (strcasecmp (name
, "sp") == 0)
841 if (strcasecmp (name
, "pc") == 0)
843 if (strcasecmp (name
, "ccr") == 0)
853 while (*p
== ' ' || *p
== '\t')
859 /* register_name() checks the string at input_line_pointer
860 to see if it is a valid register name. */
864 register_id reg_number
;
865 char c
, *p
= input_line_pointer
;
867 if (!is_name_beginner (*p
++))
870 while (is_part_of_name (*p
++))
877 /* look to see if it's in the register table. */
878 reg_number
= reg_name_search (input_line_pointer
);
879 if (reg_number
!= REG_NONE
)
884 input_line_pointer
= p
;
893 /* get_operands parses a string of operands and returns
894 an array of expressions.
896 Operand mode[0] mode[1] exp[0] exp[1]
897 #n M6811_OP_IMM16 - O_*
898 *<exp> M6811_OP_DIRECT - O_*
899 .{+-}<exp> M6811_OP_JUMP_REL - O_*
900 <exp> M6811_OP_IND16 - O_*
901 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
902 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
903 n,+r M6812_PRE_INC " "
904 n,r- M6812_POST_DEC " "
905 n,r+ M6812_POST_INC " "
906 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
907 [D,r] M6811_OP_IDX_2 M6812_OP_REG O_register O_register
908 [n,r] M6811_OP_IDX_1 M6812_OP_REG O_constant O_register
913 get_operand (oper
, which
, opmode
)
918 char *p
= input_line_pointer
;
922 oper
->exp
.X_op
= O_absent
;
923 oper
->reg1
= REG_NONE
;
924 oper
->reg2
= REG_NONE
;
925 mode
= M6811_OP_NONE
;
929 if (*p
== 0 || *p
== '\n' || *p
== '\r')
931 input_line_pointer
= p
;
935 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
937 mode
= M6811_OP_DIRECT
;
942 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
944 as_bad (_("Immediate operand is not allowed for operand %d."),
949 mode
= M6811_OP_IMM16
;
951 if (strncmp (p
, "%hi", 3) == 0)
954 mode
|= M6811_OP_HIGH_ADDR
;
956 else if (strncmp (p
, "%lo", 3) == 0)
959 mode
|= M6811_OP_LOW_ADDR
;
962 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
965 mode
= M6811_OP_JUMP_REL
;
969 if (current_architecture
& cpu6811
)
970 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
973 mode
= M6812_OP_IDX_2
;
976 else if (*p
== ',') /* Special handling of ,x and ,y. */
979 input_line_pointer
= p
;
981 reg
= register_name ();
985 oper
->exp
.X_op
= O_constant
;
986 oper
->exp
.X_add_number
= 0;
987 oper
->mode
= M6812_OP_IDX
;
990 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
993 input_line_pointer
= p
;
995 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_IDX_2
)
996 reg
= register_name ();
1000 if (reg
!= REG_NONE
)
1002 p
= skip_whites (input_line_pointer
);
1003 if (*p
== ']' && mode
== M6812_OP_IDX_2
)
1006 (_("Missing second register or offset for indexed-indirect mode."));
1011 oper
->mode
= mode
| M6812_OP_REG
;
1014 if (mode
== M6812_OP_IDX_2
)
1016 as_bad (_("Missing second register for indexed-indirect mode."));
1023 input_line_pointer
= p
;
1024 reg
= register_name ();
1025 if (reg
!= REG_NONE
)
1027 p
= skip_whites (input_line_pointer
);
1028 if (mode
== M6812_OP_IDX_2
)
1032 as_bad (_("Missing `]' to close indexed-indirect mode."));
1037 input_line_pointer
= p
;
1045 /* In MRI mode, isolate the operand because we can't distinguish
1046 operands from comments. */
1051 p
= skip_whites (p
);
1052 while (*p
&& *p
!= ' ' && *p
!= '\t')
1061 /* Parse as an expression. */
1062 expression (&oper
->exp
);
1071 expression (&oper
->exp
);
1074 if (oper
->exp
.X_op
== O_illegal
)
1076 as_bad (_("Illegal operand."));
1079 else if (oper
->exp
.X_op
== O_absent
)
1081 as_bad (_("Missing operand."));
1085 p
= input_line_pointer
;
1087 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1088 || mode
== M6812_OP_IDX_2
)
1090 p
= skip_whites (input_line_pointer
);
1096 /* 68HC12 pre increment or decrement. */
1097 if (mode
== M6811_OP_NONE
)
1101 mode
= M6812_PRE_DEC
;
1103 if (current_architecture
& cpu6811
)
1104 as_bad (_("Pre-decrement mode is not valid for 68HC11"));
1108 mode
= M6812_PRE_INC
;
1110 if (current_architecture
& cpu6811
)
1111 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1113 p
= skip_whites (p
);
1115 input_line_pointer
= p
;
1116 reg
= register_name ();
1119 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1120 && reg
!= REG_X
&& reg
!= REG_Y
1121 && reg
!= REG_PC
&& reg
!= REG_SP
)
1124 input_line_pointer
= p
;
1127 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1128 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1130 as_bad (_("Wrong register in register indirect mode."));
1133 if (mode
== M6812_OP_IDX_2
)
1135 p
= skip_whites (input_line_pointer
);
1138 as_bad (_("Missing `]' to close register indirect operand."));
1141 input_line_pointer
= p
;
1143 if (reg
!= REG_NONE
)
1146 if (mode
== M6811_OP_NONE
)
1148 p
= input_line_pointer
;
1151 mode
= M6812_POST_DEC
;
1153 if (current_architecture
& cpu6811
)
1155 (_("Post-decrement mode is not valid for 68HC11."));
1159 mode
= M6812_POST_INC
;
1161 if (current_architecture
& cpu6811
)
1163 (_("Post-increment mode is not valid for 68HC11."));
1166 mode
= M6812_OP_IDX
;
1168 input_line_pointer
= p
;
1171 mode
|= M6812_OP_IDX
;
1178 if (mode
== M6812_OP_D_IDX_2
)
1180 as_bad (_("Invalid indexed indirect mode."));
1185 /* If the mode is not known until now, this is either a label
1186 or an indirect address. */
1187 if (mode
== M6811_OP_NONE
)
1189 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1192 p
= input_line_pointer
;
1193 while (*p
== ' ' || *p
== '\t')
1195 input_line_pointer
= p
;
1201 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1202 | M6812_POST_INC | M6812_POST_DEC)
1204 /* Checks that the number 'num' fits for a given mode. */
1206 check_range (num
, mode
)
1210 /* Auto increment and decrement are ok for [-8..8] without 0. */
1211 if (mode
& M6812_AUTO_INC_DEC
)
1213 return (num
!= 0 && num
<= 8 && num
>= -8);
1216 /* The 68HC12 supports 5, 9 and 16-bits offsets. */
1217 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1219 mode
= M6811_OP_IND16
;
1222 if (mode
& M6812_OP_JUMP_REL16
)
1223 mode
= M6811_OP_IND16
;
1229 case M6811_OP_DIRECT
:
1230 return (num
>= 0 && num
<= 255) ? 1 : 0;
1232 case M6811_OP_BITMASK
:
1234 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1237 case M6811_OP_JUMP_REL
:
1238 return (num
>= -128 && num
<= 127) ? 1 : 0;
1240 case M6811_OP_IND16
:
1241 case M6811_OP_IMM16
:
1242 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1245 case M6812_OP_IBCC_MARKER
:
1246 case M6812_OP_TBCC_MARKER
:
1247 case M6812_OP_DBCC_MARKER
:
1248 return (num
>= -256 && num
<= 255) ? 1 : 0;
1250 case M6812_OP_TRAP_ID
:
1251 return ((num
>= 0x30 && num
<= 0x39)
1252 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1260 /* Gas fixup generation. */
1262 /* Put a 1 byte expression described by 'oper'. If this expression contains
1263 unresolved symbols, generate an 8-bit fixup. */
1265 fixup8 (oper
, mode
, opmode
)
1274 if (oper
->X_op
== O_constant
)
1276 if (mode
& M6812_OP_TRAP_ID
1277 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1279 static char trap_id_warn_once
= 0;
1281 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1282 if (trap_id_warn_once
== 0)
1284 trap_id_warn_once
= 1;
1285 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1289 if (!(mode
& M6812_OP_TRAP_ID
)
1290 && !check_range (oper
->X_add_number
, mode
))
1292 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1294 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1296 else if (oper
->X_op
!= O_register
)
1298 if (mode
& M6812_OP_TRAP_ID
)
1299 as_bad (_("The trap id must be a constant."));
1301 if (mode
== M6811_OP_JUMP_REL
)
1305 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1306 oper
, true, BFD_RELOC_8_PCREL
);
1307 fixp
->fx_pcrel_adjust
= 1;
1311 /* Now create an 8-bit fixup. If there was some %hi or %lo
1312 modifier, generate the reloc accordingly. */
1313 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1315 ((opmode
& M6811_OP_HIGH_ADDR
)
1316 ? BFD_RELOC_M68HC11_HI8
1317 : ((opmode
& M6811_OP_LOW_ADDR
)
1318 ? BFD_RELOC_M68HC11_LO8
: BFD_RELOC_8
)));
1320 number_to_chars_bigendian (f
, 0, 1);
1324 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1328 /* Put a 2 bytes expression described by 'oper'. If this expression contains
1329 unresolved symbols, generate a 16-bit fixup. */
1331 fixup16 (oper
, mode
, opmode
)
1334 int opmode ATTRIBUTE_UNUSED
;
1340 if (oper
->X_op
== O_constant
)
1342 if (!check_range (oper
->X_add_number
, mode
))
1344 as_bad (_("Operand out of 16-bit range: `%ld'."),
1345 oper
->X_add_number
);
1347 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1349 else if (oper
->X_op
!= O_register
)
1353 /* Now create a 16-bit fixup. */
1354 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1356 (mode
& M6812_OP_JUMP_REL16
? true : false),
1357 (mode
& M6812_OP_JUMP_REL16
1358 ? BFD_RELOC_16_PCREL
: BFD_RELOC_16
));
1359 number_to_chars_bigendian (f
, 0, 2);
1360 if (mode
& M6812_OP_JUMP_REL16
)
1361 fixp
->fx_pcrel_adjust
= 2;
1365 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1370 /* 68HC11 and 68HC12 code generation. */
1372 /* Translate the short branch/bsr instruction into a long branch. */
1373 static unsigned char
1374 convert_branch (code
)
1377 if (IS_OPCODE (code
, M6812_BSR
))
1379 else if (IS_OPCODE (code
, M6811_BSR
))
1381 else if (IS_OPCODE (code
, M6811_BRA
))
1382 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1384 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1386 /* Keep gcc happy. */
1390 /* Start a new insn that contains at least 'size' bytes. Record the
1391 line information of that insn in the dwarf2 debug sections. */
1393 m68hc11_new_insn (size
)
1398 f
= frag_more (size
);
1400 /* Emit line number information in dwarf2 debug sections. */
1401 if (debug_type
== DEBUG_DWARF2
)
1405 dwarf2_where (&debug_line
);
1406 addr
= frag_now
->fr_address
+ frag_now_fix () - size
;
1407 dwarf2_gen_line_info (addr
, &debug_line
);
1412 /* Builds a jump instruction (bra, bcc, bsr). */
1414 build_jump_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1415 struct m68hc11_opcode
*opcode
;
1425 /* The relative branch convertion is not supported for
1427 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1428 assert (nb_operands
== 1);
1429 assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1431 code
= opcode
->opcode
;
1434 n
= operands
[0].exp
.X_add_number
;
1436 /* Turn into a long branch:
1437 - when force long branch option (and not for jbcc pseudos),
1438 - when jbcc and the constant is out of -128..127 range,
1439 - when branch optimization is allowed and branch out of range. */
1440 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1441 || (operands
[0].exp
.X_op
== O_constant
1442 && (!check_range (n
, opcode
->format
) &&
1443 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1445 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1447 code
= convert_branch (code
);
1449 f
= m68hc11_new_insn (1);
1450 number_to_chars_bigendian (f
, code
, 1);
1452 else if (current_architecture
& cpu6812
)
1454 /* 68HC12: translate the bcc into a lbcc. */
1455 f
= m68hc11_new_insn (2);
1456 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1457 number_to_chars_bigendian (f
+ 1, code
, 1);
1458 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1459 M6812_OP_JUMP_REL16
);
1464 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1465 f
= m68hc11_new_insn (3);
1467 number_to_chars_bigendian (f
, code
, 1);
1468 number_to_chars_bigendian (f
+ 1, 3, 1);
1469 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1471 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1475 /* Branch with a constant that must fit in 8-bits. */
1476 if (operands
[0].exp
.X_op
== O_constant
)
1478 if (!check_range (n
, opcode
->format
))
1480 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1483 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1485 f
= m68hc11_new_insn (4);
1486 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1487 number_to_chars_bigendian (f
+ 1, code
, 1);
1488 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1492 f
= m68hc11_new_insn (2);
1493 number_to_chars_bigendian (f
, code
, 1);
1494 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1497 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1499 f
= m68hc11_new_insn (2);
1500 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1501 number_to_chars_bigendian (f
+ 1, code
, 1);
1502 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1508 /* Branch offset must fit in 8-bits, don't do some relax. */
1509 if (jmp_mode
== 0 && flag_fixed_branchs
)
1511 opcode
= m68hc11_new_insn (1);
1512 number_to_chars_bigendian (opcode
, code
, 1);
1513 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1516 /* bra/bsr made be changed into jmp/jsr. */
1517 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1519 opcode
= m68hc11_new_insn (2);
1520 number_to_chars_bigendian (opcode
, code
, 1);
1521 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1522 frag_var (rs_machine_dependent
, 1, 1,
1523 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1524 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1526 else if (current_architecture
& cpu6812
)
1528 opcode
= m68hc11_new_insn (2);
1529 number_to_chars_bigendian (opcode
, code
, 1);
1530 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1531 frag_var (rs_machine_dependent
, 2, 2,
1532 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1533 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1537 opcode
= m68hc11_new_insn (2);
1538 number_to_chars_bigendian (opcode
, code
, 1);
1539 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1540 frag_var (rs_machine_dependent
, 3, 3,
1541 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1542 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1547 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1549 build_dbranch_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1550 struct m68hc11_opcode
*opcode
;
1560 /* The relative branch convertion is not supported for
1562 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1563 assert (nb_operands
== 2);
1564 assert (operands
[0].reg1
!= REG_NONE
);
1566 code
= opcode
->opcode
& 0x0FF;
1569 f
= m68hc11_new_insn (1);
1570 number_to_chars_bigendian (f
, code
, 1);
1572 n
= operands
[1].exp
.X_add_number
;
1573 code
= operands
[0].reg1
;
1575 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
1576 || operands
[0].reg1
== REG_PC
)
1577 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1579 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
1581 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
1584 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
1587 /* Turn into a long branch:
1588 - when force long branch option (and not for jbcc pseudos),
1589 - when jdbcc and the constant is out of -256..255 range,
1590 - when branch optimization is allowed and branch out of range. */
1591 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1592 || (operands
[1].exp
.X_op
== O_constant
1593 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
1594 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1598 number_to_chars_bigendian (f
, code
, 1);
1599 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
1600 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1604 /* Branch with a constant that must fit in 9-bits. */
1605 if (operands
[1].exp
.X_op
== O_constant
)
1607 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
1609 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1618 number_to_chars_bigendian (f
, code
, 1);
1619 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1624 /* Branch offset must fit in 8-bits, don't do some relax. */
1625 if (jmp_mode
== 0 && flag_fixed_branchs
)
1627 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1633 number_to_chars_bigendian (f
, code
, 1);
1634 number_to_chars_bigendian (f
+ 1, 0, 1);
1635 frag_var (rs_machine_dependent
, 3, 3,
1636 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
1637 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
1642 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1644 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1646 build_indexed_byte (op
, format
, move_insn
)
1648 int format ATTRIBUTE_UNUSED
;
1651 unsigned char byte
= 0;
1656 val
= op
->exp
.X_add_number
;
1658 if (mode
& M6812_AUTO_INC_DEC
)
1661 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
1664 if (op
->exp
.X_op
== O_constant
)
1666 if (!check_range (val
, mode
))
1668 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1671 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
1672 byte
|= (val
- 1) & 0x07;
1674 byte
|= (8 - ((val
) & 7)) | 0x8;
1679 as_fatal (_("Expecting a register."));
1694 as_bad (_("Invalid register for post/pre increment."));
1699 number_to_chars_bigendian (f
, byte
, 1);
1703 if (mode
& M6812_OP_IDX
)
1724 as_bad (_("Invalid register."));
1727 if (op
->exp
.X_op
== O_constant
)
1729 if (!check_range (val
, M6812_OP_IDX
))
1731 as_bad (_("Offset out of 16-bit range: %ld."), val
);
1734 if (move_insn
&& !(val
>= -16 && val
<= 15))
1736 as_bad (_("Offset out of 5-bit range for movw/movb insn."));
1740 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_IDX_2
))
1745 number_to_chars_bigendian (f
, byte
, 1);
1748 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_IDX_2
))
1755 number_to_chars_bigendian (f
, byte
, 1);
1756 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
1762 if (mode
& M6812_OP_IDX_2
)
1768 number_to_chars_bigendian (f
, byte
, 1);
1769 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
1774 number_to_chars_bigendian (f
, byte
, 1);
1776 fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1777 &op->exp, false, BFD_RELOC_16); */
1778 frag_var (rs_machine_dependent
, 2, 2,
1779 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
1780 op
->exp
.X_add_symbol
, val
, f
);
1784 if (mode
& M6812_OP_REG
)
1786 if (mode
& M6812_OP_IDX_2
)
1788 if (op
->reg1
!= REG_D
)
1789 as_bad (_("Expecting register D for indexed indirect mode."));
1791 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
1808 as_bad (_("Invalid accumulator register."));
1833 as_bad (_("Invalid indexed register."));
1837 number_to_chars_bigendian (f
, byte
, 1);
1841 as_fatal (_("Addressing mode not implemented yet."));
1845 /* Assemble the 68HC12 register mode byte. */
1847 build_reg_mode (op
, format
)
1854 if (format
& M6812_OP_SEX_MARKER
1855 && op
->reg1
!= REG_A
&& op
->reg1
!= REG_B
&& op
->reg1
!= REG_CCR
)
1856 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
1857 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
1858 as_bad (_("Invalid source register."));
1860 if (format
& M6812_OP_SEX_MARKER
1861 && op
->reg2
!= REG_D
1862 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
1863 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
1864 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
1865 as_bad (_("Invalid destination register."));
1867 byte
= (op
->reg1
<< 4) | (op
->reg2
);
1868 if (format
& M6812_OP_EXG_MARKER
)
1872 number_to_chars_bigendian (f
, byte
, 1);
1876 /* build_insn takes a pointer to the opcode entry in the opcode table,
1877 the array of operand expressions and builds the correspding instruction.
1878 This operation only deals with non relative jumps insn (need special
1881 build_insn (opcode
, operands
, nb_operands
)
1882 struct m68hc11_opcode
*opcode
;
1884 int nb_operands ATTRIBUTE_UNUSED
;
1892 /* Put the page code instruction if there is one. */
1893 format
= opcode
->format
;
1894 if (format
& OP_EXTENDED
)
1898 f
= m68hc11_new_insn (2);
1899 if (format
& M6811_OP_PAGE2
)
1900 page_code
= M6811_OPCODE_PAGE2
;
1901 else if (format
& M6811_OP_PAGE3
)
1902 page_code
= M6811_OPCODE_PAGE3
;
1904 page_code
= M6811_OPCODE_PAGE4
;
1906 number_to_chars_bigendian (f
, page_code
, 1);
1911 f
= m68hc11_new_insn (1);
1913 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
1917 /* The 68HC12 movb and movw instructions are special. We have to handle
1918 them in a special way. */
1919 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
1922 if (format
& M6812_OP_IDX
)
1924 insn_size
+= build_indexed_byte (&operands
[0], format
, 1);
1926 format
&= ~M6812_OP_IDX
;
1928 if (format
& M6812_OP_IDX_P2
)
1930 insn_size
+= build_indexed_byte (&operands
[1], format
, 1);
1932 format
&= ~M6812_OP_IDX_P2
;
1936 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
1939 fixup8 (&operands
[i
].exp
,
1940 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
1944 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
1947 fixup16 (&operands
[i
].exp
, format
& (M6811_OP_IMM16
| M6811_OP_IND16
),
1951 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
1953 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
1954 as_bad (_("Invalid indexed register, expecting register X."));
1955 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
1956 as_bad (_("Invalid indexed register, expecting register Y."));
1959 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
1963 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
| M6812_OP_D_IDX
))
1965 insn_size
+= build_indexed_byte (&operands
[i
], format
, move_insn
);
1968 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
1970 insn_size
+= build_reg_mode (&operands
[i
], format
);
1973 if (format
& M6811_OP_BITMASK
)
1976 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
1979 if (format
& M6811_OP_JUMP_REL
)
1982 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
1985 else if (format
& M6812_OP_IND16_P2
)
1988 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
1993 /* Opcode identification and operand analysis. */
1995 /* find() gets a pointer to an entry in the opcode table. It must look at all
1996 opcodes with the same name and use the operands to choose the correct
1997 opcode. Returns the opcode pointer if there was a match and 0 if none. */
1998 static struct m68hc11_opcode
*
1999 find (opc
, operands
, nb_operands
)
2000 struct m68hc11_opcode_def
*opc
;
2005 struct m68hc11_opcode
*opcode
;
2006 struct m68hc11_opcode
*op_indirect
;
2009 opcode
= opc
->opcode
;
2011 /* Now search the opcode table table for one with operands
2012 that matches what we've got. We're only done if the operands matched so
2013 far AND there are no more to check. */
2014 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2016 int poss_indirect
= 0;
2017 long format
= opcode
->format
;
2021 if (opcode
->format
& M6811_OP_MASK
)
2023 if (opcode
->format
& M6811_OP_BITMASK
)
2025 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2027 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2030 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2032 int mode
= operands
[i
].mode
;
2034 if (mode
& M6811_OP_IMM16
)
2037 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2041 if (mode
== M6811_OP_DIRECT
)
2043 if (format
& M6811_OP_DIRECT
)
2046 /* If the operand is a page 0 operand, remember a
2047 possible <abs-16> addressing mode. We mark
2048 this and continue to check other operands. */
2049 if (format
& M6811_OP_IND16
2050 && flag_strict_direct_addressing
&& op_indirect
== 0)
2057 if (mode
& M6811_OP_IND16
)
2059 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2061 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2063 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2066 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2068 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2071 if (mode
& M6812_OP_REG
)
2073 if (i
== 0 && format
& M6812_OP_REG
2074 && operands
[i
].reg2
== REG_NONE
)
2076 if (i
== 0 && format
& M6812_OP_REG
2077 && format
& M6812_OP_REG_2
&& operands
[i
].reg2
!= REG_NONE
)
2081 if (i
== 0 && format
& M6812_OP_D_IDX
)
2083 if (i
== 0 && (format
& M6812_OP_IDX
)
2084 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2086 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2090 if (mode
& M6812_OP_IDX
)
2092 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2094 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2097 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2098 && (operands
[i
].reg1
== REG_X
2099 || operands
[i
].reg1
== REG_Y
2100 || operands
[i
].reg1
== REG_SP
2101 || operands
[i
].reg1
== REG_PC
))
2103 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2106 if (mode
& M6812_AUTO_INC_DEC
)
2109 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2112 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2117 match
= i
== nb_operands
;
2119 /* Operands are ok but an operand uses page 0 addressing mode
2120 while the insn supports abs-16 mode. Keep a reference to this
2121 insns in case there is no insn supporting page 0 addressing. */
2122 if (match
&& poss_indirect
)
2124 op_indirect
= opcode
;
2131 /* Page 0 addressing is used but not supported by any insn.
2132 If absolute addresses are supported, we use that insn. */
2133 if (match
== 0 && op_indirect
)
2135 opcode
= op_indirect
;
2148 /* Find the real opcode and its associated operands. We use a progressive
2149 approach here. On entry, 'opc' points to the first opcode in the
2150 table that matches the opcode name in the source line. We try to
2151 isolate an operand, find a possible match in the opcode table.
2152 We isolate another operand if no match were found. The table 'operands'
2153 is filled while operands are recognized.
2155 Returns the opcode pointer that matches the opcode name in the
2156 source line and the associated operands. */
2157 static struct m68hc11_opcode
*
2158 find_opcode (opc
, operands
, nb_operands
)
2159 struct m68hc11_opcode_def
*opc
;
2163 struct m68hc11_opcode
*opcode
;
2166 if (opc
->max_operands
== 0)
2172 for (i
= 0; i
< opc
->max_operands
;)
2176 result
= get_operand (&operands
[i
], i
, opc
->format
);
2182 /* Special case where the bitmask of the bclr/brclr
2183 instructions is not introduced by #.
2184 Example: bclr 3,x $80. */
2185 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2186 && (operands
[i
].mode
& M6811_OP_IND16
))
2188 operands
[i
].mode
= M6811_OP_IMM16
;
2193 if (i
>= opc
->min_operands
)
2195 opcode
= find (opc
, operands
, i
);
2202 if (*input_line_pointer
== ',')
2203 input_line_pointer
++;
2208 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2209 | M6812_OP_DBCC_MARKER \
2210 | M6812_OP_IBCC_MARKER)
2213 /* Gas line assembler entry point. */
2215 /* This is the main entry point for the machine-dependent assembler. str
2216 points to a machine-dependent instruction. This function is supposed to
2217 emit the frags/bytes it assembles to. */
2222 struct m68hc11_opcode_def
*opc
;
2223 struct m68hc11_opcode
*opcode
;
2225 unsigned char *op_start
, *save
;
2226 unsigned char *op_end
;
2229 operand operands
[M6811_MAX_OPERANDS
];
2231 int branch_optimize
= 0;
2234 /* Drop leading whitespace */
2238 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2239 lower case (the opcode table only has lower case op-codes). */
2240 for (op_start
= op_end
= (unsigned char *) (str
);
2241 *op_end
&& nlen
< 20 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2244 name
[nlen
] = tolower (op_start
[nlen
]);
2251 as_bad (_("No instruction or missing opcode."));
2255 /* Find the opcode definition given its name. */
2256 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
2258 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2259 pseudo insns for relative branch. For these branchs, we always
2260 optimize them (turned into absolute branchs) even if --short-branchs
2262 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
2264 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, &name
[1]);
2266 && (!(opc
->format
& M6811_OP_JUMP_REL
)
2267 || (opc
->format
& M6811_OP_BITMASK
)))
2270 branch_optimize
= 1;
2273 /* The following test should probably be removed. This is not conform
2274 to Motorola assembler specs. */
2275 if (opc
== NULL
&& flag_mri
)
2277 if (*op_end
== ' ' || *op_end
== '\t')
2279 while (*op_end
== ' ' || *op_end
== '\t')
2284 (is_end_of_line
[op_end
[1]]
2285 || op_end
[1] == ' ' || op_end
[1] == '\t'
2286 || !isalnum (op_end
[1])))
2287 && (*op_end
== 'a' || *op_end
== 'b'
2288 || *op_end
== 'A' || *op_end
== 'B'
2289 || *op_end
== 'd' || *op_end
== 'D'
2290 || *op_end
== 'x' || *op_end
== 'X'
2291 || *op_end
== 'y' || *op_end
== 'Y'))
2293 name
[nlen
++] = tolower (*op_end
++);
2295 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
,
2301 /* Identify a possible instruction alias. There are some on the
2302 68HC12 to emulate a fiew 68HC11 instructions. */
2303 if (opc
== NULL
&& (current_architecture
& cpu6812
))
2307 for (i
= 0; i
< m68hc12_num_alias
; i
++)
2308 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
2314 if (opc
== NULL
&& alias_id
< 0)
2316 as_bad (_("Opcode `%s' is not recognized."), name
);
2319 save
= input_line_pointer
;
2320 input_line_pointer
= op_end
;
2325 opcode
= find_opcode (opc
, operands
, &nb_operands
);
2330 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
2332 char *p
= input_line_pointer
;
2334 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
2337 if (*p
!= '\n' && *p
)
2338 as_bad (_("Garbage at end of instruction: `%s'."), p
);
2341 input_line_pointer
= save
;
2345 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
2347 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
2348 if (m68hc12_alias
[alias_id
].size
> 1)
2349 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
2354 /* Opcode is known but does not have valid operands. Print out the
2355 syntax for this opcode. */
2358 if (flag_print_insn_syntax
)
2359 print_insn_format (name
);
2361 as_bad (_("Invalid operand for `%s'"), name
);
2365 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2366 relative and must be in the range -256..255 (9-bits). */
2367 if ((opcode
->format
& M6812_XBCC_MARKER
)
2368 && (opcode
->format
& M6811_OP_JUMP_REL
))
2369 build_dbranch_insn (opcode
, operands
, nb_operands
);
2371 /* Relative jumps instructions are taken care of separately. We have to make
2372 sure that the relative branch is within the range -128..127. If it's out
2373 of range, the instructions are changed into absolute instructions.
2374 This is not supported for the brset and brclr instructions. */
2375 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2376 && !(opcode
->format
& M6811_OP_BITMASK
))
2377 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2379 build_insn (opcode
, operands
, nb_operands
);
2383 /* Relocation, relaxation and frag conversions. */
2386 md_pcrel_from_section (fixp
, sec
)
2391 if (fixp
->fx_addsy
!= (symbolS
*) NULL
2392 && (!S_IS_DEFINED (fixp
->fx_addsy
)
2393 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
2396 adjust
= fixp
->fx_pcrel_adjust
;
2397 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
+ adjust
;
2400 /* If while processing a fixup, a reloc really needs to be created
2401 then it is done here. */
2403 tc_gen_reloc (section
, fixp
)
2409 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2410 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2411 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2412 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2413 if (fixp
->fx_r_type
== 0)
2414 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
2416 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2417 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
2419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2420 _("Relocation %d is not supported by object file format."),
2421 (int) fixp
->fx_r_type
);
2425 if (!fixp
->fx_pcrel
)
2426 reloc
->addend
= fixp
->fx_addnumber
;
2428 reloc
->addend
= (section
->vma
2429 + (fixp
->fx_pcrel_adjust
== 64
2430 ? -1 : fixp
->fx_pcrel_adjust
)
2431 + fixp
->fx_addnumber
2432 + md_pcrel_from_section (fixp
, section
));
2437 md_convert_frag (abfd
, sec
, fragP
)
2438 bfd
*abfd ATTRIBUTE_UNUSED
;
2439 asection
*sec ATTRIBUTE_UNUSED
;
2444 char *buffer_address
= fragP
->fr_literal
;
2446 /* Address in object code of the displacement. */
2447 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
2449 buffer_address
+= fragP
->fr_fix
;
2451 /* The displacement of the address, from current location. */
2452 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
2453 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
2454 disp
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
2456 switch (fragP
->fr_subtype
)
2458 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
2459 fragP
->fr_opcode
[1] = disp
;
2462 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
2463 /* This relax is only for bsr and bra. */
2464 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2465 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2466 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2468 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
2470 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
2471 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2475 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
2476 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
2477 fragP
->fr_opcode
[1] = disp
;
2480 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
2481 /* Invert branch. */
2482 fragP
->fr_opcode
[0] ^= 1;
2483 fragP
->fr_opcode
[1] = 3; /* Branch offset */
2484 buffer_address
[0] = M6811_JMP
;
2485 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2486 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2490 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
2491 /* Translate branch into a long branch. */
2492 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
2493 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
2495 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2496 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
2497 BFD_RELOC_16_PCREL
);
2498 fixp
->fx_pcrel_adjust
= 2;
2502 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
2503 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 5;
2504 fragP
->fr_opcode
[0] |= disp
& 0x1f;
2507 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
2508 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2509 fragP
->fr_opcode
[0] |= 0xE0;
2510 fix_new (fragP
, fragP
->fr_fix
+ 1, 1,
2511 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_8
);
2515 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
2516 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2517 fragP
->fr_opcode
[0] |= 0xE2;
2518 fix_new (fragP
, fragP
->fr_fix
, 2,
2519 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2523 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
2525 fragP
->fr_opcode
[0] |= 0x10;
2527 fragP
->fr_opcode
[1] = disp
& 0x0FF;
2530 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
2531 /* Invert branch. */
2532 fragP
->fr_opcode
[0] ^= 0x20;
2533 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2534 buffer_address
[0] = M6812_JMP
;
2535 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2536 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2545 /* Force truly undefined symbols to their maximum size, and generally set up
2546 the frag list to be relaxed. */
2548 md_estimate_size_before_relax (fragP
, segment
)
2553 char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
2555 old_fr_fix
= fragP
->fr_fix
;
2557 switch (fragP
->fr_subtype
)
2559 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
):
2561 /* This relax is only for bsr and bra. */
2562 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2563 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2564 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2566 /* A relaxable case. */
2567 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
2569 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
2573 if (flag_fixed_branchs
)
2574 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
2575 _("bra or bsr with undefined symbol."));
2577 /* The symbol is undefined or in a separate section. Turn bra into a
2578 jmp and bsr into a jsr. The insn becomes 3 bytes long (instead of
2579 2). A fixup is necessary for the unresolved symbol address. */
2581 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
2584 fix_new (fragP
, old_fr_fix
- 1, 2, fragP
->fr_symbol
,
2585 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2590 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
):
2591 assert (current_architecture
& cpu6811
);
2593 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
2595 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
2600 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
2601 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes) */
2603 /* Don't use fr_opcode[2] because this may be
2604 in a different frag. */
2605 buffer_address
[0] = M6811_JMP
;
2608 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2609 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2615 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
):
2616 assert (current_architecture
& cpu6812
);
2618 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
2620 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
2625 /* Switch the indexed operation to 16-bit mode. */
2626 if ((fragP
->fr_opcode
[1] & 0x21) == 0x20)
2627 fragP
->fr_opcode
[1] = (fragP
->fr_opcode
[1] >> 3) | 0xc0 | 0x02;
2630 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2631 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2637 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
):
2638 assert (current_architecture
& cpu6812
);
2640 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
2642 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
2646 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
2647 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
2649 /* Don't use fr_opcode[2] because this may be
2650 in a different frag. */
2651 buffer_address
[0] = M6812_JMP
;
2654 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2655 fragP
->fr_offset
, 0, BFD_RELOC_16
);
2661 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
):
2662 assert (current_architecture
& cpu6812
);
2664 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
2666 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
2671 /* Translate into a lbcc branch. */
2672 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
2673 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
2675 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
2676 fragP
->fr_offset
, 0, BFD_RELOC_16_PCREL
);
2683 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
2686 return (fragP
->fr_fix
- old_fr_fix
);
2690 md_apply_fix (fixp
, valuep
)
2698 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
2703 else if (fixp
->fx_pcrel
)
2709 value
= fixp
->fx_offset
;
2710 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
2712 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
2714 value
-= S_GET_VALUE (fixp
->fx_subsy
);
2718 /* We don't actually support subtracting a symbol. */
2719 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2720 _("Expression too complex."));
2725 op_type
= fixp
->fx_r_type
;
2727 /* Patch the instruction with the resolved operand. Elf relocation
2728 info will also be generated to take care of linker/loader fixups.
2729 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
2730 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
2731 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
2732 because it's either resolved or turned out into non-relative insns (see
2733 relax table, bcc, bra, bsr transformations)
2735 The BFD_RELOC_32 is necessary for the support of --gstabs. */
2736 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
2738 switch (fixp
->fx_r_type
)
2741 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
2745 case BFD_RELOC_16_PCREL
:
2746 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
2747 if (value
< -65537 || value
> 65535)
2748 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2749 _("Value out of 16-bit range."));
2752 case BFD_RELOC_M68HC11_HI8
:
2756 case BFD_RELOC_M68HC11_LO8
:
2758 /*bfd_putb8 ((bfd_vma) value, (unsigned char *) where); */
2759 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
2762 case BFD_RELOC_8_PCREL
:
2763 /*bfd_putb8 ((bfd_vma) value, (unsigned char *) where); */
2764 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
2766 if (value
< -128 || value
> 127)
2767 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2768 _("Value %ld too large for 8-bit PC-relative branch."),
2772 case BFD_RELOC_M68HC11_3B
:
2773 if (value
<= 0 || value
> 8)
2774 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2775 _("Auto increment/decrement offset '%ld' is out of range."),
2782 where
[0] = where
[0] | (value
& 0x07);
2786 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
2787 fixp
->fx_line
, fixp
->fx_r_type
);
2799 m68hc11_end_of_source ()
2802 subsegT saved_subseg
;
2805 long total_size
= 0;
2807 if (debug_type
!= DEBUG_DWARF2
)
2812 saved_seg
= now_seg
;
2813 saved_subseg
= now_subseg
;
2815 debug_info
= subseg_new (".debug_info", 0);
2816 bfd_set_section_flags (stdoutput
, debug_info
, SEC_READONLY
);
2817 subseg_set (debug_info
, 0);
2821 # define STUFF(val,size) md_number_to_chars (p, val, size); p += size;
2822 STUFF (total_size
, 4); /* Length of compilation unit. */
2823 STUFF (2, 2); /* Dwarf version */
2825 STUFF (2, 1); /* Pointer size */
2826 STUFF (1, 1); /* Compile unit */
2829 now_subseg
= saved_subseg
;
2830 now_seg
= saved_seg
;