1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs
; /* -l option. */
80 static int flag_long_jumps
; /* -S option. */
81 static int flag_keep_pcrel
; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
86 int flag_reg_prefix_optional
;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen
;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum
= COP1
;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd
;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick
= 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32
= 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline
;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line
*next
;
127 /* The list of labels. */
129 static struct label_line
*labels
;
131 /* The current label. */
133 static struct label_line
*current_label
;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn
;
144 const char *m_operands
;
145 unsigned long m_opcode
;
149 struct m68k_incant
*m_next
;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl
[] = { 0 };
156 static const enum m68k_register m68010_ctrl
[] = {
160 static const enum m68k_register m68020_ctrl
[] = {
161 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
164 static const enum m68k_register m68040_ctrl
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
166 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
169 static const enum m68k_register m68060_ctrl
[] = {
170 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
171 USP
, VBR
, URP
, SRP
, PCR
,
174 static const enum m68k_register mcf_ctrl
[] = {
175 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
176 RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
,
179 static const enum m68k_register mcf51qe_ctrl
[] = {
183 static const enum m68k_register mcf5206_ctrl
[] = {
184 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
187 static const enum m68k_register mcf5208_ctrl
[] = {
188 CACR
, ACR0
, ACR1
, VBR
, RAMBAR
, RAMBAR1
,
191 static const enum m68k_register mcf5210a_ctrl
[] = {
192 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, RAMBAR1
, MBAR
,
195 static const enum m68k_register mcf5213_ctrl
[] = {
196 VBR
, RAMBAR
, RAMBAR1
, FLASHBAR
,
199 static const enum m68k_register mcf5216_ctrl
[] = {
200 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
203 static const enum m68k_register mcf52223_ctrl
[] = {
204 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
207 static const enum m68k_register mcf52235_ctrl
[] = {
208 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
211 static const enum m68k_register mcf5225_ctrl
[] = {
212 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
, RAMBAR1
,
215 static const enum m68k_register mcf5235_ctrl
[] = {
216 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
219 static const enum m68k_register mcf5249_ctrl
[] = {
220 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
223 static const enum m68k_register mcf5250_ctrl
[] = {
227 static const enum m68k_register mcf5253_ctrl
[] = {
228 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
231 static const enum m68k_register mcf5271_ctrl
[] = {
232 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
235 static const enum m68k_register mcf5272_ctrl
[] = {
236 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR_ALT
, RAMBAR0
, MBAR
,
239 static const enum m68k_register mcf5275_ctrl
[] = {
240 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
243 static const enum m68k_register mcf5282_ctrl
[] = {
244 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
247 static const enum m68k_register mcf5307_ctrl
[] = {
248 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
251 static const enum m68k_register mcf5329_ctrl
[] = {
252 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
255 static const enum m68k_register mcf5373_ctrl
[] = {
256 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
259 static const enum m68k_register mcfv4e_ctrl
[] = {
260 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
261 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
263 MPCR
/* Multiprocessor Control register */,
264 EDRAMBAR
/* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
267 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
269 TC
/* ASID */, BUSCR
/* MMUBAR */,
270 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
271 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
272 ROMBAR
/* ROMBAR0 */, RAMBAR
/* RAMBAR1 */,
275 static const enum m68k_register mcf5407_ctrl
[] = {
276 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
,
277 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
280 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
281 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
284 static const enum m68k_register mcf54455_ctrl
[] = {
285 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
286 VBR
, PC
, RAMBAR1
, MBAR
,
288 TC
/* ASID */, BUSCR
/* MMUBAR */,
289 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
290 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
293 static const enum m68k_register mcf5475_ctrl
[] = {
294 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
295 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
297 TC
/* ASID */, BUSCR
/* MMUBAR */,
298 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
299 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
302 static const enum m68k_register mcf5485_ctrl
[] = {
303 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
304 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
306 TC
/* ASID */, BUSCR
/* MMUBAR */,
307 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
308 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
311 static const enum m68k_register fido_ctrl
[] = {
312 SFC
, DFC
, USP
, VBR
, CAC
, MBB
,
315 #define cpu32_ctrl m68010_ctrl
317 static const enum m68k_register
*control_regs
;
319 /* Internal form of a 68020 instruction. */
323 const char *args
; /* List of opcode info. */
326 int numo
; /* Number of shorts in opcode. */
329 struct m68k_op operands
[6];
331 int nexp
; /* Number of exprs in use. */
332 struct m68k_exp exprs
[4];
334 int nfrag
; /* Number of frags we have to produce. */
337 int fragoff
; /* Where in the current opcode the frag ends. */
344 int nrel
; /* Num of reloc strucs in use. */
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
360 /* Whether this expression needs special pic relocation, and if
362 enum pic_relocation pic_reloc
;
365 reloc
[5]; /* Five is enough??? */
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
384 static struct m68k_it the_ins
; /* The instruction being assembled. */
386 #define op(ex) ((ex)->exp.X_op)
387 #define adds(ex) ((ex)->exp.X_add_symbol)
388 #define subs(ex) ((ex)->exp.X_op_symbol)
389 #define offs(ex) ((ex)->exp.X_add_number)
391 /* Macros for adding things to the m68k_it struct. */
392 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
394 /* Like addword, but goes BEFORE general operands. */
397 insop (int w
, const struct m68k_incant
*opcode
)
400 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
401 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
402 for (z
= 0; z
< the_ins
.nrel
; z
++)
403 the_ins
.reloc
[z
].n
+= 2;
404 for (z
= 0; z
< the_ins
.nfrag
; z
++)
405 the_ins
.fragb
[z
].fragoff
++;
406 the_ins
.opcode
[opcode
->m_codenum
] = w
;
410 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
413 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
415 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
416 ? the_ins
.numo
* 2 - 1
418 ? the_ins
.numo
* 2 + 1
419 : the_ins
.numo
* 2));
420 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
421 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
422 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
424 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
426 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
429 /* Cause an extra frag to be generated here, inserting up to 10 bytes
430 (that value is chosen in the frag_var call in md_assemble). TYPE
431 is the subtype of the frag to be generated; its primary type is
432 rs_machine_dependent.
434 The TYPE parameter is also used by md_convert_frag_1 and
435 md_estimate_size_before_relax. The appropriate type of fixup will
436 be emitted by md_convert_frag_1.
438 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
440 add_frag (symbolS
*add
, offsetT off
, int type
)
442 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
443 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
444 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
445 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
449 (op (ex) != O_constant && op (ex) != O_big)
451 static char *crack_operand (char *str
, struct m68k_op
*opP
);
452 static int get_num (struct m68k_exp
*exp
, int ok
);
453 static int reverse_16_bits (int in
);
454 static int reverse_8_bits (int in
);
455 static void install_gen_operand (int mode
, int val
);
456 static void install_operand (int mode
, int val
);
457 static void s_bss (int);
458 static void s_data1 (int);
459 static void s_data2 (int);
460 static void s_even (int);
461 static void s_proc (int);
462 static void s_chip (int);
463 static void s_fopt (int);
464 static void s_opt (int);
465 static void s_reg (int);
466 static void s_restore (int);
467 static void s_save (int);
468 static void s_mri_if (int);
469 static void s_mri_else (int);
470 static void s_mri_endi (int);
471 static void s_mri_break (int);
472 static void s_mri_next (int);
473 static void s_mri_for (int);
474 static void s_mri_endf (int);
475 static void s_mri_repeat (int);
476 static void s_mri_until (int);
477 static void s_mri_while (int);
478 static void s_mri_endw (int);
479 static void s_m68k_cpu (int);
480 static void s_m68k_arch (int);
484 unsigned long arch
; /* Architecture features. */
485 const enum m68k_register
*control_regs
; /* Control regs on chip */
486 const char *name
; /* Name */
487 int alias
; /* Alias for a cannonical name. If 1, then
488 succeeds canonical name, if -1 then
489 succeeds canonical name, if <-1 ||>1 this is a
490 deprecated name, and the next/previous name
494 /* We hold flags for features explicitly enabled and explicitly
496 static int current_architecture
;
497 static int not_current_architecture
;
498 static const struct m68k_cpu
*selected_arch
;
499 static const struct m68k_cpu
*selected_cpu
;
500 static int initialized
;
502 /* Architecture models. */
503 static const struct m68k_cpu m68k_archs
[] =
505 {m68000
, m68000_ctrl
, "68000", 0},
506 {m68010
, m68010_ctrl
, "68010", 0},
507 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
508 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
509 {m68040
, m68040_ctrl
, "68040", 0},
510 {m68060
, m68060_ctrl
, "68060", 0},
511 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
512 {fido_a
, fido_ctrl
, "fidoa", 0},
513 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
514 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
515 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
516 {mcfisa_a
|mcfhwdiv
|mcfisa_c
|mcfusp
, NULL
, "isac", 0},
517 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
518 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
522 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
524 static const struct m68k_cpu m68k_extensions
[] =
526 {m68851
, NULL
, "68851", -1},
527 {m68881
, NULL
, "68881", -1},
528 {m68881
, NULL
, "68882", -1},
530 {cfloat
|m68881
, NULL
, "float", 0},
532 {mcfhwdiv
, NULL
, "div", 1},
533 {mcfusp
, NULL
, "usp", 1},
534 {mcfmac
, NULL
, "mac", 1},
535 {mcfemac
, NULL
, "emac", 1},
541 static const struct m68k_cpu m68k_cpus
[] =
543 {m68000
, m68000_ctrl
, "68000", 0},
544 {m68000
, m68000_ctrl
, "68ec000", 1},
545 {m68000
, m68000_ctrl
, "68hc000", 1},
546 {m68000
, m68000_ctrl
, "68hc001", 1},
547 {m68000
, m68000_ctrl
, "68008", 1},
548 {m68000
, m68000_ctrl
, "68302", 1},
549 {m68000
, m68000_ctrl
, "68306", 1},
550 {m68000
, m68000_ctrl
, "68307", 1},
551 {m68000
, m68000_ctrl
, "68322", 1},
552 {m68000
, m68000_ctrl
, "68356", 1},
553 {m68010
, m68010_ctrl
, "68010", 0},
554 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
555 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
556 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
557 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
558 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
559 {m68040
, m68040_ctrl
, "68040", 0},
560 {m68040
, m68040_ctrl
, "68ec040", 1},
561 {m68060
, m68060_ctrl
, "68060", 0},
562 {m68060
, m68060_ctrl
, "68ec060", 1},
564 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
565 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
566 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
567 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
568 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
569 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
570 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
571 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
572 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
573 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
574 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
576 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51qe_ctrl
, "51qe", 0},
578 {mcfisa_a
, mcf_ctrl
, "5200", 0},
579 {mcfisa_a
, mcf_ctrl
, "5202", 1},
580 {mcfisa_a
, mcf_ctrl
, "5204", 1},
581 {mcfisa_a
, mcf5206_ctrl
, "5206", 1},
583 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206_ctrl
, "5206e", 0},
585 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
586 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
588 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
589 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
591 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
592 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
593 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
595 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
596 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
597 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
599 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52221", -1},
600 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52223", 0},
602 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
603 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
604 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
605 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
607 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
608 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
610 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
611 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
612 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
613 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
614 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
616 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
617 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
618 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5253_ctrl
, "5253", 0},
620 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
621 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
623 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
625 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
626 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
628 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
629 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
630 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
631 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
633 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307_ctrl
, "5307", 0},
635 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
636 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
637 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
638 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
640 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
641 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
642 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
644 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf5407_ctrl
, "5407",0},
646 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54450", -1},
647 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54451", -1},
648 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54452", -1},
649 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54453", -1},
650 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54454", -1},
651 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54455", 0},
653 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
654 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
655 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
656 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
657 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
658 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
659 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
661 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
662 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
663 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
664 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
665 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
666 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
667 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
669 {fido_a
, fido_ctrl
, "fidoa", 0},
670 {fido_a
, fido_ctrl
, "fido", 1},
675 static const struct m68k_cpu
*m68k_lookup_cpu
676 (const char *, const struct m68k_cpu
*, int, int *);
677 static int m68k_set_arch (const char *, int, int);
678 static int m68k_set_cpu (const char *, int, int);
679 static int m68k_set_extension (const char *, int, int);
680 static void m68k_init_arch (void);
682 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
683 architecture and we have a lot of relaxation modes. */
685 /* Macros used in the relaxation code. */
686 #define TAB(x,y) (((x) << 2) + (y))
687 #define TABTYPE(x) ((x) >> 2)
689 /* Relaxation states. */
695 /* Here are all the relaxation modes we support. First we can relax ordinary
696 branches. On 68020 and higher and on CPU32 all branch instructions take
697 three forms, so on these CPUs all branches always remain as such. When we
698 have to expand to the LONG form on a 68000, though, we substitute an
699 absolute jump instead. This is a direct replacement for unconditional
700 branches and a branch over a jump for conditional branches. However, if the
701 user requires PIC and disables this with --pcrel, we can only relax between
702 BYTE and SHORT forms, punting if that isn't enough. This gives us four
703 different relaxation modes for branches: */
705 #define BRANCHBWL 0 /* Branch byte, word, or long. */
706 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
707 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
708 #define BRANCHBW 3 /* Branch byte or word. */
710 /* We also relax coprocessor branches and DBcc's. All CPUs that support
711 coprocessor branches support them in word and long forms, so we have only
712 one relaxation mode for them. DBcc's are word only on all CPUs. We can
713 relax them to the LONG form with a branch-around sequence. This sequence
714 can use a long branch (if available) or an absolute jump (if acceptable).
715 This gives us two relaxation modes. If long branches are not available and
716 absolute jumps are not acceptable, we don't relax DBcc's. */
718 #define FBRANCH 4 /* Coprocessor branch. */
719 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
720 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
722 /* That's all for instruction relaxation. However, we also relax PC-relative
723 operands. Specifically, we have three operand relaxation modes. On the
724 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
725 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
726 two. Also PC+displacement+index operands in their simple form (with a non-
727 suppressed index without memory indirection) are supported on all CPUs, but
728 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
729 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
730 form of the PC+displacement+index operand. Finally, some absolute operands
731 can be relaxed down to 16-bit PC-relative. */
733 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
734 #define PCINDEX 8 /* PC + displacement + index. */
735 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
737 /* Note that calls to frag_var need to specify the maximum expansion
738 needed; this is currently 10 bytes for DBCC. */
741 How far Forward this mode will reach:
742 How far Backward this mode will reach:
743 How many bytes this mode will add to the size of the frag
744 Which mode to go to if the offset won't fit in this one
746 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
747 relax_typeS md_relax_table
[] =
749 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
750 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
754 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
755 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
759 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
760 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
764 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
769 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
774 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
775 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
779 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
784 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
785 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
789 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
790 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
794 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
795 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
800 /* These are the machine dependent pseudo-ops. These are included so
801 the assembler can work on the output from the SUN C compiler, which
804 /* This table describes all the machine specific pseudo-ops the assembler
805 has to support. The fields are:
806 pseudo-op name without dot
807 function to call to execute this pseudo-op
808 Integer arg to pass to the function. */
809 const pseudo_typeS md_pseudo_table
[] =
811 {"data1", s_data1
, 0},
812 {"data2", s_data2
, 0},
815 {"skip", s_space
, 0},
817 #if defined (TE_SUN3) || defined (OBJ_ELF)
818 {"align", s_align_bytes
, 0},
821 {"swbeg", s_ignore
, 0},
823 {"extend", float_cons
, 'x'},
824 {"ldouble", float_cons
, 'x'},
826 {"arch", s_m68k_arch
, 0},
827 {"cpu", s_m68k_cpu
, 0},
829 /* The following pseudo-ops are supported for MRI compatibility. */
831 {"comline", s_space
, 1},
833 {"mask2", s_ignore
, 0},
836 {"restore", s_restore
, 0},
840 {"if.b", s_mri_if
, 'b'},
841 {"if.w", s_mri_if
, 'w'},
842 {"if.l", s_mri_if
, 'l'},
843 {"else", s_mri_else
, 0},
844 {"else.s", s_mri_else
, 's'},
845 {"else.l", s_mri_else
, 'l'},
846 {"endi", s_mri_endi
, 0},
847 {"break", s_mri_break
, 0},
848 {"break.s", s_mri_break
, 's'},
849 {"break.l", s_mri_break
, 'l'},
850 {"next", s_mri_next
, 0},
851 {"next.s", s_mri_next
, 's'},
852 {"next.l", s_mri_next
, 'l'},
853 {"for", s_mri_for
, 0},
854 {"for.b", s_mri_for
, 'b'},
855 {"for.w", s_mri_for
, 'w'},
856 {"for.l", s_mri_for
, 'l'},
857 {"endf", s_mri_endf
, 0},
858 {"repeat", s_mri_repeat
, 0},
859 {"until", s_mri_until
, 0},
860 {"until.b", s_mri_until
, 'b'},
861 {"until.w", s_mri_until
, 'w'},
862 {"until.l", s_mri_until
, 'l'},
863 {"while", s_mri_while
, 0},
864 {"while.b", s_mri_while
, 'b'},
865 {"while.w", s_mri_while
, 'w'},
866 {"while.l", s_mri_while
, 'l'},
867 {"endw", s_mri_endw
, 0},
872 /* The mote pseudo ops are put into the opcode table, since they
873 don't start with a . they look like opcodes to gas. */
875 const pseudo_typeS mote_pseudo_table
[] =
888 {"xdef", s_globl
, 0},
890 {"align", s_align_bytes
, 0},
892 {"align", s_align_ptwo
, 0},
895 {"sect", obj_coff_section
, 0},
896 {"section", obj_coff_section
, 0},
901 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
902 gives identical results to a 32-bit host. */
903 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
904 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
906 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
907 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
908 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
909 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
911 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
912 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
913 #define islong(x) (1)
915 static char notend_table
[256];
916 static char alt_notend_table
[256];
918 (! (notend_table[(unsigned char) *s] \
920 && alt_notend_table[(unsigned char) s[1]])))
924 /* Return zero if the reference to SYMBOL from within the same segment may
927 /* On an ELF system, we can't relax an externally visible symbol,
928 because it may be overridden by a shared library. However, if
929 TARGET_OS is "elf", then we presume that we are assembling for an
930 embedded system, in which case we don't have to worry about shared
931 libraries, and we can relax any external sym. */
933 #define relaxable_symbol(symbol) \
934 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
935 || S_IS_WEAK (symbol)))
937 /* Compute the relocation code for a fixup of SIZE bytes, using pc
938 relative relocation if PCREL is non-zero. PIC says whether a special
939 pic relocation was requested. */
941 static bfd_reloc_code_real_type
942 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
950 return BFD_RELOC_8_GOT_PCREL
;
952 return BFD_RELOC_16_GOT_PCREL
;
954 return BFD_RELOC_32_GOT_PCREL
;
962 return BFD_RELOC_8_GOTOFF
;
964 return BFD_RELOC_16_GOTOFF
;
966 return BFD_RELOC_32_GOTOFF
;
974 return BFD_RELOC_8_PLT_PCREL
;
976 return BFD_RELOC_16_PLT_PCREL
;
978 return BFD_RELOC_32_PLT_PCREL
;
986 return BFD_RELOC_8_PLTOFF
;
988 return BFD_RELOC_16_PLTOFF
;
990 return BFD_RELOC_32_PLTOFF
;
1000 return BFD_RELOC_8_PCREL
;
1002 return BFD_RELOC_16_PCREL
;
1004 return BFD_RELOC_32_PCREL
;
1014 return BFD_RELOC_16
;
1016 return BFD_RELOC_32
;
1023 if (pic
== pic_none
)
1024 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
1026 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
1030 if (pic
== pic_none
)
1031 as_bad (_("Can not do %d byte relocation"), size
);
1033 as_bad (_("Can not do %d byte pic relocation"), size
);
1036 return BFD_RELOC_NONE
;
1039 /* Here we decide which fixups can be adjusted to make them relative
1040 to the beginning of the section instead of the symbol. Basically
1041 we need to make sure that the dynamic relocations are done
1042 correctly, so in some cases we force the original symbol to be
1045 tc_m68k_fix_adjustable (fixS
*fixP
)
1047 /* Adjust_reloc_syms doesn't know about the GOT. */
1048 switch (fixP
->fx_r_type
)
1050 case BFD_RELOC_8_GOT_PCREL
:
1051 case BFD_RELOC_16_GOT_PCREL
:
1052 case BFD_RELOC_32_GOT_PCREL
:
1053 case BFD_RELOC_8_GOTOFF
:
1054 case BFD_RELOC_16_GOTOFF
:
1055 case BFD_RELOC_32_GOTOFF
:
1056 case BFD_RELOC_8_PLT_PCREL
:
1057 case BFD_RELOC_16_PLT_PCREL
:
1058 case BFD_RELOC_32_PLT_PCREL
:
1059 case BFD_RELOC_8_PLTOFF
:
1060 case BFD_RELOC_16_PLTOFF
:
1061 case BFD_RELOC_32_PLTOFF
:
1064 case BFD_RELOC_VTABLE_INHERIT
:
1065 case BFD_RELOC_VTABLE_ENTRY
:
1073 #else /* !OBJ_ELF */
1075 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1077 /* PR gas/3041 Weak symbols are not relaxable
1078 because they must be treated as extern. */
1079 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1081 #endif /* OBJ_ELF */
1084 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1087 bfd_reloc_code_real_type code
;
1089 /* If the tcbit is set, then this was a fixup of a negative value
1090 that was never resolved. We do not have a reloc to handle this,
1091 so just return. We assume that other code will have detected this
1092 situation and produced a helpful error message, so we just tell the
1093 user that the reloc cannot be produced. */
1097 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1098 _("Unable to produce reloc against symbol '%s'"),
1099 S_GET_NAME (fixp
->fx_addsy
));
1103 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1105 code
= fixp
->fx_r_type
;
1107 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1108 that fixup_segment converted a non-PC relative reloc into a
1109 PC relative reloc. In such a case, we need to convert the
1116 code
= BFD_RELOC_8_PCREL
;
1119 code
= BFD_RELOC_16_PCREL
;
1122 code
= BFD_RELOC_32_PCREL
;
1124 case BFD_RELOC_8_PCREL
:
1125 case BFD_RELOC_16_PCREL
:
1126 case BFD_RELOC_32_PCREL
:
1127 case BFD_RELOC_8_GOT_PCREL
:
1128 case BFD_RELOC_16_GOT_PCREL
:
1129 case BFD_RELOC_32_GOT_PCREL
:
1130 case BFD_RELOC_8_GOTOFF
:
1131 case BFD_RELOC_16_GOTOFF
:
1132 case BFD_RELOC_32_GOTOFF
:
1133 case BFD_RELOC_8_PLT_PCREL
:
1134 case BFD_RELOC_16_PLT_PCREL
:
1135 case BFD_RELOC_32_PLT_PCREL
:
1136 case BFD_RELOC_8_PLTOFF
:
1137 case BFD_RELOC_16_PLTOFF
:
1138 case BFD_RELOC_32_PLTOFF
:
1141 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1142 _("Cannot make %s relocation PC relative"),
1143 bfd_get_reloc_code_name (code
));
1149 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1150 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1152 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1153 MAP (1, 0, BFD_RELOC_8
);
1154 MAP (2, 0, BFD_RELOC_16
);
1155 MAP (4, 0, BFD_RELOC_32
);
1156 MAP (1, 1, BFD_RELOC_8_PCREL
);
1157 MAP (2, 1, BFD_RELOC_16_PCREL
);
1158 MAP (4, 1, BFD_RELOC_32_PCREL
);
1166 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1167 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1168 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1169 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1172 reloc
->addend
= fixp
->fx_addnumber
;
1173 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
1175 && S_IS_WEAK (fixp
->fx_addsy
)
1176 && ! bfd_is_und_section (S_GET_SEGMENT (fixp
->fx_addsy
)))
1177 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1178 to put the symbol offset into frags referencing a weak symbol. */
1179 reloc
->addend
= fixp
->fx_addnumber
1180 - (S_GET_VALUE (fixp
->fx_addsy
) * 2);
1184 if (!fixp
->fx_pcrel
)
1185 reloc
->addend
= fixp
->fx_addnumber
;
1187 reloc
->addend
= (section
->vma
1188 /* Explicit sign extension in case char is
1190 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1191 + fixp
->fx_addnumber
1192 + md_pcrel_from (fixp
));
1195 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1196 assert (reloc
->howto
!= 0);
1201 /* Handle of the OPCODE hash table. NULL means any use before
1202 m68k_ip_begin() will crash. */
1203 static struct hash_control
*op_hash
;
1205 /* Assemble an m68k instruction. */
1208 m68k_ip (char *instring
)
1211 register struct m68k_op
*opP
;
1212 register const struct m68k_incant
*opcode
;
1213 register const char *s
;
1214 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1215 char *pdot
, *pdotmove
;
1216 enum m68k_size siz1
, siz2
;
1220 struct m68k_op operands_backup
[6];
1221 LITTLENUM_TYPE words
[6];
1222 LITTLENUM_TYPE
*wordp
;
1223 unsigned long ok_arch
= 0;
1225 if (*instring
== ' ')
1226 instring
++; /* Skip leading whitespace. */
1228 /* Scan up to end of operation-code, which MUST end in end-of-string
1229 or exactly 1 space. */
1231 for (p
= instring
; *p
!= '\0'; p
++)
1241 the_ins
.error
= _("No operator");
1245 /* p now points to the end of the opcode name, probably whitespace.
1246 Make sure the name is null terminated by clobbering the
1247 whitespace, look it up in the hash table, then fix it back.
1248 Remove a dot, first, since the opcode tables have none. */
1251 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1252 *pdotmove
= pdotmove
[1];
1258 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1263 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1264 *pdotmove
= pdotmove
[-1];
1271 the_ins
.error
= _("Unknown operator");
1275 /* Found a legitimate opcode, start matching operands. */
1279 if (opcode
->m_operands
== 0)
1281 char *old
= input_line_pointer
;
1283 input_line_pointer
= p
;
1284 /* Ahh - it's a motorola style psuedo op. */
1285 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1286 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1287 input_line_pointer
= old
;
1293 if (flag_mri
&& opcode
->m_opnum
== 0)
1295 /* In MRI mode, random garbage is allowed after an instruction
1296 which accepts no operands. */
1297 the_ins
.args
= opcode
->m_operands
;
1298 the_ins
.numargs
= opcode
->m_opnum
;
1299 the_ins
.numo
= opcode
->m_codenum
;
1300 the_ins
.opcode
[0] = getone (opcode
);
1301 the_ins
.opcode
[1] = gettwo (opcode
);
1305 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1307 p
= crack_operand (p
, opP
);
1311 the_ins
.error
= opP
->error
;
1316 opsfound
= opP
- &the_ins
.operands
[0];
1318 /* This ugly hack is to support the floating pt opcodes in their
1319 standard form. Essentially, we fake a first enty of type COP#1 */
1320 if (opcode
->m_operands
[0] == 'I')
1324 for (n
= opsfound
; n
> 0; --n
)
1325 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1327 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1328 the_ins
.operands
[0].mode
= CONTROL
;
1329 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1333 /* We've got the operands. Find an opcode that'll accept them. */
1336 /* If we didn't get the right number of ops, or we have no
1337 common model with this pattern then reject this pattern. */
1339 ok_arch
|= opcode
->m_arch
;
1340 if (opsfound
!= opcode
->m_opnum
1341 || ((opcode
->m_arch
& current_architecture
) == 0))
1347 /* Make a copy of the operands of this insn so that
1348 we can modify them safely, should we want to. */
1349 assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1350 for (i
= 0; i
< opsfound
; i
++)
1351 operands_backup
[i
] = the_ins
.operands
[i
];
1353 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1357 /* Warning: this switch is huge! */
1358 /* I've tried to organize the cases into this order:
1359 non-alpha first, then alpha by letter. Lower-case
1360 goes directly before uppercase counterpart. */
1361 /* Code with multiple case ...: gets sorted by the lowest
1362 case ... it belongs to. I hope this makes sense. */
1468 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1485 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1504 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1514 if (opP
->mode
!= IMMED
)
1516 else if (s
[1] == 'b'
1517 && ! isvar (&opP
->disp
)
1518 && (opP
->disp
.exp
.X_op
!= O_constant
1519 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1521 else if (s
[1] == 'B'
1522 && ! isvar (&opP
->disp
)
1523 && (opP
->disp
.exp
.X_op
!= O_constant
1524 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1526 else if (s
[1] == 'w'
1527 && ! isvar (&opP
->disp
)
1528 && (opP
->disp
.exp
.X_op
!= O_constant
1529 || ! isword (opP
->disp
.exp
.X_add_number
)))
1531 else if (s
[1] == 'W'
1532 && ! isvar (&opP
->disp
)
1533 && (opP
->disp
.exp
.X_op
!= O_constant
1534 || ! issword (opP
->disp
.exp
.X_add_number
)))
1540 if (opP
->mode
!= IMMED
)
1545 if (opP
->mode
== AREG
1546 || opP
->mode
== CONTROL
1547 || opP
->mode
== FPREG
1548 || opP
->mode
== IMMED
1549 || opP
->mode
== REGLST
1550 || (opP
->mode
!= ABSL
1552 || opP
->reg
== ZPC
)))
1557 if (opP
->mode
== CONTROL
1558 || opP
->mode
== FPREG
1559 || opP
->mode
== REGLST
1560 || opP
->mode
== IMMED
1561 || (opP
->mode
!= ABSL
1563 || opP
->reg
== ZPC
)))
1591 if (opP
->mode
== CONTROL
1592 || opP
->mode
== FPREG
1593 || opP
->mode
== REGLST
)
1598 if (opP
->mode
!= AINC
)
1603 if (opP
->mode
!= ADEC
)
1653 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1674 case '~': /* For now! (JF FOO is this right?) */
1696 if (opP
->mode
!= CONTROL
1697 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1702 if (opP
->mode
!= AREG
)
1707 if (opP
->mode
!= AINDR
)
1712 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1713 && (opP
->mode
!= DISP
1715 || opP
->reg
> ADDR7
))
1720 if (opP
->mode
!= ABSL
1722 && strncmp (instring
, "jbsr", 4) == 0))
1745 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1750 if (opP
->mode
!= DISP
1752 || opP
->reg
> ADDR7
)
1757 if (opP
->mode
!= DREG
)
1762 if (opP
->reg
!= ACC
)
1767 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1768 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1773 if (opP
->mode
!= FPREG
)
1778 if (opP
->reg
!= MACSR
)
1783 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1788 if (opP
->reg
!= MASK
)
1793 if (opP
->mode
!= CONTROL
1800 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1805 if (opP
->mode
!= CONTROL
1807 || opP
->reg
> last_movec_reg
1812 const enum m68k_register
*rp
;
1814 for (rp
= control_regs
; *rp
; rp
++)
1816 if (*rp
== opP
->reg
)
1818 /* In most CPUs RAMBAR refers to control reg
1819 c05 (RAMBAR1), but a few CPUs have it
1820 refer to c04 (RAMBAR0). */
1821 else if (*rp
== RAMBAR_ALT
&& opP
->reg
== RAMBAR
)
1823 opP
->reg
= RAMBAR_ALT
;
1833 if (opP
->mode
!= IMMED
)
1839 if (opP
->mode
== DREG
1840 || opP
->mode
== AREG
1841 || opP
->mode
== FPREG
)
1850 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1853 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1856 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1864 else if (opP
->mode
== CONTROL
)
1873 opP
->mask
= 1 << 24;
1876 opP
->mask
= 1 << 25;
1879 opP
->mask
= 1 << 26;
1888 else if (opP
->mode
!= REGLST
)
1890 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1892 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1897 if (opP
->mode
!= IMMED
)
1899 else if (opP
->disp
.exp
.X_op
!= O_constant
1900 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1902 else if (! m68k_quick
1903 && instring
[3] != 'q'
1904 && instring
[4] != 'q')
1909 if (opP
->mode
!= DREG
1910 && opP
->mode
!= IMMED
1911 && opP
->mode
!= ABSL
)
1916 if (opP
->mode
!= IMMED
)
1918 else if (opP
->disp
.exp
.X_op
!= O_constant
1919 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1921 else if (! m68k_quick
1922 && (strncmp (instring
, "add", 3) == 0
1923 || strncmp (instring
, "sub", 3) == 0)
1924 && instring
[3] != 'q')
1929 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1934 if (opP
->mode
!= AINDR
1935 && (opP
->mode
!= BASE
1937 && opP
->reg
!= ZADDR0
)
1938 || opP
->disp
.exp
.X_op
!= O_absent
1939 || ((opP
->index
.reg
< DATA0
1940 || opP
->index
.reg
> DATA7
)
1941 && (opP
->index
.reg
< ADDR0
1942 || opP
->index
.reg
> ADDR7
))
1943 || opP
->index
.size
!= SIZE_UNSPEC
1944 || opP
->index
.scale
!= 1))
1949 if (opP
->mode
!= CONTROL
1950 || ! (opP
->reg
== FPI
1952 || opP
->reg
== FPC
))
1957 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1962 if (opP
->mode
!= IMMED
)
1964 else if (opP
->disp
.exp
.X_op
!= O_constant
1965 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
1970 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1975 if (opP
->mode
!= IMMED
)
1977 else if (opP
->disp
.exp
.X_op
!= O_constant
1978 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
1979 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
1984 if (opP
->mode
!= IMMED
)
1986 else if (opP
->disp
.exp
.X_op
!= O_constant
1987 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1992 if (opP
->mode
!= IMMED
)
1994 else if (opP
->disp
.exp
.X_op
!= O_constant
1995 || TRUNC (opP
->disp
.exp
.X_add_number
) > 511)
1999 /* JF these are out of order. We could put them
2000 in order if we were willing to put up with
2001 bunches of #ifdef m68851s in the code.
2003 Don't forget that you need these operands
2004 to use 68030 MMU instructions. */
2006 /* Memory addressing mode used by pflushr. */
2008 if (opP
->mode
== CONTROL
2009 || opP
->mode
== FPREG
2010 || opP
->mode
== DREG
2011 || opP
->mode
== AREG
2012 || opP
->mode
== REGLST
)
2014 /* We should accept immediate operands, but they
2015 supposedly have to be quad word, and we don't
2016 handle that. I would like to see what a Motorola
2017 assembler does before doing something here. */
2018 if (opP
->mode
== IMMED
)
2023 if (opP
->mode
!= CONTROL
2024 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2029 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
2034 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
2039 if (opP
->mode
!= CONTROL
2042 && opP
->reg
!= SCC
))
2047 if (opP
->mode
!= CONTROL
2053 if (opP
->mode
!= CONTROL
2056 && opP
->reg
!= CRP
))
2080 if (opP
->mode
!= CONTROL
2081 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
2082 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2087 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
2092 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2097 if (opP
->mode
!= CONTROL
2106 if (opP
->mode
!= ABSL
)
2111 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2113 /* FIXME: kludge instead of fixing parser:
2114 upper/lower registers are *not* CONTROL
2115 registers, but ordinary ones. */
2116 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2117 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2124 if (!(opP
->mode
== AINDR
2125 || (opP
->mode
== DISP
2126 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2131 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2143 /* Since we have found the correct instruction, copy
2144 in the modifications that we may have made. */
2146 for (i
= 0; i
< opsfound
; i
++)
2147 the_ins
.operands
[i
] = operands_backup
[i
];
2153 opcode
= opcode
->m_next
;
2158 && !(ok_arch
& current_architecture
))
2160 const struct m68k_cpu
*cpu
;
2163 char *buf
= xmalloc (space
+ 1);
2167 the_ins
.error
= buf
;
2168 /* Make sure there's a NUL at the end of the buffer -- strncpy
2169 won't write one when it runs out of buffer */
2171 #define APPEND(STRING) \
2172 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2174 APPEND (_("invalid instruction for this architecture; needs "));
2178 APPEND (_("ColdFire ISA_A"));
2181 APPEND (_("ColdFire hardware divide"));
2184 APPEND (_("ColdFire ISA_A+"));
2187 APPEND (_("ColdFire ISA_B"));
2190 APPEND (_("ColdFire ISA_C"));
2193 APPEND (_("ColdFire fpu"));
2196 APPEND (_("M68K fpu"));
2199 APPEND (_("M68K mmu"));
2202 APPEND (_("68020 or higher"));
2205 APPEND (_("68000 or higher"));
2208 APPEND (_("68010 or higher"));
2216 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2217 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2219 const struct m68k_cpu
*alias
;
2220 int seen_master
= 0;
2226 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2227 if (alias
[-1].alias
>= 0)
2229 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2239 APPEND (alias
->name
);
2252 /* we ran out of space, so replace the end of the list
2257 strcpy (buf
, " ...");
2261 the_ins
.error
= _("operands mismatch");
2268 /* Now assemble it. */
2269 the_ins
.args
= opcode
->m_operands
;
2270 the_ins
.numargs
= opcode
->m_opnum
;
2271 the_ins
.numo
= opcode
->m_codenum
;
2272 the_ins
.opcode
[0] = getone (opcode
);
2273 the_ins
.opcode
[1] = gettwo (opcode
);
2275 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2279 /* This switch is a doozy.
2280 Watch the first step; its a big one! */
2313 tmpreg
= 0x3c; /* 7.4 */
2314 if (strchr ("bwl", s
[1]))
2315 nextword
= get_num (&opP
->disp
, 90);
2317 nextword
= get_num (&opP
->disp
, 0);
2318 if (isvar (&opP
->disp
))
2319 add_fix (s
[1], &opP
->disp
, 0, 0);
2323 if (!isbyte (nextword
))
2324 opP
->error
= _("operand out of range");
2329 if (!isword (nextword
))
2330 opP
->error
= _("operand out of range");
2335 if (!issword (nextword
))
2336 opP
->error
= _("operand out of range");
2341 addword (nextword
>> 16);
2368 /* We gotta put out some float. */
2369 if (op (&opP
->disp
) != O_big
)
2374 /* Can other cases happen here? */
2375 if (op (&opP
->disp
) != O_constant
)
2378 val
= (valueT
) offs (&opP
->disp
);
2382 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2383 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2387 offs (&opP
->disp
) = gencnt
;
2389 if (offs (&opP
->disp
) > 0)
2391 if (offs (&opP
->disp
) > baseo
)
2393 as_warn (_("Bignum too big for %c format; truncated"),
2395 offs (&opP
->disp
) = baseo
;
2397 baseo
-= offs (&opP
->disp
);
2400 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2401 offs (&opP
->disp
)--;
2406 gen_to_words (words
, baseo
, (long) outro
);
2407 for (wordp
= words
; baseo
--; wordp
++)
2411 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2414 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2417 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2420 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2423 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2427 nextword
= get_num (&opP
->disp
, 90);
2429 /* Convert mode 5 addressing with a zero offset into
2430 mode 2 addressing to reduce the instruction size by a
2432 if (! isvar (&opP
->disp
)
2434 && (opP
->disp
.size
== SIZE_UNSPEC
)
2435 && (opP
->reg
>= ADDR0
)
2436 && (opP
->reg
<= ADDR7
))
2438 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2443 && ! isvar (&opP
->disp
)
2446 opP
->disp
.exp
.X_op
= O_symbol
;
2447 opP
->disp
.exp
.X_add_symbol
=
2448 section_symbol (absolute_section
);
2451 /* Force into index mode. Hope this works. */
2453 /* We do the first bit for 32-bit displacements, and the
2454 second bit for 16 bit ones. It is possible that we
2455 should make the default be WORD instead of LONG, but
2456 I think that'd break GCC, so we put up with a little
2457 inefficiency for the sake of working output. */
2459 if (!issword (nextword
)
2460 || (isvar (&opP
->disp
)
2461 && ((opP
->disp
.size
== SIZE_UNSPEC
2462 && flag_short_refs
== 0
2463 && cpu_of_arch (current_architecture
) >= m68020
2464 && ! arch_coldfire_p (current_architecture
))
2465 || opP
->disp
.size
== SIZE_LONG
)))
2467 if (cpu_of_arch (current_architecture
) < m68020
2468 || arch_coldfire_p (current_architecture
))
2470 _("displacement too large for this architecture; needs 68020 or higher");
2472 tmpreg
= 0x3B; /* 7.3 */
2474 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2475 if (isvar (&opP
->disp
))
2479 if (opP
->disp
.size
== SIZE_LONG
2481 /* If the displacement needs pic
2482 relocation it cannot be relaxed. */
2483 || opP
->disp
.pic_reloc
!= pic_none
2488 add_fix ('l', &opP
->disp
, 1, 2);
2492 add_frag (adds (&opP
->disp
),
2493 SEXT (offs (&opP
->disp
)),
2494 TAB (PCREL1632
, SZ_UNDEF
));
2501 add_fix ('l', &opP
->disp
, 0, 0);
2506 addword (nextword
>> 16);
2511 tmpreg
= 0x3A; /* 7.2 */
2513 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2515 if (isvar (&opP
->disp
))
2519 add_fix ('w', &opP
->disp
, 1, 0);
2522 add_fix ('w', &opP
->disp
, 0, 0);
2532 baseo
= get_num (&opP
->disp
, 90);
2533 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2534 outro
= get_num (&opP
->odisp
, 90);
2535 /* Figure out the `addressing mode'.
2536 Also turn on the BASE_DISABLE bit, if needed. */
2537 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2539 tmpreg
= 0x3b; /* 7.3 */
2540 if (opP
->reg
== ZPC
)
2543 else if (opP
->reg
== 0)
2546 tmpreg
= 0x30; /* 6.garbage */
2548 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2551 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2554 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2556 siz1
= opP
->disp
.size
;
2557 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2558 siz2
= opP
->odisp
.size
;
2562 /* Index register stuff. */
2563 if (opP
->index
.reg
!= 0
2564 && opP
->index
.reg
>= DATA
2565 && opP
->index
.reg
<= ADDR7
)
2567 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2569 if (opP
->index
.size
== SIZE_LONG
2570 || (opP
->index
.size
== SIZE_UNSPEC
2571 && m68k_index_width_default
== SIZE_LONG
))
2574 if ((opP
->index
.scale
!= 1
2575 && cpu_of_arch (current_architecture
) < m68020
)
2576 || (opP
->index
.scale
== 8
2577 && (arch_coldfire_p (current_architecture
)
2578 && !arch_coldfire_fpu (current_architecture
))))
2581 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2584 if (arch_coldfire_p (current_architecture
)
2585 && opP
->index
.size
== SIZE_WORD
)
2586 opP
->error
= _("invalid index size for coldfire");
2588 switch (opP
->index
.scale
)
2605 GET US OUT OF HERE! */
2607 /* Must be INDEX, with an index register. Address
2608 register cannot be ZERO-PC, and either :b was
2609 forced, or we know it will fit. For a 68000 or
2610 68010, force this mode anyways, because the
2611 larger modes aren't supported. */
2612 if (opP
->mode
== BASE
2613 && ((opP
->reg
>= ADDR0
2614 && opP
->reg
<= ADDR7
)
2617 if (siz1
== SIZE_BYTE
2618 || cpu_of_arch (current_architecture
) < m68020
2619 || arch_coldfire_p (current_architecture
)
2620 || (siz1
== SIZE_UNSPEC
2621 && ! isvar (&opP
->disp
)
2622 && issbyte (baseo
)))
2624 nextword
+= baseo
& 0xff;
2626 if (isvar (&opP
->disp
))
2628 /* Do a byte relocation. If it doesn't
2629 fit (possible on m68000) let the
2630 fixup processing complain later. */
2632 add_fix ('B', &opP
->disp
, 1, 1);
2634 add_fix ('B', &opP
->disp
, 0, 0);
2636 else if (siz1
!= SIZE_BYTE
)
2638 if (siz1
!= SIZE_UNSPEC
)
2639 as_warn (_("Forcing byte displacement"));
2640 if (! issbyte (baseo
))
2641 opP
->error
= _("byte displacement out of range");
2646 else if (siz1
== SIZE_UNSPEC
2648 && isvar (&opP
->disp
)
2649 && subs (&opP
->disp
) == NULL
2651 /* If the displacement needs pic
2652 relocation it cannot be relaxed. */
2653 && opP
->disp
.pic_reloc
== pic_none
2657 /* The code in md_convert_frag_1 needs to be
2658 able to adjust nextword. Call frag_grow
2659 to ensure that we have enough space in
2660 the frag obstack to make all the bytes
2663 nextword
+= baseo
& 0xff;
2665 add_frag (adds (&opP
->disp
),
2666 SEXT (offs (&opP
->disp
)),
2667 TAB (PCINDEX
, SZ_UNDEF
));
2675 nextword
|= 0x40; /* No index reg. */
2676 if (opP
->index
.reg
>= ZDATA0
2677 && opP
->index
.reg
<= ZDATA7
)
2678 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2679 else if (opP
->index
.reg
>= ZADDR0
2680 || opP
->index
.reg
<= ZADDR7
)
2681 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2684 /* It isn't simple. */
2686 if (cpu_of_arch (current_architecture
) < m68020
2687 || arch_coldfire_p (current_architecture
))
2689 _("invalid operand mode for this architecture; needs 68020 or higher");
2692 /* If the guy specified a width, we assume that it is
2693 wide enough. Maybe it isn't. If so, we lose. */
2697 if (isvar (&opP
->disp
)
2699 : ! issword (baseo
))
2704 else if (! isvar (&opP
->disp
) && baseo
== 0)
2713 as_warn (_(":b not permitted; defaulting to :w"));
2723 /* Figure out inner displacement stuff. */
2724 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2726 if (cpu_of_arch (current_architecture
) & cpu32
)
2727 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2731 if (isvar (&opP
->odisp
)
2733 : ! issword (outro
))
2738 else if (! isvar (&opP
->odisp
) && outro
== 0)
2747 as_warn (_(":b not permitted; defaulting to :w"));
2756 if (opP
->mode
== POST
2757 && (nextword
& 0x40) == 0)
2762 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2764 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2765 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2767 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2769 if (siz1
== SIZE_LONG
)
2770 addword (baseo
>> 16);
2771 if (siz1
!= SIZE_UNSPEC
)
2774 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2775 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2776 if (siz2
== SIZE_LONG
)
2777 addword (outro
>> 16);
2778 if (siz2
!= SIZE_UNSPEC
)
2784 nextword
= get_num (&opP
->disp
, 90);
2785 switch (opP
->disp
.size
)
2790 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2792 tmpreg
= 0x38; /* 7.0 */
2796 if (isvar (&opP
->disp
)
2797 && !subs (&opP
->disp
)
2798 && adds (&opP
->disp
)
2800 /* If the displacement needs pic relocation it
2801 cannot be relaxed. */
2802 && opP
->disp
.pic_reloc
== pic_none
2805 && !strchr ("~%&$?", s
[0]))
2807 tmpreg
= 0x3A; /* 7.2 */
2808 add_frag (adds (&opP
->disp
),
2809 SEXT (offs (&opP
->disp
)),
2810 TAB (ABSTOPCREL
, SZ_UNDEF
));
2813 /* Fall through into long. */
2815 if (isvar (&opP
->disp
))
2816 add_fix ('l', &opP
->disp
, 0, 0);
2818 tmpreg
= 0x39;/* 7.1 mode */
2819 addword (nextword
>> 16);
2824 as_bad (_("unsupported byte value; use a different suffix"));
2828 if (isvar (&opP
->disp
))
2829 add_fix ('w', &opP
->disp
, 0, 0);
2831 tmpreg
= 0x38;/* 7.0 mode */
2839 as_bad (_("unknown/incorrect operand"));
2843 /* If s[0] is '4', then this is for the mac instructions
2844 that can have a trailing_ampersand set. If so, set 0x100
2845 bit on tmpreg so install_gen_operand can check for it and
2846 set the appropriate bit (word2, bit 5). */
2849 if (opP
->trailing_ampersand
)
2852 install_gen_operand (s
[1], tmpreg
);
2858 { /* JF: I hate floating point! */
2873 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2874 if (isvar (&opP
->disp
))
2875 add_fix (s
[1], &opP
->disp
, 0, 0);
2878 case 'b': /* Danger: These do no check for
2879 certain types of overflow.
2881 if (!isbyte (tmpreg
))
2882 opP
->error
= _("out of range");
2883 insop (tmpreg
, opcode
);
2884 if (isvar (&opP
->disp
))
2885 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2886 (opcode
->m_codenum
) * 2 + 1;
2889 if (!issbyte (tmpreg
))
2890 opP
->error
= _("out of range");
2891 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2892 if (isvar (&opP
->disp
))
2893 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2896 if (!isword (tmpreg
))
2897 opP
->error
= _("out of range");
2898 insop (tmpreg
, opcode
);
2899 if (isvar (&opP
->disp
))
2900 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2903 if (!issword (tmpreg
))
2904 opP
->error
= _("out of range");
2905 insop (tmpreg
, opcode
);
2906 if (isvar (&opP
->disp
))
2907 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2910 /* Because of the way insop works, we put these two out
2912 insop (tmpreg
, opcode
);
2913 insop (tmpreg
>> 16, opcode
);
2914 if (isvar (&opP
->disp
))
2915 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2922 install_operand (s
[1], tmpreg
);
2933 install_operand (s
[1], opP
->reg
- ADDR
);
2937 tmpreg
= get_num (&opP
->disp
, 90);
2942 add_fix ('B', &opP
->disp
, 1, -1);
2945 add_fix ('w', &opP
->disp
, 1, 0);
2950 the_ins
.opcode
[0] |= 0xff;
2951 add_fix ('l', &opP
->disp
, 1, 0);
2955 case 'g': /* Conditional branch */
2956 have_disp
= HAVE_LONG_CALL (current_architecture
);
2959 case 'b': /* Unconditional branch */
2960 have_disp
= HAVE_LONG_BRANCH (current_architecture
);
2963 case 's': /* Unconditional subroutine */
2964 have_disp
= HAVE_LONG_CALL (current_architecture
);
2967 if (subs (&opP
->disp
) /* We can't relax it. */
2969 /* If the displacement needs pic relocation it cannot be
2971 || opP
->disp
.pic_reloc
!= pic_none
2976 as_warn (_("Can't use long branches on this architecture"));
2980 /* This could either be a symbol, or an absolute
2981 address. If it's an absolute address, turn it into
2982 an absolute jump right here and keep it out of the
2984 if (adds (&opP
->disp
) == 0)
2986 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2987 the_ins
.opcode
[0] = 0x4EF9;
2988 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2989 the_ins
.opcode
[0] = 0x4EB9;
2992 the_ins
.opcode
[0] ^= 0x0100;
2993 the_ins
.opcode
[0] |= 0x0006;
2996 add_fix ('l', &opP
->disp
, 0, 0);
3002 /* Now we know it's going into the relaxer. Now figure
3003 out which mode. We try in this order of preference:
3004 long branch, absolute jump, byte/word branches only. */
3006 add_frag (adds (&opP
->disp
),
3007 SEXT (offs (&opP
->disp
)),
3008 TAB (BRANCHBWL
, SZ_UNDEF
));
3009 else if (! flag_keep_pcrel
)
3011 if ((the_ins
.opcode
[0] == 0x6000)
3012 || (the_ins
.opcode
[0] == 0x6100))
3013 add_frag (adds (&opP
->disp
),
3014 SEXT (offs (&opP
->disp
)),
3015 TAB (BRABSJUNC
, SZ_UNDEF
));
3017 add_frag (adds (&opP
->disp
),
3018 SEXT (offs (&opP
->disp
)),
3019 TAB (BRABSJCOND
, SZ_UNDEF
));
3022 add_frag (adds (&opP
->disp
),
3023 SEXT (offs (&opP
->disp
)),
3024 TAB (BRANCHBW
, SZ_UNDEF
));
3027 if (isvar (&opP
->disp
))
3029 /* Check for DBcc instructions. We can relax them,
3030 but only if we have long branches and/or absolute
3032 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
3033 && (HAVE_LONG_BRANCH (current_architecture
)
3034 || ! flag_keep_pcrel
))
3036 if (HAVE_LONG_BRANCH (current_architecture
))
3037 add_frag (adds (&opP
->disp
),
3038 SEXT (offs (&opP
->disp
)),
3039 TAB (DBCCLBR
, SZ_UNDEF
));
3041 add_frag (adds (&opP
->disp
),
3042 SEXT (offs (&opP
->disp
)),
3043 TAB (DBCCABSJ
, SZ_UNDEF
));
3046 add_fix ('w', &opP
->disp
, 1, 0);
3050 case 'C': /* Fixed size LONG coproc branches. */
3051 add_fix ('l', &opP
->disp
, 1, 0);
3055 case 'c': /* Var size Coprocesssor branches. */
3056 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
3058 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
3059 add_fix ('l', &opP
->disp
, 1, 0);
3064 add_frag (adds (&opP
->disp
),
3065 SEXT (offs (&opP
->disp
)),
3066 TAB (FBRANCH
, SZ_UNDEF
));
3073 case 'C': /* Ignore it. */
3076 case 'd': /* JF this is a kludge. */
3077 install_operand ('s', opP
->reg
- ADDR
);
3078 tmpreg
= get_num (&opP
->disp
, 90);
3079 if (!issword (tmpreg
))
3081 as_warn (_("Expression out of range, using 0"));
3088 install_operand (s
[1], opP
->reg
- DATA
);
3091 case 'e': /* EMAC ACCx, reg/reg. */
3092 install_operand (s
[1], opP
->reg
- ACC
);
3095 case 'E': /* Ignore it. */
3099 install_operand (s
[1], opP
->reg
- FP0
);
3102 case 'g': /* EMAC ACCEXTx. */
3103 install_operand (s
[1], opP
->reg
- ACCEXT01
);
3106 case 'G': /* Ignore it. */
3111 tmpreg
= opP
->reg
- COP0
;
3112 install_operand (s
[1], tmpreg
);
3115 case 'i': /* MAC/EMAC scale factor. */
3116 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3119 case 'J': /* JF foo. */
3259 install_operand (s
[1], tmpreg
);
3263 tmpreg
= get_num (&opP
->disp
, 55);
3264 install_operand (s
[1], tmpreg
& 0x7f);
3271 if (tmpreg
& 0x7FF0000)
3272 as_bad (_("Floating point register in register list"));
3273 insop (reverse_16_bits (tmpreg
), opcode
);
3277 if (tmpreg
& 0x700FFFF)
3278 as_bad (_("Wrong register in floating-point reglist"));
3279 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3287 if (tmpreg
& 0x7FF0000)
3288 as_bad (_("Floating point register in register list"));
3289 insop (tmpreg
, opcode
);
3291 else if (s
[1] == '8')
3293 if (tmpreg
& 0x0FFFFFF)
3294 as_bad (_("incorrect register in reglist"));
3295 install_operand (s
[1], tmpreg
>> 24);
3299 if (tmpreg
& 0x700FFFF)
3300 as_bad (_("wrong register in floating-point reglist"));
3302 install_operand (s
[1], tmpreg
>> 16);
3307 install_operand (s
[1], get_num (&opP
->disp
, 60));
3311 tmpreg
= ((opP
->mode
== DREG
)
3312 ? 0x20 + (int) (opP
->reg
- DATA
)
3313 : (get_num (&opP
->disp
, 40) & 0x1F));
3314 install_operand (s
[1], tmpreg
);
3318 tmpreg
= get_num (&opP
->disp
, 10);
3321 install_operand (s
[1], tmpreg
);
3325 /* This depends on the fact that ADDR registers are eight
3326 more than their corresponding DATA regs, so the result
3327 will have the ADDR_REG bit set. */
3328 install_operand (s
[1], opP
->reg
- DATA
);
3332 if (opP
->mode
== AINDR
)
3333 install_operand (s
[1], opP
->reg
- DATA
);
3335 install_operand (s
[1], opP
->index
.reg
- DATA
);
3339 if (opP
->reg
== FPI
)
3341 else if (opP
->reg
== FPS
)
3343 else if (opP
->reg
== FPC
)
3347 install_operand (s
[1], tmpreg
);
3350 case 'S': /* Ignore it. */
3354 install_operand (s
[1], get_num (&opP
->disp
, 30));
3357 case 'U': /* Ignore it. */
3376 as_fatal (_("failed sanity check"));
3377 } /* switch on cache token. */
3378 install_operand (s
[1], tmpreg
);
3381 /* JF: These are out of order, I fear. */
3394 install_operand (s
[1], tmpreg
);
3420 install_operand (s
[1], tmpreg
);
3424 if (opP
->reg
== VAL
)
3443 install_operand (s
[1], tmpreg
);
3457 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3468 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3474 install_operand (s
[1], tmpreg
);
3477 know (opP
->reg
== PSR
);
3480 know (opP
->reg
== PCSR
);
3495 install_operand (s
[1], tmpreg
);
3498 tmpreg
= get_num (&opP
->disp
, 20);
3499 install_operand (s
[1], tmpreg
);
3501 case '_': /* used only for move16 absolute 32-bit address. */
3502 if (isvar (&opP
->disp
))
3503 add_fix ('l', &opP
->disp
, 0, 0);
3504 tmpreg
= get_num (&opP
->disp
, 90);
3505 addword (tmpreg
>> 16);
3506 addword (tmpreg
& 0xFFFF);
3509 install_operand (s
[1], opP
->reg
- DATA0L
);
3510 opP
->reg
-= (DATA0L
);
3511 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3514 tmpreg
= get_num (&opP
->disp
, 80);
3517 install_operand (s
[1], tmpreg
);
3520 tmpreg
= get_num (&opP
->disp
, 10);
3521 install_operand (s
[1], tmpreg
- 1);
3524 tmpreg
= get_num (&opP
->disp
, 65);
3525 install_operand (s
[1], tmpreg
);
3532 /* By the time whe get here (FINALLY) the_ins contains the complete
3533 instruction, ready to be emitted. . . */
3537 reverse_16_bits (int in
)
3542 static int mask
[16] =
3544 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3545 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3547 for (n
= 0; n
< 16; n
++)
3550 out
|= mask
[15 - n
];
3553 } /* reverse_16_bits() */
3556 reverse_8_bits (int in
)
3561 static int mask
[8] =
3563 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3566 for (n
= 0; n
< 8; n
++)
3572 } /* reverse_8_bits() */
3574 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3575 (that value is chosen in the frag_var call in md_assemble). TYPE
3576 is the subtype of the frag to be generated; its primary type is
3577 rs_machine_dependent.
3579 The TYPE parameter is also used by md_convert_frag_1 and
3580 md_estimate_size_before_relax. The appropriate type of fixup will
3581 be emitted by md_convert_frag_1.
3583 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3585 install_operand (int mode
, int val
)
3590 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3593 the_ins
.opcode
[0] |= val
<< 9;
3596 the_ins
.opcode
[1] |= val
<< 9;
3599 the_ins
.opcode
[1] |= val
<< 12;
3602 the_ins
.opcode
[1] |= val
<< 6;
3605 the_ins
.opcode
[1] |= val
;
3608 the_ins
.opcode
[2] |= val
<< 12;
3611 the_ins
.opcode
[2] |= val
<< 6;
3614 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3615 three words long! */
3617 the_ins
.opcode
[2] |= val
;
3620 the_ins
.opcode
[1] |= val
<< 7;
3623 the_ins
.opcode
[1] |= val
<< 10;
3627 the_ins
.opcode
[1] |= val
<< 5;
3632 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3635 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3638 the_ins
.opcode
[0] |= val
= 0xff;
3641 the_ins
.opcode
[0] |= val
<< 9;
3644 the_ins
.opcode
[1] |= val
;
3647 the_ins
.opcode
[1] |= val
;
3648 the_ins
.numo
++; /* What a hack. */
3651 the_ins
.opcode
[1] |= val
<< 4;
3659 the_ins
.opcode
[0] |= (val
<< 6);
3662 the_ins
.opcode
[1] = (val
>> 16);
3663 the_ins
.opcode
[2] = val
& 0xffff;
3666 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3667 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3668 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3670 case 'n': /* MAC/EMAC Rx on !load. */
3671 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3672 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3673 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3675 case 'o': /* MAC/EMAC Rx on load. */
3676 the_ins
.opcode
[1] |= val
<< 12;
3677 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3679 case 'M': /* MAC/EMAC Ry on !load. */
3680 the_ins
.opcode
[0] |= (val
& 0xF);
3681 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3683 case 'N': /* MAC/EMAC Ry on load. */
3684 the_ins
.opcode
[1] |= (val
& 0xF);
3685 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3688 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3691 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3694 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3696 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3697 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3698 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3700 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3701 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3702 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3705 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3708 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3712 as_fatal (_("failed sanity check."));
3717 install_gen_operand (int mode
, int val
)
3721 case '/': /* Special for mask loads for mac/msac insns with
3722 possible mask; trailing_ampersend set in bit 8. */
3723 the_ins
.opcode
[0] |= (val
& 0x3f);
3724 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3727 the_ins
.opcode
[0] |= val
;
3730 /* This is a kludge!!! */
3731 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3740 the_ins
.opcode
[0] |= val
;
3742 /* more stuff goes here. */
3744 as_fatal (_("failed sanity check."));
3748 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3749 then deal with the bitfield hack. */
3752 crack_operand (char *str
, struct m68k_op
*opP
)
3754 register int parens
;
3756 register char *beg_str
;
3764 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3770 else if (*str
== ')')
3774 opP
->error
= _("Extra )");
3780 if (flag_mri
&& *str
== '\'')
3781 inquote
= ! inquote
;
3783 if (!*str
&& parens
)
3785 opP
->error
= _("Missing )");
3790 if (m68k_ip_op (beg_str
, opP
) != 0)
3797 c
= *++str
; /* JF bitfield hack. */
3802 as_bad (_("Missing operand"));
3805 /* Detect MRI REG symbols and convert them to REGLSTs. */
3806 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3809 opP
->mask
= ~(int)opP
->reg
;
3816 /* This is the guts of the machine-dependent assembler. STR points to a
3817 machine dependent instruction. This function is supposed to emit
3818 the frags/bytes it assembles to.
3822 insert_reg (const char *regname
, int regnum
)
3827 #ifdef REGISTER_PREFIX
3828 if (!flag_reg_prefix_optional
)
3830 buf
[0] = REGISTER_PREFIX
;
3831 strcpy (buf
+ 1, regname
);
3836 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3837 &zero_address_frag
));
3839 for (i
= 0; regname
[i
]; i
++)
3840 buf
[i
] = TOUPPER (regname
[i
]);
3843 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3844 &zero_address_frag
));
3853 static const struct init_entry init_table
[] =
3913 { "accext01", ACCEXT01
},
3914 { "accext23", ACCEXT23
},
3918 /* Control registers. */
3919 { "sfc", SFC
}, /* Source Function Code. */
3921 { "dfc", DFC
}, /* Destination Function Code. */
3923 { "cacr", CACR
}, /* Cache Control Register. */
3924 { "caar", CAAR
}, /* Cache Address Register. */
3926 { "usp", USP
}, /* User Stack Pointer. */
3927 { "vbr", VBR
}, /* Vector Base Register. */
3928 { "msp", MSP
}, /* Master Stack Pointer. */
3929 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3931 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3932 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3933 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3934 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3936 /* 68ec040 versions of same */
3937 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3938 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3939 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3940 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3942 /* Coldfire versions of same. The ColdFire programmer's reference
3943 manual indicated that the order is 2,3,0,1, but Ken Rose
3944 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3945 { "acr0", ACR0
}, /* Access Control Unit 0. */
3946 { "acr1", ACR1
}, /* Access Control Unit 1. */
3947 { "acr2", ACR2
}, /* Access Control Unit 2. */
3948 { "acr3", ACR3
}, /* Access Control Unit 3. */
3950 { "tc", TC
}, /* MMU Translation Control Register. */
3954 { "mmusr", MMUSR
}, /* MMU Status Register. */
3955 { "srp", SRP
}, /* User Root Pointer. */
3956 { "urp", URP
}, /* Supervisor Root Pointer. */
3959 { "mmubar", MMUBAR
},
3962 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3963 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3964 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3965 { "mbar", MBAR
}, /* Module Base Address Register. */
3967 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3968 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3969 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
3970 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3971 { "mpcr", MPCR
}, /* mcfv4e registers. */
3972 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3973 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3974 { "asid", TC
}, /* mcfv4e registers. */
3975 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3976 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3977 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3978 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3979 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3980 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3981 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3982 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3983 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3984 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3985 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3986 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3987 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3989 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3990 { "rambar", RAMBAR
}, /* mcf528x registers. */
3992 { "mbar2", MBAR2
}, /* mcf5249 registers. */
3994 { "cac", CAC
}, /* fido registers. */
3995 { "mbb", MBB
}, /* fido registers. */
3996 /* End of control registers. */
4030 /* 68ec030 versions of same. */
4033 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4036 /* Suppressed data and address registers. */
4054 /* Upper and lower data and address registers, used by macw and msacw. */
4095 init_regtable (void)
4098 for (i
= 0; init_table
[i
].name
; i
++)
4099 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
4103 md_assemble (char *str
)
4110 int shorts_this_frag
;
4113 if (!selected_cpu
&& !selected_arch
)
4115 /* We've not selected an architecture yet. Set the default
4116 now. We do this lazily so that an initial .cpu or .arch directive
4118 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
4119 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
4124 /* In MRI mode, the instruction and operands are separated by a
4125 space. Anything following the operands is a comment. The label
4126 has already been removed. */
4134 for (s
= str
; *s
!= '\0'; s
++)
4136 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4154 inquote
= ! inquote
;
4159 memset (&the_ins
, '\0', sizeof (the_ins
));
4164 for (n
= 0; n
< the_ins
.numargs
; n
++)
4165 if (the_ins
.operands
[n
].error
)
4167 er
= the_ins
.operands
[n
].error
;
4173 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4177 /* If there is a current label, record that it marks an instruction. */
4178 if (current_label
!= NULL
)
4180 current_label
->text
= 1;
4181 current_label
= NULL
;
4185 /* Tie dwarf2 debug info to the address at the start of the insn. */
4186 dwarf2_emit_insn (0);
4189 if (the_ins
.nfrag
== 0)
4191 /* No frag hacking involved; just put it out. */
4192 toP
= frag_more (2 * the_ins
.numo
);
4193 fromP
= &the_ins
.opcode
[0];
4194 for (m
= the_ins
.numo
; m
; --m
)
4196 md_number_to_chars (toP
, (long) (*fromP
), 2);
4200 /* Put out symbol-dependent info. */
4201 for (m
= 0; m
< the_ins
.nrel
; m
++)
4203 switch (the_ins
.reloc
[m
].wid
)
4222 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4223 the_ins
.reloc
[m
].wid
);
4226 fixP
= fix_new_exp (frag_now
,
4227 ((toP
- frag_now
->fr_literal
)
4228 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4230 &the_ins
.reloc
[m
].exp
,
4231 the_ins
.reloc
[m
].pcrel
,
4232 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4233 the_ins
.reloc
[m
].pic_reloc
));
4234 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4235 if (the_ins
.reloc
[m
].wid
== 'B')
4236 fixP
->fx_signed
= 1;
4241 /* There's some frag hacking. */
4243 /* Calculate the max frag size. */
4246 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4247 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4248 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4249 /* frag_var part. */
4251 /* Make sure the whole insn fits in one chunk, in particular that
4252 the var part is attached, as we access one byte before the
4253 variable frag for byte branches. */
4257 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4262 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4264 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4265 toP
= frag_more (wid
);
4267 shorts_this_frag
= 0;
4268 for (m
= wid
/ 2; m
; --m
)
4270 md_number_to_chars (toP
, (long) (*fromP
), 2);
4275 for (m
= 0; m
< the_ins
.nrel
; m
++)
4277 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4279 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4282 wid
= the_ins
.reloc
[m
].wid
;
4285 the_ins
.reloc
[m
].wid
= 0;
4286 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4288 fixP
= fix_new_exp (frag_now
,
4289 ((toP
- frag_now
->fr_literal
)
4290 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4292 &the_ins
.reloc
[m
].exp
,
4293 the_ins
.reloc
[m
].pcrel
,
4294 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4295 the_ins
.reloc
[m
].pic_reloc
));
4296 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4298 (void) frag_var (rs_machine_dependent
, 10, 0,
4299 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4300 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4302 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4303 shorts_this_frag
= 0;
4306 toP
= frag_more (n
* 2);
4309 md_number_to_chars (toP
, (long) (*fromP
), 2);
4315 for (m
= 0; m
< the_ins
.nrel
; m
++)
4319 wid
= the_ins
.reloc
[m
].wid
;
4322 the_ins
.reloc
[m
].wid
= 0;
4323 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4325 fixP
= fix_new_exp (frag_now
,
4326 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4327 - shorts_this_frag
* 2),
4329 &the_ins
.reloc
[m
].exp
,
4330 the_ins
.reloc
[m
].pcrel
,
4331 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4332 the_ins
.reloc
[m
].pic_reloc
));
4333 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4337 /* Comparison function used by qsort to rank the opcode entries by name. */
4340 m68k_compare_opcode (const void * v1
, const void * v2
)
4342 struct m68k_opcode
* op1
, * op2
;
4348 op1
= *(struct m68k_opcode
**) v1
;
4349 op2
= *(struct m68k_opcode
**) v2
;
4351 /* Compare the two names. If different, return the comparison.
4352 If the same, return the order they are in the opcode table. */
4353 ret
= strcmp (op1
->name
, op2
->name
);
4364 const struct m68k_opcode
*ins
;
4365 struct m68k_incant
*hack
, *slak
;
4366 const char *retval
= 0; /* Empty string, or error msg text. */
4369 /* Set up hash tables with 68000 instructions.
4370 similar to what the vax assembler does. */
4371 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4372 a copy of it at runtime, adding in the information we want but isn't
4373 there. I think it'd be better to have an awk script hack the table
4374 at compile time. Or even just xstr the table and use it as-is. But
4375 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4380 flag_reg_prefix_optional
= 1;
4382 if (! m68k_rel32_from_cmdline
)
4386 /* First sort the opcode table into alphabetical order to seperate
4387 the order that the assembler wants to see the opcodes from the
4388 order that the disassembler wants to see them. */
4389 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4390 if (!m68k_sorted_opcodes
)
4391 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4392 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4394 for (i
= m68k_numopcodes
; i
--;)
4395 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4397 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4398 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4400 op_hash
= hash_new ();
4402 obstack_begin (&robyn
, 4000);
4403 for (i
= 0; i
< m68k_numopcodes
; i
++)
4405 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4408 ins
= m68k_sorted_opcodes
[i
];
4410 /* We must enter all insns into the table, because .arch and
4411 .cpu directives can change things. */
4412 slak
->m_operands
= ins
->args
;
4413 slak
->m_arch
= ins
->arch
;
4414 slak
->m_opcode
= ins
->opcode
;
4416 /* In most cases we can determine the number of opcode words
4417 by checking the second word of the mask. Unfortunately
4418 some instructions have 2 opcode words, but no fixed bits
4419 in the second word. A leading dot in the operands
4420 string also indicates 2 opcodes. */
4421 if (*slak
->m_operands
== '.')
4424 slak
->m_codenum
= 2;
4426 else if (ins
->match
& 0xffffL
)
4427 slak
->m_codenum
= 2;
4429 slak
->m_codenum
= 1;
4430 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4432 if (i
+ 1 != m68k_numopcodes
4433 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4435 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4440 slak
= slak
->m_next
;
4444 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4446 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4449 for (i
= 0; i
< m68k_numaliases
; i
++)
4451 const char *name
= m68k_opcode_aliases
[i
].primary
;
4452 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4453 PTR val
= hash_find (op_hash
, name
);
4456 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4457 retval
= hash_insert (op_hash
, alias
, val
);
4459 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4462 /* In MRI mode, all unsized branches are variable sized. Normally,
4463 they are word sized. */
4466 static struct m68k_opcode_alias mri_aliases
[] =
4487 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4490 const char *name
= mri_aliases
[i
].primary
;
4491 const char *alias
= mri_aliases
[i
].alias
;
4492 PTR val
= hash_find (op_hash
, name
);
4495 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4496 retval
= hash_jam (op_hash
, alias
, val
);
4498 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4502 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4504 notend_table
[i
] = 0;
4505 alt_notend_table
[i
] = 0;
4508 notend_table
[','] = 1;
4509 notend_table
['{'] = 1;
4510 notend_table
['}'] = 1;
4511 alt_notend_table
['a'] = 1;
4512 alt_notend_table
['A'] = 1;
4513 alt_notend_table
['d'] = 1;
4514 alt_notend_table
['D'] = 1;
4515 alt_notend_table
['#'] = 1;
4516 alt_notend_table
['&'] = 1;
4517 alt_notend_table
['f'] = 1;
4518 alt_notend_table
['F'] = 1;
4519 #ifdef REGISTER_PREFIX
4520 alt_notend_table
[REGISTER_PREFIX
] = 1;
4523 /* We need to put '(' in alt_notend_table to handle
4524 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4525 alt_notend_table
['('] = 1;
4527 /* We need to put '@' in alt_notend_table to handle
4528 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4529 alt_notend_table
['@'] = 1;
4531 /* We need to put digits in alt_notend_table to handle
4532 bfextu %d0{24:1},%d0 */
4533 alt_notend_table
['0'] = 1;
4534 alt_notend_table
['1'] = 1;
4535 alt_notend_table
['2'] = 1;
4536 alt_notend_table
['3'] = 1;
4537 alt_notend_table
['4'] = 1;
4538 alt_notend_table
['5'] = 1;
4539 alt_notend_table
['6'] = 1;
4540 alt_notend_table
['7'] = 1;
4541 alt_notend_table
['8'] = 1;
4542 alt_notend_table
['9'] = 1;
4544 #ifndef MIT_SYNTAX_ONLY
4545 /* Insert pseudo ops, these have to go into the opcode table since
4546 gas expects pseudo ops to start with a dot. */
4550 while (mote_pseudo_table
[n
].poc_name
)
4552 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4553 hash_insert (op_hash
,
4554 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4555 hack
->m_operands
= 0;
4565 record_alignment (text_section
, 2);
4566 record_alignment (data_section
, 2);
4567 record_alignment (bss_section
, 2);
4572 /* This is called when a label is defined. */
4575 m68k_frob_label (symbolS
*sym
)
4577 struct label_line
*n
;
4579 n
= (struct label_line
*) xmalloc (sizeof *n
);
4582 as_where (&n
->file
, &n
->line
);
4588 dwarf2_emit_label (sym
);
4592 /* This is called when a value that is not an instruction is emitted. */
4595 m68k_flush_pending_output (void)
4597 current_label
= NULL
;
4600 /* This is called at the end of the assembly, when the final value of
4601 the label is known. We warn if this is a text symbol aligned at an
4605 m68k_frob_symbol (symbolS
*sym
)
4607 if (S_GET_SEGMENT (sym
) == reg_section
4608 && (int) S_GET_VALUE (sym
) < 0)
4610 S_SET_SEGMENT (sym
, absolute_section
);
4611 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4613 else if ((S_GET_VALUE (sym
) & 1) != 0)
4615 struct label_line
*l
;
4617 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4619 if (l
->label
== sym
)
4622 as_warn_where (l
->file
, l
->line
,
4623 _("text label `%s' aligned to odd boundary"),
4631 /* This is called if we go in or out of MRI mode because of the .mri
4635 m68k_mri_mode_change (int on
)
4639 if (! flag_reg_prefix_optional
)
4641 flag_reg_prefix_optional
= 1;
4642 #ifdef REGISTER_PREFIX
4647 if (! m68k_rel32_from_cmdline
)
4652 if (! reg_prefix_optional_seen
)
4654 #ifdef REGISTER_PREFIX_OPTIONAL
4655 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4657 flag_reg_prefix_optional
= 0;
4659 #ifdef REGISTER_PREFIX
4664 if (! m68k_rel32_from_cmdline
)
4669 /* Equal to MAX_PRECISION in atof-ieee.c. */
4670 #define MAX_LITTLENUMS 6
4672 /* Turn a string in input_line_pointer into a floating point constant
4673 of type TYPE, and store the appropriate bytes in *LITP. The number
4674 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4675 returned, or NULL on OK. */
4678 md_atof (int type
, char *litP
, int *sizeP
)
4681 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4682 LITTLENUM_TYPE
*wordP
;
4713 return _("Bad call to MD_ATOF()");
4715 t
= atof_ieee (input_line_pointer
, type
, words
);
4717 input_line_pointer
= t
;
4719 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4720 for (wordP
= words
; prec
--;)
4722 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4723 litP
+= sizeof (LITTLENUM_TYPE
);
4729 md_number_to_chars (char *buf
, valueT val
, int n
)
4731 number_to_chars_bigendian (buf
, val
, n
);
4735 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4737 offsetT val
= *valP
;
4738 addressT upper_limit
;
4739 offsetT lower_limit
;
4741 /* This is unnecessary but it convinces the native rs6000 compiler
4742 to generate the code we want. */
4743 char *buf
= fixP
->fx_frag
->fr_literal
;
4744 buf
+= fixP
->fx_where
;
4745 /* End ibm compiler workaround. */
4749 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4755 memset (buf
, 0, fixP
->fx_size
);
4756 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4758 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4759 && !S_IS_DEFINED (fixP
->fx_addsy
)
4760 && !S_IS_WEAK (fixP
->fx_addsy
))
4761 S_SET_WEAK (fixP
->fx_addsy
);
4764 #elif defined(OBJ_AOUT)
4765 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4766 if (fixP
->fx_addsy
&& S_IS_WEAK (fixP
->fx_addsy
))
4768 memset (buf
, 0, fixP
->fx_size
);
4769 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4774 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4775 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4778 switch (fixP
->fx_size
)
4780 /* The cast to offsetT below are necessary to make code
4781 correct for machines where ints are smaller than offsetT. */
4785 lower_limit
= - (offsetT
) 0x80;
4788 *buf
++ = (val
>> 8);
4790 upper_limit
= 0x7fff;
4791 lower_limit
= - (offsetT
) 0x8000;
4794 *buf
++ = (val
>> 24);
4795 *buf
++ = (val
>> 16);
4796 *buf
++ = (val
>> 8);
4798 upper_limit
= 0x7fffffff;
4799 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4802 BAD_CASE (fixP
->fx_size
);
4805 /* Fix up a negative reloc. */
4806 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4808 fixP
->fx_addsy
= fixP
->fx_subsy
;
4809 fixP
->fx_subsy
= NULL
;
4813 /* For non-pc-relative values, it's conceivable we might get something
4814 like "0xff" for a byte field. So extend the upper part of the range
4815 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4816 so that we can do any range checking at all. */
4817 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4818 upper_limit
= upper_limit
* 2 + 1;
4820 if ((addressT
) val
> upper_limit
4821 && (val
> 0 || val
< lower_limit
))
4822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4823 _("value %ld out of range"), (long)val
);
4825 /* A one byte PC-relative reloc means a short branch. We can't use
4826 a short branch with a value of 0 or -1, because those indicate
4827 different opcodes (branches with longer offsets). fixup_segment
4828 in write.c may have clobbered fx_pcrel, so we need to examine the
4831 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4832 && fixP
->fx_size
== 1
4833 && (fixP
->fx_addsy
== NULL
4834 || S_IS_DEFINED (fixP
->fx_addsy
))
4835 && (val
== 0 || val
== -1))
4836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4837 _("invalid byte branch offset"));
4840 /* *fragP has been relaxed to its final size, and now needs to have
4841 the bytes inside it modified to conform to the new size There is UGLY
4845 md_convert_frag_1 (fragS
*fragP
)
4850 /* Address in object code of the displacement. */
4851 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4853 /* Address in gas core of the place to store the displacement. */
4854 /* This convinces the native rs6000 compiler to generate the code we
4856 register char *buffer_address
= fragP
->fr_literal
;
4857 buffer_address
+= fragP
->fr_fix
;
4858 /* End ibm compiler workaround. */
4860 /* The displacement of the address, from current location. */
4861 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4862 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4864 switch (fragP
->fr_subtype
)
4866 case TAB (BRANCHBWL
, BYTE
):
4867 case TAB (BRABSJUNC
, BYTE
):
4868 case TAB (BRABSJCOND
, BYTE
):
4869 case TAB (BRANCHBW
, BYTE
):
4870 know (issbyte (disp
));
4872 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4873 _("short branch with zero offset: use :w"));
4874 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4875 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4876 fixP
->fx_pcrel_adjust
= -1;
4878 case TAB (BRANCHBWL
, SHORT
):
4879 case TAB (BRABSJUNC
, SHORT
):
4880 case TAB (BRABSJCOND
, SHORT
):
4881 case TAB (BRANCHBW
, SHORT
):
4882 fragP
->fr_opcode
[1] = 0x00;
4883 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4884 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4887 case TAB (BRANCHBWL
, LONG
):
4888 fragP
->fr_opcode
[1] = (char) 0xFF;
4889 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4890 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4893 case TAB (BRABSJUNC
, LONG
):
4894 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4896 if (flag_keep_pcrel
)
4897 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4898 _("Conversion of PC relative BSR to absolute JSR"));
4899 fragP
->fr_opcode
[0] = 0x4E;
4900 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4901 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4902 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4905 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4907 if (flag_keep_pcrel
)
4908 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4909 _("Conversion of PC relative branch to absolute jump"));
4910 fragP
->fr_opcode
[0] = 0x4E;
4911 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4912 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4913 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4918 /* This cannot happen, because jbsr and jbra are the only two
4919 unconditional branches. */
4923 case TAB (BRABSJCOND
, LONG
):
4924 if (flag_keep_pcrel
)
4925 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4926 _("Conversion of PC relative conditional branch to absolute jump"));
4928 /* Only Bcc 68000 instructions can come here
4929 Change bcc into b!cc/jmp absl long. */
4930 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4931 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4933 /* JF: these used to be fr_opcode[2,3], but they may be in a
4934 different frag, in which case referring to them is a no-no.
4935 Only fr_opcode[0,1] are guaranteed to work. */
4936 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4937 *buffer_address
++ = (char) 0xf9;
4938 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4939 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4940 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4943 case TAB (FBRANCH
, SHORT
):
4944 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4945 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4946 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4949 case TAB (FBRANCH
, LONG
):
4950 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4951 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4952 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4955 case TAB (DBCCLBR
, SHORT
):
4956 case TAB (DBCCABSJ
, SHORT
):
4957 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4958 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4961 case TAB (DBCCLBR
, LONG
):
4962 /* Only DBcc instructions can come here.
4963 Change dbcc into dbcc/bral.
4964 JF: these used to be fr_opcode[2-7], but that's wrong. */
4965 if (flag_keep_pcrel
)
4966 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4967 _("Conversion of DBcc to absolute jump"));
4969 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4970 *buffer_address
++ = 0x04;
4971 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4972 *buffer_address
++ = 0x06;
4973 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4974 *buffer_address
++ = (char) 0xff;
4976 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4977 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4978 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4981 case TAB (DBCCABSJ
, LONG
):
4982 /* Only DBcc instructions can come here.
4983 Change dbcc into dbcc/jmp.
4984 JF: these used to be fr_opcode[2-7], but that's wrong. */
4985 if (flag_keep_pcrel
)
4986 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4987 _("Conversion of PC relative conditional branch to absolute jump"));
4989 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4990 *buffer_address
++ = 0x04;
4991 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4992 *buffer_address
++ = 0x06;
4993 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4994 *buffer_address
++ = (char) 0xf9;
4996 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4997 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4998 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5001 case TAB (PCREL1632
, SHORT
):
5002 fragP
->fr_opcode
[1] &= ~0x3F;
5003 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
5004 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5005 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5008 case TAB (PCREL1632
, LONG
):
5009 /* Already set to mode 7.3; this indicates: PC indirect with
5010 suppressed index, 32-bit displacement. */
5011 *buffer_address
++ = 0x01;
5012 *buffer_address
++ = 0x70;
5014 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5015 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5016 fixP
->fx_pcrel_adjust
= 2;
5019 case TAB (PCINDEX
, BYTE
):
5020 assert (fragP
->fr_fix
>= 2);
5021 buffer_address
[-2] &= ~1;
5022 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5023 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5024 fixP
->fx_pcrel_adjust
= 1;
5026 case TAB (PCINDEX
, SHORT
):
5027 assert (fragP
->fr_fix
>= 2);
5028 buffer_address
[-2] |= 0x1;
5029 buffer_address
[-1] = 0x20;
5030 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5031 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5032 fixP
->fx_pcrel_adjust
= 2;
5035 case TAB (PCINDEX
, LONG
):
5036 assert (fragP
->fr_fix
>= 2);
5037 buffer_address
[-2] |= 0x1;
5038 buffer_address
[-1] = 0x30;
5039 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5040 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5041 fixP
->fx_pcrel_adjust
= 2;
5044 case TAB (ABSTOPCREL
, SHORT
):
5045 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5046 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5049 case TAB (ABSTOPCREL
, LONG
):
5050 if (flag_keep_pcrel
)
5051 as_fatal (_("Conversion of PC relative displacement to absolute"));
5052 /* The thing to do here is force it to ABSOLUTE LONG, since
5053 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5054 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
5056 fragP
->fr_opcode
[1] &= ~0x3F;
5057 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
5058 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5059 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5065 fixP
->fx_file
= fragP
->fr_file
;
5066 fixP
->fx_line
= fragP
->fr_line
;
5071 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5072 segT sec ATTRIBUTE_UNUSED
,
5075 md_convert_frag_1 (fragP
);
5078 /* Force truly undefined symbols to their maximum size, and generally set up
5079 the frag list to be relaxed
5082 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
5084 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5085 switch (fragP
->fr_subtype
)
5087 case TAB (BRANCHBWL
, SZ_UNDEF
):
5088 case TAB (BRABSJUNC
, SZ_UNDEF
):
5089 case TAB (BRABSJCOND
, SZ_UNDEF
):
5091 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5092 && relaxable_symbol (fragP
->fr_symbol
))
5094 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5096 else if (flag_short_refs
)
5098 /* Symbol is undefined and we want short ref. */
5099 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5103 /* Symbol is still undefined. Make it LONG. */
5104 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5109 case TAB (BRANCHBW
, SZ_UNDEF
):
5111 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5112 && relaxable_symbol (fragP
->fr_symbol
))
5114 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5118 /* Symbol is undefined and we don't have long branches. */
5119 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5124 case TAB (FBRANCH
, SZ_UNDEF
):
5125 case TAB (DBCCLBR
, SZ_UNDEF
):
5126 case TAB (DBCCABSJ
, SZ_UNDEF
):
5127 case TAB (PCREL1632
, SZ_UNDEF
):
5129 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5130 && relaxable_symbol (fragP
->fr_symbol
))
5133 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5137 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5142 case TAB (PCINDEX
, SZ_UNDEF
):
5143 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5144 && relaxable_symbol (fragP
->fr_symbol
)))
5146 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5150 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5154 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5156 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5157 && relaxable_symbol (fragP
->fr_symbol
)))
5159 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5163 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5172 /* Now that SZ_UNDEF are taken care of, check others. */
5173 switch (fragP
->fr_subtype
)
5175 case TAB (BRANCHBWL
, BYTE
):
5176 case TAB (BRABSJUNC
, BYTE
):
5177 case TAB (BRABSJCOND
, BYTE
):
5178 case TAB (BRANCHBW
, BYTE
):
5179 /* We can't do a short jump to the next instruction, so in that
5180 case we force word mode. If the symbol is at the start of a
5181 frag, and it is the next frag with any data in it (usually
5182 this is just the next frag, but assembler listings may
5183 introduce empty frags), we must use word mode. */
5184 if (fragP
->fr_symbol
)
5188 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5189 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5193 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5197 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5204 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5207 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5208 /* the bit-field entries in the relocation_info struct plays hell
5209 with the byte-order problems of cross-assembly. So as a hack,
5210 I added this mach. dependent ri twiddler. Ugly, but it gets
5212 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5213 are symbolnum, most sig. byte first. Last byte is broken up with
5214 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5215 nibble as nuthin. (on Sun 3 at least) */
5216 /* Translate the internal relocation information into target-specific
5220 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5223 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5224 /* Now the fun stuff. */
5225 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5226 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5227 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5228 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5229 | ((ri
->r_length
<< 5) & 0x60)
5230 | ((ri
->r_extern
<< 4) & 0x10));
5235 #endif /* OBJ_AOUT or OBJ_BOUT */
5237 #ifndef WORKING_DOT_WORD
5238 int md_short_jump_size
= 4;
5239 int md_long_jump_size
= 6;
5242 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5243 fragS
*frag ATTRIBUTE_UNUSED
,
5244 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5248 offset
= to_addr
- (from_addr
+ 2);
5250 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5251 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5255 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5256 fragS
*frag
, symbolS
*to_symbol
)
5260 if (!HAVE_LONG_BRANCH (current_architecture
))
5262 if (flag_keep_pcrel
)
5263 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5264 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5265 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5266 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5267 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5272 offset
= to_addr
- (from_addr
+ 2);
5273 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5274 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5280 /* Different values of OK tell what its OK to return. Things that
5281 aren't OK are an error (what a shock, no?)
5284 10: Absolute 1:8 only
5285 20: Absolute 0:7 only
5286 30: absolute 0:15 only
5287 40: Absolute 0:31 only
5288 50: absolute 0:127 only
5289 55: absolute -64:63 only
5290 60: absolute -128:127 only
5291 65: absolute 0:511 only
5292 70: absolute 0:4095 only
5293 80: absolute -1, 1:7 only
5297 get_num (struct m68k_exp
*exp
, int ok
)
5299 if (exp
->exp
.X_op
== O_absent
)
5301 /* Do the same thing the VAX asm does. */
5302 op (exp
) = O_constant
;
5308 as_warn (_("expression out of range: defaulting to 1"));
5312 else if (exp
->exp
.X_op
== O_constant
)
5317 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5319 as_warn (_("expression out of range: defaulting to 1"));
5324 if ((valueT
) TRUNC (offs (exp
)) > 7)
5328 if ((valueT
) TRUNC (offs (exp
)) > 15)
5332 if ((valueT
) TRUNC (offs (exp
)) > 32)
5336 if ((valueT
) TRUNC (offs (exp
)) > 127)
5340 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5344 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5348 if ((valueT
) TRUNC (offs (exp
)) > 511)
5352 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5355 as_warn (_("expression out of range: defaulting to 0"));
5360 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5361 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5363 as_warn (_("expression out of range: defaulting to 1"));
5371 else if (exp
->exp
.X_op
== O_big
)
5373 if (offs (exp
) <= 0 /* flonum. */
5374 && (ok
== 90 /* no bignums */
5375 || (ok
> 10 /* Small-int ranges including 0 ok. */
5376 /* If we have a flonum zero, a zero integer should
5377 do as well (e.g., in moveq). */
5378 && generic_floating_point_number
.exponent
== 0
5379 && generic_floating_point_number
.low
[0] == 0)))
5381 /* HACK! Turn it into a long. */
5382 LITTLENUM_TYPE words
[6];
5384 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5385 op (exp
) = O_constant
;
5388 offs (exp
) = words
[1] | (words
[0] << 16);
5392 op (exp
) = O_constant
;
5395 offs (exp
) = (ok
== 10) ? 1 : 0;
5396 as_warn (_("Can't deal with expression; defaulting to %ld"),
5402 if (ok
>= 10 && ok
<= 80)
5404 op (exp
) = O_constant
;
5407 offs (exp
) = (ok
== 10) ? 1 : 0;
5408 as_warn (_("Can't deal with expression; defaulting to %ld"),
5413 if (exp
->size
!= SIZE_UNSPEC
)
5421 if (!isbyte (offs (exp
)))
5422 as_warn (_("expression doesn't fit in BYTE"));
5425 if (!isword (offs (exp
)))
5426 as_warn (_("expression doesn't fit in WORD"));
5434 /* These are the back-ends for the various machine dependent pseudo-ops. */
5437 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5439 subseg_set (data_section
, 1);
5440 demand_empty_rest_of_line ();
5444 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5446 subseg_set (data_section
, 2);
5447 demand_empty_rest_of_line ();
5451 s_bss (int ignore ATTRIBUTE_UNUSED
)
5453 /* We don't support putting frags in the BSS segment, we fake it
5454 by marking in_bss, then looking at s_skip for clues. */
5456 subseg_set (bss_section
, 0);
5457 demand_empty_rest_of_line ();
5461 s_even (int ignore ATTRIBUTE_UNUSED
)
5464 register long temp_fill
;
5466 temp
= 1; /* JF should be 2? */
5467 temp_fill
= get_absolute_expression ();
5468 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5469 frag_align (temp
, (int) temp_fill
, 0);
5470 demand_empty_rest_of_line ();
5471 record_alignment (now_seg
, temp
);
5475 s_proc (int ignore ATTRIBUTE_UNUSED
)
5477 demand_empty_rest_of_line ();
5480 /* Pseudo-ops handled for MRI compatibility. */
5482 /* This function returns non-zero if the argument is a conditional
5483 pseudo-op. This is called when checking whether a pending
5484 alignment is needed. */
5487 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5489 return (pop
->poc_handler
== s_mri_if
5490 || pop
->poc_handler
== s_mri_else
);
5493 /* Handle an MRI style chip specification. */
5502 s
= input_line_pointer
;
5503 /* We can't use get_symbol_end since the processor names are not proper
5505 while (is_part_of_name (c
= *input_line_pointer
++))
5507 *--input_line_pointer
= 0;
5508 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5509 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5511 if (!m68k_cpus
[i
].name
)
5513 as_bad (_("%s: unrecognized processor name"), s
);
5514 *input_line_pointer
= c
;
5515 ignore_rest_of_line ();
5518 *input_line_pointer
= c
;
5520 if (*input_line_pointer
== '/')
5521 current_architecture
= 0;
5523 current_architecture
&= m68881
| m68851
;
5524 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5525 control_regs
= m68k_cpus
[i
].control_regs
;
5527 while (*input_line_pointer
== '/')
5529 ++input_line_pointer
;
5530 s
= input_line_pointer
;
5531 /* We can't use get_symbol_end since the processor names are not
5533 while (is_part_of_name (c
= *input_line_pointer
++))
5535 *--input_line_pointer
= 0;
5536 if (strcmp (s
, "68881") == 0)
5537 current_architecture
|= m68881
;
5538 else if (strcmp (s
, "68851") == 0)
5539 current_architecture
|= m68851
;
5540 *input_line_pointer
= c
;
5544 /* The MRI CHIP pseudo-op. */
5547 s_chip (int ignore ATTRIBUTE_UNUSED
)
5553 stop
= mri_comment_field (&stopc
);
5556 mri_comment_end (stop
, stopc
);
5557 demand_empty_rest_of_line ();
5560 /* The MRI FOPT pseudo-op. */
5563 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5567 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5571 input_line_pointer
+= 3;
5572 temp
= get_absolute_expression ();
5573 if (temp
< 0 || temp
> 7)
5574 as_bad (_("bad coprocessor id"));
5576 m68k_float_copnum
= COP0
+ temp
;
5580 as_bad (_("unrecognized fopt option"));
5581 ignore_rest_of_line ();
5585 demand_empty_rest_of_line ();
5588 /* The structure used to handle the MRI OPT pseudo-op. */
5592 /* The name of the option. */
5595 /* If this is not NULL, just call this function. The first argument
5596 is the ARG field of this structure, the second argument is
5597 whether the option was negated. */
5598 void (*pfn
) (int arg
, int on
);
5600 /* If this is not NULL, and the PFN field is NULL, set the variable
5601 this points to. Set it to the ARG field if the option was not
5602 negated, and the NOTARG field otherwise. */
5605 /* The value to pass to PFN or to assign to *PVAR. */
5608 /* The value to assign to *PVAR if the option is negated. If PFN is
5609 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5610 the option may not be negated. */
5614 /* The table used to handle the MRI OPT pseudo-op. */
5616 static void skip_to_comma (int, int);
5617 static void opt_nest (int, int);
5618 static void opt_chip (int, int);
5619 static void opt_list (int, int);
5620 static void opt_list_symbols (int, int);
5622 static const struct opt_action opt_table
[] =
5624 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5626 /* We do relaxing, so there is little use for these options. */
5627 { "b", 0, 0, 0, 0 },
5628 { "brs", 0, 0, 0, 0 },
5629 { "brb", 0, 0, 0, 0 },
5630 { "brl", 0, 0, 0, 0 },
5631 { "brw", 0, 0, 0, 0 },
5633 { "c", 0, 0, 0, 0 },
5634 { "cex", 0, 0, 0, 0 },
5635 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5636 { "cl", 0, 0, 0, 0 },
5637 { "cre", 0, 0, 0, 0 },
5638 { "d", 0, &flag_keep_locals
, 1, 0 },
5639 { "e", 0, 0, 0, 0 },
5640 { "f", 0, &flag_short_refs
, 1, 0 },
5641 { "frs", 0, &flag_short_refs
, 1, 0 },
5642 { "frl", 0, &flag_short_refs
, 0, 1 },
5643 { "g", 0, 0, 0, 0 },
5644 { "i", 0, 0, 0, 0 },
5645 { "m", 0, 0, 0, 0 },
5646 { "mex", 0, 0, 0, 0 },
5647 { "mc", 0, 0, 0, 0 },
5648 { "md", 0, 0, 0, 0 },
5649 { "nest", opt_nest
, 0, 0, 0 },
5650 { "next", skip_to_comma
, 0, 0, 0 },
5651 { "o", 0, 0, 0, 0 },
5652 { "old", 0, 0, 0, 0 },
5653 { "op", skip_to_comma
, 0, 0, 0 },
5654 { "pco", 0, 0, 0, 0 },
5655 { "p", opt_chip
, 0, 0, 0 },
5656 { "pcr", 0, 0, 0, 0 },
5657 { "pcs", 0, 0, 0, 0 },
5658 { "r", 0, 0, 0, 0 },
5659 { "quick", 0, &m68k_quick
, 1, 0 },
5660 { "rel32", 0, &m68k_rel32
, 1, 0 },
5661 { "s", opt_list
, 0, 0, 0 },
5662 { "t", opt_list_symbols
, 0, 0, 0 },
5663 { "w", 0, &flag_no_warnings
, 0, 1 },
5667 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5669 /* The MRI OPT pseudo-op. */
5672 s_opt (int ignore ATTRIBUTE_UNUSED
)
5680 const struct opt_action
*o
;
5685 if (*input_line_pointer
== '-')
5687 ++input_line_pointer
;
5690 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5692 input_line_pointer
+= 2;
5696 s
= input_line_pointer
;
5697 c
= get_symbol_end ();
5699 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5701 if (strcasecmp (s
, o
->name
) == 0)
5705 /* Restore input_line_pointer now in case the option
5707 *input_line_pointer
= c
;
5708 (*o
->pfn
) (o
->arg
, t
);
5710 else if (o
->pvar
!= NULL
)
5712 if (! t
&& o
->arg
== o
->notarg
)
5713 as_bad (_("option `%s' may not be negated"), s
);
5714 *input_line_pointer
= c
;
5715 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5718 *input_line_pointer
= c
;
5724 as_bad (_("option `%s' not recognized"), s
);
5725 *input_line_pointer
= c
;
5728 while (*input_line_pointer
++ == ',');
5730 /* Move back to terminating character. */
5731 --input_line_pointer
;
5732 demand_empty_rest_of_line ();
5735 /* Skip ahead to a comma. This is used for OPT options which we do
5736 not support and which take arguments. */
5739 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5741 while (*input_line_pointer
!= ','
5742 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5743 ++input_line_pointer
;
5746 /* Handle the OPT NEST=depth option. */
5749 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5751 if (*input_line_pointer
!= '=')
5753 as_bad (_("bad format of OPT NEST=depth"));
5757 ++input_line_pointer
;
5758 max_macro_nest
= get_absolute_expression ();
5761 /* Handle the OPT P=chip option. */
5764 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5766 if (*input_line_pointer
!= '=')
5768 /* This is just OPT P, which we do not support. */
5772 ++input_line_pointer
;
5776 /* Handle the OPT S option. */
5779 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5784 /* Handle the OPT T option. */
5787 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5790 listing
|= LISTING_SYMBOLS
;
5792 listing
&= ~LISTING_SYMBOLS
;
5795 /* Handle the MRI REG pseudo-op. */
5798 s_reg (int ignore ATTRIBUTE_UNUSED
)
5807 if (line_label
== NULL
)
5809 as_bad (_("missing label"));
5810 ignore_rest_of_line ();
5815 stop
= mri_comment_field (&stopc
);
5819 s
= input_line_pointer
;
5820 while (ISALNUM (*input_line_pointer
)
5821 #ifdef REGISTER_PREFIX
5822 || *input_line_pointer
== REGISTER_PREFIX
5824 || *input_line_pointer
== '/'
5825 || *input_line_pointer
== '-')
5826 ++input_line_pointer
;
5827 c
= *input_line_pointer
;
5828 *input_line_pointer
= '\0';
5830 if (m68k_ip_op (s
, &rop
) != 0)
5832 if (rop
.error
== NULL
)
5833 as_bad (_("bad register list"));
5835 as_bad (_("bad register list: %s"), rop
.error
);
5836 *input_line_pointer
= c
;
5837 ignore_rest_of_line ();
5841 *input_line_pointer
= c
;
5843 if (rop
.mode
== REGLST
)
5845 else if (rop
.mode
== DREG
)
5846 mask
= 1 << (rop
.reg
- DATA0
);
5847 else if (rop
.mode
== AREG
)
5848 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5849 else if (rop
.mode
== FPREG
)
5850 mask
= 1 << (rop
.reg
- FP0
+ 16);
5851 else if (rop
.mode
== CONTROL
5854 else if (rop
.mode
== CONTROL
5857 else if (rop
.mode
== CONTROL
5862 as_bad (_("bad register list"));
5863 ignore_rest_of_line ();
5867 S_SET_SEGMENT (line_label
, reg_section
);
5868 S_SET_VALUE (line_label
, ~mask
);
5869 symbol_set_frag (line_label
, &zero_address_frag
);
5872 mri_comment_end (stop
, stopc
);
5874 demand_empty_rest_of_line ();
5877 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5881 struct save_opts
*next
;
5883 int symbols_case_sensitive
;
5887 const enum m68k_register
*control_regs
;
5892 /* FIXME: We don't save OPT S. */
5895 /* This variable holds the stack of saved options. */
5897 static struct save_opts
*save_stack
;
5899 /* The MRI SAVE pseudo-op. */
5902 s_save (int ignore ATTRIBUTE_UNUSED
)
5904 struct save_opts
*s
;
5906 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5907 s
->abspcadd
= m68k_abspcadd
;
5908 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5909 s
->keep_locals
= flag_keep_locals
;
5910 s
->short_refs
= flag_short_refs
;
5911 s
->architecture
= current_architecture
;
5912 s
->control_regs
= control_regs
;
5913 s
->quick
= m68k_quick
;
5914 s
->rel32
= m68k_rel32
;
5915 s
->listing
= listing
;
5916 s
->no_warnings
= flag_no_warnings
;
5918 s
->next
= save_stack
;
5921 demand_empty_rest_of_line ();
5924 /* The MRI RESTORE pseudo-op. */
5927 s_restore (int ignore ATTRIBUTE_UNUSED
)
5929 struct save_opts
*s
;
5931 if (save_stack
== NULL
)
5933 as_bad (_("restore without save"));
5934 ignore_rest_of_line ();
5939 save_stack
= s
->next
;
5941 m68k_abspcadd
= s
->abspcadd
;
5942 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5943 flag_keep_locals
= s
->keep_locals
;
5944 flag_short_refs
= s
->short_refs
;
5945 current_architecture
= s
->architecture
;
5946 control_regs
= s
->control_regs
;
5947 m68k_quick
= s
->quick
;
5948 m68k_rel32
= s
->rel32
;
5949 listing
= s
->listing
;
5950 flag_no_warnings
= s
->no_warnings
;
5954 demand_empty_rest_of_line ();
5957 /* Types of MRI structured control directives. */
5959 enum mri_control_type
5967 /* This structure is used to stack the MRI structured control
5970 struct mri_control_info
5972 /* The directive within which this one is enclosed. */
5973 struct mri_control_info
*outer
;
5975 /* The type of directive. */
5976 enum mri_control_type type
;
5978 /* Whether an ELSE has been in an IF. */
5981 /* The add or sub statement at the end of a FOR. */
5984 /* The label of the top of a FOR or REPEAT loop. */
5987 /* The label to jump to for the next iteration, or the else
5988 expression of a conditional. */
5991 /* The label to jump to to break out of the loop, or the label past
5992 the end of a conditional. */
5996 /* The stack of MRI structured control directives. */
5998 static struct mri_control_info
*mri_control_stack
;
6000 /* The current MRI structured control directive index number, used to
6001 generate label names. */
6003 static int mri_control_index
;
6005 /* Assemble an instruction for an MRI structured control directive. */
6008 mri_assemble (char *str
)
6012 /* md_assemble expects the opcode to be in lower case. */
6013 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
6019 /* Generate a new MRI label structured control directive label name. */
6022 mri_control_label (void)
6026 n
= (char *) xmalloc (20);
6027 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
6028 ++mri_control_index
;
6032 /* Create a new MRI structured control directive. */
6034 static struct mri_control_info
*
6035 push_mri_control (enum mri_control_type type
)
6037 struct mri_control_info
*n
;
6039 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
6043 if (type
== mri_if
|| type
== mri_while
)
6046 n
->top
= mri_control_label ();
6047 n
->next
= mri_control_label ();
6048 n
->bottom
= mri_control_label ();
6050 n
->outer
= mri_control_stack
;
6051 mri_control_stack
= n
;
6056 /* Pop off the stack of MRI structured control directives. */
6059 pop_mri_control (void)
6061 struct mri_control_info
*n
;
6063 n
= mri_control_stack
;
6064 mri_control_stack
= n
->outer
;
6072 /* Recognize a condition code in an MRI structured control expression. */
6075 parse_mri_condition (int *pcc
)
6079 know (*input_line_pointer
== '<');
6081 ++input_line_pointer
;
6082 c1
= *input_line_pointer
++;
6083 c2
= *input_line_pointer
++;
6085 if (*input_line_pointer
!= '>')
6087 as_bad (_("syntax error in structured control directive"));
6091 ++input_line_pointer
;
6097 *pcc
= (c1
<< 8) | c2
;
6102 /* Parse a single operand in an MRI structured control expression. */
6105 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
6106 char **rightstart
, char **rightstop
)
6118 if (*input_line_pointer
== '<')
6120 /* It's just a condition code. */
6121 return parse_mri_condition (pcc
);
6124 /* Look ahead for the condition code. */
6125 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6127 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6132 as_bad (_("missing condition code in structured control directive"));
6136 *leftstart
= input_line_pointer
;
6138 if (*leftstop
> *leftstart
6139 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6142 input_line_pointer
= s
;
6143 if (! parse_mri_condition (pcc
))
6146 /* Look ahead for AND or OR or end of line. */
6147 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6149 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6150 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6152 if ((s
== input_line_pointer
6155 && ((strncasecmp (s
, "AND", 3) == 0
6156 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6157 || (strncasecmp (s
, "OR", 2) == 0
6158 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6162 *rightstart
= input_line_pointer
;
6164 if (*rightstop
> *rightstart
6165 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6168 input_line_pointer
= s
;
6173 #define MCC(b1, b2) (((b1) << 8) | (b2))
6175 /* Swap the sense of a condition. This changes the condition so that
6176 it generates the same result when the operands are swapped. */
6179 swap_mri_condition (int cc
)
6183 case MCC ('h', 'i'): return MCC ('c', 's');
6184 case MCC ('l', 's'): return MCC ('c', 'c');
6185 /* <HS> is an alias for <CC>. */
6186 case MCC ('h', 's'):
6187 case MCC ('c', 'c'): return MCC ('l', 's');
6188 /* <LO> is an alias for <CS>. */
6189 case MCC ('l', 'o'):
6190 case MCC ('c', 's'): return MCC ('h', 'i');
6191 case MCC ('p', 'l'): return MCC ('m', 'i');
6192 case MCC ('m', 'i'): return MCC ('p', 'l');
6193 case MCC ('g', 'e'): return MCC ('l', 'e');
6194 case MCC ('l', 't'): return MCC ('g', 't');
6195 case MCC ('g', 't'): return MCC ('l', 't');
6196 case MCC ('l', 'e'): return MCC ('g', 'e');
6197 /* Issue a warning for conditions we can not swap. */
6198 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6199 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6200 case MCC ('v', 'c'):
6201 case MCC ('v', 's'):
6203 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6204 (char) (cc
>> 8), (char) (cc
));
6210 /* Reverse the sense of a condition. */
6213 reverse_mri_condition (int cc
)
6217 case MCC ('h', 'i'): return MCC ('l', 's');
6218 case MCC ('l', 's'): return MCC ('h', 'i');
6219 /* <HS> is an alias for <CC> */
6220 case MCC ('h', 's'): return MCC ('l', 'o');
6221 case MCC ('c', 'c'): return MCC ('c', 's');
6222 /* <LO> is an alias for <CS> */
6223 case MCC ('l', 'o'): return MCC ('h', 's');
6224 case MCC ('c', 's'): return MCC ('c', 'c');
6225 case MCC ('n', 'e'): return MCC ('e', 'q');
6226 case MCC ('e', 'q'): return MCC ('n', 'e');
6227 case MCC ('v', 'c'): return MCC ('v', 's');
6228 case MCC ('v', 's'): return MCC ('v', 'c');
6229 case MCC ('p', 'l'): return MCC ('m', 'i');
6230 case MCC ('m', 'i'): return MCC ('p', 'l');
6231 case MCC ('g', 'e'): return MCC ('l', 't');
6232 case MCC ('l', 't'): return MCC ('g', 'e');
6233 case MCC ('g', 't'): return MCC ('l', 'e');
6234 case MCC ('l', 'e'): return MCC ('g', 't');
6239 /* Build an MRI structured control expression. This generates test
6240 and branch instructions. It goes to TRUELAB if the condition is
6241 true, and to FALSELAB if the condition is false. Exactly one of
6242 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6243 is the size qualifier for the expression. EXTENT is the size to
6244 use for the branch. */
6247 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6248 char *rightstart
, char *rightstop
,
6249 const char *truelab
, const char *falselab
,
6255 if (leftstart
!= NULL
)
6257 struct m68k_op leftop
, rightop
;
6260 /* Swap the compare operands, if necessary, to produce a legal
6261 m68k compare instruction. Comparing a register operand with
6262 a non-register operand requires the register to be on the
6263 right (cmp, cmpa). Comparing an immediate value with
6264 anything requires the immediate value to be on the left
6269 (void) m68k_ip_op (leftstart
, &leftop
);
6274 (void) m68k_ip_op (rightstart
, &rightop
);
6277 if (rightop
.mode
== IMMED
6278 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6279 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6283 /* Correct conditional handling:
6284 if #1 <lt> d0 then ;means if (1 < d0)
6290 cmp #1,d0 if we do *not* swap the operands
6291 bgt true we need the swapped condition!
6298 leftstart
= rightstart
;
6301 leftstop
= rightstop
;
6306 cc
= swap_mri_condition (cc
);
6310 if (truelab
== NULL
)
6312 cc
= reverse_mri_condition (cc
);
6316 if (leftstart
!= NULL
)
6318 buf
= (char *) xmalloc (20
6319 + (leftstop
- leftstart
)
6320 + (rightstop
- rightstart
));
6326 *s
++ = TOLOWER (qual
);
6328 memcpy (s
, leftstart
, leftstop
- leftstart
);
6329 s
+= leftstop
- leftstart
;
6331 memcpy (s
, rightstart
, rightstop
- rightstart
);
6332 s
+= rightstop
- rightstart
;
6338 buf
= (char *) xmalloc (20 + strlen (truelab
));
6344 *s
++ = TOLOWER (extent
);
6346 strcpy (s
, truelab
);
6351 /* Parse an MRI structured control expression. This generates test
6352 and branch instructions. STOP is where the expression ends. It
6353 goes to TRUELAB if the condition is true, and to FALSELAB if the
6354 condition is false. Exactly one of TRUELAB and FALSELAB will be
6355 NULL, meaning to fall through. QUAL is the size qualifier for the
6356 expression. EXTENT is the size to use for the branch. */
6359 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6360 const char *falselab
, int extent
)
6372 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6373 &rightstart
, &rightstop
))
6379 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6383 if (falselab
!= NULL
)
6386 flab
= mri_control_label ();
6388 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6389 rightstop
, (const char *) NULL
, flab
, extent
);
6391 input_line_pointer
+= 3;
6392 if (*input_line_pointer
!= '.'
6393 || input_line_pointer
[1] == '\0')
6397 qual
= input_line_pointer
[1];
6398 input_line_pointer
+= 2;
6401 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6402 &rightstart
, &rightstop
))
6408 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6409 rightstop
, truelab
, falselab
, extent
);
6411 if (falselab
== NULL
)
6414 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6418 if (truelab
!= NULL
)
6421 tlab
= mri_control_label ();
6423 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6424 rightstop
, tlab
, (const char *) NULL
, extent
);
6426 input_line_pointer
+= 2;
6427 if (*input_line_pointer
!= '.'
6428 || input_line_pointer
[1] == '\0')
6432 qual
= input_line_pointer
[1];
6433 input_line_pointer
+= 2;
6436 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6437 &rightstart
, &rightstop
))
6443 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6444 rightstop
, truelab
, falselab
, extent
);
6446 if (truelab
== NULL
)
6451 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6452 rightstop
, truelab
, falselab
, extent
);
6456 if (input_line_pointer
!= stop
)
6457 as_bad (_("syntax error in structured control directive"));
6460 /* Handle the MRI IF pseudo-op. This may be a structured control
6461 directive, or it may be a regular assembler conditional, depending
6469 struct mri_control_info
*n
;
6471 /* A structured control directive must end with THEN with an
6472 optional qualifier. */
6473 s
= input_line_pointer
;
6474 /* We only accept '*' as introduction of comments if preceded by white space
6475 or at first column of a line (I think this can't actually happen here?)
6476 This is important when assembling:
6477 if d0 <ne> 12(a0,d0*2) then
6478 if d0 <ne> #CONST*20 then. */
6479 while (! (is_end_of_line
[(unsigned char) *s
]
6482 && (s
== input_line_pointer
6484 || *(s
-1) == '\t'))))
6487 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6490 if (s
- input_line_pointer
> 1
6494 if (s
- input_line_pointer
< 3
6495 || strncasecmp (s
- 3, "THEN", 4) != 0)
6499 as_bad (_("missing then"));
6500 ignore_rest_of_line ();
6504 /* It's a conditional. */
6509 /* Since this might be a conditional if, this pseudo-op will be
6510 called even if we are supported to be ignoring input. Double
6511 check now. Clobber *input_line_pointer so that ignore_input
6512 thinks that this is not a special pseudo-op. */
6513 c
= *input_line_pointer
;
6514 *input_line_pointer
= 0;
6515 if (ignore_input ())
6517 *input_line_pointer
= c
;
6518 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6519 ++input_line_pointer
;
6520 demand_empty_rest_of_line ();
6523 *input_line_pointer
= c
;
6525 n
= push_mri_control (mri_if
);
6527 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6528 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6531 input_line_pointer
= s
+ 3;
6533 input_line_pointer
= s
+ 1;
6537 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6538 ++input_line_pointer
;
6541 demand_empty_rest_of_line ();
6544 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6545 structured IF, associate the ELSE with the IF. Otherwise, assume
6546 it is a conditional else. */
6549 s_mri_else (int qual
)
6556 && (mri_control_stack
== NULL
6557 || mri_control_stack
->type
!= mri_if
6558 || mri_control_stack
->else_seen
))
6564 c
= *input_line_pointer
;
6565 *input_line_pointer
= 0;
6566 if (ignore_input ())
6568 *input_line_pointer
= c
;
6569 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6570 ++input_line_pointer
;
6571 demand_empty_rest_of_line ();
6574 *input_line_pointer
= c
;
6576 if (mri_control_stack
== NULL
6577 || mri_control_stack
->type
!= mri_if
6578 || mri_control_stack
->else_seen
)
6580 as_bad (_("else without matching if"));
6581 ignore_rest_of_line ();
6585 mri_control_stack
->else_seen
= 1;
6587 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6588 q
[0] = TOLOWER (qual
);
6590 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6594 colon (mri_control_stack
->next
);
6598 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6599 ++input_line_pointer
;
6602 demand_empty_rest_of_line ();
6605 /* Handle the MRI ENDI pseudo-op. */
6608 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6610 if (mri_control_stack
== NULL
6611 || mri_control_stack
->type
!= mri_if
)
6613 as_bad (_("endi without matching if"));
6614 ignore_rest_of_line ();
6618 /* ignore_input will not return true for ENDI, so we don't need to
6619 worry about checking it again here. */
6621 if (! mri_control_stack
->else_seen
)
6622 colon (mri_control_stack
->next
);
6623 colon (mri_control_stack
->bottom
);
6629 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6630 ++input_line_pointer
;
6633 demand_empty_rest_of_line ();
6636 /* Handle the MRI BREAK pseudo-op. */
6639 s_mri_break (int extent
)
6641 struct mri_control_info
*n
;
6645 n
= mri_control_stack
;
6647 && n
->type
!= mri_for
6648 && n
->type
!= mri_repeat
6649 && n
->type
!= mri_while
)
6653 as_bad (_("break outside of structured loop"));
6654 ignore_rest_of_line ();
6658 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6659 ex
[0] = TOLOWER (extent
);
6661 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6667 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6668 ++input_line_pointer
;
6671 demand_empty_rest_of_line ();
6674 /* Handle the MRI NEXT pseudo-op. */
6677 s_mri_next (int extent
)
6679 struct mri_control_info
*n
;
6683 n
= mri_control_stack
;
6685 && n
->type
!= mri_for
6686 && n
->type
!= mri_repeat
6687 && n
->type
!= mri_while
)
6691 as_bad (_("next outside of structured loop"));
6692 ignore_rest_of_line ();
6696 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6697 ex
[0] = TOLOWER (extent
);
6699 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6705 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6706 ++input_line_pointer
;
6709 demand_empty_rest_of_line ();
6712 /* Handle the MRI FOR pseudo-op. */
6715 s_mri_for (int qual
)
6717 const char *varstart
, *varstop
;
6718 const char *initstart
, *initstop
;
6719 const char *endstart
, *endstop
;
6720 const char *bystart
, *bystop
;
6724 struct mri_control_info
*n
;
6730 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6734 varstart
= input_line_pointer
;
6736 /* Look for the '='. */
6737 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6738 && *input_line_pointer
!= '=')
6739 ++input_line_pointer
;
6740 if (*input_line_pointer
!= '=')
6742 as_bad (_("missing ="));
6743 ignore_rest_of_line ();
6747 varstop
= input_line_pointer
;
6748 if (varstop
> varstart
6749 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6752 ++input_line_pointer
;
6754 initstart
= input_line_pointer
;
6756 /* Look for TO or DOWNTO. */
6759 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6761 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6762 && ! is_part_of_name (input_line_pointer
[2]))
6764 initstop
= input_line_pointer
;
6765 input_line_pointer
+= 2;
6768 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6769 && ! is_part_of_name (input_line_pointer
[6]))
6771 initstop
= input_line_pointer
;
6773 input_line_pointer
+= 6;
6776 ++input_line_pointer
;
6778 if (initstop
== NULL
)
6780 as_bad (_("missing to or downto"));
6781 ignore_rest_of_line ();
6784 if (initstop
> initstart
6785 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6789 endstart
= input_line_pointer
;
6791 /* Look for BY or DO. */
6794 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6796 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6797 && ! is_part_of_name (input_line_pointer
[2]))
6799 endstop
= input_line_pointer
;
6801 input_line_pointer
+= 2;
6804 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6805 && (input_line_pointer
[2] == '.'
6806 || ! is_part_of_name (input_line_pointer
[2])))
6808 endstop
= input_line_pointer
;
6809 input_line_pointer
+= 2;
6812 ++input_line_pointer
;
6814 if (endstop
== NULL
)
6816 as_bad (_("missing do"));
6817 ignore_rest_of_line ();
6820 if (endstop
> endstart
6821 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6827 bystop
= bystart
+ 2;
6832 bystart
= input_line_pointer
;
6836 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6838 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6839 && (input_line_pointer
[2] == '.'
6840 || ! is_part_of_name (input_line_pointer
[2])))
6842 bystop
= input_line_pointer
;
6843 input_line_pointer
+= 2;
6846 ++input_line_pointer
;
6850 as_bad (_("missing do"));
6851 ignore_rest_of_line ();
6854 if (bystop
> bystart
6855 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6859 if (*input_line_pointer
!= '.')
6863 extent
= input_line_pointer
[1];
6864 input_line_pointer
+= 2;
6867 /* We have fully parsed the FOR operands. Now build the loop. */
6868 n
= push_mri_control (mri_for
);
6870 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6872 /* Move init,var. */
6879 *s
++ = TOLOWER (qual
);
6881 memcpy (s
, initstart
, initstop
- initstart
);
6882 s
+= initstop
- initstart
;
6884 memcpy (s
, varstart
, varstop
- varstart
);
6885 s
+= varstop
- varstart
;
6897 *s
++ = TOLOWER (qual
);
6899 memcpy (s
, endstart
, endstop
- endstart
);
6900 s
+= endstop
- endstart
;
6902 memcpy (s
, varstart
, varstop
- varstart
);
6903 s
+= varstop
- varstart
;
6908 ex
[0] = TOLOWER (extent
);
6911 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6913 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6916 /* Put together the add or sub instruction used by ENDF. */
6924 *s
++ = TOLOWER (qual
);
6926 memcpy (s
, bystart
, bystop
- bystart
);
6927 s
+= bystop
- bystart
;
6929 memcpy (s
, varstart
, varstop
- varstart
);
6930 s
+= varstop
- varstart
;
6936 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6937 ++input_line_pointer
;
6940 demand_empty_rest_of_line ();
6943 /* Handle the MRI ENDF pseudo-op. */
6946 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6948 if (mri_control_stack
== NULL
6949 || mri_control_stack
->type
!= mri_for
)
6951 as_bad (_("endf without for"));
6952 ignore_rest_of_line ();
6956 colon (mri_control_stack
->next
);
6958 mri_assemble (mri_control_stack
->incr
);
6960 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6961 mri_assemble (mri_control_stack
->incr
);
6963 free (mri_control_stack
->incr
);
6965 colon (mri_control_stack
->bottom
);
6971 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6972 ++input_line_pointer
;
6975 demand_empty_rest_of_line ();
6978 /* Handle the MRI REPEAT pseudo-op. */
6981 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6983 struct mri_control_info
*n
;
6985 n
= push_mri_control (mri_repeat
);
6989 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6990 ++input_line_pointer
;
6992 demand_empty_rest_of_line ();
6995 /* Handle the MRI UNTIL pseudo-op. */
6998 s_mri_until (int qual
)
7002 if (mri_control_stack
== NULL
7003 || mri_control_stack
->type
!= mri_repeat
)
7005 as_bad (_("until without repeat"));
7006 ignore_rest_of_line ();
7010 colon (mri_control_stack
->next
);
7012 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
7015 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
7016 mri_control_stack
->top
, '\0');
7018 colon (mri_control_stack
->bottom
);
7020 input_line_pointer
= s
;
7026 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7027 ++input_line_pointer
;
7030 demand_empty_rest_of_line ();
7033 /* Handle the MRI WHILE pseudo-op. */
7036 s_mri_while (int qual
)
7040 struct mri_control_info
*n
;
7042 s
= input_line_pointer
;
7043 /* We only accept '*' as introduction of comments if preceded by white space
7044 or at first column of a line (I think this can't actually happen here?)
7045 This is important when assembling:
7046 while d0 <ne> 12(a0,d0*2) do
7047 while d0 <ne> #CONST*20 do. */
7048 while (! (is_end_of_line
[(unsigned char) *s
]
7051 && (s
== input_line_pointer
7053 || *(s
-1) == '\t'))))
7056 while (*s
== ' ' || *s
== '\t')
7058 if (s
- input_line_pointer
> 1
7061 if (s
- input_line_pointer
< 2
7062 || strncasecmp (s
- 1, "DO", 2) != 0)
7064 as_bad (_("missing do"));
7065 ignore_rest_of_line ();
7069 n
= push_mri_control (mri_while
);
7073 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
7074 s
[1] == '.' ? s
[2] : '\0');
7076 input_line_pointer
= s
+ 1;
7077 if (*input_line_pointer
== '.')
7078 input_line_pointer
+= 2;
7082 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7083 ++input_line_pointer
;
7086 demand_empty_rest_of_line ();
7089 /* Handle the MRI ENDW pseudo-op. */
7092 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
7096 if (mri_control_stack
== NULL
7097 || mri_control_stack
->type
!= mri_while
)
7099 as_bad (_("endw without while"));
7100 ignore_rest_of_line ();
7104 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
7105 sprintf (buf
, "bra %s", mri_control_stack
->next
);
7109 colon (mri_control_stack
->bottom
);
7115 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7116 ++input_line_pointer
;
7119 demand_empty_rest_of_line ();
7122 /* Parse a .cpu directive. */
7125 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
7132 as_bad (_("already assembled instructions"));
7133 ignore_rest_of_line ();
7137 name
= input_line_pointer
;
7138 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
7139 input_line_pointer
++;
7140 saved_char
= *input_line_pointer
;
7141 *input_line_pointer
= 0;
7143 m68k_set_cpu (name
, 1, 0);
7145 *input_line_pointer
= saved_char
;
7146 demand_empty_rest_of_line ();
7150 /* Parse a .arch directive. */
7153 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
7160 as_bad (_("already assembled instructions"));
7161 ignore_rest_of_line ();
7165 name
= input_line_pointer
;
7166 while (*input_line_pointer
&& *input_line_pointer
!= ','
7167 && !ISSPACE (*input_line_pointer
))
7168 input_line_pointer
++;
7169 saved_char
= *input_line_pointer
;
7170 *input_line_pointer
= 0;
7172 if (m68k_set_arch (name
, 1, 0))
7174 /* Scan extensions. */
7177 *input_line_pointer
++ = saved_char
;
7178 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7180 name
= input_line_pointer
;
7181 while (*input_line_pointer
&& *input_line_pointer
!= ','
7182 && !ISSPACE (*input_line_pointer
))
7183 input_line_pointer
++;
7184 saved_char
= *input_line_pointer
;
7185 *input_line_pointer
= 0;
7187 while (m68k_set_extension (name
, 1, 0));
7190 *input_line_pointer
= saved_char
;
7191 demand_empty_rest_of_line ();
7195 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7196 if none is found, the caller is responsible for emitting an error
7197 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7198 cpu name, if it begins with a '6' (possibly skipping an intervening
7199 'c'. We also allow a 'c' in the same place. if NEGATED is
7200 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7201 the option is indeed negated. */
7203 static const struct m68k_cpu
*
7204 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7205 int allow_m
, int *negated
)
7207 /* allow negated value? */
7212 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7219 /* Remove 'm' or 'mc' prefix from 68k variants. */
7226 else if (arg
[1] == 'c' && arg
[2] == '6')
7230 else if (arg
[0] == 'c' && arg
[1] == '6')
7233 for (; table
->name
; table
++)
7234 if (!strcmp (arg
, table
->name
))
7236 if (table
->alias
< -1 || table
->alias
> 1)
7237 as_bad (_("`%s' is deprecated, use `%s'"),
7238 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7244 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7247 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7249 const struct m68k_cpu
*cpu
;
7251 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7256 as_bad (_("cpu `%s' unrecognized"), name
);
7260 if (selected_cpu
&& selected_cpu
!= cpu
)
7262 as_bad (_("already selected `%s' processor"),
7263 selected_cpu
->name
);
7270 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7273 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7275 const struct m68k_cpu
*arch
;
7277 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7282 as_bad (_("architecture `%s' unrecognized"), name
);
7286 if (selected_arch
&& selected_arch
!= arch
)
7288 as_bad (_("already selected `%s' architecture"),
7289 selected_arch
->name
);
7293 selected_arch
= arch
;
7297 /* Set the architecture extension, issuing errors if it is
7298 unrecognized, or invalid */
7301 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7304 const struct m68k_cpu
*ext
;
7306 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7311 as_bad (_("extension `%s' unrecognized"), name
);
7316 not_current_architecture
|= ext
->arch
;
7318 current_architecture
|= ext
->arch
;
7323 Invocation line includes a switch not recognized by the base assembler.
7327 const char *md_shortopts
= "lSA:m:kQ:V";
7329 const char *md_shortopts
= "lSA:m:k";
7332 struct option md_longopts
[] = {
7333 #define OPTION_PIC (OPTION_MD_BASE)
7334 {"pic", no_argument
, NULL
, OPTION_PIC
},
7335 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7336 {"register-prefix-optional", no_argument
, NULL
,
7337 OPTION_REGISTER_PREFIX_OPTIONAL
},
7338 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7339 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7340 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7341 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7342 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7343 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7344 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7345 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7346 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7347 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7348 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7349 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7350 {NULL
, no_argument
, NULL
, 0}
7352 size_t md_longopts_size
= sizeof (md_longopts
);
7355 md_parse_option (int c
, char *arg
)
7359 case 'l': /* -l means keep external to 2 bit offset
7360 rather than 16 bit one. */
7361 flag_short_refs
= 1;
7364 case 'S': /* -S means that jbsr's always turn into
7366 flag_long_jumps
= 1;
7369 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7370 branches into absolute jumps. */
7371 flag_keep_pcrel
= 1;
7377 break; /* -pic, Position Independent Code. */
7379 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7380 flag_reg_prefix_optional
= 1;
7381 reg_prefix_optional_seen
= 1;
7384 /* -V: SVR4 argument to print version ID. */
7386 print_version_id ();
7389 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7390 should be emitted or not. FIXME: Not implemented. */
7394 case OPTION_BITWISE_OR
:
7399 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7401 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7405 m68k_comment_chars
= n
;
7409 case OPTION_BASE_SIZE_DEFAULT_16
:
7410 m68k_index_width_default
= SIZE_WORD
;
7413 case OPTION_BASE_SIZE_DEFAULT_32
:
7414 m68k_index_width_default
= SIZE_LONG
;
7417 case OPTION_DISP_SIZE_DEFAULT_16
:
7419 m68k_rel32_from_cmdline
= 1;
7422 case OPTION_DISP_SIZE_DEFAULT_32
:
7424 m68k_rel32_from_cmdline
= 1;
7429 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7432 /* Intentional fall-through. */
7434 if (!strncmp (arg
, "arch=", 5))
7435 m68k_set_arch (arg
+ 5, 1, 0);
7436 else if (!strncmp (arg
, "cpu=", 4))
7437 m68k_set_cpu (arg
+ 4, 1, 0);
7438 else if (m68k_set_extension (arg
, 0, 1))
7440 else if (m68k_set_arch (arg
, 0, 1))
7442 else if (m68k_set_cpu (arg
, 0, 1))
7455 /* Setup tables from the selected arch and/or cpu */
7458 m68k_init_arch (void)
7460 if (not_current_architecture
& current_architecture
)
7462 as_bad (_("architecture features both enabled and disabled"));
7463 not_current_architecture
&= ~current_architecture
;
7467 current_architecture
|= selected_arch
->arch
;
7468 control_regs
= selected_arch
->control_regs
;
7471 current_architecture
|= selected_cpu
->arch
;
7473 current_architecture
&= ~not_current_architecture
;
7475 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7477 /* Determine which float is really meant. */
7478 if (current_architecture
& (m68k_mask
& ~m68881
))
7479 current_architecture
^= cfloat
;
7481 current_architecture
^= m68881
;
7486 control_regs
= selected_cpu
->control_regs
;
7487 if (current_architecture
& ~selected_cpu
->arch
)
7489 as_bad (_("selected processor does not have all features of selected architecture"));
7490 current_architecture
7491 = selected_cpu
->arch
& ~not_current_architecture
;
7495 if ((current_architecture
& m68k_mask
)
7496 && (current_architecture
& ~m68k_mask
))
7498 as_bad (_ ("m68k and cf features both selected"));
7499 if (current_architecture
& m68k_mask
)
7500 current_architecture
&= m68k_mask
;
7502 current_architecture
&= ~m68k_mask
;
7505 /* Permit m68881 specification with all cpus; those that can't work
7506 with a coprocessor could be doing emulation. */
7507 if (current_architecture
& m68851
)
7509 if (current_architecture
& m68040
)
7510 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7512 /* What other incompatibilities could we check for? */
7514 if (cpu_of_arch (current_architecture
) < m68020
7515 || arch_coldfire_p (current_architecture
))
7516 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7522 md_show_usage (FILE *stream
)
7524 const char *default_cpu
= TARGET_CPU
;
7526 unsigned int default_arch
;
7528 /* Get the canonical name for the default target CPU. */
7529 if (*default_cpu
== 'm')
7531 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7533 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7535 default_arch
= m68k_cpus
[i
].arch
;
7536 while (m68k_cpus
[i
].alias
> 0)
7538 while (m68k_cpus
[i
].alias
< 0)
7540 default_cpu
= m68k_cpus
[i
].name
;
7544 fprintf (stream
, _("\
7545 -march=<arch> set architecture\n\
7546 -mcpu=<cpu> set cpu [default %s]\n\
7548 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7549 fprintf (stream
, _("\
7550 -m[no-]%-16s enable/disable%s architecture extension\n\
7551 "), m68k_extensions
[i
].name
,
7552 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7553 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7555 fprintf (stream
, _("\
7556 -l use 1 word for refs to undefined symbols [default 2]\n\
7557 -pic, -k generate position independent code\n\
7558 -S turn jbsr into jsr\n\
7559 --pcrel never turn PC-relative branches into absolute jumps\n\
7560 --register-prefix-optional\n\
7561 recognize register names without prefix character\n\
7562 --bitwise-or do not treat `|' as a comment character\n\
7563 --base-size-default-16 base reg without size is 16 bits\n\
7564 --base-size-default-32 base reg without size is 32 bits (default)\n\
7565 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7566 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7569 fprintf (stream
, _("Architecture variants are: "));
7570 for (i
= 0; m68k_archs
[i
].name
; i
++)
7573 fprintf (stream
, " | ");
7574 fprintf (stream
, m68k_archs
[i
].name
);
7576 fprintf (stream
, "\n");
7578 fprintf (stream
, _("Processor variants are: "));
7579 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7582 fprintf (stream
, " | ");
7583 fprintf (stream
, m68k_cpus
[i
].name
);
7585 fprintf (stream
, _("\n"));
7590 /* TEST2: Test md_assemble() */
7591 /* Warning, this routine probably doesn't work anymore. */
7595 struct m68k_it the_ins
;
7603 if (!gets (buf
) || !*buf
)
7605 if (buf
[0] == '|' || buf
[1] == '.')
7607 for (cp
= buf
; *cp
; cp
++)
7612 memset (&the_ins
, '\0', sizeof (the_ins
));
7613 m68k_ip (&the_ins
, buf
);
7616 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7620 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7621 for (n
= 0; n
< the_ins
.numo
; n
++)
7622 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7624 print_the_insn (&the_ins
.opcode
[0], stdout
);
7625 (void) putchar ('\n');
7627 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7629 if (the_ins
.operands
[n
].error
)
7631 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7634 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7635 the_ins
.operands
[n
].reg
);
7636 if (the_ins
.operands
[n
].b_const
)
7637 printf ("Constant: '%.*s', ",
7638 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7639 the_ins
.operands
[n
].b_const
);
7640 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7641 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7642 if (the_ins
.operands
[n
].b_iadd
)
7643 printf ("Iadd: '%.*s',",
7644 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7645 the_ins
.operands
[n
].b_iadd
);
7654 is_label (char *str
)
7658 while (*str
&& *str
!= ' ')
7660 if (str
[-1] == ':' || str
[1] == '=')
7667 /* Possible states for relaxation:
7669 0 0 branch offset byte (bra, etc)
7673 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7677 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7684 /* We have no need to default values of symbols. */
7687 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7692 /* Round up a section size to the appropriate boundary. */
7694 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7697 /* For a.out, force the section size to be aligned. If we don't do
7698 this, BFD will align it for us, but it will not write out the
7699 final bytes of the section. This may be a bug in BFD, but it is
7700 easier to fix it here since that is how the other a.out targets
7704 align
= bfd_get_section_alignment (stdoutput
, segment
);
7705 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7711 /* Exactly what point is a PC-relative offset relative TO?
7712 On the 68k, it is relative to the address of the first extension
7713 word. The difference between the addresses of the offset and the
7714 first extension word is stored in fx_pcrel_adjust. */
7716 md_pcrel_from (fixS
*fixP
)
7720 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7721 sign extend the value here. */
7722 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7725 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7730 m68k_elf_final_processing (void)
7734 if (arch_coldfire_fpu (current_architecture
))
7735 flags
|= EF_M68K_CFV4E
;
7736 /* Set file-specific flags if this is a cpu32 processor. */
7737 if (cpu_of_arch (current_architecture
) & cpu32
)
7738 flags
|= EF_M68K_CPU32
;
7739 else if (cpu_of_arch (current_architecture
) & fido_a
)
7740 flags
|= EF_M68K_FIDO
;
7741 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7742 && !(cpu_of_arch (current_architecture
) & m68020up
))
7743 flags
|= EF_M68K_M68000
;
7745 if (current_architecture
& mcfisa_a
)
7747 static const unsigned isa_features
[][2] =
7749 {EF_M68K_CF_ISA_A_NODIV
,mcfisa_a
},
7750 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7751 {EF_M68K_CF_ISA_A_PLUS
, mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7752 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7753 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7754 {EF_M68K_CF_ISA_C
, mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfusp
},
7755 {EF_M68K_CF_ISA_C_NODIV
,mcfisa_a
|mcfisa_c
|mcfusp
},
7758 static const unsigned mac_features
[][2] =
7760 {EF_M68K_CF_MAC
, mcfmac
},
7761 {EF_M68K_CF_EMAC
, mcfemac
},
7767 pattern
= (current_architecture
7768 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfisa_c
|mcfhwdiv
|mcfusp
));
7769 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7771 if (pattern
== isa_features
[ix
][1])
7773 flags
|= isa_features
[ix
][0];
7777 if (!isa_features
[ix
][1])
7780 as_warn (_("Not a defined coldfire architecture"));
7784 if (current_architecture
& cfloat
)
7785 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7787 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7790 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7792 if (pattern
== mac_features
[ix
][1])
7794 flags
|= mac_features
[ix
][0];
7798 if (!mac_features
[ix
][1])
7803 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7808 tc_m68k_regname_to_dw2regnum (char *regname
)
7810 unsigned int regnum
;
7811 static const char *const regnames
[] =
7813 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7814 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7815 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7819 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7820 if (strcmp (regname
, regnames
[regnum
]) == 0)
7827 tc_m68k_frame_initial_instructions (void)
7829 static int sp_regno
= -1;
7832 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7834 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7835 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);