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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #define NO_RELOC 0
23 #include "as.h"
24 #include "obstack.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
31 #ifdef OBJ_ELF
32 CONST char comment_chars[] = "|#";
33 #else
34 CONST char comment_chars[] = "|";
35 #endif
36
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 CONST char line_comment_chars[] = "#";
45
46 CONST char line_separator_chars[] = "";
47
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
50
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
53
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
55
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
59
60 const int md_reloc_size = 8; /* Size of relocation record */
61
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
64 references. */
65 int flag_want_pic;
66
67 static int flag_short_refs; /* -l option */
68 static int flag_long_jumps; /* -S option */
69
70 #ifdef REGISTER_PREFIX_OPTIONAL
71 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
72 #else
73 int flag_reg_prefix_optional;
74 #endif
75
76 /* The floating point coprocessor to use by default. */
77 static enum m68k_register m68k_float_copnum = COP1;
78
79 /* Its an arbitrary name: This means I don't approve of it */
80 /* See flames below */
81 static struct obstack robyn;
82
83 #define TAB(x,y) (((x)<<2)+(y))
84 #define TABTYPE(xy) ((xy) >> 2)
85 #define BYTE 0
86 #define SHORT 1
87 #define LONG 2
88 #define SZ_UNDEF 3
89 #undef BRANCH
90 /* Case `g' except when BCC68000 is applicable. */
91 #define ABRANCH 1
92 /* Coprocessor branches. */
93 #define FBRANCH 2
94 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
95 supported on all cpus. Widens to 32-bit absolute. */
96 #define PCREL 3
97 /* For inserting an extra jmp instruction with long offset on 68000,
98 for expanding conditional branches. (Not bsr or bra.) Since the
99 68000 doesn't support 32-bit displacements for conditional
100 branches, we fake it by reversing the condition and branching
101 around a jmp with an absolute long operand. */
102 #define BCC68000 4
103 /* For the DBcc "instructions". If the displacement requires 32 bits,
104 the branch-around-a-jump game is played here too. */
105 #define DBCC 5
106 /* Not currently used? */
107 #define PCLEA 6
108 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
109 in 16 or 8 bits. */
110 #define PCINDEX 7
111
112 struct m68k_incant
113 {
114 const char *m_operands;
115 unsigned long m_opcode;
116 short m_opnum;
117 short m_codenum;
118 int m_arch;
119 struct m68k_incant *m_next;
120 };
121
122 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
123 #define gettwo(x) (((x)->m_opcode)&0xffff)
124
125 static const enum m68k_register m68000_control_regs[] = { 0 };
126 static const enum m68k_register m68010_control_regs[] = {
127 SFC, DFC, USP, VBR,
128 0
129 };
130 static const enum m68k_register m68020_control_regs[] = {
131 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
132 0
133 };
134 static const enum m68k_register m68040_control_regs[] = {
135 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
136 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
137 0
138 };
139 static const enum m68k_register m68060_control_regs[] = {
140 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
141 USP, VBR, URP, SRP, PCR,
142 0
143 };
144 #define cpu32_control_regs m68010_control_regs
145
146 static const enum m68k_register *control_regs;
147
148 /* internal form of a 68020 instruction */
149 struct m68k_it
150 {
151 const char *error;
152 const char *args; /* list of opcode info */
153 int numargs;
154
155 int numo; /* Number of shorts in opcode */
156 short opcode[11];
157
158 struct m68k_op operands[6];
159
160 int nexp; /* number of exprs in use */
161 struct m68k_exp exprs[4];
162
163 int nfrag; /* Number of frags we have to produce */
164 struct
165 {
166 int fragoff; /* Where in the current opcode the frag ends */
167 symbolS *fadd;
168 long foff;
169 int fragty;
170 }
171 fragb[4];
172
173 int nrel; /* Num of reloc strucs in use */
174 struct
175 {
176 int n;
177 expressionS exp;
178 char wid;
179 char pcrel;
180 /* In a pc relative address the difference between the address
181 of the offset and the address that the offset is relative
182 to. This depends on the addressing mode. Basically this
183 is the value to put in the offset field to address the
184 first byte of the offset, without regarding the special
185 significance of some values (in the branch instruction, for
186 example). */
187 int pcrel_fix;
188 }
189 reloc[5]; /* Five is enough??? */
190 };
191
192 #define cpu_of_arch(x) ((x) & m68000up)
193 #define float_of_arch(x) ((x) & mfloat)
194 #define mmu_of_arch(x) ((x) & mmmu)
195
196 static struct m68k_it the_ins; /* the instruction being assembled */
197
198 #define op(ex) ((ex)->exp.X_op)
199 #define adds(ex) ((ex)->exp.X_add_symbol)
200 #define subs(ex) ((ex)->exp.X_op_symbol)
201 #define offs(ex) ((ex)->exp.X_add_number)
202
203 /* Macros for adding things to the m68k_it struct */
204
205 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
206
207 /* Like addword, but goes BEFORE general operands */
208 static void
209 insop (w, opcode)
210 int w;
211 struct m68k_incant *opcode;
212 {
213 int z;
214 for(z=the_ins.numo;z>opcode->m_codenum;--z)
215 the_ins.opcode[z]=the_ins.opcode[z-1];
216 for(z=0;z<the_ins.nrel;z++)
217 the_ins.reloc[z].n+=2;
218 for (z = 0; z < the_ins.nfrag; z++)
219 the_ins.fragb[z].fragoff++;
220 the_ins.opcode[opcode->m_codenum]=w;
221 the_ins.numo++;
222 }
223
224 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
225 Blecch. */
226 static void
227 add_fix (width, exp, pc_rel, pc_fix)
228 char width;
229 struct m68k_exp *exp;
230 int pc_rel;
231 int pc_fix;
232 {
233 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
234 ? (the_ins.numo*2-1)
235 : (((width)=='b')
236 ? (the_ins.numo*2+1)
237 : (the_ins.numo*2)));
238 the_ins.reloc[the_ins.nrel].exp = exp->exp;
239 the_ins.reloc[the_ins.nrel].wid = width;
240 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
241 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
242 }
243
244 /* Cause an extra frag to be generated here, inserting up to 10 bytes
245 (that value is chosen in the frag_var call in md_assemble). TYPE
246 is the subtype of the frag to be generated; its primary type is
247 rs_machine_dependent.
248
249 The TYPE parameter is also used by md_convert_frag_1 and
250 md_estimate_size_before_relax. The appropriate type of fixup will
251 be emitted by md_convert_frag_1.
252
253 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
254 static void
255 add_frag(add,off,type)
256 symbolS *add;
257 long off;
258 int type;
259 {
260 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
261 the_ins.fragb[the_ins.nfrag].fadd=add;
262 the_ins.fragb[the_ins.nfrag].foff=off;
263 the_ins.fragb[the_ins.nfrag++].fragty=type;
264 }
265
266 #define isvar(ex) \
267 (op (ex) != O_constant && op (ex) != O_big)
268
269 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
270 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
271 static int reverse_16_bits PARAMS ((int in));
272 static int reverse_8_bits PARAMS ((int in));
273 static void install_gen_operand PARAMS ((int mode, int val));
274 static void install_operand PARAMS ((int mode, int val));
275 static void s_bss PARAMS ((int));
276 static void s_data1 PARAMS ((int));
277 static void s_data2 PARAMS ((int));
278 static void s_even PARAMS ((int));
279 static void s_proc PARAMS ((int));
280 static void mri_chip PARAMS ((void));
281 static void s_chip PARAMS ((int));
282 static void s_fopt PARAMS ((int));
283
284 static int current_architecture;
285
286 struct m68k_cpu {
287 unsigned long arch;
288 const char *name;
289 };
290
291 static const struct m68k_cpu archs[] = {
292 { m68000, "68000" },
293 { m68010, "68010" },
294 { m68020, "68020" },
295 { m68030, "68030" },
296 { m68040, "68040" },
297 { m68060, "68060" },
298 { cpu32, "cpu32" },
299 { m68881, "68881" },
300 { m68851, "68851" },
301 /* Aliases (effectively, so far as gas is concerned) for the above
302 cpus. */
303 { m68020, "68k" },
304 { m68000, "68302" },
305 { m68000, "68008" },
306 { m68000, "68ec000" },
307 { m68000, "68hc000" },
308 { m68000, "68hc001" },
309 { m68020, "68ec020" },
310 { m68030, "68ec030" },
311 { m68040, "68ec040" },
312 { cpu32, "68330" },
313 { cpu32, "68331" },
314 { cpu32, "68332" },
315 { cpu32, "68333" },
316 { cpu32, "68340" },
317 { cpu32, "68360" },
318 { m68881, "68882" },
319 };
320
321 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
322
323 /* BCC68000 is for patching in an extra jmp instruction for long offsets
324 on the 68000. The 68000 doesn't support long branches with branchs */
325
326 /* This table desribes how you change sizes for the various types of variable
327 size expressions. This version only supports two kinds. */
328
329 /* Note that calls to frag_var need to specify the maximum expansion
330 needed; this is currently 10 bytes for DBCC. */
331
332 /* The fields are:
333 How far Forward this mode will reach:
334 How far Backward this mode will reach:
335 How many bytes this mode will add to the size of the frag
336 Which mode to go to if the offset won't fit in this one
337 */
338 relax_typeS md_relax_table[] =
339 {
340 {1, 1, 0, 0}, /* First entries aren't used */
341 {1, 1, 0, 0}, /* For no good reason except */
342 {1, 1, 0, 0}, /* that the VAX doesn't either */
343 {1, 1, 0, 0},
344
345 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
346 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
347 {0, 0, 4, 0},
348 {1, 1, 0, 0},
349
350 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
351 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
352 {0, 0, 4, 0},
353 {1, 1, 0, 0},
354
355 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
356 {(32767), (-32768), 2, TAB (PCREL, LONG)},
357 {0, 0, 4, 0},
358 {1, 1, 0, 0},
359
360 {(127), (-128), 0, TAB (BCC68000, SHORT)},
361 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
362 {0, 0, 6, 0}, /* jmp long space */
363 {1, 1, 0, 0},
364
365 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
366 {(32767), (-32768), 2, TAB (DBCC, LONG)},
367 {0, 0, 10, 0}, /* bra/jmp long space */
368 {1, 1, 0, 0},
369
370 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
371 {32767, -32768, 2, TAB (PCLEA, LONG)},
372 {0, 0, 6, 0},
373 {1, 1, 0, 0},
374
375 /* For, e.g., jmp pcrel indexed. */
376 {125, -130, 0, TAB (PCINDEX, SHORT)},
377 {32765, -32770, 2, TAB (PCINDEX, LONG)},
378 {0, 0, 4, 0},
379 {1, 1, 0, 0},
380 };
381
382 /* These are the machine dependent pseudo-ops. These are included so
383 the assembler can work on the output from the SUN C compiler, which
384 generates these.
385 */
386
387 /* This table describes all the machine specific pseudo-ops the assembler
388 has to support. The fields are:
389 pseudo-op name without dot
390 function to call to execute this pseudo-op
391 Integer arg to pass to the function
392 */
393 CONST pseudo_typeS md_pseudo_table[] =
394 {
395 {"data1", s_data1, 0},
396 {"data2", s_data2, 0},
397 {"bss", s_bss, 0},
398 {"even", s_even, 0},
399 {"skip", s_space, 0},
400 {"proc", s_proc, 0},
401 #ifdef TE_SUN3
402 {"align", s_align_bytes, 0},
403 #endif
404 #ifdef OBJ_ELF
405 {"swbeg", s_ignore, 0},
406 #endif
407
408 /* The following pseudo-ops are supported for MRI compatibility. */
409 {"chip", s_chip, 0},
410 {"comline", s_space, 1},
411 {"fopt", s_fopt, 0},
412 {"mask2", s_ignore, 0},
413
414 {0, 0, 0}
415 };
416
417
418 /* The mote pseudo ops are put into the opcode table, since they
419 don't start with a . they look like opcodes to gas.
420 */
421 extern void obj_coff_section ();
422
423 CONST pseudo_typeS mote_pseudo_table[] =
424 {
425
426 {"dcl", cons, 4},
427 {"dc", cons, 2},
428 {"dcw", cons, 2},
429 {"dcb", cons, 1},
430
431 {"dsl", s_space, 4},
432 {"ds", s_space, 2},
433 {"dsw", s_space, 2},
434 {"dsb", s_space, 1},
435
436 {"xdef", s_globl, 0},
437 {"align", s_align_ptwo, 0},
438 #ifdef M68KCOFF
439 {"sect", obj_coff_section, 0},
440 {"section", obj_coff_section, 0},
441 #endif
442 {0, 0, 0}
443 };
444
445 #define issbyte(x) ((x)>=-128 && (x)<=127)
446 #define isubyte(x) ((x)>=0 && (x)<=255)
447 #define issword(x) ((x)>=-32768 && (x)<=32767)
448 #define isuword(x) ((x)>=0 && (x)<=65535)
449
450 #define isbyte(x) ((x)>= -255 && (x)<=255)
451 #define isword(x) ((x)>=-32768 && (x)<=65535)
452 #define islong(x) (1)
453
454 extern char *input_line_pointer;
455
456 static char mklower_table[256];
457 #define mklower(c) (mklower_table[(unsigned char)(c)])
458 static char notend_table[256];
459 static char alt_notend_table[256];
460 #define notend(s) \
461 (! (notend_table[(unsigned char) *s] \
462 || (*s == ':' \
463 && alt_notend_table[(unsigned char) s[1]])))
464
465 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
466
467 #ifdef NO_PCREL_RELOCS
468
469 int
470 make_pcrel_absolute(fixP, add_number)
471 fixS *fixP;
472 long *add_number;
473 {
474 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
475
476 /* rewrite the PC relative instructions to absolute address ones.
477 * these are rumoured to be faster, and the apollo linker refuses
478 * to deal with the PC relative relocations.
479 */
480 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
481 {
482 opcode[0] = 0x4e;
483 opcode[1] = 0xf9;
484 }
485 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
486 {
487 opcode[0] = 0x4e;
488 opcode[1] = 0xb9;
489 }
490 else
491 as_fatal ("Unknown PC relative instruction");
492 *add_number -= 4;
493 return 0;
494 }
495
496 #endif /* NO_PCREL_RELOCS */
497
498 short
499 tc_coff_fix2rtype (fixP)
500 fixS *fixP;
501 {
502 #ifdef NO_PCREL_RELOCS
503 know (fixP->fx_pcrel == 0);
504 return (fixP->fx_size == 1 ? R_RELBYTE
505 : fixP->fx_size == 2 ? R_DIR16
506 : R_DIR32);
507 #else
508 return (fixP->fx_pcrel ?
509 (fixP->fx_size == 1 ? R_PCRBYTE :
510 fixP->fx_size == 2 ? R_PCRWORD :
511 R_PCRLONG) :
512 (fixP->fx_size == 1 ? R_RELBYTE :
513 fixP->fx_size == 2 ? R_RELWORD :
514 R_RELLONG));
515 #endif
516 }
517
518 #endif
519
520 #ifdef BFD_ASSEMBLER
521
522 arelent *
523 tc_gen_reloc (section, fixp)
524 asection *section;
525 fixS *fixp;
526 {
527 arelent *reloc;
528 bfd_reloc_code_real_type code;
529
530 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
531 switch (F (fixp->fx_size, fixp->fx_pcrel))
532 {
533 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
534 MAP (1, 0, BFD_RELOC_8);
535 MAP (2, 0, BFD_RELOC_16);
536 MAP (4, 0, BFD_RELOC_32);
537 MAP (1, 1, BFD_RELOC_8_PCREL);
538 MAP (2, 1, BFD_RELOC_16_PCREL);
539 MAP (4, 1, BFD_RELOC_32_PCREL);
540 default:
541 abort ();
542 }
543
544 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
545 assert (reloc != 0);
546 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
547 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
548 if (fixp->fx_pcrel)
549 reloc->addend = fixp->fx_addnumber;
550 else
551 reloc->addend = 0;
552
553 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
554 assert (reloc->howto != 0);
555
556 return reloc;
557 }
558
559 #endif /* BFD_ASSEMBLER */
560
561 /* Handle of the OPCODE hash table. NULL means any use before
562 m68k_ip_begin() will crash. */
563 static struct hash_control *op_hash;
564 \f
565 /* Assemble an m68k instruction. */
566
567 void
568 m68k_ip (instring)
569 char *instring;
570 {
571 register char *p;
572 register struct m68k_op *opP;
573 register struct m68k_incant *opcode;
574 register const char *s;
575 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
576 char *pdot, *pdotmove;
577 enum m68k_size siz1, siz2;
578 char c;
579 int losing;
580 int opsfound;
581 char *crack_operand ();
582 LITTLENUM_TYPE words[6];
583 LITTLENUM_TYPE *wordp;
584 unsigned long ok_arch = 0;
585
586 if (*instring == ' ')
587 instring++; /* skip leading whitespace */
588
589 /* Scan up to end of operation-code, which MUST end in end-of-string
590 or exactly 1 space. */
591 pdot = 0;
592 for (p = instring; *p != '\0'; p++)
593 {
594 if (*p == ' ')
595 break;
596 if (*p == '.')
597 pdot = p;
598 }
599
600 if (p == instring)
601 {
602 the_ins.error = "No operator";
603 return;
604 }
605
606 /* p now points to the end of the opcode name, probably whitespace.
607 Make sure the name is null terminated by clobbering the
608 whitespace, look it up in the hash table, then fix it back.
609 Remove a dot, first, since the opcode tables have none. */
610 if (pdot != NULL)
611 {
612 for (pdotmove = pdot; pdotmove < p; pdotmove++)
613 *pdotmove = pdotmove[1];
614 p--;
615 }
616
617 c = *p;
618 *p = '\0';
619 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
620 *p = c;
621
622 if (pdot != NULL)
623 {
624 for (pdotmove = p; pdotmove > pdot; pdotmove--)
625 *pdotmove = pdotmove[-1];
626 *pdot = '.';
627 ++p;
628 }
629
630 if (opcode == NULL)
631 {
632 the_ins.error = "Unknown operator";
633 return;
634 }
635
636 /* found a legitimate opcode, start matching operands */
637 while (*p == ' ')
638 ++p;
639
640 if (opcode->m_operands == 0)
641 {
642 char *old = input_line_pointer;
643 *old = '\n';
644 input_line_pointer = p;
645 /* Ahh - it's a motorola style psuedo op */
646 mote_pseudo_table[opcode->m_opnum].poc_handler
647 (mote_pseudo_table[opcode->m_opnum].poc_val);
648 input_line_pointer = old;
649 *old = 0;
650
651 return;
652 }
653
654 for (opP = &the_ins.operands[0]; *p; opP++)
655 {
656 p = crack_operand (p, opP);
657
658 if (opP->error)
659 {
660 the_ins.error = opP->error;
661 return;
662 }
663 }
664
665 opsfound = opP - &the_ins.operands[0];
666
667 /* This ugly hack is to support the floating pt opcodes in their
668 standard form. Essentially, we fake a first enty of type COP#1 */
669 if (opcode->m_operands[0] == 'I')
670 {
671 int n;
672
673 for (n = opsfound; n > 0; --n)
674 the_ins.operands[n] = the_ins.operands[n - 1];
675
676 memset ((char *) (&the_ins.operands[0]), '\0',
677 sizeof (the_ins.operands[0]));
678 the_ins.operands[0].mode = CONTROL;
679 the_ins.operands[0].reg = m68k_float_copnum;
680 opsfound++;
681 }
682
683 /* We've got the operands. Find an opcode that'll accept them */
684 for (losing = 0;;)
685 {
686 /* If we didn't get the right number of ops, or we have no
687 common model with this pattern then reject this pattern. */
688
689 if (opsfound != opcode->m_opnum
690 || ((opcode->m_arch & current_architecture) == 0))
691 {
692 ++losing;
693 ok_arch |= opcode->m_arch;
694 }
695 else
696 {
697 for (s = opcode->m_operands, opP = &the_ins.operands[0];
698 *s && !losing;
699 s += 2, opP++)
700 {
701 /* Warning: this switch is huge! */
702 /* I've tried to organize the cases into this order:
703 non-alpha first, then alpha by letter. Lower-case
704 goes directly before uppercase counterpart. */
705 /* Code with multiple case ...: gets sorted by the lowest
706 case ... it belongs to. I hope this makes sense. */
707 switch (*s)
708 {
709 case '!':
710 switch (opP->mode)
711 {
712 case IMMED:
713 case DREG:
714 case AREG:
715 case FPREG:
716 case CONTROL:
717 case AINC:
718 case ADEC:
719 case REGLST:
720 losing++;
721 break;
722 default:
723 break;
724 }
725 break;
726
727 case '`':
728 switch (opP->mode)
729 {
730 case IMMED:
731 case DREG:
732 case AREG:
733 case FPREG:
734 case CONTROL:
735 case AINC:
736 case REGLST:
737 case AINDR:
738 losing++;
739 break;
740 default:
741 break;
742 }
743 break;
744
745 case '#':
746 if (opP->mode != IMMED)
747 losing++;
748 else if (s[1] == 'b'
749 && ! isvar (&opP->disp)
750 && ! expr8 (&opP->disp))
751 losing++;
752 else if (s[1] == 'w'
753 && ! isvar (&opP->disp)
754 && ! expr16 (&opP->disp))
755 losing++;
756 break;
757
758 case '^':
759 case 'T':
760 if (opP->mode != IMMED)
761 losing++;
762 break;
763
764 case '$':
765 if (opP->mode == AREG
766 || opP->mode == CONTROL
767 || opP->mode == FPREG
768 || opP->mode == IMMED
769 || opP->mode == REGLST
770 || (opP->mode != ABSL
771 && (opP->reg == PC
772 || opP->reg == ZPC)))
773 losing++;
774 break;
775
776 case '%':
777 if (opP->mode == CONTROL
778 || opP->mode == FPREG
779 || opP->mode == REGLST
780 || (opP->mode != ABSL
781 && opP->mode != IMMED
782 && (opP->reg == PC
783 || opP->reg == ZPC)))
784 losing++;
785 break;
786
787 case '&':
788 switch (opP->mode)
789 {
790 case DREG:
791 case AREG:
792 case FPREG:
793 case CONTROL:
794 case IMMED:
795 case AINC:
796 case ADEC:
797 case REGLST:
798 losing++;
799 break;
800 case ABSL:
801 break;
802 default:
803 if (opP->reg == PC
804 || opP->reg == ZPC)
805 losing++;
806 break;
807 }
808 break;
809
810 case '*':
811 if (opP->mode == CONTROL
812 || opP->mode == FPREG
813 || opP->mode == REGLST)
814 losing++;
815 break;
816
817 case '+':
818 if (opP->mode != AINC)
819 losing++;
820 break;
821
822 case '-':
823 if (opP->mode != ADEC)
824 losing++;
825 break;
826
827 case '/':
828 switch (opP->mode)
829 {
830 case AREG:
831 case CONTROL:
832 case FPREG:
833 case AINC:
834 case ADEC:
835 case IMMED:
836 case REGLST:
837 losing++;
838 break;
839 default:
840 break;
841 }
842 break;
843
844 case ';':
845 switch (opP->mode)
846 {
847 case AREG:
848 case CONTROL:
849 case FPREG:
850 case REGLST:
851 losing++;
852 break;
853 default:
854 break;
855 }
856 break;
857
858 case '?':
859 switch (opP->mode)
860 {
861 case AREG:
862 case CONTROL:
863 case FPREG:
864 case AINC:
865 case ADEC:
866 case IMMED:
867 case REGLST:
868 losing++;
869 break;
870 case ABSL:
871 break;
872 default:
873 if (opP->reg == PC || opP->reg == ZPC)
874 losing++;
875 break;
876 }
877 break;
878
879 case '@':
880 switch (opP->mode)
881 {
882 case AREG:
883 case CONTROL:
884 case FPREG:
885 case IMMED:
886 case REGLST:
887 losing++;
888 break;
889 default:
890 break;
891 }
892 break;
893
894 case '~': /* For now! (JF FOO is this right?) */
895 switch (opP->mode)
896 {
897 case DREG:
898 case AREG:
899 case CONTROL:
900 case FPREG:
901 case IMMED:
902 case REGLST:
903 losing++;
904 break;
905 case ABSL:
906 break;
907 default:
908 if (opP->reg == PC
909 || opP->reg == ZPC)
910 losing++;
911 break;
912 }
913 break;
914
915 case '3':
916 if (opP->mode != CONTROL
917 || (opP->reg != TT0 && opP->reg != TT1))
918 losing++;
919 break;
920
921 case 'A':
922 if (opP->mode != AREG)
923 losing++;
924 break;
925
926 case 'a':
927 if (opP->mode != AINDR)
928 ++losing;
929 break;
930
931 case 'B': /* FOO */
932 if (opP->mode != ABSL
933 || (flag_long_jumps
934 && strncmp (instring, "jbsr", 4) == 0))
935 losing++;
936 break;
937
938 case 'C':
939 if (opP->mode != CONTROL || opP->reg != CCR)
940 losing++;
941 break;
942
943 case 'd':
944 if (opP->mode != DISP
945 || opP->reg < ADDR0
946 || opP->reg > ADDR7)
947 losing++;
948 break;
949
950 case 'D':
951 if (opP->mode != DREG)
952 losing++;
953 break;
954
955 case 'F':
956 if (opP->mode != FPREG)
957 losing++;
958 break;
959
960 case 'I':
961 if (opP->mode != CONTROL
962 || opP->reg < COP0
963 || opP->reg > COP7)
964 losing++;
965 break;
966
967 case 'J':
968 if (opP->mode != CONTROL
969 || opP->reg < USP
970 || opP->reg > last_movec_reg)
971 losing++;
972 else
973 {
974 const enum m68k_register *rp;
975 for (rp = control_regs; *rp; rp++)
976 if (*rp == opP->reg)
977 break;
978 if (*rp == 0)
979 losing++;
980 }
981 break;
982
983 case 'k':
984 if (opP->mode != IMMED)
985 losing++;
986 break;
987
988 case 'l':
989 case 'L':
990 if (opP->mode == DREG
991 || opP->mode == AREG
992 || opP->mode == FPREG)
993 {
994 if (s[1] == '8')
995 losing++;
996 else
997 {
998 switch (opP->mode)
999 {
1000 case DREG:
1001 opP->mask = 1 << (opP->reg - DATA0);
1002 break;
1003 case AREG:
1004 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1005 break;
1006 case FPREG:
1007 opP->mask = 1 << (opP->reg - FP0 + 16);
1008 break;
1009 default:
1010 abort ();
1011 }
1012 opP->mode = REGLST;
1013 }
1014 }
1015 else if (opP->mode == CONTROL)
1016 {
1017 if (s[1] != '8')
1018 losing++;
1019 else
1020 {
1021 switch (opP->reg)
1022 {
1023 case FPI:
1024 opP->mask = 1 << 24;
1025 break;
1026 case FPS:
1027 opP->mask = 1 << 25;
1028 break;
1029 case FPC:
1030 opP->mask = 1 << 26;
1031 break;
1032 default:
1033 losing++;
1034 break;
1035 }
1036 opP->mode = REGLST;
1037 }
1038 }
1039 else if (opP->mode != REGLST)
1040 losing++;
1041 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1042 losing++;
1043 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1044 losing++;
1045 break;
1046
1047 case 'M':
1048 if (opP->mode != IMMED)
1049 losing++;
1050 else if (! expr8 (&opP->disp))
1051 losing++;
1052 break;
1053
1054 case 'O':
1055 if (opP->mode != DREG && opP->mode != IMMED)
1056 losing++;
1057 break;
1058
1059 case 'Q':
1060 if (opP->mode != IMMED)
1061 losing++;
1062 else if (! expr8 (&opP->disp)
1063 || opP->disp.exp.X_add_number < 1
1064 || opP->disp.exp.X_add_number > 8)
1065 losing++;
1066 break;
1067
1068 case 'R':
1069 if (opP->mode != DREG && opP->mode != AREG)
1070 losing++;
1071 break;
1072
1073 case 'r':
1074 if (opP->mode != AINDR
1075 && (opP->mode != BASE
1076 || (opP->reg != 0
1077 && opP->reg != ZADDR0)
1078 || opP->disp.exp.X_op != O_absent
1079 || ((opP->index.reg < DATA0
1080 || opP->index.reg > DATA7)
1081 && (opP->index.reg < ADDR0
1082 || opP->index.reg > ADDR7))
1083 || opP->index.size != SIZE_UNSPEC
1084 || opP->index.scale != 1))
1085 losing++;
1086 break;
1087
1088 case 's':
1089 if (opP->mode != CONTROL
1090 || ! (opP->reg == FPI
1091 || opP->reg == FPS
1092 || opP->reg == FPC))
1093 losing++;
1094 break;
1095
1096 case 'S':
1097 if (opP->mode != CONTROL || opP->reg != SR)
1098 losing++;
1099 break;
1100
1101 case 't':
1102 if (opP->mode != IMMED)
1103 losing++;
1104 else if (! expr8 (&opP->disp)
1105 || opP->disp.exp.X_add_number < 0
1106 || opP->disp.exp.X_add_number > 7)
1107 losing++;
1108 break;
1109
1110 case 'U':
1111 if (opP->mode != CONTROL || opP->reg != USP)
1112 losing++;
1113 break;
1114
1115 /* JF these are out of order. We could put them
1116 in order if we were willing to put up with
1117 bunches of #ifdef m68851s in the code.
1118
1119 Don't forget that you need these operands
1120 to use 68030 MMU instructions. */
1121 #ifndef NO_68851
1122 /* Memory addressing mode used by pflushr */
1123 case '|':
1124 if (opP->mode == CONTROL
1125 || opP->mode == FPREG
1126 || opP->mode == DREG
1127 || opP->mode == AREG
1128 || opP->mode == REGLST)
1129 losing++;
1130 break;
1131
1132 case 'f':
1133 if (opP->mode != CONTROL
1134 || (opP->reg != SFC && opP->reg != DFC))
1135 losing++;
1136 break;
1137
1138 case 'P':
1139 if (opP->mode != CONTROL
1140 || (opP->reg != TC
1141 && opP->reg != CAL
1142 && opP->reg != VAL
1143 && opP->reg != SCC
1144 && opP->reg != AC))
1145 losing++;
1146 break;
1147
1148 case 'V':
1149 if (opP->mode != CONTROL
1150 || opP->reg != VAL)
1151 losing++;
1152 break;
1153
1154 case 'W':
1155 if (opP->mode != CONTROL
1156 || (opP->reg != DRP
1157 && opP->reg != SRP
1158 && opP->reg != CRP))
1159 losing++;
1160 break;
1161
1162 case 'X':
1163 if (opP->mode != CONTROL
1164 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1165 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1166 losing++;
1167 break;
1168
1169 case 'Y':
1170 if (opP->mode != CONTROL || opP->reg != PSR)
1171 losing++;
1172 break;
1173
1174 case 'Z':
1175 if (opP->mode != CONTROL || opP->reg != PCSR)
1176 losing++;
1177 break;
1178 #endif
1179 case 'c':
1180 if (opP->mode != CONTROL
1181 || (opP->reg != NC
1182 && opP->reg != IC
1183 && opP->reg != DC
1184 && opP->reg != BC))
1185 {
1186 losing++;
1187 } /* not a cache specifier. */
1188 break;
1189
1190 case '_':
1191 if (opP->mode != ABSL)
1192 ++losing;
1193 break;
1194
1195 default:
1196 abort ();
1197 } /* switch on type of operand */
1198
1199 if (losing)
1200 break;
1201 } /* for each operand */
1202 } /* if immediately wrong */
1203
1204 if (!losing)
1205 {
1206 break;
1207 } /* got it. */
1208
1209 opcode = opcode->m_next;
1210
1211 if (!opcode)
1212 {
1213 if (ok_arch
1214 && !(ok_arch & current_architecture))
1215 {
1216 char buf[200], *cp;
1217 int len;
1218 strcpy (buf,
1219 "invalid instruction for this architecture; needs ");
1220 cp = buf + strlen (buf);
1221 switch (ok_arch)
1222 {
1223 case mfloat:
1224 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1225 break;
1226 case mmmu:
1227 strcpy (cp, "mmu (68030 or 68851)");
1228 break;
1229 case m68020up:
1230 strcpy (cp, "68020 or higher");
1231 break;
1232 case m68000up:
1233 strcpy (cp, "68000 or higher");
1234 break;
1235 case m68010up:
1236 strcpy (cp, "68010 or higher");
1237 break;
1238 default:
1239 {
1240 int got_one = 0, idx;
1241 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1242 idx++)
1243 {
1244 if (archs[idx].arch & ok_arch)
1245 {
1246 if (got_one)
1247 {
1248 strcpy (cp, " or ");
1249 cp += strlen (cp);
1250 }
1251 got_one = 1;
1252 strcpy (cp, archs[idx].name);
1253 cp += strlen (cp);
1254 }
1255 }
1256 }
1257 }
1258 len = cp - buf + 1;
1259 cp = malloc (len);
1260 strcpy (cp, buf);
1261 the_ins.error = cp;
1262 }
1263 else
1264 the_ins.error = "operands mismatch";
1265 return;
1266 } /* Fell off the end */
1267
1268 losing = 0;
1269 }
1270
1271 /* now assemble it */
1272
1273 the_ins.args = opcode->m_operands;
1274 the_ins.numargs = opcode->m_opnum;
1275 the_ins.numo = opcode->m_codenum;
1276 the_ins.opcode[0] = getone (opcode);
1277 the_ins.opcode[1] = gettwo (opcode);
1278
1279 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1280 {
1281 /* This switch is a doozy.
1282 Watch the first step; its a big one! */
1283 switch (s[0])
1284 {
1285
1286 case '*':
1287 case '~':
1288 case '%':
1289 case ';':
1290 case '@':
1291 case '!':
1292 case '&':
1293 case '$':
1294 case '?':
1295 case '/':
1296 case '`':
1297 #ifndef NO_68851
1298 case '|':
1299 #endif
1300 switch (opP->mode)
1301 {
1302 case IMMED:
1303 tmpreg = 0x3c; /* 7.4 */
1304 if (strchr ("bwl", s[1]))
1305 nextword = get_num (&opP->disp, 80);
1306 else
1307 nextword = get_num (&opP->disp, 0);
1308 if (isvar (&opP->disp))
1309 add_fix (s[1], &opP->disp, 0, 0);
1310 switch (s[1])
1311 {
1312 case 'b':
1313 if (!isbyte (nextword))
1314 opP->error = "operand out of range";
1315 addword (nextword);
1316 baseo = 0;
1317 break;
1318 case 'w':
1319 if (!isword (nextword))
1320 opP->error = "operand out of range";
1321 addword (nextword);
1322 baseo = 0;
1323 break;
1324 case 'l':
1325 addword (nextword >> 16);
1326 addword (nextword);
1327 baseo = 0;
1328 break;
1329
1330 case 'f':
1331 baseo = 2;
1332 outro = 8;
1333 break;
1334 case 'F':
1335 baseo = 4;
1336 outro = 11;
1337 break;
1338 case 'x':
1339 baseo = 6;
1340 outro = 15;
1341 break;
1342 case 'p':
1343 baseo = 6;
1344 outro = -1;
1345 break;
1346 default:
1347 abort ();
1348 }
1349 if (!baseo)
1350 break;
1351
1352 /* We gotta put out some float */
1353 if (op (&opP->disp) != O_big)
1354 {
1355 valueT val;
1356 int gencnt;
1357
1358 /* Can other cases happen here? */
1359 if (op (&opP->disp) != O_constant)
1360 abort ();
1361
1362 val = (valueT) offs (&opP->disp);
1363 gencnt = 0;
1364 do
1365 {
1366 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1367 val >>= LITTLENUM_NUMBER_OF_BITS;
1368 ++gencnt;
1369 }
1370 while (val != 0);
1371 offs (&opP->disp) = gencnt;
1372 }
1373 if (offs (&opP->disp) > 0)
1374 {
1375 if (offs (&opP->disp) > baseo)
1376 {
1377 as_warn ("Bignum too big for %c format; truncated",
1378 s[1]);
1379 offs (&opP->disp) = baseo;
1380 }
1381 baseo -= offs (&opP->disp);
1382 while (baseo--)
1383 addword (0);
1384 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1385 offs (&opP->disp)--;
1386 --wordp)
1387 addword (*wordp);
1388 break;
1389 }
1390 gen_to_words (words, baseo, (long) outro);
1391 for (wordp = words; baseo--; wordp++)
1392 addword (*wordp);
1393 break;
1394 case DREG:
1395 tmpreg = opP->reg - DATA; /* 0.dreg */
1396 break;
1397 case AREG:
1398 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1399 break;
1400 case AINDR:
1401 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1402 break;
1403 case ADEC:
1404 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1405 break;
1406 case AINC:
1407 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1408 break;
1409 case DISP:
1410
1411 nextword = get_num (&opP->disp, 80);
1412 /* Force into index mode. Hope this works */
1413
1414 /* We do the first bit for 32-bit displacements, and the
1415 second bit for 16 bit ones. It is possible that we
1416 should make the default be WORD instead of LONG, but
1417 I think that'd break GCC, so we put up with a little
1418 inefficiency for the sake of working output. */
1419
1420 if (!issword (nextword)
1421 || (isvar (&opP->disp)
1422 && ((opP->disp.size == SIZE_UNSPEC
1423 && flag_short_refs == 0
1424 && cpu_of_arch (current_architecture) >= m68020)
1425 || opP->disp.size == SIZE_LONG)))
1426 {
1427 if (opP->reg == PC)
1428 tmpreg = 0x3B; /* 7.3 */
1429 else
1430 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1431 if (isvar (&opP->disp))
1432 {
1433 if (opP->reg == PC)
1434 {
1435 #if 0
1436 addword (0x0170);
1437 add_fix ('l', &opP->disp, 1, 2);
1438 addword (0), addword (0);
1439 #else
1440 add_frag (adds (&opP->disp),
1441 offs (&opP->disp),
1442 TAB (PCLEA, SZ_UNDEF));
1443 #endif
1444 break;
1445 }
1446 else
1447 {
1448 addword (0x0170);
1449 add_fix ('l', &opP->disp, 0, 0);
1450 }
1451 }
1452 else
1453 addword (0x0170);
1454 addword (nextword >> 16);
1455 }
1456 else
1457 {
1458 if (opP->reg == PC)
1459 tmpreg = 0x3A; /* 7.2 */
1460 else
1461 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1462
1463 if (isvar (&opP->disp))
1464 {
1465 if (opP->reg == PC)
1466 {
1467 add_fix ('w', &opP->disp, 1, 0);
1468 }
1469 else
1470 add_fix ('w', &opP->disp, 0, 0);
1471 }
1472 }
1473 addword (nextword);
1474 break;
1475
1476 case POST:
1477 case PRE:
1478 case BASE:
1479 nextword = 0;
1480 baseo = get_num (&opP->disp, 80);
1481 if (opP->mode == POST || opP->mode == PRE)
1482 outro = get_num (&opP->odisp, 80);
1483 /* Figure out the `addressing mode'.
1484 Also turn on the BASE_DISABLE bit, if needed. */
1485 if (opP->reg == PC || opP->reg == ZPC)
1486 {
1487 tmpreg = 0x3b; /* 7.3 */
1488 if (opP->reg == ZPC)
1489 nextword |= 0x80;
1490 }
1491 else if (opP->reg == 0)
1492 {
1493 nextword |= 0x80;
1494 tmpreg = 0x30; /* 6.garbage */
1495 }
1496 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1497 {
1498 nextword |= 0x80;
1499 tmpreg = 0x30 + opP->reg - ZADDR0;
1500 }
1501 else
1502 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1503
1504 siz1 = opP->disp.size;
1505 if (opP->mode == POST || opP->mode == PRE)
1506 siz2 = opP->odisp.size;
1507 else
1508 siz2 = SIZE_UNSPEC;
1509
1510 /* Index register stuff */
1511 if (opP->index.reg != 0
1512 && opP->index.reg >= DATA
1513 && opP->index.reg <= ADDR7)
1514 {
1515 nextword |= (opP->index.reg - DATA) << 12;
1516
1517 if (opP->index.size == SIZE_UNSPEC
1518 || opP->index.size == SIZE_LONG)
1519 nextword |= 0x800;
1520
1521 if (cpu_of_arch (current_architecture) < m68020)
1522 {
1523 if (opP->index.scale != 1)
1524 {
1525 opP->error =
1526 "scale factor invalid on this architecture; needs 68020 or higher";
1527 }
1528 }
1529
1530 switch (opP->index.scale)
1531 {
1532 case 1:
1533 break;
1534 case 2:
1535 nextword |= 0x200;
1536 break;
1537 case 4:
1538 nextword |= 0x400;
1539 break;
1540 case 8:
1541 nextword |= 0x600;
1542 break;
1543 default:
1544 abort ();
1545 }
1546 /* IF its simple,
1547 GET US OUT OF HERE! */
1548
1549 /* Must be INDEX, with an index register. Address
1550 register cannot be ZERO-PC, and either :b was
1551 forced, or we know it will fit. For a 68000 or
1552 68010, force this mode anyways, because the
1553 larger modes aren't supported. */
1554 if (opP->mode == BASE
1555 && ((opP->reg >= ADDR0
1556 && opP->reg <= ADDR7)
1557 || opP->reg == PC))
1558 {
1559 if (siz1 == SIZE_BYTE
1560 || cpu_of_arch (current_architecture) < m68020
1561 || (siz1 == SIZE_UNSPEC
1562 && ! isvar (&opP->disp)
1563 && issbyte (baseo)))
1564 {
1565 nextword += baseo & 0xff;
1566 addword (nextword);
1567 if (isvar (&opP->disp))
1568 {
1569 /* Do a byte relocation. If it doesn't
1570 fit (possible on m68000) let the
1571 fixup processing complain later. */
1572 if (opP->reg == PC)
1573 add_fix ('B', &opP->disp, 1, 1);
1574 else
1575 add_fix ('B', &opP->disp, 0, 0);
1576 }
1577 else if (siz1 != SIZE_BYTE)
1578 {
1579 if (siz1 != SIZE_UNSPEC)
1580 as_warn ("Forcing byte displacement");
1581 if (! issbyte (baseo))
1582 opP->error = "byte displacement out of range";
1583 }
1584
1585 break;
1586 }
1587 else if (siz1 == SIZE_UNSPEC
1588 && opP->reg == PC
1589 && isvar (&opP->disp)
1590 && subs (&opP->disp) == NULL)
1591 {
1592 nextword += baseo & 0xff;
1593 addword (nextword);
1594 add_frag (adds (&opP->disp), offs (&opP->disp),
1595 TAB (PCINDEX, SZ_UNDEF));
1596
1597 break;
1598 }
1599 }
1600 }
1601 else
1602 {
1603 nextword |= 0x40; /* No index reg */
1604 if (opP->index.reg >= ZDATA0
1605 && opP->index.reg <= ZDATA7)
1606 nextword |= (opP->index.reg - ZDATA0) << 12;
1607 else if (opP->index.reg >= ZADDR0
1608 || opP->index.reg <= ZADDR7)
1609 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1610 }
1611
1612 /* It isn't simple. */
1613
1614 if (cpu_of_arch (current_architecture) < m68020)
1615 opP->error =
1616 "invalid operand mode for this architecture; needs 68020 or higher";
1617
1618 nextword |= 0x100;
1619 /* If the guy specified a width, we assume that it is
1620 wide enough. Maybe it isn't. If so, we lose. */
1621 switch (siz1)
1622 {
1623 case SIZE_UNSPEC:
1624 if (isvar (&opP->disp) || !issword (baseo))
1625 {
1626 siz1 = SIZE_LONG;
1627 nextword |= 0x30;
1628 }
1629 else if (baseo == 0)
1630 nextword |= 0x10;
1631 else
1632 {
1633 nextword |= 0x20;
1634 siz1 = SIZE_WORD;
1635 }
1636 break;
1637 case SIZE_BYTE:
1638 as_warn (":b not permitted; defaulting to :w");
1639 /* Fall through. */
1640 case SIZE_WORD:
1641 nextword |= 0x20;
1642 break;
1643 case SIZE_LONG:
1644 nextword |= 0x30;
1645 break;
1646 }
1647
1648 /* Figure out innner displacement stuff */
1649 if (opP->mode == POST || opP->mode == PRE)
1650 {
1651 switch (siz2)
1652 {
1653 case SIZE_UNSPEC:
1654 if (isvar (&opP->odisp) || !issword (outro))
1655 {
1656 siz2 = SIZE_LONG;
1657 nextword |= 0x3;
1658 }
1659 else if (outro == 0)
1660 nextword |= 0x1;
1661 else
1662 {
1663 nextword |= 0x2;
1664 siz2 = SIZE_WORD;
1665 }
1666 break;
1667 case 1:
1668 as_warn (":b not permitted; defaulting to :w");
1669 /* Fall through. */
1670 case 2:
1671 nextword |= 0x2;
1672 break;
1673 case 3:
1674 nextword |= 0x3;
1675 break;
1676 }
1677 if (opP->mode == POST)
1678 nextword |= 0x04;
1679 }
1680 addword (nextword);
1681
1682 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1683 {
1684 if (opP->reg == PC || opP->reg == ZPC)
1685 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1686 else
1687 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1688 }
1689 if (siz1 == SIZE_LONG)
1690 addword (baseo >> 16);
1691 if (siz1 != SIZE_UNSPEC)
1692 addword (baseo);
1693
1694 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1695 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1696 if (siz2 == SIZE_LONG)
1697 addword (outro >> 16);
1698 if (siz2 != SIZE_UNSPEC)
1699 addword (outro);
1700
1701 break;
1702
1703 case ABSL:
1704 nextword = get_num (&opP->disp, 80);
1705 switch (opP->disp.size)
1706 {
1707 default:
1708 abort ();
1709 case SIZE_UNSPEC:
1710 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1711 {
1712 tmpreg = 0x38; /* 7.0 */
1713 addword (nextword);
1714 break;
1715 }
1716 /* Don't generate pc relative code on 68010 and
1717 68000. */
1718 if (isvar (&opP->disp)
1719 && !subs (&opP->disp)
1720 && adds (&opP->disp)
1721 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
1722 && now_seg == text_section
1723 && cpu_of_arch (current_architecture) >= m68020
1724 && !flag_long_jumps
1725 && !strchr ("~%&$?", s[0]))
1726 {
1727 tmpreg = 0x3A; /* 7.2 */
1728 add_frag (adds (&opP->disp),
1729 offs (&opP->disp),
1730 TAB (PCREL, SZ_UNDEF));
1731 break;
1732 }
1733 /* Fall through into long */
1734 case SIZE_LONG:
1735 if (isvar (&opP->disp))
1736 add_fix ('l', &opP->disp, 0, 0);
1737
1738 tmpreg = 0x39;/* 7.1 mode */
1739 addword (nextword >> 16);
1740 addword (nextword);
1741 break;
1742
1743 case SIZE_WORD: /* Word */
1744 if (isvar (&opP->disp))
1745 add_fix ('w', &opP->disp, 0, 0);
1746
1747 tmpreg = 0x38;/* 7.0 mode */
1748 addword (nextword);
1749 break;
1750 }
1751 break;
1752 case CONTROL:
1753 case FPREG:
1754 default:
1755 as_bad ("unknown/incorrect operand");
1756 /* abort(); */
1757 }
1758 install_gen_operand (s[1], tmpreg);
1759 break;
1760
1761 case '#':
1762 case '^':
1763 switch (s[1])
1764 { /* JF: I hate floating point! */
1765 case 'j':
1766 tmpreg = 70;
1767 break;
1768 case '8':
1769 tmpreg = 20;
1770 break;
1771 case 'C':
1772 tmpreg = 50;
1773 break;
1774 case '3':
1775 default:
1776 tmpreg = 80;
1777 break;
1778 }
1779 tmpreg = get_num (&opP->disp, tmpreg);
1780 if (isvar (&opP->disp))
1781 add_fix (s[1], &opP->disp, 0, 0);
1782 switch (s[1])
1783 {
1784 case 'b': /* Danger: These do no check for
1785 certain types of overflow.
1786 user beware! */
1787 if (!isbyte (tmpreg))
1788 opP->error = "out of range";
1789 insop (tmpreg, opcode);
1790 if (isvar (&opP->disp))
1791 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1792 break;
1793 case 'w':
1794 if (!isword (tmpreg))
1795 opP->error = "out of range";
1796 insop (tmpreg, opcode);
1797 if (isvar (&opP->disp))
1798 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1799 break;
1800 case 'l':
1801 /* Because of the way insop works, we put these two out
1802 backwards. */
1803 insop (tmpreg, opcode);
1804 insop (tmpreg >> 16, opcode);
1805 if (isvar (&opP->disp))
1806 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1807 break;
1808 case '3':
1809 tmpreg &= 0xFF;
1810 case '8':
1811 case 'C':
1812 install_operand (s[1], tmpreg);
1813 break;
1814 default:
1815 abort ();
1816 }
1817 break;
1818
1819 case '+':
1820 case '-':
1821 case 'A':
1822 case 'a':
1823 install_operand (s[1], opP->reg - ADDR);
1824 break;
1825
1826 case 'B':
1827 tmpreg = get_num (&opP->disp, 80);
1828 switch (s[1])
1829 {
1830 case 'B':
1831 add_fix ('B', &opP->disp, 1, -1);
1832 break;
1833 case 'W':
1834 add_fix ('w', &opP->disp, 1, 0);
1835 addword (0);
1836 break;
1837 case 'L':
1838 long_branch:
1839 if (cpu_of_arch (current_architecture) < m68020)
1840 as_warn ("Can't use long branches on 68000/68010");
1841 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1842 add_fix ('l', &opP->disp, 1, 0);
1843 addword (0);
1844 addword (0);
1845 break;
1846 case 'g':
1847 if (subs (&opP->disp)) /* We can't relax it */
1848 goto long_branch;
1849
1850 /* This could either be a symbol, or an absolute
1851 address. No matter, the frag hacking will finger it
1852 out. Not quite: it can't switch from BRANCH to
1853 BCC68000 for the case where opnd is absolute (it
1854 needs to use the 68000 hack since no conditional abs
1855 jumps). */
1856 if (((cpu_of_arch (current_architecture) < m68020)
1857 || (0 == adds (&opP->disp)))
1858 && (the_ins.opcode[0] >= 0x6200)
1859 && (the_ins.opcode[0] <= 0x6f00))
1860 add_frag (adds (&opP->disp), offs (&opP->disp),
1861 TAB (BCC68000, SZ_UNDEF));
1862 else
1863 add_frag (adds (&opP->disp), offs (&opP->disp),
1864 TAB (ABRANCH, SZ_UNDEF));
1865 break;
1866 case 'w':
1867 if (isvar (&opP->disp))
1868 {
1869 #if 1
1870 /* check for DBcc instruction */
1871 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1872 {
1873 /* size varies if patch */
1874 /* needed for long form */
1875 add_frag (adds (&opP->disp), offs (&opP->disp),
1876 TAB (DBCC, SZ_UNDEF));
1877 break;
1878 }
1879 #endif
1880 add_fix ('w', &opP->disp, 1, 0);
1881 }
1882 addword (0);
1883 break;
1884 case 'C': /* Fixed size LONG coproc branches */
1885 add_fix ('l', &opP->disp, 1, 0);
1886 addword (0);
1887 addword (0);
1888 break;
1889 case 'c': /* Var size Coprocesssor branches */
1890 if (subs (&opP->disp))
1891 {
1892 add_fix ('l', &opP->disp, 1, 0);
1893 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1894 }
1895 else if (adds (&opP->disp))
1896 add_frag (adds (&opP->disp), offs (&opP->disp),
1897 TAB (FBRANCH, SZ_UNDEF));
1898 else
1899 {
1900 /* add_frag((symbolS *) 0, offs(&opP->disp),
1901 TAB(FBRANCH,SHORT)); */
1902 the_ins.opcode[the_ins.numo - 1] |= 0x40;
1903 add_fix ('l', &opP->disp, 1, 0);
1904 addword (0);
1905 addword (0);
1906 }
1907 break;
1908 default:
1909 abort ();
1910 }
1911 break;
1912
1913 case 'C': /* Ignore it */
1914 break;
1915
1916 case 'd': /* JF this is a kludge */
1917 install_operand ('s', opP->reg - ADDR);
1918 tmpreg = get_num (&opP->disp, 80);
1919 if (!issword (tmpreg))
1920 {
1921 as_warn ("Expression out of range, using 0");
1922 tmpreg = 0;
1923 }
1924 addword (tmpreg);
1925 break;
1926
1927 case 'D':
1928 install_operand (s[1], opP->reg - DATA);
1929 break;
1930
1931 case 'F':
1932 install_operand (s[1], opP->reg - FP0);
1933 break;
1934
1935 case 'I':
1936 tmpreg = opP->reg - COP0;
1937 install_operand (s[1], tmpreg);
1938 break;
1939
1940 case 'J': /* JF foo */
1941 switch (opP->reg)
1942 {
1943 case SFC:
1944 tmpreg = 0x000;
1945 break;
1946 case DFC:
1947 tmpreg = 0x001;
1948 break;
1949 case CACR:
1950 tmpreg = 0x002;
1951 break;
1952 case TC:
1953 tmpreg = 0x003;
1954 break;
1955 case ITT0:
1956 tmpreg = 0x004;
1957 break;
1958 case ITT1:
1959 tmpreg = 0x005;
1960 break;
1961 case DTT0:
1962 tmpreg = 0x006;
1963 break;
1964 case DTT1:
1965 tmpreg = 0x007;
1966 break;
1967 case BUSCR:
1968 tmpreg = 0x008;
1969 break;
1970
1971 case USP:
1972 tmpreg = 0x800;
1973 break;
1974 case VBR:
1975 tmpreg = 0x801;
1976 break;
1977 case CAAR:
1978 tmpreg = 0x802;
1979 break;
1980 case MSP:
1981 tmpreg = 0x803;
1982 break;
1983 case ISP:
1984 tmpreg = 0x804;
1985 break;
1986 case MMUSR:
1987 tmpreg = 0x805;
1988 break;
1989 case URP:
1990 tmpreg = 0x806;
1991 break;
1992 case SRP:
1993 tmpreg = 0x807;
1994 break;
1995 case PCR:
1996 tmpreg = 0x808;
1997 break;
1998 default:
1999 abort ();
2000 }
2001 install_operand (s[1], tmpreg);
2002 break;
2003
2004 case 'k':
2005 tmpreg = get_num (&opP->disp, 55);
2006 install_operand (s[1], tmpreg & 0x7f);
2007 break;
2008
2009 case 'l':
2010 tmpreg = opP->mask;
2011 if (s[1] == 'w')
2012 {
2013 if (tmpreg & 0x7FF0000)
2014 as_bad ("Floating point register in register list");
2015 insop (reverse_16_bits (tmpreg), opcode);
2016 }
2017 else
2018 {
2019 if (tmpreg & 0x700FFFF)
2020 as_bad ("Wrong register in floating-point reglist");
2021 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2022 }
2023 break;
2024
2025 case 'L':
2026 tmpreg = opP->mask;
2027 if (s[1] == 'w')
2028 {
2029 if (tmpreg & 0x7FF0000)
2030 as_bad ("Floating point register in register list");
2031 insop (tmpreg, opcode);
2032 }
2033 else if (s[1] == '8')
2034 {
2035 if (tmpreg & 0x0FFFFFF)
2036 as_bad ("incorrect register in reglist");
2037 install_operand (s[1], tmpreg >> 24);
2038 }
2039 else
2040 {
2041 if (tmpreg & 0x700FFFF)
2042 as_bad ("wrong register in floating-point reglist");
2043 else
2044 install_operand (s[1], tmpreg >> 16);
2045 }
2046 break;
2047
2048 case 'M':
2049 install_operand (s[1], get_num (&opP->disp, 60));
2050 break;
2051
2052 case 'O':
2053 tmpreg = ((opP->mode == DREG)
2054 ? 0x20 + opP->reg - DATA
2055 : (get_num (&opP->disp, 40) & 0x1F));
2056 install_operand (s[1], tmpreg);
2057 break;
2058
2059 case 'Q':
2060 tmpreg = get_num (&opP->disp, 10);
2061 if (tmpreg == 8)
2062 tmpreg = 0;
2063 install_operand (s[1], tmpreg);
2064 break;
2065
2066 case 'R':
2067 /* This depends on the fact that ADDR registers are eight
2068 more than their corresponding DATA regs, so the result
2069 will have the ADDR_REG bit set */
2070 install_operand (s[1], opP->reg - DATA);
2071 break;
2072
2073 case 'r':
2074 if (opP->mode == AINDR)
2075 install_operand (s[1], opP->reg - DATA);
2076 else
2077 install_operand (s[1], opP->index.reg - DATA);
2078 break;
2079
2080 case 's':
2081 if (opP->reg == FPI)
2082 tmpreg = 0x1;
2083 else if (opP->reg == FPS)
2084 tmpreg = 0x2;
2085 else if (opP->reg == FPC)
2086 tmpreg = 0x4;
2087 else
2088 abort ();
2089 install_operand (s[1], tmpreg);
2090 break;
2091
2092 case 'S': /* Ignore it */
2093 break;
2094
2095 case 'T':
2096 install_operand (s[1], get_num (&opP->disp, 30));
2097 break;
2098
2099 case 'U': /* Ignore it */
2100 break;
2101
2102 case 'c':
2103 switch (opP->reg)
2104 {
2105 case NC:
2106 tmpreg = 0;
2107 break;
2108 case DC:
2109 tmpreg = 1;
2110 break;
2111 case IC:
2112 tmpreg = 2;
2113 break;
2114 case BC:
2115 tmpreg = 3;
2116 break;
2117 default:
2118 as_fatal ("failed sanity check");
2119 } /* switch on cache token */
2120 install_operand (s[1], tmpreg);
2121 break;
2122 #ifndef NO_68851
2123 /* JF: These are out of order, I fear. */
2124 case 'f':
2125 switch (opP->reg)
2126 {
2127 case SFC:
2128 tmpreg = 0;
2129 break;
2130 case DFC:
2131 tmpreg = 1;
2132 break;
2133 default:
2134 abort ();
2135 }
2136 install_operand (s[1], tmpreg);
2137 break;
2138
2139 case 'P':
2140 switch (opP->reg)
2141 {
2142 case TC:
2143 tmpreg = 0;
2144 break;
2145 case CAL:
2146 tmpreg = 4;
2147 break;
2148 case VAL:
2149 tmpreg = 5;
2150 break;
2151 case SCC:
2152 tmpreg = 6;
2153 break;
2154 case AC:
2155 tmpreg = 7;
2156 break;
2157 default:
2158 abort ();
2159 }
2160 install_operand (s[1], tmpreg);
2161 break;
2162
2163 case 'V':
2164 if (opP->reg == VAL)
2165 break;
2166 abort ();
2167
2168 case 'W':
2169 switch (opP->reg)
2170 {
2171 case DRP:
2172 tmpreg = 1;
2173 break;
2174 case SRP:
2175 tmpreg = 2;
2176 break;
2177 case CRP:
2178 tmpreg = 3;
2179 break;
2180 default:
2181 abort ();
2182 }
2183 install_operand (s[1], tmpreg);
2184 break;
2185
2186 case 'X':
2187 switch (opP->reg)
2188 {
2189 case BAD:
2190 case BAD + 1:
2191 case BAD + 2:
2192 case BAD + 3:
2193 case BAD + 4:
2194 case BAD + 5:
2195 case BAD + 6:
2196 case BAD + 7:
2197 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2198 break;
2199
2200 case BAC:
2201 case BAC + 1:
2202 case BAC + 2:
2203 case BAC + 3:
2204 case BAC + 4:
2205 case BAC + 5:
2206 case BAC + 6:
2207 case BAC + 7:
2208 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2209 break;
2210
2211 default:
2212 abort ();
2213 }
2214 install_operand (s[1], tmpreg);
2215 break;
2216 case 'Y':
2217 know (opP->reg == PSR);
2218 break;
2219 case 'Z':
2220 know (opP->reg == PCSR);
2221 break;
2222 #endif /* m68851 */
2223 case '3':
2224 switch (opP->reg)
2225 {
2226 case TT0:
2227 tmpreg = 2;
2228 break;
2229 case TT1:
2230 tmpreg = 3;
2231 break;
2232 default:
2233 abort ();
2234 }
2235 install_operand (s[1], tmpreg);
2236 break;
2237 case 't':
2238 tmpreg = get_num (&opP->disp, 20);
2239 install_operand (s[1], tmpreg);
2240 break;
2241 case '_': /* used only for move16 absolute 32-bit address */
2242 tmpreg = get_num (&opP->disp, 80);
2243 addword (tmpreg >> 16);
2244 addword (tmpreg & 0xFFFF);
2245 break;
2246 default:
2247 abort ();
2248 }
2249 }
2250
2251 /* By the time whe get here (FINALLY) the_ins contains the complete
2252 instruction, ready to be emitted. . . */
2253 }
2254
2255 static int
2256 reverse_16_bits (in)
2257 int in;
2258 {
2259 int out = 0;
2260 int n;
2261
2262 static int mask[16] =
2263 {
2264 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2265 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2266 };
2267 for (n = 0; n < 16; n++)
2268 {
2269 if (in & mask[n])
2270 out |= mask[15 - n];
2271 }
2272 return out;
2273 } /* reverse_16_bits() */
2274
2275 static int
2276 reverse_8_bits (in)
2277 int in;
2278 {
2279 int out = 0;
2280 int n;
2281
2282 static int mask[8] =
2283 {
2284 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2285 };
2286
2287 for (n = 0; n < 8; n++)
2288 {
2289 if (in & mask[n])
2290 out |= mask[7 - n];
2291 }
2292 return out;
2293 } /* reverse_8_bits() */
2294
2295 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2296 (that value is chosen in the frag_var call in md_assemble). TYPE
2297 is the subtype of the frag to be generated; its primary type is
2298 rs_machine_dependent.
2299
2300 The TYPE parameter is also used by md_convert_frag_1 and
2301 md_estimate_size_before_relax. The appropriate type of fixup will
2302 be emitted by md_convert_frag_1.
2303
2304 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2305 static void
2306 install_operand (mode, val)
2307 int mode;
2308 int val;
2309 {
2310 switch (mode)
2311 {
2312 case 's':
2313 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2314 break;
2315 case 'd':
2316 the_ins.opcode[0] |= val << 9;
2317 break;
2318 case '1':
2319 the_ins.opcode[1] |= val << 12;
2320 break;
2321 case '2':
2322 the_ins.opcode[1] |= val << 6;
2323 break;
2324 case '3':
2325 the_ins.opcode[1] |= val;
2326 break;
2327 case '4':
2328 the_ins.opcode[2] |= val << 12;
2329 break;
2330 case '5':
2331 the_ins.opcode[2] |= val << 6;
2332 break;
2333 case '6':
2334 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2335 three words long! */
2336 the_ins.numo++;
2337 the_ins.opcode[2] |= val;
2338 break;
2339 case '7':
2340 the_ins.opcode[1] |= val << 7;
2341 break;
2342 case '8':
2343 the_ins.opcode[1] |= val << 10;
2344 break;
2345 #ifndef NO_68851
2346 case '9':
2347 the_ins.opcode[1] |= val << 5;
2348 break;
2349 #endif
2350
2351 case 't':
2352 the_ins.opcode[1] |= (val << 10) | (val << 7);
2353 break;
2354 case 'D':
2355 the_ins.opcode[1] |= (val << 12) | val;
2356 break;
2357 case 'g':
2358 the_ins.opcode[0] |= val = 0xff;
2359 break;
2360 case 'i':
2361 the_ins.opcode[0] |= val << 9;
2362 break;
2363 case 'C':
2364 the_ins.opcode[1] |= val;
2365 break;
2366 case 'j':
2367 the_ins.opcode[1] |= val;
2368 the_ins.numo++; /* What a hack */
2369 break;
2370 case 'k':
2371 the_ins.opcode[1] |= val << 4;
2372 break;
2373 case 'b':
2374 case 'w':
2375 case 'l':
2376 break;
2377 case 'e':
2378 the_ins.opcode[0] |= (val << 6);
2379 break;
2380 case 'L':
2381 the_ins.opcode[1] = (val >> 16);
2382 the_ins.opcode[2] = val & 0xffff;
2383 break;
2384 case 'c':
2385 default:
2386 as_fatal ("failed sanity check.");
2387 }
2388 } /* install_operand() */
2389
2390 static void
2391 install_gen_operand (mode, val)
2392 int mode;
2393 int val;
2394 {
2395 switch (mode)
2396 {
2397 case 's':
2398 the_ins.opcode[0] |= val;
2399 break;
2400 case 'd':
2401 /* This is a kludge!!! */
2402 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2403 break;
2404 case 'b':
2405 case 'w':
2406 case 'l':
2407 case 'f':
2408 case 'F':
2409 case 'x':
2410 case 'p':
2411 the_ins.opcode[0] |= val;
2412 break;
2413 /* more stuff goes here */
2414 default:
2415 as_fatal ("failed sanity check.");
2416 }
2417 } /* install_gen_operand() */
2418
2419 /*
2420 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2421 * then deal with the bitfield hack.
2422 */
2423
2424 static char *
2425 crack_operand (str, opP)
2426 register char *str;
2427 register struct m68k_op *opP;
2428 {
2429 register int parens;
2430 register int c;
2431 register char *beg_str;
2432
2433 if (!str)
2434 {
2435 return str;
2436 }
2437 beg_str = str;
2438 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
2439 {
2440 if (*str == '(')
2441 parens++;
2442 else if (*str == ')')
2443 {
2444 if (!parens)
2445 { /* ERROR */
2446 opP->error = "Extra )";
2447 return str;
2448 }
2449 --parens;
2450 }
2451 }
2452 if (!*str && parens)
2453 { /* ERROR */
2454 opP->error = "Missing )";
2455 return str;
2456 }
2457 c = *str;
2458 *str = '\0';
2459 if (m68k_ip_op (beg_str, opP) != 0)
2460 {
2461 *str = c;
2462 return str;
2463 }
2464 *str = c;
2465 if (c == '}')
2466 c = *++str; /* JF bitfield hack */
2467 if (c)
2468 {
2469 c = *++str;
2470 if (!c)
2471 as_bad ("Missing operand");
2472 }
2473 return str;
2474 }
2475
2476 /* This is the guts of the machine-dependent assembler. STR points to a
2477 machine dependent instruction. This function is supposed to emit
2478 the frags/bytes it assembles to.
2479 */
2480
2481 void
2482 insert_reg (regname, regnum)
2483 char *regname;
2484 int regnum;
2485 {
2486 char buf[100];
2487 int i;
2488
2489 #ifdef REGISTER_PREFIX
2490 if (!flag_reg_prefix_optional)
2491 {
2492 buf[0] = REGISTER_PREFIX;
2493 strcpy (buf + 1, regname);
2494 regname = buf;
2495 }
2496 #endif
2497
2498 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2499 &zero_address_frag));
2500
2501 for (i = 0; regname[i]; i++)
2502 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2503 buf[i] = '\0';
2504
2505 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2506 &zero_address_frag));
2507 }
2508
2509 struct init_entry
2510 {
2511 const char *name;
2512 int number;
2513 };
2514
2515 static const struct init_entry init_table[] =
2516 {
2517 { "d0", DATA0 },
2518 { "d1", DATA1 },
2519 { "d2", DATA2 },
2520 { "d3", DATA3 },
2521 { "d4", DATA4 },
2522 { "d5", DATA5 },
2523 { "d6", DATA6 },
2524 { "d7", DATA7 },
2525 { "a0", ADDR0 },
2526 { "a1", ADDR1 },
2527 { "a2", ADDR2 },
2528 { "a3", ADDR3 },
2529 { "a4", ADDR4 },
2530 { "a5", ADDR5 },
2531 { "a6", ADDR6 },
2532 { "fp", ADDR6 },
2533 { "a7", ADDR7 },
2534 { "sp", ADDR7 },
2535 { "ssp", ADDR7 },
2536 { "fp0", FP0 },
2537 { "fp1", FP1 },
2538 { "fp2", FP2 },
2539 { "fp3", FP3 },
2540 { "fp4", FP4 },
2541 { "fp5", FP5 },
2542 { "fp6", FP6 },
2543 { "fp7", FP7 },
2544 { "fpi", FPI },
2545 { "fpiar", FPI },
2546 { "fpc", FPI },
2547 { "fps", FPS },
2548 { "fpsr", FPS },
2549 { "fpc", FPC },
2550 { "fpcr", FPC },
2551 { "control", FPC },
2552 { "status", FPS },
2553 { "iaddr", FPI },
2554
2555 { "cop0", COP0 },
2556 { "cop1", COP1 },
2557 { "cop2", COP2 },
2558 { "cop3", COP3 },
2559 { "cop4", COP4 },
2560 { "cop5", COP5 },
2561 { "cop6", COP6 },
2562 { "cop7", COP7 },
2563 { "pc", PC },
2564 { "zpc", ZPC },
2565 { "sr", SR },
2566
2567 { "ccr", CCR },
2568 { "cc", CCR },
2569
2570 { "usp", USP },
2571 { "isp", ISP },
2572 { "sfc", SFC },
2573 { "sfcr", SFC },
2574 { "dfc", DFC },
2575 { "dfcr", DFC },
2576 { "cacr", CACR },
2577 { "caar", CAAR },
2578
2579 { "vbr", VBR },
2580
2581 { "msp", MSP },
2582 { "itt0", ITT0 },
2583 { "itt1", ITT1 },
2584 { "dtt0", DTT0 },
2585 { "dtt1", DTT1 },
2586 { "mmusr", MMUSR },
2587 { "tc", TC },
2588 { "srp", SRP },
2589 { "urp", URP },
2590 { "buscr", BUSCR },
2591 { "pcr", PCR },
2592
2593 { "ac", AC },
2594 { "bc", BC },
2595 { "cal", CAL },
2596 { "crp", CRP },
2597 { "drp", DRP },
2598 { "pcsr", PCSR },
2599 { "psr", PSR },
2600 { "scc", SCC },
2601 { "val", VAL },
2602 { "bad0", BAD0 },
2603 { "bad1", BAD1 },
2604 { "bad2", BAD2 },
2605 { "bad3", BAD3 },
2606 { "bad4", BAD4 },
2607 { "bad5", BAD5 },
2608 { "bad6", BAD6 },
2609 { "bad7", BAD7 },
2610 { "bac0", BAC0 },
2611 { "bac1", BAC1 },
2612 { "bac2", BAC2 },
2613 { "bac3", BAC3 },
2614 { "bac4", BAC4 },
2615 { "bac5", BAC5 },
2616 { "bac6", BAC6 },
2617 { "bac7", BAC7 },
2618
2619 { "ic", IC },
2620 { "dc", DC },
2621 { "nc", NC },
2622
2623 { "tt0", TT0 },
2624 { "tt1", TT1 },
2625 /* 68ec030 versions of same */
2626 { "ac0", TT0 },
2627 { "ac1", TT1 },
2628 /* 68ec030 access control unit, identical to 030 MMU status reg */
2629 { "acusr", PSR },
2630
2631 /* Suppressed data and address registers. */
2632 { "zd0", ZDATA0 },
2633 { "zd1", ZDATA1 },
2634 { "zd2", ZDATA2 },
2635 { "zd3", ZDATA3 },
2636 { "zd4", ZDATA4 },
2637 { "zd5", ZDATA5 },
2638 { "zd6", ZDATA6 },
2639 { "zd7", ZDATA7 },
2640 { "za0", ZADDR0 },
2641 { "za1", ZADDR1 },
2642 { "za2", ZADDR2 },
2643 { "za3", ZADDR3 },
2644 { "za4", ZADDR4 },
2645 { "za5", ZADDR5 },
2646 { "za6", ZADDR6 },
2647 { "za7", ZADDR7 },
2648
2649 { 0, 0 }
2650 };
2651
2652 void
2653 init_regtable ()
2654 {
2655 int i;
2656 for (i = 0; init_table[i].name; i++)
2657 insert_reg (init_table[i].name, init_table[i].number);
2658 }
2659
2660 static int no_68851, no_68881;
2661
2662 #ifdef OBJ_AOUT
2663 /* a.out machine type. Default to 68020. */
2664 int m68k_aout_machtype = 2;
2665 #endif
2666
2667 void
2668 md_assemble (str)
2669 char *str;
2670 {
2671 const char *er;
2672 short *fromP;
2673 char *toP = NULL;
2674 int m, n = 0;
2675 char *to_beg_P;
2676 int shorts_this_frag;
2677 fixS *fixP;
2678
2679 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2680 m68k_ip (str);
2681 er = the_ins.error;
2682 if (!er)
2683 {
2684 for (n = 0; n < the_ins.numargs; n++)
2685 if (the_ins.operands[n].error)
2686 {
2687 er = the_ins.operands[n].error;
2688 break;
2689 }
2690 }
2691 if (er)
2692 {
2693 as_bad ("%s -- statement `%s' ignored", er, str);
2694 return;
2695 }
2696
2697 if (the_ins.nfrag == 0)
2698 {
2699 /* No frag hacking involved; just put it out */
2700 toP = frag_more (2 * the_ins.numo);
2701 fromP = &the_ins.opcode[0];
2702 for (m = the_ins.numo; m; --m)
2703 {
2704 md_number_to_chars (toP, (long) (*fromP), 2);
2705 toP += 2;
2706 fromP++;
2707 }
2708 /* put out symbol-dependent info */
2709 for (m = 0; m < the_ins.nrel; m++)
2710 {
2711 switch (the_ins.reloc[m].wid)
2712 {
2713 case 'B':
2714 n = 1;
2715 break;
2716 case 'b':
2717 n = 1;
2718 break;
2719 case '3':
2720 n = 2;
2721 break;
2722 case 'w':
2723 n = 2;
2724 break;
2725 case 'l':
2726 n = 4;
2727 break;
2728 default:
2729 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2730 the_ins.reloc[m].wid);
2731 }
2732
2733 fixP = fix_new_exp (frag_now,
2734 ((toP - frag_now->fr_literal)
2735 - the_ins.numo * 2 + the_ins.reloc[m].n),
2736 n,
2737 &the_ins.reloc[m].exp,
2738 the_ins.reloc[m].pcrel,
2739 NO_RELOC);
2740 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2741 }
2742 return;
2743 }
2744
2745 /* There's some frag hacking */
2746 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2747 {
2748 int wid;
2749
2750 if (n == 0)
2751 wid = 2 * the_ins.fragb[n].fragoff;
2752 else
2753 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2754 toP = frag_more (wid);
2755 to_beg_P = toP;
2756 shorts_this_frag = 0;
2757 for (m = wid / 2; m; --m)
2758 {
2759 md_number_to_chars (toP, (long) (*fromP), 2);
2760 toP += 2;
2761 fromP++;
2762 shorts_this_frag++;
2763 }
2764 for (m = 0; m < the_ins.nrel; m++)
2765 {
2766 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2767 {
2768 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2769 break;
2770 }
2771 wid = the_ins.reloc[m].wid;
2772 if (wid == 0)
2773 continue;
2774 the_ins.reloc[m].wid = 0;
2775 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2776
2777 fixP = fix_new_exp (frag_now,
2778 ((toP - frag_now->fr_literal)
2779 - the_ins.numo * 2 + the_ins.reloc[m].n),
2780 wid,
2781 &the_ins.reloc[m].exp,
2782 the_ins.reloc[m].pcrel,
2783 NO_RELOC);
2784 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2785 }
2786 (void) frag_var (rs_machine_dependent, 10, 0,
2787 (relax_substateT) (the_ins.fragb[n].fragty),
2788 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2789 }
2790 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2791 shorts_this_frag = 0;
2792 if (n)
2793 {
2794 toP = frag_more (n * sizeof (short));
2795 while (n--)
2796 {
2797 md_number_to_chars (toP, (long) (*fromP), 2);
2798 toP += 2;
2799 fromP++;
2800 shorts_this_frag++;
2801 }
2802 }
2803 for (m = 0; m < the_ins.nrel; m++)
2804 {
2805 int wid;
2806
2807 wid = the_ins.reloc[m].wid;
2808 if (wid == 0)
2809 continue;
2810 the_ins.reloc[m].wid = 0;
2811 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2812
2813 fixP = fix_new_exp (frag_now,
2814 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2815 - shorts_this_frag * 2),
2816 wid,
2817 &the_ins.reloc[m].exp,
2818 the_ins.reloc[m].pcrel,
2819 NO_RELOC);
2820 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2821 }
2822 }
2823
2824 void
2825 md_begin ()
2826 {
2827 /*
2828 * md_begin -- set up hash tables with 68000 instructions.
2829 * similar to what the vax assembler does. ---phr
2830 */
2831 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2832 a copy of it at runtime, adding in the information we want but isn't
2833 there. I think it'd be better to have an awk script hack the table
2834 at compile time. Or even just xstr the table and use it as-is. But
2835 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2836 names. */
2837
2838 register const struct m68k_opcode *ins;
2839 register struct m68k_incant *hack, *slak;
2840 register const char *retval = 0; /* empty string, or error msg text */
2841 register unsigned int i;
2842 register char c;
2843
2844 if (flag_mri)
2845 flag_reg_prefix_optional = 1;
2846
2847 op_hash = hash_new ();
2848
2849 obstack_begin (&robyn, 4000);
2850 for (i = 0; i < m68k_numopcodes; i++)
2851 {
2852 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2853 do
2854 {
2855 ins = &m68k_opcodes[i];
2856 /* We *could* ignore insns that don't match our arch here
2857 but just leaving them out of the hash. */
2858 slak->m_operands = ins->args;
2859 slak->m_opnum = strlen (slak->m_operands) / 2;
2860 slak->m_arch = ins->arch;
2861 slak->m_opcode = ins->opcode;
2862 /* This is kludgey */
2863 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
2864 if (i + 1 != m68k_numopcodes
2865 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
2866 {
2867 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2868 i++;
2869 }
2870 else
2871 slak->m_next = 0;
2872 slak = slak->m_next;
2873 }
2874 while (slak);
2875
2876 retval = hash_insert (op_hash, ins->name, (char *) hack);
2877 if (retval)
2878 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
2879 }
2880
2881 for (i = 0; i < m68k_numaliases; i++)
2882 {
2883 const char *name = m68k_opcode_aliases[i].primary;
2884 const char *alias = m68k_opcode_aliases[i].alias;
2885 PTR val = hash_find (op_hash, name);
2886 if (!val)
2887 as_fatal ("Internal Error: Can't find %s in hash table", name);
2888 retval = hash_insert (op_hash, alias, val);
2889 if (retval)
2890 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
2891 }
2892
2893 for (i = 0; i < sizeof (mklower_table); i++)
2894 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
2895
2896 for (i = 0; i < sizeof (notend_table); i++)
2897 {
2898 notend_table[i] = 0;
2899 alt_notend_table[i] = 0;
2900 }
2901 notend_table[','] = 1;
2902 notend_table['{'] = 1;
2903 notend_table['}'] = 1;
2904 alt_notend_table['a'] = 1;
2905 alt_notend_table['A'] = 1;
2906 alt_notend_table['d'] = 1;
2907 alt_notend_table['D'] = 1;
2908 alt_notend_table['#'] = 1;
2909 alt_notend_table['&'] = 1;
2910 alt_notend_table['f'] = 1;
2911 alt_notend_table['F'] = 1;
2912 #ifdef REGISTER_PREFIX
2913 alt_notend_table[REGISTER_PREFIX] = 1;
2914 #endif
2915
2916 /* We need to put '(' in alt_notend_table to handle
2917 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
2918 */
2919 alt_notend_table['('] = 1;
2920
2921 /* We need to put '@' in alt_notend_table to handle
2922 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
2923 */
2924 alt_notend_table['@'] = 1;
2925
2926 #ifndef MIT_SYNTAX_ONLY
2927 /* Insert pseudo ops, these have to go into the opcode table since
2928 gas expects pseudo ops to start with a dot */
2929 {
2930 int n = 0;
2931 while (mote_pseudo_table[n].poc_name)
2932 {
2933 hack = (struct m68k_incant *)
2934 obstack_alloc (&robyn, sizeof (struct m68k_incant));
2935 hash_insert (op_hash,
2936 mote_pseudo_table[n].poc_name, (char *) hack);
2937 hack->m_operands = 0;
2938 hack->m_opnum = n;
2939 n++;
2940 }
2941 }
2942 #endif
2943
2944 init_regtable ();
2945 }
2946
2947 void
2948 m68k_init_after_args ()
2949 {
2950 if (cpu_of_arch (current_architecture) == 0)
2951 {
2952 int i;
2953 const char *default_cpu = TARGET_CPU;
2954
2955 if (*default_cpu == 'm')
2956 default_cpu++;
2957 for (i = 0; i < n_archs; i++)
2958 if (strcasecmp (default_cpu, archs[i].name) == 0)
2959 break;
2960 if (i == n_archs)
2961 {
2962 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
2963 current_architecture |= m68020;
2964 }
2965 else
2966 current_architecture |= archs[i].arch;
2967 }
2968 /* Permit m68881 specification with all cpus; those that can't work
2969 with a coprocessor could be doing emulation. */
2970 if (current_architecture & m68851)
2971 {
2972 if (current_architecture & m68040)
2973 {
2974 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
2975 }
2976 }
2977 /* What other incompatibilities could we check for? */
2978
2979 /* Toss in some default assumptions about coprocessors. */
2980 if (!no_68881
2981 && (cpu_of_arch (current_architecture)
2982 /* Can CPU32 have a 68881 coprocessor?? */
2983 & (m68020 | m68030 | cpu32)))
2984 {
2985 current_architecture |= m68881;
2986 }
2987 if (!no_68851
2988 && (cpu_of_arch (current_architecture) & m68020up) != 0
2989 && (cpu_of_arch (current_architecture) & m68040up) == 0)
2990 {
2991 current_architecture |= m68851;
2992 }
2993 if (no_68881 && (current_architecture & m68881))
2994 as_bad ("options for 68881 and no-68881 both given");
2995 if (no_68851 && (current_architecture & m68851))
2996 as_bad ("options for 68851 and no-68851 both given");
2997
2998 #ifdef OBJ_AOUT
2999 /* Work out the magic number. This isn't very general. */
3000 if (current_architecture & m68000)
3001 m68k_aout_machtype = 0;
3002 else if (current_architecture & m68010)
3003 m68k_aout_machtype = 1;
3004 else if (current_architecture & m68020)
3005 m68k_aout_machtype = 2;
3006 else
3007 m68k_aout_machtype = 2;
3008 #endif
3009
3010 /* Note which set of "movec" control registers is available. */
3011 switch (cpu_of_arch (current_architecture))
3012 {
3013 case m68000:
3014 control_regs = m68000_control_regs;
3015 break;
3016 case m68010:
3017 control_regs = m68010_control_regs;
3018 break;
3019 case m68020:
3020 case m68030:
3021 control_regs = m68020_control_regs;
3022 break;
3023 case m68040:
3024 control_regs = m68040_control_regs;
3025 break;
3026 case m68060:
3027 control_regs = m68060_control_regs;
3028 break;
3029 case cpu32:
3030 control_regs = cpu32_control_regs;
3031 break;
3032 default:
3033 abort ();
3034 }
3035
3036 if (cpu_of_arch (current_architecture) < m68020)
3037 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3038 }
3039
3040 /* Equal to MAX_PRECISION in atof-ieee.c */
3041 #define MAX_LITTLENUMS 6
3042
3043 /* Turn a string in input_line_pointer into a floating point constant
3044 of type type, and store the appropriate bytes in *litP. The number
3045 of LITTLENUMS emitted is stored in *sizeP . An error message is
3046 returned, or NULL on OK. */
3047
3048 char *
3049 md_atof (type, litP, sizeP)
3050 char type;
3051 char *litP;
3052 int *sizeP;
3053 {
3054 int prec;
3055 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3056 LITTLENUM_TYPE *wordP;
3057 char *t;
3058 char *atof_ieee ();
3059
3060 switch (type)
3061 {
3062 case 'f':
3063 case 'F':
3064 case 's':
3065 case 'S':
3066 prec = 2;
3067 break;
3068
3069 case 'd':
3070 case 'D':
3071 case 'r':
3072 case 'R':
3073 prec = 4;
3074 break;
3075
3076 case 'x':
3077 case 'X':
3078 prec = 6;
3079 break;
3080
3081 case 'p':
3082 case 'P':
3083 prec = 6;
3084 break;
3085
3086 default:
3087 *sizeP = 0;
3088 return "Bad call to MD_ATOF()";
3089 }
3090 t = atof_ieee (input_line_pointer, type, words);
3091 if (t)
3092 input_line_pointer = t;
3093
3094 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3095 for (wordP = words; prec--;)
3096 {
3097 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3098 litP += sizeof (LITTLENUM_TYPE);
3099 }
3100 return 0;
3101 }
3102
3103 void
3104 md_number_to_chars (buf, val, n)
3105 char *buf;
3106 valueT val;
3107 int n;
3108 {
3109 number_to_chars_bigendian (buf, val, n);
3110 }
3111
3112 static void
3113 md_apply_fix_2 (fixP, val)
3114 fixS *fixP;
3115 offsetT val;
3116 {
3117 addressT upper_limit;
3118 offsetT lower_limit;
3119
3120 /* This is unnecessary but it convinces the native rs6000 compiler
3121 to generate the code we want. */
3122 char *buf = fixP->fx_frag->fr_literal;
3123 buf += fixP->fx_where;
3124 /* end ibm compiler workaround */
3125
3126 if (val & 0x80000000)
3127 val |= ~(addressT)0x7fffffff;
3128 else
3129 val &= 0x7fffffff;
3130
3131 switch (fixP->fx_size)
3132 {
3133 /* The cast to offsetT below are necessary to make code correct for
3134 machines where ints are smaller than offsetT */
3135 case 1:
3136 *buf++ = val;
3137 upper_limit = 0x7f;
3138 lower_limit = - (offsetT) 0x80;
3139 break;
3140 case 2:
3141 *buf++ = (val >> 8);
3142 *buf++ = val;
3143 upper_limit = 0x7fff;
3144 lower_limit = - (offsetT) 0x8000;
3145 break;
3146 case 4:
3147 *buf++ = (val >> 24);
3148 *buf++ = (val >> 16);
3149 *buf++ = (val >> 8);
3150 *buf++ = val;
3151 upper_limit = 0x7fffffff;
3152 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3153 break;
3154 default:
3155 BAD_CASE (fixP->fx_size);
3156 }
3157
3158 /* For non-pc-relative values, it's conceivable we might get something
3159 like "0xff" for a byte field. So extend the upper part of the range
3160 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3161 so that we can do any range checking at all. */
3162 if (!fixP->fx_pcrel)
3163 upper_limit = upper_limit * 2 + 1;
3164
3165 if ((addressT) val > upper_limit
3166 && (val > 0 || val < lower_limit))
3167 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3168
3169 /* A one byte PC-relative reloc means a short branch. We can't use
3170 a short branch with a value of 0 or -1, because those indicate
3171 different opcodes (branches with longer offsets). */
3172 if (fixP->fx_pcrel
3173 && fixP->fx_size == 1
3174 && (fixP->fx_addsy == NULL
3175 || S_IS_DEFINED (fixP->fx_addsy))
3176 && (val == 0 || val == -1))
3177 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3178 }
3179
3180 #ifdef BFD_ASSEMBLER
3181 int
3182 md_apply_fix (fixP, valp)
3183 fixS *fixP;
3184 valueT *valp;
3185 {
3186 md_apply_fix_2 (fixP, (addressT) *valp);
3187 return 1;
3188 }
3189 #else
3190 void md_apply_fix (fixP, val)
3191 fixS *fixP;
3192 long val;
3193 {
3194 md_apply_fix_2 (fixP, (addressT) val);
3195 }
3196 #endif
3197
3198 /* *fragP has been relaxed to its final size, and now needs to have
3199 the bytes inside it modified to conform to the new size There is UGLY
3200 MAGIC here. ..
3201 */
3202 void
3203 md_convert_frag_1 (fragP)
3204 register fragS *fragP;
3205 {
3206 long disp;
3207 long ext = 0;
3208 fixS *fixP;
3209
3210 /* Address in object code of the displacement. */
3211 register int object_address = fragP->fr_fix + fragP->fr_address;
3212
3213 /* Address in gas core of the place to store the displacement. */
3214 /* This convinces the native rs6000 compiler to generate the code we
3215 want. */
3216 register char *buffer_address = fragP->fr_literal;
3217 buffer_address += fragP->fr_fix;
3218 /* end ibm compiler workaround */
3219
3220 /* The displacement of the address, from current location. */
3221 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3222 disp = (disp + fragP->fr_offset) - object_address;
3223
3224 #ifdef BFD_ASSEMBLER
3225 disp += fragP->fr_symbol->sy_frag->fr_address;
3226 #endif
3227
3228 switch (fragP->fr_subtype)
3229 {
3230 case TAB (BCC68000, BYTE):
3231 case TAB (ABRANCH, BYTE):
3232 know (issbyte (disp));
3233 if (disp == 0)
3234 as_bad ("short branch with zero offset: use :w");
3235 fragP->fr_opcode[1] = disp;
3236 ext = 0;
3237 break;
3238 case TAB (DBCC, SHORT):
3239 know (issword (disp));
3240 ext = 2;
3241 break;
3242 case TAB (BCC68000, SHORT):
3243 case TAB (ABRANCH, SHORT):
3244 know (issword (disp));
3245 fragP->fr_opcode[1] = 0x00;
3246 ext = 2;
3247 break;
3248 case TAB (ABRANCH, LONG):
3249 if (cpu_of_arch (current_architecture) < m68020)
3250 {
3251 if (fragP->fr_opcode[0] == 0x61)
3252 /* BSR */
3253 {
3254 fragP->fr_opcode[0] = 0x4E;
3255 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3256 subseg_change (text_section, 0); /* @@ */
3257
3258 fix_new (fragP,
3259 fragP->fr_fix,
3260 4,
3261 fragP->fr_symbol,
3262 fragP->fr_offset,
3263 0,
3264 NO_RELOC);
3265
3266 fragP->fr_fix += 4;
3267 ext = 0;
3268 }
3269 /* BRA */
3270 else if (fragP->fr_opcode[0] == 0x60)
3271 {
3272 fragP->fr_opcode[0] = 0x4E;
3273 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3274 subseg_change (text_section, 0); /* @@ */
3275 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3276 fragP->fr_offset, 0, NO_RELOC);
3277 fragP->fr_fix += 4;
3278 ext = 0;
3279 }
3280 else
3281 {
3282 as_bad ("Long branch offset not supported.");
3283 }
3284 }
3285 else
3286 {
3287 fragP->fr_opcode[1] = (char) 0xff;
3288 ext = 4;
3289 }
3290 break;
3291 case TAB (BCC68000, LONG):
3292 /* only Bcc 68000 instructions can come here */
3293 /* change bcc into b!cc/jmp absl long */
3294 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3295 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3296
3297 /* JF: these used to be fr_opcode[2,3], but they may be in a
3298 different frag, in which case refering to them is a no-no.
3299 Only fr_opcode[0,1] are guaranteed to work. */
3300 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3301 *buffer_address++ = (char) 0xf9;
3302 fragP->fr_fix += 2; /* account for jmp instruction */
3303 subseg_change (text_section, 0);
3304 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3305 fragP->fr_offset, 0, NO_RELOC);
3306 fragP->fr_fix += 4;
3307 ext = 0;
3308 break;
3309 case TAB (DBCC, LONG):
3310 /* only DBcc 68000 instructions can come here */
3311 /* change dbcc into dbcc/jmp absl long */
3312 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3313 *buffer_address++ = 0x00; /* branch offset = 4 */
3314 *buffer_address++ = 0x04;
3315 *buffer_address++ = 0x60; /* put in bra pc+6 */
3316 *buffer_address++ = 0x06;
3317 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3318 *buffer_address++ = (char) 0xf9;
3319
3320 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3321 subseg_change (text_section, 0);
3322 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3323 fragP->fr_offset, 0, NO_RELOC);
3324 fragP->fr_fix += 4;
3325 ext = 0;
3326 break;
3327 case TAB (FBRANCH, SHORT):
3328 know ((fragP->fr_opcode[1] & 0x40) == 0);
3329 ext = 2;
3330 break;
3331 case TAB (FBRANCH, LONG):
3332 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3333 ext = 4;
3334 break;
3335 case TAB (PCREL, SHORT):
3336 ext = 2;
3337 break;
3338 case TAB (PCREL, LONG):
3339 /* The thing to do here is force it to ABSOLUTE LONG, since
3340 PCREL is really trying to shorten an ABSOLUTE address anyway */
3341 /* JF FOO This code has not been tested */
3342 subseg_change (text_section, 0);
3343 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3344 0, NO_RELOC);
3345 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3346 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3347 (unsigned) fragP->fr_opcode[0],
3348 (unsigned long) fragP->fr_address);
3349 fragP->fr_opcode[1] &= ~0x3F;
3350 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3351 fragP->fr_fix += 4;
3352 ext = 0;
3353 break;
3354 case TAB (PCLEA, SHORT):
3355 subseg_change (text_section, 0);
3356 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3357 fragP->fr_offset, 1, NO_RELOC);
3358 fragP->fr_opcode[1] &= ~0x3F;
3359 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3360 ext = 2;
3361 break;
3362 case TAB (PCLEA, LONG):
3363 subseg_change (text_section, 0);
3364 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3365 fragP->fr_offset, 1, NO_RELOC);
3366 fixP->fx_pcrel_adjust = 2;
3367 /* Already set to mode 7.3; this indicates: PC indirect with
3368 suppressed index, 32-bit displacement. */
3369 *buffer_address++ = 0x01;
3370 *buffer_address++ = 0x70;
3371 fragP->fr_fix += 2;
3372 ext = 4;
3373 break;
3374
3375 case TAB (PCINDEX, BYTE):
3376 disp += 2;
3377 if (!issbyte (disp))
3378 {
3379 as_bad ("displacement doesn't fit in one byte");
3380 disp = 0;
3381 }
3382 assert (fragP->fr_fix >= 2);
3383 buffer_address[-2] &= ~1;
3384 buffer_address[-1] = disp;
3385 ext = 0;
3386 break;
3387 case TAB (PCINDEX, SHORT):
3388 subseg_change (text_section, 0);
3389 disp += 2;
3390 assert (issword (disp));
3391 assert (fragP->fr_fix >= 2);
3392 buffer_address[-2] |= 0x1;
3393 buffer_address[-1] = 0x20;
3394 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3395 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3396 NO_RELOC);
3397 fixP->fx_pcrel_adjust = 2;
3398 ext = 2;
3399 break;
3400 case TAB (PCINDEX, LONG):
3401 subseg_change (text_section, 0);
3402 disp += 2;
3403 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3404 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3405 NO_RELOC);
3406 fixP->fx_pcrel_adjust = 2;
3407 assert (fragP->fr_fix >= 2);
3408 buffer_address[-2] |= 0x1;
3409 buffer_address[-1] = 0x30;
3410 ext = 4;
3411 break;
3412 }
3413
3414 if (ext)
3415 {
3416 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3417 fragP->fr_fix += ext;
3418 }
3419 }
3420
3421 #ifndef BFD_ASSEMBLER
3422
3423 void
3424 md_convert_frag (headers, sec, fragP)
3425 object_headers *headers;
3426 segT sec;
3427 fragS *fragP;
3428 {
3429 md_convert_frag_1 (fragP);
3430 }
3431
3432 #else
3433
3434 void
3435 md_convert_frag (abfd, sec, fragP)
3436 bfd *abfd;
3437 segT sec;
3438 fragS *fragP;
3439 {
3440 md_convert_frag_1 (fragP);
3441 }
3442 #endif
3443
3444 /* Force truly undefined symbols to their maximum size, and generally set up
3445 the frag list to be relaxed
3446 */
3447 int
3448 md_estimate_size_before_relax (fragP, segment)
3449 register fragS *fragP;
3450 segT segment;
3451 {
3452 int old_fix;
3453 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3454
3455 old_fix = fragP->fr_fix;
3456
3457 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3458 switch (fragP->fr_subtype)
3459 {
3460
3461 case TAB (ABRANCH, SZ_UNDEF):
3462 {
3463 if ((fragP->fr_symbol != NULL) /* Not absolute */
3464 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3465 {
3466 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3467 break;
3468 }
3469 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3470 {
3471 /* On 68000, or for absolute value, switch to abs long */
3472 /* FIXME, we should check abs val, pick short or long */
3473 if (fragP->fr_opcode[0] == 0x61)
3474 {
3475 fragP->fr_opcode[0] = 0x4E;
3476 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3477 subseg_change (text_section, 0);
3478 fix_new (fragP, fragP->fr_fix, 4,
3479 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3480 fragP->fr_fix += 4;
3481 frag_wane (fragP);
3482 }
3483 else if (fragP->fr_opcode[0] == 0x60)
3484 {
3485 fragP->fr_opcode[0] = 0x4E;
3486 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3487 subseg_change (text_section, 0);
3488 fix_new (fragP, fragP->fr_fix, 4,
3489 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3490 fragP->fr_fix += 4;
3491 frag_wane (fragP);
3492 }
3493 else
3494 {
3495 as_warn ("Long branch offset to extern symbol not supported.");
3496 }
3497 }
3498 else
3499 { /* Symbol is still undefined. Make it simple */
3500 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3501 fragP->fr_offset, 1, NO_RELOC);
3502 fragP->fr_fix += 4;
3503 fragP->fr_opcode[1] = (char) 0xff;
3504 frag_wane (fragP);
3505 break;
3506 }
3507
3508 break;
3509 } /* case TAB(ABRANCH,SZ_UNDEF) */
3510
3511 case TAB (FBRANCH, SZ_UNDEF):
3512 {
3513 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3514 {
3515 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3516 fragP->fr_var += 2;
3517 }
3518 else
3519 {
3520 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3521 fragP->fr_offset, 1, NO_RELOC);
3522 fragP->fr_fix += 4;
3523 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3524 frag_wane (fragP);
3525 }
3526 break;
3527 } /* TAB(FBRANCH,SZ_UNDEF) */
3528
3529 case TAB (PCREL, SZ_UNDEF):
3530 {
3531 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3532 || flag_short_refs
3533 || cpu_of_arch (current_architecture) < m68020)
3534 {
3535 fragP->fr_subtype = TAB (PCREL, SHORT);
3536 fragP->fr_var += 2;
3537 }
3538 else
3539 {
3540 fragP->fr_subtype = TAB (PCREL, LONG);
3541 fragP->fr_var += 4;
3542 }
3543 break;
3544 } /* TAB(PCREL,SZ_UNDEF) */
3545
3546 case TAB (BCC68000, SZ_UNDEF):
3547 {
3548 if ((fragP->fr_symbol != NULL)
3549 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3550 {
3551 fragP->fr_subtype = TAB (BCC68000, BYTE);
3552 break;
3553 }
3554 /* only Bcc 68000 instructions can come here */
3555 /* change bcc into b!cc/jmp absl long */
3556 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3557 if (flag_short_refs)
3558 {
3559 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3560 /* JF: these were fr_opcode[2,3] */
3561 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3562 buffer_address[1] = (char) 0xf8;
3563 fragP->fr_fix += 2; /* account for jmp instruction */
3564 subseg_change (text_section, 0);
3565 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3566 fragP->fr_offset, 0, NO_RELOC);
3567 fragP->fr_fix += 2;
3568 }
3569 else
3570 {
3571 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3572 /* JF: these were fr_opcode[2,3] */
3573 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3574 buffer_address[1] = (char) 0xf9;
3575 fragP->fr_fix += 2; /* account for jmp instruction */
3576 subseg_change (text_section, 0);
3577 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3578 fragP->fr_offset, 0, NO_RELOC);
3579 fragP->fr_fix += 4;
3580 }
3581 frag_wane (fragP);
3582 break;
3583 } /* case TAB(BCC68000,SZ_UNDEF) */
3584
3585 case TAB (DBCC, SZ_UNDEF):
3586 {
3587 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3588 {
3589 fragP->fr_subtype = TAB (DBCC, SHORT);
3590 fragP->fr_var += 2;
3591 break;
3592 }
3593 /* only DBcc 68000 instructions can come here */
3594 /* change dbcc into dbcc/jmp absl long */
3595 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3596 buffer_address[0] = 0x00; /* branch offset = 4 */
3597 buffer_address[1] = 0x04;
3598 buffer_address[2] = 0x60; /* put in bra pc + ... */
3599
3600 if (flag_short_refs)
3601 {
3602 /* JF: these were fr_opcode[5-7] */
3603 buffer_address[3] = 0x04; /* plus 4 */
3604 buffer_address[4] = 0x4e; /* Put in Jump Word */
3605 buffer_address[5] = (char) 0xf8;
3606 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3607 subseg_change (text_section, 0);
3608 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3609 fragP->fr_offset, 0, NO_RELOC);
3610 fragP->fr_fix += 2;
3611 }
3612 else
3613 {
3614 /* JF: these were fr_opcode[5-7] */
3615 buffer_address[3] = 0x06; /* Plus 6 */
3616 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3617 buffer_address[5] = (char) 0xf9;
3618 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3619 subseg_change (text_section, 0);
3620 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3621 fragP->fr_offset, 0, NO_RELOC);
3622 fragP->fr_fix += 4;
3623 }
3624
3625 frag_wane (fragP);
3626 break;
3627 } /* case TAB(DBCC,SZ_UNDEF) */
3628
3629 case TAB (PCLEA, SZ_UNDEF):
3630 {
3631 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3632 || flag_short_refs
3633 || cpu_of_arch (current_architecture) < m68020)
3634 {
3635 fragP->fr_subtype = TAB (PCLEA, SHORT);
3636 fragP->fr_var += 2;
3637 }
3638 else
3639 {
3640 fragP->fr_subtype = TAB (PCLEA, LONG);
3641 fragP->fr_var += 6;
3642 }
3643 break;
3644 } /* TAB(PCLEA,SZ_UNDEF) */
3645
3646 case TAB (PCINDEX, SZ_UNDEF):
3647 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3648 || cpu_of_arch (current_architecture) < m68020)
3649 {
3650 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3651 }
3652 else
3653 {
3654 fragP->fr_subtype = TAB (PCINDEX, LONG);
3655 fragP->fr_var += 4;
3656 }
3657 break;
3658
3659 default:
3660 break;
3661 }
3662
3663 /* now that SZ_UNDEF are taken care of, check others */
3664 switch (fragP->fr_subtype)
3665 {
3666 case TAB (BCC68000, BYTE):
3667 case TAB (ABRANCH, BYTE):
3668 /* We can't do a short jump to the next instruction,
3669 so we force word mode. */
3670 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3671 fragP->fr_symbol->sy_frag == fragP->fr_next)
3672 {
3673 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3674 fragP->fr_var += 2;
3675 }
3676 break;
3677 default:
3678 break;
3679 }
3680 return fragP->fr_var + fragP->fr_fix - old_fix;
3681 }
3682
3683 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3684 /* the bit-field entries in the relocation_info struct plays hell
3685 with the byte-order problems of cross-assembly. So as a hack,
3686 I added this mach. dependent ri twiddler. Ugly, but it gets
3687 you there. -KWK */
3688 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3689 are symbolnum, most sig. byte first. Last byte is broken up with
3690 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3691 nibble as nuthin. (on Sun 3 at least) */
3692 /* Translate the internal relocation information into target-specific
3693 format. */
3694 #ifdef comment
3695 void
3696 md_ri_to_chars (the_bytes, ri)
3697 char *the_bytes;
3698 struct reloc_info_generic *ri;
3699 {
3700 /* this is easy */
3701 md_number_to_chars (the_bytes, ri->r_address, 4);
3702 /* now the fun stuff */
3703 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3704 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3705 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3706 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3707 ((ri->r_extern << 4) & 0x10));
3708 }
3709
3710 #endif /* comment */
3711
3712 #ifndef BFD_ASSEMBLER
3713 void
3714 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3715 char *where;
3716 fixS *fixP;
3717 relax_addressT segment_address_in_file;
3718 {
3719 /*
3720 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3721 * Out: GNU LD relocation length code: 0, 1, or 2.
3722 */
3723
3724 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3725 long r_symbolnum;
3726
3727 know (fixP->fx_addsy != NULL);
3728
3729 md_number_to_chars (where,
3730 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3731 4);
3732
3733 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3734 ? S_GET_TYPE (fixP->fx_addsy)
3735 : fixP->fx_addsy->sy_number);
3736
3737 where[4] = (r_symbolnum >> 16) & 0x0ff;
3738 where[5] = (r_symbolnum >> 8) & 0x0ff;
3739 where[6] = r_symbolnum & 0x0ff;
3740 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3741 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3742 }
3743 #endif
3744
3745 #endif /* OBJ_AOUT or OBJ_BOUT */
3746
3747 #ifndef WORKING_DOT_WORD
3748 CONST int md_short_jump_size = 4;
3749 CONST int md_long_jump_size = 6;
3750
3751 void
3752 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3753 char *ptr;
3754 addressT from_addr, to_addr;
3755 fragS *frag;
3756 symbolS *to_symbol;
3757 {
3758 valueT offset;
3759
3760 offset = to_addr - (from_addr + 2);
3761
3762 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3763 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3764 }
3765
3766 void
3767 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3768 char *ptr;
3769 addressT from_addr, to_addr;
3770 fragS *frag;
3771 symbolS *to_symbol;
3772 {
3773 valueT offset;
3774
3775 if (cpu_of_arch (current_architecture) < m68020)
3776 {
3777 offset = to_addr - S_GET_VALUE (to_symbol);
3778 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3779 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3780 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3781 0, NO_RELOC);
3782 }
3783 else
3784 {
3785 offset = to_addr - (from_addr + 2);
3786 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3787 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3788 }
3789 }
3790
3791 #endif
3792
3793 /* Different values of OK tell what its OK to return. Things that
3794 aren't OK are an error (what a shock, no?)
3795
3796 0: Everything is OK
3797 10: Absolute 1:8 only
3798 20: Absolute 0:7 only
3799 30: absolute 0:15 only
3800 40: Absolute 0:31 only
3801 50: absolute 0:127 only
3802 55: absolute -64:63 only
3803 60: absolute -128:127 only
3804 70: absolute 0:4095 only
3805 80: No bignums
3806
3807 */
3808
3809 static int
3810 get_num (exp, ok)
3811 struct m68k_exp *exp;
3812 int ok;
3813 {
3814 if (exp->exp.X_op == O_absent)
3815 {
3816 /* Do the same thing the VAX asm does */
3817 op (exp) = O_constant;
3818 adds (exp) = 0;
3819 subs (exp) = 0;
3820 offs (exp) = 0;
3821 if (ok == 10)
3822 {
3823 as_warn ("expression out of range: defaulting to 1");
3824 offs (exp) = 1;
3825 }
3826 }
3827 else if (exp->exp.X_op == O_constant)
3828 {
3829 switch (ok)
3830 {
3831 case 10:
3832 if (offs (exp) < 1 || offs (exp) > 8)
3833 {
3834 as_warn ("expression out of range: defaulting to 1");
3835 offs (exp) = 1;
3836 }
3837 break;
3838 case 20:
3839 if (offs (exp) < 0 || offs (exp) > 7)
3840 goto outrange;
3841 break;
3842 case 30:
3843 if (offs (exp) < 0 || offs (exp) > 15)
3844 goto outrange;
3845 break;
3846 case 40:
3847 if (offs (exp) < 0 || offs (exp) > 32)
3848 goto outrange;
3849 break;
3850 case 50:
3851 if (offs (exp) < 0 || offs (exp) > 127)
3852 goto outrange;
3853 break;
3854 case 55:
3855 if (offs (exp) < -64 || offs (exp) > 63)
3856 goto outrange;
3857 break;
3858 case 60:
3859 if (offs (exp) < -128 || offs (exp) > 127)
3860 goto outrange;
3861 break;
3862 case 70:
3863 if (offs (exp) < 0 || offs (exp) > 4095)
3864 {
3865 outrange:
3866 as_warn ("expression out of range: defaulting to 0");
3867 offs (exp) = 0;
3868 }
3869 break;
3870 default:
3871 break;
3872 }
3873 }
3874 else if (exp->exp.X_op == O_big)
3875 {
3876 if (offs (exp) <= 0 /* flonum */
3877 && (ok == 80 /* no bignums */
3878 || (ok > 10 /* small-int ranges including 0 ok */
3879 /* If we have a flonum zero, a zero integer should
3880 do as well (e.g., in moveq). */
3881 && generic_floating_point_number.exponent == 0
3882 && generic_floating_point_number.low[0] == 0)))
3883 {
3884 /* HACK! Turn it into a long */
3885 LITTLENUM_TYPE words[6];
3886
3887 gen_to_words (words, 2, 8L); /* These numbers are magic! */
3888 op (exp) = O_constant;
3889 adds (exp) = 0;
3890 subs (exp) = 0;
3891 offs (exp) = words[1] | (words[0] << 16);
3892 }
3893 else if (ok != 0)
3894 {
3895 op (exp) = O_constant;
3896 adds (exp) = 0;
3897 subs (exp) = 0;
3898 offs (exp) = (ok == 10) ? 1 : 0;
3899 as_warn ("Can't deal with expression; defaulting to %ld",
3900 offs (exp));
3901 }
3902 }
3903 else
3904 {
3905 if (ok >= 10 && ok <= 70)
3906 {
3907 op (exp) = O_constant;
3908 adds (exp) = 0;
3909 subs (exp) = 0;
3910 offs (exp) = (ok == 10) ? 1 : 0;
3911 as_warn ("Can't deal with expression; defaulting to %ld",
3912 offs (exp));
3913 }
3914 }
3915
3916 if (exp->size != SIZE_UNSPEC)
3917 {
3918 switch (exp->size)
3919 {
3920 case SIZE_UNSPEC:
3921 case SIZE_LONG:
3922 break;
3923 case SIZE_BYTE:
3924 if (!isbyte (offs (exp)))
3925 as_warn ("expression doesn't fit in BYTE");
3926 break;
3927 case SIZE_WORD:
3928 if (!isword (offs (exp)))
3929 as_warn ("expression doesn't fit in WORD");
3930 break;
3931 }
3932 }
3933
3934 return offs (exp);
3935 }
3936
3937 /* These are the back-ends for the various machine dependent pseudo-ops. */
3938 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
3939
3940 static void
3941 s_data1 (ignore)
3942 int ignore;
3943 {
3944 subseg_set (data_section, 1);
3945 demand_empty_rest_of_line ();
3946 }
3947
3948 static void
3949 s_data2 (ignore)
3950 int ignore;
3951 {
3952 subseg_set (data_section, 2);
3953 demand_empty_rest_of_line ();
3954 }
3955
3956 static void
3957 s_bss (ignore)
3958 int ignore;
3959 {
3960 /* We don't support putting frags in the BSS segment, we fake it
3961 by marking in_bss, then looking at s_skip for clues. */
3962
3963 subseg_set (bss_section, 0);
3964 demand_empty_rest_of_line ();
3965 }
3966
3967 static void
3968 s_even (ignore)
3969 int ignore;
3970 {
3971 register int temp;
3972 register long temp_fill;
3973
3974 temp = 1; /* JF should be 2? */
3975 temp_fill = get_absolute_expression ();
3976 if (!need_pass_2) /* Never make frag if expect extra pass. */
3977 frag_align (temp, (int) temp_fill);
3978 demand_empty_rest_of_line ();
3979 }
3980
3981 static void
3982 s_proc (ignore)
3983 int ignore;
3984 {
3985 demand_empty_rest_of_line ();
3986 }
3987 \f
3988 /* Pseudo-ops handled for MRI compatibility. */
3989
3990 /* Handle an MRI style chip specification. */
3991
3992 static void
3993 mri_chip ()
3994 {
3995 char *s;
3996 char c;
3997 int i;
3998
3999 s = input_line_pointer;
4000 c = get_symbol_end ();
4001 for (i = 0; i < n_archs; i++)
4002 if (strcasecmp (s, archs[i].name) == 0)
4003 break;
4004 if (i >= n_archs)
4005 {
4006 as_bad ("%s: unrecognized processor name", s);
4007 *input_line_pointer = c;
4008 ignore_rest_of_line ();
4009 return;
4010 }
4011 *input_line_pointer = c;
4012
4013 if (*input_line_pointer == '/')
4014 current_architecture = 0;
4015 else
4016 current_architecture &= m68881 | m68851;
4017 current_architecture |= archs[i].arch;
4018
4019 while (*input_line_pointer == '/')
4020 {
4021 ++input_line_pointer;
4022 s = input_line_pointer;
4023 c = get_symbol_end ();
4024 if (strcmp (s, "68881") == 0)
4025 current_architecture |= m68881;
4026 else if (strcmp (s, "68851") == 0)
4027 current_architecture |= m68851;
4028 *input_line_pointer = c;
4029 }
4030 }
4031
4032 /* The MRI CHIP pseudo-op. */
4033
4034 static void
4035 s_chip (ignore)
4036 int ignore;
4037 {
4038 mri_chip ();
4039 demand_empty_rest_of_line ();
4040 }
4041
4042 /* The MRI FOPT pseudo-op. */
4043
4044 static void
4045 s_fopt (ignore)
4046 int ignore;
4047 {
4048 SKIP_WHITESPACE ();
4049
4050 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4051 {
4052 int temp;
4053
4054 input_line_pointer += 3;
4055 temp = get_absolute_expression ();
4056 if (temp < 0 || temp > 7)
4057 as_bad ("bad coprocessor id");
4058 else
4059 m68k_float_copnum = COP0 + temp;
4060 }
4061 else
4062 {
4063 as_bad ("unrecognized fopt option");
4064 ignore_rest_of_line ();
4065 return;
4066 }
4067
4068 demand_empty_rest_of_line ();
4069 }
4070 \f
4071 /*
4072 * md_parse_option
4073 * Invocation line includes a switch not recognized by the base assembler.
4074 * See if it's a processor-specific option. These are:
4075 *
4076 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4077 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4078 * Select the architecture. Instructions or features not
4079 * supported by the selected architecture cause fatal
4080 * errors. More than one may be specified. The default is
4081 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4082 * for -m68000, and -m68882 is a synonym for -m68881.
4083 * -[A]m[c]no-68851, -[A]m[c]no-68881
4084 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4085 * so don't use or document it, but that's the way the parsing
4086 * works).
4087 *
4088 * -pic Indicates PIC.
4089 * -k Indicates PIC. (Sun 3 only.)
4090 *
4091 */
4092
4093 #ifdef OBJ_ELF
4094 CONST char *md_shortopts = "lSA:m:kQ:V";
4095 #else
4096 CONST char *md_shortopts = "lSA:m:k";
4097 #endif
4098
4099 struct option md_longopts[] = {
4100 #define OPTION_PIC (OPTION_MD_BASE)
4101 {"pic", no_argument, NULL, OPTION_PIC},
4102 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4103 {"register-prefix-optional", no_argument, NULL,
4104 OPTION_REGISTER_PREFIX_OPTIONAL},
4105 {NULL, no_argument, NULL, 0}
4106 };
4107 size_t md_longopts_size = sizeof(md_longopts);
4108
4109 int
4110 md_parse_option (c, arg)
4111 int c;
4112 char *arg;
4113 {
4114 switch (c)
4115 {
4116 case 'l': /* -l means keep external to 2 bit offset
4117 rather than 16 bit one */
4118 flag_short_refs = 1;
4119 break;
4120
4121 case 'S': /* -S means that jbsr's always turn into
4122 jsr's. */
4123 flag_long_jumps = 1;
4124 break;
4125
4126 case 'A':
4127 if (*arg == 'm')
4128 arg++;
4129 /* intentional fall-through */
4130 case 'm':
4131
4132 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
4133 {
4134 int i;
4135 unsigned long arch;
4136 const char *oarg = arg;
4137
4138 arg += 3;
4139 if (*arg == 'm')
4140 {
4141 arg++;
4142 if (arg[0] == 'c' && arg[1] == '6')
4143 arg++;
4144 }
4145 for (i = 0; i < n_archs; i++)
4146 if (!strcmp (arg, archs[i].name))
4147 break;
4148 if (i == n_archs)
4149 {
4150 unknown:
4151 as_bad ("unrecognized option `%s'", oarg);
4152 return 0;
4153 }
4154 arch = archs[i].arch;
4155 if (arch == m68881)
4156 no_68881 = 1;
4157 else if (arch == m68851)
4158 no_68851 = 1;
4159 else
4160 goto unknown;
4161 }
4162 else
4163 {
4164 int i;
4165
4166 if (arg[0] == 'c' && arg[1] == '6')
4167 arg++;
4168
4169 for (i = 0; i < n_archs; i++)
4170 if (!strcmp (arg, archs[i].name))
4171 {
4172 unsigned long arch = archs[i].arch;
4173 if (cpu_of_arch (arch))
4174 /* It's a cpu spec. */
4175 {
4176 current_architecture &= ~m68000up;
4177 current_architecture |= arch;
4178 }
4179 else if (arch == m68881)
4180 {
4181 current_architecture |= m68881;
4182 no_68881 = 0;
4183 }
4184 else if (arch == m68851)
4185 {
4186 current_architecture |= m68851;
4187 no_68851 = 0;
4188 }
4189 else
4190 /* ??? */
4191 abort ();
4192 break;
4193 }
4194 if (i == n_archs)
4195 {
4196 as_bad ("unrecognized architecture specification `%s'", arg);
4197 return 0;
4198 }
4199 }
4200 break;
4201
4202 case OPTION_PIC:
4203 case 'k':
4204 flag_want_pic = 1;
4205 break; /* -pic, Position Independent Code */
4206
4207 case OPTION_REGISTER_PREFIX_OPTIONAL:
4208 flag_reg_prefix_optional = 1;
4209 break;
4210
4211 case 'Q':
4212 case 'V':
4213 break;
4214
4215 default:
4216 return 0;
4217 }
4218
4219 return 1;
4220 }
4221
4222 void
4223 md_show_usage (stream)
4224 FILE *stream;
4225 {
4226 fprintf(stream, "\
4227 680X0 options:\n\
4228 -l use 1 word for refs to undefined symbols [default 2]\n\
4229 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
4230 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
4231 | -mcpu32\n\
4232 specify variant of 680X0 architecture [default 68020]\n\
4233 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
4234 target has/lacks floating-point coprocessor\n\
4235 [default yes for 68020, 68030, and cpu32]\n\
4236 -m68851 | -mno-68851\n\
4237 target has/lacks memory-management unit coprocessor\n\
4238 [default yes for 68020 and up]\n\
4239 -pic, -k generate position independent code\n\
4240 -S turn jbsr into jsr\n\
4241 --register-prefix-optional\n\
4242 recognize register names without prefix character\n");
4243 }
4244 \f
4245 #ifdef TEST2
4246
4247 /* TEST2: Test md_assemble() */
4248 /* Warning, this routine probably doesn't work anymore */
4249
4250 main ()
4251 {
4252 struct m68k_it the_ins;
4253 char buf[120];
4254 char *cp;
4255 int n;
4256
4257 m68k_ip_begin ();
4258 for (;;)
4259 {
4260 if (!gets (buf) || !*buf)
4261 break;
4262 if (buf[0] == '|' || buf[1] == '.')
4263 continue;
4264 for (cp = buf; *cp; cp++)
4265 if (*cp == '\t')
4266 *cp = ' ';
4267 if (is_label (buf))
4268 continue;
4269 memset (&the_ins, '\0', sizeof (the_ins));
4270 m68k_ip (&the_ins, buf);
4271 if (the_ins.error)
4272 {
4273 printf ("Error %s in %s\n", the_ins.error, buf);
4274 }
4275 else
4276 {
4277 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4278 for (n = 0; n < the_ins.numo; n++)
4279 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4280 printf (" ");
4281 print_the_insn (&the_ins.opcode[0], stdout);
4282 (void) putchar ('\n');
4283 }
4284 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4285 {
4286 if (the_ins.operands[n].error)
4287 {
4288 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4289 continue;
4290 }
4291 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4292 if (the_ins.operands[n].b_const)
4293 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4294 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4295 if (the_ins.operands[n].b_iadd)
4296 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4297 (void) putchar ('\n');
4298 }
4299 }
4300 m68k_ip_end ();
4301 return 0;
4302 }
4303
4304 is_label (str)
4305 char *str;
4306 {
4307 while (*str == ' ')
4308 str++;
4309 while (*str && *str != ' ')
4310 str++;
4311 if (str[-1] == ':' || str[1] == '=')
4312 return 1;
4313 return 0;
4314 }
4315
4316 #endif
4317
4318 /* Possible states for relaxation:
4319
4320 0 0 branch offset byte (bra, etc)
4321 0 1 word
4322 0 2 long
4323
4324 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4325 1 1 word
4326 1 2 long
4327
4328 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4329 2 1 word-long
4330 2 2 long-word
4331 2 3 long-long
4332
4333 */
4334
4335 /* We have no need to default values of symbols. */
4336
4337 /* ARGSUSED */
4338 symbolS *
4339 md_undefined_symbol (name)
4340 char *name;
4341 {
4342 return 0;
4343 }
4344
4345 /* Round up a section size to the appropriate boundary. */
4346 valueT
4347 md_section_align (segment, size)
4348 segT segment;
4349 valueT size;
4350 {
4351 return size; /* Byte alignment is fine */
4352 }
4353
4354 /* Exactly what point is a PC-relative offset relative TO?
4355 On the 68k, it is relative to the address of the first extension
4356 word. The difference between the addresses of the offset and the
4357 first extension word is stored in fx_pcrel_adjust. */
4358 long
4359 md_pcrel_from (fixP)
4360 fixS *fixP;
4361 {
4362 return (fixP->fx_where + fixP->fx_frag->fr_address - fixP->fx_pcrel_adjust);
4363 }
4364
4365 #ifndef BFD_ASSEMBLER
4366 /*ARGSUSED*/
4367 void
4368 tc_coff_symbol_emit_hook (ignore)
4369 symbolS *ignore;
4370 {
4371 }
4372
4373 int
4374 tc_coff_sizemachdep (frag)
4375 fragS *frag;
4376 {
4377 switch (frag->fr_subtype & 0x3)
4378 {
4379 case BYTE:
4380 return 1;
4381 case SHORT:
4382 return 2;
4383 case LONG:
4384 return 4;
4385 default:
4386 abort ();
4387 return 0;
4388 }
4389 }
4390 #endif
4391
4392 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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