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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <ctype.h>
24 #include "as.h"
25 #include "obstack.h"
26 #include "subsegs.h"
27
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
30
31 #if defined (OBJ_ELF)
32 #include "elf/m68k.h"
33 #endif
34
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars = "|#";
41 #else
42 const char *m68k_comment_chars = "|";
43 #endif
44
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars[] = "#*";
53
54 const char line_separator_chars[] = ";";
55
56 /* Chars that can be used to separate mant from exp in floating point nums */
57 CONST char EXP_CHARS[] = "eE";
58
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
62 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
68 const int md_reloc_size = 8; /* Size of relocation record */
69
70 /* Are we trying to generate PIC code? If so, absolute references
71 ought to be made into linkage table references or pc-relative
72 references. Not implemented. For ELF there are other means
73 to denote pic relocations. */
74 int flag_want_pic;
75
76 static int flag_short_refs; /* -l option */
77 static int flag_long_jumps; /* -S option */
78 static int flag_keep_pcrel; /* --pcrel option. */
79
80 #ifdef REGISTER_PREFIX_OPTIONAL
81 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
82 #else
83 int flag_reg_prefix_optional;
84 #endif
85
86 /* Whether --register-prefix-optional was used on the command line. */
87 static int reg_prefix_optional_seen;
88
89 /* The floating point coprocessor to use by default. */
90 static enum m68k_register m68k_float_copnum = COP1;
91
92 /* If this is non-zero, then references to number(%pc) will be taken
93 to refer to number, rather than to %pc + number. */
94 static int m68k_abspcadd;
95
96 /* If this is non-zero, then the quick forms of the move, add, and sub
97 instructions are used when possible. */
98 static int m68k_quick = 1;
99
100 /* If this is non-zero, then if the size is not specified for a base
101 or outer displacement, the assembler assumes that the size should
102 be 32 bits. */
103 static int m68k_rel32 = 1;
104
105 /* This is non-zero if m68k_rel32 was set from the command line. */
106 static int m68k_rel32_from_cmdline;
107
108 /* The default width to use for an index register when using a base
109 displacement. */
110 static enum m68k_size m68k_index_width_default = SIZE_LONG;
111
112 /* We want to warn if any text labels are misaligned. In order to get
113 the right line number, we need to record the line number for each
114 label. */
115
116 struct label_line
117 {
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123 };
124
125 /* The list of labels. */
126
127 static struct label_line *labels;
128
129 /* The current label. */
130
131 static struct label_line *current_label;
132
133 /* Its an arbitrary name: This means I don't approve of it */
134 /* See flames below */
135 static struct obstack robyn;
136
137 struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
149
150 static const enum m68k_register m68000_control_regs[] = { 0 };
151 static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154 };
155 static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158 };
159 static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163 };
164 static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168 };
169 static const enum m68k_register mcf_control_regs[] = {
170 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
171 RAMBAR0, RAMBAR1, MBAR,
172 0
173 };
174 #define cpu32_control_regs m68010_control_regs
175
176 static const enum m68k_register *control_regs;
177
178 /* internal form of a 68020 instruction */
179 struct m68k_it
180 {
181 const char *error;
182 const char *args; /* list of opcode info */
183 int numargs;
184
185 int numo; /* Number of shorts in opcode */
186 short opcode[11];
187
188 struct m68k_op operands[6];
189
190 int nexp; /* number of exprs in use */
191 struct m68k_exp exprs[4];
192
193 int nfrag; /* Number of frags we have to produce */
194 struct
195 {
196 int fragoff; /* Where in the current opcode the frag ends */
197 symbolS *fadd;
198 offsetT foff;
199 int fragty;
200 }
201 fragb[4];
202
203 int nrel; /* Num of reloc strucs in use */
204 struct
205 {
206 int n;
207 expressionS exp;
208 char wid;
209 char pcrel;
210 /* In a pc relative address the difference between the address
211 of the offset and the address that the offset is relative
212 to. This depends on the addressing mode. Basically this
213 is the value to put in the offset field to address the
214 first byte of the offset, without regarding the special
215 significance of some values (in the branch instruction, for
216 example). */
217 int pcrel_fix;
218 #ifdef OBJ_ELF
219 /* Whether this expression needs special pic relocation, and if
220 so, which. */
221 enum pic_relocation pic_reloc;
222 #endif
223 }
224 reloc[5]; /* Five is enough??? */
225 };
226
227 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
228 #define float_of_arch(x) ((x) & mfloat)
229 #define mmu_of_arch(x) ((x) & mmmu)
230 #define arch_coldfire_p(x) (((x) & mcf) != 0)
231
232 /* Macros for determining if cpu supports a specific addressing mode */
233 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
234
235 static struct m68k_it the_ins; /* the instruction being assembled */
236
237 #define op(ex) ((ex)->exp.X_op)
238 #define adds(ex) ((ex)->exp.X_add_symbol)
239 #define subs(ex) ((ex)->exp.X_op_symbol)
240 #define offs(ex) ((ex)->exp.X_add_number)
241
242 /* Macros for adding things to the m68k_it struct */
243
244 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
245
246 /* Static functions. */
247
248 static void insop PARAMS ((int, const struct m68k_incant *));
249 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
250 static void add_frag PARAMS ((symbolS *, offsetT, int));
251
252 /* Like addword, but goes BEFORE general operands */
253 static void
254 insop (w, opcode)
255 int w;
256 const struct m68k_incant *opcode;
257 {
258 int z;
259 for(z=the_ins.numo;z>opcode->m_codenum;--z)
260 the_ins.opcode[z]=the_ins.opcode[z-1];
261 for(z=0;z<the_ins.nrel;z++)
262 the_ins.reloc[z].n+=2;
263 for (z = 0; z < the_ins.nfrag; z++)
264 the_ins.fragb[z].fragoff++;
265 the_ins.opcode[opcode->m_codenum]=w;
266 the_ins.numo++;
267 }
268
269 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
270 Blecch. */
271 static void
272 add_fix (width, exp, pc_rel, pc_fix)
273 int width;
274 struct m68k_exp *exp;
275 int pc_rel;
276 int pc_fix;
277 {
278 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
279 ? (the_ins.numo*2-1)
280 : (((width)=='b')
281 ? (the_ins.numo*2+1)
282 : (the_ins.numo*2)));
283 the_ins.reloc[the_ins.nrel].exp = exp->exp;
284 the_ins.reloc[the_ins.nrel].wid = width;
285 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
286 #ifdef OBJ_ELF
287 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
288 #endif
289 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
290 }
291
292 /* Cause an extra frag to be generated here, inserting up to 10 bytes
293 (that value is chosen in the frag_var call in md_assemble). TYPE
294 is the subtype of the frag to be generated; its primary type is
295 rs_machine_dependent.
296
297 The TYPE parameter is also used by md_convert_frag_1 and
298 md_estimate_size_before_relax. The appropriate type of fixup will
299 be emitted by md_convert_frag_1.
300
301 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
302 static void
303 add_frag (add, off, type)
304 symbolS *add;
305 offsetT off;
306 int type;
307 {
308 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
309 the_ins.fragb[the_ins.nfrag].fadd=add;
310 the_ins.fragb[the_ins.nfrag].foff=off;
311 the_ins.fragb[the_ins.nfrag++].fragty=type;
312 }
313
314 #define isvar(ex) \
315 (op (ex) != O_constant && op (ex) != O_big)
316
317 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
318 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
319 static void m68k_ip PARAMS ((char *));
320 static void insert_reg PARAMS ((const char *, int));
321 static void select_control_regs PARAMS ((void));
322 static void init_regtable PARAMS ((void));
323 static int reverse_16_bits PARAMS ((int in));
324 static int reverse_8_bits PARAMS ((int in));
325 static void install_gen_operand PARAMS ((int mode, int val));
326 static void install_operand PARAMS ((int mode, int val));
327 static void s_bss PARAMS ((int));
328 static void s_data1 PARAMS ((int));
329 static void s_data2 PARAMS ((int));
330 static void s_even PARAMS ((int));
331 static void s_proc PARAMS ((int));
332 static void mri_chip PARAMS ((void));
333 static void s_chip PARAMS ((int));
334 static void s_fopt PARAMS ((int));
335 static void s_opt PARAMS ((int));
336 static void s_reg PARAMS ((int));
337 static void s_restore PARAMS ((int));
338 static void s_save PARAMS ((int));
339 static void s_mri_if PARAMS ((int));
340 static void s_mri_else PARAMS ((int));
341 static void s_mri_endi PARAMS ((int));
342 static void s_mri_break PARAMS ((int));
343 static void s_mri_next PARAMS ((int));
344 static void s_mri_for PARAMS ((int));
345 static void s_mri_endf PARAMS ((int));
346 static void s_mri_repeat PARAMS ((int));
347 static void s_mri_until PARAMS ((int));
348 static void s_mri_while PARAMS ((int));
349 static void s_mri_endw PARAMS ((int));
350 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
351 static void md_convert_frag_1 PARAMS ((fragS *));
352
353 static int current_architecture;
354
355 struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
361
362 static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
408
409 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
411 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
413
414 /* Macros used in the relaxation code. */
415 #define TAB(x,y) (((x) << 2) + (y))
416 #define TABTYPE(x) ((x) >> 2)
417
418 /* Relaxation states. */
419 #define BYTE 0
420 #define SHORT 1
421 #define LONG 2
422 #define SZ_UNDEF 3
423
424 /* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
434 #define BRANCHBWL 1 /* branch byte, word, or long */
435 #define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
436 #define BRABSJCOND 3 /* absolute jump for LONG, conditional */
437 #define BRANCHBW 4 /* branch byte or word */
438
439 /* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
447 #define FBRANCH 5 /* coprocessor branch */
448 #define DBCCLBR 6 /* DBcc relaxable with a long branch */
449 #define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
450
451 /* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
462 #define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
463 #define PCINDEX 9 /* PC+displacement+index */
464 #define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
465
466 /* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469 /* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
474 */
475 relax_typeS md_relax_table[] =
476 {
477 {1, 1, 0, 0}, /* First entries aren't used */
478 {1, 1, 0, 0}, /* For no good reason except */
479 {1, 1, 0, 0}, /* that the VAX doesn't either */
480 {1, 1, 0, 0},
481
482 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
483 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
484 {0, 0, 4, 0},
485 {1, 1, 0, 0},
486
487 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
488 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
489 {0, 0, 4, 0},
490 {1, 1, 0, 0},
491
492 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
493 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
494 {0, 0, 6, 0},
495 {1, 1, 0, 0},
496
497 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
498 {0, 0, 2, 0},
499 {1, 1, 0, 0},
500 {1, 1, 0, 0},
501
502 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
503 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
504 {0, 0, 4, 0},
505 {1, 1, 0, 0},
506
507 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
508 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
509 {0, 0, 10, 0},
510 {1, 1, 0, 0},
511
512 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
513 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
514 {0, 0, 10, 0},
515 {1, 1, 0, 0},
516
517 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
518 {32767, -32768, 2, TAB (PCREL1632, LONG)},
519 {0, 0, 6, 0},
520 {1, 1, 0, 0},
521
522 {125, -130, 0, TAB (PCINDEX, SHORT)},
523 {32765, -32770, 2, TAB (PCINDEX, LONG)},
524 {0, 0, 4, 0},
525 {1, 1, 0, 0},
526
527 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
528 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
529 {0, 0, 4, 0},
530 {1, 1, 0, 0},
531 };
532
533 /* These are the machine dependent pseudo-ops. These are included so
534 the assembler can work on the output from the SUN C compiler, which
535 generates these.
536 */
537
538 /* This table describes all the machine specific pseudo-ops the assembler
539 has to support. The fields are:
540 pseudo-op name without dot
541 function to call to execute this pseudo-op
542 Integer arg to pass to the function
543 */
544 const pseudo_typeS md_pseudo_table[] =
545 {
546 {"data1", s_data1, 0},
547 {"data2", s_data2, 0},
548 {"bss", s_bss, 0},
549 {"even", s_even, 0},
550 {"skip", s_space, 0},
551 {"proc", s_proc, 0},
552 #if defined (TE_SUN3) || defined (OBJ_ELF)
553 {"align", s_align_bytes, 0},
554 #endif
555 #ifdef OBJ_ELF
556 {"swbeg", s_ignore, 0},
557 #endif
558 {"extend", float_cons, 'x'},
559 {"ldouble", float_cons, 'x'},
560
561 /* The following pseudo-ops are supported for MRI compatibility. */
562 {"chip", s_chip, 0},
563 {"comline", s_space, 1},
564 {"fopt", s_fopt, 0},
565 {"mask2", s_ignore, 0},
566 {"opt", s_opt, 0},
567 {"reg", s_reg, 0},
568 {"restore", s_restore, 0},
569 {"save", s_save, 0},
570
571 {"if", s_mri_if, 0},
572 {"if.b", s_mri_if, 'b'},
573 {"if.w", s_mri_if, 'w'},
574 {"if.l", s_mri_if, 'l'},
575 {"else", s_mri_else, 0},
576 {"else.s", s_mri_else, 's'},
577 {"else.l", s_mri_else, 'l'},
578 {"endi", s_mri_endi, 0},
579 {"break", s_mri_break, 0},
580 {"break.s", s_mri_break, 's'},
581 {"break.l", s_mri_break, 'l'},
582 {"next", s_mri_next, 0},
583 {"next.s", s_mri_next, 's'},
584 {"next.l", s_mri_next, 'l'},
585 {"for", s_mri_for, 0},
586 {"for.b", s_mri_for, 'b'},
587 {"for.w", s_mri_for, 'w'},
588 {"for.l", s_mri_for, 'l'},
589 {"endf", s_mri_endf, 0},
590 {"repeat", s_mri_repeat, 0},
591 {"until", s_mri_until, 0},
592 {"until.b", s_mri_until, 'b'},
593 {"until.w", s_mri_until, 'w'},
594 {"until.l", s_mri_until, 'l'},
595 {"while", s_mri_while, 0},
596 {"while.b", s_mri_while, 'b'},
597 {"while.w", s_mri_while, 'w'},
598 {"while.l", s_mri_while, 'l'},
599 {"endw", s_mri_endw, 0},
600
601 {0, 0, 0}
602 };
603
604 /* The mote pseudo ops are put into the opcode table, since they
605 don't start with a . they look like opcodes to gas.
606 */
607
608 #ifdef M68KCOFF
609 extern void obj_coff_section PARAMS ((int));
610 #endif
611
612 CONST pseudo_typeS mote_pseudo_table[] =
613 {
614
615 {"dcl", cons, 4},
616 {"dc", cons, 2},
617 {"dcw", cons, 2},
618 {"dcb", cons, 1},
619
620 {"dsl", s_space, 4},
621 {"ds", s_space, 2},
622 {"dsw", s_space, 2},
623 {"dsb", s_space, 1},
624
625 {"xdef", s_globl, 0},
626 #ifdef OBJ_ELF
627 {"align", s_align_bytes, 0},
628 #else
629 {"align", s_align_ptwo, 0},
630 #endif
631 #ifdef M68KCOFF
632 {"sect", obj_coff_section, 0},
633 {"section", obj_coff_section, 0},
634 #endif
635 {0, 0, 0}
636 };
637
638 #define issbyte(x) ((x)>=-128 && (x)<=127)
639 #define isubyte(x) ((x)>=0 && (x)<=255)
640 #define issword(x) ((x)>=-32768 && (x)<=32767)
641 #define isuword(x) ((x)>=0 && (x)<=65535)
642
643 #define isbyte(x) ((x)>= -255 && (x)<=255)
644 #define isword(x) ((x)>=-65536 && (x)<=65535)
645 #define islong(x) (1)
646
647 extern char *input_line_pointer;
648
649 static char mklower_table[256];
650 #define mklower(c) (mklower_table[(unsigned char) (c)])
651 static char notend_table[256];
652 static char alt_notend_table[256];
653 #define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660 #ifdef NO_PCREL_RELOCS
661
662 int
663 make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666 {
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687 }
688
689 #endif /* NO_PCREL_RELOCS */
690
691 short
692 tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694 {
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697 #ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702 #else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710 #endif
711 }
712
713 #endif
714
715 #ifdef OBJ_ELF
716
717 /* Compute the relocation code for a fixup of SIZE bytes, using pc
718 relative relocation if PCREL is non-zero. PIC says whether a special
719 pic relocation was requested. */
720
721 static bfd_reloc_code_real_type get_reloc_code
722 PARAMS ((int, int, enum pic_relocation));
723
724 static bfd_reloc_code_real_type
725 get_reloc_code (size, pcrel, pic)
726 int size;
727 int pcrel;
728 enum pic_relocation pic;
729 {
730 switch (pic)
731 {
732 case pic_got_pcrel:
733 switch (size)
734 {
735 case 1:
736 return BFD_RELOC_8_GOT_PCREL;
737 case 2:
738 return BFD_RELOC_16_GOT_PCREL;
739 case 4:
740 return BFD_RELOC_32_GOT_PCREL;
741 }
742 break;
743
744 case pic_got_off:
745 switch (size)
746 {
747 case 1:
748 return BFD_RELOC_8_GOTOFF;
749 case 2:
750 return BFD_RELOC_16_GOTOFF;
751 case 4:
752 return BFD_RELOC_32_GOTOFF;
753 }
754 break;
755
756 case pic_plt_pcrel:
757 switch (size)
758 {
759 case 1:
760 return BFD_RELOC_8_PLT_PCREL;
761 case 2:
762 return BFD_RELOC_16_PLT_PCREL;
763 case 4:
764 return BFD_RELOC_32_PLT_PCREL;
765 }
766 break;
767
768 case pic_plt_off:
769 switch (size)
770 {
771 case 1:
772 return BFD_RELOC_8_PLTOFF;
773 case 2:
774 return BFD_RELOC_16_PLTOFF;
775 case 4:
776 return BFD_RELOC_32_PLTOFF;
777 }
778 break;
779
780 case pic_none:
781 if (pcrel)
782 {
783 switch (size)
784 {
785 case 1:
786 return BFD_RELOC_8_PCREL;
787 case 2:
788 return BFD_RELOC_16_PCREL;
789 case 4:
790 return BFD_RELOC_32_PCREL;
791 }
792 }
793 else
794 {
795 switch (size)
796 {
797 case 1:
798 return BFD_RELOC_8;
799 case 2:
800 return BFD_RELOC_16;
801 case 4:
802 return BFD_RELOC_32;
803 }
804 }
805 }
806
807 if (pcrel)
808 {
809 if (pic == pic_none)
810 as_bad (_("Can not do %d byte pc-relative relocation"), size);
811 else
812 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
813 }
814 else
815 {
816 if (pic == pic_none)
817 as_bad (_("Can not do %d byte relocation"), size);
818 else
819 as_bad (_("Can not do %d byte pic relocation"), size);
820 }
821
822 return BFD_RELOC_NONE;
823 }
824
825 /* Here we decide which fixups can be adjusted to make them relative
826 to the beginning of the section instead of the symbol. Basically
827 we need to make sure that the dynamic relocations are done
828 correctly, so in some cases we force the original symbol to be
829 used. */
830 int
831 tc_m68k_fix_adjustable (fixP)
832 fixS *fixP;
833 {
834 /* Prevent all adjustments to global symbols. */
835 if (S_IS_EXTERNAL (fixP->fx_addsy)
836 || S_IS_WEAK (fixP->fx_addsy))
837 return 0;
838
839 /* adjust_reloc_syms doesn't know about the GOT */
840 switch (fixP->fx_r_type)
841 {
842 case BFD_RELOC_8_GOT_PCREL:
843 case BFD_RELOC_16_GOT_PCREL:
844 case BFD_RELOC_32_GOT_PCREL:
845 case BFD_RELOC_8_GOTOFF:
846 case BFD_RELOC_16_GOTOFF:
847 case BFD_RELOC_32_GOTOFF:
848 case BFD_RELOC_8_PLT_PCREL:
849 case BFD_RELOC_16_PLT_PCREL:
850 case BFD_RELOC_32_PLT_PCREL:
851 case BFD_RELOC_8_PLTOFF:
852 case BFD_RELOC_16_PLTOFF:
853 case BFD_RELOC_32_PLTOFF:
854 return 0;
855
856 case BFD_RELOC_VTABLE_INHERIT:
857 case BFD_RELOC_VTABLE_ENTRY:
858 return 0;
859
860 default:
861 return 1;
862 }
863 }
864
865 #else /* !OBJ_ELF */
866
867 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
868
869 #endif /* OBJ_ELF */
870
871 #ifdef BFD_ASSEMBLER
872
873 arelent *
874 tc_gen_reloc (section, fixp)
875 asection *section;
876 fixS *fixp;
877 {
878 arelent *reloc;
879 bfd_reloc_code_real_type code;
880
881 /* If the tcbit is set, then this was a fixup of a negative value
882 that was never resolved. We do not have a reloc to handle this,
883 so just return. We assume that other code will have detected this
884 situation and produced a helpful error message, so we just tell the
885 user that the reloc cannot be produced. */
886 if (fixp->fx_tcbit)
887 {
888 if (fixp->fx_addsy)
889 as_bad (_("Unable to produce reloc against symbol '%s'"),
890 S_GET_NAME (fixp->fx_addsy));
891 return NULL;
892 }
893
894 if (fixp->fx_r_type != BFD_RELOC_NONE)
895 {
896 code = fixp->fx_r_type;
897
898 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
899 that fixup_segment converted a non-PC relative reloc into a
900 PC relative reloc. In such a case, we need to convert the
901 reloc code. */
902 if (fixp->fx_pcrel)
903 {
904 switch (code)
905 {
906 case BFD_RELOC_8:
907 code = BFD_RELOC_8_PCREL;
908 break;
909 case BFD_RELOC_16:
910 code = BFD_RELOC_16_PCREL;
911 break;
912 case BFD_RELOC_32:
913 code = BFD_RELOC_32_PCREL;
914 break;
915 case BFD_RELOC_8_PCREL:
916 case BFD_RELOC_16_PCREL:
917 case BFD_RELOC_32_PCREL:
918 case BFD_RELOC_8_GOT_PCREL:
919 case BFD_RELOC_16_GOT_PCREL:
920 case BFD_RELOC_32_GOT_PCREL:
921 case BFD_RELOC_8_GOTOFF:
922 case BFD_RELOC_16_GOTOFF:
923 case BFD_RELOC_32_GOTOFF:
924 case BFD_RELOC_8_PLT_PCREL:
925 case BFD_RELOC_16_PLT_PCREL:
926 case BFD_RELOC_32_PLT_PCREL:
927 case BFD_RELOC_8_PLTOFF:
928 case BFD_RELOC_16_PLTOFF:
929 case BFD_RELOC_32_PLTOFF:
930 break;
931 default:
932 as_bad_where (fixp->fx_file, fixp->fx_line,
933 _("Cannot make %s relocation PC relative"),
934 bfd_get_reloc_code_name (code));
935 }
936 }
937 }
938 else
939 {
940 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
941 switch (F (fixp->fx_size, fixp->fx_pcrel))
942 {
943 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
944 MAP (1, 0, BFD_RELOC_8);
945 MAP (2, 0, BFD_RELOC_16);
946 MAP (4, 0, BFD_RELOC_32);
947 MAP (1, 1, BFD_RELOC_8_PCREL);
948 MAP (2, 1, BFD_RELOC_16_PCREL);
949 MAP (4, 1, BFD_RELOC_32_PCREL);
950 default:
951 abort ();
952 }
953 }
954 #undef F
955 #undef MAP
956
957 reloc = (arelent *) xmalloc (sizeof (arelent));
958 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
959 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
960 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
961 #ifndef OBJ_ELF
962 if (fixp->fx_pcrel)
963 reloc->addend = fixp->fx_addnumber;
964 else
965 reloc->addend = 0;
966 #else
967 if (!fixp->fx_pcrel)
968 reloc->addend = fixp->fx_addnumber;
969 else
970 reloc->addend = (section->vma
971 + (fixp->fx_pcrel_adjust == 64
972 ? -1 : fixp->fx_pcrel_adjust)
973 + fixp->fx_addnumber
974 + md_pcrel_from (fixp));
975 #endif
976
977 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
978 assert (reloc->howto != 0);
979
980 return reloc;
981 }
982
983 #endif /* BFD_ASSEMBLER */
984
985 /* Return zero if the reference to SYMBOL from within the same segment may
986 be relaxed. */
987 #ifdef OBJ_ELF
988
989 /* On an ELF system, we can't relax an externally visible symbol,
990 because it may be overridden by a shared library. However, if
991 TARGET_OS is "elf", then we presume that we are assembling for an
992 embedded system, in which case we don't have to worry about shared
993 libraries, and we can relax anything. */
994
995 #define relaxable_symbol(symbol) \
996 (strcmp (TARGET_OS, "elf") == 0 \
997 || (! S_IS_EXTERNAL (symbol) \
998 && ! S_IS_WEAK (symbol)))
999
1000 #else
1001
1002 #define relaxable_symbol(symbol) 1
1003
1004 #endif
1005
1006 /* Handle of the OPCODE hash table. NULL means any use before
1007 m68k_ip_begin() will crash. */
1008 static struct hash_control *op_hash;
1009 \f
1010 /* Assemble an m68k instruction. */
1011
1012 static void
1013 m68k_ip (instring)
1014 char *instring;
1015 {
1016 register char *p;
1017 register struct m68k_op *opP;
1018 register const struct m68k_incant *opcode;
1019 register const char *s;
1020 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1021 char *pdot, *pdotmove;
1022 enum m68k_size siz1, siz2;
1023 char c;
1024 int losing;
1025 int opsfound;
1026 LITTLENUM_TYPE words[6];
1027 LITTLENUM_TYPE *wordp;
1028 unsigned long ok_arch = 0;
1029
1030 if (*instring == ' ')
1031 instring++; /* skip leading whitespace */
1032
1033 /* Scan up to end of operation-code, which MUST end in end-of-string
1034 or exactly 1 space. */
1035 pdot = 0;
1036 for (p = instring; *p != '\0'; p++)
1037 {
1038 if (*p == ' ')
1039 break;
1040 if (*p == '.')
1041 pdot = p;
1042 }
1043
1044 if (p == instring)
1045 {
1046 the_ins.error = _("No operator");
1047 return;
1048 }
1049
1050 /* p now points to the end of the opcode name, probably whitespace.
1051 Make sure the name is null terminated by clobbering the
1052 whitespace, look it up in the hash table, then fix it back.
1053 Remove a dot, first, since the opcode tables have none. */
1054 if (pdot != NULL)
1055 {
1056 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1057 *pdotmove = pdotmove[1];
1058 p--;
1059 }
1060
1061 c = *p;
1062 *p = '\0';
1063 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1064 *p = c;
1065
1066 if (pdot != NULL)
1067 {
1068 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1069 *pdotmove = pdotmove[-1];
1070 *pdot = '.';
1071 ++p;
1072 }
1073
1074 if (opcode == NULL)
1075 {
1076 the_ins.error = _("Unknown operator");
1077 return;
1078 }
1079
1080 /* found a legitimate opcode, start matching operands */
1081 while (*p == ' ')
1082 ++p;
1083
1084 if (opcode->m_operands == 0)
1085 {
1086 char *old = input_line_pointer;
1087 *old = '\n';
1088 input_line_pointer = p;
1089 /* Ahh - it's a motorola style psuedo op */
1090 mote_pseudo_table[opcode->m_opnum].poc_handler
1091 (mote_pseudo_table[opcode->m_opnum].poc_val);
1092 input_line_pointer = old;
1093 *old = 0;
1094
1095 return;
1096 }
1097
1098 if (flag_mri && opcode->m_opnum == 0)
1099 {
1100 /* In MRI mode, random garbage is allowed after an instruction
1101 which accepts no operands. */
1102 the_ins.args = opcode->m_operands;
1103 the_ins.numargs = opcode->m_opnum;
1104 the_ins.numo = opcode->m_codenum;
1105 the_ins.opcode[0] = getone (opcode);
1106 the_ins.opcode[1] = gettwo (opcode);
1107 return;
1108 }
1109
1110 for (opP = &the_ins.operands[0]; *p; opP++)
1111 {
1112 p = crack_operand (p, opP);
1113
1114 if (opP->error)
1115 {
1116 the_ins.error = opP->error;
1117 return;
1118 }
1119 }
1120
1121 opsfound = opP - &the_ins.operands[0];
1122
1123 /* This ugly hack is to support the floating pt opcodes in their
1124 standard form. Essentially, we fake a first enty of type COP#1 */
1125 if (opcode->m_operands[0] == 'I')
1126 {
1127 int n;
1128
1129 for (n = opsfound; n > 0; --n)
1130 the_ins.operands[n] = the_ins.operands[n - 1];
1131
1132 memset ((char *) (&the_ins.operands[0]), '\0',
1133 sizeof (the_ins.operands[0]));
1134 the_ins.operands[0].mode = CONTROL;
1135 the_ins.operands[0].reg = m68k_float_copnum;
1136 opsfound++;
1137 }
1138
1139 /* We've got the operands. Find an opcode that'll accept them */
1140 for (losing = 0;;)
1141 {
1142 /* If we didn't get the right number of ops, or we have no
1143 common model with this pattern then reject this pattern. */
1144
1145 ok_arch |= opcode->m_arch;
1146 if (opsfound != opcode->m_opnum
1147 || ((opcode->m_arch & current_architecture) == 0))
1148 ++losing;
1149 else
1150 {
1151 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1152 *s && !losing;
1153 s += 2, opP++)
1154 {
1155 /* Warning: this switch is huge! */
1156 /* I've tried to organize the cases into this order:
1157 non-alpha first, then alpha by letter. Lower-case
1158 goes directly before uppercase counterpart. */
1159 /* Code with multiple case ...: gets sorted by the lowest
1160 case ... it belongs to. I hope this makes sense. */
1161 switch (*s)
1162 {
1163 case '!':
1164 switch (opP->mode)
1165 {
1166 case IMMED:
1167 case DREG:
1168 case AREG:
1169 case FPREG:
1170 case CONTROL:
1171 case AINC:
1172 case ADEC:
1173 case REGLST:
1174 losing++;
1175 break;
1176 default:
1177 break;
1178 }
1179 break;
1180
1181 case '<':
1182 switch (opP->mode)
1183 {
1184 case DREG:
1185 case AREG:
1186 case FPREG:
1187 case CONTROL:
1188 case IMMED:
1189 case ADEC:
1190 case REGLST:
1191 losing++;
1192 break;
1193 default:
1194 break;
1195 }
1196 break;
1197
1198 case '>':
1199 switch (opP->mode)
1200 {
1201 case DREG:
1202 case AREG:
1203 case FPREG:
1204 case CONTROL:
1205 case IMMED:
1206 case AINC:
1207 case REGLST:
1208 losing++;
1209 break;
1210 case ABSL:
1211 break;
1212 default:
1213 if (opP->reg == PC
1214 || opP->reg == ZPC)
1215 losing++;
1216 break;
1217 }
1218 break;
1219
1220 case 'm':
1221 switch (opP->mode)
1222 {
1223 case DREG:
1224 case AREG:
1225 case AINDR:
1226 case AINC:
1227 case ADEC:
1228 break;
1229 default:
1230 losing++;
1231 }
1232 break;
1233
1234 case 'n':
1235 switch (opP->mode)
1236 {
1237 case DISP:
1238 break;
1239 default:
1240 losing++;
1241 }
1242 break;
1243
1244 case 'o':
1245 switch (opP->mode)
1246 {
1247 case BASE:
1248 case ABSL:
1249 case IMMED:
1250 break;
1251 default:
1252 losing++;
1253 }
1254 break;
1255
1256 case 'p':
1257 switch (opP->mode)
1258 {
1259 case DREG:
1260 case AREG:
1261 case AINDR:
1262 case AINC:
1263 case ADEC:
1264 break;
1265 case DISP:
1266 if (opP->reg == PC || opP->reg == ZPC)
1267 losing++;
1268 break;
1269 default:
1270 losing++;
1271 }
1272 break;
1273
1274 case 'q':
1275 switch (opP->mode)
1276 {
1277 case DREG:
1278 case AINDR:
1279 case AINC:
1280 case ADEC:
1281 break;
1282 case DISP:
1283 if (opP->reg == PC || opP->reg == ZPC)
1284 losing++;
1285 break;
1286 default:
1287 losing++;
1288 break;
1289 }
1290 break;
1291
1292 case 'v':
1293 switch (opP->mode)
1294 {
1295 case DREG:
1296 case AINDR:
1297 case AINC:
1298 case ADEC:
1299 case ABSL:
1300 break;
1301 case DISP:
1302 if (opP->reg == PC || opP->reg == ZPC)
1303 losing++;
1304 break;
1305 default:
1306 losing++;
1307 break;
1308 }
1309 break;
1310
1311 case '#':
1312 if (opP->mode != IMMED)
1313 losing++;
1314 else if (s[1] == 'b'
1315 && ! isvar (&opP->disp)
1316 && (opP->disp.exp.X_op != O_constant
1317 || ! isbyte (opP->disp.exp.X_add_number)))
1318 losing++;
1319 else if (s[1] == 'B'
1320 && ! isvar (&opP->disp)
1321 && (opP->disp.exp.X_op != O_constant
1322 || ! issbyte (opP->disp.exp.X_add_number)))
1323 losing++;
1324 else if (s[1] == 'w'
1325 && ! isvar (&opP->disp)
1326 && (opP->disp.exp.X_op != O_constant
1327 || ! isword (opP->disp.exp.X_add_number)))
1328 losing++;
1329 else if (s[1] == 'W'
1330 && ! isvar (&opP->disp)
1331 && (opP->disp.exp.X_op != O_constant
1332 || ! issword (opP->disp.exp.X_add_number)))
1333 losing++;
1334 break;
1335
1336 case '^':
1337 case 'T':
1338 if (opP->mode != IMMED)
1339 losing++;
1340 break;
1341
1342 case '$':
1343 if (opP->mode == AREG
1344 || opP->mode == CONTROL
1345 || opP->mode == FPREG
1346 || opP->mode == IMMED
1347 || opP->mode == REGLST
1348 || (opP->mode != ABSL
1349 && (opP->reg == PC
1350 || opP->reg == ZPC)))
1351 losing++;
1352 break;
1353
1354 case '%':
1355 if (opP->mode == CONTROL
1356 || opP->mode == FPREG
1357 || opP->mode == REGLST
1358 || opP->mode == IMMED
1359 || (opP->mode != ABSL
1360 && (opP->reg == PC
1361 || opP->reg == ZPC)))
1362 losing++;
1363 break;
1364
1365 case '&':
1366 switch (opP->mode)
1367 {
1368 case DREG:
1369 case AREG:
1370 case FPREG:
1371 case CONTROL:
1372 case IMMED:
1373 case AINC:
1374 case ADEC:
1375 case REGLST:
1376 losing++;
1377 break;
1378 case ABSL:
1379 break;
1380 default:
1381 if (opP->reg == PC
1382 || opP->reg == ZPC)
1383 losing++;
1384 break;
1385 }
1386 break;
1387
1388 case '*':
1389 if (opP->mode == CONTROL
1390 || opP->mode == FPREG
1391 || opP->mode == REGLST)
1392 losing++;
1393 break;
1394
1395 case '+':
1396 if (opP->mode != AINC)
1397 losing++;
1398 break;
1399
1400 case '-':
1401 if (opP->mode != ADEC)
1402 losing++;
1403 break;
1404
1405 case '/':
1406 switch (opP->mode)
1407 {
1408 case AREG:
1409 case CONTROL:
1410 case FPREG:
1411 case AINC:
1412 case ADEC:
1413 case IMMED:
1414 case REGLST:
1415 losing++;
1416 break;
1417 default:
1418 break;
1419 }
1420 break;
1421
1422 case ';':
1423 switch (opP->mode)
1424 {
1425 case AREG:
1426 case CONTROL:
1427 case FPREG:
1428 case REGLST:
1429 losing++;
1430 break;
1431 default:
1432 break;
1433 }
1434 break;
1435
1436 case '?':
1437 switch (opP->mode)
1438 {
1439 case AREG:
1440 case CONTROL:
1441 case FPREG:
1442 case AINC:
1443 case ADEC:
1444 case IMMED:
1445 case REGLST:
1446 losing++;
1447 break;
1448 case ABSL:
1449 break;
1450 default:
1451 if (opP->reg == PC || opP->reg == ZPC)
1452 losing++;
1453 break;
1454 }
1455 break;
1456
1457 case '@':
1458 switch (opP->mode)
1459 {
1460 case AREG:
1461 case CONTROL:
1462 case FPREG:
1463 case IMMED:
1464 case REGLST:
1465 losing++;
1466 break;
1467 default:
1468 break;
1469 }
1470 break;
1471
1472 case '~': /* For now! (JF FOO is this right?) */
1473 switch (opP->mode)
1474 {
1475 case DREG:
1476 case AREG:
1477 case CONTROL:
1478 case FPREG:
1479 case IMMED:
1480 case REGLST:
1481 losing++;
1482 break;
1483 case ABSL:
1484 break;
1485 default:
1486 if (opP->reg == PC
1487 || opP->reg == ZPC)
1488 losing++;
1489 break;
1490 }
1491 break;
1492
1493 case '3':
1494 if (opP->mode != CONTROL
1495 || (opP->reg != TT0 && opP->reg != TT1))
1496 losing++;
1497 break;
1498
1499 case 'A':
1500 if (opP->mode != AREG)
1501 losing++;
1502 break;
1503
1504 case 'a':
1505 if (opP->mode != AINDR)
1506 ++losing;
1507 break;
1508
1509 case 'B': /* FOO */
1510 if (opP->mode != ABSL
1511 || (flag_long_jumps
1512 && strncmp (instring, "jbsr", 4) == 0))
1513 losing++;
1514 break;
1515
1516 case 'C':
1517 if (opP->mode != CONTROL || opP->reg != CCR)
1518 losing++;
1519 break;
1520
1521 case 'd':
1522 if (opP->mode != DISP
1523 || opP->reg < ADDR0
1524 || opP->reg > ADDR7)
1525 losing++;
1526 break;
1527
1528 case 'D':
1529 if (opP->mode != DREG)
1530 losing++;
1531 break;
1532
1533 case 'E':
1534 if (opP->reg != ACC)
1535 losing++;
1536 break;
1537
1538 case 'F':
1539 if (opP->mode != FPREG)
1540 losing++;
1541 break;
1542
1543 case 'G':
1544 if (opP->reg != MACSR)
1545 losing++;
1546 break;
1547
1548 case 'H':
1549 if (opP->reg != MASK)
1550 losing++;
1551 break;
1552
1553 case 'I':
1554 if (opP->mode != CONTROL
1555 || opP->reg < COP0
1556 || opP->reg > COP7)
1557 losing++;
1558 break;
1559
1560 case 'J':
1561 if (opP->mode != CONTROL
1562 || opP->reg < USP
1563 || opP->reg > last_movec_reg)
1564 losing++;
1565 else
1566 {
1567 const enum m68k_register *rp;
1568 for (rp = control_regs; *rp; rp++)
1569 if (*rp == opP->reg)
1570 break;
1571 if (*rp == 0)
1572 losing++;
1573 }
1574 break;
1575
1576 case 'k':
1577 if (opP->mode != IMMED)
1578 losing++;
1579 break;
1580
1581 case 'l':
1582 case 'L':
1583 if (opP->mode == DREG
1584 || opP->mode == AREG
1585 || opP->mode == FPREG)
1586 {
1587 if (s[1] == '8')
1588 losing++;
1589 else
1590 {
1591 switch (opP->mode)
1592 {
1593 case DREG:
1594 opP->mask = 1 << (opP->reg - DATA0);
1595 break;
1596 case AREG:
1597 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1598 break;
1599 case FPREG:
1600 opP->mask = 1 << (opP->reg - FP0 + 16);
1601 break;
1602 default:
1603 abort ();
1604 }
1605 opP->mode = REGLST;
1606 }
1607 }
1608 else if (opP->mode == CONTROL)
1609 {
1610 if (s[1] != '8')
1611 losing++;
1612 else
1613 {
1614 switch (opP->reg)
1615 {
1616 case FPI:
1617 opP->mask = 1 << 24;
1618 break;
1619 case FPS:
1620 opP->mask = 1 << 25;
1621 break;
1622 case FPC:
1623 opP->mask = 1 << 26;
1624 break;
1625 default:
1626 losing++;
1627 break;
1628 }
1629 opP->mode = REGLST;
1630 }
1631 }
1632 else if (opP->mode != REGLST)
1633 losing++;
1634 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1635 losing++;
1636 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1637 losing++;
1638 break;
1639
1640 case 'M':
1641 if (opP->mode != IMMED)
1642 losing++;
1643 else if (opP->disp.exp.X_op != O_constant
1644 || ! issbyte (opP->disp.exp.X_add_number))
1645 losing++;
1646 else if (! m68k_quick
1647 && instring[3] != 'q'
1648 && instring[4] != 'q')
1649 losing++;
1650 break;
1651
1652 case 'O':
1653 if (opP->mode != DREG
1654 && opP->mode != IMMED
1655 && opP->mode != ABSL)
1656 losing++;
1657 break;
1658
1659 case 'Q':
1660 if (opP->mode != IMMED)
1661 losing++;
1662 else if (opP->disp.exp.X_op != O_constant
1663 || opP->disp.exp.X_add_number < 1
1664 || opP->disp.exp.X_add_number > 8)
1665 losing++;
1666 else if (! m68k_quick
1667 && (strncmp (instring, "add", 3) == 0
1668 || strncmp (instring, "sub", 3) == 0)
1669 && instring[3] != 'q')
1670 losing++;
1671 break;
1672
1673 case 'R':
1674 if (opP->mode != DREG && opP->mode != AREG)
1675 losing++;
1676 break;
1677
1678 case 'r':
1679 if (opP->mode != AINDR
1680 && (opP->mode != BASE
1681 || (opP->reg != 0
1682 && opP->reg != ZADDR0)
1683 || opP->disp.exp.X_op != O_absent
1684 || ((opP->index.reg < DATA0
1685 || opP->index.reg > DATA7)
1686 && (opP->index.reg < ADDR0
1687 || opP->index.reg > ADDR7))
1688 || opP->index.size != SIZE_UNSPEC
1689 || opP->index.scale != 1))
1690 losing++;
1691 break;
1692
1693 case 's':
1694 if (opP->mode != CONTROL
1695 || ! (opP->reg == FPI
1696 || opP->reg == FPS
1697 || opP->reg == FPC))
1698 losing++;
1699 break;
1700
1701 case 'S':
1702 if (opP->mode != CONTROL || opP->reg != SR)
1703 losing++;
1704 break;
1705
1706 case 't':
1707 if (opP->mode != IMMED)
1708 losing++;
1709 else if (opP->disp.exp.X_op != O_constant
1710 || opP->disp.exp.X_add_number < 0
1711 || opP->disp.exp.X_add_number > 7)
1712 losing++;
1713 break;
1714
1715 case 'U':
1716 if (opP->mode != CONTROL || opP->reg != USP)
1717 losing++;
1718 break;
1719
1720 /* JF these are out of order. We could put them
1721 in order if we were willing to put up with
1722 bunches of #ifdef m68851s in the code.
1723
1724 Don't forget that you need these operands
1725 to use 68030 MMU instructions. */
1726 #ifndef NO_68851
1727 /* Memory addressing mode used by pflushr */
1728 case '|':
1729 if (opP->mode == CONTROL
1730 || opP->mode == FPREG
1731 || opP->mode == DREG
1732 || opP->mode == AREG
1733 || opP->mode == REGLST)
1734 losing++;
1735 /* We should accept immediate operands, but they
1736 supposedly have to be quad word, and we don't
1737 handle that. I would like to see what a Motorola
1738 assembler does before doing something here. */
1739 if (opP->mode == IMMED)
1740 losing++;
1741 break;
1742
1743 case 'f':
1744 if (opP->mode != CONTROL
1745 || (opP->reg != SFC && opP->reg != DFC))
1746 losing++;
1747 break;
1748
1749 case '0':
1750 if (opP->mode != CONTROL || opP->reg != TC)
1751 losing++;
1752 break;
1753
1754 case '1':
1755 if (opP->mode != CONTROL || opP->reg != AC)
1756 losing++;
1757 break;
1758
1759 case '2':
1760 if (opP->mode != CONTROL
1761 || (opP->reg != CAL
1762 && opP->reg != VAL
1763 && opP->reg != SCC))
1764 losing++;
1765 break;
1766
1767 case 'V':
1768 if (opP->mode != CONTROL
1769 || opP->reg != VAL)
1770 losing++;
1771 break;
1772
1773 case 'W':
1774 if (opP->mode != CONTROL
1775 || (opP->reg != DRP
1776 && opP->reg != SRP
1777 && opP->reg != CRP))
1778 losing++;
1779 break;
1780
1781 case 'X':
1782 if (opP->mode != CONTROL
1783 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1784 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1785 losing++;
1786 break;
1787
1788 case 'Y':
1789 if (opP->mode != CONTROL || opP->reg != PSR)
1790 losing++;
1791 break;
1792
1793 case 'Z':
1794 if (opP->mode != CONTROL || opP->reg != PCSR)
1795 losing++;
1796 break;
1797 #endif
1798 case 'c':
1799 if (opP->mode != CONTROL
1800 || (opP->reg != NC
1801 && opP->reg != IC
1802 && opP->reg != DC
1803 && opP->reg != BC))
1804 {
1805 losing++;
1806 } /* not a cache specifier. */
1807 break;
1808
1809 case '_':
1810 if (opP->mode != ABSL)
1811 ++losing;
1812 break;
1813
1814 case 'u':
1815 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1816 losing++;
1817 /* FIXME: kludge instead of fixing parser:
1818 upper/lower registers are *not* CONTROL
1819 registers, but ordinary ones. */
1820 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1821 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1822 opP->mode = DREG;
1823 else
1824 opP->mode = AREG;
1825 break;
1826
1827 default:
1828 abort ();
1829 } /* switch on type of operand */
1830
1831 if (losing)
1832 break;
1833 } /* for each operand */
1834 } /* if immediately wrong */
1835
1836 if (!losing)
1837 {
1838 break;
1839 } /* got it. */
1840
1841 opcode = opcode->m_next;
1842
1843 if (!opcode)
1844 {
1845 if (ok_arch
1846 && !(ok_arch & current_architecture))
1847 {
1848 char buf[200], *cp;
1849
1850 strcpy (buf,
1851 _("invalid instruction for this architecture; needs "));
1852 cp = buf + strlen (buf);
1853 switch (ok_arch)
1854 {
1855 case mfloat:
1856 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1857 break;
1858 case mmmu:
1859 strcpy (cp, _("mmu (68030 or 68851)"));
1860 break;
1861 case m68020up:
1862 strcpy (cp, _("68020 or higher"));
1863 break;
1864 case m68000up:
1865 strcpy (cp, _("68000 or higher"));
1866 break;
1867 case m68010up:
1868 strcpy (cp, _("68010 or higher"));
1869 break;
1870 default:
1871 {
1872 int got_one = 0, idx;
1873 for (idx = 0;
1874 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1875 idx++)
1876 {
1877 if ((archs[idx].arch & ok_arch)
1878 && ! archs[idx].alias)
1879 {
1880 if (got_one)
1881 {
1882 strcpy (cp, " or ");
1883 cp += strlen (cp);
1884 }
1885 got_one = 1;
1886 strcpy (cp, archs[idx].name);
1887 cp += strlen (cp);
1888 }
1889 }
1890 }
1891 }
1892 cp = xmalloc (strlen (buf) + 1);
1893 strcpy (cp, buf);
1894 the_ins.error = cp;
1895 }
1896 else
1897 the_ins.error = _("operands mismatch");
1898 return;
1899 } /* Fell off the end */
1900
1901 losing = 0;
1902 }
1903
1904 /* now assemble it */
1905
1906 the_ins.args = opcode->m_operands;
1907 the_ins.numargs = opcode->m_opnum;
1908 the_ins.numo = opcode->m_codenum;
1909 the_ins.opcode[0] = getone (opcode);
1910 the_ins.opcode[1] = gettwo (opcode);
1911
1912 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1913 {
1914 /* This switch is a doozy.
1915 Watch the first step; its a big one! */
1916 switch (s[0])
1917 {
1918
1919 case '*':
1920 case '~':
1921 case '%':
1922 case ';':
1923 case '@':
1924 case '!':
1925 case '&':
1926 case '$':
1927 case '?':
1928 case '/':
1929 case '<':
1930 case '>':
1931 case 'm':
1932 case 'n':
1933 case 'o':
1934 case 'p':
1935 case 'q':
1936 case 'v':
1937 #ifndef NO_68851
1938 case '|':
1939 #endif
1940 switch (opP->mode)
1941 {
1942 case IMMED:
1943 tmpreg = 0x3c; /* 7.4 */
1944 if (strchr ("bwl", s[1]))
1945 nextword = get_num (&opP->disp, 80);
1946 else
1947 nextword = get_num (&opP->disp, 0);
1948 if (isvar (&opP->disp))
1949 add_fix (s[1], &opP->disp, 0, 0);
1950 switch (s[1])
1951 {
1952 case 'b':
1953 if (!isbyte (nextword))
1954 opP->error = _("operand out of range");
1955 addword (nextword);
1956 baseo = 0;
1957 break;
1958 case 'w':
1959 if (!isword (nextword))
1960 opP->error = _("operand out of range");
1961 addword (nextword);
1962 baseo = 0;
1963 break;
1964 case 'W':
1965 if (!issword (nextword))
1966 opP->error = _("operand out of range");
1967 addword (nextword);
1968 baseo = 0;
1969 break;
1970 case 'l':
1971 addword (nextword >> 16);
1972 addword (nextword);
1973 baseo = 0;
1974 break;
1975
1976 case 'f':
1977 baseo = 2;
1978 outro = 8;
1979 break;
1980 case 'F':
1981 baseo = 4;
1982 outro = 11;
1983 break;
1984 case 'x':
1985 baseo = 6;
1986 outro = 15;
1987 break;
1988 case 'p':
1989 baseo = 6;
1990 outro = -1;
1991 break;
1992 default:
1993 abort ();
1994 }
1995 if (!baseo)
1996 break;
1997
1998 /* We gotta put out some float */
1999 if (op (&opP->disp) != O_big)
2000 {
2001 valueT val;
2002 int gencnt;
2003
2004 /* Can other cases happen here? */
2005 if (op (&opP->disp) != O_constant)
2006 abort ();
2007
2008 val = (valueT) offs (&opP->disp);
2009 gencnt = 0;
2010 do
2011 {
2012 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2013 val >>= LITTLENUM_NUMBER_OF_BITS;
2014 ++gencnt;
2015 }
2016 while (val != 0);
2017 offs (&opP->disp) = gencnt;
2018 }
2019 if (offs (&opP->disp) > 0)
2020 {
2021 if (offs (&opP->disp) > baseo)
2022 {
2023 as_warn (_("Bignum too big for %c format; truncated"),
2024 s[1]);
2025 offs (&opP->disp) = baseo;
2026 }
2027 baseo -= offs (&opP->disp);
2028 while (baseo--)
2029 addword (0);
2030 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2031 offs (&opP->disp)--;
2032 --wordp)
2033 addword (*wordp);
2034 break;
2035 }
2036 gen_to_words (words, baseo, (long) outro);
2037 for (wordp = words; baseo--; wordp++)
2038 addword (*wordp);
2039 break;
2040 case DREG:
2041 tmpreg = opP->reg - DATA; /* 0.dreg */
2042 break;
2043 case AREG:
2044 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2045 break;
2046 case AINDR:
2047 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2048 break;
2049 case ADEC:
2050 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2051 break;
2052 case AINC:
2053 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2054 break;
2055 case DISP:
2056
2057 nextword = get_num (&opP->disp, 80);
2058
2059 if (opP->reg == PC
2060 && ! isvar (&opP->disp)
2061 && m68k_abspcadd)
2062 {
2063 opP->disp.exp.X_op = O_symbol;
2064 #ifndef BFD_ASSEMBLER
2065 opP->disp.exp.X_add_symbol = &abs_symbol;
2066 #else
2067 opP->disp.exp.X_add_symbol =
2068 section_symbol (absolute_section);
2069 #endif
2070 }
2071
2072 /* Force into index mode. Hope this works */
2073
2074 /* We do the first bit for 32-bit displacements, and the
2075 second bit for 16 bit ones. It is possible that we
2076 should make the default be WORD instead of LONG, but
2077 I think that'd break GCC, so we put up with a little
2078 inefficiency for the sake of working output. */
2079
2080 if (!issword (nextword)
2081 || (isvar (&opP->disp)
2082 && ((opP->disp.size == SIZE_UNSPEC
2083 && flag_short_refs == 0
2084 && cpu_of_arch (current_architecture) >= m68020
2085 && ! arch_coldfire_p (current_architecture))
2086 || opP->disp.size == SIZE_LONG)))
2087 {
2088 if (cpu_of_arch (current_architecture) < m68020
2089 || arch_coldfire_p (current_architecture))
2090 opP->error =
2091 _("displacement too large for this architecture; needs 68020 or higher");
2092 if (opP->reg == PC)
2093 tmpreg = 0x3B; /* 7.3 */
2094 else
2095 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2096 if (isvar (&opP->disp))
2097 {
2098 if (opP->reg == PC)
2099 {
2100 if (opP->disp.size == SIZE_LONG
2101 #ifdef OBJ_ELF
2102 /* If the displacement needs pic
2103 relocation it cannot be relaxed. */
2104 || opP->disp.pic_reloc != pic_none
2105 #endif
2106 )
2107 {
2108 addword (0x0170);
2109 add_fix ('l', &opP->disp, 1, 2);
2110 }
2111 else
2112 {
2113 add_frag (adds (&opP->disp),
2114 offs (&opP->disp),
2115 TAB (PCREL1632, SZ_UNDEF));
2116 break;
2117 }
2118 }
2119 else
2120 {
2121 addword (0x0170);
2122 add_fix ('l', &opP->disp, 0, 0);
2123 }
2124 }
2125 else
2126 addword (0x0170);
2127 addword (nextword >> 16);
2128 }
2129 else
2130 {
2131 if (opP->reg == PC)
2132 tmpreg = 0x3A; /* 7.2 */
2133 else
2134 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2135
2136 if (isvar (&opP->disp))
2137 {
2138 if (opP->reg == PC)
2139 {
2140 add_fix ('w', &opP->disp, 1, 0);
2141 }
2142 else
2143 add_fix ('w', &opP->disp, 0, 0);
2144 }
2145 }
2146 addword (nextword);
2147 break;
2148
2149 case POST:
2150 case PRE:
2151 case BASE:
2152 nextword = 0;
2153 baseo = get_num (&opP->disp, 80);
2154 if (opP->mode == POST || opP->mode == PRE)
2155 outro = get_num (&opP->odisp, 80);
2156 /* Figure out the `addressing mode'.
2157 Also turn on the BASE_DISABLE bit, if needed. */
2158 if (opP->reg == PC || opP->reg == ZPC)
2159 {
2160 tmpreg = 0x3b; /* 7.3 */
2161 if (opP->reg == ZPC)
2162 nextword |= 0x80;
2163 }
2164 else if (opP->reg == 0)
2165 {
2166 nextword |= 0x80;
2167 tmpreg = 0x30; /* 6.garbage */
2168 }
2169 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2170 {
2171 nextword |= 0x80;
2172 tmpreg = 0x30 + opP->reg - ZADDR0;
2173 }
2174 else
2175 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2176
2177 siz1 = opP->disp.size;
2178 if (opP->mode == POST || opP->mode == PRE)
2179 siz2 = opP->odisp.size;
2180 else
2181 siz2 = SIZE_UNSPEC;
2182
2183 /* Index register stuff */
2184 if (opP->index.reg != 0
2185 && opP->index.reg >= DATA
2186 && opP->index.reg <= ADDR7)
2187 {
2188 nextword |= (opP->index.reg - DATA) << 12;
2189
2190 if (opP->index.size == SIZE_LONG
2191 || (opP->index.size == SIZE_UNSPEC
2192 && m68k_index_width_default == SIZE_LONG))
2193 nextword |= 0x800;
2194
2195 if ((opP->index.scale != 1
2196 && cpu_of_arch (current_architecture) < m68020)
2197 || (opP->index.scale == 8
2198 && arch_coldfire_p (current_architecture)))
2199 {
2200 opP->error =
2201 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2202 }
2203
2204 if (arch_coldfire_p (current_architecture)
2205 && opP->index.size == SIZE_WORD)
2206 opP->error = _("invalid index size for coldfire");
2207
2208 switch (opP->index.scale)
2209 {
2210 case 1:
2211 break;
2212 case 2:
2213 nextword |= 0x200;
2214 break;
2215 case 4:
2216 nextword |= 0x400;
2217 break;
2218 case 8:
2219 nextword |= 0x600;
2220 break;
2221 default:
2222 abort ();
2223 }
2224 /* IF its simple,
2225 GET US OUT OF HERE! */
2226
2227 /* Must be INDEX, with an index register. Address
2228 register cannot be ZERO-PC, and either :b was
2229 forced, or we know it will fit. For a 68000 or
2230 68010, force this mode anyways, because the
2231 larger modes aren't supported. */
2232 if (opP->mode == BASE
2233 && ((opP->reg >= ADDR0
2234 && opP->reg <= ADDR7)
2235 || opP->reg == PC))
2236 {
2237 if (siz1 == SIZE_BYTE
2238 || cpu_of_arch (current_architecture) < m68020
2239 || arch_coldfire_p (current_architecture)
2240 || (siz1 == SIZE_UNSPEC
2241 && ! isvar (&opP->disp)
2242 && issbyte (baseo)))
2243 {
2244 nextword += baseo & 0xff;
2245 addword (nextword);
2246 if (isvar (&opP->disp))
2247 {
2248 /* Do a byte relocation. If it doesn't
2249 fit (possible on m68000) let the
2250 fixup processing complain later. */
2251 if (opP->reg == PC)
2252 add_fix ('B', &opP->disp, 1, 1);
2253 else
2254 add_fix ('B', &opP->disp, 0, 0);
2255 }
2256 else if (siz1 != SIZE_BYTE)
2257 {
2258 if (siz1 != SIZE_UNSPEC)
2259 as_warn (_("Forcing byte displacement"));
2260 if (! issbyte (baseo))
2261 opP->error = _("byte displacement out of range");
2262 }
2263
2264 break;
2265 }
2266 else if (siz1 == SIZE_UNSPEC
2267 && opP->reg == PC
2268 && isvar (&opP->disp)
2269 && subs (&opP->disp) == NULL
2270 #ifdef OBJ_ELF
2271 /* If the displacement needs pic
2272 relocation it cannot be relaxed. */
2273 && opP->disp.pic_reloc == pic_none
2274 #endif
2275 )
2276 {
2277 /* The code in md_convert_frag_1 needs to be
2278 able to adjust nextword. Call frag_grow
2279 to ensure that we have enough space in
2280 the frag obstack to make all the bytes
2281 contiguous. */
2282 frag_grow (14);
2283 nextword += baseo & 0xff;
2284 addword (nextword);
2285 add_frag (adds (&opP->disp), offs (&opP->disp),
2286 TAB (PCINDEX, SZ_UNDEF));
2287
2288 break;
2289 }
2290 }
2291 }
2292 else
2293 {
2294 nextword |= 0x40; /* No index reg */
2295 if (opP->index.reg >= ZDATA0
2296 && opP->index.reg <= ZDATA7)
2297 nextword |= (opP->index.reg - ZDATA0) << 12;
2298 else if (opP->index.reg >= ZADDR0
2299 || opP->index.reg <= ZADDR7)
2300 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2301 }
2302
2303 /* It isn't simple. */
2304
2305 if (cpu_of_arch (current_architecture) < m68020
2306 || arch_coldfire_p (current_architecture))
2307 opP->error =
2308 _("invalid operand mode for this architecture; needs 68020 or higher");
2309
2310 nextword |= 0x100;
2311 /* If the guy specified a width, we assume that it is
2312 wide enough. Maybe it isn't. If so, we lose. */
2313 switch (siz1)
2314 {
2315 case SIZE_UNSPEC:
2316 if (isvar (&opP->disp)
2317 ? m68k_rel32
2318 : ! issword (baseo))
2319 {
2320 siz1 = SIZE_LONG;
2321 nextword |= 0x30;
2322 }
2323 else if (! isvar (&opP->disp) && baseo == 0)
2324 nextword |= 0x10;
2325 else
2326 {
2327 nextword |= 0x20;
2328 siz1 = SIZE_WORD;
2329 }
2330 break;
2331 case SIZE_BYTE:
2332 as_warn (_(":b not permitted; defaulting to :w"));
2333 /* Fall through. */
2334 case SIZE_WORD:
2335 nextword |= 0x20;
2336 break;
2337 case SIZE_LONG:
2338 nextword |= 0x30;
2339 break;
2340 }
2341
2342 /* Figure out innner displacement stuff */
2343 if (opP->mode == POST || opP->mode == PRE)
2344 {
2345 if (cpu_of_arch (current_architecture) & cpu32)
2346 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2347 switch (siz2)
2348 {
2349 case SIZE_UNSPEC:
2350 if (isvar (&opP->odisp)
2351 ? m68k_rel32
2352 : ! issword (outro))
2353 {
2354 siz2 = SIZE_LONG;
2355 nextword |= 0x3;
2356 }
2357 else if (! isvar (&opP->odisp) && outro == 0)
2358 nextword |= 0x1;
2359 else
2360 {
2361 nextword |= 0x2;
2362 siz2 = SIZE_WORD;
2363 }
2364 break;
2365 case 1:
2366 as_warn (_(":b not permitted; defaulting to :w"));
2367 /* Fall through. */
2368 case 2:
2369 nextword |= 0x2;
2370 break;
2371 case 3:
2372 nextword |= 0x3;
2373 break;
2374 }
2375 if (opP->mode == POST
2376 && (nextword & 0x40) == 0)
2377 nextword |= 0x04;
2378 }
2379 addword (nextword);
2380
2381 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2382 {
2383 if (opP->reg == PC || opP->reg == ZPC)
2384 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2385 else
2386 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2387 }
2388 if (siz1 == SIZE_LONG)
2389 addword (baseo >> 16);
2390 if (siz1 != SIZE_UNSPEC)
2391 addword (baseo);
2392
2393 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2394 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2395 if (siz2 == SIZE_LONG)
2396 addword (outro >> 16);
2397 if (siz2 != SIZE_UNSPEC)
2398 addword (outro);
2399
2400 break;
2401
2402 case ABSL:
2403 nextword = get_num (&opP->disp, 80);
2404 switch (opP->disp.size)
2405 {
2406 default:
2407 abort ();
2408 case SIZE_UNSPEC:
2409 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2410 {
2411 tmpreg = 0x38; /* 7.0 */
2412 addword (nextword);
2413 break;
2414 }
2415 if (isvar (&opP->disp)
2416 && !subs (&opP->disp)
2417 && adds (&opP->disp)
2418 #ifdef OBJ_ELF
2419 /* If the displacement needs pic relocation it
2420 cannot be relaxed. */
2421 && opP->disp.pic_reloc == pic_none
2422 #endif
2423 && !flag_long_jumps
2424 && !strchr ("~%&$?", s[0]))
2425 {
2426 tmpreg = 0x3A; /* 7.2 */
2427 add_frag (adds (&opP->disp),
2428 offs (&opP->disp),
2429 TAB (ABSTOPCREL, SZ_UNDEF));
2430 break;
2431 }
2432 /* Fall through into long */
2433 case SIZE_LONG:
2434 if (isvar (&opP->disp))
2435 add_fix ('l', &opP->disp, 0, 0);
2436
2437 tmpreg = 0x39;/* 7.1 mode */
2438 addword (nextword >> 16);
2439 addword (nextword);
2440 break;
2441
2442 case SIZE_BYTE:
2443 as_bad (_("unsupported byte value; use a different suffix"));
2444 /* Fall through. */
2445 case SIZE_WORD: /* Word */
2446 if (isvar (&opP->disp))
2447 add_fix ('w', &opP->disp, 0, 0);
2448
2449 tmpreg = 0x38;/* 7.0 mode */
2450 addword (nextword);
2451 break;
2452 }
2453 break;
2454 case CONTROL:
2455 case FPREG:
2456 default:
2457 as_bad (_("unknown/incorrect operand"));
2458 /* abort (); */
2459 }
2460 install_gen_operand (s[1], tmpreg);
2461 break;
2462
2463 case '#':
2464 case '^':
2465 switch (s[1])
2466 { /* JF: I hate floating point! */
2467 case 'j':
2468 tmpreg = 70;
2469 break;
2470 case '8':
2471 tmpreg = 20;
2472 break;
2473 case 'C':
2474 tmpreg = 50;
2475 break;
2476 case '3':
2477 default:
2478 tmpreg = 80;
2479 break;
2480 }
2481 tmpreg = get_num (&opP->disp, tmpreg);
2482 if (isvar (&opP->disp))
2483 add_fix (s[1], &opP->disp, 0, 0);
2484 switch (s[1])
2485 {
2486 case 'b': /* Danger: These do no check for
2487 certain types of overflow.
2488 user beware! */
2489 if (!isbyte (tmpreg))
2490 opP->error = _("out of range");
2491 insop (tmpreg, opcode);
2492 if (isvar (&opP->disp))
2493 the_ins.reloc[the_ins.nrel - 1].n =
2494 (opcode->m_codenum) * 2 + 1;
2495 break;
2496 case 'B':
2497 if (!issbyte (tmpreg))
2498 opP->error = _("out of range");
2499 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2500 if (isvar (&opP->disp))
2501 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2502 break;
2503 case 'w':
2504 if (!isword (tmpreg))
2505 opP->error = _("out of range");
2506 insop (tmpreg, opcode);
2507 if (isvar (&opP->disp))
2508 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2509 break;
2510 case 'W':
2511 if (!issword (tmpreg))
2512 opP->error = _("out of range");
2513 insop (tmpreg, opcode);
2514 if (isvar (&opP->disp))
2515 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2516 break;
2517 case 'l':
2518 /* Because of the way insop works, we put these two out
2519 backwards. */
2520 insop (tmpreg, opcode);
2521 insop (tmpreg >> 16, opcode);
2522 if (isvar (&opP->disp))
2523 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2524 break;
2525 case '3':
2526 tmpreg &= 0xFF;
2527 case '8':
2528 case 'C':
2529 case 'j':
2530 install_operand (s[1], tmpreg);
2531 break;
2532 default:
2533 abort ();
2534 }
2535 break;
2536
2537 case '+':
2538 case '-':
2539 case 'A':
2540 case 'a':
2541 install_operand (s[1], opP->reg - ADDR);
2542 break;
2543
2544 case 'B':
2545 tmpreg = get_num (&opP->disp, 80);
2546 switch (s[1])
2547 {
2548 case 'B':
2549 /* The pc_fix argument winds up in fx_pcrel_adjust,
2550 which is a char, and may therefore be unsigned. We
2551 want to pass -1, but we pass 64 instead, and convert
2552 back in md_pcrel_from. */
2553 add_fix ('B', &opP->disp, 1, 64);
2554 break;
2555 case 'W':
2556 add_fix ('w', &opP->disp, 1, 0);
2557 addword (0);
2558 break;
2559 case 'L':
2560 long_branch:
2561 if (! HAVE_LONG_BRANCH (current_architecture))
2562 as_warn (_("Can't use long branches on 68000/68010/5200"));
2563 the_ins.opcode[0] |= 0xff;
2564 add_fix ('l', &opP->disp, 1, 0);
2565 addword (0);
2566 addword (0);
2567 break;
2568 case 'g':
2569 if (subs (&opP->disp)) /* We can't relax it */
2570 goto long_branch;
2571
2572 #ifdef OBJ_ELF
2573 /* If the displacement needs pic relocation it cannot be
2574 relaxed. */
2575 if (opP->disp.pic_reloc != pic_none)
2576 goto long_branch;
2577 #endif
2578 /* This could either be a symbol, or an absolute
2579 address. If it's an absolute address, turn it into
2580 an absolute jump right here and keep it out of the
2581 relaxer. */
2582 if (adds (&opP->disp) == 0)
2583 {
2584 if (the_ins.opcode[0] == 0x6000) /* jbra */
2585 the_ins.opcode[0] = 0x4EF1;
2586 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2587 the_ins.opcode[0] = 0x4EB1;
2588 else /* jCC */
2589 {
2590 the_ins.opcode[0] ^= 0x0100;
2591 the_ins.opcode[0] |= 0x0006;
2592 addword (0x4EF1);
2593 }
2594 add_fix ('l', &opP->disp, 0, 0);
2595 addword (0);
2596 addword (0);
2597 break;
2598 }
2599
2600 /* Now we know it's going into the relaxer. Now figure
2601 out which mode. We try in this order of preference:
2602 long branch, absolute jump, byte/word branches only. */
2603 if (HAVE_LONG_BRANCH (current_architecture))
2604 add_frag (adds (&opP->disp), offs (&opP->disp),
2605 TAB (BRANCHBWL, SZ_UNDEF));
2606 else if (! flag_keep_pcrel)
2607 {
2608 if ((the_ins.opcode[0] == 0x6000)
2609 || (the_ins.opcode[0] == 0x6100))
2610 add_frag (adds (&opP->disp), offs (&opP->disp),
2611 TAB (BRABSJUNC, SZ_UNDEF));
2612 else
2613 add_frag (adds (&opP->disp), offs (&opP->disp),
2614 TAB (BRABSJCOND, SZ_UNDEF));
2615 }
2616 else
2617 add_frag (adds (&opP->disp), offs (&opP->disp),
2618 TAB (BRANCHBW, SZ_UNDEF));
2619 break;
2620 case 'w':
2621 if (isvar (&opP->disp))
2622 {
2623 /* Check for DBcc instructions. We can relax them,
2624 but only if we have long branches and/or absolute
2625 jumps. */
2626 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2627 && (HAVE_LONG_BRANCH (current_architecture)
2628 || (! flag_keep_pcrel)))
2629 {
2630 if (HAVE_LONG_BRANCH (current_architecture))
2631 add_frag (adds (&opP->disp), offs (&opP->disp),
2632 TAB (DBCCLBR, SZ_UNDEF));
2633 else
2634 add_frag (adds (&opP->disp), offs (&opP->disp),
2635 TAB (DBCCABSJ, SZ_UNDEF));
2636 break;
2637 }
2638 add_fix ('w', &opP->disp, 1, 0);
2639 }
2640 addword (0);
2641 break;
2642 case 'C': /* Fixed size LONG coproc branches */
2643 add_fix ('l', &opP->disp, 1, 0);
2644 addword (0);
2645 addword (0);
2646 break;
2647 case 'c': /* Var size Coprocesssor branches */
2648 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2649 {
2650 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2651 add_fix ('l', &opP->disp, 1, 0);
2652 addword (0);
2653 addword (0);
2654 }
2655 else
2656 add_frag (adds (&opP->disp), offs (&opP->disp),
2657 TAB (FBRANCH, SZ_UNDEF));
2658 break;
2659 default:
2660 abort ();
2661 }
2662 break;
2663
2664 case 'C': /* Ignore it */
2665 break;
2666
2667 case 'd': /* JF this is a kludge */
2668 install_operand ('s', opP->reg - ADDR);
2669 tmpreg = get_num (&opP->disp, 80);
2670 if (!issword (tmpreg))
2671 {
2672 as_warn (_("Expression out of range, using 0"));
2673 tmpreg = 0;
2674 }
2675 addword (tmpreg);
2676 break;
2677
2678 case 'D':
2679 install_operand (s[1], opP->reg - DATA);
2680 break;
2681
2682 case 'E': /* Ignore it */
2683 break;
2684
2685 case 'F':
2686 install_operand (s[1], opP->reg - FP0);
2687 break;
2688
2689 case 'G': /* Ignore it */
2690 case 'H':
2691 break;
2692
2693 case 'I':
2694 tmpreg = opP->reg - COP0;
2695 install_operand (s[1], tmpreg);
2696 break;
2697
2698 case 'J': /* JF foo */
2699 switch (opP->reg)
2700 {
2701 case SFC:
2702 tmpreg = 0x000;
2703 break;
2704 case DFC:
2705 tmpreg = 0x001;
2706 break;
2707 case CACR:
2708 tmpreg = 0x002;
2709 break;
2710 case TC:
2711 tmpreg = 0x003;
2712 break;
2713 case ITT0:
2714 tmpreg = 0x004;
2715 break;
2716 case ITT1:
2717 tmpreg = 0x005;
2718 break;
2719 case DTT0:
2720 tmpreg = 0x006;
2721 break;
2722 case DTT1:
2723 tmpreg = 0x007;
2724 break;
2725 case BUSCR:
2726 tmpreg = 0x008;
2727 break;
2728
2729 case USP:
2730 tmpreg = 0x800;
2731 break;
2732 case VBR:
2733 tmpreg = 0x801;
2734 break;
2735 case CAAR:
2736 tmpreg = 0x802;
2737 break;
2738 case MSP:
2739 tmpreg = 0x803;
2740 break;
2741 case ISP:
2742 tmpreg = 0x804;
2743 break;
2744 case MMUSR:
2745 tmpreg = 0x805;
2746 break;
2747 case URP:
2748 tmpreg = 0x806;
2749 break;
2750 case SRP:
2751 tmpreg = 0x807;
2752 break;
2753 case PCR:
2754 tmpreg = 0x808;
2755 break;
2756 case ROMBAR:
2757 tmpreg = 0xC00;
2758 break;
2759 case RAMBAR0:
2760 tmpreg = 0xC04;
2761 break;
2762 case RAMBAR1:
2763 tmpreg = 0xC05;
2764 break;
2765 case MBAR:
2766 tmpreg = 0xC0F;
2767 break;
2768 default:
2769 abort ();
2770 }
2771 install_operand (s[1], tmpreg);
2772 break;
2773
2774 case 'k':
2775 tmpreg = get_num (&opP->disp, 55);
2776 install_operand (s[1], tmpreg & 0x7f);
2777 break;
2778
2779 case 'l':
2780 tmpreg = opP->mask;
2781 if (s[1] == 'w')
2782 {
2783 if (tmpreg & 0x7FF0000)
2784 as_bad (_("Floating point register in register list"));
2785 insop (reverse_16_bits (tmpreg), opcode);
2786 }
2787 else
2788 {
2789 if (tmpreg & 0x700FFFF)
2790 as_bad (_("Wrong register in floating-point reglist"));
2791 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2792 }
2793 break;
2794
2795 case 'L':
2796 tmpreg = opP->mask;
2797 if (s[1] == 'w')
2798 {
2799 if (tmpreg & 0x7FF0000)
2800 as_bad (_("Floating point register in register list"));
2801 insop (tmpreg, opcode);
2802 }
2803 else if (s[1] == '8')
2804 {
2805 if (tmpreg & 0x0FFFFFF)
2806 as_bad (_("incorrect register in reglist"));
2807 install_operand (s[1], tmpreg >> 24);
2808 }
2809 else
2810 {
2811 if (tmpreg & 0x700FFFF)
2812 as_bad (_("wrong register in floating-point reglist"));
2813 else
2814 install_operand (s[1], tmpreg >> 16);
2815 }
2816 break;
2817
2818 case 'M':
2819 install_operand (s[1], get_num (&opP->disp, 60));
2820 break;
2821
2822 case 'O':
2823 tmpreg = ((opP->mode == DREG)
2824 ? 0x20 + (int) (opP->reg - DATA)
2825 : (get_num (&opP->disp, 40) & 0x1F));
2826 install_operand (s[1], tmpreg);
2827 break;
2828
2829 case 'Q':
2830 tmpreg = get_num (&opP->disp, 10);
2831 if (tmpreg == 8)
2832 tmpreg = 0;
2833 install_operand (s[1], tmpreg);
2834 break;
2835
2836 case 'R':
2837 /* This depends on the fact that ADDR registers are eight
2838 more than their corresponding DATA regs, so the result
2839 will have the ADDR_REG bit set */
2840 install_operand (s[1], opP->reg - DATA);
2841 break;
2842
2843 case 'r':
2844 if (opP->mode == AINDR)
2845 install_operand (s[1], opP->reg - DATA);
2846 else
2847 install_operand (s[1], opP->index.reg - DATA);
2848 break;
2849
2850 case 's':
2851 if (opP->reg == FPI)
2852 tmpreg = 0x1;
2853 else if (opP->reg == FPS)
2854 tmpreg = 0x2;
2855 else if (opP->reg == FPC)
2856 tmpreg = 0x4;
2857 else
2858 abort ();
2859 install_operand (s[1], tmpreg);
2860 break;
2861
2862 case 'S': /* Ignore it */
2863 break;
2864
2865 case 'T':
2866 install_operand (s[1], get_num (&opP->disp, 30));
2867 break;
2868
2869 case 'U': /* Ignore it */
2870 break;
2871
2872 case 'c':
2873 switch (opP->reg)
2874 {
2875 case NC:
2876 tmpreg = 0;
2877 break;
2878 case DC:
2879 tmpreg = 1;
2880 break;
2881 case IC:
2882 tmpreg = 2;
2883 break;
2884 case BC:
2885 tmpreg = 3;
2886 break;
2887 default:
2888 as_fatal (_("failed sanity check"));
2889 } /* switch on cache token */
2890 install_operand (s[1], tmpreg);
2891 break;
2892 #ifndef NO_68851
2893 /* JF: These are out of order, I fear. */
2894 case 'f':
2895 switch (opP->reg)
2896 {
2897 case SFC:
2898 tmpreg = 0;
2899 break;
2900 case DFC:
2901 tmpreg = 1;
2902 break;
2903 default:
2904 abort ();
2905 }
2906 install_operand (s[1], tmpreg);
2907 break;
2908
2909 case '0':
2910 case '1':
2911 case '2':
2912 switch (opP->reg)
2913 {
2914 case TC:
2915 tmpreg = 0;
2916 break;
2917 case CAL:
2918 tmpreg = 4;
2919 break;
2920 case VAL:
2921 tmpreg = 5;
2922 break;
2923 case SCC:
2924 tmpreg = 6;
2925 break;
2926 case AC:
2927 tmpreg = 7;
2928 break;
2929 default:
2930 abort ();
2931 }
2932 install_operand (s[1], tmpreg);
2933 break;
2934
2935 case 'V':
2936 if (opP->reg == VAL)
2937 break;
2938 abort ();
2939
2940 case 'W':
2941 switch (opP->reg)
2942 {
2943 case DRP:
2944 tmpreg = 1;
2945 break;
2946 case SRP:
2947 tmpreg = 2;
2948 break;
2949 case CRP:
2950 tmpreg = 3;
2951 break;
2952 default:
2953 abort ();
2954 }
2955 install_operand (s[1], tmpreg);
2956 break;
2957
2958 case 'X':
2959 switch (opP->reg)
2960 {
2961 case BAD:
2962 case BAD + 1:
2963 case BAD + 2:
2964 case BAD + 3:
2965 case BAD + 4:
2966 case BAD + 5:
2967 case BAD + 6:
2968 case BAD + 7:
2969 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2970 break;
2971
2972 case BAC:
2973 case BAC + 1:
2974 case BAC + 2:
2975 case BAC + 3:
2976 case BAC + 4:
2977 case BAC + 5:
2978 case BAC + 6:
2979 case BAC + 7:
2980 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2981 break;
2982
2983 default:
2984 abort ();
2985 }
2986 install_operand (s[1], tmpreg);
2987 break;
2988 case 'Y':
2989 know (opP->reg == PSR);
2990 break;
2991 case 'Z':
2992 know (opP->reg == PCSR);
2993 break;
2994 #endif /* m68851 */
2995 case '3':
2996 switch (opP->reg)
2997 {
2998 case TT0:
2999 tmpreg = 2;
3000 break;
3001 case TT1:
3002 tmpreg = 3;
3003 break;
3004 default:
3005 abort ();
3006 }
3007 install_operand (s[1], tmpreg);
3008 break;
3009 case 't':
3010 tmpreg = get_num (&opP->disp, 20);
3011 install_operand (s[1], tmpreg);
3012 break;
3013 case '_': /* used only for move16 absolute 32-bit address */
3014 if (isvar (&opP->disp))
3015 add_fix ('l', &opP->disp, 0, 0);
3016 tmpreg = get_num (&opP->disp, 80);
3017 addword (tmpreg >> 16);
3018 addword (tmpreg & 0xFFFF);
3019 break;
3020 case 'u':
3021 install_operand (s[1], opP->reg - DATA0L);
3022 opP->reg -= (DATA0L);
3023 opP->reg &= 0x0F; /* remove upper/lower bit */
3024 break;
3025 default:
3026 abort ();
3027 }
3028 }
3029
3030 /* By the time whe get here (FINALLY) the_ins contains the complete
3031 instruction, ready to be emitted. . . */
3032 }
3033
3034 static int
3035 reverse_16_bits (in)
3036 int in;
3037 {
3038 int out = 0;
3039 int n;
3040
3041 static int mask[16] =
3042 {
3043 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3044 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3045 };
3046 for (n = 0; n < 16; n++)
3047 {
3048 if (in & mask[n])
3049 out |= mask[15 - n];
3050 }
3051 return out;
3052 } /* reverse_16_bits() */
3053
3054 static int
3055 reverse_8_bits (in)
3056 int in;
3057 {
3058 int out = 0;
3059 int n;
3060
3061 static int mask[8] =
3062 {
3063 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3064 };
3065
3066 for (n = 0; n < 8; n++)
3067 {
3068 if (in & mask[n])
3069 out |= mask[7 - n];
3070 }
3071 return out;
3072 } /* reverse_8_bits() */
3073
3074 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3075 (that value is chosen in the frag_var call in md_assemble). TYPE
3076 is the subtype of the frag to be generated; its primary type is
3077 rs_machine_dependent.
3078
3079 The TYPE parameter is also used by md_convert_frag_1 and
3080 md_estimate_size_before_relax. The appropriate type of fixup will
3081 be emitted by md_convert_frag_1.
3082
3083 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3084 static void
3085 install_operand (mode, val)
3086 int mode;
3087 int val;
3088 {
3089 switch (mode)
3090 {
3091 case 's':
3092 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3093 break;
3094 case 'd':
3095 the_ins.opcode[0] |= val << 9;
3096 break;
3097 case '1':
3098 the_ins.opcode[1] |= val << 12;
3099 break;
3100 case '2':
3101 the_ins.opcode[1] |= val << 6;
3102 break;
3103 case '3':
3104 the_ins.opcode[1] |= val;
3105 break;
3106 case '4':
3107 the_ins.opcode[2] |= val << 12;
3108 break;
3109 case '5':
3110 the_ins.opcode[2] |= val << 6;
3111 break;
3112 case '6':
3113 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3114 three words long! */
3115 the_ins.numo++;
3116 the_ins.opcode[2] |= val;
3117 break;
3118 case '7':
3119 the_ins.opcode[1] |= val << 7;
3120 break;
3121 case '8':
3122 the_ins.opcode[1] |= val << 10;
3123 break;
3124 #ifndef NO_68851
3125 case '9':
3126 the_ins.opcode[1] |= val << 5;
3127 break;
3128 #endif
3129
3130 case 't':
3131 the_ins.opcode[1] |= (val << 10) | (val << 7);
3132 break;
3133 case 'D':
3134 the_ins.opcode[1] |= (val << 12) | val;
3135 break;
3136 case 'g':
3137 the_ins.opcode[0] |= val = 0xff;
3138 break;
3139 case 'i':
3140 the_ins.opcode[0] |= val << 9;
3141 break;
3142 case 'C':
3143 the_ins.opcode[1] |= val;
3144 break;
3145 case 'j':
3146 the_ins.opcode[1] |= val;
3147 the_ins.numo++; /* What a hack */
3148 break;
3149 case 'k':
3150 the_ins.opcode[1] |= val << 4;
3151 break;
3152 case 'b':
3153 case 'w':
3154 case 'W':
3155 case 'l':
3156 break;
3157 case 'e':
3158 the_ins.opcode[0] |= (val << 6);
3159 break;
3160 case 'L':
3161 the_ins.opcode[1] = (val >> 16);
3162 the_ins.opcode[2] = val & 0xffff;
3163 break;
3164 case 'm':
3165 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3166 the_ins.opcode[0] |= ((val & 0x7) << 9);
3167 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3168 break;
3169 case 'n':
3170 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3171 the_ins.opcode[0] |= ((val & 0x7) << 9);
3172 break;
3173 case 'o':
3174 the_ins.opcode[1] |= val << 12;
3175 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3176 break;
3177 case 'M':
3178 the_ins.opcode[0] |= (val & 0xF);
3179 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3180 break;
3181 case 'N':
3182 the_ins.opcode[1] |= (val & 0xF);
3183 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3184 break;
3185 case 'h':
3186 the_ins.opcode[1] |= ((val != 1) << 10);
3187 break;
3188 case 'c':
3189 default:
3190 as_fatal (_("failed sanity check."));
3191 }
3192 } /* install_operand() */
3193
3194 static void
3195 install_gen_operand (mode, val)
3196 int mode;
3197 int val;
3198 {
3199 switch (mode)
3200 {
3201 case 's':
3202 the_ins.opcode[0] |= val;
3203 break;
3204 case 'd':
3205 /* This is a kludge!!! */
3206 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3207 break;
3208 case 'b':
3209 case 'w':
3210 case 'l':
3211 case 'f':
3212 case 'F':
3213 case 'x':
3214 case 'p':
3215 the_ins.opcode[0] |= val;
3216 break;
3217 /* more stuff goes here */
3218 default:
3219 as_fatal (_("failed sanity check."));
3220 }
3221 } /* install_gen_operand() */
3222
3223 /*
3224 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3225 * then deal with the bitfield hack.
3226 */
3227
3228 static char *
3229 crack_operand (str, opP)
3230 register char *str;
3231 register struct m68k_op *opP;
3232 {
3233 register int parens;
3234 register int c;
3235 register char *beg_str;
3236 int inquote = 0;
3237
3238 if (!str)
3239 {
3240 return str;
3241 }
3242 beg_str = str;
3243 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3244 {
3245 if (! inquote)
3246 {
3247 if (*str == '(')
3248 parens++;
3249 else if (*str == ')')
3250 {
3251 if (!parens)
3252 { /* ERROR */
3253 opP->error = _("Extra )");
3254 return str;
3255 }
3256 --parens;
3257 }
3258 }
3259 if (flag_mri && *str == '\'')
3260 inquote = ! inquote;
3261 }
3262 if (!*str && parens)
3263 { /* ERROR */
3264 opP->error = _("Missing )");
3265 return str;
3266 }
3267 c = *str;
3268 *str = '\0';
3269 if (m68k_ip_op (beg_str, opP) != 0)
3270 {
3271 *str = c;
3272 return str;
3273 }
3274 *str = c;
3275 if (c == '}')
3276 c = *++str; /* JF bitfield hack */
3277 if (c)
3278 {
3279 c = *++str;
3280 if (!c)
3281 as_bad (_("Missing operand"));
3282 }
3283
3284 /* Detect MRI REG symbols and convert them to REGLSTs. */
3285 if (opP->mode == CONTROL && (int)opP->reg < 0)
3286 {
3287 opP->mode = REGLST;
3288 opP->mask = ~(int)opP->reg;
3289 opP->reg = 0;
3290 }
3291
3292 return str;
3293 }
3294
3295 /* This is the guts of the machine-dependent assembler. STR points to a
3296 machine dependent instruction. This function is supposed to emit
3297 the frags/bytes it assembles to.
3298 */
3299
3300 static void
3301 insert_reg (regname, regnum)
3302 const char *regname;
3303 int regnum;
3304 {
3305 char buf[100];
3306 int i;
3307
3308 #ifdef REGISTER_PREFIX
3309 if (!flag_reg_prefix_optional)
3310 {
3311 buf[0] = REGISTER_PREFIX;
3312 strcpy (buf + 1, regname);
3313 regname = buf;
3314 }
3315 #endif
3316
3317 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3318 &zero_address_frag));
3319
3320 for (i = 0; regname[i]; i++)
3321 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3322 buf[i] = '\0';
3323
3324 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3325 &zero_address_frag));
3326 }
3327
3328 struct init_entry
3329 {
3330 const char *name;
3331 int number;
3332 };
3333
3334 static const struct init_entry init_table[] =
3335 {
3336 { "d0", DATA0 },
3337 { "d1", DATA1 },
3338 { "d2", DATA2 },
3339 { "d3", DATA3 },
3340 { "d4", DATA4 },
3341 { "d5", DATA5 },
3342 { "d6", DATA6 },
3343 { "d7", DATA7 },
3344 { "a0", ADDR0 },
3345 { "a1", ADDR1 },
3346 { "a2", ADDR2 },
3347 { "a3", ADDR3 },
3348 { "a4", ADDR4 },
3349 { "a5", ADDR5 },
3350 { "a6", ADDR6 },
3351 { "fp", ADDR6 },
3352 { "a7", ADDR7 },
3353 { "sp", ADDR7 },
3354 { "ssp", ADDR7 },
3355 { "fp0", FP0 },
3356 { "fp1", FP1 },
3357 { "fp2", FP2 },
3358 { "fp3", FP3 },
3359 { "fp4", FP4 },
3360 { "fp5", FP5 },
3361 { "fp6", FP6 },
3362 { "fp7", FP7 },
3363 { "fpi", FPI },
3364 { "fpiar", FPI },
3365 { "fpc", FPI },
3366 { "fps", FPS },
3367 { "fpsr", FPS },
3368 { "fpc", FPC },
3369 { "fpcr", FPC },
3370 { "control", FPC },
3371 { "status", FPS },
3372 { "iaddr", FPI },
3373
3374 { "cop0", COP0 },
3375 { "cop1", COP1 },
3376 { "cop2", COP2 },
3377 { "cop3", COP3 },
3378 { "cop4", COP4 },
3379 { "cop5", COP5 },
3380 { "cop6", COP6 },
3381 { "cop7", COP7 },
3382 { "pc", PC },
3383 { "zpc", ZPC },
3384 { "sr", SR },
3385
3386 { "ccr", CCR },
3387 { "cc", CCR },
3388
3389 { "acc", ACC },
3390 { "macsr", MACSR },
3391 { "mask", MASK },
3392
3393 /* control registers */
3394 { "sfc", SFC }, /* Source Function Code */
3395 { "sfcr", SFC },
3396 { "dfc", DFC }, /* Destination Function Code */
3397 { "dfcr", DFC },
3398 { "cacr", CACR }, /* Cache Control Register */
3399 { "caar", CAAR }, /* Cache Address Register */
3400
3401 { "usp", USP }, /* User Stack Pointer */
3402 { "vbr", VBR }, /* Vector Base Register */
3403 { "msp", MSP }, /* Master Stack Pointer */
3404 { "isp", ISP }, /* Interrupt Stack Pointer */
3405
3406 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3407 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3408 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3409 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3410
3411 /* 68ec040 versions of same */
3412 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3413 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3414 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3415 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3416
3417 /* mcf5200 versions of same. The ColdFire programmer's reference
3418 manual indicated that the order is 2,3,0,1, but Ken Rose
3419 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3420 { "acr0", ITT0 }, /* Access Control Unit 0 */
3421 { "acr1", ITT1 }, /* Access Control Unit 1 */
3422 { "acr2", DTT0 }, /* Access Control Unit 2 */
3423 { "acr3", DTT1 }, /* Access Control Unit 3 */
3424
3425 { "tc", TC }, /* MMU Translation Control Register */
3426 { "tcr", TC },
3427
3428 { "mmusr", MMUSR }, /* MMU Status Register */
3429 { "srp", SRP }, /* User Root Pointer */
3430 { "urp", URP }, /* Supervisor Root Pointer */
3431
3432 { "buscr", BUSCR },
3433 { "pcr", PCR },
3434
3435 { "rombar", ROMBAR }, /* ROM Base Address Register */
3436 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3437 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3438 { "mbar", MBAR }, /* Module Base Address Register */
3439 /* end of control registers */
3440
3441 { "ac", AC },
3442 { "bc", BC },
3443 { "cal", CAL },
3444 { "crp", CRP },
3445 { "drp", DRP },
3446 { "pcsr", PCSR },
3447 { "psr", PSR },
3448 { "scc", SCC },
3449 { "val", VAL },
3450 { "bad0", BAD0 },
3451 { "bad1", BAD1 },
3452 { "bad2", BAD2 },
3453 { "bad3", BAD3 },
3454 { "bad4", BAD4 },
3455 { "bad5", BAD5 },
3456 { "bad6", BAD6 },
3457 { "bad7", BAD7 },
3458 { "bac0", BAC0 },
3459 { "bac1", BAC1 },
3460 { "bac2", BAC2 },
3461 { "bac3", BAC3 },
3462 { "bac4", BAC4 },
3463 { "bac5", BAC5 },
3464 { "bac6", BAC6 },
3465 { "bac7", BAC7 },
3466
3467 { "ic", IC },
3468 { "dc", DC },
3469 { "nc", NC },
3470
3471 { "tt0", TT0 },
3472 { "tt1", TT1 },
3473 /* 68ec030 versions of same */
3474 { "ac0", TT0 },
3475 { "ac1", TT1 },
3476 /* 68ec030 access control unit, identical to 030 MMU status reg */
3477 { "acusr", PSR },
3478
3479 /* Suppressed data and address registers. */
3480 { "zd0", ZDATA0 },
3481 { "zd1", ZDATA1 },
3482 { "zd2", ZDATA2 },
3483 { "zd3", ZDATA3 },
3484 { "zd4", ZDATA4 },
3485 { "zd5", ZDATA5 },
3486 { "zd6", ZDATA6 },
3487 { "zd7", ZDATA7 },
3488 { "za0", ZADDR0 },
3489 { "za1", ZADDR1 },
3490 { "za2", ZADDR2 },
3491 { "za3", ZADDR3 },
3492 { "za4", ZADDR4 },
3493 { "za5", ZADDR5 },
3494 { "za6", ZADDR6 },
3495 { "za7", ZADDR7 },
3496
3497 /* Upper and lower data and address registers, used by macw and msacw. */
3498 { "d0l", DATA0L },
3499 { "d1l", DATA1L },
3500 { "d2l", DATA2L },
3501 { "d3l", DATA3L },
3502 { "d4l", DATA4L },
3503 { "d5l", DATA5L },
3504 { "d6l", DATA6L },
3505 { "d7l", DATA7L },
3506
3507 { "a0l", ADDR0L },
3508 { "a1l", ADDR1L },
3509 { "a2l", ADDR2L },
3510 { "a3l", ADDR3L },
3511 { "a4l", ADDR4L },
3512 { "a5l", ADDR5L },
3513 { "a6l", ADDR6L },
3514 { "a7l", ADDR7L },
3515
3516 { "d0u", DATA0U },
3517 { "d1u", DATA1U },
3518 { "d2u", DATA2U },
3519 { "d3u", DATA3U },
3520 { "d4u", DATA4U },
3521 { "d5u", DATA5U },
3522 { "d6u", DATA6U },
3523 { "d7u", DATA7U },
3524
3525 { "a0u", ADDR0U },
3526 { "a1u", ADDR1U },
3527 { "a2u", ADDR2U },
3528 { "a3u", ADDR3U },
3529 { "a4u", ADDR4U },
3530 { "a5u", ADDR5U },
3531 { "a6u", ADDR6U },
3532 { "a7u", ADDR7U },
3533
3534 { 0, 0 }
3535 };
3536
3537 static void
3538 init_regtable ()
3539 {
3540 int i;
3541 for (i = 0; init_table[i].name; i++)
3542 insert_reg (init_table[i].name, init_table[i].number);
3543 }
3544
3545 static int no_68851, no_68881;
3546
3547 #ifdef OBJ_AOUT
3548 /* a.out machine type. Default to 68020. */
3549 int m68k_aout_machtype = 2;
3550 #endif
3551
3552 void
3553 md_assemble (str)
3554 char *str;
3555 {
3556 const char *er;
3557 short *fromP;
3558 char *toP = NULL;
3559 int m, n = 0;
3560 char *to_beg_P;
3561 int shorts_this_frag;
3562 fixS *fixP;
3563
3564 /* In MRI mode, the instruction and operands are separated by a
3565 space. Anything following the operands is a comment. The label
3566 has already been removed. */
3567 if (flag_mri)
3568 {
3569 char *s;
3570 int fields = 0;
3571 int infield = 0;
3572 int inquote = 0;
3573
3574 for (s = str; *s != '\0'; s++)
3575 {
3576 if ((*s == ' ' || *s == '\t') && ! inquote)
3577 {
3578 if (infield)
3579 {
3580 ++fields;
3581 if (fields >= 2)
3582 {
3583 *s = '\0';
3584 break;
3585 }
3586 infield = 0;
3587 }
3588 }
3589 else
3590 {
3591 if (! infield)
3592 infield = 1;
3593 if (*s == '\'')
3594 inquote = ! inquote;
3595 }
3596 }
3597 }
3598
3599 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3600 m68k_ip (str);
3601 er = the_ins.error;
3602 if (!er)
3603 {
3604 for (n = 0; n < the_ins.numargs; n++)
3605 if (the_ins.operands[n].error)
3606 {
3607 er = the_ins.operands[n].error;
3608 break;
3609 }
3610 }
3611 if (er)
3612 {
3613 as_bad (_("%s -- statement `%s' ignored"), er, str);
3614 return;
3615 }
3616
3617 /* If there is a current label, record that it marks an instruction. */
3618 if (current_label != NULL)
3619 {
3620 current_label->text = 1;
3621 current_label = NULL;
3622 }
3623
3624 if (the_ins.nfrag == 0)
3625 {
3626 /* No frag hacking involved; just put it out */
3627 toP = frag_more (2 * the_ins.numo);
3628 fromP = &the_ins.opcode[0];
3629 for (m = the_ins.numo; m; --m)
3630 {
3631 md_number_to_chars (toP, (long) (*fromP), 2);
3632 toP += 2;
3633 fromP++;
3634 }
3635 /* put out symbol-dependent info */
3636 for (m = 0; m < the_ins.nrel; m++)
3637 {
3638 switch (the_ins.reloc[m].wid)
3639 {
3640 case 'B':
3641 n = 1;
3642 break;
3643 case 'b':
3644 n = 1;
3645 break;
3646 case '3':
3647 n = 1;
3648 break;
3649 case 'w':
3650 case 'W':
3651 n = 2;
3652 break;
3653 case 'l':
3654 n = 4;
3655 break;
3656 default:
3657 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3658 the_ins.reloc[m].wid);
3659 }
3660
3661 fixP = fix_new_exp (frag_now,
3662 ((toP - frag_now->fr_literal)
3663 - the_ins.numo * 2 + the_ins.reloc[m].n),
3664 n,
3665 &the_ins.reloc[m].exp,
3666 the_ins.reloc[m].pcrel,
3667 get_reloc_code (n, the_ins.reloc[m].pcrel,
3668 the_ins.reloc[m].pic_reloc));
3669 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3670 if (the_ins.reloc[m].wid == 'B')
3671 fixP->fx_signed = 1;
3672 }
3673 return;
3674 }
3675
3676 /* There's some frag hacking */
3677 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3678 {
3679 int wid;
3680
3681 if (n == 0)
3682 wid = 2 * the_ins.fragb[n].fragoff;
3683 else
3684 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3685 toP = frag_more (wid);
3686 to_beg_P = toP;
3687 shorts_this_frag = 0;
3688 for (m = wid / 2; m; --m)
3689 {
3690 md_number_to_chars (toP, (long) (*fromP), 2);
3691 toP += 2;
3692 fromP++;
3693 shorts_this_frag++;
3694 }
3695 for (m = 0; m < the_ins.nrel; m++)
3696 {
3697 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3698 {
3699 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3700 break;
3701 }
3702 wid = the_ins.reloc[m].wid;
3703 if (wid == 0)
3704 continue;
3705 the_ins.reloc[m].wid = 0;
3706 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3707
3708 fixP = fix_new_exp (frag_now,
3709 ((toP - frag_now->fr_literal)
3710 - the_ins.numo * 2 + the_ins.reloc[m].n),
3711 wid,
3712 &the_ins.reloc[m].exp,
3713 the_ins.reloc[m].pcrel,
3714 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3715 the_ins.reloc[m].pic_reloc));
3716 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3717 }
3718 (void) frag_var (rs_machine_dependent, 10, 0,
3719 (relax_substateT) (the_ins.fragb[n].fragty),
3720 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3721 }
3722 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3723 shorts_this_frag = 0;
3724 if (n)
3725 {
3726 toP = frag_more (n * sizeof (short));
3727 while (n--)
3728 {
3729 md_number_to_chars (toP, (long) (*fromP), 2);
3730 toP += 2;
3731 fromP++;
3732 shorts_this_frag++;
3733 }
3734 }
3735 for (m = 0; m < the_ins.nrel; m++)
3736 {
3737 int wid;
3738
3739 wid = the_ins.reloc[m].wid;
3740 if (wid == 0)
3741 continue;
3742 the_ins.reloc[m].wid = 0;
3743 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3744
3745 fixP = fix_new_exp (frag_now,
3746 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3747 - shorts_this_frag * 2),
3748 wid,
3749 &the_ins.reloc[m].exp,
3750 the_ins.reloc[m].pcrel,
3751 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3752 the_ins.reloc[m].pic_reloc));
3753 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3754 }
3755 }
3756
3757 void
3758 md_begin ()
3759 {
3760 /*
3761 * md_begin -- set up hash tables with 68000 instructions.
3762 * similar to what the vax assembler does. ---phr
3763 */
3764 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3765 a copy of it at runtime, adding in the information we want but isn't
3766 there. I think it'd be better to have an awk script hack the table
3767 at compile time. Or even just xstr the table and use it as-is. But
3768 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3769 names. */
3770
3771 register const struct m68k_opcode *ins;
3772 register struct m68k_incant *hack, *slak;
3773 register const char *retval = 0; /* empty string, or error msg text */
3774 register int i;
3775 register char c;
3776
3777 if (flag_mri)
3778 {
3779 flag_reg_prefix_optional = 1;
3780 m68k_abspcadd = 1;
3781 if (! m68k_rel32_from_cmdline)
3782 m68k_rel32 = 0;
3783 }
3784
3785 op_hash = hash_new ();
3786
3787 obstack_begin (&robyn, 4000);
3788 for (i = 0; i < m68k_numopcodes; i++)
3789 {
3790 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3791 do
3792 {
3793 ins = &m68k_opcodes[i];
3794 /* We *could* ignore insns that don't match our arch here
3795 but just leaving them out of the hash. */
3796 slak->m_operands = ins->args;
3797 slak->m_opnum = strlen (slak->m_operands) / 2;
3798 slak->m_arch = ins->arch;
3799 slak->m_opcode = ins->opcode;
3800 /* This is kludgey */
3801 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3802 if (i + 1 != m68k_numopcodes
3803 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3804 {
3805 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3806 i++;
3807 }
3808 else
3809 slak->m_next = 0;
3810 slak = slak->m_next;
3811 }
3812 while (slak);
3813
3814 retval = hash_insert (op_hash, ins->name, (char *) hack);
3815 if (retval)
3816 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3817 }
3818
3819 for (i = 0; i < m68k_numaliases; i++)
3820 {
3821 const char *name = m68k_opcode_aliases[i].primary;
3822 const char *alias = m68k_opcode_aliases[i].alias;
3823 PTR val = hash_find (op_hash, name);
3824 if (!val)
3825 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3826 retval = hash_insert (op_hash, alias, val);
3827 if (retval)
3828 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3829 }
3830
3831 /* In MRI mode, all unsized branches are variable sized. Normally,
3832 they are word sized. */
3833 if (flag_mri)
3834 {
3835 static struct m68k_opcode_alias mri_aliases[] =
3836 {
3837 { "bhi", "jhi", },
3838 { "bls", "jls", },
3839 { "bcc", "jcc", },
3840 { "bcs", "jcs", },
3841 { "bne", "jne", },
3842 { "beq", "jeq", },
3843 { "bvc", "jvc", },
3844 { "bvs", "jvs", },
3845 { "bpl", "jpl", },
3846 { "bmi", "jmi", },
3847 { "bge", "jge", },
3848 { "blt", "jlt", },
3849 { "bgt", "jgt", },
3850 { "ble", "jle", },
3851 { "bra", "jra", },
3852 { "bsr", "jbsr", },
3853 };
3854
3855 for (i = 0;
3856 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3857 i++)
3858 {
3859 const char *name = mri_aliases[i].primary;
3860 const char *alias = mri_aliases[i].alias;
3861 PTR val = hash_find (op_hash, name);
3862 if (!val)
3863 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3864 retval = hash_jam (op_hash, alias, val);
3865 if (retval)
3866 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3867 }
3868 }
3869
3870 for (i = 0; i < (int) sizeof (mklower_table); i++)
3871 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3872
3873 for (i = 0; i < (int) sizeof (notend_table); i++)
3874 {
3875 notend_table[i] = 0;
3876 alt_notend_table[i] = 0;
3877 }
3878 notend_table[','] = 1;
3879 notend_table['{'] = 1;
3880 notend_table['}'] = 1;
3881 alt_notend_table['a'] = 1;
3882 alt_notend_table['A'] = 1;
3883 alt_notend_table['d'] = 1;
3884 alt_notend_table['D'] = 1;
3885 alt_notend_table['#'] = 1;
3886 alt_notend_table['&'] = 1;
3887 alt_notend_table['f'] = 1;
3888 alt_notend_table['F'] = 1;
3889 #ifdef REGISTER_PREFIX
3890 alt_notend_table[REGISTER_PREFIX] = 1;
3891 #endif
3892
3893 /* We need to put '(' in alt_notend_table to handle
3894 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3895 */
3896 alt_notend_table['('] = 1;
3897
3898 /* We need to put '@' in alt_notend_table to handle
3899 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3900 */
3901 alt_notend_table['@'] = 1;
3902
3903 /* We need to put digits in alt_notend_table to handle
3904 bfextu %d0{24:1},%d0
3905 */
3906 alt_notend_table['0'] = 1;
3907 alt_notend_table['1'] = 1;
3908 alt_notend_table['2'] = 1;
3909 alt_notend_table['3'] = 1;
3910 alt_notend_table['4'] = 1;
3911 alt_notend_table['5'] = 1;
3912 alt_notend_table['6'] = 1;
3913 alt_notend_table['7'] = 1;
3914 alt_notend_table['8'] = 1;
3915 alt_notend_table['9'] = 1;
3916
3917 #ifndef MIT_SYNTAX_ONLY
3918 /* Insert pseudo ops, these have to go into the opcode table since
3919 gas expects pseudo ops to start with a dot */
3920 {
3921 int n = 0;
3922 while (mote_pseudo_table[n].poc_name)
3923 {
3924 hack = (struct m68k_incant *)
3925 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3926 hash_insert (op_hash,
3927 mote_pseudo_table[n].poc_name, (char *) hack);
3928 hack->m_operands = 0;
3929 hack->m_opnum = n;
3930 n++;
3931 }
3932 }
3933 #endif
3934
3935 init_regtable ();
3936
3937 #ifdef OBJ_ELF
3938 record_alignment (text_section, 2);
3939 record_alignment (data_section, 2);
3940 record_alignment (bss_section, 2);
3941 #endif
3942 }
3943
3944 static void
3945 select_control_regs ()
3946 {
3947 /* Note which set of "movec" control registers is available. */
3948 switch (cpu_of_arch (current_architecture))
3949 {
3950 case m68000:
3951 control_regs = m68000_control_regs;
3952 break;
3953 case m68010:
3954 control_regs = m68010_control_regs;
3955 break;
3956 case m68020:
3957 case m68030:
3958 control_regs = m68020_control_regs;
3959 break;
3960 case m68040:
3961 control_regs = m68040_control_regs;
3962 break;
3963 case m68060:
3964 control_regs = m68060_control_regs;
3965 break;
3966 case cpu32:
3967 control_regs = cpu32_control_regs;
3968 break;
3969 case mcf5200:
3970 case mcf5206e:
3971 case mcf5307:
3972 case mcf5407:
3973 control_regs = mcf_control_regs;
3974 break;
3975 default:
3976 abort ();
3977 }
3978 }
3979
3980 void
3981 m68k_init_after_args ()
3982 {
3983 if (cpu_of_arch (current_architecture) == 0)
3984 {
3985 int i;
3986 const char *default_cpu = TARGET_CPU;
3987
3988 if (*default_cpu == 'm')
3989 default_cpu++;
3990 for (i = 0; i < n_archs; i++)
3991 if (strcasecmp (default_cpu, archs[i].name) == 0)
3992 break;
3993 if (i == n_archs)
3994 {
3995 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3996 current_architecture |= m68020;
3997 }
3998 else
3999 current_architecture |= archs[i].arch;
4000 }
4001 /* Permit m68881 specification with all cpus; those that can't work
4002 with a coprocessor could be doing emulation. */
4003 if (current_architecture & m68851)
4004 {
4005 if (current_architecture & m68040)
4006 {
4007 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4008 }
4009 }
4010 /* What other incompatibilities could we check for? */
4011
4012 /* Toss in some default assumptions about coprocessors. */
4013 if (!no_68881
4014 && (cpu_of_arch (current_architecture)
4015 /* Can CPU32 have a 68881 coprocessor?? */
4016 & (m68020 | m68030 | cpu32)))
4017 {
4018 current_architecture |= m68881;
4019 }
4020 if (!no_68851
4021 && (cpu_of_arch (current_architecture) & m68020up) != 0
4022 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4023 {
4024 current_architecture |= m68851;
4025 }
4026 if (no_68881 && (current_architecture & m68881))
4027 as_bad (_("options for 68881 and no-68881 both given"));
4028 if (no_68851 && (current_architecture & m68851))
4029 as_bad (_("options for 68851 and no-68851 both given"));
4030
4031 #ifdef OBJ_AOUT
4032 /* Work out the magic number. This isn't very general. */
4033 if (current_architecture & m68000)
4034 m68k_aout_machtype = 0;
4035 else if (current_architecture & m68010)
4036 m68k_aout_machtype = 1;
4037 else if (current_architecture & m68020)
4038 m68k_aout_machtype = 2;
4039 else
4040 m68k_aout_machtype = 2;
4041 #endif
4042
4043 /* Note which set of "movec" control registers is available. */
4044 select_control_regs ();
4045
4046 if (cpu_of_arch (current_architecture) < m68020
4047 || arch_coldfire_p (current_architecture))
4048 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4049 }
4050 \f
4051 /* This is called when a label is defined. */
4052
4053 void
4054 m68k_frob_label (sym)
4055 symbolS *sym;
4056 {
4057 struct label_line *n;
4058
4059 n = (struct label_line *) xmalloc (sizeof *n);
4060 n->next = labels;
4061 n->label = sym;
4062 as_where (&n->file, &n->line);
4063 n->text = 0;
4064 labels = n;
4065 current_label = n;
4066 }
4067
4068 /* This is called when a value that is not an instruction is emitted. */
4069
4070 void
4071 m68k_flush_pending_output ()
4072 {
4073 current_label = NULL;
4074 }
4075
4076 /* This is called at the end of the assembly, when the final value of
4077 the label is known. We warn if this is a text symbol aligned at an
4078 odd location. */
4079
4080 void
4081 m68k_frob_symbol (sym)
4082 symbolS *sym;
4083 {
4084 if (S_GET_SEGMENT (sym) == reg_section
4085 && (int) S_GET_VALUE (sym) < 0)
4086 {
4087 S_SET_SEGMENT (sym, absolute_section);
4088 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4089 }
4090 else if ((S_GET_VALUE (sym) & 1) != 0)
4091 {
4092 struct label_line *l;
4093
4094 for (l = labels; l != NULL; l = l->next)
4095 {
4096 if (l->label == sym)
4097 {
4098 if (l->text)
4099 as_warn_where (l->file, l->line,
4100 _("text label `%s' aligned to odd boundary"),
4101 S_GET_NAME (sym));
4102 break;
4103 }
4104 }
4105 }
4106 }
4107 \f
4108 /* This is called if we go in or out of MRI mode because of the .mri
4109 pseudo-op. */
4110
4111 void
4112 m68k_mri_mode_change (on)
4113 int on;
4114 {
4115 if (on)
4116 {
4117 if (! flag_reg_prefix_optional)
4118 {
4119 flag_reg_prefix_optional = 1;
4120 #ifdef REGISTER_PREFIX
4121 init_regtable ();
4122 #endif
4123 }
4124 m68k_abspcadd = 1;
4125 if (! m68k_rel32_from_cmdline)
4126 m68k_rel32 = 0;
4127 }
4128 else
4129 {
4130 if (! reg_prefix_optional_seen)
4131 {
4132 #ifdef REGISTER_PREFIX_OPTIONAL
4133 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4134 #else
4135 flag_reg_prefix_optional = 0;
4136 #endif
4137 #ifdef REGISTER_PREFIX
4138 init_regtable ();
4139 #endif
4140 }
4141 m68k_abspcadd = 0;
4142 if (! m68k_rel32_from_cmdline)
4143 m68k_rel32 = 1;
4144 }
4145 }
4146
4147 /* Equal to MAX_PRECISION in atof-ieee.c */
4148 #define MAX_LITTLENUMS 6
4149
4150 /* Turn a string in input_line_pointer into a floating point constant
4151 of type TYPE, and store the appropriate bytes in *LITP. The number
4152 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4153 returned, or NULL on OK. */
4154
4155 char *
4156 md_atof (type, litP, sizeP)
4157 char type;
4158 char *litP;
4159 int *sizeP;
4160 {
4161 int prec;
4162 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4163 LITTLENUM_TYPE *wordP;
4164 char *t;
4165
4166 switch (type)
4167 {
4168 case 'f':
4169 case 'F':
4170 case 's':
4171 case 'S':
4172 prec = 2;
4173 break;
4174
4175 case 'd':
4176 case 'D':
4177 case 'r':
4178 case 'R':
4179 prec = 4;
4180 break;
4181
4182 case 'x':
4183 case 'X':
4184 prec = 6;
4185 break;
4186
4187 case 'p':
4188 case 'P':
4189 prec = 6;
4190 break;
4191
4192 default:
4193 *sizeP = 0;
4194 return _("Bad call to MD_ATOF()");
4195 }
4196 t = atof_ieee (input_line_pointer, type, words);
4197 if (t)
4198 input_line_pointer = t;
4199
4200 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4201 for (wordP = words; prec--;)
4202 {
4203 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4204 litP += sizeof (LITTLENUM_TYPE);
4205 }
4206 return 0;
4207 }
4208
4209 void
4210 md_number_to_chars (buf, val, n)
4211 char *buf;
4212 valueT val;
4213 int n;
4214 {
4215 number_to_chars_bigendian (buf, val, n);
4216 }
4217
4218 static void
4219 md_apply_fix_2 (fixP, val)
4220 fixS *fixP;
4221 offsetT val;
4222 {
4223 addressT upper_limit;
4224 offsetT lower_limit;
4225
4226 /* This is unnecessary but it convinces the native rs6000 compiler
4227 to generate the code we want. */
4228 char *buf = fixP->fx_frag->fr_literal;
4229 buf += fixP->fx_where;
4230 /* end ibm compiler workaround */
4231
4232 if (val & 0x80000000)
4233 val |= ~(addressT)0x7fffffff;
4234 else
4235 val &= 0x7fffffff;
4236
4237 #ifdef OBJ_ELF
4238 if (fixP->fx_addsy)
4239 {
4240 memset (buf, 0, fixP->fx_size);
4241 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4242
4243 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4244 && !S_IS_DEFINED (fixP->fx_addsy)
4245 && !S_IS_WEAK (fixP->fx_addsy))
4246 S_SET_WEAK (fixP->fx_addsy);
4247 return;
4248 }
4249 #endif
4250
4251 #ifdef BFD_ASSEMBLER
4252 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4253 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4254 return;
4255 #endif
4256
4257 switch (fixP->fx_size)
4258 {
4259 /* The cast to offsetT below are necessary to make code correct for
4260 machines where ints are smaller than offsetT */
4261 case 1:
4262 *buf++ = val;
4263 upper_limit = 0x7f;
4264 lower_limit = - (offsetT) 0x80;
4265 break;
4266 case 2:
4267 *buf++ = (val >> 8);
4268 *buf++ = val;
4269 upper_limit = 0x7fff;
4270 lower_limit = - (offsetT) 0x8000;
4271 break;
4272 case 4:
4273 *buf++ = (val >> 24);
4274 *buf++ = (val >> 16);
4275 *buf++ = (val >> 8);
4276 *buf++ = val;
4277 upper_limit = 0x7fffffff;
4278 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4279 break;
4280 default:
4281 BAD_CASE (fixP->fx_size);
4282 }
4283
4284 /* Fix up a negative reloc. */
4285 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4286 {
4287 fixP->fx_addsy = fixP->fx_subsy;
4288 fixP->fx_subsy = NULL;
4289 fixP->fx_tcbit = 1;
4290 }
4291
4292 /* For non-pc-relative values, it's conceivable we might get something
4293 like "0xff" for a byte field. So extend the upper part of the range
4294 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4295 so that we can do any range checking at all. */
4296 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4297 upper_limit = upper_limit * 2 + 1;
4298
4299 if ((addressT) val > upper_limit
4300 && (val > 0 || val < lower_limit))
4301 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4302
4303 /* A one byte PC-relative reloc means a short branch. We can't use
4304 a short branch with a value of 0 or -1, because those indicate
4305 different opcodes (branches with longer offsets). fixup_segment
4306 in write.c may have clobbered fx_pcrel, so we need to examine the
4307 reloc type. */
4308 if ((fixP->fx_pcrel
4309 #ifdef BFD_ASSEMBLER
4310 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4311 #endif
4312 )
4313 && fixP->fx_size == 1
4314 && (fixP->fx_addsy == NULL
4315 || S_IS_DEFINED (fixP->fx_addsy))
4316 && (val == 0 || val == -1))
4317 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4318 }
4319
4320 #ifdef BFD_ASSEMBLER
4321 int
4322 md_apply_fix (fixP, valp)
4323 fixS *fixP;
4324 valueT *valp;
4325 {
4326 md_apply_fix_2 (fixP, (addressT) *valp);
4327 return 1;
4328 }
4329 #else
4330 void md_apply_fix (fixP, val)
4331 fixS *fixP;
4332 long val;
4333 {
4334 md_apply_fix_2 (fixP, (addressT) val);
4335 }
4336 #endif
4337
4338 /* *fragP has been relaxed to its final size, and now needs to have
4339 the bytes inside it modified to conform to the new size There is UGLY
4340 MAGIC here. ..
4341 */
4342 static void
4343 md_convert_frag_1 (fragP)
4344 register fragS *fragP;
4345 {
4346 long disp;
4347 fixS *fixP;
4348
4349 /* Address in object code of the displacement. */
4350 register int object_address = fragP->fr_fix + fragP->fr_address;
4351
4352 /* Address in gas core of the place to store the displacement. */
4353 /* This convinces the native rs6000 compiler to generate the code we
4354 want. */
4355 register char *buffer_address = fragP->fr_literal;
4356 buffer_address += fragP->fr_fix;
4357 /* end ibm compiler workaround */
4358
4359 /* The displacement of the address, from current location. */
4360 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4361 disp = (disp + fragP->fr_offset) - object_address;
4362
4363 #ifdef BFD_ASSEMBLER
4364 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4365 #endif
4366
4367 switch (fragP->fr_subtype)
4368 {
4369 case TAB (BRANCHBWL, BYTE):
4370 case TAB (BRABSJUNC, BYTE):
4371 case TAB (BRABSJCOND, BYTE):
4372 case TAB (BRANCHBW, BYTE):
4373 know (issbyte (disp));
4374 if (disp == 0)
4375 as_bad (_("short branch with zero offset: use :w"));
4376 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4377 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4378 fixP->fx_pcrel_adjust = -1;
4379 break;
4380 case TAB (BRANCHBWL, SHORT):
4381 case TAB (BRABSJUNC, SHORT):
4382 case TAB (BRABSJCOND, SHORT):
4383 case TAB (BRANCHBW, SHORT):
4384 fragP->fr_opcode[1] = 0x00;
4385 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4386 1, RELAX_RELOC_PC16);
4387 fragP->fr_fix += 2;
4388 break;
4389 case TAB (BRANCHBWL, LONG):
4390 fragP->fr_opcode[1] = (char) 0xFF;
4391 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4392 1, RELAX_RELOC_PC32);
4393 fragP->fr_fix += 4;
4394 break;
4395 case TAB (BRABSJUNC, LONG):
4396 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4397 {
4398 fragP->fr_opcode[0] = 0x4E;
4399 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4400 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4401 0, RELAX_RELOC_ABS32);
4402 fragP->fr_fix += 4;
4403 }
4404 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4405 {
4406 fragP->fr_opcode[0] = 0x4E;
4407 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4408 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4409 0, RELAX_RELOC_ABS32);
4410 fragP->fr_fix += 4;
4411 }
4412 else
4413 {
4414 /* This cannot happen, because jbsr and jbra are the only two
4415 unconditional branches. */
4416 abort ();
4417 }
4418 break;
4419 case TAB (BRABSJCOND, LONG):
4420 /* Only Bcc 68000 instructions can come here. */
4421 /* Change bcc into b!cc/jmp absl long. */
4422
4423 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4424 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4425
4426 /* JF: these used to be fr_opcode[2,3], but they may be in a
4427 different frag, in which case refering to them is a no-no.
4428 Only fr_opcode[0,1] are guaranteed to work. */
4429 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4430 *buffer_address++ = (char) 0xf9;
4431 fragP->fr_fix += 2; /* account for jmp instruction */
4432 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4433 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4434 fragP->fr_fix += 4;
4435 break;
4436 case TAB (FBRANCH, SHORT):
4437 know ((fragP->fr_opcode[1] & 0x40) == 0);
4438 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4439 1, RELAX_RELOC_PC16);
4440 fragP->fr_fix += 2;
4441 break;
4442 case TAB (FBRANCH, LONG):
4443 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4444 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4445 1, RELAX_RELOC_PC32);
4446 fragP->fr_fix += 4;
4447 break;
4448 case TAB (DBCCLBR, SHORT):
4449 case TAB (DBCCABSJ, SHORT):
4450 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4451 1, RELAX_RELOC_PC16);
4452 fragP->fr_fix += 2;
4453 break;
4454 case TAB (DBCCLBR, LONG):
4455 /* only DBcc instructions can come here */
4456 /* Change dbcc into dbcc/bral. */
4457
4458 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4459 *buffer_address++ = 0x00; /* branch offset = 4 */
4460 *buffer_address++ = 0x04;
4461 *buffer_address++ = 0x60; /* put in bra pc+6 */
4462 *buffer_address++ = 0x06;
4463 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4464 *buffer_address++ = (char) 0xff;
4465
4466 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4467 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4468 RELAX_RELOC_PC32);
4469 fragP->fr_fix += 4;
4470 break;
4471 case TAB (DBCCABSJ, LONG):
4472 /* only DBcc instructions can come here */
4473 /* Change dbcc into dbcc/jmp. */
4474
4475 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4476 *buffer_address++ = 0x00; /* branch offset = 4 */
4477 *buffer_address++ = 0x04;
4478 *buffer_address++ = 0x60; /* put in bra pc+6 */
4479 *buffer_address++ = 0x06;
4480 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4481 *buffer_address++ = (char) 0xf9;
4482
4483 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4484 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4485 RELAX_RELOC_ABS32);
4486 fragP->fr_fix += 4;
4487 break;
4488 case TAB (PCREL1632, SHORT):
4489 fragP->fr_opcode[1] &= ~0x3F;
4490 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4491 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4492 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4493 fragP->fr_fix += 2;
4494 break;
4495 case TAB (PCREL1632, LONG):
4496 /* Already set to mode 7.3; this indicates: PC indirect with
4497 suppressed index, 32-bit displacement. */
4498 *buffer_address++ = 0x01;
4499 *buffer_address++ = 0x70;
4500 fragP->fr_fix += 2;
4501 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4502 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4503 fixP->fx_pcrel_adjust = 2;
4504 fragP->fr_fix += 4;
4505 break;
4506 case TAB (PCINDEX, BYTE):
4507 assert (fragP->fr_fix >= 2);
4508 buffer_address[-2] &= ~1;
4509 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4510 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4511 fixP->fx_pcrel_adjust = 1;
4512 break;
4513 case TAB (PCINDEX, SHORT):
4514 assert (fragP->fr_fix >= 2);
4515 buffer_address[-2] |= 0x1;
4516 buffer_address[-1] = 0x20;
4517 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4518 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4519 fixP->fx_pcrel_adjust = 2;
4520 fragP->fr_fix += 2;
4521 break;
4522 case TAB (PCINDEX, LONG):
4523 assert (fragP->fr_fix >= 2);
4524 buffer_address[-2] |= 0x1;
4525 buffer_address[-1] = 0x30;
4526 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4527 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4528 fixP->fx_pcrel_adjust = 2;
4529 fragP->fr_fix += 4;
4530 break;
4531 case TAB (ABSTOPCREL, SHORT):
4532 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4533 1, RELAX_RELOC_PC16);
4534 fragP->fr_fix += 2;
4535 break;
4536 case TAB (ABSTOPCREL, LONG):
4537 /* The thing to do here is force it to ABSOLUTE LONG, since
4538 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4539 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4540 abort ();
4541 fragP->fr_opcode[1] &= ~0x3F;
4542 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4543 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4544 0, RELAX_RELOC_ABS32);
4545 fragP->fr_fix += 4;
4546 break;
4547 }
4548 }
4549
4550 #ifndef BFD_ASSEMBLER
4551
4552 void
4553 md_convert_frag (headers, sec, fragP)
4554 object_headers *headers ATTRIBUTE_UNUSED;
4555 segT sec ATTRIBUTE_UNUSED;
4556 fragS *fragP;
4557 {
4558 md_convert_frag_1 (fragP);
4559 }
4560
4561 #else
4562
4563 void
4564 md_convert_frag (abfd, sec, fragP)
4565 bfd *abfd ATTRIBUTE_UNUSED;
4566 segT sec ATTRIBUTE_UNUSED;
4567 fragS *fragP;
4568 {
4569 md_convert_frag_1 (fragP);
4570 }
4571 #endif
4572
4573 /* Force truly undefined symbols to their maximum size, and generally set up
4574 the frag list to be relaxed
4575 */
4576 int
4577 md_estimate_size_before_relax (fragP, segment)
4578 register fragS *fragP;
4579 segT segment;
4580 {
4581 int old_fix;
4582
4583 old_fix = fragP->fr_fix;
4584
4585 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4586 switch (fragP->fr_subtype)
4587 {
4588 case TAB (BRANCHBWL, SZ_UNDEF):
4589 case TAB (BRABSJUNC, SZ_UNDEF):
4590 {
4591 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4592 && relaxable_symbol (fragP->fr_symbol))
4593 {
4594 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4595 }
4596 else if (flag_short_refs)
4597 {
4598 /* Symbol is undefined and we want short ref. */
4599 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4600 fragP->fr_var += 2;
4601 }
4602 else
4603 {
4604 /* Symbol is still undefined. Make it LONG. */
4605 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4606 fragP->fr_var += 4;
4607 }
4608 break;
4609 }
4610
4611 case TAB (BRABSJCOND, SZ_UNDEF):
4612 {
4613 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4614 && relaxable_symbol (fragP->fr_symbol))
4615 {
4616 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4617 }
4618 else if (flag_short_refs)
4619 {
4620 /* Symbol is undefined and we want short ref. */
4621 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4622 fragP->fr_var += 2;
4623 }
4624 else
4625 {
4626 /* Symbol is still undefined. Make it LONG. */
4627 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4628 fragP->fr_var += 6;
4629 }
4630 break;
4631 }
4632
4633 case TAB (BRANCHBW, SZ_UNDEF):
4634 {
4635 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4636 && relaxable_symbol (fragP->fr_symbol))
4637 {
4638 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4639 }
4640 else
4641 {
4642 /* Symbol is undefined and we don't have long branches. */
4643 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4644 fragP->fr_var += 2;
4645 }
4646 break;
4647 }
4648
4649 case TAB (FBRANCH, SZ_UNDEF):
4650 {
4651 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4652 && relaxable_symbol (fragP->fr_symbol))
4653 || flag_short_refs)
4654 {
4655 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4656 fragP->fr_var += 2;
4657 }
4658 else
4659 {
4660 fragP->fr_subtype = TAB (FBRANCH, LONG);
4661 fragP->fr_var += 4;
4662 }
4663 break;
4664 }
4665
4666 case TAB (DBCCLBR, SZ_UNDEF):
4667 case TAB (DBCCABSJ, SZ_UNDEF):
4668 {
4669 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4670 && relaxable_symbol (fragP->fr_symbol))
4671 || flag_short_refs)
4672 {
4673 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4674 fragP->fr_var += 2;
4675 }
4676 else
4677 {
4678 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4679 fragP->fr_var += 10;
4680 }
4681 break;
4682 }
4683
4684 case TAB (PCREL1632, SZ_UNDEF):
4685 {
4686 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4687 && relaxable_symbol (fragP->fr_symbol))
4688 || flag_short_refs)
4689 {
4690 fragP->fr_subtype = TAB (PCREL1632, SHORT);
4691 fragP->fr_var += 2;
4692 }
4693 else
4694 {
4695 fragP->fr_subtype = TAB (PCREL1632, LONG);
4696 fragP->fr_var += 6;
4697 }
4698 break;
4699 }
4700
4701 case TAB (PCINDEX, SZ_UNDEF):
4702 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4703 && relaxable_symbol (fragP->fr_symbol)))
4704 {
4705 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4706 }
4707 else
4708 {
4709 fragP->fr_subtype = TAB (PCINDEX, LONG);
4710 fragP->fr_var += 4;
4711 }
4712 break;
4713
4714 case TAB (ABSTOPCREL, SZ_UNDEF):
4715 {
4716 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4717 && relaxable_symbol (fragP->fr_symbol)))
4718 {
4719 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4720 fragP->fr_var += 2;
4721 }
4722 else
4723 {
4724 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4725 fragP->fr_var += 4;
4726 }
4727 break;
4728 }
4729
4730 default:
4731 break;
4732 }
4733
4734 /* Now that SZ_UNDEF are taken care of, check others. */
4735 switch (fragP->fr_subtype)
4736 {
4737 case TAB (BRANCHBWL, BYTE):
4738 case TAB (BRABSJUNC, BYTE):
4739 case TAB (BRABSJCOND, BYTE):
4740 case TAB (BRANCHBW, BYTE):
4741 /* We can't do a short jump to the next instruction, so in that
4742 case we force word mode. At this point S_GET_VALUE should
4743 return the offset of the symbol within its frag. If the
4744 symbol is at the start of a frag, and it is the next frag
4745 with any data in it (usually this is just the next frag, but
4746 assembler listings may introduce empty frags), we must use
4747 word mode. */
4748 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4749 {
4750 fragS *stop;
4751 fragS *l;
4752
4753 stop = symbol_get_frag (fragP->fr_symbol);
4754 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4755 if (l->fr_fix + l->fr_var != 0)
4756 break;
4757 if (l == stop)
4758 {
4759 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4760 fragP->fr_var += 2;
4761 }
4762 }
4763 break;
4764 default:
4765 break;
4766 }
4767 return fragP->fr_var + fragP->fr_fix - old_fix;
4768 }
4769
4770 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4771 /* the bit-field entries in the relocation_info struct plays hell
4772 with the byte-order problems of cross-assembly. So as a hack,
4773 I added this mach. dependent ri twiddler. Ugly, but it gets
4774 you there. -KWK */
4775 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4776 are symbolnum, most sig. byte first. Last byte is broken up with
4777 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4778 nibble as nuthin. (on Sun 3 at least) */
4779 /* Translate the internal relocation information into target-specific
4780 format. */
4781 #ifdef comment
4782 void
4783 md_ri_to_chars (the_bytes, ri)
4784 char *the_bytes;
4785 struct reloc_info_generic *ri;
4786 {
4787 /* this is easy */
4788 md_number_to_chars (the_bytes, ri->r_address, 4);
4789 /* now the fun stuff */
4790 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4791 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4792 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4793 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4794 ((ri->r_extern << 4) & 0x10));
4795 }
4796
4797 #endif /* comment */
4798
4799 #ifndef BFD_ASSEMBLER
4800 void
4801 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4802 char *where;
4803 fixS *fixP;
4804 relax_addressT segment_address_in_file;
4805 {
4806 /*
4807 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4808 * Out: GNU LD relocation length code: 0, 1, or 2.
4809 */
4810
4811 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4812 long r_symbolnum;
4813
4814 know (fixP->fx_addsy != NULL);
4815
4816 md_number_to_chars (where,
4817 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4818 4);
4819
4820 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4821 ? S_GET_TYPE (fixP->fx_addsy)
4822 : fixP->fx_addsy->sy_number);
4823
4824 where[4] = (r_symbolnum >> 16) & 0x0ff;
4825 where[5] = (r_symbolnum >> 8) & 0x0ff;
4826 where[6] = r_symbolnum & 0x0ff;
4827 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4828 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4829 }
4830 #endif
4831
4832 #endif /* OBJ_AOUT or OBJ_BOUT */
4833
4834 #ifndef WORKING_DOT_WORD
4835 CONST int md_short_jump_size = 4;
4836 CONST int md_long_jump_size = 6;
4837
4838 void
4839 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4840 char *ptr;
4841 addressT from_addr, to_addr;
4842 fragS *frag ATTRIBUTE_UNUSED;
4843 symbolS *to_symbol ATTRIBUTE_UNUSED;
4844 {
4845 valueT offset;
4846
4847 offset = to_addr - (from_addr + 2);
4848
4849 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4850 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4851 }
4852
4853 void
4854 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4855 char *ptr;
4856 addressT from_addr, to_addr;
4857 fragS *frag;
4858 symbolS *to_symbol;
4859 {
4860 valueT offset;
4861
4862 if (!HAVE_LONG_BRANCH(current_architecture))
4863 {
4864 offset = to_addr - S_GET_VALUE (to_symbol);
4865 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4866 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4867 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4868 0, NO_RELOC);
4869 }
4870 else
4871 {
4872 offset = to_addr - (from_addr + 2);
4873 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4874 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4875 }
4876 }
4877
4878 #endif
4879
4880 /* Different values of OK tell what its OK to return. Things that
4881 aren't OK are an error (what a shock, no?)
4882
4883 0: Everything is OK
4884 10: Absolute 1:8 only
4885 20: Absolute 0:7 only
4886 30: absolute 0:15 only
4887 40: Absolute 0:31 only
4888 50: absolute 0:127 only
4889 55: absolute -64:63 only
4890 60: absolute -128:127 only
4891 70: absolute 0:4095 only
4892 80: No bignums
4893
4894 */
4895
4896 static int
4897 get_num (exp, ok)
4898 struct m68k_exp *exp;
4899 int ok;
4900 {
4901 if (exp->exp.X_op == O_absent)
4902 {
4903 /* Do the same thing the VAX asm does */
4904 op (exp) = O_constant;
4905 adds (exp) = 0;
4906 subs (exp) = 0;
4907 offs (exp) = 0;
4908 if (ok == 10)
4909 {
4910 as_warn (_("expression out of range: defaulting to 1"));
4911 offs (exp) = 1;
4912 }
4913 }
4914 else if (exp->exp.X_op == O_constant)
4915 {
4916 switch (ok)
4917 {
4918 case 10:
4919 if (offs (exp) < 1 || offs (exp) > 8)
4920 {
4921 as_warn (_("expression out of range: defaulting to 1"));
4922 offs (exp) = 1;
4923 }
4924 break;
4925 case 20:
4926 if (offs (exp) < 0 || offs (exp) > 7)
4927 goto outrange;
4928 break;
4929 case 30:
4930 if (offs (exp) < 0 || offs (exp) > 15)
4931 goto outrange;
4932 break;
4933 case 40:
4934 if (offs (exp) < 0 || offs (exp) > 32)
4935 goto outrange;
4936 break;
4937 case 50:
4938 if (offs (exp) < 0 || offs (exp) > 127)
4939 goto outrange;
4940 break;
4941 case 55:
4942 if (offs (exp) < -64 || offs (exp) > 63)
4943 goto outrange;
4944 break;
4945 case 60:
4946 if (offs (exp) < -128 || offs (exp) > 127)
4947 goto outrange;
4948 break;
4949 case 70:
4950 if (offs (exp) < 0 || offs (exp) > 4095)
4951 {
4952 outrange:
4953 as_warn (_("expression out of range: defaulting to 0"));
4954 offs (exp) = 0;
4955 }
4956 break;
4957 default:
4958 break;
4959 }
4960 }
4961 else if (exp->exp.X_op == O_big)
4962 {
4963 if (offs (exp) <= 0 /* flonum */
4964 && (ok == 80 /* no bignums */
4965 || (ok > 10 /* small-int ranges including 0 ok */
4966 /* If we have a flonum zero, a zero integer should
4967 do as well (e.g., in moveq). */
4968 && generic_floating_point_number.exponent == 0
4969 && generic_floating_point_number.low[0] == 0)))
4970 {
4971 /* HACK! Turn it into a long */
4972 LITTLENUM_TYPE words[6];
4973
4974 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4975 op (exp) = O_constant;
4976 adds (exp) = 0;
4977 subs (exp) = 0;
4978 offs (exp) = words[1] | (words[0] << 16);
4979 }
4980 else if (ok != 0)
4981 {
4982 op (exp) = O_constant;
4983 adds (exp) = 0;
4984 subs (exp) = 0;
4985 offs (exp) = (ok == 10) ? 1 : 0;
4986 as_warn (_("Can't deal with expression; defaulting to %ld"),
4987 offs (exp));
4988 }
4989 }
4990 else
4991 {
4992 if (ok >= 10 && ok <= 70)
4993 {
4994 op (exp) = O_constant;
4995 adds (exp) = 0;
4996 subs (exp) = 0;
4997 offs (exp) = (ok == 10) ? 1 : 0;
4998 as_warn (_("Can't deal with expression; defaulting to %ld"),
4999 offs (exp));
5000 }
5001 }
5002
5003 if (exp->size != SIZE_UNSPEC)
5004 {
5005 switch (exp->size)
5006 {
5007 case SIZE_UNSPEC:
5008 case SIZE_LONG:
5009 break;
5010 case SIZE_BYTE:
5011 if (!isbyte (offs (exp)))
5012 as_warn (_("expression doesn't fit in BYTE"));
5013 break;
5014 case SIZE_WORD:
5015 if (!isword (offs (exp)))
5016 as_warn (_("expression doesn't fit in WORD"));
5017 break;
5018 }
5019 }
5020
5021 return offs (exp);
5022 }
5023
5024 /* These are the back-ends for the various machine dependent pseudo-ops. */
5025
5026 static void
5027 s_data1 (ignore)
5028 int ignore ATTRIBUTE_UNUSED;
5029 {
5030 subseg_set (data_section, 1);
5031 demand_empty_rest_of_line ();
5032 }
5033
5034 static void
5035 s_data2 (ignore)
5036 int ignore ATTRIBUTE_UNUSED;
5037 {
5038 subseg_set (data_section, 2);
5039 demand_empty_rest_of_line ();
5040 }
5041
5042 static void
5043 s_bss (ignore)
5044 int ignore ATTRIBUTE_UNUSED;
5045 {
5046 /* We don't support putting frags in the BSS segment, we fake it
5047 by marking in_bss, then looking at s_skip for clues. */
5048
5049 subseg_set (bss_section, 0);
5050 demand_empty_rest_of_line ();
5051 }
5052
5053 static void
5054 s_even (ignore)
5055 int ignore ATTRIBUTE_UNUSED;
5056 {
5057 register int temp;
5058 register long temp_fill;
5059
5060 temp = 1; /* JF should be 2? */
5061 temp_fill = get_absolute_expression ();
5062 if (!need_pass_2) /* Never make frag if expect extra pass. */
5063 frag_align (temp, (int) temp_fill, 0);
5064 demand_empty_rest_of_line ();
5065 record_alignment (now_seg, temp);
5066 }
5067
5068 static void
5069 s_proc (ignore)
5070 int ignore ATTRIBUTE_UNUSED;
5071 {
5072 demand_empty_rest_of_line ();
5073 }
5074 \f
5075 /* Pseudo-ops handled for MRI compatibility. */
5076
5077 /* This function returns non-zero if the argument is a conditional
5078 pseudo-op. This is called when checking whether a pending
5079 alignment is needed. */
5080
5081 int
5082 m68k_conditional_pseudoop (pop)
5083 pseudo_typeS *pop;
5084 {
5085 return (pop->poc_handler == s_mri_if
5086 || pop->poc_handler == s_mri_else);
5087 }
5088
5089 /* Handle an MRI style chip specification. */
5090
5091 static void
5092 mri_chip ()
5093 {
5094 char *s;
5095 char c;
5096 int i;
5097
5098 s = input_line_pointer;
5099 /* We can't use get_symbol_end since the processor names are not proper
5100 symbols. */
5101 while (is_part_of_name (c = *input_line_pointer++))
5102 ;
5103 *--input_line_pointer = 0;
5104 for (i = 0; i < n_archs; i++)
5105 if (strcasecmp (s, archs[i].name) == 0)
5106 break;
5107 if (i >= n_archs)
5108 {
5109 as_bad (_("%s: unrecognized processor name"), s);
5110 *input_line_pointer = c;
5111 ignore_rest_of_line ();
5112 return;
5113 }
5114 *input_line_pointer = c;
5115
5116 if (*input_line_pointer == '/')
5117 current_architecture = 0;
5118 else
5119 current_architecture &= m68881 | m68851;
5120 current_architecture |= archs[i].arch;
5121
5122 while (*input_line_pointer == '/')
5123 {
5124 ++input_line_pointer;
5125 s = input_line_pointer;
5126 /* We can't use get_symbol_end since the processor names are not
5127 proper symbols. */
5128 while (is_part_of_name (c = *input_line_pointer++))
5129 ;
5130 *--input_line_pointer = 0;
5131 if (strcmp (s, "68881") == 0)
5132 current_architecture |= m68881;
5133 else if (strcmp (s, "68851") == 0)
5134 current_architecture |= m68851;
5135 *input_line_pointer = c;
5136 }
5137
5138 /* Update info about available control registers. */
5139 select_control_regs ();
5140 }
5141
5142 /* The MRI CHIP pseudo-op. */
5143
5144 static void
5145 s_chip (ignore)
5146 int ignore ATTRIBUTE_UNUSED;
5147 {
5148 char *stop = NULL;
5149 char stopc;
5150
5151 if (flag_mri)
5152 stop = mri_comment_field (&stopc);
5153 mri_chip ();
5154 if (flag_mri)
5155 mri_comment_end (stop, stopc);
5156 demand_empty_rest_of_line ();
5157 }
5158
5159 /* The MRI FOPT pseudo-op. */
5160
5161 static void
5162 s_fopt (ignore)
5163 int ignore ATTRIBUTE_UNUSED;
5164 {
5165 SKIP_WHITESPACE ();
5166
5167 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5168 {
5169 int temp;
5170
5171 input_line_pointer += 3;
5172 temp = get_absolute_expression ();
5173 if (temp < 0 || temp > 7)
5174 as_bad (_("bad coprocessor id"));
5175 else
5176 m68k_float_copnum = COP0 + temp;
5177 }
5178 else
5179 {
5180 as_bad (_("unrecognized fopt option"));
5181 ignore_rest_of_line ();
5182 return;
5183 }
5184
5185 demand_empty_rest_of_line ();
5186 }
5187
5188 /* The structure used to handle the MRI OPT pseudo-op. */
5189
5190 struct opt_action
5191 {
5192 /* The name of the option. */
5193 const char *name;
5194
5195 /* If this is not NULL, just call this function. The first argument
5196 is the ARG field of this structure, the second argument is
5197 whether the option was negated. */
5198 void (*pfn) PARAMS ((int arg, int on));
5199
5200 /* If this is not NULL, and the PFN field is NULL, set the variable
5201 this points to. Set it to the ARG field if the option was not
5202 negated, and the NOTARG field otherwise. */
5203 int *pvar;
5204
5205 /* The value to pass to PFN or to assign to *PVAR. */
5206 int arg;
5207
5208 /* The value to assign to *PVAR if the option is negated. If PFN is
5209 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5210 the option may not be negated. */
5211 int notarg;
5212 };
5213
5214 /* The table used to handle the MRI OPT pseudo-op. */
5215
5216 static void skip_to_comma PARAMS ((int, int));
5217 static void opt_nest PARAMS ((int, int));
5218 static void opt_chip PARAMS ((int, int));
5219 static void opt_list PARAMS ((int, int));
5220 static void opt_list_symbols PARAMS ((int, int));
5221
5222 static const struct opt_action opt_table[] =
5223 {
5224 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5225
5226 /* We do relaxing, so there is little use for these options. */
5227 { "b", 0, 0, 0, 0 },
5228 { "brs", 0, 0, 0, 0 },
5229 { "brb", 0, 0, 0, 0 },
5230 { "brl", 0, 0, 0, 0 },
5231 { "brw", 0, 0, 0, 0 },
5232
5233 { "c", 0, 0, 0, 0 },
5234 { "cex", 0, 0, 0, 0 },
5235 { "case", 0, &symbols_case_sensitive, 1, 0 },
5236 { "cl", 0, 0, 0, 0 },
5237 { "cre", 0, 0, 0, 0 },
5238 { "d", 0, &flag_keep_locals, 1, 0 },
5239 { "e", 0, 0, 0, 0 },
5240 { "f", 0, &flag_short_refs, 1, 0 },
5241 { "frs", 0, &flag_short_refs, 1, 0 },
5242 { "frl", 0, &flag_short_refs, 0, 1 },
5243 { "g", 0, 0, 0, 0 },
5244 { "i", 0, 0, 0, 0 },
5245 { "m", 0, 0, 0, 0 },
5246 { "mex", 0, 0, 0, 0 },
5247 { "mc", 0, 0, 0, 0 },
5248 { "md", 0, 0, 0, 0 },
5249 { "nest", opt_nest, 0, 0, 0 },
5250 { "next", skip_to_comma, 0, 0, 0 },
5251 { "o", 0, 0, 0, 0 },
5252 { "old", 0, 0, 0, 0 },
5253 { "op", skip_to_comma, 0, 0, 0 },
5254 { "pco", 0, 0, 0, 0 },
5255 { "p", opt_chip, 0, 0, 0 },
5256 { "pcr", 0, 0, 0, 0 },
5257 { "pcs", 0, 0, 0, 0 },
5258 { "r", 0, 0, 0, 0 },
5259 { "quick", 0, &m68k_quick, 1, 0 },
5260 { "rel32", 0, &m68k_rel32, 1, 0 },
5261 { "s", opt_list, 0, 0, 0 },
5262 { "t", opt_list_symbols, 0, 0, 0 },
5263 { "w", 0, &flag_no_warnings, 0, 1 },
5264 { "x", 0, 0, 0, 0 }
5265 };
5266
5267 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5268
5269 /* The MRI OPT pseudo-op. */
5270
5271 static void
5272 s_opt (ignore)
5273 int ignore ATTRIBUTE_UNUSED;
5274 {
5275 do
5276 {
5277 int t;
5278 char *s;
5279 char c;
5280 int i;
5281 const struct opt_action *o;
5282
5283 SKIP_WHITESPACE ();
5284
5285 t = 1;
5286 if (*input_line_pointer == '-')
5287 {
5288 ++input_line_pointer;
5289 t = 0;
5290 }
5291 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5292 {
5293 input_line_pointer += 2;
5294 t = 0;
5295 }
5296
5297 s = input_line_pointer;
5298 c = get_symbol_end ();
5299
5300 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5301 {
5302 if (strcasecmp (s, o->name) == 0)
5303 {
5304 if (o->pfn)
5305 {
5306 /* Restore input_line_pointer now in case the option
5307 takes arguments. */
5308 *input_line_pointer = c;
5309 (*o->pfn) (o->arg, t);
5310 }
5311 else if (o->pvar != NULL)
5312 {
5313 if (! t && o->arg == o->notarg)
5314 as_bad (_("option `%s' may not be negated"), s);
5315 *input_line_pointer = c;
5316 *o->pvar = t ? o->arg : o->notarg;
5317 }
5318 else
5319 *input_line_pointer = c;
5320 break;
5321 }
5322 }
5323 if (i >= OPTCOUNT)
5324 {
5325 as_bad (_("option `%s' not recognized"), s);
5326 *input_line_pointer = c;
5327 }
5328 }
5329 while (*input_line_pointer++ == ',');
5330
5331 /* Move back to terminating character. */
5332 --input_line_pointer;
5333 demand_empty_rest_of_line ();
5334 }
5335
5336 /* Skip ahead to a comma. This is used for OPT options which we do
5337 not suppor tand which take arguments. */
5338
5339 static void
5340 skip_to_comma (arg, on)
5341 int arg ATTRIBUTE_UNUSED;
5342 int on ATTRIBUTE_UNUSED;
5343 {
5344 while (*input_line_pointer != ','
5345 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5346 ++input_line_pointer;
5347 }
5348
5349 /* Handle the OPT NEST=depth option. */
5350
5351 static void
5352 opt_nest (arg, on)
5353 int arg ATTRIBUTE_UNUSED;
5354 int on ATTRIBUTE_UNUSED;
5355 {
5356 if (*input_line_pointer != '=')
5357 {
5358 as_bad (_("bad format of OPT NEST=depth"));
5359 return;
5360 }
5361
5362 ++input_line_pointer;
5363 max_macro_nest = get_absolute_expression ();
5364 }
5365
5366 /* Handle the OPT P=chip option. */
5367
5368 static void
5369 opt_chip (arg, on)
5370 int arg ATTRIBUTE_UNUSED;
5371 int on ATTRIBUTE_UNUSED;
5372 {
5373 if (*input_line_pointer != '=')
5374 {
5375 /* This is just OPT P, which we do not support. */
5376 return;
5377 }
5378
5379 ++input_line_pointer;
5380 mri_chip ();
5381 }
5382
5383 /* Handle the OPT S option. */
5384
5385 static void
5386 opt_list (arg, on)
5387 int arg ATTRIBUTE_UNUSED;
5388 int on;
5389 {
5390 listing_list (on);
5391 }
5392
5393 /* Handle the OPT T option. */
5394
5395 static void
5396 opt_list_symbols (arg, on)
5397 int arg ATTRIBUTE_UNUSED;
5398 int on;
5399 {
5400 if (on)
5401 listing |= LISTING_SYMBOLS;
5402 else
5403 listing &=~ LISTING_SYMBOLS;
5404 }
5405
5406 /* Handle the MRI REG pseudo-op. */
5407
5408 static void
5409 s_reg (ignore)
5410 int ignore ATTRIBUTE_UNUSED;
5411 {
5412 char *s;
5413 int c;
5414 struct m68k_op rop;
5415 int mask;
5416 char *stop = NULL;
5417 char stopc;
5418
5419 if (line_label == NULL)
5420 {
5421 as_bad (_("missing label"));
5422 ignore_rest_of_line ();
5423 return;
5424 }
5425
5426 if (flag_mri)
5427 stop = mri_comment_field (&stopc);
5428
5429 SKIP_WHITESPACE ();
5430
5431 s = input_line_pointer;
5432 while (isalnum ((unsigned char) *input_line_pointer)
5433 #ifdef REGISTER_PREFIX
5434 || *input_line_pointer == REGISTER_PREFIX
5435 #endif
5436 || *input_line_pointer == '/'
5437 || *input_line_pointer == '-')
5438 ++input_line_pointer;
5439 c = *input_line_pointer;
5440 *input_line_pointer = '\0';
5441
5442 if (m68k_ip_op (s, &rop) != 0)
5443 {
5444 if (rop.error == NULL)
5445 as_bad (_("bad register list"));
5446 else
5447 as_bad (_("bad register list: %s"), rop.error);
5448 *input_line_pointer = c;
5449 ignore_rest_of_line ();
5450 return;
5451 }
5452
5453 *input_line_pointer = c;
5454
5455 if (rop.mode == REGLST)
5456 mask = rop.mask;
5457 else if (rop.mode == DREG)
5458 mask = 1 << (rop.reg - DATA0);
5459 else if (rop.mode == AREG)
5460 mask = 1 << (rop.reg - ADDR0 + 8);
5461 else if (rop.mode == FPREG)
5462 mask = 1 << (rop.reg - FP0 + 16);
5463 else if (rop.mode == CONTROL
5464 && rop.reg == FPI)
5465 mask = 1 << 24;
5466 else if (rop.mode == CONTROL
5467 && rop.reg == FPS)
5468 mask = 1 << 25;
5469 else if (rop.mode == CONTROL
5470 && rop.reg == FPC)
5471 mask = 1 << 26;
5472 else
5473 {
5474 as_bad (_("bad register list"));
5475 ignore_rest_of_line ();
5476 return;
5477 }
5478
5479 S_SET_SEGMENT (line_label, reg_section);
5480 S_SET_VALUE (line_label, ~mask);
5481 symbol_set_frag (line_label, &zero_address_frag);
5482
5483 if (flag_mri)
5484 mri_comment_end (stop, stopc);
5485
5486 demand_empty_rest_of_line ();
5487 }
5488
5489 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5490
5491 struct save_opts
5492 {
5493 struct save_opts *next;
5494 int abspcadd;
5495 int symbols_case_sensitive;
5496 int keep_locals;
5497 int short_refs;
5498 int architecture;
5499 int quick;
5500 int rel32;
5501 int listing;
5502 int no_warnings;
5503 /* FIXME: We don't save OPT S. */
5504 };
5505
5506 /* This variable holds the stack of saved options. */
5507
5508 static struct save_opts *save_stack;
5509
5510 /* The MRI SAVE pseudo-op. */
5511
5512 static void
5513 s_save (ignore)
5514 int ignore ATTRIBUTE_UNUSED;
5515 {
5516 struct save_opts *s;
5517
5518 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5519 s->abspcadd = m68k_abspcadd;
5520 s->symbols_case_sensitive = symbols_case_sensitive;
5521 s->keep_locals = flag_keep_locals;
5522 s->short_refs = flag_short_refs;
5523 s->architecture = current_architecture;
5524 s->quick = m68k_quick;
5525 s->rel32 = m68k_rel32;
5526 s->listing = listing;
5527 s->no_warnings = flag_no_warnings;
5528
5529 s->next = save_stack;
5530 save_stack = s;
5531
5532 demand_empty_rest_of_line ();
5533 }
5534
5535 /* The MRI RESTORE pseudo-op. */
5536
5537 static void
5538 s_restore (ignore)
5539 int ignore ATTRIBUTE_UNUSED;
5540 {
5541 struct save_opts *s;
5542
5543 if (save_stack == NULL)
5544 {
5545 as_bad (_("restore without save"));
5546 ignore_rest_of_line ();
5547 return;
5548 }
5549
5550 s = save_stack;
5551 save_stack = s->next;
5552
5553 m68k_abspcadd = s->abspcadd;
5554 symbols_case_sensitive = s->symbols_case_sensitive;
5555 flag_keep_locals = s->keep_locals;
5556 flag_short_refs = s->short_refs;
5557 current_architecture = s->architecture;
5558 m68k_quick = s->quick;
5559 m68k_rel32 = s->rel32;
5560 listing = s->listing;
5561 flag_no_warnings = s->no_warnings;
5562
5563 free (s);
5564
5565 demand_empty_rest_of_line ();
5566 }
5567
5568 /* Types of MRI structured control directives. */
5569
5570 enum mri_control_type
5571 {
5572 mri_for,
5573 mri_if,
5574 mri_repeat,
5575 mri_while
5576 };
5577
5578 /* This structure is used to stack the MRI structured control
5579 directives. */
5580
5581 struct mri_control_info
5582 {
5583 /* The directive within which this one is enclosed. */
5584 struct mri_control_info *outer;
5585
5586 /* The type of directive. */
5587 enum mri_control_type type;
5588
5589 /* Whether an ELSE has been in an IF. */
5590 int else_seen;
5591
5592 /* The add or sub statement at the end of a FOR. */
5593 char *incr;
5594
5595 /* The label of the top of a FOR or REPEAT loop. */
5596 char *top;
5597
5598 /* The label to jump to for the next iteration, or the else
5599 expression of a conditional. */
5600 char *next;
5601
5602 /* The label to jump to to break out of the loop, or the label past
5603 the end of a conditional. */
5604 char *bottom;
5605 };
5606
5607 /* The stack of MRI structured control directives. */
5608
5609 static struct mri_control_info *mri_control_stack;
5610
5611 /* The current MRI structured control directive index number, used to
5612 generate label names. */
5613
5614 static int mri_control_index;
5615
5616 /* Some function prototypes. */
5617
5618 static void mri_assemble PARAMS ((char *));
5619 static char *mri_control_label PARAMS ((void));
5620 static struct mri_control_info *push_mri_control
5621 PARAMS ((enum mri_control_type));
5622 static void pop_mri_control PARAMS ((void));
5623 static int parse_mri_condition PARAMS ((int *));
5624 static int parse_mri_control_operand
5625 PARAMS ((int *, char **, char **, char **, char **));
5626 static int swap_mri_condition PARAMS ((int));
5627 static int reverse_mri_condition PARAMS ((int));
5628 static void build_mri_control_operand
5629 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5630 const char *, int));
5631 static void parse_mri_control_expression
5632 PARAMS ((char *, int, const char *, const char *, int));
5633
5634 /* Assemble an instruction for an MRI structured control directive. */
5635
5636 static void
5637 mri_assemble (str)
5638 char *str;
5639 {
5640 char *s;
5641
5642 /* md_assemble expects the opcode to be in lower case. */
5643 for (s = str; *s != ' ' && *s != '\0'; s++)
5644 {
5645 if (isupper ((unsigned char) *s))
5646 *s = tolower ((unsigned char) *s);
5647 }
5648
5649 md_assemble (str);
5650 }
5651
5652 /* Generate a new MRI label structured control directive label name. */
5653
5654 static char *
5655 mri_control_label ()
5656 {
5657 char *n;
5658
5659 n = (char *) xmalloc (20);
5660 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5661 ++mri_control_index;
5662 return n;
5663 }
5664
5665 /* Create a new MRI structured control directive. */
5666
5667 static struct mri_control_info *
5668 push_mri_control (type)
5669 enum mri_control_type type;
5670 {
5671 struct mri_control_info *n;
5672
5673 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5674
5675 n->type = type;
5676 n->else_seen = 0;
5677 if (type == mri_if || type == mri_while)
5678 n->top = NULL;
5679 else
5680 n->top = mri_control_label ();
5681 n->next = mri_control_label ();
5682 n->bottom = mri_control_label ();
5683
5684 n->outer = mri_control_stack;
5685 mri_control_stack = n;
5686
5687 return n;
5688 }
5689
5690 /* Pop off the stack of MRI structured control directives. */
5691
5692 static void
5693 pop_mri_control ()
5694 {
5695 struct mri_control_info *n;
5696
5697 n = mri_control_stack;
5698 mri_control_stack = n->outer;
5699 if (n->top != NULL)
5700 free (n->top);
5701 free (n->next);
5702 free (n->bottom);
5703 free (n);
5704 }
5705
5706 /* Recognize a condition code in an MRI structured control expression. */
5707
5708 static int
5709 parse_mri_condition (pcc)
5710 int *pcc;
5711 {
5712 char c1, c2;
5713
5714 know (*input_line_pointer == '<');
5715
5716 ++input_line_pointer;
5717 c1 = *input_line_pointer++;
5718 c2 = *input_line_pointer++;
5719
5720 if (*input_line_pointer != '>')
5721 {
5722 as_bad (_("syntax error in structured control directive"));
5723 return 0;
5724 }
5725
5726 ++input_line_pointer;
5727 SKIP_WHITESPACE ();
5728
5729 if (isupper (c1))
5730 c1 = tolower (c1);
5731 if (isupper (c2))
5732 c2 = tolower (c2);
5733
5734 *pcc = (c1 << 8) | c2;
5735
5736 return 1;
5737 }
5738
5739 /* Parse a single operand in an MRI structured control expression. */
5740
5741 static int
5742 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5743 int *pcc;
5744 char **leftstart;
5745 char **leftstop;
5746 char **rightstart;
5747 char **rightstop;
5748 {
5749 char *s;
5750
5751 SKIP_WHITESPACE ();
5752
5753 *pcc = -1;
5754 *leftstart = NULL;
5755 *leftstop = NULL;
5756 *rightstart = NULL;
5757 *rightstop = NULL;
5758
5759 if (*input_line_pointer == '<')
5760 {
5761 /* It's just a condition code. */
5762 return parse_mri_condition (pcc);
5763 }
5764
5765 /* Look ahead for the condition code. */
5766 for (s = input_line_pointer; *s != '\0'; ++s)
5767 {
5768 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5769 break;
5770 }
5771 if (*s == '\0')
5772 {
5773 as_bad (_("missing condition code in structured control directive"));
5774 return 0;
5775 }
5776
5777 *leftstart = input_line_pointer;
5778 *leftstop = s;
5779 if (*leftstop > *leftstart
5780 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5781 --*leftstop;
5782
5783 input_line_pointer = s;
5784 if (! parse_mri_condition (pcc))
5785 return 0;
5786
5787 /* Look ahead for AND or OR or end of line. */
5788 for (s = input_line_pointer; *s != '\0'; ++s)
5789 {
5790 if ((strncasecmp (s, "AND", 3) == 0
5791 && (s[3] == '.' || ! is_part_of_name (s[3])))
5792 || (strncasecmp (s, "OR", 2) == 0
5793 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5794 break;
5795 }
5796
5797 *rightstart = input_line_pointer;
5798 *rightstop = s;
5799 if (*rightstop > *rightstart
5800 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5801 --*rightstop;
5802
5803 input_line_pointer = s;
5804
5805 return 1;
5806 }
5807
5808 #define MCC(b1, b2) (((b1) << 8) | (b2))
5809
5810 /* Swap the sense of a condition. This changes the condition so that
5811 it generates the same result when the operands are swapped. */
5812
5813 static int
5814 swap_mri_condition (cc)
5815 int cc;
5816 {
5817 switch (cc)
5818 {
5819 case MCC ('h', 'i'): return MCC ('c', 's');
5820 case MCC ('l', 's'): return MCC ('c', 'c');
5821 case MCC ('c', 'c'): return MCC ('l', 's');
5822 case MCC ('c', 's'): return MCC ('h', 'i');
5823 case MCC ('p', 'l'): return MCC ('m', 'i');
5824 case MCC ('m', 'i'): return MCC ('p', 'l');
5825 case MCC ('g', 'e'): return MCC ('l', 'e');
5826 case MCC ('l', 't'): return MCC ('g', 't');
5827 case MCC ('g', 't'): return MCC ('l', 't');
5828 case MCC ('l', 'e'): return MCC ('g', 'e');
5829 }
5830 return cc;
5831 }
5832
5833 /* Reverse the sense of a condition. */
5834
5835 static int
5836 reverse_mri_condition (cc)
5837 int cc;
5838 {
5839 switch (cc)
5840 {
5841 case MCC ('h', 'i'): return MCC ('l', 's');
5842 case MCC ('l', 's'): return MCC ('h', 'i');
5843 case MCC ('c', 'c'): return MCC ('c', 's');
5844 case MCC ('c', 's'): return MCC ('c', 'c');
5845 case MCC ('n', 'e'): return MCC ('e', 'q');
5846 case MCC ('e', 'q'): return MCC ('n', 'e');
5847 case MCC ('v', 'c'): return MCC ('v', 's');
5848 case MCC ('v', 's'): return MCC ('v', 'c');
5849 case MCC ('p', 'l'): return MCC ('m', 'i');
5850 case MCC ('m', 'i'): return MCC ('p', 'l');
5851 case MCC ('g', 'e'): return MCC ('l', 't');
5852 case MCC ('l', 't'): return MCC ('g', 'e');
5853 case MCC ('g', 't'): return MCC ('l', 'e');
5854 case MCC ('l', 'e'): return MCC ('g', 't');
5855 }
5856 return cc;
5857 }
5858
5859 /* Build an MRI structured control expression. This generates test
5860 and branch instructions. It goes to TRUELAB if the condition is
5861 true, and to FALSELAB if the condition is false. Exactly one of
5862 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5863 is the size qualifier for the expression. EXTENT is the size to
5864 use for the branch. */
5865
5866 static void
5867 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5868 rightstop, truelab, falselab, extent)
5869 int qual;
5870 int cc;
5871 char *leftstart;
5872 char *leftstop;
5873 char *rightstart;
5874 char *rightstop;
5875 const char *truelab;
5876 const char *falselab;
5877 int extent;
5878 {
5879 char *buf;
5880 char *s;
5881
5882 if (leftstart != NULL)
5883 {
5884 struct m68k_op leftop, rightop;
5885 char c;
5886
5887 /* Swap the compare operands, if necessary, to produce a legal
5888 m68k compare instruction. Comparing a register operand with
5889 a non-register operand requires the register to be on the
5890 right (cmp, cmpa). Comparing an immediate value with
5891 anything requires the immediate value to be on the left
5892 (cmpi). */
5893
5894 c = *leftstop;
5895 *leftstop = '\0';
5896 (void) m68k_ip_op (leftstart, &leftop);
5897 *leftstop = c;
5898
5899 c = *rightstop;
5900 *rightstop = '\0';
5901 (void) m68k_ip_op (rightstart, &rightop);
5902 *rightstop = c;
5903
5904 if (rightop.mode == IMMED
5905 || ((leftop.mode == DREG || leftop.mode == AREG)
5906 && (rightop.mode != DREG && rightop.mode != AREG)))
5907 {
5908 char *temp;
5909
5910 cc = swap_mri_condition (cc);
5911 temp = leftstart;
5912 leftstart = rightstart;
5913 rightstart = temp;
5914 temp = leftstop;
5915 leftstop = rightstop;
5916 rightstop = temp;
5917 }
5918 }
5919
5920 if (truelab == NULL)
5921 {
5922 cc = reverse_mri_condition (cc);
5923 truelab = falselab;
5924 }
5925
5926 if (leftstart != NULL)
5927 {
5928 buf = (char *) xmalloc (20
5929 + (leftstop - leftstart)
5930 + (rightstop - rightstart));
5931 s = buf;
5932 *s++ = 'c';
5933 *s++ = 'm';
5934 *s++ = 'p';
5935 if (qual != '\0')
5936 *s++ = qual;
5937 *s++ = ' ';
5938 memcpy (s, leftstart, leftstop - leftstart);
5939 s += leftstop - leftstart;
5940 *s++ = ',';
5941 memcpy (s, rightstart, rightstop - rightstart);
5942 s += rightstop - rightstart;
5943 *s = '\0';
5944 mri_assemble (buf);
5945 free (buf);
5946 }
5947
5948 buf = (char *) xmalloc (20 + strlen (truelab));
5949 s = buf;
5950 *s++ = 'b';
5951 *s++ = cc >> 8;
5952 *s++ = cc & 0xff;
5953 if (extent != '\0')
5954 *s++ = extent;
5955 *s++ = ' ';
5956 strcpy (s, truelab);
5957 mri_assemble (buf);
5958 free (buf);
5959 }
5960
5961 /* Parse an MRI structured control expression. This generates test
5962 and branch instructions. STOP is where the expression ends. It
5963 goes to TRUELAB if the condition is true, and to FALSELAB if the
5964 condition is false. Exactly one of TRUELAB and FALSELAB will be
5965 NULL, meaning to fall through. QUAL is the size qualifier for the
5966 expression. EXTENT is the size to use for the branch. */
5967
5968 static void
5969 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5970 char *stop;
5971 int qual;
5972 const char *truelab;
5973 const char *falselab;
5974 int extent;
5975 {
5976 int c;
5977 int cc;
5978 char *leftstart;
5979 char *leftstop;
5980 char *rightstart;
5981 char *rightstop;
5982
5983 c = *stop;
5984 *stop = '\0';
5985
5986 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5987 &rightstart, &rightstop))
5988 {
5989 *stop = c;
5990 return;
5991 }
5992
5993 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5994 {
5995 const char *flab;
5996
5997 if (falselab != NULL)
5998 flab = falselab;
5999 else
6000 flab = mri_control_label ();
6001
6002 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6003 rightstop, (const char *) NULL, flab, extent);
6004
6005 input_line_pointer += 3;
6006 if (*input_line_pointer != '.'
6007 || input_line_pointer[1] == '\0')
6008 qual = '\0';
6009 else
6010 {
6011 qual = input_line_pointer[1];
6012 input_line_pointer += 2;
6013 }
6014
6015 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6016 &rightstart, &rightstop))
6017 {
6018 *stop = c;
6019 return;
6020 }
6021
6022 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6023 rightstop, truelab, falselab, extent);
6024
6025 if (falselab == NULL)
6026 colon (flab);
6027 }
6028 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6029 {
6030 const char *tlab;
6031
6032 if (truelab != NULL)
6033 tlab = truelab;
6034 else
6035 tlab = mri_control_label ();
6036
6037 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6038 rightstop, tlab, (const char *) NULL, extent);
6039
6040 input_line_pointer += 2;
6041 if (*input_line_pointer != '.'
6042 || input_line_pointer[1] == '\0')
6043 qual = '\0';
6044 else
6045 {
6046 qual = input_line_pointer[1];
6047 input_line_pointer += 2;
6048 }
6049
6050 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6051 &rightstart, &rightstop))
6052 {
6053 *stop = c;
6054 return;
6055 }
6056
6057 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6058 rightstop, truelab, falselab, extent);
6059
6060 if (truelab == NULL)
6061 colon (tlab);
6062 }
6063 else
6064 {
6065 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6066 rightstop, truelab, falselab, extent);
6067 }
6068
6069 *stop = c;
6070 if (input_line_pointer != stop)
6071 as_bad (_("syntax error in structured control directive"));
6072 }
6073
6074 /* Handle the MRI IF pseudo-op. This may be a structured control
6075 directive, or it may be a regular assembler conditional, depending
6076 on its operands. */
6077
6078 static void
6079 s_mri_if (qual)
6080 int qual;
6081 {
6082 char *s;
6083 int c;
6084 struct mri_control_info *n;
6085
6086 /* A structured control directive must end with THEN with an
6087 optional qualifier. */
6088 s = input_line_pointer;
6089 while (! is_end_of_line[(unsigned char) *s]
6090 && (! flag_mri || *s != '*'))
6091 ++s;
6092 --s;
6093 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6094 --s;
6095
6096 if (s - input_line_pointer > 1
6097 && s[-1] == '.')
6098 s -= 2;
6099
6100 if (s - input_line_pointer < 3
6101 || strncasecmp (s - 3, "THEN", 4) != 0)
6102 {
6103 if (qual != '\0')
6104 {
6105 as_bad (_("missing then"));
6106 ignore_rest_of_line ();
6107 return;
6108 }
6109
6110 /* It's a conditional. */
6111 s_if (O_ne);
6112 return;
6113 }
6114
6115 /* Since this might be a conditional if, this pseudo-op will be
6116 called even if we are supported to be ignoring input. Double
6117 check now. Clobber *input_line_pointer so that ignore_input
6118 thinks that this is not a special pseudo-op. */
6119 c = *input_line_pointer;
6120 *input_line_pointer = 0;
6121 if (ignore_input ())
6122 {
6123 *input_line_pointer = c;
6124 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6125 ++input_line_pointer;
6126 demand_empty_rest_of_line ();
6127 return;
6128 }
6129 *input_line_pointer = c;
6130
6131 n = push_mri_control (mri_if);
6132
6133 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6134 n->next, s[1] == '.' ? s[2] : '\0');
6135
6136 if (s[1] == '.')
6137 input_line_pointer = s + 3;
6138 else
6139 input_line_pointer = s + 1;
6140
6141 if (flag_mri)
6142 {
6143 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6144 ++input_line_pointer;
6145 }
6146
6147 demand_empty_rest_of_line ();
6148 }
6149
6150 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6151 structured IF, associate the ELSE with the IF. Otherwise, assume
6152 it is a conditional else. */
6153
6154 static void
6155 s_mri_else (qual)
6156 int qual;
6157 {
6158 int c;
6159 char *buf;
6160 char q[2];
6161
6162 if (qual == '\0'
6163 && (mri_control_stack == NULL
6164 || mri_control_stack->type != mri_if
6165 || mri_control_stack->else_seen))
6166 {
6167 s_else (0);
6168 return;
6169 }
6170
6171 c = *input_line_pointer;
6172 *input_line_pointer = 0;
6173 if (ignore_input ())
6174 {
6175 *input_line_pointer = c;
6176 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6177 ++input_line_pointer;
6178 demand_empty_rest_of_line ();
6179 return;
6180 }
6181 *input_line_pointer = c;
6182
6183 if (mri_control_stack == NULL
6184 || mri_control_stack->type != mri_if
6185 || mri_control_stack->else_seen)
6186 {
6187 as_bad (_("else without matching if"));
6188 ignore_rest_of_line ();
6189 return;
6190 }
6191
6192 mri_control_stack->else_seen = 1;
6193
6194 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6195 q[0] = qual;
6196 q[1] = '\0';
6197 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6198 mri_assemble (buf);
6199 free (buf);
6200
6201 colon (mri_control_stack->next);
6202
6203 if (flag_mri)
6204 {
6205 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6206 ++input_line_pointer;
6207 }
6208
6209 demand_empty_rest_of_line ();
6210 }
6211
6212 /* Handle the MRI ENDI pseudo-op. */
6213
6214 static void
6215 s_mri_endi (ignore)
6216 int ignore ATTRIBUTE_UNUSED;
6217 {
6218 if (mri_control_stack == NULL
6219 || mri_control_stack->type != mri_if)
6220 {
6221 as_bad (_("endi without matching if"));
6222 ignore_rest_of_line ();
6223 return;
6224 }
6225
6226 /* ignore_input will not return true for ENDI, so we don't need to
6227 worry about checking it again here. */
6228
6229 if (! mri_control_stack->else_seen)
6230 colon (mri_control_stack->next);
6231 colon (mri_control_stack->bottom);
6232
6233 pop_mri_control ();
6234
6235 if (flag_mri)
6236 {
6237 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6238 ++input_line_pointer;
6239 }
6240
6241 demand_empty_rest_of_line ();
6242 }
6243
6244 /* Handle the MRI BREAK pseudo-op. */
6245
6246 static void
6247 s_mri_break (extent)
6248 int extent;
6249 {
6250 struct mri_control_info *n;
6251 char *buf;
6252 char ex[2];
6253
6254 n = mri_control_stack;
6255 while (n != NULL
6256 && n->type != mri_for
6257 && n->type != mri_repeat
6258 && n->type != mri_while)
6259 n = n->outer;
6260 if (n == NULL)
6261 {
6262 as_bad (_("break outside of structured loop"));
6263 ignore_rest_of_line ();
6264 return;
6265 }
6266
6267 buf = (char *) xmalloc (20 + strlen (n->bottom));
6268 ex[0] = extent;
6269 ex[1] = '\0';
6270 sprintf (buf, "bra%s %s", ex, n->bottom);
6271 mri_assemble (buf);
6272 free (buf);
6273
6274 if (flag_mri)
6275 {
6276 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6277 ++input_line_pointer;
6278 }
6279
6280 demand_empty_rest_of_line ();
6281 }
6282
6283 /* Handle the MRI NEXT pseudo-op. */
6284
6285 static void
6286 s_mri_next (extent)
6287 int extent;
6288 {
6289 struct mri_control_info *n;
6290 char *buf;
6291 char ex[2];
6292
6293 n = mri_control_stack;
6294 while (n != NULL
6295 && n->type != mri_for
6296 && n->type != mri_repeat
6297 && n->type != mri_while)
6298 n = n->outer;
6299 if (n == NULL)
6300 {
6301 as_bad (_("next outside of structured loop"));
6302 ignore_rest_of_line ();
6303 return;
6304 }
6305
6306 buf = (char *) xmalloc (20 + strlen (n->next));
6307 ex[0] = extent;
6308 ex[1] = '\0';
6309 sprintf (buf, "bra%s %s", ex, n->next);
6310 mri_assemble (buf);
6311 free (buf);
6312
6313 if (flag_mri)
6314 {
6315 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6316 ++input_line_pointer;
6317 }
6318
6319 demand_empty_rest_of_line ();
6320 }
6321
6322 /* Handle the MRI FOR pseudo-op. */
6323
6324 static void
6325 s_mri_for (qual)
6326 int qual;
6327 {
6328 const char *varstart, *varstop;
6329 const char *initstart, *initstop;
6330 const char *endstart, *endstop;
6331 const char *bystart, *bystop;
6332 int up;
6333 int by;
6334 int extent;
6335 struct mri_control_info *n;
6336 char *buf;
6337 char *s;
6338 char ex[2];
6339
6340 /* The syntax is
6341 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6342 */
6343
6344 SKIP_WHITESPACE ();
6345 varstart = input_line_pointer;
6346
6347 /* Look for the '='. */
6348 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6349 && *input_line_pointer != '=')
6350 ++input_line_pointer;
6351 if (*input_line_pointer != '=')
6352 {
6353 as_bad (_("missing ="));
6354 ignore_rest_of_line ();
6355 return;
6356 }
6357
6358 varstop = input_line_pointer;
6359 if (varstop > varstart
6360 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6361 --varstop;
6362
6363 ++input_line_pointer;
6364
6365 initstart = input_line_pointer;
6366
6367 /* Look for TO or DOWNTO. */
6368 up = 1;
6369 initstop = NULL;
6370 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6371 {
6372 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6373 && ! is_part_of_name (input_line_pointer[2]))
6374 {
6375 initstop = input_line_pointer;
6376 input_line_pointer += 2;
6377 break;
6378 }
6379 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6380 && ! is_part_of_name (input_line_pointer[6]))
6381 {
6382 initstop = input_line_pointer;
6383 up = 0;
6384 input_line_pointer += 6;
6385 break;
6386 }
6387 ++input_line_pointer;
6388 }
6389 if (initstop == NULL)
6390 {
6391 as_bad (_("missing to or downto"));
6392 ignore_rest_of_line ();
6393 return;
6394 }
6395 if (initstop > initstart
6396 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6397 --initstop;
6398
6399 SKIP_WHITESPACE ();
6400 endstart = input_line_pointer;
6401
6402 /* Look for BY or DO. */
6403 by = 0;
6404 endstop = NULL;
6405 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6406 {
6407 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6408 && ! is_part_of_name (input_line_pointer[2]))
6409 {
6410 endstop = input_line_pointer;
6411 by = 1;
6412 input_line_pointer += 2;
6413 break;
6414 }
6415 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6416 && (input_line_pointer[2] == '.'
6417 || ! is_part_of_name (input_line_pointer[2])))
6418 {
6419 endstop = input_line_pointer;
6420 input_line_pointer += 2;
6421 break;
6422 }
6423 ++input_line_pointer;
6424 }
6425 if (endstop == NULL)
6426 {
6427 as_bad (_("missing do"));
6428 ignore_rest_of_line ();
6429 return;
6430 }
6431 if (endstop > endstart
6432 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6433 --endstop;
6434
6435 if (! by)
6436 {
6437 bystart = "#1";
6438 bystop = bystart + 2;
6439 }
6440 else
6441 {
6442 SKIP_WHITESPACE ();
6443 bystart = input_line_pointer;
6444
6445 /* Look for DO. */
6446 bystop = NULL;
6447 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6448 {
6449 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6450 && (input_line_pointer[2] == '.'
6451 || ! is_part_of_name (input_line_pointer[2])))
6452 {
6453 bystop = input_line_pointer;
6454 input_line_pointer += 2;
6455 break;
6456 }
6457 ++input_line_pointer;
6458 }
6459 if (bystop == NULL)
6460 {
6461 as_bad (_("missing do"));
6462 ignore_rest_of_line ();
6463 return;
6464 }
6465 if (bystop > bystart
6466 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6467 --bystop;
6468 }
6469
6470 if (*input_line_pointer != '.')
6471 extent = '\0';
6472 else
6473 {
6474 extent = input_line_pointer[1];
6475 input_line_pointer += 2;
6476 }
6477
6478 /* We have fully parsed the FOR operands. Now build the loop. */
6479
6480 n = push_mri_control (mri_for);
6481
6482 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6483
6484 /* move init,var */
6485 s = buf;
6486 *s++ = 'm';
6487 *s++ = 'o';
6488 *s++ = 'v';
6489 *s++ = 'e';
6490 if (qual != '\0')
6491 *s++ = qual;
6492 *s++ = ' ';
6493 memcpy (s, initstart, initstop - initstart);
6494 s += initstop - initstart;
6495 *s++ = ',';
6496 memcpy (s, varstart, varstop - varstart);
6497 s += varstop - varstart;
6498 *s = '\0';
6499 mri_assemble (buf);
6500
6501 colon (n->top);
6502
6503 /* cmp end,var */
6504 s = buf;
6505 *s++ = 'c';
6506 *s++ = 'm';
6507 *s++ = 'p';
6508 if (qual != '\0')
6509 *s++ = qual;
6510 *s++ = ' ';
6511 memcpy (s, endstart, endstop - endstart);
6512 s += endstop - endstart;
6513 *s++ = ',';
6514 memcpy (s, varstart, varstop - varstart);
6515 s += varstop - varstart;
6516 *s = '\0';
6517 mri_assemble (buf);
6518
6519 /* bcc bottom */
6520 ex[0] = extent;
6521 ex[1] = '\0';
6522 if (up)
6523 sprintf (buf, "blt%s %s", ex, n->bottom);
6524 else
6525 sprintf (buf, "bgt%s %s", ex, n->bottom);
6526 mri_assemble (buf);
6527
6528 /* Put together the add or sub instruction used by ENDF. */
6529 s = buf;
6530 if (up)
6531 strcpy (s, "add");
6532 else
6533 strcpy (s, "sub");
6534 s += 3;
6535 if (qual != '\0')
6536 *s++ = qual;
6537 *s++ = ' ';
6538 memcpy (s, bystart, bystop - bystart);
6539 s += bystop - bystart;
6540 *s++ = ',';
6541 memcpy (s, varstart, varstop - varstart);
6542 s += varstop - varstart;
6543 *s = '\0';
6544 n->incr = buf;
6545
6546 if (flag_mri)
6547 {
6548 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6549 ++input_line_pointer;
6550 }
6551
6552 demand_empty_rest_of_line ();
6553 }
6554
6555 /* Handle the MRI ENDF pseudo-op. */
6556
6557 static void
6558 s_mri_endf (ignore)
6559 int ignore ATTRIBUTE_UNUSED;
6560 {
6561 if (mri_control_stack == NULL
6562 || mri_control_stack->type != mri_for)
6563 {
6564 as_bad (_("endf without for"));
6565 ignore_rest_of_line ();
6566 return;
6567 }
6568
6569 colon (mri_control_stack->next);
6570
6571 mri_assemble (mri_control_stack->incr);
6572
6573 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6574 mri_assemble (mri_control_stack->incr);
6575
6576 free (mri_control_stack->incr);
6577
6578 colon (mri_control_stack->bottom);
6579
6580 pop_mri_control ();
6581
6582 if (flag_mri)
6583 {
6584 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6585 ++input_line_pointer;
6586 }
6587
6588 demand_empty_rest_of_line ();
6589 }
6590
6591 /* Handle the MRI REPEAT pseudo-op. */
6592
6593 static void
6594 s_mri_repeat (ignore)
6595 int ignore ATTRIBUTE_UNUSED;
6596 {
6597 struct mri_control_info *n;
6598
6599 n = push_mri_control (mri_repeat);
6600 colon (n->top);
6601 if (flag_mri)
6602 {
6603 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6604 ++input_line_pointer;
6605 }
6606 demand_empty_rest_of_line ();
6607 }
6608
6609 /* Handle the MRI UNTIL pseudo-op. */
6610
6611 static void
6612 s_mri_until (qual)
6613 int qual;
6614 {
6615 char *s;
6616
6617 if (mri_control_stack == NULL
6618 || mri_control_stack->type != mri_repeat)
6619 {
6620 as_bad (_("until without repeat"));
6621 ignore_rest_of_line ();
6622 return;
6623 }
6624
6625 colon (mri_control_stack->next);
6626
6627 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6628 ;
6629
6630 parse_mri_control_expression (s, qual, (const char *) NULL,
6631 mri_control_stack->top, '\0');
6632
6633 colon (mri_control_stack->bottom);
6634
6635 input_line_pointer = s;
6636
6637 pop_mri_control ();
6638
6639 if (flag_mri)
6640 {
6641 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6642 ++input_line_pointer;
6643 }
6644
6645 demand_empty_rest_of_line ();
6646 }
6647
6648 /* Handle the MRI WHILE pseudo-op. */
6649
6650 static void
6651 s_mri_while (qual)
6652 int qual;
6653 {
6654 char *s;
6655
6656 struct mri_control_info *n;
6657
6658 s = input_line_pointer;
6659 while (! is_end_of_line[(unsigned char) *s]
6660 && (! flag_mri || *s != '*'))
6661 s++;
6662 --s;
6663 while (*s == ' ' || *s == '\t')
6664 --s;
6665 if (s - input_line_pointer > 1
6666 && s[-1] == '.')
6667 s -= 2;
6668 if (s - input_line_pointer < 2
6669 || strncasecmp (s - 1, "DO", 2) != 0)
6670 {
6671 as_bad (_("missing do"));
6672 ignore_rest_of_line ();
6673 return;
6674 }
6675
6676 n = push_mri_control (mri_while);
6677
6678 colon (n->next);
6679
6680 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6681 s[1] == '.' ? s[2] : '\0');
6682
6683 input_line_pointer = s + 1;
6684 if (*input_line_pointer == '.')
6685 input_line_pointer += 2;
6686
6687 if (flag_mri)
6688 {
6689 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6690 ++input_line_pointer;
6691 }
6692
6693 demand_empty_rest_of_line ();
6694 }
6695
6696 /* Handle the MRI ENDW pseudo-op. */
6697
6698 static void
6699 s_mri_endw (ignore)
6700 int ignore ATTRIBUTE_UNUSED;
6701 {
6702 char *buf;
6703
6704 if (mri_control_stack == NULL
6705 || mri_control_stack->type != mri_while)
6706 {
6707 as_bad (_("endw without while"));
6708 ignore_rest_of_line ();
6709 return;
6710 }
6711
6712 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6713 sprintf (buf, "bra %s", mri_control_stack->next);
6714 mri_assemble (buf);
6715 free (buf);
6716
6717 colon (mri_control_stack->bottom);
6718
6719 pop_mri_control ();
6720
6721 if (flag_mri)
6722 {
6723 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6724 ++input_line_pointer;
6725 }
6726
6727 demand_empty_rest_of_line ();
6728 }
6729 \f
6730 /*
6731 * md_parse_option
6732 * Invocation line includes a switch not recognized by the base assembler.
6733 * See if it's a processor-specific option. These are:
6734 *
6735 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6736 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6737 * Select the architecture. Instructions or features not
6738 * supported by the selected architecture cause fatal
6739 * errors. More than one may be specified. The default is
6740 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6741 * for -m68000, and -m68882 is a synonym for -m68881.
6742 * -[A]m[c]no-68851, -[A]m[c]no-68881
6743 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6744 * so don't use or document it, but that's the way the parsing
6745 * works).
6746 *
6747 * -pic Indicates PIC.
6748 * -k Indicates PIC. (Sun 3 only.)
6749 * --pcrel Never turn PC-relative branches into absolute jumps.
6750 *
6751 * --bitwise-or
6752 * Permit `|' to be used in expressions.
6753 *
6754 */
6755
6756 #ifdef OBJ_ELF
6757 CONST char *md_shortopts = "lSA:m:kQ:V";
6758 #else
6759 CONST char *md_shortopts = "lSA:m:k";
6760 #endif
6761
6762 struct option md_longopts[] = {
6763 #define OPTION_PIC (OPTION_MD_BASE)
6764 {"pic", no_argument, NULL, OPTION_PIC},
6765 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6766 {"register-prefix-optional", no_argument, NULL,
6767 OPTION_REGISTER_PREFIX_OPTIONAL},
6768 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6769 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6770 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6771 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6772 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6773 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6774 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6775 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6776 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6777 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6778 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6779 {"pcrel", no_argument, NULL, OPTION_PCREL},
6780 {NULL, no_argument, NULL, 0}
6781 };
6782 size_t md_longopts_size = sizeof (md_longopts);
6783
6784 int
6785 md_parse_option (c, arg)
6786 int c;
6787 char *arg;
6788 {
6789 switch (c)
6790 {
6791 case 'l': /* -l means keep external to 2 bit offset
6792 rather than 16 bit one */
6793 flag_short_refs = 1;
6794 break;
6795
6796 case 'S': /* -S means that jbsr's always turn into
6797 jsr's. */
6798 flag_long_jumps = 1;
6799 break;
6800
6801 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6802 branches into absolute jumps. */
6803 flag_keep_pcrel = 1;
6804 break;
6805
6806 case 'A':
6807 if (*arg == 'm')
6808 arg++;
6809 /* intentional fall-through */
6810 case 'm':
6811
6812 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6813 {
6814 int i;
6815 unsigned long arch;
6816 const char *oarg = arg;
6817
6818 arg += 3;
6819 if (*arg == 'm')
6820 {
6821 arg++;
6822 if (arg[0] == 'c' && arg[1] == '6')
6823 arg++;
6824 }
6825 for (i = 0; i < n_archs; i++)
6826 if (!strcmp (arg, archs[i].name))
6827 break;
6828 if (i == n_archs)
6829 {
6830 unknown:
6831 as_bad (_("unrecognized option `%s'"), oarg);
6832 return 0;
6833 }
6834 arch = archs[i].arch;
6835 if (arch == m68881)
6836 no_68881 = 1;
6837 else if (arch == m68851)
6838 no_68851 = 1;
6839 else
6840 goto unknown;
6841 }
6842 else
6843 {
6844 int i;
6845
6846 if (arg[0] == 'c' && arg[1] == '6')
6847 arg++;
6848
6849 for (i = 0; i < n_archs; i++)
6850 if (!strcmp (arg, archs[i].name))
6851 {
6852 unsigned long arch = archs[i].arch;
6853 if (cpu_of_arch (arch))
6854 /* It's a cpu spec. */
6855 {
6856 current_architecture &= ~m68000up;
6857 current_architecture |= arch;
6858 }
6859 else if (arch == m68881)
6860 {
6861 current_architecture |= m68881;
6862 no_68881 = 0;
6863 }
6864 else if (arch == m68851)
6865 {
6866 current_architecture |= m68851;
6867 no_68851 = 0;
6868 }
6869 else
6870 /* ??? */
6871 abort ();
6872 break;
6873 }
6874 if (i == n_archs)
6875 {
6876 as_bad (_("unrecognized architecture specification `%s'"), arg);
6877 return 0;
6878 }
6879 }
6880 break;
6881
6882 case OPTION_PIC:
6883 case 'k':
6884 flag_want_pic = 1;
6885 break; /* -pic, Position Independent Code */
6886
6887 case OPTION_REGISTER_PREFIX_OPTIONAL:
6888 flag_reg_prefix_optional = 1;
6889 reg_prefix_optional_seen = 1;
6890 break;
6891
6892 /* -V: SVR4 argument to print version ID. */
6893 case 'V':
6894 print_version_id ();
6895 break;
6896
6897 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6898 should be emitted or not. FIXME: Not implemented. */
6899 case 'Q':
6900 break;
6901
6902 case OPTION_BITWISE_OR:
6903 {
6904 char *n, *t;
6905 const char *s;
6906
6907 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6908 t = n;
6909 for (s = m68k_comment_chars; *s != '\0'; s++)
6910 if (*s != '|')
6911 *t++ = *s;
6912 *t = '\0';
6913 m68k_comment_chars = n;
6914 }
6915 break;
6916
6917 case OPTION_BASE_SIZE_DEFAULT_16:
6918 m68k_index_width_default = SIZE_WORD;
6919 break;
6920
6921 case OPTION_BASE_SIZE_DEFAULT_32:
6922 m68k_index_width_default = SIZE_LONG;
6923 break;
6924
6925 case OPTION_DISP_SIZE_DEFAULT_16:
6926 m68k_rel32 = 0;
6927 m68k_rel32_from_cmdline = 1;
6928 break;
6929
6930 case OPTION_DISP_SIZE_DEFAULT_32:
6931 m68k_rel32 = 1;
6932 m68k_rel32_from_cmdline = 1;
6933 break;
6934
6935 default:
6936 return 0;
6937 }
6938
6939 return 1;
6940 }
6941
6942 void
6943 md_show_usage (stream)
6944 FILE *stream;
6945 {
6946 fprintf (stream, _("\
6947 680X0 options:\n\
6948 -l use 1 word for refs to undefined symbols [default 2]\n\
6949 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6950 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6951 | -mcpu32 | -m5200\n\
6952 specify variant of 680X0 architecture [default 68020]\n\
6953 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6954 target has/lacks floating-point coprocessor\n\
6955 [default yes for 68020, 68030, and cpu32]\n"));
6956 fprintf (stream, _("\
6957 -m68851 | -mno-68851\n\
6958 target has/lacks memory-management unit coprocessor\n\
6959 [default yes for 68020 and up]\n\
6960 -pic, -k generate position independent code\n\
6961 -S turn jbsr into jsr\n\
6962 --pcrel never turn PC-relative branches into absolute jumps\n\
6963 --register-prefix-optional\n\
6964 recognize register names without prefix character\n\
6965 --bitwise-or do not treat `|' as a comment character\n"));
6966 fprintf (stream, _("\
6967 --base-size-default-16 base reg without size is 16 bits\n\
6968 --base-size-default-32 base reg without size is 32 bits (default)\n\
6969 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6970 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6971 }
6972 \f
6973 #ifdef TEST2
6974
6975 /* TEST2: Test md_assemble() */
6976 /* Warning, this routine probably doesn't work anymore */
6977
6978 main ()
6979 {
6980 struct m68k_it the_ins;
6981 char buf[120];
6982 char *cp;
6983 int n;
6984
6985 m68k_ip_begin ();
6986 for (;;)
6987 {
6988 if (!gets (buf) || !*buf)
6989 break;
6990 if (buf[0] == '|' || buf[1] == '.')
6991 continue;
6992 for (cp = buf; *cp; cp++)
6993 if (*cp == '\t')
6994 *cp = ' ';
6995 if (is_label (buf))
6996 continue;
6997 memset (&the_ins, '\0', sizeof (the_ins));
6998 m68k_ip (&the_ins, buf);
6999 if (the_ins.error)
7000 {
7001 printf (_("Error %s in %s\n"), the_ins.error, buf);
7002 }
7003 else
7004 {
7005 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7006 for (n = 0; n < the_ins.numo; n++)
7007 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7008 printf (" ");
7009 print_the_insn (&the_ins.opcode[0], stdout);
7010 (void) putchar ('\n');
7011 }
7012 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7013 {
7014 if (the_ins.operands[n].error)
7015 {
7016 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7017 continue;
7018 }
7019 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7020 if (the_ins.operands[n].b_const)
7021 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7022 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7023 if (the_ins.operands[n].b_iadd)
7024 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7025 (void) putchar ('\n');
7026 }
7027 }
7028 m68k_ip_end ();
7029 return 0;
7030 }
7031
7032 is_label (str)
7033 char *str;
7034 {
7035 while (*str == ' ')
7036 str++;
7037 while (*str && *str != ' ')
7038 str++;
7039 if (str[-1] == ':' || str[1] == '=')
7040 return 1;
7041 return 0;
7042 }
7043
7044 #endif
7045
7046 /* Possible states for relaxation:
7047
7048 0 0 branch offset byte (bra, etc)
7049 0 1 word
7050 0 2 long
7051
7052 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7053 1 1 word
7054 1 2 long
7055
7056 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7057 2 1 word-long
7058 2 2 long-word
7059 2 3 long-long
7060
7061 */
7062
7063 /* We have no need to default values of symbols. */
7064
7065 symbolS *
7066 md_undefined_symbol (name)
7067 char *name ATTRIBUTE_UNUSED;
7068 {
7069 return 0;
7070 }
7071
7072 /* Round up a section size to the appropriate boundary. */
7073 valueT
7074 md_section_align (segment, size)
7075 segT segment ATTRIBUTE_UNUSED;
7076 valueT size;
7077 {
7078 #ifdef OBJ_AOUT
7079 #ifdef BFD_ASSEMBLER
7080 /* For a.out, force the section size to be aligned. If we don't do
7081 this, BFD will align it for us, but it will not write out the
7082 final bytes of the section. This may be a bug in BFD, but it is
7083 easier to fix it here since that is how the other a.out targets
7084 work. */
7085 int align;
7086
7087 align = bfd_get_section_alignment (stdoutput, segment);
7088 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7089 #endif
7090 #endif
7091
7092 return size;
7093 }
7094
7095 /* Exactly what point is a PC-relative offset relative TO?
7096 On the 68k, it is relative to the address of the first extension
7097 word. The difference between the addresses of the offset and the
7098 first extension word is stored in fx_pcrel_adjust. */
7099 long
7100 md_pcrel_from (fixP)
7101 fixS *fixP;
7102 {
7103 int adjust;
7104
7105 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7106 -1 as 64. */
7107 adjust = fixP->fx_pcrel_adjust;
7108 if (adjust == 64)
7109 adjust = -1;
7110 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7111 }
7112
7113 #ifndef BFD_ASSEMBLER
7114 #ifdef OBJ_COFF
7115
7116 void
7117 tc_coff_symbol_emit_hook (ignore)
7118 symbolS *ignore ATTRIBUTE_UNUSED;
7119 {
7120 }
7121
7122 int
7123 tc_coff_sizemachdep (frag)
7124 fragS *frag;
7125 {
7126 switch (frag->fr_subtype & 0x3)
7127 {
7128 case BYTE:
7129 return 1;
7130 case SHORT:
7131 return 2;
7132 case LONG:
7133 return 4;
7134 default:
7135 abort ();
7136 return 0;
7137 }
7138 }
7139
7140 #endif
7141 #endif
7142 #ifdef OBJ_ELF
7143 void m68k_elf_final_processing()
7144 {
7145 /* Set file-specific flags if this is a cpu32 processor */
7146 if (cpu_of_arch (current_architecture) & cpu32)
7147 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7148 }
7149 #endif
GDB Binutils - Deliverables
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