1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
4 Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
31 /* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
34 #define DO_BREAK_UP_BIG_DECL
35 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
39 /* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
41 #include "opcode/m68k.h"
43 /* This array holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful */
45 CONST
char comment_chars
[] = "|";
47 /* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50 /* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53 /* Also note that comments like this one will always work. */
54 CONST
char line_comment_chars
[] = "#";
56 CONST
char line_separator_chars
[] = "";
58 /* Chars that can be used to separate mant from exp in floating point nums */
59 CONST
char EXP_CHARS
[] = "eE";
61 /* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
64 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
70 const int md_reloc_size
= 8; /* Size of relocation record */
72 /* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
77 #ifdef REGISTER_PREFIX_OPTIONAL
78 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
80 int flag_reg_prefix_optional
;
83 /* Its an arbitrary name: This means I don't approve of it */
84 /* See flames below */
85 static struct obstack robyn
;
87 #define TAB(x,y) (((x)<<2)+(y))
88 #define TABTYPE(xy) ((xy) >> 2)
104 unsigned long m_opcode
;
108 struct m68k_incant
*m_next
;
111 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
112 #define gettwo(x) (((x)->m_opcode)&0xffff)
114 /* Operands we can parse: (And associated modes)
120 reg: address or data register
121 areg: address register
122 apc: address register, PC, ZPC or empty string
123 num: 16 or 32 bit num
125 sz: w or l if omitted, l assumed
126 scale: 1 2 4 or 8 if omitted, 1 assumed
128 7.4 IMMED #num --> NUM
129 0.? DREG dreg --> dreg
130 1.? AREG areg --> areg
131 2.? AINDR areg@ --> *(areg)
132 3.? AINC areg@+ --> *(areg++)
133 4.? ADEC areg@- --> *(--areg)
134 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
135 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
136 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
137 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
138 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
139 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
140 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
141 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
142 7.0 ABSL num:sz --> *(num)
143 num --> *(num) (sz L assumed)
144 *** MSCR otherreg --> Magic
146 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
147 ?.? DINDR dreg@ --> (dreg) -- cas2 only
157 a1@(5,d2:w:1) @(45,d6:l:4)
162 #name@(numw) -->turn into PC rel mode
163 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
193 short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
196 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
197 0-7==data reg, 8-15==addr reg for operands that take both types.
199 We don't use forms like "ADDR0 = ADDR" here because this file is
200 likely to be used on an Apollo, and the broken Apollo compiler
201 gives an `undefined variable' error if we do that, according to
202 troy@cbme.unsw.edu.au. */
214 DATA0
= 1, /* 1- 8 == data registers 0-7 */
232 /* Note that COP0==processor #1 -- COP0+7==#8, which stores as 000 */
235 FP0
, /* Eight FP registers */
244 COP0
, /* Co-processor #1-#8 */
253 PC
, /* Program counter */
254 ZPC
, /* Hack for Program space, but 0 addressing */
256 CCR
, /* Condition code Reg */
258 /* These have to be grouped together for the movec instruction to work. */
259 USP
, /* User Stack Pointer */
260 ISP
, /* Interrupt stack pointer */
275 BUSCR
, /* 68060 added these */
277 #define last_movec_reg PCR
278 /* end of movec ordering constraints */
284 DRP
, /* 68851 or 68030 MMU regs */
306 PSR
, /* aka MMUSR on 68030 (but not MMUSR on 68040)
307 and ACUSR on 68ec030 */
310 IC
, /* instruction cache token */
311 DC
, /* data cache token */
312 NC
, /* no cache token */
313 BC
, /* both caches token */
315 TT0
, /* 68030 access control unit regs */
319 static const enum _register m68000_control_regs
[] = { 0 };
320 static const enum _register m68010_control_regs
[] = {
324 static const enum _register m68020_control_regs
[] = {
325 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
328 static const enum _register m68040_control_regs
[] = {
329 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
330 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
333 static const enum _register m68060_control_regs
[] = {
334 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
335 USP
, VBR
, URP
, SRP
, PCR
,
339 static const enum _register
*control_regs
;
341 /* Internal form of an operand. */
344 char *error
; /* Couldn't parse it */
345 enum operand_type mode
; /* What mode this instruction is in. */
346 enum _register reg
; /* Base register */
347 struct m68k_exp
*con1
;
348 int ireg
; /* Index register */
349 int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
350 int imul
; /* Multipy ireg by this (1,2,4,or 8) */
351 struct m68k_exp
*con2
;
354 /* internal form of a 68020 instruction */
358 char *args
; /* list of opcode info */
361 int numo
; /* Number of shorts in opcode */
364 struct m68k_op operands
[6];
366 int nexp
; /* number of exprs in use */
367 struct m68k_exp exprs
[4];
369 int nfrag
; /* Number of frags we have to produce */
372 int fragoff
; /* Where in the current opcode[] the frag ends */
379 int nrel
; /* Num of reloc strucs in use */
387 reloc
[5]; /* Five is enough??? */
390 #define cpu_of_arch(x) ((x) & m68000up)
391 #define float_of_arch(x) ((x) & mfloat)
392 #define mmu_of_arch(x) ((x) & mmmu)
394 static struct m68k_it the_ins
; /* the instruction being assembled */
396 #define seg(exp) ((exp)->e_seg)
397 #define op(exp) ((exp)->e_exp.X_op)
398 #define adds(exp) ((exp)->e_exp.X_add_symbol)
399 #define subs(exp) ((exp)->e_exp.X_op_symbol)
400 #define offs(exp) ((exp)->e_exp.X_add_number)
402 /* Macros for adding things to the m68k_it struct */
404 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
406 /* Like addword, but goes BEFORE general operands */
410 struct m68k_incant
*opcode
;
413 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
414 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
415 for(z
=0;z
<the_ins
.nrel
;z
++)
416 the_ins
.reloc
[z
].n
+=2;
417 the_ins
.opcode
[opcode
->m_codenum
]=w
;
421 static struct m68k_exp
*
426 the_ins
.exprs
[the_ins
.nexp
].e_beg
=beg
;
427 the_ins
.exprs
[the_ins
.nexp
].e_end
=end
;
428 return &the_ins
.exprs
[the_ins
.nexp
++];
432 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
435 add_fix (width
, exp
, pc_rel
)
437 struct m68k_exp
*exp
;
440 the_ins
.reloc
[the_ins
.nrel
].n
= (((width
)=='B')
443 ? ((the_ins
.numo
-1)*2)
444 : (the_ins
.numo
*2)));
445 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->e_exp
;
446 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
447 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
451 add_frag(add
,off
,type
)
456 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
457 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
458 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
459 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
463 ((exp) && op (exp) != O_constant && op (exp) != O_big)
465 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
466 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
467 static int get_regs
PARAMS ((int i
, char *str
, struct m68k_op
*opP
));
468 static int reverse_16_bits
PARAMS ((int in
));
469 static int reverse_8_bits
PARAMS ((int in
));
470 static int try_index
PARAMS ((char **s
, struct m68k_op
*opP
));
471 static void install_gen_operand
PARAMS ((int mode
, int val
));
472 static void install_operand
PARAMS ((int mode
, int val
));
473 static void s_bss
PARAMS ((int));
474 static void s_data1
PARAMS ((int));
475 static void s_data2
PARAMS ((int));
476 static void s_even
PARAMS ((int));
477 static void s_proc
PARAMS ((int));
479 static int current_architecture
;
481 /* BCC68000 is for patching in an extra jmp instruction for long offsets
482 on the 68000. The 68000 doesn't support long branches with branchs */
484 /* This table desribes how you change sizes for the various types of variable
485 size expressions. This version only supports two kinds. */
487 /* Note that calls to frag_var need to specify the maximum expansion
488 needed; this is currently 10 bytes for DBCC. */
491 How far Forward this mode will reach:
492 How far Backward this mode will reach:
493 How many bytes this mode will add to the size of the frag
494 Which mode to go to if the offset won't fit in this one
496 CONST relax_typeS md_relax_table
[] =
498 {1, 1, 0, 0}, /* First entries aren't used */
499 {1, 1, 0, 0}, /* For no good reason except */
500 {1, 1, 0, 0}, /* that the VAX doesn't either */
503 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
504 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
508 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
509 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
513 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
514 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
518 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
519 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
520 {0, 0, 6, 0}, /* jmp long space */
523 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
524 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
525 {0, 0, 10, 0}, /* bra/jmp long space */
528 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
529 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
535 /* These are the machine dependent pseudo-ops. These are included so
536 the assembler can work on the output from the SUN C compiler, which
540 /* This table describes all the machine specific pseudo-ops the assembler
541 has to support. The fields are:
542 pseudo-op name without dot
543 function to call to execute this pseudo-op
544 Integer arg to pass to the function
546 CONST pseudo_typeS md_pseudo_table
[] =
548 {"data1", s_data1
, 0},
549 {"data2", s_data2
, 0},
552 {"skip", s_space
, 0},
555 {"align", s_align_bytes
, 0},
561 /* The mote pseudo ops are put into the opcode table, since they
562 don't start with a . they look like opcodes to gas.
564 extern void obj_coff_section ();
566 CONST pseudo_typeS mote_pseudo_table
[] =
574 {"ds.l", s_space
, 4},
576 {"ds.w", s_space
, 2},
577 {"ds.b", s_space
, 1},
579 {"xdef", s_globl
, 0},
580 {"align", s_align_ptwo
, 0},
582 {"sect", obj_coff_section
, 0},
583 {"section", obj_coff_section
, 0},
588 #define issbyte(x) ((x)>=-128 && (x)<=127)
589 #define isubyte(x) ((x)>=0 && (x)<=255)
590 #define issword(x) ((x)>=-32768 && (x)<=32767)
591 #define isuword(x) ((x)>=0 && (x)<=65535)
593 #define isbyte(x) ((x)>= -255 && (x)<=255)
594 #define isword(x) ((x)>=-32768 && (x)<=65535)
595 #define islong(x) (1)
597 extern char *input_line_pointer
;
605 /* JF these tables here are for speed at the expense of size */
606 /* You can replace them with the #if 0 versions if you really
607 need space and don't mind it running a bit slower */
609 static char mklower_table
[256];
610 #define mklower(c) (mklower_table[(unsigned char)(c)])
611 static char notend_table
[256];
612 static char alt_notend_table
[256];
613 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
614 alt_notend_table[(unsigned char)(s[1])])))
617 #define mklower(c) (isupper(c) ? tolower(c) : c)
621 /* JF modified this to handle cases where the first part of a symbol name
622 looks like a register */
625 * m68k_reg_parse() := if it looks like a register, return it's token &
626 * advance the pointer.
638 if (flag_reg_prefix_optional
)
640 if (*start
== REGISTER_PREFIX
)
646 if (*start
!= REGISTER_PREFIX
)
651 if (!isalpha (*p
) || !is_name_beginner (*p
))
655 while (isalpha (c
) || isdigit (c
) || c
== '_')
661 symbolP
= symbol_find (start
);
664 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
667 return S_GET_VALUE (symbolP
);
673 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
674 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
676 /* Parse an index specification using Motorola syntax. */
679 try_moto_index (s
, opP
)
690 i
= m68k_reg_parse (&ss
);
691 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
692 { /* if i is not DATA or ADDR reg */
693 opP
->error
= "Invalid index register";
709 opP
->error
= "Missing . in index register";
714 if (mklower (*ss
) == 'w')
716 else if (mklower (*ss
) == 'l')
720 opP
->error
= "Size spec not .W or .L";
725 if (*ss
== '.' || *ss
== '*')
734 opP
->imul
= *ss
- '0';
737 opP
->error
= "index multiplier not 1, 2, 4 or 8";
747 opP
->error
= "Missing )";
758 * try_index := data_or_address_register + ')' + SKIP_W
759 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
761 * multiplier := <empty>
762 * | ':' + multiplier_number
765 * multiplier_number := '1' | '2' | '4' | '8' ;
767 * size_spec := 'l' | 'L' | 'w' | 'W' ;
769 * SKIP_W := <empty> | ' ' ;
783 i
= m68k_reg_parse (&ss
);
784 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
785 { /* if i is not DATA or ADDR reg */
801 opP
->error
= "Missing : in index register";
817 opP
->error
= "Index register size spec not :w or :l";
831 if (cpu_of_arch (current_architecture
) < m68020
)
833 opP
->error
= "no index scaling in pre-68020's";
837 opP
->imul
= *ss
- '0';
840 opP
->error
= "index multiplier not 1, 2, 4 or 8";
850 opP
->error
= "Missing )";
859 /* Ian Taylor expanded this function to accept both MIT and Motorola
860 syntax. I removed the old comment, since it was wrong. The syntax
861 this accepted even before my changes was complex and undocumented.
862 I mainly added a large case when the operand string does not
863 contain an '@', since the Motorola syntax does not use the '@'
867 m68k_ip_op (str
, opP
)
869 register struct m68k_op
*opP
;
873 char *parse_index ();
879 } /* Find the beginning of the string */
883 opP
->error
= "Missing operand";
887 for (strend
= str
; *strend
; strend
++)
891 if (*str
== '#' || *str
== '&')
894 opP
->con1
= add_exp (str
, strend
);
897 } /* Guess what: A constant. Shar and enjoy */
899 i
= m68k_reg_parse (&str
);
903 if (*str
== '/' || *str
== '-')
905 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
907 return get_regs (i
, str
, opP
);
912 /* "Rn" Register Direct mode */
913 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
915 else if (i
>= ADDR
+ 0 && i
<= ADDR
+ 7)
927 if ((stmp
= strchr (str
, '@')) != 0)
929 opP
->con1
= add_exp (str
, stmp
- 1);
936 if ((current_architecture
& m68020up
) == 0)
939 } /* if target is not a '20 or better */
942 if (*stmp
++ != '(' || *strend
-- != ')')
944 opP
->error
= "Malformed operand";
947 i
= try_index (&stmp
, opP
);
948 opP
->con2
= add_exp (stmp
, strend
);
959 } /* if there's an '@' */
961 #ifndef MIT_SYNTAX_ONLY
962 /* The operand has no '@'. Try to parse it using
964 /* Logic of the parsing switch(*str):
968 REG AREG or DREG or MSCR 3 or 2 or 13
969 REG- or REG/ REGLST 14
974 (EXPR,REG,INDX) AINDX 8
977 EXP2(REG,INDX) AINDX 8
980 REG means truth(m68k_reg_parse(&str))
981 INDX means truth(try_moto_index(&str,opP))
983 EXP2 means not REG and not '(' and not '-('
989 i
= m68k_reg_parse (&str
);
990 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7)
991 && (i
< DATA
+ 0 || i
> DATA
+ 7
992 || *str
!= ')' || str
[1] != '0')
993 && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
995 /* Can't indirect off non address regs */
996 opP
->error
= "Invalid indirect register";
1007 /* "(An)" Address Register Indirect mode
1008 or "(Dn)" for cas2. */
1009 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
1019 /* "(An)+" Register Indirect w Postincrement */
1024 opP
->error
= "Junk after indirect";
1030 i
= try_moto_index (&str
, opP
);
1033 /* "(An,Rn)" Register Indirect with Index mode*/
1039 opP
->error
= "Bad indirect syntax";
1045 /* "(EXPR,..." , a displacement */
1048 if ((stmp
= strchr (str
, ',')) != NULL
)
1050 opP
->con1
= add_exp (str
, stmp
- 1);
1053 i
= m68k_reg_parse (&str
);
1054 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
)
1056 /* Can't indirect off non address regs */
1057 opP
->error
= "Invalid indirect register";
1065 /* "(d,An)" Register Indirect w Displacement */
1072 i
= try_moto_index (&str
, opP
);
1075 /* "(d,An,Rn)" Register Indirect with Index */
1081 opP
->error
= "Bad indirect syntax";
1087 opP
->error
= "Invalid register";
1094 opP
->con1
= add_exp (str
- 1, strend
);
1105 i
= m68k_reg_parse (&str
);
1106 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
1108 /* Can't indirect off non address regs */
1109 opP
->error
= "Invalid indirect register";
1120 /* "-(An)" Register Indirect with Predecrement */
1124 opP
->error
= "Junk after indirect";
1127 opP
->error
= "Bad indirect syntax";
1131 opP
->con1
= add_exp (str
- 2, strend
);
1134 /* if '-' but not "-(', do nothing */
1137 /* whether *str=='-' or not */
1139 /* "EXP2" or "EXP2(REG..." */
1141 if ((stmp
= strchr (str
, '(')) != NULL
)
1145 opP
->con1
= add_exp (str
, stmp
- 1);
1147 i
= m68k_reg_parse (&str
);
1148 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
1149 && i
!= ZPC
&& i
!= FAIL
)
1151 /* Can't indirect off non address regs */
1152 opP
->error
= "Invalid indirect register";
1160 /* "d(An)" Register Indirect w Displacement */
1167 i
= try_moto_index (&str
, opP
);
1170 /* "d(An,Rn)" Register Indirect with Index */
1176 opP
->error
= "Bad indirect syntax";
1183 opP
->con1
= add_exp (ostr
, strend
);
1189 /* "EXP2" Absolute */
1192 if (strend
[-1] == '.' || strend
[-1] == ':')
1194 /* mode ==foo.[wl] */
1207 opP
->con1
= add_exp (str
, strend
);
1212 #else /* defined (MIT_SYNTAX_ONLY) */
1214 opP
->con1
= add_exp (str
, strend
);
1216 #endif /* defined (MIT_SYNTAX_ONLY) */
1221 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1222 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
1223 && (str
[1] != '\0' || i
< DATA
+ 0 || i
> DATA
+ 7))
1225 opP
->error
= "Invalid indirect register";
1234 if (i
< DATA
+ 0 || i
> DATA
+ 7)
1249 opP
->error
= "Junk after indirect";
1252 /* Some kind of indexing involved. Lets find out how bad it is */
1253 i
= try_index (&str
, opP
);
1254 /* Didn't start with an index reg, maybe its offset or offset,reg */
1265 opP
->error
= "Missing )";
1298 opP
->error
="Specified size isn't :w or :l";
1301 opP
->con1
=add_exp(beg_str
,str
-4);
1302 opP
->con1
->e_siz
=siz
;
1306 opP
->con1
= add_exp (beg_str
, str
- 2);
1307 /* Should be offset,reg */
1310 i
= try_index (&str
, opP
);
1313 opP
->error
= "Malformed index reg";
1318 /* We've now got offset) offset,reg) or reg) */
1322 /* Th-the-thats all folks */
1323 if (opP
->reg
== FAIL
)
1324 opP
->mode
= AINDX
; /* Other form of indirect */
1325 else if (opP
->ireg
== FAIL
)
1331 /* Next thing had better be another @ */
1346 if ((current_architecture
& m68020up
) == 0)
1349 } /* if target is not a '20 or better */
1352 if (opP
->ireg
!= FAIL
)
1356 i
= try_index (&str
, opP
);
1359 opP
->error
= "Two index registers! not allowed!";
1365 i
= try_index (&str
, opP
);
1380 opP
->error
= "Missing )";
1395 opP
->con2
= add_exp (beg_str
, str
- 2);
1399 if (opP
->ireg
!= FAIL
)
1401 opP
->error
= "Can't have two index regs";
1405 i
= try_index (&str
, opP
);
1409 opP
->error
= "malformed index reg";
1415 else if (opP
->ireg
!= FAIL
)
1431 opP
->error
= "Junk after indirect";
1435 } /* m68k_ip_op() */
1438 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1440 #ifdef NO_PCREL_RELOCS
1443 make_pcrel_absolute(fixP
, add_number
)
1447 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
1449 /* rewrite the PC relative instructions to absolute address ones.
1450 * these are rumoured to be faster, and the apollo linker refuses
1451 * to deal with the PC relative relocations.
1453 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
1458 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
1464 as_fatal ("Unknown PC relative instruction");
1469 #endif /* NO_PCREL_RELOCS */
1472 tc_coff_fix2rtype (fixP
)
1475 #ifdef NO_PCREL_RELOCS
1476 know (fixP
->fx_pcrel
== 0);
1477 return (fixP
->fx_size
== 1 ? R_RELBYTE
1478 : fixP
->fx_size
== 2 ? R_DIR16
1481 return (fixP
->fx_pcrel
?
1482 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
1483 fixP
->fx_size
== 2 ? R_PCRWORD
:
1485 (fixP
->fx_size
== 1 ? R_RELBYTE
:
1486 fixP
->fx_size
== 2 ? R_RELWORD
:
1493 #ifdef BFD_ASSEMBLER
1496 tc_gen_reloc (section
, fixp
)
1501 bfd_reloc_code_real_type code
;
1503 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1504 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1506 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1507 MAP (1, 0, BFD_RELOC_8
);
1508 MAP (2, 0, BFD_RELOC_16
);
1509 MAP (4, 0, BFD_RELOC_32
);
1510 MAP (1, 1, BFD_RELOC_8_PCREL
);
1511 MAP (2, 1, BFD_RELOC_16_PCREL
);
1512 MAP (4, 1, BFD_RELOC_32_PCREL
);
1517 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1518 assert (reloc
!= 0);
1519 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1520 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1522 reloc
->addend
= fixp
->fx_addnumber
;
1526 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1527 assert (reloc
->howto
!= 0);
1532 #endif /* BFD_ASSEMBLER */
1534 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1538 struct m68k_op thark
;
1544 memset (&thark
, '\0', sizeof (thark
));
1545 if (!m68k_ip_op (buf
, &thark
))
1548 printf ("op1 error %s in %s\n", thark
.error
, buf
);
1549 printf ("mode %d, reg %d, ", thark
.mode
, thark
.reg
);
1551 printf ("Constant: '%.*s',", 1 + thark
.e_const
- thark
.b_const
, thark
.b_const
);
1552 printf ("ireg %d, isiz %d, imul %d ", thark
.ireg
, thark
.isiz
, thark
.imul
);
1554 printf ("Iadd: '%.*s'", 1 + thark
.e_iadd
- thark
.b_iadd
, thark
.b_iadd
);
1563 /* Handle of the OPCODE hash table. NULL means any use before
1564 m68k_ip_begin() will crash. */
1565 static struct hash_control
*op_hash
;
1571 * This converts a string into a 68k instruction.
1572 * The string must be a bare single instruction in sun format
1573 * with RMS-style 68020 indirects
1576 * It provides some error messages: at most one fatal error message (which
1577 * stops the scan) and at most one warning message for each operand.
1578 * The 68k instruction is returned in exploded form, since we have no
1579 * knowledge of how you parse (or evaluate) your expressions.
1580 * We do however strip off and decode addressing modes and operation
1583 * This function's value is a string. If it is not "" then an internal
1584 * logic error was found: read this code to assign meaning to the string.
1585 * No argument string should generate such an error string:
1586 * it means a bug in our code, not in the user's text.
1588 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1592 /* JF this function no longer returns a useful value. Sorry */
1598 register struct m68k_op
*opP
;
1599 register struct m68k_incant
*opcode
;
1601 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1602 char *pdot
, *pdotmove
;
1607 char *crack_operand ();
1608 LITTLENUM_TYPE words
[6];
1609 LITTLENUM_TYPE
*wordp
;
1610 unsigned long ok_arch
= 0;
1612 if (*instring
== ' ')
1613 instring
++; /* skip leading whitespace */
1615 /* Scan up to end of operation-code, which MUST end in end-of-string
1616 or exactly 1 space. */
1618 for (p
= instring
; *p
!= '\0'; p
++)
1628 the_ins
.error
= "No operator";
1629 the_ins
.opcode
[0] = 0;
1630 /* the_ins.numo=1; */
1634 /* p now points to the end of the opcode name, probably whitespace.
1635 make sure the name is null terminated by clobbering the whitespace,
1636 look it up in the hash table, then fix it back.
1637 Remove a dot, first, since the opcode tables have none. */
1640 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1641 *pdotmove
= pdotmove
[1];
1647 opcode
= (struct m68k_incant
*) hash_find (op_hash
, instring
);
1652 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1653 *pdotmove
= pdotmove
[-1];
1660 the_ins
.error
= "Unknown operator";
1661 the_ins
.opcode
[0] = 0;
1662 /* the_ins.numo=1; */
1666 /* found a legitimate opcode, start matching operands */
1671 if (opcode
->m_operands
== 0)
1673 char *old
= input_line_pointer
;
1675 input_line_pointer
= p
;
1676 /* Ahh - it's a motorola style psuedo op */
1677 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1678 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1679 input_line_pointer
= old
;
1685 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1688 p
= crack_operand (p
, opP
);
1692 the_ins
.error
= opP
->error
;
1697 opsfound
= opP
- &the_ins
.operands
[0];
1699 /* This ugly hack is to support the floating pt opcodes in their standard form */
1700 /* Essentially, we fake a first enty of type COP#1 */
1701 if (opcode
->m_operands
[0] == 'I')
1705 for (n
= opsfound
; n
> 0; --n
)
1706 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1708 memset ((char *) (&the_ins
.operands
[0]), '\0', sizeof (the_ins
.operands
[0]));
1709 the_ins
.operands
[0].mode
= MSCR
;
1710 the_ins
.operands
[0].reg
= COPNUM
; /* COP #1 */
1714 /* We've got the operands. Find an opcode that'll accept them */
1717 /* If we didn't get the right number of ops, or we have no
1718 common model with this pattern then reject this pattern. */
1720 if (opsfound
!= opcode
->m_opnum
1721 || ((opcode
->m_arch
& current_architecture
) == 0))
1724 ok_arch
|= opcode
->m_arch
;
1728 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0]; *s
&& !losing
; s
+= 2, opP
++)
1730 /* Warning: this switch is huge! */
1731 /* I've tried to organize the cases into this order:
1732 non-alpha first, then alpha by letter. Lower-case
1733 goes directly before uppercase counterpart. */
1734 /* Code with multiple case ...: gets sorted by the lowest
1735 case ... it belongs to. I hope this makes sense. */
1739 if (opP
->mode
== MSCR
|| opP
->mode
== IMMED
1740 || opP
->mode
== DREG
|| opP
->mode
== AREG
1741 || opP
->mode
== AINC
|| opP
->mode
== ADEC
1742 || opP
->mode
== REGLST
)
1764 if (opP
->mode
!= IMMED
)
1770 t
= get_num (opP
->con1
, 80);
1771 if (s
[1] == 'b' && !isbyte (t
))
1773 else if (s
[1] == 'w' && !isword (t
))
1780 if (opP
->mode
!= IMMED
)
1785 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1786 opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1791 if (opP
->mode
== MSCR
|| opP
->reg
== PC
||
1792 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1798 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1799 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
||
1800 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== REGLST
)
1805 if (opP
->mode
== MSCR
|| opP
->mode
== REGLST
)
1810 if (opP
->mode
!= AINC
)
1815 if (opP
->mode
!= ADEC
)
1820 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1821 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1826 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
|| opP
->mode
== REGLST
)
1831 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1832 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->reg
== PC
||
1833 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1838 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1839 opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1843 case '~': /* For now! (JF FOO is this right?) */
1844 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1845 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1850 if (opP
->mode
!= MSCR
|| (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1855 if (opP
->mode
!= AREG
)
1859 if (opP
->mode
!= AINDR
)
1862 } /* if not address register indirect */
1865 if (opP
->mode
!= ABSL
|| (flagseen
['S'] && instring
[0] == 'j'
1866 && instring
[1] == 'b'
1867 && instring
[2] == 's'
1868 && instring
[3] == 'r'))
1873 if (opP
->mode
!= MSCR
|| opP
->reg
!= CCR
)
1877 case 'd': /* FOO This mode is a KLUDGE!! */
1878 if (opP
->mode
!= AOFF
&& (opP
->mode
!= ABSL
||
1879 opP
->con1
->e_beg
[0] != '(' || opP
->con1
->e_end
[0] != ')'))
1884 if (opP
->mode
!= DREG
)
1889 if (opP
->mode
!= MSCR
|| opP
->reg
< (FPREG
+ 0) || opP
->reg
> (FPREG
+ 7))
1894 if (opP
->mode
!= MSCR
|| opP
->reg
< COPNUM
||
1895 opP
->reg
>= COPNUM
+ 7)
1900 if (opP
->mode
!= MSCR
1902 || opP
->reg
> last_movec_reg
)
1907 for (rp
= control_regs
; *rp
; rp
++)
1908 if (*rp
== opP
->reg
)
1916 if (opP
->mode
!= IMMED
)
1922 if (opP
->mode
== DREG
|| opP
->mode
== AREG
|| opP
->mode
== FPREG
)
1929 opP
->reg
= 1 << (opP
->reg
- DATA
);
1932 else if (opP
->mode
!= REGLST
)
1936 else if (s
[1] == '8' && opP
->reg
& 0x0FFffFF)
1938 else if (s
[1] == '3' && opP
->reg
& 0x7000000)
1943 if (opP
->mode
!= IMMED
)
1949 t
= get_num (opP
->con1
, 0);
1951 || isvar (opP
->con1
))
1957 if (opP
->mode
!= DREG
&& opP
->mode
!= IMMED
)
1962 if (opP
->mode
!= IMMED
)
1968 t
= get_num (opP
->con1
, 80);
1969 if (t
< 1 || t
> 8 || isvar (opP
->con1
))
1975 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1980 if (opP
->mode
!= AINDR
&& opP
->mode
!= DINDR
)
1985 if (opP
->mode
!= MSCR
|| !(opP
->reg
== FPI
|| opP
->reg
== FPS
|| opP
->reg
== FPC
))
1990 if (opP
->mode
!= MSCR
|| opP
->reg
!= SR
)
1995 if (opP
->mode
!= IMMED
)
1999 long t
= get_num (opP
->con1
, 80);
2000 if (t
< 0 || t
> 7 || isvar (opP
->con1
))
2006 if (opP
->mode
!= MSCR
|| opP
->reg
!= USP
)
2010 /* JF these are out of order. We could put them
2011 in order if we were willing to put up with
2012 bunches of #ifdef m68851s in the code.
2014 Don't forget that you need these operands
2015 to use 68030 MMU instructions. */
2017 /* Memory addressing mode used by pflushr */
2019 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
2020 opP
->mode
== AREG
|| opP
->mode
== REGLST
)
2025 if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2030 if (opP
->mode
!= MSCR
2031 || (opP
->reg
!= TC
&& opP
->reg
!= CAL
2032 && opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
2037 if (opP
->reg
!= VAL
)
2042 if (opP
->mode
!= MSCR
2043 || (opP
->reg
!= DRP
&& opP
->reg
!= SRP
2044 && opP
->reg
!= CRP
))
2049 if (opP
->mode
!= MSCR
||
2050 (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7) &&
2051 !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2056 if (opP
->reg
!= PSR
)
2061 if (opP
->reg
!= PCSR
)
2072 } /* not a cache specifier. */
2076 if (opP
->mode
!= ABSL
)
2079 } /* not absolute */
2083 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2084 *s
, __LINE__
, __FILE__
);
2085 } /* switch on type of operand */
2089 } /* for each operand */
2090 } /* if immediately wrong */
2097 opcode
= opcode
->m_next
;
2102 && !(ok_arch
& current_architecture
))
2106 strcpy (buf
, "invalid instruction for this architecture; needs ");
2107 cp
= buf
+ strlen (buf
);
2111 strcpy (cp
, "fpu (68040, 68060 or 68881/68882)");
2114 strcpy (cp
, "mmu (68030 or 68851)");
2117 strcpy (cp
, "68020 or higher");
2120 strcpy (cp
, "68000 or higher");
2123 strcpy (cp
, "68010 or higher");
2127 int got_one
= 0, idx
;
2135 { m68000
, "68000" },
2136 { m68010
, "68010" },
2137 { m68020
, "68020" },
2138 { m68030
, "68030" },
2139 { m68040
, "68040" },
2140 { m68060
, "68060" },
2142 { m68881
, "68881" },
2145 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]); idx
++)
2147 if (archs
[idx
].arch
& ok_arch
)
2151 strcpy (cp
, " or ");
2155 strcpy (cp
, archs
[idx
].name
);
2167 the_ins
.error
= "operands mismatch";
2169 } /* Fell off the end */
2174 /* now assemble it */
2176 the_ins
.args
= opcode
->m_operands
;
2177 the_ins
.numargs
= opcode
->m_opnum
;
2178 the_ins
.numo
= opcode
->m_codenum
;
2179 the_ins
.opcode
[0] = getone (opcode
);
2180 the_ins
.opcode
[1] = gettwo (opcode
);
2182 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2184 /* This switch is a doozy.
2185 Watch the first step; its a big one! */
2206 tmpreg
= 0x3c; /* 7.4 */
2207 if (strchr ("bwl", s
[1]))
2208 nextword
= get_num (opP
->con1
, 80);
2210 nextword
= get_num (opP
->con1
, 0);
2211 if (isvar (opP
->con1
))
2212 add_fix (s
[1], opP
->con1
, 0);
2216 if (!isbyte (nextword
))
2217 opP
->error
= "operand out of range";
2222 if (!isword (nextword
))
2223 opP
->error
= "operand out of range";
2228 addword (nextword
>> 16);
2250 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2251 *s
, s
[1], __LINE__
, __FILE__
);
2256 /* We gotta put out some float */
2257 if (op (opP
->con1
) != O_big
)
2262 /* Can other cases happen here? */
2263 if (op (opP
->con1
) != O_constant
)
2266 val
= (valueT
) offs (opP
->con1
);
2270 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2271 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2275 offs (opP
->con1
) = gencnt
;
2277 if (offs (opP
->con1
) > 0)
2279 if (offs (opP
->con1
) > baseo
)
2281 as_warn ("Bignum too big for %c format; truncated", s
[1]);
2282 offs (opP
->con1
) = baseo
;
2284 baseo
-= offs (opP
->con1
);
2287 for (wordp
= generic_bignum
+ offs (opP
->con1
) - 1; offs (opP
->con1
)--; --wordp
)
2291 gen_to_words (words
, baseo
, (long) outro
);
2292 for (wordp
= words
; baseo
--; wordp
++)
2296 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2299 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2302 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2305 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2308 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2312 nextword
= get_num (opP
->con1
, 80);
2313 /* Force into index mode. Hope this works */
2315 /* We do the first bit for 32-bit displacements, and the
2316 second bit for 16 bit ones. It is possible that we
2317 should make the default be WORD instead of LONG, but
2318 I think that'd break GCC, so we put up with a little
2319 inefficiency for the sake of working output. */
2321 if (!issword (nextword
)
2322 || (isvar (opP
->con1
)
2323 && ((opP
->con1
->e_siz
== 0
2324 && flagseen
['l'] == 0)
2325 || opP
->con1
->e_siz
== 3)))
2329 tmpreg
= 0x3B; /* 7.3 */
2331 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2332 if (isvar (opP
->con1
))
2337 opP
->con1
->e_exp
.X_add_number
+= 6;
2338 add_fix ('l', opP
->con1
, 1);
2339 addword (0), addword (0);
2345 add_fix ('l', opP
->con1
, 0);
2350 addword (nextword
>> 16);
2355 tmpreg
= 0x3A; /* 7.2 */
2357 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2359 if (isvar (opP
->con1
))
2363 opP
->con1
->e_exp
.X_add_number
+= 2;
2364 add_fix ('w', opP
->con1
, 1);
2367 add_fix ('w', opP
->con1
, 0);
2376 know (current_architecture
& m68020up
);
2377 /* intentional fall-through */
2380 baseo
= get_num (opP
->con1
, 80);
2381 outro
= get_num (opP
->con2
, 80);
2382 /* Figure out the `addressing mode'.
2383 Also turn on the BASE_DISABLE bit, if needed. */
2384 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2386 tmpreg
= 0x3b;/* 7.3 */
2387 if (opP
->reg
== ZPC
)
2390 else if (opP
->reg
== FAIL
)
2393 tmpreg
= 0x30;/* 6.garbage */
2396 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2398 siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
2399 siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
2401 /* Index register stuff */
2402 if (opP
->ireg
>= DATA
+ 0 && opP
->ireg
<= ADDR
+ 7)
2404 nextword
|= (opP
->ireg
- DATA
) << 12;
2406 if (opP
->isiz
== 0 || opP
->isiz
== 3)
2422 as_fatal ("failed sanity check.");
2425 GET US OUT OF HERE! */
2427 /* Must be INDEX, with an index
2428 register. Address register
2429 cannot be ZERO-PC, and either
2430 :b was forced, or we know
2432 if (opP
->mode
== AINDX
2437 && !isvar (opP
->con1
))))
2439 nextword
+= baseo
& 0xff;
2441 if (isvar (opP
->con1
))
2442 add_fix ('B', opP
->con1
, 0);
2447 nextword
|= 0x40; /* No index reg */
2449 /* It isn't simple. */
2451 /* If the guy specified a width, we assume that it is
2452 wide enough. Maybe it isn't. If so, we lose. */
2456 if (isvar (opP
->con1
) || !issword (baseo
))
2461 else if (baseo
== 0)
2470 as_warn ("Byte dispacement won't work. Defaulting to :w");
2479 /* Figure out innner displacement stuff */
2480 if (opP
->mode
!= AINDX
)
2485 if (isvar (opP
->con2
) || !issword (outro
))
2490 else if (outro
== 0)
2499 as_warn ("Byte dispacement won't work. Defaulting to :w");
2507 if (opP
->mode
== APODX
)
2509 else if (opP
->mode
== AMIND
)
2514 if (isvar (opP
->con1
))
2516 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2518 opP
->con1
->e_exp
.X_add_number
+= 6;
2519 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 1);
2522 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 0);
2525 addword (baseo
>> 16);
2529 if (isvar (opP
->con2
))
2531 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2533 opP
->con1
->e_exp
.X_add_number
+= 6;
2534 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 1);
2537 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 0);
2540 addword (outro
>> 16);
2547 nextword
= get_num (opP
->con1
, 80);
2548 switch (opP
->con1
->e_siz
)
2551 as_warn ("Unknown size for absolute reference");
2553 if (!isvar (opP
->con1
) && issword (offs (opP
->con1
)))
2555 tmpreg
= 0x38; /* 7.0 */
2559 /* Don't generate pc relative code on 68010 and
2561 if (isvar (opP
->con1
)
2562 && !subs (opP
->con1
)
2563 && seg (opP
->con1
) == text_section
2564 && now_seg
== text_section
2565 && cpu_of_arch (current_architecture
) >= m68020
2567 && !strchr ("~%&$?", s
[0]))
2569 tmpreg
= 0x3A; /* 7.2 */
2570 add_frag (adds (opP
->con1
),
2572 TAB (PCREL
, SZ_UNDEF
));
2575 case 3: /* Fall through into long */
2576 if (isvar (opP
->con1
))
2577 add_fix ('l', opP
->con1
, 0);
2579 tmpreg
= 0x39;/* 7.1 mode */
2580 addword (nextword
>> 16);
2585 if (isvar (opP
->con1
))
2586 add_fix ('w', opP
->con1
, 0);
2588 tmpreg
= 0x38;/* 7.0 mode */
2594 as_bad ("invalid indirect register");
2598 as_bad ("unknown/incorrect operand");
2601 install_gen_operand (s
[1], tmpreg
);
2607 { /* JF: I hate floating point! */
2622 tmpreg
= get_num (opP
->con1
, tmpreg
);
2623 if (isvar (opP
->con1
))
2624 add_fix (s
[1], opP
->con1
, 0);
2627 case 'b': /* Danger: These do no check for
2628 certain types of overflow.
2630 if (!isbyte (tmpreg
))
2631 opP
->error
= "out of range";
2632 insop (tmpreg
, opcode
);
2633 if (isvar (opP
->con1
))
2634 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2637 if (!isword (tmpreg
))
2638 opP
->error
= "out of range";
2639 insop (tmpreg
, opcode
);
2640 if (isvar (opP
->con1
))
2641 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2644 /* Because of the way insop works, we put these two out
2646 insop (tmpreg
, opcode
);
2647 insop (tmpreg
>> 16, opcode
);
2648 if (isvar (opP
->con1
))
2649 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2655 install_operand (s
[1], tmpreg
);
2658 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s
[1], __LINE__
, __FILE__
);
2666 install_operand (s
[1], opP
->reg
- ADDR
);
2670 tmpreg
= get_num (opP
->con1
, 80);
2674 /* Needs no offsetting */
2675 add_fix ('B', opP
->con1
, 1);
2678 /* Offset the displacement to be relative to byte disp location */
2679 opP
->con1
->e_exp
.X_add_number
+= 2;
2680 add_fix ('w', opP
->con1
, 1);
2685 if (cpu_of_arch (current_architecture
) < m68020
) /* 68000 or 010 */
2686 as_warn ("Can't use long branches on 68000/68010");
2687 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2688 /* Offset the displacement to be relative to byte disp location */
2689 opP
->con1
->e_exp
.X_add_number
+= 4;
2690 add_fix ('l', opP
->con1
, 1);
2695 if (subs (opP
->con1
)) /* We can't relax it */
2698 /* This could either be a symbol, or an
2699 absolute address. No matter, the
2700 frag hacking will finger it out.
2701 Not quite: it can't switch from
2702 BRANCH to BCC68000 for the case
2703 where opnd is absolute (it needs
2704 to use the 68000 hack since no
2705 conditional abs jumps). */
2706 if (((cpu_of_arch (current_architecture
) < m68020
) || (0 == adds (opP
->con1
)))
2707 && (the_ins
.opcode
[0] >= 0x6200)
2708 && (the_ins
.opcode
[0] <= 0x6f00))
2710 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (BCC68000
, SZ_UNDEF
));
2714 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (ABRANCH
, SZ_UNDEF
));
2718 if (isvar (opP
->con1
))
2721 /* check for DBcc instruction */
2722 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2724 /* size varies if patch */
2725 /* needed for long form */
2726 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (DBCC
, SZ_UNDEF
));
2731 opP
->con1
->e_exp
.X_add_number
+= 2;
2732 add_fix ('w', opP
->con1
, 1);
2736 case 'C': /* Fixed size LONG coproc branches */
2737 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2738 /* Offset the displacement to be relative to byte disp location */
2739 /* Coproc branches don't have a byte disp option, but they are
2740 compatible with the ordinary branches, which do... */
2741 opP
->con1
->e_exp
.X_add_number
+= 4;
2742 add_fix ('l', opP
->con1
, 1);
2746 case 'c': /* Var size Coprocesssor branches */
2747 if (subs (opP
->con1
))
2749 add_fix ('l', opP
->con1
, 1);
2750 add_frag ((symbolS
*) 0, (long) 0, TAB (FBRANCH
, LONG
));
2752 else if (adds (opP
->con1
))
2754 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (FBRANCH
, SZ_UNDEF
));
2758 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2759 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2760 add_fix ('l', opP
->con1
, 1);
2766 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2767 s
[1], __LINE__
, __FILE__
);
2771 case 'C': /* Ignore it */
2774 case 'd': /* JF this is a kludge */
2775 if (opP
->mode
== AOFF
)
2777 install_operand ('s', opP
->reg
- ADDR
);
2783 tmpP
= opP
->con1
->e_end
- 2;
2785 opP
->con1
->e_end
-= 4; /* point to the , */
2786 baseo
= m68k_reg_parse (&tmpP
);
2787 if (baseo
< ADDR
+ 0 || baseo
> ADDR
+ 7)
2789 as_bad ("Unknown address reg, using A0");
2794 install_operand ('s', baseo
);
2796 tmpreg
= get_num (opP
->con1
, 80);
2797 if (!issword (tmpreg
))
2799 as_warn ("Expression out of range, using 0");
2806 install_operand (s
[1], opP
->reg
- DATA
);
2810 install_operand (s
[1], opP
->reg
- FPREG
);
2814 tmpreg
= 1 + opP
->reg
- COPNUM
;
2817 install_operand (s
[1], tmpreg
);
2820 case 'J': /* JF foo */
2873 as_fatal ("failed sanity check.");
2875 install_operand (s
[1], tmpreg
);
2879 tmpreg
= get_num (opP
->con1
, 55);
2880 install_operand (s
[1], tmpreg
& 0x7f);
2887 if (tmpreg
& 0x7FF0000)
2888 as_bad ("Floating point register in register list");
2889 insop (reverse_16_bits (tmpreg
), opcode
);
2893 if (tmpreg
& 0x700FFFF)
2894 as_bad ("Wrong register in floating-point reglist");
2895 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2903 if (tmpreg
& 0x7FF0000)
2904 as_bad ("Floating point register in register list");
2905 insop (tmpreg
, opcode
);
2907 else if (s
[1] == '8')
2909 if (tmpreg
& 0x0FFFFFF)
2910 as_bad ("incorrect register in reglist");
2911 install_operand (s
[1], tmpreg
>> 24);
2915 if (tmpreg
& 0x700FFFF)
2916 as_bad ("wrong register in floating-point reglist");
2918 install_operand (s
[1], tmpreg
>> 16);
2923 install_operand (s
[1], get_num (opP
->con1
, 60));
2927 tmpreg
= (opP
->mode
== DREG
)
2928 ? 0x20 + opP
->reg
- DATA
2929 : (get_num (opP
->con1
, 40) & 0x1F);
2930 install_operand (s
[1], tmpreg
);
2934 tmpreg
= get_num (opP
->con1
, 10);
2937 install_operand (s
[1], tmpreg
);
2942 /* This depends on the fact that ADDR registers are
2943 eight more than their corresponding DATA regs, so
2944 the result will have the ADDR_REG bit set */
2945 install_operand (s
[1], opP
->reg
- DATA
);
2949 if (opP
->reg
== FPI
)
2951 else if (opP
->reg
== FPS
)
2953 else if (opP
->reg
== FPC
)
2956 as_fatal ("failed sanity check.");
2957 install_operand (s
[1], tmpreg
);
2960 case 'S': /* Ignore it */
2964 install_operand (s
[1], get_num (opP
->con1
, 30));
2967 case 'U': /* Ignore it */
2986 as_fatal ("failed sanity check");
2987 } /* switch on cache token */
2988 install_operand (s
[1], tmpreg
);
2991 /* JF: These are out of order, I fear. */
3002 as_fatal ("failed sanity check.");
3004 install_operand (s
[1], tmpreg
);
3026 as_fatal ("failed sanity check.");
3028 install_operand (s
[1], tmpreg
);
3032 if (opP
->reg
== VAL
)
3034 as_fatal ("failed sanity check.");
3050 as_fatal ("failed sanity check.");
3052 install_operand (s
[1], tmpreg
);
3066 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3077 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3081 as_fatal ("failed sanity check.");
3083 install_operand (s
[1], tmpreg
);
3086 know (opP
->reg
== PSR
);
3089 know (opP
->reg
== PCSR
);
3102 as_fatal ("failed sanity check");
3104 install_operand (s
[1], tmpreg
);
3107 tmpreg
= get_num (opP
->con1
, 20);
3108 install_operand (s
[1], tmpreg
);
3110 case '_': /* used only for move16 absolute 32-bit address */
3111 tmpreg
= get_num (opP
->con1
, 80);
3112 addword (tmpreg
>> 16);
3113 addword (tmpreg
& 0xFFFF);
3116 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3117 s
[0], __LINE__
, __FILE__
);
3121 /* By the time whe get here (FINALLY) the_ins contains the complete
3122 instruction, ready to be emitted. . . */
3126 * get_regs := '/' + ?
3127 * | '-' + <register>
3128 * | '-' + <register> + ?
3133 * The idea here must be to scan in a set of registers but I don't
3134 * understand it. Looks awfully sloppy to me but I don't have any doc on
3142 get_regs (i
, str
, opP
)
3144 struct m68k_op
*opP
;
3147 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3148 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3149 unsigned long cur_regs
= 0;
3152 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3153 else if(x==FPS) cur_regs|=(1<<25);\
3154 else if(x==FPC) cur_regs|=(1<<26);\
3155 else cur_regs|=(1<<(x-1)); }
3165 else if (*str
== '-')
3168 reg2
= m68k_reg_parse (&str
);
3169 if (reg2
< DATA
|| reg2
>= FPREG
+ 8 || reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
)
3171 opP
->error
= "unknown register in register list";
3174 while (reg1
<= reg2
)
3182 else if (*str
== '\0')
3189 opP
->error
= "unknow character in register list";
3192 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3195 reg1
= m68k_reg_parse (&str
);
3196 if ((reg1
< DATA
|| reg1
>= FPREG
+ 8) && !(reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
))
3198 opP
->error
= "unknown register in register list";
3202 opP
->reg
= cur_regs
;
3207 reverse_16_bits (in
)
3213 static int mask
[16] =
3215 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3216 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3218 for (n
= 0; n
< 16; n
++)
3221 out
|= mask
[15 - n
];
3224 } /* reverse_16_bits() */
3233 static int mask
[8] =
3235 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3238 for (n
= 0; n
< 8; n
++)
3244 } /* reverse_8_bits() */
3247 install_operand (mode
, val
)
3254 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
3257 the_ins
.opcode
[0] |= val
<< 9;
3260 the_ins
.opcode
[1] |= val
<< 12;
3263 the_ins
.opcode
[1] |= val
<< 6;
3266 the_ins
.opcode
[1] |= val
;
3269 the_ins
.opcode
[2] |= val
<< 12;
3272 the_ins
.opcode
[2] |= val
<< 6;
3275 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3276 three words long! */
3278 the_ins
.opcode
[2] |= val
;
3281 the_ins
.opcode
[1] |= val
<< 7;
3284 the_ins
.opcode
[1] |= val
<< 10;
3288 the_ins
.opcode
[1] |= val
<< 5;
3293 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3296 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3299 the_ins
.opcode
[0] |= val
= 0xff;
3302 the_ins
.opcode
[0] |= val
<< 9;
3305 the_ins
.opcode
[1] |= val
;
3308 the_ins
.opcode
[1] |= val
;
3309 the_ins
.numo
++; /* What a hack */
3312 the_ins
.opcode
[1] |= val
<< 4;
3319 the_ins
.opcode
[0] |= (val
<< 6);
3322 the_ins
.opcode
[1] = (val
>> 16);
3323 the_ins
.opcode
[2] = val
& 0xffff;
3327 as_fatal ("failed sanity check.");
3329 } /* install_operand() */
3332 install_gen_operand (mode
, val
)
3339 the_ins
.opcode
[0] |= val
;
3342 /* This is a kludge!!! */
3343 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3352 the_ins
.opcode
[0] |= val
;
3354 /* more stuff goes here */
3356 as_fatal ("failed sanity check.");
3358 } /* install_gen_operand() */
3361 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3362 * then deal with the bitfield hack.
3366 crack_operand (str
, opP
)
3368 register struct m68k_op
*opP
;
3370 register int parens
;
3372 register char *beg_str
;
3379 for (parens
= 0; *str
&& (parens
> 0 || notend (str
)); str
++)
3383 else if (*str
== ')')
3387 opP
->error
= "Extra )";
3393 if (!*str
&& parens
)
3395 opP
->error
= "Missing )";
3400 if (m68k_ip_op (beg_str
, opP
) == FAIL
)
3407 c
= *++str
; /* JF bitfield hack */
3412 as_bad ("Missing operand");
3417 /* See the comment up above where the #define notend(... is */
3424 if (*s
== '{' || *s
== '}')
3428 /* This kludge here is for the division cmd, which is a kludge */
3429 if (index ("aAdD#", s
[1]))
3436 /* This is the guts of the machine-dependent assembler. STR points to a
3437 machine dependent instruction. This function is supposed to emit
3438 the frags/bytes it assembles to.
3442 insert_reg (regname
, regnum
)
3449 #ifdef REGISTER_PREFIX
3450 if (!flag_reg_prefix_optional
)
3452 buf
[0] = REGISTER_PREFIX
;
3453 strcpy (buf
+ 1, regname
);
3458 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3459 &zero_address_frag
));
3461 for (i
= 0; regname
[i
]; i
++)
3462 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3465 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3466 &zero_address_frag
));
3475 static const struct init_entry init_table
[] =
3577 /* 68ec030 versions of same */
3580 /* 68ec030 access control unit, identical to 030 MMU status reg */
3590 for (i
= 0; init_table
[i
].name
; i
++)
3591 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3594 static int no_68851
, no_68881
;
3597 /* a.out machine type. Default to 68020. */
3598 int m68k_aout_machtype
= 2;
3610 int shorts_this_frag
;
3612 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3617 for (n
= the_ins
.numargs
; n
; --n
)
3618 if (the_ins
.operands
[n
].error
)
3620 er
= the_ins
.operands
[n
].error
;
3626 as_bad ("%s -- statement `%s' ignored", er
, str
);
3630 if (the_ins
.nfrag
== 0)
3632 /* No frag hacking involved; just put it out */
3633 toP
= frag_more (2 * the_ins
.numo
);
3634 fromP
= &the_ins
.opcode
[0];
3635 for (m
= the_ins
.numo
; m
; --m
)
3637 md_number_to_chars (toP
, (long) (*fromP
), 2);
3641 /* put out symbol-dependent info */
3642 for (m
= 0; m
< the_ins
.nrel
; m
++)
3644 switch (the_ins
.reloc
[m
].wid
)
3662 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3663 the_ins
.reloc
[m
].wid
);
3666 fix_new_exp (frag_now
,
3667 ((toP
- frag_now
->fr_literal
)
3668 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3670 &the_ins
.reloc
[m
].exp
,
3671 the_ins
.reloc
[m
].pcrel
,
3677 /* There's some frag hacking */
3678 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3683 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3685 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3686 toP
= frag_more (wid
);
3688 shorts_this_frag
= 0;
3689 for (m
= wid
/ 2; m
; --m
)
3691 md_number_to_chars (toP
, (long) (*fromP
), 2);
3696 for (m
= 0; m
< the_ins
.nrel
; m
++)
3698 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3700 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3703 wid
= the_ins
.reloc
[m
].wid
;
3706 the_ins
.reloc
[m
].wid
= 0;
3707 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3709 fix_new_exp (frag_now
,
3710 ((toP
- frag_now
->fr_literal
)
3711 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3713 &the_ins
.reloc
[m
].exp
,
3714 the_ins
.reloc
[m
].pcrel
,
3717 (void) frag_var (rs_machine_dependent
, 10, 0,
3718 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3719 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3721 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3722 shorts_this_frag
= 0;
3725 toP
= frag_more (n
* sizeof (short));
3728 md_number_to_chars (toP
, (long) (*fromP
), 2);
3734 for (m
= 0; m
< the_ins
.nrel
; m
++)
3738 wid
= the_ins
.reloc
[m
].wid
;
3741 the_ins
.reloc
[m
].wid
= 0;
3742 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3744 fix_new_exp (frag_now
,
3745 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3746 - shorts_this_frag
* 2),
3748 &the_ins
.reloc
[m
].exp
,
3749 the_ins
.reloc
[m
].pcrel
,
3754 /* See BREAK_UP_BIG_DECL definition, above. */
3755 static struct m68k_opcode
*
3759 #ifdef DO_BREAK_UP_BIG_DECL
3760 int lim1
= sizeof (m68k_opcodes
) / sizeof (m68k_opcodes
[0]);
3762 return m68k_opcodes_2
+ (i
- lim1
);
3764 return m68k_opcodes
+ i
;
3771 * md_begin -- set up hash tables with 68000 instructions.
3772 * similar to what the vax assembler does. ---phr
3774 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3775 a copy of it at runtime, adding in the information we want but isn't
3776 there. I think it'd be better to have an awk script hack the table
3777 at compile time. Or even just xstr the table and use it as-is. But
3778 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3781 register CONST
struct m68k_opcode
*ins
;
3782 register struct m68k_incant
*hack
, *slak
;
3783 register const char *retval
= 0; /* empty string, or error msg text */
3784 register unsigned int i
;
3787 op_hash
= hash_new ();
3789 obstack_begin (&robyn
, 4000);
3790 for (i
= 0; i
< numopcodes
; i
++)
3792 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3795 ins
= opcode_ptr (i
);
3796 /* We *could* ignore insns that don't match our arch here
3797 but just leaving them out of the hash. */
3798 slak
->m_operands
= ins
->args
;
3799 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3800 slak
->m_arch
= ins
->arch
;
3801 slak
->m_opcode
= ins
->opcode
;
3802 /* This is kludgey */
3803 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3804 if (i
+ 1 != numopcodes
3805 && !strcmp (ins
->name
, opcode_ptr (i
+ 1)->name
))
3807 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3812 slak
= slak
->m_next
;
3816 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3818 as_bad ("Internal Error: Can't hash %s: %s", ins
->name
, retval
);
3821 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3822 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3824 for (i
= 0; i
< sizeof (notend_table
); i
++)
3826 notend_table
[i
] = 0;
3827 alt_notend_table
[i
] = 0;
3829 notend_table
[','] = 1;
3830 notend_table
['{'] = 1;
3831 notend_table
['}'] = 1;
3832 alt_notend_table
['a'] = 1;
3833 alt_notend_table
['A'] = 1;
3834 alt_notend_table
['d'] = 1;
3835 alt_notend_table
['D'] = 1;
3836 alt_notend_table
['#'] = 1;
3837 alt_notend_table
['f'] = 1;
3838 alt_notend_table
['F'] = 1;
3839 #ifdef REGISTER_PREFIX
3840 alt_notend_table
[REGISTER_PREFIX
] = 1;
3843 #ifndef MIT_SYNTAX_ONLY
3844 /* Insert pseudo ops, these have to go into the opcode table since
3845 gas expects pseudo ops to start with a dot */
3848 while (mote_pseudo_table
[n
].poc_name
)
3850 hack
= (struct m68k_incant
*)
3851 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3852 hash_insert (op_hash
,
3853 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3854 hack
->m_operands
= 0;
3865 m68k_init_after_args ()
3867 if (cpu_of_arch (current_architecture
) == 0)
3871 if (strcmp (TARGET_CPU
, "m68000") == 0
3872 || strcmp (TARGET_CPU
, "m68302") == 0)
3874 else if (strcmp (TARGET_CPU
, "m68010") == 0)
3876 else if (strcmp (TARGET_CPU
, "m68020") == 0
3877 || strcmp (TARGET_CPU
, "m68k") == 0)
3879 else if (strcmp (TARGET_CPU
, "m68030") == 0)
3881 else if (strcmp (TARGET_CPU
, "m68040") == 0)
3883 else if (strcmp (TARGET_CPU
, "m68060") == 0)
3885 else if (strcmp (TARGET_CPU
, "cpu32") == 0
3886 || strcmp (TARGET_CPU
, "m68331") == 0
3887 || strcmp (TARGET_CPU
, "m68332") == 0
3888 || strcmp (TARGET_CPU
, "m68333") == 0
3889 || strcmp (TARGET_CPU
, "m68340") == 0)
3894 current_architecture
|= cpu_type
;
3896 #if 0 /* Could be doing emulation. */
3897 if (current_architecture
& m68881
)
3899 if (current_architecture
& m68000
)
3900 as_bad ("incompatible processors 68000 and 68881/2 specified");
3901 if (current_architecture
& m68010
)
3902 as_bad ("incompatible processors 68010 and 68881/2 specified");
3903 if (current_architecture
& m68040
)
3904 as_bad ("incompatible processors 68040 and 68881/2 specified");
3907 if (current_architecture
& m68851
)
3909 if (current_architecture
& m68040
)
3911 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3914 /* What other incompatibilities could we check for? */
3916 /* Toss in some default assumptions about coprocessors. */
3918 && (cpu_of_arch (current_architecture
)
3919 /* Can CPU32 have a 68881 coprocessor?? */
3920 & (m68020
| m68030
| cpu32
)))
3922 current_architecture
|= m68881
;
3925 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3926 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
3928 current_architecture
|= m68851
;
3930 if (no_68881
&& (current_architecture
& m68881
))
3931 as_bad ("options for 68881 and no-68881 both given");
3932 if (no_68851
&& (current_architecture
& m68851
))
3933 as_bad ("options for 68851 and no-68851 both given");
3936 /* Work out the magic number. This isn't very general. */
3937 if (current_architecture
& m68000
)
3938 m68k_aout_machtype
= 0;
3939 else if (current_architecture
& m68010
)
3940 m68k_aout_machtype
= 1;
3941 else if (current_architecture
& m68020
)
3942 m68k_aout_machtype
= 2;
3944 m68k_aout_machtype
= 2;
3947 /* Note which set of "movec" control registers is available. */
3948 switch (cpu_of_arch (current_architecture
))
3951 control_regs
= m68000_control_regs
;
3954 control_regs
= m68010_control_regs
;
3958 control_regs
= m68020_control_regs
;
3961 control_regs
= m68040_control_regs
;
3964 control_regs
= m68060_control_regs
;
3972 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3973 || (*s == ':' && strchr("aAdD#", s[1]))) \
3977 /* Equal to MAX_PRECISION in atof-ieee.c */
3978 #define MAX_LITTLENUMS 6
3980 /* Turn a string in input_line_pointer into a floating point constant of type
3981 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3982 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3985 md_atof (type
, litP
, sizeP
)
3991 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3992 LITTLENUM_TYPE
*wordP
;
4024 return "Bad call to MD_ATOF()";
4026 t
= atof_ieee (input_line_pointer
, type
, words
);
4028 input_line_pointer
= t
;
4030 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4031 for (wordP
= words
; prec
--;)
4033 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4034 litP
+= sizeof (LITTLENUM_TYPE
);
4040 md_number_to_chars (buf
, val
, n
)
4045 number_to_chars_bigendian (buf
, val
, n
);
4049 md_apply_fix_2 (fixP
, val
)
4053 unsigned long upper_limit
;
4056 #ifdef IBM_COMPILER_SUX
4057 /* This is unnecessary but it convinces the native rs6000
4058 compiler to generate the code we want. */
4059 char *buf
= fixP
->fx_frag
->fr_literal
;
4060 buf
+= fixP
->fx_where
;
4061 #else /* IBM_COMPILER_SUX */
4062 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4063 #endif /* IBM_COMPILER_SUX */
4065 switch (fixP
->fx_size
)
4070 lower_limit
= -0x80;
4073 *buf
++ = (val
>> 8);
4075 upper_limit
= 0x7fff;
4076 lower_limit
= -0x8000;
4079 *buf
++ = (val
>> 24);
4080 *buf
++ = (val
>> 16);
4081 *buf
++ = (val
>> 8);
4083 upper_limit
= 0x7fffffff;
4084 lower_limit
= -0x80000000;
4087 BAD_CASE (fixP
->fx_size
);
4090 /* For non-pc-relative values, it's conceivable we might get something
4091 like "0xff" for a byte field. So extend the upper part of the range
4092 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4093 so that we can do any range checking at all. */
4094 if (!fixP
->fx_pcrel
)
4095 upper_limit
= upper_limit
* 2 + 1;
4097 if ((unsigned) val
> upper_limit
&& (val
> 0 || val
< lower_limit
))
4098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "value out of range");
4100 /* A one byte PC-relative reloc means a short branch. We can't use
4101 a short branch with a value of 0 or -1, because those indicate
4102 different opcodes (branches with longer offsets). */
4104 && fixP
->fx_size
== 1
4105 && (fixP
->fx_addsy
== NULL
4106 || S_IS_DEFINED (fixP
->fx_addsy
))
4107 && (val
== 0 || val
== -1))
4108 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "invalid byte branch offset");
4111 #ifdef BFD_ASSEMBLER
4113 md_apply_fix (fixP
, valp
)
4117 md_apply_fix_2 (fixP
, *valp
);
4121 void md_apply_fix (fixP
, val
)
4125 md_apply_fix_2 (fixP
, val
);
4129 /* *fragP has been relaxed to its final size, and now needs to have
4130 the bytes inside it modified to conform to the new size There is UGLY
4134 md_convert_frag_1 (fragP
)
4135 register fragS
*fragP
;
4140 /* Address in object code of the displacement. */
4141 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4143 #ifdef IBM_COMPILER_SUX
4144 /* This is wrong but it convinces the native rs6000 compiler to
4145 generate the code we want. */
4146 register char *buffer_address
= fragP
->fr_literal
;
4147 buffer_address
+= fragP
->fr_fix
;
4148 #else /* IBM_COMPILER_SUX */
4149 /* Address in gas core of the place to store the displacement. */
4150 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4151 #endif /* IBM_COMPILER_SUX */
4153 /* No longer true: know(fragP->fr_symbol); */
4155 /* The displacement of the address, from current location. */
4156 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4157 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4159 switch (fragP
->fr_subtype
)
4161 case TAB (BCC68000
, BYTE
):
4162 case TAB (ABRANCH
, BYTE
):
4163 know (issbyte (disp
));
4165 as_bad ("short branch with zero offset: use :w");
4166 fragP
->fr_opcode
[1] = disp
;
4169 case TAB (DBCC
, SHORT
):
4170 know (issword (disp
));
4173 case TAB (BCC68000
, SHORT
):
4174 case TAB (ABRANCH
, SHORT
):
4175 know (issword (disp
));
4176 fragP
->fr_opcode
[1] = 0x00;
4179 case TAB (ABRANCH
, LONG
):
4180 if (cpu_of_arch (current_architecture
) < m68020
)
4182 if (fragP
->fr_opcode
[0] == 0x61)
4184 fragP
->fr_opcode
[0] = 0x4E;
4185 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4186 subseg_change (text_section
, 0); /* @@ */
4199 else if (fragP
->fr_opcode
[0] == 0x60)
4201 fragP
->fr_opcode
[0] = 0x4E;
4202 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4203 subseg_change (text_section
, 0); /* @@ */
4204 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4205 fragP
->fr_offset
, 0, NO_RELOC
);
4211 as_bad ("Long branch offset not supported.");
4216 fragP
->fr_opcode
[1] = (char) 0xff;
4220 case TAB (BCC68000
, LONG
):
4221 /* only Bcc 68000 instructions can come here */
4222 /* change bcc into b!cc/jmp absl long */
4223 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4224 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4226 /* JF: these used to be fr_opcode[2,3], but they may be in a
4227 different frag, in which case refering to them is a no-no.
4228 Only fr_opcode[0,1] are guaranteed to work. */
4229 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4230 *buffer_address
++ = (char) 0xf9;
4231 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4232 subseg_change (text_section
, 0);
4233 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4234 fragP
->fr_offset
, 0, NO_RELOC
);
4238 case TAB (DBCC
, LONG
):
4239 /* only DBcc 68000 instructions can come here */
4240 /* change dbcc into dbcc/jmp absl long */
4241 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4242 *buffer_address
++ = 0x00; /* branch offset = 4 */
4243 *buffer_address
++ = 0x04;
4244 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4245 *buffer_address
++ = 0x06;
4246 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4247 *buffer_address
++ = (char) 0xf9;
4249 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4250 subseg_change (text_section
, 0);
4251 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4252 fragP
->fr_offset
, 0, NO_RELOC
);
4256 case TAB (FBRANCH
, SHORT
):
4257 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4260 case TAB (FBRANCH
, LONG
):
4261 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4264 case TAB (PCREL
, SHORT
):
4267 case TAB (PCREL
, LONG
):
4268 /* The thing to do here is force it to ABSOLUTE LONG, since
4269 PCREL is really trying to shorten an ABSOLUTE address anyway */
4270 /* JF FOO This code has not been tested */
4271 subseg_change (text_section
, 0);
4272 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4274 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4275 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4276 (unsigned) fragP
->fr_opcode
[0],
4277 (unsigned long) fragP
->fr_address
);
4278 fragP
->fr_opcode
[1] &= ~0x3F;
4279 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4283 case TAB (PCLEA
, SHORT
):
4284 subseg_change (text_section
, 0);
4285 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4286 fragP
->fr_offset
, 1, NO_RELOC
);
4287 fragP
->fr_opcode
[1] &= ~0x3F;
4288 fragP
->fr_opcode
[1] |= 0x3A;
4291 case TAB (PCLEA
, LONG
):
4292 subseg_change (text_section
, 0);
4293 fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
4294 fragP
->fr_offset
+ 2, 1, NO_RELOC
);
4295 *buffer_address
++ = 0x01;
4296 *buffer_address
++ = 0x70;
4304 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
4305 fragP
->fr_fix
+= ext
;
4309 #ifndef BFD_ASSEMBLER
4312 md_convert_frag (headers
, fragP
)
4313 object_headers
*headers
;
4316 md_convert_frag_1 (fragP
);
4322 md_convert_frag (abfd
, sec
, fragP
)
4327 md_convert_frag_1 (fragP
);
4331 /* Force truly undefined symbols to their maximum size, and generally set up
4332 the frag list to be relaxed
4335 md_estimate_size_before_relax (fragP
, segment
)
4336 register fragS
*fragP
;
4340 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4342 old_fix
= fragP
->fr_fix
;
4344 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4345 switch (fragP
->fr_subtype
)
4348 case TAB (ABRANCH
, SZ_UNDEF
):
4350 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
4351 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4353 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4356 else if ((fragP
->fr_symbol
== 0) || (cpu_of_arch (current_architecture
) < m68020
))
4358 /* On 68000, or for absolute value, switch to abs long */
4359 /* FIXME, we should check abs val, pick short or long */
4360 if (fragP
->fr_opcode
[0] == 0x61)
4362 fragP
->fr_opcode
[0] = 0x4E;
4363 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4364 subseg_change (text_section
, 0);
4365 fix_new (fragP
, fragP
->fr_fix
, 4,
4366 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4370 else if (fragP
->fr_opcode
[0] == 0x60)
4372 fragP
->fr_opcode
[0] = 0x4E;
4373 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4374 subseg_change (text_section
, 0);
4375 fix_new (fragP
, fragP
->fr_fix
, 4,
4376 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4382 as_warn ("Long branch offset to extern symbol not supported.");
4386 { /* Symbol is still undefined. Make it simple */
4387 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4388 fragP
->fr_offset
+ 4, 1, NO_RELOC
);
4390 fragP
->fr_opcode
[1] = (char) 0xff;
4396 } /* case TAB(ABRANCH,SZ_UNDEF) */
4398 case TAB (FBRANCH
, SZ_UNDEF
):
4400 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flagseen
['l'])
4402 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4407 fragP
->fr_subtype
= TAB (FBRANCH
, LONG
);
4411 } /* TAB(FBRANCH,SZ_UNDEF) */
4413 case TAB (PCREL
, SZ_UNDEF
):
4415 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flagseen
['l'])
4417 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4422 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4426 } /* TAB(PCREL,SZ_UNDEF) */
4428 case TAB (BCC68000
, SZ_UNDEF
):
4430 if ((fragP
->fr_symbol
!= NULL
)
4431 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4433 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4436 /* only Bcc 68000 instructions can come here */
4437 /* change bcc into b!cc/jmp absl long */
4438 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4441 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4442 /* JF: these were fr_opcode[2,3] */
4443 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4444 buffer_address
[1] = (char) 0xf8;
4445 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4446 subseg_change (text_section
, 0);
4447 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4448 fragP
->fr_offset
, 0, NO_RELOC
);
4453 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4454 /* JF: these were fr_opcode[2,3] */
4455 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4456 buffer_address
[1] = (char) 0xf9;
4457 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4458 subseg_change (text_section
, 0);
4459 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4460 fragP
->fr_offset
, 0, NO_RELOC
);
4465 } /* case TAB(BCC68000,SZ_UNDEF) */
4467 case TAB (DBCC
, SZ_UNDEF
):
4469 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4471 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4475 /* only DBcc 68000 instructions can come here */
4476 /* change dbcc into dbcc/jmp absl long */
4477 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4478 buffer_address
[0] = 0x00; /* branch offset = 4 */
4479 buffer_address
[1] = 0x04;
4480 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4484 /* JF: these were fr_opcode[5-7] */
4485 buffer_address
[3] = 0x04; /* plus 4 */
4486 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4487 buffer_address
[5] = (char) 0xf8;
4488 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4489 subseg_change (text_section
, 0);
4490 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4491 fragP
->fr_offset
, 0, NO_RELOC
);
4496 /* JF: these were fr_opcode[5-7] */
4497 buffer_address
[3] = 0x06; /* Plus 6 */
4498 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4499 buffer_address
[5] = (char) 0xf9;
4500 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4501 subseg_change (text_section
, 0);
4502 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4503 fragP
->fr_offset
, 0, NO_RELOC
);
4509 } /* case TAB(DBCC,SZ_UNDEF) */
4511 case TAB (PCLEA
, SZ_UNDEF
):
4513 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
|| flagseen
['l'])
4515 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4520 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4524 } /* TAB(PCLEA,SZ_UNDEF) */
4529 } /* switch on subtype looking for SZ_UNDEF's. */
4531 /* now that SZ_UNDEF are taken care of, check others */
4532 switch (fragP
->fr_subtype
)
4534 case TAB (BCC68000
, BYTE
):
4535 case TAB (ABRANCH
, BYTE
):
4536 /* We can't do a short jump to the next instruction,
4537 so we force word mode. */
4538 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0 &&
4539 fragP
->fr_symbol
->sy_frag
== fragP
->fr_next
)
4541 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4548 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4551 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4552 /* the bit-field entries in the relocation_info struct plays hell
4553 with the byte-order problems of cross-assembly. So as a hack,
4554 I added this mach. dependent ri twiddler. Ugly, but it gets
4556 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4557 are symbolnum, most sig. byte first. Last byte is broken up with
4558 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4559 nibble as nuthin. (on Sun 3 at least) */
4560 /* Translate the internal relocation information into target-specific
4564 md_ri_to_chars (the_bytes
, ri
)
4566 struct reloc_info_generic
*ri
;
4569 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4570 /* now the fun stuff */
4571 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4572 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4573 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4574 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4575 ((ri
->r_extern
<< 4) & 0x10));
4578 #endif /* comment */
4580 #ifndef BFD_ASSEMBLER
4582 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4585 relax_addressT segment_address_in_file
;
4588 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4589 * Out: GNU LD relocation length code: 0, 1, or 2.
4592 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4595 know (fixP
->fx_addsy
!= NULL
);
4597 md_number_to_chars (where
,
4598 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4601 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4602 ? S_GET_TYPE (fixP
->fx_addsy
)
4603 : fixP
->fx_addsy
->sy_number
);
4605 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4606 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4607 where
[6] = r_symbolnum
& 0x0ff;
4608 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4609 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4613 #endif /* OBJ_AOUT or OBJ_BOUT */
4615 #ifndef WORKING_DOT_WORD
4616 CONST
int md_short_jump_size
= 4;
4617 CONST
int md_long_jump_size
= 6;
4620 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4622 addressT from_addr
, to_addr
;
4628 offset
= to_addr
- (from_addr
+ 2);
4630 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4631 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4635 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4637 addressT from_addr
, to_addr
;
4643 if (cpu_of_arch (current_architecture
) < m68020
)
4645 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4646 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4647 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4648 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4653 offset
= to_addr
- (from_addr
+ 2);
4654 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4655 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4660 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4663 10: Absolute 1:8 only
4664 20: Absolute 0:7 only
4665 30: absolute 0:15 only
4666 40: Absolute 0:31 only
4667 50: absolute 0:127 only
4668 55: absolute -64:63 only
4669 60: absolute -128:127 only
4670 70: absolute 0:4095 only
4677 struct m68k_exp
*exp
;
4685 if (*exp
->e_beg
== '0')
4687 if (exp
->e_beg
[1] == 'x')
4688 sscanf (exp
->e_beg
+ 2, "%x", &l
);
4690 sscanf (exp
->e_beg
+ 1, "%O", &l
);
4693 return atol (exp
->e_beg
);
4701 /* Can't do anything */
4704 if (!exp
->e_beg
|| !exp
->e_end
)
4706 seg (exp
) = absolute_section
;
4709 offs (exp
) = (ok
== 10) ? 1 : 0;
4710 as_warn ("Null expression defaults to %ld", offs (exp
));
4715 if ( /* ok!=80 && */ (exp
->e_end
[-1] == ':' || exp
->e_end
[-1] == '.')
4716 && (exp
->e_end
- exp
->e_beg
) >= 2)
4718 switch (exp
->e_end
[0])
4738 if (exp
->e_end
[-1] == ':')
4739 as_bad ("Unknown size for expression \"%c\"", exp
->e_end
[0]);
4743 c_save
= exp
->e_end
[1];
4744 exp
->e_end
[1] = '\0';
4745 save_in
= input_line_pointer
;
4746 input_line_pointer
= exp
->e_beg
;
4747 section
= expression (&exp
->e_exp
);
4748 seg (exp
) = section
;
4749 if (exp
->e_exp
.X_op
== O_absent
)
4751 /* Do the same thing the VAX asm does */
4752 seg (exp
) = absolute_section
;
4753 op (exp
) = O_constant
;
4759 as_warn ("expression out of range: defaulting to 1");
4763 else if (exp
->e_exp
.X_op
== O_constant
)
4768 if (offs (exp
) < 1 || offs (exp
) > 8)
4770 as_warn ("expression out of range: defaulting to 1");
4775 if (offs (exp
) < 0 || offs (exp
) > 7)
4779 if (offs (exp
) < 0 || offs (exp
) > 15)
4783 if (offs (exp
) < 0 || offs (exp
) > 32)
4787 if (offs (exp
) < 0 || offs (exp
) > 127)
4791 if (offs (exp
) < -64 || offs (exp
) > 63)
4795 if (offs (exp
) < -128 || offs (exp
) > 127)
4799 if (offs (exp
) < 0 || offs (exp
) > 4095)
4802 as_warn ("expression out of range: defaulting to 0");
4810 else if (exp
->e_exp
.X_op
== O_big
)
4812 if (offs (exp
) <= 0 /* flonum */
4813 && (ok
== 80 /* no bignums */
4814 || (ok
> 10 /* small-int ranges including 0 ok */
4815 /* If we have a flonum zero, a zero integer should
4816 do as well (e.g., in moveq). */
4817 && generic_floating_point_number
.exponent
== 0
4818 && generic_floating_point_number
.low
[0] == 0)))
4820 /* HACK! Turn it into a long */
4821 LITTLENUM_TYPE words
[6];
4823 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4824 seg (exp
) = absolute_section
;
4825 op (exp
) = O_constant
;
4828 offs (exp
) = words
[1] | (words
[0] << 16);
4832 seg (exp
) = absolute_section
;
4833 op (exp
) = O_constant
;
4836 offs (exp
) = (ok
== 10) ? 1 : 0;
4837 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4842 if (ok
>= 10 && ok
<= 70)
4844 seg (exp
) = absolute_section
;
4845 op (exp
) = O_constant
;
4848 offs (exp
) = (ok
== 10) ? 1 : 0;
4849 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4853 if (input_line_pointer
!= exp
->e_end
+ 1)
4854 as_bad ("Ignoring junk after expression");
4855 exp
->e_end
[1] = c_save
;
4856 input_line_pointer
= save_in
;
4862 if (!isbyte (offs (exp
)))
4863 as_warn ("expression doesn't fit in BYTE");
4866 if (!isword (offs (exp
)))
4867 as_warn ("expression doesn't fit in WORD");
4875 /* These are the back-ends for the various machine dependent pseudo-ops. */
4876 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4882 subseg_set (data_section
, 1);
4883 demand_empty_rest_of_line ();
4890 subseg_set (data_section
, 2);
4891 demand_empty_rest_of_line ();
4898 /* We don't support putting frags in the BSS segment, we fake it
4899 by marking in_bss, then looking at s_skip for clues. */
4901 subseg_set (bss_section
, 0);
4902 demand_empty_rest_of_line ();
4910 register long temp_fill
;
4912 temp
= 1; /* JF should be 2? */
4913 temp_fill
= get_absolute_expression ();
4914 if (!need_pass_2
) /* Never make frag if expect extra pass. */
4915 frag_align (temp
, (int) temp_fill
);
4916 demand_empty_rest_of_line ();
4923 demand_empty_rest_of_line ();
4926 /* s_space is defined in read.c .skip is simply an alias to it. */
4931 * Invocation line includes a switch not recognized by the base assembler.
4932 * See if it's a processor-specific option. These are:
4934 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4935 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4936 * Select the architecture. Instructions or features not
4937 * supported by the selected architecture cause fatal
4938 * errors. More than one may be specified. The default is
4939 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4940 * for -m68000, and -m68882 is a synonym for -m68881.
4941 * -[A]m[c]no-68851, -[A]m[c]no-68881
4942 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4943 * so don't use or document it, but that's the way the parsing
4946 * -pic Indicates PIC.
4947 * -k Indicates PIC. (Sun 3 only.)
4949 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4950 * (e.g. m68020) also requests that float instructions be included. This
4951 * is the default setup, mostly to avoid hassling users. A better
4952 * rearrangement of this structure would be to add an option to DENY
4953 * floating point opcodes, for people who want to really know there's none
4954 * of that funny floaty stuff going on. FIXME-later.
4956 #ifndef MAYBE_FLOAT_TOO
4957 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4960 CONST
char *md_shortopts
= "lSA:m:k";
4961 struct option md_longopts
[] = {
4962 #define OPTION_PIC (OPTION_MD_BASE)
4963 {"pic", no_argument
, NULL
, OPTION_PIC
},
4964 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4965 {"register-prefix-optional", no_argument
, NULL
,
4966 OPTION_REGISTER_PREFIX_OPTIONAL
},
4967 {NULL
, no_argument
, NULL
, 0}
4969 size_t md_longopts_size
= sizeof(md_longopts
);
4972 md_parse_option (c
, arg
)
4978 case 'l': /* -l means keep external to 2 bit offset
4979 rather than 16 bit one */
4982 case 'S': /* -S means that jbsr's always turn into
4989 /* intentional fall-through */
4994 if (!strcmp (arg
, "68000")
4995 || !strcmp (arg
, "68008")
4996 || !strcmp (arg
, "68302"))
4998 current_architecture
|= m68000
;
5000 else if (!strcmp (arg
, "68010"))
5002 current_architecture
|= m68010
;
5004 else if (!strcmp (arg
, "68020"))
5006 current_architecture
|= m68020
| MAYBE_FLOAT_TOO
;
5008 else if (!strcmp (arg
, "68030"))
5010 current_architecture
|= m68030
| MAYBE_FLOAT_TOO
;
5012 else if (!strcmp (arg
, "68040"))
5014 current_architecture
|= m68040
| MAYBE_FLOAT_TOO
;
5016 else if (!strcmp (arg
, "68060"))
5018 current_architecture
|= m68060
| MAYBE_FLOAT_TOO
;
5021 else if (!strcmp (arg
, "68881"))
5023 current_architecture
|= m68881
;
5025 else if (!strcmp (arg
, "68882"))
5027 current_architecture
|= m68882
;
5029 #endif /* NO_68881 */
5030 /* Even if we aren't configured to support the processor,
5031 it should still be possible to assert that the user
5032 doesn't have it... */
5033 else if (!strcmp (arg
, "no-68881")
5034 || !strcmp (arg
, "no-68882"))
5039 else if (!strcmp (arg
, "68851"))
5041 current_architecture
|= m68851
;
5043 #endif /* NO_68851 */
5044 else if (!strcmp (arg
, "no-68851"))
5048 else if (!strcmp (arg
, "pu32") /* "cpu32" minus 'c' */
5049 || !strcmp (arg
, "68331")
5050 || !strcmp (arg
, "68332")
5051 || !strcmp (arg
, "68333")
5052 || !strcmp (arg
, "68340"))
5054 current_architecture
|= cpu32
;
5058 as_bad ("invalid architecture %s", arg
);
5066 break; /* -pic, Position Independent Code */
5068 case OPTION_REGISTER_PREFIX_OPTIONAL
:
5069 flag_reg_prefix_optional
= 1;
5080 md_show_usage (stream
)
5085 -l use 1 word for refs to undefined symbols [default 2]\n\
5086 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040\n\
5087 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32\n\
5088 specify variant of 680X0 architecture [default 68020]\n\
5089 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5090 target has/lacks floating-point coprocessor\n\
5091 [default yes for 68020, 68030, and cpu32]\n\
5092 -m68851 | -mno-68851\n\
5093 target has/lacks memory-management unit coprocessor\n\
5094 [default yes for 68020 and up]\n\
5095 -pic, -k generate position independent code\n\
5096 -S turn jbsr into jsr\n\
5097 --register-prefix-optional\n\
5098 recognize register names without prefix character\n");
5103 /* TEST2: Test md_assemble() */
5104 /* Warning, this routine probably doesn't work anymore */
5108 struct m68k_it the_ins
;
5116 if (!gets (buf
) || !*buf
)
5118 if (buf
[0] == '|' || buf
[1] == '.')
5120 for (cp
= buf
; *cp
; cp
++)
5125 memset (&the_ins
, '\0', sizeof (the_ins
));
5126 m68k_ip (&the_ins
, buf
);
5129 printf ("Error %s in %s\n", the_ins
.error
, buf
);
5133 printf ("Opcode(%d.%s): ", the_ins
.numo
, the_ins
.args
);
5134 for (n
= 0; n
< the_ins
.numo
; n
++)
5135 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
5137 print_the_insn (&the_ins
.opcode
[0], stdout
);
5138 (void) putchar ('\n');
5140 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
5142 if (the_ins
.operands
[n
].error
)
5144 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
5147 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
5148 if (the_ins
.operands
[n
].b_const
)
5149 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
5150 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
5151 if (the_ins
.operands
[n
].b_iadd
)
5152 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
5153 (void) putchar ('\n');
5165 while (*str
&& *str
!= ' ')
5167 if (str
[-1] == ':' || str
[1] == '=')
5174 /* Possible states for relaxation:
5176 0 0 branch offset byte (bra, etc)
5180 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5184 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5191 /* We have no need to default values of symbols. */
5195 md_undefined_symbol (name
)
5201 /* Parse an operand that is machine-specific.
5202 We just return without modifying the expression if we have nothing
5207 md_operand (expressionP
)
5208 expressionS
*expressionP
;
5212 /* Round up a section size to the appropriate boundary. */
5214 md_section_align (segment
, size
)
5218 return size
; /* Byte alignment is fine */
5221 /* Exactly what point is a PC-relative offset relative TO?
5222 On the 68k, they're relative to the address of the offset, plus
5223 its size. (??? Is this right? FIXME-SOON!) */
5225 md_pcrel_from (fixP
)
5228 return (fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
);
5231 #ifndef BFD_ASSEMBLER
5233 tc_coff_symbol_emit_hook ()
5238 tc_coff_sizemachdep (frag
)
5241 switch (frag
->fr_subtype
& 0x3)
5255 /* end of tc-m68k.c */