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* tc_mips.c (load_address): Reflect change to MAX_GPREL_OFFSET.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <ctype.h>
24 #include "as.h"
25 #include "obstack.h"
26 #include "subsegs.h"
27 #include "dwarf2dbg.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars = "|#";
42 #else
43 const char *m68k_comment_chars = "|";
44 #endif
45
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#*";
54
55 const char line_separator_chars[] = ";";
56
57 /* Chars that can be used to separate mant from exp in floating point nums */
58 CONST char EXP_CHARS[] = "eE";
59
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
63 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69 const int md_reloc_size = 8; /* Size of relocation record */
70
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
75 int flag_want_pic;
76
77 static int flag_short_refs; /* -l option */
78 static int flag_long_jumps; /* -S option */
79 static int flag_keep_pcrel; /* --pcrel option. */
80
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83 #else
84 int flag_reg_prefix_optional;
85 #endif
86
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen;
89
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum = COP1;
92
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd;
96
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick = 1;
100
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104 static int m68k_rel32 = 1;
105
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline;
108
109 /* The default width to use for an index register when using a base
110 displacement. */
111 static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117 struct label_line
118 {
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124 };
125
126 /* The list of labels. */
127
128 static struct label_line *labels;
129
130 /* The current label. */
131
132 static struct label_line *current_label;
133
134 /* Its an arbitrary name: This means I don't approve of it */
135 /* See flames below */
136 static struct obstack robyn;
137
138 struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149 #define gettwo(x) (((x)->m_opcode)&0xffff)
150
151 static const enum m68k_register m68000_control_regs[] = { 0 };
152 static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155 };
156 static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159 };
160 static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164 };
165 static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169 };
170 static const enum m68k_register mcf_control_regs[] = {
171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
172 RAMBAR0, RAMBAR1, MBAR,
173 0
174 };
175 #define cpu32_control_regs m68010_control_regs
176
177 static const enum m68k_register *control_regs;
178
179 /* internal form of a 68020 instruction */
180 struct m68k_it
181 {
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219 #ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223 #endif
224 }
225 reloc[5]; /* Five is enough??? */
226 };
227
228 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
229 #define float_of_arch(x) ((x) & mfloat)
230 #define mmu_of_arch(x) ((x) & mmmu)
231 #define arch_coldfire_p(x) (((x) & mcf) != 0)
232
233 /* Macros for determining if cpu supports a specific addressing mode */
234 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
235
236 static struct m68k_it the_ins; /* the instruction being assembled */
237
238 #define op(ex) ((ex)->exp.X_op)
239 #define adds(ex) ((ex)->exp.X_add_symbol)
240 #define subs(ex) ((ex)->exp.X_op_symbol)
241 #define offs(ex) ((ex)->exp.X_add_number)
242
243 /* Macros for adding things to the m68k_it struct */
244
245 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247 /* Static functions. */
248
249 static void insop PARAMS ((int, const struct m68k_incant *));
250 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251 static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253 /* Like addword, but goes BEFORE general operands */
254 static void
255 insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258 {
259 int z;
260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
261 the_ins.opcode[z]=the_ins.opcode[z-1];
262 for (z = 0;z < the_ins.nrel; z++)
263 the_ins.reloc[z].n+=2;
264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
266 the_ins.opcode[opcode->m_codenum]=w;
267 the_ins.numo++;
268 }
269
270 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272 static void
273 add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278 {
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287 #ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289 #endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291 }
292
293 /* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303 static void
304 add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308 {
309 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd=add;
311 the_ins.fragb[the_ins.nfrag].foff=off;
312 the_ins.fragb[the_ins.nfrag++].fragty=type;
313 }
314
315 #define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320 static void m68k_ip PARAMS ((char *));
321 static void insert_reg PARAMS ((const char *, int));
322 static void select_control_regs PARAMS ((void));
323 static void init_regtable PARAMS ((void));
324 static int reverse_16_bits PARAMS ((int in));
325 static int reverse_8_bits PARAMS ((int in));
326 static void install_gen_operand PARAMS ((int mode, int val));
327 static void install_operand PARAMS ((int mode, int val));
328 static void s_bss PARAMS ((int));
329 static void s_data1 PARAMS ((int));
330 static void s_data2 PARAMS ((int));
331 static void s_even PARAMS ((int));
332 static void s_proc PARAMS ((int));
333 static void mri_chip PARAMS ((void));
334 static void s_chip PARAMS ((int));
335 static void s_fopt PARAMS ((int));
336 static void s_opt PARAMS ((int));
337 static void s_reg PARAMS ((int));
338 static void s_restore PARAMS ((int));
339 static void s_save PARAMS ((int));
340 static void s_mri_if PARAMS ((int));
341 static void s_mri_else PARAMS ((int));
342 static void s_mri_endi PARAMS ((int));
343 static void s_mri_break PARAMS ((int));
344 static void s_mri_next PARAMS ((int));
345 static void s_mri_for PARAMS ((int));
346 static void s_mri_endf PARAMS ((int));
347 static void s_mri_repeat PARAMS ((int));
348 static void s_mri_until PARAMS ((int));
349 static void s_mri_while PARAMS ((int));
350 static void s_mri_endw PARAMS ((int));
351 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
352 static void md_convert_frag_1 PARAMS ((fragS *));
353
354 static int current_architecture;
355
356 struct m68k_cpu
357 {
358 unsigned long arch;
359 const char *name;
360 int alias;
361 };
362
363 static const struct m68k_cpu archs[] =
364 {
365 { m68000, "68000", 0 },
366 { m68010, "68010", 0 },
367 { m68020, "68020", 0 },
368 { m68030, "68030", 0 },
369 { m68040, "68040", 0 },
370 { m68060, "68060", 0 },
371 { cpu32, "cpu32", 0 },
372 { m68881, "68881", 0 },
373 { m68851, "68851", 0 },
374 { mcf5200, "5200", 0 },
375 { mcf5206e, "5206e", 0 },
376 { mcf5307, "5307", 0},
377 { mcf5407, "5407", 0},
378 /* Aliases (effectively, so far as gas is concerned) for the above
379 cpus. */
380 { m68020, "68k", 1 },
381 { m68000, "68008", 1 },
382 { m68000, "68302", 1 },
383 { m68000, "68306", 1 },
384 { m68000, "68307", 1 },
385 { m68000, "68322", 1 },
386 { m68000, "68356", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68334", 1 },
399 { cpu32, "68336", 1 },
400 { cpu32, "68340", 1 },
401 { cpu32, "68341", 1 },
402 { cpu32, "68349", 1 },
403 { cpu32, "68360", 1 },
404 { m68881, "68882", 1 },
405 { mcf5200, "5202", 1 },
406 { mcf5200, "5204", 1 },
407 { mcf5200, "5206", 1 },
408 };
409
410 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
411
412 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
413 architecture and we have a lot of relaxation modes. */
414
415 /* Macros used in the relaxation code. */
416 #define TAB(x,y) (((x) << 2) + (y))
417 #define TABTYPE(x) ((x) >> 2)
418
419 /* Relaxation states. */
420 #define BYTE 0
421 #define SHORT 1
422 #define LONG 2
423 #define SZ_UNDEF 3
424
425 /* Here are all the relaxation modes we support. First we can relax ordinary
426 branches. On 68020 and higher and on CPU32 all branch instructions take
427 three forms, so on these CPUs all branches always remain as such. When we
428 have to expand to the LONG form on a 68000, though, we substitute an
429 absolute jump instead. This is a direct replacement for unconditional
430 branches and a branch over a jump for conditional branches. However, if the
431 user requires PIC and disables this with --pcrel, we can only relax between
432 BYTE and SHORT forms, punting if that isn't enough. This gives us four
433 different relaxation modes for branches: */
434
435 #define BRANCHBWL 0 /* branch byte, word, or long */
436 #define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
437 #define BRABSJCOND 2 /* absolute jump for LONG, conditional */
438 #define BRANCHBW 3 /* branch byte or word */
439
440 /* We also relax coprocessor branches and DBcc's. All CPUs that support
441 coprocessor branches support them in word and long forms, so we have only
442 one relaxation mode for them. DBcc's are word only on all CPUs. We can
443 relax them to the LONG form with a branch-around sequence. This sequence
444 can use a long branch (if available) or an absolute jump (if acceptable).
445 This gives us two relaxation modes. If long branches are not available and
446 absolute jumps are not acceptable, we don't relax DBcc's. */
447
448 #define FBRANCH 4 /* coprocessor branch */
449 #define DBCCLBR 5 /* DBcc relaxable with a long branch */
450 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
451
452 /* That's all for instruction relaxation. However, we also relax PC-relative
453 operands. Specifically, we have three operand relaxation modes. On the
454 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
455 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
456 two. Also PC+displacement+index operands in their simple form (with a non-
457 suppressed index without memory indirection) are supported on all CPUs, but
458 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
459 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
460 form of the PC+displacement+index operand. Finally, some absolute operands
461 can be relaxed down to 16-bit PC-relative. */
462
463 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
464 #define PCINDEX 8 /* PC+displacement+index */
465 #define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
466
467 /* Note that calls to frag_var need to specify the maximum expansion
468 needed; this is currently 10 bytes for DBCC. */
469
470 /* The fields are:
471 How far Forward this mode will reach:
472 How far Backward this mode will reach:
473 How many bytes this mode will add to the size of the frag
474 Which mode to go to if the offset won't fit in this one
475 */
476 relax_typeS md_relax_table[] =
477 {
478 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
479 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
480 { 0, 0, 4, 0 },
481 { 1, 1, 0, 0 },
482
483 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
484 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
485 { 0, 0, 4, 0 },
486 { 1, 1, 0, 0 },
487
488 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
489 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
490 { 0, 0, 6, 0 },
491 { 1, 1, 0, 0 },
492
493 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
494 { 0, 0, 2, 0 },
495 { 1, 1, 0, 0 },
496 { 1, 1, 0, 0 },
497
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
500 { 0, 0, 4, 0 },
501 { 1, 1, 0, 0 },
502
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
505 { 0, 0, 10, 0 },
506 { 1, 1, 0, 0 },
507
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
510 { 0, 0, 10, 0 },
511 { 1, 1, 0, 0 },
512
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
515 { 0, 0, 6, 0 },
516 { 1, 1, 0, 0 },
517
518 { 125, -130, 0, TAB (PCINDEX, SHORT) },
519 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
520 { 0, 0, 4, 0 },
521 { 1, 1, 0, 0 },
522
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
525 { 0, 0, 4, 0 },
526 { 1, 1, 0, 0 },
527 };
528
529 /* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534 /* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540 const pseudo_typeS md_pseudo_table[] =
541 {
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548 #if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550 #endif
551 #ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553 #endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
557 #ifdef OBJ_ELF
558 /* Dwarf2 support for Gcc. */
559 {"file", dwarf2_directive_file, 0},
560 {"loc", dwarf2_directive_loc, 0},
561 #endif
562
563 /* The following pseudo-ops are supported for MRI compatibility. */
564 {"chip", s_chip, 0},
565 {"comline", s_space, 1},
566 {"fopt", s_fopt, 0},
567 {"mask2", s_ignore, 0},
568 {"opt", s_opt, 0},
569 {"reg", s_reg, 0},
570 {"restore", s_restore, 0},
571 {"save", s_save, 0},
572
573 {"if", s_mri_if, 0},
574 {"if.b", s_mri_if, 'b'},
575 {"if.w", s_mri_if, 'w'},
576 {"if.l", s_mri_if, 'l'},
577 {"else", s_mri_else, 0},
578 {"else.s", s_mri_else, 's'},
579 {"else.l", s_mri_else, 'l'},
580 {"endi", s_mri_endi, 0},
581 {"break", s_mri_break, 0},
582 {"break.s", s_mri_break, 's'},
583 {"break.l", s_mri_break, 'l'},
584 {"next", s_mri_next, 0},
585 {"next.s", s_mri_next, 's'},
586 {"next.l", s_mri_next, 'l'},
587 {"for", s_mri_for, 0},
588 {"for.b", s_mri_for, 'b'},
589 {"for.w", s_mri_for, 'w'},
590 {"for.l", s_mri_for, 'l'},
591 {"endf", s_mri_endf, 0},
592 {"repeat", s_mri_repeat, 0},
593 {"until", s_mri_until, 0},
594 {"until.b", s_mri_until, 'b'},
595 {"until.w", s_mri_until, 'w'},
596 {"until.l", s_mri_until, 'l'},
597 {"while", s_mri_while, 0},
598 {"while.b", s_mri_while, 'b'},
599 {"while.w", s_mri_while, 'w'},
600 {"while.l", s_mri_while, 'l'},
601 {"endw", s_mri_endw, 0},
602
603 {0, 0, 0}
604 };
605
606 /* The mote pseudo ops are put into the opcode table, since they
607 don't start with a . they look like opcodes to gas.
608 */
609
610 #ifdef M68KCOFF
611 extern void obj_coff_section PARAMS ((int));
612 #endif
613
614 CONST pseudo_typeS mote_pseudo_table[] =
615 {
616
617 {"dcl", cons, 4},
618 {"dc", cons, 2},
619 {"dcw", cons, 2},
620 {"dcb", cons, 1},
621
622 {"dsl", s_space, 4},
623 {"ds", s_space, 2},
624 {"dsw", s_space, 2},
625 {"dsb", s_space, 1},
626
627 {"xdef", s_globl, 0},
628 #ifdef OBJ_ELF
629 {"align", s_align_bytes, 0},
630 #else
631 {"align", s_align_ptwo, 0},
632 #endif
633 #ifdef M68KCOFF
634 {"sect", obj_coff_section, 0},
635 {"section", obj_coff_section, 0},
636 #endif
637 {0, 0, 0}
638 };
639
640 #define issbyte(x) ((x)>=-128 && (x)<=127)
641 #define isubyte(x) ((x)>=0 && (x)<=255)
642 #define issword(x) ((x)>=-32768 && (x)<=32767)
643 #define isuword(x) ((x)>=0 && (x)<=65535)
644
645 #define isbyte(x) ((x)>= -255 && (x)<=255)
646 #define isword(x) ((x)>=-65536 && (x)<=65535)
647 #define islong(x) (1)
648
649 extern char *input_line_pointer;
650
651 static char mklower_table[256];
652 #define mklower(c) (mklower_table[(unsigned char) (c)])
653 static char notend_table[256];
654 static char alt_notend_table[256];
655 #define notend(s) \
656 (! (notend_table[(unsigned char) *s] \
657 || (*s == ':' \
658 && alt_notend_table[(unsigned char) s[1]])))
659
660 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
661
662 #ifdef NO_PCREL_RELOCS
663
664 int
665 make_pcrel_absolute(fixP, add_number)
666 fixS *fixP;
667 long *add_number;
668 {
669 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
670
671 /* rewrite the PC relative instructions to absolute address ones.
672 * these are rumoured to be faster, and the apollo linker refuses
673 * to deal with the PC relative relocations.
674 */
675 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
676 {
677 opcode[0] = 0x4e;
678 opcode[1] = 0xf9;
679 }
680 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
681 {
682 opcode[0] = 0x4e;
683 opcode[1] = 0xb9;
684 }
685 else
686 as_fatal (_("Unknown PC relative instruction"));
687 *add_number -= 4;
688 return 0;
689 }
690
691 #endif /* NO_PCREL_RELOCS */
692
693 short
694 tc_coff_fix2rtype (fixP)
695 fixS *fixP;
696 {
697 if (fixP->fx_tcbit && fixP->fx_size == 4)
698 return R_RELLONG_NEG;
699 #ifdef NO_PCREL_RELOCS
700 know (fixP->fx_pcrel == 0);
701 return (fixP->fx_size == 1 ? R_RELBYTE
702 : fixP->fx_size == 2 ? R_DIR16
703 : R_DIR32);
704 #else
705 return (fixP->fx_pcrel ?
706 (fixP->fx_size == 1 ? R_PCRBYTE :
707 fixP->fx_size == 2 ? R_PCRWORD :
708 R_PCRLONG) :
709 (fixP->fx_size == 1 ? R_RELBYTE :
710 fixP->fx_size == 2 ? R_RELWORD :
711 R_RELLONG));
712 #endif
713 }
714
715 #endif
716
717 #ifdef OBJ_ELF
718
719 /* Return zero if the reference to SYMBOL from within the same segment may
720 be relaxed. */
721
722 /* On an ELF system, we can't relax an externally visible symbol,
723 because it may be overridden by a shared library. However, if
724 TARGET_OS is "elf", then we presume that we are assembling for an
725 embedded system, in which case we don't have to worry about shared
726 libraries, and we can relax any external sym. */
727
728 #define relaxable_symbol(symbol) \
729 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
730 || S_IS_WEAK (symbol)))
731
732 /* Compute the relocation code for a fixup of SIZE bytes, using pc
733 relative relocation if PCREL is non-zero. PIC says whether a special
734 pic relocation was requested. */
735
736 static bfd_reloc_code_real_type get_reloc_code
737 PARAMS ((int, int, enum pic_relocation));
738
739 static bfd_reloc_code_real_type
740 get_reloc_code (size, pcrel, pic)
741 int size;
742 int pcrel;
743 enum pic_relocation pic;
744 {
745 switch (pic)
746 {
747 case pic_got_pcrel:
748 switch (size)
749 {
750 case 1:
751 return BFD_RELOC_8_GOT_PCREL;
752 case 2:
753 return BFD_RELOC_16_GOT_PCREL;
754 case 4:
755 return BFD_RELOC_32_GOT_PCREL;
756 }
757 break;
758
759 case pic_got_off:
760 switch (size)
761 {
762 case 1:
763 return BFD_RELOC_8_GOTOFF;
764 case 2:
765 return BFD_RELOC_16_GOTOFF;
766 case 4:
767 return BFD_RELOC_32_GOTOFF;
768 }
769 break;
770
771 case pic_plt_pcrel:
772 switch (size)
773 {
774 case 1:
775 return BFD_RELOC_8_PLT_PCREL;
776 case 2:
777 return BFD_RELOC_16_PLT_PCREL;
778 case 4:
779 return BFD_RELOC_32_PLT_PCREL;
780 }
781 break;
782
783 case pic_plt_off:
784 switch (size)
785 {
786 case 1:
787 return BFD_RELOC_8_PLTOFF;
788 case 2:
789 return BFD_RELOC_16_PLTOFF;
790 case 4:
791 return BFD_RELOC_32_PLTOFF;
792 }
793 break;
794
795 case pic_none:
796 if (pcrel)
797 {
798 switch (size)
799 {
800 case 1:
801 return BFD_RELOC_8_PCREL;
802 case 2:
803 return BFD_RELOC_16_PCREL;
804 case 4:
805 return BFD_RELOC_32_PCREL;
806 }
807 }
808 else
809 {
810 switch (size)
811 {
812 case 1:
813 return BFD_RELOC_8;
814 case 2:
815 return BFD_RELOC_16;
816 case 4:
817 return BFD_RELOC_32;
818 }
819 }
820 }
821
822 if (pcrel)
823 {
824 if (pic == pic_none)
825 as_bad (_("Can not do %d byte pc-relative relocation"), size);
826 else
827 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
828 }
829 else
830 {
831 if (pic == pic_none)
832 as_bad (_("Can not do %d byte relocation"), size);
833 else
834 as_bad (_("Can not do %d byte pic relocation"), size);
835 }
836
837 return BFD_RELOC_NONE;
838 }
839
840 /* Here we decide which fixups can be adjusted to make them relative
841 to the beginning of the section instead of the symbol. Basically
842 we need to make sure that the dynamic relocations are done
843 correctly, so in some cases we force the original symbol to be
844 used. */
845 int
846 tc_m68k_fix_adjustable (fixP)
847 fixS *fixP;
848 {
849 /* Prevent all adjustments to global symbols. */
850 if (! relaxable_symbol (fixP->fx_addsy))
851 return 0;
852
853 /* adjust_reloc_syms doesn't know about the GOT */
854 switch (fixP->fx_r_type)
855 {
856 case BFD_RELOC_8_GOT_PCREL:
857 case BFD_RELOC_16_GOT_PCREL:
858 case BFD_RELOC_32_GOT_PCREL:
859 case BFD_RELOC_8_GOTOFF:
860 case BFD_RELOC_16_GOTOFF:
861 case BFD_RELOC_32_GOTOFF:
862 case BFD_RELOC_8_PLT_PCREL:
863 case BFD_RELOC_16_PLT_PCREL:
864 case BFD_RELOC_32_PLT_PCREL:
865 case BFD_RELOC_8_PLTOFF:
866 case BFD_RELOC_16_PLTOFF:
867 case BFD_RELOC_32_PLTOFF:
868 return 0;
869
870 case BFD_RELOC_VTABLE_INHERIT:
871 case BFD_RELOC_VTABLE_ENTRY:
872 return 0;
873
874 default:
875 return 1;
876 }
877 }
878
879 #else /* !OBJ_ELF */
880
881 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
882
883 #define relaxable_symbol(symbol) 1
884
885 #endif /* OBJ_ELF */
886
887 #ifdef BFD_ASSEMBLER
888
889 arelent *
890 tc_gen_reloc (section, fixp)
891 asection *section;
892 fixS *fixp;
893 {
894 arelent *reloc;
895 bfd_reloc_code_real_type code;
896
897 /* If the tcbit is set, then this was a fixup of a negative value
898 that was never resolved. We do not have a reloc to handle this,
899 so just return. We assume that other code will have detected this
900 situation and produced a helpful error message, so we just tell the
901 user that the reloc cannot be produced. */
902 if (fixp->fx_tcbit)
903 {
904 if (fixp->fx_addsy)
905 as_bad_where (fixp->fx_file, fixp->fx_line,
906 _("Unable to produce reloc against symbol '%s'"),
907 S_GET_NAME (fixp->fx_addsy));
908 return NULL;
909 }
910
911 if (fixp->fx_r_type != BFD_RELOC_NONE)
912 {
913 code = fixp->fx_r_type;
914
915 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
916 that fixup_segment converted a non-PC relative reloc into a
917 PC relative reloc. In such a case, we need to convert the
918 reloc code. */
919 if (fixp->fx_pcrel)
920 {
921 switch (code)
922 {
923 case BFD_RELOC_8:
924 code = BFD_RELOC_8_PCREL;
925 break;
926 case BFD_RELOC_16:
927 code = BFD_RELOC_16_PCREL;
928 break;
929 case BFD_RELOC_32:
930 code = BFD_RELOC_32_PCREL;
931 break;
932 case BFD_RELOC_8_PCREL:
933 case BFD_RELOC_16_PCREL:
934 case BFD_RELOC_32_PCREL:
935 case BFD_RELOC_8_GOT_PCREL:
936 case BFD_RELOC_16_GOT_PCREL:
937 case BFD_RELOC_32_GOT_PCREL:
938 case BFD_RELOC_8_GOTOFF:
939 case BFD_RELOC_16_GOTOFF:
940 case BFD_RELOC_32_GOTOFF:
941 case BFD_RELOC_8_PLT_PCREL:
942 case BFD_RELOC_16_PLT_PCREL:
943 case BFD_RELOC_32_PLT_PCREL:
944 case BFD_RELOC_8_PLTOFF:
945 case BFD_RELOC_16_PLTOFF:
946 case BFD_RELOC_32_PLTOFF:
947 break;
948 default:
949 as_bad_where (fixp->fx_file, fixp->fx_line,
950 _("Cannot make %s relocation PC relative"),
951 bfd_get_reloc_code_name (code));
952 }
953 }
954 }
955 else
956 {
957 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
958 switch (F (fixp->fx_size, fixp->fx_pcrel))
959 {
960 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
961 MAP (1, 0, BFD_RELOC_8);
962 MAP (2, 0, BFD_RELOC_16);
963 MAP (4, 0, BFD_RELOC_32);
964 MAP (1, 1, BFD_RELOC_8_PCREL);
965 MAP (2, 1, BFD_RELOC_16_PCREL);
966 MAP (4, 1, BFD_RELOC_32_PCREL);
967 default:
968 abort ();
969 }
970 }
971 #undef F
972 #undef MAP
973
974 reloc = (arelent *) xmalloc (sizeof (arelent));
975 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
976 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
977 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
978 #ifndef OBJ_ELF
979 if (fixp->fx_pcrel)
980 reloc->addend = fixp->fx_addnumber;
981 else
982 reloc->addend = 0;
983 #else
984 if (!fixp->fx_pcrel)
985 reloc->addend = fixp->fx_addnumber;
986 else
987 reloc->addend = (section->vma
988 /* Explicit sign extension in case char is
989 unsigned. */
990 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
991 + fixp->fx_addnumber
992 + md_pcrel_from (fixp));
993 #endif
994
995 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
996 assert (reloc->howto != 0);
997
998 return reloc;
999 }
1000
1001 #endif /* BFD_ASSEMBLER */
1002
1003 /* Handle of the OPCODE hash table. NULL means any use before
1004 m68k_ip_begin() will crash. */
1005 static struct hash_control *op_hash;
1006 \f
1007 /* Assemble an m68k instruction. */
1008
1009 static void
1010 m68k_ip (instring)
1011 char *instring;
1012 {
1013 register char *p;
1014 register struct m68k_op *opP;
1015 register const struct m68k_incant *opcode;
1016 register const char *s;
1017 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1018 char *pdot, *pdotmove;
1019 enum m68k_size siz1, siz2;
1020 char c;
1021 int losing;
1022 int opsfound;
1023 LITTLENUM_TYPE words[6];
1024 LITTLENUM_TYPE *wordp;
1025 unsigned long ok_arch = 0;
1026
1027 if (*instring == ' ')
1028 instring++; /* skip leading whitespace */
1029
1030 /* Scan up to end of operation-code, which MUST end in end-of-string
1031 or exactly 1 space. */
1032 pdot = 0;
1033 for (p = instring; *p != '\0'; p++)
1034 {
1035 if (*p == ' ')
1036 break;
1037 if (*p == '.')
1038 pdot = p;
1039 }
1040
1041 if (p == instring)
1042 {
1043 the_ins.error = _("No operator");
1044 return;
1045 }
1046
1047 /* p now points to the end of the opcode name, probably whitespace.
1048 Make sure the name is null terminated by clobbering the
1049 whitespace, look it up in the hash table, then fix it back.
1050 Remove a dot, first, since the opcode tables have none. */
1051 if (pdot != NULL)
1052 {
1053 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1054 *pdotmove = pdotmove[1];
1055 p--;
1056 }
1057
1058 c = *p;
1059 *p = '\0';
1060 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1061 *p = c;
1062
1063 if (pdot != NULL)
1064 {
1065 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1066 *pdotmove = pdotmove[-1];
1067 *pdot = '.';
1068 ++p;
1069 }
1070
1071 if (opcode == NULL)
1072 {
1073 the_ins.error = _("Unknown operator");
1074 return;
1075 }
1076
1077 /* found a legitimate opcode, start matching operands */
1078 while (*p == ' ')
1079 ++p;
1080
1081 if (opcode->m_operands == 0)
1082 {
1083 char *old = input_line_pointer;
1084 *old = '\n';
1085 input_line_pointer = p;
1086 /* Ahh - it's a motorola style psuedo op */
1087 mote_pseudo_table[opcode->m_opnum].poc_handler
1088 (mote_pseudo_table[opcode->m_opnum].poc_val);
1089 input_line_pointer = old;
1090 *old = 0;
1091
1092 return;
1093 }
1094
1095 if (flag_mri && opcode->m_opnum == 0)
1096 {
1097 /* In MRI mode, random garbage is allowed after an instruction
1098 which accepts no operands. */
1099 the_ins.args = opcode->m_operands;
1100 the_ins.numargs = opcode->m_opnum;
1101 the_ins.numo = opcode->m_codenum;
1102 the_ins.opcode[0] = getone (opcode);
1103 the_ins.opcode[1] = gettwo (opcode);
1104 return;
1105 }
1106
1107 for (opP = &the_ins.operands[0]; *p; opP++)
1108 {
1109 p = crack_operand (p, opP);
1110
1111 if (opP->error)
1112 {
1113 the_ins.error = opP->error;
1114 return;
1115 }
1116 }
1117
1118 opsfound = opP - &the_ins.operands[0];
1119
1120 /* This ugly hack is to support the floating pt opcodes in their
1121 standard form. Essentially, we fake a first enty of type COP#1 */
1122 if (opcode->m_operands[0] == 'I')
1123 {
1124 int n;
1125
1126 for (n = opsfound; n > 0; --n)
1127 the_ins.operands[n] = the_ins.operands[n - 1];
1128
1129 memset ((char *) (&the_ins.operands[0]), '\0',
1130 sizeof (the_ins.operands[0]));
1131 the_ins.operands[0].mode = CONTROL;
1132 the_ins.operands[0].reg = m68k_float_copnum;
1133 opsfound++;
1134 }
1135
1136 /* We've got the operands. Find an opcode that'll accept them */
1137 for (losing = 0;;)
1138 {
1139 /* If we didn't get the right number of ops, or we have no
1140 common model with this pattern then reject this pattern. */
1141
1142 ok_arch |= opcode->m_arch;
1143 if (opsfound != opcode->m_opnum
1144 || ((opcode->m_arch & current_architecture) == 0))
1145 ++losing;
1146 else
1147 {
1148 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1149 *s && !losing;
1150 s += 2, opP++)
1151 {
1152 /* Warning: this switch is huge! */
1153 /* I've tried to organize the cases into this order:
1154 non-alpha first, then alpha by letter. Lower-case
1155 goes directly before uppercase counterpart. */
1156 /* Code with multiple case ...: gets sorted by the lowest
1157 case ... it belongs to. I hope this makes sense. */
1158 switch (*s)
1159 {
1160 case '!':
1161 switch (opP->mode)
1162 {
1163 case IMMED:
1164 case DREG:
1165 case AREG:
1166 case FPREG:
1167 case CONTROL:
1168 case AINC:
1169 case ADEC:
1170 case REGLST:
1171 losing++;
1172 break;
1173 default:
1174 break;
1175 }
1176 break;
1177
1178 case '<':
1179 switch (opP->mode)
1180 {
1181 case DREG:
1182 case AREG:
1183 case FPREG:
1184 case CONTROL:
1185 case IMMED:
1186 case ADEC:
1187 case REGLST:
1188 losing++;
1189 break;
1190 default:
1191 break;
1192 }
1193 break;
1194
1195 case '>':
1196 switch (opP->mode)
1197 {
1198 case DREG:
1199 case AREG:
1200 case FPREG:
1201 case CONTROL:
1202 case IMMED:
1203 case AINC:
1204 case REGLST:
1205 losing++;
1206 break;
1207 case ABSL:
1208 break;
1209 default:
1210 if (opP->reg == PC
1211 || opP->reg == ZPC)
1212 losing++;
1213 break;
1214 }
1215 break;
1216
1217 case 'm':
1218 switch (opP->mode)
1219 {
1220 case DREG:
1221 case AREG:
1222 case AINDR:
1223 case AINC:
1224 case ADEC:
1225 break;
1226 default:
1227 losing++;
1228 }
1229 break;
1230
1231 case 'n':
1232 switch (opP->mode)
1233 {
1234 case DISP:
1235 break;
1236 default:
1237 losing++;
1238 }
1239 break;
1240
1241 case 'o':
1242 switch (opP->mode)
1243 {
1244 case BASE:
1245 case ABSL:
1246 case IMMED:
1247 break;
1248 default:
1249 losing++;
1250 }
1251 break;
1252
1253 case 'p':
1254 switch (opP->mode)
1255 {
1256 case DREG:
1257 case AREG:
1258 case AINDR:
1259 case AINC:
1260 case ADEC:
1261 break;
1262 case DISP:
1263 if (opP->reg == PC || opP->reg == ZPC)
1264 losing++;
1265 break;
1266 default:
1267 losing++;
1268 }
1269 break;
1270
1271 case 'q':
1272 switch (opP->mode)
1273 {
1274 case DREG:
1275 case AINDR:
1276 case AINC:
1277 case ADEC:
1278 break;
1279 case DISP:
1280 if (opP->reg == PC || opP->reg == ZPC)
1281 losing++;
1282 break;
1283 default:
1284 losing++;
1285 break;
1286 }
1287 break;
1288
1289 case 'v':
1290 switch (opP->mode)
1291 {
1292 case DREG:
1293 case AINDR:
1294 case AINC:
1295 case ADEC:
1296 case ABSL:
1297 break;
1298 case DISP:
1299 if (opP->reg == PC || opP->reg == ZPC)
1300 losing++;
1301 break;
1302 default:
1303 losing++;
1304 break;
1305 }
1306 break;
1307
1308 case '#':
1309 if (opP->mode != IMMED)
1310 losing++;
1311 else if (s[1] == 'b'
1312 && ! isvar (&opP->disp)
1313 && (opP->disp.exp.X_op != O_constant
1314 || ! isbyte (opP->disp.exp.X_add_number)))
1315 losing++;
1316 else if (s[1] == 'B'
1317 && ! isvar (&opP->disp)
1318 && (opP->disp.exp.X_op != O_constant
1319 || ! issbyte (opP->disp.exp.X_add_number)))
1320 losing++;
1321 else if (s[1] == 'w'
1322 && ! isvar (&opP->disp)
1323 && (opP->disp.exp.X_op != O_constant
1324 || ! isword (opP->disp.exp.X_add_number)))
1325 losing++;
1326 else if (s[1] == 'W'
1327 && ! isvar (&opP->disp)
1328 && (opP->disp.exp.X_op != O_constant
1329 || ! issword (opP->disp.exp.X_add_number)))
1330 losing++;
1331 break;
1332
1333 case '^':
1334 case 'T':
1335 if (opP->mode != IMMED)
1336 losing++;
1337 break;
1338
1339 case '$':
1340 if (opP->mode == AREG
1341 || opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == IMMED
1344 || opP->mode == REGLST
1345 || (opP->mode != ABSL
1346 && (opP->reg == PC
1347 || opP->reg == ZPC)))
1348 losing++;
1349 break;
1350
1351 case '%':
1352 if (opP->mode == CONTROL
1353 || opP->mode == FPREG
1354 || opP->mode == REGLST
1355 || opP->mode == IMMED
1356 || (opP->mode != ABSL
1357 && (opP->reg == PC
1358 || opP->reg == ZPC)))
1359 losing++;
1360 break;
1361
1362 case '&':
1363 switch (opP->mode)
1364 {
1365 case DREG:
1366 case AREG:
1367 case FPREG:
1368 case CONTROL:
1369 case IMMED:
1370 case AINC:
1371 case ADEC:
1372 case REGLST:
1373 losing++;
1374 break;
1375 case ABSL:
1376 break;
1377 default:
1378 if (opP->reg == PC
1379 || opP->reg == ZPC)
1380 losing++;
1381 break;
1382 }
1383 break;
1384
1385 case '*':
1386 if (opP->mode == CONTROL
1387 || opP->mode == FPREG
1388 || opP->mode == REGLST)
1389 losing++;
1390 break;
1391
1392 case '+':
1393 if (opP->mode != AINC)
1394 losing++;
1395 break;
1396
1397 case '-':
1398 if (opP->mode != ADEC)
1399 losing++;
1400 break;
1401
1402 case '/':
1403 switch (opP->mode)
1404 {
1405 case AREG:
1406 case CONTROL:
1407 case FPREG:
1408 case AINC:
1409 case ADEC:
1410 case IMMED:
1411 case REGLST:
1412 losing++;
1413 break;
1414 default:
1415 break;
1416 }
1417 break;
1418
1419 case ';':
1420 switch (opP->mode)
1421 {
1422 case AREG:
1423 case CONTROL:
1424 case FPREG:
1425 case REGLST:
1426 losing++;
1427 break;
1428 default:
1429 break;
1430 }
1431 break;
1432
1433 case '?':
1434 switch (opP->mode)
1435 {
1436 case AREG:
1437 case CONTROL:
1438 case FPREG:
1439 case AINC:
1440 case ADEC:
1441 case IMMED:
1442 case REGLST:
1443 losing++;
1444 break;
1445 case ABSL:
1446 break;
1447 default:
1448 if (opP->reg == PC || opP->reg == ZPC)
1449 losing++;
1450 break;
1451 }
1452 break;
1453
1454 case '@':
1455 switch (opP->mode)
1456 {
1457 case AREG:
1458 case CONTROL:
1459 case FPREG:
1460 case IMMED:
1461 case REGLST:
1462 losing++;
1463 break;
1464 default:
1465 break;
1466 }
1467 break;
1468
1469 case '~': /* For now! (JF FOO is this right?) */
1470 switch (opP->mode)
1471 {
1472 case DREG:
1473 case AREG:
1474 case CONTROL:
1475 case FPREG:
1476 case IMMED:
1477 case REGLST:
1478 losing++;
1479 break;
1480 case ABSL:
1481 break;
1482 default:
1483 if (opP->reg == PC
1484 || opP->reg == ZPC)
1485 losing++;
1486 break;
1487 }
1488 break;
1489
1490 case '3':
1491 if (opP->mode != CONTROL
1492 || (opP->reg != TT0 && opP->reg != TT1))
1493 losing++;
1494 break;
1495
1496 case 'A':
1497 if (opP->mode != AREG)
1498 losing++;
1499 break;
1500
1501 case 'a':
1502 if (opP->mode != AINDR)
1503 ++losing;
1504 break;
1505
1506 case 'B': /* FOO */
1507 if (opP->mode != ABSL
1508 || (flag_long_jumps
1509 && strncmp (instring, "jbsr", 4) == 0))
1510 losing++;
1511 break;
1512
1513 case 'C':
1514 if (opP->mode != CONTROL || opP->reg != CCR)
1515 losing++;
1516 break;
1517
1518 case 'd':
1519 if (opP->mode != DISP
1520 || opP->reg < ADDR0
1521 || opP->reg > ADDR7)
1522 losing++;
1523 break;
1524
1525 case 'D':
1526 if (opP->mode != DREG)
1527 losing++;
1528 break;
1529
1530 case 'E':
1531 if (opP->reg != ACC)
1532 losing++;
1533 break;
1534
1535 case 'F':
1536 if (opP->mode != FPREG)
1537 losing++;
1538 break;
1539
1540 case 'G':
1541 if (opP->reg != MACSR)
1542 losing++;
1543 break;
1544
1545 case 'H':
1546 if (opP->reg != MASK)
1547 losing++;
1548 break;
1549
1550 case 'I':
1551 if (opP->mode != CONTROL
1552 || opP->reg < COP0
1553 || opP->reg > COP7)
1554 losing++;
1555 break;
1556
1557 case 'J':
1558 if (opP->mode != CONTROL
1559 || opP->reg < USP
1560 || opP->reg > last_movec_reg)
1561 losing++;
1562 else
1563 {
1564 const enum m68k_register *rp;
1565 for (rp = control_regs; *rp; rp++)
1566 if (*rp == opP->reg)
1567 break;
1568 if (*rp == 0)
1569 losing++;
1570 }
1571 break;
1572
1573 case 'k':
1574 if (opP->mode != IMMED)
1575 losing++;
1576 break;
1577
1578 case 'l':
1579 case 'L':
1580 if (opP->mode == DREG
1581 || opP->mode == AREG
1582 || opP->mode == FPREG)
1583 {
1584 if (s[1] == '8')
1585 losing++;
1586 else
1587 {
1588 switch (opP->mode)
1589 {
1590 case DREG:
1591 opP->mask = 1 << (opP->reg - DATA0);
1592 break;
1593 case AREG:
1594 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1595 break;
1596 case FPREG:
1597 opP->mask = 1 << (opP->reg - FP0 + 16);
1598 break;
1599 default:
1600 abort ();
1601 }
1602 opP->mode = REGLST;
1603 }
1604 }
1605 else if (opP->mode == CONTROL)
1606 {
1607 if (s[1] != '8')
1608 losing++;
1609 else
1610 {
1611 switch (opP->reg)
1612 {
1613 case FPI:
1614 opP->mask = 1 << 24;
1615 break;
1616 case FPS:
1617 opP->mask = 1 << 25;
1618 break;
1619 case FPC:
1620 opP->mask = 1 << 26;
1621 break;
1622 default:
1623 losing++;
1624 break;
1625 }
1626 opP->mode = REGLST;
1627 }
1628 }
1629 else if (opP->mode != REGLST)
1630 losing++;
1631 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1632 losing++;
1633 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1634 losing++;
1635 break;
1636
1637 case 'M':
1638 if (opP->mode != IMMED)
1639 losing++;
1640 else if (opP->disp.exp.X_op != O_constant
1641 || ! issbyte (opP->disp.exp.X_add_number))
1642 losing++;
1643 else if (! m68k_quick
1644 && instring[3] != 'q'
1645 && instring[4] != 'q')
1646 losing++;
1647 break;
1648
1649 case 'O':
1650 if (opP->mode != DREG
1651 && opP->mode != IMMED
1652 && opP->mode != ABSL)
1653 losing++;
1654 break;
1655
1656 case 'Q':
1657 if (opP->mode != IMMED)
1658 losing++;
1659 else if (opP->disp.exp.X_op != O_constant
1660 || opP->disp.exp.X_add_number < 1
1661 || opP->disp.exp.X_add_number > 8)
1662 losing++;
1663 else if (! m68k_quick
1664 && (strncmp (instring, "add", 3) == 0
1665 || strncmp (instring, "sub", 3) == 0)
1666 && instring[3] != 'q')
1667 losing++;
1668 break;
1669
1670 case 'R':
1671 if (opP->mode != DREG && opP->mode != AREG)
1672 losing++;
1673 break;
1674
1675 case 'r':
1676 if (opP->mode != AINDR
1677 && (opP->mode != BASE
1678 || (opP->reg != 0
1679 && opP->reg != ZADDR0)
1680 || opP->disp.exp.X_op != O_absent
1681 || ((opP->index.reg < DATA0
1682 || opP->index.reg > DATA7)
1683 && (opP->index.reg < ADDR0
1684 || opP->index.reg > ADDR7))
1685 || opP->index.size != SIZE_UNSPEC
1686 || opP->index.scale != 1))
1687 losing++;
1688 break;
1689
1690 case 's':
1691 if (opP->mode != CONTROL
1692 || ! (opP->reg == FPI
1693 || opP->reg == FPS
1694 || opP->reg == FPC))
1695 losing++;
1696 break;
1697
1698 case 'S':
1699 if (opP->mode != CONTROL || opP->reg != SR)
1700 losing++;
1701 break;
1702
1703 case 't':
1704 if (opP->mode != IMMED)
1705 losing++;
1706 else if (opP->disp.exp.X_op != O_constant
1707 || opP->disp.exp.X_add_number < 0
1708 || opP->disp.exp.X_add_number > 7)
1709 losing++;
1710 break;
1711
1712 case 'U':
1713 if (opP->mode != CONTROL || opP->reg != USP)
1714 losing++;
1715 break;
1716
1717 /* JF these are out of order. We could put them
1718 in order if we were willing to put up with
1719 bunches of #ifdef m68851s in the code.
1720
1721 Don't forget that you need these operands
1722 to use 68030 MMU instructions. */
1723 #ifndef NO_68851
1724 /* Memory addressing mode used by pflushr */
1725 case '|':
1726 if (opP->mode == CONTROL
1727 || opP->mode == FPREG
1728 || opP->mode == DREG
1729 || opP->mode == AREG
1730 || opP->mode == REGLST)
1731 losing++;
1732 /* We should accept immediate operands, but they
1733 supposedly have to be quad word, and we don't
1734 handle that. I would like to see what a Motorola
1735 assembler does before doing something here. */
1736 if (opP->mode == IMMED)
1737 losing++;
1738 break;
1739
1740 case 'f':
1741 if (opP->mode != CONTROL
1742 || (opP->reg != SFC && opP->reg != DFC))
1743 losing++;
1744 break;
1745
1746 case '0':
1747 if (opP->mode != CONTROL || opP->reg != TC)
1748 losing++;
1749 break;
1750
1751 case '1':
1752 if (opP->mode != CONTROL || opP->reg != AC)
1753 losing++;
1754 break;
1755
1756 case '2':
1757 if (opP->mode != CONTROL
1758 || (opP->reg != CAL
1759 && opP->reg != VAL
1760 && opP->reg != SCC))
1761 losing++;
1762 break;
1763
1764 case 'V':
1765 if (opP->mode != CONTROL
1766 || opP->reg != VAL)
1767 losing++;
1768 break;
1769
1770 case 'W':
1771 if (opP->mode != CONTROL
1772 || (opP->reg != DRP
1773 && opP->reg != SRP
1774 && opP->reg != CRP))
1775 losing++;
1776 break;
1777
1778 case 'X':
1779 if (opP->mode != CONTROL
1780 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1781 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1782 losing++;
1783 break;
1784
1785 case 'Y':
1786 if (opP->mode != CONTROL || opP->reg != PSR)
1787 losing++;
1788 break;
1789
1790 case 'Z':
1791 if (opP->mode != CONTROL || opP->reg != PCSR)
1792 losing++;
1793 break;
1794 #endif
1795 case 'c':
1796 if (opP->mode != CONTROL
1797 || (opP->reg != NC
1798 && opP->reg != IC
1799 && opP->reg != DC
1800 && opP->reg != BC))
1801 {
1802 losing++;
1803 } /* not a cache specifier. */
1804 break;
1805
1806 case '_':
1807 if (opP->mode != ABSL)
1808 ++losing;
1809 break;
1810
1811 case 'u':
1812 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1813 losing++;
1814 /* FIXME: kludge instead of fixing parser:
1815 upper/lower registers are *not* CONTROL
1816 registers, but ordinary ones. */
1817 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1818 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1819 opP->mode = DREG;
1820 else
1821 opP->mode = AREG;
1822 break;
1823
1824 default:
1825 abort ();
1826 } /* switch on type of operand */
1827
1828 if (losing)
1829 break;
1830 } /* for each operand */
1831 } /* if immediately wrong */
1832
1833 if (!losing)
1834 {
1835 break;
1836 } /* got it. */
1837
1838 opcode = opcode->m_next;
1839
1840 if (!opcode)
1841 {
1842 if (ok_arch
1843 && !(ok_arch & current_architecture))
1844 {
1845 char buf[200], *cp;
1846
1847 strcpy (buf,
1848 _("invalid instruction for this architecture; needs "));
1849 cp = buf + strlen (buf);
1850 switch (ok_arch)
1851 {
1852 case mfloat:
1853 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1854 break;
1855 case mmmu:
1856 strcpy (cp, _("mmu (68030 or 68851)"));
1857 break;
1858 case m68020up:
1859 strcpy (cp, _("68020 or higher"));
1860 break;
1861 case m68000up:
1862 strcpy (cp, _("68000 or higher"));
1863 break;
1864 case m68010up:
1865 strcpy (cp, _("68010 or higher"));
1866 break;
1867 default:
1868 {
1869 int got_one = 0, idx;
1870 for (idx = 0;
1871 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1872 idx++)
1873 {
1874 if ((archs[idx].arch & ok_arch)
1875 && ! archs[idx].alias)
1876 {
1877 if (got_one)
1878 {
1879 strcpy (cp, " or ");
1880 cp += strlen (cp);
1881 }
1882 got_one = 1;
1883 strcpy (cp, archs[idx].name);
1884 cp += strlen (cp);
1885 }
1886 }
1887 }
1888 }
1889 cp = xmalloc (strlen (buf) + 1);
1890 strcpy (cp, buf);
1891 the_ins.error = cp;
1892 }
1893 else
1894 the_ins.error = _("operands mismatch");
1895 return;
1896 } /* Fell off the end */
1897
1898 losing = 0;
1899 }
1900
1901 /* now assemble it */
1902
1903 the_ins.args = opcode->m_operands;
1904 the_ins.numargs = opcode->m_opnum;
1905 the_ins.numo = opcode->m_codenum;
1906 the_ins.opcode[0] = getone (opcode);
1907 the_ins.opcode[1] = gettwo (opcode);
1908
1909 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1910 {
1911 /* This switch is a doozy.
1912 Watch the first step; its a big one! */
1913 switch (s[0])
1914 {
1915
1916 case '*':
1917 case '~':
1918 case '%':
1919 case ';':
1920 case '@':
1921 case '!':
1922 case '&':
1923 case '$':
1924 case '?':
1925 case '/':
1926 case '<':
1927 case '>':
1928 case 'm':
1929 case 'n':
1930 case 'o':
1931 case 'p':
1932 case 'q':
1933 case 'v':
1934 #ifndef NO_68851
1935 case '|':
1936 #endif
1937 switch (opP->mode)
1938 {
1939 case IMMED:
1940 tmpreg = 0x3c; /* 7.4 */
1941 if (strchr ("bwl", s[1]))
1942 nextword = get_num (&opP->disp, 80);
1943 else
1944 nextword = get_num (&opP->disp, 0);
1945 if (isvar (&opP->disp))
1946 add_fix (s[1], &opP->disp, 0, 0);
1947 switch (s[1])
1948 {
1949 case 'b':
1950 if (!isbyte (nextword))
1951 opP->error = _("operand out of range");
1952 addword (nextword);
1953 baseo = 0;
1954 break;
1955 case 'w':
1956 if (!isword (nextword))
1957 opP->error = _("operand out of range");
1958 addword (nextword);
1959 baseo = 0;
1960 break;
1961 case 'W':
1962 if (!issword (nextword))
1963 opP->error = _("operand out of range");
1964 addword (nextword);
1965 baseo = 0;
1966 break;
1967 case 'l':
1968 addword (nextword >> 16);
1969 addword (nextword);
1970 baseo = 0;
1971 break;
1972
1973 case 'f':
1974 baseo = 2;
1975 outro = 8;
1976 break;
1977 case 'F':
1978 baseo = 4;
1979 outro = 11;
1980 break;
1981 case 'x':
1982 baseo = 6;
1983 outro = 15;
1984 break;
1985 case 'p':
1986 baseo = 6;
1987 outro = -1;
1988 break;
1989 default:
1990 abort ();
1991 }
1992 if (!baseo)
1993 break;
1994
1995 /* We gotta put out some float */
1996 if (op (&opP->disp) != O_big)
1997 {
1998 valueT val;
1999 int gencnt;
2000
2001 /* Can other cases happen here? */
2002 if (op (&opP->disp) != O_constant)
2003 abort ();
2004
2005 val = (valueT) offs (&opP->disp);
2006 gencnt = 0;
2007 do
2008 {
2009 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2010 val >>= LITTLENUM_NUMBER_OF_BITS;
2011 ++gencnt;
2012 }
2013 while (val != 0);
2014 offs (&opP->disp) = gencnt;
2015 }
2016 if (offs (&opP->disp) > 0)
2017 {
2018 if (offs (&opP->disp) > baseo)
2019 {
2020 as_warn (_("Bignum too big for %c format; truncated"),
2021 s[1]);
2022 offs (&opP->disp) = baseo;
2023 }
2024 baseo -= offs (&opP->disp);
2025 while (baseo--)
2026 addword (0);
2027 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2028 offs (&opP->disp)--;
2029 --wordp)
2030 addword (*wordp);
2031 break;
2032 }
2033 gen_to_words (words, baseo, (long) outro);
2034 for (wordp = words; baseo--; wordp++)
2035 addword (*wordp);
2036 break;
2037 case DREG:
2038 tmpreg = opP->reg - DATA; /* 0.dreg */
2039 break;
2040 case AREG:
2041 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2042 break;
2043 case AINDR:
2044 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2045 break;
2046 case ADEC:
2047 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2048 break;
2049 case AINC:
2050 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2051 break;
2052 case DISP:
2053
2054 nextword = get_num (&opP->disp, 80);
2055
2056 if (opP->reg == PC
2057 && ! isvar (&opP->disp)
2058 && m68k_abspcadd)
2059 {
2060 opP->disp.exp.X_op = O_symbol;
2061 #ifndef BFD_ASSEMBLER
2062 opP->disp.exp.X_add_symbol = &abs_symbol;
2063 #else
2064 opP->disp.exp.X_add_symbol =
2065 section_symbol (absolute_section);
2066 #endif
2067 }
2068
2069 /* Force into index mode. Hope this works */
2070
2071 /* We do the first bit for 32-bit displacements, and the
2072 second bit for 16 bit ones. It is possible that we
2073 should make the default be WORD instead of LONG, but
2074 I think that'd break GCC, so we put up with a little
2075 inefficiency for the sake of working output. */
2076
2077 if (!issword (nextword)
2078 || (isvar (&opP->disp)
2079 && ((opP->disp.size == SIZE_UNSPEC
2080 && flag_short_refs == 0
2081 && cpu_of_arch (current_architecture) >= m68020
2082 && ! arch_coldfire_p (current_architecture))
2083 || opP->disp.size == SIZE_LONG)))
2084 {
2085 if (cpu_of_arch (current_architecture) < m68020
2086 || arch_coldfire_p (current_architecture))
2087 opP->error =
2088 _("displacement too large for this architecture; needs 68020 or higher");
2089 if (opP->reg == PC)
2090 tmpreg = 0x3B; /* 7.3 */
2091 else
2092 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2093 if (isvar (&opP->disp))
2094 {
2095 if (opP->reg == PC)
2096 {
2097 if (opP->disp.size == SIZE_LONG
2098 #ifdef OBJ_ELF
2099 /* If the displacement needs pic
2100 relocation it cannot be relaxed. */
2101 || opP->disp.pic_reloc != pic_none
2102 #endif
2103 )
2104 {
2105 addword (0x0170);
2106 add_fix ('l', &opP->disp, 1, 2);
2107 }
2108 else
2109 {
2110 add_frag (adds (&opP->disp),
2111 offs (&opP->disp),
2112 TAB (PCREL1632, SZ_UNDEF));
2113 break;
2114 }
2115 }
2116 else
2117 {
2118 addword (0x0170);
2119 add_fix ('l', &opP->disp, 0, 0);
2120 }
2121 }
2122 else
2123 addword (0x0170);
2124 addword (nextword >> 16);
2125 }
2126 else
2127 {
2128 if (opP->reg == PC)
2129 tmpreg = 0x3A; /* 7.2 */
2130 else
2131 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2132
2133 if (isvar (&opP->disp))
2134 {
2135 if (opP->reg == PC)
2136 {
2137 add_fix ('w', &opP->disp, 1, 0);
2138 }
2139 else
2140 add_fix ('w', &opP->disp, 0, 0);
2141 }
2142 }
2143 addword (nextword);
2144 break;
2145
2146 case POST:
2147 case PRE:
2148 case BASE:
2149 nextword = 0;
2150 baseo = get_num (&opP->disp, 80);
2151 if (opP->mode == POST || opP->mode == PRE)
2152 outro = get_num (&opP->odisp, 80);
2153 /* Figure out the `addressing mode'.
2154 Also turn on the BASE_DISABLE bit, if needed. */
2155 if (opP->reg == PC || opP->reg == ZPC)
2156 {
2157 tmpreg = 0x3b; /* 7.3 */
2158 if (opP->reg == ZPC)
2159 nextword |= 0x80;
2160 }
2161 else if (opP->reg == 0)
2162 {
2163 nextword |= 0x80;
2164 tmpreg = 0x30; /* 6.garbage */
2165 }
2166 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2167 {
2168 nextword |= 0x80;
2169 tmpreg = 0x30 + opP->reg - ZADDR0;
2170 }
2171 else
2172 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2173
2174 siz1 = opP->disp.size;
2175 if (opP->mode == POST || opP->mode == PRE)
2176 siz2 = opP->odisp.size;
2177 else
2178 siz2 = SIZE_UNSPEC;
2179
2180 /* Index register stuff */
2181 if (opP->index.reg != 0
2182 && opP->index.reg >= DATA
2183 && opP->index.reg <= ADDR7)
2184 {
2185 nextword |= (opP->index.reg - DATA) << 12;
2186
2187 if (opP->index.size == SIZE_LONG
2188 || (opP->index.size == SIZE_UNSPEC
2189 && m68k_index_width_default == SIZE_LONG))
2190 nextword |= 0x800;
2191
2192 if ((opP->index.scale != 1
2193 && cpu_of_arch (current_architecture) < m68020)
2194 || (opP->index.scale == 8
2195 && arch_coldfire_p (current_architecture)))
2196 {
2197 opP->error =
2198 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2199 }
2200
2201 if (arch_coldfire_p (current_architecture)
2202 && opP->index.size == SIZE_WORD)
2203 opP->error = _("invalid index size for coldfire");
2204
2205 switch (opP->index.scale)
2206 {
2207 case 1:
2208 break;
2209 case 2:
2210 nextword |= 0x200;
2211 break;
2212 case 4:
2213 nextword |= 0x400;
2214 break;
2215 case 8:
2216 nextword |= 0x600;
2217 break;
2218 default:
2219 abort ();
2220 }
2221 /* IF its simple,
2222 GET US OUT OF HERE! */
2223
2224 /* Must be INDEX, with an index register. Address
2225 register cannot be ZERO-PC, and either :b was
2226 forced, or we know it will fit. For a 68000 or
2227 68010, force this mode anyways, because the
2228 larger modes aren't supported. */
2229 if (opP->mode == BASE
2230 && ((opP->reg >= ADDR0
2231 && opP->reg <= ADDR7)
2232 || opP->reg == PC))
2233 {
2234 if (siz1 == SIZE_BYTE
2235 || cpu_of_arch (current_architecture) < m68020
2236 || arch_coldfire_p (current_architecture)
2237 || (siz1 == SIZE_UNSPEC
2238 && ! isvar (&opP->disp)
2239 && issbyte (baseo)))
2240 {
2241 nextword += baseo & 0xff;
2242 addword (nextword);
2243 if (isvar (&opP->disp))
2244 {
2245 /* Do a byte relocation. If it doesn't
2246 fit (possible on m68000) let the
2247 fixup processing complain later. */
2248 if (opP->reg == PC)
2249 add_fix ('B', &opP->disp, 1, 1);
2250 else
2251 add_fix ('B', &opP->disp, 0, 0);
2252 }
2253 else if (siz1 != SIZE_BYTE)
2254 {
2255 if (siz1 != SIZE_UNSPEC)
2256 as_warn (_("Forcing byte displacement"));
2257 if (! issbyte (baseo))
2258 opP->error = _("byte displacement out of range");
2259 }
2260
2261 break;
2262 }
2263 else if (siz1 == SIZE_UNSPEC
2264 && opP->reg == PC
2265 && isvar (&opP->disp)
2266 && subs (&opP->disp) == NULL
2267 #ifdef OBJ_ELF
2268 /* If the displacement needs pic
2269 relocation it cannot be relaxed. */
2270 && opP->disp.pic_reloc == pic_none
2271 #endif
2272 )
2273 {
2274 /* The code in md_convert_frag_1 needs to be
2275 able to adjust nextword. Call frag_grow
2276 to ensure that we have enough space in
2277 the frag obstack to make all the bytes
2278 contiguous. */
2279 frag_grow (14);
2280 nextword += baseo & 0xff;
2281 addword (nextword);
2282 add_frag (adds (&opP->disp), offs (&opP->disp),
2283 TAB (PCINDEX, SZ_UNDEF));
2284
2285 break;
2286 }
2287 }
2288 }
2289 else
2290 {
2291 nextword |= 0x40; /* No index reg */
2292 if (opP->index.reg >= ZDATA0
2293 && opP->index.reg <= ZDATA7)
2294 nextword |= (opP->index.reg - ZDATA0) << 12;
2295 else if (opP->index.reg >= ZADDR0
2296 || opP->index.reg <= ZADDR7)
2297 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2298 }
2299
2300 /* It isn't simple. */
2301
2302 if (cpu_of_arch (current_architecture) < m68020
2303 || arch_coldfire_p (current_architecture))
2304 opP->error =
2305 _("invalid operand mode for this architecture; needs 68020 or higher");
2306
2307 nextword |= 0x100;
2308 /* If the guy specified a width, we assume that it is
2309 wide enough. Maybe it isn't. If so, we lose. */
2310 switch (siz1)
2311 {
2312 case SIZE_UNSPEC:
2313 if (isvar (&opP->disp)
2314 ? m68k_rel32
2315 : ! issword (baseo))
2316 {
2317 siz1 = SIZE_LONG;
2318 nextword |= 0x30;
2319 }
2320 else if (! isvar (&opP->disp) && baseo == 0)
2321 nextword |= 0x10;
2322 else
2323 {
2324 nextword |= 0x20;
2325 siz1 = SIZE_WORD;
2326 }
2327 break;
2328 case SIZE_BYTE:
2329 as_warn (_(":b not permitted; defaulting to :w"));
2330 /* Fall through. */
2331 case SIZE_WORD:
2332 nextword |= 0x20;
2333 break;
2334 case SIZE_LONG:
2335 nextword |= 0x30;
2336 break;
2337 }
2338
2339 /* Figure out innner displacement stuff */
2340 if (opP->mode == POST || opP->mode == PRE)
2341 {
2342 if (cpu_of_arch (current_architecture) & cpu32)
2343 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2344 switch (siz2)
2345 {
2346 case SIZE_UNSPEC:
2347 if (isvar (&opP->odisp)
2348 ? m68k_rel32
2349 : ! issword (outro))
2350 {
2351 siz2 = SIZE_LONG;
2352 nextword |= 0x3;
2353 }
2354 else if (! isvar (&opP->odisp) && outro == 0)
2355 nextword |= 0x1;
2356 else
2357 {
2358 nextword |= 0x2;
2359 siz2 = SIZE_WORD;
2360 }
2361 break;
2362 case 1:
2363 as_warn (_(":b not permitted; defaulting to :w"));
2364 /* Fall through. */
2365 case 2:
2366 nextword |= 0x2;
2367 break;
2368 case 3:
2369 nextword |= 0x3;
2370 break;
2371 }
2372 if (opP->mode == POST
2373 && (nextword & 0x40) == 0)
2374 nextword |= 0x04;
2375 }
2376 addword (nextword);
2377
2378 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2379 {
2380 if (opP->reg == PC || opP->reg == ZPC)
2381 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2382 else
2383 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2384 }
2385 if (siz1 == SIZE_LONG)
2386 addword (baseo >> 16);
2387 if (siz1 != SIZE_UNSPEC)
2388 addword (baseo);
2389
2390 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2391 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2392 if (siz2 == SIZE_LONG)
2393 addword (outro >> 16);
2394 if (siz2 != SIZE_UNSPEC)
2395 addword (outro);
2396
2397 break;
2398
2399 case ABSL:
2400 nextword = get_num (&opP->disp, 80);
2401 switch (opP->disp.size)
2402 {
2403 default:
2404 abort ();
2405 case SIZE_UNSPEC:
2406 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2407 {
2408 tmpreg = 0x38; /* 7.0 */
2409 addword (nextword);
2410 break;
2411 }
2412 if (isvar (&opP->disp)
2413 && !subs (&opP->disp)
2414 && adds (&opP->disp)
2415 #ifdef OBJ_ELF
2416 /* If the displacement needs pic relocation it
2417 cannot be relaxed. */
2418 && opP->disp.pic_reloc == pic_none
2419 #endif
2420 && !flag_long_jumps
2421 && !strchr ("~%&$?", s[0]))
2422 {
2423 tmpreg = 0x3A; /* 7.2 */
2424 add_frag (adds (&opP->disp),
2425 offs (&opP->disp),
2426 TAB (ABSTOPCREL, SZ_UNDEF));
2427 break;
2428 }
2429 /* Fall through into long */
2430 case SIZE_LONG:
2431 if (isvar (&opP->disp))
2432 add_fix ('l', &opP->disp, 0, 0);
2433
2434 tmpreg = 0x39;/* 7.1 mode */
2435 addword (nextword >> 16);
2436 addword (nextword);
2437 break;
2438
2439 case SIZE_BYTE:
2440 as_bad (_("unsupported byte value; use a different suffix"));
2441 /* Fall through. */
2442 case SIZE_WORD: /* Word */
2443 if (isvar (&opP->disp))
2444 add_fix ('w', &opP->disp, 0, 0);
2445
2446 tmpreg = 0x38;/* 7.0 mode */
2447 addword (nextword);
2448 break;
2449 }
2450 break;
2451 case CONTROL:
2452 case FPREG:
2453 default:
2454 as_bad (_("unknown/incorrect operand"));
2455 /* abort (); */
2456 }
2457 install_gen_operand (s[1], tmpreg);
2458 break;
2459
2460 case '#':
2461 case '^':
2462 switch (s[1])
2463 { /* JF: I hate floating point! */
2464 case 'j':
2465 tmpreg = 70;
2466 break;
2467 case '8':
2468 tmpreg = 20;
2469 break;
2470 case 'C':
2471 tmpreg = 50;
2472 break;
2473 case '3':
2474 default:
2475 tmpreg = 80;
2476 break;
2477 }
2478 tmpreg = get_num (&opP->disp, tmpreg);
2479 if (isvar (&opP->disp))
2480 add_fix (s[1], &opP->disp, 0, 0);
2481 switch (s[1])
2482 {
2483 case 'b': /* Danger: These do no check for
2484 certain types of overflow.
2485 user beware! */
2486 if (!isbyte (tmpreg))
2487 opP->error = _("out of range");
2488 insop (tmpreg, opcode);
2489 if (isvar (&opP->disp))
2490 the_ins.reloc[the_ins.nrel - 1].n =
2491 (opcode->m_codenum) * 2 + 1;
2492 break;
2493 case 'B':
2494 if (!issbyte (tmpreg))
2495 opP->error = _("out of range");
2496 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2497 if (isvar (&opP->disp))
2498 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2499 break;
2500 case 'w':
2501 if (!isword (tmpreg))
2502 opP->error = _("out of range");
2503 insop (tmpreg, opcode);
2504 if (isvar (&opP->disp))
2505 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2506 break;
2507 case 'W':
2508 if (!issword (tmpreg))
2509 opP->error = _("out of range");
2510 insop (tmpreg, opcode);
2511 if (isvar (&opP->disp))
2512 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2513 break;
2514 case 'l':
2515 /* Because of the way insop works, we put these two out
2516 backwards. */
2517 insop (tmpreg, opcode);
2518 insop (tmpreg >> 16, opcode);
2519 if (isvar (&opP->disp))
2520 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2521 break;
2522 case '3':
2523 tmpreg &= 0xFF;
2524 case '8':
2525 case 'C':
2526 case 'j':
2527 install_operand (s[1], tmpreg);
2528 break;
2529 default:
2530 abort ();
2531 }
2532 break;
2533
2534 case '+':
2535 case '-':
2536 case 'A':
2537 case 'a':
2538 install_operand (s[1], opP->reg - ADDR);
2539 break;
2540
2541 case 'B':
2542 tmpreg = get_num (&opP->disp, 80);
2543 switch (s[1])
2544 {
2545 case 'B':
2546 add_fix ('B', &opP->disp, 1, -1);
2547 break;
2548 case 'W':
2549 add_fix ('w', &opP->disp, 1, 0);
2550 addword (0);
2551 break;
2552 case 'L':
2553 long_branch:
2554 if (! HAVE_LONG_BRANCH (current_architecture))
2555 as_warn (_("Can't use long branches on 68000/68010/5200"));
2556 the_ins.opcode[0] |= 0xff;
2557 add_fix ('l', &opP->disp, 1, 0);
2558 addword (0);
2559 addword (0);
2560 break;
2561 case 'g':
2562 if (subs (&opP->disp)) /* We can't relax it */
2563 goto long_branch;
2564
2565 #ifdef OBJ_ELF
2566 /* If the displacement needs pic relocation it cannot be
2567 relaxed. */
2568 if (opP->disp.pic_reloc != pic_none)
2569 goto long_branch;
2570 #endif
2571 /* This could either be a symbol, or an absolute
2572 address. If it's an absolute address, turn it into
2573 an absolute jump right here and keep it out of the
2574 relaxer. */
2575 if (adds (&opP->disp) == 0)
2576 {
2577 if (the_ins.opcode[0] == 0x6000) /* jbra */
2578 the_ins.opcode[0] = 0x4EF1;
2579 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2580 the_ins.opcode[0] = 0x4EB1;
2581 else /* jCC */
2582 {
2583 the_ins.opcode[0] ^= 0x0100;
2584 the_ins.opcode[0] |= 0x0006;
2585 addword (0x4EF1);
2586 }
2587 add_fix ('l', &opP->disp, 0, 0);
2588 addword (0);
2589 addword (0);
2590 break;
2591 }
2592
2593 /* Now we know it's going into the relaxer. Now figure
2594 out which mode. We try in this order of preference:
2595 long branch, absolute jump, byte/word branches only. */
2596 if (HAVE_LONG_BRANCH (current_architecture))
2597 add_frag (adds (&opP->disp), offs (&opP->disp),
2598 TAB (BRANCHBWL, SZ_UNDEF));
2599 else if (! flag_keep_pcrel)
2600 {
2601 if ((the_ins.opcode[0] == 0x6000)
2602 || (the_ins.opcode[0] == 0x6100))
2603 add_frag (adds (&opP->disp), offs (&opP->disp),
2604 TAB (BRABSJUNC, SZ_UNDEF));
2605 else
2606 add_frag (adds (&opP->disp), offs (&opP->disp),
2607 TAB (BRABSJCOND, SZ_UNDEF));
2608 }
2609 else
2610 add_frag (adds (&opP->disp), offs (&opP->disp),
2611 TAB (BRANCHBW, SZ_UNDEF));
2612 break;
2613 case 'w':
2614 if (isvar (&opP->disp))
2615 {
2616 /* Check for DBcc instructions. We can relax them,
2617 but only if we have long branches and/or absolute
2618 jumps. */
2619 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2620 && (HAVE_LONG_BRANCH (current_architecture)
2621 || (! flag_keep_pcrel)))
2622 {
2623 if (HAVE_LONG_BRANCH (current_architecture))
2624 add_frag (adds (&opP->disp), offs (&opP->disp),
2625 TAB (DBCCLBR, SZ_UNDEF));
2626 else
2627 add_frag (adds (&opP->disp), offs (&opP->disp),
2628 TAB (DBCCABSJ, SZ_UNDEF));
2629 break;
2630 }
2631 add_fix ('w', &opP->disp, 1, 0);
2632 }
2633 addword (0);
2634 break;
2635 case 'C': /* Fixed size LONG coproc branches */
2636 add_fix ('l', &opP->disp, 1, 0);
2637 addword (0);
2638 addword (0);
2639 break;
2640 case 'c': /* Var size Coprocesssor branches */
2641 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2642 {
2643 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2644 add_fix ('l', &opP->disp, 1, 0);
2645 addword (0);
2646 addword (0);
2647 }
2648 else
2649 add_frag (adds (&opP->disp), offs (&opP->disp),
2650 TAB (FBRANCH, SZ_UNDEF));
2651 break;
2652 default:
2653 abort ();
2654 }
2655 break;
2656
2657 case 'C': /* Ignore it */
2658 break;
2659
2660 case 'd': /* JF this is a kludge */
2661 install_operand ('s', opP->reg - ADDR);
2662 tmpreg = get_num (&opP->disp, 80);
2663 if (!issword (tmpreg))
2664 {
2665 as_warn (_("Expression out of range, using 0"));
2666 tmpreg = 0;
2667 }
2668 addword (tmpreg);
2669 break;
2670
2671 case 'D':
2672 install_operand (s[1], opP->reg - DATA);
2673 break;
2674
2675 case 'E': /* Ignore it */
2676 break;
2677
2678 case 'F':
2679 install_operand (s[1], opP->reg - FP0);
2680 break;
2681
2682 case 'G': /* Ignore it */
2683 case 'H':
2684 break;
2685
2686 case 'I':
2687 tmpreg = opP->reg - COP0;
2688 install_operand (s[1], tmpreg);
2689 break;
2690
2691 case 'J': /* JF foo */
2692 switch (opP->reg)
2693 {
2694 case SFC:
2695 tmpreg = 0x000;
2696 break;
2697 case DFC:
2698 tmpreg = 0x001;
2699 break;
2700 case CACR:
2701 tmpreg = 0x002;
2702 break;
2703 case TC:
2704 tmpreg = 0x003;
2705 break;
2706 case ITT0:
2707 tmpreg = 0x004;
2708 break;
2709 case ITT1:
2710 tmpreg = 0x005;
2711 break;
2712 case DTT0:
2713 tmpreg = 0x006;
2714 break;
2715 case DTT1:
2716 tmpreg = 0x007;
2717 break;
2718 case BUSCR:
2719 tmpreg = 0x008;
2720 break;
2721
2722 case USP:
2723 tmpreg = 0x800;
2724 break;
2725 case VBR:
2726 tmpreg = 0x801;
2727 break;
2728 case CAAR:
2729 tmpreg = 0x802;
2730 break;
2731 case MSP:
2732 tmpreg = 0x803;
2733 break;
2734 case ISP:
2735 tmpreg = 0x804;
2736 break;
2737 case MMUSR:
2738 tmpreg = 0x805;
2739 break;
2740 case URP:
2741 tmpreg = 0x806;
2742 break;
2743 case SRP:
2744 tmpreg = 0x807;
2745 break;
2746 case PCR:
2747 tmpreg = 0x808;
2748 break;
2749 case ROMBAR:
2750 tmpreg = 0xC00;
2751 break;
2752 case RAMBAR0:
2753 tmpreg = 0xC04;
2754 break;
2755 case RAMBAR1:
2756 tmpreg = 0xC05;
2757 break;
2758 case MBAR:
2759 tmpreg = 0xC0F;
2760 break;
2761 default:
2762 abort ();
2763 }
2764 install_operand (s[1], tmpreg);
2765 break;
2766
2767 case 'k':
2768 tmpreg = get_num (&opP->disp, 55);
2769 install_operand (s[1], tmpreg & 0x7f);
2770 break;
2771
2772 case 'l':
2773 tmpreg = opP->mask;
2774 if (s[1] == 'w')
2775 {
2776 if (tmpreg & 0x7FF0000)
2777 as_bad (_("Floating point register in register list"));
2778 insop (reverse_16_bits (tmpreg), opcode);
2779 }
2780 else
2781 {
2782 if (tmpreg & 0x700FFFF)
2783 as_bad (_("Wrong register in floating-point reglist"));
2784 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2785 }
2786 break;
2787
2788 case 'L':
2789 tmpreg = opP->mask;
2790 if (s[1] == 'w')
2791 {
2792 if (tmpreg & 0x7FF0000)
2793 as_bad (_("Floating point register in register list"));
2794 insop (tmpreg, opcode);
2795 }
2796 else if (s[1] == '8')
2797 {
2798 if (tmpreg & 0x0FFFFFF)
2799 as_bad (_("incorrect register in reglist"));
2800 install_operand (s[1], tmpreg >> 24);
2801 }
2802 else
2803 {
2804 if (tmpreg & 0x700FFFF)
2805 as_bad (_("wrong register in floating-point reglist"));
2806 else
2807 install_operand (s[1], tmpreg >> 16);
2808 }
2809 break;
2810
2811 case 'M':
2812 install_operand (s[1], get_num (&opP->disp, 60));
2813 break;
2814
2815 case 'O':
2816 tmpreg = ((opP->mode == DREG)
2817 ? 0x20 + (int) (opP->reg - DATA)
2818 : (get_num (&opP->disp, 40) & 0x1F));
2819 install_operand (s[1], tmpreg);
2820 break;
2821
2822 case 'Q':
2823 tmpreg = get_num (&opP->disp, 10);
2824 if (tmpreg == 8)
2825 tmpreg = 0;
2826 install_operand (s[1], tmpreg);
2827 break;
2828
2829 case 'R':
2830 /* This depends on the fact that ADDR registers are eight
2831 more than their corresponding DATA regs, so the result
2832 will have the ADDR_REG bit set */
2833 install_operand (s[1], opP->reg - DATA);
2834 break;
2835
2836 case 'r':
2837 if (opP->mode == AINDR)
2838 install_operand (s[1], opP->reg - DATA);
2839 else
2840 install_operand (s[1], opP->index.reg - DATA);
2841 break;
2842
2843 case 's':
2844 if (opP->reg == FPI)
2845 tmpreg = 0x1;
2846 else if (opP->reg == FPS)
2847 tmpreg = 0x2;
2848 else if (opP->reg == FPC)
2849 tmpreg = 0x4;
2850 else
2851 abort ();
2852 install_operand (s[1], tmpreg);
2853 break;
2854
2855 case 'S': /* Ignore it */
2856 break;
2857
2858 case 'T':
2859 install_operand (s[1], get_num (&opP->disp, 30));
2860 break;
2861
2862 case 'U': /* Ignore it */
2863 break;
2864
2865 case 'c':
2866 switch (opP->reg)
2867 {
2868 case NC:
2869 tmpreg = 0;
2870 break;
2871 case DC:
2872 tmpreg = 1;
2873 break;
2874 case IC:
2875 tmpreg = 2;
2876 break;
2877 case BC:
2878 tmpreg = 3;
2879 break;
2880 default:
2881 as_fatal (_("failed sanity check"));
2882 } /* switch on cache token */
2883 install_operand (s[1], tmpreg);
2884 break;
2885 #ifndef NO_68851
2886 /* JF: These are out of order, I fear. */
2887 case 'f':
2888 switch (opP->reg)
2889 {
2890 case SFC:
2891 tmpreg = 0;
2892 break;
2893 case DFC:
2894 tmpreg = 1;
2895 break;
2896 default:
2897 abort ();
2898 }
2899 install_operand (s[1], tmpreg);
2900 break;
2901
2902 case '0':
2903 case '1':
2904 case '2':
2905 switch (opP->reg)
2906 {
2907 case TC:
2908 tmpreg = 0;
2909 break;
2910 case CAL:
2911 tmpreg = 4;
2912 break;
2913 case VAL:
2914 tmpreg = 5;
2915 break;
2916 case SCC:
2917 tmpreg = 6;
2918 break;
2919 case AC:
2920 tmpreg = 7;
2921 break;
2922 default:
2923 abort ();
2924 }
2925 install_operand (s[1], tmpreg);
2926 break;
2927
2928 case 'V':
2929 if (opP->reg == VAL)
2930 break;
2931 abort ();
2932
2933 case 'W':
2934 switch (opP->reg)
2935 {
2936 case DRP:
2937 tmpreg = 1;
2938 break;
2939 case SRP:
2940 tmpreg = 2;
2941 break;
2942 case CRP:
2943 tmpreg = 3;
2944 break;
2945 default:
2946 abort ();
2947 }
2948 install_operand (s[1], tmpreg);
2949 break;
2950
2951 case 'X':
2952 switch (opP->reg)
2953 {
2954 case BAD:
2955 case BAD + 1:
2956 case BAD + 2:
2957 case BAD + 3:
2958 case BAD + 4:
2959 case BAD + 5:
2960 case BAD + 6:
2961 case BAD + 7:
2962 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2963 break;
2964
2965 case BAC:
2966 case BAC + 1:
2967 case BAC + 2:
2968 case BAC + 3:
2969 case BAC + 4:
2970 case BAC + 5:
2971 case BAC + 6:
2972 case BAC + 7:
2973 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2974 break;
2975
2976 default:
2977 abort ();
2978 }
2979 install_operand (s[1], tmpreg);
2980 break;
2981 case 'Y':
2982 know (opP->reg == PSR);
2983 break;
2984 case 'Z':
2985 know (opP->reg == PCSR);
2986 break;
2987 #endif /* m68851 */
2988 case '3':
2989 switch (opP->reg)
2990 {
2991 case TT0:
2992 tmpreg = 2;
2993 break;
2994 case TT1:
2995 tmpreg = 3;
2996 break;
2997 default:
2998 abort ();
2999 }
3000 install_operand (s[1], tmpreg);
3001 break;
3002 case 't':
3003 tmpreg = get_num (&opP->disp, 20);
3004 install_operand (s[1], tmpreg);
3005 break;
3006 case '_': /* used only for move16 absolute 32-bit address */
3007 if (isvar (&opP->disp))
3008 add_fix ('l', &opP->disp, 0, 0);
3009 tmpreg = get_num (&opP->disp, 80);
3010 addword (tmpreg >> 16);
3011 addword (tmpreg & 0xFFFF);
3012 break;
3013 case 'u':
3014 install_operand (s[1], opP->reg - DATA0L);
3015 opP->reg -= (DATA0L);
3016 opP->reg &= 0x0F; /* remove upper/lower bit */
3017 break;
3018 default:
3019 abort ();
3020 }
3021 }
3022
3023 /* By the time whe get here (FINALLY) the_ins contains the complete
3024 instruction, ready to be emitted. . . */
3025 }
3026
3027 static int
3028 reverse_16_bits (in)
3029 int in;
3030 {
3031 int out = 0;
3032 int n;
3033
3034 static int mask[16] =
3035 {
3036 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3037 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3038 };
3039 for (n = 0; n < 16; n++)
3040 {
3041 if (in & mask[n])
3042 out |= mask[15 - n];
3043 }
3044 return out;
3045 } /* reverse_16_bits() */
3046
3047 static int
3048 reverse_8_bits (in)
3049 int in;
3050 {
3051 int out = 0;
3052 int n;
3053
3054 static int mask[8] =
3055 {
3056 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3057 };
3058
3059 for (n = 0; n < 8; n++)
3060 {
3061 if (in & mask[n])
3062 out |= mask[7 - n];
3063 }
3064 return out;
3065 } /* reverse_8_bits() */
3066
3067 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3068 (that value is chosen in the frag_var call in md_assemble). TYPE
3069 is the subtype of the frag to be generated; its primary type is
3070 rs_machine_dependent.
3071
3072 The TYPE parameter is also used by md_convert_frag_1 and
3073 md_estimate_size_before_relax. The appropriate type of fixup will
3074 be emitted by md_convert_frag_1.
3075
3076 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3077 static void
3078 install_operand (mode, val)
3079 int mode;
3080 int val;
3081 {
3082 switch (mode)
3083 {
3084 case 's':
3085 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3086 break;
3087 case 'd':
3088 the_ins.opcode[0] |= val << 9;
3089 break;
3090 case '1':
3091 the_ins.opcode[1] |= val << 12;
3092 break;
3093 case '2':
3094 the_ins.opcode[1] |= val << 6;
3095 break;
3096 case '3':
3097 the_ins.opcode[1] |= val;
3098 break;
3099 case '4':
3100 the_ins.opcode[2] |= val << 12;
3101 break;
3102 case '5':
3103 the_ins.opcode[2] |= val << 6;
3104 break;
3105 case '6':
3106 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3107 three words long! */
3108 the_ins.numo++;
3109 the_ins.opcode[2] |= val;
3110 break;
3111 case '7':
3112 the_ins.opcode[1] |= val << 7;
3113 break;
3114 case '8':
3115 the_ins.opcode[1] |= val << 10;
3116 break;
3117 #ifndef NO_68851
3118 case '9':
3119 the_ins.opcode[1] |= val << 5;
3120 break;
3121 #endif
3122
3123 case 't':
3124 the_ins.opcode[1] |= (val << 10) | (val << 7);
3125 break;
3126 case 'D':
3127 the_ins.opcode[1] |= (val << 12) | val;
3128 break;
3129 case 'g':
3130 the_ins.opcode[0] |= val = 0xff;
3131 break;
3132 case 'i':
3133 the_ins.opcode[0] |= val << 9;
3134 break;
3135 case 'C':
3136 the_ins.opcode[1] |= val;
3137 break;
3138 case 'j':
3139 the_ins.opcode[1] |= val;
3140 the_ins.numo++; /* What a hack */
3141 break;
3142 case 'k':
3143 the_ins.opcode[1] |= val << 4;
3144 break;
3145 case 'b':
3146 case 'w':
3147 case 'W':
3148 case 'l':
3149 break;
3150 case 'e':
3151 the_ins.opcode[0] |= (val << 6);
3152 break;
3153 case 'L':
3154 the_ins.opcode[1] = (val >> 16);
3155 the_ins.opcode[2] = val & 0xffff;
3156 break;
3157 case 'm':
3158 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3159 the_ins.opcode[0] |= ((val & 0x7) << 9);
3160 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3161 break;
3162 case 'n':
3163 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3164 the_ins.opcode[0] |= ((val & 0x7) << 9);
3165 break;
3166 case 'o':
3167 the_ins.opcode[1] |= val << 12;
3168 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3169 break;
3170 case 'M':
3171 the_ins.opcode[0] |= (val & 0xF);
3172 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3173 break;
3174 case 'N':
3175 the_ins.opcode[1] |= (val & 0xF);
3176 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3177 break;
3178 case 'h':
3179 the_ins.opcode[1] |= ((val != 1) << 10);
3180 break;
3181 case 'c':
3182 default:
3183 as_fatal (_("failed sanity check."));
3184 }
3185 } /* install_operand() */
3186
3187 static void
3188 install_gen_operand (mode, val)
3189 int mode;
3190 int val;
3191 {
3192 switch (mode)
3193 {
3194 case 's':
3195 the_ins.opcode[0] |= val;
3196 break;
3197 case 'd':
3198 /* This is a kludge!!! */
3199 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3200 break;
3201 case 'b':
3202 case 'w':
3203 case 'l':
3204 case 'f':
3205 case 'F':
3206 case 'x':
3207 case 'p':
3208 the_ins.opcode[0] |= val;
3209 break;
3210 /* more stuff goes here */
3211 default:
3212 as_fatal (_("failed sanity check."));
3213 }
3214 } /* install_gen_operand() */
3215
3216 /*
3217 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3218 * then deal with the bitfield hack.
3219 */
3220
3221 static char *
3222 crack_operand (str, opP)
3223 register char *str;
3224 register struct m68k_op *opP;
3225 {
3226 register int parens;
3227 register int c;
3228 register char *beg_str;
3229 int inquote = 0;
3230
3231 if (!str)
3232 {
3233 return str;
3234 }
3235 beg_str = str;
3236 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3237 {
3238 if (! inquote)
3239 {
3240 if (*str == '(')
3241 parens++;
3242 else if (*str == ')')
3243 {
3244 if (!parens)
3245 { /* ERROR */
3246 opP->error = _("Extra )");
3247 return str;
3248 }
3249 --parens;
3250 }
3251 }
3252 if (flag_mri && *str == '\'')
3253 inquote = ! inquote;
3254 }
3255 if (!*str && parens)
3256 { /* ERROR */
3257 opP->error = _("Missing )");
3258 return str;
3259 }
3260 c = *str;
3261 *str = '\0';
3262 if (m68k_ip_op (beg_str, opP) != 0)
3263 {
3264 *str = c;
3265 return str;
3266 }
3267 *str = c;
3268 if (c == '}')
3269 c = *++str; /* JF bitfield hack */
3270 if (c)
3271 {
3272 c = *++str;
3273 if (!c)
3274 as_bad (_("Missing operand"));
3275 }
3276
3277 /* Detect MRI REG symbols and convert them to REGLSTs. */
3278 if (opP->mode == CONTROL && (int)opP->reg < 0)
3279 {
3280 opP->mode = REGLST;
3281 opP->mask = ~(int)opP->reg;
3282 opP->reg = 0;
3283 }
3284
3285 return str;
3286 }
3287
3288 /* This is the guts of the machine-dependent assembler. STR points to a
3289 machine dependent instruction. This function is supposed to emit
3290 the frags/bytes it assembles to.
3291 */
3292
3293 static void
3294 insert_reg (regname, regnum)
3295 const char *regname;
3296 int regnum;
3297 {
3298 char buf[100];
3299 int i;
3300
3301 #ifdef REGISTER_PREFIX
3302 if (!flag_reg_prefix_optional)
3303 {
3304 buf[0] = REGISTER_PREFIX;
3305 strcpy (buf + 1, regname);
3306 regname = buf;
3307 }
3308 #endif
3309
3310 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3311 &zero_address_frag));
3312
3313 for (i = 0; regname[i]; i++)
3314 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3315 buf[i] = '\0';
3316
3317 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3318 &zero_address_frag));
3319 }
3320
3321 struct init_entry
3322 {
3323 const char *name;
3324 int number;
3325 };
3326
3327 static const struct init_entry init_table[] =
3328 {
3329 { "d0", DATA0 },
3330 { "d1", DATA1 },
3331 { "d2", DATA2 },
3332 { "d3", DATA3 },
3333 { "d4", DATA4 },
3334 { "d5", DATA5 },
3335 { "d6", DATA6 },
3336 { "d7", DATA7 },
3337 { "a0", ADDR0 },
3338 { "a1", ADDR1 },
3339 { "a2", ADDR2 },
3340 { "a3", ADDR3 },
3341 { "a4", ADDR4 },
3342 { "a5", ADDR5 },
3343 { "a6", ADDR6 },
3344 { "fp", ADDR6 },
3345 { "a7", ADDR7 },
3346 { "sp", ADDR7 },
3347 { "ssp", ADDR7 },
3348 { "fp0", FP0 },
3349 { "fp1", FP1 },
3350 { "fp2", FP2 },
3351 { "fp3", FP3 },
3352 { "fp4", FP4 },
3353 { "fp5", FP5 },
3354 { "fp6", FP6 },
3355 { "fp7", FP7 },
3356 { "fpi", FPI },
3357 { "fpiar", FPI },
3358 { "fpc", FPI },
3359 { "fps", FPS },
3360 { "fpsr", FPS },
3361 { "fpc", FPC },
3362 { "fpcr", FPC },
3363 { "control", FPC },
3364 { "status", FPS },
3365 { "iaddr", FPI },
3366
3367 { "cop0", COP0 },
3368 { "cop1", COP1 },
3369 { "cop2", COP2 },
3370 { "cop3", COP3 },
3371 { "cop4", COP4 },
3372 { "cop5", COP5 },
3373 { "cop6", COP6 },
3374 { "cop7", COP7 },
3375 { "pc", PC },
3376 { "zpc", ZPC },
3377 { "sr", SR },
3378
3379 { "ccr", CCR },
3380 { "cc", CCR },
3381
3382 { "acc", ACC },
3383 { "macsr", MACSR },
3384 { "mask", MASK },
3385
3386 /* control registers */
3387 { "sfc", SFC }, /* Source Function Code */
3388 { "sfcr", SFC },
3389 { "dfc", DFC }, /* Destination Function Code */
3390 { "dfcr", DFC },
3391 { "cacr", CACR }, /* Cache Control Register */
3392 { "caar", CAAR }, /* Cache Address Register */
3393
3394 { "usp", USP }, /* User Stack Pointer */
3395 { "vbr", VBR }, /* Vector Base Register */
3396 { "msp", MSP }, /* Master Stack Pointer */
3397 { "isp", ISP }, /* Interrupt Stack Pointer */
3398
3399 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3400 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3401 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3402 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3403
3404 /* 68ec040 versions of same */
3405 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3406 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3407 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3408 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3409
3410 /* mcf5200 versions of same. The ColdFire programmer's reference
3411 manual indicated that the order is 2,3,0,1, but Ken Rose
3412 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3413 { "acr0", ITT0 }, /* Access Control Unit 0 */
3414 { "acr1", ITT1 }, /* Access Control Unit 1 */
3415 { "acr2", DTT0 }, /* Access Control Unit 2 */
3416 { "acr3", DTT1 }, /* Access Control Unit 3 */
3417
3418 { "tc", TC }, /* MMU Translation Control Register */
3419 { "tcr", TC },
3420
3421 { "mmusr", MMUSR }, /* MMU Status Register */
3422 { "srp", SRP }, /* User Root Pointer */
3423 { "urp", URP }, /* Supervisor Root Pointer */
3424
3425 { "buscr", BUSCR },
3426 { "pcr", PCR },
3427
3428 { "rombar", ROMBAR }, /* ROM Base Address Register */
3429 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3430 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3431 { "mbar", MBAR }, /* Module Base Address Register */
3432 /* end of control registers */
3433
3434 { "ac", AC },
3435 { "bc", BC },
3436 { "cal", CAL },
3437 { "crp", CRP },
3438 { "drp", DRP },
3439 { "pcsr", PCSR },
3440 { "psr", PSR },
3441 { "scc", SCC },
3442 { "val", VAL },
3443 { "bad0", BAD0 },
3444 { "bad1", BAD1 },
3445 { "bad2", BAD2 },
3446 { "bad3", BAD3 },
3447 { "bad4", BAD4 },
3448 { "bad5", BAD5 },
3449 { "bad6", BAD6 },
3450 { "bad7", BAD7 },
3451 { "bac0", BAC0 },
3452 { "bac1", BAC1 },
3453 { "bac2", BAC2 },
3454 { "bac3", BAC3 },
3455 { "bac4", BAC4 },
3456 { "bac5", BAC5 },
3457 { "bac6", BAC6 },
3458 { "bac7", BAC7 },
3459
3460 { "ic", IC },
3461 { "dc", DC },
3462 { "nc", NC },
3463
3464 { "tt0", TT0 },
3465 { "tt1", TT1 },
3466 /* 68ec030 versions of same */
3467 { "ac0", TT0 },
3468 { "ac1", TT1 },
3469 /* 68ec030 access control unit, identical to 030 MMU status reg */
3470 { "acusr", PSR },
3471
3472 /* Suppressed data and address registers. */
3473 { "zd0", ZDATA0 },
3474 { "zd1", ZDATA1 },
3475 { "zd2", ZDATA2 },
3476 { "zd3", ZDATA3 },
3477 { "zd4", ZDATA4 },
3478 { "zd5", ZDATA5 },
3479 { "zd6", ZDATA6 },
3480 { "zd7", ZDATA7 },
3481 { "za0", ZADDR0 },
3482 { "za1", ZADDR1 },
3483 { "za2", ZADDR2 },
3484 { "za3", ZADDR3 },
3485 { "za4", ZADDR4 },
3486 { "za5", ZADDR5 },
3487 { "za6", ZADDR6 },
3488 { "za7", ZADDR7 },
3489
3490 /* Upper and lower data and address registers, used by macw and msacw. */
3491 { "d0l", DATA0L },
3492 { "d1l", DATA1L },
3493 { "d2l", DATA2L },
3494 { "d3l", DATA3L },
3495 { "d4l", DATA4L },
3496 { "d5l", DATA5L },
3497 { "d6l", DATA6L },
3498 { "d7l", DATA7L },
3499
3500 { "a0l", ADDR0L },
3501 { "a1l", ADDR1L },
3502 { "a2l", ADDR2L },
3503 { "a3l", ADDR3L },
3504 { "a4l", ADDR4L },
3505 { "a5l", ADDR5L },
3506 { "a6l", ADDR6L },
3507 { "a7l", ADDR7L },
3508
3509 { "d0u", DATA0U },
3510 { "d1u", DATA1U },
3511 { "d2u", DATA2U },
3512 { "d3u", DATA3U },
3513 { "d4u", DATA4U },
3514 { "d5u", DATA5U },
3515 { "d6u", DATA6U },
3516 { "d7u", DATA7U },
3517
3518 { "a0u", ADDR0U },
3519 { "a1u", ADDR1U },
3520 { "a2u", ADDR2U },
3521 { "a3u", ADDR3U },
3522 { "a4u", ADDR4U },
3523 { "a5u", ADDR5U },
3524 { "a6u", ADDR6U },
3525 { "a7u", ADDR7U },
3526
3527 { 0, 0 }
3528 };
3529
3530 static void
3531 init_regtable ()
3532 {
3533 int i;
3534 for (i = 0; init_table[i].name; i++)
3535 insert_reg (init_table[i].name, init_table[i].number);
3536 }
3537
3538 static int no_68851, no_68881;
3539
3540 #ifdef OBJ_AOUT
3541 /* a.out machine type. Default to 68020. */
3542 int m68k_aout_machtype = 2;
3543 #endif
3544
3545 void
3546 md_assemble (str)
3547 char *str;
3548 {
3549 const char *er;
3550 short *fromP;
3551 char *toP = NULL;
3552 int m, n = 0;
3553 char *to_beg_P;
3554 int shorts_this_frag;
3555 fixS *fixP;
3556
3557 /* In MRI mode, the instruction and operands are separated by a
3558 space. Anything following the operands is a comment. The label
3559 has already been removed. */
3560 if (flag_mri)
3561 {
3562 char *s;
3563 int fields = 0;
3564 int infield = 0;
3565 int inquote = 0;
3566
3567 for (s = str; *s != '\0'; s++)
3568 {
3569 if ((*s == ' ' || *s == '\t') && ! inquote)
3570 {
3571 if (infield)
3572 {
3573 ++fields;
3574 if (fields >= 2)
3575 {
3576 *s = '\0';
3577 break;
3578 }
3579 infield = 0;
3580 }
3581 }
3582 else
3583 {
3584 if (! infield)
3585 infield = 1;
3586 if (*s == '\'')
3587 inquote = ! inquote;
3588 }
3589 }
3590 }
3591
3592 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3593 m68k_ip (str);
3594 er = the_ins.error;
3595 if (!er)
3596 {
3597 for (n = 0; n < the_ins.numargs; n++)
3598 if (the_ins.operands[n].error)
3599 {
3600 er = the_ins.operands[n].error;
3601 break;
3602 }
3603 }
3604 if (er)
3605 {
3606 as_bad (_("%s -- statement `%s' ignored"), er, str);
3607 return;
3608 }
3609
3610 /* If there is a current label, record that it marks an instruction. */
3611 if (current_label != NULL)
3612 {
3613 current_label->text = 1;
3614 current_label = NULL;
3615 }
3616
3617 #ifdef OBJ_ELF
3618 /* Tie dwarf2 debug info to the address at the start of the insn. */
3619 dwarf2_emit_insn (0);
3620 #endif
3621
3622 if (the_ins.nfrag == 0)
3623 {
3624 /* No frag hacking involved; just put it out */
3625 toP = frag_more (2 * the_ins.numo);
3626 fromP = &the_ins.opcode[0];
3627 for (m = the_ins.numo; m; --m)
3628 {
3629 md_number_to_chars (toP, (long) (*fromP), 2);
3630 toP += 2;
3631 fromP++;
3632 }
3633 /* put out symbol-dependent info */
3634 for (m = 0; m < the_ins.nrel; m++)
3635 {
3636 switch (the_ins.reloc[m].wid)
3637 {
3638 case 'B':
3639 n = 1;
3640 break;
3641 case 'b':
3642 n = 1;
3643 break;
3644 case '3':
3645 n = 1;
3646 break;
3647 case 'w':
3648 case 'W':
3649 n = 2;
3650 break;
3651 case 'l':
3652 n = 4;
3653 break;
3654 default:
3655 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3656 the_ins.reloc[m].wid);
3657 }
3658
3659 fixP = fix_new_exp (frag_now,
3660 ((toP - frag_now->fr_literal)
3661 - the_ins.numo * 2 + the_ins.reloc[m].n),
3662 n,
3663 &the_ins.reloc[m].exp,
3664 the_ins.reloc[m].pcrel,
3665 get_reloc_code (n, the_ins.reloc[m].pcrel,
3666 the_ins.reloc[m].pic_reloc));
3667 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3668 if (the_ins.reloc[m].wid == 'B')
3669 fixP->fx_signed = 1;
3670 }
3671 return;
3672 }
3673
3674 /* There's some frag hacking */
3675 {
3676 /* Calculate the max frag size. */
3677 int wid;
3678
3679 wid = 2 * the_ins.fragb[0].fragoff;
3680 for (n = 1; n < the_ins.nfrag; n++)
3681 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3682 /* frag_var part. */
3683 wid += 10;
3684 /* Make sure the whole insn fits in one chunk, in particular that
3685 the var part is attached, as we access one byte before the
3686 variable frag for byte branches. */
3687 frag_grow (wid);
3688 }
3689
3690 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3691 {
3692 int wid;
3693
3694 if (n == 0)
3695 wid = 2 * the_ins.fragb[n].fragoff;
3696 else
3697 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3698 toP = frag_more (wid);
3699 to_beg_P = toP;
3700 shorts_this_frag = 0;
3701 for (m = wid / 2; m; --m)
3702 {
3703 md_number_to_chars (toP, (long) (*fromP), 2);
3704 toP += 2;
3705 fromP++;
3706 shorts_this_frag++;
3707 }
3708 for (m = 0; m < the_ins.nrel; m++)
3709 {
3710 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3711 {
3712 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3713 break;
3714 }
3715 wid = the_ins.reloc[m].wid;
3716 if (wid == 0)
3717 continue;
3718 the_ins.reloc[m].wid = 0;
3719 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3720
3721 fixP = fix_new_exp (frag_now,
3722 ((toP - frag_now->fr_literal)
3723 - the_ins.numo * 2 + the_ins.reloc[m].n),
3724 wid,
3725 &the_ins.reloc[m].exp,
3726 the_ins.reloc[m].pcrel,
3727 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3728 the_ins.reloc[m].pic_reloc));
3729 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3730 }
3731 (void) frag_var (rs_machine_dependent, 10, 0,
3732 (relax_substateT) (the_ins.fragb[n].fragty),
3733 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3734 }
3735 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3736 shorts_this_frag = 0;
3737 if (n)
3738 {
3739 toP = frag_more (n * sizeof (short));
3740 while (n--)
3741 {
3742 md_number_to_chars (toP, (long) (*fromP), 2);
3743 toP += 2;
3744 fromP++;
3745 shorts_this_frag++;
3746 }
3747 }
3748 for (m = 0; m < the_ins.nrel; m++)
3749 {
3750 int wid;
3751
3752 wid = the_ins.reloc[m].wid;
3753 if (wid == 0)
3754 continue;
3755 the_ins.reloc[m].wid = 0;
3756 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3757
3758 fixP = fix_new_exp (frag_now,
3759 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3760 - shorts_this_frag * 2),
3761 wid,
3762 &the_ins.reloc[m].exp,
3763 the_ins.reloc[m].pcrel,
3764 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3765 the_ins.reloc[m].pic_reloc));
3766 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3767 }
3768 }
3769
3770 void
3771 md_begin ()
3772 {
3773 /*
3774 * md_begin -- set up hash tables with 68000 instructions.
3775 * similar to what the vax assembler does. ---phr
3776 */
3777 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3778 a copy of it at runtime, adding in the information we want but isn't
3779 there. I think it'd be better to have an awk script hack the table
3780 at compile time. Or even just xstr the table and use it as-is. But
3781 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3782 names. */
3783
3784 register const struct m68k_opcode *ins;
3785 register struct m68k_incant *hack, *slak;
3786 register const char *retval = 0; /* empty string, or error msg text */
3787 register int i;
3788 register char c;
3789
3790 if (flag_mri)
3791 {
3792 flag_reg_prefix_optional = 1;
3793 m68k_abspcadd = 1;
3794 if (! m68k_rel32_from_cmdline)
3795 m68k_rel32 = 0;
3796 }
3797
3798 op_hash = hash_new ();
3799
3800 obstack_begin (&robyn, 4000);
3801 for (i = 0; i < m68k_numopcodes; i++)
3802 {
3803 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3804 do
3805 {
3806 ins = &m68k_opcodes[i];
3807 /* We *could* ignore insns that don't match our arch here
3808 but just leaving them out of the hash. */
3809 slak->m_operands = ins->args;
3810 slak->m_opnum = strlen (slak->m_operands) / 2;
3811 slak->m_arch = ins->arch;
3812 slak->m_opcode = ins->opcode;
3813 /* This is kludgey */
3814 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3815 if (i + 1 != m68k_numopcodes
3816 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3817 {
3818 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3819 i++;
3820 }
3821 else
3822 slak->m_next = 0;
3823 slak = slak->m_next;
3824 }
3825 while (slak);
3826
3827 retval = hash_insert (op_hash, ins->name, (char *) hack);
3828 if (retval)
3829 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3830 }
3831
3832 for (i = 0; i < m68k_numaliases; i++)
3833 {
3834 const char *name = m68k_opcode_aliases[i].primary;
3835 const char *alias = m68k_opcode_aliases[i].alias;
3836 PTR val = hash_find (op_hash, name);
3837 if (!val)
3838 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3839 retval = hash_insert (op_hash, alias, val);
3840 if (retval)
3841 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3842 }
3843
3844 /* In MRI mode, all unsized branches are variable sized. Normally,
3845 they are word sized. */
3846 if (flag_mri)
3847 {
3848 static struct m68k_opcode_alias mri_aliases[] =
3849 {
3850 { "bhi", "jhi", },
3851 { "bls", "jls", },
3852 { "bcc", "jcc", },
3853 { "bcs", "jcs", },
3854 { "bne", "jne", },
3855 { "beq", "jeq", },
3856 { "bvc", "jvc", },
3857 { "bvs", "jvs", },
3858 { "bpl", "jpl", },
3859 { "bmi", "jmi", },
3860 { "bge", "jge", },
3861 { "blt", "jlt", },
3862 { "bgt", "jgt", },
3863 { "ble", "jle", },
3864 { "bra", "jra", },
3865 { "bsr", "jbsr", },
3866 };
3867
3868 for (i = 0;
3869 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3870 i++)
3871 {
3872 const char *name = mri_aliases[i].primary;
3873 const char *alias = mri_aliases[i].alias;
3874 PTR val = hash_find (op_hash, name);
3875 if (!val)
3876 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3877 retval = hash_jam (op_hash, alias, val);
3878 if (retval)
3879 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3880 }
3881 }
3882
3883 for (i = 0; i < (int) sizeof (mklower_table); i++)
3884 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3885
3886 for (i = 0; i < (int) sizeof (notend_table); i++)
3887 {
3888 notend_table[i] = 0;
3889 alt_notend_table[i] = 0;
3890 }
3891 notend_table[','] = 1;
3892 notend_table['{'] = 1;
3893 notend_table['}'] = 1;
3894 alt_notend_table['a'] = 1;
3895 alt_notend_table['A'] = 1;
3896 alt_notend_table['d'] = 1;
3897 alt_notend_table['D'] = 1;
3898 alt_notend_table['#'] = 1;
3899 alt_notend_table['&'] = 1;
3900 alt_notend_table['f'] = 1;
3901 alt_notend_table['F'] = 1;
3902 #ifdef REGISTER_PREFIX
3903 alt_notend_table[REGISTER_PREFIX] = 1;
3904 #endif
3905
3906 /* We need to put '(' in alt_notend_table to handle
3907 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3908 */
3909 alt_notend_table['('] = 1;
3910
3911 /* We need to put '@' in alt_notend_table to handle
3912 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3913 */
3914 alt_notend_table['@'] = 1;
3915
3916 /* We need to put digits in alt_notend_table to handle
3917 bfextu %d0{24:1},%d0
3918 */
3919 alt_notend_table['0'] = 1;
3920 alt_notend_table['1'] = 1;
3921 alt_notend_table['2'] = 1;
3922 alt_notend_table['3'] = 1;
3923 alt_notend_table['4'] = 1;
3924 alt_notend_table['5'] = 1;
3925 alt_notend_table['6'] = 1;
3926 alt_notend_table['7'] = 1;
3927 alt_notend_table['8'] = 1;
3928 alt_notend_table['9'] = 1;
3929
3930 #ifndef MIT_SYNTAX_ONLY
3931 /* Insert pseudo ops, these have to go into the opcode table since
3932 gas expects pseudo ops to start with a dot */
3933 {
3934 int n = 0;
3935 while (mote_pseudo_table[n].poc_name)
3936 {
3937 hack = (struct m68k_incant *)
3938 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3939 hash_insert (op_hash,
3940 mote_pseudo_table[n].poc_name, (char *) hack);
3941 hack->m_operands = 0;
3942 hack->m_opnum = n;
3943 n++;
3944 }
3945 }
3946 #endif
3947
3948 init_regtable ();
3949
3950 #ifdef OBJ_ELF
3951 record_alignment (text_section, 2);
3952 record_alignment (data_section, 2);
3953 record_alignment (bss_section, 2);
3954 #endif
3955 }
3956
3957 static void
3958 select_control_regs ()
3959 {
3960 /* Note which set of "movec" control registers is available. */
3961 switch (cpu_of_arch (current_architecture))
3962 {
3963 case m68000:
3964 control_regs = m68000_control_regs;
3965 break;
3966 case m68010:
3967 control_regs = m68010_control_regs;
3968 break;
3969 case m68020:
3970 case m68030:
3971 control_regs = m68020_control_regs;
3972 break;
3973 case m68040:
3974 control_regs = m68040_control_regs;
3975 break;
3976 case m68060:
3977 control_regs = m68060_control_regs;
3978 break;
3979 case cpu32:
3980 control_regs = cpu32_control_regs;
3981 break;
3982 case mcf5200:
3983 case mcf5206e:
3984 case mcf5307:
3985 case mcf5407:
3986 control_regs = mcf_control_regs;
3987 break;
3988 default:
3989 abort ();
3990 }
3991 }
3992
3993 void
3994 m68k_init_after_args ()
3995 {
3996 if (cpu_of_arch (current_architecture) == 0)
3997 {
3998 int i;
3999 const char *default_cpu = TARGET_CPU;
4000
4001 if (*default_cpu == 'm')
4002 default_cpu++;
4003 for (i = 0; i < n_archs; i++)
4004 if (strcasecmp (default_cpu, archs[i].name) == 0)
4005 break;
4006 if (i == n_archs)
4007 {
4008 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4009 current_architecture |= m68020;
4010 }
4011 else
4012 current_architecture |= archs[i].arch;
4013 }
4014 /* Permit m68881 specification with all cpus; those that can't work
4015 with a coprocessor could be doing emulation. */
4016 if (current_architecture & m68851)
4017 {
4018 if (current_architecture & m68040)
4019 {
4020 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4021 }
4022 }
4023 /* What other incompatibilities could we check for? */
4024
4025 /* Toss in some default assumptions about coprocessors. */
4026 if (!no_68881
4027 && (cpu_of_arch (current_architecture)
4028 /* Can CPU32 have a 68881 coprocessor?? */
4029 & (m68020 | m68030 | cpu32)))
4030 {
4031 current_architecture |= m68881;
4032 }
4033 if (!no_68851
4034 && (cpu_of_arch (current_architecture) & m68020up) != 0
4035 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4036 {
4037 current_architecture |= m68851;
4038 }
4039 if (no_68881 && (current_architecture & m68881))
4040 as_bad (_("options for 68881 and no-68881 both given"));
4041 if (no_68851 && (current_architecture & m68851))
4042 as_bad (_("options for 68851 and no-68851 both given"));
4043
4044 #ifdef OBJ_AOUT
4045 /* Work out the magic number. This isn't very general. */
4046 if (current_architecture & m68000)
4047 m68k_aout_machtype = 0;
4048 else if (current_architecture & m68010)
4049 m68k_aout_machtype = 1;
4050 else if (current_architecture & m68020)
4051 m68k_aout_machtype = 2;
4052 else
4053 m68k_aout_machtype = 2;
4054 #endif
4055
4056 /* Note which set of "movec" control registers is available. */
4057 select_control_regs ();
4058
4059 if (cpu_of_arch (current_architecture) < m68020
4060 || arch_coldfire_p (current_architecture))
4061 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4062 }
4063 \f
4064 /* This is called when a label is defined. */
4065
4066 void
4067 m68k_frob_label (sym)
4068 symbolS *sym;
4069 {
4070 struct label_line *n;
4071
4072 n = (struct label_line *) xmalloc (sizeof *n);
4073 n->next = labels;
4074 n->label = sym;
4075 as_where (&n->file, &n->line);
4076 n->text = 0;
4077 labels = n;
4078 current_label = n;
4079 }
4080
4081 /* This is called when a value that is not an instruction is emitted. */
4082
4083 void
4084 m68k_flush_pending_output ()
4085 {
4086 current_label = NULL;
4087 }
4088
4089 /* This is called at the end of the assembly, when the final value of
4090 the label is known. We warn if this is a text symbol aligned at an
4091 odd location. */
4092
4093 void
4094 m68k_frob_symbol (sym)
4095 symbolS *sym;
4096 {
4097 if (S_GET_SEGMENT (sym) == reg_section
4098 && (int) S_GET_VALUE (sym) < 0)
4099 {
4100 S_SET_SEGMENT (sym, absolute_section);
4101 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4102 }
4103 else if ((S_GET_VALUE (sym) & 1) != 0)
4104 {
4105 struct label_line *l;
4106
4107 for (l = labels; l != NULL; l = l->next)
4108 {
4109 if (l->label == sym)
4110 {
4111 if (l->text)
4112 as_warn_where (l->file, l->line,
4113 _("text label `%s' aligned to odd boundary"),
4114 S_GET_NAME (sym));
4115 break;
4116 }
4117 }
4118 }
4119 }
4120 \f
4121 /* This is called if we go in or out of MRI mode because of the .mri
4122 pseudo-op. */
4123
4124 void
4125 m68k_mri_mode_change (on)
4126 int on;
4127 {
4128 if (on)
4129 {
4130 if (! flag_reg_prefix_optional)
4131 {
4132 flag_reg_prefix_optional = 1;
4133 #ifdef REGISTER_PREFIX
4134 init_regtable ();
4135 #endif
4136 }
4137 m68k_abspcadd = 1;
4138 if (! m68k_rel32_from_cmdline)
4139 m68k_rel32 = 0;
4140 }
4141 else
4142 {
4143 if (! reg_prefix_optional_seen)
4144 {
4145 #ifdef REGISTER_PREFIX_OPTIONAL
4146 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4147 #else
4148 flag_reg_prefix_optional = 0;
4149 #endif
4150 #ifdef REGISTER_PREFIX
4151 init_regtable ();
4152 #endif
4153 }
4154 m68k_abspcadd = 0;
4155 if (! m68k_rel32_from_cmdline)
4156 m68k_rel32 = 1;
4157 }
4158 }
4159
4160 /* Equal to MAX_PRECISION in atof-ieee.c */
4161 #define MAX_LITTLENUMS 6
4162
4163 /* Turn a string in input_line_pointer into a floating point constant
4164 of type TYPE, and store the appropriate bytes in *LITP. The number
4165 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4166 returned, or NULL on OK. */
4167
4168 char *
4169 md_atof (type, litP, sizeP)
4170 char type;
4171 char *litP;
4172 int *sizeP;
4173 {
4174 int prec;
4175 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4176 LITTLENUM_TYPE *wordP;
4177 char *t;
4178
4179 switch (type)
4180 {
4181 case 'f':
4182 case 'F':
4183 case 's':
4184 case 'S':
4185 prec = 2;
4186 break;
4187
4188 case 'd':
4189 case 'D':
4190 case 'r':
4191 case 'R':
4192 prec = 4;
4193 break;
4194
4195 case 'x':
4196 case 'X':
4197 prec = 6;
4198 break;
4199
4200 case 'p':
4201 case 'P':
4202 prec = 6;
4203 break;
4204
4205 default:
4206 *sizeP = 0;
4207 return _("Bad call to MD_ATOF()");
4208 }
4209 t = atof_ieee (input_line_pointer, type, words);
4210 if (t)
4211 input_line_pointer = t;
4212
4213 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4214 for (wordP = words; prec--;)
4215 {
4216 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4217 litP += sizeof (LITTLENUM_TYPE);
4218 }
4219 return 0;
4220 }
4221
4222 void
4223 md_number_to_chars (buf, val, n)
4224 char *buf;
4225 valueT val;
4226 int n;
4227 {
4228 number_to_chars_bigendian (buf, val, n);
4229 }
4230
4231 static void
4232 md_apply_fix_2 (fixP, val)
4233 fixS *fixP;
4234 offsetT val;
4235 {
4236 addressT upper_limit;
4237 offsetT lower_limit;
4238
4239 /* This is unnecessary but it convinces the native rs6000 compiler
4240 to generate the code we want. */
4241 char *buf = fixP->fx_frag->fr_literal;
4242 buf += fixP->fx_where;
4243 /* end ibm compiler workaround */
4244
4245 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4246
4247 #ifdef OBJ_ELF
4248 if (fixP->fx_addsy)
4249 {
4250 memset (buf, 0, fixP->fx_size);
4251 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4252
4253 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4254 && !S_IS_DEFINED (fixP->fx_addsy)
4255 && !S_IS_WEAK (fixP->fx_addsy))
4256 S_SET_WEAK (fixP->fx_addsy);
4257 return;
4258 }
4259 #endif
4260
4261 #ifdef BFD_ASSEMBLER
4262 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4263 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4264 return;
4265 #endif
4266
4267 switch (fixP->fx_size)
4268 {
4269 /* The cast to offsetT below are necessary to make code correct for
4270 machines where ints are smaller than offsetT */
4271 case 1:
4272 *buf++ = val;
4273 upper_limit = 0x7f;
4274 lower_limit = - (offsetT) 0x80;
4275 break;
4276 case 2:
4277 *buf++ = (val >> 8);
4278 *buf++ = val;
4279 upper_limit = 0x7fff;
4280 lower_limit = - (offsetT) 0x8000;
4281 break;
4282 case 4:
4283 *buf++ = (val >> 24);
4284 *buf++ = (val >> 16);
4285 *buf++ = (val >> 8);
4286 *buf++ = val;
4287 upper_limit = 0x7fffffff;
4288 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4289 break;
4290 default:
4291 BAD_CASE (fixP->fx_size);
4292 }
4293
4294 /* Fix up a negative reloc. */
4295 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4296 {
4297 fixP->fx_addsy = fixP->fx_subsy;
4298 fixP->fx_subsy = NULL;
4299 fixP->fx_tcbit = 1;
4300 }
4301
4302 /* For non-pc-relative values, it's conceivable we might get something
4303 like "0xff" for a byte field. So extend the upper part of the range
4304 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4305 so that we can do any range checking at all. */
4306 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4307 upper_limit = upper_limit * 2 + 1;
4308
4309 if ((addressT) val > upper_limit
4310 && (val > 0 || val < lower_limit))
4311 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4312
4313 /* A one byte PC-relative reloc means a short branch. We can't use
4314 a short branch with a value of 0 or -1, because those indicate
4315 different opcodes (branches with longer offsets). fixup_segment
4316 in write.c may have clobbered fx_pcrel, so we need to examine the
4317 reloc type. */
4318 if ((fixP->fx_pcrel
4319 #ifdef BFD_ASSEMBLER
4320 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4321 #endif
4322 )
4323 && fixP->fx_size == 1
4324 && (fixP->fx_addsy == NULL
4325 || S_IS_DEFINED (fixP->fx_addsy))
4326 && (val == 0 || val == -1))
4327 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4328 }
4329
4330 #ifdef BFD_ASSEMBLER
4331 int
4332 md_apply_fix (fixP, valp)
4333 fixS *fixP;
4334 valueT *valp;
4335 {
4336 md_apply_fix_2 (fixP, (addressT) *valp);
4337 return 1;
4338 }
4339 #else
4340 void md_apply_fix (fixP, val)
4341 fixS *fixP;
4342 long val;
4343 {
4344 md_apply_fix_2 (fixP, (addressT) val);
4345 }
4346 #endif
4347
4348 /* *fragP has been relaxed to its final size, and now needs to have
4349 the bytes inside it modified to conform to the new size There is UGLY
4350 MAGIC here. ..
4351 */
4352 static void
4353 md_convert_frag_1 (fragP)
4354 register fragS *fragP;
4355 {
4356 long disp;
4357 fixS *fixP;
4358
4359 /* Address in object code of the displacement. */
4360 register int object_address = fragP->fr_fix + fragP->fr_address;
4361
4362 /* Address in gas core of the place to store the displacement. */
4363 /* This convinces the native rs6000 compiler to generate the code we
4364 want. */
4365 register char *buffer_address = fragP->fr_literal;
4366 buffer_address += fragP->fr_fix;
4367 /* end ibm compiler workaround */
4368
4369 /* The displacement of the address, from current location. */
4370 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4371 disp = (disp + fragP->fr_offset) - object_address;
4372
4373 switch (fragP->fr_subtype)
4374 {
4375 case TAB (BRANCHBWL, BYTE):
4376 case TAB (BRABSJUNC, BYTE):
4377 case TAB (BRABSJCOND, BYTE):
4378 case TAB (BRANCHBW, BYTE):
4379 know (issbyte (disp));
4380 if (disp == 0)
4381 as_bad_where (fragP->fr_file, fragP->fr_line,
4382 _("short branch with zero offset: use :w"));
4383 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4384 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4385 fixP->fx_pcrel_adjust = -1;
4386 break;
4387 case TAB (BRANCHBWL, SHORT):
4388 case TAB (BRABSJUNC, SHORT):
4389 case TAB (BRABSJCOND, SHORT):
4390 case TAB (BRANCHBW, SHORT):
4391 fragP->fr_opcode[1] = 0x00;
4392 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4393 1, RELAX_RELOC_PC16);
4394 fragP->fr_fix += 2;
4395 break;
4396 case TAB (BRANCHBWL, LONG):
4397 fragP->fr_opcode[1] = (char) 0xFF;
4398 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4399 1, RELAX_RELOC_PC32);
4400 fragP->fr_fix += 4;
4401 break;
4402 case TAB (BRABSJUNC, LONG):
4403 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4404 {
4405 fragP->fr_opcode[0] = 0x4E;
4406 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4407 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4408 0, RELAX_RELOC_ABS32);
4409 fragP->fr_fix += 4;
4410 }
4411 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4412 {
4413 fragP->fr_opcode[0] = 0x4E;
4414 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4415 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4416 0, RELAX_RELOC_ABS32);
4417 fragP->fr_fix += 4;
4418 }
4419 else
4420 {
4421 /* This cannot happen, because jbsr and jbra are the only two
4422 unconditional branches. */
4423 abort ();
4424 }
4425 break;
4426 case TAB (BRABSJCOND, LONG):
4427 /* Only Bcc 68000 instructions can come here. */
4428 /* Change bcc into b!cc/jmp absl long. */
4429
4430 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4431 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4432
4433 /* JF: these used to be fr_opcode[2,3], but they may be in a
4434 different frag, in which case refering to them is a no-no.
4435 Only fr_opcode[0,1] are guaranteed to work. */
4436 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4437 *buffer_address++ = (char) 0xf9;
4438 fragP->fr_fix += 2; /* account for jmp instruction */
4439 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4440 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4441 fragP->fr_fix += 4;
4442 break;
4443 case TAB (FBRANCH, SHORT):
4444 know ((fragP->fr_opcode[1] & 0x40) == 0);
4445 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4446 1, RELAX_RELOC_PC16);
4447 fragP->fr_fix += 2;
4448 break;
4449 case TAB (FBRANCH, LONG):
4450 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4451 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4452 1, RELAX_RELOC_PC32);
4453 fragP->fr_fix += 4;
4454 break;
4455 case TAB (DBCCLBR, SHORT):
4456 case TAB (DBCCABSJ, SHORT):
4457 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4458 1, RELAX_RELOC_PC16);
4459 fragP->fr_fix += 2;
4460 break;
4461 case TAB (DBCCLBR, LONG):
4462 /* only DBcc instructions can come here */
4463 /* Change dbcc into dbcc/bral. */
4464
4465 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4466 *buffer_address++ = 0x00; /* branch offset = 4 */
4467 *buffer_address++ = 0x04;
4468 *buffer_address++ = 0x60; /* put in bra pc+6 */
4469 *buffer_address++ = 0x06;
4470 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4471 *buffer_address++ = (char) 0xff;
4472
4473 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4474 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4475 RELAX_RELOC_PC32);
4476 fragP->fr_fix += 4;
4477 break;
4478 case TAB (DBCCABSJ, LONG):
4479 /* only DBcc instructions can come here */
4480 /* Change dbcc into dbcc/jmp. */
4481
4482 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4483 *buffer_address++ = 0x00; /* branch offset = 4 */
4484 *buffer_address++ = 0x04;
4485 *buffer_address++ = 0x60; /* put in bra pc+6 */
4486 *buffer_address++ = 0x06;
4487 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4488 *buffer_address++ = (char) 0xf9;
4489
4490 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4491 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4492 RELAX_RELOC_ABS32);
4493 fragP->fr_fix += 4;
4494 break;
4495 case TAB (PCREL1632, SHORT):
4496 fragP->fr_opcode[1] &= ~0x3F;
4497 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4498 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4499 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4500 fragP->fr_fix += 2;
4501 break;
4502 case TAB (PCREL1632, LONG):
4503 /* Already set to mode 7.3; this indicates: PC indirect with
4504 suppressed index, 32-bit displacement. */
4505 *buffer_address++ = 0x01;
4506 *buffer_address++ = 0x70;
4507 fragP->fr_fix += 2;
4508 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4509 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4510 fixP->fx_pcrel_adjust = 2;
4511 fragP->fr_fix += 4;
4512 break;
4513 case TAB (PCINDEX, BYTE):
4514 assert (fragP->fr_fix >= 2);
4515 buffer_address[-2] &= ~1;
4516 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4517 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4518 fixP->fx_pcrel_adjust = 1;
4519 break;
4520 case TAB (PCINDEX, SHORT):
4521 assert (fragP->fr_fix >= 2);
4522 buffer_address[-2] |= 0x1;
4523 buffer_address[-1] = 0x20;
4524 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4525 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4526 fixP->fx_pcrel_adjust = 2;
4527 fragP->fr_fix += 2;
4528 break;
4529 case TAB (PCINDEX, LONG):
4530 assert (fragP->fr_fix >= 2);
4531 buffer_address[-2] |= 0x1;
4532 buffer_address[-1] = 0x30;
4533 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4534 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4535 fixP->fx_pcrel_adjust = 2;
4536 fragP->fr_fix += 4;
4537 break;
4538 case TAB (ABSTOPCREL, SHORT):
4539 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4540 1, RELAX_RELOC_PC16);
4541 fragP->fr_fix += 2;
4542 break;
4543 case TAB (ABSTOPCREL, LONG):
4544 /* The thing to do here is force it to ABSOLUTE LONG, since
4545 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4546 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4547 abort ();
4548 fragP->fr_opcode[1] &= ~0x3F;
4549 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4550 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4551 0, RELAX_RELOC_ABS32);
4552 fragP->fr_fix += 4;
4553 break;
4554 }
4555 }
4556
4557 #ifndef BFD_ASSEMBLER
4558
4559 void
4560 md_convert_frag (headers, sec, fragP)
4561 object_headers *headers ATTRIBUTE_UNUSED;
4562 segT sec ATTRIBUTE_UNUSED;
4563 fragS *fragP;
4564 {
4565 md_convert_frag_1 (fragP);
4566 }
4567
4568 #else
4569
4570 void
4571 md_convert_frag (abfd, sec, fragP)
4572 bfd *abfd ATTRIBUTE_UNUSED;
4573 segT sec ATTRIBUTE_UNUSED;
4574 fragS *fragP;
4575 {
4576 md_convert_frag_1 (fragP);
4577 }
4578 #endif
4579
4580 /* Force truly undefined symbols to their maximum size, and generally set up
4581 the frag list to be relaxed
4582 */
4583 int
4584 md_estimate_size_before_relax (fragP, segment)
4585 register fragS *fragP;
4586 segT segment;
4587 {
4588 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4589 switch (fragP->fr_subtype)
4590 {
4591 case TAB (BRANCHBWL, SZ_UNDEF):
4592 case TAB (BRABSJUNC, SZ_UNDEF):
4593 case TAB (BRABSJCOND, SZ_UNDEF):
4594 {
4595 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4596 && relaxable_symbol (fragP->fr_symbol))
4597 {
4598 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4599 }
4600 else if (flag_short_refs)
4601 {
4602 /* Symbol is undefined and we want short ref. */
4603 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4604 }
4605 else
4606 {
4607 /* Symbol is still undefined. Make it LONG. */
4608 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4609 }
4610 break;
4611 }
4612
4613 case TAB (BRANCHBW, SZ_UNDEF):
4614 {
4615 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4616 && relaxable_symbol (fragP->fr_symbol))
4617 {
4618 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4619 }
4620 else
4621 {
4622 /* Symbol is undefined and we don't have long branches. */
4623 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4624 }
4625 break;
4626 }
4627
4628 case TAB (FBRANCH, SZ_UNDEF):
4629 case TAB (DBCCLBR, SZ_UNDEF):
4630 case TAB (DBCCABSJ, SZ_UNDEF):
4631 case TAB (PCREL1632, SZ_UNDEF):
4632 {
4633 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4634 && relaxable_symbol (fragP->fr_symbol))
4635 || flag_short_refs)
4636 {
4637 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4638 }
4639 else
4640 {
4641 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4642 }
4643 break;
4644 }
4645
4646 case TAB (PCINDEX, SZ_UNDEF):
4647 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4648 && relaxable_symbol (fragP->fr_symbol)))
4649 {
4650 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4651 }
4652 else
4653 {
4654 fragP->fr_subtype = TAB (PCINDEX, LONG);
4655 }
4656 break;
4657
4658 case TAB (ABSTOPCREL, SZ_UNDEF):
4659 {
4660 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4661 && relaxable_symbol (fragP->fr_symbol)))
4662 {
4663 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4664 }
4665 else
4666 {
4667 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4668 }
4669 break;
4670 }
4671
4672 default:
4673 break;
4674 }
4675
4676 /* Now that SZ_UNDEF are taken care of, check others. */
4677 switch (fragP->fr_subtype)
4678 {
4679 case TAB (BRANCHBWL, BYTE):
4680 case TAB (BRABSJUNC, BYTE):
4681 case TAB (BRABSJCOND, BYTE):
4682 case TAB (BRANCHBW, BYTE):
4683 /* We can't do a short jump to the next instruction, so in that
4684 case we force word mode. If the symbol is at the start of a
4685 frag, and it is the next frag with any data in it (usually
4686 this is just the next frag, but assembler listings may
4687 introduce empty frags), we must use word mode. */
4688 if (fragP->fr_symbol)
4689 {
4690 fragS *sym_frag;
4691
4692 sym_frag = symbol_get_frag (fragP->fr_symbol);
4693 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4694 {
4695 fragS *l;
4696
4697 for (l = fragP->fr_next; l != sym_frag; l = l->fr_next)
4698 if (l->fr_fix != 0)
4699 break;
4700 if (l == sym_frag)
4701 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4702 }
4703 }
4704 break;
4705 default:
4706 break;
4707 }
4708 return md_relax_table[fragP->fr_subtype].rlx_length;
4709 }
4710
4711 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4712 /* the bit-field entries in the relocation_info struct plays hell
4713 with the byte-order problems of cross-assembly. So as a hack,
4714 I added this mach. dependent ri twiddler. Ugly, but it gets
4715 you there. -KWK */
4716 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4717 are symbolnum, most sig. byte first. Last byte is broken up with
4718 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4719 nibble as nuthin. (on Sun 3 at least) */
4720 /* Translate the internal relocation information into target-specific
4721 format. */
4722 #ifdef comment
4723 void
4724 md_ri_to_chars (the_bytes, ri)
4725 char *the_bytes;
4726 struct reloc_info_generic *ri;
4727 {
4728 /* this is easy */
4729 md_number_to_chars (the_bytes, ri->r_address, 4);
4730 /* now the fun stuff */
4731 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4732 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4733 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4734 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4735 ((ri->r_extern << 4) & 0x10));
4736 }
4737
4738 #endif /* comment */
4739
4740 #ifndef BFD_ASSEMBLER
4741 void
4742 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4743 char *where;
4744 fixS *fixP;
4745 relax_addressT segment_address_in_file;
4746 {
4747 /*
4748 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4749 * Out: GNU LD relocation length code: 0, 1, or 2.
4750 */
4751
4752 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4753 long r_symbolnum;
4754
4755 know (fixP->fx_addsy != NULL);
4756
4757 md_number_to_chars (where,
4758 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4759 4);
4760
4761 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4762 ? S_GET_TYPE (fixP->fx_addsy)
4763 : fixP->fx_addsy->sy_number);
4764
4765 where[4] = (r_symbolnum >> 16) & 0x0ff;
4766 where[5] = (r_symbolnum >> 8) & 0x0ff;
4767 where[6] = r_symbolnum & 0x0ff;
4768 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4769 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4770 }
4771 #endif
4772
4773 #endif /* OBJ_AOUT or OBJ_BOUT */
4774
4775 #ifndef WORKING_DOT_WORD
4776 CONST int md_short_jump_size = 4;
4777 CONST int md_long_jump_size = 6;
4778
4779 void
4780 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4781 char *ptr;
4782 addressT from_addr, to_addr;
4783 fragS *frag ATTRIBUTE_UNUSED;
4784 symbolS *to_symbol ATTRIBUTE_UNUSED;
4785 {
4786 valueT offset;
4787
4788 offset = to_addr - (from_addr + 2);
4789
4790 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4791 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4792 }
4793
4794 void
4795 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4796 char *ptr;
4797 addressT from_addr, to_addr;
4798 fragS *frag;
4799 symbolS *to_symbol;
4800 {
4801 valueT offset;
4802
4803 if (!HAVE_LONG_BRANCH(current_architecture))
4804 {
4805 offset = to_addr - S_GET_VALUE (to_symbol);
4806 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4807 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4808 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4809 0, NO_RELOC);
4810 }
4811 else
4812 {
4813 offset = to_addr - (from_addr + 2);
4814 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4815 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4816 }
4817 }
4818
4819 #endif
4820
4821 /* Different values of OK tell what its OK to return. Things that
4822 aren't OK are an error (what a shock, no?)
4823
4824 0: Everything is OK
4825 10: Absolute 1:8 only
4826 20: Absolute 0:7 only
4827 30: absolute 0:15 only
4828 40: Absolute 0:31 only
4829 50: absolute 0:127 only
4830 55: absolute -64:63 only
4831 60: absolute -128:127 only
4832 70: absolute 0:4095 only
4833 80: No bignums
4834
4835 */
4836
4837 static int
4838 get_num (exp, ok)
4839 struct m68k_exp *exp;
4840 int ok;
4841 {
4842 if (exp->exp.X_op == O_absent)
4843 {
4844 /* Do the same thing the VAX asm does */
4845 op (exp) = O_constant;
4846 adds (exp) = 0;
4847 subs (exp) = 0;
4848 offs (exp) = 0;
4849 if (ok == 10)
4850 {
4851 as_warn (_("expression out of range: defaulting to 1"));
4852 offs (exp) = 1;
4853 }
4854 }
4855 else if (exp->exp.X_op == O_constant)
4856 {
4857 switch (ok)
4858 {
4859 case 10:
4860 if (offs (exp) < 1 || offs (exp) > 8)
4861 {
4862 as_warn (_("expression out of range: defaulting to 1"));
4863 offs (exp) = 1;
4864 }
4865 break;
4866 case 20:
4867 if (offs (exp) < 0 || offs (exp) > 7)
4868 goto outrange;
4869 break;
4870 case 30:
4871 if (offs (exp) < 0 || offs (exp) > 15)
4872 goto outrange;
4873 break;
4874 case 40:
4875 if (offs (exp) < 0 || offs (exp) > 32)
4876 goto outrange;
4877 break;
4878 case 50:
4879 if (offs (exp) < 0 || offs (exp) > 127)
4880 goto outrange;
4881 break;
4882 case 55:
4883 if (offs (exp) < -64 || offs (exp) > 63)
4884 goto outrange;
4885 break;
4886 case 60:
4887 if (offs (exp) < -128 || offs (exp) > 127)
4888 goto outrange;
4889 break;
4890 case 70:
4891 if (offs (exp) < 0 || offs (exp) > 4095)
4892 {
4893 outrange:
4894 as_warn (_("expression out of range: defaulting to 0"));
4895 offs (exp) = 0;
4896 }
4897 break;
4898 default:
4899 break;
4900 }
4901 }
4902 else if (exp->exp.X_op == O_big)
4903 {
4904 if (offs (exp) <= 0 /* flonum */
4905 && (ok == 80 /* no bignums */
4906 || (ok > 10 /* small-int ranges including 0 ok */
4907 /* If we have a flonum zero, a zero integer should
4908 do as well (e.g., in moveq). */
4909 && generic_floating_point_number.exponent == 0
4910 && generic_floating_point_number.low[0] == 0)))
4911 {
4912 /* HACK! Turn it into a long */
4913 LITTLENUM_TYPE words[6];
4914
4915 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4916 op (exp) = O_constant;
4917 adds (exp) = 0;
4918 subs (exp) = 0;
4919 offs (exp) = words[1] | (words[0] << 16);
4920 }
4921 else if (ok != 0)
4922 {
4923 op (exp) = O_constant;
4924 adds (exp) = 0;
4925 subs (exp) = 0;
4926 offs (exp) = (ok == 10) ? 1 : 0;
4927 as_warn (_("Can't deal with expression; defaulting to %ld"),
4928 offs (exp));
4929 }
4930 }
4931 else
4932 {
4933 if (ok >= 10 && ok <= 70)
4934 {
4935 op (exp) = O_constant;
4936 adds (exp) = 0;
4937 subs (exp) = 0;
4938 offs (exp) = (ok == 10) ? 1 : 0;
4939 as_warn (_("Can't deal with expression; defaulting to %ld"),
4940 offs (exp));
4941 }
4942 }
4943
4944 if (exp->size != SIZE_UNSPEC)
4945 {
4946 switch (exp->size)
4947 {
4948 case SIZE_UNSPEC:
4949 case SIZE_LONG:
4950 break;
4951 case SIZE_BYTE:
4952 if (!isbyte (offs (exp)))
4953 as_warn (_("expression doesn't fit in BYTE"));
4954 break;
4955 case SIZE_WORD:
4956 if (!isword (offs (exp)))
4957 as_warn (_("expression doesn't fit in WORD"));
4958 break;
4959 }
4960 }
4961
4962 return offs (exp);
4963 }
4964
4965 /* These are the back-ends for the various machine dependent pseudo-ops. */
4966
4967 static void
4968 s_data1 (ignore)
4969 int ignore ATTRIBUTE_UNUSED;
4970 {
4971 subseg_set (data_section, 1);
4972 demand_empty_rest_of_line ();
4973 }
4974
4975 static void
4976 s_data2 (ignore)
4977 int ignore ATTRIBUTE_UNUSED;
4978 {
4979 subseg_set (data_section, 2);
4980 demand_empty_rest_of_line ();
4981 }
4982
4983 static void
4984 s_bss (ignore)
4985 int ignore ATTRIBUTE_UNUSED;
4986 {
4987 /* We don't support putting frags in the BSS segment, we fake it
4988 by marking in_bss, then looking at s_skip for clues. */
4989
4990 subseg_set (bss_section, 0);
4991 demand_empty_rest_of_line ();
4992 }
4993
4994 static void
4995 s_even (ignore)
4996 int ignore ATTRIBUTE_UNUSED;
4997 {
4998 register int temp;
4999 register long temp_fill;
5000
5001 temp = 1; /* JF should be 2? */
5002 temp_fill = get_absolute_expression ();
5003 if (!need_pass_2) /* Never make frag if expect extra pass. */
5004 frag_align (temp, (int) temp_fill, 0);
5005 demand_empty_rest_of_line ();
5006 record_alignment (now_seg, temp);
5007 }
5008
5009 static void
5010 s_proc (ignore)
5011 int ignore ATTRIBUTE_UNUSED;
5012 {
5013 demand_empty_rest_of_line ();
5014 }
5015 \f
5016 /* Pseudo-ops handled for MRI compatibility. */
5017
5018 /* This function returns non-zero if the argument is a conditional
5019 pseudo-op. This is called when checking whether a pending
5020 alignment is needed. */
5021
5022 int
5023 m68k_conditional_pseudoop (pop)
5024 pseudo_typeS *pop;
5025 {
5026 return (pop->poc_handler == s_mri_if
5027 || pop->poc_handler == s_mri_else);
5028 }
5029
5030 /* Handle an MRI style chip specification. */
5031
5032 static void
5033 mri_chip ()
5034 {
5035 char *s;
5036 char c;
5037 int i;
5038
5039 s = input_line_pointer;
5040 /* We can't use get_symbol_end since the processor names are not proper
5041 symbols. */
5042 while (is_part_of_name (c = *input_line_pointer++))
5043 ;
5044 *--input_line_pointer = 0;
5045 for (i = 0; i < n_archs; i++)
5046 if (strcasecmp (s, archs[i].name) == 0)
5047 break;
5048 if (i >= n_archs)
5049 {
5050 as_bad (_("%s: unrecognized processor name"), s);
5051 *input_line_pointer = c;
5052 ignore_rest_of_line ();
5053 return;
5054 }
5055 *input_line_pointer = c;
5056
5057 if (*input_line_pointer == '/')
5058 current_architecture = 0;
5059 else
5060 current_architecture &= m68881 | m68851;
5061 current_architecture |= archs[i].arch;
5062
5063 while (*input_line_pointer == '/')
5064 {
5065 ++input_line_pointer;
5066 s = input_line_pointer;
5067 /* We can't use get_symbol_end since the processor names are not
5068 proper symbols. */
5069 while (is_part_of_name (c = *input_line_pointer++))
5070 ;
5071 *--input_line_pointer = 0;
5072 if (strcmp (s, "68881") == 0)
5073 current_architecture |= m68881;
5074 else if (strcmp (s, "68851") == 0)
5075 current_architecture |= m68851;
5076 *input_line_pointer = c;
5077 }
5078
5079 /* Update info about available control registers. */
5080 select_control_regs ();
5081 }
5082
5083 /* The MRI CHIP pseudo-op. */
5084
5085 static void
5086 s_chip (ignore)
5087 int ignore ATTRIBUTE_UNUSED;
5088 {
5089 char *stop = NULL;
5090 char stopc;
5091
5092 if (flag_mri)
5093 stop = mri_comment_field (&stopc);
5094 mri_chip ();
5095 if (flag_mri)
5096 mri_comment_end (stop, stopc);
5097 demand_empty_rest_of_line ();
5098 }
5099
5100 /* The MRI FOPT pseudo-op. */
5101
5102 static void
5103 s_fopt (ignore)
5104 int ignore ATTRIBUTE_UNUSED;
5105 {
5106 SKIP_WHITESPACE ();
5107
5108 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5109 {
5110 int temp;
5111
5112 input_line_pointer += 3;
5113 temp = get_absolute_expression ();
5114 if (temp < 0 || temp > 7)
5115 as_bad (_("bad coprocessor id"));
5116 else
5117 m68k_float_copnum = COP0 + temp;
5118 }
5119 else
5120 {
5121 as_bad (_("unrecognized fopt option"));
5122 ignore_rest_of_line ();
5123 return;
5124 }
5125
5126 demand_empty_rest_of_line ();
5127 }
5128
5129 /* The structure used to handle the MRI OPT pseudo-op. */
5130
5131 struct opt_action
5132 {
5133 /* The name of the option. */
5134 const char *name;
5135
5136 /* If this is not NULL, just call this function. The first argument
5137 is the ARG field of this structure, the second argument is
5138 whether the option was negated. */
5139 void (*pfn) PARAMS ((int arg, int on));
5140
5141 /* If this is not NULL, and the PFN field is NULL, set the variable
5142 this points to. Set it to the ARG field if the option was not
5143 negated, and the NOTARG field otherwise. */
5144 int *pvar;
5145
5146 /* The value to pass to PFN or to assign to *PVAR. */
5147 int arg;
5148
5149 /* The value to assign to *PVAR if the option is negated. If PFN is
5150 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5151 the option may not be negated. */
5152 int notarg;
5153 };
5154
5155 /* The table used to handle the MRI OPT pseudo-op. */
5156
5157 static void skip_to_comma PARAMS ((int, int));
5158 static void opt_nest PARAMS ((int, int));
5159 static void opt_chip PARAMS ((int, int));
5160 static void opt_list PARAMS ((int, int));
5161 static void opt_list_symbols PARAMS ((int, int));
5162
5163 static const struct opt_action opt_table[] =
5164 {
5165 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5166
5167 /* We do relaxing, so there is little use for these options. */
5168 { "b", 0, 0, 0, 0 },
5169 { "brs", 0, 0, 0, 0 },
5170 { "brb", 0, 0, 0, 0 },
5171 { "brl", 0, 0, 0, 0 },
5172 { "brw", 0, 0, 0, 0 },
5173
5174 { "c", 0, 0, 0, 0 },
5175 { "cex", 0, 0, 0, 0 },
5176 { "case", 0, &symbols_case_sensitive, 1, 0 },
5177 { "cl", 0, 0, 0, 0 },
5178 { "cre", 0, 0, 0, 0 },
5179 { "d", 0, &flag_keep_locals, 1, 0 },
5180 { "e", 0, 0, 0, 0 },
5181 { "f", 0, &flag_short_refs, 1, 0 },
5182 { "frs", 0, &flag_short_refs, 1, 0 },
5183 { "frl", 0, &flag_short_refs, 0, 1 },
5184 { "g", 0, 0, 0, 0 },
5185 { "i", 0, 0, 0, 0 },
5186 { "m", 0, 0, 0, 0 },
5187 { "mex", 0, 0, 0, 0 },
5188 { "mc", 0, 0, 0, 0 },
5189 { "md", 0, 0, 0, 0 },
5190 { "nest", opt_nest, 0, 0, 0 },
5191 { "next", skip_to_comma, 0, 0, 0 },
5192 { "o", 0, 0, 0, 0 },
5193 { "old", 0, 0, 0, 0 },
5194 { "op", skip_to_comma, 0, 0, 0 },
5195 { "pco", 0, 0, 0, 0 },
5196 { "p", opt_chip, 0, 0, 0 },
5197 { "pcr", 0, 0, 0, 0 },
5198 { "pcs", 0, 0, 0, 0 },
5199 { "r", 0, 0, 0, 0 },
5200 { "quick", 0, &m68k_quick, 1, 0 },
5201 { "rel32", 0, &m68k_rel32, 1, 0 },
5202 { "s", opt_list, 0, 0, 0 },
5203 { "t", opt_list_symbols, 0, 0, 0 },
5204 { "w", 0, &flag_no_warnings, 0, 1 },
5205 { "x", 0, 0, 0, 0 }
5206 };
5207
5208 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5209
5210 /* The MRI OPT pseudo-op. */
5211
5212 static void
5213 s_opt (ignore)
5214 int ignore ATTRIBUTE_UNUSED;
5215 {
5216 do
5217 {
5218 int t;
5219 char *s;
5220 char c;
5221 int i;
5222 const struct opt_action *o;
5223
5224 SKIP_WHITESPACE ();
5225
5226 t = 1;
5227 if (*input_line_pointer == '-')
5228 {
5229 ++input_line_pointer;
5230 t = 0;
5231 }
5232 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5233 {
5234 input_line_pointer += 2;
5235 t = 0;
5236 }
5237
5238 s = input_line_pointer;
5239 c = get_symbol_end ();
5240
5241 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5242 {
5243 if (strcasecmp (s, o->name) == 0)
5244 {
5245 if (o->pfn)
5246 {
5247 /* Restore input_line_pointer now in case the option
5248 takes arguments. */
5249 *input_line_pointer = c;
5250 (*o->pfn) (o->arg, t);
5251 }
5252 else if (o->pvar != NULL)
5253 {
5254 if (! t && o->arg == o->notarg)
5255 as_bad (_("option `%s' may not be negated"), s);
5256 *input_line_pointer = c;
5257 *o->pvar = t ? o->arg : o->notarg;
5258 }
5259 else
5260 *input_line_pointer = c;
5261 break;
5262 }
5263 }
5264 if (i >= OPTCOUNT)
5265 {
5266 as_bad (_("option `%s' not recognized"), s);
5267 *input_line_pointer = c;
5268 }
5269 }
5270 while (*input_line_pointer++ == ',');
5271
5272 /* Move back to terminating character. */
5273 --input_line_pointer;
5274 demand_empty_rest_of_line ();
5275 }
5276
5277 /* Skip ahead to a comma. This is used for OPT options which we do
5278 not suppor tand which take arguments. */
5279
5280 static void
5281 skip_to_comma (arg, on)
5282 int arg ATTRIBUTE_UNUSED;
5283 int on ATTRIBUTE_UNUSED;
5284 {
5285 while (*input_line_pointer != ','
5286 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5287 ++input_line_pointer;
5288 }
5289
5290 /* Handle the OPT NEST=depth option. */
5291
5292 static void
5293 opt_nest (arg, on)
5294 int arg ATTRIBUTE_UNUSED;
5295 int on ATTRIBUTE_UNUSED;
5296 {
5297 if (*input_line_pointer != '=')
5298 {
5299 as_bad (_("bad format of OPT NEST=depth"));
5300 return;
5301 }
5302
5303 ++input_line_pointer;
5304 max_macro_nest = get_absolute_expression ();
5305 }
5306
5307 /* Handle the OPT P=chip option. */
5308
5309 static void
5310 opt_chip (arg, on)
5311 int arg ATTRIBUTE_UNUSED;
5312 int on ATTRIBUTE_UNUSED;
5313 {
5314 if (*input_line_pointer != '=')
5315 {
5316 /* This is just OPT P, which we do not support. */
5317 return;
5318 }
5319
5320 ++input_line_pointer;
5321 mri_chip ();
5322 }
5323
5324 /* Handle the OPT S option. */
5325
5326 static void
5327 opt_list (arg, on)
5328 int arg ATTRIBUTE_UNUSED;
5329 int on;
5330 {
5331 listing_list (on);
5332 }
5333
5334 /* Handle the OPT T option. */
5335
5336 static void
5337 opt_list_symbols (arg, on)
5338 int arg ATTRIBUTE_UNUSED;
5339 int on;
5340 {
5341 if (on)
5342 listing |= LISTING_SYMBOLS;
5343 else
5344 listing &=~ LISTING_SYMBOLS;
5345 }
5346
5347 /* Handle the MRI REG pseudo-op. */
5348
5349 static void
5350 s_reg (ignore)
5351 int ignore ATTRIBUTE_UNUSED;
5352 {
5353 char *s;
5354 int c;
5355 struct m68k_op rop;
5356 int mask;
5357 char *stop = NULL;
5358 char stopc;
5359
5360 if (line_label == NULL)
5361 {
5362 as_bad (_("missing label"));
5363 ignore_rest_of_line ();
5364 return;
5365 }
5366
5367 if (flag_mri)
5368 stop = mri_comment_field (&stopc);
5369
5370 SKIP_WHITESPACE ();
5371
5372 s = input_line_pointer;
5373 while (isalnum ((unsigned char) *input_line_pointer)
5374 #ifdef REGISTER_PREFIX
5375 || *input_line_pointer == REGISTER_PREFIX
5376 #endif
5377 || *input_line_pointer == '/'
5378 || *input_line_pointer == '-')
5379 ++input_line_pointer;
5380 c = *input_line_pointer;
5381 *input_line_pointer = '\0';
5382
5383 if (m68k_ip_op (s, &rop) != 0)
5384 {
5385 if (rop.error == NULL)
5386 as_bad (_("bad register list"));
5387 else
5388 as_bad (_("bad register list: %s"), rop.error);
5389 *input_line_pointer = c;
5390 ignore_rest_of_line ();
5391 return;
5392 }
5393
5394 *input_line_pointer = c;
5395
5396 if (rop.mode == REGLST)
5397 mask = rop.mask;
5398 else if (rop.mode == DREG)
5399 mask = 1 << (rop.reg - DATA0);
5400 else if (rop.mode == AREG)
5401 mask = 1 << (rop.reg - ADDR0 + 8);
5402 else if (rop.mode == FPREG)
5403 mask = 1 << (rop.reg - FP0 + 16);
5404 else if (rop.mode == CONTROL
5405 && rop.reg == FPI)
5406 mask = 1 << 24;
5407 else if (rop.mode == CONTROL
5408 && rop.reg == FPS)
5409 mask = 1 << 25;
5410 else if (rop.mode == CONTROL
5411 && rop.reg == FPC)
5412 mask = 1 << 26;
5413 else
5414 {
5415 as_bad (_("bad register list"));
5416 ignore_rest_of_line ();
5417 return;
5418 }
5419
5420 S_SET_SEGMENT (line_label, reg_section);
5421 S_SET_VALUE (line_label, ~mask);
5422 symbol_set_frag (line_label, &zero_address_frag);
5423
5424 if (flag_mri)
5425 mri_comment_end (stop, stopc);
5426
5427 demand_empty_rest_of_line ();
5428 }
5429
5430 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5431
5432 struct save_opts
5433 {
5434 struct save_opts *next;
5435 int abspcadd;
5436 int symbols_case_sensitive;
5437 int keep_locals;
5438 int short_refs;
5439 int architecture;
5440 int quick;
5441 int rel32;
5442 int listing;
5443 int no_warnings;
5444 /* FIXME: We don't save OPT S. */
5445 };
5446
5447 /* This variable holds the stack of saved options. */
5448
5449 static struct save_opts *save_stack;
5450
5451 /* The MRI SAVE pseudo-op. */
5452
5453 static void
5454 s_save (ignore)
5455 int ignore ATTRIBUTE_UNUSED;
5456 {
5457 struct save_opts *s;
5458
5459 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5460 s->abspcadd = m68k_abspcadd;
5461 s->symbols_case_sensitive = symbols_case_sensitive;
5462 s->keep_locals = flag_keep_locals;
5463 s->short_refs = flag_short_refs;
5464 s->architecture = current_architecture;
5465 s->quick = m68k_quick;
5466 s->rel32 = m68k_rel32;
5467 s->listing = listing;
5468 s->no_warnings = flag_no_warnings;
5469
5470 s->next = save_stack;
5471 save_stack = s;
5472
5473 demand_empty_rest_of_line ();
5474 }
5475
5476 /* The MRI RESTORE pseudo-op. */
5477
5478 static void
5479 s_restore (ignore)
5480 int ignore ATTRIBUTE_UNUSED;
5481 {
5482 struct save_opts *s;
5483
5484 if (save_stack == NULL)
5485 {
5486 as_bad (_("restore without save"));
5487 ignore_rest_of_line ();
5488 return;
5489 }
5490
5491 s = save_stack;
5492 save_stack = s->next;
5493
5494 m68k_abspcadd = s->abspcadd;
5495 symbols_case_sensitive = s->symbols_case_sensitive;
5496 flag_keep_locals = s->keep_locals;
5497 flag_short_refs = s->short_refs;
5498 current_architecture = s->architecture;
5499 m68k_quick = s->quick;
5500 m68k_rel32 = s->rel32;
5501 listing = s->listing;
5502 flag_no_warnings = s->no_warnings;
5503
5504 free (s);
5505
5506 demand_empty_rest_of_line ();
5507 }
5508
5509 /* Types of MRI structured control directives. */
5510
5511 enum mri_control_type
5512 {
5513 mri_for,
5514 mri_if,
5515 mri_repeat,
5516 mri_while
5517 };
5518
5519 /* This structure is used to stack the MRI structured control
5520 directives. */
5521
5522 struct mri_control_info
5523 {
5524 /* The directive within which this one is enclosed. */
5525 struct mri_control_info *outer;
5526
5527 /* The type of directive. */
5528 enum mri_control_type type;
5529
5530 /* Whether an ELSE has been in an IF. */
5531 int else_seen;
5532
5533 /* The add or sub statement at the end of a FOR. */
5534 char *incr;
5535
5536 /* The label of the top of a FOR or REPEAT loop. */
5537 char *top;
5538
5539 /* The label to jump to for the next iteration, or the else
5540 expression of a conditional. */
5541 char *next;
5542
5543 /* The label to jump to to break out of the loop, or the label past
5544 the end of a conditional. */
5545 char *bottom;
5546 };
5547
5548 /* The stack of MRI structured control directives. */
5549
5550 static struct mri_control_info *mri_control_stack;
5551
5552 /* The current MRI structured control directive index number, used to
5553 generate label names. */
5554
5555 static int mri_control_index;
5556
5557 /* Some function prototypes. */
5558
5559 static void mri_assemble PARAMS ((char *));
5560 static char *mri_control_label PARAMS ((void));
5561 static struct mri_control_info *push_mri_control
5562 PARAMS ((enum mri_control_type));
5563 static void pop_mri_control PARAMS ((void));
5564 static int parse_mri_condition PARAMS ((int *));
5565 static int parse_mri_control_operand
5566 PARAMS ((int *, char **, char **, char **, char **));
5567 static int swap_mri_condition PARAMS ((int));
5568 static int reverse_mri_condition PARAMS ((int));
5569 static void build_mri_control_operand
5570 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5571 const char *, int));
5572 static void parse_mri_control_expression
5573 PARAMS ((char *, int, const char *, const char *, int));
5574
5575 /* Assemble an instruction for an MRI structured control directive. */
5576
5577 static void
5578 mri_assemble (str)
5579 char *str;
5580 {
5581 char *s;
5582
5583 /* md_assemble expects the opcode to be in lower case. */
5584 for (s = str; *s != ' ' && *s != '\0'; s++)
5585 {
5586 if (isupper ((unsigned char) *s))
5587 *s = tolower ((unsigned char) *s);
5588 }
5589
5590 md_assemble (str);
5591 }
5592
5593 /* Generate a new MRI label structured control directive label name. */
5594
5595 static char *
5596 mri_control_label ()
5597 {
5598 char *n;
5599
5600 n = (char *) xmalloc (20);
5601 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5602 ++mri_control_index;
5603 return n;
5604 }
5605
5606 /* Create a new MRI structured control directive. */
5607
5608 static struct mri_control_info *
5609 push_mri_control (type)
5610 enum mri_control_type type;
5611 {
5612 struct mri_control_info *n;
5613
5614 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5615
5616 n->type = type;
5617 n->else_seen = 0;
5618 if (type == mri_if || type == mri_while)
5619 n->top = NULL;
5620 else
5621 n->top = mri_control_label ();
5622 n->next = mri_control_label ();
5623 n->bottom = mri_control_label ();
5624
5625 n->outer = mri_control_stack;
5626 mri_control_stack = n;
5627
5628 return n;
5629 }
5630
5631 /* Pop off the stack of MRI structured control directives. */
5632
5633 static void
5634 pop_mri_control ()
5635 {
5636 struct mri_control_info *n;
5637
5638 n = mri_control_stack;
5639 mri_control_stack = n->outer;
5640 if (n->top != NULL)
5641 free (n->top);
5642 free (n->next);
5643 free (n->bottom);
5644 free (n);
5645 }
5646
5647 /* Recognize a condition code in an MRI structured control expression. */
5648
5649 static int
5650 parse_mri_condition (pcc)
5651 int *pcc;
5652 {
5653 char c1, c2;
5654
5655 know (*input_line_pointer == '<');
5656
5657 ++input_line_pointer;
5658 c1 = *input_line_pointer++;
5659 c2 = *input_line_pointer++;
5660
5661 if (*input_line_pointer != '>')
5662 {
5663 as_bad (_("syntax error in structured control directive"));
5664 return 0;
5665 }
5666
5667 ++input_line_pointer;
5668 SKIP_WHITESPACE ();
5669
5670 if (isupper (c1))
5671 c1 = tolower (c1);
5672 if (isupper (c2))
5673 c2 = tolower (c2);
5674
5675 *pcc = (c1 << 8) | c2;
5676
5677 return 1;
5678 }
5679
5680 /* Parse a single operand in an MRI structured control expression. */
5681
5682 static int
5683 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5684 int *pcc;
5685 char **leftstart;
5686 char **leftstop;
5687 char **rightstart;
5688 char **rightstop;
5689 {
5690 char *s;
5691
5692 SKIP_WHITESPACE ();
5693
5694 *pcc = -1;
5695 *leftstart = NULL;
5696 *leftstop = NULL;
5697 *rightstart = NULL;
5698 *rightstop = NULL;
5699
5700 if (*input_line_pointer == '<')
5701 {
5702 /* It's just a condition code. */
5703 return parse_mri_condition (pcc);
5704 }
5705
5706 /* Look ahead for the condition code. */
5707 for (s = input_line_pointer; *s != '\0'; ++s)
5708 {
5709 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5710 break;
5711 }
5712 if (*s == '\0')
5713 {
5714 as_bad (_("missing condition code in structured control directive"));
5715 return 0;
5716 }
5717
5718 *leftstart = input_line_pointer;
5719 *leftstop = s;
5720 if (*leftstop > *leftstart
5721 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5722 --*leftstop;
5723
5724 input_line_pointer = s;
5725 if (! parse_mri_condition (pcc))
5726 return 0;
5727
5728 /* Look ahead for AND or OR or end of line. */
5729 for (s = input_line_pointer; *s != '\0'; ++s)
5730 {
5731 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5732 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5733 ^^^ ^^ */
5734 if ( ( s == input_line_pointer
5735 || *(s-1) == ' '
5736 || *(s-1) == '\t')
5737 && ( ( strncasecmp (s, "AND", 3) == 0
5738 && (s[3] == '.' || ! is_part_of_name (s[3])))
5739 || ( strncasecmp (s, "OR", 2) == 0
5740 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5741 break;
5742 }
5743
5744 *rightstart = input_line_pointer;
5745 *rightstop = s;
5746 if (*rightstop > *rightstart
5747 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5748 --*rightstop;
5749
5750 input_line_pointer = s;
5751
5752 return 1;
5753 }
5754
5755 #define MCC(b1, b2) (((b1) << 8) | (b2))
5756
5757 /* Swap the sense of a condition. This changes the condition so that
5758 it generates the same result when the operands are swapped. */
5759
5760 static int
5761 swap_mri_condition (cc)
5762 int cc;
5763 {
5764 switch (cc)
5765 {
5766 case MCC ('h', 'i'): return MCC ('c', 's');
5767 case MCC ('l', 's'): return MCC ('c', 'c');
5768 /* <HS> is an alias for <CC> */
5769 case MCC ('h', 's'):
5770 case MCC ('c', 'c'): return MCC ('l', 's');
5771 /* <LO> is an alias for <CS> */
5772 case MCC ('l', 'o'):
5773 case MCC ('c', 's'): return MCC ('h', 'i');
5774 case MCC ('p', 'l'): return MCC ('m', 'i');
5775 case MCC ('m', 'i'): return MCC ('p', 'l');
5776 case MCC ('g', 'e'): return MCC ('l', 'e');
5777 case MCC ('l', 't'): return MCC ('g', 't');
5778 case MCC ('g', 't'): return MCC ('l', 't');
5779 case MCC ('l', 'e'): return MCC ('g', 'e');
5780 /* issue a warning for conditions we can not swap */
5781 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5782 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5783 case MCC ('v', 'c'):
5784 case MCC ('v', 's'):
5785 default :
5786 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5787 (char) (cc >> 8), (char) (cc));
5788 break;
5789 }
5790 return cc;
5791 }
5792
5793 /* Reverse the sense of a condition. */
5794
5795 static int
5796 reverse_mri_condition (cc)
5797 int cc;
5798 {
5799 switch (cc)
5800 {
5801 case MCC ('h', 'i'): return MCC ('l', 's');
5802 case MCC ('l', 's'): return MCC ('h', 'i');
5803 /* <HS> is an alias for <CC> */
5804 case MCC ('h', 's'): return MCC ('l', 'o');
5805 case MCC ('c', 'c'): return MCC ('c', 's');
5806 /* <LO> is an alias for <CS> */
5807 case MCC ('l', 'o'): return MCC ('h', 's');
5808 case MCC ('c', 's'): return MCC ('c', 'c');
5809 case MCC ('n', 'e'): return MCC ('e', 'q');
5810 case MCC ('e', 'q'): return MCC ('n', 'e');
5811 case MCC ('v', 'c'): return MCC ('v', 's');
5812 case MCC ('v', 's'): return MCC ('v', 'c');
5813 case MCC ('p', 'l'): return MCC ('m', 'i');
5814 case MCC ('m', 'i'): return MCC ('p', 'l');
5815 case MCC ('g', 'e'): return MCC ('l', 't');
5816 case MCC ('l', 't'): return MCC ('g', 'e');
5817 case MCC ('g', 't'): return MCC ('l', 'e');
5818 case MCC ('l', 'e'): return MCC ('g', 't');
5819 }
5820 return cc;
5821 }
5822
5823 /* Build an MRI structured control expression. This generates test
5824 and branch instructions. It goes to TRUELAB if the condition is
5825 true, and to FALSELAB if the condition is false. Exactly one of
5826 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5827 is the size qualifier for the expression. EXTENT is the size to
5828 use for the branch. */
5829
5830 static void
5831 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5832 rightstop, truelab, falselab, extent)
5833 int qual;
5834 int cc;
5835 char *leftstart;
5836 char *leftstop;
5837 char *rightstart;
5838 char *rightstop;
5839 const char *truelab;
5840 const char *falselab;
5841 int extent;
5842 {
5843 char *buf;
5844 char *s;
5845
5846 if (leftstart != NULL)
5847 {
5848 struct m68k_op leftop, rightop;
5849 char c;
5850
5851 /* Swap the compare operands, if necessary, to produce a legal
5852 m68k compare instruction. Comparing a register operand with
5853 a non-register operand requires the register to be on the
5854 right (cmp, cmpa). Comparing an immediate value with
5855 anything requires the immediate value to be on the left
5856 (cmpi). */
5857
5858 c = *leftstop;
5859 *leftstop = '\0';
5860 (void) m68k_ip_op (leftstart, &leftop);
5861 *leftstop = c;
5862
5863 c = *rightstop;
5864 *rightstop = '\0';
5865 (void) m68k_ip_op (rightstart, &rightop);
5866 *rightstop = c;
5867
5868 if (rightop.mode == IMMED
5869 || ((leftop.mode == DREG || leftop.mode == AREG)
5870 && (rightop.mode != DREG && rightop.mode != AREG)))
5871 {
5872 char *temp;
5873
5874 /* Correct conditional handling:
5875 if #1 <lt> d0 then ;means if (1 < d0)
5876 ...
5877 endi
5878
5879 should assemble to:
5880
5881 cmp #1,d0 if we do *not* swap the operands
5882 bgt true we need the swapped condition!
5883 ble false
5884 true:
5885 ...
5886 false:
5887 */
5888 temp = leftstart;
5889 leftstart = rightstart;
5890 rightstart = temp;
5891 temp = leftstop;
5892 leftstop = rightstop;
5893 rightstop = temp;
5894 } else {
5895 cc = swap_mri_condition (cc);
5896 }
5897 }
5898
5899 if (truelab == NULL)
5900 {
5901 cc = reverse_mri_condition (cc);
5902 truelab = falselab;
5903 }
5904
5905 if (leftstart != NULL)
5906 {
5907 buf = (char *) xmalloc (20
5908 + (leftstop - leftstart)
5909 + (rightstop - rightstart));
5910 s = buf;
5911 *s++ = 'c';
5912 *s++ = 'm';
5913 *s++ = 'p';
5914 if (qual != '\0')
5915 *s++ = tolower (qual);
5916 *s++ = ' ';
5917 memcpy (s, leftstart, leftstop - leftstart);
5918 s += leftstop - leftstart;
5919 *s++ = ',';
5920 memcpy (s, rightstart, rightstop - rightstart);
5921 s += rightstop - rightstart;
5922 *s = '\0';
5923 mri_assemble (buf);
5924 free (buf);
5925 }
5926
5927 buf = (char *) xmalloc (20 + strlen (truelab));
5928 s = buf;
5929 *s++ = 'b';
5930 *s++ = cc >> 8;
5931 *s++ = cc & 0xff;
5932 if (extent != '\0')
5933 *s++ = tolower (extent);
5934 *s++ = ' ';
5935 strcpy (s, truelab);
5936 mri_assemble (buf);
5937 free (buf);
5938 }
5939
5940 /* Parse an MRI structured control expression. This generates test
5941 and branch instructions. STOP is where the expression ends. It
5942 goes to TRUELAB if the condition is true, and to FALSELAB if the
5943 condition is false. Exactly one of TRUELAB and FALSELAB will be
5944 NULL, meaning to fall through. QUAL is the size qualifier for the
5945 expression. EXTENT is the size to use for the branch. */
5946
5947 static void
5948 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5949 char *stop;
5950 int qual;
5951 const char *truelab;
5952 const char *falselab;
5953 int extent;
5954 {
5955 int c;
5956 int cc;
5957 char *leftstart;
5958 char *leftstop;
5959 char *rightstart;
5960 char *rightstop;
5961
5962 c = *stop;
5963 *stop = '\0';
5964
5965 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5966 &rightstart, &rightstop))
5967 {
5968 *stop = c;
5969 return;
5970 }
5971
5972 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5973 {
5974 const char *flab;
5975
5976 if (falselab != NULL)
5977 flab = falselab;
5978 else
5979 flab = mri_control_label ();
5980
5981 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5982 rightstop, (const char *) NULL, flab, extent);
5983
5984 input_line_pointer += 3;
5985 if (*input_line_pointer != '.'
5986 || input_line_pointer[1] == '\0')
5987 qual = '\0';
5988 else
5989 {
5990 qual = input_line_pointer[1];
5991 input_line_pointer += 2;
5992 }
5993
5994 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5995 &rightstart, &rightstop))
5996 {
5997 *stop = c;
5998 return;
5999 }
6000
6001 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6002 rightstop, truelab, falselab, extent);
6003
6004 if (falselab == NULL)
6005 colon (flab);
6006 }
6007 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6008 {
6009 const char *tlab;
6010
6011 if (truelab != NULL)
6012 tlab = truelab;
6013 else
6014 tlab = mri_control_label ();
6015
6016 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6017 rightstop, tlab, (const char *) NULL, extent);
6018
6019 input_line_pointer += 2;
6020 if (*input_line_pointer != '.'
6021 || input_line_pointer[1] == '\0')
6022 qual = '\0';
6023 else
6024 {
6025 qual = input_line_pointer[1];
6026 input_line_pointer += 2;
6027 }
6028
6029 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6030 &rightstart, &rightstop))
6031 {
6032 *stop = c;
6033 return;
6034 }
6035
6036 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6037 rightstop, truelab, falselab, extent);
6038
6039 if (truelab == NULL)
6040 colon (tlab);
6041 }
6042 else
6043 {
6044 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6045 rightstop, truelab, falselab, extent);
6046 }
6047
6048 *stop = c;
6049 if (input_line_pointer != stop)
6050 as_bad (_("syntax error in structured control directive"));
6051 }
6052
6053 /* Handle the MRI IF pseudo-op. This may be a structured control
6054 directive, or it may be a regular assembler conditional, depending
6055 on its operands. */
6056
6057 static void
6058 s_mri_if (qual)
6059 int qual;
6060 {
6061 char *s;
6062 int c;
6063 struct mri_control_info *n;
6064
6065 /* A structured control directive must end with THEN with an
6066 optional qualifier. */
6067 s = input_line_pointer;
6068 /* We only accept '*' as introduction of comments if preceded by white space
6069 or at first column of a line (I think this can't actually happen here?)
6070 This is important when assembling:
6071 if d0 <ne> 12(a0,d0*2) then
6072 if d0 <ne> #CONST*20 then */
6073 while ( ! ( is_end_of_line[(unsigned char) *s]
6074 || ( flag_mri
6075 && *s == '*'
6076 && ( s == input_line_pointer
6077 || *(s-1) == ' '
6078 || *(s-1) == '\t'))))
6079 ++s;
6080 --s;
6081 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6082 --s;
6083
6084 if (s - input_line_pointer > 1
6085 && s[-1] == '.')
6086 s -= 2;
6087
6088 if (s - input_line_pointer < 3
6089 || strncasecmp (s - 3, "THEN", 4) != 0)
6090 {
6091 if (qual != '\0')
6092 {
6093 as_bad (_("missing then"));
6094 ignore_rest_of_line ();
6095 return;
6096 }
6097
6098 /* It's a conditional. */
6099 s_if (O_ne);
6100 return;
6101 }
6102
6103 /* Since this might be a conditional if, this pseudo-op will be
6104 called even if we are supported to be ignoring input. Double
6105 check now. Clobber *input_line_pointer so that ignore_input
6106 thinks that this is not a special pseudo-op. */
6107 c = *input_line_pointer;
6108 *input_line_pointer = 0;
6109 if (ignore_input ())
6110 {
6111 *input_line_pointer = c;
6112 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6113 ++input_line_pointer;
6114 demand_empty_rest_of_line ();
6115 return;
6116 }
6117 *input_line_pointer = c;
6118
6119 n = push_mri_control (mri_if);
6120
6121 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6122 n->next, s[1] == '.' ? s[2] : '\0');
6123
6124 if (s[1] == '.')
6125 input_line_pointer = s + 3;
6126 else
6127 input_line_pointer = s + 1;
6128
6129 if (flag_mri)
6130 {
6131 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6132 ++input_line_pointer;
6133 }
6134
6135 demand_empty_rest_of_line ();
6136 }
6137
6138 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6139 structured IF, associate the ELSE with the IF. Otherwise, assume
6140 it is a conditional else. */
6141
6142 static void
6143 s_mri_else (qual)
6144 int qual;
6145 {
6146 int c;
6147 char *buf;
6148 char q[2];
6149
6150 if (qual == '\0'
6151 && (mri_control_stack == NULL
6152 || mri_control_stack->type != mri_if
6153 || mri_control_stack->else_seen))
6154 {
6155 s_else (0);
6156 return;
6157 }
6158
6159 c = *input_line_pointer;
6160 *input_line_pointer = 0;
6161 if (ignore_input ())
6162 {
6163 *input_line_pointer = c;
6164 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6165 ++input_line_pointer;
6166 demand_empty_rest_of_line ();
6167 return;
6168 }
6169 *input_line_pointer = c;
6170
6171 if (mri_control_stack == NULL
6172 || mri_control_stack->type != mri_if
6173 || mri_control_stack->else_seen)
6174 {
6175 as_bad (_("else without matching if"));
6176 ignore_rest_of_line ();
6177 return;
6178 }
6179
6180 mri_control_stack->else_seen = 1;
6181
6182 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6183 q[0] = tolower (qual);
6184 q[1] = '\0';
6185 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6186 mri_assemble (buf);
6187 free (buf);
6188
6189 colon (mri_control_stack->next);
6190
6191 if (flag_mri)
6192 {
6193 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6194 ++input_line_pointer;
6195 }
6196
6197 demand_empty_rest_of_line ();
6198 }
6199
6200 /* Handle the MRI ENDI pseudo-op. */
6201
6202 static void
6203 s_mri_endi (ignore)
6204 int ignore ATTRIBUTE_UNUSED;
6205 {
6206 if (mri_control_stack == NULL
6207 || mri_control_stack->type != mri_if)
6208 {
6209 as_bad (_("endi without matching if"));
6210 ignore_rest_of_line ();
6211 return;
6212 }
6213
6214 /* ignore_input will not return true for ENDI, so we don't need to
6215 worry about checking it again here. */
6216
6217 if (! mri_control_stack->else_seen)
6218 colon (mri_control_stack->next);
6219 colon (mri_control_stack->bottom);
6220
6221 pop_mri_control ();
6222
6223 if (flag_mri)
6224 {
6225 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6226 ++input_line_pointer;
6227 }
6228
6229 demand_empty_rest_of_line ();
6230 }
6231
6232 /* Handle the MRI BREAK pseudo-op. */
6233
6234 static void
6235 s_mri_break (extent)
6236 int extent;
6237 {
6238 struct mri_control_info *n;
6239 char *buf;
6240 char ex[2];
6241
6242 n = mri_control_stack;
6243 while (n != NULL
6244 && n->type != mri_for
6245 && n->type != mri_repeat
6246 && n->type != mri_while)
6247 n = n->outer;
6248 if (n == NULL)
6249 {
6250 as_bad (_("break outside of structured loop"));
6251 ignore_rest_of_line ();
6252 return;
6253 }
6254
6255 buf = (char *) xmalloc (20 + strlen (n->bottom));
6256 ex[0] = tolower (extent);
6257 ex[1] = '\0';
6258 sprintf (buf, "bra%s %s", ex, n->bottom);
6259 mri_assemble (buf);
6260 free (buf);
6261
6262 if (flag_mri)
6263 {
6264 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6265 ++input_line_pointer;
6266 }
6267
6268 demand_empty_rest_of_line ();
6269 }
6270
6271 /* Handle the MRI NEXT pseudo-op. */
6272
6273 static void
6274 s_mri_next (extent)
6275 int extent;
6276 {
6277 struct mri_control_info *n;
6278 char *buf;
6279 char ex[2];
6280
6281 n = mri_control_stack;
6282 while (n != NULL
6283 && n->type != mri_for
6284 && n->type != mri_repeat
6285 && n->type != mri_while)
6286 n = n->outer;
6287 if (n == NULL)
6288 {
6289 as_bad (_("next outside of structured loop"));
6290 ignore_rest_of_line ();
6291 return;
6292 }
6293
6294 buf = (char *) xmalloc (20 + strlen (n->next));
6295 ex[0] = tolower (extent);
6296 ex[1] = '\0';
6297 sprintf (buf, "bra%s %s", ex, n->next);
6298 mri_assemble (buf);
6299 free (buf);
6300
6301 if (flag_mri)
6302 {
6303 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6304 ++input_line_pointer;
6305 }
6306
6307 demand_empty_rest_of_line ();
6308 }
6309
6310 /* Handle the MRI FOR pseudo-op. */
6311
6312 static void
6313 s_mri_for (qual)
6314 int qual;
6315 {
6316 const char *varstart, *varstop;
6317 const char *initstart, *initstop;
6318 const char *endstart, *endstop;
6319 const char *bystart, *bystop;
6320 int up;
6321 int by;
6322 int extent;
6323 struct mri_control_info *n;
6324 char *buf;
6325 char *s;
6326 char ex[2];
6327
6328 /* The syntax is
6329 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6330 */
6331
6332 SKIP_WHITESPACE ();
6333 varstart = input_line_pointer;
6334
6335 /* Look for the '='. */
6336 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6337 && *input_line_pointer != '=')
6338 ++input_line_pointer;
6339 if (*input_line_pointer != '=')
6340 {
6341 as_bad (_("missing ="));
6342 ignore_rest_of_line ();
6343 return;
6344 }
6345
6346 varstop = input_line_pointer;
6347 if (varstop > varstart
6348 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6349 --varstop;
6350
6351 ++input_line_pointer;
6352
6353 initstart = input_line_pointer;
6354
6355 /* Look for TO or DOWNTO. */
6356 up = 1;
6357 initstop = NULL;
6358 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6359 {
6360 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6361 && ! is_part_of_name (input_line_pointer[2]))
6362 {
6363 initstop = input_line_pointer;
6364 input_line_pointer += 2;
6365 break;
6366 }
6367 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6368 && ! is_part_of_name (input_line_pointer[6]))
6369 {
6370 initstop = input_line_pointer;
6371 up = 0;
6372 input_line_pointer += 6;
6373 break;
6374 }
6375 ++input_line_pointer;
6376 }
6377 if (initstop == NULL)
6378 {
6379 as_bad (_("missing to or downto"));
6380 ignore_rest_of_line ();
6381 return;
6382 }
6383 if (initstop > initstart
6384 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6385 --initstop;
6386
6387 SKIP_WHITESPACE ();
6388 endstart = input_line_pointer;
6389
6390 /* Look for BY or DO. */
6391 by = 0;
6392 endstop = NULL;
6393 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6394 {
6395 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6396 && ! is_part_of_name (input_line_pointer[2]))
6397 {
6398 endstop = input_line_pointer;
6399 by = 1;
6400 input_line_pointer += 2;
6401 break;
6402 }
6403 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6404 && (input_line_pointer[2] == '.'
6405 || ! is_part_of_name (input_line_pointer[2])))
6406 {
6407 endstop = input_line_pointer;
6408 input_line_pointer += 2;
6409 break;
6410 }
6411 ++input_line_pointer;
6412 }
6413 if (endstop == NULL)
6414 {
6415 as_bad (_("missing do"));
6416 ignore_rest_of_line ();
6417 return;
6418 }
6419 if (endstop > endstart
6420 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6421 --endstop;
6422
6423 if (! by)
6424 {
6425 bystart = "#1";
6426 bystop = bystart + 2;
6427 }
6428 else
6429 {
6430 SKIP_WHITESPACE ();
6431 bystart = input_line_pointer;
6432
6433 /* Look for DO. */
6434 bystop = NULL;
6435 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6436 {
6437 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6438 && (input_line_pointer[2] == '.'
6439 || ! is_part_of_name (input_line_pointer[2])))
6440 {
6441 bystop = input_line_pointer;
6442 input_line_pointer += 2;
6443 break;
6444 }
6445 ++input_line_pointer;
6446 }
6447 if (bystop == NULL)
6448 {
6449 as_bad (_("missing do"));
6450 ignore_rest_of_line ();
6451 return;
6452 }
6453 if (bystop > bystart
6454 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6455 --bystop;
6456 }
6457
6458 if (*input_line_pointer != '.')
6459 extent = '\0';
6460 else
6461 {
6462 extent = input_line_pointer[1];
6463 input_line_pointer += 2;
6464 }
6465
6466 /* We have fully parsed the FOR operands. Now build the loop. */
6467
6468 n = push_mri_control (mri_for);
6469
6470 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6471
6472 /* move init,var */
6473 s = buf;
6474 *s++ = 'm';
6475 *s++ = 'o';
6476 *s++ = 'v';
6477 *s++ = 'e';
6478 if (qual != '\0')
6479 *s++ = tolower (qual);
6480 *s++ = ' ';
6481 memcpy (s, initstart, initstop - initstart);
6482 s += initstop - initstart;
6483 *s++ = ',';
6484 memcpy (s, varstart, varstop - varstart);
6485 s += varstop - varstart;
6486 *s = '\0';
6487 mri_assemble (buf);
6488
6489 colon (n->top);
6490
6491 /* cmp end,var */
6492 s = buf;
6493 *s++ = 'c';
6494 *s++ = 'm';
6495 *s++ = 'p';
6496 if (qual != '\0')
6497 *s++ = tolower (qual);
6498 *s++ = ' ';
6499 memcpy (s, endstart, endstop - endstart);
6500 s += endstop - endstart;
6501 *s++ = ',';
6502 memcpy (s, varstart, varstop - varstart);
6503 s += varstop - varstart;
6504 *s = '\0';
6505 mri_assemble (buf);
6506
6507 /* bcc bottom */
6508 ex[0] = tolower (extent);
6509 ex[1] = '\0';
6510 if (up)
6511 sprintf (buf, "blt%s %s", ex, n->bottom);
6512 else
6513 sprintf (buf, "bgt%s %s", ex, n->bottom);
6514 mri_assemble (buf);
6515
6516 /* Put together the add or sub instruction used by ENDF. */
6517 s = buf;
6518 if (up)
6519 strcpy (s, "add");
6520 else
6521 strcpy (s, "sub");
6522 s += 3;
6523 if (qual != '\0')
6524 *s++ = tolower (qual);
6525 *s++ = ' ';
6526 memcpy (s, bystart, bystop - bystart);
6527 s += bystop - bystart;
6528 *s++ = ',';
6529 memcpy (s, varstart, varstop - varstart);
6530 s += varstop - varstart;
6531 *s = '\0';
6532 n->incr = buf;
6533
6534 if (flag_mri)
6535 {
6536 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6537 ++input_line_pointer;
6538 }
6539
6540 demand_empty_rest_of_line ();
6541 }
6542
6543 /* Handle the MRI ENDF pseudo-op. */
6544
6545 static void
6546 s_mri_endf (ignore)
6547 int ignore ATTRIBUTE_UNUSED;
6548 {
6549 if (mri_control_stack == NULL
6550 || mri_control_stack->type != mri_for)
6551 {
6552 as_bad (_("endf without for"));
6553 ignore_rest_of_line ();
6554 return;
6555 }
6556
6557 colon (mri_control_stack->next);
6558
6559 mri_assemble (mri_control_stack->incr);
6560
6561 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6562 mri_assemble (mri_control_stack->incr);
6563
6564 free (mri_control_stack->incr);
6565
6566 colon (mri_control_stack->bottom);
6567
6568 pop_mri_control ();
6569
6570 if (flag_mri)
6571 {
6572 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6573 ++input_line_pointer;
6574 }
6575
6576 demand_empty_rest_of_line ();
6577 }
6578
6579 /* Handle the MRI REPEAT pseudo-op. */
6580
6581 static void
6582 s_mri_repeat (ignore)
6583 int ignore ATTRIBUTE_UNUSED;
6584 {
6585 struct mri_control_info *n;
6586
6587 n = push_mri_control (mri_repeat);
6588 colon (n->top);
6589 if (flag_mri)
6590 {
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6592 ++input_line_pointer;
6593 }
6594 demand_empty_rest_of_line ();
6595 }
6596
6597 /* Handle the MRI UNTIL pseudo-op. */
6598
6599 static void
6600 s_mri_until (qual)
6601 int qual;
6602 {
6603 char *s;
6604
6605 if (mri_control_stack == NULL
6606 || mri_control_stack->type != mri_repeat)
6607 {
6608 as_bad (_("until without repeat"));
6609 ignore_rest_of_line ();
6610 return;
6611 }
6612
6613 colon (mri_control_stack->next);
6614
6615 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6616 ;
6617
6618 parse_mri_control_expression (s, qual, (const char *) NULL,
6619 mri_control_stack->top, '\0');
6620
6621 colon (mri_control_stack->bottom);
6622
6623 input_line_pointer = s;
6624
6625 pop_mri_control ();
6626
6627 if (flag_mri)
6628 {
6629 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6630 ++input_line_pointer;
6631 }
6632
6633 demand_empty_rest_of_line ();
6634 }
6635
6636 /* Handle the MRI WHILE pseudo-op. */
6637
6638 static void
6639 s_mri_while (qual)
6640 int qual;
6641 {
6642 char *s;
6643
6644 struct mri_control_info *n;
6645
6646 s = input_line_pointer;
6647 /* We only accept '*' as introduction of comments if preceded by white space
6648 or at first column of a line (I think this can't actually happen here?)
6649 This is important when assembling:
6650 while d0 <ne> 12(a0,d0*2) do
6651 while d0 <ne> #CONST*20 do */
6652 while ( ! ( is_end_of_line[(unsigned char) *s]
6653 || ( flag_mri
6654 && *s == '*'
6655 && ( s == input_line_pointer
6656 || *(s-1) == ' '
6657 || *(s-1) == '\t'))))
6658 s++;
6659 --s;
6660 while (*s == ' ' || *s == '\t')
6661 --s;
6662 if (s - input_line_pointer > 1
6663 && s[-1] == '.')
6664 s -= 2;
6665 if (s - input_line_pointer < 2
6666 || strncasecmp (s - 1, "DO", 2) != 0)
6667 {
6668 as_bad (_("missing do"));
6669 ignore_rest_of_line ();
6670 return;
6671 }
6672
6673 n = push_mri_control (mri_while);
6674
6675 colon (n->next);
6676
6677 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6678 s[1] == '.' ? s[2] : '\0');
6679
6680 input_line_pointer = s + 1;
6681 if (*input_line_pointer == '.')
6682 input_line_pointer += 2;
6683
6684 if (flag_mri)
6685 {
6686 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6687 ++input_line_pointer;
6688 }
6689
6690 demand_empty_rest_of_line ();
6691 }
6692
6693 /* Handle the MRI ENDW pseudo-op. */
6694
6695 static void
6696 s_mri_endw (ignore)
6697 int ignore ATTRIBUTE_UNUSED;
6698 {
6699 char *buf;
6700
6701 if (mri_control_stack == NULL
6702 || mri_control_stack->type != mri_while)
6703 {
6704 as_bad (_("endw without while"));
6705 ignore_rest_of_line ();
6706 return;
6707 }
6708
6709 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6710 sprintf (buf, "bra %s", mri_control_stack->next);
6711 mri_assemble (buf);
6712 free (buf);
6713
6714 colon (mri_control_stack->bottom);
6715
6716 pop_mri_control ();
6717
6718 if (flag_mri)
6719 {
6720 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6721 ++input_line_pointer;
6722 }
6723
6724 demand_empty_rest_of_line ();
6725 }
6726 \f
6727 /*
6728 * md_parse_option
6729 * Invocation line includes a switch not recognized by the base assembler.
6730 * See if it's a processor-specific option. These are:
6731 *
6732 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6733 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6734 * Select the architecture. Instructions or features not
6735 * supported by the selected architecture cause fatal
6736 * errors. More than one may be specified. The default is
6737 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6738 * for -m68000, and -m68882 is a synonym for -m68881.
6739 * -[A]m[c]no-68851, -[A]m[c]no-68881
6740 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6741 * so don't use or document it, but that's the way the parsing
6742 * works).
6743 *
6744 * -pic Indicates PIC.
6745 * -k Indicates PIC. (Sun 3 only.)
6746 * --pcrel Never turn PC-relative branches into absolute jumps.
6747 *
6748 * --bitwise-or
6749 * Permit `|' to be used in expressions.
6750 *
6751 */
6752
6753 #ifdef OBJ_ELF
6754 CONST char *md_shortopts = "lSA:m:kQ:V";
6755 #else
6756 CONST char *md_shortopts = "lSA:m:k";
6757 #endif
6758
6759 struct option md_longopts[] = {
6760 #define OPTION_PIC (OPTION_MD_BASE)
6761 {"pic", no_argument, NULL, OPTION_PIC},
6762 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6763 {"register-prefix-optional", no_argument, NULL,
6764 OPTION_REGISTER_PREFIX_OPTIONAL},
6765 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6766 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6767 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6768 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6769 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6770 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6771 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6772 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6773 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6774 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6775 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6776 {"pcrel", no_argument, NULL, OPTION_PCREL},
6777 {NULL, no_argument, NULL, 0}
6778 };
6779 size_t md_longopts_size = sizeof (md_longopts);
6780
6781 int
6782 md_parse_option (c, arg)
6783 int c;
6784 char *arg;
6785 {
6786 switch (c)
6787 {
6788 case 'l': /* -l means keep external to 2 bit offset
6789 rather than 16 bit one */
6790 flag_short_refs = 1;
6791 break;
6792
6793 case 'S': /* -S means that jbsr's always turn into
6794 jsr's. */
6795 flag_long_jumps = 1;
6796 break;
6797
6798 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6799 branches into absolute jumps. */
6800 flag_keep_pcrel = 1;
6801 break;
6802
6803 case 'A':
6804 if (*arg == 'm')
6805 arg++;
6806 /* intentional fall-through */
6807 case 'm':
6808
6809 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6810 {
6811 int i;
6812 unsigned long arch;
6813 const char *oarg = arg;
6814
6815 arg += 3;
6816 if (*arg == 'm')
6817 {
6818 arg++;
6819 if (arg[0] == 'c' && arg[1] == '6')
6820 arg++;
6821 }
6822 for (i = 0; i < n_archs; i++)
6823 if (!strcmp (arg, archs[i].name))
6824 break;
6825 if (i == n_archs)
6826 {
6827 unknown:
6828 as_bad (_("unrecognized option `%s'"), oarg);
6829 return 0;
6830 }
6831 arch = archs[i].arch;
6832 if (arch == m68881)
6833 no_68881 = 1;
6834 else if (arch == m68851)
6835 no_68851 = 1;
6836 else
6837 goto unknown;
6838 }
6839 else
6840 {
6841 int i;
6842
6843 if (arg[0] == 'c' && arg[1] == '6')
6844 arg++;
6845
6846 for (i = 0; i < n_archs; i++)
6847 if (!strcmp (arg, archs[i].name))
6848 {
6849 unsigned long arch = archs[i].arch;
6850 if (cpu_of_arch (arch))
6851 /* It's a cpu spec. */
6852 {
6853 current_architecture &= ~m68000up;
6854 current_architecture |= arch;
6855 }
6856 else if (arch == m68881)
6857 {
6858 current_architecture |= m68881;
6859 no_68881 = 0;
6860 }
6861 else if (arch == m68851)
6862 {
6863 current_architecture |= m68851;
6864 no_68851 = 0;
6865 }
6866 else
6867 /* ??? */
6868 abort ();
6869 break;
6870 }
6871 if (i == n_archs)
6872 {
6873 as_bad (_("unrecognized architecture specification `%s'"), arg);
6874 return 0;
6875 }
6876 }
6877 break;
6878
6879 case OPTION_PIC:
6880 case 'k':
6881 flag_want_pic = 1;
6882 break; /* -pic, Position Independent Code */
6883
6884 case OPTION_REGISTER_PREFIX_OPTIONAL:
6885 flag_reg_prefix_optional = 1;
6886 reg_prefix_optional_seen = 1;
6887 break;
6888
6889 /* -V: SVR4 argument to print version ID. */
6890 case 'V':
6891 print_version_id ();
6892 break;
6893
6894 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6895 should be emitted or not. FIXME: Not implemented. */
6896 case 'Q':
6897 break;
6898
6899 case OPTION_BITWISE_OR:
6900 {
6901 char *n, *t;
6902 const char *s;
6903
6904 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6905 t = n;
6906 for (s = m68k_comment_chars; *s != '\0'; s++)
6907 if (*s != '|')
6908 *t++ = *s;
6909 *t = '\0';
6910 m68k_comment_chars = n;
6911 }
6912 break;
6913
6914 case OPTION_BASE_SIZE_DEFAULT_16:
6915 m68k_index_width_default = SIZE_WORD;
6916 break;
6917
6918 case OPTION_BASE_SIZE_DEFAULT_32:
6919 m68k_index_width_default = SIZE_LONG;
6920 break;
6921
6922 case OPTION_DISP_SIZE_DEFAULT_16:
6923 m68k_rel32 = 0;
6924 m68k_rel32_from_cmdline = 1;
6925 break;
6926
6927 case OPTION_DISP_SIZE_DEFAULT_32:
6928 m68k_rel32 = 1;
6929 m68k_rel32_from_cmdline = 1;
6930 break;
6931
6932 default:
6933 return 0;
6934 }
6935
6936 return 1;
6937 }
6938
6939 void
6940 md_show_usage (stream)
6941 FILE *stream;
6942 {
6943 fprintf (stream, _("\
6944 680X0 options:\n\
6945 -l use 1 word for refs to undefined symbols [default 2]\n\
6946 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6947 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6948 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
6949 specify variant of 680X0 architecture [default 68020]\n\
6950 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6951 target has/lacks floating-point coprocessor\n\
6952 [default yes for 68020, 68030, and cpu32]\n"));
6953 fprintf (stream, _("\
6954 -m68851 | -mno-68851\n\
6955 target has/lacks memory-management unit coprocessor\n\
6956 [default yes for 68020 and up]\n\
6957 -pic, -k generate position independent code\n\
6958 -S turn jbsr into jsr\n\
6959 --pcrel never turn PC-relative branches into absolute jumps\n\
6960 --register-prefix-optional\n\
6961 recognize register names without prefix character\n\
6962 --bitwise-or do not treat `|' as a comment character\n"));
6963 fprintf (stream, _("\
6964 --base-size-default-16 base reg without size is 16 bits\n\
6965 --base-size-default-32 base reg without size is 32 bits (default)\n\
6966 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6967 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6968 }
6969 \f
6970 #ifdef TEST2
6971
6972 /* TEST2: Test md_assemble() */
6973 /* Warning, this routine probably doesn't work anymore */
6974
6975 main ()
6976 {
6977 struct m68k_it the_ins;
6978 char buf[120];
6979 char *cp;
6980 int n;
6981
6982 m68k_ip_begin ();
6983 for (;;)
6984 {
6985 if (!gets (buf) || !*buf)
6986 break;
6987 if (buf[0] == '|' || buf[1] == '.')
6988 continue;
6989 for (cp = buf; *cp; cp++)
6990 if (*cp == '\t')
6991 *cp = ' ';
6992 if (is_label (buf))
6993 continue;
6994 memset (&the_ins, '\0', sizeof (the_ins));
6995 m68k_ip (&the_ins, buf);
6996 if (the_ins.error)
6997 {
6998 printf (_("Error %s in %s\n"), the_ins.error, buf);
6999 }
7000 else
7001 {
7002 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7003 for (n = 0; n < the_ins.numo; n++)
7004 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7005 printf (" ");
7006 print_the_insn (&the_ins.opcode[0], stdout);
7007 (void) putchar ('\n');
7008 }
7009 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7010 {
7011 if (the_ins.operands[n].error)
7012 {
7013 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7014 continue;
7015 }
7016 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7017 if (the_ins.operands[n].b_const)
7018 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7019 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7020 if (the_ins.operands[n].b_iadd)
7021 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7022 (void) putchar ('\n');
7023 }
7024 }
7025 m68k_ip_end ();
7026 return 0;
7027 }
7028
7029 is_label (str)
7030 char *str;
7031 {
7032 while (*str == ' ')
7033 str++;
7034 while (*str && *str != ' ')
7035 str++;
7036 if (str[-1] == ':' || str[1] == '=')
7037 return 1;
7038 return 0;
7039 }
7040
7041 #endif
7042
7043 /* Possible states for relaxation:
7044
7045 0 0 branch offset byte (bra, etc)
7046 0 1 word
7047 0 2 long
7048
7049 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7050 1 1 word
7051 1 2 long
7052
7053 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7054 2 1 word-long
7055 2 2 long-word
7056 2 3 long-long
7057
7058 */
7059
7060 /* We have no need to default values of symbols. */
7061
7062 symbolS *
7063 md_undefined_symbol (name)
7064 char *name ATTRIBUTE_UNUSED;
7065 {
7066 return 0;
7067 }
7068
7069 /* Round up a section size to the appropriate boundary. */
7070 valueT
7071 md_section_align (segment, size)
7072 segT segment ATTRIBUTE_UNUSED;
7073 valueT size;
7074 {
7075 #ifdef OBJ_AOUT
7076 #ifdef BFD_ASSEMBLER
7077 /* For a.out, force the section size to be aligned. If we don't do
7078 this, BFD will align it for us, but it will not write out the
7079 final bytes of the section. This may be a bug in BFD, but it is
7080 easier to fix it here since that is how the other a.out targets
7081 work. */
7082 int align;
7083
7084 align = bfd_get_section_alignment (stdoutput, segment);
7085 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7086 #endif
7087 #endif
7088
7089 return size;
7090 }
7091
7092 /* Exactly what point is a PC-relative offset relative TO?
7093 On the 68k, it is relative to the address of the first extension
7094 word. The difference between the addresses of the offset and the
7095 first extension word is stored in fx_pcrel_adjust. */
7096 long
7097 md_pcrel_from (fixP)
7098 fixS *fixP;
7099 {
7100 int adjust;
7101
7102 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7103 sign extend the value here. */
7104 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7105 if (adjust == 64)
7106 adjust = -1;
7107 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7108 }
7109
7110 #ifndef BFD_ASSEMBLER
7111 #ifdef OBJ_COFF
7112
7113 void
7114 tc_coff_symbol_emit_hook (ignore)
7115 symbolS *ignore ATTRIBUTE_UNUSED;
7116 {
7117 }
7118
7119 int
7120 tc_coff_sizemachdep (frag)
7121 fragS *frag;
7122 {
7123 switch (frag->fr_subtype & 0x3)
7124 {
7125 case BYTE:
7126 return 1;
7127 case SHORT:
7128 return 2;
7129 case LONG:
7130 return 4;
7131 default:
7132 abort ();
7133 return 0;
7134 }
7135 }
7136
7137 #endif
7138 #endif
7139 #ifdef OBJ_ELF
7140 void m68k_elf_final_processing()
7141 {
7142 /* Set file-specific flags if this is a cpu32 processor */
7143 if (cpu_of_arch (current_architecture) & cpu32)
7144 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7145 }
7146 #endif
GDB Binutils - Deliverables
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