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relax_align is now static
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25
26 /* need TARGET_CPU */
27 #include "config.h"
28
29 #include "obstack.h"
30
31 /* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
33 #ifdef __GNUC__
34 #define DO_BREAK_UP_BIG_DECL
35 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
37 #endif
38
39 /* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
41 #include "opcode/m68k.h"
42
43 #ifndef BFD_ASSEMBLER
44 #ifdef TE_SUN
45 /* This variable contains the value to write out at the beginning of
46 the a.out file. The 2<<16 means that this is a 68020 file instead
47 of an old-style 68000 file */
48
49 long omagic = 2 << 16 | OMAGIC; /* Magic byte for header file */
50 #else
51 long omagic = OMAGIC;
52 #endif
53 #endif
54
55 /* This array holds the chars that always start a comment. If the
56 pre-processor is disabled, these aren't very useful */
57 CONST char comment_chars[] = "|";
58
59 /* This array holds the chars that only start a comment at the beginning of
60 a line. If the line seems to have the form '# 123 filename'
61 .line and .file directives will appear in the pre-processed output */
62 /* Note that input_file.c hand checks for '#' at the beginning of the
63 first line of the input file. This is because the compiler outputs
64 #NO_APP at the beginning of its output. */
65 /* Also note that comments like this one will always work. */
66 CONST char line_comment_chars[] = "#";
67
68 CONST char line_separator_chars[] = "";
69
70 /* Chars that can be used to separate mant from exp in floating point nums */
71 CONST char EXP_CHARS[] = "eE";
72
73 /* Chars that mean this number is a floating point constant, as
74 in "0f12.456" or "0d1.2345e12". */
75
76 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
77
78 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
79 changed in read.c . Ideally it shouldn't have to know about it at all,
80 but nothing is ideal around here. */
81
82 const int md_reloc_size = 8; /* Size of relocation record */
83
84 /* Its an arbitrary name: This means I don't approve of it */
85 /* See flames below */
86 static struct obstack robyn;
87
88 #define TAB(x,y) (((x)<<2)+(y))
89 #define TABTYPE(xy) ((xy) >> 2)
90 #define BYTE 0
91 #define SHORT 1
92 #define LONG 2
93 #define SZ_UNDEF 3
94 #undef BRANCH
95 #define ABRANCH 1
96 #define FBRANCH 2
97 #define PCREL 3
98 #define BCC68000 4
99 #define DBCC 5
100 #define PCLEA 6
101
102 /* Operands we can parse: (And associated modes)
103
104 numb: 8 bit num
105 numw: 16 bit num
106 numl: 32 bit num
107 dreg: data reg 0-7
108 reg: address or data register
109 areg: address register
110 apc: address register, PC, ZPC or empty string
111 num: 16 or 32 bit num
112 num2: like num
113 sz: w or l if omitted, l assumed
114 scale: 1 2 4 or 8 if omitted, 1 assumed
115
116 7.4 IMMED #num --> NUM
117 0.? DREG dreg --> dreg
118 1.? AREG areg --> areg
119 2.? AINDR areg@ --> *(areg)
120 3.? AINC areg@+ --> *(areg++)
121 4.? ADEC areg@- --> *(--areg)
122 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
123 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
124 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
125 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
126 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
127 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
128 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
129 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
130 7.0 ABSL num:sz --> *(num)
131 num --> *(num) (sz L assumed)
132 *** MSCR otherreg --> Magic
133 With -l option
134 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
135 ?.? DINDR dreg@ --> (dreg) -- cas2 only
136
137 examples:
138 #foo #0x35 #12
139 d2
140 a4
141 a3@
142 a5@+
143 a6@-
144 a2@(12) pc@(14)
145 a1@(5,d2:w:1) @(45,d6:l:4)
146 pc@(a2) @(d4)
147 etc . . .
148
149
150 #name@(numw) -->turn into PC rel mode
151 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
152
153 */
154
155 enum operand_type
156 {
157 IMMED = 1,
158 DREG,
159 AREG,
160 AINDR,
161 ADEC,
162 AINC,
163 AOFF,
164 AINDX,
165 APODX,
166 AMIND,
167 APRDX,
168 ABSL,
169 MSCR,
170 REGLST,
171 DINDR
172 };
173
174
175 struct m68k_exp
176 {
177 char *e_beg;
178 char *e_end;
179 expressionS e_exp;
180 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
181 };
182
183 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
184 8-15==addr reg for operands that take both types */
185
186 enum _register
187 {
188 DATA = 1, /* 1- 8 == data registers 0-7 */
189 DATA0 = DATA,
190 DATA1,
191 DATA2,
192 DATA3,
193 DATA4,
194 DATA5,
195 DATA6,
196 DATA7,
197
198 ADDR,
199 ADDR0 = ADDR,
200 ADDR1,
201 ADDR2,
202 ADDR3,
203 ADDR4,
204 ADDR5,
205 ADDR6,
206 ADDR7,
207
208 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
209 /* I think. . . */
210
211 SP = ADDR7,
212
213 FPREG, /* Eight FP registers */
214 FP0 = FPREG,
215 FP1,
216 FP2,
217 FP3,
218 FP4,
219 FP5,
220 FP6,
221 FP7,
222 COPNUM = (FPREG + 8), /* Co-processor #1-#8 */
223 COP0 = COPNUM,
224 COP1,
225 COP2,
226 COP3,
227 COP4,
228 COP5,
229 COP6,
230 COP7,
231 PC, /* Program counter */
232 ZPC, /* Hack for Program space, but 0 addressing */
233 SR, /* Status Reg */
234 CCR, /* Condition code Reg */
235
236 /* These have to be in order for the movec instruction to work. */
237 USP, /* User Stack Pointer */
238 ISP, /* Interrupt stack pointer */
239 SFC,
240 DFC,
241 CACR,
242 VBR,
243 CAAR,
244 MSP,
245 ITT0,
246 ITT1,
247 DTT0,
248 DTT1,
249 MMUSR,
250 TC,
251 SRP,
252 URP,
253 /* end of movec ordering constraints */
254
255 FPI,
256 FPS,
257 FPC,
258
259 DRP, /* 68851 or 68030 MMU regs */
260 CRP,
261 CAL,
262 VAL,
263 SCC,
264 AC,
265 BAD,
266 BAD0 = BAD,
267 BAD1,
268 BAD2,
269 BAD3,
270 BAD4,
271 BAD5,
272 BAD6,
273 BAD7,
274 BAC,
275 BAC0 = BAC,
276 BAC1,
277 BAC2,
278 BAC3,
279 BAC4,
280 BAC5,
281 BAC6,
282 BAC7,
283 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
284 and ACUSR on 68ec030 */
285 PCSR,
286
287 IC, /* instruction cache token */
288 DC, /* data cache token */
289 NC, /* no cache token */
290 BC, /* both caches token */
291
292 TT0, /* 68030 access control unit regs */
293 TT1,
294 };
295
296 /* Internal form of an operand. */
297 struct m68k_op
298 {
299 char *error; /* Couldn't parse it */
300 enum operand_type mode; /* What mode this instruction is in. */
301 enum _register reg; /* Base register */
302 struct m68k_exp *con1;
303 int ireg; /* Index register */
304 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
305 int imul; /* Multipy ireg by this (1,2,4,or 8) */
306 struct m68k_exp *con2;
307 };
308
309 /* internal form of a 68020 instruction */
310 struct m68k_it
311 {
312 char *error;
313 char *args; /* list of opcode info */
314 int numargs;
315
316 int numo; /* Number of shorts in opcode */
317 short opcode[11];
318
319 struct m68k_op operands[6];
320
321 int nexp; /* number of exprs in use */
322 struct m68k_exp exprs[4];
323
324 int nfrag; /* Number of frags we have to produce */
325 struct
326 {
327 int fragoff; /* Where in the current opcode[] the frag ends */
328 symbolS *fadd;
329 long foff;
330 int fragty;
331 }
332 fragb[4];
333
334 int nrel; /* Num of reloc strucs in use */
335 struct
336 {
337 int n;
338 symbolS *add, *sub;
339 long off;
340 char wid;
341 char pcrel;
342 }
343 reloc[5]; /* Five is enough??? */
344 };
345
346 #define cpu_of_arch(x) ((x) & m68000up)
347 #define float_of_arch(x) ((x) & mfloat)
348 #define mmu_of_arch(x) ((x) & mmmu)
349
350 static struct m68k_it the_ins; /* the instruction being assembled */
351
352 #define seg(exp) ((exp)->e_exp.X_seg)
353 #define adds(exp) ((exp)->e_exp.X_add_symbol)
354 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
355 #define offs(exp) ((exp)->e_exp.X_add_number)
356
357 /* Macros for adding things to the m68k_it struct */
358
359 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
360
361 /* Like addword, but goes BEFORE general operands */
362 #define insop(w) {int z;\
363 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
364 the_ins.opcode[z]=the_ins.opcode[z-1];\
365 for(z=0;z<the_ins.nrel;z++)\
366 the_ins.reloc[z].n+=2;\
367 the_ins.opcode[opcode->m_codenum]=w;\
368 the_ins.numo++;\
369 }
370
371
372 #define add_exp(beg,end) (\
373 the_ins.exprs[the_ins.nexp].e_beg=beg,\
374 the_ins.exprs[the_ins.nexp].e_end=end,\
375 &the_ins.exprs[the_ins.nexp++]\
376 )
377
378
379 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
380 Blecch. */
381 static void
382 add_fix (width, exp, pc_rel)
383 char width;
384 struct m68k_exp *exp;
385 int pc_rel;
386 {
387 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
388 ? (the_ins.numo*2-1)
389 : (((width)=='b')
390 ? ((the_ins.numo-1)*2)
391 : (the_ins.numo*2)));
392 the_ins.reloc[the_ins.nrel].add = adds((exp));
393 the_ins.reloc[the_ins.nrel].sub = subs((exp));
394 the_ins.reloc[the_ins.nrel].off = offs((exp));
395 the_ins.reloc[the_ins.nrel].wid = width;
396 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
397 }
398
399 static void
400 add_frag(add,off,type)
401 symbolS *add;
402 long off;
403 int type;
404 {
405 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
406 the_ins.fragb[the_ins.nfrag].fadd=add;
407 the_ins.fragb[the_ins.nfrag].foff=off;
408 the_ins.fragb[the_ins.nfrag++].fragty=type;
409 }
410
411 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
412
413 struct m68k_incant
414 {
415 char *m_operands;
416 unsigned long m_opcode;
417 short m_opnum;
418 short m_codenum;
419 int m_arch;
420 struct m68k_incant *m_next;
421 };
422
423
424
425 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
426 #define gettwo(x) (((x)->m_opcode)&0xffff)
427
428
429 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
430 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
431 static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP));
432 static int reverse_16_bits PARAMS ((int in));
433 static int reverse_8_bits PARAMS ((int in));
434 static int try_index PARAMS ((char **s, struct m68k_op *opP));
435 static void install_gen_operand PARAMS ((int mode, int val));
436 static void install_operand PARAMS ((int mode, int val));
437 static void s_bss PARAMS ((void));
438 static void s_data1 PARAMS ((void));
439 static void s_data2 PARAMS ((void));
440 static void s_even PARAMS ((void));
441 static void s_proc PARAMS ((void));
442
443 static int current_architecture;
444
445 /* BCC68000 is for patching in an extra jmp instruction for long offsets
446 on the 68000. The 68000 doesn't support long branches with branchs */
447
448 /* This table desribes how you change sizes for the various types of variable
449 size expressions. This version only supports two kinds. */
450
451 /* Note that calls to frag_var need to specify the maximum expansion
452 needed; this is currently 10 bytes for DBCC. */
453
454 /* The fields are:
455 How far Forward this mode will reach:
456 How far Backward this mode will reach:
457 How many bytes this mode will add to the size of the frag
458 Which mode to go to if the offset won't fit in this one
459 */
460 CONST relax_typeS md_relax_table[] =
461 {
462 {1, 1, 0, 0}, /* First entries aren't used */
463 {1, 1, 0, 0}, /* For no good reason except */
464 {1, 1, 0, 0}, /* that the VAX doesn't either */
465 {1, 1, 0, 0},
466
467 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
468 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
469 {0, 0, 4, 0},
470 {1, 1, 0, 0},
471
472 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
473 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
474 {0, 0, 4, 0},
475 {1, 1, 0, 0},
476
477 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
478 {(32767), (-32768), 2, TAB (PCREL, LONG)},
479 {0, 0, 4, 0},
480 {1, 1, 0, 0},
481
482 {(127), (-128), 0, TAB (BCC68000, SHORT)},
483 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
484 {0, 0, 6, 0}, /* jmp long space */
485 {1, 1, 0, 0},
486
487 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
488 {(32767), (-32768), 2, TAB (DBCC, LONG)},
489 {0, 0, 10, 0}, /* bra/jmp long space */
490 {1, 1, 0, 0},
491
492 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
493 {32767, -32768, 2, TAB (PCLEA, LONG)},
494 {0, 0, 6, 0},
495 {1, 1, 0, 0},
496
497 };
498
499 /* These are the machine dependent pseudo-ops. These are included so
500 the assembler can work on the output from the SUN C compiler, which
501 generates these.
502 */
503
504 /* This table describes all the machine specific pseudo-ops the assembler
505 has to support. The fields are:
506 pseudo-op name without dot
507 function to call to execute this pseudo-op
508 Integer arg to pass to the function
509 */
510 CONST pseudo_typeS md_pseudo_table[] =
511 {
512 {"data1", s_data1, 0},
513 {"data2", s_data2, 0},
514 {"bss", s_bss, 0},
515 {"even", s_even, 0},
516 {"skip", s_space, 0},
517 {"proc", s_proc, 0},
518 #ifdef TE_SUN3
519 {"align", s_align_bytes, 0},
520 #endif
521 {0, 0, 0}
522 };
523
524
525 /* The mote pseudo ops are put into the opcode table, since they
526 don't start with a . they look like opcodes to gas.
527 */
528 extern void obj_coff_section ();
529
530 CONST pseudo_typeS mote_pseudo_table[] =
531 {
532
533 {"dc.l", cons, 4},
534 {"dc", cons, 2},
535 {"dc.w", cons, 2},
536 {"dc.b", cons, 1},
537
538 {"ds.l", s_space, 4},
539 {"ds", s_space, 2},
540 {"ds.w", s_space, 2},
541 {"ds.b", s_space, 1},
542
543 {"xdef", s_globl, 0},
544 {"align", s_align_ptwo, 0},
545 #ifdef M68KCOFF
546 {"sect", obj_coff_section, 0},
547 {"section", obj_coff_section, 0},
548 #endif
549 0,
550 };
551
552 #define issbyte(x) ((x)>=-128 && (x)<=127)
553 #define isubyte(x) ((x)>=0 && (x)<=255)
554 #define issword(x) ((x)>=-32768 && (x)<=32767)
555 #define isuword(x) ((x)>=0 && (x)<=65535)
556
557 #define isbyte(x) ((x)>= -255 && (x)<=255)
558 #define isword(x) ((x)>=-32768 && (x)<=65535)
559 #define islong(x) (1)
560
561 extern char *input_line_pointer;
562
563 enum
564 {
565 FAIL = 0,
566 OK = 1,
567 };
568
569 /* JF these tables here are for speed at the expense of size */
570 /* You can replace them with the #if 0 versions if you really
571 need space and don't mind it running a bit slower */
572
573 static char mklower_table[256];
574 #define mklower(c) (mklower_table[(unsigned char)(c)])
575 static char notend_table[256];
576 static char alt_notend_table[256];
577 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
578 alt_notend_table[(unsigned char)(s[1])])))
579
580 #if 0
581 #define mklower(c) (isupper(c) ? tolower(c) : c)
582 #endif
583
584
585 /* JF modified this to handle cases where the first part of a symbol name
586 looks like a register */
587
588 /*
589 * m68k_reg_parse() := if it looks like a register, return it's token &
590 * advance the pointer.
591 */
592
593 enum _register
594 m68k_reg_parse (ccp)
595 register char **ccp;
596 {
597 char *start = *ccp;
598 char c;
599 char *p;
600 symbolS *symbolP;
601
602 #ifdef REGISTER_PREFIX
603 if (*start != REGISTER_PREFIX)
604 return FAIL;
605 p = start + 1;
606 #else
607 p = start;
608 if (*p == OPTIONAL_REGISTER_PREFIX)
609 p++, start++;
610 #endif
611 if (!isalpha (*p) || !is_name_beginner (*p))
612 return FAIL;
613
614 c = *p++;
615 while (isalpha (c) || isdigit (c) || c == '_')
616 {
617 c = *p++;
618 }
619
620 *--p = 0;
621 symbolP = symbol_find (start);
622 *p = c;
623
624 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
625 {
626 *ccp = p;
627 return S_GET_VALUE (symbolP);
628 }
629
630 return FAIL;
631 }
632
633 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
634 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
635
636 /* Parse an index specification using Motorola syntax. */
637
638 static int
639 try_moto_index (s, opP)
640 char **s;
641 struct m68k_op *opP;
642 {
643 register int i;
644 char *ss;
645
646 ss = *s;
647 /* SKIP_W(); */
648 if (*ss == ' ')
649 ss++;
650 i = m68k_reg_parse (&ss);
651 if (!(i >= DATA + 0 && i <= ADDR + 7))
652 { /* if i is not DATA or ADDR reg */
653 opP->error = "Invalid index register";
654 *s = ss;
655 return FAIL;
656 }
657 opP->ireg = i;
658 /* SKIP_W(); */
659 if (*ss == ')')
660 {
661 opP->isiz = 0;
662 opP->imul = 1;
663 SKIP_W ();
664 *s = ss;
665 return OK;
666 }
667 if (*ss != '.')
668 {
669 opP->error = "Missing . in index register";
670 *s = ss;
671 return FAIL;
672 }
673 SKIP_W ();
674 if (mklower (*ss) == 'w')
675 opP->isiz = 2;
676 else if (mklower (*ss) == 'l')
677 opP->isiz = 3;
678 else
679 {
680 opP->error = "Size spec not .W or .L";
681 *s = ss;
682 return FAIL;
683 }
684 SKIP_W ();
685 if (*ss == '.' || *ss == '*')
686 {
687 SKIP_W ();
688 switch (*ss)
689 {
690 case '1':
691 case '2':
692 case '4':
693 case '8':
694 opP->imul = *ss - '0';
695 break;
696 default:
697 opP->error = "index multiplier not 1, 2, 4 or 8";
698 *s = ss;
699 return FAIL;
700 }
701 SKIP_W ();
702 }
703 else
704 opP->imul = 1;
705 if (*ss != ')')
706 {
707 opP->error = "Missing )";
708 *s = ss;
709 return FAIL;
710 }
711 SKIP_W ();
712 *s = ss;
713 return OK;
714 }
715
716 /*
717 *
718 * try_index := data_or_address_register + ')' + SKIP_W
719 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
720 *
721 * multiplier := <empty>
722 * | ':' + multiplier_number
723 * ;
724 *
725 * multiplier_number := '1' | '2' | '4' | '8' ;
726 *
727 * size_spec := 'l' | 'L' | 'w' | 'W' ;
728 *
729 * SKIP_W := <empty> | ' ' ;
730 *
731 */
732
733 static int
734 try_index (s, opP)
735 char **s;
736 struct m68k_op *opP;
737 {
738 register int i;
739 char *ss;
740
741 ss = *s;
742 /* SKIP_W(); */
743 i = m68k_reg_parse (&ss);
744 if (!(i >= DATA + 0 && i <= ADDR + 7))
745 { /* if i is not DATA or ADDR reg */
746 *s = ss;
747 return FAIL;
748 }
749 opP->ireg = i;
750 /* SKIP_W(); */
751 if (*ss == ')')
752 {
753 opP->isiz = 0;
754 opP->imul = 1;
755 SKIP_W ();
756 *s = ss;
757 return OK;
758 }
759 if (*ss != ':')
760 {
761 opP->error = "Missing : in index register";
762 *s = ss;
763 return FAIL;
764 }
765 SKIP_W ();
766 switch (*ss)
767 {
768 case 'w':
769 case 'W':
770 opP->isiz = 2;
771 break;
772 case 'l':
773 case 'L':
774 opP->isiz = 3;
775 break;
776 default:
777 opP->error = "Index register size spec not :w or :l";
778 *s = ss;
779 return FAIL;
780 }
781 SKIP_W ();
782 if (*ss == ':')
783 {
784 SKIP_W ();
785 switch (*ss)
786 {
787 case '1':
788 case '2':
789 case '4':
790 case '8':
791 if (cpu_of_arch (current_architecture) < m68020)
792 {
793 opP->error = "no index scaling in pre-68020's";
794 *s = ss;
795 return FAIL;
796 }
797 opP->imul = *ss - '0';
798 break;
799 default:
800 opP->error = "index multiplier not 1, 2, 4 or 8";
801 *s = ss;
802 return FAIL;
803 }
804 SKIP_W ();
805 }
806 else
807 opP->imul = 1;
808 if (*ss != ')')
809 {
810 opP->error = "Missing )";
811 *s = ss;
812 return FAIL;
813 }
814 SKIP_W ();
815 *s = ss;
816 return OK;
817 } /* try_index() */
818
819 /* Ian Taylor expanded this function to accept both MIT and Motorola
820 syntax. I removed the old comment, since it was wrong. The syntax
821 this accepted even before my changes was complex and undocumented.
822 I mainly added a large case when the operand string does not
823 contain an '@', since the Motorola syntax does not use the '@'
824 character. */
825
826 int
827 m68k_ip_op (str, opP)
828 char *str;
829 register struct m68k_op *opP;
830 {
831 char *strend;
832 long i;
833 char *parse_index ();
834 int needp;
835
836 if (*str == ' ')
837 {
838 str++;
839 } /* Find the beginning of the string */
840
841 if (!*str)
842 {
843 opP->error = "Missing operand";
844 return FAIL;
845 } /* Out of gas */
846
847 for (strend = str; *strend; strend++)
848 ;
849 --strend;
850
851 if (*str == '#')
852 {
853 str++;
854 opP->con1 = add_exp (str, strend);
855 opP->mode = IMMED;
856 return OK;
857 } /* Guess what: A constant. Shar and enjoy */
858
859 i = m68k_reg_parse (&str);
860
861 if (i != FAIL)
862 {
863 if (*str == '/' || *str == '-')
864 {
865 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
866 opP->mode = REGLST;
867 return get_regs (i, str, opP);
868 }
869 if (*str == '\0')
870 {
871 opP->reg = i;
872 /* "Rn" Register Direct mode */
873 if (i >= DATA + 0 && i <= DATA + 7)
874 opP->mode = DREG;
875 else if (i >= ADDR + 0 && i <= ADDR + 7)
876 opP->mode = AREG;
877 else
878 opP->mode = MSCR;
879 return OK;
880 }
881 }
882
883 if (*str != '@')
884 {
885 char *stmp;
886
887 if ((stmp = strchr (str, '@')) != 0)
888 {
889 opP->con1 = add_exp (str, stmp - 1);
890 if (stmp == strend)
891 {
892 opP->mode = AINDX;
893 return (OK);
894 }
895
896 if ((current_architecture & m68020up) == 0)
897 {
898 return (FAIL);
899 } /* if target is not a '20 or better */
900
901 stmp++;
902 if (*stmp++ != '(' || *strend-- != ')')
903 {
904 opP->error = "Malformed operand";
905 return (FAIL);
906 }
907 i = try_index (&stmp, opP);
908 opP->con2 = add_exp (stmp, strend);
909
910 if (i == FAIL)
911 {
912 opP->mode = AMIND;
913 }
914 else
915 {
916 opP->mode = APODX;
917 }
918 return (OK);
919 } /* if there's an '@' */
920
921 #ifndef MIT_SYNTAX_ONLY
922 /* The operand has no '@'. Try to parse it using
923 Motorola syntax. */
924 /* Logic of the parsing switch(*str):
925 case opP->mode =
926 ---- -----------
927 #anything IMMED 1
928 REG AREG or DREG or MSCR 3 or 2 or 13
929 REG- or REG/ REGLST 14
930 (REG) AINDR 4
931 (REG)+ AINC 6
932 (REG,INDX) AINDX 8
933 (EXPR,REG) AOFF 7
934 (EXPR,REG,INDX) AINDX 8
935 -(REG) ADEC 5
936 EXP2(REG) AOFF 7
937 EXP2(REG,INDX) AINDX 8
938 EXP2 ABSL 12
939
940 REG means truth(m68k_reg_parse(&str))
941 INDX means truth(try_moto_index(&str,opP))
942 EXPR means not REG
943 EXP2 means not REG and not '(' and not '-('
944 */
945
946 if (*str == '(')
947 {
948 str++;
949 i = m68k_reg_parse (&str);
950 if ((i < ADDR + 0 || i > ADDR + 7)
951 && (i < DATA + 0 || i > DATA + 7
952 || *str != ')' || str[1] != '0')
953 && i != PC && i != ZPC && i != FAIL)
954 {
955 /* Can't indirect off non address regs */
956 opP->error = "Invalid indirect register";
957 return FAIL;
958 }
959 if (i != FAIL)
960 {
961 opP->reg = i;
962 if (*str == ')')
963 {
964 str++;
965 if (*str == '\0')
966 {
967 /* "(An)" Address Register Indirect mode
968 or "(Dn)" for cas2. */
969 if (i >= DATA + 0 && i <= DATA + 7)
970 opP->mode = DINDR;
971 else
972 opP->mode = AINDR;
973 return OK;
974 }
975 if (*str == '+')
976 {
977 if (str[1] == '\0')
978 {
979 /* "(An)+" Register Indirect w Postincrement */
980 opP->mode = AINC;
981 return OK;
982 }
983 }
984 opP->error = "Junk after indirect";
985 return FAIL;
986 }
987 if (*str == ',')
988 {
989 str++;
990 i = try_moto_index (&str, opP);
991 if (i == FAIL)
992 return FAIL;
993 /* "(An,Rn)" Register Indirect with Index mode*/
994 opP->mode = AINDX;
995 return OK;
996 }
997 else
998 {
999 opP->error = "Bad indirect syntax";
1000 return FAIL;
1001 }
1002 }
1003 else
1004 {
1005 /* "(EXPR,..." , a displacement */
1006 char *stmp;
1007 char *index ();
1008
1009 if (stmp = index (str, ','))
1010 {
1011 opP->con1 = add_exp (str, stmp - 1);
1012 str = stmp;
1013 SKIP_WHITE ();
1014 i = m68k_reg_parse (&str);
1015 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1016 {
1017 /* Can't indirect off non address regs */
1018 opP->error = "Invalid indirect register";
1019 return FAIL;
1020 }
1021 if (i != FAIL)
1022 {
1023 opP->reg = i;
1024 if (*str == ')')
1025 {
1026 /* "(d,An)" Register Indirect w Displacement */
1027 opP->mode = AOFF;
1028 return OK;
1029 }
1030 if (*str == ',')
1031 {
1032 str++;
1033 i = try_moto_index (&str, opP);
1034 if (i == FAIL)
1035 return FAIL;
1036 /* "(d,An,Rn)" Register Indirect with Index */
1037 opP->mode = AINDX;
1038 return OK;
1039 }
1040 else
1041 {
1042 opP->error = "Bad indirect syntax";
1043 return FAIL;
1044 }
1045 }
1046 else
1047 {
1048 opP->error = "Invalid register";
1049 return FAIL;
1050 }
1051 }
1052 else
1053 {
1054 opP->mode = ABSL;
1055 opP->con1 = add_exp (str - 1, strend);
1056 return OK;
1057 }
1058 }
1059 }
1060
1061 if (*str == '-')
1062 {
1063 if (str[1] == '(')
1064 {
1065 str = str + 2;
1066 i = m68k_reg_parse (&str);
1067 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1068 {
1069 /* Can't indirect off non address regs */
1070 opP->error = "Invalid indirect register";
1071 return FAIL;
1072 }
1073 if (i != FAIL)
1074 {
1075 opP->reg = i;
1076 if (*str == ')')
1077 {
1078 str++;
1079 if (*str == '\0')
1080 {
1081 /* "-(An)" Register Indirect with Predecrement */
1082 opP->mode = ADEC;
1083 return OK;
1084 }
1085 opP->error = "Junk after indirect";
1086 return FAIL;
1087 }
1088 opP->error = "Bad indirect syntax";
1089 return FAIL;
1090 }
1091 opP->mode = ABSL;
1092 opP->con1 = add_exp (str - 2, strend);
1093 return OK;
1094 }
1095 /* if '-' but not "-(', do nothing */
1096 }
1097
1098 /* whether *str=='-' or not */
1099 {
1100 /* "EXP2" or "EXP2(REG..." */
1101 char *stmp;
1102 char *index ();
1103 if (stmp = index (str, '('))
1104 {
1105 char *ostr = str;
1106
1107 opP->con1 = add_exp (str, stmp - 1);
1108 str = stmp + 1;
1109 i = m68k_reg_parse (&str);
1110 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1111 && i != ZPC && i != FAIL)
1112 {
1113 /* Can't indirect off non address regs */
1114 opP->error = "Invalid indirect register";
1115 return FAIL;
1116 }
1117 if (i != FAIL)
1118 {
1119 opP->reg = i;
1120 if (*str == ')')
1121 {
1122 /* "d(An)" Register Indirect w Displacement */
1123 opP->mode = AOFF;
1124 return OK;
1125 }
1126 if (*str == ',')
1127 {
1128 str++;
1129 i = try_moto_index (&str, opP);
1130 if (i == FAIL)
1131 return FAIL;
1132 /* "d(An,Rn)" Register Indirect with Index */
1133 opP->mode = AINDX;
1134 return OK;
1135 }
1136 else
1137 {
1138 opP->error = "Bad indirect syntax";
1139 return FAIL;
1140 }
1141 }
1142 else
1143 {
1144 opP->mode = ABSL;
1145 opP->con1 = add_exp (ostr, strend);
1146 return OK;
1147 }
1148 }
1149 else
1150 {
1151 /* "EXP2" Absolute */
1152 opP->mode = ABSL;
1153 opP->isiz = 0;
1154 if (strend[-1] == '.' || strend[-1] == ':')
1155 {
1156 /* mode ==foo.[wl] */
1157 switch (*strend)
1158 {
1159 case 'w':
1160 case 'W':
1161 opP->isiz = 2;
1162 break;
1163 case 'l':
1164 case 'L':
1165 opP->isiz = 3;
1166 break;
1167 }
1168 }
1169 opP->con1 = add_exp (str, strend);
1170 return OK;
1171 }
1172 }
1173 /*NOTREACHED*/
1174 #else /* defined (MIT_SYNTAX_ONLY) */
1175 opP->mode = ABSL;
1176 opP->con1 = add_exp (str, strend);
1177 return OK;
1178 #endif /* defined (MIT_SYNTAX_ONLY) */
1179 }
1180
1181 opP->reg = i;
1182
1183 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1184 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1185 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1186 {
1187 opP->error = "Invalid indirect register";
1188 return FAIL;
1189 }
1190 know (*str == '@');
1191
1192 str++;
1193 switch (*str)
1194 {
1195 case '\0':
1196 if (i < DATA + 0 || i > DATA + 7)
1197 opP->mode = AINDR;
1198 else
1199 opP->mode = DINDR;
1200 return OK;
1201 case '-':
1202 opP->mode = ADEC;
1203 return OK;
1204 case '+':
1205 opP->mode = AINC;
1206 return OK;
1207 case '(':
1208 str++;
1209 break;
1210 default:
1211 opP->error = "Junk after indirect";
1212 return FAIL;
1213 }
1214 /* Some kind of indexing involved. Lets find out how bad it is */
1215 i = try_index (&str, opP);
1216 /* Didn't start with an index reg, maybe its offset or offset,reg */
1217 if (i == FAIL)
1218 {
1219 char *beg_str;
1220
1221 beg_str = str;
1222 for (i = 1; i;)
1223 {
1224 switch (*str++)
1225 {
1226 case '\0':
1227 opP->error = "Missing )";
1228 return FAIL;
1229 case ',':
1230 i = 0;
1231 break;
1232 case '(':
1233 i++;
1234 break;
1235 case ')':
1236 --i;
1237 break;
1238 }
1239 }
1240 #if 0
1241 if (str[-3]==':')
1242 {
1243 int siz;
1244
1245 switch (str[-2])
1246 {
1247 case 'b':
1248 case 'B':
1249 siz=1;
1250 break;
1251 case 'w':
1252 case 'W':
1253 siz=2;
1254 break;
1255 case 'l':
1256 case 'L':
1257 siz=3;
1258 break;
1259 default:
1260 opP->error="Specified size isn't :w or :l";
1261 return FAIL;
1262 }
1263 opP->con1=add_exp(beg_str,str-4);
1264 opP->con1->e_siz=siz;
1265 }
1266 else
1267 #endif
1268 opP->con1 = add_exp (beg_str, str - 2);
1269 /* Should be offset,reg */
1270 if (str[-1] == ',')
1271 {
1272 i = try_index (&str, opP);
1273 if (i == FAIL)
1274 {
1275 opP->error = "Malformed index reg";
1276 return FAIL;
1277 }
1278 }
1279 }
1280 /* We've now got offset) offset,reg) or reg) */
1281
1282 if (*str == '\0')
1283 {
1284 /* Th-the-thats all folks */
1285 if (opP->reg == FAIL)
1286 opP->mode = AINDX; /* Other form of indirect */
1287 else if (opP->ireg == FAIL)
1288 opP->mode = AOFF;
1289 else
1290 opP->mode = AINDX;
1291 return (OK);
1292 }
1293 /* Next thing had better be another @ */
1294 if (*str == '@')
1295 {
1296 if (str[1] == '(')
1297 {
1298 needp = 1;
1299 str += 2;
1300 }
1301 else
1302 {
1303 needp = 0;
1304 str++;
1305 }
1306 }
1307
1308 if ((current_architecture & m68020up) == 0)
1309 {
1310 return (FAIL);
1311 } /* if target is not a '20 or better */
1312
1313
1314 if (opP->ireg != FAIL)
1315 {
1316 opP->mode = APRDX;
1317
1318 i = try_index (&str, opP);
1319 if (i != FAIL)
1320 {
1321 opP->error = "Two index registers! not allowed!";
1322 return (FAIL);
1323 }
1324 }
1325 else
1326 {
1327 i = try_index (&str, opP);
1328 }
1329
1330 if (i == FAIL)
1331 {
1332 char *beg_str;
1333
1334 beg_str = str;
1335
1336 for (i = 1; i;)
1337 {
1338 switch (*str++)
1339 {
1340 case '\0':
1341 if (needp)
1342 opP->error = "Missing )";
1343 return (FAIL);
1344 break;
1345 case ',':
1346 i = 0;
1347 break;
1348 case '(':
1349 i++;
1350 break;
1351 case ')':
1352 --i;
1353 break;
1354 }
1355 }
1356
1357 opP->con2 = add_exp (beg_str, str - 2);
1358
1359 if (str[-1] == ',')
1360 {
1361 if (opP->ireg != FAIL)
1362 {
1363 opP->error = "Can't have two index regs";
1364 return (FAIL);
1365 }
1366
1367 i = try_index (&str, opP);
1368
1369 if (i == FAIL)
1370 {
1371 opP->error = "malformed index reg";
1372 return (FAIL);
1373 }
1374
1375 opP->mode = APODX;
1376 }
1377 else if (opP->ireg != FAIL)
1378 {
1379 opP->mode = APRDX;
1380 }
1381 else
1382 {
1383 opP->mode = AMIND;
1384 }
1385 }
1386 else
1387 {
1388 opP->mode = APODX;
1389 }
1390
1391 if (*str != '\0')
1392 {
1393 opP->error = "Junk after indirect";
1394 return FAIL;
1395 }
1396 return (OK);
1397 } /* m68k_ip_op() */
1398
1399
1400 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1401
1402 short
1403 tc_coff_fix2rtype (fixP)
1404 fixS *fixP;
1405 {
1406 return (fixP->fx_pcrel ?
1407 (fixP->fx_size == 1 ? R_PCRBYTE :
1408 fixP->fx_size == 2 ? R_PCRWORD :
1409 R_PCRLONG) :
1410 (fixP->fx_size == 1 ? R_RELBYTE :
1411 fixP->fx_size == 2 ? R_RELWORD :
1412 R_RELLONG));
1413
1414
1415 }
1416
1417 #endif
1418
1419 #ifdef BFD_ASSEMBLER
1420
1421 arelent *
1422 tc_gen_reloc (section, fixp)
1423 asection *section;
1424 fixS *fixp;
1425 {
1426 arelent *reloc;
1427 bfd_reloc_code_real_type code;
1428
1429 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1430 switch (F (fixp->fx_size, fixp->fx_pcrel))
1431 {
1432 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1433 MAP (1, 0, BFD_RELOC_8);
1434 MAP (2, 0, BFD_RELOC_16);
1435 MAP (4, 0, BFD_RELOC_32);
1436 MAP (1, 1, BFD_RELOC_8_PCREL);
1437 MAP (2, 1, BFD_RELOC_16_PCREL);
1438 MAP (4, 1, BFD_RELOC_32_PCREL);
1439 default:
1440 abort ();
1441 }
1442
1443 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1444 assert (reloc != 0);
1445 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1446 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1447 if (fixp->fx_pcrel)
1448 reloc->addend = fixp->fx_addnumber;
1449 else
1450 reloc->addend = 0;
1451
1452 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1453 assert (reloc->howto != 0);
1454
1455 return reloc;
1456 }
1457
1458 #endif /* BFD_ASSEMBLER */
1459
1460 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1461 main ()
1462 {
1463 char buf[128];
1464 struct m68k_op thark;
1465
1466 for (;;)
1467 {
1468 if (!gets (buf))
1469 break;
1470 memset (&thark, '\0', sizeof (thark));
1471 if (!m68k_ip_op (buf, &thark))
1472 printf ("FAIL:");
1473 if (thark.error)
1474 printf ("op1 error %s in %s\n", thark.error, buf);
1475 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1476 if (thark.b_const)
1477 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1478 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1479 if (thark.b_iadd)
1480 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1481 printf ("\n");
1482 }
1483 exit (0);
1484 }
1485
1486 #endif
1487
1488
1489 /* Handle of the OPCODE hash table. NULL means any use before
1490 m68k_ip_begin() will crash. */
1491 static struct hash_control *op_hash;
1492 \f
1493
1494 /*
1495 * m 6 8 k _ i p ( )
1496 *
1497 * This converts a string into a 68k instruction.
1498 * The string must be a bare single instruction in sun format
1499 * with RMS-style 68020 indirects
1500 * (example: )
1501 *
1502 * It provides some error messages: at most one fatal error message (which
1503 * stops the scan) and at most one warning message for each operand.
1504 * The 68k instruction is returned in exploded form, since we have no
1505 * knowledge of how you parse (or evaluate) your expressions.
1506 * We do however strip off and decode addressing modes and operation
1507 * mnemonic.
1508 *
1509 * This function's value is a string. If it is not "" then an internal
1510 * logic error was found: read this code to assign meaning to the string.
1511 * No argument string should generate such an error string:
1512 * it means a bug in our code, not in the user's text.
1513 *
1514 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1515 * this function.
1516 */
1517
1518 /* JF this function no longer returns a useful value. Sorry */
1519 void
1520 m68k_ip (instring)
1521 char *instring;
1522 {
1523 register char *p;
1524 register struct m68k_op *opP;
1525 register struct m68k_incant *opcode;
1526 register char *s;
1527 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1528 char *pdot, *pdotmove;
1529 int siz1, siz2;
1530 char c;
1531 int losing;
1532 int opsfound;
1533 char *crack_operand ();
1534 LITTLENUM_TYPE words[6];
1535 LITTLENUM_TYPE *wordp;
1536 unsigned long ok_arch = 0;
1537
1538 if (*instring == ' ')
1539 instring++; /* skip leading whitespace */
1540
1541 /* Scan up to end of operation-code, which MUST end in end-of-string
1542 or exactly 1 space. */
1543 pdot = 0;
1544 for (p = instring; *p != '\0'; p++)
1545 {
1546 if (*p == ' ')
1547 break;
1548 if (*p == '.')
1549 pdot = p;
1550 }
1551
1552 if (p == instring)
1553 {
1554 the_ins.error = "No operator";
1555 the_ins.opcode[0] = NULL;
1556 /* the_ins.numo=1; */
1557 return;
1558 }
1559
1560 /* p now points to the end of the opcode name, probably whitespace.
1561 make sure the name is null terminated by clobbering the whitespace,
1562 look it up in the hash table, then fix it back.
1563 Remove a dot, first, since the opcode tables have none. */
1564 if (pdot != NULL)
1565 {
1566 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1567 *pdotmove = pdotmove[1];
1568 p--;
1569 }
1570
1571 c = *p;
1572 *p = '\0';
1573 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
1574 *p = c;
1575
1576 if (pdot != NULL)
1577 {
1578 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1579 *pdotmove = pdotmove[-1];
1580 *pdot = '.';
1581 ++p;
1582 }
1583
1584 if (opcode == NULL)
1585 {
1586 the_ins.error = "Unknown operator";
1587 the_ins.opcode[0] = NULL;
1588 /* the_ins.numo=1; */
1589 return;
1590 }
1591
1592 /* found a legitimate opcode, start matching operands */
1593 while (*p == ' ')
1594 ++p;
1595
1596
1597 if (opcode->m_operands == 0)
1598 {
1599 char *old = input_line_pointer;
1600 *old = '\n';
1601 input_line_pointer = p;
1602 /* Ahh - it's a motorola style psuedo op */
1603 mote_pseudo_table[opcode->m_opnum].poc_handler
1604 (mote_pseudo_table[opcode->m_opnum].poc_val);
1605 input_line_pointer = old;
1606 *old = 0;
1607
1608 return;
1609 }
1610
1611 for (opP = &the_ins.operands[0]; *p; opP++)
1612 {
1613
1614 p = crack_operand (p, opP);
1615
1616 if (opP->error)
1617 {
1618 the_ins.error = opP->error;
1619 return;
1620 }
1621 }
1622
1623 opsfound = opP - &the_ins.operands[0];
1624
1625 /* This ugly hack is to support the floating pt opcodes in their standard form */
1626 /* Essentially, we fake a first enty of type COP#1 */
1627 if (opcode->m_operands[0] == 'I')
1628 {
1629 int n;
1630
1631 for (n = opsfound; n > 0; --n)
1632 the_ins.operands[n] = the_ins.operands[n - 1];
1633
1634 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1635 the_ins.operands[0].mode = MSCR;
1636 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1637 opsfound++;
1638 }
1639
1640 /* We've got the operands. Find an opcode that'll accept them */
1641 for (losing = 0;;)
1642 {
1643 /* If we didn't get the right number of ops, or we have no
1644 common model with this pattern then reject this pattern. */
1645
1646 if (opsfound != opcode->m_opnum
1647 || ((opcode->m_arch & current_architecture) == 0))
1648 {
1649 ++losing;
1650 ok_arch |= opcode->m_arch;
1651 }
1652 else
1653 {
1654 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1655 {
1656 /* Warning: this switch is huge! */
1657 /* I've tried to organize the cases into this order:
1658 non-alpha first, then alpha by letter. Lower-case
1659 goes directly before uppercase counterpart. */
1660 /* Code with multiple case ...: gets sorted by the lowest
1661 case ... it belongs to. I hope this makes sense. */
1662 switch (*s)
1663 {
1664 case '!':
1665 if (opP->mode == MSCR || opP->mode == IMMED
1666 || opP->mode == DREG || opP->mode == AREG
1667 || opP->mode == AINC || opP->mode == ADEC
1668 || opP->mode == REGLST)
1669 losing++;
1670 break;
1671
1672 case '`':
1673 switch (opP->mode)
1674 {
1675 case MSCR:
1676 case IMMED:
1677 case DREG:
1678 case AREG:
1679 case AINC:
1680 case REGLST:
1681 case AINDR:
1682 losing++;
1683 }
1684 break;
1685
1686 case '#':
1687 if (opP->mode != IMMED)
1688 losing++;
1689 else
1690 {
1691 long t;
1692
1693 t = get_num (opP->con1, 80);
1694 if (s[1] == 'b' && !isbyte (t))
1695 losing++;
1696 else if (s[1] == 'w' && !isword (t))
1697 losing++;
1698 }
1699 break;
1700
1701 case '^':
1702 case 'T':
1703 if (opP->mode != IMMED)
1704 losing++;
1705 break;
1706
1707 case '$':
1708 if (opP->mode == MSCR || opP->mode == AREG ||
1709 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1710 losing++;
1711 break;
1712
1713 case '%':
1714 if (opP->mode == MSCR || opP->reg == PC ||
1715 opP->reg == ZPC || opP->mode == REGLST)
1716 losing++;
1717 break;
1718
1719
1720 case '&':
1721 if (opP->mode == MSCR || opP->mode == DREG ||
1722 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1723 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1724 losing++;
1725 break;
1726
1727 case '*':
1728 if (opP->mode == MSCR || opP->mode == REGLST)
1729 losing++;
1730 break;
1731
1732 case '+':
1733 if (opP->mode != AINC)
1734 losing++;
1735 break;
1736
1737 case '-':
1738 if (opP->mode != ADEC)
1739 losing++;
1740 break;
1741
1742 case '/':
1743 if (opP->mode == MSCR || opP->mode == AREG ||
1744 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1745 losing++;
1746 break;
1747
1748 case ';':
1749 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1750 losing++;
1751 break;
1752
1753 case '?':
1754 if (opP->mode == MSCR || opP->mode == AREG ||
1755 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1756 opP->reg == ZPC || opP->mode == REGLST)
1757 losing++;
1758 break;
1759
1760 case '@':
1761 if (opP->mode == MSCR || opP->mode == AREG ||
1762 opP->mode == IMMED || opP->mode == REGLST)
1763 losing++;
1764 break;
1765
1766 case '~': /* For now! (JF FOO is this right?) */
1767 if (opP->mode == MSCR || opP->mode == DREG ||
1768 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1769 losing++;
1770 break;
1771
1772 case '3':
1773 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1774 losing++;
1775 break;
1776
1777 case 'A':
1778 if (opP->mode != AREG)
1779 losing++;
1780 break;
1781 case 'a':
1782 if (opP->mode != AINDR)
1783 {
1784 ++losing;
1785 } /* if not address register indirect */
1786 break;
1787 case 'B': /* FOO */
1788 if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j'
1789 && instring[1] == 'b'
1790 && instring[2] == 's'
1791 && instring[3] == 'r'))
1792 losing++;
1793 break;
1794
1795 case 'C':
1796 if (opP->mode != MSCR || opP->reg != CCR)
1797 losing++;
1798 break;
1799
1800 case 'd': /* FOO This mode is a KLUDGE!! */
1801 if (opP->mode != AOFF && (opP->mode != ABSL ||
1802 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1803 losing++;
1804 break;
1805
1806 case 'D':
1807 if (opP->mode != DREG)
1808 losing++;
1809 break;
1810
1811 case 'F':
1812 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1813 losing++;
1814 break;
1815
1816 case 'I':
1817 if (opP->mode != MSCR || opP->reg < COPNUM ||
1818 opP->reg >= COPNUM + 7)
1819 losing++;
1820 break;
1821
1822 case 'J':
1823 if (opP->mode != MSCR
1824 || opP->reg < USP
1825 || opP->reg > URP
1826 || cpu_of_arch (current_architecture) < m68010 /* before 68010 had none */
1827 || (cpu_of_arch (current_architecture) < m68020
1828 && opP->reg != SFC
1829 && opP->reg != DFC
1830 && opP->reg != USP
1831 && opP->reg != VBR) /* 68010's had only these */
1832 || (cpu_of_arch (current_architecture) < m68040
1833 && opP->reg != SFC
1834 && opP->reg != DFC
1835 && opP->reg != USP
1836 && opP->reg != VBR
1837 && opP->reg != CACR
1838 && opP->reg != CAAR
1839 && opP->reg != MSP
1840 && opP->reg != ISP) /* 680[23]0's have only these */
1841 || (cpu_of_arch (current_architecture) == m68040 /* 68040 has all but this */
1842 && opP->reg == CAAR))
1843 {
1844 losing++;
1845 } /* doesn't cut it */
1846 break;
1847
1848 case 'k':
1849 if (opP->mode != IMMED)
1850 losing++;
1851 break;
1852
1853 case 'l':
1854 case 'L':
1855 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1856 {
1857 if (s[1] == '8')
1858 losing++;
1859 else
1860 {
1861 opP->mode = REGLST;
1862 opP->reg = 1 << (opP->reg - DATA);
1863 }
1864 }
1865 else if (opP->mode != REGLST)
1866 {
1867 losing++;
1868 }
1869 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1870 losing++;
1871 else if (s[1] == '3' && opP->reg & 0x7000000)
1872 losing++;
1873 break;
1874
1875 case 'M':
1876 if (opP->mode != IMMED)
1877 losing++;
1878 else
1879 {
1880 long t;
1881
1882 t = get_num (opP->con1, 0);
1883 if (!issbyte (t)
1884 || isvar (opP->con1)
1885 || seg (opP->con1) != absolute_section)
1886 losing++;
1887 }
1888 break;
1889
1890 case 'O':
1891 if (opP->mode != DREG && opP->mode != IMMED)
1892 losing++;
1893 break;
1894
1895 case 'Q':
1896 if (opP->mode != IMMED)
1897 losing++;
1898 else
1899 {
1900 long t;
1901
1902 t = get_num (opP->con1, 80);
1903 if (t < 1 || t > 8 || isvar (opP->con1))
1904 losing++;
1905 }
1906 break;
1907
1908 case 'R':
1909 if (opP->mode != DREG && opP->mode != AREG)
1910 losing++;
1911 break;
1912
1913 case 'r':
1914 if (opP->mode != AINDR && opP->mode != DINDR)
1915 losing++;
1916 break;
1917
1918 case 's':
1919 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1920 losing++;
1921 break;
1922
1923 case 'S':
1924 if (opP->mode != MSCR || opP->reg != SR)
1925 losing++;
1926 break;
1927
1928 case 't':
1929 if (opP->mode != IMMED)
1930 losing++;
1931 else
1932 {
1933 long t = get_num (opP->con1, 80);
1934 if (t < 0 || t > 7 || isvar (opP->con1))
1935 losing++;
1936 }
1937 break;
1938
1939 case 'U':
1940 if (opP->mode != MSCR || opP->reg != USP)
1941 losing++;
1942 break;
1943
1944 /* JF these are out of order. We could put them
1945 in order if we were willing to put up with
1946 bunches of #ifdef m68851s in the code.
1947
1948 Don't forget that you need these operands
1949 to use 68030 MMU instructions. */
1950 #ifndef NO_68851
1951 /* Memory addressing mode used by pflushr */
1952 case '|':
1953 if (opP->mode == MSCR || opP->mode == DREG ||
1954 opP->mode == AREG || opP->mode == REGLST)
1955 losing++;
1956 break;
1957
1958 case 'f':
1959 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1960 losing++;
1961 break;
1962
1963 case 'P':
1964 if (opP->mode != MSCR
1965 || (opP->reg != TC && opP->reg != CAL
1966 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1967 losing++;
1968 break;
1969
1970 case 'V':
1971 if (opP->reg != VAL)
1972 losing++;
1973 break;
1974
1975 case 'W':
1976 if (opP->mode != MSCR
1977 || (opP->reg != DRP && opP->reg != SRP
1978 && opP->reg != CRP))
1979 losing++;
1980 break;
1981
1982 case 'X':
1983 if (opP->mode != MSCR ||
1984 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
1985 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1986 losing++;
1987 break;
1988
1989 case 'Y':
1990 if (opP->reg != PSR)
1991 losing++;
1992 break;
1993
1994 case 'Z':
1995 if (opP->reg != PCSR)
1996 losing++;
1997 break;
1998 #endif
1999 case 'c':
2000 if (opP->reg != NC
2001 && opP->reg != IC
2002 && opP->reg != DC
2003 && opP->reg != BC)
2004 {
2005 losing++;
2006 } /* not a cache specifier. */
2007 break;
2008
2009 case '_':
2010 if (opP->mode != ABSL)
2011 {
2012 ++losing;
2013 } /* not absolute */
2014 break;
2015
2016 default:
2017 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2018 *s, __LINE__, __FILE__);
2019 } /* switch on type of operand */
2020
2021 if (losing)
2022 break;
2023 } /* for each operand */
2024 } /* if immediately wrong */
2025
2026 if (!losing)
2027 {
2028 break;
2029 } /* got it. */
2030
2031 opcode = opcode->m_next;
2032
2033 if (!opcode)
2034 {
2035 if (ok_arch
2036 && !(ok_arch & current_architecture))
2037 {
2038 char buf[200], *cp;
2039 int len;
2040 strcpy (buf, "invalid instruction for this architecture; needs ");
2041 cp = buf + strlen (buf);
2042 switch (ok_arch)
2043 {
2044 case mfloat:
2045 strcpy (cp, "fpu (68040 or 68881/68882)");
2046 break;
2047 case mmmu:
2048 strcpy (cp, "mmu (68030 or 68851)");
2049 break;
2050 case m68020up:
2051 strcpy (cp, "68020 or higher");
2052 break;
2053 case m68000up:
2054 strcpy (cp, "68000 or higher");
2055 break;
2056 case m68010up:
2057 strcpy (cp, "68010 or higher");
2058 break;
2059 default:
2060 {
2061 int got_one = 0, idx;
2062 CONST static struct
2063 {
2064 int arch;
2065 CONST char *name;
2066 }
2067 archs[] =
2068 {
2069 m68000, "68000",
2070 m68010, "68010",
2071 m68020, "68020",
2072 m68030, "68030",
2073 m68040, "68040",
2074 cpu32, "cpu32",
2075 m68881, "68881",
2076 m68851, "68851",
2077 };
2078 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
2079 {
2080 if (archs[idx].arch & ok_arch)
2081 {
2082 if (got_one)
2083 {
2084 strcpy (cp, " or ");
2085 cp += strlen (cp);
2086 }
2087 got_one = 1;
2088 strcpy (cp, archs[idx].name);
2089 cp += strlen (cp);
2090 }
2091 }
2092 }
2093 }
2094 len = cp - buf + 1;
2095 cp = malloc (len);
2096 strcpy (cp, buf);
2097 the_ins.error = cp;
2098 }
2099 else
2100 the_ins.error = "operands mismatch";
2101 return;
2102 } /* Fell off the end */
2103
2104 losing = 0;
2105 }
2106
2107 /* now assemble it */
2108
2109 the_ins.args = opcode->m_operands;
2110 the_ins.numargs = opcode->m_opnum;
2111 the_ins.numo = opcode->m_codenum;
2112 the_ins.opcode[0] = getone (opcode);
2113 the_ins.opcode[1] = gettwo (opcode);
2114
2115 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2116 {
2117 /* This switch is a doozy.
2118 Watch the first step; its a big one! */
2119 switch (s[0])
2120 {
2121
2122 case '*':
2123 case '~':
2124 case '%':
2125 case ';':
2126 case '@':
2127 case '!':
2128 case '&':
2129 case '$':
2130 case '?':
2131 case '/':
2132 case '`':
2133 #ifndef NO_68851
2134 case '|':
2135 #endif
2136 switch (opP->mode)
2137 {
2138 case IMMED:
2139 tmpreg = 0x3c; /* 7.4 */
2140 if (strchr ("bwl", s[1]))
2141 nextword = get_num (opP->con1, 80);
2142 else
2143 nextword = get_num (opP->con1, 0);
2144 if (isvar (opP->con1))
2145 add_fix (s[1], opP->con1, 0);
2146 switch (s[1])
2147 {
2148 case 'b':
2149 if (!isbyte (nextword))
2150 opP->error = "operand out of range";
2151 addword (nextword);
2152 baseo = 0;
2153 break;
2154 case 'w':
2155 if (!isword (nextword))
2156 opP->error = "operand out of range";
2157 addword (nextword);
2158 baseo = 0;
2159 break;
2160 case 'l':
2161 addword (nextword >> 16);
2162 addword (nextword);
2163 baseo = 0;
2164 break;
2165
2166 case 'f':
2167 baseo = 2;
2168 outro = 8;
2169 break;
2170 case 'F':
2171 baseo = 4;
2172 outro = 11;
2173 break;
2174 case 'x':
2175 baseo = 6;
2176 outro = 15;
2177 break;
2178 case 'p':
2179 baseo = 6;
2180 outro = -1;
2181 break;
2182 default:
2183 as_fatal ("Internal error: Can't decode %c%c in line %s of file \"%s\"",
2184 *s, s[1], __LINE__, __FILE__);
2185 }
2186 if (!baseo)
2187 break;
2188
2189 /* We gotta put out some float */
2190 #if 0
2191 if (seg (opP->con1) != SEG_BIG)
2192 {
2193 int_to_gen (nextword);
2194 gen_to_words (words, baseo, (long int) outro);
2195 for (wordp = words; baseo--; wordp++)
2196 addword (*wordp);
2197 break;
2198 } /* Its BIG */
2199 #else
2200 if (seg (opP->con1) != big_section)
2201 {
2202 abort ();
2203 }
2204 #endif
2205 if (offs (opP->con1) > 0)
2206 {
2207 if (offs (opP->con1) > baseo)
2208 {
2209 as_warn ("Bignum too big for %c format; truncated", s[1]);
2210 offs (opP->con1) = baseo;
2211 }
2212 baseo -= offs (opP->con1);
2213 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2214 addword (*wordp);
2215 while (baseo--)
2216 addword (0);
2217 break;
2218 }
2219 gen_to_words (words, baseo, (long) outro);
2220 for (wordp = words; baseo--; wordp++)
2221 addword (*wordp);
2222 break;
2223 case DREG:
2224 tmpreg = opP->reg - DATA; /* 0.dreg */
2225 break;
2226 case AREG:
2227 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2228 break;
2229 case AINDR:
2230 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2231 break;
2232 case ADEC:
2233 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2234 break;
2235 case AINC:
2236 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2237 break;
2238 case AOFF:
2239
2240 nextword = get_num (opP->con1, 80);
2241 /* Force into index mode. Hope this works */
2242
2243 /* We do the first bit for 32-bit displacements, and the
2244 second bit for 16 bit ones. It is possible that we
2245 should make the default be WORD instead of LONG, but
2246 I think that'd break GCC, so we put up with a little
2247 inefficiency for the sake of working output. */
2248
2249 if (!issword (nextword)
2250 || (isvar (opP->con1)
2251 && ((opP->con1->e_siz == 0
2252 && flagseen['l'] == 0)
2253 || opP->con1->e_siz == 3)))
2254 {
2255
2256 if (opP->reg == PC)
2257 tmpreg = 0x3B; /* 7.3 */
2258 else
2259 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2260 if (isvar (opP->con1))
2261 {
2262 if (opP->reg == PC)
2263 {
2264 add_frag (adds (opP->con1),
2265 offs (opP->con1) + 2,
2266 TAB (PCLEA, SZ_UNDEF));
2267 break;
2268 }
2269 else
2270 {
2271 addword (0x0170);
2272 add_fix ('l', opP->con1, 0);
2273 }
2274 }
2275 else
2276 addword (0x0170);
2277 addword (nextword >> 16);
2278 }
2279 else
2280 {
2281 if (opP->reg == PC)
2282 tmpreg = 0x3A; /* 7.2 */
2283 else
2284 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2285
2286 if (isvar (opP->con1))
2287 {
2288 if (opP->reg == PC)
2289 {
2290 add_fix ('w', opP->con1, 1);
2291 }
2292 else
2293 add_fix ('w', opP->con1, 0);
2294 }
2295 }
2296 addword (nextword);
2297 break;
2298
2299 case APODX:
2300 case AMIND:
2301 case APRDX:
2302 know (current_architecture & m68020up);
2303 /* intentional fall-through */
2304 case AINDX:
2305 nextword = 0;
2306 baseo = get_num (opP->con1, 80);
2307 outro = get_num (opP->con2, 80);
2308 /* Figure out the `addressing mode'.
2309 Also turn on the BASE_DISABLE bit, if needed. */
2310 if (opP->reg == PC || opP->reg == ZPC)
2311 {
2312 tmpreg = 0x3b;/* 7.3 */
2313 if (opP->reg == ZPC)
2314 nextword |= 0x80;
2315 }
2316 else if (opP->reg == FAIL)
2317 {
2318 nextword |= 0x80;
2319 tmpreg = 0x30;/* 6.garbage */
2320 }
2321 else
2322 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2323
2324 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2325 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2326
2327 /* Index register stuff */
2328 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2329 {
2330 nextword |= (opP->ireg - DATA) << 12;
2331
2332 if (opP->isiz == 0 || opP->isiz == 3)
2333 nextword |= 0x800;
2334 switch (opP->imul)
2335 {
2336 case 1:
2337 break;
2338 case 2:
2339 nextword |= 0x200;
2340 break;
2341 case 4:
2342 nextword |= 0x400;
2343 break;
2344 case 8:
2345 nextword |= 0x600;
2346 break;
2347 default:
2348 as_fatal ("failed sanity check.");
2349 }
2350 /* IF its simple,
2351 GET US OUT OF HERE! */
2352
2353 /* Must be INDEX, with an index
2354 register. Address register
2355 cannot be ZERO-PC, and either
2356 :b was forced, or we know
2357 it will fit */
2358 if (opP->mode == AINDX
2359 && opP->reg != FAIL
2360 && opP->reg != ZPC
2361 && (siz1 == 1
2362 || (issbyte (baseo)
2363 && !isvar (opP->con1))))
2364 {
2365 nextword += baseo & 0xff;
2366 addword (nextword);
2367 if (isvar (opP->con1))
2368 add_fix ('B', opP->con1, 0);
2369 break;
2370 }
2371 }
2372 else
2373 nextword |= 0x40; /* No index reg */
2374
2375 /* It isn't simple. */
2376 nextword |= 0x100;
2377 /* If the guy specified a width, we assume that it is
2378 wide enough. Maybe it isn't. If so, we lose. */
2379 switch (siz1)
2380 {
2381 case 0:
2382 if (isvar (opP->con1) || !issword (baseo))
2383 {
2384 siz1 = 3;
2385 nextword |= 0x30;
2386 }
2387 else if (baseo == 0)
2388 nextword |= 0x10;
2389 else
2390 {
2391 nextword |= 0x20;
2392 siz1 = 2;
2393 }
2394 break;
2395 case 1:
2396 as_warn ("Byte dispacement won't work. Defaulting to :w");
2397 case 2:
2398 nextword |= 0x20;
2399 break;
2400 case 3:
2401 nextword |= 0x30;
2402 break;
2403 }
2404
2405 /* Figure out innner displacement stuff */
2406 if (opP->mode != AINDX)
2407 {
2408 switch (siz2)
2409 {
2410 case 0:
2411 if (isvar (opP->con2) || !issword (outro))
2412 {
2413 siz2 = 3;
2414 nextword |= 0x3;
2415 }
2416 else if (outro == 0)
2417 nextword |= 0x1;
2418 else
2419 {
2420 nextword |= 0x2;
2421 siz2 = 2;
2422 }
2423 break;
2424 case 1:
2425 as_warn ("Byte dispacement won't work. Defaulting to :w");
2426 case 2:
2427 nextword |= 0x2;
2428 break;
2429 case 3:
2430 nextword |= 0x3;
2431 break;
2432 }
2433 if (opP->mode == APODX)
2434 nextword |= 0x04;
2435 else if (opP->mode == AMIND)
2436 nextword |= 0x40;
2437 }
2438 addword (nextword);
2439
2440 if (isvar (opP->con1))
2441 {
2442 if (opP->reg == PC || opP->reg == ZPC)
2443 {
2444 opP->con1->e_exp.X_add_number += 6;
2445 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
2446 }
2447 else
2448 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2449 }
2450 if (siz1 == 3)
2451 addword (baseo >> 16);
2452 if (siz1)
2453 addword (baseo);
2454
2455 if (isvar (opP->con2))
2456 {
2457 if (opP->reg == PC || opP->reg == ZPC)
2458 {
2459 opP->con1->e_exp.X_add_number += 6;
2460 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
2461 }
2462 else
2463 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2464 }
2465 if (siz2 == 3)
2466 addword (outro >> 16);
2467 if (siz2)
2468 addword (outro);
2469
2470 break;
2471
2472 case ABSL:
2473 nextword = get_num (opP->con1, 80);
2474 switch (opP->con1->e_siz)
2475 {
2476 default:
2477 as_warn ("Unknown size for absolute reference");
2478 case 0:
2479 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2480 {
2481 tmpreg = 0x38; /* 7.0 */
2482 addword (nextword);
2483 break;
2484 }
2485 /* Don't generate pc relative code
2486 on 68010 and 68000 */
2487 if (isvar (opP->con1)
2488 && !subs (opP->con1)
2489 && seg (opP->con1) == text_section
2490 && now_seg == text_section
2491 && cpu_of_arch (current_architecture) >= m68020
2492 && !flagseen['S']
2493 && !strchr ("~%&$?", s[0]))
2494 {
2495 tmpreg = 0x3A; /* 7.2 */
2496 add_frag (adds (opP->con1),
2497 offs (opP->con1),
2498 TAB (PCREL, SZ_UNDEF));
2499 break;
2500 }
2501 case 3: /* Fall through into long */
2502 if (isvar (opP->con1))
2503 add_fix ('l', opP->con1, 0);
2504
2505 tmpreg = 0x39;/* 7.1 mode */
2506 addword (nextword >> 16);
2507 addword (nextword);
2508 break;
2509
2510 case 2: /* Word */
2511 if (isvar (opP->con1))
2512 add_fix ('w', opP->con1, 0);
2513
2514 tmpreg = 0x38;/* 7.0 mode */
2515 addword (nextword);
2516 break;
2517 }
2518 break;
2519 case DINDR:
2520 as_bad ("invalid indirect register");
2521 break;
2522 case MSCR:
2523 default:
2524 as_bad ("unknown/incorrect operand");
2525 /* abort(); */
2526 }
2527 install_gen_operand (s[1], tmpreg);
2528 break;
2529
2530 case '#':
2531 case '^':
2532 switch (s[1])
2533 { /* JF: I hate floating point! */
2534 case 'j':
2535 tmpreg = 70;
2536 break;
2537 case '8':
2538 tmpreg = 20;
2539 break;
2540 case 'C':
2541 tmpreg = 50;
2542 break;
2543 case '3':
2544 default:
2545 tmpreg = 80;
2546 break;
2547 }
2548 tmpreg = get_num (opP->con1, tmpreg);
2549 if (isvar (opP->con1))
2550 add_fix (s[1], opP->con1, 0);
2551 switch (s[1])
2552 {
2553 case 'b': /* Danger: These do no check for
2554 certain types of overflow.
2555 user beware! */
2556 if (!isbyte (tmpreg))
2557 opP->error = "out of range";
2558 insop (tmpreg);
2559 if (isvar (opP->con1))
2560 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2561 break;
2562 case 'w':
2563 if (!isword (tmpreg))
2564 opP->error = "out of range";
2565 insop (tmpreg);
2566 if (isvar (opP->con1))
2567 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2568 break;
2569 case 'l':
2570 insop (tmpreg); /* Because of the way insop works, we put these two out backwards */
2571 insop (tmpreg >> 16);
2572 if (isvar (opP->con1))
2573 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2574 break;
2575 case '3':
2576 tmpreg &= 0xFF;
2577 case '8':
2578 case 'C':
2579 install_operand (s[1], tmpreg);
2580 break;
2581 default:
2582 as_fatal ("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2583 }
2584 break;
2585
2586 case '+':
2587 case '-':
2588 case 'A':
2589 case 'a':
2590 install_operand (s[1], opP->reg - ADDR);
2591 break;
2592
2593 case 'B':
2594 tmpreg = get_num (opP->con1, 80);
2595 switch (s[1])
2596 {
2597 case 'B':
2598 /* Needs no offsetting */
2599 add_fix ('B', opP->con1, 1);
2600 break;
2601 case 'W':
2602 /* Offset the displacement to be relative to byte disp location */
2603 opP->con1->e_exp.X_add_number += 2;
2604 add_fix ('w', opP->con1, 1);
2605 addword (0);
2606 break;
2607 case 'L':
2608 long_branch:
2609 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2610 as_warn ("Can't use long branches on 68000/68010");
2611 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2612 /* Offset the displacement to be relative to byte disp location */
2613 opP->con1->e_exp.X_add_number += 4;
2614 add_fix ('l', opP->con1, 1);
2615 addword (0);
2616 addword (0);
2617 break;
2618 case 'g':
2619 if (subs (opP->con1)) /* We can't relax it */
2620 goto long_branch;
2621
2622 /* This could either be a symbol, or an
2623 absolute address. No matter, the
2624 frag hacking will finger it out.
2625 Not quite: it can't switch from
2626 BRANCH to BCC68000 for the case
2627 where opnd is absolute (it needs
2628 to use the 68000 hack since no
2629 conditional abs jumps). */
2630 if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1)))
2631 && (the_ins.opcode[0] >= 0x6200)
2632 && (the_ins.opcode[0] <= 0x6f00))
2633 {
2634 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2635 }
2636 else
2637 {
2638 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2639 }
2640 break;
2641 case 'w':
2642 if (isvar (opP->con1))
2643 {
2644 #if 1
2645 /* check for DBcc instruction */
2646 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2647 {
2648 /* size varies if patch */
2649 /* needed for long form */
2650 add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF));
2651 break;
2652 }
2653 #endif
2654 /* Don't ask! */
2655 opP->con1->e_exp.X_add_number += 2;
2656 add_fix ('w', opP->con1, 1);
2657 }
2658 addword (0);
2659 break;
2660 case 'C': /* Fixed size LONG coproc branches */
2661 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2662 /* Offset the displacement to be relative to byte disp location */
2663 /* Coproc branches don't have a byte disp option, but they are
2664 compatible with the ordinary branches, which do... */
2665 opP->con1->e_exp.X_add_number += 4;
2666 add_fix ('l', opP->con1, 1);
2667 addword (0);
2668 addword (0);
2669 break;
2670 case 'c': /* Var size Coprocesssor branches */
2671 if (subs (opP->con1))
2672 {
2673 add_fix ('l', opP->con1, 1);
2674 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2675 }
2676 else if (adds (opP->con1))
2677 {
2678 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2679 }
2680 else
2681 {
2682 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2683 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2684 add_fix ('l', opP->con1, 1);
2685 addword (0);
2686 addword (4);
2687 }
2688 break;
2689 default:
2690 as_fatal ("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2691 s[1], __LINE__, __FILE__);
2692 }
2693 break;
2694
2695 case 'C': /* Ignore it */
2696 break;
2697
2698 case 'd': /* JF this is a kludge */
2699 if (opP->mode == AOFF)
2700 {
2701 install_operand ('s', opP->reg - ADDR);
2702 }
2703 else
2704 {
2705 char *tmpP;
2706
2707 tmpP = opP->con1->e_end - 2;
2708 opP->con1->e_beg++;
2709 opP->con1->e_end -= 4; /* point to the , */
2710 baseo = m68k_reg_parse (&tmpP);
2711 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2712 {
2713 as_bad ("Unknown address reg, using A0");
2714 baseo = 0;
2715 }
2716 else
2717 baseo -= ADDR;
2718 install_operand ('s', baseo);
2719 }
2720 tmpreg = get_num (opP->con1, 80);
2721 if (!issword (tmpreg))
2722 {
2723 as_warn ("Expression out of range, using 0");
2724 tmpreg = 0;
2725 }
2726 addword (tmpreg);
2727 break;
2728
2729 case 'D':
2730 install_operand (s[1], opP->reg - DATA);
2731 break;
2732
2733 case 'F':
2734 install_operand (s[1], opP->reg - FPREG);
2735 break;
2736
2737 case 'I':
2738 tmpreg = 1 + opP->reg - COPNUM;
2739 if (tmpreg == 8)
2740 tmpreg = 0;
2741 install_operand (s[1], tmpreg);
2742 break;
2743
2744 case 'J': /* JF foo */
2745 switch (opP->reg)
2746 {
2747 case SFC:
2748 tmpreg = 0x000;
2749 break;
2750 case DFC:
2751 tmpreg = 0x001;
2752 break;
2753 case CACR:
2754 tmpreg = 0x002;
2755 break;
2756 case TC:
2757 tmpreg = 0x003;
2758 break;
2759 case ITT0:
2760 tmpreg = 0x004;
2761 break;
2762 case ITT1:
2763 tmpreg = 0x005;
2764 break;
2765 case DTT0:
2766 tmpreg = 0x006;
2767 break;
2768 case DTT1:
2769 tmpreg = 0x007;
2770 break;
2771
2772 case USP:
2773 tmpreg = 0x800;
2774 break;
2775 case VBR:
2776 tmpreg = 0x801;
2777 break;
2778 case CAAR:
2779 tmpreg = 0x802;
2780 break;
2781 case MSP:
2782 tmpreg = 0x803;
2783 break;
2784 case ISP:
2785 tmpreg = 0x804;
2786 break;
2787 case MMUSR:
2788 tmpreg = 0x805;
2789 break;
2790 case URP:
2791 tmpreg = 0x806;
2792 break;
2793 case SRP:
2794 tmpreg = 0x807;
2795 break;
2796 default:
2797 as_fatal ("failed sanity check.");
2798 }
2799 install_operand (s[1], tmpreg);
2800 break;
2801
2802 case 'k':
2803 tmpreg = get_num (opP->con1, 55);
2804 install_operand (s[1], tmpreg & 0x7f);
2805 break;
2806
2807 case 'l':
2808 tmpreg = opP->reg;
2809 if (s[1] == 'w')
2810 {
2811 if (tmpreg & 0x7FF0000)
2812 as_bad ("Floating point register in register list");
2813 insop (reverse_16_bits (tmpreg));
2814 }
2815 else
2816 {
2817 if (tmpreg & 0x700FFFF)
2818 as_bad ("Wrong register in floating-point reglist");
2819 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2820 }
2821 break;
2822
2823 case 'L':
2824 tmpreg = opP->reg;
2825 if (s[1] == 'w')
2826 {
2827 if (tmpreg & 0x7FF0000)
2828 as_bad ("Floating point register in register list");
2829 insop (tmpreg);
2830 }
2831 else if (s[1] == '8')
2832 {
2833 if (tmpreg & 0x0FFFFFF)
2834 as_bad ("incorrect register in reglist");
2835 install_operand (s[1], tmpreg >> 24);
2836 }
2837 else
2838 {
2839 if (tmpreg & 0x700FFFF)
2840 as_bad ("wrong register in floating-point reglist");
2841 else
2842 install_operand (s[1], tmpreg >> 16);
2843 }
2844 break;
2845
2846 case 'M':
2847 install_operand (s[1], get_num (opP->con1, 60));
2848 break;
2849
2850 case 'O':
2851 tmpreg = (opP->mode == DREG)
2852 ? 0x20 + opP->reg - DATA
2853 : (get_num (opP->con1, 40) & 0x1F);
2854 install_operand (s[1], tmpreg);
2855 break;
2856
2857 case 'Q':
2858 tmpreg = get_num (opP->con1, 10);
2859 if (tmpreg == 8)
2860 tmpreg = 0;
2861 install_operand (s[1], tmpreg);
2862 break;
2863
2864 case 'R':
2865 case 'r':
2866 /* This depends on the fact that ADDR registers are
2867 eight more than their corresponding DATA regs, so
2868 the result will have the ADDR_REG bit set */
2869 install_operand (s[1], opP->reg - DATA);
2870 break;
2871
2872 case 's':
2873 if (opP->reg == FPI)
2874 tmpreg = 0x1;
2875 else if (opP->reg == FPS)
2876 tmpreg = 0x2;
2877 else if (opP->reg == FPC)
2878 tmpreg = 0x4;
2879 else
2880 as_fatal ("failed sanity check.");
2881 install_operand (s[1], tmpreg);
2882 break;
2883
2884 case 'S': /* Ignore it */
2885 break;
2886
2887 case 'T':
2888 install_operand (s[1], get_num (opP->con1, 30));
2889 break;
2890
2891 case 'U': /* Ignore it */
2892 break;
2893
2894 case 'c':
2895 switch (opP->reg)
2896 {
2897 case NC:
2898 tmpreg = 0;
2899 break;
2900 case DC:
2901 tmpreg = 1;
2902 break;
2903 case IC:
2904 tmpreg = 2;
2905 break;
2906 case BC:
2907 tmpreg = 3;
2908 break;
2909 default:
2910 as_fatal ("failed sanity check");
2911 } /* switch on cache token */
2912 install_operand (s[1], tmpreg);
2913 break;
2914 #ifndef NO_68851
2915 /* JF: These are out of order, I fear. */
2916 case 'f':
2917 switch (opP->reg)
2918 {
2919 case SFC:
2920 tmpreg = 0;
2921 break;
2922 case DFC:
2923 tmpreg = 1;
2924 break;
2925 default:
2926 as_fatal ("failed sanity check.");
2927 }
2928 install_operand (s[1], tmpreg);
2929 break;
2930
2931 case 'P':
2932 switch (opP->reg)
2933 {
2934 case TC:
2935 tmpreg = 0;
2936 break;
2937 case CAL:
2938 tmpreg = 4;
2939 break;
2940 case VAL:
2941 tmpreg = 5;
2942 break;
2943 case SCC:
2944 tmpreg = 6;
2945 break;
2946 case AC:
2947 tmpreg = 7;
2948 break;
2949 default:
2950 as_fatal ("failed sanity check.");
2951 }
2952 install_operand (s[1], tmpreg);
2953 break;
2954
2955 case 'V':
2956 if (opP->reg == VAL)
2957 break;
2958 as_fatal ("failed sanity check.");
2959
2960 case 'W':
2961 switch (opP->reg)
2962 {
2963
2964 case DRP:
2965 tmpreg = 1;
2966 break;
2967 case SRP:
2968 tmpreg = 2;
2969 break;
2970 case CRP:
2971 tmpreg = 3;
2972 break;
2973 default:
2974 as_fatal ("failed sanity check.");
2975 }
2976 install_operand (s[1], tmpreg);
2977 break;
2978
2979 case 'X':
2980 switch (opP->reg)
2981 {
2982 case BAD:
2983 case BAD + 1:
2984 case BAD + 2:
2985 case BAD + 3:
2986 case BAD + 4:
2987 case BAD + 5:
2988 case BAD + 6:
2989 case BAD + 7:
2990 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2991 break;
2992
2993 case BAC:
2994 case BAC + 1:
2995 case BAC + 2:
2996 case BAC + 3:
2997 case BAC + 4:
2998 case BAC + 5:
2999 case BAC + 6:
3000 case BAC + 7:
3001 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3002 break;
3003
3004 default:
3005 as_fatal ("failed sanity check.");
3006 }
3007 install_operand (s[1], tmpreg);
3008 break;
3009 case 'Y':
3010 know (opP->reg == PSR);
3011 break;
3012 case 'Z':
3013 know (opP->reg == PCSR);
3014 break;
3015 #endif /* m68851 */
3016 case '3':
3017 switch (opP->reg)
3018 {
3019 case TT0:
3020 tmpreg = 2;
3021 break;
3022 case TT1:
3023 tmpreg = 3;
3024 break;
3025 default:
3026 as_fatal ("failed sanity check");
3027 }
3028 install_operand (s[1], tmpreg);
3029 break;
3030 case 't':
3031 tmpreg = get_num (opP->con1, 20);
3032 install_operand (s[1], tmpreg);
3033 break;
3034 case '_': /* used only for move16 absolute 32-bit address */
3035 tmpreg = get_num (opP->con1, 80);
3036 addword (tmpreg >> 16);
3037 addword (tmpreg & 0xFFFF);
3038 break;
3039 default:
3040 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3041 s[0], __LINE__, __FILE__);
3042 }
3043 }
3044
3045 /* By the time whe get here (FINALLY) the_ins contains the complete
3046 instruction, ready to be emitted. . . */
3047 } /* m68k_ip() */
3048
3049 /*
3050 * get_regs := '/' + ?
3051 * | '-' + <register>
3052 * | '-' + <register> + ?
3053 * | <empty>
3054 * ;
3055 *
3056
3057 * The idea here must be to scan in a set of registers but I don't
3058 * understand it. Looks awfully sloppy to me but I don't have any doc on
3059 * this format so...
3060
3061 *
3062 *
3063 */
3064
3065 static int
3066 get_regs (i, str, opP)
3067 int i;
3068 struct m68k_op *opP;
3069 char *str;
3070 {
3071 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3072 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3073 unsigned long cur_regs = 0;
3074 int reg1, reg2;
3075
3076 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3077 else if(x==FPS) cur_regs|=(1<<25);\
3078 else if(x==FPC) cur_regs|=(1<<26);\
3079 else cur_regs|=(1<<(x-1)); }
3080
3081 reg1 = i;
3082 for (;;)
3083 {
3084 if (*str == '/')
3085 {
3086 ADD_REG (reg1);
3087 str++;
3088 }
3089 else if (*str == '-')
3090 {
3091 str++;
3092 reg2 = m68k_reg_parse (&str);
3093 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3094 {
3095 opP->error = "unknown register in register list";
3096 return FAIL;
3097 }
3098 while (reg1 <= reg2)
3099 {
3100 ADD_REG (reg1);
3101 reg1++;
3102 }
3103 if (*str == '\0')
3104 break;
3105 }
3106 else if (*str == '\0')
3107 {
3108 ADD_REG (reg1);
3109 break;
3110 }
3111 else
3112 {
3113 opP->error = "unknow character in register list";
3114 return FAIL;
3115 }
3116 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3117 if (*str == '/')
3118 str++;
3119 reg1 = m68k_reg_parse (&str);
3120 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3121 {
3122 opP->error = "unknown register in register list";
3123 return FAIL;
3124 }
3125 }
3126 opP->reg = cur_regs;
3127 return OK;
3128 } /* get_regs() */
3129
3130 static int
3131 reverse_16_bits (in)
3132 int in;
3133 {
3134 int out = 0;
3135 int n;
3136
3137 static int mask[16] =
3138 {
3139 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3140 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3141 };
3142 for (n = 0; n < 16; n++)
3143 {
3144 if (in & mask[n])
3145 out |= mask[15 - n];
3146 }
3147 return out;
3148 } /* reverse_16_bits() */
3149
3150 static int
3151 reverse_8_bits (in)
3152 int in;
3153 {
3154 int out = 0;
3155 int n;
3156
3157 static int mask[8] =
3158 {
3159 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3160 };
3161
3162 for (n = 0; n < 8; n++)
3163 {
3164 if (in & mask[n])
3165 out |= mask[7 - n];
3166 }
3167 return out;
3168 } /* reverse_8_bits() */
3169
3170 static void
3171 install_operand (mode, val)
3172 int mode;
3173 int val;
3174 {
3175 switch (mode)
3176 {
3177 case 's':
3178 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3179 break;
3180 case 'd':
3181 the_ins.opcode[0] |= val << 9;
3182 break;
3183 case '1':
3184 the_ins.opcode[1] |= val << 12;
3185 break;
3186 case '2':
3187 the_ins.opcode[1] |= val << 6;
3188 break;
3189 case '3':
3190 the_ins.opcode[1] |= val;
3191 break;
3192 case '4':
3193 the_ins.opcode[2] |= val << 12;
3194 break;
3195 case '5':
3196 the_ins.opcode[2] |= val << 6;
3197 break;
3198 case '6':
3199 /* DANGER! This is a hack to force cas2l and cas2w cmds
3200 to be three words long! */
3201 the_ins.numo++;
3202 the_ins.opcode[2] |= val;
3203 break;
3204 case '7':
3205 the_ins.opcode[1] |= val << 7;
3206 break;
3207 case '8':
3208 the_ins.opcode[1] |= val << 10;
3209 break;
3210 #ifndef NO_68851
3211 case '9':
3212 the_ins.opcode[1] |= val << 5;
3213 break;
3214 #endif
3215
3216 case 't':
3217 the_ins.opcode[1] |= (val << 10) | (val << 7);
3218 break;
3219 case 'D':
3220 the_ins.opcode[1] |= (val << 12) | val;
3221 break;
3222 case 'g':
3223 the_ins.opcode[0] |= val = 0xff;
3224 break;
3225 case 'i':
3226 the_ins.opcode[0] |= val << 9;
3227 break;
3228 case 'C':
3229 the_ins.opcode[1] |= val;
3230 break;
3231 case 'j':
3232 the_ins.opcode[1] |= val;
3233 the_ins.numo++; /* What a hack */
3234 break;
3235 case 'k':
3236 the_ins.opcode[1] |= val << 4;
3237 break;
3238 case 'b':
3239 case 'w':
3240 case 'l':
3241 break;
3242 case 'e':
3243 the_ins.opcode[0] |= (val << 6);
3244 break;
3245 case 'L':
3246 the_ins.opcode[1] = (val >> 16);
3247 the_ins.opcode[2] = val & 0xffff;
3248 break;
3249 case 'c':
3250 default:
3251 as_fatal ("failed sanity check.");
3252 }
3253 } /* install_operand() */
3254
3255 static void
3256 install_gen_operand (mode, val)
3257 int mode;
3258 int val;
3259 {
3260 switch (mode)
3261 {
3262 case 's':
3263 the_ins.opcode[0] |= val;
3264 break;
3265 case 'd':
3266 /* This is a kludge!!! */
3267 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3268 break;
3269 case 'b':
3270 case 'w':
3271 case 'l':
3272 case 'f':
3273 case 'F':
3274 case 'x':
3275 case 'p':
3276 the_ins.opcode[0] |= val;
3277 break;
3278 /* more stuff goes here */
3279 default:
3280 as_fatal ("failed sanity check.");
3281 }
3282 } /* install_gen_operand() */
3283
3284 /*
3285 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3286 * then deal with the bitfield hack.
3287 */
3288
3289 static char *
3290 crack_operand (str, opP)
3291 register char *str;
3292 register struct m68k_op *opP;
3293 {
3294 register int parens;
3295 register int c;
3296 register char *beg_str;
3297
3298 if (!str)
3299 {
3300 return str;
3301 }
3302 beg_str = str;
3303 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3304 {
3305 if (*str == '(')
3306 parens++;
3307 else if (*str == ')')
3308 {
3309 if (!parens)
3310 { /* ERROR */
3311 opP->error = "Extra )";
3312 return str;
3313 }
3314 --parens;
3315 }
3316 }
3317 if (!*str && parens)
3318 { /* ERROR */
3319 opP->error = "Missing )";
3320 return str;
3321 }
3322 c = *str;
3323 *str = '\0';
3324 if (m68k_ip_op (beg_str, opP) == FAIL)
3325 {
3326 *str = c;
3327 return str;
3328 }
3329 *str = c;
3330 if (c == '}')
3331 c = *++str; /* JF bitfield hack */
3332 if (c)
3333 {
3334 c = *++str;
3335 if (!c)
3336 as_bad ("Missing operand");
3337 }
3338 return str;
3339 }
3340
3341 /* See the comment up above where the #define notend(... is */
3342 #if 0
3343 notend (s)
3344 char *s;
3345 {
3346 if (*s == ',')
3347 return 0;
3348 if (*s == '{' || *s == '}')
3349 return 0;
3350 if (*s != ':')
3351 return 1;
3352 /* This kludge here is for the division cmd, which is a kludge */
3353 if (index ("aAdD#", s[1]))
3354 return 0;
3355 return 1;
3356 }
3357
3358 #endif
3359
3360 /* This is the guts of the machine-dependent assembler. STR points to a
3361 machine dependent instruction. This function is supposed to emit
3362 the frags/bytes it assembles to.
3363 */
3364
3365 void
3366 insert_reg (regname, regnum)
3367 char *regname;
3368 int regnum;
3369 {
3370 char buf[100];
3371 int i;
3372 symbolS *s;
3373
3374 #ifdef REGISTER_PREFIX
3375 buf[0] = REGISTER_PREFIX;
3376 strcpy (buf + 1, regname);
3377 regname = buf;
3378 #endif
3379
3380 symbol_table_insert (s = symbol_new (regname, reg_section, regnum, &zero_address_frag));
3381
3382 verify_symbol_chain_2 (s);
3383
3384 for (i = 0; regname[i]; i++)
3385 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3386 buf[i] = '\0';
3387
3388 symbol_table_insert (s = symbol_new (buf, reg_section, regnum, &zero_address_frag));
3389 verify_symbol_chain_2 (s);
3390 }
3391
3392 struct init_entry
3393 {
3394 char *name;
3395 int number;
3396 };
3397
3398 static CONST struct init_entry init_table[] =
3399 {
3400 "d0", DATA0,
3401 "d1", DATA1,
3402 "d2", DATA2,
3403 "d3", DATA3,
3404 "d4", DATA4,
3405 "d5", DATA5,
3406 "d6", DATA6,
3407 "d7", DATA7,
3408 "a0", ADDR0,
3409 "a1", ADDR1,
3410 "a2", ADDR2,
3411 "a3", ADDR3,
3412 "a4", ADDR4,
3413 "a5", ADDR5,
3414 "a6", ADDR6,
3415 "fp", ADDR6,
3416 "a7", ADDR7,
3417 "sp", ADDR7,
3418 "fp0", FP0,
3419 "fp1", FP1,
3420 "fp2", FP2,
3421 "fp3", FP3,
3422 "fp4", FP4,
3423 "fp5", FP5,
3424 "fp6", FP6,
3425 "fp7", FP7,
3426 "fpi", FPI,
3427 "fpiar", FPI,
3428 "fpc", FPI,
3429 "fps", FPS,
3430 "fpsr", FPS,
3431 "fpc", FPC,
3432 "fpcr", FPC,
3433
3434 "cop0", COP0,
3435 "cop1", COP1,
3436 "cop2", COP2,
3437 "cop3", COP3,
3438 "cop4", COP4,
3439 "cop5", COP5,
3440 "cop6", COP6,
3441 "cop7", COP7,
3442 "pc", PC,
3443 "zpc", ZPC,
3444 "sr", SR,
3445
3446 "ccr", CCR,
3447 "cc", CCR,
3448
3449 "usp", USP,
3450 "isp", ISP,
3451 "sfc", SFC,
3452 "dfc", DFC,
3453 "cacr", CACR,
3454 "caar", CAAR,
3455
3456 "vbr", VBR,
3457
3458 "msp", MSP,
3459 "itt0", ITT0,
3460 "itt1", ITT1,
3461 "dtt0", DTT0,
3462 "dtt1", DTT1,
3463 "mmusr", MMUSR,
3464 "tc", TC,
3465 "srp", SRP,
3466 "urp", URP,
3467
3468 "ac", AC,
3469 "bc", BC,
3470 "cal", CAL,
3471 "crp", CRP,
3472 "drp", DRP,
3473 "pcsr", PCSR,
3474 "psr", PSR,
3475 "scc", SCC,
3476 "val", VAL,
3477 "bad0", BAD0,
3478 "bad1", BAD1,
3479 "bad2", BAD2,
3480 "bad3", BAD3,
3481 "bad4", BAD4,
3482 "bad5", BAD5,
3483 "bad6", BAD6,
3484 "bad7", BAD7,
3485 "bac0", BAC0,
3486 "bac1", BAC1,
3487 "bac2", BAC2,
3488 "bac3", BAC3,
3489 "bac4", BAC4,
3490 "bac5", BAC5,
3491 "bac6", BAC6,
3492 "bac7", BAC7,
3493
3494 "ic", IC,
3495 "dc", DC,
3496 "nc", NC,
3497
3498 "tt0", TT0,
3499 "tt1", TT1,
3500 /* 68ec030 versions of same */
3501 "ac0", TT0,
3502 "ac1", TT1,
3503 /* 68ec030 access control unit, identical to 030 MMU status reg */
3504 "acusr", PSR,
3505
3506 0,
3507
3508 };
3509
3510
3511 void
3512 init_regtable ()
3513 {
3514 int i;
3515 for (i = 0; init_table[i].name; i++)
3516 insert_reg (init_table[i].name, init_table[i].number);
3517 }
3518
3519 static int no_68851, no_68881;
3520
3521 void
3522 md_assemble (str)
3523 char *str;
3524 {
3525 char *er;
3526 short *fromP;
3527 char *toP = NULL;
3528 int m, n = 0;
3529 char *to_beg_P;
3530 int shorts_this_frag;
3531 static int done_first_time;
3532
3533 if (!done_first_time)
3534 {
3535 done_first_time = 1;
3536
3537 if (cpu_of_arch (current_architecture) == 0)
3538 {
3539 int cpu_type;
3540
3541 if (strcmp (TARGET_CPU, "m68000") == 0
3542 || strcmp (TARGET_CPU, "m68302") == 0)
3543 cpu_type = m68000;
3544 else if (strcmp (TARGET_CPU, "m68010") == 0)
3545 cpu_type = m68010;
3546 else if (strcmp (TARGET_CPU, "m68020") == 0
3547 || strcmp (TARGET_CPU, "m68k") == 0)
3548 cpu_type = m68020;
3549 else if (strcmp (TARGET_CPU, "m68030") == 0)
3550 cpu_type = m68030;
3551 else if (strcmp (TARGET_CPU, "m68040") == 0)
3552 cpu_type = m68040;
3553 else if (strcmp (TARGET_CPU, "cpu32") == 0
3554 || strcmp (TARGET_CPU, "m68331") == 0
3555 || strcmp (TARGET_CPU, "m68332") == 0
3556 || strcmp (TARGET_CPU, "m68333") == 0
3557 || strcmp (TARGET_CPU, "m68340") == 0)
3558 cpu_type = cpu32;
3559 else
3560 cpu_type = m68020;
3561
3562 current_architecture |= cpu_type;
3563 }
3564 #if 0 /* Could be doing emulation. */
3565 if (current_architecture & m68881)
3566 {
3567 if (current_architecture & m68000)
3568 as_bad ("incompatible processors 68000 and 68881/2 specified");
3569 if (current_architecture & m68010)
3570 as_bad ("incompatible processors 68010 and 68881/2 specified");
3571 if (current_architecture & m68040)
3572 as_bad ("incompatible processors 68040 and 68881/2 specified");
3573 }
3574 #endif
3575 /* What other incompatibilities could we check for? */
3576
3577 /* Toss in some default assumptions about coprocessors. */
3578 if (!no_68881
3579 && (cpu_of_arch (current_architecture)
3580 /* Can CPU32 have a 68881 coprocessor?? */
3581 & (m68020 | m68030 | cpu32)))
3582 {
3583 current_architecture |= m68881;
3584 }
3585 if (!no_68851
3586 && (cpu_of_arch (current_architecture) & m68020up) != 0
3587 && cpu_of_arch (current_architecture) != m68040)
3588 {
3589 current_architecture |= m68851;
3590 }
3591 if (no_68881 && (current_architecture & m68881))
3592 as_bad ("options for 68881 and no-68881 both given");
3593 if (no_68851 && (current_architecture & m68851))
3594 as_bad ("options for 68851 and no-68851 both given");
3595 done_first_time = 1;
3596 }
3597
3598 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3599 m68k_ip (str);
3600 er = the_ins.error;
3601 if (!er)
3602 {
3603 for (n = the_ins.numargs; n; --n)
3604 if (the_ins.operands[n].error)
3605 {
3606 er = the_ins.operands[n].error;
3607 break;
3608 }
3609 }
3610 if (er)
3611 {
3612 as_bad ("%s -- statement `%s' ignored", er, str);
3613 return;
3614 }
3615
3616 if (the_ins.nfrag == 0)
3617 {
3618 /* No frag hacking involved; just put it out */
3619 toP = frag_more (2 * the_ins.numo);
3620 fromP = &the_ins.opcode[0];
3621 for (m = the_ins.numo; m; --m)
3622 {
3623 md_number_to_chars (toP, (long) (*fromP), 2);
3624 toP += 2;
3625 fromP++;
3626 }
3627 /* put out symbol-dependent info */
3628 for (m = 0; m < the_ins.nrel; m++)
3629 {
3630 switch (the_ins.reloc[m].wid)
3631 {
3632 case 'B':
3633 n = 1;
3634 break;
3635 case 'b':
3636 n = 1;
3637 break;
3638 case '3':
3639 n = 2;
3640 break;
3641 case 'w':
3642 n = 2;
3643 break;
3644 case 'l':
3645 n = 4;
3646 break;
3647 default:
3648 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3649 the_ins.reloc[m].wid);
3650 }
3651
3652 fix_new (frag_now,
3653 (toP - frag_now->fr_literal) - the_ins.numo * 2 + the_ins.reloc[m].n,
3654 n,
3655 the_ins.reloc[m].add,
3656 the_ins.reloc[m].sub,
3657 the_ins.reloc[m].off,
3658 the_ins.reloc[m].pcrel,
3659 NO_RELOC);
3660 }
3661 return;
3662 }
3663
3664 /* There's some frag hacking */
3665 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3666 {
3667 int wid;
3668
3669 if (n == 0)
3670 wid = 2 * the_ins.fragb[n].fragoff;
3671 else
3672 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3673 toP = frag_more (wid);
3674 to_beg_P = toP;
3675 shorts_this_frag = 0;
3676 for (m = wid / 2; m; --m)
3677 {
3678 md_number_to_chars (toP, (long) (*fromP), 2);
3679 toP += 2;
3680 fromP++;
3681 shorts_this_frag++;
3682 }
3683 for (m = 0; m < the_ins.nrel; m++)
3684 {
3685 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3686 {
3687 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3688 break;
3689 }
3690 wid = the_ins.reloc[m].wid;
3691 if (wid == 0)
3692 continue;
3693 the_ins.reloc[m].wid = 0;
3694 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3695
3696 fix_new (frag_now,
3697 (toP - frag_now->fr_literal) - the_ins.numo * 2 + the_ins.reloc[m].n,
3698 wid,
3699 the_ins.reloc[m].add,
3700 the_ins.reloc[m].sub,
3701 the_ins.reloc[m].off,
3702 the_ins.reloc[m].pcrel,
3703 NO_RELOC);
3704 }
3705 (void) frag_var (rs_machine_dependent, 10, 0,
3706 (relax_substateT) (the_ins.fragb[n].fragty),
3707 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3708 }
3709 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3710 shorts_this_frag = 0;
3711 if (n)
3712 {
3713 toP = frag_more (n * sizeof (short));
3714 while (n--)
3715 {
3716 md_number_to_chars (toP, (long) (*fromP), 2);
3717 toP += 2;
3718 fromP++;
3719 shorts_this_frag++;
3720 }
3721 }
3722 for (m = 0; m < the_ins.nrel; m++)
3723 {
3724 int wid;
3725
3726 wid = the_ins.reloc[m].wid;
3727 if (wid == 0)
3728 continue;
3729 the_ins.reloc[m].wid = 0;
3730 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3731
3732 fix_new (frag_now,
3733 (the_ins.reloc[m].n + toP - frag_now->fr_literal) - shorts_this_frag * 2,
3734 wid,
3735 the_ins.reloc[m].add,
3736 the_ins.reloc[m].sub,
3737 the_ins.reloc[m].off,
3738 the_ins.reloc[m].pcrel,
3739 NO_RELOC);
3740 }
3741 }
3742
3743 /* See BREAK_UP_BIG_DECL definition, above. */
3744 static struct m68k_opcode *
3745 opcode_ptr (i)
3746 int i;
3747 {
3748 #ifdef DO_BREAK_UP_BIG_DECL
3749 int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]);
3750 if (i >= lim1)
3751 return m68k_opcodes_2 + (i - lim1);
3752 #endif
3753 return m68k_opcodes + i;
3754 }
3755
3756 void
3757 md_begin ()
3758 {
3759 /*
3760 * md_begin -- set up hash tables with 68000 instructions.
3761 * similar to what the vax assembler does. ---phr
3762 */
3763 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3764 a copy of it at runtime, adding in the information we want but isn't
3765 there. I think it'd be better to have an awk script hack the table
3766 at compile time. Or even just xstr the table and use it as-is. But
3767 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3768 names. */
3769
3770 register CONST struct m68k_opcode *ins;
3771 register struct m68k_incant *hack, *slak;
3772 register char *retval = 0; /* empty string, or error msg text */
3773 register unsigned int i;
3774 register char c;
3775
3776 if ((op_hash = hash_new ()) == NULL)
3777 as_fatal ("Virtual memory exhausted");
3778
3779 obstack_begin (&robyn, 4000);
3780 for (i = 0; i < numopcodes; i++)
3781 {
3782 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3783 do
3784 {
3785 ins = opcode_ptr (i);
3786 /* We *could* ignore insns that don't match our arch here
3787 but just leaving them out of the hash. */
3788 slak->m_operands = ins->args;
3789 slak->m_opnum = strlen (slak->m_operands) / 2;
3790 slak->m_arch = ins->arch;
3791 slak->m_opcode = ins->opcode;
3792 /* This is kludgey */
3793 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3794 if (i + 1 != numopcodes
3795 && !strcmp (ins->name, opcode_ptr (i + 1)->name))
3796 {
3797 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3798 i++;
3799 }
3800 else
3801 slak->m_next = 0;
3802 slak = slak->m_next;
3803 }
3804 while (slak);
3805
3806 retval = hash_insert (op_hash, ins->name, (char *) hack);
3807 /* Didn't his mommy tell him about null pointers? */
3808 if (retval && *retval)
3809 as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval);
3810 }
3811
3812 for (i = 0; i < sizeof (mklower_table); i++)
3813 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3814
3815 for (i = 0; i < sizeof (notend_table); i++)
3816 {
3817 notend_table[i] = 0;
3818 alt_notend_table[i] = 0;
3819 }
3820 notend_table[','] = 1;
3821 notend_table['{'] = 1;
3822 notend_table['}'] = 1;
3823 alt_notend_table['a'] = 1;
3824 alt_notend_table['A'] = 1;
3825 alt_notend_table['d'] = 1;
3826 alt_notend_table['D'] = 1;
3827 alt_notend_table['#'] = 1;
3828 alt_notend_table['f'] = 1;
3829 alt_notend_table['F'] = 1;
3830 #ifdef REGISTER_PREFIX
3831 alt_notend_table[REGISTER_PREFIX] = 1;
3832 #endif
3833 #ifdef OPTIONAL_REGISTER_PREFIX
3834 alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1;
3835 #endif
3836
3837 #ifndef MIT_SYNTAX_ONLY
3838 /* Insert pseudo ops, these have to go into the opcode table since
3839 gas expects pseudo ops to start with a dot */
3840 {
3841 int n = 0;
3842 while (mote_pseudo_table[n].poc_name)
3843 {
3844 hack = (struct m68k_incant *)
3845 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3846 hash_insert (op_hash,
3847 mote_pseudo_table[n].poc_name, (char *) hack);
3848 hack->m_operands = 0;
3849 hack->m_opnum = n;
3850 n++;
3851 }
3852 }
3853 #endif
3854
3855 init_regtable ();
3856 }
3857
3858 #if 0
3859 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3860 || (*s == ':' && strchr("aAdD#", s[1]))) \
3861 ? 0 : 1)
3862 #endif
3863
3864 /* This funciton is called once, before the assembler exits. It is
3865 supposed to do any final cleanup for this part of the assembler.
3866 */
3867 void
3868 md_end ()
3869 {
3870 }
3871
3872 /* Equal to MAX_PRECISION in atof-ieee.c */
3873 #define MAX_LITTLENUMS 6
3874
3875 /* Turn a string in input_line_pointer into a floating point constant of type
3876 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3877 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3878 */
3879 char *
3880 md_atof (type, litP, sizeP)
3881 char type;
3882 char *litP;
3883 int *sizeP;
3884 {
3885 int prec;
3886 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3887 LITTLENUM_TYPE *wordP;
3888 char *t;
3889 char *atof_ieee ();
3890
3891 switch (type)
3892 {
3893 case 'f':
3894 case 'F':
3895 case 's':
3896 case 'S':
3897 prec = 2;
3898 break;
3899
3900 case 'd':
3901 case 'D':
3902 case 'r':
3903 case 'R':
3904 prec = 4;
3905 break;
3906
3907 case 'x':
3908 case 'X':
3909 prec = 6;
3910 break;
3911
3912 case 'p':
3913 case 'P':
3914 prec = 6;
3915 break;
3916
3917 default:
3918 *sizeP = 0;
3919 return "Bad call to MD_ATOF()";
3920 }
3921 t = atof_ieee (input_line_pointer, type, words);
3922 if (t)
3923 input_line_pointer = t;
3924
3925 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3926 for (wordP = words; prec--;)
3927 {
3928 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3929 litP += sizeof (LITTLENUM_TYPE);
3930 }
3931 return 0;
3932 }
3933
3934 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3935 for use in the a.out file, and stores them in the array pointed to by buf.
3936 This knows about the endian-ness of the target machine and does
3937 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3938 2 (short) and 4 (long) Floating numbers are put out as a series of
3939 LITTLENUMS (shorts, here at least)
3940 */
3941 void
3942 md_number_to_chars (buf, val, n)
3943 char *buf;
3944 valueT val;
3945 int n;
3946 {
3947 switch (n)
3948 {
3949 case 1:
3950 *buf++ = val;
3951 break;
3952 case 2:
3953 *buf++ = (val >> 8);
3954 *buf++ = val;
3955 break;
3956 case 4:
3957 *buf++ = (val >> 24);
3958 *buf++ = (val >> 16);
3959 *buf++ = (val >> 8);
3960 *buf++ = val;
3961 break;
3962 default:
3963 as_fatal ("failed sanity check.");
3964 }
3965 }
3966
3967 static void
3968 md_apply_fix_2 (fixP, val)
3969 fixS *fixP;
3970 long val;
3971 {
3972 unsigned long upper_limit;
3973 long lower_limit;
3974
3975 #ifdef IBM_COMPILER_SUX
3976 /* This is unnecessary but it convinces the native rs6000
3977 compiler to generate the code we want. */
3978 char *buf = fixP->fx_frag->fr_literal;
3979 buf += fixP->fx_where;
3980 #else /* IBM_COMPILER_SUX */
3981 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3982 #endif /* IBM_COMPILER_SUX */
3983
3984 switch (fixP->fx_size)
3985 {
3986 case 1:
3987 *buf++ = val;
3988 upper_limit = 0x7f;
3989 lower_limit = -0x80;
3990 break;
3991 case 2:
3992 *buf++ = (val >> 8);
3993 *buf++ = val;
3994 upper_limit = 0x7fff;
3995 lower_limit = -0x8000;
3996 break;
3997 case 4:
3998 *buf++ = (val >> 24);
3999 *buf++ = (val >> 16);
4000 *buf++ = (val >> 8);
4001 *buf++ = val;
4002 upper_limit = 0x7fffffff;
4003 lower_limit = -0x80000000;
4004 break;
4005 default:
4006 BAD_CASE (fixP->fx_size);
4007 }
4008
4009 /* For non-pc-relative values, it's conceivable we might get something
4010 like "0xff" for a byte field. So extend the upper part of the range
4011 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4012 so that we can do any range checking at all. */
4013 if (!fixP->fx_pcrel)
4014 upper_limit = upper_limit * 2 + 1;
4015
4016 if ((unsigned) val > upper_limit && (val > 0 || val < lower_limit))
4017 as_bad ("value out of range");
4018 }
4019
4020 #ifdef BFD_ASSEMBLER
4021 int
4022 md_apply_fix (fixP, valp)
4023 fixS *fixP;
4024 long *valp;
4025 {
4026 md_apply_fix_2 (fixP, *valp);
4027 return 1;
4028 }
4029 #else
4030 void md_apply_fix (fixP, val)
4031 fixS *fixP;
4032 long val;
4033 {
4034 md_apply_fix_2 (fixP, val);
4035 }
4036 #endif
4037
4038 /* *fragP has been relaxed to its final size, and now needs to have
4039 the bytes inside it modified to conform to the new size There is UGLY
4040 MAGIC here. ..
4041 */
4042 void
4043 md_convert_frag_1 (fragP)
4044 register fragS *fragP;
4045 {
4046 long disp;
4047 long ext = 0;
4048
4049 /* Address in object code of the displacement. */
4050 register int object_address = fragP->fr_fix + fragP->fr_address;
4051
4052 #ifdef IBM_COMPILER_SUX
4053 /* This is wrong but it convinces the native rs6000 compiler to
4054 generate the code we want. */
4055 register char *buffer_address = fragP->fr_literal;
4056 buffer_address += fragP->fr_fix;
4057 #else /* IBM_COMPILER_SUX */
4058 /* Address in gas core of the place to store the displacement. */
4059 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4060 #endif /* IBM_COMPILER_SUX */
4061
4062 /* No longer true: know(fragP->fr_symbol); */
4063
4064 /* The displacement of the address, from current location. */
4065 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4066 disp = (disp + fragP->fr_offset) - object_address;
4067
4068 switch (fragP->fr_subtype)
4069 {
4070 case TAB (BCC68000, BYTE):
4071 case TAB (ABRANCH, BYTE):
4072 know (issbyte (disp));
4073 if (disp == 0)
4074 as_bad ("short branch with zero offset: use :w");
4075 fragP->fr_opcode[1] = disp;
4076 ext = 0;
4077 break;
4078 case TAB (DBCC, SHORT):
4079 know (issword (disp));
4080 ext = 2;
4081 break;
4082 case TAB (BCC68000, SHORT):
4083 case TAB (ABRANCH, SHORT):
4084 know (issword (disp));
4085 fragP->fr_opcode[1] = 0x00;
4086 ext = 2;
4087 break;
4088 case TAB (ABRANCH, LONG):
4089 if (cpu_of_arch (current_architecture) < m68020)
4090 {
4091 if (fragP->fr_opcode[0] == 0x61)
4092 {
4093 fragP->fr_opcode[0] = 0x4E;
4094 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */
4095 subseg_change (text_section, 0); /* @@ */
4096
4097 fix_new (fragP,
4098 fragP->fr_fix,
4099 4,
4100 fragP->fr_symbol,
4101 0,
4102 fragP->fr_offset,
4103 0,
4104 NO_RELOC);
4105
4106 fragP->fr_fix += 4;
4107 ext = 0;
4108 }
4109 else if (fragP->fr_opcode[0] == 0x60)
4110 {
4111 fragP->fr_opcode[0] = 0x4E;
4112 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */
4113 subseg_change (text_section, 0); /* @@ */
4114 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0,
4115 NO_RELOC);
4116 fragP->fr_fix += 4;
4117 ext = 0;
4118 }
4119 else
4120 {
4121 as_bad ("Long branch offset not supported.");
4122 }
4123 }
4124 else
4125 {
4126 fragP->fr_opcode[1] = 0xff;
4127 ext = 4;
4128 }
4129 break;
4130 case TAB (BCC68000, LONG):
4131 /* only Bcc 68000 instructions can come here */
4132 /* change bcc into b!cc/jmp absl long */
4133 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4134 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4135
4136 /* JF: these used to be fr_opcode[2,3], but they may be in a
4137 different frag, in which case refering to them is a no-no.
4138 Only fr_opcode[0,1] are guaranteed to work. */
4139 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4140 *buffer_address++ = 0xf9;
4141 fragP->fr_fix += 2; /* account for jmp instruction */
4142 subseg_change (text_section, 0);
4143 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4144 fragP->fr_offset, 0,
4145 NO_RELOC);
4146 fragP->fr_fix += 4;
4147 ext = 0;
4148 break;
4149 case TAB (DBCC, LONG):
4150 /* only DBcc 68000 instructions can come here */
4151 /* change dbcc into dbcc/jmp absl long */
4152 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4153 *buffer_address++ = 0x00; /* branch offset = 4 */
4154 *buffer_address++ = 0x04;
4155 *buffer_address++ = 0x60; /* put in bra pc+6 */
4156 *buffer_address++ = 0x06;
4157 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4158 *buffer_address++ = 0xf9;
4159
4160 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4161 subseg_change (text_section, 0);
4162 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4163 fragP->fr_offset, 0, NO_RELOC);
4164 fragP->fr_fix += 4;
4165 ext = 0;
4166 break;
4167 case TAB (FBRANCH, SHORT):
4168 know ((fragP->fr_opcode[1] & 0x40) == 0);
4169 ext = 2;
4170 break;
4171 case TAB (FBRANCH, LONG):
4172 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4173 ext = 4;
4174 break;
4175 case TAB (PCREL, SHORT):
4176 ext = 2;
4177 break;
4178 case TAB (PCREL, LONG):
4179 /* The thing to do here is force it to ABSOLUTE LONG, since
4180 PCREL is really trying to shorten an ABSOLUTE address anyway */
4181 /* JF FOO This code has not been tested */
4182 subseg_change (text_section, 0);
4183 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,
4184 0, NO_RELOC);
4185 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4186 as_bad ("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
4187 fragP->fr_opcode[0], fragP->fr_address);
4188 fragP->fr_opcode[1] &= ~0x3F;
4189 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4190 fragP->fr_fix += 4;
4191 ext = 0;
4192 break;
4193 case TAB (PCLEA, SHORT):
4194 subseg_change (text_section, 0);
4195 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4196 (symbolS *) 0, fragP->fr_offset, 1, NO_RELOC);
4197 fragP->fr_opcode[1] &= ~0x3F;
4198 fragP->fr_opcode[1] |= 0x3A;
4199 ext = 2;
4200 break;
4201 case TAB (PCLEA, LONG):
4202 subseg_change (text_section, 0);
4203 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4204 (symbolS *) 0, fragP->fr_offset + 2, 1, NO_RELOC);
4205 *buffer_address++ = 0x01;
4206 *buffer_address++ = 0x70;
4207 fragP->fr_fix += 2;
4208 ext = 4;
4209 break;
4210 }
4211
4212 if (ext)
4213 {
4214 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4215 fragP->fr_fix += ext;
4216 }
4217 }
4218
4219 #ifndef BFD_ASSEMBLER
4220
4221 void
4222 md_convert_frag (headers, fragP)
4223 object_headers *headers;
4224 fragS *fragP;
4225 {
4226 md_convert_frag_1 (fragP);
4227 }
4228
4229 #else
4230
4231 void
4232 md_convert_frag (abfd, sec, fragP)
4233 bfd *abfd;
4234 asection sec;
4235 fragS *fragP;
4236 {
4237 md_convert_frag_1 (fragP);
4238 }
4239 #endif
4240
4241 /* Force truly undefined symbols to their maximum size, and generally set up
4242 the frag list to be relaxed
4243 */
4244 int
4245 md_estimate_size_before_relax (fragP, segment)
4246 register fragS *fragP;
4247 segT segment;
4248 {
4249 int old_fix;
4250 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4251
4252 old_fix = fragP->fr_fix;
4253
4254 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4255 switch (fragP->fr_subtype)
4256 {
4257
4258 case TAB (ABRANCH, SZ_UNDEF):
4259 {
4260 if ((fragP->fr_symbol != NULL) /* Not absolute */
4261 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4262 {
4263 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4264 break;
4265 }
4266 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4267 {
4268 /* On 68000, or for absolute value, switch to abs long */
4269 /* FIXME, we should check abs val, pick short or long */
4270 if (fragP->fr_opcode[0] == 0x61)
4271 {
4272 fragP->fr_opcode[0] = 0x4E;
4273 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */
4274 subseg_change (text_section, 0);
4275 fix_new (fragP, fragP->fr_fix, 4,
4276 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4277 fragP->fr_fix += 4;
4278 frag_wane (fragP);
4279 }
4280 else if (fragP->fr_opcode[0] == 0x60)
4281 {
4282 fragP->fr_opcode[0] = 0x4E;
4283 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */
4284 subseg_change (text_section, 0);
4285 fix_new (fragP, fragP->fr_fix, 4,
4286 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4287 fragP->fr_fix += 4;
4288 frag_wane (fragP);
4289 }
4290 else
4291 {
4292 as_warn ("Long branch offset to extern symbol not supported.");
4293 }
4294 }
4295 else
4296 { /* Symbol is still undefined. Make it simple */
4297 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4298 (symbolS *) 0, fragP->fr_offset + 4, 1, NO_RELOC);
4299 fragP->fr_fix += 4;
4300 fragP->fr_opcode[1] = 0xff;
4301 frag_wane (fragP);
4302 break;
4303 }
4304
4305 break;
4306 } /* case TAB(ABRANCH,SZ_UNDEF) */
4307
4308 case TAB (FBRANCH, SZ_UNDEF):
4309 {
4310 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4311 {
4312 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4313 fragP->fr_var += 2;
4314 }
4315 else
4316 {
4317 fragP->fr_subtype = TAB (FBRANCH, LONG);
4318 fragP->fr_var += 4;
4319 }
4320 break;
4321 } /* TAB(FBRANCH,SZ_UNDEF) */
4322
4323 case TAB (PCREL, SZ_UNDEF):
4324 {
4325 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4326 {
4327 fragP->fr_subtype = TAB (PCREL, SHORT);
4328 fragP->fr_var += 2;
4329 }
4330 else
4331 {
4332 fragP->fr_subtype = TAB (PCREL, LONG);
4333 fragP->fr_var += 4;
4334 }
4335 break;
4336 } /* TAB(PCREL,SZ_UNDEF) */
4337
4338 case TAB (BCC68000, SZ_UNDEF):
4339 {
4340 if ((fragP->fr_symbol != NULL)
4341 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4342 {
4343 fragP->fr_subtype = TAB (BCC68000, BYTE);
4344 break;
4345 }
4346 /* only Bcc 68000 instructions can come here */
4347 /* change bcc into b!cc/jmp absl long */
4348 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4349 if (flagseen['l'])
4350 {
4351 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4352 /* JF: these were fr_opcode[2,3] */
4353 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4354 buffer_address[1] = 0xf8;
4355 fragP->fr_fix += 2; /* account for jmp instruction */
4356 subseg_change (text_section, 0);
4357 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
4358 fragP->fr_offset, 0, NO_RELOC);
4359 fragP->fr_fix += 2;
4360 }
4361 else
4362 {
4363 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4364 /* JF: these were fr_opcode[2,3] */
4365 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4366 buffer_address[1] = 0xf9;
4367 fragP->fr_fix += 2; /* account for jmp instruction */
4368 subseg_change (text_section, 0);
4369 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4370 fragP->fr_offset, 0, NO_RELOC);
4371 fragP->fr_fix += 4;
4372 }
4373 frag_wane (fragP);
4374 break;
4375 } /* case TAB(BCC68000,SZ_UNDEF) */
4376
4377 case TAB (DBCC, SZ_UNDEF):
4378 {
4379 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4380 {
4381 fragP->fr_subtype = TAB (DBCC, SHORT);
4382 fragP->fr_var += 2;
4383 break;
4384 }
4385 /* only DBcc 68000 instructions can come here */
4386 /* change dbcc into dbcc/jmp absl long */
4387 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4388 buffer_address[0] = 0x00; /* branch offset = 4 */
4389 buffer_address[1] = 0x04;
4390 buffer_address[2] = 0x60; /* put in bra pc + ... */
4391
4392 if (flagseen['l'])
4393 {
4394 /* JF: these were fr_opcode[5-7] */
4395 buffer_address[3] = 0x04; /* plus 4 */
4396 buffer_address[4] = 0x4e; /* Put in Jump Word */
4397 buffer_address[5] = 0xf8;
4398 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4399 subseg_change (text_section, 0);
4400 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
4401
4402
4403 fragP->fr_offset, 0, NO_RELOC);
4404 fragP->fr_fix += 2;
4405 }
4406 else
4407 {
4408 /* JF: these were fr_opcode[5-7] */
4409 buffer_address[3] = 0x06; /* Plus 6 */
4410 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4411 buffer_address[5] = 0xf9;
4412 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4413 subseg_change (text_section, 0);
4414 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4415 fragP->fr_offset, 0, NO_RELOC);
4416 fragP->fr_fix += 4;
4417 }
4418
4419 frag_wane (fragP);
4420 break;
4421 } /* case TAB(DBCC,SZ_UNDEF) */
4422
4423 case TAB (PCLEA, SZ_UNDEF):
4424 {
4425 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l'])
4426 {
4427 fragP->fr_subtype = TAB (PCLEA, SHORT);
4428 fragP->fr_var += 2;
4429 }
4430 else
4431 {
4432 fragP->fr_subtype = TAB (PCLEA, LONG);
4433 fragP->fr_var += 6;
4434 }
4435 break;
4436 } /* TAB(PCLEA,SZ_UNDEF) */
4437
4438 default:
4439 break;
4440
4441 } /* switch on subtype looking for SZ_UNDEF's. */
4442
4443 /* now that SZ_UNDEF are taken care of, check others */
4444 switch (fragP->fr_subtype)
4445 {
4446 case TAB (BCC68000, BYTE):
4447 case TAB (ABRANCH, BYTE):
4448 /* We can't do a short jump to the next instruction,
4449 so we force word mode. */
4450 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4451 fragP->fr_symbol->sy_frag == fragP->fr_next)
4452 {
4453 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4454 fragP->fr_var += 2;
4455 }
4456 break;
4457 default:
4458 break;
4459 }
4460 return fragP->fr_var + fragP->fr_fix - old_fix;
4461 }
4462
4463 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4464 /* the bit-field entries in the relocation_info struct plays hell
4465 with the byte-order problems of cross-assembly. So as a hack,
4466 I added this mach. dependent ri twiddler. Ugly, but it gets
4467 you there. -KWK */
4468 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4469 are symbolnum, most sig. byte first. Last byte is broken up with
4470 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4471 nibble as nuthin. (on Sun 3 at least) */
4472 /* Translate the internal relocation information into target-specific
4473 format. */
4474 #ifdef comment
4475 void
4476 md_ri_to_chars (the_bytes, ri)
4477 char *the_bytes;
4478 struct reloc_info_generic *ri;
4479 {
4480 /* this is easy */
4481 md_number_to_chars (the_bytes, ri->r_address, 4);
4482 /* now the fun stuff */
4483 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4484 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4485 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4486 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4487 ((ri->r_extern << 4) & 0x10));
4488 }
4489
4490 #endif /* comment */
4491
4492 #ifndef BFD_ASSEMBLER
4493 void
4494 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4495 char *where;
4496 fixS *fixP;
4497 relax_addressT segment_address_in_file;
4498 {
4499 /*
4500 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4501 * Out: GNU LD relocation length code: 0, 1, or 2.
4502 */
4503
4504 static CONST unsigned char nbytes_r_length[] =
4505 {42, 0, 1, 42, 2};
4506 long r_symbolnum;
4507
4508 know (fixP->fx_addsy != NULL);
4509
4510 md_number_to_chars (where,
4511 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4512 4);
4513
4514 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4515 ? S_GET_TYPE (fixP->fx_addsy)
4516 : fixP->fx_addsy->sy_number);
4517
4518 where[4] = (r_symbolnum >> 16) & 0x0ff;
4519 where[5] = (r_symbolnum >> 8) & 0x0ff;
4520 where[6] = r_symbolnum & 0x0ff;
4521 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4522 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4523
4524 return;
4525 }
4526 #endif
4527
4528 #endif /* OBJ_AOUT or OBJ_BOUT */
4529
4530 #ifndef WORKING_DOT_WORD
4531 CONST int md_short_jump_size = 4;
4532 CONST int md_long_jump_size = 6;
4533
4534 void
4535 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4536 char *ptr;
4537 addressT from_addr, to_addr;
4538 fragS *frag;
4539 symbolS *to_symbol;
4540 {
4541 valueT offset;
4542
4543 offset = to_addr - (from_addr + 2);
4544
4545 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4546 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4547 }
4548
4549 void
4550 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4551 char *ptr;
4552 addressT from_addr, to_addr;
4553 fragS *frag;
4554 symbolS *to_symbol;
4555 {
4556 valueT offset;
4557
4558 if (cpu_of_arch (current_architecture) < m68020)
4559 {
4560 offset = to_addr - S_GET_VALUE (to_symbol);
4561 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4562 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4563 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (symbolS *) 0, (long) 0, 0,
4564 NO_RELOC);
4565 }
4566 else
4567 {
4568 offset = to_addr - (from_addr + 2);
4569 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4570 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4571 }
4572 }
4573
4574 #endif
4575 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4576
4577 0: Everything is OK
4578 10: Absolute 1:8 only
4579 20: Absolute 0:7 only
4580 30: absolute 0:15 only
4581 40: Absolute 0:31 only
4582 50: absolute 0:127 only
4583 55: absolute -64:63 only
4584 60: absolute -128:127 only
4585 70: absolute 0:4095 only
4586 80: No bignums
4587
4588 */
4589
4590 static int
4591 get_num (exp, ok)
4592 struct m68k_exp *exp;
4593 int ok;
4594 {
4595 #ifdef TEST2
4596 long l = 0;
4597
4598 if (!exp->e_beg)
4599 return 0;
4600 if (*exp->e_beg == '0')
4601 {
4602 if (exp->e_beg[1] == 'x')
4603 sscanf (exp->e_beg + 2, "%x", &l);
4604 else
4605 sscanf (exp->e_beg + 1, "%O", &l);
4606 return l;
4607 }
4608 return atol (exp->e_beg);
4609 #else
4610 char *save_in;
4611 char c_save;
4612 segT section;
4613
4614 if (!exp)
4615 {
4616 /* Can't do anything */
4617 return 0;
4618 }
4619 if (!exp->e_beg || !exp->e_end)
4620 {
4621 seg (exp) = absolute_section;
4622 adds (exp) = 0;
4623 subs (exp) = 0;
4624 offs (exp) = (ok == 10) ? 1 : 0;
4625 as_warn ("Null expression defaults to %ld", offs (exp));
4626 return 0;
4627 }
4628
4629 exp->e_siz = 0;
4630 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4631 && (exp->e_end - exp->e_beg) >= 2)
4632 {
4633 switch (exp->e_end[0])
4634 {
4635 case 's':
4636 case 'S':
4637 case 'b':
4638 case 'B':
4639 exp->e_siz = 1;
4640 exp->e_end -= 2;
4641 break;
4642 case 'w':
4643 case 'W':
4644 exp->e_siz = 2;
4645 exp->e_end -= 2;
4646 break;
4647 case 'l':
4648 case 'L':
4649 exp->e_siz = 3;
4650 exp->e_end -= 2;
4651 break;
4652 default:
4653 if (exp->e_end[-1] == ':')
4654 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4655 break;
4656 }
4657 }
4658 c_save = exp->e_end[1];
4659 exp->e_end[1] = '\0';
4660 save_in = input_line_pointer;
4661 input_line_pointer = exp->e_beg;
4662 section = expression (&exp->e_exp);
4663 if (section == pass1_section)
4664 {
4665 seg (exp) = absolute_section;
4666 adds (exp) = 0;
4667 subs (exp) = 0;
4668 offs (exp) = (ok == 10) ? 1 : 0;
4669 as_warn ("Unknown expression: '%s' defaulting to %d", exp->e_beg, offs (exp));
4670 }
4671 else if (section == absent_section)
4672 {
4673 /* Do the same thing the VAX asm does */
4674 seg (exp) = absolute_section;
4675 adds (exp) = 0;
4676 subs (exp) = 0;
4677 offs (exp) = 0;
4678 if (ok == 10)
4679 {
4680 as_warn ("expression out of range: defaulting to 1");
4681 offs (exp) = 1;
4682 }
4683 }
4684 else if (section == absolute_section)
4685 {
4686 switch (ok)
4687 {
4688 case 10:
4689 if (offs (exp) < 1 || offs (exp) > 8)
4690 {
4691 as_warn ("expression out of range: defaulting to 1");
4692 offs (exp) = 1;
4693 }
4694 break;
4695 case 20:
4696 if (offs (exp) < 0 || offs (exp) > 7)
4697 goto outrange;
4698 break;
4699 case 30:
4700 if (offs (exp) < 0 || offs (exp) > 15)
4701 goto outrange;
4702 break;
4703 case 40:
4704 if (offs (exp) < 0 || offs (exp) > 32)
4705 goto outrange;
4706 break;
4707 case 50:
4708 if (offs (exp) < 0 || offs (exp) > 127)
4709 goto outrange;
4710 break;
4711 case 55:
4712 if (offs (exp) < -64 || offs (exp) > 63)
4713 goto outrange;
4714 break;
4715 case 60:
4716 if (offs (exp) < -128 || offs (exp) > 127)
4717 goto outrange;
4718 break;
4719 case 70:
4720 if (offs (exp) < 0 || offs (exp) > 4095)
4721 {
4722 outrange:
4723 as_warn ("expression out of range: defaulting to 0");
4724 offs (exp) = 0;
4725 }
4726 break;
4727 default:
4728 break;
4729 }
4730 }
4731 else if (section == big_section)
4732 {
4733 if (offs (exp) < 0 /* flonum */
4734 && (ok == 80 /* no bignums */
4735 || (ok > 10 /* small-int ranges including 0 ok */
4736 /* If we have a flonum zero, a zero integer should
4737 do as well (e.g., in moveq). */
4738 && generic_floating_point_number.exponent == 0
4739 && generic_floating_point_number.low[0] == 0)))
4740 {
4741 /* HACK! Turn it into a long */
4742 LITTLENUM_TYPE words[6];
4743
4744 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4745 seg (exp) = absolute_section;
4746 adds (exp) = 0;
4747 subs (exp) = 0;
4748 offs (exp) = words[1] | (words[0] << 16);
4749 }
4750 else if (ok != 0)
4751 {
4752 seg (exp) = absolute_section;
4753 adds (exp) = 0;
4754 subs (exp) = 0;
4755 offs (exp) = (ok == 10) ? 1 : 0;
4756 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4757 }
4758 }
4759 else
4760 {
4761 if (ok >= 10 && ok <= 70)
4762 {
4763 seg (exp) = absolute_section;
4764 adds (exp) = 0;
4765 subs (exp) = 0;
4766 offs (exp) = (ok == 10) ? 1 : 0;
4767 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4768 }
4769 }
4770
4771 if (input_line_pointer != exp->e_end + 1)
4772 as_bad ("Ignoring junk after expression");
4773 exp->e_end[1] = c_save;
4774 input_line_pointer = save_in;
4775 if (exp->e_siz)
4776 {
4777 switch (exp->e_siz)
4778 {
4779 case 1:
4780 if (!isbyte (offs (exp)))
4781 as_warn ("expression doesn't fit in BYTE");
4782 break;
4783 case 2:
4784 if (!isword (offs (exp)))
4785 as_warn ("expression doesn't fit in WORD");
4786 break;
4787 }
4788 }
4789 return offs (exp);
4790 #endif
4791 }
4792
4793 /* These are the back-ends for the various machine dependent pseudo-ops. */
4794 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4795
4796 static void
4797 s_data1 ()
4798 {
4799 subseg_new (data_section, 1);
4800 demand_empty_rest_of_line ();
4801 }
4802
4803 static void
4804 s_data2 ()
4805 {
4806 subseg_new (data_section, 2);
4807 demand_empty_rest_of_line ();
4808 }
4809
4810 static void
4811 s_bss ()
4812 {
4813 /* We don't support putting frags in the BSS segment, we fake it
4814 by marking in_bss, then looking at s_skip for clues. */
4815
4816 subseg_new (bss_section, 0);
4817 demand_empty_rest_of_line ();
4818 }
4819
4820 static void
4821 s_even ()
4822 {
4823 register int temp;
4824 register long temp_fill;
4825
4826 temp = 1; /* JF should be 2? */
4827 temp_fill = get_absolute_expression ();
4828 if (!need_pass_2) /* Never make frag if expect extra pass. */
4829 frag_align (temp, (int) temp_fill);
4830 demand_empty_rest_of_line ();
4831 }
4832
4833 static void
4834 s_proc ()
4835 {
4836 demand_empty_rest_of_line ();
4837 }
4838
4839 /* s_space is defined in read.c .skip is simply an alias to it. */
4840
4841 /*
4842 * md_parse_option
4843 * Invocation line includes a switch not recognized by the base assembler.
4844 * See if it's a processor-specific option. These are:
4845 *
4846 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4847 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4848 * Select the architecture. Instructions or features not
4849 * supported by the selected architecture cause fatal
4850 * errors. More than one may be specified. The default is
4851 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4852 * for -m68000, and -m68882 is a synonym for -m68881.
4853 * -[A]m[c]no-68851, -[A]m[c]no-68881
4854 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4855 * so don't use or document it, but that's the way the parsing
4856 * works).
4857 *
4858 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4859 * (e.g. m68020) also requests that float instructions be included. This
4860 * is the default setup, mostly to avoid hassling users. A better
4861 * rearrangement of this structure would be to add an option to DENY
4862 * floating point opcodes, for people who want to really know there's none
4863 * of that funny floaty stuff going on. FIXME-later.
4864 */
4865 #ifndef MAYBE_FLOAT_TOO
4866 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4867 #endif
4868
4869 int
4870 md_parse_option (argP, cntP, vecP)
4871 char **argP;
4872 int *cntP;
4873 char ***vecP;
4874 {
4875 switch (**argP)
4876 {
4877 case 'l': /* -l means keep external to 2 bit offset
4878 rather than 16 bit one */
4879 break;
4880
4881 case 'S': /* -S means that jbsr's always turn into
4882 jsr's. */
4883 break;
4884
4885 case 'A':
4886 (*argP)++;
4887 /* intentional fall-through */
4888 case 'm':
4889 (*argP)++;
4890
4891 if (**argP == 'c')
4892 {
4893 (*argP)++;
4894 } /* allow an optional "c" */
4895
4896 if (!strcmp (*argP, "68000")
4897 || !strcmp (*argP, "68008")
4898 || !strcmp (*argP, "68302"))
4899 {
4900 current_architecture |= m68000;
4901 }
4902 else if (!strcmp (*argP, "68010"))
4903 {
4904 #ifdef TE_SUN
4905 omagic = 1 << 16 | OMAGIC;
4906 #endif
4907 current_architecture |= m68010;
4908 }
4909 else if (!strcmp (*argP, "68020"))
4910 {
4911 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
4912 }
4913 else if (!strcmp (*argP, "68030"))
4914 {
4915 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
4916 }
4917 else if (!strcmp (*argP, "68040"))
4918 {
4919 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
4920 }
4921 #ifndef NO_68881
4922 else if (!strcmp (*argP, "68881"))
4923 {
4924 current_architecture |= m68881;
4925 }
4926 else if (!strcmp (*argP, "68882"))
4927 {
4928 current_architecture |= m68882;
4929 }
4930 #endif /* NO_68881 */
4931 /* Even if we aren't configured to support the processor,
4932 it should still be possible to assert that the user
4933 doesn't have it... */
4934 else if (!strcmp (*argP, "no-68881")
4935 || !strcmp (*argP, "no-68882"))
4936 {
4937 no_68881 = 1;
4938 }
4939 #ifndef NO_68851
4940 else if (!strcmp (*argP, "68851"))
4941 {
4942 current_architecture |= m68851;
4943 }
4944 #endif /* NO_68851 */
4945 else if (!strcmp (*argP, "no-68851"))
4946 {
4947 no_68851 = 1;
4948 }
4949 else if (!strcmp (*argP, "pu32") /* "cpu32" minus 'c' */
4950 || !strcmp (*argP, "68331")
4951 || !strcmp (*argP, "68332")
4952 || !strcmp (*argP, "68333")
4953 || !strcmp (*argP, "68340"))
4954 {
4955 current_architecture |= cpu32;
4956 }
4957 else
4958 {
4959 as_warn ("Unknown architecture, \"%s\". option ignored", *argP);
4960 } /* switch on architecture */
4961
4962 while (**argP)
4963 (*argP)++;
4964
4965 break;
4966
4967 case 'p':
4968 if (!strcmp (*argP, "pic"))
4969 {
4970 (*argP) += 3;
4971 break; /* -pic, Position Independent Code */
4972 }
4973 else
4974 {
4975 return 0;
4976 } /* pic or not */
4977
4978 default:
4979 return 0;
4980 }
4981 return 1;
4982 }
4983
4984
4985 #ifdef TEST2
4986
4987 /* TEST2: Test md_assemble() */
4988 /* Warning, this routine probably doesn't work anymore */
4989
4990 main ()
4991 {
4992 struct m68k_it the_ins;
4993 char buf[120];
4994 char *cp;
4995 int n;
4996
4997 m68k_ip_begin ();
4998 for (;;)
4999 {
5000 if (!gets (buf) || !*buf)
5001 break;
5002 if (buf[0] == '|' || buf[1] == '.')
5003 continue;
5004 for (cp = buf; *cp; cp++)
5005 if (*cp == '\t')
5006 *cp = ' ';
5007 if (is_label (buf))
5008 continue;
5009 memset (&the_ins, '\0', sizeof (the_ins));
5010 m68k_ip (&the_ins, buf);
5011 if (the_ins.error)
5012 {
5013 printf ("Error %s in %s\n", the_ins.error, buf);
5014 }
5015 else
5016 {
5017 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5018 for (n = 0; n < the_ins.numo; n++)
5019 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5020 printf (" ");
5021 print_the_insn (&the_ins.opcode[0], stdout);
5022 (void) putchar ('\n');
5023 }
5024 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5025 {
5026 if (the_ins.operands[n].error)
5027 {
5028 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5029 continue;
5030 }
5031 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5032 if (the_ins.operands[n].b_const)
5033 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5034 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5035 if (the_ins.operands[n].b_iadd)
5036 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5037 (void) putchar ('\n');
5038 }
5039 }
5040 m68k_ip_end ();
5041 return 0;
5042 }
5043
5044 is_label (str)
5045 char *str;
5046 {
5047 while (*str == ' ')
5048 str++;
5049 while (*str && *str != ' ')
5050 str++;
5051 if (str[-1] == ':' || str[1] == '=')
5052 return 1;
5053 return 0;
5054 }
5055
5056 #endif
5057
5058 /* Possible states for relaxation:
5059
5060 0 0 branch offset byte (bra, etc)
5061 0 1 word
5062 0 2 long
5063
5064 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5065 1 1 word
5066 1 2 long
5067
5068 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5069 2 1 word-long
5070 2 2 long-word
5071 2 3 long-long
5072
5073 */
5074
5075 /* We have no need to default values of symbols. */
5076
5077 /* ARGSUSED */
5078 symbolS *
5079 md_undefined_symbol (name)
5080 char *name;
5081 {
5082 return 0;
5083 }
5084
5085 /* Parse an operand that is machine-specific.
5086 We just return without modifying the expression if we have nothing
5087 to do. */
5088
5089 /* ARGSUSED */
5090 void
5091 md_operand (expressionP)
5092 expressionS *expressionP;
5093 {
5094 }
5095
5096 /* Round up a section size to the appropriate boundary. */
5097 valueT
5098 md_section_align (segment, size)
5099 segT segment;
5100 valueT size;
5101 {
5102 return size; /* Byte alignment is fine */
5103 }
5104
5105 /* Exactly what point is a PC-relative offset relative TO?
5106 On the 68k, they're relative to the address of the offset, plus
5107 its size. (??? Is this right? FIXME-SOON!) */
5108 long
5109 md_pcrel_from (fixP)
5110 fixS *fixP;
5111 {
5112 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
5113 }
5114
5115 #ifndef BFD_ASSEMBLER
5116 void
5117 tc_coff_symbol_emit_hook ()
5118 {
5119 }
5120
5121 int
5122 tc_coff_sizemachdep (frag)
5123 fragS *frag;
5124 {
5125 switch (frag->fr_subtype & 0x3)
5126 {
5127 case BYTE:
5128 return 1;
5129 case SHORT:
5130 return 2;
5131 case LONG:
5132 return 4;
5133 default:
5134 abort ();
5135 }
5136 }
5137 #endif
5138
5139 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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