1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs
; /* -l option. */
80 static int flag_long_jumps
; /* -S option. */
81 static int flag_keep_pcrel
; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
86 int flag_reg_prefix_optional
;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen
;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum
= COP1
;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd
;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick
= 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32
= 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline
;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line
*next
;
127 /* The list of labels. */
129 static struct label_line
*labels
;
131 /* The current label. */
133 static struct label_line
*current_label
;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn
;
144 const char *m_operands
;
145 unsigned long m_opcode
;
149 struct m68k_incant
*m_next
;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl
[] = { 0 };
156 static const enum m68k_register m68010_ctrl
[] = {
160 static const enum m68k_register m68020_ctrl
[] = {
161 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
164 static const enum m68k_register m68040_ctrl
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
166 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
169 static const enum m68k_register m68060_ctrl
[] = {
170 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
171 USP
, VBR
, URP
, SRP
, PCR
,
174 static const enum m68k_register mcf_ctrl
[] = {
175 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
176 RAMBAR0
, RAMBAR1
, MBAR
,
179 static const enum m68k_register mcf5208_ctrl
[] = {
180 CACR
, ACR0
, ACR1
, VBR
, RAMBAR1
,
183 static const enum m68k_register mcf5213_ctrl
[] = {
184 VBR
, RAMBAR
, FLASHBAR
,
187 static const enum m68k_register mcf5216_ctrl
[] = {
188 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
,
191 static const enum m68k_register mcf5235_ctrl
[] = {
192 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
195 static const enum m68k_register mcf5249_ctrl
[] = {
196 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, MBAR
, MBAR2
,
199 static const enum m68k_register mcf5250_ctrl
[] = {
203 static const enum m68k_register mcf5271_ctrl
[] = {
204 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
207 static const enum m68k_register mcf5272_ctrl
[] = {
208 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, MBAR
,
211 static const enum m68k_register mcf5275_ctrl
[] = {
212 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
215 static const enum m68k_register mcf5282_ctrl
[] = {
216 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
,
219 static const enum m68k_register mcf5329_ctrl
[] = {
220 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
223 static const enum m68k_register mcf5373_ctrl
[] = {
224 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
227 static const enum m68k_register mcfv4e_ctrl
[] = {
228 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
, VBR
, PC
, ROMBAR
,
229 ROMBAR1
, RAMBAR0
, RAMBAR1
, MPCR
, EDRAMBAR
, SECMBAR
, MBAR
, MBAR0
, MBAR1
,
230 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
231 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
234 #define cpu32_ctrl m68010_ctrl
236 static const enum m68k_register
*control_regs
;
238 /* Internal form of a 68020 instruction. */
242 const char *args
; /* List of opcode info. */
245 int numo
; /* Number of shorts in opcode. */
248 struct m68k_op operands
[6];
250 int nexp
; /* Number of exprs in use. */
251 struct m68k_exp exprs
[4];
253 int nfrag
; /* Number of frags we have to produce. */
256 int fragoff
; /* Where in the current opcode the frag ends. */
263 int nrel
; /* Num of reloc strucs in use. */
270 /* In a pc relative address the difference between the address
271 of the offset and the address that the offset is relative
272 to. This depends on the addressing mode. Basically this
273 is the value to put in the offset field to address the
274 first byte of the offset, without regarding the special
275 significance of some values (in the branch instruction, for
279 /* Whether this expression needs special pic relocation, and if
281 enum pic_relocation pic_reloc
;
284 reloc
[5]; /* Five is enough??? */
287 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
288 #define float_of_arch(x) ((x) & mfloat)
289 #define mmu_of_arch(x) ((x) & mmmu)
290 #define arch_coldfire_p(x) ((x) & mcfisa_a)
291 #define arch_coldfire_fpu(x) ((x) & cfloat)
293 /* Macros for determining if cpu supports a specific addressing mode. */
294 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
296 static struct m68k_it the_ins
; /* The instruction being assembled. */
298 #define op(ex) ((ex)->exp.X_op)
299 #define adds(ex) ((ex)->exp.X_add_symbol)
300 #define subs(ex) ((ex)->exp.X_op_symbol)
301 #define offs(ex) ((ex)->exp.X_add_number)
303 /* Macros for adding things to the m68k_it struct. */
304 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
306 /* Like addword, but goes BEFORE general operands. */
309 insop (int w
, const struct m68k_incant
*opcode
)
312 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
313 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
314 for (z
= 0; z
< the_ins
.nrel
; z
++)
315 the_ins
.reloc
[z
].n
+= 2;
316 for (z
= 0; z
< the_ins
.nfrag
; z
++)
317 the_ins
.fragb
[z
].fragoff
++;
318 the_ins
.opcode
[opcode
->m_codenum
] = w
;
322 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
325 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
327 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
328 ? the_ins
.numo
* 2 - 1
330 ? the_ins
.numo
* 2 + 1
331 : the_ins
.numo
* 2));
332 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
333 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
334 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
336 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
338 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
341 /* Cause an extra frag to be generated here, inserting up to 10 bytes
342 (that value is chosen in the frag_var call in md_assemble). TYPE
343 is the subtype of the frag to be generated; its primary type is
344 rs_machine_dependent.
346 The TYPE parameter is also used by md_convert_frag_1 and
347 md_estimate_size_before_relax. The appropriate type of fixup will
348 be emitted by md_convert_frag_1.
350 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
352 add_frag (symbolS
*add
, offsetT off
, int type
)
354 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
355 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
356 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
357 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
361 (op (ex) != O_constant && op (ex) != O_big)
363 static char *crack_operand (char *str
, struct m68k_op
*opP
);
364 static int get_num (struct m68k_exp
*exp
, int ok
);
365 static int reverse_16_bits (int in
);
366 static int reverse_8_bits (int in
);
367 static void install_gen_operand (int mode
, int val
);
368 static void install_operand (int mode
, int val
);
369 static void s_bss (int);
370 static void s_data1 (int);
371 static void s_data2 (int);
372 static void s_even (int);
373 static void s_proc (int);
374 static void s_chip (int);
375 static void s_fopt (int);
376 static void s_opt (int);
377 static void s_reg (int);
378 static void s_restore (int);
379 static void s_save (int);
380 static void s_mri_if (int);
381 static void s_mri_else (int);
382 static void s_mri_endi (int);
383 static void s_mri_break (int);
384 static void s_mri_next (int);
385 static void s_mri_for (int);
386 static void s_mri_endf (int);
387 static void s_mri_repeat (int);
388 static void s_mri_until (int);
389 static void s_mri_while (int);
390 static void s_mri_endw (int);
391 static void s_m68k_cpu (int);
392 static void s_m68k_arch (int);
396 unsigned long arch
; /* Architecture features. */
397 const enum m68k_register
*control_regs
; /* Control regs on chip */
398 const char *name
; /* Name */
399 int alias
; /* Alias for a cannonical name. If 1, then
400 succeeds canonical name, if -1 then
401 succeeds canonical name, if <-1 ||>1 this is a
402 deprecated name, and the next/previous name
406 /* We hold flags for features explicitly enabled and explicitly
408 static int current_architecture
;
409 static int not_current_architecture
;
410 static const struct m68k_cpu
*selected_arch
;
411 static const struct m68k_cpu
*selected_cpu
;
412 static int initialized
;
414 /* Architecture models. */
415 static const struct m68k_cpu m68k_archs
[] =
417 {m68000
, m68000_ctrl
, "68000", 0},
418 {m68010
, m68010_ctrl
, "68010", 0},
419 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
420 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
421 {m68040
, m68040_ctrl
, "68040", 0},
422 {m68060
, m68060_ctrl
, "68060", 0},
423 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
424 {cpu32
|fido_a
, cpu32_ctrl
, "fidoa", 0},
425 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
426 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
427 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
428 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
429 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
433 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
435 static const struct m68k_cpu m68k_extensions
[] =
437 {m68851
, NULL
, "68851", -1},
438 {m68881
, NULL
, "68881", -1},
439 {m68881
, NULL
, "68882", -1},
441 {cfloat
|m68881
, NULL
, "float", 0},
443 {mcfhwdiv
, NULL
, "div", 1},
444 {mcfusp
, NULL
, "usp", 1},
445 {mcfmac
, NULL
, "mac", 1},
446 {mcfemac
, NULL
, "emac", 1},
452 static const struct m68k_cpu m68k_cpus
[] =
454 {m68000
, m68000_ctrl
, "68000", 0},
455 {m68000
, m68000_ctrl
, "68ec000", 1},
456 {m68000
, m68000_ctrl
, "68hc000", 1},
457 {m68000
, m68000_ctrl
, "68hc001", 1},
458 {m68000
, m68000_ctrl
, "68008", 1},
459 {m68000
, m68000_ctrl
, "68302", 1},
460 {m68000
, m68000_ctrl
, "68306", 1},
461 {m68000
, m68000_ctrl
, "68307", 1},
462 {m68000
, m68000_ctrl
, "68322", 1},
463 {m68000
, m68000_ctrl
, "68356", 1},
464 {m68010
, m68010_ctrl
, "68010", 0},
465 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
466 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
467 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
468 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
469 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
470 {m68040
, m68040_ctrl
, "68040", 0},
471 {m68040
, m68040_ctrl
, "68ec040", 1},
472 {m68060
, m68060_ctrl
, "68060", 0},
473 {m68060
, m68060_ctrl
, "68ec060", 1},
475 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
476 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
477 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
478 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
479 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
480 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
481 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
482 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
483 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
484 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
485 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
487 {mcfisa_a
, mcf_ctrl
, "5200", 0},
488 {mcfisa_a
, mcf_ctrl
, "5202", 1},
489 {mcfisa_a
, mcf_ctrl
, "5204", 1},
490 {mcfisa_a
, mcf_ctrl
, "5206", 1},
492 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5206e", 0},
494 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
495 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
497 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
498 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
499 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
501 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
502 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
503 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
505 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
506 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
507 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
508 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
509 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
511 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
512 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
514 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
515 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
517 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
519 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
520 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
522 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
523 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
524 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
525 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
527 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5307", 0},
529 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
530 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
531 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
532 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
534 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
535 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
536 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
538 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5407",0},
540 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5470", -1},
541 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5471", -1},
542 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5472", -1},
543 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5473", -1},
544 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5474", -1},
545 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5475", -1},
546 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "547x", 0},
548 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5480", -1},
549 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5481", -1},
550 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5482", -1},
551 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5483", -1},
552 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5484", -1},
553 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "5485", -1},
554 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "548x", 0},
556 {cpu32
|fido_a
, cpu32_ctrl
, "fido", 1},
561 static const struct m68k_cpu
*m68k_lookup_cpu
562 (const char *, const struct m68k_cpu
*, int, int *);
563 static int m68k_set_arch (const char *, int, int);
564 static int m68k_set_cpu (const char *, int, int);
565 static int m68k_set_extension (const char *, int, int);
566 static void m68k_init_arch (void);
568 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
569 architecture and we have a lot of relaxation modes. */
571 /* Macros used in the relaxation code. */
572 #define TAB(x,y) (((x) << 2) + (y))
573 #define TABTYPE(x) ((x) >> 2)
575 /* Relaxation states. */
581 /* Here are all the relaxation modes we support. First we can relax ordinary
582 branches. On 68020 and higher and on CPU32 all branch instructions take
583 three forms, so on these CPUs all branches always remain as such. When we
584 have to expand to the LONG form on a 68000, though, we substitute an
585 absolute jump instead. This is a direct replacement for unconditional
586 branches and a branch over a jump for conditional branches. However, if the
587 user requires PIC and disables this with --pcrel, we can only relax between
588 BYTE and SHORT forms, punting if that isn't enough. This gives us four
589 different relaxation modes for branches: */
591 #define BRANCHBWL 0 /* Branch byte, word, or long. */
592 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
593 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
594 #define BRANCHBW 3 /* Branch byte or word. */
596 /* We also relax coprocessor branches and DBcc's. All CPUs that support
597 coprocessor branches support them in word and long forms, so we have only
598 one relaxation mode for them. DBcc's are word only on all CPUs. We can
599 relax them to the LONG form with a branch-around sequence. This sequence
600 can use a long branch (if available) or an absolute jump (if acceptable).
601 This gives us two relaxation modes. If long branches are not available and
602 absolute jumps are not acceptable, we don't relax DBcc's. */
604 #define FBRANCH 4 /* Coprocessor branch. */
605 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
606 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
608 /* That's all for instruction relaxation. However, we also relax PC-relative
609 operands. Specifically, we have three operand relaxation modes. On the
610 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
611 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
612 two. Also PC+displacement+index operands in their simple form (with a non-
613 suppressed index without memory indirection) are supported on all CPUs, but
614 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
615 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
616 form of the PC+displacement+index operand. Finally, some absolute operands
617 can be relaxed down to 16-bit PC-relative. */
619 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
620 #define PCINDEX 8 /* PC + displacement + index. */
621 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
623 /* Note that calls to frag_var need to specify the maximum expansion
624 needed; this is currently 10 bytes for DBCC. */
627 How far Forward this mode will reach:
628 How far Backward this mode will reach:
629 How many bytes this mode will add to the size of the frag
630 Which mode to go to if the offset won't fit in this one
632 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
633 relax_typeS md_relax_table
[] =
635 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
636 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
640 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
641 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
645 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
646 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
650 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
655 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
656 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
660 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
661 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
665 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
666 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
670 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
671 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
675 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
676 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
680 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
681 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
686 /* These are the machine dependent pseudo-ops. These are included so
687 the assembler can work on the output from the SUN C compiler, which
690 /* This table describes all the machine specific pseudo-ops the assembler
691 has to support. The fields are:
692 pseudo-op name without dot
693 function to call to execute this pseudo-op
694 Integer arg to pass to the function. */
695 const pseudo_typeS md_pseudo_table
[] =
697 {"data1", s_data1
, 0},
698 {"data2", s_data2
, 0},
701 {"skip", s_space
, 0},
703 #if defined (TE_SUN3) || defined (OBJ_ELF)
704 {"align", s_align_bytes
, 0},
707 {"swbeg", s_ignore
, 0},
709 {"extend", float_cons
, 'x'},
710 {"ldouble", float_cons
, 'x'},
712 {"arch", s_m68k_arch
, 0},
713 {"cpu", s_m68k_cpu
, 0},
715 /* The following pseudo-ops are supported for MRI compatibility. */
717 {"comline", s_space
, 1},
719 {"mask2", s_ignore
, 0},
722 {"restore", s_restore
, 0},
726 {"if.b", s_mri_if
, 'b'},
727 {"if.w", s_mri_if
, 'w'},
728 {"if.l", s_mri_if
, 'l'},
729 {"else", s_mri_else
, 0},
730 {"else.s", s_mri_else
, 's'},
731 {"else.l", s_mri_else
, 'l'},
732 {"endi", s_mri_endi
, 0},
733 {"break", s_mri_break
, 0},
734 {"break.s", s_mri_break
, 's'},
735 {"break.l", s_mri_break
, 'l'},
736 {"next", s_mri_next
, 0},
737 {"next.s", s_mri_next
, 's'},
738 {"next.l", s_mri_next
, 'l'},
739 {"for", s_mri_for
, 0},
740 {"for.b", s_mri_for
, 'b'},
741 {"for.w", s_mri_for
, 'w'},
742 {"for.l", s_mri_for
, 'l'},
743 {"endf", s_mri_endf
, 0},
744 {"repeat", s_mri_repeat
, 0},
745 {"until", s_mri_until
, 0},
746 {"until.b", s_mri_until
, 'b'},
747 {"until.w", s_mri_until
, 'w'},
748 {"until.l", s_mri_until
, 'l'},
749 {"while", s_mri_while
, 0},
750 {"while.b", s_mri_while
, 'b'},
751 {"while.w", s_mri_while
, 'w'},
752 {"while.l", s_mri_while
, 'l'},
753 {"endw", s_mri_endw
, 0},
758 /* The mote pseudo ops are put into the opcode table, since they
759 don't start with a . they look like opcodes to gas. */
761 const pseudo_typeS mote_pseudo_table
[] =
774 {"xdef", s_globl
, 0},
776 {"align", s_align_bytes
, 0},
778 {"align", s_align_ptwo
, 0},
781 {"sect", obj_coff_section
, 0},
782 {"section", obj_coff_section
, 0},
787 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
788 gives identical results to a 32-bit host. */
789 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
790 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
792 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
793 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
794 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
795 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
797 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
798 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
799 #define islong(x) (1)
801 static char notend_table
[256];
802 static char alt_notend_table
[256];
804 (! (notend_table[(unsigned char) *s] \
806 && alt_notend_table[(unsigned char) s[1]])))
810 /* Return zero if the reference to SYMBOL from within the same segment may
813 /* On an ELF system, we can't relax an externally visible symbol,
814 because it may be overridden by a shared library. However, if
815 TARGET_OS is "elf", then we presume that we are assembling for an
816 embedded system, in which case we don't have to worry about shared
817 libraries, and we can relax any external sym. */
819 #define relaxable_symbol(symbol) \
820 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
821 || S_IS_WEAK (symbol)))
823 /* Compute the relocation code for a fixup of SIZE bytes, using pc
824 relative relocation if PCREL is non-zero. PIC says whether a special
825 pic relocation was requested. */
827 static bfd_reloc_code_real_type
828 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
836 return BFD_RELOC_8_GOT_PCREL
;
838 return BFD_RELOC_16_GOT_PCREL
;
840 return BFD_RELOC_32_GOT_PCREL
;
848 return BFD_RELOC_8_GOTOFF
;
850 return BFD_RELOC_16_GOTOFF
;
852 return BFD_RELOC_32_GOTOFF
;
860 return BFD_RELOC_8_PLT_PCREL
;
862 return BFD_RELOC_16_PLT_PCREL
;
864 return BFD_RELOC_32_PLT_PCREL
;
872 return BFD_RELOC_8_PLTOFF
;
874 return BFD_RELOC_16_PLTOFF
;
876 return BFD_RELOC_32_PLTOFF
;
886 return BFD_RELOC_8_PCREL
;
888 return BFD_RELOC_16_PCREL
;
890 return BFD_RELOC_32_PCREL
;
910 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
912 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
917 as_bad (_("Can not do %d byte relocation"), size
);
919 as_bad (_("Can not do %d byte pic relocation"), size
);
922 return BFD_RELOC_NONE
;
925 /* Here we decide which fixups can be adjusted to make them relative
926 to the beginning of the section instead of the symbol. Basically
927 we need to make sure that the dynamic relocations are done
928 correctly, so in some cases we force the original symbol to be
931 tc_m68k_fix_adjustable (fixS
*fixP
)
933 /* Adjust_reloc_syms doesn't know about the GOT. */
934 switch (fixP
->fx_r_type
)
936 case BFD_RELOC_8_GOT_PCREL
:
937 case BFD_RELOC_16_GOT_PCREL
:
938 case BFD_RELOC_32_GOT_PCREL
:
939 case BFD_RELOC_8_GOTOFF
:
940 case BFD_RELOC_16_GOTOFF
:
941 case BFD_RELOC_32_GOTOFF
:
942 case BFD_RELOC_8_PLT_PCREL
:
943 case BFD_RELOC_16_PLT_PCREL
:
944 case BFD_RELOC_32_PLT_PCREL
:
945 case BFD_RELOC_8_PLTOFF
:
946 case BFD_RELOC_16_PLTOFF
:
947 case BFD_RELOC_32_PLTOFF
:
950 case BFD_RELOC_VTABLE_INHERIT
:
951 case BFD_RELOC_VTABLE_ENTRY
:
961 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
963 #define relaxable_symbol(symbol) 1
968 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
971 bfd_reloc_code_real_type code
;
973 /* If the tcbit is set, then this was a fixup of a negative value
974 that was never resolved. We do not have a reloc to handle this,
975 so just return. We assume that other code will have detected this
976 situation and produced a helpful error message, so we just tell the
977 user that the reloc cannot be produced. */
981 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
982 _("Unable to produce reloc against symbol '%s'"),
983 S_GET_NAME (fixp
->fx_addsy
));
987 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
989 code
= fixp
->fx_r_type
;
991 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
992 that fixup_segment converted a non-PC relative reloc into a
993 PC relative reloc. In such a case, we need to convert the
1000 code
= BFD_RELOC_8_PCREL
;
1003 code
= BFD_RELOC_16_PCREL
;
1006 code
= BFD_RELOC_32_PCREL
;
1008 case BFD_RELOC_8_PCREL
:
1009 case BFD_RELOC_16_PCREL
:
1010 case BFD_RELOC_32_PCREL
:
1011 case BFD_RELOC_8_GOT_PCREL
:
1012 case BFD_RELOC_16_GOT_PCREL
:
1013 case BFD_RELOC_32_GOT_PCREL
:
1014 case BFD_RELOC_8_GOTOFF
:
1015 case BFD_RELOC_16_GOTOFF
:
1016 case BFD_RELOC_32_GOTOFF
:
1017 case BFD_RELOC_8_PLT_PCREL
:
1018 case BFD_RELOC_16_PLT_PCREL
:
1019 case BFD_RELOC_32_PLT_PCREL
:
1020 case BFD_RELOC_8_PLTOFF
:
1021 case BFD_RELOC_16_PLTOFF
:
1022 case BFD_RELOC_32_PLTOFF
:
1025 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1026 _("Cannot make %s relocation PC relative"),
1027 bfd_get_reloc_code_name (code
));
1033 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1034 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1036 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1037 MAP (1, 0, BFD_RELOC_8
);
1038 MAP (2, 0, BFD_RELOC_16
);
1039 MAP (4, 0, BFD_RELOC_32
);
1040 MAP (1, 1, BFD_RELOC_8_PCREL
);
1041 MAP (2, 1, BFD_RELOC_16_PCREL
);
1042 MAP (4, 1, BFD_RELOC_32_PCREL
);
1050 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1051 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1052 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1053 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1056 reloc
->addend
= fixp
->fx_addnumber
;
1060 if (!fixp
->fx_pcrel
)
1061 reloc
->addend
= fixp
->fx_addnumber
;
1063 reloc
->addend
= (section
->vma
1064 /* Explicit sign extension in case char is
1066 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1067 + fixp
->fx_addnumber
1068 + md_pcrel_from (fixp
));
1071 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1072 assert (reloc
->howto
!= 0);
1077 /* Handle of the OPCODE hash table. NULL means any use before
1078 m68k_ip_begin() will crash. */
1079 static struct hash_control
*op_hash
;
1081 /* Assemble an m68k instruction. */
1084 m68k_ip (char *instring
)
1087 register struct m68k_op
*opP
;
1088 register const struct m68k_incant
*opcode
;
1089 register const char *s
;
1090 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1091 char *pdot
, *pdotmove
;
1092 enum m68k_size siz1
, siz2
;
1096 struct m68k_op operands_backup
[6];
1097 LITTLENUM_TYPE words
[6];
1098 LITTLENUM_TYPE
*wordp
;
1099 unsigned long ok_arch
= 0;
1101 if (*instring
== ' ')
1102 instring
++; /* Skip leading whitespace. */
1104 /* Scan up to end of operation-code, which MUST end in end-of-string
1105 or exactly 1 space. */
1107 for (p
= instring
; *p
!= '\0'; p
++)
1117 the_ins
.error
= _("No operator");
1121 /* p now points to the end of the opcode name, probably whitespace.
1122 Make sure the name is null terminated by clobbering the
1123 whitespace, look it up in the hash table, then fix it back.
1124 Remove a dot, first, since the opcode tables have none. */
1127 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1128 *pdotmove
= pdotmove
[1];
1134 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1139 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1140 *pdotmove
= pdotmove
[-1];
1147 the_ins
.error
= _("Unknown operator");
1151 /* Found a legitimate opcode, start matching operands. */
1155 if (opcode
->m_operands
== 0)
1157 char *old
= input_line_pointer
;
1159 input_line_pointer
= p
;
1160 /* Ahh - it's a motorola style psuedo op. */
1161 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1162 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1163 input_line_pointer
= old
;
1169 if (flag_mri
&& opcode
->m_opnum
== 0)
1171 /* In MRI mode, random garbage is allowed after an instruction
1172 which accepts no operands. */
1173 the_ins
.args
= opcode
->m_operands
;
1174 the_ins
.numargs
= opcode
->m_opnum
;
1175 the_ins
.numo
= opcode
->m_codenum
;
1176 the_ins
.opcode
[0] = getone (opcode
);
1177 the_ins
.opcode
[1] = gettwo (opcode
);
1181 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1183 p
= crack_operand (p
, opP
);
1187 the_ins
.error
= opP
->error
;
1192 opsfound
= opP
- &the_ins
.operands
[0];
1194 /* This ugly hack is to support the floating pt opcodes in their
1195 standard form. Essentially, we fake a first enty of type COP#1 */
1196 if (opcode
->m_operands
[0] == 'I')
1200 for (n
= opsfound
; n
> 0; --n
)
1201 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1203 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1204 the_ins
.operands
[0].mode
= CONTROL
;
1205 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1209 /* We've got the operands. Find an opcode that'll accept them. */
1212 /* If we didn't get the right number of ops, or we have no
1213 common model with this pattern then reject this pattern. */
1215 ok_arch
|= opcode
->m_arch
;
1216 if (opsfound
!= opcode
->m_opnum
1217 || ((opcode
->m_arch
& current_architecture
) == 0))
1223 /* Make a copy of the operands of this insn so that
1224 we can modify them safely, should we want to. */
1225 assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1226 for (i
= 0; i
< opsfound
; i
++)
1227 operands_backup
[i
] = the_ins
.operands
[i
];
1229 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1233 /* Warning: this switch is huge! */
1234 /* I've tried to organize the cases into this order:
1235 non-alpha first, then alpha by letter. Lower-case
1236 goes directly before uppercase counterpart. */
1237 /* Code with multiple case ...: gets sorted by the lowest
1238 case ... it belongs to. I hope this makes sense. */
1344 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1361 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1380 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1390 if (opP
->mode
!= IMMED
)
1392 else if (s
[1] == 'b'
1393 && ! isvar (&opP
->disp
)
1394 && (opP
->disp
.exp
.X_op
!= O_constant
1395 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1397 else if (s
[1] == 'B'
1398 && ! isvar (&opP
->disp
)
1399 && (opP
->disp
.exp
.X_op
!= O_constant
1400 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1402 else if (s
[1] == 'w'
1403 && ! isvar (&opP
->disp
)
1404 && (opP
->disp
.exp
.X_op
!= O_constant
1405 || ! isword (opP
->disp
.exp
.X_add_number
)))
1407 else if (s
[1] == 'W'
1408 && ! isvar (&opP
->disp
)
1409 && (opP
->disp
.exp
.X_op
!= O_constant
1410 || ! issword (opP
->disp
.exp
.X_add_number
)))
1416 if (opP
->mode
!= IMMED
)
1421 if (opP
->mode
== AREG
1422 || opP
->mode
== CONTROL
1423 || opP
->mode
== FPREG
1424 || opP
->mode
== IMMED
1425 || opP
->mode
== REGLST
1426 || (opP
->mode
!= ABSL
1428 || opP
->reg
== ZPC
)))
1433 if (opP
->mode
== CONTROL
1434 || opP
->mode
== FPREG
1435 || opP
->mode
== REGLST
1436 || opP
->mode
== IMMED
1437 || (opP
->mode
!= ABSL
1439 || opP
->reg
== ZPC
)))
1467 if (opP
->mode
== CONTROL
1468 || opP
->mode
== FPREG
1469 || opP
->mode
== REGLST
)
1474 if (opP
->mode
!= AINC
)
1479 if (opP
->mode
!= ADEC
)
1529 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1550 case '~': /* For now! (JF FOO is this right?) */
1572 if (opP
->mode
!= CONTROL
1573 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1578 if (opP
->mode
!= AREG
)
1583 if (opP
->mode
!= AINDR
)
1588 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1589 && (opP
->mode
!= DISP
1591 || opP
->reg
> ADDR7
))
1596 if (opP
->mode
!= ABSL
1598 && strncmp (instring
, "jbsr", 4) == 0))
1621 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1626 if (opP
->mode
!= DISP
1628 || opP
->reg
> ADDR7
)
1633 if (opP
->mode
!= DREG
)
1638 if (opP
->reg
!= ACC
)
1643 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1644 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1649 if (opP
->mode
!= FPREG
)
1654 if (opP
->reg
!= MACSR
)
1659 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1664 if (opP
->reg
!= MASK
)
1669 if (opP
->mode
!= CONTROL
1676 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1681 if (opP
->mode
!= CONTROL
1683 || opP
->reg
> last_movec_reg
1688 const enum m68k_register
*rp
;
1690 for (rp
= control_regs
; *rp
; rp
++)
1691 if (*rp
== opP
->reg
)
1699 if (opP
->mode
!= IMMED
)
1705 if (opP
->mode
== DREG
1706 || opP
->mode
== AREG
1707 || opP
->mode
== FPREG
)
1716 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1719 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1722 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1730 else if (opP
->mode
== CONTROL
)
1739 opP
->mask
= 1 << 24;
1742 opP
->mask
= 1 << 25;
1745 opP
->mask
= 1 << 26;
1754 else if (opP
->mode
!= REGLST
)
1756 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1758 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1763 if (opP
->mode
!= IMMED
)
1765 else if (opP
->disp
.exp
.X_op
!= O_constant
1766 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1768 else if (! m68k_quick
1769 && instring
[3] != 'q'
1770 && instring
[4] != 'q')
1775 if (opP
->mode
!= DREG
1776 && opP
->mode
!= IMMED
1777 && opP
->mode
!= ABSL
)
1782 if (opP
->mode
!= IMMED
)
1784 else if (opP
->disp
.exp
.X_op
!= O_constant
1785 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1787 else if (! m68k_quick
1788 && (strncmp (instring
, "add", 3) == 0
1789 || strncmp (instring
, "sub", 3) == 0)
1790 && instring
[3] != 'q')
1795 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1800 if (opP
->mode
!= AINDR
1801 && (opP
->mode
!= BASE
1803 && opP
->reg
!= ZADDR0
)
1804 || opP
->disp
.exp
.X_op
!= O_absent
1805 || ((opP
->index
.reg
< DATA0
1806 || opP
->index
.reg
> DATA7
)
1807 && (opP
->index
.reg
< ADDR0
1808 || opP
->index
.reg
> ADDR7
))
1809 || opP
->index
.size
!= SIZE_UNSPEC
1810 || opP
->index
.scale
!= 1))
1815 if (opP
->mode
!= CONTROL
1816 || ! (opP
->reg
== FPI
1818 || opP
->reg
== FPC
))
1823 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1828 if (opP
->mode
!= IMMED
)
1830 else if (opP
->disp
.exp
.X_op
!= O_constant
1831 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
1836 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1841 if (opP
->mode
!= IMMED
)
1843 else if (opP
->disp
.exp
.X_op
!= O_constant
1844 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
1845 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
1849 /* JF these are out of order. We could put them
1850 in order if we were willing to put up with
1851 bunches of #ifdef m68851s in the code.
1853 Don't forget that you need these operands
1854 to use 68030 MMU instructions. */
1856 /* Memory addressing mode used by pflushr. */
1858 if (opP
->mode
== CONTROL
1859 || opP
->mode
== FPREG
1860 || opP
->mode
== DREG
1861 || opP
->mode
== AREG
1862 || opP
->mode
== REGLST
)
1864 /* We should accept immediate operands, but they
1865 supposedly have to be quad word, and we don't
1866 handle that. I would like to see what a Motorola
1867 assembler does before doing something here. */
1868 if (opP
->mode
== IMMED
)
1873 if (opP
->mode
!= CONTROL
1874 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1879 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1884 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1889 if (opP
->mode
!= CONTROL
1892 && opP
->reg
!= SCC
))
1897 if (opP
->mode
!= CONTROL
1903 if (opP
->mode
!= CONTROL
1906 && opP
->reg
!= CRP
))
1930 if (opP
->mode
!= CONTROL
1931 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1932 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1937 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1942 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1947 if (opP
->mode
!= CONTROL
1956 if (opP
->mode
!= ABSL
)
1961 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
1963 /* FIXME: kludge instead of fixing parser:
1964 upper/lower registers are *not* CONTROL
1965 registers, but ordinary ones. */
1966 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
1967 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
1974 if (!(opP
->mode
== AINDR
1975 || (opP
->mode
== DISP
1976 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
1981 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
1993 /* Since we have found the correct instruction, copy
1994 in the modifications that we may have made. */
1996 for (i
= 0; i
< opsfound
; i
++)
1997 the_ins
.operands
[i
] = operands_backup
[i
];
2003 opcode
= opcode
->m_next
;
2008 && !(ok_arch
& current_architecture
))
2010 const struct m68k_cpu
*cpu
;
2013 char *buf
= xmalloc (space
+ 1);
2017 the_ins
.error
= buf
;
2018 /* Make sure there's a NUL at the end of the buffer -- strncpy
2019 won't write one when it runs out of buffer */
2021 #define APPEND(STRING) \
2022 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2024 APPEND (_("invalid instruction for this architecture; needs "));
2028 APPEND (_("ColdFire ISA_A"));
2031 APPEND (_("ColdFire hardware divide"));
2034 APPEND (_("ColdFire ISA_A+"));
2037 APPEND (_("ColdFire ISA_B"));
2040 APPEND (_("ColdFire fpu"));
2043 APPEND (_("M68K fpu"));
2046 APPEND (_("M68K mmu"));
2049 APPEND (_("68020 or higher"));
2052 APPEND (_("68000 or higher"));
2055 APPEND (_("68010 or higher"));
2063 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2064 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2066 const struct m68k_cpu
*alias
;
2067 int seen_master
= 0;
2073 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2074 if (alias
[-1].alias
>= 0)
2076 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2086 APPEND (alias
->name
);
2099 /* we ran out of space, so replace the end of the list
2104 strcpy (buf
, " ...");
2108 the_ins
.error
= _("operands mismatch");
2115 /* Now assemble it. */
2116 the_ins
.args
= opcode
->m_operands
;
2117 the_ins
.numargs
= opcode
->m_opnum
;
2118 the_ins
.numo
= opcode
->m_codenum
;
2119 the_ins
.opcode
[0] = getone (opcode
);
2120 the_ins
.opcode
[1] = gettwo (opcode
);
2122 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2124 /* This switch is a doozy.
2125 Watch the first step; its a big one! */
2158 tmpreg
= 0x3c; /* 7.4 */
2159 if (strchr ("bwl", s
[1]))
2160 nextword
= get_num (&opP
->disp
, 90);
2162 nextword
= get_num (&opP
->disp
, 0);
2163 if (isvar (&opP
->disp
))
2164 add_fix (s
[1], &opP
->disp
, 0, 0);
2168 if (!isbyte (nextword
))
2169 opP
->error
= _("operand out of range");
2174 if (!isword (nextword
))
2175 opP
->error
= _("operand out of range");
2180 if (!issword (nextword
))
2181 opP
->error
= _("operand out of range");
2186 addword (nextword
>> 16);
2213 /* We gotta put out some float. */
2214 if (op (&opP
->disp
) != O_big
)
2219 /* Can other cases happen here? */
2220 if (op (&opP
->disp
) != O_constant
)
2223 val
= (valueT
) offs (&opP
->disp
);
2227 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2228 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2232 offs (&opP
->disp
) = gencnt
;
2234 if (offs (&opP
->disp
) > 0)
2236 if (offs (&opP
->disp
) > baseo
)
2238 as_warn (_("Bignum too big for %c format; truncated"),
2240 offs (&opP
->disp
) = baseo
;
2242 baseo
-= offs (&opP
->disp
);
2245 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2246 offs (&opP
->disp
)--;
2251 gen_to_words (words
, baseo
, (long) outro
);
2252 for (wordp
= words
; baseo
--; wordp
++)
2256 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2259 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2262 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2265 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2268 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2272 nextword
= get_num (&opP
->disp
, 90);
2274 /* Convert mode 5 addressing with a zero offset into
2275 mode 2 addressing to reduce the instruction size by a
2277 if (! isvar (&opP
->disp
)
2279 && (opP
->disp
.size
== SIZE_UNSPEC
)
2280 && (opP
->reg
>= ADDR0
)
2281 && (opP
->reg
<= ADDR7
))
2283 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2288 && ! isvar (&opP
->disp
)
2291 opP
->disp
.exp
.X_op
= O_symbol
;
2292 opP
->disp
.exp
.X_add_symbol
=
2293 section_symbol (absolute_section
);
2296 /* Force into index mode. Hope this works. */
2298 /* We do the first bit for 32-bit displacements, and the
2299 second bit for 16 bit ones. It is possible that we
2300 should make the default be WORD instead of LONG, but
2301 I think that'd break GCC, so we put up with a little
2302 inefficiency for the sake of working output. */
2304 if (!issword (nextword
)
2305 || (isvar (&opP
->disp
)
2306 && ((opP
->disp
.size
== SIZE_UNSPEC
2307 && flag_short_refs
== 0
2308 && cpu_of_arch (current_architecture
) >= m68020
2309 && ! arch_coldfire_p (current_architecture
))
2310 || opP
->disp
.size
== SIZE_LONG
)))
2312 if (cpu_of_arch (current_architecture
) < m68020
2313 || arch_coldfire_p (current_architecture
))
2315 _("displacement too large for this architecture; needs 68020 or higher");
2317 tmpreg
= 0x3B; /* 7.3 */
2319 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2320 if (isvar (&opP
->disp
))
2324 if (opP
->disp
.size
== SIZE_LONG
2326 /* If the displacement needs pic
2327 relocation it cannot be relaxed. */
2328 || opP
->disp
.pic_reloc
!= pic_none
2333 add_fix ('l', &opP
->disp
, 1, 2);
2337 add_frag (adds (&opP
->disp
),
2338 SEXT (offs (&opP
->disp
)),
2339 TAB (PCREL1632
, SZ_UNDEF
));
2346 add_fix ('l', &opP
->disp
, 0, 0);
2351 addword (nextword
>> 16);
2356 tmpreg
= 0x3A; /* 7.2 */
2358 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2360 if (isvar (&opP
->disp
))
2364 add_fix ('w', &opP
->disp
, 1, 0);
2367 add_fix ('w', &opP
->disp
, 0, 0);
2377 baseo
= get_num (&opP
->disp
, 90);
2378 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2379 outro
= get_num (&opP
->odisp
, 90);
2380 /* Figure out the `addressing mode'.
2381 Also turn on the BASE_DISABLE bit, if needed. */
2382 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2384 tmpreg
= 0x3b; /* 7.3 */
2385 if (opP
->reg
== ZPC
)
2388 else if (opP
->reg
== 0)
2391 tmpreg
= 0x30; /* 6.garbage */
2393 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2396 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2399 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2401 siz1
= opP
->disp
.size
;
2402 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2403 siz2
= opP
->odisp
.size
;
2407 /* Index register stuff. */
2408 if (opP
->index
.reg
!= 0
2409 && opP
->index
.reg
>= DATA
2410 && opP
->index
.reg
<= ADDR7
)
2412 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2414 if (opP
->index
.size
== SIZE_LONG
2415 || (opP
->index
.size
== SIZE_UNSPEC
2416 && m68k_index_width_default
== SIZE_LONG
))
2419 if ((opP
->index
.scale
!= 1
2420 && cpu_of_arch (current_architecture
) < m68020
)
2421 || (opP
->index
.scale
== 8
2422 && (arch_coldfire_p (current_architecture
)
2423 && !arch_coldfire_fpu (current_architecture
))))
2426 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2429 if (arch_coldfire_p (current_architecture
)
2430 && opP
->index
.size
== SIZE_WORD
)
2431 opP
->error
= _("invalid index size for coldfire");
2433 switch (opP
->index
.scale
)
2450 GET US OUT OF HERE! */
2452 /* Must be INDEX, with an index register. Address
2453 register cannot be ZERO-PC, and either :b was
2454 forced, or we know it will fit. For a 68000 or
2455 68010, force this mode anyways, because the
2456 larger modes aren't supported. */
2457 if (opP
->mode
== BASE
2458 && ((opP
->reg
>= ADDR0
2459 && opP
->reg
<= ADDR7
)
2462 if (siz1
== SIZE_BYTE
2463 || cpu_of_arch (current_architecture
) < m68020
2464 || arch_coldfire_p (current_architecture
)
2465 || (siz1
== SIZE_UNSPEC
2466 && ! isvar (&opP
->disp
)
2467 && issbyte (baseo
)))
2469 nextword
+= baseo
& 0xff;
2471 if (isvar (&opP
->disp
))
2473 /* Do a byte relocation. If it doesn't
2474 fit (possible on m68000) let the
2475 fixup processing complain later. */
2477 add_fix ('B', &opP
->disp
, 1, 1);
2479 add_fix ('B', &opP
->disp
, 0, 0);
2481 else if (siz1
!= SIZE_BYTE
)
2483 if (siz1
!= SIZE_UNSPEC
)
2484 as_warn (_("Forcing byte displacement"));
2485 if (! issbyte (baseo
))
2486 opP
->error
= _("byte displacement out of range");
2491 else if (siz1
== SIZE_UNSPEC
2493 && isvar (&opP
->disp
)
2494 && subs (&opP
->disp
) == NULL
2496 /* If the displacement needs pic
2497 relocation it cannot be relaxed. */
2498 && opP
->disp
.pic_reloc
== pic_none
2502 /* The code in md_convert_frag_1 needs to be
2503 able to adjust nextword. Call frag_grow
2504 to ensure that we have enough space in
2505 the frag obstack to make all the bytes
2508 nextword
+= baseo
& 0xff;
2510 add_frag (adds (&opP
->disp
),
2511 SEXT (offs (&opP
->disp
)),
2512 TAB (PCINDEX
, SZ_UNDEF
));
2520 nextword
|= 0x40; /* No index reg. */
2521 if (opP
->index
.reg
>= ZDATA0
2522 && opP
->index
.reg
<= ZDATA7
)
2523 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2524 else if (opP
->index
.reg
>= ZADDR0
2525 || opP
->index
.reg
<= ZADDR7
)
2526 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2529 /* It isn't simple. */
2531 if (cpu_of_arch (current_architecture
) < m68020
2532 || arch_coldfire_p (current_architecture
))
2534 _("invalid operand mode for this architecture; needs 68020 or higher");
2537 /* If the guy specified a width, we assume that it is
2538 wide enough. Maybe it isn't. If so, we lose. */
2542 if (isvar (&opP
->disp
)
2544 : ! issword (baseo
))
2549 else if (! isvar (&opP
->disp
) && baseo
== 0)
2558 as_warn (_(":b not permitted; defaulting to :w"));
2568 /* Figure out inner displacement stuff. */
2569 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2571 if (cpu_of_arch (current_architecture
) & cpu32
)
2572 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2576 if (isvar (&opP
->odisp
)
2578 : ! issword (outro
))
2583 else if (! isvar (&opP
->odisp
) && outro
== 0)
2592 as_warn (_(":b not permitted; defaulting to :w"));
2601 if (opP
->mode
== POST
2602 && (nextword
& 0x40) == 0)
2607 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2609 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2610 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2612 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2614 if (siz1
== SIZE_LONG
)
2615 addword (baseo
>> 16);
2616 if (siz1
!= SIZE_UNSPEC
)
2619 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2620 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2621 if (siz2
== SIZE_LONG
)
2622 addword (outro
>> 16);
2623 if (siz2
!= SIZE_UNSPEC
)
2629 nextword
= get_num (&opP
->disp
, 90);
2630 switch (opP
->disp
.size
)
2635 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2637 tmpreg
= 0x38; /* 7.0 */
2641 if (isvar (&opP
->disp
)
2642 && !subs (&opP
->disp
)
2643 && adds (&opP
->disp
)
2645 /* If the displacement needs pic relocation it
2646 cannot be relaxed. */
2647 && opP
->disp
.pic_reloc
== pic_none
2650 && !strchr ("~%&$?", s
[0]))
2652 tmpreg
= 0x3A; /* 7.2 */
2653 add_frag (adds (&opP
->disp
),
2654 SEXT (offs (&opP
->disp
)),
2655 TAB (ABSTOPCREL
, SZ_UNDEF
));
2658 /* Fall through into long. */
2660 if (isvar (&opP
->disp
))
2661 add_fix ('l', &opP
->disp
, 0, 0);
2663 tmpreg
= 0x39;/* 7.1 mode */
2664 addword (nextword
>> 16);
2669 as_bad (_("unsupported byte value; use a different suffix"));
2673 if (isvar (&opP
->disp
))
2674 add_fix ('w', &opP
->disp
, 0, 0);
2676 tmpreg
= 0x38;/* 7.0 mode */
2684 as_bad (_("unknown/incorrect operand"));
2688 /* If s[0] is '4', then this is for the mac instructions
2689 that can have a trailing_ampersand set. If so, set 0x100
2690 bit on tmpreg so install_gen_operand can check for it and
2691 set the appropriate bit (word2, bit 5). */
2694 if (opP
->trailing_ampersand
)
2697 install_gen_operand (s
[1], tmpreg
);
2703 { /* JF: I hate floating point! */
2718 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2719 if (isvar (&opP
->disp
))
2720 add_fix (s
[1], &opP
->disp
, 0, 0);
2723 case 'b': /* Danger: These do no check for
2724 certain types of overflow.
2726 if (!isbyte (tmpreg
))
2727 opP
->error
= _("out of range");
2728 insop (tmpreg
, opcode
);
2729 if (isvar (&opP
->disp
))
2730 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2731 (opcode
->m_codenum
) * 2 + 1;
2734 if (!issbyte (tmpreg
))
2735 opP
->error
= _("out of range");
2736 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2737 if (isvar (&opP
->disp
))
2738 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2741 if (!isword (tmpreg
))
2742 opP
->error
= _("out of range");
2743 insop (tmpreg
, opcode
);
2744 if (isvar (&opP
->disp
))
2745 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2748 if (!issword (tmpreg
))
2749 opP
->error
= _("out of range");
2750 insop (tmpreg
, opcode
);
2751 if (isvar (&opP
->disp
))
2752 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2755 /* Because of the way insop works, we put these two out
2757 insop (tmpreg
, opcode
);
2758 insop (tmpreg
>> 16, opcode
);
2759 if (isvar (&opP
->disp
))
2760 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2767 install_operand (s
[1], tmpreg
);
2778 install_operand (s
[1], opP
->reg
- ADDR
);
2782 tmpreg
= get_num (&opP
->disp
, 90);
2786 add_fix ('B', &opP
->disp
, 1, -1);
2789 add_fix ('w', &opP
->disp
, 1, 0);
2794 if (! HAVE_LONG_BRANCH (current_architecture
))
2795 as_warn (_("Can't use long branches on 68000/68010/5200"));
2796 the_ins
.opcode
[0] |= 0xff;
2797 add_fix ('l', &opP
->disp
, 1, 0);
2802 if (subs (&opP
->disp
)) /* We can't relax it. */
2806 /* If the displacement needs pic relocation it cannot be
2808 if (opP
->disp
.pic_reloc
!= pic_none
)
2811 /* This could either be a symbol, or an absolute
2812 address. If it's an absolute address, turn it into
2813 an absolute jump right here and keep it out of the
2815 if (adds (&opP
->disp
) == 0)
2817 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2818 the_ins
.opcode
[0] = 0x4EF9;
2819 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2820 the_ins
.opcode
[0] = 0x4EB9;
2823 the_ins
.opcode
[0] ^= 0x0100;
2824 the_ins
.opcode
[0] |= 0x0006;
2827 add_fix ('l', &opP
->disp
, 0, 0);
2833 /* Now we know it's going into the relaxer. Now figure
2834 out which mode. We try in this order of preference:
2835 long branch, absolute jump, byte/word branches only. */
2836 if (HAVE_LONG_BRANCH (current_architecture
))
2837 add_frag (adds (&opP
->disp
),
2838 SEXT (offs (&opP
->disp
)),
2839 TAB (BRANCHBWL
, SZ_UNDEF
));
2840 else if (! flag_keep_pcrel
)
2842 if ((the_ins
.opcode
[0] == 0x6000)
2843 || (the_ins
.opcode
[0] == 0x6100))
2844 add_frag (adds (&opP
->disp
),
2845 SEXT (offs (&opP
->disp
)),
2846 TAB (BRABSJUNC
, SZ_UNDEF
));
2848 add_frag (adds (&opP
->disp
),
2849 SEXT (offs (&opP
->disp
)),
2850 TAB (BRABSJCOND
, SZ_UNDEF
));
2853 add_frag (adds (&opP
->disp
),
2854 SEXT (offs (&opP
->disp
)),
2855 TAB (BRANCHBW
, SZ_UNDEF
));
2858 if (isvar (&opP
->disp
))
2860 /* Check for DBcc instructions. We can relax them,
2861 but only if we have long branches and/or absolute
2863 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2864 && (HAVE_LONG_BRANCH (current_architecture
)
2865 || (! flag_keep_pcrel
)))
2867 if (HAVE_LONG_BRANCH (current_architecture
))
2868 add_frag (adds (&opP
->disp
),
2869 SEXT (offs (&opP
->disp
)),
2870 TAB (DBCCLBR
, SZ_UNDEF
));
2872 add_frag (adds (&opP
->disp
),
2873 SEXT (offs (&opP
->disp
)),
2874 TAB (DBCCABSJ
, SZ_UNDEF
));
2877 add_fix ('w', &opP
->disp
, 1, 0);
2881 case 'C': /* Fixed size LONG coproc branches. */
2882 add_fix ('l', &opP
->disp
, 1, 0);
2886 case 'c': /* Var size Coprocesssor branches. */
2887 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2889 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2890 add_fix ('l', &opP
->disp
, 1, 0);
2895 add_frag (adds (&opP
->disp
),
2896 SEXT (offs (&opP
->disp
)),
2897 TAB (FBRANCH
, SZ_UNDEF
));
2904 case 'C': /* Ignore it. */
2907 case 'd': /* JF this is a kludge. */
2908 install_operand ('s', opP
->reg
- ADDR
);
2909 tmpreg
= get_num (&opP
->disp
, 90);
2910 if (!issword (tmpreg
))
2912 as_warn (_("Expression out of range, using 0"));
2919 install_operand (s
[1], opP
->reg
- DATA
);
2922 case 'e': /* EMAC ACCx, reg/reg. */
2923 install_operand (s
[1], opP
->reg
- ACC
);
2926 case 'E': /* Ignore it. */
2930 install_operand (s
[1], opP
->reg
- FP0
);
2933 case 'g': /* EMAC ACCEXTx. */
2934 install_operand (s
[1], opP
->reg
- ACCEXT01
);
2937 case 'G': /* Ignore it. */
2942 tmpreg
= opP
->reg
- COP0
;
2943 install_operand (s
[1], tmpreg
);
2946 case 'i': /* MAC/EMAC scale factor. */
2947 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
2950 case 'J': /* JF foo. */
3080 install_operand (s
[1], tmpreg
);
3084 tmpreg
= get_num (&opP
->disp
, 55);
3085 install_operand (s
[1], tmpreg
& 0x7f);
3092 if (tmpreg
& 0x7FF0000)
3093 as_bad (_("Floating point register in register list"));
3094 insop (reverse_16_bits (tmpreg
), opcode
);
3098 if (tmpreg
& 0x700FFFF)
3099 as_bad (_("Wrong register in floating-point reglist"));
3100 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3108 if (tmpreg
& 0x7FF0000)
3109 as_bad (_("Floating point register in register list"));
3110 insop (tmpreg
, opcode
);
3112 else if (s
[1] == '8')
3114 if (tmpreg
& 0x0FFFFFF)
3115 as_bad (_("incorrect register in reglist"));
3116 install_operand (s
[1], tmpreg
>> 24);
3120 if (tmpreg
& 0x700FFFF)
3121 as_bad (_("wrong register in floating-point reglist"));
3123 install_operand (s
[1], tmpreg
>> 16);
3128 install_operand (s
[1], get_num (&opP
->disp
, 60));
3132 tmpreg
= ((opP
->mode
== DREG
)
3133 ? 0x20 + (int) (opP
->reg
- DATA
)
3134 : (get_num (&opP
->disp
, 40) & 0x1F));
3135 install_operand (s
[1], tmpreg
);
3139 tmpreg
= get_num (&opP
->disp
, 10);
3142 install_operand (s
[1], tmpreg
);
3146 /* This depends on the fact that ADDR registers are eight
3147 more than their corresponding DATA regs, so the result
3148 will have the ADDR_REG bit set. */
3149 install_operand (s
[1], opP
->reg
- DATA
);
3153 if (opP
->mode
== AINDR
)
3154 install_operand (s
[1], opP
->reg
- DATA
);
3156 install_operand (s
[1], opP
->index
.reg
- DATA
);
3160 if (opP
->reg
== FPI
)
3162 else if (opP
->reg
== FPS
)
3164 else if (opP
->reg
== FPC
)
3168 install_operand (s
[1], tmpreg
);
3171 case 'S': /* Ignore it. */
3175 install_operand (s
[1], get_num (&opP
->disp
, 30));
3178 case 'U': /* Ignore it. */
3197 as_fatal (_("failed sanity check"));
3198 } /* switch on cache token. */
3199 install_operand (s
[1], tmpreg
);
3202 /* JF: These are out of order, I fear. */
3215 install_operand (s
[1], tmpreg
);
3241 install_operand (s
[1], tmpreg
);
3245 if (opP
->reg
== VAL
)
3264 install_operand (s
[1], tmpreg
);
3278 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3289 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3295 install_operand (s
[1], tmpreg
);
3298 know (opP
->reg
== PSR
);
3301 know (opP
->reg
== PCSR
);
3316 install_operand (s
[1], tmpreg
);
3319 tmpreg
= get_num (&opP
->disp
, 20);
3320 install_operand (s
[1], tmpreg
);
3322 case '_': /* used only for move16 absolute 32-bit address. */
3323 if (isvar (&opP
->disp
))
3324 add_fix ('l', &opP
->disp
, 0, 0);
3325 tmpreg
= get_num (&opP
->disp
, 90);
3326 addword (tmpreg
>> 16);
3327 addword (tmpreg
& 0xFFFF);
3330 install_operand (s
[1], opP
->reg
- DATA0L
);
3331 opP
->reg
-= (DATA0L
);
3332 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3335 tmpreg
= get_num (&opP
->disp
, 80);
3338 install_operand (s
[1], tmpreg
);
3345 /* By the time whe get here (FINALLY) the_ins contains the complete
3346 instruction, ready to be emitted. . . */
3350 reverse_16_bits (int in
)
3355 static int mask
[16] =
3357 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3358 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3360 for (n
= 0; n
< 16; n
++)
3363 out
|= mask
[15 - n
];
3366 } /* reverse_16_bits() */
3369 reverse_8_bits (int in
)
3374 static int mask
[8] =
3376 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3379 for (n
= 0; n
< 8; n
++)
3385 } /* reverse_8_bits() */
3387 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3388 (that value is chosen in the frag_var call in md_assemble). TYPE
3389 is the subtype of the frag to be generated; its primary type is
3390 rs_machine_dependent.
3392 The TYPE parameter is also used by md_convert_frag_1 and
3393 md_estimate_size_before_relax. The appropriate type of fixup will
3394 be emitted by md_convert_frag_1.
3396 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3398 install_operand (int mode
, int val
)
3403 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3406 the_ins
.opcode
[0] |= val
<< 9;
3409 the_ins
.opcode
[1] |= val
<< 12;
3412 the_ins
.opcode
[1] |= val
<< 6;
3415 the_ins
.opcode
[1] |= val
;
3418 the_ins
.opcode
[2] |= val
<< 12;
3421 the_ins
.opcode
[2] |= val
<< 6;
3424 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3425 three words long! */
3427 the_ins
.opcode
[2] |= val
;
3430 the_ins
.opcode
[1] |= val
<< 7;
3433 the_ins
.opcode
[1] |= val
<< 10;
3437 the_ins
.opcode
[1] |= val
<< 5;
3442 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3445 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3448 the_ins
.opcode
[0] |= val
= 0xff;
3451 the_ins
.opcode
[0] |= val
<< 9;
3454 the_ins
.opcode
[1] |= val
;
3457 the_ins
.opcode
[1] |= val
;
3458 the_ins
.numo
++; /* What a hack. */
3461 the_ins
.opcode
[1] |= val
<< 4;
3469 the_ins
.opcode
[0] |= (val
<< 6);
3472 the_ins
.opcode
[1] = (val
>> 16);
3473 the_ins
.opcode
[2] = val
& 0xffff;
3476 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3477 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3478 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3480 case 'n': /* MAC/EMAC Rx on !load. */
3481 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3482 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3483 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3485 case 'o': /* MAC/EMAC Rx on load. */
3486 the_ins
.opcode
[1] |= val
<< 12;
3487 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3489 case 'M': /* MAC/EMAC Ry on !load. */
3490 the_ins
.opcode
[0] |= (val
& 0xF);
3491 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3493 case 'N': /* MAC/EMAC Ry on load. */
3494 the_ins
.opcode
[1] |= (val
& 0xF);
3495 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3498 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3501 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3504 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3506 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3507 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3508 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3510 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3511 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3512 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3515 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3518 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3522 as_fatal (_("failed sanity check."));
3527 install_gen_operand (int mode
, int val
)
3531 case '/': /* Special for mask loads for mac/msac insns with
3532 possible mask; trailing_ampersend set in bit 8. */
3533 the_ins
.opcode
[0] |= (val
& 0x3f);
3534 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3537 the_ins
.opcode
[0] |= val
;
3540 /* This is a kludge!!! */
3541 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3550 the_ins
.opcode
[0] |= val
;
3552 /* more stuff goes here. */
3554 as_fatal (_("failed sanity check."));
3558 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3559 then deal with the bitfield hack. */
3562 crack_operand (char *str
, struct m68k_op
*opP
)
3564 register int parens
;
3566 register char *beg_str
;
3574 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3580 else if (*str
== ')')
3584 opP
->error
= _("Extra )");
3590 if (flag_mri
&& *str
== '\'')
3591 inquote
= ! inquote
;
3593 if (!*str
&& parens
)
3595 opP
->error
= _("Missing )");
3600 if (m68k_ip_op (beg_str
, opP
) != 0)
3607 c
= *++str
; /* JF bitfield hack. */
3612 as_bad (_("Missing operand"));
3615 /* Detect MRI REG symbols and convert them to REGLSTs. */
3616 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3619 opP
->mask
= ~(int)opP
->reg
;
3626 /* This is the guts of the machine-dependent assembler. STR points to a
3627 machine dependent instruction. This function is supposed to emit
3628 the frags/bytes it assembles to.
3632 insert_reg (const char *regname
, int regnum
)
3637 #ifdef REGISTER_PREFIX
3638 if (!flag_reg_prefix_optional
)
3640 buf
[0] = REGISTER_PREFIX
;
3641 strcpy (buf
+ 1, regname
);
3646 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3647 &zero_address_frag
));
3649 for (i
= 0; regname
[i
]; i
++)
3650 buf
[i
] = TOUPPER (regname
[i
]);
3653 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3654 &zero_address_frag
));
3663 static const struct init_entry init_table
[] =
3723 { "accext01", ACCEXT01
},
3724 { "accext23", ACCEXT23
},
3728 /* Control registers. */
3729 { "sfc", SFC
}, /* Source Function Code. */
3731 { "dfc", DFC
}, /* Destination Function Code. */
3733 { "cacr", CACR
}, /* Cache Control Register. */
3734 { "caar", CAAR
}, /* Cache Address Register. */
3736 { "usp", USP
}, /* User Stack Pointer. */
3737 { "vbr", VBR
}, /* Vector Base Register. */
3738 { "msp", MSP
}, /* Master Stack Pointer. */
3739 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3741 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3742 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3743 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3744 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3746 /* 68ec040 versions of same */
3747 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3748 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3749 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3750 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3752 /* mcf5200 versions of same. The ColdFire programmer's reference
3753 manual indicated that the order is 2,3,0,1, but Ken Rose
3754 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3755 { "acr0", ACR0
}, /* Access Control Unit 0. */
3756 { "acr1", ACR1
}, /* Access Control Unit 1. */
3757 { "acr2", ACR2
}, /* Access Control Unit 2. */
3758 { "acr3", ACR3
}, /* Access Control Unit 3. */
3760 { "tc", TC
}, /* MMU Translation Control Register. */
3763 { "mmusr", MMUSR
}, /* MMU Status Register. */
3764 { "srp", SRP
}, /* User Root Pointer. */
3765 { "urp", URP
}, /* Supervisor Root Pointer. */
3770 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3771 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3772 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3773 { "mbar", MBAR
}, /* Module Base Address Register. */
3775 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3776 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3777 { "rombar0", ROMBAR
}, /* mcfv4e registers. */
3778 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3779 { "mpcr", MPCR
}, /* mcfv4e registers. */
3780 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3781 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3782 { "asid", TC
}, /* mcfv4e registers. */
3783 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3784 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3785 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3786 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3787 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3788 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3789 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3790 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3791 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3792 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3793 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3794 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3795 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3797 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3798 { "rambar", RAMBAR
}, /* mcf528x registers. */
3800 { "mbar2", MBAR2
}, /* mcf5249 registers. */
3801 /* End of control registers. */
3835 /* 68ec030 versions of same. */
3838 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3841 /* Suppressed data and address registers. */
3859 /* Upper and lower data and address registers, used by macw and msacw. */
3900 init_regtable (void)
3903 for (i
= 0; init_table
[i
].name
; i
++)
3904 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3908 md_assemble (char *str
)
3915 int shorts_this_frag
;
3918 if (!selected_cpu
&& !selected_arch
)
3920 /* We've not selected an architecture yet. Set the default
3921 now. We do this lazily so that an initial .cpu or .arch directive
3923 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
3924 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
3929 /* In MRI mode, the instruction and operands are separated by a
3930 space. Anything following the operands is a comment. The label
3931 has already been removed. */
3939 for (s
= str
; *s
!= '\0'; s
++)
3941 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3959 inquote
= ! inquote
;
3964 memset (&the_ins
, '\0', sizeof (the_ins
));
3969 for (n
= 0; n
< the_ins
.numargs
; n
++)
3970 if (the_ins
.operands
[n
].error
)
3972 er
= the_ins
.operands
[n
].error
;
3978 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3982 /* If there is a current label, record that it marks an instruction. */
3983 if (current_label
!= NULL
)
3985 current_label
->text
= 1;
3986 current_label
= NULL
;
3990 /* Tie dwarf2 debug info to the address at the start of the insn. */
3991 dwarf2_emit_insn (0);
3994 if (the_ins
.nfrag
== 0)
3996 /* No frag hacking involved; just put it out. */
3997 toP
= frag_more (2 * the_ins
.numo
);
3998 fromP
= &the_ins
.opcode
[0];
3999 for (m
= the_ins
.numo
; m
; --m
)
4001 md_number_to_chars (toP
, (long) (*fromP
), 2);
4005 /* Put out symbol-dependent info. */
4006 for (m
= 0; m
< the_ins
.nrel
; m
++)
4008 switch (the_ins
.reloc
[m
].wid
)
4027 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4028 the_ins
.reloc
[m
].wid
);
4031 fixP
= fix_new_exp (frag_now
,
4032 ((toP
- frag_now
->fr_literal
)
4033 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4035 &the_ins
.reloc
[m
].exp
,
4036 the_ins
.reloc
[m
].pcrel
,
4037 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4038 the_ins
.reloc
[m
].pic_reloc
));
4039 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4040 if (the_ins
.reloc
[m
].wid
== 'B')
4041 fixP
->fx_signed
= 1;
4046 /* There's some frag hacking. */
4048 /* Calculate the max frag size. */
4051 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4052 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4053 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4054 /* frag_var part. */
4056 /* Make sure the whole insn fits in one chunk, in particular that
4057 the var part is attached, as we access one byte before the
4058 variable frag for byte branches. */
4062 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4067 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4069 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4070 toP
= frag_more (wid
);
4072 shorts_this_frag
= 0;
4073 for (m
= wid
/ 2; m
; --m
)
4075 md_number_to_chars (toP
, (long) (*fromP
), 2);
4080 for (m
= 0; m
< the_ins
.nrel
; m
++)
4082 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4084 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4087 wid
= the_ins
.reloc
[m
].wid
;
4090 the_ins
.reloc
[m
].wid
= 0;
4091 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4093 fixP
= fix_new_exp (frag_now
,
4094 ((toP
- frag_now
->fr_literal
)
4095 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4097 &the_ins
.reloc
[m
].exp
,
4098 the_ins
.reloc
[m
].pcrel
,
4099 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4100 the_ins
.reloc
[m
].pic_reloc
));
4101 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4103 (void) frag_var (rs_machine_dependent
, 10, 0,
4104 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4105 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4107 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4108 shorts_this_frag
= 0;
4111 toP
= frag_more (n
* 2);
4114 md_number_to_chars (toP
, (long) (*fromP
), 2);
4120 for (m
= 0; m
< the_ins
.nrel
; m
++)
4124 wid
= the_ins
.reloc
[m
].wid
;
4127 the_ins
.reloc
[m
].wid
= 0;
4128 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4130 fixP
= fix_new_exp (frag_now
,
4131 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4132 - shorts_this_frag
* 2),
4134 &the_ins
.reloc
[m
].exp
,
4135 the_ins
.reloc
[m
].pcrel
,
4136 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4137 the_ins
.reloc
[m
].pic_reloc
));
4138 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4142 /* Comparison function used by qsort to rank the opcode entries by name. */
4145 m68k_compare_opcode (const void * v1
, const void * v2
)
4147 struct m68k_opcode
* op1
, * op2
;
4153 op1
= *(struct m68k_opcode
**) v1
;
4154 op2
= *(struct m68k_opcode
**) v2
;
4156 /* Compare the two names. If different, return the comparison.
4157 If the same, return the order they are in the opcode table. */
4158 ret
= strcmp (op1
->name
, op2
->name
);
4169 const struct m68k_opcode
*ins
;
4170 struct m68k_incant
*hack
, *slak
;
4171 const char *retval
= 0; /* Empty string, or error msg text. */
4174 /* Set up hash tables with 68000 instructions.
4175 similar to what the vax assembler does. */
4176 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4177 a copy of it at runtime, adding in the information we want but isn't
4178 there. I think it'd be better to have an awk script hack the table
4179 at compile time. Or even just xstr the table and use it as-is. But
4180 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4185 flag_reg_prefix_optional
= 1;
4187 if (! m68k_rel32_from_cmdline
)
4191 /* First sort the opcode table into alphabetical order to seperate
4192 the order that the assembler wants to see the opcodes from the
4193 order that the disassembler wants to see them. */
4194 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4195 if (!m68k_sorted_opcodes
)
4196 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4197 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4199 for (i
= m68k_numopcodes
; i
--;)
4200 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4202 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4203 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4205 op_hash
= hash_new ();
4207 obstack_begin (&robyn
, 4000);
4208 for (i
= 0; i
< m68k_numopcodes
; i
++)
4210 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4213 ins
= m68k_sorted_opcodes
[i
];
4215 /* We *could* ignore insns that don't match our
4216 arch here by just leaving them out of the hash. */
4217 slak
->m_operands
= ins
->args
;
4218 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4219 slak
->m_arch
= ins
->arch
;
4220 slak
->m_opcode
= ins
->opcode
;
4221 /* This is kludgey. */
4222 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4223 if (i
+ 1 != m68k_numopcodes
4224 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4226 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4231 slak
= slak
->m_next
;
4235 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4237 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4240 for (i
= 0; i
< m68k_numaliases
; i
++)
4242 const char *name
= m68k_opcode_aliases
[i
].primary
;
4243 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4244 PTR val
= hash_find (op_hash
, name
);
4247 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4248 retval
= hash_insert (op_hash
, alias
, val
);
4250 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4253 /* In MRI mode, all unsized branches are variable sized. Normally,
4254 they are word sized. */
4257 static struct m68k_opcode_alias mri_aliases
[] =
4278 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4281 const char *name
= mri_aliases
[i
].primary
;
4282 const char *alias
= mri_aliases
[i
].alias
;
4283 PTR val
= hash_find (op_hash
, name
);
4286 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4287 retval
= hash_jam (op_hash
, alias
, val
);
4289 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4293 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4295 notend_table
[i
] = 0;
4296 alt_notend_table
[i
] = 0;
4299 notend_table
[','] = 1;
4300 notend_table
['{'] = 1;
4301 notend_table
['}'] = 1;
4302 alt_notend_table
['a'] = 1;
4303 alt_notend_table
['A'] = 1;
4304 alt_notend_table
['d'] = 1;
4305 alt_notend_table
['D'] = 1;
4306 alt_notend_table
['#'] = 1;
4307 alt_notend_table
['&'] = 1;
4308 alt_notend_table
['f'] = 1;
4309 alt_notend_table
['F'] = 1;
4310 #ifdef REGISTER_PREFIX
4311 alt_notend_table
[REGISTER_PREFIX
] = 1;
4314 /* We need to put '(' in alt_notend_table to handle
4315 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4316 alt_notend_table
['('] = 1;
4318 /* We need to put '@' in alt_notend_table to handle
4319 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4320 alt_notend_table
['@'] = 1;
4322 /* We need to put digits in alt_notend_table to handle
4323 bfextu %d0{24:1},%d0 */
4324 alt_notend_table
['0'] = 1;
4325 alt_notend_table
['1'] = 1;
4326 alt_notend_table
['2'] = 1;
4327 alt_notend_table
['3'] = 1;
4328 alt_notend_table
['4'] = 1;
4329 alt_notend_table
['5'] = 1;
4330 alt_notend_table
['6'] = 1;
4331 alt_notend_table
['7'] = 1;
4332 alt_notend_table
['8'] = 1;
4333 alt_notend_table
['9'] = 1;
4335 #ifndef MIT_SYNTAX_ONLY
4336 /* Insert pseudo ops, these have to go into the opcode table since
4337 gas expects pseudo ops to start with a dot. */
4341 while (mote_pseudo_table
[n
].poc_name
)
4343 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4344 hash_insert (op_hash
,
4345 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4346 hack
->m_operands
= 0;
4356 record_alignment (text_section
, 2);
4357 record_alignment (data_section
, 2);
4358 record_alignment (bss_section
, 2);
4363 /* This is called when a label is defined. */
4366 m68k_frob_label (symbolS
*sym
)
4368 struct label_line
*n
;
4370 n
= (struct label_line
*) xmalloc (sizeof *n
);
4373 as_where (&n
->file
, &n
->line
);
4379 dwarf2_emit_label (sym
);
4383 /* This is called when a value that is not an instruction is emitted. */
4386 m68k_flush_pending_output (void)
4388 current_label
= NULL
;
4391 /* This is called at the end of the assembly, when the final value of
4392 the label is known. We warn if this is a text symbol aligned at an
4396 m68k_frob_symbol (symbolS
*sym
)
4398 if (S_GET_SEGMENT (sym
) == reg_section
4399 && (int) S_GET_VALUE (sym
) < 0)
4401 S_SET_SEGMENT (sym
, absolute_section
);
4402 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4404 else if ((S_GET_VALUE (sym
) & 1) != 0)
4406 struct label_line
*l
;
4408 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4410 if (l
->label
== sym
)
4413 as_warn_where (l
->file
, l
->line
,
4414 _("text label `%s' aligned to odd boundary"),
4422 /* This is called if we go in or out of MRI mode because of the .mri
4426 m68k_mri_mode_change (int on
)
4430 if (! flag_reg_prefix_optional
)
4432 flag_reg_prefix_optional
= 1;
4433 #ifdef REGISTER_PREFIX
4438 if (! m68k_rel32_from_cmdline
)
4443 if (! reg_prefix_optional_seen
)
4445 #ifdef REGISTER_PREFIX_OPTIONAL
4446 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4448 flag_reg_prefix_optional
= 0;
4450 #ifdef REGISTER_PREFIX
4455 if (! m68k_rel32_from_cmdline
)
4460 /* Equal to MAX_PRECISION in atof-ieee.c. */
4461 #define MAX_LITTLENUMS 6
4463 /* Turn a string in input_line_pointer into a floating point constant
4464 of type TYPE, and store the appropriate bytes in *LITP. The number
4465 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4466 returned, or NULL on OK. */
4469 md_atof (int type
, char *litP
, int *sizeP
)
4472 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4473 LITTLENUM_TYPE
*wordP
;
4504 return _("Bad call to MD_ATOF()");
4506 t
= atof_ieee (input_line_pointer
, type
, words
);
4508 input_line_pointer
= t
;
4510 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4511 for (wordP
= words
; prec
--;)
4513 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4514 litP
+= sizeof (LITTLENUM_TYPE
);
4520 md_number_to_chars (char *buf
, valueT val
, int n
)
4522 number_to_chars_bigendian (buf
, val
, n
);
4526 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4528 offsetT val
= *valP
;
4529 addressT upper_limit
;
4530 offsetT lower_limit
;
4532 /* This is unnecessary but it convinces the native rs6000 compiler
4533 to generate the code we want. */
4534 char *buf
= fixP
->fx_frag
->fr_literal
;
4535 buf
+= fixP
->fx_where
;
4536 /* End ibm compiler workaround. */
4540 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4546 memset (buf
, 0, fixP
->fx_size
);
4547 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4549 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4550 && !S_IS_DEFINED (fixP
->fx_addsy
)
4551 && !S_IS_WEAK (fixP
->fx_addsy
))
4552 S_SET_WEAK (fixP
->fx_addsy
);
4557 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4558 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4561 switch (fixP
->fx_size
)
4563 /* The cast to offsetT below are necessary to make code
4564 correct for machines where ints are smaller than offsetT. */
4568 lower_limit
= - (offsetT
) 0x80;
4571 *buf
++ = (val
>> 8);
4573 upper_limit
= 0x7fff;
4574 lower_limit
= - (offsetT
) 0x8000;
4577 *buf
++ = (val
>> 24);
4578 *buf
++ = (val
>> 16);
4579 *buf
++ = (val
>> 8);
4581 upper_limit
= 0x7fffffff;
4582 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4585 BAD_CASE (fixP
->fx_size
);
4588 /* Fix up a negative reloc. */
4589 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4591 fixP
->fx_addsy
= fixP
->fx_subsy
;
4592 fixP
->fx_subsy
= NULL
;
4596 /* For non-pc-relative values, it's conceivable we might get something
4597 like "0xff" for a byte field. So extend the upper part of the range
4598 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4599 so that we can do any range checking at all. */
4600 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4601 upper_limit
= upper_limit
* 2 + 1;
4603 if ((addressT
) val
> upper_limit
4604 && (val
> 0 || val
< lower_limit
))
4605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4607 /* A one byte PC-relative reloc means a short branch. We can't use
4608 a short branch with a value of 0 or -1, because those indicate
4609 different opcodes (branches with longer offsets). fixup_segment
4610 in write.c may have clobbered fx_pcrel, so we need to examine the
4613 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4614 && fixP
->fx_size
== 1
4615 && (fixP
->fx_addsy
== NULL
4616 || S_IS_DEFINED (fixP
->fx_addsy
))
4617 && (val
== 0 || val
== -1))
4618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4621 /* *fragP has been relaxed to its final size, and now needs to have
4622 the bytes inside it modified to conform to the new size There is UGLY
4626 md_convert_frag_1 (fragS
*fragP
)
4631 /* Address in object code of the displacement. */
4632 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4634 /* Address in gas core of the place to store the displacement. */
4635 /* This convinces the native rs6000 compiler to generate the code we
4637 register char *buffer_address
= fragP
->fr_literal
;
4638 buffer_address
+= fragP
->fr_fix
;
4639 /* End ibm compiler workaround. */
4641 /* The displacement of the address, from current location. */
4642 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4643 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4645 switch (fragP
->fr_subtype
)
4647 case TAB (BRANCHBWL
, BYTE
):
4648 case TAB (BRABSJUNC
, BYTE
):
4649 case TAB (BRABSJCOND
, BYTE
):
4650 case TAB (BRANCHBW
, BYTE
):
4651 know (issbyte (disp
));
4653 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4654 _("short branch with zero offset: use :w"));
4655 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4656 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4657 fixP
->fx_pcrel_adjust
= -1;
4659 case TAB (BRANCHBWL
, SHORT
):
4660 case TAB (BRABSJUNC
, SHORT
):
4661 case TAB (BRABSJCOND
, SHORT
):
4662 case TAB (BRANCHBW
, SHORT
):
4663 fragP
->fr_opcode
[1] = 0x00;
4664 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4665 1, RELAX_RELOC_PC16
);
4668 case TAB (BRANCHBWL
, LONG
):
4669 fragP
->fr_opcode
[1] = (char) 0xFF;
4670 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4671 1, RELAX_RELOC_PC32
);
4674 case TAB (BRABSJUNC
, LONG
):
4675 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4677 if (flag_keep_pcrel
)
4678 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4679 fragP
->fr_opcode
[0] = 0x4E;
4680 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4681 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4682 0, RELAX_RELOC_ABS32
);
4685 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4687 if (flag_keep_pcrel
)
4688 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4689 fragP
->fr_opcode
[0] = 0x4E;
4690 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4691 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4692 0, RELAX_RELOC_ABS32
);
4697 /* This cannot happen, because jbsr and jbra are the only two
4698 unconditional branches. */
4702 case TAB (BRABSJCOND
, LONG
):
4703 if (flag_keep_pcrel
)
4704 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4706 /* Only Bcc 68000 instructions can come here
4707 Change bcc into b!cc/jmp absl long. */
4708 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4709 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4711 /* JF: these used to be fr_opcode[2,3], but they may be in a
4712 different frag, in which case referring to them is a no-no.
4713 Only fr_opcode[0,1] are guaranteed to work. */
4714 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4715 *buffer_address
++ = (char) 0xf9;
4716 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4717 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4718 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4721 case TAB (FBRANCH
, SHORT
):
4722 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4723 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4724 1, RELAX_RELOC_PC16
);
4727 case TAB (FBRANCH
, LONG
):
4728 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4729 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4730 1, RELAX_RELOC_PC32
);
4733 case TAB (DBCCLBR
, SHORT
):
4734 case TAB (DBCCABSJ
, SHORT
):
4735 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4736 1, RELAX_RELOC_PC16
);
4739 case TAB (DBCCLBR
, LONG
):
4740 /* Only DBcc instructions can come here.
4741 Change dbcc into dbcc/bral.
4742 JF: these used to be fr_opcode[2-7], but that's wrong. */
4743 if (flag_keep_pcrel
)
4744 as_fatal (_("Tried to convert DBcc to absolute jump"));
4746 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4747 *buffer_address
++ = 0x04;
4748 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4749 *buffer_address
++ = 0x06;
4750 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4751 *buffer_address
++ = (char) 0xff;
4753 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4754 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4758 case TAB (DBCCABSJ
, LONG
):
4759 /* Only DBcc instructions can come here.
4760 Change dbcc into dbcc/jmp.
4761 JF: these used to be fr_opcode[2-7], but that's wrong. */
4762 if (flag_keep_pcrel
)
4763 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4765 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4766 *buffer_address
++ = 0x04;
4767 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4768 *buffer_address
++ = 0x06;
4769 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4770 *buffer_address
++ = (char) 0xf9;
4772 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4773 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4777 case TAB (PCREL1632
, SHORT
):
4778 fragP
->fr_opcode
[1] &= ~0x3F;
4779 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4780 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4781 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4784 case TAB (PCREL1632
, LONG
):
4785 /* Already set to mode 7.3; this indicates: PC indirect with
4786 suppressed index, 32-bit displacement. */
4787 *buffer_address
++ = 0x01;
4788 *buffer_address
++ = 0x70;
4790 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4791 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4792 fixP
->fx_pcrel_adjust
= 2;
4795 case TAB (PCINDEX
, BYTE
):
4796 assert (fragP
->fr_fix
>= 2);
4797 buffer_address
[-2] &= ~1;
4798 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4799 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4800 fixP
->fx_pcrel_adjust
= 1;
4802 case TAB (PCINDEX
, SHORT
):
4803 assert (fragP
->fr_fix
>= 2);
4804 buffer_address
[-2] |= 0x1;
4805 buffer_address
[-1] = 0x20;
4806 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4807 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4808 fixP
->fx_pcrel_adjust
= 2;
4811 case TAB (PCINDEX
, LONG
):
4812 assert (fragP
->fr_fix
>= 2);
4813 buffer_address
[-2] |= 0x1;
4814 buffer_address
[-1] = 0x30;
4815 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4816 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4817 fixP
->fx_pcrel_adjust
= 2;
4820 case TAB (ABSTOPCREL
, SHORT
):
4821 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4822 1, RELAX_RELOC_PC16
);
4825 case TAB (ABSTOPCREL
, LONG
):
4826 if (flag_keep_pcrel
)
4827 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4828 /* The thing to do here is force it to ABSOLUTE LONG, since
4829 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4830 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4832 fragP
->fr_opcode
[1] &= ~0x3F;
4833 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4834 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4835 0, RELAX_RELOC_ABS32
);
4842 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
4843 segT sec ATTRIBUTE_UNUSED
,
4846 md_convert_frag_1 (fragP
);
4849 /* Force truly undefined symbols to their maximum size, and generally set up
4850 the frag list to be relaxed
4853 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
4855 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4856 switch (fragP
->fr_subtype
)
4858 case TAB (BRANCHBWL
, SZ_UNDEF
):
4859 case TAB (BRABSJUNC
, SZ_UNDEF
):
4860 case TAB (BRABSJCOND
, SZ_UNDEF
):
4862 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4863 && relaxable_symbol (fragP
->fr_symbol
))
4865 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4867 else if (flag_short_refs
)
4869 /* Symbol is undefined and we want short ref. */
4870 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4874 /* Symbol is still undefined. Make it LONG. */
4875 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4880 case TAB (BRANCHBW
, SZ_UNDEF
):
4882 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4883 && relaxable_symbol (fragP
->fr_symbol
))
4885 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4889 /* Symbol is undefined and we don't have long branches. */
4890 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4895 case TAB (FBRANCH
, SZ_UNDEF
):
4896 case TAB (DBCCLBR
, SZ_UNDEF
):
4897 case TAB (DBCCABSJ
, SZ_UNDEF
):
4898 case TAB (PCREL1632
, SZ_UNDEF
):
4900 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4901 && relaxable_symbol (fragP
->fr_symbol
))
4904 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4908 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4913 case TAB (PCINDEX
, SZ_UNDEF
):
4914 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4915 && relaxable_symbol (fragP
->fr_symbol
)))
4917 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4921 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4925 case TAB (ABSTOPCREL
, SZ_UNDEF
):
4927 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4928 && relaxable_symbol (fragP
->fr_symbol
)))
4930 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
4934 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
4943 /* Now that SZ_UNDEF are taken care of, check others. */
4944 switch (fragP
->fr_subtype
)
4946 case TAB (BRANCHBWL
, BYTE
):
4947 case TAB (BRABSJUNC
, BYTE
):
4948 case TAB (BRABSJCOND
, BYTE
):
4949 case TAB (BRANCHBW
, BYTE
):
4950 /* We can't do a short jump to the next instruction, so in that
4951 case we force word mode. If the symbol is at the start of a
4952 frag, and it is the next frag with any data in it (usually
4953 this is just the next frag, but assembler listings may
4954 introduce empty frags), we must use word mode. */
4955 if (fragP
->fr_symbol
)
4959 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
4960 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
4964 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
4968 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4975 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4978 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4979 /* the bit-field entries in the relocation_info struct plays hell
4980 with the byte-order problems of cross-assembly. So as a hack,
4981 I added this mach. dependent ri twiddler. Ugly, but it gets
4983 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4984 are symbolnum, most sig. byte first. Last byte is broken up with
4985 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4986 nibble as nuthin. (on Sun 3 at least) */
4987 /* Translate the internal relocation information into target-specific
4991 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
4994 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4995 /* Now the fun stuff. */
4996 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4997 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4998 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4999 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5000 | ((ri
->r_length
<< 5) & 0x60)
5001 | ((ri
->r_extern
<< 4) & 0x10));
5006 #endif /* OBJ_AOUT or OBJ_BOUT */
5008 #ifndef WORKING_DOT_WORD
5009 int md_short_jump_size
= 4;
5010 int md_long_jump_size
= 6;
5013 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5014 fragS
*frag ATTRIBUTE_UNUSED
,
5015 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5019 offset
= to_addr
- (from_addr
+ 2);
5021 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5022 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5026 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5027 fragS
*frag
, symbolS
*to_symbol
)
5031 if (!HAVE_LONG_BRANCH (current_architecture
))
5033 if (flag_keep_pcrel
)
5034 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5035 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5036 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5037 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5038 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5043 offset
= to_addr
- (from_addr
+ 2);
5044 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5045 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5051 /* Different values of OK tell what its OK to return. Things that
5052 aren't OK are an error (what a shock, no?)
5055 10: Absolute 1:8 only
5056 20: Absolute 0:7 only
5057 30: absolute 0:15 only
5058 40: Absolute 0:31 only
5059 50: absolute 0:127 only
5060 55: absolute -64:63 only
5061 60: absolute -128:127 only
5062 70: absolute 0:4095 only
5063 80: absolute -1, 1:7 only
5067 get_num (struct m68k_exp
*exp
, int ok
)
5069 if (exp
->exp
.X_op
== O_absent
)
5071 /* Do the same thing the VAX asm does. */
5072 op (exp
) = O_constant
;
5078 as_warn (_("expression out of range: defaulting to 1"));
5082 else if (exp
->exp
.X_op
== O_constant
)
5087 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5089 as_warn (_("expression out of range: defaulting to 1"));
5094 if ((valueT
) TRUNC (offs (exp
)) > 7)
5098 if ((valueT
) TRUNC (offs (exp
)) > 15)
5102 if ((valueT
) TRUNC (offs (exp
)) > 32)
5106 if ((valueT
) TRUNC (offs (exp
)) > 127)
5110 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5114 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5118 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5121 as_warn (_("expression out of range: defaulting to 0"));
5126 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5127 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5129 as_warn (_("expression out of range: defaulting to 1"));
5137 else if (exp
->exp
.X_op
== O_big
)
5139 if (offs (exp
) <= 0 /* flonum. */
5140 && (ok
== 90 /* no bignums */
5141 || (ok
> 10 /* Small-int ranges including 0 ok. */
5142 /* If we have a flonum zero, a zero integer should
5143 do as well (e.g., in moveq). */
5144 && generic_floating_point_number
.exponent
== 0
5145 && generic_floating_point_number
.low
[0] == 0)))
5147 /* HACK! Turn it into a long. */
5148 LITTLENUM_TYPE words
[6];
5150 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5151 op (exp
) = O_constant
;
5154 offs (exp
) = words
[1] | (words
[0] << 16);
5158 op (exp
) = O_constant
;
5161 offs (exp
) = (ok
== 10) ? 1 : 0;
5162 as_warn (_("Can't deal with expression; defaulting to %ld"),
5168 if (ok
>= 10 && ok
<= 80)
5170 op (exp
) = O_constant
;
5173 offs (exp
) = (ok
== 10) ? 1 : 0;
5174 as_warn (_("Can't deal with expression; defaulting to %ld"),
5179 if (exp
->size
!= SIZE_UNSPEC
)
5187 if (!isbyte (offs (exp
)))
5188 as_warn (_("expression doesn't fit in BYTE"));
5191 if (!isword (offs (exp
)))
5192 as_warn (_("expression doesn't fit in WORD"));
5200 /* These are the back-ends for the various machine dependent pseudo-ops. */
5203 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5205 subseg_set (data_section
, 1);
5206 demand_empty_rest_of_line ();
5210 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5212 subseg_set (data_section
, 2);
5213 demand_empty_rest_of_line ();
5217 s_bss (int ignore ATTRIBUTE_UNUSED
)
5219 /* We don't support putting frags in the BSS segment, we fake it
5220 by marking in_bss, then looking at s_skip for clues. */
5222 subseg_set (bss_section
, 0);
5223 demand_empty_rest_of_line ();
5227 s_even (int ignore ATTRIBUTE_UNUSED
)
5230 register long temp_fill
;
5232 temp
= 1; /* JF should be 2? */
5233 temp_fill
= get_absolute_expression ();
5234 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5235 frag_align (temp
, (int) temp_fill
, 0);
5236 demand_empty_rest_of_line ();
5237 record_alignment (now_seg
, temp
);
5241 s_proc (int ignore ATTRIBUTE_UNUSED
)
5243 demand_empty_rest_of_line ();
5246 /* Pseudo-ops handled for MRI compatibility. */
5248 /* This function returns non-zero if the argument is a conditional
5249 pseudo-op. This is called when checking whether a pending
5250 alignment is needed. */
5253 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5255 return (pop
->poc_handler
== s_mri_if
5256 || pop
->poc_handler
== s_mri_else
);
5259 /* Handle an MRI style chip specification. */
5268 s
= input_line_pointer
;
5269 /* We can't use get_symbol_end since the processor names are not proper
5271 while (is_part_of_name (c
= *input_line_pointer
++))
5273 *--input_line_pointer
= 0;
5274 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5275 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5277 if (!m68k_cpus
[i
].name
)
5279 as_bad (_("%s: unrecognized processor name"), s
);
5280 *input_line_pointer
= c
;
5281 ignore_rest_of_line ();
5284 *input_line_pointer
= c
;
5286 if (*input_line_pointer
== '/')
5287 current_architecture
= 0;
5289 current_architecture
&= m68881
| m68851
;
5290 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5291 control_regs
= m68k_cpus
[i
].control_regs
;
5293 while (*input_line_pointer
== '/')
5295 ++input_line_pointer
;
5296 s
= input_line_pointer
;
5297 /* We can't use get_symbol_end since the processor names are not
5299 while (is_part_of_name (c
= *input_line_pointer
++))
5301 *--input_line_pointer
= 0;
5302 if (strcmp (s
, "68881") == 0)
5303 current_architecture
|= m68881
;
5304 else if (strcmp (s
, "68851") == 0)
5305 current_architecture
|= m68851
;
5306 *input_line_pointer
= c
;
5310 /* The MRI CHIP pseudo-op. */
5313 s_chip (int ignore ATTRIBUTE_UNUSED
)
5319 stop
= mri_comment_field (&stopc
);
5322 mri_comment_end (stop
, stopc
);
5323 demand_empty_rest_of_line ();
5326 /* The MRI FOPT pseudo-op. */
5329 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5333 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5337 input_line_pointer
+= 3;
5338 temp
= get_absolute_expression ();
5339 if (temp
< 0 || temp
> 7)
5340 as_bad (_("bad coprocessor id"));
5342 m68k_float_copnum
= COP0
+ temp
;
5346 as_bad (_("unrecognized fopt option"));
5347 ignore_rest_of_line ();
5351 demand_empty_rest_of_line ();
5354 /* The structure used to handle the MRI OPT pseudo-op. */
5358 /* The name of the option. */
5361 /* If this is not NULL, just call this function. The first argument
5362 is the ARG field of this structure, the second argument is
5363 whether the option was negated. */
5364 void (*pfn
) (int arg
, int on
);
5366 /* If this is not NULL, and the PFN field is NULL, set the variable
5367 this points to. Set it to the ARG field if the option was not
5368 negated, and the NOTARG field otherwise. */
5371 /* The value to pass to PFN or to assign to *PVAR. */
5374 /* The value to assign to *PVAR if the option is negated. If PFN is
5375 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5376 the option may not be negated. */
5380 /* The table used to handle the MRI OPT pseudo-op. */
5382 static void skip_to_comma (int, int);
5383 static void opt_nest (int, int);
5384 static void opt_chip (int, int);
5385 static void opt_list (int, int);
5386 static void opt_list_symbols (int, int);
5388 static const struct opt_action opt_table
[] =
5390 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5392 /* We do relaxing, so there is little use for these options. */
5393 { "b", 0, 0, 0, 0 },
5394 { "brs", 0, 0, 0, 0 },
5395 { "brb", 0, 0, 0, 0 },
5396 { "brl", 0, 0, 0, 0 },
5397 { "brw", 0, 0, 0, 0 },
5399 { "c", 0, 0, 0, 0 },
5400 { "cex", 0, 0, 0, 0 },
5401 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5402 { "cl", 0, 0, 0, 0 },
5403 { "cre", 0, 0, 0, 0 },
5404 { "d", 0, &flag_keep_locals
, 1, 0 },
5405 { "e", 0, 0, 0, 0 },
5406 { "f", 0, &flag_short_refs
, 1, 0 },
5407 { "frs", 0, &flag_short_refs
, 1, 0 },
5408 { "frl", 0, &flag_short_refs
, 0, 1 },
5409 { "g", 0, 0, 0, 0 },
5410 { "i", 0, 0, 0, 0 },
5411 { "m", 0, 0, 0, 0 },
5412 { "mex", 0, 0, 0, 0 },
5413 { "mc", 0, 0, 0, 0 },
5414 { "md", 0, 0, 0, 0 },
5415 { "nest", opt_nest
, 0, 0, 0 },
5416 { "next", skip_to_comma
, 0, 0, 0 },
5417 { "o", 0, 0, 0, 0 },
5418 { "old", 0, 0, 0, 0 },
5419 { "op", skip_to_comma
, 0, 0, 0 },
5420 { "pco", 0, 0, 0, 0 },
5421 { "p", opt_chip
, 0, 0, 0 },
5422 { "pcr", 0, 0, 0, 0 },
5423 { "pcs", 0, 0, 0, 0 },
5424 { "r", 0, 0, 0, 0 },
5425 { "quick", 0, &m68k_quick
, 1, 0 },
5426 { "rel32", 0, &m68k_rel32
, 1, 0 },
5427 { "s", opt_list
, 0, 0, 0 },
5428 { "t", opt_list_symbols
, 0, 0, 0 },
5429 { "w", 0, &flag_no_warnings
, 0, 1 },
5433 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5435 /* The MRI OPT pseudo-op. */
5438 s_opt (int ignore ATTRIBUTE_UNUSED
)
5446 const struct opt_action
*o
;
5451 if (*input_line_pointer
== '-')
5453 ++input_line_pointer
;
5456 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5458 input_line_pointer
+= 2;
5462 s
= input_line_pointer
;
5463 c
= get_symbol_end ();
5465 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5467 if (strcasecmp (s
, o
->name
) == 0)
5471 /* Restore input_line_pointer now in case the option
5473 *input_line_pointer
= c
;
5474 (*o
->pfn
) (o
->arg
, t
);
5476 else if (o
->pvar
!= NULL
)
5478 if (! t
&& o
->arg
== o
->notarg
)
5479 as_bad (_("option `%s' may not be negated"), s
);
5480 *input_line_pointer
= c
;
5481 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5484 *input_line_pointer
= c
;
5490 as_bad (_("option `%s' not recognized"), s
);
5491 *input_line_pointer
= c
;
5494 while (*input_line_pointer
++ == ',');
5496 /* Move back to terminating character. */
5497 --input_line_pointer
;
5498 demand_empty_rest_of_line ();
5501 /* Skip ahead to a comma. This is used for OPT options which we do
5502 not support and which take arguments. */
5505 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5507 while (*input_line_pointer
!= ','
5508 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5509 ++input_line_pointer
;
5512 /* Handle the OPT NEST=depth option. */
5515 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5517 if (*input_line_pointer
!= '=')
5519 as_bad (_("bad format of OPT NEST=depth"));
5523 ++input_line_pointer
;
5524 max_macro_nest
= get_absolute_expression ();
5527 /* Handle the OPT P=chip option. */
5530 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5532 if (*input_line_pointer
!= '=')
5534 /* This is just OPT P, which we do not support. */
5538 ++input_line_pointer
;
5542 /* Handle the OPT S option. */
5545 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5550 /* Handle the OPT T option. */
5553 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5556 listing
|= LISTING_SYMBOLS
;
5558 listing
&= ~LISTING_SYMBOLS
;
5561 /* Handle the MRI REG pseudo-op. */
5564 s_reg (int ignore ATTRIBUTE_UNUSED
)
5573 if (line_label
== NULL
)
5575 as_bad (_("missing label"));
5576 ignore_rest_of_line ();
5581 stop
= mri_comment_field (&stopc
);
5585 s
= input_line_pointer
;
5586 while (ISALNUM (*input_line_pointer
)
5587 #ifdef REGISTER_PREFIX
5588 || *input_line_pointer
== REGISTER_PREFIX
5590 || *input_line_pointer
== '/'
5591 || *input_line_pointer
== '-')
5592 ++input_line_pointer
;
5593 c
= *input_line_pointer
;
5594 *input_line_pointer
= '\0';
5596 if (m68k_ip_op (s
, &rop
) != 0)
5598 if (rop
.error
== NULL
)
5599 as_bad (_("bad register list"));
5601 as_bad (_("bad register list: %s"), rop
.error
);
5602 *input_line_pointer
= c
;
5603 ignore_rest_of_line ();
5607 *input_line_pointer
= c
;
5609 if (rop
.mode
== REGLST
)
5611 else if (rop
.mode
== DREG
)
5612 mask
= 1 << (rop
.reg
- DATA0
);
5613 else if (rop
.mode
== AREG
)
5614 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5615 else if (rop
.mode
== FPREG
)
5616 mask
= 1 << (rop
.reg
- FP0
+ 16);
5617 else if (rop
.mode
== CONTROL
5620 else if (rop
.mode
== CONTROL
5623 else if (rop
.mode
== CONTROL
5628 as_bad (_("bad register list"));
5629 ignore_rest_of_line ();
5633 S_SET_SEGMENT (line_label
, reg_section
);
5634 S_SET_VALUE (line_label
, ~mask
);
5635 symbol_set_frag (line_label
, &zero_address_frag
);
5638 mri_comment_end (stop
, stopc
);
5640 demand_empty_rest_of_line ();
5643 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5647 struct save_opts
*next
;
5649 int symbols_case_sensitive
;
5653 const enum m68k_register
*control_regs
;
5658 /* FIXME: We don't save OPT S. */
5661 /* This variable holds the stack of saved options. */
5663 static struct save_opts
*save_stack
;
5665 /* The MRI SAVE pseudo-op. */
5668 s_save (int ignore ATTRIBUTE_UNUSED
)
5670 struct save_opts
*s
;
5672 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5673 s
->abspcadd
= m68k_abspcadd
;
5674 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5675 s
->keep_locals
= flag_keep_locals
;
5676 s
->short_refs
= flag_short_refs
;
5677 s
->architecture
= current_architecture
;
5678 s
->control_regs
= control_regs
;
5679 s
->quick
= m68k_quick
;
5680 s
->rel32
= m68k_rel32
;
5681 s
->listing
= listing
;
5682 s
->no_warnings
= flag_no_warnings
;
5684 s
->next
= save_stack
;
5687 demand_empty_rest_of_line ();
5690 /* The MRI RESTORE pseudo-op. */
5693 s_restore (int ignore ATTRIBUTE_UNUSED
)
5695 struct save_opts
*s
;
5697 if (save_stack
== NULL
)
5699 as_bad (_("restore without save"));
5700 ignore_rest_of_line ();
5705 save_stack
= s
->next
;
5707 m68k_abspcadd
= s
->abspcadd
;
5708 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5709 flag_keep_locals
= s
->keep_locals
;
5710 flag_short_refs
= s
->short_refs
;
5711 current_architecture
= s
->architecture
;
5712 control_regs
= s
->control_regs
;
5713 m68k_quick
= s
->quick
;
5714 m68k_rel32
= s
->rel32
;
5715 listing
= s
->listing
;
5716 flag_no_warnings
= s
->no_warnings
;
5720 demand_empty_rest_of_line ();
5723 /* Types of MRI structured control directives. */
5725 enum mri_control_type
5733 /* This structure is used to stack the MRI structured control
5736 struct mri_control_info
5738 /* The directive within which this one is enclosed. */
5739 struct mri_control_info
*outer
;
5741 /* The type of directive. */
5742 enum mri_control_type type
;
5744 /* Whether an ELSE has been in an IF. */
5747 /* The add or sub statement at the end of a FOR. */
5750 /* The label of the top of a FOR or REPEAT loop. */
5753 /* The label to jump to for the next iteration, or the else
5754 expression of a conditional. */
5757 /* The label to jump to to break out of the loop, or the label past
5758 the end of a conditional. */
5762 /* The stack of MRI structured control directives. */
5764 static struct mri_control_info
*mri_control_stack
;
5766 /* The current MRI structured control directive index number, used to
5767 generate label names. */
5769 static int mri_control_index
;
5771 /* Assemble an instruction for an MRI structured control directive. */
5774 mri_assemble (char *str
)
5778 /* md_assemble expects the opcode to be in lower case. */
5779 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5785 /* Generate a new MRI label structured control directive label name. */
5788 mri_control_label (void)
5792 n
= (char *) xmalloc (20);
5793 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5794 ++mri_control_index
;
5798 /* Create a new MRI structured control directive. */
5800 static struct mri_control_info
*
5801 push_mri_control (enum mri_control_type type
)
5803 struct mri_control_info
*n
;
5805 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5809 if (type
== mri_if
|| type
== mri_while
)
5812 n
->top
= mri_control_label ();
5813 n
->next
= mri_control_label ();
5814 n
->bottom
= mri_control_label ();
5816 n
->outer
= mri_control_stack
;
5817 mri_control_stack
= n
;
5822 /* Pop off the stack of MRI structured control directives. */
5825 pop_mri_control (void)
5827 struct mri_control_info
*n
;
5829 n
= mri_control_stack
;
5830 mri_control_stack
= n
->outer
;
5838 /* Recognize a condition code in an MRI structured control expression. */
5841 parse_mri_condition (int *pcc
)
5845 know (*input_line_pointer
== '<');
5847 ++input_line_pointer
;
5848 c1
= *input_line_pointer
++;
5849 c2
= *input_line_pointer
++;
5851 if (*input_line_pointer
!= '>')
5853 as_bad (_("syntax error in structured control directive"));
5857 ++input_line_pointer
;
5863 *pcc
= (c1
<< 8) | c2
;
5868 /* Parse a single operand in an MRI structured control expression. */
5871 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
5872 char **rightstart
, char **rightstop
)
5884 if (*input_line_pointer
== '<')
5886 /* It's just a condition code. */
5887 return parse_mri_condition (pcc
);
5890 /* Look ahead for the condition code. */
5891 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5893 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5898 as_bad (_("missing condition code in structured control directive"));
5902 *leftstart
= input_line_pointer
;
5904 if (*leftstop
> *leftstart
5905 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5908 input_line_pointer
= s
;
5909 if (! parse_mri_condition (pcc
))
5912 /* Look ahead for AND or OR or end of line. */
5913 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5915 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5916 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5918 if ((s
== input_line_pointer
5921 && ((strncasecmp (s
, "AND", 3) == 0
5922 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5923 || (strncasecmp (s
, "OR", 2) == 0
5924 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
5928 *rightstart
= input_line_pointer
;
5930 if (*rightstop
> *rightstart
5931 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5934 input_line_pointer
= s
;
5939 #define MCC(b1, b2) (((b1) << 8) | (b2))
5941 /* Swap the sense of a condition. This changes the condition so that
5942 it generates the same result when the operands are swapped. */
5945 swap_mri_condition (int cc
)
5949 case MCC ('h', 'i'): return MCC ('c', 's');
5950 case MCC ('l', 's'): return MCC ('c', 'c');
5951 /* <HS> is an alias for <CC>. */
5952 case MCC ('h', 's'):
5953 case MCC ('c', 'c'): return MCC ('l', 's');
5954 /* <LO> is an alias for <CS>. */
5955 case MCC ('l', 'o'):
5956 case MCC ('c', 's'): return MCC ('h', 'i');
5957 case MCC ('p', 'l'): return MCC ('m', 'i');
5958 case MCC ('m', 'i'): return MCC ('p', 'l');
5959 case MCC ('g', 'e'): return MCC ('l', 'e');
5960 case MCC ('l', 't'): return MCC ('g', 't');
5961 case MCC ('g', 't'): return MCC ('l', 't');
5962 case MCC ('l', 'e'): return MCC ('g', 'e');
5963 /* Issue a warning for conditions we can not swap. */
5964 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5965 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5966 case MCC ('v', 'c'):
5967 case MCC ('v', 's'):
5969 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5970 (char) (cc
>> 8), (char) (cc
));
5976 /* Reverse the sense of a condition. */
5979 reverse_mri_condition (int cc
)
5983 case MCC ('h', 'i'): return MCC ('l', 's');
5984 case MCC ('l', 's'): return MCC ('h', 'i');
5985 /* <HS> is an alias for <CC> */
5986 case MCC ('h', 's'): return MCC ('l', 'o');
5987 case MCC ('c', 'c'): return MCC ('c', 's');
5988 /* <LO> is an alias for <CS> */
5989 case MCC ('l', 'o'): return MCC ('h', 's');
5990 case MCC ('c', 's'): return MCC ('c', 'c');
5991 case MCC ('n', 'e'): return MCC ('e', 'q');
5992 case MCC ('e', 'q'): return MCC ('n', 'e');
5993 case MCC ('v', 'c'): return MCC ('v', 's');
5994 case MCC ('v', 's'): return MCC ('v', 'c');
5995 case MCC ('p', 'l'): return MCC ('m', 'i');
5996 case MCC ('m', 'i'): return MCC ('p', 'l');
5997 case MCC ('g', 'e'): return MCC ('l', 't');
5998 case MCC ('l', 't'): return MCC ('g', 'e');
5999 case MCC ('g', 't'): return MCC ('l', 'e');
6000 case MCC ('l', 'e'): return MCC ('g', 't');
6005 /* Build an MRI structured control expression. This generates test
6006 and branch instructions. It goes to TRUELAB if the condition is
6007 true, and to FALSELAB if the condition is false. Exactly one of
6008 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6009 is the size qualifier for the expression. EXTENT is the size to
6010 use for the branch. */
6013 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6014 char *rightstart
, char *rightstop
,
6015 const char *truelab
, const char *falselab
,
6021 if (leftstart
!= NULL
)
6023 struct m68k_op leftop
, rightop
;
6026 /* Swap the compare operands, if necessary, to produce a legal
6027 m68k compare instruction. Comparing a register operand with
6028 a non-register operand requires the register to be on the
6029 right (cmp, cmpa). Comparing an immediate value with
6030 anything requires the immediate value to be on the left
6035 (void) m68k_ip_op (leftstart
, &leftop
);
6040 (void) m68k_ip_op (rightstart
, &rightop
);
6043 if (rightop
.mode
== IMMED
6044 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6045 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6049 /* Correct conditional handling:
6050 if #1 <lt> d0 then ;means if (1 < d0)
6056 cmp #1,d0 if we do *not* swap the operands
6057 bgt true we need the swapped condition!
6064 leftstart
= rightstart
;
6067 leftstop
= rightstop
;
6072 cc
= swap_mri_condition (cc
);
6076 if (truelab
== NULL
)
6078 cc
= reverse_mri_condition (cc
);
6082 if (leftstart
!= NULL
)
6084 buf
= (char *) xmalloc (20
6085 + (leftstop
- leftstart
)
6086 + (rightstop
- rightstart
));
6092 *s
++ = TOLOWER (qual
);
6094 memcpy (s
, leftstart
, leftstop
- leftstart
);
6095 s
+= leftstop
- leftstart
;
6097 memcpy (s
, rightstart
, rightstop
- rightstart
);
6098 s
+= rightstop
- rightstart
;
6104 buf
= (char *) xmalloc (20 + strlen (truelab
));
6110 *s
++ = TOLOWER (extent
);
6112 strcpy (s
, truelab
);
6117 /* Parse an MRI structured control expression. This generates test
6118 and branch instructions. STOP is where the expression ends. It
6119 goes to TRUELAB if the condition is true, and to FALSELAB if the
6120 condition is false. Exactly one of TRUELAB and FALSELAB will be
6121 NULL, meaning to fall through. QUAL is the size qualifier for the
6122 expression. EXTENT is the size to use for the branch. */
6125 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6126 const char *falselab
, int extent
)
6138 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6139 &rightstart
, &rightstop
))
6145 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6149 if (falselab
!= NULL
)
6152 flab
= mri_control_label ();
6154 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6155 rightstop
, (const char *) NULL
, flab
, extent
);
6157 input_line_pointer
+= 3;
6158 if (*input_line_pointer
!= '.'
6159 || input_line_pointer
[1] == '\0')
6163 qual
= input_line_pointer
[1];
6164 input_line_pointer
+= 2;
6167 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6168 &rightstart
, &rightstop
))
6174 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6175 rightstop
, truelab
, falselab
, extent
);
6177 if (falselab
== NULL
)
6180 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6184 if (truelab
!= NULL
)
6187 tlab
= mri_control_label ();
6189 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6190 rightstop
, tlab
, (const char *) NULL
, extent
);
6192 input_line_pointer
+= 2;
6193 if (*input_line_pointer
!= '.'
6194 || input_line_pointer
[1] == '\0')
6198 qual
= input_line_pointer
[1];
6199 input_line_pointer
+= 2;
6202 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6203 &rightstart
, &rightstop
))
6209 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6210 rightstop
, truelab
, falselab
, extent
);
6212 if (truelab
== NULL
)
6217 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6218 rightstop
, truelab
, falselab
, extent
);
6222 if (input_line_pointer
!= stop
)
6223 as_bad (_("syntax error in structured control directive"));
6226 /* Handle the MRI IF pseudo-op. This may be a structured control
6227 directive, or it may be a regular assembler conditional, depending
6235 struct mri_control_info
*n
;
6237 /* A structured control directive must end with THEN with an
6238 optional qualifier. */
6239 s
= input_line_pointer
;
6240 /* We only accept '*' as introduction of comments if preceded by white space
6241 or at first column of a line (I think this can't actually happen here?)
6242 This is important when assembling:
6243 if d0 <ne> 12(a0,d0*2) then
6244 if d0 <ne> #CONST*20 then. */
6245 while (! (is_end_of_line
[(unsigned char) *s
]
6248 && (s
== input_line_pointer
6250 || *(s
-1) == '\t'))))
6253 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6256 if (s
- input_line_pointer
> 1
6260 if (s
- input_line_pointer
< 3
6261 || strncasecmp (s
- 3, "THEN", 4) != 0)
6265 as_bad (_("missing then"));
6266 ignore_rest_of_line ();
6270 /* It's a conditional. */
6275 /* Since this might be a conditional if, this pseudo-op will be
6276 called even if we are supported to be ignoring input. Double
6277 check now. Clobber *input_line_pointer so that ignore_input
6278 thinks that this is not a special pseudo-op. */
6279 c
= *input_line_pointer
;
6280 *input_line_pointer
= 0;
6281 if (ignore_input ())
6283 *input_line_pointer
= c
;
6284 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6285 ++input_line_pointer
;
6286 demand_empty_rest_of_line ();
6289 *input_line_pointer
= c
;
6291 n
= push_mri_control (mri_if
);
6293 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6294 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6297 input_line_pointer
= s
+ 3;
6299 input_line_pointer
= s
+ 1;
6303 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6304 ++input_line_pointer
;
6307 demand_empty_rest_of_line ();
6310 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6311 structured IF, associate the ELSE with the IF. Otherwise, assume
6312 it is a conditional else. */
6315 s_mri_else (int qual
)
6322 && (mri_control_stack
== NULL
6323 || mri_control_stack
->type
!= mri_if
6324 || mri_control_stack
->else_seen
))
6330 c
= *input_line_pointer
;
6331 *input_line_pointer
= 0;
6332 if (ignore_input ())
6334 *input_line_pointer
= c
;
6335 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6336 ++input_line_pointer
;
6337 demand_empty_rest_of_line ();
6340 *input_line_pointer
= c
;
6342 if (mri_control_stack
== NULL
6343 || mri_control_stack
->type
!= mri_if
6344 || mri_control_stack
->else_seen
)
6346 as_bad (_("else without matching if"));
6347 ignore_rest_of_line ();
6351 mri_control_stack
->else_seen
= 1;
6353 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6354 q
[0] = TOLOWER (qual
);
6356 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6360 colon (mri_control_stack
->next
);
6364 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6365 ++input_line_pointer
;
6368 demand_empty_rest_of_line ();
6371 /* Handle the MRI ENDI pseudo-op. */
6374 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6376 if (mri_control_stack
== NULL
6377 || mri_control_stack
->type
!= mri_if
)
6379 as_bad (_("endi without matching if"));
6380 ignore_rest_of_line ();
6384 /* ignore_input will not return true for ENDI, so we don't need to
6385 worry about checking it again here. */
6387 if (! mri_control_stack
->else_seen
)
6388 colon (mri_control_stack
->next
);
6389 colon (mri_control_stack
->bottom
);
6395 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6396 ++input_line_pointer
;
6399 demand_empty_rest_of_line ();
6402 /* Handle the MRI BREAK pseudo-op. */
6405 s_mri_break (int extent
)
6407 struct mri_control_info
*n
;
6411 n
= mri_control_stack
;
6413 && n
->type
!= mri_for
6414 && n
->type
!= mri_repeat
6415 && n
->type
!= mri_while
)
6419 as_bad (_("break outside of structured loop"));
6420 ignore_rest_of_line ();
6424 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6425 ex
[0] = TOLOWER (extent
);
6427 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6433 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6434 ++input_line_pointer
;
6437 demand_empty_rest_of_line ();
6440 /* Handle the MRI NEXT pseudo-op. */
6443 s_mri_next (int extent
)
6445 struct mri_control_info
*n
;
6449 n
= mri_control_stack
;
6451 && n
->type
!= mri_for
6452 && n
->type
!= mri_repeat
6453 && n
->type
!= mri_while
)
6457 as_bad (_("next outside of structured loop"));
6458 ignore_rest_of_line ();
6462 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6463 ex
[0] = TOLOWER (extent
);
6465 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6471 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6472 ++input_line_pointer
;
6475 demand_empty_rest_of_line ();
6478 /* Handle the MRI FOR pseudo-op. */
6481 s_mri_for (int qual
)
6483 const char *varstart
, *varstop
;
6484 const char *initstart
, *initstop
;
6485 const char *endstart
, *endstop
;
6486 const char *bystart
, *bystop
;
6490 struct mri_control_info
*n
;
6496 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6500 varstart
= input_line_pointer
;
6502 /* Look for the '='. */
6503 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6504 && *input_line_pointer
!= '=')
6505 ++input_line_pointer
;
6506 if (*input_line_pointer
!= '=')
6508 as_bad (_("missing ="));
6509 ignore_rest_of_line ();
6513 varstop
= input_line_pointer
;
6514 if (varstop
> varstart
6515 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6518 ++input_line_pointer
;
6520 initstart
= input_line_pointer
;
6522 /* Look for TO or DOWNTO. */
6525 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6527 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6528 && ! is_part_of_name (input_line_pointer
[2]))
6530 initstop
= input_line_pointer
;
6531 input_line_pointer
+= 2;
6534 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6535 && ! is_part_of_name (input_line_pointer
[6]))
6537 initstop
= input_line_pointer
;
6539 input_line_pointer
+= 6;
6542 ++input_line_pointer
;
6544 if (initstop
== NULL
)
6546 as_bad (_("missing to or downto"));
6547 ignore_rest_of_line ();
6550 if (initstop
> initstart
6551 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6555 endstart
= input_line_pointer
;
6557 /* Look for BY or DO. */
6560 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6562 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6563 && ! is_part_of_name (input_line_pointer
[2]))
6565 endstop
= input_line_pointer
;
6567 input_line_pointer
+= 2;
6570 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6571 && (input_line_pointer
[2] == '.'
6572 || ! is_part_of_name (input_line_pointer
[2])))
6574 endstop
= input_line_pointer
;
6575 input_line_pointer
+= 2;
6578 ++input_line_pointer
;
6580 if (endstop
== NULL
)
6582 as_bad (_("missing do"));
6583 ignore_rest_of_line ();
6586 if (endstop
> endstart
6587 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6593 bystop
= bystart
+ 2;
6598 bystart
= input_line_pointer
;
6602 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6604 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6605 && (input_line_pointer
[2] == '.'
6606 || ! is_part_of_name (input_line_pointer
[2])))
6608 bystop
= input_line_pointer
;
6609 input_line_pointer
+= 2;
6612 ++input_line_pointer
;
6616 as_bad (_("missing do"));
6617 ignore_rest_of_line ();
6620 if (bystop
> bystart
6621 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6625 if (*input_line_pointer
!= '.')
6629 extent
= input_line_pointer
[1];
6630 input_line_pointer
+= 2;
6633 /* We have fully parsed the FOR operands. Now build the loop. */
6634 n
= push_mri_control (mri_for
);
6636 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6638 /* Move init,var. */
6645 *s
++ = TOLOWER (qual
);
6647 memcpy (s
, initstart
, initstop
- initstart
);
6648 s
+= initstop
- initstart
;
6650 memcpy (s
, varstart
, varstop
- varstart
);
6651 s
+= varstop
- varstart
;
6663 *s
++ = TOLOWER (qual
);
6665 memcpy (s
, endstart
, endstop
- endstart
);
6666 s
+= endstop
- endstart
;
6668 memcpy (s
, varstart
, varstop
- varstart
);
6669 s
+= varstop
- varstart
;
6674 ex
[0] = TOLOWER (extent
);
6677 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6679 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6682 /* Put together the add or sub instruction used by ENDF. */
6690 *s
++ = TOLOWER (qual
);
6692 memcpy (s
, bystart
, bystop
- bystart
);
6693 s
+= bystop
- bystart
;
6695 memcpy (s
, varstart
, varstop
- varstart
);
6696 s
+= varstop
- varstart
;
6702 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6703 ++input_line_pointer
;
6706 demand_empty_rest_of_line ();
6709 /* Handle the MRI ENDF pseudo-op. */
6712 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6714 if (mri_control_stack
== NULL
6715 || mri_control_stack
->type
!= mri_for
)
6717 as_bad (_("endf without for"));
6718 ignore_rest_of_line ();
6722 colon (mri_control_stack
->next
);
6724 mri_assemble (mri_control_stack
->incr
);
6726 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6727 mri_assemble (mri_control_stack
->incr
);
6729 free (mri_control_stack
->incr
);
6731 colon (mri_control_stack
->bottom
);
6737 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6738 ++input_line_pointer
;
6741 demand_empty_rest_of_line ();
6744 /* Handle the MRI REPEAT pseudo-op. */
6747 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6749 struct mri_control_info
*n
;
6751 n
= push_mri_control (mri_repeat
);
6755 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6756 ++input_line_pointer
;
6758 demand_empty_rest_of_line ();
6761 /* Handle the MRI UNTIL pseudo-op. */
6764 s_mri_until (int qual
)
6768 if (mri_control_stack
== NULL
6769 || mri_control_stack
->type
!= mri_repeat
)
6771 as_bad (_("until without repeat"));
6772 ignore_rest_of_line ();
6776 colon (mri_control_stack
->next
);
6778 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6781 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6782 mri_control_stack
->top
, '\0');
6784 colon (mri_control_stack
->bottom
);
6786 input_line_pointer
= s
;
6792 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6793 ++input_line_pointer
;
6796 demand_empty_rest_of_line ();
6799 /* Handle the MRI WHILE pseudo-op. */
6802 s_mri_while (int qual
)
6806 struct mri_control_info
*n
;
6808 s
= input_line_pointer
;
6809 /* We only accept '*' as introduction of comments if preceded by white space
6810 or at first column of a line (I think this can't actually happen here?)
6811 This is important when assembling:
6812 while d0 <ne> 12(a0,d0*2) do
6813 while d0 <ne> #CONST*20 do. */
6814 while (! (is_end_of_line
[(unsigned char) *s
]
6817 && (s
== input_line_pointer
6819 || *(s
-1) == '\t'))))
6822 while (*s
== ' ' || *s
== '\t')
6824 if (s
- input_line_pointer
> 1
6827 if (s
- input_line_pointer
< 2
6828 || strncasecmp (s
- 1, "DO", 2) != 0)
6830 as_bad (_("missing do"));
6831 ignore_rest_of_line ();
6835 n
= push_mri_control (mri_while
);
6839 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6840 s
[1] == '.' ? s
[2] : '\0');
6842 input_line_pointer
= s
+ 1;
6843 if (*input_line_pointer
== '.')
6844 input_line_pointer
+= 2;
6848 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6849 ++input_line_pointer
;
6852 demand_empty_rest_of_line ();
6855 /* Handle the MRI ENDW pseudo-op. */
6858 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
6862 if (mri_control_stack
== NULL
6863 || mri_control_stack
->type
!= mri_while
)
6865 as_bad (_("endw without while"));
6866 ignore_rest_of_line ();
6870 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6871 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6875 colon (mri_control_stack
->bottom
);
6881 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6882 ++input_line_pointer
;
6885 demand_empty_rest_of_line ();
6888 /* Parse a .cpu directive. */
6891 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
6898 as_bad (_("already assembled instructions"));
6899 ignore_rest_of_line ();
6903 name
= input_line_pointer
;
6904 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
6905 input_line_pointer
++;
6906 saved_char
= *input_line_pointer
;
6907 *input_line_pointer
= 0;
6909 m68k_set_cpu (name
, 1, 0);
6911 *input_line_pointer
= saved_char
;
6912 demand_empty_rest_of_line ();
6916 /* Parse a .arch directive. */
6919 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
6926 as_bad (_("already assembled instructions"));
6927 ignore_rest_of_line ();
6931 name
= input_line_pointer
;
6932 while (*input_line_pointer
&& *input_line_pointer
!= ','
6933 && !ISSPACE (*input_line_pointer
))
6934 input_line_pointer
++;
6935 saved_char
= *input_line_pointer
;
6936 *input_line_pointer
= 0;
6938 if (m68k_set_arch (name
, 1, 0))
6940 /* Scan extensions. */
6943 *input_line_pointer
++ = saved_char
;
6944 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
6946 name
= input_line_pointer
;
6947 while (*input_line_pointer
&& *input_line_pointer
!= ','
6948 && !ISSPACE (*input_line_pointer
))
6949 input_line_pointer
++;
6950 saved_char
= *input_line_pointer
;
6951 *input_line_pointer
= 0;
6953 while (m68k_set_extension (name
, 1, 0));
6956 *input_line_pointer
= saved_char
;
6957 demand_empty_rest_of_line ();
6961 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
6962 if none is found, the caller is responsible for emitting an error
6963 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6964 cpu name, if it begins with a '6' (possibly skipping an intervening
6965 'c'. We also allow a 'c' in the same place. if NEGATED is
6966 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6967 the option is indeed negated. */
6969 static const struct m68k_cpu
*
6970 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
6971 int allow_m
, int *negated
)
6973 /* allow negated value? */
6978 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
6985 /* Remove 'm' or 'mc' prefix from 68k variants. */
6992 else if (arg
[1] == 'c' && arg
[2] == '6')
6996 else if (arg
[0] == 'c' && arg
[1] == '6')
6999 for (; table
->name
; table
++)
7000 if (!strcmp (arg
, table
->name
))
7002 if (table
->alias
< -1 || table
->alias
> 1)
7003 as_bad (_("`%s' is deprecated, use `%s'"),
7004 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7010 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7013 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7015 const struct m68k_cpu
*cpu
;
7017 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7022 as_bad (_("cpu `%s' unrecognized"), name
);
7026 if (selected_cpu
&& selected_cpu
!= cpu
)
7028 as_bad (_("already selected `%s' processor"),
7029 selected_cpu
->name
);
7036 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7039 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7041 const struct m68k_cpu
*arch
;
7043 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7048 as_bad (_("architecture `%s' unrecognized"), name
);
7052 if (selected_arch
&& selected_arch
!= arch
)
7054 as_bad (_("already selected `%s' architecture"),
7055 selected_arch
->name
);
7059 selected_arch
= arch
;
7063 /* Set the architecture extension, issuing errors if it is
7064 unrecognized, or invalid */
7067 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7070 const struct m68k_cpu
*ext
;
7072 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7077 as_bad (_("extension `%s' unrecognized"), name
);
7082 not_current_architecture
|= ext
->arch
;
7084 current_architecture
|= ext
->arch
;
7089 Invocation line includes a switch not recognized by the base assembler.
7093 const char *md_shortopts
= "lSA:m:kQ:V";
7095 const char *md_shortopts
= "lSA:m:k";
7098 struct option md_longopts
[] = {
7099 #define OPTION_PIC (OPTION_MD_BASE)
7100 {"pic", no_argument
, NULL
, OPTION_PIC
},
7101 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7102 {"register-prefix-optional", no_argument
, NULL
,
7103 OPTION_REGISTER_PREFIX_OPTIONAL
},
7104 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7105 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7106 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7107 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7108 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7109 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7110 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7111 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7112 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7113 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7114 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7115 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7116 {NULL
, no_argument
, NULL
, 0}
7118 size_t md_longopts_size
= sizeof (md_longopts
);
7121 md_parse_option (int c
, char *arg
)
7125 case 'l': /* -l means keep external to 2 bit offset
7126 rather than 16 bit one. */
7127 flag_short_refs
= 1;
7130 case 'S': /* -S means that jbsr's always turn into
7132 flag_long_jumps
= 1;
7135 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7136 branches into absolute jumps. */
7137 flag_keep_pcrel
= 1;
7143 break; /* -pic, Position Independent Code. */
7145 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7146 flag_reg_prefix_optional
= 1;
7147 reg_prefix_optional_seen
= 1;
7150 /* -V: SVR4 argument to print version ID. */
7152 print_version_id ();
7155 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7156 should be emitted or not. FIXME: Not implemented. */
7160 case OPTION_BITWISE_OR
:
7165 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7167 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7171 m68k_comment_chars
= n
;
7175 case OPTION_BASE_SIZE_DEFAULT_16
:
7176 m68k_index_width_default
= SIZE_WORD
;
7179 case OPTION_BASE_SIZE_DEFAULT_32
:
7180 m68k_index_width_default
= SIZE_LONG
;
7183 case OPTION_DISP_SIZE_DEFAULT_16
:
7185 m68k_rel32_from_cmdline
= 1;
7188 case OPTION_DISP_SIZE_DEFAULT_32
:
7190 m68k_rel32_from_cmdline
= 1;
7195 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7198 /* Intentional fall-through. */
7200 if (!strncmp (arg
, "arch=", 5))
7201 m68k_set_arch (arg
+ 5, 1, 0);
7202 else if (!strncmp (arg
, "cpu=", 4))
7203 m68k_set_cpu (arg
+ 4, 1, 0);
7204 else if (m68k_set_extension (arg
, 0, 1))
7206 else if (m68k_set_arch (arg
, 0, 1))
7208 else if (m68k_set_cpu (arg
, 0, 1))
7221 /* Setup tables from the selected arch and/or cpu */
7224 m68k_init_arch (void)
7226 if (not_current_architecture
& current_architecture
)
7228 as_bad (_("architecture features both enabled and disabled"));
7229 not_current_architecture
&= ~current_architecture
;
7233 current_architecture
|= selected_arch
->arch
;
7234 control_regs
= selected_arch
->control_regs
;
7237 current_architecture
|= selected_cpu
->arch
;
7239 current_architecture
&= ~not_current_architecture
;
7241 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7243 /* Determine which float is really meant. */
7244 if (current_architecture
& (m68k_mask
& ~m68881
))
7245 current_architecture
^= cfloat
;
7247 current_architecture
^= m68881
;
7252 control_regs
= selected_cpu
->control_regs
;
7253 if (current_architecture
& ~selected_cpu
->arch
)
7255 as_bad (_("selected processor does not have all features of selected architecture"));
7256 current_architecture
7257 = selected_cpu
->arch
& ~not_current_architecture
;
7261 if ((current_architecture
& m68k_mask
)
7262 && (current_architecture
& ~m68k_mask
))
7264 as_bad (_ ("m68k and cf features both selected"));
7265 if (current_architecture
& m68k_mask
)
7266 current_architecture
&= m68k_mask
;
7268 current_architecture
&= ~m68k_mask
;
7271 /* Permit m68881 specification with all cpus; those that can't work
7272 with a coprocessor could be doing emulation. */
7273 if (current_architecture
& m68851
)
7275 if (current_architecture
& m68040
)
7276 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7278 /* What other incompatibilities could we check for? */
7280 if (cpu_of_arch (current_architecture
) < m68020
7281 || arch_coldfire_p (current_architecture
))
7282 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7288 md_show_usage (FILE *stream
)
7290 const char *default_cpu
= TARGET_CPU
;
7292 unsigned int default_arch
;
7294 /* Get the canonical name for the default target CPU. */
7295 if (*default_cpu
== 'm')
7297 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7299 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7301 default_arch
= m68k_cpus
[i
].arch
;
7302 while (m68k_cpus
[i
].alias
> 0)
7304 while (m68k_cpus
[i
].alias
< 0)
7306 default_cpu
= m68k_cpus
[i
].name
;
7310 fprintf (stream
, _("\
7311 -march=<arch> set architecture\n\
7312 -mcpu=<cpu> set cpu [default %s]\n\
7314 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7315 fprintf (stream
, _("\
7316 -m[no-]%-16s enable/disable%s architecture extension\n\
7317 "), m68k_extensions
[i
].name
,
7318 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7319 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7321 fprintf (stream
, _("\
7322 -l use 1 word for refs to undefined symbols [default 2]\n\
7323 -pic, -k generate position independent code\n\
7324 -S turn jbsr into jsr\n\
7325 --pcrel never turn PC-relative branches into absolute jumps\n\
7326 --register-prefix-optional\n\
7327 recognize register names without prefix character\n\
7328 --bitwise-or do not treat `|' as a comment character\n\
7329 --base-size-default-16 base reg without size is 16 bits\n\
7330 --base-size-default-32 base reg without size is 32 bits (default)\n\
7331 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7332 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7335 fprintf (stream
, _("Architecture variants are: "));
7336 for (i
= 0; m68k_archs
[i
].name
; i
++)
7339 fprintf (stream
, " | ");
7340 fprintf (stream
, m68k_archs
[i
].name
);
7342 fprintf (stream
, "\n");
7344 fprintf (stream
, _("Processor variants are: "));
7345 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7348 fprintf (stream
, " | ");
7349 fprintf (stream
, m68k_cpus
[i
].name
);
7351 fprintf (stream
, _("\n"));
7356 /* TEST2: Test md_assemble() */
7357 /* Warning, this routine probably doesn't work anymore. */
7361 struct m68k_it the_ins
;
7369 if (!gets (buf
) || !*buf
)
7371 if (buf
[0] == '|' || buf
[1] == '.')
7373 for (cp
= buf
; *cp
; cp
++)
7378 memset (&the_ins
, '\0', sizeof (the_ins
));
7379 m68k_ip (&the_ins
, buf
);
7382 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7386 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7387 for (n
= 0; n
< the_ins
.numo
; n
++)
7388 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7390 print_the_insn (&the_ins
.opcode
[0], stdout
);
7391 (void) putchar ('\n');
7393 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7395 if (the_ins
.operands
[n
].error
)
7397 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7400 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7401 the_ins
.operands
[n
].reg
);
7402 if (the_ins
.operands
[n
].b_const
)
7403 printf ("Constant: '%.*s', ",
7404 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7405 the_ins
.operands
[n
].b_const
);
7406 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7407 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7408 if (the_ins
.operands
[n
].b_iadd
)
7409 printf ("Iadd: '%.*s',",
7410 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7411 the_ins
.operands
[n
].b_iadd
);
7420 is_label (char *str
)
7424 while (*str
&& *str
!= ' ')
7426 if (str
[-1] == ':' || str
[1] == '=')
7433 /* Possible states for relaxation:
7435 0 0 branch offset byte (bra, etc)
7439 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7443 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7450 /* We have no need to default values of symbols. */
7453 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7458 /* Round up a section size to the appropriate boundary. */
7460 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7463 /* For a.out, force the section size to be aligned. If we don't do
7464 this, BFD will align it for us, but it will not write out the
7465 final bytes of the section. This may be a bug in BFD, but it is
7466 easier to fix it here since that is how the other a.out targets
7470 align
= bfd_get_section_alignment (stdoutput
, segment
);
7471 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7477 /* Exactly what point is a PC-relative offset relative TO?
7478 On the 68k, it is relative to the address of the first extension
7479 word. The difference between the addresses of the offset and the
7480 first extension word is stored in fx_pcrel_adjust. */
7482 md_pcrel_from (fixS
*fixP
)
7486 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7487 sign extend the value here. */
7488 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7491 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7496 m68k_elf_final_processing (void)
7500 if (arch_coldfire_fpu (current_architecture
))
7501 flags
|= EF_M68K_CFV4E
;
7502 /* Set file-specific flags if this is a cpu32 processor. */
7503 if (cpu_of_arch (current_architecture
) & cpu32
)
7505 flags
|= EF_M68K_CPU32
;
7506 if (cpu_of_arch (current_architecture
) & fido_a
)
7507 flags
|= EF_M68K_CPU32_FIDO_A
;
7509 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7510 && !(cpu_of_arch (current_architecture
) & m68020up
))
7511 flags
|= EF_M68K_M68000
;
7513 if (current_architecture
& mcfisa_a
)
7515 static const unsigned isa_features
[][2] =
7517 {EF_M68K_CF_ISA_A_NODIV
, mcfisa_a
},
7518 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7519 {EF_M68K_CF_ISA_A_PLUS
,mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7520 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7521 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7524 static const unsigned mac_features
[][2] =
7526 {EF_M68K_CF_MAC
, mcfmac
},
7527 {EF_M68K_CF_EMAC
, mcfemac
},
7533 pattern
= (current_architecture
7534 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfhwdiv
|mcfusp
));
7535 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7537 if (pattern
== isa_features
[ix
][1])
7539 flags
|= isa_features
[ix
][0];
7543 if (!isa_features
[ix
][1])
7546 as_warn (_("Not a defined coldfire architecture"));
7550 if (current_architecture
& cfloat
)
7551 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7553 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7556 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7558 if (pattern
== mac_features
[ix
][1])
7560 flags
|= mac_features
[ix
][0];
7564 if (!mac_features
[ix
][1])
7569 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7574 tc_m68k_regname_to_dw2regnum (char *regname
)
7576 unsigned int regnum
;
7577 static const char *const regnames
[] =
7579 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7580 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7581 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7585 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7586 if (strcmp (regname
, regnames
[regnum
]) == 0)
7593 tc_m68k_frame_initial_instructions (void)
7595 static int sp_regno
= -1;
7598 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7600 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7601 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);