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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
181 0
182 };
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
189 0
190 };
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
193 0
194 };
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52235_ctrl[] = {
204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5225_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5235_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5249_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
217 0
218 };
219 static const enum m68k_register mcf5250_ctrl[] = {
220 VBR,
221 0
222 };
223 static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
225 0
226 };
227 static const enum m68k_register mcf5271_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
229 0
230 };
231 static const enum m68k_register mcf5272_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
233 0
234 };
235 static const enum m68k_register mcf5275_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
237 0
238 };
239 static const enum m68k_register mcf5282_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
245 0
246 };
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
249 0
250 };
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
269 0
270 };
271 static const enum m68k_register mcf54455_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279 };
280 static const enum m68k_register mcf5475_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
287 0
288 };
289 static const enum m68k_register mcf5485_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
295 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
296 0
297 };
298 static const enum m68k_register fido_ctrl[] = {
299 SFC, DFC, USP, VBR, CAC, MBB,
300 0
301 };
302 #define cpu32_ctrl m68010_ctrl
303
304 static const enum m68k_register *control_regs;
305
306 /* Internal form of a 68020 instruction. */
307 struct m68k_it
308 {
309 const char *error;
310 const char *args; /* List of opcode info. */
311 int numargs;
312
313 int numo; /* Number of shorts in opcode. */
314 short opcode[11];
315
316 struct m68k_op operands[6];
317
318 int nexp; /* Number of exprs in use. */
319 struct m68k_exp exprs[4];
320
321 int nfrag; /* Number of frags we have to produce. */
322 struct
323 {
324 int fragoff; /* Where in the current opcode the frag ends. */
325 symbolS *fadd;
326 offsetT foff;
327 int fragty;
328 }
329 fragb[4];
330
331 int nrel; /* Num of reloc strucs in use. */
332 struct
333 {
334 int n;
335 expressionS exp;
336 char wid;
337 char pcrel;
338 /* In a pc relative address the difference between the address
339 of the offset and the address that the offset is relative
340 to. This depends on the addressing mode. Basically this
341 is the value to put in the offset field to address the
342 first byte of the offset, without regarding the special
343 significance of some values (in the branch instruction, for
344 example). */
345 int pcrel_fix;
346 #ifdef OBJ_ELF
347 /* Whether this expression needs special pic relocation, and if
348 so, which. */
349 enum pic_relocation pic_reloc;
350 #endif
351 }
352 reloc[5]; /* Five is enough??? */
353 };
354
355 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
356 #define float_of_arch(x) ((x) & mfloat)
357 #define mmu_of_arch(x) ((x) & mmmu)
358 #define arch_coldfire_p(x) ((x) & mcfisa_a)
359 #define arch_coldfire_fpu(x) ((x) & cfloat)
360
361 /* Macros for determining if cpu supports a specific addressing mode. */
362 #define HAVE_LONG_DISP(x) \
363 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
364 #define HAVE_LONG_CALL(x) \
365 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
366 #define HAVE_LONG_COND(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368 #define HAVE_LONG_BRANCH(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
370
371 static struct m68k_it the_ins; /* The instruction being assembled. */
372
373 #define op(ex) ((ex)->exp.X_op)
374 #define adds(ex) ((ex)->exp.X_add_symbol)
375 #define subs(ex) ((ex)->exp.X_op_symbol)
376 #define offs(ex) ((ex)->exp.X_add_number)
377
378 /* Macros for adding things to the m68k_it struct. */
379 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
380
381 /* Like addword, but goes BEFORE general operands. */
382
383 static void
384 insop (int w, const struct m68k_incant *opcode)
385 {
386 int z;
387 for (z = the_ins.numo; z > opcode->m_codenum; --z)
388 the_ins.opcode[z] = the_ins.opcode[z - 1];
389 for (z = 0; z < the_ins.nrel; z++)
390 the_ins.reloc[z].n += 2;
391 for (z = 0; z < the_ins.nfrag; z++)
392 the_ins.fragb[z].fragoff++;
393 the_ins.opcode[opcode->m_codenum] = w;
394 the_ins.numo++;
395 }
396
397 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
398 Blecch. */
399 static void
400 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
401 {
402 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
403 ? the_ins.numo * 2 - 1
404 : (width == 'b'
405 ? the_ins.numo * 2 + 1
406 : the_ins.numo * 2));
407 the_ins.reloc[the_ins.nrel].exp = exp->exp;
408 the_ins.reloc[the_ins.nrel].wid = width;
409 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
410 #ifdef OBJ_ELF
411 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
412 #endif
413 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
414 }
415
416 /* Cause an extra frag to be generated here, inserting up to 10 bytes
417 (that value is chosen in the frag_var call in md_assemble). TYPE
418 is the subtype of the frag to be generated; its primary type is
419 rs_machine_dependent.
420
421 The TYPE parameter is also used by md_convert_frag_1 and
422 md_estimate_size_before_relax. The appropriate type of fixup will
423 be emitted by md_convert_frag_1.
424
425 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
426 static void
427 add_frag (symbolS *add, offsetT off, int type)
428 {
429 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
430 the_ins.fragb[the_ins.nfrag].fadd = add;
431 the_ins.fragb[the_ins.nfrag].foff = off;
432 the_ins.fragb[the_ins.nfrag++].fragty = type;
433 }
434
435 #define isvar(ex) \
436 (op (ex) != O_constant && op (ex) != O_big)
437
438 static char *crack_operand (char *str, struct m68k_op *opP);
439 static int get_num (struct m68k_exp *exp, int ok);
440 static int reverse_16_bits (int in);
441 static int reverse_8_bits (int in);
442 static void install_gen_operand (int mode, int val);
443 static void install_operand (int mode, int val);
444 static void s_bss (int);
445 static void s_data1 (int);
446 static void s_data2 (int);
447 static void s_even (int);
448 static void s_proc (int);
449 static void s_chip (int);
450 static void s_fopt (int);
451 static void s_opt (int);
452 static void s_reg (int);
453 static void s_restore (int);
454 static void s_save (int);
455 static void s_mri_if (int);
456 static void s_mri_else (int);
457 static void s_mri_endi (int);
458 static void s_mri_break (int);
459 static void s_mri_next (int);
460 static void s_mri_for (int);
461 static void s_mri_endf (int);
462 static void s_mri_repeat (int);
463 static void s_mri_until (int);
464 static void s_mri_while (int);
465 static void s_mri_endw (int);
466 static void s_m68k_cpu (int);
467 static void s_m68k_arch (int);
468
469 struct m68k_cpu
470 {
471 unsigned long arch; /* Architecture features. */
472 const enum m68k_register *control_regs; /* Control regs on chip */
473 const char *name; /* Name */
474 int alias; /* Alias for a cannonical name. If 1, then
475 succeeds canonical name, if -1 then
476 succeeds canonical name, if <-1 ||>1 this is a
477 deprecated name, and the next/previous name
478 should be used. */
479 };
480
481 /* We hold flags for features explicitly enabled and explicitly
482 disabled. */
483 static int current_architecture;
484 static int not_current_architecture;
485 static const struct m68k_cpu *selected_arch;
486 static const struct m68k_cpu *selected_cpu;
487 static int initialized;
488
489 /* Architecture models. */
490 static const struct m68k_cpu m68k_archs[] =
491 {
492 {m68000, m68000_ctrl, "68000", 0},
493 {m68010, m68010_ctrl, "68010", 0},
494 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
495 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
496 {m68040, m68040_ctrl, "68040", 0},
497 {m68060, m68060_ctrl, "68060", 0},
498 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
499 {fido_a, fido_ctrl, "fidoa", 0},
500 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
501 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
502 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
503 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
504 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
506 {0,0,NULL, 0}
507 };
508
509 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
510 for either. */
511 static const struct m68k_cpu m68k_extensions[] =
512 {
513 {m68851, NULL, "68851", -1},
514 {m68881, NULL, "68881", -1},
515 {m68881, NULL, "68882", -1},
516
517 {cfloat|m68881, NULL, "float", 0},
518
519 {mcfhwdiv, NULL, "div", 1},
520 {mcfusp, NULL, "usp", 1},
521 {mcfmac, NULL, "mac", 1},
522 {mcfemac, NULL, "emac", 1},
523
524 {0,NULL,NULL, 0}
525 };
526
527 /* Processor list */
528 static const struct m68k_cpu m68k_cpus[] =
529 {
530 {m68000, m68000_ctrl, "68000", 0},
531 {m68000, m68000_ctrl, "68ec000", 1},
532 {m68000, m68000_ctrl, "68hc000", 1},
533 {m68000, m68000_ctrl, "68hc001", 1},
534 {m68000, m68000_ctrl, "68008", 1},
535 {m68000, m68000_ctrl, "68302", 1},
536 {m68000, m68000_ctrl, "68306", 1},
537 {m68000, m68000_ctrl, "68307", 1},
538 {m68000, m68000_ctrl, "68322", 1},
539 {m68000, m68000_ctrl, "68356", 1},
540 {m68010, m68010_ctrl, "68010", 0},
541 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
542 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
543 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
544 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
545 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
546 {m68040, m68040_ctrl, "68040", 0},
547 {m68040, m68040_ctrl, "68ec040", 1},
548 {m68060, m68060_ctrl, "68060", 0},
549 {m68060, m68060_ctrl, "68ec060", 1},
550
551 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
552 {cpu32|m68881, cpu32_ctrl, "68330", 1},
553 {cpu32|m68881, cpu32_ctrl, "68331", 1},
554 {cpu32|m68881, cpu32_ctrl, "68332", 1},
555 {cpu32|m68881, cpu32_ctrl, "68333", 1},
556 {cpu32|m68881, cpu32_ctrl, "68334", 1},
557 {cpu32|m68881, cpu32_ctrl, "68336", 1},
558 {cpu32|m68881, cpu32_ctrl, "68340", 1},
559 {cpu32|m68881, cpu32_ctrl, "68341", 1},
560 {cpu32|m68881, cpu32_ctrl, "68349", 1},
561 {cpu32|m68881, cpu32_ctrl, "68360", 1},
562
563 {mcfisa_a, mcf_ctrl, "5200", 0},
564 {mcfisa_a, mcf_ctrl, "5202", 1},
565 {mcfisa_a, mcf_ctrl, "5204", 1},
566 {mcfisa_a, mcf5206_ctrl, "5206", 1},
567
568 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
569
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
572
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
579
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
583
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
586
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
594
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
600
601 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
602 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
603 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
604
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
607
608 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
612
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
617
618 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
628
629 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
630
631 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
632 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
633 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
634 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
635 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
636 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
637
638 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
639 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
640 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
641 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
642 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
643 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
645
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
651 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
653
654 {fido_a, fido_ctrl, "fidoa", 0},
655 {fido_a, fido_ctrl, "fido", 1},
656
657 {0,NULL,NULL, 0}
658 };
659
660 static const struct m68k_cpu *m68k_lookup_cpu
661 (const char *, const struct m68k_cpu *, int, int *);
662 static int m68k_set_arch (const char *, int, int);
663 static int m68k_set_cpu (const char *, int, int);
664 static int m68k_set_extension (const char *, int, int);
665 static void m68k_init_arch (void);
666
667 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
668 architecture and we have a lot of relaxation modes. */
669
670 /* Macros used in the relaxation code. */
671 #define TAB(x,y) (((x) << 2) + (y))
672 #define TABTYPE(x) ((x) >> 2)
673
674 /* Relaxation states. */
675 #define BYTE 0
676 #define SHORT 1
677 #define LONG 2
678 #define SZ_UNDEF 3
679
680 /* Here are all the relaxation modes we support. First we can relax ordinary
681 branches. On 68020 and higher and on CPU32 all branch instructions take
682 three forms, so on these CPUs all branches always remain as such. When we
683 have to expand to the LONG form on a 68000, though, we substitute an
684 absolute jump instead. This is a direct replacement for unconditional
685 branches and a branch over a jump for conditional branches. However, if the
686 user requires PIC and disables this with --pcrel, we can only relax between
687 BYTE and SHORT forms, punting if that isn't enough. This gives us four
688 different relaxation modes for branches: */
689
690 #define BRANCHBWL 0 /* Branch byte, word, or long. */
691 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
692 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
693 #define BRANCHBW 3 /* Branch byte or word. */
694
695 /* We also relax coprocessor branches and DBcc's. All CPUs that support
696 coprocessor branches support them in word and long forms, so we have only
697 one relaxation mode for them. DBcc's are word only on all CPUs. We can
698 relax them to the LONG form with a branch-around sequence. This sequence
699 can use a long branch (if available) or an absolute jump (if acceptable).
700 This gives us two relaxation modes. If long branches are not available and
701 absolute jumps are not acceptable, we don't relax DBcc's. */
702
703 #define FBRANCH 4 /* Coprocessor branch. */
704 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
705 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
706
707 /* That's all for instruction relaxation. However, we also relax PC-relative
708 operands. Specifically, we have three operand relaxation modes. On the
709 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
710 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
711 two. Also PC+displacement+index operands in their simple form (with a non-
712 suppressed index without memory indirection) are supported on all CPUs, but
713 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
714 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
715 form of the PC+displacement+index operand. Finally, some absolute operands
716 can be relaxed down to 16-bit PC-relative. */
717
718 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
719 #define PCINDEX 8 /* PC + displacement + index. */
720 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
721
722 /* Note that calls to frag_var need to specify the maximum expansion
723 needed; this is currently 10 bytes for DBCC. */
724
725 /* The fields are:
726 How far Forward this mode will reach:
727 How far Backward this mode will reach:
728 How many bytes this mode will add to the size of the frag
729 Which mode to go to if the offset won't fit in this one
730
731 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
732 relax_typeS md_relax_table[] =
733 {
734 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
735 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
736 { 0, 0, 4, 0 },
737 { 1, 1, 0, 0 },
738
739 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
740 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
741 { 0, 0, 4, 0 },
742 { 1, 1, 0, 0 },
743
744 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
745 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
746 { 0, 0, 6, 0 },
747 { 1, 1, 0, 0 },
748
749 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
750 { 0, 0, 2, 0 },
751 { 1, 1, 0, 0 },
752 { 1, 1, 0, 0 },
753
754 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
755 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
759 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
760 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
761 { 0, 0, 10, 0 },
762 { 1, 1, 0, 0 },
763
764 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
765 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
766 { 0, 0, 10, 0 },
767 { 1, 1, 0, 0 },
768
769 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
771 { 0, 0, 6, 0 },
772 { 1, 1, 0, 0 },
773
774 { 125, -130, 0, TAB (PCINDEX, SHORT) },
775 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
776 { 0, 0, 4, 0 },
777 { 1, 1, 0, 0 },
778
779 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
781 { 0, 0, 4, 0 },
782 { 1, 1, 0, 0 },
783 };
784
785 /* These are the machine dependent pseudo-ops. These are included so
786 the assembler can work on the output from the SUN C compiler, which
787 generates these. */
788
789 /* This table describes all the machine specific pseudo-ops the assembler
790 has to support. The fields are:
791 pseudo-op name without dot
792 function to call to execute this pseudo-op
793 Integer arg to pass to the function. */
794 const pseudo_typeS md_pseudo_table[] =
795 {
796 {"data1", s_data1, 0},
797 {"data2", s_data2, 0},
798 {"bss", s_bss, 0},
799 {"even", s_even, 0},
800 {"skip", s_space, 0},
801 {"proc", s_proc, 0},
802 #if defined (TE_SUN3) || defined (OBJ_ELF)
803 {"align", s_align_bytes, 0},
804 #endif
805 #ifdef OBJ_ELF
806 {"swbeg", s_ignore, 0},
807 #endif
808 {"extend", float_cons, 'x'},
809 {"ldouble", float_cons, 'x'},
810
811 {"arch", s_m68k_arch, 0},
812 {"cpu", s_m68k_cpu, 0},
813
814 /* The following pseudo-ops are supported for MRI compatibility. */
815 {"chip", s_chip, 0},
816 {"comline", s_space, 1},
817 {"fopt", s_fopt, 0},
818 {"mask2", s_ignore, 0},
819 {"opt", s_opt, 0},
820 {"reg", s_reg, 0},
821 {"restore", s_restore, 0},
822 {"save", s_save, 0},
823
824 {"if", s_mri_if, 0},
825 {"if.b", s_mri_if, 'b'},
826 {"if.w", s_mri_if, 'w'},
827 {"if.l", s_mri_if, 'l'},
828 {"else", s_mri_else, 0},
829 {"else.s", s_mri_else, 's'},
830 {"else.l", s_mri_else, 'l'},
831 {"endi", s_mri_endi, 0},
832 {"break", s_mri_break, 0},
833 {"break.s", s_mri_break, 's'},
834 {"break.l", s_mri_break, 'l'},
835 {"next", s_mri_next, 0},
836 {"next.s", s_mri_next, 's'},
837 {"next.l", s_mri_next, 'l'},
838 {"for", s_mri_for, 0},
839 {"for.b", s_mri_for, 'b'},
840 {"for.w", s_mri_for, 'w'},
841 {"for.l", s_mri_for, 'l'},
842 {"endf", s_mri_endf, 0},
843 {"repeat", s_mri_repeat, 0},
844 {"until", s_mri_until, 0},
845 {"until.b", s_mri_until, 'b'},
846 {"until.w", s_mri_until, 'w'},
847 {"until.l", s_mri_until, 'l'},
848 {"while", s_mri_while, 0},
849 {"while.b", s_mri_while, 'b'},
850 {"while.w", s_mri_while, 'w'},
851 {"while.l", s_mri_while, 'l'},
852 {"endw", s_mri_endw, 0},
853
854 {0, 0, 0}
855 };
856
857 /* The mote pseudo ops are put into the opcode table, since they
858 don't start with a . they look like opcodes to gas. */
859
860 const pseudo_typeS mote_pseudo_table[] =
861 {
862
863 {"dcl", cons, 4},
864 {"dc", cons, 2},
865 {"dcw", cons, 2},
866 {"dcb", cons, 1},
867
868 {"dsl", s_space, 4},
869 {"ds", s_space, 2},
870 {"dsw", s_space, 2},
871 {"dsb", s_space, 1},
872
873 {"xdef", s_globl, 0},
874 #ifdef OBJ_ELF
875 {"align", s_align_bytes, 0},
876 #else
877 {"align", s_align_ptwo, 0},
878 #endif
879 #ifdef M68KCOFF
880 {"sect", obj_coff_section, 0},
881 {"section", obj_coff_section, 0},
882 #endif
883 {0, 0, 0}
884 };
885
886 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
887 gives identical results to a 32-bit host. */
888 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
889 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
890
891 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
892 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
893 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
894 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
895
896 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
897 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
898 #define islong(x) (1)
899
900 static char notend_table[256];
901 static char alt_notend_table[256];
902 #define notend(s) \
903 (! (notend_table[(unsigned char) *s] \
904 || (*s == ':' \
905 && alt_notend_table[(unsigned char) s[1]])))
906
907 #ifdef OBJ_ELF
908
909 /* Return zero if the reference to SYMBOL from within the same segment may
910 be relaxed. */
911
912 /* On an ELF system, we can't relax an externally visible symbol,
913 because it may be overridden by a shared library. However, if
914 TARGET_OS is "elf", then we presume that we are assembling for an
915 embedded system, in which case we don't have to worry about shared
916 libraries, and we can relax any external sym. */
917
918 #define relaxable_symbol(symbol) \
919 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
920 || S_IS_WEAK (symbol)))
921
922 /* Compute the relocation code for a fixup of SIZE bytes, using pc
923 relative relocation if PCREL is non-zero. PIC says whether a special
924 pic relocation was requested. */
925
926 static bfd_reloc_code_real_type
927 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
928 {
929 switch (pic)
930 {
931 case pic_got_pcrel:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_GOT_PCREL;
936 case 2:
937 return BFD_RELOC_16_GOT_PCREL;
938 case 4:
939 return BFD_RELOC_32_GOT_PCREL;
940 }
941 break;
942
943 case pic_got_off:
944 switch (size)
945 {
946 case 1:
947 return BFD_RELOC_8_GOTOFF;
948 case 2:
949 return BFD_RELOC_16_GOTOFF;
950 case 4:
951 return BFD_RELOC_32_GOTOFF;
952 }
953 break;
954
955 case pic_plt_pcrel:
956 switch (size)
957 {
958 case 1:
959 return BFD_RELOC_8_PLT_PCREL;
960 case 2:
961 return BFD_RELOC_16_PLT_PCREL;
962 case 4:
963 return BFD_RELOC_32_PLT_PCREL;
964 }
965 break;
966
967 case pic_plt_off:
968 switch (size)
969 {
970 case 1:
971 return BFD_RELOC_8_PLTOFF;
972 case 2:
973 return BFD_RELOC_16_PLTOFF;
974 case 4:
975 return BFD_RELOC_32_PLTOFF;
976 }
977 break;
978
979 case pic_none:
980 if (pcrel)
981 {
982 switch (size)
983 {
984 case 1:
985 return BFD_RELOC_8_PCREL;
986 case 2:
987 return BFD_RELOC_16_PCREL;
988 case 4:
989 return BFD_RELOC_32_PCREL;
990 }
991 }
992 else
993 {
994 switch (size)
995 {
996 case 1:
997 return BFD_RELOC_8;
998 case 2:
999 return BFD_RELOC_16;
1000 case 4:
1001 return BFD_RELOC_32;
1002 }
1003 }
1004 }
1005
1006 if (pcrel)
1007 {
1008 if (pic == pic_none)
1009 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1010 else
1011 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1012 }
1013 else
1014 {
1015 if (pic == pic_none)
1016 as_bad (_("Can not do %d byte relocation"), size);
1017 else
1018 as_bad (_("Can not do %d byte pic relocation"), size);
1019 }
1020
1021 return BFD_RELOC_NONE;
1022 }
1023
1024 /* Here we decide which fixups can be adjusted to make them relative
1025 to the beginning of the section instead of the symbol. Basically
1026 we need to make sure that the dynamic relocations are done
1027 correctly, so in some cases we force the original symbol to be
1028 used. */
1029 int
1030 tc_m68k_fix_adjustable (fixS *fixP)
1031 {
1032 /* Adjust_reloc_syms doesn't know about the GOT. */
1033 switch (fixP->fx_r_type)
1034 {
1035 case BFD_RELOC_8_GOT_PCREL:
1036 case BFD_RELOC_16_GOT_PCREL:
1037 case BFD_RELOC_32_GOT_PCREL:
1038 case BFD_RELOC_8_GOTOFF:
1039 case BFD_RELOC_16_GOTOFF:
1040 case BFD_RELOC_32_GOTOFF:
1041 case BFD_RELOC_8_PLT_PCREL:
1042 case BFD_RELOC_16_PLT_PCREL:
1043 case BFD_RELOC_32_PLT_PCREL:
1044 case BFD_RELOC_8_PLTOFF:
1045 case BFD_RELOC_16_PLTOFF:
1046 case BFD_RELOC_32_PLTOFF:
1047 return 0;
1048
1049 case BFD_RELOC_VTABLE_INHERIT:
1050 case BFD_RELOC_VTABLE_ENTRY:
1051 return 0;
1052
1053 default:
1054 return 1;
1055 }
1056 }
1057
1058 #else /* !OBJ_ELF */
1059
1060 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1061
1062 #define relaxable_symbol(symbol) 1
1063
1064 #endif /* OBJ_ELF */
1065
1066 arelent *
1067 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1068 {
1069 arelent *reloc;
1070 bfd_reloc_code_real_type code;
1071
1072 /* If the tcbit is set, then this was a fixup of a negative value
1073 that was never resolved. We do not have a reloc to handle this,
1074 so just return. We assume that other code will have detected this
1075 situation and produced a helpful error message, so we just tell the
1076 user that the reloc cannot be produced. */
1077 if (fixp->fx_tcbit)
1078 {
1079 if (fixp->fx_addsy)
1080 as_bad_where (fixp->fx_file, fixp->fx_line,
1081 _("Unable to produce reloc against symbol '%s'"),
1082 S_GET_NAME (fixp->fx_addsy));
1083 return NULL;
1084 }
1085
1086 if (fixp->fx_r_type != BFD_RELOC_NONE)
1087 {
1088 code = fixp->fx_r_type;
1089
1090 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1091 that fixup_segment converted a non-PC relative reloc into a
1092 PC relative reloc. In such a case, we need to convert the
1093 reloc code. */
1094 if (fixp->fx_pcrel)
1095 {
1096 switch (code)
1097 {
1098 case BFD_RELOC_8:
1099 code = BFD_RELOC_8_PCREL;
1100 break;
1101 case BFD_RELOC_16:
1102 code = BFD_RELOC_16_PCREL;
1103 break;
1104 case BFD_RELOC_32:
1105 code = BFD_RELOC_32_PCREL;
1106 break;
1107 case BFD_RELOC_8_PCREL:
1108 case BFD_RELOC_16_PCREL:
1109 case BFD_RELOC_32_PCREL:
1110 case BFD_RELOC_8_GOT_PCREL:
1111 case BFD_RELOC_16_GOT_PCREL:
1112 case BFD_RELOC_32_GOT_PCREL:
1113 case BFD_RELOC_8_GOTOFF:
1114 case BFD_RELOC_16_GOTOFF:
1115 case BFD_RELOC_32_GOTOFF:
1116 case BFD_RELOC_8_PLT_PCREL:
1117 case BFD_RELOC_16_PLT_PCREL:
1118 case BFD_RELOC_32_PLT_PCREL:
1119 case BFD_RELOC_8_PLTOFF:
1120 case BFD_RELOC_16_PLTOFF:
1121 case BFD_RELOC_32_PLTOFF:
1122 break;
1123 default:
1124 as_bad_where (fixp->fx_file, fixp->fx_line,
1125 _("Cannot make %s relocation PC relative"),
1126 bfd_get_reloc_code_name (code));
1127 }
1128 }
1129 }
1130 else
1131 {
1132 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1133 switch (F (fixp->fx_size, fixp->fx_pcrel))
1134 {
1135 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1136 MAP (1, 0, BFD_RELOC_8);
1137 MAP (2, 0, BFD_RELOC_16);
1138 MAP (4, 0, BFD_RELOC_32);
1139 MAP (1, 1, BFD_RELOC_8_PCREL);
1140 MAP (2, 1, BFD_RELOC_16_PCREL);
1141 MAP (4, 1, BFD_RELOC_32_PCREL);
1142 default:
1143 abort ();
1144 }
1145 }
1146 #undef F
1147 #undef MAP
1148
1149 reloc = (arelent *) xmalloc (sizeof (arelent));
1150 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1151 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1152 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1153 #ifndef OBJ_ELF
1154 if (fixp->fx_pcrel)
1155 reloc->addend = fixp->fx_addnumber;
1156 else
1157 reloc->addend = 0;
1158 #else
1159 if (!fixp->fx_pcrel)
1160 reloc->addend = fixp->fx_addnumber;
1161 else
1162 reloc->addend = (section->vma
1163 /* Explicit sign extension in case char is
1164 unsigned. */
1165 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1166 + fixp->fx_addnumber
1167 + md_pcrel_from (fixp));
1168 #endif
1169
1170 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1171 assert (reloc->howto != 0);
1172
1173 return reloc;
1174 }
1175
1176 /* Handle of the OPCODE hash table. NULL means any use before
1177 m68k_ip_begin() will crash. */
1178 static struct hash_control *op_hash;
1179 \f
1180 /* Assemble an m68k instruction. */
1181
1182 static void
1183 m68k_ip (char *instring)
1184 {
1185 register char *p;
1186 register struct m68k_op *opP;
1187 register const struct m68k_incant *opcode;
1188 register const char *s;
1189 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1190 char *pdot, *pdotmove;
1191 enum m68k_size siz1, siz2;
1192 char c;
1193 int losing;
1194 int opsfound;
1195 struct m68k_op operands_backup[6];
1196 LITTLENUM_TYPE words[6];
1197 LITTLENUM_TYPE *wordp;
1198 unsigned long ok_arch = 0;
1199
1200 if (*instring == ' ')
1201 instring++; /* Skip leading whitespace. */
1202
1203 /* Scan up to end of operation-code, which MUST end in end-of-string
1204 or exactly 1 space. */
1205 pdot = 0;
1206 for (p = instring; *p != '\0'; p++)
1207 {
1208 if (*p == ' ')
1209 break;
1210 if (*p == '.')
1211 pdot = p;
1212 }
1213
1214 if (p == instring)
1215 {
1216 the_ins.error = _("No operator");
1217 return;
1218 }
1219
1220 /* p now points to the end of the opcode name, probably whitespace.
1221 Make sure the name is null terminated by clobbering the
1222 whitespace, look it up in the hash table, then fix it back.
1223 Remove a dot, first, since the opcode tables have none. */
1224 if (pdot != NULL)
1225 {
1226 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1227 *pdotmove = pdotmove[1];
1228 p--;
1229 }
1230
1231 c = *p;
1232 *p = '\0';
1233 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1234 *p = c;
1235
1236 if (pdot != NULL)
1237 {
1238 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1239 *pdotmove = pdotmove[-1];
1240 *pdot = '.';
1241 ++p;
1242 }
1243
1244 if (opcode == NULL)
1245 {
1246 the_ins.error = _("Unknown operator");
1247 return;
1248 }
1249
1250 /* Found a legitimate opcode, start matching operands. */
1251 while (*p == ' ')
1252 ++p;
1253
1254 if (opcode->m_operands == 0)
1255 {
1256 char *old = input_line_pointer;
1257 *old = '\n';
1258 input_line_pointer = p;
1259 /* Ahh - it's a motorola style psuedo op. */
1260 mote_pseudo_table[opcode->m_opnum].poc_handler
1261 (mote_pseudo_table[opcode->m_opnum].poc_val);
1262 input_line_pointer = old;
1263 *old = 0;
1264
1265 return;
1266 }
1267
1268 if (flag_mri && opcode->m_opnum == 0)
1269 {
1270 /* In MRI mode, random garbage is allowed after an instruction
1271 which accepts no operands. */
1272 the_ins.args = opcode->m_operands;
1273 the_ins.numargs = opcode->m_opnum;
1274 the_ins.numo = opcode->m_codenum;
1275 the_ins.opcode[0] = getone (opcode);
1276 the_ins.opcode[1] = gettwo (opcode);
1277 return;
1278 }
1279
1280 for (opP = &the_ins.operands[0]; *p; opP++)
1281 {
1282 p = crack_operand (p, opP);
1283
1284 if (opP->error)
1285 {
1286 the_ins.error = opP->error;
1287 return;
1288 }
1289 }
1290
1291 opsfound = opP - &the_ins.operands[0];
1292
1293 /* This ugly hack is to support the floating pt opcodes in their
1294 standard form. Essentially, we fake a first enty of type COP#1 */
1295 if (opcode->m_operands[0] == 'I')
1296 {
1297 int n;
1298
1299 for (n = opsfound; n > 0; --n)
1300 the_ins.operands[n] = the_ins.operands[n - 1];
1301
1302 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1303 the_ins.operands[0].mode = CONTROL;
1304 the_ins.operands[0].reg = m68k_float_copnum;
1305 opsfound++;
1306 }
1307
1308 /* We've got the operands. Find an opcode that'll accept them. */
1309 for (losing = 0;;)
1310 {
1311 /* If we didn't get the right number of ops, or we have no
1312 common model with this pattern then reject this pattern. */
1313
1314 ok_arch |= opcode->m_arch;
1315 if (opsfound != opcode->m_opnum
1316 || ((opcode->m_arch & current_architecture) == 0))
1317 ++losing;
1318 else
1319 {
1320 int i;
1321
1322 /* Make a copy of the operands of this insn so that
1323 we can modify them safely, should we want to. */
1324 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1325 for (i = 0; i < opsfound; i++)
1326 operands_backup[i] = the_ins.operands[i];
1327
1328 for (s = opcode->m_operands, opP = &operands_backup[0];
1329 *s && !losing;
1330 s += 2, opP++)
1331 {
1332 /* Warning: this switch is huge! */
1333 /* I've tried to organize the cases into this order:
1334 non-alpha first, then alpha by letter. Lower-case
1335 goes directly before uppercase counterpart. */
1336 /* Code with multiple case ...: gets sorted by the lowest
1337 case ... it belongs to. I hope this makes sense. */
1338 switch (*s)
1339 {
1340 case '!':
1341 switch (opP->mode)
1342 {
1343 case IMMED:
1344 case DREG:
1345 case AREG:
1346 case FPREG:
1347 case CONTROL:
1348 case AINC:
1349 case ADEC:
1350 case REGLST:
1351 losing++;
1352 break;
1353 default:
1354 break;
1355 }
1356 break;
1357
1358 case '<':
1359 switch (opP->mode)
1360 {
1361 case DREG:
1362 case AREG:
1363 case FPREG:
1364 case CONTROL:
1365 case IMMED:
1366 case ADEC:
1367 case REGLST:
1368 losing++;
1369 break;
1370 default:
1371 break;
1372 }
1373 break;
1374
1375 case '>':
1376 switch (opP->mode)
1377 {
1378 case DREG:
1379 case AREG:
1380 case FPREG:
1381 case CONTROL:
1382 case IMMED:
1383 case AINC:
1384 case REGLST:
1385 losing++;
1386 break;
1387 case ABSL:
1388 break;
1389 default:
1390 if (opP->reg == PC
1391 || opP->reg == ZPC)
1392 losing++;
1393 break;
1394 }
1395 break;
1396
1397 case 'm':
1398 switch (opP->mode)
1399 {
1400 case DREG:
1401 case AREG:
1402 case AINDR:
1403 case AINC:
1404 case ADEC:
1405 break;
1406 default:
1407 losing++;
1408 }
1409 break;
1410
1411 case 'n':
1412 switch (opP->mode)
1413 {
1414 case DISP:
1415 break;
1416 default:
1417 losing++;
1418 }
1419 break;
1420
1421 case 'o':
1422 switch (opP->mode)
1423 {
1424 case BASE:
1425 case ABSL:
1426 case IMMED:
1427 break;
1428 default:
1429 losing++;
1430 }
1431 break;
1432
1433 case 'p':
1434 switch (opP->mode)
1435 {
1436 case DREG:
1437 case AREG:
1438 case AINDR:
1439 case AINC:
1440 case ADEC:
1441 break;
1442 case DISP:
1443 if (opP->reg == PC || opP->reg == ZPC)
1444 losing++;
1445 break;
1446 default:
1447 losing++;
1448 }
1449 break;
1450
1451 case 'q':
1452 switch (opP->mode)
1453 {
1454 case DREG:
1455 case AINDR:
1456 case AINC:
1457 case ADEC:
1458 break;
1459 case DISP:
1460 if (opP->reg == PC || opP->reg == ZPC)
1461 losing++;
1462 break;
1463 default:
1464 losing++;
1465 break;
1466 }
1467 break;
1468
1469 case 'v':
1470 switch (opP->mode)
1471 {
1472 case DREG:
1473 case AINDR:
1474 case AINC:
1475 case ADEC:
1476 case ABSL:
1477 break;
1478 case DISP:
1479 if (opP->reg == PC || opP->reg == ZPC)
1480 losing++;
1481 break;
1482 default:
1483 losing++;
1484 break;
1485 }
1486 break;
1487
1488 case '#':
1489 if (opP->mode != IMMED)
1490 losing++;
1491 else if (s[1] == 'b'
1492 && ! isvar (&opP->disp)
1493 && (opP->disp.exp.X_op != O_constant
1494 || ! isbyte (opP->disp.exp.X_add_number)))
1495 losing++;
1496 else if (s[1] == 'B'
1497 && ! isvar (&opP->disp)
1498 && (opP->disp.exp.X_op != O_constant
1499 || ! issbyte (opP->disp.exp.X_add_number)))
1500 losing++;
1501 else if (s[1] == 'w'
1502 && ! isvar (&opP->disp)
1503 && (opP->disp.exp.X_op != O_constant
1504 || ! isword (opP->disp.exp.X_add_number)))
1505 losing++;
1506 else if (s[1] == 'W'
1507 && ! isvar (&opP->disp)
1508 && (opP->disp.exp.X_op != O_constant
1509 || ! issword (opP->disp.exp.X_add_number)))
1510 losing++;
1511 break;
1512
1513 case '^':
1514 case 'T':
1515 if (opP->mode != IMMED)
1516 losing++;
1517 break;
1518
1519 case '$':
1520 if (opP->mode == AREG
1521 || opP->mode == CONTROL
1522 || opP->mode == FPREG
1523 || opP->mode == IMMED
1524 || opP->mode == REGLST
1525 || (opP->mode != ABSL
1526 && (opP->reg == PC
1527 || opP->reg == ZPC)))
1528 losing++;
1529 break;
1530
1531 case '%':
1532 if (opP->mode == CONTROL
1533 || opP->mode == FPREG
1534 || opP->mode == REGLST
1535 || opP->mode == IMMED
1536 || (opP->mode != ABSL
1537 && (opP->reg == PC
1538 || opP->reg == ZPC)))
1539 losing++;
1540 break;
1541
1542 case '&':
1543 switch (opP->mode)
1544 {
1545 case DREG:
1546 case AREG:
1547 case FPREG:
1548 case CONTROL:
1549 case IMMED:
1550 case AINC:
1551 case ADEC:
1552 case REGLST:
1553 losing++;
1554 break;
1555 case ABSL:
1556 break;
1557 default:
1558 if (opP->reg == PC
1559 || opP->reg == ZPC)
1560 losing++;
1561 break;
1562 }
1563 break;
1564
1565 case '*':
1566 if (opP->mode == CONTROL
1567 || opP->mode == FPREG
1568 || opP->mode == REGLST)
1569 losing++;
1570 break;
1571
1572 case '+':
1573 if (opP->mode != AINC)
1574 losing++;
1575 break;
1576
1577 case '-':
1578 if (opP->mode != ADEC)
1579 losing++;
1580 break;
1581
1582 case '/':
1583 switch (opP->mode)
1584 {
1585 case AREG:
1586 case CONTROL:
1587 case FPREG:
1588 case AINC:
1589 case ADEC:
1590 case IMMED:
1591 case REGLST:
1592 losing++;
1593 break;
1594 default:
1595 break;
1596 }
1597 break;
1598
1599 case ';':
1600 switch (opP->mode)
1601 {
1602 case AREG:
1603 case CONTROL:
1604 case FPREG:
1605 case REGLST:
1606 losing++;
1607 break;
1608 default:
1609 break;
1610 }
1611 break;
1612
1613 case '?':
1614 switch (opP->mode)
1615 {
1616 case AREG:
1617 case CONTROL:
1618 case FPREG:
1619 case AINC:
1620 case ADEC:
1621 case IMMED:
1622 case REGLST:
1623 losing++;
1624 break;
1625 case ABSL:
1626 break;
1627 default:
1628 if (opP->reg == PC || opP->reg == ZPC)
1629 losing++;
1630 break;
1631 }
1632 break;
1633
1634 case '@':
1635 switch (opP->mode)
1636 {
1637 case AREG:
1638 case CONTROL:
1639 case FPREG:
1640 case IMMED:
1641 case REGLST:
1642 losing++;
1643 break;
1644 default:
1645 break;
1646 }
1647 break;
1648
1649 case '~': /* For now! (JF FOO is this right?) */
1650 switch (opP->mode)
1651 {
1652 case DREG:
1653 case AREG:
1654 case CONTROL:
1655 case FPREG:
1656 case IMMED:
1657 case REGLST:
1658 losing++;
1659 break;
1660 case ABSL:
1661 break;
1662 default:
1663 if (opP->reg == PC
1664 || opP->reg == ZPC)
1665 losing++;
1666 break;
1667 }
1668 break;
1669
1670 case '3':
1671 if (opP->mode != CONTROL
1672 || (opP->reg != TT0 && opP->reg != TT1))
1673 losing++;
1674 break;
1675
1676 case 'A':
1677 if (opP->mode != AREG)
1678 losing++;
1679 break;
1680
1681 case 'a':
1682 if (opP->mode != AINDR)
1683 ++losing;
1684 break;
1685
1686 case '4':
1687 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1688 && (opP->mode != DISP
1689 || opP->reg < ADDR0
1690 || opP->reg > ADDR7))
1691 ++losing;
1692 break;
1693
1694 case 'B': /* FOO */
1695 if (opP->mode != ABSL
1696 || (flag_long_jumps
1697 && strncmp (instring, "jbsr", 4) == 0))
1698 losing++;
1699 break;
1700
1701 case 'b':
1702 switch (opP->mode)
1703 {
1704 case IMMED:
1705 case ABSL:
1706 case AREG:
1707 case FPREG:
1708 case CONTROL:
1709 case POST:
1710 case PRE:
1711 case REGLST:
1712 losing++;
1713 break;
1714 default:
1715 break;
1716 }
1717 break;
1718
1719 case 'C':
1720 if (opP->mode != CONTROL || opP->reg != CCR)
1721 losing++;
1722 break;
1723
1724 case 'd':
1725 if (opP->mode != DISP
1726 || opP->reg < ADDR0
1727 || opP->reg > ADDR7)
1728 losing++;
1729 break;
1730
1731 case 'D':
1732 if (opP->mode != DREG)
1733 losing++;
1734 break;
1735
1736 case 'E':
1737 if (opP->reg != ACC)
1738 losing++;
1739 break;
1740
1741 case 'e':
1742 if (opP->reg != ACC && opP->reg != ACC1
1743 && opP->reg != ACC2 && opP->reg != ACC3)
1744 losing++;
1745 break;
1746
1747 case 'F':
1748 if (opP->mode != FPREG)
1749 losing++;
1750 break;
1751
1752 case 'G':
1753 if (opP->reg != MACSR)
1754 losing++;
1755 break;
1756
1757 case 'g':
1758 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1759 losing++;
1760 break;
1761
1762 case 'H':
1763 if (opP->reg != MASK)
1764 losing++;
1765 break;
1766
1767 case 'I':
1768 if (opP->mode != CONTROL
1769 || opP->reg < COP0
1770 || opP->reg > COP7)
1771 losing++;
1772 break;
1773
1774 case 'i':
1775 if (opP->mode != LSH && opP->mode != RSH)
1776 losing++;
1777 break;
1778
1779 case 'J':
1780 if (opP->mode != CONTROL
1781 || opP->reg < USP
1782 || opP->reg > last_movec_reg
1783 || !control_regs)
1784 losing++;
1785 else
1786 {
1787 const enum m68k_register *rp;
1788
1789 for (rp = control_regs; *rp; rp++)
1790 {
1791 if (*rp == opP->reg)
1792 break;
1793 /* In most CPUs RAMBAR refers to control reg
1794 c05 (RAMBAR1), but a few CPUs have it
1795 refer to c04 (RAMBAR0). */
1796 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1797 {
1798 opP->reg = RAMBAR_ALT;
1799 break;
1800 }
1801 }
1802 if (*rp == 0)
1803 losing++;
1804 }
1805 break;
1806
1807 case 'k':
1808 if (opP->mode != IMMED)
1809 losing++;
1810 break;
1811
1812 case 'l':
1813 case 'L':
1814 if (opP->mode == DREG
1815 || opP->mode == AREG
1816 || opP->mode == FPREG)
1817 {
1818 if (s[1] == '8')
1819 losing++;
1820 else
1821 {
1822 switch (opP->mode)
1823 {
1824 case DREG:
1825 opP->mask = 1 << (opP->reg - DATA0);
1826 break;
1827 case AREG:
1828 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1829 break;
1830 case FPREG:
1831 opP->mask = 1 << (opP->reg - FP0 + 16);
1832 break;
1833 default:
1834 abort ();
1835 }
1836 opP->mode = REGLST;
1837 }
1838 }
1839 else if (opP->mode == CONTROL)
1840 {
1841 if (s[1] != '8')
1842 losing++;
1843 else
1844 {
1845 switch (opP->reg)
1846 {
1847 case FPI:
1848 opP->mask = 1 << 24;
1849 break;
1850 case FPS:
1851 opP->mask = 1 << 25;
1852 break;
1853 case FPC:
1854 opP->mask = 1 << 26;
1855 break;
1856 default:
1857 losing++;
1858 break;
1859 }
1860 opP->mode = REGLST;
1861 }
1862 }
1863 else if (opP->mode != REGLST)
1864 losing++;
1865 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1866 losing++;
1867 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1868 losing++;
1869 break;
1870
1871 case 'M':
1872 if (opP->mode != IMMED)
1873 losing++;
1874 else if (opP->disp.exp.X_op != O_constant
1875 || ! issbyte (opP->disp.exp.X_add_number))
1876 losing++;
1877 else if (! m68k_quick
1878 && instring[3] != 'q'
1879 && instring[4] != 'q')
1880 losing++;
1881 break;
1882
1883 case 'O':
1884 if (opP->mode != DREG
1885 && opP->mode != IMMED
1886 && opP->mode != ABSL)
1887 losing++;
1888 break;
1889
1890 case 'Q':
1891 if (opP->mode != IMMED)
1892 losing++;
1893 else if (opP->disp.exp.X_op != O_constant
1894 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1895 losing++;
1896 else if (! m68k_quick
1897 && (strncmp (instring, "add", 3) == 0
1898 || strncmp (instring, "sub", 3) == 0)
1899 && instring[3] != 'q')
1900 losing++;
1901 break;
1902
1903 case 'R':
1904 if (opP->mode != DREG && opP->mode != AREG)
1905 losing++;
1906 break;
1907
1908 case 'r':
1909 if (opP->mode != AINDR
1910 && (opP->mode != BASE
1911 || (opP->reg != 0
1912 && opP->reg != ZADDR0)
1913 || opP->disp.exp.X_op != O_absent
1914 || ((opP->index.reg < DATA0
1915 || opP->index.reg > DATA7)
1916 && (opP->index.reg < ADDR0
1917 || opP->index.reg > ADDR7))
1918 || opP->index.size != SIZE_UNSPEC
1919 || opP->index.scale != 1))
1920 losing++;
1921 break;
1922
1923 case 's':
1924 if (opP->mode != CONTROL
1925 || ! (opP->reg == FPI
1926 || opP->reg == FPS
1927 || opP->reg == FPC))
1928 losing++;
1929 break;
1930
1931 case 'S':
1932 if (opP->mode != CONTROL || opP->reg != SR)
1933 losing++;
1934 break;
1935
1936 case 't':
1937 if (opP->mode != IMMED)
1938 losing++;
1939 else if (opP->disp.exp.X_op != O_constant
1940 || TRUNC (opP->disp.exp.X_add_number) > 7)
1941 losing++;
1942 break;
1943
1944 case 'U':
1945 if (opP->mode != CONTROL || opP->reg != USP)
1946 losing++;
1947 break;
1948
1949 case 'x':
1950 if (opP->mode != IMMED)
1951 losing++;
1952 else if (opP->disp.exp.X_op != O_constant
1953 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1954 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1955 losing++;
1956 break;
1957
1958 /* JF these are out of order. We could put them
1959 in order if we were willing to put up with
1960 bunches of #ifdef m68851s in the code.
1961
1962 Don't forget that you need these operands
1963 to use 68030 MMU instructions. */
1964 #ifndef NO_68851
1965 /* Memory addressing mode used by pflushr. */
1966 case '|':
1967 if (opP->mode == CONTROL
1968 || opP->mode == FPREG
1969 || opP->mode == DREG
1970 || opP->mode == AREG
1971 || opP->mode == REGLST)
1972 losing++;
1973 /* We should accept immediate operands, but they
1974 supposedly have to be quad word, and we don't
1975 handle that. I would like to see what a Motorola
1976 assembler does before doing something here. */
1977 if (opP->mode == IMMED)
1978 losing++;
1979 break;
1980
1981 case 'f':
1982 if (opP->mode != CONTROL
1983 || (opP->reg != SFC && opP->reg != DFC))
1984 losing++;
1985 break;
1986
1987 case '0':
1988 if (opP->mode != CONTROL || opP->reg != TC)
1989 losing++;
1990 break;
1991
1992 case '1':
1993 if (opP->mode != CONTROL || opP->reg != AC)
1994 losing++;
1995 break;
1996
1997 case '2':
1998 if (opP->mode != CONTROL
1999 || (opP->reg != CAL
2000 && opP->reg != VAL
2001 && opP->reg != SCC))
2002 losing++;
2003 break;
2004
2005 case 'V':
2006 if (opP->mode != CONTROL
2007 || opP->reg != VAL)
2008 losing++;
2009 break;
2010
2011 case 'W':
2012 if (opP->mode != CONTROL
2013 || (opP->reg != DRP
2014 && opP->reg != SRP
2015 && opP->reg != CRP))
2016 losing++;
2017 break;
2018
2019 case 'w':
2020 switch (opP->mode)
2021 {
2022 case IMMED:
2023 case ABSL:
2024 case AREG:
2025 case DREG:
2026 case FPREG:
2027 case CONTROL:
2028 case POST:
2029 case PRE:
2030 case REGLST:
2031 losing++;
2032 break;
2033 default:
2034 break;
2035 }
2036 break;
2037
2038 case 'X':
2039 if (opP->mode != CONTROL
2040 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2041 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2042 losing++;
2043 break;
2044
2045 case 'Y':
2046 if (opP->mode != CONTROL || opP->reg != PSR)
2047 losing++;
2048 break;
2049
2050 case 'Z':
2051 if (opP->mode != CONTROL || opP->reg != PCSR)
2052 losing++;
2053 break;
2054 #endif
2055 case 'c':
2056 if (opP->mode != CONTROL
2057 || (opP->reg != NC
2058 && opP->reg != IC
2059 && opP->reg != DC
2060 && opP->reg != BC))
2061 losing++;
2062 break;
2063
2064 case '_':
2065 if (opP->mode != ABSL)
2066 ++losing;
2067 break;
2068
2069 case 'u':
2070 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2071 losing++;
2072 /* FIXME: kludge instead of fixing parser:
2073 upper/lower registers are *not* CONTROL
2074 registers, but ordinary ones. */
2075 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2076 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2077 opP->mode = DREG;
2078 else
2079 opP->mode = AREG;
2080 break;
2081
2082 case 'y':
2083 if (!(opP->mode == AINDR
2084 || (opP->mode == DISP
2085 && !(opP->reg == PC || opP->reg == ZPC))))
2086 losing++;
2087 break;
2088
2089 case 'z':
2090 if (!(opP->mode == AINDR || opP->mode == DISP))
2091 losing++;
2092 break;
2093
2094 default:
2095 abort ();
2096 }
2097
2098 if (losing)
2099 break;
2100 }
2101
2102 /* Since we have found the correct instruction, copy
2103 in the modifications that we may have made. */
2104 if (!losing)
2105 for (i = 0; i < opsfound; i++)
2106 the_ins.operands[i] = operands_backup[i];
2107 }
2108
2109 if (!losing)
2110 break;
2111
2112 opcode = opcode->m_next;
2113
2114 if (!opcode)
2115 {
2116 if (ok_arch
2117 && !(ok_arch & current_architecture))
2118 {
2119 const struct m68k_cpu *cpu;
2120 int any = 0;
2121 size_t space = 400;
2122 char *buf = xmalloc (space + 1);
2123 size_t len;
2124 int paren = 1;
2125
2126 the_ins.error = buf;
2127 /* Make sure there's a NUL at the end of the buffer -- strncpy
2128 won't write one when it runs out of buffer */
2129 buf[space] = 0;
2130 #define APPEND(STRING) \
2131 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2132
2133 APPEND (_("invalid instruction for this architecture; needs "));
2134 switch (ok_arch)
2135 {
2136 case mcfisa_a:
2137 APPEND (_("ColdFire ISA_A"));
2138 break;
2139 case mcfhwdiv:
2140 APPEND (_("ColdFire hardware divide"));
2141 break;
2142 case mcfisa_aa:
2143 APPEND (_("ColdFire ISA_A+"));
2144 break;
2145 case mcfisa_b:
2146 APPEND (_("ColdFire ISA_B"));
2147 break;
2148 case cfloat:
2149 APPEND (_("ColdFire fpu"));
2150 break;
2151 case mfloat:
2152 APPEND (_("M68K fpu"));
2153 break;
2154 case mmmu:
2155 APPEND (_("M68K mmu"));
2156 break;
2157 case m68020up:
2158 APPEND (_("68020 or higher"));
2159 break;
2160 case m68000up:
2161 APPEND (_("68000 or higher"));
2162 break;
2163 case m68010up:
2164 APPEND (_("68010 or higher"));
2165 break;
2166 default:
2167 paren = 0;
2168 }
2169 if (paren)
2170 APPEND (" (");
2171
2172 for (cpu = m68k_cpus; cpu->name; cpu++)
2173 if (!cpu->alias && (cpu->arch & ok_arch))
2174 {
2175 const struct m68k_cpu *alias;
2176 int seen_master = 0;
2177
2178 if (any)
2179 APPEND (", ");
2180 any = 0;
2181 APPEND (cpu->name);
2182 for (alias = cpu; alias != m68k_cpus; alias--)
2183 if (alias[-1].alias >= 0)
2184 break;
2185 for (; !seen_master || alias->alias > 0; alias++)
2186 {
2187 if (!alias->alias)
2188 seen_master = 1;
2189 else
2190 {
2191 if (any)
2192 APPEND (", ");
2193 else
2194 APPEND (" [");
2195 APPEND (alias->name);
2196 any = 1;
2197 }
2198 }
2199 if (any)
2200 APPEND ("]");
2201 any = 1;
2202 }
2203 if (paren)
2204 APPEND (")");
2205 #undef APPEND
2206 if (!space)
2207 {
2208 /* we ran out of space, so replace the end of the list
2209 with ellipsis. */
2210 buf -= 4;
2211 while (*buf != ' ')
2212 buf--;
2213 strcpy (buf, " ...");
2214 }
2215 }
2216 else
2217 the_ins.error = _("operands mismatch");
2218 return;
2219 }
2220
2221 losing = 0;
2222 }
2223
2224 /* Now assemble it. */
2225 the_ins.args = opcode->m_operands;
2226 the_ins.numargs = opcode->m_opnum;
2227 the_ins.numo = opcode->m_codenum;
2228 the_ins.opcode[0] = getone (opcode);
2229 the_ins.opcode[1] = gettwo (opcode);
2230
2231 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2232 {
2233 int have_disp = 0;
2234
2235 /* This switch is a doozy.
2236 Watch the first step; its a big one! */
2237 switch (s[0])
2238 {
2239
2240 case '*':
2241 case '~':
2242 case '%':
2243 case ';':
2244 case '@':
2245 case '!':
2246 case '&':
2247 case '$':
2248 case '?':
2249 case '/':
2250 case '<':
2251 case '>':
2252 case 'b':
2253 case 'm':
2254 case 'n':
2255 case 'o':
2256 case 'p':
2257 case 'q':
2258 case 'v':
2259 case 'w':
2260 case 'y':
2261 case 'z':
2262 case '4':
2263 #ifndef NO_68851
2264 case '|':
2265 #endif
2266 switch (opP->mode)
2267 {
2268 case IMMED:
2269 tmpreg = 0x3c; /* 7.4 */
2270 if (strchr ("bwl", s[1]))
2271 nextword = get_num (&opP->disp, 90);
2272 else
2273 nextword = get_num (&opP->disp, 0);
2274 if (isvar (&opP->disp))
2275 add_fix (s[1], &opP->disp, 0, 0);
2276 switch (s[1])
2277 {
2278 case 'b':
2279 if (!isbyte (nextword))
2280 opP->error = _("operand out of range");
2281 addword (nextword);
2282 baseo = 0;
2283 break;
2284 case 'w':
2285 if (!isword (nextword))
2286 opP->error = _("operand out of range");
2287 addword (nextword);
2288 baseo = 0;
2289 break;
2290 case 'W':
2291 if (!issword (nextword))
2292 opP->error = _("operand out of range");
2293 addword (nextword);
2294 baseo = 0;
2295 break;
2296 case 'l':
2297 addword (nextword >> 16);
2298 addword (nextword);
2299 baseo = 0;
2300 break;
2301
2302 case 'f':
2303 baseo = 2;
2304 outro = 8;
2305 break;
2306 case 'F':
2307 baseo = 4;
2308 outro = 11;
2309 break;
2310 case 'x':
2311 baseo = 6;
2312 outro = 15;
2313 break;
2314 case 'p':
2315 baseo = 6;
2316 outro = -1;
2317 break;
2318 default:
2319 abort ();
2320 }
2321 if (!baseo)
2322 break;
2323
2324 /* We gotta put out some float. */
2325 if (op (&opP->disp) != O_big)
2326 {
2327 valueT val;
2328 int gencnt;
2329
2330 /* Can other cases happen here? */
2331 if (op (&opP->disp) != O_constant)
2332 abort ();
2333
2334 val = (valueT) offs (&opP->disp);
2335 gencnt = 0;
2336 do
2337 {
2338 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2339 val >>= LITTLENUM_NUMBER_OF_BITS;
2340 ++gencnt;
2341 }
2342 while (val != 0);
2343 offs (&opP->disp) = gencnt;
2344 }
2345 if (offs (&opP->disp) > 0)
2346 {
2347 if (offs (&opP->disp) > baseo)
2348 {
2349 as_warn (_("Bignum too big for %c format; truncated"),
2350 s[1]);
2351 offs (&opP->disp) = baseo;
2352 }
2353 baseo -= offs (&opP->disp);
2354 while (baseo--)
2355 addword (0);
2356 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2357 offs (&opP->disp)--;
2358 --wordp)
2359 addword (*wordp);
2360 break;
2361 }
2362 gen_to_words (words, baseo, (long) outro);
2363 for (wordp = words; baseo--; wordp++)
2364 addword (*wordp);
2365 break;
2366 case DREG:
2367 tmpreg = opP->reg - DATA; /* 0.dreg */
2368 break;
2369 case AREG:
2370 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2371 break;
2372 case AINDR:
2373 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2374 break;
2375 case ADEC:
2376 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2377 break;
2378 case AINC:
2379 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2380 break;
2381 case DISP:
2382
2383 nextword = get_num (&opP->disp, 90);
2384
2385 /* Convert mode 5 addressing with a zero offset into
2386 mode 2 addressing to reduce the instruction size by a
2387 word. */
2388 if (! isvar (&opP->disp)
2389 && (nextword == 0)
2390 && (opP->disp.size == SIZE_UNSPEC)
2391 && (opP->reg >= ADDR0)
2392 && (opP->reg <= ADDR7))
2393 {
2394 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2395 break;
2396 }
2397
2398 if (opP->reg == PC
2399 && ! isvar (&opP->disp)
2400 && m68k_abspcadd)
2401 {
2402 opP->disp.exp.X_op = O_symbol;
2403 opP->disp.exp.X_add_symbol =
2404 section_symbol (absolute_section);
2405 }
2406
2407 /* Force into index mode. Hope this works. */
2408
2409 /* We do the first bit for 32-bit displacements, and the
2410 second bit for 16 bit ones. It is possible that we
2411 should make the default be WORD instead of LONG, but
2412 I think that'd break GCC, so we put up with a little
2413 inefficiency for the sake of working output. */
2414
2415 if (!issword (nextword)
2416 || (isvar (&opP->disp)
2417 && ((opP->disp.size == SIZE_UNSPEC
2418 && flag_short_refs == 0
2419 && cpu_of_arch (current_architecture) >= m68020
2420 && ! arch_coldfire_p (current_architecture))
2421 || opP->disp.size == SIZE_LONG)))
2422 {
2423 if (cpu_of_arch (current_architecture) < m68020
2424 || arch_coldfire_p (current_architecture))
2425 opP->error =
2426 _("displacement too large for this architecture; needs 68020 or higher");
2427 if (opP->reg == PC)
2428 tmpreg = 0x3B; /* 7.3 */
2429 else
2430 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2431 if (isvar (&opP->disp))
2432 {
2433 if (opP->reg == PC)
2434 {
2435 if (opP->disp.size == SIZE_LONG
2436 #ifdef OBJ_ELF
2437 /* If the displacement needs pic
2438 relocation it cannot be relaxed. */
2439 || opP->disp.pic_reloc != pic_none
2440 #endif
2441 )
2442 {
2443 addword (0x0170);
2444 add_fix ('l', &opP->disp, 1, 2);
2445 }
2446 else
2447 {
2448 add_frag (adds (&opP->disp),
2449 SEXT (offs (&opP->disp)),
2450 TAB (PCREL1632, SZ_UNDEF));
2451 break;
2452 }
2453 }
2454 else
2455 {
2456 addword (0x0170);
2457 add_fix ('l', &opP->disp, 0, 0);
2458 }
2459 }
2460 else
2461 addword (0x0170);
2462 addword (nextword >> 16);
2463 }
2464 else
2465 {
2466 if (opP->reg == PC)
2467 tmpreg = 0x3A; /* 7.2 */
2468 else
2469 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2470
2471 if (isvar (&opP->disp))
2472 {
2473 if (opP->reg == PC)
2474 {
2475 add_fix ('w', &opP->disp, 1, 0);
2476 }
2477 else
2478 add_fix ('w', &opP->disp, 0, 0);
2479 }
2480 }
2481 addword (nextword);
2482 break;
2483
2484 case POST:
2485 case PRE:
2486 case BASE:
2487 nextword = 0;
2488 baseo = get_num (&opP->disp, 90);
2489 if (opP->mode == POST || opP->mode == PRE)
2490 outro = get_num (&opP->odisp, 90);
2491 /* Figure out the `addressing mode'.
2492 Also turn on the BASE_DISABLE bit, if needed. */
2493 if (opP->reg == PC || opP->reg == ZPC)
2494 {
2495 tmpreg = 0x3b; /* 7.3 */
2496 if (opP->reg == ZPC)
2497 nextword |= 0x80;
2498 }
2499 else if (opP->reg == 0)
2500 {
2501 nextword |= 0x80;
2502 tmpreg = 0x30; /* 6.garbage */
2503 }
2504 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2505 {
2506 nextword |= 0x80;
2507 tmpreg = 0x30 + opP->reg - ZADDR0;
2508 }
2509 else
2510 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2511
2512 siz1 = opP->disp.size;
2513 if (opP->mode == POST || opP->mode == PRE)
2514 siz2 = opP->odisp.size;
2515 else
2516 siz2 = SIZE_UNSPEC;
2517
2518 /* Index register stuff. */
2519 if (opP->index.reg != 0
2520 && opP->index.reg >= DATA
2521 && opP->index.reg <= ADDR7)
2522 {
2523 nextword |= (opP->index.reg - DATA) << 12;
2524
2525 if (opP->index.size == SIZE_LONG
2526 || (opP->index.size == SIZE_UNSPEC
2527 && m68k_index_width_default == SIZE_LONG))
2528 nextword |= 0x800;
2529
2530 if ((opP->index.scale != 1
2531 && cpu_of_arch (current_architecture) < m68020)
2532 || (opP->index.scale == 8
2533 && (arch_coldfire_p (current_architecture)
2534 && !arch_coldfire_fpu (current_architecture))))
2535 {
2536 opP->error =
2537 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2538 }
2539
2540 if (arch_coldfire_p (current_architecture)
2541 && opP->index.size == SIZE_WORD)
2542 opP->error = _("invalid index size for coldfire");
2543
2544 switch (opP->index.scale)
2545 {
2546 case 1:
2547 break;
2548 case 2:
2549 nextword |= 0x200;
2550 break;
2551 case 4:
2552 nextword |= 0x400;
2553 break;
2554 case 8:
2555 nextword |= 0x600;
2556 break;
2557 default:
2558 abort ();
2559 }
2560 /* IF its simple,
2561 GET US OUT OF HERE! */
2562
2563 /* Must be INDEX, with an index register. Address
2564 register cannot be ZERO-PC, and either :b was
2565 forced, or we know it will fit. For a 68000 or
2566 68010, force this mode anyways, because the
2567 larger modes aren't supported. */
2568 if (opP->mode == BASE
2569 && ((opP->reg >= ADDR0
2570 && opP->reg <= ADDR7)
2571 || opP->reg == PC))
2572 {
2573 if (siz1 == SIZE_BYTE
2574 || cpu_of_arch (current_architecture) < m68020
2575 || arch_coldfire_p (current_architecture)
2576 || (siz1 == SIZE_UNSPEC
2577 && ! isvar (&opP->disp)
2578 && issbyte (baseo)))
2579 {
2580 nextword += baseo & 0xff;
2581 addword (nextword);
2582 if (isvar (&opP->disp))
2583 {
2584 /* Do a byte relocation. If it doesn't
2585 fit (possible on m68000) let the
2586 fixup processing complain later. */
2587 if (opP->reg == PC)
2588 add_fix ('B', &opP->disp, 1, 1);
2589 else
2590 add_fix ('B', &opP->disp, 0, 0);
2591 }
2592 else if (siz1 != SIZE_BYTE)
2593 {
2594 if (siz1 != SIZE_UNSPEC)
2595 as_warn (_("Forcing byte displacement"));
2596 if (! issbyte (baseo))
2597 opP->error = _("byte displacement out of range");
2598 }
2599
2600 break;
2601 }
2602 else if (siz1 == SIZE_UNSPEC
2603 && opP->reg == PC
2604 && isvar (&opP->disp)
2605 && subs (&opP->disp) == NULL
2606 #ifdef OBJ_ELF
2607 /* If the displacement needs pic
2608 relocation it cannot be relaxed. */
2609 && opP->disp.pic_reloc == pic_none
2610 #endif
2611 )
2612 {
2613 /* The code in md_convert_frag_1 needs to be
2614 able to adjust nextword. Call frag_grow
2615 to ensure that we have enough space in
2616 the frag obstack to make all the bytes
2617 contiguous. */
2618 frag_grow (14);
2619 nextword += baseo & 0xff;
2620 addword (nextword);
2621 add_frag (adds (&opP->disp),
2622 SEXT (offs (&opP->disp)),
2623 TAB (PCINDEX, SZ_UNDEF));
2624
2625 break;
2626 }
2627 }
2628 }
2629 else
2630 {
2631 nextword |= 0x40; /* No index reg. */
2632 if (opP->index.reg >= ZDATA0
2633 && opP->index.reg <= ZDATA7)
2634 nextword |= (opP->index.reg - ZDATA0) << 12;
2635 else if (opP->index.reg >= ZADDR0
2636 || opP->index.reg <= ZADDR7)
2637 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2638 }
2639
2640 /* It isn't simple. */
2641
2642 if (cpu_of_arch (current_architecture) < m68020
2643 || arch_coldfire_p (current_architecture))
2644 opP->error =
2645 _("invalid operand mode for this architecture; needs 68020 or higher");
2646
2647 nextword |= 0x100;
2648 /* If the guy specified a width, we assume that it is
2649 wide enough. Maybe it isn't. If so, we lose. */
2650 switch (siz1)
2651 {
2652 case SIZE_UNSPEC:
2653 if (isvar (&opP->disp)
2654 ? m68k_rel32
2655 : ! issword (baseo))
2656 {
2657 siz1 = SIZE_LONG;
2658 nextword |= 0x30;
2659 }
2660 else if (! isvar (&opP->disp) && baseo == 0)
2661 nextword |= 0x10;
2662 else
2663 {
2664 nextword |= 0x20;
2665 siz1 = SIZE_WORD;
2666 }
2667 break;
2668 case SIZE_BYTE:
2669 as_warn (_(":b not permitted; defaulting to :w"));
2670 /* Fall through. */
2671 case SIZE_WORD:
2672 nextword |= 0x20;
2673 break;
2674 case SIZE_LONG:
2675 nextword |= 0x30;
2676 break;
2677 }
2678
2679 /* Figure out inner displacement stuff. */
2680 if (opP->mode == POST || opP->mode == PRE)
2681 {
2682 if (cpu_of_arch (current_architecture) & cpu32)
2683 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2684 switch (siz2)
2685 {
2686 case SIZE_UNSPEC:
2687 if (isvar (&opP->odisp)
2688 ? m68k_rel32
2689 : ! issword (outro))
2690 {
2691 siz2 = SIZE_LONG;
2692 nextword |= 0x3;
2693 }
2694 else if (! isvar (&opP->odisp) && outro == 0)
2695 nextword |= 0x1;
2696 else
2697 {
2698 nextword |= 0x2;
2699 siz2 = SIZE_WORD;
2700 }
2701 break;
2702 case 1:
2703 as_warn (_(":b not permitted; defaulting to :w"));
2704 /* Fall through. */
2705 case 2:
2706 nextword |= 0x2;
2707 break;
2708 case 3:
2709 nextword |= 0x3;
2710 break;
2711 }
2712 if (opP->mode == POST
2713 && (nextword & 0x40) == 0)
2714 nextword |= 0x04;
2715 }
2716 addword (nextword);
2717
2718 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2719 {
2720 if (opP->reg == PC || opP->reg == ZPC)
2721 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2722 else
2723 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2724 }
2725 if (siz1 == SIZE_LONG)
2726 addword (baseo >> 16);
2727 if (siz1 != SIZE_UNSPEC)
2728 addword (baseo);
2729
2730 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2731 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2732 if (siz2 == SIZE_LONG)
2733 addword (outro >> 16);
2734 if (siz2 != SIZE_UNSPEC)
2735 addword (outro);
2736
2737 break;
2738
2739 case ABSL:
2740 nextword = get_num (&opP->disp, 90);
2741 switch (opP->disp.size)
2742 {
2743 default:
2744 abort ();
2745 case SIZE_UNSPEC:
2746 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2747 {
2748 tmpreg = 0x38; /* 7.0 */
2749 addword (nextword);
2750 break;
2751 }
2752 if (isvar (&opP->disp)
2753 && !subs (&opP->disp)
2754 && adds (&opP->disp)
2755 #ifdef OBJ_ELF
2756 /* If the displacement needs pic relocation it
2757 cannot be relaxed. */
2758 && opP->disp.pic_reloc == pic_none
2759 #endif
2760 && !flag_long_jumps
2761 && !strchr ("~%&$?", s[0]))
2762 {
2763 tmpreg = 0x3A; /* 7.2 */
2764 add_frag (adds (&opP->disp),
2765 SEXT (offs (&opP->disp)),
2766 TAB (ABSTOPCREL, SZ_UNDEF));
2767 break;
2768 }
2769 /* Fall through into long. */
2770 case SIZE_LONG:
2771 if (isvar (&opP->disp))
2772 add_fix ('l', &opP->disp, 0, 0);
2773
2774 tmpreg = 0x39;/* 7.1 mode */
2775 addword (nextword >> 16);
2776 addword (nextword);
2777 break;
2778
2779 case SIZE_BYTE:
2780 as_bad (_("unsupported byte value; use a different suffix"));
2781 /* Fall through. */
2782
2783 case SIZE_WORD:
2784 if (isvar (&opP->disp))
2785 add_fix ('w', &opP->disp, 0, 0);
2786
2787 tmpreg = 0x38;/* 7.0 mode */
2788 addword (nextword);
2789 break;
2790 }
2791 break;
2792 case CONTROL:
2793 case FPREG:
2794 default:
2795 as_bad (_("unknown/incorrect operand"));
2796 /* abort (); */
2797 }
2798
2799 /* If s[0] is '4', then this is for the mac instructions
2800 that can have a trailing_ampersand set. If so, set 0x100
2801 bit on tmpreg so install_gen_operand can check for it and
2802 set the appropriate bit (word2, bit 5). */
2803 if (s[0] == '4')
2804 {
2805 if (opP->trailing_ampersand)
2806 tmpreg |= 0x100;
2807 }
2808 install_gen_operand (s[1], tmpreg);
2809 break;
2810
2811 case '#':
2812 case '^':
2813 switch (s[1])
2814 { /* JF: I hate floating point! */
2815 case 'j':
2816 tmpreg = 70;
2817 break;
2818 case '8':
2819 tmpreg = 20;
2820 break;
2821 case 'C':
2822 tmpreg = 50;
2823 break;
2824 case '3':
2825 default:
2826 tmpreg = 90;
2827 break;
2828 }
2829 tmpreg = get_num (&opP->disp, tmpreg);
2830 if (isvar (&opP->disp))
2831 add_fix (s[1], &opP->disp, 0, 0);
2832 switch (s[1])
2833 {
2834 case 'b': /* Danger: These do no check for
2835 certain types of overflow.
2836 user beware! */
2837 if (!isbyte (tmpreg))
2838 opP->error = _("out of range");
2839 insop (tmpreg, opcode);
2840 if (isvar (&opP->disp))
2841 the_ins.reloc[the_ins.nrel - 1].n =
2842 (opcode->m_codenum) * 2 + 1;
2843 break;
2844 case 'B':
2845 if (!issbyte (tmpreg))
2846 opP->error = _("out of range");
2847 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2848 if (isvar (&opP->disp))
2849 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2850 break;
2851 case 'w':
2852 if (!isword (tmpreg))
2853 opP->error = _("out of range");
2854 insop (tmpreg, opcode);
2855 if (isvar (&opP->disp))
2856 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2857 break;
2858 case 'W':
2859 if (!issword (tmpreg))
2860 opP->error = _("out of range");
2861 insop (tmpreg, opcode);
2862 if (isvar (&opP->disp))
2863 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2864 break;
2865 case 'l':
2866 /* Because of the way insop works, we put these two out
2867 backwards. */
2868 insop (tmpreg, opcode);
2869 insop (tmpreg >> 16, opcode);
2870 if (isvar (&opP->disp))
2871 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2872 break;
2873 case '3':
2874 tmpreg &= 0xFF;
2875 case '8':
2876 case 'C':
2877 case 'j':
2878 install_operand (s[1], tmpreg);
2879 break;
2880 default:
2881 abort ();
2882 }
2883 break;
2884
2885 case '+':
2886 case '-':
2887 case 'A':
2888 case 'a':
2889 install_operand (s[1], opP->reg - ADDR);
2890 break;
2891
2892 case 'B':
2893 tmpreg = get_num (&opP->disp, 90);
2894
2895 switch (s[1])
2896 {
2897 case 'B':
2898 add_fix ('B', &opP->disp, 1, -1);
2899 break;
2900 case 'W':
2901 add_fix ('w', &opP->disp, 1, 0);
2902 addword (0);
2903 break;
2904 case 'L':
2905 long_branch:
2906 the_ins.opcode[0] |= 0xff;
2907 add_fix ('l', &opP->disp, 1, 0);
2908 addword (0);
2909 addword (0);
2910 break;
2911 case 'g': /* Conditional branch */
2912 have_disp = HAVE_LONG_CALL (current_architecture);
2913 goto var_branch;
2914
2915 case 'b': /* Unconditional branch */
2916 have_disp = HAVE_LONG_BRANCH (current_architecture);
2917 goto var_branch;
2918
2919 case 's': /* Unconditional subroutine */
2920 have_disp = HAVE_LONG_CALL (current_architecture);
2921
2922 var_branch:
2923 if (subs (&opP->disp) /* We can't relax it. */
2924 #ifdef OBJ_ELF
2925 /* If the displacement needs pic relocation it cannot be
2926 relaxed. */
2927 || opP->disp.pic_reloc != pic_none
2928 #endif
2929 || 0)
2930 {
2931 if (!have_disp)
2932 as_warn (_("Can't use long branches on this architecture"));
2933 goto long_branch;
2934 }
2935
2936 /* This could either be a symbol, or an absolute
2937 address. If it's an absolute address, turn it into
2938 an absolute jump right here and keep it out of the
2939 relaxer. */
2940 if (adds (&opP->disp) == 0)
2941 {
2942 if (the_ins.opcode[0] == 0x6000) /* jbra */
2943 the_ins.opcode[0] = 0x4EF9;
2944 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2945 the_ins.opcode[0] = 0x4EB9;
2946 else /* jCC */
2947 {
2948 the_ins.opcode[0] ^= 0x0100;
2949 the_ins.opcode[0] |= 0x0006;
2950 addword (0x4EF9);
2951 }
2952 add_fix ('l', &opP->disp, 0, 0);
2953 addword (0);
2954 addword (0);
2955 break;
2956 }
2957
2958 /* Now we know it's going into the relaxer. Now figure
2959 out which mode. We try in this order of preference:
2960 long branch, absolute jump, byte/word branches only. */
2961 if (have_disp)
2962 add_frag (adds (&opP->disp),
2963 SEXT (offs (&opP->disp)),
2964 TAB (BRANCHBWL, SZ_UNDEF));
2965 else if (! flag_keep_pcrel)
2966 {
2967 if ((the_ins.opcode[0] == 0x6000)
2968 || (the_ins.opcode[0] == 0x6100))
2969 add_frag (adds (&opP->disp),
2970 SEXT (offs (&opP->disp)),
2971 TAB (BRABSJUNC, SZ_UNDEF));
2972 else
2973 add_frag (adds (&opP->disp),
2974 SEXT (offs (&opP->disp)),
2975 TAB (BRABSJCOND, SZ_UNDEF));
2976 }
2977 else
2978 add_frag (adds (&opP->disp),
2979 SEXT (offs (&opP->disp)),
2980 TAB (BRANCHBW, SZ_UNDEF));
2981 break;
2982 case 'w':
2983 if (isvar (&opP->disp))
2984 {
2985 /* Check for DBcc instructions. We can relax them,
2986 but only if we have long branches and/or absolute
2987 jumps. */
2988 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2989 && (HAVE_LONG_BRANCH (current_architecture)
2990 || ! flag_keep_pcrel))
2991 {
2992 if (HAVE_LONG_BRANCH (current_architecture))
2993 add_frag (adds (&opP->disp),
2994 SEXT (offs (&opP->disp)),
2995 TAB (DBCCLBR, SZ_UNDEF));
2996 else
2997 add_frag (adds (&opP->disp),
2998 SEXT (offs (&opP->disp)),
2999 TAB (DBCCABSJ, SZ_UNDEF));
3000 break;
3001 }
3002 add_fix ('w', &opP->disp, 1, 0);
3003 }
3004 addword (0);
3005 break;
3006 case 'C': /* Fixed size LONG coproc branches. */
3007 add_fix ('l', &opP->disp, 1, 0);
3008 addword (0);
3009 addword (0);
3010 break;
3011 case 'c': /* Var size Coprocesssor branches. */
3012 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3013 {
3014 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3015 add_fix ('l', &opP->disp, 1, 0);
3016 addword (0);
3017 addword (0);
3018 }
3019 else
3020 add_frag (adds (&opP->disp),
3021 SEXT (offs (&opP->disp)),
3022 TAB (FBRANCH, SZ_UNDEF));
3023 break;
3024 default:
3025 abort ();
3026 }
3027 break;
3028
3029 case 'C': /* Ignore it. */
3030 break;
3031
3032 case 'd': /* JF this is a kludge. */
3033 install_operand ('s', opP->reg - ADDR);
3034 tmpreg = get_num (&opP->disp, 90);
3035 if (!issword (tmpreg))
3036 {
3037 as_warn (_("Expression out of range, using 0"));
3038 tmpreg = 0;
3039 }
3040 addword (tmpreg);
3041 break;
3042
3043 case 'D':
3044 install_operand (s[1], opP->reg - DATA);
3045 break;
3046
3047 case 'e': /* EMAC ACCx, reg/reg. */
3048 install_operand (s[1], opP->reg - ACC);
3049 break;
3050
3051 case 'E': /* Ignore it. */
3052 break;
3053
3054 case 'F':
3055 install_operand (s[1], opP->reg - FP0);
3056 break;
3057
3058 case 'g': /* EMAC ACCEXTx. */
3059 install_operand (s[1], opP->reg - ACCEXT01);
3060 break;
3061
3062 case 'G': /* Ignore it. */
3063 case 'H':
3064 break;
3065
3066 case 'I':
3067 tmpreg = opP->reg - COP0;
3068 install_operand (s[1], tmpreg);
3069 break;
3070
3071 case 'i': /* MAC/EMAC scale factor. */
3072 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3073 break;
3074
3075 case 'J': /* JF foo. */
3076 switch (opP->reg)
3077 {
3078 case SFC:
3079 tmpreg = 0x000;
3080 break;
3081 case DFC:
3082 tmpreg = 0x001;
3083 break;
3084 case CACR:
3085 tmpreg = 0x002;
3086 break;
3087 case TC:
3088 case ASID:
3089 tmpreg = 0x003;
3090 break;
3091 case ACR0:
3092 case ITT0:
3093 tmpreg = 0x004;
3094 break;
3095 case ACR1:
3096 case ITT1:
3097 tmpreg = 0x005;
3098 break;
3099 case ACR2:
3100 case DTT0:
3101 tmpreg = 0x006;
3102 break;
3103 case ACR3:
3104 case DTT1:
3105 tmpreg = 0x007;
3106 break;
3107 case BUSCR:
3108 case MMUBAR:
3109 tmpreg = 0x008;
3110 break;
3111
3112 case USP:
3113 tmpreg = 0x800;
3114 break;
3115 case VBR:
3116 tmpreg = 0x801;
3117 break;
3118 case CAAR:
3119 tmpreg = 0x802;
3120 break;
3121 case MSP:
3122 tmpreg = 0x803;
3123 break;
3124 case ISP:
3125 tmpreg = 0x804;
3126 break;
3127 case MMUSR:
3128 tmpreg = 0x805;
3129 break;
3130 case URP:
3131 tmpreg = 0x806;
3132 break;
3133 case SRP:
3134 tmpreg = 0x807;
3135 break;
3136 case PCR:
3137 tmpreg = 0x808;
3138 break;
3139 case ROMBAR:
3140 case ROMBAR0:
3141 tmpreg = 0xC00;
3142 break;
3143 case ROMBAR1:
3144 tmpreg = 0xC01;
3145 break;
3146 case FLASHBAR:
3147 case RAMBAR0:
3148 case RAMBAR_ALT:
3149 tmpreg = 0xC04;
3150 break;
3151 case RAMBAR:
3152 case RAMBAR1:
3153 tmpreg = 0xC05;
3154 break;
3155 case MPCR:
3156 tmpreg = 0xC0C;
3157 break;
3158 case EDRAMBAR:
3159 tmpreg = 0xC0D;
3160 break;
3161 case MBAR0:
3162 case MBAR2:
3163 case SECMBAR:
3164 tmpreg = 0xC0E;
3165 break;
3166 case MBAR1:
3167 case MBAR:
3168 tmpreg = 0xC0F;
3169 break;
3170 case PCR1U0:
3171 tmpreg = 0xD02;
3172 break;
3173 case PCR1L0:
3174 tmpreg = 0xD03;
3175 break;
3176 case PCR2U0:
3177 tmpreg = 0xD04;
3178 break;
3179 case PCR2L0:
3180 tmpreg = 0xD05;
3181 break;
3182 case PCR3U0:
3183 tmpreg = 0xD06;
3184 break;
3185 case PCR3L0:
3186 tmpreg = 0xD07;
3187 break;
3188 case PCR1L1:
3189 tmpreg = 0xD0A;
3190 break;
3191 case PCR1U1:
3192 tmpreg = 0xD0B;
3193 break;
3194 case PCR2L1:
3195 tmpreg = 0xD0C;
3196 break;
3197 case PCR2U1:
3198 tmpreg = 0xD0D;
3199 break;
3200 case PCR3L1:
3201 tmpreg = 0xD0E;
3202 break;
3203 case PCR3U1:
3204 tmpreg = 0xD0F;
3205 break;
3206 case CAC:
3207 tmpreg = 0xFFE;
3208 break;
3209 case MBB:
3210 tmpreg = 0xFFF;
3211 break;
3212 default:
3213 abort ();
3214 }
3215 install_operand (s[1], tmpreg);
3216 break;
3217
3218 case 'k':
3219 tmpreg = get_num (&opP->disp, 55);
3220 install_operand (s[1], tmpreg & 0x7f);
3221 break;
3222
3223 case 'l':
3224 tmpreg = opP->mask;
3225 if (s[1] == 'w')
3226 {
3227 if (tmpreg & 0x7FF0000)
3228 as_bad (_("Floating point register in register list"));
3229 insop (reverse_16_bits (tmpreg), opcode);
3230 }
3231 else
3232 {
3233 if (tmpreg & 0x700FFFF)
3234 as_bad (_("Wrong register in floating-point reglist"));
3235 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3236 }
3237 break;
3238
3239 case 'L':
3240 tmpreg = opP->mask;
3241 if (s[1] == 'w')
3242 {
3243 if (tmpreg & 0x7FF0000)
3244 as_bad (_("Floating point register in register list"));
3245 insop (tmpreg, opcode);
3246 }
3247 else if (s[1] == '8')
3248 {
3249 if (tmpreg & 0x0FFFFFF)
3250 as_bad (_("incorrect register in reglist"));
3251 install_operand (s[1], tmpreg >> 24);
3252 }
3253 else
3254 {
3255 if (tmpreg & 0x700FFFF)
3256 as_bad (_("wrong register in floating-point reglist"));
3257 else
3258 install_operand (s[1], tmpreg >> 16);
3259 }
3260 break;
3261
3262 case 'M':
3263 install_operand (s[1], get_num (&opP->disp, 60));
3264 break;
3265
3266 case 'O':
3267 tmpreg = ((opP->mode == DREG)
3268 ? 0x20 + (int) (opP->reg - DATA)
3269 : (get_num (&opP->disp, 40) & 0x1F));
3270 install_operand (s[1], tmpreg);
3271 break;
3272
3273 case 'Q':
3274 tmpreg = get_num (&opP->disp, 10);
3275 if (tmpreg == 8)
3276 tmpreg = 0;
3277 install_operand (s[1], tmpreg);
3278 break;
3279
3280 case 'R':
3281 /* This depends on the fact that ADDR registers are eight
3282 more than their corresponding DATA regs, so the result
3283 will have the ADDR_REG bit set. */
3284 install_operand (s[1], opP->reg - DATA);
3285 break;
3286
3287 case 'r':
3288 if (opP->mode == AINDR)
3289 install_operand (s[1], opP->reg - DATA);
3290 else
3291 install_operand (s[1], opP->index.reg - DATA);
3292 break;
3293
3294 case 's':
3295 if (opP->reg == FPI)
3296 tmpreg = 0x1;
3297 else if (opP->reg == FPS)
3298 tmpreg = 0x2;
3299 else if (opP->reg == FPC)
3300 tmpreg = 0x4;
3301 else
3302 abort ();
3303 install_operand (s[1], tmpreg);
3304 break;
3305
3306 case 'S': /* Ignore it. */
3307 break;
3308
3309 case 'T':
3310 install_operand (s[1], get_num (&opP->disp, 30));
3311 break;
3312
3313 case 'U': /* Ignore it. */
3314 break;
3315
3316 case 'c':
3317 switch (opP->reg)
3318 {
3319 case NC:
3320 tmpreg = 0;
3321 break;
3322 case DC:
3323 tmpreg = 1;
3324 break;
3325 case IC:
3326 tmpreg = 2;
3327 break;
3328 case BC:
3329 tmpreg = 3;
3330 break;
3331 default:
3332 as_fatal (_("failed sanity check"));
3333 } /* switch on cache token. */
3334 install_operand (s[1], tmpreg);
3335 break;
3336 #ifndef NO_68851
3337 /* JF: These are out of order, I fear. */
3338 case 'f':
3339 switch (opP->reg)
3340 {
3341 case SFC:
3342 tmpreg = 0;
3343 break;
3344 case DFC:
3345 tmpreg = 1;
3346 break;
3347 default:
3348 abort ();
3349 }
3350 install_operand (s[1], tmpreg);
3351 break;
3352
3353 case '0':
3354 case '1':
3355 case '2':
3356 switch (opP->reg)
3357 {
3358 case TC:
3359 tmpreg = 0;
3360 break;
3361 case CAL:
3362 tmpreg = 4;
3363 break;
3364 case VAL:
3365 tmpreg = 5;
3366 break;
3367 case SCC:
3368 tmpreg = 6;
3369 break;
3370 case AC:
3371 tmpreg = 7;
3372 break;
3373 default:
3374 abort ();
3375 }
3376 install_operand (s[1], tmpreg);
3377 break;
3378
3379 case 'V':
3380 if (opP->reg == VAL)
3381 break;
3382 abort ();
3383
3384 case 'W':
3385 switch (opP->reg)
3386 {
3387 case DRP:
3388 tmpreg = 1;
3389 break;
3390 case SRP:
3391 tmpreg = 2;
3392 break;
3393 case CRP:
3394 tmpreg = 3;
3395 break;
3396 default:
3397 abort ();
3398 }
3399 install_operand (s[1], tmpreg);
3400 break;
3401
3402 case 'X':
3403 switch (opP->reg)
3404 {
3405 case BAD:
3406 case BAD + 1:
3407 case BAD + 2:
3408 case BAD + 3:
3409 case BAD + 4:
3410 case BAD + 5:
3411 case BAD + 6:
3412 case BAD + 7:
3413 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3414 break;
3415
3416 case BAC:
3417 case BAC + 1:
3418 case BAC + 2:
3419 case BAC + 3:
3420 case BAC + 4:
3421 case BAC + 5:
3422 case BAC + 6:
3423 case BAC + 7:
3424 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3425 break;
3426
3427 default:
3428 abort ();
3429 }
3430 install_operand (s[1], tmpreg);
3431 break;
3432 case 'Y':
3433 know (opP->reg == PSR);
3434 break;
3435 case 'Z':
3436 know (opP->reg == PCSR);
3437 break;
3438 #endif /* m68851 */
3439 case '3':
3440 switch (opP->reg)
3441 {
3442 case TT0:
3443 tmpreg = 2;
3444 break;
3445 case TT1:
3446 tmpreg = 3;
3447 break;
3448 default:
3449 abort ();
3450 }
3451 install_operand (s[1], tmpreg);
3452 break;
3453 case 't':
3454 tmpreg = get_num (&opP->disp, 20);
3455 install_operand (s[1], tmpreg);
3456 break;
3457 case '_': /* used only for move16 absolute 32-bit address. */
3458 if (isvar (&opP->disp))
3459 add_fix ('l', &opP->disp, 0, 0);
3460 tmpreg = get_num (&opP->disp, 90);
3461 addword (tmpreg >> 16);
3462 addword (tmpreg & 0xFFFF);
3463 break;
3464 case 'u':
3465 install_operand (s[1], opP->reg - DATA0L);
3466 opP->reg -= (DATA0L);
3467 opP->reg &= 0x0F; /* remove upper/lower bit. */
3468 break;
3469 case 'x':
3470 tmpreg = get_num (&opP->disp, 80);
3471 if (tmpreg == -1)
3472 tmpreg = 0;
3473 install_operand (s[1], tmpreg);
3474 break;
3475 default:
3476 abort ();
3477 }
3478 }
3479
3480 /* By the time whe get here (FINALLY) the_ins contains the complete
3481 instruction, ready to be emitted. . . */
3482 }
3483
3484 static int
3485 reverse_16_bits (int in)
3486 {
3487 int out = 0;
3488 int n;
3489
3490 static int mask[16] =
3491 {
3492 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3493 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3494 };
3495 for (n = 0; n < 16; n++)
3496 {
3497 if (in & mask[n])
3498 out |= mask[15 - n];
3499 }
3500 return out;
3501 } /* reverse_16_bits() */
3502
3503 static int
3504 reverse_8_bits (int in)
3505 {
3506 int out = 0;
3507 int n;
3508
3509 static int mask[8] =
3510 {
3511 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3512 };
3513
3514 for (n = 0; n < 8; n++)
3515 {
3516 if (in & mask[n])
3517 out |= mask[7 - n];
3518 }
3519 return out;
3520 } /* reverse_8_bits() */
3521
3522 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3523 (that value is chosen in the frag_var call in md_assemble). TYPE
3524 is the subtype of the frag to be generated; its primary type is
3525 rs_machine_dependent.
3526
3527 The TYPE parameter is also used by md_convert_frag_1 and
3528 md_estimate_size_before_relax. The appropriate type of fixup will
3529 be emitted by md_convert_frag_1.
3530
3531 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3532 static void
3533 install_operand (int mode, int val)
3534 {
3535 switch (mode)
3536 {
3537 case 's':
3538 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3539 break;
3540 case 'd':
3541 the_ins.opcode[0] |= val << 9;
3542 break;
3543 case '1':
3544 the_ins.opcode[1] |= val << 12;
3545 break;
3546 case '2':
3547 the_ins.opcode[1] |= val << 6;
3548 break;
3549 case '3':
3550 the_ins.opcode[1] |= val;
3551 break;
3552 case '4':
3553 the_ins.opcode[2] |= val << 12;
3554 break;
3555 case '5':
3556 the_ins.opcode[2] |= val << 6;
3557 break;
3558 case '6':
3559 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3560 three words long! */
3561 the_ins.numo++;
3562 the_ins.opcode[2] |= val;
3563 break;
3564 case '7':
3565 the_ins.opcode[1] |= val << 7;
3566 break;
3567 case '8':
3568 the_ins.opcode[1] |= val << 10;
3569 break;
3570 #ifndef NO_68851
3571 case '9':
3572 the_ins.opcode[1] |= val << 5;
3573 break;
3574 #endif
3575
3576 case 't':
3577 the_ins.opcode[1] |= (val << 10) | (val << 7);
3578 break;
3579 case 'D':
3580 the_ins.opcode[1] |= (val << 12) | val;
3581 break;
3582 case 'g':
3583 the_ins.opcode[0] |= val = 0xff;
3584 break;
3585 case 'i':
3586 the_ins.opcode[0] |= val << 9;
3587 break;
3588 case 'C':
3589 the_ins.opcode[1] |= val;
3590 break;
3591 case 'j':
3592 the_ins.opcode[1] |= val;
3593 the_ins.numo++; /* What a hack. */
3594 break;
3595 case 'k':
3596 the_ins.opcode[1] |= val << 4;
3597 break;
3598 case 'b':
3599 case 'w':
3600 case 'W':
3601 case 'l':
3602 break;
3603 case 'e':
3604 the_ins.opcode[0] |= (val << 6);
3605 break;
3606 case 'L':
3607 the_ins.opcode[1] = (val >> 16);
3608 the_ins.opcode[2] = val & 0xffff;
3609 break;
3610 case 'm':
3611 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3612 the_ins.opcode[0] |= ((val & 0x7) << 9);
3613 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3614 break;
3615 case 'n': /* MAC/EMAC Rx on !load. */
3616 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3617 the_ins.opcode[0] |= ((val & 0x7) << 9);
3618 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3619 break;
3620 case 'o': /* MAC/EMAC Rx on load. */
3621 the_ins.opcode[1] |= val << 12;
3622 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3623 break;
3624 case 'M': /* MAC/EMAC Ry on !load. */
3625 the_ins.opcode[0] |= (val & 0xF);
3626 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3627 break;
3628 case 'N': /* MAC/EMAC Ry on load. */
3629 the_ins.opcode[1] |= (val & 0xF);
3630 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3631 break;
3632 case 'h':
3633 the_ins.opcode[1] |= ((val != 1) << 10);
3634 break;
3635 case 'F':
3636 the_ins.opcode[0] |= ((val & 0x3) << 9);
3637 break;
3638 case 'f':
3639 the_ins.opcode[0] |= ((val & 0x3) << 0);
3640 break;
3641 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3642 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3643 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3644 break;
3645 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3646 the_ins.opcode[0] |= ((val & 0x1) << 7);
3647 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3648 break;
3649 case 'I':
3650 the_ins.opcode[1] |= ((val & 0x3) << 9);
3651 break;
3652 case ']':
3653 the_ins.opcode[0] |= (val & 0x1) <<10;
3654 break;
3655 case 'c':
3656 default:
3657 as_fatal (_("failed sanity check."));
3658 }
3659 }
3660
3661 static void
3662 install_gen_operand (int mode, int val)
3663 {
3664 switch (mode)
3665 {
3666 case '/': /* Special for mask loads for mac/msac insns with
3667 possible mask; trailing_ampersend set in bit 8. */
3668 the_ins.opcode[0] |= (val & 0x3f);
3669 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3670 break;
3671 case 's':
3672 the_ins.opcode[0] |= val;
3673 break;
3674 case 'd':
3675 /* This is a kludge!!! */
3676 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3677 break;
3678 case 'b':
3679 case 'w':
3680 case 'l':
3681 case 'f':
3682 case 'F':
3683 case 'x':
3684 case 'p':
3685 the_ins.opcode[0] |= val;
3686 break;
3687 /* more stuff goes here. */
3688 default:
3689 as_fatal (_("failed sanity check."));
3690 }
3691 }
3692
3693 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3694 then deal with the bitfield hack. */
3695
3696 static char *
3697 crack_operand (char *str, struct m68k_op *opP)
3698 {
3699 register int parens;
3700 register int c;
3701 register char *beg_str;
3702 int inquote = 0;
3703
3704 if (!str)
3705 {
3706 return str;
3707 }
3708 beg_str = str;
3709 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3710 {
3711 if (! inquote)
3712 {
3713 if (*str == '(')
3714 parens++;
3715 else if (*str == ')')
3716 {
3717 if (!parens)
3718 { /* ERROR. */
3719 opP->error = _("Extra )");
3720 return str;
3721 }
3722 --parens;
3723 }
3724 }
3725 if (flag_mri && *str == '\'')
3726 inquote = ! inquote;
3727 }
3728 if (!*str && parens)
3729 { /* ERROR. */
3730 opP->error = _("Missing )");
3731 return str;
3732 }
3733 c = *str;
3734 *str = '\0';
3735 if (m68k_ip_op (beg_str, opP) != 0)
3736 {
3737 *str = c;
3738 return str;
3739 }
3740 *str = c;
3741 if (c == '}')
3742 c = *++str; /* JF bitfield hack. */
3743 if (c)
3744 {
3745 c = *++str;
3746 if (!c)
3747 as_bad (_("Missing operand"));
3748 }
3749
3750 /* Detect MRI REG symbols and convert them to REGLSTs. */
3751 if (opP->mode == CONTROL && (int)opP->reg < 0)
3752 {
3753 opP->mode = REGLST;
3754 opP->mask = ~(int)opP->reg;
3755 opP->reg = 0;
3756 }
3757
3758 return str;
3759 }
3760
3761 /* This is the guts of the machine-dependent assembler. STR points to a
3762 machine dependent instruction. This function is supposed to emit
3763 the frags/bytes it assembles to.
3764 */
3765
3766 static void
3767 insert_reg (const char *regname, int regnum)
3768 {
3769 char buf[100];
3770 int i;
3771
3772 #ifdef REGISTER_PREFIX
3773 if (!flag_reg_prefix_optional)
3774 {
3775 buf[0] = REGISTER_PREFIX;
3776 strcpy (buf + 1, regname);
3777 regname = buf;
3778 }
3779 #endif
3780
3781 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3782 &zero_address_frag));
3783
3784 for (i = 0; regname[i]; i++)
3785 buf[i] = TOUPPER (regname[i]);
3786 buf[i] = '\0';
3787
3788 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3789 &zero_address_frag));
3790 }
3791
3792 struct init_entry
3793 {
3794 const char *name;
3795 int number;
3796 };
3797
3798 static const struct init_entry init_table[] =
3799 {
3800 { "d0", DATA0 },
3801 { "d1", DATA1 },
3802 { "d2", DATA2 },
3803 { "d3", DATA3 },
3804 { "d4", DATA4 },
3805 { "d5", DATA5 },
3806 { "d6", DATA6 },
3807 { "d7", DATA7 },
3808 { "a0", ADDR0 },
3809 { "a1", ADDR1 },
3810 { "a2", ADDR2 },
3811 { "a3", ADDR3 },
3812 { "a4", ADDR4 },
3813 { "a5", ADDR5 },
3814 { "a6", ADDR6 },
3815 { "fp", ADDR6 },
3816 { "a7", ADDR7 },
3817 { "sp", ADDR7 },
3818 { "ssp", ADDR7 },
3819 { "fp0", FP0 },
3820 { "fp1", FP1 },
3821 { "fp2", FP2 },
3822 { "fp3", FP3 },
3823 { "fp4", FP4 },
3824 { "fp5", FP5 },
3825 { "fp6", FP6 },
3826 { "fp7", FP7 },
3827 { "fpi", FPI },
3828 { "fpiar", FPI },
3829 { "fpc", FPI },
3830 { "fps", FPS },
3831 { "fpsr", FPS },
3832 { "fpc", FPC },
3833 { "fpcr", FPC },
3834 { "control", FPC },
3835 { "status", FPS },
3836 { "iaddr", FPI },
3837
3838 { "cop0", COP0 },
3839 { "cop1", COP1 },
3840 { "cop2", COP2 },
3841 { "cop3", COP3 },
3842 { "cop4", COP4 },
3843 { "cop5", COP5 },
3844 { "cop6", COP6 },
3845 { "cop7", COP7 },
3846 { "pc", PC },
3847 { "zpc", ZPC },
3848 { "sr", SR },
3849
3850 { "ccr", CCR },
3851 { "cc", CCR },
3852
3853 { "acc", ACC },
3854 { "acc0", ACC },
3855 { "acc1", ACC1 },
3856 { "acc2", ACC2 },
3857 { "acc3", ACC3 },
3858 { "accext01", ACCEXT01 },
3859 { "accext23", ACCEXT23 },
3860 { "macsr", MACSR },
3861 { "mask", MASK },
3862
3863 /* Control registers. */
3864 { "sfc", SFC }, /* Source Function Code. */
3865 { "sfcr", SFC },
3866 { "dfc", DFC }, /* Destination Function Code. */
3867 { "dfcr", DFC },
3868 { "cacr", CACR }, /* Cache Control Register. */
3869 { "caar", CAAR }, /* Cache Address Register. */
3870
3871 { "usp", USP }, /* User Stack Pointer. */
3872 { "vbr", VBR }, /* Vector Base Register. */
3873 { "msp", MSP }, /* Master Stack Pointer. */
3874 { "isp", ISP }, /* Interrupt Stack Pointer. */
3875
3876 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3877 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3878 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3879 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3880
3881 /* 68ec040 versions of same */
3882 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3883 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3884 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3885 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3886
3887 /* Coldfire versions of same. The ColdFire programmer's reference
3888 manual indicated that the order is 2,3,0,1, but Ken Rose
3889 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3890 { "acr0", ACR0 }, /* Access Control Unit 0. */
3891 { "acr1", ACR1 }, /* Access Control Unit 1. */
3892 { "acr2", ACR2 }, /* Access Control Unit 2. */
3893 { "acr3", ACR3 }, /* Access Control Unit 3. */
3894
3895 { "tc", TC }, /* MMU Translation Control Register. */
3896 { "tcr", TC },
3897 { "asid", ASID },
3898
3899 { "mmusr", MMUSR }, /* MMU Status Register. */
3900 { "srp", SRP }, /* User Root Pointer. */
3901 { "urp", URP }, /* Supervisor Root Pointer. */
3902
3903 { "buscr", BUSCR },
3904 { "mmubar", MMUBAR },
3905 { "pcr", PCR },
3906
3907 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3908 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3909 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3910 { "mbar", MBAR }, /* Module Base Address Register. */
3911
3912 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3913 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3914 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3915 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3916 { "mpcr", MPCR }, /* mcfv4e registers. */
3917 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3918 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3919 { "asid", TC }, /* mcfv4e registers. */
3920 { "mmubar", BUSCR }, /* mcfv4e registers. */
3921 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3922 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3923 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3924 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3925 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3926 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3927 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3928 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3929 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3930 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3931 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3932 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3933
3934 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3935 { "rambar", RAMBAR }, /* mcf528x registers. */
3936
3937 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3938
3939 { "cac", CAC }, /* fido registers. */
3940 { "mbb", MBB }, /* fido registers. */
3941 /* End of control registers. */
3942
3943 { "ac", AC },
3944 { "bc", BC },
3945 { "cal", CAL },
3946 { "crp", CRP },
3947 { "drp", DRP },
3948 { "pcsr", PCSR },
3949 { "psr", PSR },
3950 { "scc", SCC },
3951 { "val", VAL },
3952 { "bad0", BAD0 },
3953 { "bad1", BAD1 },
3954 { "bad2", BAD2 },
3955 { "bad3", BAD3 },
3956 { "bad4", BAD4 },
3957 { "bad5", BAD5 },
3958 { "bad6", BAD6 },
3959 { "bad7", BAD7 },
3960 { "bac0", BAC0 },
3961 { "bac1", BAC1 },
3962 { "bac2", BAC2 },
3963 { "bac3", BAC3 },
3964 { "bac4", BAC4 },
3965 { "bac5", BAC5 },
3966 { "bac6", BAC6 },
3967 { "bac7", BAC7 },
3968
3969 { "ic", IC },
3970 { "dc", DC },
3971 { "nc", NC },
3972
3973 { "tt0", TT0 },
3974 { "tt1", TT1 },
3975 /* 68ec030 versions of same. */
3976 { "ac0", TT0 },
3977 { "ac1", TT1 },
3978 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3979 { "acusr", PSR },
3980
3981 /* Suppressed data and address registers. */
3982 { "zd0", ZDATA0 },
3983 { "zd1", ZDATA1 },
3984 { "zd2", ZDATA2 },
3985 { "zd3", ZDATA3 },
3986 { "zd4", ZDATA4 },
3987 { "zd5", ZDATA5 },
3988 { "zd6", ZDATA6 },
3989 { "zd7", ZDATA7 },
3990 { "za0", ZADDR0 },
3991 { "za1", ZADDR1 },
3992 { "za2", ZADDR2 },
3993 { "za3", ZADDR3 },
3994 { "za4", ZADDR4 },
3995 { "za5", ZADDR5 },
3996 { "za6", ZADDR6 },
3997 { "za7", ZADDR7 },
3998
3999 /* Upper and lower data and address registers, used by macw and msacw. */
4000 { "d0l", DATA0L },
4001 { "d1l", DATA1L },
4002 { "d2l", DATA2L },
4003 { "d3l", DATA3L },
4004 { "d4l", DATA4L },
4005 { "d5l", DATA5L },
4006 { "d6l", DATA6L },
4007 { "d7l", DATA7L },
4008
4009 { "a0l", ADDR0L },
4010 { "a1l", ADDR1L },
4011 { "a2l", ADDR2L },
4012 { "a3l", ADDR3L },
4013 { "a4l", ADDR4L },
4014 { "a5l", ADDR5L },
4015 { "a6l", ADDR6L },
4016 { "a7l", ADDR7L },
4017
4018 { "d0u", DATA0U },
4019 { "d1u", DATA1U },
4020 { "d2u", DATA2U },
4021 { "d3u", DATA3U },
4022 { "d4u", DATA4U },
4023 { "d5u", DATA5U },
4024 { "d6u", DATA6U },
4025 { "d7u", DATA7U },
4026
4027 { "a0u", ADDR0U },
4028 { "a1u", ADDR1U },
4029 { "a2u", ADDR2U },
4030 { "a3u", ADDR3U },
4031 { "a4u", ADDR4U },
4032 { "a5u", ADDR5U },
4033 { "a6u", ADDR6U },
4034 { "a7u", ADDR7U },
4035
4036 { 0, 0 }
4037 };
4038
4039 static void
4040 init_regtable (void)
4041 {
4042 int i;
4043 for (i = 0; init_table[i].name; i++)
4044 insert_reg (init_table[i].name, init_table[i].number);
4045 }
4046
4047 void
4048 md_assemble (char *str)
4049 {
4050 const char *er;
4051 short *fromP;
4052 char *toP = NULL;
4053 int m, n = 0;
4054 char *to_beg_P;
4055 int shorts_this_frag;
4056 fixS *fixP;
4057
4058 if (!selected_cpu && !selected_arch)
4059 {
4060 /* We've not selected an architecture yet. Set the default
4061 now. We do this lazily so that an initial .cpu or .arch directive
4062 can specify. */
4063 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4064 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4065 }
4066 if (!initialized)
4067 m68k_init_arch ();
4068
4069 /* In MRI mode, the instruction and operands are separated by a
4070 space. Anything following the operands is a comment. The label
4071 has already been removed. */
4072 if (flag_mri)
4073 {
4074 char *s;
4075 int fields = 0;
4076 int infield = 0;
4077 int inquote = 0;
4078
4079 for (s = str; *s != '\0'; s++)
4080 {
4081 if ((*s == ' ' || *s == '\t') && ! inquote)
4082 {
4083 if (infield)
4084 {
4085 ++fields;
4086 if (fields >= 2)
4087 {
4088 *s = '\0';
4089 break;
4090 }
4091 infield = 0;
4092 }
4093 }
4094 else
4095 {
4096 if (! infield)
4097 infield = 1;
4098 if (*s == '\'')
4099 inquote = ! inquote;
4100 }
4101 }
4102 }
4103
4104 memset (&the_ins, '\0', sizeof (the_ins));
4105 m68k_ip (str);
4106 er = the_ins.error;
4107 if (!er)
4108 {
4109 for (n = 0; n < the_ins.numargs; n++)
4110 if (the_ins.operands[n].error)
4111 {
4112 er = the_ins.operands[n].error;
4113 break;
4114 }
4115 }
4116 if (er)
4117 {
4118 as_bad (_("%s -- statement `%s' ignored"), er, str);
4119 return;
4120 }
4121
4122 /* If there is a current label, record that it marks an instruction. */
4123 if (current_label != NULL)
4124 {
4125 current_label->text = 1;
4126 current_label = NULL;
4127 }
4128
4129 #ifdef OBJ_ELF
4130 /* Tie dwarf2 debug info to the address at the start of the insn. */
4131 dwarf2_emit_insn (0);
4132 #endif
4133
4134 if (the_ins.nfrag == 0)
4135 {
4136 /* No frag hacking involved; just put it out. */
4137 toP = frag_more (2 * the_ins.numo);
4138 fromP = &the_ins.opcode[0];
4139 for (m = the_ins.numo; m; --m)
4140 {
4141 md_number_to_chars (toP, (long) (*fromP), 2);
4142 toP += 2;
4143 fromP++;
4144 }
4145 /* Put out symbol-dependent info. */
4146 for (m = 0; m < the_ins.nrel; m++)
4147 {
4148 switch (the_ins.reloc[m].wid)
4149 {
4150 case 'B':
4151 n = 1;
4152 break;
4153 case 'b':
4154 n = 1;
4155 break;
4156 case '3':
4157 n = 1;
4158 break;
4159 case 'w':
4160 case 'W':
4161 n = 2;
4162 break;
4163 case 'l':
4164 n = 4;
4165 break;
4166 default:
4167 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4168 the_ins.reloc[m].wid);
4169 }
4170
4171 fixP = fix_new_exp (frag_now,
4172 ((toP - frag_now->fr_literal)
4173 - the_ins.numo * 2 + the_ins.reloc[m].n),
4174 n,
4175 &the_ins.reloc[m].exp,
4176 the_ins.reloc[m].pcrel,
4177 get_reloc_code (n, the_ins.reloc[m].pcrel,
4178 the_ins.reloc[m].pic_reloc));
4179 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4180 if (the_ins.reloc[m].wid == 'B')
4181 fixP->fx_signed = 1;
4182 }
4183 return;
4184 }
4185
4186 /* There's some frag hacking. */
4187 {
4188 /* Calculate the max frag size. */
4189 int wid;
4190
4191 wid = 2 * the_ins.fragb[0].fragoff;
4192 for (n = 1; n < the_ins.nfrag; n++)
4193 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4194 /* frag_var part. */
4195 wid += 10;
4196 /* Make sure the whole insn fits in one chunk, in particular that
4197 the var part is attached, as we access one byte before the
4198 variable frag for byte branches. */
4199 frag_grow (wid);
4200 }
4201
4202 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4203 {
4204 int wid;
4205
4206 if (n == 0)
4207 wid = 2 * the_ins.fragb[n].fragoff;
4208 else
4209 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4210 toP = frag_more (wid);
4211 to_beg_P = toP;
4212 shorts_this_frag = 0;
4213 for (m = wid / 2; m; --m)
4214 {
4215 md_number_to_chars (toP, (long) (*fromP), 2);
4216 toP += 2;
4217 fromP++;
4218 shorts_this_frag++;
4219 }
4220 for (m = 0; m < the_ins.nrel; m++)
4221 {
4222 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4223 {
4224 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4225 break;
4226 }
4227 wid = the_ins.reloc[m].wid;
4228 if (wid == 0)
4229 continue;
4230 the_ins.reloc[m].wid = 0;
4231 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4232
4233 fixP = fix_new_exp (frag_now,
4234 ((toP - frag_now->fr_literal)
4235 - the_ins.numo * 2 + the_ins.reloc[m].n),
4236 wid,
4237 &the_ins.reloc[m].exp,
4238 the_ins.reloc[m].pcrel,
4239 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4240 the_ins.reloc[m].pic_reloc));
4241 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4242 }
4243 (void) frag_var (rs_machine_dependent, 10, 0,
4244 (relax_substateT) (the_ins.fragb[n].fragty),
4245 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4246 }
4247 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4248 shorts_this_frag = 0;
4249 if (n)
4250 {
4251 toP = frag_more (n * 2);
4252 while (n--)
4253 {
4254 md_number_to_chars (toP, (long) (*fromP), 2);
4255 toP += 2;
4256 fromP++;
4257 shorts_this_frag++;
4258 }
4259 }
4260 for (m = 0; m < the_ins.nrel; m++)
4261 {
4262 int wid;
4263
4264 wid = the_ins.reloc[m].wid;
4265 if (wid == 0)
4266 continue;
4267 the_ins.reloc[m].wid = 0;
4268 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4269
4270 fixP = fix_new_exp (frag_now,
4271 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4272 - shorts_this_frag * 2),
4273 wid,
4274 &the_ins.reloc[m].exp,
4275 the_ins.reloc[m].pcrel,
4276 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4277 the_ins.reloc[m].pic_reloc));
4278 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4279 }
4280 }
4281
4282 /* Comparison function used by qsort to rank the opcode entries by name. */
4283
4284 static int
4285 m68k_compare_opcode (const void * v1, const void * v2)
4286 {
4287 struct m68k_opcode * op1, * op2;
4288 int ret;
4289
4290 if (v1 == v2)
4291 return 0;
4292
4293 op1 = *(struct m68k_opcode **) v1;
4294 op2 = *(struct m68k_opcode **) v2;
4295
4296 /* Compare the two names. If different, return the comparison.
4297 If the same, return the order they are in the opcode table. */
4298 ret = strcmp (op1->name, op2->name);
4299 if (ret)
4300 return ret;
4301 if (op1 < op2)
4302 return -1;
4303 return 1;
4304 }
4305
4306 void
4307 md_begin (void)
4308 {
4309 const struct m68k_opcode *ins;
4310 struct m68k_incant *hack, *slak;
4311 const char *retval = 0; /* Empty string, or error msg text. */
4312 int i;
4313
4314 /* Set up hash tables with 68000 instructions.
4315 similar to what the vax assembler does. */
4316 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4317 a copy of it at runtime, adding in the information we want but isn't
4318 there. I think it'd be better to have an awk script hack the table
4319 at compile time. Or even just xstr the table and use it as-is. But
4320 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4321 names. */
4322
4323 if (flag_mri)
4324 {
4325 flag_reg_prefix_optional = 1;
4326 m68k_abspcadd = 1;
4327 if (! m68k_rel32_from_cmdline)
4328 m68k_rel32 = 0;
4329 }
4330
4331 /* First sort the opcode table into alphabetical order to seperate
4332 the order that the assembler wants to see the opcodes from the
4333 order that the disassembler wants to see them. */
4334 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4335 if (!m68k_sorted_opcodes)
4336 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4337 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4338
4339 for (i = m68k_numopcodes; i--;)
4340 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4341
4342 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4343 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4344
4345 op_hash = hash_new ();
4346
4347 obstack_begin (&robyn, 4000);
4348 for (i = 0; i < m68k_numopcodes; i++)
4349 {
4350 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4351 do
4352 {
4353 ins = m68k_sorted_opcodes[i];
4354
4355 /* We *could* ignore insns that don't match our
4356 arch here by just leaving them out of the hash. */
4357 slak->m_operands = ins->args;
4358 slak->m_opnum = strlen (slak->m_operands) / 2;
4359 slak->m_arch = ins->arch;
4360 slak->m_opcode = ins->opcode;
4361 /* This is kludgey. */
4362 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4363 if (i + 1 != m68k_numopcodes
4364 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4365 {
4366 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4367 i++;
4368 }
4369 else
4370 slak->m_next = 0;
4371 slak = slak->m_next;
4372 }
4373 while (slak);
4374
4375 retval = hash_insert (op_hash, ins->name, (char *) hack);
4376 if (retval)
4377 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4378 }
4379
4380 for (i = 0; i < m68k_numaliases; i++)
4381 {
4382 const char *name = m68k_opcode_aliases[i].primary;
4383 const char *alias = m68k_opcode_aliases[i].alias;
4384 PTR val = hash_find (op_hash, name);
4385
4386 if (!val)
4387 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4388 retval = hash_insert (op_hash, alias, val);
4389 if (retval)
4390 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4391 }
4392
4393 /* In MRI mode, all unsized branches are variable sized. Normally,
4394 they are word sized. */
4395 if (flag_mri)
4396 {
4397 static struct m68k_opcode_alias mri_aliases[] =
4398 {
4399 { "bhi", "jhi", },
4400 { "bls", "jls", },
4401 { "bcc", "jcc", },
4402 { "bcs", "jcs", },
4403 { "bne", "jne", },
4404 { "beq", "jeq", },
4405 { "bvc", "jvc", },
4406 { "bvs", "jvs", },
4407 { "bpl", "jpl", },
4408 { "bmi", "jmi", },
4409 { "bge", "jge", },
4410 { "blt", "jlt", },
4411 { "bgt", "jgt", },
4412 { "ble", "jle", },
4413 { "bra", "jra", },
4414 { "bsr", "jbsr", },
4415 };
4416
4417 for (i = 0;
4418 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4419 i++)
4420 {
4421 const char *name = mri_aliases[i].primary;
4422 const char *alias = mri_aliases[i].alias;
4423 PTR val = hash_find (op_hash, name);
4424
4425 if (!val)
4426 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4427 retval = hash_jam (op_hash, alias, val);
4428 if (retval)
4429 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4430 }
4431 }
4432
4433 for (i = 0; i < (int) sizeof (notend_table); i++)
4434 {
4435 notend_table[i] = 0;
4436 alt_notend_table[i] = 0;
4437 }
4438
4439 notend_table[','] = 1;
4440 notend_table['{'] = 1;
4441 notend_table['}'] = 1;
4442 alt_notend_table['a'] = 1;
4443 alt_notend_table['A'] = 1;
4444 alt_notend_table['d'] = 1;
4445 alt_notend_table['D'] = 1;
4446 alt_notend_table['#'] = 1;
4447 alt_notend_table['&'] = 1;
4448 alt_notend_table['f'] = 1;
4449 alt_notend_table['F'] = 1;
4450 #ifdef REGISTER_PREFIX
4451 alt_notend_table[REGISTER_PREFIX] = 1;
4452 #endif
4453
4454 /* We need to put '(' in alt_notend_table to handle
4455 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4456 alt_notend_table['('] = 1;
4457
4458 /* We need to put '@' in alt_notend_table to handle
4459 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4460 alt_notend_table['@'] = 1;
4461
4462 /* We need to put digits in alt_notend_table to handle
4463 bfextu %d0{24:1},%d0 */
4464 alt_notend_table['0'] = 1;
4465 alt_notend_table['1'] = 1;
4466 alt_notend_table['2'] = 1;
4467 alt_notend_table['3'] = 1;
4468 alt_notend_table['4'] = 1;
4469 alt_notend_table['5'] = 1;
4470 alt_notend_table['6'] = 1;
4471 alt_notend_table['7'] = 1;
4472 alt_notend_table['8'] = 1;
4473 alt_notend_table['9'] = 1;
4474
4475 #ifndef MIT_SYNTAX_ONLY
4476 /* Insert pseudo ops, these have to go into the opcode table since
4477 gas expects pseudo ops to start with a dot. */
4478 {
4479 int n = 0;
4480
4481 while (mote_pseudo_table[n].poc_name)
4482 {
4483 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4484 hash_insert (op_hash,
4485 mote_pseudo_table[n].poc_name, (char *) hack);
4486 hack->m_operands = 0;
4487 hack->m_opnum = n;
4488 n++;
4489 }
4490 }
4491 #endif
4492
4493 init_regtable ();
4494
4495 #ifdef OBJ_ELF
4496 record_alignment (text_section, 2);
4497 record_alignment (data_section, 2);
4498 record_alignment (bss_section, 2);
4499 #endif
4500 }
4501
4502 \f
4503 /* This is called when a label is defined. */
4504
4505 void
4506 m68k_frob_label (symbolS *sym)
4507 {
4508 struct label_line *n;
4509
4510 n = (struct label_line *) xmalloc (sizeof *n);
4511 n->next = labels;
4512 n->label = sym;
4513 as_where (&n->file, &n->line);
4514 n->text = 0;
4515 labels = n;
4516 current_label = n;
4517
4518 #ifdef OBJ_ELF
4519 dwarf2_emit_label (sym);
4520 #endif
4521 }
4522
4523 /* This is called when a value that is not an instruction is emitted. */
4524
4525 void
4526 m68k_flush_pending_output (void)
4527 {
4528 current_label = NULL;
4529 }
4530
4531 /* This is called at the end of the assembly, when the final value of
4532 the label is known. We warn if this is a text symbol aligned at an
4533 odd location. */
4534
4535 void
4536 m68k_frob_symbol (symbolS *sym)
4537 {
4538 if (S_GET_SEGMENT (sym) == reg_section
4539 && (int) S_GET_VALUE (sym) < 0)
4540 {
4541 S_SET_SEGMENT (sym, absolute_section);
4542 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4543 }
4544 else if ((S_GET_VALUE (sym) & 1) != 0)
4545 {
4546 struct label_line *l;
4547
4548 for (l = labels; l != NULL; l = l->next)
4549 {
4550 if (l->label == sym)
4551 {
4552 if (l->text)
4553 as_warn_where (l->file, l->line,
4554 _("text label `%s' aligned to odd boundary"),
4555 S_GET_NAME (sym));
4556 break;
4557 }
4558 }
4559 }
4560 }
4561 \f
4562 /* This is called if we go in or out of MRI mode because of the .mri
4563 pseudo-op. */
4564
4565 void
4566 m68k_mri_mode_change (int on)
4567 {
4568 if (on)
4569 {
4570 if (! flag_reg_prefix_optional)
4571 {
4572 flag_reg_prefix_optional = 1;
4573 #ifdef REGISTER_PREFIX
4574 init_regtable ();
4575 #endif
4576 }
4577 m68k_abspcadd = 1;
4578 if (! m68k_rel32_from_cmdline)
4579 m68k_rel32 = 0;
4580 }
4581 else
4582 {
4583 if (! reg_prefix_optional_seen)
4584 {
4585 #ifdef REGISTER_PREFIX_OPTIONAL
4586 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4587 #else
4588 flag_reg_prefix_optional = 0;
4589 #endif
4590 #ifdef REGISTER_PREFIX
4591 init_regtable ();
4592 #endif
4593 }
4594 m68k_abspcadd = 0;
4595 if (! m68k_rel32_from_cmdline)
4596 m68k_rel32 = 1;
4597 }
4598 }
4599
4600 /* Equal to MAX_PRECISION in atof-ieee.c. */
4601 #define MAX_LITTLENUMS 6
4602
4603 /* Turn a string in input_line_pointer into a floating point constant
4604 of type TYPE, and store the appropriate bytes in *LITP. The number
4605 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4606 returned, or NULL on OK. */
4607
4608 char *
4609 md_atof (int type, char *litP, int *sizeP)
4610 {
4611 int prec;
4612 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4613 LITTLENUM_TYPE *wordP;
4614 char *t;
4615
4616 switch (type)
4617 {
4618 case 'f':
4619 case 'F':
4620 case 's':
4621 case 'S':
4622 prec = 2;
4623 break;
4624
4625 case 'd':
4626 case 'D':
4627 case 'r':
4628 case 'R':
4629 prec = 4;
4630 break;
4631
4632 case 'x':
4633 case 'X':
4634 prec = 6;
4635 break;
4636
4637 case 'p':
4638 case 'P':
4639 prec = 6;
4640 break;
4641
4642 default:
4643 *sizeP = 0;
4644 return _("Bad call to MD_ATOF()");
4645 }
4646 t = atof_ieee (input_line_pointer, type, words);
4647 if (t)
4648 input_line_pointer = t;
4649
4650 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4651 for (wordP = words; prec--;)
4652 {
4653 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4654 litP += sizeof (LITTLENUM_TYPE);
4655 }
4656 return 0;
4657 }
4658
4659 void
4660 md_number_to_chars (char *buf, valueT val, int n)
4661 {
4662 number_to_chars_bigendian (buf, val, n);
4663 }
4664
4665 void
4666 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4667 {
4668 offsetT val = *valP;
4669 addressT upper_limit;
4670 offsetT lower_limit;
4671
4672 /* This is unnecessary but it convinces the native rs6000 compiler
4673 to generate the code we want. */
4674 char *buf = fixP->fx_frag->fr_literal;
4675 buf += fixP->fx_where;
4676 /* End ibm compiler workaround. */
4677
4678 val = SEXT (val);
4679
4680 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4681 fixP->fx_done = 1;
4682
4683 #ifdef OBJ_ELF
4684 if (fixP->fx_addsy)
4685 {
4686 memset (buf, 0, fixP->fx_size);
4687 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4688
4689 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4690 && !S_IS_DEFINED (fixP->fx_addsy)
4691 && !S_IS_WEAK (fixP->fx_addsy))
4692 S_SET_WEAK (fixP->fx_addsy);
4693 return;
4694 }
4695 #endif
4696
4697 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4698 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4699 return;
4700
4701 switch (fixP->fx_size)
4702 {
4703 /* The cast to offsetT below are necessary to make code
4704 correct for machines where ints are smaller than offsetT. */
4705 case 1:
4706 *buf++ = val;
4707 upper_limit = 0x7f;
4708 lower_limit = - (offsetT) 0x80;
4709 break;
4710 case 2:
4711 *buf++ = (val >> 8);
4712 *buf++ = val;
4713 upper_limit = 0x7fff;
4714 lower_limit = - (offsetT) 0x8000;
4715 break;
4716 case 4:
4717 *buf++ = (val >> 24);
4718 *buf++ = (val >> 16);
4719 *buf++ = (val >> 8);
4720 *buf++ = val;
4721 upper_limit = 0x7fffffff;
4722 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4723 break;
4724 default:
4725 BAD_CASE (fixP->fx_size);
4726 }
4727
4728 /* Fix up a negative reloc. */
4729 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4730 {
4731 fixP->fx_addsy = fixP->fx_subsy;
4732 fixP->fx_subsy = NULL;
4733 fixP->fx_tcbit = 1;
4734 }
4735
4736 /* For non-pc-relative values, it's conceivable we might get something
4737 like "0xff" for a byte field. So extend the upper part of the range
4738 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4739 so that we can do any range checking at all. */
4740 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4741 upper_limit = upper_limit * 2 + 1;
4742
4743 if ((addressT) val > upper_limit
4744 && (val > 0 || val < lower_limit))
4745 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4746
4747 /* A one byte PC-relative reloc means a short branch. We can't use
4748 a short branch with a value of 0 or -1, because those indicate
4749 different opcodes (branches with longer offsets). fixup_segment
4750 in write.c may have clobbered fx_pcrel, so we need to examine the
4751 reloc type. */
4752 if ((fixP->fx_pcrel
4753 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4754 && fixP->fx_size == 1
4755 && (fixP->fx_addsy == NULL
4756 || S_IS_DEFINED (fixP->fx_addsy))
4757 && (val == 0 || val == -1))
4758 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4759 }
4760
4761 /* *fragP has been relaxed to its final size, and now needs to have
4762 the bytes inside it modified to conform to the new size There is UGLY
4763 MAGIC here. ..
4764 */
4765 static void
4766 md_convert_frag_1 (fragS *fragP)
4767 {
4768 long disp;
4769 fixS *fixP;
4770
4771 /* Address in object code of the displacement. */
4772 register int object_address = fragP->fr_fix + fragP->fr_address;
4773
4774 /* Address in gas core of the place to store the displacement. */
4775 /* This convinces the native rs6000 compiler to generate the code we
4776 want. */
4777 register char *buffer_address = fragP->fr_literal;
4778 buffer_address += fragP->fr_fix;
4779 /* End ibm compiler workaround. */
4780
4781 /* The displacement of the address, from current location. */
4782 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4783 disp = (disp + fragP->fr_offset) - object_address;
4784
4785 switch (fragP->fr_subtype)
4786 {
4787 case TAB (BRANCHBWL, BYTE):
4788 case TAB (BRABSJUNC, BYTE):
4789 case TAB (BRABSJCOND, BYTE):
4790 case TAB (BRANCHBW, BYTE):
4791 know (issbyte (disp));
4792 if (disp == 0)
4793 as_bad_where (fragP->fr_file, fragP->fr_line,
4794 _("short branch with zero offset: use :w"));
4795 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4796 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4797 fixP->fx_pcrel_adjust = -1;
4798 break;
4799 case TAB (BRANCHBWL, SHORT):
4800 case TAB (BRABSJUNC, SHORT):
4801 case TAB (BRABSJCOND, SHORT):
4802 case TAB (BRANCHBW, SHORT):
4803 fragP->fr_opcode[1] = 0x00;
4804 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4805 1, RELAX_RELOC_PC16);
4806 fragP->fr_fix += 2;
4807 break;
4808 case TAB (BRANCHBWL, LONG):
4809 fragP->fr_opcode[1] = (char) 0xFF;
4810 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4811 1, RELAX_RELOC_PC32);
4812 fragP->fr_fix += 4;
4813 break;
4814 case TAB (BRABSJUNC, LONG):
4815 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4816 {
4817 if (flag_keep_pcrel)
4818 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4819 fragP->fr_opcode[0] = 0x4E;
4820 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4821 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4822 0, RELAX_RELOC_ABS32);
4823 fragP->fr_fix += 4;
4824 }
4825 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4826 {
4827 if (flag_keep_pcrel)
4828 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4829 fragP->fr_opcode[0] = 0x4E;
4830 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4831 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4832 0, RELAX_RELOC_ABS32);
4833 fragP->fr_fix += 4;
4834 }
4835 else
4836 {
4837 /* This cannot happen, because jbsr and jbra are the only two
4838 unconditional branches. */
4839 abort ();
4840 }
4841 break;
4842 case TAB (BRABSJCOND, LONG):
4843 if (flag_keep_pcrel)
4844 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4845
4846 /* Only Bcc 68000 instructions can come here
4847 Change bcc into b!cc/jmp absl long. */
4848 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4849 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4850
4851 /* JF: these used to be fr_opcode[2,3], but they may be in a
4852 different frag, in which case referring to them is a no-no.
4853 Only fr_opcode[0,1] are guaranteed to work. */
4854 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4855 *buffer_address++ = (char) 0xf9;
4856 fragP->fr_fix += 2; /* Account for jmp instruction. */
4857 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4858 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4859 fragP->fr_fix += 4;
4860 break;
4861 case TAB (FBRANCH, SHORT):
4862 know ((fragP->fr_opcode[1] & 0x40) == 0);
4863 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4864 1, RELAX_RELOC_PC16);
4865 fragP->fr_fix += 2;
4866 break;
4867 case TAB (FBRANCH, LONG):
4868 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4869 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4870 1, RELAX_RELOC_PC32);
4871 fragP->fr_fix += 4;
4872 break;
4873 case TAB (DBCCLBR, SHORT):
4874 case TAB (DBCCABSJ, SHORT):
4875 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4876 1, RELAX_RELOC_PC16);
4877 fragP->fr_fix += 2;
4878 break;
4879 case TAB (DBCCLBR, LONG):
4880 /* Only DBcc instructions can come here.
4881 Change dbcc into dbcc/bral.
4882 JF: these used to be fr_opcode[2-7], but that's wrong. */
4883 if (flag_keep_pcrel)
4884 as_fatal (_("Tried to convert DBcc to absolute jump"));
4885
4886 *buffer_address++ = 0x00; /* Branch offset = 4. */
4887 *buffer_address++ = 0x04;
4888 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4889 *buffer_address++ = 0x06;
4890 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4891 *buffer_address++ = (char) 0xff;
4892
4893 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4894 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4895 RELAX_RELOC_PC32);
4896 fragP->fr_fix += 4;
4897 break;
4898 case TAB (DBCCABSJ, LONG):
4899 /* Only DBcc instructions can come here.
4900 Change dbcc into dbcc/jmp.
4901 JF: these used to be fr_opcode[2-7], but that's wrong. */
4902 if (flag_keep_pcrel)
4903 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4904
4905 *buffer_address++ = 0x00; /* Branch offset = 4. */
4906 *buffer_address++ = 0x04;
4907 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4908 *buffer_address++ = 0x06;
4909 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4910 *buffer_address++ = (char) 0xf9;
4911
4912 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4913 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4914 RELAX_RELOC_ABS32);
4915 fragP->fr_fix += 4;
4916 break;
4917 case TAB (PCREL1632, SHORT):
4918 fragP->fr_opcode[1] &= ~0x3F;
4919 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4920 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4921 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4922 fragP->fr_fix += 2;
4923 break;
4924 case TAB (PCREL1632, LONG):
4925 /* Already set to mode 7.3; this indicates: PC indirect with
4926 suppressed index, 32-bit displacement. */
4927 *buffer_address++ = 0x01;
4928 *buffer_address++ = 0x70;
4929 fragP->fr_fix += 2;
4930 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4931 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4932 fixP->fx_pcrel_adjust = 2;
4933 fragP->fr_fix += 4;
4934 break;
4935 case TAB (PCINDEX, BYTE):
4936 assert (fragP->fr_fix >= 2);
4937 buffer_address[-2] &= ~1;
4938 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4939 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4940 fixP->fx_pcrel_adjust = 1;
4941 break;
4942 case TAB (PCINDEX, SHORT):
4943 assert (fragP->fr_fix >= 2);
4944 buffer_address[-2] |= 0x1;
4945 buffer_address[-1] = 0x20;
4946 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4947 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4948 fixP->fx_pcrel_adjust = 2;
4949 fragP->fr_fix += 2;
4950 break;
4951 case TAB (PCINDEX, LONG):
4952 assert (fragP->fr_fix >= 2);
4953 buffer_address[-2] |= 0x1;
4954 buffer_address[-1] = 0x30;
4955 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4956 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4957 fixP->fx_pcrel_adjust = 2;
4958 fragP->fr_fix += 4;
4959 break;
4960 case TAB (ABSTOPCREL, SHORT):
4961 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4962 1, RELAX_RELOC_PC16);
4963 fragP->fr_fix += 2;
4964 break;
4965 case TAB (ABSTOPCREL, LONG):
4966 if (flag_keep_pcrel)
4967 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4968 /* The thing to do here is force it to ABSOLUTE LONG, since
4969 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4970 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4971 abort ();
4972 fragP->fr_opcode[1] &= ~0x3F;
4973 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4974 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4975 0, RELAX_RELOC_ABS32);
4976 fragP->fr_fix += 4;
4977 break;
4978 }
4979 }
4980
4981 void
4982 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4983 segT sec ATTRIBUTE_UNUSED,
4984 fragS *fragP)
4985 {
4986 md_convert_frag_1 (fragP);
4987 }
4988
4989 /* Force truly undefined symbols to their maximum size, and generally set up
4990 the frag list to be relaxed
4991 */
4992 int
4993 md_estimate_size_before_relax (fragS *fragP, segT segment)
4994 {
4995 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4996 switch (fragP->fr_subtype)
4997 {
4998 case TAB (BRANCHBWL, SZ_UNDEF):
4999 case TAB (BRABSJUNC, SZ_UNDEF):
5000 case TAB (BRABSJCOND, SZ_UNDEF):
5001 {
5002 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5003 && relaxable_symbol (fragP->fr_symbol))
5004 {
5005 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5006 }
5007 else if (flag_short_refs)
5008 {
5009 /* Symbol is undefined and we want short ref. */
5010 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5011 }
5012 else
5013 {
5014 /* Symbol is still undefined. Make it LONG. */
5015 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5016 }
5017 break;
5018 }
5019
5020 case TAB (BRANCHBW, SZ_UNDEF):
5021 {
5022 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5023 && relaxable_symbol (fragP->fr_symbol))
5024 {
5025 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5026 }
5027 else
5028 {
5029 /* Symbol is undefined and we don't have long branches. */
5030 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5031 }
5032 break;
5033 }
5034
5035 case TAB (FBRANCH, SZ_UNDEF):
5036 case TAB (DBCCLBR, SZ_UNDEF):
5037 case TAB (DBCCABSJ, SZ_UNDEF):
5038 case TAB (PCREL1632, SZ_UNDEF):
5039 {
5040 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5041 && relaxable_symbol (fragP->fr_symbol))
5042 || flag_short_refs)
5043 {
5044 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5045 }
5046 else
5047 {
5048 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5049 }
5050 break;
5051 }
5052
5053 case TAB (PCINDEX, SZ_UNDEF):
5054 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5055 && relaxable_symbol (fragP->fr_symbol)))
5056 {
5057 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5058 }
5059 else
5060 {
5061 fragP->fr_subtype = TAB (PCINDEX, LONG);
5062 }
5063 break;
5064
5065 case TAB (ABSTOPCREL, SZ_UNDEF):
5066 {
5067 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5068 && relaxable_symbol (fragP->fr_symbol)))
5069 {
5070 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5071 }
5072 else
5073 {
5074 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5075 }
5076 break;
5077 }
5078
5079 default:
5080 break;
5081 }
5082
5083 /* Now that SZ_UNDEF are taken care of, check others. */
5084 switch (fragP->fr_subtype)
5085 {
5086 case TAB (BRANCHBWL, BYTE):
5087 case TAB (BRABSJUNC, BYTE):
5088 case TAB (BRABSJCOND, BYTE):
5089 case TAB (BRANCHBW, BYTE):
5090 /* We can't do a short jump to the next instruction, so in that
5091 case we force word mode. If the symbol is at the start of a
5092 frag, and it is the next frag with any data in it (usually
5093 this is just the next frag, but assembler listings may
5094 introduce empty frags), we must use word mode. */
5095 if (fragP->fr_symbol)
5096 {
5097 fragS *sym_frag;
5098
5099 sym_frag = symbol_get_frag (fragP->fr_symbol);
5100 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5101 {
5102 fragS *l;
5103
5104 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5105 if (l->fr_fix != 0)
5106 break;
5107 if (l == sym_frag)
5108 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5109 }
5110 }
5111 break;
5112 default:
5113 break;
5114 }
5115 return md_relax_table[fragP->fr_subtype].rlx_length;
5116 }
5117
5118 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5119 /* the bit-field entries in the relocation_info struct plays hell
5120 with the byte-order problems of cross-assembly. So as a hack,
5121 I added this mach. dependent ri twiddler. Ugly, but it gets
5122 you there. -KWK */
5123 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5124 are symbolnum, most sig. byte first. Last byte is broken up with
5125 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5126 nibble as nuthin. (on Sun 3 at least) */
5127 /* Translate the internal relocation information into target-specific
5128 format. */
5129 #ifdef comment
5130 void
5131 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5132 {
5133 /* This is easy. */
5134 md_number_to_chars (the_bytes, ri->r_address, 4);
5135 /* Now the fun stuff. */
5136 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5137 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5138 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5139 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5140 | ((ri->r_length << 5) & 0x60)
5141 | ((ri->r_extern << 4) & 0x10));
5142 }
5143
5144 #endif
5145
5146 #endif /* OBJ_AOUT or OBJ_BOUT */
5147
5148 #ifndef WORKING_DOT_WORD
5149 int md_short_jump_size = 4;
5150 int md_long_jump_size = 6;
5151
5152 void
5153 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5154 fragS *frag ATTRIBUTE_UNUSED,
5155 symbolS *to_symbol ATTRIBUTE_UNUSED)
5156 {
5157 valueT offset;
5158
5159 offset = to_addr - (from_addr + 2);
5160
5161 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5162 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5163 }
5164
5165 void
5166 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5167 fragS *frag, symbolS *to_symbol)
5168 {
5169 valueT offset;
5170
5171 if (!HAVE_LONG_BRANCH (current_architecture))
5172 {
5173 if (flag_keep_pcrel)
5174 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5175 offset = to_addr - S_GET_VALUE (to_symbol);
5176 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5177 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5178 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5179 0, NO_RELOC);
5180 }
5181 else
5182 {
5183 offset = to_addr - (from_addr + 2);
5184 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5185 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5186 }
5187 }
5188
5189 #endif
5190
5191 /* Different values of OK tell what its OK to return. Things that
5192 aren't OK are an error (what a shock, no?)
5193
5194 0: Everything is OK
5195 10: Absolute 1:8 only
5196 20: Absolute 0:7 only
5197 30: absolute 0:15 only
5198 40: Absolute 0:31 only
5199 50: absolute 0:127 only
5200 55: absolute -64:63 only
5201 60: absolute -128:127 only
5202 70: absolute 0:4095 only
5203 80: absolute -1, 1:7 only
5204 90: No bignums. */
5205
5206 static int
5207 get_num (struct m68k_exp *exp, int ok)
5208 {
5209 if (exp->exp.X_op == O_absent)
5210 {
5211 /* Do the same thing the VAX asm does. */
5212 op (exp) = O_constant;
5213 adds (exp) = 0;
5214 subs (exp) = 0;
5215 offs (exp) = 0;
5216 if (ok == 10)
5217 {
5218 as_warn (_("expression out of range: defaulting to 1"));
5219 offs (exp) = 1;
5220 }
5221 }
5222 else if (exp->exp.X_op == O_constant)
5223 {
5224 switch (ok)
5225 {
5226 case 10:
5227 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5228 {
5229 as_warn (_("expression out of range: defaulting to 1"));
5230 offs (exp) = 1;
5231 }
5232 break;
5233 case 20:
5234 if ((valueT) TRUNC (offs (exp)) > 7)
5235 goto outrange;
5236 break;
5237 case 30:
5238 if ((valueT) TRUNC (offs (exp)) > 15)
5239 goto outrange;
5240 break;
5241 case 40:
5242 if ((valueT) TRUNC (offs (exp)) > 32)
5243 goto outrange;
5244 break;
5245 case 50:
5246 if ((valueT) TRUNC (offs (exp)) > 127)
5247 goto outrange;
5248 break;
5249 case 55:
5250 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5251 goto outrange;
5252 break;
5253 case 60:
5254 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5255 goto outrange;
5256 break;
5257 case 70:
5258 if ((valueT) TRUNC (offs (exp)) > 4095)
5259 {
5260 outrange:
5261 as_warn (_("expression out of range: defaulting to 0"));
5262 offs (exp) = 0;
5263 }
5264 break;
5265 case 80:
5266 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5267 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5268 {
5269 as_warn (_("expression out of range: defaulting to 1"));
5270 offs (exp) = 1;
5271 }
5272 break;
5273 default:
5274 break;
5275 }
5276 }
5277 else if (exp->exp.X_op == O_big)
5278 {
5279 if (offs (exp) <= 0 /* flonum. */
5280 && (ok == 90 /* no bignums */
5281 || (ok > 10 /* Small-int ranges including 0 ok. */
5282 /* If we have a flonum zero, a zero integer should
5283 do as well (e.g., in moveq). */
5284 && generic_floating_point_number.exponent == 0
5285 && generic_floating_point_number.low[0] == 0)))
5286 {
5287 /* HACK! Turn it into a long. */
5288 LITTLENUM_TYPE words[6];
5289
5290 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5291 op (exp) = O_constant;
5292 adds (exp) = 0;
5293 subs (exp) = 0;
5294 offs (exp) = words[1] | (words[0] << 16);
5295 }
5296 else if (ok != 0)
5297 {
5298 op (exp) = O_constant;
5299 adds (exp) = 0;
5300 subs (exp) = 0;
5301 offs (exp) = (ok == 10) ? 1 : 0;
5302 as_warn (_("Can't deal with expression; defaulting to %ld"),
5303 (long) offs (exp));
5304 }
5305 }
5306 else
5307 {
5308 if (ok >= 10 && ok <= 80)
5309 {
5310 op (exp) = O_constant;
5311 adds (exp) = 0;
5312 subs (exp) = 0;
5313 offs (exp) = (ok == 10) ? 1 : 0;
5314 as_warn (_("Can't deal with expression; defaulting to %ld"),
5315 (long) offs (exp));
5316 }
5317 }
5318
5319 if (exp->size != SIZE_UNSPEC)
5320 {
5321 switch (exp->size)
5322 {
5323 case SIZE_UNSPEC:
5324 case SIZE_LONG:
5325 break;
5326 case SIZE_BYTE:
5327 if (!isbyte (offs (exp)))
5328 as_warn (_("expression doesn't fit in BYTE"));
5329 break;
5330 case SIZE_WORD:
5331 if (!isword (offs (exp)))
5332 as_warn (_("expression doesn't fit in WORD"));
5333 break;
5334 }
5335 }
5336
5337 return offs (exp);
5338 }
5339
5340 /* These are the back-ends for the various machine dependent pseudo-ops. */
5341
5342 static void
5343 s_data1 (int ignore ATTRIBUTE_UNUSED)
5344 {
5345 subseg_set (data_section, 1);
5346 demand_empty_rest_of_line ();
5347 }
5348
5349 static void
5350 s_data2 (int ignore ATTRIBUTE_UNUSED)
5351 {
5352 subseg_set (data_section, 2);
5353 demand_empty_rest_of_line ();
5354 }
5355
5356 static void
5357 s_bss (int ignore ATTRIBUTE_UNUSED)
5358 {
5359 /* We don't support putting frags in the BSS segment, we fake it
5360 by marking in_bss, then looking at s_skip for clues. */
5361
5362 subseg_set (bss_section, 0);
5363 demand_empty_rest_of_line ();
5364 }
5365
5366 static void
5367 s_even (int ignore ATTRIBUTE_UNUSED)
5368 {
5369 register int temp;
5370 register long temp_fill;
5371
5372 temp = 1; /* JF should be 2? */
5373 temp_fill = get_absolute_expression ();
5374 if (!need_pass_2) /* Never make frag if expect extra pass. */
5375 frag_align (temp, (int) temp_fill, 0);
5376 demand_empty_rest_of_line ();
5377 record_alignment (now_seg, temp);
5378 }
5379
5380 static void
5381 s_proc (int ignore ATTRIBUTE_UNUSED)
5382 {
5383 demand_empty_rest_of_line ();
5384 }
5385 \f
5386 /* Pseudo-ops handled for MRI compatibility. */
5387
5388 /* This function returns non-zero if the argument is a conditional
5389 pseudo-op. This is called when checking whether a pending
5390 alignment is needed. */
5391
5392 int
5393 m68k_conditional_pseudoop (pseudo_typeS *pop)
5394 {
5395 return (pop->poc_handler == s_mri_if
5396 || pop->poc_handler == s_mri_else);
5397 }
5398
5399 /* Handle an MRI style chip specification. */
5400
5401 static void
5402 mri_chip (void)
5403 {
5404 char *s;
5405 char c;
5406 int i;
5407
5408 s = input_line_pointer;
5409 /* We can't use get_symbol_end since the processor names are not proper
5410 symbols. */
5411 while (is_part_of_name (c = *input_line_pointer++))
5412 ;
5413 *--input_line_pointer = 0;
5414 for (i = 0; m68k_cpus[i].name; i++)
5415 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5416 break;
5417 if (!m68k_cpus[i].name)
5418 {
5419 as_bad (_("%s: unrecognized processor name"), s);
5420 *input_line_pointer = c;
5421 ignore_rest_of_line ();
5422 return;
5423 }
5424 *input_line_pointer = c;
5425
5426 if (*input_line_pointer == '/')
5427 current_architecture = 0;
5428 else
5429 current_architecture &= m68881 | m68851;
5430 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5431 control_regs = m68k_cpus[i].control_regs;
5432
5433 while (*input_line_pointer == '/')
5434 {
5435 ++input_line_pointer;
5436 s = input_line_pointer;
5437 /* We can't use get_symbol_end since the processor names are not
5438 proper symbols. */
5439 while (is_part_of_name (c = *input_line_pointer++))
5440 ;
5441 *--input_line_pointer = 0;
5442 if (strcmp (s, "68881") == 0)
5443 current_architecture |= m68881;
5444 else if (strcmp (s, "68851") == 0)
5445 current_architecture |= m68851;
5446 *input_line_pointer = c;
5447 }
5448 }
5449
5450 /* The MRI CHIP pseudo-op. */
5451
5452 static void
5453 s_chip (int ignore ATTRIBUTE_UNUSED)
5454 {
5455 char *stop = NULL;
5456 char stopc;
5457
5458 if (flag_mri)
5459 stop = mri_comment_field (&stopc);
5460 mri_chip ();
5461 if (flag_mri)
5462 mri_comment_end (stop, stopc);
5463 demand_empty_rest_of_line ();
5464 }
5465
5466 /* The MRI FOPT pseudo-op. */
5467
5468 static void
5469 s_fopt (int ignore ATTRIBUTE_UNUSED)
5470 {
5471 SKIP_WHITESPACE ();
5472
5473 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5474 {
5475 int temp;
5476
5477 input_line_pointer += 3;
5478 temp = get_absolute_expression ();
5479 if (temp < 0 || temp > 7)
5480 as_bad (_("bad coprocessor id"));
5481 else
5482 m68k_float_copnum = COP0 + temp;
5483 }
5484 else
5485 {
5486 as_bad (_("unrecognized fopt option"));
5487 ignore_rest_of_line ();
5488 return;
5489 }
5490
5491 demand_empty_rest_of_line ();
5492 }
5493
5494 /* The structure used to handle the MRI OPT pseudo-op. */
5495
5496 struct opt_action
5497 {
5498 /* The name of the option. */
5499 const char *name;
5500
5501 /* If this is not NULL, just call this function. The first argument
5502 is the ARG field of this structure, the second argument is
5503 whether the option was negated. */
5504 void (*pfn) (int arg, int on);
5505
5506 /* If this is not NULL, and the PFN field is NULL, set the variable
5507 this points to. Set it to the ARG field if the option was not
5508 negated, and the NOTARG field otherwise. */
5509 int *pvar;
5510
5511 /* The value to pass to PFN or to assign to *PVAR. */
5512 int arg;
5513
5514 /* The value to assign to *PVAR if the option is negated. If PFN is
5515 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5516 the option may not be negated. */
5517 int notarg;
5518 };
5519
5520 /* The table used to handle the MRI OPT pseudo-op. */
5521
5522 static void skip_to_comma (int, int);
5523 static void opt_nest (int, int);
5524 static void opt_chip (int, int);
5525 static void opt_list (int, int);
5526 static void opt_list_symbols (int, int);
5527
5528 static const struct opt_action opt_table[] =
5529 {
5530 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5531
5532 /* We do relaxing, so there is little use for these options. */
5533 { "b", 0, 0, 0, 0 },
5534 { "brs", 0, 0, 0, 0 },
5535 { "brb", 0, 0, 0, 0 },
5536 { "brl", 0, 0, 0, 0 },
5537 { "brw", 0, 0, 0, 0 },
5538
5539 { "c", 0, 0, 0, 0 },
5540 { "cex", 0, 0, 0, 0 },
5541 { "case", 0, &symbols_case_sensitive, 1, 0 },
5542 { "cl", 0, 0, 0, 0 },
5543 { "cre", 0, 0, 0, 0 },
5544 { "d", 0, &flag_keep_locals, 1, 0 },
5545 { "e", 0, 0, 0, 0 },
5546 { "f", 0, &flag_short_refs, 1, 0 },
5547 { "frs", 0, &flag_short_refs, 1, 0 },
5548 { "frl", 0, &flag_short_refs, 0, 1 },
5549 { "g", 0, 0, 0, 0 },
5550 { "i", 0, 0, 0, 0 },
5551 { "m", 0, 0, 0, 0 },
5552 { "mex", 0, 0, 0, 0 },
5553 { "mc", 0, 0, 0, 0 },
5554 { "md", 0, 0, 0, 0 },
5555 { "nest", opt_nest, 0, 0, 0 },
5556 { "next", skip_to_comma, 0, 0, 0 },
5557 { "o", 0, 0, 0, 0 },
5558 { "old", 0, 0, 0, 0 },
5559 { "op", skip_to_comma, 0, 0, 0 },
5560 { "pco", 0, 0, 0, 0 },
5561 { "p", opt_chip, 0, 0, 0 },
5562 { "pcr", 0, 0, 0, 0 },
5563 { "pcs", 0, 0, 0, 0 },
5564 { "r", 0, 0, 0, 0 },
5565 { "quick", 0, &m68k_quick, 1, 0 },
5566 { "rel32", 0, &m68k_rel32, 1, 0 },
5567 { "s", opt_list, 0, 0, 0 },
5568 { "t", opt_list_symbols, 0, 0, 0 },
5569 { "w", 0, &flag_no_warnings, 0, 1 },
5570 { "x", 0, 0, 0, 0 }
5571 };
5572
5573 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5574
5575 /* The MRI OPT pseudo-op. */
5576
5577 static void
5578 s_opt (int ignore ATTRIBUTE_UNUSED)
5579 {
5580 do
5581 {
5582 int t;
5583 char *s;
5584 char c;
5585 int i;
5586 const struct opt_action *o;
5587
5588 SKIP_WHITESPACE ();
5589
5590 t = 1;
5591 if (*input_line_pointer == '-')
5592 {
5593 ++input_line_pointer;
5594 t = 0;
5595 }
5596 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5597 {
5598 input_line_pointer += 2;
5599 t = 0;
5600 }
5601
5602 s = input_line_pointer;
5603 c = get_symbol_end ();
5604
5605 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5606 {
5607 if (strcasecmp (s, o->name) == 0)
5608 {
5609 if (o->pfn)
5610 {
5611 /* Restore input_line_pointer now in case the option
5612 takes arguments. */
5613 *input_line_pointer = c;
5614 (*o->pfn) (o->arg, t);
5615 }
5616 else if (o->pvar != NULL)
5617 {
5618 if (! t && o->arg == o->notarg)
5619 as_bad (_("option `%s' may not be negated"), s);
5620 *input_line_pointer = c;
5621 *o->pvar = t ? o->arg : o->notarg;
5622 }
5623 else
5624 *input_line_pointer = c;
5625 break;
5626 }
5627 }
5628 if (i >= OPTCOUNT)
5629 {
5630 as_bad (_("option `%s' not recognized"), s);
5631 *input_line_pointer = c;
5632 }
5633 }
5634 while (*input_line_pointer++ == ',');
5635
5636 /* Move back to terminating character. */
5637 --input_line_pointer;
5638 demand_empty_rest_of_line ();
5639 }
5640
5641 /* Skip ahead to a comma. This is used for OPT options which we do
5642 not support and which take arguments. */
5643
5644 static void
5645 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5646 {
5647 while (*input_line_pointer != ','
5648 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5649 ++input_line_pointer;
5650 }
5651
5652 /* Handle the OPT NEST=depth option. */
5653
5654 static void
5655 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5656 {
5657 if (*input_line_pointer != '=')
5658 {
5659 as_bad (_("bad format of OPT NEST=depth"));
5660 return;
5661 }
5662
5663 ++input_line_pointer;
5664 max_macro_nest = get_absolute_expression ();
5665 }
5666
5667 /* Handle the OPT P=chip option. */
5668
5669 static void
5670 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5671 {
5672 if (*input_line_pointer != '=')
5673 {
5674 /* This is just OPT P, which we do not support. */
5675 return;
5676 }
5677
5678 ++input_line_pointer;
5679 mri_chip ();
5680 }
5681
5682 /* Handle the OPT S option. */
5683
5684 static void
5685 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5686 {
5687 listing_list (on);
5688 }
5689
5690 /* Handle the OPT T option. */
5691
5692 static void
5693 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5694 {
5695 if (on)
5696 listing |= LISTING_SYMBOLS;
5697 else
5698 listing &= ~LISTING_SYMBOLS;
5699 }
5700
5701 /* Handle the MRI REG pseudo-op. */
5702
5703 static void
5704 s_reg (int ignore ATTRIBUTE_UNUSED)
5705 {
5706 char *s;
5707 int c;
5708 struct m68k_op rop;
5709 int mask;
5710 char *stop = NULL;
5711 char stopc;
5712
5713 if (line_label == NULL)
5714 {
5715 as_bad (_("missing label"));
5716 ignore_rest_of_line ();
5717 return;
5718 }
5719
5720 if (flag_mri)
5721 stop = mri_comment_field (&stopc);
5722
5723 SKIP_WHITESPACE ();
5724
5725 s = input_line_pointer;
5726 while (ISALNUM (*input_line_pointer)
5727 #ifdef REGISTER_PREFIX
5728 || *input_line_pointer == REGISTER_PREFIX
5729 #endif
5730 || *input_line_pointer == '/'
5731 || *input_line_pointer == '-')
5732 ++input_line_pointer;
5733 c = *input_line_pointer;
5734 *input_line_pointer = '\0';
5735
5736 if (m68k_ip_op (s, &rop) != 0)
5737 {
5738 if (rop.error == NULL)
5739 as_bad (_("bad register list"));
5740 else
5741 as_bad (_("bad register list: %s"), rop.error);
5742 *input_line_pointer = c;
5743 ignore_rest_of_line ();
5744 return;
5745 }
5746
5747 *input_line_pointer = c;
5748
5749 if (rop.mode == REGLST)
5750 mask = rop.mask;
5751 else if (rop.mode == DREG)
5752 mask = 1 << (rop.reg - DATA0);
5753 else if (rop.mode == AREG)
5754 mask = 1 << (rop.reg - ADDR0 + 8);
5755 else if (rop.mode == FPREG)
5756 mask = 1 << (rop.reg - FP0 + 16);
5757 else if (rop.mode == CONTROL
5758 && rop.reg == FPI)
5759 mask = 1 << 24;
5760 else if (rop.mode == CONTROL
5761 && rop.reg == FPS)
5762 mask = 1 << 25;
5763 else if (rop.mode == CONTROL
5764 && rop.reg == FPC)
5765 mask = 1 << 26;
5766 else
5767 {
5768 as_bad (_("bad register list"));
5769 ignore_rest_of_line ();
5770 return;
5771 }
5772
5773 S_SET_SEGMENT (line_label, reg_section);
5774 S_SET_VALUE (line_label, ~mask);
5775 symbol_set_frag (line_label, &zero_address_frag);
5776
5777 if (flag_mri)
5778 mri_comment_end (stop, stopc);
5779
5780 demand_empty_rest_of_line ();
5781 }
5782
5783 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5784
5785 struct save_opts
5786 {
5787 struct save_opts *next;
5788 int abspcadd;
5789 int symbols_case_sensitive;
5790 int keep_locals;
5791 int short_refs;
5792 int architecture;
5793 const enum m68k_register *control_regs;
5794 int quick;
5795 int rel32;
5796 int listing;
5797 int no_warnings;
5798 /* FIXME: We don't save OPT S. */
5799 };
5800
5801 /* This variable holds the stack of saved options. */
5802
5803 static struct save_opts *save_stack;
5804
5805 /* The MRI SAVE pseudo-op. */
5806
5807 static void
5808 s_save (int ignore ATTRIBUTE_UNUSED)
5809 {
5810 struct save_opts *s;
5811
5812 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5813 s->abspcadd = m68k_abspcadd;
5814 s->symbols_case_sensitive = symbols_case_sensitive;
5815 s->keep_locals = flag_keep_locals;
5816 s->short_refs = flag_short_refs;
5817 s->architecture = current_architecture;
5818 s->control_regs = control_regs;
5819 s->quick = m68k_quick;
5820 s->rel32 = m68k_rel32;
5821 s->listing = listing;
5822 s->no_warnings = flag_no_warnings;
5823
5824 s->next = save_stack;
5825 save_stack = s;
5826
5827 demand_empty_rest_of_line ();
5828 }
5829
5830 /* The MRI RESTORE pseudo-op. */
5831
5832 static void
5833 s_restore (int ignore ATTRIBUTE_UNUSED)
5834 {
5835 struct save_opts *s;
5836
5837 if (save_stack == NULL)
5838 {
5839 as_bad (_("restore without save"));
5840 ignore_rest_of_line ();
5841 return;
5842 }
5843
5844 s = save_stack;
5845 save_stack = s->next;
5846
5847 m68k_abspcadd = s->abspcadd;
5848 symbols_case_sensitive = s->symbols_case_sensitive;
5849 flag_keep_locals = s->keep_locals;
5850 flag_short_refs = s->short_refs;
5851 current_architecture = s->architecture;
5852 control_regs = s->control_regs;
5853 m68k_quick = s->quick;
5854 m68k_rel32 = s->rel32;
5855 listing = s->listing;
5856 flag_no_warnings = s->no_warnings;
5857
5858 free (s);
5859
5860 demand_empty_rest_of_line ();
5861 }
5862
5863 /* Types of MRI structured control directives. */
5864
5865 enum mri_control_type
5866 {
5867 mri_for,
5868 mri_if,
5869 mri_repeat,
5870 mri_while
5871 };
5872
5873 /* This structure is used to stack the MRI structured control
5874 directives. */
5875
5876 struct mri_control_info
5877 {
5878 /* The directive within which this one is enclosed. */
5879 struct mri_control_info *outer;
5880
5881 /* The type of directive. */
5882 enum mri_control_type type;
5883
5884 /* Whether an ELSE has been in an IF. */
5885 int else_seen;
5886
5887 /* The add or sub statement at the end of a FOR. */
5888 char *incr;
5889
5890 /* The label of the top of a FOR or REPEAT loop. */
5891 char *top;
5892
5893 /* The label to jump to for the next iteration, or the else
5894 expression of a conditional. */
5895 char *next;
5896
5897 /* The label to jump to to break out of the loop, or the label past
5898 the end of a conditional. */
5899 char *bottom;
5900 };
5901
5902 /* The stack of MRI structured control directives. */
5903
5904 static struct mri_control_info *mri_control_stack;
5905
5906 /* The current MRI structured control directive index number, used to
5907 generate label names. */
5908
5909 static int mri_control_index;
5910
5911 /* Assemble an instruction for an MRI structured control directive. */
5912
5913 static void
5914 mri_assemble (char *str)
5915 {
5916 char *s;
5917
5918 /* md_assemble expects the opcode to be in lower case. */
5919 for (s = str; *s != ' ' && *s != '\0'; s++)
5920 *s = TOLOWER (*s);
5921
5922 md_assemble (str);
5923 }
5924
5925 /* Generate a new MRI label structured control directive label name. */
5926
5927 static char *
5928 mri_control_label (void)
5929 {
5930 char *n;
5931
5932 n = (char *) xmalloc (20);
5933 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5934 ++mri_control_index;
5935 return n;
5936 }
5937
5938 /* Create a new MRI structured control directive. */
5939
5940 static struct mri_control_info *
5941 push_mri_control (enum mri_control_type type)
5942 {
5943 struct mri_control_info *n;
5944
5945 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5946
5947 n->type = type;
5948 n->else_seen = 0;
5949 if (type == mri_if || type == mri_while)
5950 n->top = NULL;
5951 else
5952 n->top = mri_control_label ();
5953 n->next = mri_control_label ();
5954 n->bottom = mri_control_label ();
5955
5956 n->outer = mri_control_stack;
5957 mri_control_stack = n;
5958
5959 return n;
5960 }
5961
5962 /* Pop off the stack of MRI structured control directives. */
5963
5964 static void
5965 pop_mri_control (void)
5966 {
5967 struct mri_control_info *n;
5968
5969 n = mri_control_stack;
5970 mri_control_stack = n->outer;
5971 if (n->top != NULL)
5972 free (n->top);
5973 free (n->next);
5974 free (n->bottom);
5975 free (n);
5976 }
5977
5978 /* Recognize a condition code in an MRI structured control expression. */
5979
5980 static int
5981 parse_mri_condition (int *pcc)
5982 {
5983 char c1, c2;
5984
5985 know (*input_line_pointer == '<');
5986
5987 ++input_line_pointer;
5988 c1 = *input_line_pointer++;
5989 c2 = *input_line_pointer++;
5990
5991 if (*input_line_pointer != '>')
5992 {
5993 as_bad (_("syntax error in structured control directive"));
5994 return 0;
5995 }
5996
5997 ++input_line_pointer;
5998 SKIP_WHITESPACE ();
5999
6000 c1 = TOLOWER (c1);
6001 c2 = TOLOWER (c2);
6002
6003 *pcc = (c1 << 8) | c2;
6004
6005 return 1;
6006 }
6007
6008 /* Parse a single operand in an MRI structured control expression. */
6009
6010 static int
6011 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6012 char **rightstart, char **rightstop)
6013 {
6014 char *s;
6015
6016 SKIP_WHITESPACE ();
6017
6018 *pcc = -1;
6019 *leftstart = NULL;
6020 *leftstop = NULL;
6021 *rightstart = NULL;
6022 *rightstop = NULL;
6023
6024 if (*input_line_pointer == '<')
6025 {
6026 /* It's just a condition code. */
6027 return parse_mri_condition (pcc);
6028 }
6029
6030 /* Look ahead for the condition code. */
6031 for (s = input_line_pointer; *s != '\0'; ++s)
6032 {
6033 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6034 break;
6035 }
6036 if (*s == '\0')
6037 {
6038 as_bad (_("missing condition code in structured control directive"));
6039 return 0;
6040 }
6041
6042 *leftstart = input_line_pointer;
6043 *leftstop = s;
6044 if (*leftstop > *leftstart
6045 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6046 --*leftstop;
6047
6048 input_line_pointer = s;
6049 if (! parse_mri_condition (pcc))
6050 return 0;
6051
6052 /* Look ahead for AND or OR or end of line. */
6053 for (s = input_line_pointer; *s != '\0'; ++s)
6054 {
6055 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6056 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6057 ^^^ ^^ */
6058 if ((s == input_line_pointer
6059 || *(s-1) == ' '
6060 || *(s-1) == '\t')
6061 && ((strncasecmp (s, "AND", 3) == 0
6062 && (s[3] == '.' || ! is_part_of_name (s[3])))
6063 || (strncasecmp (s, "OR", 2) == 0
6064 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6065 break;
6066 }
6067
6068 *rightstart = input_line_pointer;
6069 *rightstop = s;
6070 if (*rightstop > *rightstart
6071 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6072 --*rightstop;
6073
6074 input_line_pointer = s;
6075
6076 return 1;
6077 }
6078
6079 #define MCC(b1, b2) (((b1) << 8) | (b2))
6080
6081 /* Swap the sense of a condition. This changes the condition so that
6082 it generates the same result when the operands are swapped. */
6083
6084 static int
6085 swap_mri_condition (int cc)
6086 {
6087 switch (cc)
6088 {
6089 case MCC ('h', 'i'): return MCC ('c', 's');
6090 case MCC ('l', 's'): return MCC ('c', 'c');
6091 /* <HS> is an alias for <CC>. */
6092 case MCC ('h', 's'):
6093 case MCC ('c', 'c'): return MCC ('l', 's');
6094 /* <LO> is an alias for <CS>. */
6095 case MCC ('l', 'o'):
6096 case MCC ('c', 's'): return MCC ('h', 'i');
6097 case MCC ('p', 'l'): return MCC ('m', 'i');
6098 case MCC ('m', 'i'): return MCC ('p', 'l');
6099 case MCC ('g', 'e'): return MCC ('l', 'e');
6100 case MCC ('l', 't'): return MCC ('g', 't');
6101 case MCC ('g', 't'): return MCC ('l', 't');
6102 case MCC ('l', 'e'): return MCC ('g', 'e');
6103 /* Issue a warning for conditions we can not swap. */
6104 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6105 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6106 case MCC ('v', 'c'):
6107 case MCC ('v', 's'):
6108 default :
6109 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6110 (char) (cc >> 8), (char) (cc));
6111 break;
6112 }
6113 return cc;
6114 }
6115
6116 /* Reverse the sense of a condition. */
6117
6118 static int
6119 reverse_mri_condition (int cc)
6120 {
6121 switch (cc)
6122 {
6123 case MCC ('h', 'i'): return MCC ('l', 's');
6124 case MCC ('l', 's'): return MCC ('h', 'i');
6125 /* <HS> is an alias for <CC> */
6126 case MCC ('h', 's'): return MCC ('l', 'o');
6127 case MCC ('c', 'c'): return MCC ('c', 's');
6128 /* <LO> is an alias for <CS> */
6129 case MCC ('l', 'o'): return MCC ('h', 's');
6130 case MCC ('c', 's'): return MCC ('c', 'c');
6131 case MCC ('n', 'e'): return MCC ('e', 'q');
6132 case MCC ('e', 'q'): return MCC ('n', 'e');
6133 case MCC ('v', 'c'): return MCC ('v', 's');
6134 case MCC ('v', 's'): return MCC ('v', 'c');
6135 case MCC ('p', 'l'): return MCC ('m', 'i');
6136 case MCC ('m', 'i'): return MCC ('p', 'l');
6137 case MCC ('g', 'e'): return MCC ('l', 't');
6138 case MCC ('l', 't'): return MCC ('g', 'e');
6139 case MCC ('g', 't'): return MCC ('l', 'e');
6140 case MCC ('l', 'e'): return MCC ('g', 't');
6141 }
6142 return cc;
6143 }
6144
6145 /* Build an MRI structured control expression. This generates test
6146 and branch instructions. It goes to TRUELAB if the condition is
6147 true, and to FALSELAB if the condition is false. Exactly one of
6148 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6149 is the size qualifier for the expression. EXTENT is the size to
6150 use for the branch. */
6151
6152 static void
6153 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6154 char *rightstart, char *rightstop,
6155 const char *truelab, const char *falselab,
6156 int extent)
6157 {
6158 char *buf;
6159 char *s;
6160
6161 if (leftstart != NULL)
6162 {
6163 struct m68k_op leftop, rightop;
6164 char c;
6165
6166 /* Swap the compare operands, if necessary, to produce a legal
6167 m68k compare instruction. Comparing a register operand with
6168 a non-register operand requires the register to be on the
6169 right (cmp, cmpa). Comparing an immediate value with
6170 anything requires the immediate value to be on the left
6171 (cmpi). */
6172
6173 c = *leftstop;
6174 *leftstop = '\0';
6175 (void) m68k_ip_op (leftstart, &leftop);
6176 *leftstop = c;
6177
6178 c = *rightstop;
6179 *rightstop = '\0';
6180 (void) m68k_ip_op (rightstart, &rightop);
6181 *rightstop = c;
6182
6183 if (rightop.mode == IMMED
6184 || ((leftop.mode == DREG || leftop.mode == AREG)
6185 && (rightop.mode != DREG && rightop.mode != AREG)))
6186 {
6187 char *temp;
6188
6189 /* Correct conditional handling:
6190 if #1 <lt> d0 then ;means if (1 < d0)
6191 ...
6192 endi
6193
6194 should assemble to:
6195
6196 cmp #1,d0 if we do *not* swap the operands
6197 bgt true we need the swapped condition!
6198 ble false
6199 true:
6200 ...
6201 false:
6202 */
6203 temp = leftstart;
6204 leftstart = rightstart;
6205 rightstart = temp;
6206 temp = leftstop;
6207 leftstop = rightstop;
6208 rightstop = temp;
6209 }
6210 else
6211 {
6212 cc = swap_mri_condition (cc);
6213 }
6214 }
6215
6216 if (truelab == NULL)
6217 {
6218 cc = reverse_mri_condition (cc);
6219 truelab = falselab;
6220 }
6221
6222 if (leftstart != NULL)
6223 {
6224 buf = (char *) xmalloc (20
6225 + (leftstop - leftstart)
6226 + (rightstop - rightstart));
6227 s = buf;
6228 *s++ = 'c';
6229 *s++ = 'm';
6230 *s++ = 'p';
6231 if (qual != '\0')
6232 *s++ = TOLOWER (qual);
6233 *s++ = ' ';
6234 memcpy (s, leftstart, leftstop - leftstart);
6235 s += leftstop - leftstart;
6236 *s++ = ',';
6237 memcpy (s, rightstart, rightstop - rightstart);
6238 s += rightstop - rightstart;
6239 *s = '\0';
6240 mri_assemble (buf);
6241 free (buf);
6242 }
6243
6244 buf = (char *) xmalloc (20 + strlen (truelab));
6245 s = buf;
6246 *s++ = 'b';
6247 *s++ = cc >> 8;
6248 *s++ = cc & 0xff;
6249 if (extent != '\0')
6250 *s++ = TOLOWER (extent);
6251 *s++ = ' ';
6252 strcpy (s, truelab);
6253 mri_assemble (buf);
6254 free (buf);
6255 }
6256
6257 /* Parse an MRI structured control expression. This generates test
6258 and branch instructions. STOP is where the expression ends. It
6259 goes to TRUELAB if the condition is true, and to FALSELAB if the
6260 condition is false. Exactly one of TRUELAB and FALSELAB will be
6261 NULL, meaning to fall through. QUAL is the size qualifier for the
6262 expression. EXTENT is the size to use for the branch. */
6263
6264 static void
6265 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6266 const char *falselab, int extent)
6267 {
6268 int c;
6269 int cc;
6270 char *leftstart;
6271 char *leftstop;
6272 char *rightstart;
6273 char *rightstop;
6274
6275 c = *stop;
6276 *stop = '\0';
6277
6278 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6279 &rightstart, &rightstop))
6280 {
6281 *stop = c;
6282 return;
6283 }
6284
6285 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6286 {
6287 const char *flab;
6288
6289 if (falselab != NULL)
6290 flab = falselab;
6291 else
6292 flab = mri_control_label ();
6293
6294 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6295 rightstop, (const char *) NULL, flab, extent);
6296
6297 input_line_pointer += 3;
6298 if (*input_line_pointer != '.'
6299 || input_line_pointer[1] == '\0')
6300 qual = '\0';
6301 else
6302 {
6303 qual = input_line_pointer[1];
6304 input_line_pointer += 2;
6305 }
6306
6307 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6308 &rightstart, &rightstop))
6309 {
6310 *stop = c;
6311 return;
6312 }
6313
6314 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6315 rightstop, truelab, falselab, extent);
6316
6317 if (falselab == NULL)
6318 colon (flab);
6319 }
6320 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6321 {
6322 const char *tlab;
6323
6324 if (truelab != NULL)
6325 tlab = truelab;
6326 else
6327 tlab = mri_control_label ();
6328
6329 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6330 rightstop, tlab, (const char *) NULL, extent);
6331
6332 input_line_pointer += 2;
6333 if (*input_line_pointer != '.'
6334 || input_line_pointer[1] == '\0')
6335 qual = '\0';
6336 else
6337 {
6338 qual = input_line_pointer[1];
6339 input_line_pointer += 2;
6340 }
6341
6342 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6343 &rightstart, &rightstop))
6344 {
6345 *stop = c;
6346 return;
6347 }
6348
6349 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6350 rightstop, truelab, falselab, extent);
6351
6352 if (truelab == NULL)
6353 colon (tlab);
6354 }
6355 else
6356 {
6357 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6358 rightstop, truelab, falselab, extent);
6359 }
6360
6361 *stop = c;
6362 if (input_line_pointer != stop)
6363 as_bad (_("syntax error in structured control directive"));
6364 }
6365
6366 /* Handle the MRI IF pseudo-op. This may be a structured control
6367 directive, or it may be a regular assembler conditional, depending
6368 on its operands. */
6369
6370 static void
6371 s_mri_if (int qual)
6372 {
6373 char *s;
6374 int c;
6375 struct mri_control_info *n;
6376
6377 /* A structured control directive must end with THEN with an
6378 optional qualifier. */
6379 s = input_line_pointer;
6380 /* We only accept '*' as introduction of comments if preceded by white space
6381 or at first column of a line (I think this can't actually happen here?)
6382 This is important when assembling:
6383 if d0 <ne> 12(a0,d0*2) then
6384 if d0 <ne> #CONST*20 then. */
6385 while (! (is_end_of_line[(unsigned char) *s]
6386 || (flag_mri
6387 && *s == '*'
6388 && (s == input_line_pointer
6389 || *(s-1) == ' '
6390 || *(s-1) == '\t'))))
6391 ++s;
6392 --s;
6393 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6394 --s;
6395
6396 if (s - input_line_pointer > 1
6397 && s[-1] == '.')
6398 s -= 2;
6399
6400 if (s - input_line_pointer < 3
6401 || strncasecmp (s - 3, "THEN", 4) != 0)
6402 {
6403 if (qual != '\0')
6404 {
6405 as_bad (_("missing then"));
6406 ignore_rest_of_line ();
6407 return;
6408 }
6409
6410 /* It's a conditional. */
6411 s_if (O_ne);
6412 return;
6413 }
6414
6415 /* Since this might be a conditional if, this pseudo-op will be
6416 called even if we are supported to be ignoring input. Double
6417 check now. Clobber *input_line_pointer so that ignore_input
6418 thinks that this is not a special pseudo-op. */
6419 c = *input_line_pointer;
6420 *input_line_pointer = 0;
6421 if (ignore_input ())
6422 {
6423 *input_line_pointer = c;
6424 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6425 ++input_line_pointer;
6426 demand_empty_rest_of_line ();
6427 return;
6428 }
6429 *input_line_pointer = c;
6430
6431 n = push_mri_control (mri_if);
6432
6433 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6434 n->next, s[1] == '.' ? s[2] : '\0');
6435
6436 if (s[1] == '.')
6437 input_line_pointer = s + 3;
6438 else
6439 input_line_pointer = s + 1;
6440
6441 if (flag_mri)
6442 {
6443 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6444 ++input_line_pointer;
6445 }
6446
6447 demand_empty_rest_of_line ();
6448 }
6449
6450 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6451 structured IF, associate the ELSE with the IF. Otherwise, assume
6452 it is a conditional else. */
6453
6454 static void
6455 s_mri_else (int qual)
6456 {
6457 int c;
6458 char *buf;
6459 char q[2];
6460
6461 if (qual == '\0'
6462 && (mri_control_stack == NULL
6463 || mri_control_stack->type != mri_if
6464 || mri_control_stack->else_seen))
6465 {
6466 s_else (0);
6467 return;
6468 }
6469
6470 c = *input_line_pointer;
6471 *input_line_pointer = 0;
6472 if (ignore_input ())
6473 {
6474 *input_line_pointer = c;
6475 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6476 ++input_line_pointer;
6477 demand_empty_rest_of_line ();
6478 return;
6479 }
6480 *input_line_pointer = c;
6481
6482 if (mri_control_stack == NULL
6483 || mri_control_stack->type != mri_if
6484 || mri_control_stack->else_seen)
6485 {
6486 as_bad (_("else without matching if"));
6487 ignore_rest_of_line ();
6488 return;
6489 }
6490
6491 mri_control_stack->else_seen = 1;
6492
6493 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6494 q[0] = TOLOWER (qual);
6495 q[1] = '\0';
6496 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6497 mri_assemble (buf);
6498 free (buf);
6499
6500 colon (mri_control_stack->next);
6501
6502 if (flag_mri)
6503 {
6504 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6505 ++input_line_pointer;
6506 }
6507
6508 demand_empty_rest_of_line ();
6509 }
6510
6511 /* Handle the MRI ENDI pseudo-op. */
6512
6513 static void
6514 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6515 {
6516 if (mri_control_stack == NULL
6517 || mri_control_stack->type != mri_if)
6518 {
6519 as_bad (_("endi without matching if"));
6520 ignore_rest_of_line ();
6521 return;
6522 }
6523
6524 /* ignore_input will not return true for ENDI, so we don't need to
6525 worry about checking it again here. */
6526
6527 if (! mri_control_stack->else_seen)
6528 colon (mri_control_stack->next);
6529 colon (mri_control_stack->bottom);
6530
6531 pop_mri_control ();
6532
6533 if (flag_mri)
6534 {
6535 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6536 ++input_line_pointer;
6537 }
6538
6539 demand_empty_rest_of_line ();
6540 }
6541
6542 /* Handle the MRI BREAK pseudo-op. */
6543
6544 static void
6545 s_mri_break (int extent)
6546 {
6547 struct mri_control_info *n;
6548 char *buf;
6549 char ex[2];
6550
6551 n = mri_control_stack;
6552 while (n != NULL
6553 && n->type != mri_for
6554 && n->type != mri_repeat
6555 && n->type != mri_while)
6556 n = n->outer;
6557 if (n == NULL)
6558 {
6559 as_bad (_("break outside of structured loop"));
6560 ignore_rest_of_line ();
6561 return;
6562 }
6563
6564 buf = (char *) xmalloc (20 + strlen (n->bottom));
6565 ex[0] = TOLOWER (extent);
6566 ex[1] = '\0';
6567 sprintf (buf, "bra%s %s", ex, n->bottom);
6568 mri_assemble (buf);
6569 free (buf);
6570
6571 if (flag_mri)
6572 {
6573 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6574 ++input_line_pointer;
6575 }
6576
6577 demand_empty_rest_of_line ();
6578 }
6579
6580 /* Handle the MRI NEXT pseudo-op. */
6581
6582 static void
6583 s_mri_next (int extent)
6584 {
6585 struct mri_control_info *n;
6586 char *buf;
6587 char ex[2];
6588
6589 n = mri_control_stack;
6590 while (n != NULL
6591 && n->type != mri_for
6592 && n->type != mri_repeat
6593 && n->type != mri_while)
6594 n = n->outer;
6595 if (n == NULL)
6596 {
6597 as_bad (_("next outside of structured loop"));
6598 ignore_rest_of_line ();
6599 return;
6600 }
6601
6602 buf = (char *) xmalloc (20 + strlen (n->next));
6603 ex[0] = TOLOWER (extent);
6604 ex[1] = '\0';
6605 sprintf (buf, "bra%s %s", ex, n->next);
6606 mri_assemble (buf);
6607 free (buf);
6608
6609 if (flag_mri)
6610 {
6611 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6612 ++input_line_pointer;
6613 }
6614
6615 demand_empty_rest_of_line ();
6616 }
6617
6618 /* Handle the MRI FOR pseudo-op. */
6619
6620 static void
6621 s_mri_for (int qual)
6622 {
6623 const char *varstart, *varstop;
6624 const char *initstart, *initstop;
6625 const char *endstart, *endstop;
6626 const char *bystart, *bystop;
6627 int up;
6628 int by;
6629 int extent;
6630 struct mri_control_info *n;
6631 char *buf;
6632 char *s;
6633 char ex[2];
6634
6635 /* The syntax is
6636 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6637 */
6638
6639 SKIP_WHITESPACE ();
6640 varstart = input_line_pointer;
6641
6642 /* Look for the '='. */
6643 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6644 && *input_line_pointer != '=')
6645 ++input_line_pointer;
6646 if (*input_line_pointer != '=')
6647 {
6648 as_bad (_("missing ="));
6649 ignore_rest_of_line ();
6650 return;
6651 }
6652
6653 varstop = input_line_pointer;
6654 if (varstop > varstart
6655 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6656 --varstop;
6657
6658 ++input_line_pointer;
6659
6660 initstart = input_line_pointer;
6661
6662 /* Look for TO or DOWNTO. */
6663 up = 1;
6664 initstop = NULL;
6665 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6666 {
6667 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6668 && ! is_part_of_name (input_line_pointer[2]))
6669 {
6670 initstop = input_line_pointer;
6671 input_line_pointer += 2;
6672 break;
6673 }
6674 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6675 && ! is_part_of_name (input_line_pointer[6]))
6676 {
6677 initstop = input_line_pointer;
6678 up = 0;
6679 input_line_pointer += 6;
6680 break;
6681 }
6682 ++input_line_pointer;
6683 }
6684 if (initstop == NULL)
6685 {
6686 as_bad (_("missing to or downto"));
6687 ignore_rest_of_line ();
6688 return;
6689 }
6690 if (initstop > initstart
6691 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6692 --initstop;
6693
6694 SKIP_WHITESPACE ();
6695 endstart = input_line_pointer;
6696
6697 /* Look for BY or DO. */
6698 by = 0;
6699 endstop = NULL;
6700 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6701 {
6702 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6703 && ! is_part_of_name (input_line_pointer[2]))
6704 {
6705 endstop = input_line_pointer;
6706 by = 1;
6707 input_line_pointer += 2;
6708 break;
6709 }
6710 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6711 && (input_line_pointer[2] == '.'
6712 || ! is_part_of_name (input_line_pointer[2])))
6713 {
6714 endstop = input_line_pointer;
6715 input_line_pointer += 2;
6716 break;
6717 }
6718 ++input_line_pointer;
6719 }
6720 if (endstop == NULL)
6721 {
6722 as_bad (_("missing do"));
6723 ignore_rest_of_line ();
6724 return;
6725 }
6726 if (endstop > endstart
6727 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6728 --endstop;
6729
6730 if (! by)
6731 {
6732 bystart = "#1";
6733 bystop = bystart + 2;
6734 }
6735 else
6736 {
6737 SKIP_WHITESPACE ();
6738 bystart = input_line_pointer;
6739
6740 /* Look for DO. */
6741 bystop = NULL;
6742 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6743 {
6744 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6745 && (input_line_pointer[2] == '.'
6746 || ! is_part_of_name (input_line_pointer[2])))
6747 {
6748 bystop = input_line_pointer;
6749 input_line_pointer += 2;
6750 break;
6751 }
6752 ++input_line_pointer;
6753 }
6754 if (bystop == NULL)
6755 {
6756 as_bad (_("missing do"));
6757 ignore_rest_of_line ();
6758 return;
6759 }
6760 if (bystop > bystart
6761 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6762 --bystop;
6763 }
6764
6765 if (*input_line_pointer != '.')
6766 extent = '\0';
6767 else
6768 {
6769 extent = input_line_pointer[1];
6770 input_line_pointer += 2;
6771 }
6772
6773 /* We have fully parsed the FOR operands. Now build the loop. */
6774 n = push_mri_control (mri_for);
6775
6776 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6777
6778 /* Move init,var. */
6779 s = buf;
6780 *s++ = 'm';
6781 *s++ = 'o';
6782 *s++ = 'v';
6783 *s++ = 'e';
6784 if (qual != '\0')
6785 *s++ = TOLOWER (qual);
6786 *s++ = ' ';
6787 memcpy (s, initstart, initstop - initstart);
6788 s += initstop - initstart;
6789 *s++ = ',';
6790 memcpy (s, varstart, varstop - varstart);
6791 s += varstop - varstart;
6792 *s = '\0';
6793 mri_assemble (buf);
6794
6795 colon (n->top);
6796
6797 /* cmp end,var. */
6798 s = buf;
6799 *s++ = 'c';
6800 *s++ = 'm';
6801 *s++ = 'p';
6802 if (qual != '\0')
6803 *s++ = TOLOWER (qual);
6804 *s++ = ' ';
6805 memcpy (s, endstart, endstop - endstart);
6806 s += endstop - endstart;
6807 *s++ = ',';
6808 memcpy (s, varstart, varstop - varstart);
6809 s += varstop - varstart;
6810 *s = '\0';
6811 mri_assemble (buf);
6812
6813 /* bcc bottom. */
6814 ex[0] = TOLOWER (extent);
6815 ex[1] = '\0';
6816 if (up)
6817 sprintf (buf, "blt%s %s", ex, n->bottom);
6818 else
6819 sprintf (buf, "bgt%s %s", ex, n->bottom);
6820 mri_assemble (buf);
6821
6822 /* Put together the add or sub instruction used by ENDF. */
6823 s = buf;
6824 if (up)
6825 strcpy (s, "add");
6826 else
6827 strcpy (s, "sub");
6828 s += 3;
6829 if (qual != '\0')
6830 *s++ = TOLOWER (qual);
6831 *s++ = ' ';
6832 memcpy (s, bystart, bystop - bystart);
6833 s += bystop - bystart;
6834 *s++ = ',';
6835 memcpy (s, varstart, varstop - varstart);
6836 s += varstop - varstart;
6837 *s = '\0';
6838 n->incr = buf;
6839
6840 if (flag_mri)
6841 {
6842 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6843 ++input_line_pointer;
6844 }
6845
6846 demand_empty_rest_of_line ();
6847 }
6848
6849 /* Handle the MRI ENDF pseudo-op. */
6850
6851 static void
6852 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6853 {
6854 if (mri_control_stack == NULL
6855 || mri_control_stack->type != mri_for)
6856 {
6857 as_bad (_("endf without for"));
6858 ignore_rest_of_line ();
6859 return;
6860 }
6861
6862 colon (mri_control_stack->next);
6863
6864 mri_assemble (mri_control_stack->incr);
6865
6866 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6867 mri_assemble (mri_control_stack->incr);
6868
6869 free (mri_control_stack->incr);
6870
6871 colon (mri_control_stack->bottom);
6872
6873 pop_mri_control ();
6874
6875 if (flag_mri)
6876 {
6877 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6878 ++input_line_pointer;
6879 }
6880
6881 demand_empty_rest_of_line ();
6882 }
6883
6884 /* Handle the MRI REPEAT pseudo-op. */
6885
6886 static void
6887 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6888 {
6889 struct mri_control_info *n;
6890
6891 n = push_mri_control (mri_repeat);
6892 colon (n->top);
6893 if (flag_mri)
6894 {
6895 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6896 ++input_line_pointer;
6897 }
6898 demand_empty_rest_of_line ();
6899 }
6900
6901 /* Handle the MRI UNTIL pseudo-op. */
6902
6903 static void
6904 s_mri_until (int qual)
6905 {
6906 char *s;
6907
6908 if (mri_control_stack == NULL
6909 || mri_control_stack->type != mri_repeat)
6910 {
6911 as_bad (_("until without repeat"));
6912 ignore_rest_of_line ();
6913 return;
6914 }
6915
6916 colon (mri_control_stack->next);
6917
6918 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6919 ;
6920
6921 parse_mri_control_expression (s, qual, (const char *) NULL,
6922 mri_control_stack->top, '\0');
6923
6924 colon (mri_control_stack->bottom);
6925
6926 input_line_pointer = s;
6927
6928 pop_mri_control ();
6929
6930 if (flag_mri)
6931 {
6932 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6933 ++input_line_pointer;
6934 }
6935
6936 demand_empty_rest_of_line ();
6937 }
6938
6939 /* Handle the MRI WHILE pseudo-op. */
6940
6941 static void
6942 s_mri_while (int qual)
6943 {
6944 char *s;
6945
6946 struct mri_control_info *n;
6947
6948 s = input_line_pointer;
6949 /* We only accept '*' as introduction of comments if preceded by white space
6950 or at first column of a line (I think this can't actually happen here?)
6951 This is important when assembling:
6952 while d0 <ne> 12(a0,d0*2) do
6953 while d0 <ne> #CONST*20 do. */
6954 while (! (is_end_of_line[(unsigned char) *s]
6955 || (flag_mri
6956 && *s == '*'
6957 && (s == input_line_pointer
6958 || *(s-1) == ' '
6959 || *(s-1) == '\t'))))
6960 s++;
6961 --s;
6962 while (*s == ' ' || *s == '\t')
6963 --s;
6964 if (s - input_line_pointer > 1
6965 && s[-1] == '.')
6966 s -= 2;
6967 if (s - input_line_pointer < 2
6968 || strncasecmp (s - 1, "DO", 2) != 0)
6969 {
6970 as_bad (_("missing do"));
6971 ignore_rest_of_line ();
6972 return;
6973 }
6974
6975 n = push_mri_control (mri_while);
6976
6977 colon (n->next);
6978
6979 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6980 s[1] == '.' ? s[2] : '\0');
6981
6982 input_line_pointer = s + 1;
6983 if (*input_line_pointer == '.')
6984 input_line_pointer += 2;
6985
6986 if (flag_mri)
6987 {
6988 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6989 ++input_line_pointer;
6990 }
6991
6992 demand_empty_rest_of_line ();
6993 }
6994
6995 /* Handle the MRI ENDW pseudo-op. */
6996
6997 static void
6998 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6999 {
7000 char *buf;
7001
7002 if (mri_control_stack == NULL
7003 || mri_control_stack->type != mri_while)
7004 {
7005 as_bad (_("endw without while"));
7006 ignore_rest_of_line ();
7007 return;
7008 }
7009
7010 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7011 sprintf (buf, "bra %s", mri_control_stack->next);
7012 mri_assemble (buf);
7013 free (buf);
7014
7015 colon (mri_control_stack->bottom);
7016
7017 pop_mri_control ();
7018
7019 if (flag_mri)
7020 {
7021 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7022 ++input_line_pointer;
7023 }
7024
7025 demand_empty_rest_of_line ();
7026 }
7027 \f
7028 /* Parse a .cpu directive. */
7029
7030 static void
7031 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7032 {
7033 char saved_char;
7034 char *name;
7035
7036 if (initialized)
7037 {
7038 as_bad (_("already assembled instructions"));
7039 ignore_rest_of_line ();
7040 return;
7041 }
7042
7043 name = input_line_pointer;
7044 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7045 input_line_pointer++;
7046 saved_char = *input_line_pointer;
7047 *input_line_pointer = 0;
7048
7049 m68k_set_cpu (name, 1, 0);
7050
7051 *input_line_pointer = saved_char;
7052 demand_empty_rest_of_line ();
7053 return;
7054 }
7055
7056 /* Parse a .arch directive. */
7057
7058 static void
7059 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7060 {
7061 char saved_char;
7062 char *name;
7063
7064 if (initialized)
7065 {
7066 as_bad (_("already assembled instructions"));
7067 ignore_rest_of_line ();
7068 return;
7069 }
7070
7071 name = input_line_pointer;
7072 while (*input_line_pointer && *input_line_pointer != ','
7073 && !ISSPACE (*input_line_pointer))
7074 input_line_pointer++;
7075 saved_char = *input_line_pointer;
7076 *input_line_pointer = 0;
7077
7078 if (m68k_set_arch (name, 1, 0))
7079 {
7080 /* Scan extensions. */
7081 do
7082 {
7083 *input_line_pointer++ = saved_char;
7084 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7085 break;
7086 name = input_line_pointer;
7087 while (*input_line_pointer && *input_line_pointer != ','
7088 && !ISSPACE (*input_line_pointer))
7089 input_line_pointer++;
7090 saved_char = *input_line_pointer;
7091 *input_line_pointer = 0;
7092 }
7093 while (m68k_set_extension (name, 1, 0));
7094 }
7095
7096 *input_line_pointer = saved_char;
7097 demand_empty_rest_of_line ();
7098 return;
7099 }
7100 \f
7101 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7102 if none is found, the caller is responsible for emitting an error
7103 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7104 cpu name, if it begins with a '6' (possibly skipping an intervening
7105 'c'. We also allow a 'c' in the same place. if NEGATED is
7106 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7107 the option is indeed negated. */
7108
7109 static const struct m68k_cpu *
7110 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7111 int allow_m, int *negated)
7112 {
7113 /* allow negated value? */
7114 if (negated)
7115 {
7116 *negated = 0;
7117
7118 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7119 {
7120 arg += 3;
7121 *negated = 1;
7122 }
7123 }
7124
7125 /* Remove 'm' or 'mc' prefix from 68k variants. */
7126 if (allow_m)
7127 {
7128 if (arg[0] == 'm')
7129 {
7130 if (arg[1] == '6')
7131 arg += 1;
7132 else if (arg[1] == 'c' && arg[2] == '6')
7133 arg += 2;
7134 }
7135 }
7136 else if (arg[0] == 'c' && arg[1] == '6')
7137 arg += 1;
7138
7139 for (; table->name; table++)
7140 if (!strcmp (arg, table->name))
7141 {
7142 if (table->alias < -1 || table->alias > 1)
7143 as_bad (_("`%s' is deprecated, use `%s'"),
7144 table->name, table[table->alias < 0 ? 1 : -1].name);
7145 return table;
7146 }
7147 return 0;
7148 }
7149
7150 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7151
7152 static int
7153 m68k_set_cpu (char const *name, int allow_m, int silent)
7154 {
7155 const struct m68k_cpu *cpu;
7156
7157 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7158
7159 if (!cpu)
7160 {
7161 if (!silent)
7162 as_bad (_("cpu `%s' unrecognized"), name);
7163 return 0;
7164 }
7165
7166 if (selected_cpu && selected_cpu != cpu)
7167 {
7168 as_bad (_("already selected `%s' processor"),
7169 selected_cpu->name);
7170 return 0;
7171 }
7172 selected_cpu = cpu;
7173 return 1;
7174 }
7175
7176 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7177
7178 static int
7179 m68k_set_arch (char const *name, int allow_m, int silent)
7180 {
7181 const struct m68k_cpu *arch;
7182
7183 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7184
7185 if (!arch)
7186 {
7187 if (!silent)
7188 as_bad (_("architecture `%s' unrecognized"), name);
7189 return 0;
7190 }
7191
7192 if (selected_arch && selected_arch != arch)
7193 {
7194 as_bad (_("already selected `%s' architecture"),
7195 selected_arch->name);
7196 return 0;
7197 }
7198
7199 selected_arch = arch;
7200 return 1;
7201 }
7202
7203 /* Set the architecture extension, issuing errors if it is
7204 unrecognized, or invalid */
7205
7206 static int
7207 m68k_set_extension (char const *name, int allow_m, int silent)
7208 {
7209 int negated;
7210 const struct m68k_cpu *ext;
7211
7212 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7213
7214 if (!ext)
7215 {
7216 if (!silent)
7217 as_bad (_("extension `%s' unrecognized"), name);
7218 return 0;
7219 }
7220
7221 if (negated)
7222 not_current_architecture |= ext->arch;
7223 else
7224 current_architecture |= ext->arch;
7225 return 1;
7226 }
7227
7228 /* md_parse_option
7229 Invocation line includes a switch not recognized by the base assembler.
7230 */
7231
7232 #ifdef OBJ_ELF
7233 const char *md_shortopts = "lSA:m:kQ:V";
7234 #else
7235 const char *md_shortopts = "lSA:m:k";
7236 #endif
7237
7238 struct option md_longopts[] = {
7239 #define OPTION_PIC (OPTION_MD_BASE)
7240 {"pic", no_argument, NULL, OPTION_PIC},
7241 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7242 {"register-prefix-optional", no_argument, NULL,
7243 OPTION_REGISTER_PREFIX_OPTIONAL},
7244 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7245 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7246 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7247 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7248 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7249 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7250 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7251 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7252 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7253 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7254 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7255 {"pcrel", no_argument, NULL, OPTION_PCREL},
7256 {NULL, no_argument, NULL, 0}
7257 };
7258 size_t md_longopts_size = sizeof (md_longopts);
7259
7260 int
7261 md_parse_option (int c, char *arg)
7262 {
7263 switch (c)
7264 {
7265 case 'l': /* -l means keep external to 2 bit offset
7266 rather than 16 bit one. */
7267 flag_short_refs = 1;
7268 break;
7269
7270 case 'S': /* -S means that jbsr's always turn into
7271 jsr's. */
7272 flag_long_jumps = 1;
7273 break;
7274
7275 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7276 branches into absolute jumps. */
7277 flag_keep_pcrel = 1;
7278 break;
7279
7280 case OPTION_PIC:
7281 case 'k':
7282 flag_want_pic = 1;
7283 break; /* -pic, Position Independent Code. */
7284
7285 case OPTION_REGISTER_PREFIX_OPTIONAL:
7286 flag_reg_prefix_optional = 1;
7287 reg_prefix_optional_seen = 1;
7288 break;
7289
7290 /* -V: SVR4 argument to print version ID. */
7291 case 'V':
7292 print_version_id ();
7293 break;
7294
7295 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7296 should be emitted or not. FIXME: Not implemented. */
7297 case 'Q':
7298 break;
7299
7300 case OPTION_BITWISE_OR:
7301 {
7302 char *n, *t;
7303 const char *s;
7304
7305 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7306 t = n;
7307 for (s = m68k_comment_chars; *s != '\0'; s++)
7308 if (*s != '|')
7309 *t++ = *s;
7310 *t = '\0';
7311 m68k_comment_chars = n;
7312 }
7313 break;
7314
7315 case OPTION_BASE_SIZE_DEFAULT_16:
7316 m68k_index_width_default = SIZE_WORD;
7317 break;
7318
7319 case OPTION_BASE_SIZE_DEFAULT_32:
7320 m68k_index_width_default = SIZE_LONG;
7321 break;
7322
7323 case OPTION_DISP_SIZE_DEFAULT_16:
7324 m68k_rel32 = 0;
7325 m68k_rel32_from_cmdline = 1;
7326 break;
7327
7328 case OPTION_DISP_SIZE_DEFAULT_32:
7329 m68k_rel32 = 1;
7330 m68k_rel32_from_cmdline = 1;
7331 break;
7332
7333 case 'A':
7334 #if WARN_DEPRECATED
7335 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7336 arg, arg));
7337 #endif
7338 /* Intentional fall-through. */
7339 case 'm':
7340 if (!strncmp (arg, "arch=", 5))
7341 m68k_set_arch (arg + 5, 1, 0);
7342 else if (!strncmp (arg, "cpu=", 4))
7343 m68k_set_cpu (arg + 4, 1, 0);
7344 else if (m68k_set_extension (arg, 0, 1))
7345 ;
7346 else if (m68k_set_arch (arg, 0, 1))
7347 ;
7348 else if (m68k_set_cpu (arg, 0, 1))
7349 ;
7350 else
7351 return 0;
7352 break;
7353
7354 default:
7355 return 0;
7356 }
7357
7358 return 1;
7359 }
7360
7361 /* Setup tables from the selected arch and/or cpu */
7362
7363 static void
7364 m68k_init_arch (void)
7365 {
7366 if (not_current_architecture & current_architecture)
7367 {
7368 as_bad (_("architecture features both enabled and disabled"));
7369 not_current_architecture &= ~current_architecture;
7370 }
7371 if (selected_arch)
7372 {
7373 current_architecture |= selected_arch->arch;
7374 control_regs = selected_arch->control_regs;
7375 }
7376 else
7377 current_architecture |= selected_cpu->arch;
7378
7379 current_architecture &= ~not_current_architecture;
7380
7381 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7382 {
7383 /* Determine which float is really meant. */
7384 if (current_architecture & (m68k_mask & ~m68881))
7385 current_architecture ^= cfloat;
7386 else
7387 current_architecture ^= m68881;
7388 }
7389
7390 if (selected_cpu)
7391 {
7392 control_regs = selected_cpu->control_regs;
7393 if (current_architecture & ~selected_cpu->arch)
7394 {
7395 as_bad (_("selected processor does not have all features of selected architecture"));
7396 current_architecture
7397 = selected_cpu->arch & ~not_current_architecture;
7398 }
7399 }
7400
7401 if ((current_architecture & m68k_mask)
7402 && (current_architecture & ~m68k_mask))
7403 {
7404 as_bad (_ ("m68k and cf features both selected"));
7405 if (current_architecture & m68k_mask)
7406 current_architecture &= m68k_mask;
7407 else
7408 current_architecture &= ~m68k_mask;
7409 }
7410
7411 /* Permit m68881 specification with all cpus; those that can't work
7412 with a coprocessor could be doing emulation. */
7413 if (current_architecture & m68851)
7414 {
7415 if (current_architecture & m68040)
7416 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7417 }
7418 /* What other incompatibilities could we check for? */
7419
7420 if (cpu_of_arch (current_architecture) < m68020
7421 || arch_coldfire_p (current_architecture))
7422 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7423
7424 initialized = 1;
7425 }
7426
7427 void
7428 md_show_usage (FILE *stream)
7429 {
7430 const char *default_cpu = TARGET_CPU;
7431 int i;
7432 unsigned int default_arch;
7433
7434 /* Get the canonical name for the default target CPU. */
7435 if (*default_cpu == 'm')
7436 default_cpu++;
7437 for (i = 0; m68k_cpus[i].name; i++)
7438 {
7439 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7440 {
7441 default_arch = m68k_cpus[i].arch;
7442 while (m68k_cpus[i].alias > 0)
7443 i--;
7444 while (m68k_cpus[i].alias < 0)
7445 i++;
7446 default_cpu = m68k_cpus[i].name;
7447 }
7448 }
7449
7450 fprintf (stream, _("\
7451 -march=<arch> set architecture\n\
7452 -mcpu=<cpu> set cpu [default %s]\n\
7453 "), default_cpu);
7454 for (i = 0; m68k_extensions[i].name; i++)
7455 fprintf (stream, _("\
7456 -m[no-]%-16s enable/disable%s architecture extension\n\
7457 "), m68k_extensions[i].name,
7458 m68k_extensions[i].alias > 0 ? " ColdFire"
7459 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7460
7461 fprintf (stream, _("\
7462 -l use 1 word for refs to undefined symbols [default 2]\n\
7463 -pic, -k generate position independent code\n\
7464 -S turn jbsr into jsr\n\
7465 --pcrel never turn PC-relative branches into absolute jumps\n\
7466 --register-prefix-optional\n\
7467 recognize register names without prefix character\n\
7468 --bitwise-or do not treat `|' as a comment character\n\
7469 --base-size-default-16 base reg without size is 16 bits\n\
7470 --base-size-default-32 base reg without size is 32 bits (default)\n\
7471 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7472 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7473 "));
7474
7475 fprintf (stream, _("Architecture variants are: "));
7476 for (i = 0; m68k_archs[i].name; i++)
7477 {
7478 if (i)
7479 fprintf (stream, " | ");
7480 fprintf (stream, m68k_archs[i].name);
7481 }
7482 fprintf (stream, "\n");
7483
7484 fprintf (stream, _("Processor variants are: "));
7485 for (i = 0; m68k_cpus[i].name; i++)
7486 {
7487 if (i)
7488 fprintf (stream, " | ");
7489 fprintf (stream, m68k_cpus[i].name);
7490 }
7491 fprintf (stream, _("\n"));
7492 }
7493 \f
7494 #ifdef TEST2
7495
7496 /* TEST2: Test md_assemble() */
7497 /* Warning, this routine probably doesn't work anymore. */
7498 int
7499 main (void)
7500 {
7501 struct m68k_it the_ins;
7502 char buf[120];
7503 char *cp;
7504 int n;
7505
7506 m68k_ip_begin ();
7507 for (;;)
7508 {
7509 if (!gets (buf) || !*buf)
7510 break;
7511 if (buf[0] == '|' || buf[1] == '.')
7512 continue;
7513 for (cp = buf; *cp; cp++)
7514 if (*cp == '\t')
7515 *cp = ' ';
7516 if (is_label (buf))
7517 continue;
7518 memset (&the_ins, '\0', sizeof (the_ins));
7519 m68k_ip (&the_ins, buf);
7520 if (the_ins.error)
7521 {
7522 printf (_("Error %s in %s\n"), the_ins.error, buf);
7523 }
7524 else
7525 {
7526 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7527 for (n = 0; n < the_ins.numo; n++)
7528 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7529 printf (" ");
7530 print_the_insn (&the_ins.opcode[0], stdout);
7531 (void) putchar ('\n');
7532 }
7533 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7534 {
7535 if (the_ins.operands[n].error)
7536 {
7537 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7538 continue;
7539 }
7540 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7541 the_ins.operands[n].reg);
7542 if (the_ins.operands[n].b_const)
7543 printf ("Constant: '%.*s', ",
7544 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7545 the_ins.operands[n].b_const);
7546 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7547 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7548 if (the_ins.operands[n].b_iadd)
7549 printf ("Iadd: '%.*s',",
7550 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7551 the_ins.operands[n].b_iadd);
7552 putchar ('\n');
7553 }
7554 }
7555 m68k_ip_end ();
7556 return 0;
7557 }
7558
7559 int
7560 is_label (char *str)
7561 {
7562 while (*str == ' ')
7563 str++;
7564 while (*str && *str != ' ')
7565 str++;
7566 if (str[-1] == ':' || str[1] == '=')
7567 return 1;
7568 return 0;
7569 }
7570
7571 #endif
7572
7573 /* Possible states for relaxation:
7574
7575 0 0 branch offset byte (bra, etc)
7576 0 1 word
7577 0 2 long
7578
7579 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7580 1 1 word
7581 1 2 long
7582
7583 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7584 2 1 word-long
7585 2 2 long-word
7586 2 3 long-long
7587
7588 */
7589
7590 /* We have no need to default values of symbols. */
7591
7592 symbolS *
7593 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7594 {
7595 return 0;
7596 }
7597
7598 /* Round up a section size to the appropriate boundary. */
7599 valueT
7600 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7601 {
7602 #ifdef OBJ_AOUT
7603 /* For a.out, force the section size to be aligned. If we don't do
7604 this, BFD will align it for us, but it will not write out the
7605 final bytes of the section. This may be a bug in BFD, but it is
7606 easier to fix it here since that is how the other a.out targets
7607 work. */
7608 int align;
7609
7610 align = bfd_get_section_alignment (stdoutput, segment);
7611 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7612 #endif
7613
7614 return size;
7615 }
7616
7617 /* Exactly what point is a PC-relative offset relative TO?
7618 On the 68k, it is relative to the address of the first extension
7619 word. The difference between the addresses of the offset and the
7620 first extension word is stored in fx_pcrel_adjust. */
7621 long
7622 md_pcrel_from (fixS *fixP)
7623 {
7624 int adjust;
7625
7626 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7627 sign extend the value here. */
7628 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7629 if (adjust == 64)
7630 adjust = -1;
7631 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7632 }
7633
7634 #ifdef OBJ_ELF
7635 void
7636 m68k_elf_final_processing (void)
7637 {
7638 unsigned flags = 0;
7639
7640 if (arch_coldfire_fpu (current_architecture))
7641 flags |= EF_M68K_CFV4E;
7642 /* Set file-specific flags if this is a cpu32 processor. */
7643 if (cpu_of_arch (current_architecture) & cpu32)
7644 flags |= EF_M68K_CPU32;
7645 else if (cpu_of_arch (current_architecture) & fido_a)
7646 flags |= EF_M68K_FIDO;
7647 else if ((cpu_of_arch (current_architecture) & m68000up)
7648 && !(cpu_of_arch (current_architecture) & m68020up))
7649 flags |= EF_M68K_M68000;
7650
7651 if (current_architecture & mcfisa_a)
7652 {
7653 static const unsigned isa_features[][2] =
7654 {
7655 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7656 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7657 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7658 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7659 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7660 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7661 {0,0},
7662 };
7663 static const unsigned mac_features[][2] =
7664 {
7665 {EF_M68K_CF_MAC, mcfmac},
7666 {EF_M68K_CF_EMAC, mcfemac},
7667 {0,0},
7668 };
7669 unsigned ix;
7670 unsigned pattern;
7671
7672 pattern = (current_architecture
7673 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7674 for (ix = 0; isa_features[ix][1]; ix++)
7675 {
7676 if (pattern == isa_features[ix][1])
7677 {
7678 flags |= isa_features[ix][0];
7679 break;
7680 }
7681 }
7682 if (!isa_features[ix][1])
7683 {
7684 cf_bad:
7685 as_warn (_("Not a defined coldfire architecture"));
7686 }
7687 else
7688 {
7689 if (current_architecture & cfloat)
7690 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7691
7692 pattern = current_architecture & (mcfmac|mcfemac);
7693 if (pattern)
7694 {
7695 for (ix = 0; mac_features[ix][1]; ix++)
7696 {
7697 if (pattern == mac_features[ix][1])
7698 {
7699 flags |= mac_features[ix][0];
7700 break;
7701 }
7702 }
7703 if (!mac_features[ix][1])
7704 goto cf_bad;
7705 }
7706 }
7707 }
7708 elf_elfheader (stdoutput)->e_flags |= flags;
7709 }
7710 #endif
7711
7712 int
7713 tc_m68k_regname_to_dw2regnum (char *regname)
7714 {
7715 unsigned int regnum;
7716 static const char *const regnames[] =
7717 {
7718 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7719 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7720 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7721 "pc"
7722 };
7723
7724 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7725 if (strcmp (regname, regnames[regnum]) == 0)
7726 return regnum;
7727
7728 return -1;
7729 }
7730
7731 void
7732 tc_m68k_frame_initial_instructions (void)
7733 {
7734 static int sp_regno = -1;
7735
7736 if (sp_regno < 0)
7737 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7738
7739 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7740 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7741 }
GDB Binutils - Deliverables
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