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* config/tc-m68k.c (m68k_ip): When recognizing '#', use isbyte and
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #define NO_RELOC 0
23 #include "as.h"
24 #include "obstack.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
31 #ifdef OBJ_ELF
32 CONST char comment_chars[] = "|#";
33 #else
34 CONST char comment_chars[] = "|";
35 #endif
36
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 CONST char line_comment_chars[] = "#";
45
46 CONST char line_separator_chars[] = "";
47
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
50
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
53
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
55
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
59
60 const int md_reloc_size = 8; /* Size of relocation record */
61
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
64 references. */
65 int flag_want_pic;
66
67 static int flag_short_refs; /* -l option */
68 static int flag_long_jumps; /* -S option */
69
70 #ifdef REGISTER_PREFIX_OPTIONAL
71 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
72 #else
73 int flag_reg_prefix_optional;
74 #endif
75
76 /* The floating point coprocessor to use by default. */
77 static enum m68k_register m68k_float_copnum = COP1;
78
79 /* If this is non-zero, then references to number(%pc) will be taken
80 to refer to number, rather than to %pc + number. */
81 static int m68k_abspcadd;
82
83 /* If this is non-zero, then the quick forms of the move, add, and sub
84 instructions are used when possible. */
85 static int m68k_quick = 1;
86
87 /* If this is non-zero, then if the size is not specified for a base
88 or outer displacement, the assembler assumes that the size should
89 be 32 bits. */
90 static int m68k_rel32 = 1;
91
92 /* Its an arbitrary name: This means I don't approve of it */
93 /* See flames below */
94 static struct obstack robyn;
95
96 #define TAB(x,y) (((x)<<2)+(y))
97 #define TABTYPE(xy) ((xy) >> 2)
98 #define BYTE 0
99 #define SHORT 1
100 #define LONG 2
101 #define SZ_UNDEF 3
102 #undef BRANCH
103 /* Case `g' except when BCC68000 is applicable. */
104 #define ABRANCH 1
105 /* Coprocessor branches. */
106 #define FBRANCH 2
107 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
108 supported on all cpus. Widens to 32-bit absolute. */
109 #define PCREL 3
110 /* For inserting an extra jmp instruction with long offset on 68000,
111 for expanding conditional branches. (Not bsr or bra.) Since the
112 68000 doesn't support 32-bit displacements for conditional
113 branches, we fake it by reversing the condition and branching
114 around a jmp with an absolute long operand. */
115 #define BCC68000 4
116 /* For the DBcc "instructions". If the displacement requires 32 bits,
117 the branch-around-a-jump game is played here too. */
118 #define DBCC 5
119 /* Not currently used? */
120 #define PCLEA 6
121 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
122 in 16 or 8 bits. */
123 #define PCINDEX 7
124
125 struct m68k_incant
126 {
127 const char *m_operands;
128 unsigned long m_opcode;
129 short m_opnum;
130 short m_codenum;
131 int m_arch;
132 struct m68k_incant *m_next;
133 };
134
135 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
136 #define gettwo(x) (((x)->m_opcode)&0xffff)
137
138 static const enum m68k_register m68000_control_regs[] = { 0 };
139 static const enum m68k_register m68010_control_regs[] = {
140 SFC, DFC, USP, VBR,
141 0
142 };
143 static const enum m68k_register m68020_control_regs[] = {
144 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
145 0
146 };
147 static const enum m68k_register m68040_control_regs[] = {
148 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
149 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
150 0
151 };
152 static const enum m68k_register m68060_control_regs[] = {
153 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
154 USP, VBR, URP, SRP, PCR,
155 0
156 };
157 #define cpu32_control_regs m68010_control_regs
158
159 static const enum m68k_register *control_regs;
160
161 /* internal form of a 68020 instruction */
162 struct m68k_it
163 {
164 const char *error;
165 const char *args; /* list of opcode info */
166 int numargs;
167
168 int numo; /* Number of shorts in opcode */
169 short opcode[11];
170
171 struct m68k_op operands[6];
172
173 int nexp; /* number of exprs in use */
174 struct m68k_exp exprs[4];
175
176 int nfrag; /* Number of frags we have to produce */
177 struct
178 {
179 int fragoff; /* Where in the current opcode the frag ends */
180 symbolS *fadd;
181 long foff;
182 int fragty;
183 }
184 fragb[4];
185
186 int nrel; /* Num of reloc strucs in use */
187 struct
188 {
189 int n;
190 expressionS exp;
191 char wid;
192 char pcrel;
193 /* In a pc relative address the difference between the address
194 of the offset and the address that the offset is relative
195 to. This depends on the addressing mode. Basically this
196 is the value to put in the offset field to address the
197 first byte of the offset, without regarding the special
198 significance of some values (in the branch instruction, for
199 example). */
200 int pcrel_fix;
201 }
202 reloc[5]; /* Five is enough??? */
203 };
204
205 #define cpu_of_arch(x) ((x) & m68000up)
206 #define float_of_arch(x) ((x) & mfloat)
207 #define mmu_of_arch(x) ((x) & mmmu)
208
209 static struct m68k_it the_ins; /* the instruction being assembled */
210
211 #define op(ex) ((ex)->exp.X_op)
212 #define adds(ex) ((ex)->exp.X_add_symbol)
213 #define subs(ex) ((ex)->exp.X_op_symbol)
214 #define offs(ex) ((ex)->exp.X_add_number)
215
216 /* Macros for adding things to the m68k_it struct */
217
218 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
219
220 /* Like addword, but goes BEFORE general operands */
221 static void
222 insop (w, opcode)
223 int w;
224 struct m68k_incant *opcode;
225 {
226 int z;
227 for(z=the_ins.numo;z>opcode->m_codenum;--z)
228 the_ins.opcode[z]=the_ins.opcode[z-1];
229 for(z=0;z<the_ins.nrel;z++)
230 the_ins.reloc[z].n+=2;
231 for (z = 0; z < the_ins.nfrag; z++)
232 the_ins.fragb[z].fragoff++;
233 the_ins.opcode[opcode->m_codenum]=w;
234 the_ins.numo++;
235 }
236
237 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
238 Blecch. */
239 static void
240 add_fix (width, exp, pc_rel, pc_fix)
241 char width;
242 struct m68k_exp *exp;
243 int pc_rel;
244 int pc_fix;
245 {
246 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
247 ? (the_ins.numo*2-1)
248 : (((width)=='b')
249 ? (the_ins.numo*2+1)
250 : (the_ins.numo*2)));
251 the_ins.reloc[the_ins.nrel].exp = exp->exp;
252 the_ins.reloc[the_ins.nrel].wid = width;
253 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
254 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
255 }
256
257 /* Cause an extra frag to be generated here, inserting up to 10 bytes
258 (that value is chosen in the frag_var call in md_assemble). TYPE
259 is the subtype of the frag to be generated; its primary type is
260 rs_machine_dependent.
261
262 The TYPE parameter is also used by md_convert_frag_1 and
263 md_estimate_size_before_relax. The appropriate type of fixup will
264 be emitted by md_convert_frag_1.
265
266 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
267 static void
268 add_frag(add,off,type)
269 symbolS *add;
270 long off;
271 int type;
272 {
273 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
274 the_ins.fragb[the_ins.nfrag].fadd=add;
275 the_ins.fragb[the_ins.nfrag].foff=off;
276 the_ins.fragb[the_ins.nfrag++].fragty=type;
277 }
278
279 #define isvar(ex) \
280 (op (ex) != O_constant && op (ex) != O_big)
281
282 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
283 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
284 static int reverse_16_bits PARAMS ((int in));
285 static int reverse_8_bits PARAMS ((int in));
286 static void install_gen_operand PARAMS ((int mode, int val));
287 static void install_operand PARAMS ((int mode, int val));
288 static void s_bss PARAMS ((int));
289 static void s_data1 PARAMS ((int));
290 static void s_data2 PARAMS ((int));
291 static void s_even PARAMS ((int));
292 static void s_proc PARAMS ((int));
293 static void mri_chip PARAMS ((void));
294 static void s_chip PARAMS ((int));
295 static void s_fopt PARAMS ((int));
296 static void s_opt PARAMS ((int));
297 static void s_reg PARAMS ((int));
298 static void s_restore PARAMS ((int));
299 static void s_save PARAMS ((int));
300
301 static int current_architecture;
302
303 struct m68k_cpu {
304 unsigned long arch;
305 const char *name;
306 };
307
308 static const struct m68k_cpu archs[] = {
309 { m68000, "68000" },
310 { m68010, "68010" },
311 { m68020, "68020" },
312 { m68030, "68030" },
313 { m68040, "68040" },
314 { m68060, "68060" },
315 { cpu32, "cpu32" },
316 { m68881, "68881" },
317 { m68851, "68851" },
318 /* Aliases (effectively, so far as gas is concerned) for the above
319 cpus. */
320 { m68020, "68k" },
321 { m68000, "68302" },
322 { m68000, "68008" },
323 { m68000, "68ec000" },
324 { m68000, "68hc000" },
325 { m68000, "68hc001" },
326 { m68020, "68ec020" },
327 { m68030, "68ec030" },
328 { m68040, "68ec040" },
329 { cpu32, "68330" },
330 { cpu32, "68331" },
331 { cpu32, "68332" },
332 { cpu32, "68333" },
333 { cpu32, "68340" },
334 { cpu32, "68360" },
335 { m68881, "68882" },
336 };
337
338 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
339
340 /* BCC68000 is for patching in an extra jmp instruction for long offsets
341 on the 68000. The 68000 doesn't support long branches with branchs */
342
343 /* This table desribes how you change sizes for the various types of variable
344 size expressions. This version only supports two kinds. */
345
346 /* Note that calls to frag_var need to specify the maximum expansion
347 needed; this is currently 10 bytes for DBCC. */
348
349 /* The fields are:
350 How far Forward this mode will reach:
351 How far Backward this mode will reach:
352 How many bytes this mode will add to the size of the frag
353 Which mode to go to if the offset won't fit in this one
354 */
355 relax_typeS md_relax_table[] =
356 {
357 {1, 1, 0, 0}, /* First entries aren't used */
358 {1, 1, 0, 0}, /* For no good reason except */
359 {1, 1, 0, 0}, /* that the VAX doesn't either */
360 {1, 1, 0, 0},
361
362 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
363 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
364 {0, 0, 4, 0},
365 {1, 1, 0, 0},
366
367 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
368 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
369 {0, 0, 4, 0},
370 {1, 1, 0, 0},
371
372 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
373 {(32767), (-32768), 2, TAB (PCREL, LONG)},
374 {0, 0, 4, 0},
375 {1, 1, 0, 0},
376
377 {(127), (-128), 0, TAB (BCC68000, SHORT)},
378 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
379 {0, 0, 6, 0}, /* jmp long space */
380 {1, 1, 0, 0},
381
382 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
383 {(32767), (-32768), 2, TAB (DBCC, LONG)},
384 {0, 0, 10, 0}, /* bra/jmp long space */
385 {1, 1, 0, 0},
386
387 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
388 {32767, -32768, 2, TAB (PCLEA, LONG)},
389 {0, 0, 6, 0},
390 {1, 1, 0, 0},
391
392 /* For, e.g., jmp pcrel indexed. */
393 {125, -130, 0, TAB (PCINDEX, SHORT)},
394 {32765, -32770, 2, TAB (PCINDEX, LONG)},
395 {0, 0, 4, 0},
396 {1, 1, 0, 0},
397 };
398
399 /* These are the machine dependent pseudo-ops. These are included so
400 the assembler can work on the output from the SUN C compiler, which
401 generates these.
402 */
403
404 /* This table describes all the machine specific pseudo-ops the assembler
405 has to support. The fields are:
406 pseudo-op name without dot
407 function to call to execute this pseudo-op
408 Integer arg to pass to the function
409 */
410 CONST pseudo_typeS md_pseudo_table[] =
411 {
412 {"data1", s_data1, 0},
413 {"data2", s_data2, 0},
414 {"bss", s_bss, 0},
415 {"even", s_even, 0},
416 {"skip", s_space, 0},
417 {"proc", s_proc, 0},
418 #ifdef TE_SUN3
419 {"align", s_align_bytes, 0},
420 #endif
421 #ifdef OBJ_ELF
422 {"swbeg", s_ignore, 0},
423 #endif
424
425 /* The following pseudo-ops are supported for MRI compatibility. */
426 {"chip", s_chip, 0},
427 {"comline", s_space, 1},
428 {"fopt", s_fopt, 0},
429 {"mask2", s_ignore, 0},
430 {"opt", s_opt, 0},
431 {"reg", s_reg, 0},
432 {"restore", s_restore, 0},
433 {"save", s_save, 0},
434
435 {0, 0, 0}
436 };
437
438
439 /* The mote pseudo ops are put into the opcode table, since they
440 don't start with a . they look like opcodes to gas.
441 */
442 extern void obj_coff_section ();
443
444 CONST pseudo_typeS mote_pseudo_table[] =
445 {
446
447 {"dcl", cons, 4},
448 {"dc", cons, 2},
449 {"dcw", cons, 2},
450 {"dcb", cons, 1},
451
452 {"dsl", s_space, 4},
453 {"ds", s_space, 2},
454 {"dsw", s_space, 2},
455 {"dsb", s_space, 1},
456
457 {"xdef", s_globl, 0},
458 {"align", s_align_ptwo, 0},
459 #ifdef M68KCOFF
460 {"sect", obj_coff_section, 0},
461 {"section", obj_coff_section, 0},
462 #endif
463 {0, 0, 0}
464 };
465
466 #define issbyte(x) ((x)>=-128 && (x)<=127)
467 #define isubyte(x) ((x)>=0 && (x)<=255)
468 #define issword(x) ((x)>=-32768 && (x)<=32767)
469 #define isuword(x) ((x)>=0 && (x)<=65535)
470
471 #define isbyte(x) ((x)>= -255 && (x)<=255)
472 #define isword(x) ((x)>=-32768 && (x)<=65535)
473 #define islong(x) (1)
474
475 extern char *input_line_pointer;
476
477 static char mklower_table[256];
478 #define mklower(c) (mklower_table[(unsigned char)(c)])
479 static char notend_table[256];
480 static char alt_notend_table[256];
481 #define notend(s) \
482 (! (notend_table[(unsigned char) *s] \
483 || (*s == ':' \
484 && alt_notend_table[(unsigned char) s[1]])))
485
486 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
487
488 #ifdef NO_PCREL_RELOCS
489
490 int
491 make_pcrel_absolute(fixP, add_number)
492 fixS *fixP;
493 long *add_number;
494 {
495 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
496
497 /* rewrite the PC relative instructions to absolute address ones.
498 * these are rumoured to be faster, and the apollo linker refuses
499 * to deal with the PC relative relocations.
500 */
501 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
502 {
503 opcode[0] = 0x4e;
504 opcode[1] = 0xf9;
505 }
506 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
507 {
508 opcode[0] = 0x4e;
509 opcode[1] = 0xb9;
510 }
511 else
512 as_fatal ("Unknown PC relative instruction");
513 *add_number -= 4;
514 return 0;
515 }
516
517 #endif /* NO_PCREL_RELOCS */
518
519 short
520 tc_coff_fix2rtype (fixP)
521 fixS *fixP;
522 {
523 #ifdef NO_PCREL_RELOCS
524 know (fixP->fx_pcrel == 0);
525 return (fixP->fx_size == 1 ? R_RELBYTE
526 : fixP->fx_size == 2 ? R_DIR16
527 : R_DIR32);
528 #else
529 return (fixP->fx_pcrel ?
530 (fixP->fx_size == 1 ? R_PCRBYTE :
531 fixP->fx_size == 2 ? R_PCRWORD :
532 R_PCRLONG) :
533 (fixP->fx_size == 1 ? R_RELBYTE :
534 fixP->fx_size == 2 ? R_RELWORD :
535 R_RELLONG));
536 #endif
537 }
538
539 #endif
540
541 #ifdef BFD_ASSEMBLER
542
543 arelent *
544 tc_gen_reloc (section, fixp)
545 asection *section;
546 fixS *fixp;
547 {
548 arelent *reloc;
549 bfd_reloc_code_real_type code;
550
551 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
552 switch (F (fixp->fx_size, fixp->fx_pcrel))
553 {
554 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
555 MAP (1, 0, BFD_RELOC_8);
556 MAP (2, 0, BFD_RELOC_16);
557 MAP (4, 0, BFD_RELOC_32);
558 MAP (1, 1, BFD_RELOC_8_PCREL);
559 MAP (2, 1, BFD_RELOC_16_PCREL);
560 MAP (4, 1, BFD_RELOC_32_PCREL);
561 default:
562 abort ();
563 }
564
565 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
566 assert (reloc != 0);
567 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
568 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
569 if (fixp->fx_pcrel)
570 reloc->addend = fixp->fx_addnumber;
571 else
572 reloc->addend = 0;
573
574 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
575 assert (reloc->howto != 0);
576
577 return reloc;
578 }
579
580 #endif /* BFD_ASSEMBLER */
581
582 /* Handle of the OPCODE hash table. NULL means any use before
583 m68k_ip_begin() will crash. */
584 static struct hash_control *op_hash;
585 \f
586 /* Assemble an m68k instruction. */
587
588 void
589 m68k_ip (instring)
590 char *instring;
591 {
592 register char *p;
593 register struct m68k_op *opP;
594 register struct m68k_incant *opcode;
595 register const char *s;
596 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
597 char *pdot, *pdotmove;
598 enum m68k_size siz1, siz2;
599 char c;
600 int losing;
601 int opsfound;
602 char *crack_operand ();
603 LITTLENUM_TYPE words[6];
604 LITTLENUM_TYPE *wordp;
605 unsigned long ok_arch = 0;
606
607 if (*instring == ' ')
608 instring++; /* skip leading whitespace */
609
610 /* Scan up to end of operation-code, which MUST end in end-of-string
611 or exactly 1 space. */
612 pdot = 0;
613 for (p = instring; *p != '\0'; p++)
614 {
615 if (*p == ' ')
616 break;
617 if (*p == '.')
618 pdot = p;
619 }
620
621 if (p == instring)
622 {
623 the_ins.error = "No operator";
624 return;
625 }
626
627 /* p now points to the end of the opcode name, probably whitespace.
628 Make sure the name is null terminated by clobbering the
629 whitespace, look it up in the hash table, then fix it back.
630 Remove a dot, first, since the opcode tables have none. */
631 if (pdot != NULL)
632 {
633 for (pdotmove = pdot; pdotmove < p; pdotmove++)
634 *pdotmove = pdotmove[1];
635 p--;
636 }
637
638 c = *p;
639 *p = '\0';
640 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
641 *p = c;
642
643 if (pdot != NULL)
644 {
645 for (pdotmove = p; pdotmove > pdot; pdotmove--)
646 *pdotmove = pdotmove[-1];
647 *pdot = '.';
648 ++p;
649 }
650
651 if (opcode == NULL)
652 {
653 the_ins.error = "Unknown operator";
654 return;
655 }
656
657 /* found a legitimate opcode, start matching operands */
658 while (*p == ' ')
659 ++p;
660
661 if (opcode->m_operands == 0)
662 {
663 char *old = input_line_pointer;
664 *old = '\n';
665 input_line_pointer = p;
666 /* Ahh - it's a motorola style psuedo op */
667 mote_pseudo_table[opcode->m_opnum].poc_handler
668 (mote_pseudo_table[opcode->m_opnum].poc_val);
669 input_line_pointer = old;
670 *old = 0;
671
672 return;
673 }
674
675 for (opP = &the_ins.operands[0]; *p; opP++)
676 {
677 p = crack_operand (p, opP);
678
679 if (opP->error)
680 {
681 the_ins.error = opP->error;
682 return;
683 }
684 }
685
686 opsfound = opP - &the_ins.operands[0];
687
688 /* This ugly hack is to support the floating pt opcodes in their
689 standard form. Essentially, we fake a first enty of type COP#1 */
690 if (opcode->m_operands[0] == 'I')
691 {
692 int n;
693
694 for (n = opsfound; n > 0; --n)
695 the_ins.operands[n] = the_ins.operands[n - 1];
696
697 memset ((char *) (&the_ins.operands[0]), '\0',
698 sizeof (the_ins.operands[0]));
699 the_ins.operands[0].mode = CONTROL;
700 the_ins.operands[0].reg = m68k_float_copnum;
701 opsfound++;
702 }
703
704 /* We've got the operands. Find an opcode that'll accept them */
705 for (losing = 0;;)
706 {
707 /* If we didn't get the right number of ops, or we have no
708 common model with this pattern then reject this pattern. */
709
710 if (opsfound != opcode->m_opnum
711 || ((opcode->m_arch & current_architecture) == 0))
712 {
713 ++losing;
714 ok_arch |= opcode->m_arch;
715 }
716 else
717 {
718 for (s = opcode->m_operands, opP = &the_ins.operands[0];
719 *s && !losing;
720 s += 2, opP++)
721 {
722 /* Warning: this switch is huge! */
723 /* I've tried to organize the cases into this order:
724 non-alpha first, then alpha by letter. Lower-case
725 goes directly before uppercase counterpart. */
726 /* Code with multiple case ...: gets sorted by the lowest
727 case ... it belongs to. I hope this makes sense. */
728 switch (*s)
729 {
730 case '!':
731 switch (opP->mode)
732 {
733 case IMMED:
734 case DREG:
735 case AREG:
736 case FPREG:
737 case CONTROL:
738 case AINC:
739 case ADEC:
740 case REGLST:
741 losing++;
742 break;
743 default:
744 break;
745 }
746 break;
747
748 case '`':
749 switch (opP->mode)
750 {
751 case IMMED:
752 case DREG:
753 case AREG:
754 case FPREG:
755 case CONTROL:
756 case AINC:
757 case REGLST:
758 case AINDR:
759 losing++;
760 break;
761 default:
762 break;
763 }
764 break;
765
766 case '#':
767 if (opP->mode != IMMED)
768 losing++;
769 else if (s[1] == 'b'
770 && ! isvar (&opP->disp)
771 && (opP->disp.exp.X_op != O_constant
772 || ! isbyte (opP->disp.exp.X_add_number)))
773 losing++;
774 else if (s[1] == 'w'
775 && ! isvar (&opP->disp)
776 && (opP->disp.exp.X_op != O_constant
777 || ! isword (opP->disp.exp.X_add_number)))
778 losing++;
779 break;
780
781 case '^':
782 case 'T':
783 if (opP->mode != IMMED)
784 losing++;
785 break;
786
787 case '$':
788 if (opP->mode == AREG
789 || opP->mode == CONTROL
790 || opP->mode == FPREG
791 || opP->mode == IMMED
792 || opP->mode == REGLST
793 || (opP->mode != ABSL
794 && (opP->reg == PC
795 || opP->reg == ZPC)))
796 losing++;
797 break;
798
799 case '%':
800 if (opP->mode == CONTROL
801 || opP->mode == FPREG
802 || opP->mode == REGLST
803 || (opP->mode != ABSL
804 && opP->mode != IMMED
805 && (opP->reg == PC
806 || opP->reg == ZPC)))
807 losing++;
808 break;
809
810 case '&':
811 switch (opP->mode)
812 {
813 case DREG:
814 case AREG:
815 case FPREG:
816 case CONTROL:
817 case IMMED:
818 case AINC:
819 case ADEC:
820 case REGLST:
821 losing++;
822 break;
823 case ABSL:
824 break;
825 default:
826 if (opP->reg == PC
827 || opP->reg == ZPC)
828 losing++;
829 break;
830 }
831 break;
832
833 case '*':
834 if (opP->mode == CONTROL
835 || opP->mode == FPREG
836 || opP->mode == REGLST)
837 losing++;
838 break;
839
840 case '+':
841 if (opP->mode != AINC)
842 losing++;
843 break;
844
845 case '-':
846 if (opP->mode != ADEC)
847 losing++;
848 break;
849
850 case '/':
851 switch (opP->mode)
852 {
853 case AREG:
854 case CONTROL:
855 case FPREG:
856 case AINC:
857 case ADEC:
858 case IMMED:
859 case REGLST:
860 losing++;
861 break;
862 default:
863 break;
864 }
865 break;
866
867 case ';':
868 switch (opP->mode)
869 {
870 case AREG:
871 case CONTROL:
872 case FPREG:
873 case REGLST:
874 losing++;
875 break;
876 default:
877 break;
878 }
879 break;
880
881 case '?':
882 switch (opP->mode)
883 {
884 case AREG:
885 case CONTROL:
886 case FPREG:
887 case AINC:
888 case ADEC:
889 case IMMED:
890 case REGLST:
891 losing++;
892 break;
893 case ABSL:
894 break;
895 default:
896 if (opP->reg == PC || opP->reg == ZPC)
897 losing++;
898 break;
899 }
900 break;
901
902 case '@':
903 switch (opP->mode)
904 {
905 case AREG:
906 case CONTROL:
907 case FPREG:
908 case IMMED:
909 case REGLST:
910 losing++;
911 break;
912 default:
913 break;
914 }
915 break;
916
917 case '~': /* For now! (JF FOO is this right?) */
918 switch (opP->mode)
919 {
920 case DREG:
921 case AREG:
922 case CONTROL:
923 case FPREG:
924 case IMMED:
925 case REGLST:
926 losing++;
927 break;
928 case ABSL:
929 break;
930 default:
931 if (opP->reg == PC
932 || opP->reg == ZPC)
933 losing++;
934 break;
935 }
936 break;
937
938 case '3':
939 if (opP->mode != CONTROL
940 || (opP->reg != TT0 && opP->reg != TT1))
941 losing++;
942 break;
943
944 case 'A':
945 if (opP->mode != AREG)
946 losing++;
947 break;
948
949 case 'a':
950 if (opP->mode != AINDR)
951 ++losing;
952 break;
953
954 case 'B': /* FOO */
955 if (opP->mode != ABSL
956 || (flag_long_jumps
957 && strncmp (instring, "jbsr", 4) == 0))
958 losing++;
959 break;
960
961 case 'C':
962 if (opP->mode != CONTROL || opP->reg != CCR)
963 losing++;
964 break;
965
966 case 'd':
967 if (opP->mode != DISP
968 || opP->reg < ADDR0
969 || opP->reg > ADDR7)
970 losing++;
971 break;
972
973 case 'D':
974 if (opP->mode != DREG)
975 losing++;
976 break;
977
978 case 'F':
979 if (opP->mode != FPREG)
980 losing++;
981 break;
982
983 case 'I':
984 if (opP->mode != CONTROL
985 || opP->reg < COP0
986 || opP->reg > COP7)
987 losing++;
988 break;
989
990 case 'J':
991 if (opP->mode != CONTROL
992 || opP->reg < USP
993 || opP->reg > last_movec_reg)
994 losing++;
995 else
996 {
997 const enum m68k_register *rp;
998 for (rp = control_regs; *rp; rp++)
999 if (*rp == opP->reg)
1000 break;
1001 if (*rp == 0)
1002 losing++;
1003 }
1004 break;
1005
1006 case 'k':
1007 if (opP->mode != IMMED)
1008 losing++;
1009 break;
1010
1011 case 'l':
1012 case 'L':
1013 if (opP->mode == DREG
1014 || opP->mode == AREG
1015 || opP->mode == FPREG)
1016 {
1017 if (s[1] == '8')
1018 losing++;
1019 else
1020 {
1021 switch (opP->mode)
1022 {
1023 case DREG:
1024 opP->mask = 1 << (opP->reg - DATA0);
1025 break;
1026 case AREG:
1027 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1028 break;
1029 case FPREG:
1030 opP->mask = 1 << (opP->reg - FP0 + 16);
1031 break;
1032 default:
1033 abort ();
1034 }
1035 opP->mode = REGLST;
1036 }
1037 }
1038 else if (opP->mode == CONTROL)
1039 {
1040 if (s[1] != '8')
1041 losing++;
1042 else
1043 {
1044 switch (opP->reg)
1045 {
1046 case FPI:
1047 opP->mask = 1 << 24;
1048 break;
1049 case FPS:
1050 opP->mask = 1 << 25;
1051 break;
1052 case FPC:
1053 opP->mask = 1 << 26;
1054 break;
1055 default:
1056 losing++;
1057 break;
1058 }
1059 opP->mode = REGLST;
1060 }
1061 }
1062 else if (opP->mode == ABSL
1063 && opP->disp.size == SIZE_UNSPEC
1064 && opP->disp.exp.X_op == O_constant)
1065 {
1066 /* This is what the MRI REG pseudo-op generates. */
1067 opP->mode = REGLST;
1068 opP->mask = opP->disp.exp.X_add_number;
1069 }
1070 else if (opP->mode != REGLST)
1071 losing++;
1072 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1073 losing++;
1074 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1075 losing++;
1076 break;
1077
1078 case 'M':
1079 if (opP->mode != IMMED)
1080 losing++;
1081 else if (opP->disp.exp.X_op != O_constant
1082 || ! issbyte (opP->disp.exp.X_add_number))
1083 losing++;
1084 else if (! m68k_quick
1085 && instring[3] != 'q'
1086 && instring[4] != 'q')
1087 losing++;
1088 break;
1089
1090 case 'O':
1091 if (opP->mode != DREG && opP->mode != IMMED)
1092 losing++;
1093 break;
1094
1095 case 'Q':
1096 if (opP->mode != IMMED)
1097 losing++;
1098 else if (opP->disp.exp.X_op != O_constant
1099 || opP->disp.exp.X_add_number < 1
1100 || opP->disp.exp.X_add_number > 8)
1101 losing++;
1102 else if (! m68k_quick
1103 && (strncmp (instring, "add", 3) == 0
1104 || strncmp (instring, "sub", 3) == 0)
1105 && instring[3] != 'q')
1106 losing++;
1107 break;
1108
1109 case 'R':
1110 if (opP->mode != DREG && opP->mode != AREG)
1111 losing++;
1112 break;
1113
1114 case 'r':
1115 if (opP->mode != AINDR
1116 && (opP->mode != BASE
1117 || (opP->reg != 0
1118 && opP->reg != ZADDR0)
1119 || opP->disp.exp.X_op != O_absent
1120 || ((opP->index.reg < DATA0
1121 || opP->index.reg > DATA7)
1122 && (opP->index.reg < ADDR0
1123 || opP->index.reg > ADDR7))
1124 || opP->index.size != SIZE_UNSPEC
1125 || opP->index.scale != 1))
1126 losing++;
1127 break;
1128
1129 case 's':
1130 if (opP->mode != CONTROL
1131 || ! (opP->reg == FPI
1132 || opP->reg == FPS
1133 || opP->reg == FPC))
1134 losing++;
1135 break;
1136
1137 case 'S':
1138 if (opP->mode != CONTROL || opP->reg != SR)
1139 losing++;
1140 break;
1141
1142 case 't':
1143 if (opP->mode != IMMED)
1144 losing++;
1145 else if (opP->disp.exp.X_op != O_constant
1146 || opP->disp.exp.X_add_number < 0
1147 || opP->disp.exp.X_add_number > 7)
1148 losing++;
1149 break;
1150
1151 case 'U':
1152 if (opP->mode != CONTROL || opP->reg != USP)
1153 losing++;
1154 break;
1155
1156 /* JF these are out of order. We could put them
1157 in order if we were willing to put up with
1158 bunches of #ifdef m68851s in the code.
1159
1160 Don't forget that you need these operands
1161 to use 68030 MMU instructions. */
1162 #ifndef NO_68851
1163 /* Memory addressing mode used by pflushr */
1164 case '|':
1165 if (opP->mode == CONTROL
1166 || opP->mode == FPREG
1167 || opP->mode == DREG
1168 || opP->mode == AREG
1169 || opP->mode == REGLST)
1170 losing++;
1171 break;
1172
1173 case 'f':
1174 if (opP->mode != CONTROL
1175 || (opP->reg != SFC && opP->reg != DFC))
1176 losing++;
1177 break;
1178
1179 case 'P':
1180 if (opP->mode != CONTROL
1181 || (opP->reg != TC
1182 && opP->reg != CAL
1183 && opP->reg != VAL
1184 && opP->reg != SCC
1185 && opP->reg != AC))
1186 losing++;
1187 break;
1188
1189 case 'V':
1190 if (opP->mode != CONTROL
1191 || opP->reg != VAL)
1192 losing++;
1193 break;
1194
1195 case 'W':
1196 if (opP->mode != CONTROL
1197 || (opP->reg != DRP
1198 && opP->reg != SRP
1199 && opP->reg != CRP))
1200 losing++;
1201 break;
1202
1203 case 'X':
1204 if (opP->mode != CONTROL
1205 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1206 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1207 losing++;
1208 break;
1209
1210 case 'Y':
1211 if (opP->mode != CONTROL || opP->reg != PSR)
1212 losing++;
1213 break;
1214
1215 case 'Z':
1216 if (opP->mode != CONTROL || opP->reg != PCSR)
1217 losing++;
1218 break;
1219 #endif
1220 case 'c':
1221 if (opP->mode != CONTROL
1222 || (opP->reg != NC
1223 && opP->reg != IC
1224 && opP->reg != DC
1225 && opP->reg != BC))
1226 {
1227 losing++;
1228 } /* not a cache specifier. */
1229 break;
1230
1231 case '_':
1232 if (opP->mode != ABSL)
1233 ++losing;
1234 break;
1235
1236 default:
1237 abort ();
1238 } /* switch on type of operand */
1239
1240 if (losing)
1241 break;
1242 } /* for each operand */
1243 } /* if immediately wrong */
1244
1245 if (!losing)
1246 {
1247 break;
1248 } /* got it. */
1249
1250 opcode = opcode->m_next;
1251
1252 if (!opcode)
1253 {
1254 if (ok_arch
1255 && !(ok_arch & current_architecture))
1256 {
1257 char buf[200], *cp;
1258 int len;
1259 strcpy (buf,
1260 "invalid instruction for this architecture; needs ");
1261 cp = buf + strlen (buf);
1262 switch (ok_arch)
1263 {
1264 case mfloat:
1265 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1266 break;
1267 case mmmu:
1268 strcpy (cp, "mmu (68030 or 68851)");
1269 break;
1270 case m68020up:
1271 strcpy (cp, "68020 or higher");
1272 break;
1273 case m68000up:
1274 strcpy (cp, "68000 or higher");
1275 break;
1276 case m68010up:
1277 strcpy (cp, "68010 or higher");
1278 break;
1279 default:
1280 {
1281 int got_one = 0, idx;
1282 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1283 idx++)
1284 {
1285 if (archs[idx].arch & ok_arch)
1286 {
1287 if (got_one)
1288 {
1289 strcpy (cp, " or ");
1290 cp += strlen (cp);
1291 }
1292 got_one = 1;
1293 strcpy (cp, archs[idx].name);
1294 cp += strlen (cp);
1295 }
1296 }
1297 }
1298 }
1299 len = cp - buf + 1;
1300 cp = malloc (len);
1301 strcpy (cp, buf);
1302 the_ins.error = cp;
1303 }
1304 else
1305 the_ins.error = "operands mismatch";
1306 return;
1307 } /* Fell off the end */
1308
1309 losing = 0;
1310 }
1311
1312 /* now assemble it */
1313
1314 the_ins.args = opcode->m_operands;
1315 the_ins.numargs = opcode->m_opnum;
1316 the_ins.numo = opcode->m_codenum;
1317 the_ins.opcode[0] = getone (opcode);
1318 the_ins.opcode[1] = gettwo (opcode);
1319
1320 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1321 {
1322 /* This switch is a doozy.
1323 Watch the first step; its a big one! */
1324 switch (s[0])
1325 {
1326
1327 case '*':
1328 case '~':
1329 case '%':
1330 case ';':
1331 case '@':
1332 case '!':
1333 case '&':
1334 case '$':
1335 case '?':
1336 case '/':
1337 case '`':
1338 #ifndef NO_68851
1339 case '|':
1340 #endif
1341 switch (opP->mode)
1342 {
1343 case IMMED:
1344 tmpreg = 0x3c; /* 7.4 */
1345 if (strchr ("bwl", s[1]))
1346 nextword = get_num (&opP->disp, 80);
1347 else
1348 nextword = get_num (&opP->disp, 0);
1349 if (isvar (&opP->disp))
1350 add_fix (s[1], &opP->disp, 0, 0);
1351 switch (s[1])
1352 {
1353 case 'b':
1354 if (!isbyte (nextword))
1355 opP->error = "operand out of range";
1356 addword (nextword);
1357 baseo = 0;
1358 break;
1359 case 'w':
1360 if (!isword (nextword))
1361 opP->error = "operand out of range";
1362 addword (nextword);
1363 baseo = 0;
1364 break;
1365 case 'l':
1366 addword (nextword >> 16);
1367 addword (nextword);
1368 baseo = 0;
1369 break;
1370
1371 case 'f':
1372 baseo = 2;
1373 outro = 8;
1374 break;
1375 case 'F':
1376 baseo = 4;
1377 outro = 11;
1378 break;
1379 case 'x':
1380 baseo = 6;
1381 outro = 15;
1382 break;
1383 case 'p':
1384 baseo = 6;
1385 outro = -1;
1386 break;
1387 default:
1388 abort ();
1389 }
1390 if (!baseo)
1391 break;
1392
1393 /* We gotta put out some float */
1394 if (op (&opP->disp) != O_big)
1395 {
1396 valueT val;
1397 int gencnt;
1398
1399 /* Can other cases happen here? */
1400 if (op (&opP->disp) != O_constant)
1401 abort ();
1402
1403 val = (valueT) offs (&opP->disp);
1404 gencnt = 0;
1405 do
1406 {
1407 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1408 val >>= LITTLENUM_NUMBER_OF_BITS;
1409 ++gencnt;
1410 }
1411 while (val != 0);
1412 offs (&opP->disp) = gencnt;
1413 }
1414 if (offs (&opP->disp) > 0)
1415 {
1416 if (offs (&opP->disp) > baseo)
1417 {
1418 as_warn ("Bignum too big for %c format; truncated",
1419 s[1]);
1420 offs (&opP->disp) = baseo;
1421 }
1422 baseo -= offs (&opP->disp);
1423 while (baseo--)
1424 addword (0);
1425 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1426 offs (&opP->disp)--;
1427 --wordp)
1428 addword (*wordp);
1429 break;
1430 }
1431 gen_to_words (words, baseo, (long) outro);
1432 for (wordp = words; baseo--; wordp++)
1433 addword (*wordp);
1434 break;
1435 case DREG:
1436 tmpreg = opP->reg - DATA; /* 0.dreg */
1437 break;
1438 case AREG:
1439 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1440 break;
1441 case AINDR:
1442 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1443 break;
1444 case ADEC:
1445 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1446 break;
1447 case AINC:
1448 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1449 break;
1450 case DISP:
1451
1452 nextword = get_num (&opP->disp, 80);
1453
1454 if (opP->reg == PC
1455 && ! isvar (&opP->disp)
1456 && m68k_abspcadd)
1457 {
1458 opP->disp.exp.X_op = O_symbol;
1459 #ifndef BFD_ASSEMBLER
1460 opP->disp.exp.X_add_symbol = &abs_symbol;
1461 #else
1462 opP->disp.exp.X_add_symbol =
1463 section_symbol (absolute_section);
1464 #endif
1465 }
1466
1467 /* Force into index mode. Hope this works */
1468
1469 /* We do the first bit for 32-bit displacements, and the
1470 second bit for 16 bit ones. It is possible that we
1471 should make the default be WORD instead of LONG, but
1472 I think that'd break GCC, so we put up with a little
1473 inefficiency for the sake of working output. */
1474
1475 if (!issword (nextword)
1476 || (isvar (&opP->disp)
1477 && ((opP->disp.size == SIZE_UNSPEC
1478 && flag_short_refs == 0
1479 && cpu_of_arch (current_architecture) >= m68020)
1480 || opP->disp.size == SIZE_LONG)))
1481 {
1482 if (opP->reg == PC)
1483 tmpreg = 0x3B; /* 7.3 */
1484 else
1485 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1486 if (isvar (&opP->disp))
1487 {
1488 if (opP->reg == PC)
1489 {
1490 #if 0
1491 addword (0x0170);
1492 add_fix ('l', &opP->disp, 1, 2);
1493 addword (0), addword (0);
1494 #else
1495 add_frag (adds (&opP->disp),
1496 offs (&opP->disp),
1497 TAB (PCLEA, SZ_UNDEF));
1498 #endif
1499 break;
1500 }
1501 else
1502 {
1503 addword (0x0170);
1504 add_fix ('l', &opP->disp, 0, 0);
1505 }
1506 }
1507 else
1508 addword (0x0170);
1509 addword (nextword >> 16);
1510 }
1511 else
1512 {
1513 if (opP->reg == PC)
1514 tmpreg = 0x3A; /* 7.2 */
1515 else
1516 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1517
1518 if (isvar (&opP->disp))
1519 {
1520 if (opP->reg == PC)
1521 {
1522 add_fix ('w', &opP->disp, 1, 0);
1523 }
1524 else
1525 add_fix ('w', &opP->disp, 0, 0);
1526 }
1527 }
1528 addword (nextword);
1529 break;
1530
1531 case POST:
1532 case PRE:
1533 case BASE:
1534 nextword = 0;
1535 baseo = get_num (&opP->disp, 80);
1536 if (opP->mode == POST || opP->mode == PRE)
1537 outro = get_num (&opP->odisp, 80);
1538 /* Figure out the `addressing mode'.
1539 Also turn on the BASE_DISABLE bit, if needed. */
1540 if (opP->reg == PC || opP->reg == ZPC)
1541 {
1542 tmpreg = 0x3b; /* 7.3 */
1543 if (opP->reg == ZPC)
1544 nextword |= 0x80;
1545 }
1546 else if (opP->reg == 0)
1547 {
1548 nextword |= 0x80;
1549 tmpreg = 0x30; /* 6.garbage */
1550 }
1551 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1552 {
1553 nextword |= 0x80;
1554 tmpreg = 0x30 + opP->reg - ZADDR0;
1555 }
1556 else
1557 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1558
1559 siz1 = opP->disp.size;
1560 if (opP->mode == POST || opP->mode == PRE)
1561 siz2 = opP->odisp.size;
1562 else
1563 siz2 = SIZE_UNSPEC;
1564
1565 /* Index register stuff */
1566 if (opP->index.reg != 0
1567 && opP->index.reg >= DATA
1568 && opP->index.reg <= ADDR7)
1569 {
1570 nextword |= (opP->index.reg - DATA) << 12;
1571
1572 if (opP->index.size == SIZE_UNSPEC
1573 || opP->index.size == SIZE_LONG)
1574 nextword |= 0x800;
1575
1576 if (cpu_of_arch (current_architecture) < m68020)
1577 {
1578 if (opP->index.scale != 1)
1579 {
1580 opP->error =
1581 "scale factor invalid on this architecture; needs 68020 or higher";
1582 }
1583 }
1584
1585 switch (opP->index.scale)
1586 {
1587 case 1:
1588 break;
1589 case 2:
1590 nextword |= 0x200;
1591 break;
1592 case 4:
1593 nextword |= 0x400;
1594 break;
1595 case 8:
1596 nextword |= 0x600;
1597 break;
1598 default:
1599 abort ();
1600 }
1601 /* IF its simple,
1602 GET US OUT OF HERE! */
1603
1604 /* Must be INDEX, with an index register. Address
1605 register cannot be ZERO-PC, and either :b was
1606 forced, or we know it will fit. For a 68000 or
1607 68010, force this mode anyways, because the
1608 larger modes aren't supported. */
1609 if (opP->mode == BASE
1610 && ((opP->reg >= ADDR0
1611 && opP->reg <= ADDR7)
1612 || opP->reg == PC))
1613 {
1614 if (siz1 == SIZE_BYTE
1615 || cpu_of_arch (current_architecture) < m68020
1616 || (siz1 == SIZE_UNSPEC
1617 && ! isvar (&opP->disp)
1618 && issbyte (baseo)))
1619 {
1620 nextword += baseo & 0xff;
1621 addword (nextword);
1622 if (isvar (&opP->disp))
1623 {
1624 /* Do a byte relocation. If it doesn't
1625 fit (possible on m68000) let the
1626 fixup processing complain later. */
1627 if (opP->reg == PC)
1628 add_fix ('B', &opP->disp, 1, 1);
1629 else
1630 add_fix ('B', &opP->disp, 0, 0);
1631 }
1632 else if (siz1 != SIZE_BYTE)
1633 {
1634 if (siz1 != SIZE_UNSPEC)
1635 as_warn ("Forcing byte displacement");
1636 if (! issbyte (baseo))
1637 opP->error = "byte displacement out of range";
1638 }
1639
1640 break;
1641 }
1642 else if (siz1 == SIZE_UNSPEC
1643 && opP->reg == PC
1644 && isvar (&opP->disp)
1645 && subs (&opP->disp) == NULL)
1646 {
1647 nextword += baseo & 0xff;
1648 addword (nextword);
1649 add_frag (adds (&opP->disp), offs (&opP->disp),
1650 TAB (PCINDEX, SZ_UNDEF));
1651
1652 break;
1653 }
1654 }
1655 }
1656 else
1657 {
1658 nextword |= 0x40; /* No index reg */
1659 if (opP->index.reg >= ZDATA0
1660 && opP->index.reg <= ZDATA7)
1661 nextword |= (opP->index.reg - ZDATA0) << 12;
1662 else if (opP->index.reg >= ZADDR0
1663 || opP->index.reg <= ZADDR7)
1664 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1665 }
1666
1667 /* It isn't simple. */
1668
1669 if (cpu_of_arch (current_architecture) < m68020)
1670 opP->error =
1671 "invalid operand mode for this architecture; needs 68020 or higher";
1672
1673 nextword |= 0x100;
1674 /* If the guy specified a width, we assume that it is
1675 wide enough. Maybe it isn't. If so, we lose. */
1676 switch (siz1)
1677 {
1678 case SIZE_UNSPEC:
1679 if (isvar (&opP->disp)
1680 ? m68k_rel32
1681 : ! issword (baseo))
1682 {
1683 siz1 = SIZE_LONG;
1684 nextword |= 0x30;
1685 }
1686 else if (! isvar (&opP->disp) && baseo == 0)
1687 nextword |= 0x10;
1688 else
1689 {
1690 nextword |= 0x20;
1691 siz1 = SIZE_WORD;
1692 }
1693 break;
1694 case SIZE_BYTE:
1695 as_warn (":b not permitted; defaulting to :w");
1696 /* Fall through. */
1697 case SIZE_WORD:
1698 nextword |= 0x20;
1699 break;
1700 case SIZE_LONG:
1701 nextword |= 0x30;
1702 break;
1703 }
1704
1705 /* Figure out innner displacement stuff */
1706 if (opP->mode == POST || opP->mode == PRE)
1707 {
1708 switch (siz2)
1709 {
1710 case SIZE_UNSPEC:
1711 if (isvar (&opP->odisp)
1712 ? m68k_rel32
1713 : ! issword (outro))
1714 {
1715 siz2 = SIZE_LONG;
1716 nextword |= 0x3;
1717 }
1718 else if (! isvar (&opP->disp) && outro == 0)
1719 nextword |= 0x1;
1720 else
1721 {
1722 nextword |= 0x2;
1723 siz2 = SIZE_WORD;
1724 }
1725 break;
1726 case 1:
1727 as_warn (":b not permitted; defaulting to :w");
1728 /* Fall through. */
1729 case 2:
1730 nextword |= 0x2;
1731 break;
1732 case 3:
1733 nextword |= 0x3;
1734 break;
1735 }
1736 if (opP->mode == POST)
1737 nextword |= 0x04;
1738 }
1739 addword (nextword);
1740
1741 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1742 {
1743 if (opP->reg == PC || opP->reg == ZPC)
1744 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1745 else
1746 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1747 }
1748 if (siz1 == SIZE_LONG)
1749 addword (baseo >> 16);
1750 if (siz1 != SIZE_UNSPEC)
1751 addword (baseo);
1752
1753 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1754 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1755 if (siz2 == SIZE_LONG)
1756 addword (outro >> 16);
1757 if (siz2 != SIZE_UNSPEC)
1758 addword (outro);
1759
1760 break;
1761
1762 case ABSL:
1763 nextword = get_num (&opP->disp, 80);
1764 switch (opP->disp.size)
1765 {
1766 default:
1767 abort ();
1768 case SIZE_UNSPEC:
1769 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1770 {
1771 tmpreg = 0x38; /* 7.0 */
1772 addword (nextword);
1773 break;
1774 }
1775 /* Don't generate pc relative code on 68010 and
1776 68000. */
1777 if (isvar (&opP->disp)
1778 && !subs (&opP->disp)
1779 && adds (&opP->disp)
1780 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
1781 && now_seg == text_section
1782 && cpu_of_arch (current_architecture) >= m68020
1783 && !flag_long_jumps
1784 && !strchr ("~%&$?", s[0]))
1785 {
1786 tmpreg = 0x3A; /* 7.2 */
1787 add_frag (adds (&opP->disp),
1788 offs (&opP->disp),
1789 TAB (PCREL, SZ_UNDEF));
1790 break;
1791 }
1792 /* Fall through into long */
1793 case SIZE_LONG:
1794 if (isvar (&opP->disp))
1795 add_fix ('l', &opP->disp, 0, 0);
1796
1797 tmpreg = 0x39;/* 7.1 mode */
1798 addword (nextword >> 16);
1799 addword (nextword);
1800 break;
1801
1802 case SIZE_WORD: /* Word */
1803 if (isvar (&opP->disp))
1804 add_fix ('w', &opP->disp, 0, 0);
1805
1806 tmpreg = 0x38;/* 7.0 mode */
1807 addword (nextword);
1808 break;
1809 }
1810 break;
1811 case CONTROL:
1812 case FPREG:
1813 default:
1814 as_bad ("unknown/incorrect operand");
1815 /* abort(); */
1816 }
1817 install_gen_operand (s[1], tmpreg);
1818 break;
1819
1820 case '#':
1821 case '^':
1822 switch (s[1])
1823 { /* JF: I hate floating point! */
1824 case 'j':
1825 tmpreg = 70;
1826 break;
1827 case '8':
1828 tmpreg = 20;
1829 break;
1830 case 'C':
1831 tmpreg = 50;
1832 break;
1833 case '3':
1834 default:
1835 tmpreg = 80;
1836 break;
1837 }
1838 tmpreg = get_num (&opP->disp, tmpreg);
1839 if (isvar (&opP->disp))
1840 add_fix (s[1], &opP->disp, 0, 0);
1841 switch (s[1])
1842 {
1843 case 'b': /* Danger: These do no check for
1844 certain types of overflow.
1845 user beware! */
1846 if (!isbyte (tmpreg))
1847 opP->error = "out of range";
1848 insop (tmpreg, opcode);
1849 if (isvar (&opP->disp))
1850 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1851 break;
1852 case 'w':
1853 if (!isword (tmpreg))
1854 opP->error = "out of range";
1855 insop (tmpreg, opcode);
1856 if (isvar (&opP->disp))
1857 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1858 break;
1859 case 'l':
1860 /* Because of the way insop works, we put these two out
1861 backwards. */
1862 insop (tmpreg, opcode);
1863 insop (tmpreg >> 16, opcode);
1864 if (isvar (&opP->disp))
1865 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1866 break;
1867 case '3':
1868 tmpreg &= 0xFF;
1869 case '8':
1870 case 'C':
1871 install_operand (s[1], tmpreg);
1872 break;
1873 default:
1874 abort ();
1875 }
1876 break;
1877
1878 case '+':
1879 case '-':
1880 case 'A':
1881 case 'a':
1882 install_operand (s[1], opP->reg - ADDR);
1883 break;
1884
1885 case 'B':
1886 tmpreg = get_num (&opP->disp, 80);
1887 switch (s[1])
1888 {
1889 case 'B':
1890 add_fix ('B', &opP->disp, 1, -1);
1891 break;
1892 case 'W':
1893 add_fix ('w', &opP->disp, 1, 0);
1894 addword (0);
1895 break;
1896 case 'L':
1897 long_branch:
1898 if (cpu_of_arch (current_architecture) < m68020)
1899 as_warn ("Can't use long branches on 68000/68010");
1900 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1901 add_fix ('l', &opP->disp, 1, 0);
1902 addword (0);
1903 addword (0);
1904 break;
1905 case 'g':
1906 if (subs (&opP->disp)) /* We can't relax it */
1907 goto long_branch;
1908
1909 /* This could either be a symbol, or an absolute
1910 address. No matter, the frag hacking will finger it
1911 out. Not quite: it can't switch from BRANCH to
1912 BCC68000 for the case where opnd is absolute (it
1913 needs to use the 68000 hack since no conditional abs
1914 jumps). */
1915 if (((cpu_of_arch (current_architecture) < m68020)
1916 || (0 == adds (&opP->disp)))
1917 && (the_ins.opcode[0] >= 0x6200)
1918 && (the_ins.opcode[0] <= 0x6f00))
1919 add_frag (adds (&opP->disp), offs (&opP->disp),
1920 TAB (BCC68000, SZ_UNDEF));
1921 else
1922 add_frag (adds (&opP->disp), offs (&opP->disp),
1923 TAB (ABRANCH, SZ_UNDEF));
1924 break;
1925 case 'w':
1926 if (isvar (&opP->disp))
1927 {
1928 #if 1
1929 /* check for DBcc instruction */
1930 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1931 {
1932 /* size varies if patch */
1933 /* needed for long form */
1934 add_frag (adds (&opP->disp), offs (&opP->disp),
1935 TAB (DBCC, SZ_UNDEF));
1936 break;
1937 }
1938 #endif
1939 add_fix ('w', &opP->disp, 1, 0);
1940 }
1941 addword (0);
1942 break;
1943 case 'C': /* Fixed size LONG coproc branches */
1944 add_fix ('l', &opP->disp, 1, 0);
1945 addword (0);
1946 addword (0);
1947 break;
1948 case 'c': /* Var size Coprocesssor branches */
1949 if (subs (&opP->disp))
1950 {
1951 add_fix ('l', &opP->disp, 1, 0);
1952 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1953 }
1954 else if (adds (&opP->disp))
1955 add_frag (adds (&opP->disp), offs (&opP->disp),
1956 TAB (FBRANCH, SZ_UNDEF));
1957 else
1958 {
1959 /* add_frag((symbolS *) 0, offs(&opP->disp),
1960 TAB(FBRANCH,SHORT)); */
1961 the_ins.opcode[the_ins.numo - 1] |= 0x40;
1962 add_fix ('l', &opP->disp, 1, 0);
1963 addword (0);
1964 addword (0);
1965 }
1966 break;
1967 default:
1968 abort ();
1969 }
1970 break;
1971
1972 case 'C': /* Ignore it */
1973 break;
1974
1975 case 'd': /* JF this is a kludge */
1976 install_operand ('s', opP->reg - ADDR);
1977 tmpreg = get_num (&opP->disp, 80);
1978 if (!issword (tmpreg))
1979 {
1980 as_warn ("Expression out of range, using 0");
1981 tmpreg = 0;
1982 }
1983 addword (tmpreg);
1984 break;
1985
1986 case 'D':
1987 install_operand (s[1], opP->reg - DATA);
1988 break;
1989
1990 case 'F':
1991 install_operand (s[1], opP->reg - FP0);
1992 break;
1993
1994 case 'I':
1995 tmpreg = opP->reg - COP0;
1996 install_operand (s[1], tmpreg);
1997 break;
1998
1999 case 'J': /* JF foo */
2000 switch (opP->reg)
2001 {
2002 case SFC:
2003 tmpreg = 0x000;
2004 break;
2005 case DFC:
2006 tmpreg = 0x001;
2007 break;
2008 case CACR:
2009 tmpreg = 0x002;
2010 break;
2011 case TC:
2012 tmpreg = 0x003;
2013 break;
2014 case ITT0:
2015 tmpreg = 0x004;
2016 break;
2017 case ITT1:
2018 tmpreg = 0x005;
2019 break;
2020 case DTT0:
2021 tmpreg = 0x006;
2022 break;
2023 case DTT1:
2024 tmpreg = 0x007;
2025 break;
2026 case BUSCR:
2027 tmpreg = 0x008;
2028 break;
2029
2030 case USP:
2031 tmpreg = 0x800;
2032 break;
2033 case VBR:
2034 tmpreg = 0x801;
2035 break;
2036 case CAAR:
2037 tmpreg = 0x802;
2038 break;
2039 case MSP:
2040 tmpreg = 0x803;
2041 break;
2042 case ISP:
2043 tmpreg = 0x804;
2044 break;
2045 case MMUSR:
2046 tmpreg = 0x805;
2047 break;
2048 case URP:
2049 tmpreg = 0x806;
2050 break;
2051 case SRP:
2052 tmpreg = 0x807;
2053 break;
2054 case PCR:
2055 tmpreg = 0x808;
2056 break;
2057 default:
2058 abort ();
2059 }
2060 install_operand (s[1], tmpreg);
2061 break;
2062
2063 case 'k':
2064 tmpreg = get_num (&opP->disp, 55);
2065 install_operand (s[1], tmpreg & 0x7f);
2066 break;
2067
2068 case 'l':
2069 tmpreg = opP->mask;
2070 if (s[1] == 'w')
2071 {
2072 if (tmpreg & 0x7FF0000)
2073 as_bad ("Floating point register in register list");
2074 insop (reverse_16_bits (tmpreg), opcode);
2075 }
2076 else
2077 {
2078 if (tmpreg & 0x700FFFF)
2079 as_bad ("Wrong register in floating-point reglist");
2080 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2081 }
2082 break;
2083
2084 case 'L':
2085 tmpreg = opP->mask;
2086 if (s[1] == 'w')
2087 {
2088 if (tmpreg & 0x7FF0000)
2089 as_bad ("Floating point register in register list");
2090 insop (tmpreg, opcode);
2091 }
2092 else if (s[1] == '8')
2093 {
2094 if (tmpreg & 0x0FFFFFF)
2095 as_bad ("incorrect register in reglist");
2096 install_operand (s[1], tmpreg >> 24);
2097 }
2098 else
2099 {
2100 if (tmpreg & 0x700FFFF)
2101 as_bad ("wrong register in floating-point reglist");
2102 else
2103 install_operand (s[1], tmpreg >> 16);
2104 }
2105 break;
2106
2107 case 'M':
2108 install_operand (s[1], get_num (&opP->disp, 60));
2109 break;
2110
2111 case 'O':
2112 tmpreg = ((opP->mode == DREG)
2113 ? 0x20 + opP->reg - DATA
2114 : (get_num (&opP->disp, 40) & 0x1F));
2115 install_operand (s[1], tmpreg);
2116 break;
2117
2118 case 'Q':
2119 tmpreg = get_num (&opP->disp, 10);
2120 if (tmpreg == 8)
2121 tmpreg = 0;
2122 install_operand (s[1], tmpreg);
2123 break;
2124
2125 case 'R':
2126 /* This depends on the fact that ADDR registers are eight
2127 more than their corresponding DATA regs, so the result
2128 will have the ADDR_REG bit set */
2129 install_operand (s[1], opP->reg - DATA);
2130 break;
2131
2132 case 'r':
2133 if (opP->mode == AINDR)
2134 install_operand (s[1], opP->reg - DATA);
2135 else
2136 install_operand (s[1], opP->index.reg - DATA);
2137 break;
2138
2139 case 's':
2140 if (opP->reg == FPI)
2141 tmpreg = 0x1;
2142 else if (opP->reg == FPS)
2143 tmpreg = 0x2;
2144 else if (opP->reg == FPC)
2145 tmpreg = 0x4;
2146 else
2147 abort ();
2148 install_operand (s[1], tmpreg);
2149 break;
2150
2151 case 'S': /* Ignore it */
2152 break;
2153
2154 case 'T':
2155 install_operand (s[1], get_num (&opP->disp, 30));
2156 break;
2157
2158 case 'U': /* Ignore it */
2159 break;
2160
2161 case 'c':
2162 switch (opP->reg)
2163 {
2164 case NC:
2165 tmpreg = 0;
2166 break;
2167 case DC:
2168 tmpreg = 1;
2169 break;
2170 case IC:
2171 tmpreg = 2;
2172 break;
2173 case BC:
2174 tmpreg = 3;
2175 break;
2176 default:
2177 as_fatal ("failed sanity check");
2178 } /* switch on cache token */
2179 install_operand (s[1], tmpreg);
2180 break;
2181 #ifndef NO_68851
2182 /* JF: These are out of order, I fear. */
2183 case 'f':
2184 switch (opP->reg)
2185 {
2186 case SFC:
2187 tmpreg = 0;
2188 break;
2189 case DFC:
2190 tmpreg = 1;
2191 break;
2192 default:
2193 abort ();
2194 }
2195 install_operand (s[1], tmpreg);
2196 break;
2197
2198 case 'P':
2199 switch (opP->reg)
2200 {
2201 case TC:
2202 tmpreg = 0;
2203 break;
2204 case CAL:
2205 tmpreg = 4;
2206 break;
2207 case VAL:
2208 tmpreg = 5;
2209 break;
2210 case SCC:
2211 tmpreg = 6;
2212 break;
2213 case AC:
2214 tmpreg = 7;
2215 break;
2216 default:
2217 abort ();
2218 }
2219 install_operand (s[1], tmpreg);
2220 break;
2221
2222 case 'V':
2223 if (opP->reg == VAL)
2224 break;
2225 abort ();
2226
2227 case 'W':
2228 switch (opP->reg)
2229 {
2230 case DRP:
2231 tmpreg = 1;
2232 break;
2233 case SRP:
2234 tmpreg = 2;
2235 break;
2236 case CRP:
2237 tmpreg = 3;
2238 break;
2239 default:
2240 abort ();
2241 }
2242 install_operand (s[1], tmpreg);
2243 break;
2244
2245 case 'X':
2246 switch (opP->reg)
2247 {
2248 case BAD:
2249 case BAD + 1:
2250 case BAD + 2:
2251 case BAD + 3:
2252 case BAD + 4:
2253 case BAD + 5:
2254 case BAD + 6:
2255 case BAD + 7:
2256 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2257 break;
2258
2259 case BAC:
2260 case BAC + 1:
2261 case BAC + 2:
2262 case BAC + 3:
2263 case BAC + 4:
2264 case BAC + 5:
2265 case BAC + 6:
2266 case BAC + 7:
2267 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2268 break;
2269
2270 default:
2271 abort ();
2272 }
2273 install_operand (s[1], tmpreg);
2274 break;
2275 case 'Y':
2276 know (opP->reg == PSR);
2277 break;
2278 case 'Z':
2279 know (opP->reg == PCSR);
2280 break;
2281 #endif /* m68851 */
2282 case '3':
2283 switch (opP->reg)
2284 {
2285 case TT0:
2286 tmpreg = 2;
2287 break;
2288 case TT1:
2289 tmpreg = 3;
2290 break;
2291 default:
2292 abort ();
2293 }
2294 install_operand (s[1], tmpreg);
2295 break;
2296 case 't':
2297 tmpreg = get_num (&opP->disp, 20);
2298 install_operand (s[1], tmpreg);
2299 break;
2300 case '_': /* used only for move16 absolute 32-bit address */
2301 tmpreg = get_num (&opP->disp, 80);
2302 addword (tmpreg >> 16);
2303 addword (tmpreg & 0xFFFF);
2304 break;
2305 default:
2306 abort ();
2307 }
2308 }
2309
2310 /* By the time whe get here (FINALLY) the_ins contains the complete
2311 instruction, ready to be emitted. . . */
2312 }
2313
2314 static int
2315 reverse_16_bits (in)
2316 int in;
2317 {
2318 int out = 0;
2319 int n;
2320
2321 static int mask[16] =
2322 {
2323 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2324 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2325 };
2326 for (n = 0; n < 16; n++)
2327 {
2328 if (in & mask[n])
2329 out |= mask[15 - n];
2330 }
2331 return out;
2332 } /* reverse_16_bits() */
2333
2334 static int
2335 reverse_8_bits (in)
2336 int in;
2337 {
2338 int out = 0;
2339 int n;
2340
2341 static int mask[8] =
2342 {
2343 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2344 };
2345
2346 for (n = 0; n < 8; n++)
2347 {
2348 if (in & mask[n])
2349 out |= mask[7 - n];
2350 }
2351 return out;
2352 } /* reverse_8_bits() */
2353
2354 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2355 (that value is chosen in the frag_var call in md_assemble). TYPE
2356 is the subtype of the frag to be generated; its primary type is
2357 rs_machine_dependent.
2358
2359 The TYPE parameter is also used by md_convert_frag_1 and
2360 md_estimate_size_before_relax. The appropriate type of fixup will
2361 be emitted by md_convert_frag_1.
2362
2363 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2364 static void
2365 install_operand (mode, val)
2366 int mode;
2367 int val;
2368 {
2369 switch (mode)
2370 {
2371 case 's':
2372 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2373 break;
2374 case 'd':
2375 the_ins.opcode[0] |= val << 9;
2376 break;
2377 case '1':
2378 the_ins.opcode[1] |= val << 12;
2379 break;
2380 case '2':
2381 the_ins.opcode[1] |= val << 6;
2382 break;
2383 case '3':
2384 the_ins.opcode[1] |= val;
2385 break;
2386 case '4':
2387 the_ins.opcode[2] |= val << 12;
2388 break;
2389 case '5':
2390 the_ins.opcode[2] |= val << 6;
2391 break;
2392 case '6':
2393 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2394 three words long! */
2395 the_ins.numo++;
2396 the_ins.opcode[2] |= val;
2397 break;
2398 case '7':
2399 the_ins.opcode[1] |= val << 7;
2400 break;
2401 case '8':
2402 the_ins.opcode[1] |= val << 10;
2403 break;
2404 #ifndef NO_68851
2405 case '9':
2406 the_ins.opcode[1] |= val << 5;
2407 break;
2408 #endif
2409
2410 case 't':
2411 the_ins.opcode[1] |= (val << 10) | (val << 7);
2412 break;
2413 case 'D':
2414 the_ins.opcode[1] |= (val << 12) | val;
2415 break;
2416 case 'g':
2417 the_ins.opcode[0] |= val = 0xff;
2418 break;
2419 case 'i':
2420 the_ins.opcode[0] |= val << 9;
2421 break;
2422 case 'C':
2423 the_ins.opcode[1] |= val;
2424 break;
2425 case 'j':
2426 the_ins.opcode[1] |= val;
2427 the_ins.numo++; /* What a hack */
2428 break;
2429 case 'k':
2430 the_ins.opcode[1] |= val << 4;
2431 break;
2432 case 'b':
2433 case 'w':
2434 case 'l':
2435 break;
2436 case 'e':
2437 the_ins.opcode[0] |= (val << 6);
2438 break;
2439 case 'L':
2440 the_ins.opcode[1] = (val >> 16);
2441 the_ins.opcode[2] = val & 0xffff;
2442 break;
2443 case 'c':
2444 default:
2445 as_fatal ("failed sanity check.");
2446 }
2447 } /* install_operand() */
2448
2449 static void
2450 install_gen_operand (mode, val)
2451 int mode;
2452 int val;
2453 {
2454 switch (mode)
2455 {
2456 case 's':
2457 the_ins.opcode[0] |= val;
2458 break;
2459 case 'd':
2460 /* This is a kludge!!! */
2461 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2462 break;
2463 case 'b':
2464 case 'w':
2465 case 'l':
2466 case 'f':
2467 case 'F':
2468 case 'x':
2469 case 'p':
2470 the_ins.opcode[0] |= val;
2471 break;
2472 /* more stuff goes here */
2473 default:
2474 as_fatal ("failed sanity check.");
2475 }
2476 } /* install_gen_operand() */
2477
2478 /*
2479 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2480 * then deal with the bitfield hack.
2481 */
2482
2483 static char *
2484 crack_operand (str, opP)
2485 register char *str;
2486 register struct m68k_op *opP;
2487 {
2488 register int parens;
2489 register int c;
2490 register char *beg_str;
2491
2492 if (!str)
2493 {
2494 return str;
2495 }
2496 beg_str = str;
2497 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
2498 {
2499 if (*str == '(')
2500 parens++;
2501 else if (*str == ')')
2502 {
2503 if (!parens)
2504 { /* ERROR */
2505 opP->error = "Extra )";
2506 return str;
2507 }
2508 --parens;
2509 }
2510 }
2511 if (!*str && parens)
2512 { /* ERROR */
2513 opP->error = "Missing )";
2514 return str;
2515 }
2516 c = *str;
2517 *str = '\0';
2518 if (m68k_ip_op (beg_str, opP) != 0)
2519 {
2520 *str = c;
2521 return str;
2522 }
2523 *str = c;
2524 if (c == '}')
2525 c = *++str; /* JF bitfield hack */
2526 if (c)
2527 {
2528 c = *++str;
2529 if (!c)
2530 as_bad ("Missing operand");
2531 }
2532 return str;
2533 }
2534
2535 /* This is the guts of the machine-dependent assembler. STR points to a
2536 machine dependent instruction. This function is supposed to emit
2537 the frags/bytes it assembles to.
2538 */
2539
2540 void
2541 insert_reg (regname, regnum)
2542 char *regname;
2543 int regnum;
2544 {
2545 char buf[100];
2546 int i;
2547
2548 #ifdef REGISTER_PREFIX
2549 if (!flag_reg_prefix_optional)
2550 {
2551 buf[0] = REGISTER_PREFIX;
2552 strcpy (buf + 1, regname);
2553 regname = buf;
2554 }
2555 #endif
2556
2557 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2558 &zero_address_frag));
2559
2560 for (i = 0; regname[i]; i++)
2561 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2562 buf[i] = '\0';
2563
2564 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2565 &zero_address_frag));
2566 }
2567
2568 struct init_entry
2569 {
2570 const char *name;
2571 int number;
2572 };
2573
2574 static const struct init_entry init_table[] =
2575 {
2576 { "d0", DATA0 },
2577 { "d1", DATA1 },
2578 { "d2", DATA2 },
2579 { "d3", DATA3 },
2580 { "d4", DATA4 },
2581 { "d5", DATA5 },
2582 { "d6", DATA6 },
2583 { "d7", DATA7 },
2584 { "a0", ADDR0 },
2585 { "a1", ADDR1 },
2586 { "a2", ADDR2 },
2587 { "a3", ADDR3 },
2588 { "a4", ADDR4 },
2589 { "a5", ADDR5 },
2590 { "a6", ADDR6 },
2591 { "fp", ADDR6 },
2592 { "a7", ADDR7 },
2593 { "sp", ADDR7 },
2594 { "ssp", ADDR7 },
2595 { "fp0", FP0 },
2596 { "fp1", FP1 },
2597 { "fp2", FP2 },
2598 { "fp3", FP3 },
2599 { "fp4", FP4 },
2600 { "fp5", FP5 },
2601 { "fp6", FP6 },
2602 { "fp7", FP7 },
2603 { "fpi", FPI },
2604 { "fpiar", FPI },
2605 { "fpc", FPI },
2606 { "fps", FPS },
2607 { "fpsr", FPS },
2608 { "fpc", FPC },
2609 { "fpcr", FPC },
2610 { "control", FPC },
2611 { "status", FPS },
2612 { "iaddr", FPI },
2613
2614 { "cop0", COP0 },
2615 { "cop1", COP1 },
2616 { "cop2", COP2 },
2617 { "cop3", COP3 },
2618 { "cop4", COP4 },
2619 { "cop5", COP5 },
2620 { "cop6", COP6 },
2621 { "cop7", COP7 },
2622 { "pc", PC },
2623 { "zpc", ZPC },
2624 { "sr", SR },
2625
2626 { "ccr", CCR },
2627 { "cc", CCR },
2628
2629 { "usp", USP },
2630 { "isp", ISP },
2631 { "sfc", SFC },
2632 { "sfcr", SFC },
2633 { "dfc", DFC },
2634 { "dfcr", DFC },
2635 { "cacr", CACR },
2636 { "caar", CAAR },
2637
2638 { "vbr", VBR },
2639
2640 { "msp", MSP },
2641 { "itt0", ITT0 },
2642 { "itt1", ITT1 },
2643 { "dtt0", DTT0 },
2644 { "dtt1", DTT1 },
2645 { "mmusr", MMUSR },
2646 { "tc", TC },
2647 { "srp", SRP },
2648 { "urp", URP },
2649 { "buscr", BUSCR },
2650 { "pcr", PCR },
2651
2652 { "ac", AC },
2653 { "bc", BC },
2654 { "cal", CAL },
2655 { "crp", CRP },
2656 { "drp", DRP },
2657 { "pcsr", PCSR },
2658 { "psr", PSR },
2659 { "scc", SCC },
2660 { "val", VAL },
2661 { "bad0", BAD0 },
2662 { "bad1", BAD1 },
2663 { "bad2", BAD2 },
2664 { "bad3", BAD3 },
2665 { "bad4", BAD4 },
2666 { "bad5", BAD5 },
2667 { "bad6", BAD6 },
2668 { "bad7", BAD7 },
2669 { "bac0", BAC0 },
2670 { "bac1", BAC1 },
2671 { "bac2", BAC2 },
2672 { "bac3", BAC3 },
2673 { "bac4", BAC4 },
2674 { "bac5", BAC5 },
2675 { "bac6", BAC6 },
2676 { "bac7", BAC7 },
2677
2678 { "ic", IC },
2679 { "dc", DC },
2680 { "nc", NC },
2681
2682 { "tt0", TT0 },
2683 { "tt1", TT1 },
2684 /* 68ec030 versions of same */
2685 { "ac0", TT0 },
2686 { "ac1", TT1 },
2687 /* 68ec030 access control unit, identical to 030 MMU status reg */
2688 { "acusr", PSR },
2689
2690 /* Suppressed data and address registers. */
2691 { "zd0", ZDATA0 },
2692 { "zd1", ZDATA1 },
2693 { "zd2", ZDATA2 },
2694 { "zd3", ZDATA3 },
2695 { "zd4", ZDATA4 },
2696 { "zd5", ZDATA5 },
2697 { "zd6", ZDATA6 },
2698 { "zd7", ZDATA7 },
2699 { "za0", ZADDR0 },
2700 { "za1", ZADDR1 },
2701 { "za2", ZADDR2 },
2702 { "za3", ZADDR3 },
2703 { "za4", ZADDR4 },
2704 { "za5", ZADDR5 },
2705 { "za6", ZADDR6 },
2706 { "za7", ZADDR7 },
2707
2708 { 0, 0 }
2709 };
2710
2711 void
2712 init_regtable ()
2713 {
2714 int i;
2715 for (i = 0; init_table[i].name; i++)
2716 insert_reg (init_table[i].name, init_table[i].number);
2717 }
2718
2719 static int no_68851, no_68881;
2720
2721 #ifdef OBJ_AOUT
2722 /* a.out machine type. Default to 68020. */
2723 int m68k_aout_machtype = 2;
2724 #endif
2725
2726 void
2727 md_assemble (str)
2728 char *str;
2729 {
2730 const char *er;
2731 short *fromP;
2732 char *toP = NULL;
2733 int m, n = 0;
2734 char *to_beg_P;
2735 int shorts_this_frag;
2736 fixS *fixP;
2737
2738 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2739 m68k_ip (str);
2740 er = the_ins.error;
2741 if (!er)
2742 {
2743 for (n = 0; n < the_ins.numargs; n++)
2744 if (the_ins.operands[n].error)
2745 {
2746 er = the_ins.operands[n].error;
2747 break;
2748 }
2749 }
2750 if (er)
2751 {
2752 as_bad ("%s -- statement `%s' ignored", er, str);
2753 return;
2754 }
2755
2756 if (the_ins.nfrag == 0)
2757 {
2758 /* No frag hacking involved; just put it out */
2759 toP = frag_more (2 * the_ins.numo);
2760 fromP = &the_ins.opcode[0];
2761 for (m = the_ins.numo; m; --m)
2762 {
2763 md_number_to_chars (toP, (long) (*fromP), 2);
2764 toP += 2;
2765 fromP++;
2766 }
2767 /* put out symbol-dependent info */
2768 for (m = 0; m < the_ins.nrel; m++)
2769 {
2770 switch (the_ins.reloc[m].wid)
2771 {
2772 case 'B':
2773 n = 1;
2774 break;
2775 case 'b':
2776 n = 1;
2777 break;
2778 case '3':
2779 n = 2;
2780 break;
2781 case 'w':
2782 n = 2;
2783 break;
2784 case 'l':
2785 n = 4;
2786 break;
2787 default:
2788 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2789 the_ins.reloc[m].wid);
2790 }
2791
2792 fixP = fix_new_exp (frag_now,
2793 ((toP - frag_now->fr_literal)
2794 - the_ins.numo * 2 + the_ins.reloc[m].n),
2795 n,
2796 &the_ins.reloc[m].exp,
2797 the_ins.reloc[m].pcrel,
2798 NO_RELOC);
2799 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2800 }
2801 return;
2802 }
2803
2804 /* There's some frag hacking */
2805 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2806 {
2807 int wid;
2808
2809 if (n == 0)
2810 wid = 2 * the_ins.fragb[n].fragoff;
2811 else
2812 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2813 toP = frag_more (wid);
2814 to_beg_P = toP;
2815 shorts_this_frag = 0;
2816 for (m = wid / 2; m; --m)
2817 {
2818 md_number_to_chars (toP, (long) (*fromP), 2);
2819 toP += 2;
2820 fromP++;
2821 shorts_this_frag++;
2822 }
2823 for (m = 0; m < the_ins.nrel; m++)
2824 {
2825 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2826 {
2827 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2828 break;
2829 }
2830 wid = the_ins.reloc[m].wid;
2831 if (wid == 0)
2832 continue;
2833 the_ins.reloc[m].wid = 0;
2834 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2835
2836 fixP = fix_new_exp (frag_now,
2837 ((toP - frag_now->fr_literal)
2838 - the_ins.numo * 2 + the_ins.reloc[m].n),
2839 wid,
2840 &the_ins.reloc[m].exp,
2841 the_ins.reloc[m].pcrel,
2842 NO_RELOC);
2843 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2844 }
2845 (void) frag_var (rs_machine_dependent, 10, 0,
2846 (relax_substateT) (the_ins.fragb[n].fragty),
2847 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2848 }
2849 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2850 shorts_this_frag = 0;
2851 if (n)
2852 {
2853 toP = frag_more (n * sizeof (short));
2854 while (n--)
2855 {
2856 md_number_to_chars (toP, (long) (*fromP), 2);
2857 toP += 2;
2858 fromP++;
2859 shorts_this_frag++;
2860 }
2861 }
2862 for (m = 0; m < the_ins.nrel; m++)
2863 {
2864 int wid;
2865
2866 wid = the_ins.reloc[m].wid;
2867 if (wid == 0)
2868 continue;
2869 the_ins.reloc[m].wid = 0;
2870 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2871
2872 fixP = fix_new_exp (frag_now,
2873 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2874 - shorts_this_frag * 2),
2875 wid,
2876 &the_ins.reloc[m].exp,
2877 the_ins.reloc[m].pcrel,
2878 NO_RELOC);
2879 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2880 }
2881 }
2882
2883 void
2884 md_begin ()
2885 {
2886 /*
2887 * md_begin -- set up hash tables with 68000 instructions.
2888 * similar to what the vax assembler does. ---phr
2889 */
2890 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2891 a copy of it at runtime, adding in the information we want but isn't
2892 there. I think it'd be better to have an awk script hack the table
2893 at compile time. Or even just xstr the table and use it as-is. But
2894 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2895 names. */
2896
2897 register const struct m68k_opcode *ins;
2898 register struct m68k_incant *hack, *slak;
2899 register const char *retval = 0; /* empty string, or error msg text */
2900 register unsigned int i;
2901 register char c;
2902
2903 if (flag_mri)
2904 {
2905 flag_reg_prefix_optional = 1;
2906 m68k_abspcadd = 1;
2907 m68k_rel32 = 0;
2908 }
2909
2910 op_hash = hash_new ();
2911
2912 obstack_begin (&robyn, 4000);
2913 for (i = 0; i < m68k_numopcodes; i++)
2914 {
2915 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2916 do
2917 {
2918 ins = &m68k_opcodes[i];
2919 /* We *could* ignore insns that don't match our arch here
2920 but just leaving them out of the hash. */
2921 slak->m_operands = ins->args;
2922 slak->m_opnum = strlen (slak->m_operands) / 2;
2923 slak->m_arch = ins->arch;
2924 slak->m_opcode = ins->opcode;
2925 /* This is kludgey */
2926 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
2927 if (i + 1 != m68k_numopcodes
2928 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
2929 {
2930 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2931 i++;
2932 }
2933 else
2934 slak->m_next = 0;
2935 slak = slak->m_next;
2936 }
2937 while (slak);
2938
2939 retval = hash_insert (op_hash, ins->name, (char *) hack);
2940 if (retval)
2941 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
2942 }
2943
2944 for (i = 0; i < m68k_numaliases; i++)
2945 {
2946 const char *name = m68k_opcode_aliases[i].primary;
2947 const char *alias = m68k_opcode_aliases[i].alias;
2948 PTR val = hash_find (op_hash, name);
2949 if (!val)
2950 as_fatal ("Internal Error: Can't find %s in hash table", name);
2951 retval = hash_insert (op_hash, alias, val);
2952 if (retval)
2953 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
2954 }
2955
2956 /* In MRI mode, all unsized branches are variable sized. Normally,
2957 they are word sized. */
2958 if (flag_mri)
2959 {
2960 static struct m68k_opcode_alias mri_aliases[] =
2961 {
2962 { "bhi", "jhi", },
2963 { "bls", "jls", },
2964 { "bcc", "jcc", },
2965 { "bcs", "jcs", },
2966 { "bne", "jne", },
2967 { "beq", "jeq", },
2968 { "bvc", "jvc", },
2969 { "bvs", "jvs", },
2970 { "bpl", "jpl", },
2971 { "bmi", "jmi", },
2972 { "bge", "jge", },
2973 { "blt", "jlt", },
2974 { "bgt", "jgt", },
2975 { "ble", "jle", },
2976 { "bra", "jra", },
2977 { "bsr", "jbsr", },
2978 };
2979
2980 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
2981 {
2982 const char *name = mri_aliases[i].primary;
2983 const char *alias = mri_aliases[i].alias;
2984 PTR val = hash_find (op_hash, name);
2985 if (!val)
2986 as_fatal ("Internal Error: Can't find %s in hash table", name);
2987 retval = hash_jam (op_hash, alias, val);
2988 if (retval)
2989 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
2990 }
2991 }
2992
2993 for (i = 0; i < sizeof (mklower_table); i++)
2994 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
2995
2996 for (i = 0; i < sizeof (notend_table); i++)
2997 {
2998 notend_table[i] = 0;
2999 alt_notend_table[i] = 0;
3000 }
3001 notend_table[','] = 1;
3002 notend_table['{'] = 1;
3003 notend_table['}'] = 1;
3004 alt_notend_table['a'] = 1;
3005 alt_notend_table['A'] = 1;
3006 alt_notend_table['d'] = 1;
3007 alt_notend_table['D'] = 1;
3008 alt_notend_table['#'] = 1;
3009 alt_notend_table['&'] = 1;
3010 alt_notend_table['f'] = 1;
3011 alt_notend_table['F'] = 1;
3012 #ifdef REGISTER_PREFIX
3013 alt_notend_table[REGISTER_PREFIX] = 1;
3014 #endif
3015
3016 /* We need to put '(' in alt_notend_table to handle
3017 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3018 */
3019 alt_notend_table['('] = 1;
3020
3021 /* We need to put '@' in alt_notend_table to handle
3022 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3023 */
3024 alt_notend_table['@'] = 1;
3025
3026 #ifndef MIT_SYNTAX_ONLY
3027 /* Insert pseudo ops, these have to go into the opcode table since
3028 gas expects pseudo ops to start with a dot */
3029 {
3030 int n = 0;
3031 while (mote_pseudo_table[n].poc_name)
3032 {
3033 hack = (struct m68k_incant *)
3034 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3035 hash_insert (op_hash,
3036 mote_pseudo_table[n].poc_name, (char *) hack);
3037 hack->m_operands = 0;
3038 hack->m_opnum = n;
3039 n++;
3040 }
3041 }
3042 #endif
3043
3044 init_regtable ();
3045 }
3046
3047 void
3048 m68k_init_after_args ()
3049 {
3050 if (cpu_of_arch (current_architecture) == 0)
3051 {
3052 int i;
3053 const char *default_cpu = TARGET_CPU;
3054
3055 if (*default_cpu == 'm')
3056 default_cpu++;
3057 for (i = 0; i < n_archs; i++)
3058 if (strcasecmp (default_cpu, archs[i].name) == 0)
3059 break;
3060 if (i == n_archs)
3061 {
3062 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3063 current_architecture |= m68020;
3064 }
3065 else
3066 current_architecture |= archs[i].arch;
3067 }
3068 /* Permit m68881 specification with all cpus; those that can't work
3069 with a coprocessor could be doing emulation. */
3070 if (current_architecture & m68851)
3071 {
3072 if (current_architecture & m68040)
3073 {
3074 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3075 }
3076 }
3077 /* What other incompatibilities could we check for? */
3078
3079 /* Toss in some default assumptions about coprocessors. */
3080 if (!no_68881
3081 && (cpu_of_arch (current_architecture)
3082 /* Can CPU32 have a 68881 coprocessor?? */
3083 & (m68020 | m68030 | cpu32)))
3084 {
3085 current_architecture |= m68881;
3086 }
3087 if (!no_68851
3088 && (cpu_of_arch (current_architecture) & m68020up) != 0
3089 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3090 {
3091 current_architecture |= m68851;
3092 }
3093 if (no_68881 && (current_architecture & m68881))
3094 as_bad ("options for 68881 and no-68881 both given");
3095 if (no_68851 && (current_architecture & m68851))
3096 as_bad ("options for 68851 and no-68851 both given");
3097
3098 #ifdef OBJ_AOUT
3099 /* Work out the magic number. This isn't very general. */
3100 if (current_architecture & m68000)
3101 m68k_aout_machtype = 0;
3102 else if (current_architecture & m68010)
3103 m68k_aout_machtype = 1;
3104 else if (current_architecture & m68020)
3105 m68k_aout_machtype = 2;
3106 else
3107 m68k_aout_machtype = 2;
3108 #endif
3109
3110 /* Note which set of "movec" control registers is available. */
3111 switch (cpu_of_arch (current_architecture))
3112 {
3113 case m68000:
3114 control_regs = m68000_control_regs;
3115 break;
3116 case m68010:
3117 control_regs = m68010_control_regs;
3118 break;
3119 case m68020:
3120 case m68030:
3121 control_regs = m68020_control_regs;
3122 break;
3123 case m68040:
3124 control_regs = m68040_control_regs;
3125 break;
3126 case m68060:
3127 control_regs = m68060_control_regs;
3128 break;
3129 case cpu32:
3130 control_regs = cpu32_control_regs;
3131 break;
3132 default:
3133 abort ();
3134 }
3135
3136 if (cpu_of_arch (current_architecture) < m68020)
3137 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3138 }
3139
3140 /* Equal to MAX_PRECISION in atof-ieee.c */
3141 #define MAX_LITTLENUMS 6
3142
3143 /* Turn a string in input_line_pointer into a floating point constant
3144 of type type, and store the appropriate bytes in *litP. The number
3145 of LITTLENUMS emitted is stored in *sizeP . An error message is
3146 returned, or NULL on OK. */
3147
3148 char *
3149 md_atof (type, litP, sizeP)
3150 char type;
3151 char *litP;
3152 int *sizeP;
3153 {
3154 int prec;
3155 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3156 LITTLENUM_TYPE *wordP;
3157 char *t;
3158 char *atof_ieee ();
3159
3160 switch (type)
3161 {
3162 case 'f':
3163 case 'F':
3164 case 's':
3165 case 'S':
3166 prec = 2;
3167 break;
3168
3169 case 'd':
3170 case 'D':
3171 case 'r':
3172 case 'R':
3173 prec = 4;
3174 break;
3175
3176 case 'x':
3177 case 'X':
3178 prec = 6;
3179 break;
3180
3181 case 'p':
3182 case 'P':
3183 prec = 6;
3184 break;
3185
3186 default:
3187 *sizeP = 0;
3188 return "Bad call to MD_ATOF()";
3189 }
3190 t = atof_ieee (input_line_pointer, type, words);
3191 if (t)
3192 input_line_pointer = t;
3193
3194 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3195 for (wordP = words; prec--;)
3196 {
3197 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3198 litP += sizeof (LITTLENUM_TYPE);
3199 }
3200 return 0;
3201 }
3202
3203 void
3204 md_number_to_chars (buf, val, n)
3205 char *buf;
3206 valueT val;
3207 int n;
3208 {
3209 number_to_chars_bigendian (buf, val, n);
3210 }
3211
3212 static void
3213 md_apply_fix_2 (fixP, val)
3214 fixS *fixP;
3215 offsetT val;
3216 {
3217 addressT upper_limit;
3218 offsetT lower_limit;
3219
3220 /* This is unnecessary but it convinces the native rs6000 compiler
3221 to generate the code we want. */
3222 char *buf = fixP->fx_frag->fr_literal;
3223 buf += fixP->fx_where;
3224 /* end ibm compiler workaround */
3225
3226 if (val & 0x80000000)
3227 val |= ~(addressT)0x7fffffff;
3228 else
3229 val &= 0x7fffffff;
3230
3231 switch (fixP->fx_size)
3232 {
3233 /* The cast to offsetT below are necessary to make code correct for
3234 machines where ints are smaller than offsetT */
3235 case 1:
3236 *buf++ = val;
3237 upper_limit = 0x7f;
3238 lower_limit = - (offsetT) 0x80;
3239 break;
3240 case 2:
3241 *buf++ = (val >> 8);
3242 *buf++ = val;
3243 upper_limit = 0x7fff;
3244 lower_limit = - (offsetT) 0x8000;
3245 break;
3246 case 4:
3247 *buf++ = (val >> 24);
3248 *buf++ = (val >> 16);
3249 *buf++ = (val >> 8);
3250 *buf++ = val;
3251 upper_limit = 0x7fffffff;
3252 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3253 break;
3254 default:
3255 BAD_CASE (fixP->fx_size);
3256 }
3257
3258 /* For non-pc-relative values, it's conceivable we might get something
3259 like "0xff" for a byte field. So extend the upper part of the range
3260 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3261 so that we can do any range checking at all. */
3262 if (!fixP->fx_pcrel)
3263 upper_limit = upper_limit * 2 + 1;
3264
3265 if ((addressT) val > upper_limit
3266 && (val > 0 || val < lower_limit))
3267 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3268
3269 /* A one byte PC-relative reloc means a short branch. We can't use
3270 a short branch with a value of 0 or -1, because those indicate
3271 different opcodes (branches with longer offsets). */
3272 if (fixP->fx_pcrel
3273 && fixP->fx_size == 1
3274 && (fixP->fx_addsy == NULL
3275 || S_IS_DEFINED (fixP->fx_addsy))
3276 && (val == 0 || val == -1))
3277 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3278 }
3279
3280 #ifdef BFD_ASSEMBLER
3281 int
3282 md_apply_fix (fixP, valp)
3283 fixS *fixP;
3284 valueT *valp;
3285 {
3286 md_apply_fix_2 (fixP, (addressT) *valp);
3287 return 1;
3288 }
3289 #else
3290 void md_apply_fix (fixP, val)
3291 fixS *fixP;
3292 long val;
3293 {
3294 md_apply_fix_2 (fixP, (addressT) val);
3295 }
3296 #endif
3297
3298 /* *fragP has been relaxed to its final size, and now needs to have
3299 the bytes inside it modified to conform to the new size There is UGLY
3300 MAGIC here. ..
3301 */
3302 void
3303 md_convert_frag_1 (fragP)
3304 register fragS *fragP;
3305 {
3306 long disp;
3307 long ext = 0;
3308 fixS *fixP;
3309
3310 /* Address in object code of the displacement. */
3311 register int object_address = fragP->fr_fix + fragP->fr_address;
3312
3313 /* Address in gas core of the place to store the displacement. */
3314 /* This convinces the native rs6000 compiler to generate the code we
3315 want. */
3316 register char *buffer_address = fragP->fr_literal;
3317 buffer_address += fragP->fr_fix;
3318 /* end ibm compiler workaround */
3319
3320 /* The displacement of the address, from current location. */
3321 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3322 disp = (disp + fragP->fr_offset) - object_address;
3323
3324 #ifdef BFD_ASSEMBLER
3325 disp += fragP->fr_symbol->sy_frag->fr_address;
3326 #endif
3327
3328 switch (fragP->fr_subtype)
3329 {
3330 case TAB (BCC68000, BYTE):
3331 case TAB (ABRANCH, BYTE):
3332 know (issbyte (disp));
3333 if (disp == 0)
3334 as_bad ("short branch with zero offset: use :w");
3335 fragP->fr_opcode[1] = disp;
3336 ext = 0;
3337 break;
3338 case TAB (DBCC, SHORT):
3339 know (issword (disp));
3340 ext = 2;
3341 break;
3342 case TAB (BCC68000, SHORT):
3343 case TAB (ABRANCH, SHORT):
3344 know (issword (disp));
3345 fragP->fr_opcode[1] = 0x00;
3346 ext = 2;
3347 break;
3348 case TAB (ABRANCH, LONG):
3349 if (cpu_of_arch (current_architecture) < m68020)
3350 {
3351 if (fragP->fr_opcode[0] == 0x61)
3352 /* BSR */
3353 {
3354 fragP->fr_opcode[0] = 0x4E;
3355 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3356 subseg_change (text_section, 0); /* @@ */
3357
3358 fix_new (fragP,
3359 fragP->fr_fix,
3360 4,
3361 fragP->fr_symbol,
3362 fragP->fr_offset,
3363 0,
3364 NO_RELOC);
3365
3366 fragP->fr_fix += 4;
3367 ext = 0;
3368 }
3369 /* BRA */
3370 else if (fragP->fr_opcode[0] == 0x60)
3371 {
3372 fragP->fr_opcode[0] = 0x4E;
3373 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3374 subseg_change (text_section, 0); /* @@ */
3375 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3376 fragP->fr_offset, 0, NO_RELOC);
3377 fragP->fr_fix += 4;
3378 ext = 0;
3379 }
3380 else
3381 {
3382 as_bad ("Long branch offset not supported.");
3383 }
3384 }
3385 else
3386 {
3387 fragP->fr_opcode[1] = (char) 0xff;
3388 ext = 4;
3389 }
3390 break;
3391 case TAB (BCC68000, LONG):
3392 /* only Bcc 68000 instructions can come here */
3393 /* change bcc into b!cc/jmp absl long */
3394 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3395 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3396
3397 /* JF: these used to be fr_opcode[2,3], but they may be in a
3398 different frag, in which case refering to them is a no-no.
3399 Only fr_opcode[0,1] are guaranteed to work. */
3400 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3401 *buffer_address++ = (char) 0xf9;
3402 fragP->fr_fix += 2; /* account for jmp instruction */
3403 subseg_change (text_section, 0);
3404 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3405 fragP->fr_offset, 0, NO_RELOC);
3406 fragP->fr_fix += 4;
3407 ext = 0;
3408 break;
3409 case TAB (DBCC, LONG):
3410 /* only DBcc 68000 instructions can come here */
3411 /* change dbcc into dbcc/jmp absl long */
3412 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3413 *buffer_address++ = 0x00; /* branch offset = 4 */
3414 *buffer_address++ = 0x04;
3415 *buffer_address++ = 0x60; /* put in bra pc+6 */
3416 *buffer_address++ = 0x06;
3417 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3418 *buffer_address++ = (char) 0xf9;
3419
3420 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3421 subseg_change (text_section, 0);
3422 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3423 fragP->fr_offset, 0, NO_RELOC);
3424 fragP->fr_fix += 4;
3425 ext = 0;
3426 break;
3427 case TAB (FBRANCH, SHORT):
3428 know ((fragP->fr_opcode[1] & 0x40) == 0);
3429 ext = 2;
3430 break;
3431 case TAB (FBRANCH, LONG):
3432 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3433 ext = 4;
3434 break;
3435 case TAB (PCREL, SHORT):
3436 ext = 2;
3437 break;
3438 case TAB (PCREL, LONG):
3439 /* The thing to do here is force it to ABSOLUTE LONG, since
3440 PCREL is really trying to shorten an ABSOLUTE address anyway */
3441 /* JF FOO This code has not been tested */
3442 subseg_change (text_section, 0);
3443 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3444 0, NO_RELOC);
3445 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3446 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3447 (unsigned) fragP->fr_opcode[0],
3448 (unsigned long) fragP->fr_address);
3449 fragP->fr_opcode[1] &= ~0x3F;
3450 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3451 fragP->fr_fix += 4;
3452 ext = 0;
3453 break;
3454 case TAB (PCLEA, SHORT):
3455 subseg_change (text_section, 0);
3456 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3457 fragP->fr_offset, 1, NO_RELOC);
3458 fragP->fr_opcode[1] &= ~0x3F;
3459 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3460 ext = 2;
3461 break;
3462 case TAB (PCLEA, LONG):
3463 subseg_change (text_section, 0);
3464 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3465 fragP->fr_offset, 1, NO_RELOC);
3466 fixP->fx_pcrel_adjust = 2;
3467 /* Already set to mode 7.3; this indicates: PC indirect with
3468 suppressed index, 32-bit displacement. */
3469 *buffer_address++ = 0x01;
3470 *buffer_address++ = 0x70;
3471 fragP->fr_fix += 2;
3472 ext = 4;
3473 break;
3474
3475 case TAB (PCINDEX, BYTE):
3476 disp += 2;
3477 if (!issbyte (disp))
3478 {
3479 as_bad ("displacement doesn't fit in one byte");
3480 disp = 0;
3481 }
3482 assert (fragP->fr_fix >= 2);
3483 buffer_address[-2] &= ~1;
3484 buffer_address[-1] = disp;
3485 ext = 0;
3486 break;
3487 case TAB (PCINDEX, SHORT):
3488 subseg_change (text_section, 0);
3489 disp += 2;
3490 assert (issword (disp));
3491 assert (fragP->fr_fix >= 2);
3492 buffer_address[-2] |= 0x1;
3493 buffer_address[-1] = 0x20;
3494 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3495 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3496 NO_RELOC);
3497 fixP->fx_pcrel_adjust = 2;
3498 ext = 2;
3499 break;
3500 case TAB (PCINDEX, LONG):
3501 subseg_change (text_section, 0);
3502 disp += 2;
3503 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3504 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3505 NO_RELOC);
3506 fixP->fx_pcrel_adjust = 2;
3507 assert (fragP->fr_fix >= 2);
3508 buffer_address[-2] |= 0x1;
3509 buffer_address[-1] = 0x30;
3510 ext = 4;
3511 break;
3512 }
3513
3514 if (ext)
3515 {
3516 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3517 fragP->fr_fix += ext;
3518 }
3519 }
3520
3521 #ifndef BFD_ASSEMBLER
3522
3523 void
3524 md_convert_frag (headers, sec, fragP)
3525 object_headers *headers;
3526 segT sec;
3527 fragS *fragP;
3528 {
3529 md_convert_frag_1 (fragP);
3530 }
3531
3532 #else
3533
3534 void
3535 md_convert_frag (abfd, sec, fragP)
3536 bfd *abfd;
3537 segT sec;
3538 fragS *fragP;
3539 {
3540 md_convert_frag_1 (fragP);
3541 }
3542 #endif
3543
3544 /* Force truly undefined symbols to their maximum size, and generally set up
3545 the frag list to be relaxed
3546 */
3547 int
3548 md_estimate_size_before_relax (fragP, segment)
3549 register fragS *fragP;
3550 segT segment;
3551 {
3552 int old_fix;
3553 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3554
3555 old_fix = fragP->fr_fix;
3556
3557 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3558 switch (fragP->fr_subtype)
3559 {
3560
3561 case TAB (ABRANCH, SZ_UNDEF):
3562 {
3563 if ((fragP->fr_symbol != NULL) /* Not absolute */
3564 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3565 {
3566 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3567 break;
3568 }
3569 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3570 {
3571 /* On 68000, or for absolute value, switch to abs long */
3572 /* FIXME, we should check abs val, pick short or long */
3573 if (fragP->fr_opcode[0] == 0x61)
3574 {
3575 fragP->fr_opcode[0] = 0x4E;
3576 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3577 subseg_change (text_section, 0);
3578 fix_new (fragP, fragP->fr_fix, 4,
3579 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3580 fragP->fr_fix += 4;
3581 frag_wane (fragP);
3582 }
3583 else if (fragP->fr_opcode[0] == 0x60)
3584 {
3585 fragP->fr_opcode[0] = 0x4E;
3586 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3587 subseg_change (text_section, 0);
3588 fix_new (fragP, fragP->fr_fix, 4,
3589 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3590 fragP->fr_fix += 4;
3591 frag_wane (fragP);
3592 }
3593 else
3594 {
3595 as_warn ("Long branch offset to extern symbol not supported.");
3596 }
3597 }
3598 else
3599 { /* Symbol is still undefined. Make it simple */
3600 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3601 fragP->fr_offset, 1, NO_RELOC);
3602 fragP->fr_fix += 4;
3603 fragP->fr_opcode[1] = (char) 0xff;
3604 frag_wane (fragP);
3605 break;
3606 }
3607
3608 break;
3609 } /* case TAB(ABRANCH,SZ_UNDEF) */
3610
3611 case TAB (FBRANCH, SZ_UNDEF):
3612 {
3613 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3614 {
3615 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3616 fragP->fr_var += 2;
3617 }
3618 else
3619 {
3620 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3621 fragP->fr_offset, 1, NO_RELOC);
3622 fragP->fr_fix += 4;
3623 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3624 frag_wane (fragP);
3625 }
3626 break;
3627 } /* TAB(FBRANCH,SZ_UNDEF) */
3628
3629 case TAB (PCREL, SZ_UNDEF):
3630 {
3631 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3632 || flag_short_refs
3633 || cpu_of_arch (current_architecture) < m68020)
3634 {
3635 fragP->fr_subtype = TAB (PCREL, SHORT);
3636 fragP->fr_var += 2;
3637 }
3638 else
3639 {
3640 fragP->fr_subtype = TAB (PCREL, LONG);
3641 fragP->fr_var += 4;
3642 }
3643 break;
3644 } /* TAB(PCREL,SZ_UNDEF) */
3645
3646 case TAB (BCC68000, SZ_UNDEF):
3647 {
3648 if ((fragP->fr_symbol != NULL)
3649 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3650 {
3651 fragP->fr_subtype = TAB (BCC68000, BYTE);
3652 break;
3653 }
3654 /* only Bcc 68000 instructions can come here */
3655 /* change bcc into b!cc/jmp absl long */
3656 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3657 if (flag_short_refs)
3658 {
3659 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3660 /* JF: these were fr_opcode[2,3] */
3661 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3662 buffer_address[1] = (char) 0xf8;
3663 fragP->fr_fix += 2; /* account for jmp instruction */
3664 subseg_change (text_section, 0);
3665 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3666 fragP->fr_offset, 0, NO_RELOC);
3667 fragP->fr_fix += 2;
3668 }
3669 else
3670 {
3671 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3672 /* JF: these were fr_opcode[2,3] */
3673 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3674 buffer_address[1] = (char) 0xf9;
3675 fragP->fr_fix += 2; /* account for jmp instruction */
3676 subseg_change (text_section, 0);
3677 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3678 fragP->fr_offset, 0, NO_RELOC);
3679 fragP->fr_fix += 4;
3680 }
3681 frag_wane (fragP);
3682 break;
3683 } /* case TAB(BCC68000,SZ_UNDEF) */
3684
3685 case TAB (DBCC, SZ_UNDEF):
3686 {
3687 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3688 {
3689 fragP->fr_subtype = TAB (DBCC, SHORT);
3690 fragP->fr_var += 2;
3691 break;
3692 }
3693 /* only DBcc 68000 instructions can come here */
3694 /* change dbcc into dbcc/jmp absl long */
3695 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3696 buffer_address[0] = 0x00; /* branch offset = 4 */
3697 buffer_address[1] = 0x04;
3698 buffer_address[2] = 0x60; /* put in bra pc + ... */
3699
3700 if (flag_short_refs)
3701 {
3702 /* JF: these were fr_opcode[5-7] */
3703 buffer_address[3] = 0x04; /* plus 4 */
3704 buffer_address[4] = 0x4e; /* Put in Jump Word */
3705 buffer_address[5] = (char) 0xf8;
3706 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3707 subseg_change (text_section, 0);
3708 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3709 fragP->fr_offset, 0, NO_RELOC);
3710 fragP->fr_fix += 2;
3711 }
3712 else
3713 {
3714 /* JF: these were fr_opcode[5-7] */
3715 buffer_address[3] = 0x06; /* Plus 6 */
3716 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3717 buffer_address[5] = (char) 0xf9;
3718 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3719 subseg_change (text_section, 0);
3720 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3721 fragP->fr_offset, 0, NO_RELOC);
3722 fragP->fr_fix += 4;
3723 }
3724
3725 frag_wane (fragP);
3726 break;
3727 } /* case TAB(DBCC,SZ_UNDEF) */
3728
3729 case TAB (PCLEA, SZ_UNDEF):
3730 {
3731 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3732 || flag_short_refs
3733 || cpu_of_arch (current_architecture) < m68020)
3734 {
3735 fragP->fr_subtype = TAB (PCLEA, SHORT);
3736 fragP->fr_var += 2;
3737 }
3738 else
3739 {
3740 fragP->fr_subtype = TAB (PCLEA, LONG);
3741 fragP->fr_var += 6;
3742 }
3743 break;
3744 } /* TAB(PCLEA,SZ_UNDEF) */
3745
3746 case TAB (PCINDEX, SZ_UNDEF):
3747 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3748 || cpu_of_arch (current_architecture) < m68020)
3749 {
3750 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3751 }
3752 else
3753 {
3754 fragP->fr_subtype = TAB (PCINDEX, LONG);
3755 fragP->fr_var += 4;
3756 }
3757 break;
3758
3759 default:
3760 break;
3761 }
3762
3763 /* now that SZ_UNDEF are taken care of, check others */
3764 switch (fragP->fr_subtype)
3765 {
3766 case TAB (BCC68000, BYTE):
3767 case TAB (ABRANCH, BYTE):
3768 /* We can't do a short jump to the next instruction,
3769 so we force word mode. */
3770 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3771 fragP->fr_symbol->sy_frag == fragP->fr_next)
3772 {
3773 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3774 fragP->fr_var += 2;
3775 }
3776 break;
3777 default:
3778 break;
3779 }
3780 return fragP->fr_var + fragP->fr_fix - old_fix;
3781 }
3782
3783 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3784 /* the bit-field entries in the relocation_info struct plays hell
3785 with the byte-order problems of cross-assembly. So as a hack,
3786 I added this mach. dependent ri twiddler. Ugly, but it gets
3787 you there. -KWK */
3788 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3789 are symbolnum, most sig. byte first. Last byte is broken up with
3790 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3791 nibble as nuthin. (on Sun 3 at least) */
3792 /* Translate the internal relocation information into target-specific
3793 format. */
3794 #ifdef comment
3795 void
3796 md_ri_to_chars (the_bytes, ri)
3797 char *the_bytes;
3798 struct reloc_info_generic *ri;
3799 {
3800 /* this is easy */
3801 md_number_to_chars (the_bytes, ri->r_address, 4);
3802 /* now the fun stuff */
3803 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3804 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3805 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3806 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3807 ((ri->r_extern << 4) & 0x10));
3808 }
3809
3810 #endif /* comment */
3811
3812 #ifndef BFD_ASSEMBLER
3813 void
3814 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3815 char *where;
3816 fixS *fixP;
3817 relax_addressT segment_address_in_file;
3818 {
3819 /*
3820 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3821 * Out: GNU LD relocation length code: 0, 1, or 2.
3822 */
3823
3824 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3825 long r_symbolnum;
3826
3827 know (fixP->fx_addsy != NULL);
3828
3829 md_number_to_chars (where,
3830 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3831 4);
3832
3833 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3834 ? S_GET_TYPE (fixP->fx_addsy)
3835 : fixP->fx_addsy->sy_number);
3836
3837 where[4] = (r_symbolnum >> 16) & 0x0ff;
3838 where[5] = (r_symbolnum >> 8) & 0x0ff;
3839 where[6] = r_symbolnum & 0x0ff;
3840 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3841 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3842 }
3843 #endif
3844
3845 #endif /* OBJ_AOUT or OBJ_BOUT */
3846
3847 #ifndef WORKING_DOT_WORD
3848 CONST int md_short_jump_size = 4;
3849 CONST int md_long_jump_size = 6;
3850
3851 void
3852 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3853 char *ptr;
3854 addressT from_addr, to_addr;
3855 fragS *frag;
3856 symbolS *to_symbol;
3857 {
3858 valueT offset;
3859
3860 offset = to_addr - (from_addr + 2);
3861
3862 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3863 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3864 }
3865
3866 void
3867 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3868 char *ptr;
3869 addressT from_addr, to_addr;
3870 fragS *frag;
3871 symbolS *to_symbol;
3872 {
3873 valueT offset;
3874
3875 if (cpu_of_arch (current_architecture) < m68020)
3876 {
3877 offset = to_addr - S_GET_VALUE (to_symbol);
3878 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3879 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3880 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3881 0, NO_RELOC);
3882 }
3883 else
3884 {
3885 offset = to_addr - (from_addr + 2);
3886 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3887 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3888 }
3889 }
3890
3891 #endif
3892
3893 /* Different values of OK tell what its OK to return. Things that
3894 aren't OK are an error (what a shock, no?)
3895
3896 0: Everything is OK
3897 10: Absolute 1:8 only
3898 20: Absolute 0:7 only
3899 30: absolute 0:15 only
3900 40: Absolute 0:31 only
3901 50: absolute 0:127 only
3902 55: absolute -64:63 only
3903 60: absolute -128:127 only
3904 70: absolute 0:4095 only
3905 80: No bignums
3906
3907 */
3908
3909 static int
3910 get_num (exp, ok)
3911 struct m68k_exp *exp;
3912 int ok;
3913 {
3914 if (exp->exp.X_op == O_absent)
3915 {
3916 /* Do the same thing the VAX asm does */
3917 op (exp) = O_constant;
3918 adds (exp) = 0;
3919 subs (exp) = 0;
3920 offs (exp) = 0;
3921 if (ok == 10)
3922 {
3923 as_warn ("expression out of range: defaulting to 1");
3924 offs (exp) = 1;
3925 }
3926 }
3927 else if (exp->exp.X_op == O_constant)
3928 {
3929 switch (ok)
3930 {
3931 case 10:
3932 if (offs (exp) < 1 || offs (exp) > 8)
3933 {
3934 as_warn ("expression out of range: defaulting to 1");
3935 offs (exp) = 1;
3936 }
3937 break;
3938 case 20:
3939 if (offs (exp) < 0 || offs (exp) > 7)
3940 goto outrange;
3941 break;
3942 case 30:
3943 if (offs (exp) < 0 || offs (exp) > 15)
3944 goto outrange;
3945 break;
3946 case 40:
3947 if (offs (exp) < 0 || offs (exp) > 32)
3948 goto outrange;
3949 break;
3950 case 50:
3951 if (offs (exp) < 0 || offs (exp) > 127)
3952 goto outrange;
3953 break;
3954 case 55:
3955 if (offs (exp) < -64 || offs (exp) > 63)
3956 goto outrange;
3957 break;
3958 case 60:
3959 if (offs (exp) < -128 || offs (exp) > 127)
3960 goto outrange;
3961 break;
3962 case 70:
3963 if (offs (exp) < 0 || offs (exp) > 4095)
3964 {
3965 outrange:
3966 as_warn ("expression out of range: defaulting to 0");
3967 offs (exp) = 0;
3968 }
3969 break;
3970 default:
3971 break;
3972 }
3973 }
3974 else if (exp->exp.X_op == O_big)
3975 {
3976 if (offs (exp) <= 0 /* flonum */
3977 && (ok == 80 /* no bignums */
3978 || (ok > 10 /* small-int ranges including 0 ok */
3979 /* If we have a flonum zero, a zero integer should
3980 do as well (e.g., in moveq). */
3981 && generic_floating_point_number.exponent == 0
3982 && generic_floating_point_number.low[0] == 0)))
3983 {
3984 /* HACK! Turn it into a long */
3985 LITTLENUM_TYPE words[6];
3986
3987 gen_to_words (words, 2, 8L); /* These numbers are magic! */
3988 op (exp) = O_constant;
3989 adds (exp) = 0;
3990 subs (exp) = 0;
3991 offs (exp) = words[1] | (words[0] << 16);
3992 }
3993 else if (ok != 0)
3994 {
3995 op (exp) = O_constant;
3996 adds (exp) = 0;
3997 subs (exp) = 0;
3998 offs (exp) = (ok == 10) ? 1 : 0;
3999 as_warn ("Can't deal with expression; defaulting to %ld",
4000 offs (exp));
4001 }
4002 }
4003 else
4004 {
4005 if (ok >= 10 && ok <= 70)
4006 {
4007 op (exp) = O_constant;
4008 adds (exp) = 0;
4009 subs (exp) = 0;
4010 offs (exp) = (ok == 10) ? 1 : 0;
4011 as_warn ("Can't deal with expression; defaulting to %ld",
4012 offs (exp));
4013 }
4014 }
4015
4016 if (exp->size != SIZE_UNSPEC)
4017 {
4018 switch (exp->size)
4019 {
4020 case SIZE_UNSPEC:
4021 case SIZE_LONG:
4022 break;
4023 case SIZE_BYTE:
4024 if (!isbyte (offs (exp)))
4025 as_warn ("expression doesn't fit in BYTE");
4026 break;
4027 case SIZE_WORD:
4028 if (!isword (offs (exp)))
4029 as_warn ("expression doesn't fit in WORD");
4030 break;
4031 }
4032 }
4033
4034 return offs (exp);
4035 }
4036
4037 /* These are the back-ends for the various machine dependent pseudo-ops. */
4038 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4039
4040 static void
4041 s_data1 (ignore)
4042 int ignore;
4043 {
4044 subseg_set (data_section, 1);
4045 demand_empty_rest_of_line ();
4046 }
4047
4048 static void
4049 s_data2 (ignore)
4050 int ignore;
4051 {
4052 subseg_set (data_section, 2);
4053 demand_empty_rest_of_line ();
4054 }
4055
4056 static void
4057 s_bss (ignore)
4058 int ignore;
4059 {
4060 /* We don't support putting frags in the BSS segment, we fake it
4061 by marking in_bss, then looking at s_skip for clues. */
4062
4063 subseg_set (bss_section, 0);
4064 demand_empty_rest_of_line ();
4065 }
4066
4067 static void
4068 s_even (ignore)
4069 int ignore;
4070 {
4071 register int temp;
4072 register long temp_fill;
4073
4074 temp = 1; /* JF should be 2? */
4075 temp_fill = get_absolute_expression ();
4076 if (!need_pass_2) /* Never make frag if expect extra pass. */
4077 frag_align (temp, (int) temp_fill);
4078 demand_empty_rest_of_line ();
4079 }
4080
4081 static void
4082 s_proc (ignore)
4083 int ignore;
4084 {
4085 demand_empty_rest_of_line ();
4086 }
4087 \f
4088 /* Pseudo-ops handled for MRI compatibility. */
4089
4090 /* Handle an MRI style chip specification. */
4091
4092 static void
4093 mri_chip ()
4094 {
4095 char *s;
4096 char c;
4097 int i;
4098
4099 s = input_line_pointer;
4100 c = get_symbol_end ();
4101 for (i = 0; i < n_archs; i++)
4102 if (strcasecmp (s, archs[i].name) == 0)
4103 break;
4104 if (i >= n_archs)
4105 {
4106 as_bad ("%s: unrecognized processor name", s);
4107 *input_line_pointer = c;
4108 ignore_rest_of_line ();
4109 return;
4110 }
4111 *input_line_pointer = c;
4112
4113 if (*input_line_pointer == '/')
4114 current_architecture = 0;
4115 else
4116 current_architecture &= m68881 | m68851;
4117 current_architecture |= archs[i].arch;
4118
4119 while (*input_line_pointer == '/')
4120 {
4121 ++input_line_pointer;
4122 s = input_line_pointer;
4123 c = get_symbol_end ();
4124 if (strcmp (s, "68881") == 0)
4125 current_architecture |= m68881;
4126 else if (strcmp (s, "68851") == 0)
4127 current_architecture |= m68851;
4128 *input_line_pointer = c;
4129 }
4130 }
4131
4132 /* The MRI CHIP pseudo-op. */
4133
4134 static void
4135 s_chip (ignore)
4136 int ignore;
4137 {
4138 mri_chip ();
4139 demand_empty_rest_of_line ();
4140 }
4141
4142 /* The MRI FOPT pseudo-op. */
4143
4144 static void
4145 s_fopt (ignore)
4146 int ignore;
4147 {
4148 SKIP_WHITESPACE ();
4149
4150 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4151 {
4152 int temp;
4153
4154 input_line_pointer += 3;
4155 temp = get_absolute_expression ();
4156 if (temp < 0 || temp > 7)
4157 as_bad ("bad coprocessor id");
4158 else
4159 m68k_float_copnum = COP0 + temp;
4160 }
4161 else
4162 {
4163 as_bad ("unrecognized fopt option");
4164 ignore_rest_of_line ();
4165 return;
4166 }
4167
4168 demand_empty_rest_of_line ();
4169 }
4170
4171 /* The structure used to handle the MRI OPT pseudo-op. */
4172
4173 struct opt_action
4174 {
4175 /* The name of the option. */
4176 const char *name;
4177
4178 /* If this is not NULL, just call this function. The first argument
4179 is the ARG field of this structure, the second argument is
4180 whether the option was negated. */
4181 void (*pfn) PARAMS ((int arg, int on));
4182
4183 /* If this is not NULL, and the PFN field is NULL, set the variable
4184 this points to. Set it to the ARG field if the option was not
4185 negated, and the NOTARG field otherwise. */
4186 int *pvar;
4187
4188 /* The value to pass to PFN or to assign to *PVAR. */
4189 int arg;
4190
4191 /* The value to assign to *PVAR if the option is negated. If PFN is
4192 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4193 the option may not be negated. */
4194 int notarg;
4195 };
4196
4197 /* The table used to handle the MRI OPT pseudo-op. */
4198
4199 static void skip_to_comma PARAMS ((int, int));
4200 static void opt_chip PARAMS ((int, int));
4201 static void opt_list PARAMS ((int, int));
4202 static void opt_list_symbols PARAMS ((int, int));
4203
4204 static const struct opt_action opt_table[] =
4205 {
4206 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4207
4208 /* We do relaxing, so there is little use for these options. */
4209 { "b", 0, 0, 0, 0 },
4210 { "brs", 0, 0, 0, 0 },
4211 { "brb", 0, 0, 0, 0 },
4212 { "brl", 0, 0, 0, 0 },
4213 { "brw", 0, 0, 0, 0 },
4214
4215 { "c", 0, 0, 0, 0 },
4216 { "cex", 0, 0, 0, 0 },
4217 { "case", 0, &symbols_case_sensitive, 1, 0 },
4218 { "cl", 0, 0, 0, 0 },
4219 { "cre", 0, 0, 0, 0 },
4220 { "d", 0, &flag_keep_locals, 1, 0 },
4221 { "e", 0, 0, 0, 0 },
4222 { "f", 0, &flag_short_refs, 1, 0 },
4223 { "frs", 0, &flag_short_refs, 1, 0 },
4224 { "frl", 0, &flag_short_refs, 0, 1 },
4225 { "g", 0, 0, 0, 0 },
4226 { "i", 0, 0, 0, 0 },
4227 { "m", 0, 0, 0, 0 },
4228 { "mex", 0, 0, 0, 0 },
4229 { "mc", 0, 0, 0, 0 },
4230 { "md", 0, 0, 0, 0 },
4231 { "next", skip_to_comma, 0, 0, 0 },
4232 { "o", 0, 0, 0, 0 },
4233 { "old", 0, 0, 0, 0 },
4234 { "op", skip_to_comma, 0, 0, 0 },
4235 { "pco", 0, 0, 0, 0 },
4236 { "p", opt_chip, 0, 0, 0 },
4237 { "pcr", 0, 0, 0, 0 },
4238 { "pcs", 0, 0, 0, 0 },
4239 { "r", 0, 0, 0, 0 },
4240 { "quick", 0, &m68k_quick, 1, 0 },
4241 { "rel32", 0, &m68k_rel32, 1, 0 },
4242 { "s", opt_list, 0, 0, 0 },
4243 { "t", opt_list_symbols, 0, 0, 0 },
4244 { "w", 0, &flag_no_warnings, 0, 1 },
4245 { "x", 0, 0, 0, 0 }
4246 };
4247
4248 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4249
4250 /* The MRI OPT pseudo-op. */
4251
4252 static void
4253 s_opt (ignore)
4254 int ignore;
4255 {
4256 do
4257 {
4258 int t;
4259 char *s;
4260 char c;
4261 int i;
4262 const struct opt_action *o;
4263
4264 SKIP_WHITESPACE ();
4265
4266 t = 1;
4267 if (*input_line_pointer == '-')
4268 {
4269 ++input_line_pointer;
4270 t = 0;
4271 }
4272 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4273 {
4274 input_line_pointer += 2;
4275 t = 0;
4276 }
4277
4278 s = input_line_pointer;
4279 c = get_symbol_end ();
4280
4281 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4282 {
4283 if (strcasecmp (s, o->name) == 0)
4284 {
4285 if (o->pfn)
4286 {
4287 /* Restore input_line_pointer now in case the option
4288 takes arguments. */
4289 *input_line_pointer = c;
4290 (*o->pfn) (o->arg, t);
4291 }
4292 else if (o->pvar != NULL)
4293 {
4294 if (! t && o->arg == o->notarg)
4295 as_bad ("option `%s' may not be negated", s);
4296 *input_line_pointer = c;
4297 *o->pvar = t ? o->arg : o->notarg;
4298 }
4299 break;
4300 }
4301 }
4302 if (i >= OPTCOUNT)
4303 {
4304 as_bad ("option `%s' not recognized", s);
4305 *input_line_pointer = c;
4306 }
4307 }
4308 while (*input_line_pointer++ == ',');
4309
4310 /* Move back to terminating character. */
4311 --input_line_pointer;
4312 demand_empty_rest_of_line ();
4313 }
4314
4315 /* Skip ahead to a comma. This is used for OPT options which we do
4316 not suppor tand which take arguments. */
4317
4318 static void
4319 skip_to_comma (arg, on)
4320 int arg;
4321 int on;
4322 {
4323 while (*input_line_pointer != ','
4324 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4325 ++input_line_pointer;
4326 }
4327
4328 /* Handle the OPT P=chip option. */
4329
4330 static void
4331 opt_chip (arg, on)
4332 int arg;
4333 int on;
4334 {
4335 if (*input_line_pointer != '=')
4336 {
4337 /* This is just OPT P, which we do not support. */
4338 return;
4339 }
4340
4341 ++input_line_pointer;
4342 mri_chip ();
4343 }
4344
4345 /* Handle the OPT S option. */
4346
4347 static void
4348 opt_list (arg, on)
4349 int arg;
4350 int on;
4351 {
4352 listing_list (on);
4353 }
4354
4355 /* Handle the OPT T option. */
4356
4357 static void
4358 opt_list_symbols (arg, on)
4359 int arg;
4360 int on;
4361 {
4362 if (on)
4363 listing |= LISTING_SYMBOLS;
4364 else
4365 listing &=~ LISTING_SYMBOLS;
4366 }
4367
4368 /* Handle the MRI REG pseudo-op. */
4369
4370 static void
4371 s_reg (ignore)
4372 int ignore;
4373 {
4374 char *s;
4375 int c;
4376 struct m68k_op op;
4377 unsigned long mask;
4378
4379 if (mri_line_label == NULL)
4380 {
4381 as_bad ("missing label");
4382 ignore_rest_of_line ();
4383 return;
4384 }
4385
4386 SKIP_WHITESPACE ();
4387
4388 s = input_line_pointer;
4389 while (isalnum ((unsigned char) *input_line_pointer)
4390 #ifdef REGISTER_PREFIX
4391 || *input_line_pointer == REGISTER_PREFIX
4392 #endif
4393 || *input_line_pointer == '/'
4394 || *input_line_pointer == '-')
4395 ++input_line_pointer;
4396 c = *input_line_pointer;
4397 *input_line_pointer = '\0';
4398
4399 if (m68k_ip_op (s, &op) != 0)
4400 {
4401 if (op.error == NULL)
4402 as_bad ("bad register list");
4403 else
4404 as_bad ("bad register list: %s", op.error);
4405 *input_line_pointer = c;
4406 ignore_rest_of_line ();
4407 return;
4408 }
4409
4410 *input_line_pointer = c;
4411
4412 if (op.mode == REGLST)
4413 mask = op.mask;
4414 else if (op.mode == DREG)
4415 mask = 1 << (op.reg - DATA0);
4416 else if (op.mode == AREG)
4417 mask = 1 << (op.reg - ADDR0 + 8);
4418 else if (op.mode == FPREG)
4419 mask = 1 << (op.reg - FP0 + 16);
4420 else if (op.mode == CONTROL
4421 && op.reg == FPI)
4422 mask = 1 << 24;
4423 else if (op.mode == CONTROL
4424 && op.reg == FPS)
4425 mask = 1 << 25;
4426 else if (op.mode == CONTROL
4427 && op.reg == FPC)
4428 mask = 1 << 26;
4429 else
4430 {
4431 as_bad ("bad register list");
4432 ignore_rest_of_line ();
4433 return;
4434 }
4435
4436 S_SET_SEGMENT (mri_line_label, absolute_section);
4437 S_SET_VALUE (mri_line_label, mask);
4438 mri_line_label->sy_frag = &zero_address_frag;
4439
4440 demand_empty_rest_of_line ();
4441 }
4442
4443 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4444
4445 struct save_opts
4446 {
4447 struct save_opts *next;
4448 int abspcadd;
4449 int symbols_case_sensitive;
4450 int keep_locals;
4451 int short_refs;
4452 int architecture;
4453 int quick;
4454 int rel32;
4455 int listing;
4456 int no_warnings;
4457 /* FIXME: We don't save OPT S. */
4458 };
4459
4460 /* This variable holds the stack of saved options. */
4461
4462 static struct save_opts *save_stack;
4463
4464 /* The MRI SAVE pseudo-op. */
4465
4466 static void
4467 s_save (ignore)
4468 int ignore;
4469 {
4470 struct save_opts *s;
4471
4472 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4473 s->abspcadd = m68k_abspcadd;
4474 s->symbols_case_sensitive = symbols_case_sensitive;
4475 s->keep_locals = flag_keep_locals;
4476 s->short_refs = flag_short_refs;
4477 s->architecture = current_architecture;
4478 s->quick = m68k_quick;
4479 s->rel32 = m68k_rel32;
4480 s->listing = listing;
4481 s->no_warnings = flag_no_warnings;
4482
4483 s->next = save_stack;
4484 save_stack = s;
4485
4486 demand_empty_rest_of_line ();
4487 }
4488
4489 /* The MRI RESTORE pseudo-op. */
4490
4491 static void
4492 s_restore (ignore)
4493 int ignore;
4494 {
4495 struct save_opts *s;
4496
4497 if (save_stack == NULL)
4498 {
4499 as_bad ("restore without save");
4500 ignore_rest_of_line ();
4501 return;
4502 }
4503
4504 s = save_stack;
4505 save_stack = s->next;
4506
4507 m68k_abspcadd = s->abspcadd;
4508 symbols_case_sensitive = s->symbols_case_sensitive;
4509 flag_keep_locals = s->keep_locals;
4510 flag_short_refs = s->short_refs;
4511 current_architecture = s->architecture;
4512 m68k_quick = s->quick;
4513 m68k_rel32 = s->rel32;
4514 listing = s->listing;
4515 flag_no_warnings = s->no_warnings;
4516
4517 free (s);
4518
4519 demand_empty_rest_of_line ();
4520 }
4521 \f
4522 /*
4523 * md_parse_option
4524 * Invocation line includes a switch not recognized by the base assembler.
4525 * See if it's a processor-specific option. These are:
4526 *
4527 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4528 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4529 * Select the architecture. Instructions or features not
4530 * supported by the selected architecture cause fatal
4531 * errors. More than one may be specified. The default is
4532 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4533 * for -m68000, and -m68882 is a synonym for -m68881.
4534 * -[A]m[c]no-68851, -[A]m[c]no-68881
4535 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4536 * so don't use or document it, but that's the way the parsing
4537 * works).
4538 *
4539 * -pic Indicates PIC.
4540 * -k Indicates PIC. (Sun 3 only.)
4541 *
4542 */
4543
4544 #ifdef OBJ_ELF
4545 CONST char *md_shortopts = "lSA:m:kQ:V";
4546 #else
4547 CONST char *md_shortopts = "lSA:m:k";
4548 #endif
4549
4550 struct option md_longopts[] = {
4551 #define OPTION_PIC (OPTION_MD_BASE)
4552 {"pic", no_argument, NULL, OPTION_PIC},
4553 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4554 {"register-prefix-optional", no_argument, NULL,
4555 OPTION_REGISTER_PREFIX_OPTIONAL},
4556 {NULL, no_argument, NULL, 0}
4557 };
4558 size_t md_longopts_size = sizeof(md_longopts);
4559
4560 int
4561 md_parse_option (c, arg)
4562 int c;
4563 char *arg;
4564 {
4565 switch (c)
4566 {
4567 case 'l': /* -l means keep external to 2 bit offset
4568 rather than 16 bit one */
4569 flag_short_refs = 1;
4570 break;
4571
4572 case 'S': /* -S means that jbsr's always turn into
4573 jsr's. */
4574 flag_long_jumps = 1;
4575 break;
4576
4577 case 'A':
4578 if (*arg == 'm')
4579 arg++;
4580 /* intentional fall-through */
4581 case 'm':
4582
4583 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
4584 {
4585 int i;
4586 unsigned long arch;
4587 const char *oarg = arg;
4588
4589 arg += 3;
4590 if (*arg == 'm')
4591 {
4592 arg++;
4593 if (arg[0] == 'c' && arg[1] == '6')
4594 arg++;
4595 }
4596 for (i = 0; i < n_archs; i++)
4597 if (!strcmp (arg, archs[i].name))
4598 break;
4599 if (i == n_archs)
4600 {
4601 unknown:
4602 as_bad ("unrecognized option `%s'", oarg);
4603 return 0;
4604 }
4605 arch = archs[i].arch;
4606 if (arch == m68881)
4607 no_68881 = 1;
4608 else if (arch == m68851)
4609 no_68851 = 1;
4610 else
4611 goto unknown;
4612 }
4613 else
4614 {
4615 int i;
4616
4617 if (arg[0] == 'c' && arg[1] == '6')
4618 arg++;
4619
4620 for (i = 0; i < n_archs; i++)
4621 if (!strcmp (arg, archs[i].name))
4622 {
4623 unsigned long arch = archs[i].arch;
4624 if (cpu_of_arch (arch))
4625 /* It's a cpu spec. */
4626 {
4627 current_architecture &= ~m68000up;
4628 current_architecture |= arch;
4629 }
4630 else if (arch == m68881)
4631 {
4632 current_architecture |= m68881;
4633 no_68881 = 0;
4634 }
4635 else if (arch == m68851)
4636 {
4637 current_architecture |= m68851;
4638 no_68851 = 0;
4639 }
4640 else
4641 /* ??? */
4642 abort ();
4643 break;
4644 }
4645 if (i == n_archs)
4646 {
4647 as_bad ("unrecognized architecture specification `%s'", arg);
4648 return 0;
4649 }
4650 }
4651 break;
4652
4653 case OPTION_PIC:
4654 case 'k':
4655 flag_want_pic = 1;
4656 break; /* -pic, Position Independent Code */
4657
4658 case OPTION_REGISTER_PREFIX_OPTIONAL:
4659 flag_reg_prefix_optional = 1;
4660 break;
4661
4662 case 'Q':
4663 case 'V':
4664 break;
4665
4666 default:
4667 return 0;
4668 }
4669
4670 return 1;
4671 }
4672
4673 void
4674 md_show_usage (stream)
4675 FILE *stream;
4676 {
4677 fprintf(stream, "\
4678 680X0 options:\n\
4679 -l use 1 word for refs to undefined symbols [default 2]\n\
4680 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
4681 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
4682 | -mcpu32\n\
4683 specify variant of 680X0 architecture [default 68020]\n\
4684 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
4685 target has/lacks floating-point coprocessor\n\
4686 [default yes for 68020, 68030, and cpu32]\n\
4687 -m68851 | -mno-68851\n\
4688 target has/lacks memory-management unit coprocessor\n\
4689 [default yes for 68020 and up]\n\
4690 -pic, -k generate position independent code\n\
4691 -S turn jbsr into jsr\n\
4692 --register-prefix-optional\n\
4693 recognize register names without prefix character\n");
4694 }
4695 \f
4696 #ifdef TEST2
4697
4698 /* TEST2: Test md_assemble() */
4699 /* Warning, this routine probably doesn't work anymore */
4700
4701 main ()
4702 {
4703 struct m68k_it the_ins;
4704 char buf[120];
4705 char *cp;
4706 int n;
4707
4708 m68k_ip_begin ();
4709 for (;;)
4710 {
4711 if (!gets (buf) || !*buf)
4712 break;
4713 if (buf[0] == '|' || buf[1] == '.')
4714 continue;
4715 for (cp = buf; *cp; cp++)
4716 if (*cp == '\t')
4717 *cp = ' ';
4718 if (is_label (buf))
4719 continue;
4720 memset (&the_ins, '\0', sizeof (the_ins));
4721 m68k_ip (&the_ins, buf);
4722 if (the_ins.error)
4723 {
4724 printf ("Error %s in %s\n", the_ins.error, buf);
4725 }
4726 else
4727 {
4728 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4729 for (n = 0; n < the_ins.numo; n++)
4730 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4731 printf (" ");
4732 print_the_insn (&the_ins.opcode[0], stdout);
4733 (void) putchar ('\n');
4734 }
4735 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4736 {
4737 if (the_ins.operands[n].error)
4738 {
4739 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4740 continue;
4741 }
4742 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4743 if (the_ins.operands[n].b_const)
4744 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4745 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4746 if (the_ins.operands[n].b_iadd)
4747 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4748 (void) putchar ('\n');
4749 }
4750 }
4751 m68k_ip_end ();
4752 return 0;
4753 }
4754
4755 is_label (str)
4756 char *str;
4757 {
4758 while (*str == ' ')
4759 str++;
4760 while (*str && *str != ' ')
4761 str++;
4762 if (str[-1] == ':' || str[1] == '=')
4763 return 1;
4764 return 0;
4765 }
4766
4767 #endif
4768
4769 /* Possible states for relaxation:
4770
4771 0 0 branch offset byte (bra, etc)
4772 0 1 word
4773 0 2 long
4774
4775 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4776 1 1 word
4777 1 2 long
4778
4779 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4780 2 1 word-long
4781 2 2 long-word
4782 2 3 long-long
4783
4784 */
4785
4786 /* We have no need to default values of symbols. */
4787
4788 /* ARGSUSED */
4789 symbolS *
4790 md_undefined_symbol (name)
4791 char *name;
4792 {
4793 return 0;
4794 }
4795
4796 /* Round up a section size to the appropriate boundary. */
4797 valueT
4798 md_section_align (segment, size)
4799 segT segment;
4800 valueT size;
4801 {
4802 return size; /* Byte alignment is fine */
4803 }
4804
4805 /* Exactly what point is a PC-relative offset relative TO?
4806 On the 68k, it is relative to the address of the first extension
4807 word. The difference between the addresses of the offset and the
4808 first extension word is stored in fx_pcrel_adjust. */
4809 long
4810 md_pcrel_from (fixP)
4811 fixS *fixP;
4812 {
4813 return (fixP->fx_where + fixP->fx_frag->fr_address - fixP->fx_pcrel_adjust);
4814 }
4815
4816 #ifndef BFD_ASSEMBLER
4817 /*ARGSUSED*/
4818 void
4819 tc_coff_symbol_emit_hook (ignore)
4820 symbolS *ignore;
4821 {
4822 }
4823
4824 int
4825 tc_coff_sizemachdep (frag)
4826 fragS *frag;
4827 {
4828 switch (frag->fr_subtype & 0x3)
4829 {
4830 case BYTE:
4831 return 1;
4832 case SHORT:
4833 return 2;
4834 case LONG:
4835 return 4;
4836 default:
4837 abort ();
4838 return 0;
4839 }
4840 }
4841 #endif
4842
4843 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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