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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
181 0
182 };
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
189 0
190 };
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
193 0
194 };
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52235_ctrl[] = {
200 VBR, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf5225_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5249_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
213 0
214 };
215 static const enum m68k_register mcf5250_ctrl[] = {
216 VBR,
217 0
218 };
219 static const enum m68k_register mcf5271_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
221 0
222 };
223 static const enum m68k_register mcf5272_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
225 0
226 };
227 static const enum m68k_register mcf5275_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
229 0
230 };
231 static const enum m68k_register mcf5282_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
233 0
234 };
235 static const enum m68k_register mcf5307_ctrl[] = {
236 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
237 0
238 };
239 static const enum m68k_register mcf5329_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5373_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
245 0
246 };
247 static const enum m68k_register mcfv4e_ctrl[] = {
248 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
249 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
250 MBAR, SECMBAR,
251 MPCR /* Multiprocessor Control register */,
252 EDRAMBAR /* Embedded DRAM Base Address Register */,
253 /* Permutation control registers. */
254 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
255 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
256 /* Legacy names */
257 TC /* ASID */, BUSCR /* MMUBAR */,
258 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
259 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
260 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
261 0
262 };
263 static const enum m68k_register mcf5475_ctrl[] = {
264 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
265 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
266 /* Legacy names */
267 TC /* ASID */, BUSCR /* MMUBAR */,
268 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
269 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
270 0
271 };
272 static const enum m68k_register mcf5485_ctrl[] = {
273 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
274 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
275 /* Legacy names */
276 TC /* ASID */, BUSCR /* MMUBAR */,
277 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
278 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
279 0
280 };
281 static const enum m68k_register fido_ctrl[] = {
282 SFC, DFC, USP, VBR, CAC, MBB,
283 0
284 };
285 #define cpu32_ctrl m68010_ctrl
286
287 static const enum m68k_register *control_regs;
288
289 /* Internal form of a 68020 instruction. */
290 struct m68k_it
291 {
292 const char *error;
293 const char *args; /* List of opcode info. */
294 int numargs;
295
296 int numo; /* Number of shorts in opcode. */
297 short opcode[11];
298
299 struct m68k_op operands[6];
300
301 int nexp; /* Number of exprs in use. */
302 struct m68k_exp exprs[4];
303
304 int nfrag; /* Number of frags we have to produce. */
305 struct
306 {
307 int fragoff; /* Where in the current opcode the frag ends. */
308 symbolS *fadd;
309 offsetT foff;
310 int fragty;
311 }
312 fragb[4];
313
314 int nrel; /* Num of reloc strucs in use. */
315 struct
316 {
317 int n;
318 expressionS exp;
319 char wid;
320 char pcrel;
321 /* In a pc relative address the difference between the address
322 of the offset and the address that the offset is relative
323 to. This depends on the addressing mode. Basically this
324 is the value to put in the offset field to address the
325 first byte of the offset, without regarding the special
326 significance of some values (in the branch instruction, for
327 example). */
328 int pcrel_fix;
329 #ifdef OBJ_ELF
330 /* Whether this expression needs special pic relocation, and if
331 so, which. */
332 enum pic_relocation pic_reloc;
333 #endif
334 }
335 reloc[5]; /* Five is enough??? */
336 };
337
338 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
339 #define float_of_arch(x) ((x) & mfloat)
340 #define mmu_of_arch(x) ((x) & mmmu)
341 #define arch_coldfire_p(x) ((x) & mcfisa_a)
342 #define arch_coldfire_fpu(x) ((x) & cfloat)
343
344 /* Macros for determining if cpu supports a specific addressing mode. */
345 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
346
347 static struct m68k_it the_ins; /* The instruction being assembled. */
348
349 #define op(ex) ((ex)->exp.X_op)
350 #define adds(ex) ((ex)->exp.X_add_symbol)
351 #define subs(ex) ((ex)->exp.X_op_symbol)
352 #define offs(ex) ((ex)->exp.X_add_number)
353
354 /* Macros for adding things to the m68k_it struct. */
355 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
356
357 /* Like addword, but goes BEFORE general operands. */
358
359 static void
360 insop (int w, const struct m68k_incant *opcode)
361 {
362 int z;
363 for (z = the_ins.numo; z > opcode->m_codenum; --z)
364 the_ins.opcode[z] = the_ins.opcode[z - 1];
365 for (z = 0; z < the_ins.nrel; z++)
366 the_ins.reloc[z].n += 2;
367 for (z = 0; z < the_ins.nfrag; z++)
368 the_ins.fragb[z].fragoff++;
369 the_ins.opcode[opcode->m_codenum] = w;
370 the_ins.numo++;
371 }
372
373 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
374 Blecch. */
375 static void
376 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
377 {
378 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
379 ? the_ins.numo * 2 - 1
380 : (width == 'b'
381 ? the_ins.numo * 2 + 1
382 : the_ins.numo * 2));
383 the_ins.reloc[the_ins.nrel].exp = exp->exp;
384 the_ins.reloc[the_ins.nrel].wid = width;
385 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
386 #ifdef OBJ_ELF
387 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
388 #endif
389 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
390 }
391
392 /* Cause an extra frag to be generated here, inserting up to 10 bytes
393 (that value is chosen in the frag_var call in md_assemble). TYPE
394 is the subtype of the frag to be generated; its primary type is
395 rs_machine_dependent.
396
397 The TYPE parameter is also used by md_convert_frag_1 and
398 md_estimate_size_before_relax. The appropriate type of fixup will
399 be emitted by md_convert_frag_1.
400
401 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
402 static void
403 add_frag (symbolS *add, offsetT off, int type)
404 {
405 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
406 the_ins.fragb[the_ins.nfrag].fadd = add;
407 the_ins.fragb[the_ins.nfrag].foff = off;
408 the_ins.fragb[the_ins.nfrag++].fragty = type;
409 }
410
411 #define isvar(ex) \
412 (op (ex) != O_constant && op (ex) != O_big)
413
414 static char *crack_operand (char *str, struct m68k_op *opP);
415 static int get_num (struct m68k_exp *exp, int ok);
416 static int reverse_16_bits (int in);
417 static int reverse_8_bits (int in);
418 static void install_gen_operand (int mode, int val);
419 static void install_operand (int mode, int val);
420 static void s_bss (int);
421 static void s_data1 (int);
422 static void s_data2 (int);
423 static void s_even (int);
424 static void s_proc (int);
425 static void s_chip (int);
426 static void s_fopt (int);
427 static void s_opt (int);
428 static void s_reg (int);
429 static void s_restore (int);
430 static void s_save (int);
431 static void s_mri_if (int);
432 static void s_mri_else (int);
433 static void s_mri_endi (int);
434 static void s_mri_break (int);
435 static void s_mri_next (int);
436 static void s_mri_for (int);
437 static void s_mri_endf (int);
438 static void s_mri_repeat (int);
439 static void s_mri_until (int);
440 static void s_mri_while (int);
441 static void s_mri_endw (int);
442 static void s_m68k_cpu (int);
443 static void s_m68k_arch (int);
444
445 struct m68k_cpu
446 {
447 unsigned long arch; /* Architecture features. */
448 const enum m68k_register *control_regs; /* Control regs on chip */
449 const char *name; /* Name */
450 int alias; /* Alias for a cannonical name. If 1, then
451 succeeds canonical name, if -1 then
452 succeeds canonical name, if <-1 ||>1 this is a
453 deprecated name, and the next/previous name
454 should be used. */
455 };
456
457 /* We hold flags for features explicitly enabled and explicitly
458 disabled. */
459 static int current_architecture;
460 static int not_current_architecture;
461 static const struct m68k_cpu *selected_arch;
462 static const struct m68k_cpu *selected_cpu;
463 static int initialized;
464
465 /* Architecture models. */
466 static const struct m68k_cpu m68k_archs[] =
467 {
468 {m68000, m68000_ctrl, "68000", 0},
469 {m68010, m68010_ctrl, "68010", 0},
470 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
471 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
472 {m68040, m68040_ctrl, "68040", 0},
473 {m68060, m68060_ctrl, "68060", 0},
474 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
475 {fido_a, fido_ctrl, "fidoa", 0},
476 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
477 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
478 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
479 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
480 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
481 {0,0,NULL, 0}
482 };
483
484 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
485 for either. */
486 static const struct m68k_cpu m68k_extensions[] =
487 {
488 {m68851, NULL, "68851", -1},
489 {m68881, NULL, "68881", -1},
490 {m68881, NULL, "68882", -1},
491
492 {cfloat|m68881, NULL, "float", 0},
493
494 {mcfhwdiv, NULL, "div", 1},
495 {mcfusp, NULL, "usp", 1},
496 {mcfmac, NULL, "mac", 1},
497 {mcfemac, NULL, "emac", 1},
498
499 {0,NULL,NULL, 0}
500 };
501
502 /* Processor list */
503 static const struct m68k_cpu m68k_cpus[] =
504 {
505 {m68000, m68000_ctrl, "68000", 0},
506 {m68000, m68000_ctrl, "68ec000", 1},
507 {m68000, m68000_ctrl, "68hc000", 1},
508 {m68000, m68000_ctrl, "68hc001", 1},
509 {m68000, m68000_ctrl, "68008", 1},
510 {m68000, m68000_ctrl, "68302", 1},
511 {m68000, m68000_ctrl, "68306", 1},
512 {m68000, m68000_ctrl, "68307", 1},
513 {m68000, m68000_ctrl, "68322", 1},
514 {m68000, m68000_ctrl, "68356", 1},
515 {m68010, m68010_ctrl, "68010", 0},
516 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
517 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
518 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
519 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
520 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
521 {m68040, m68040_ctrl, "68040", 0},
522 {m68040, m68040_ctrl, "68ec040", 1},
523 {m68060, m68060_ctrl, "68060", 0},
524 {m68060, m68060_ctrl, "68ec060", 1},
525
526 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
527 {cpu32|m68881, cpu32_ctrl, "68330", 1},
528 {cpu32|m68881, cpu32_ctrl, "68331", 1},
529 {cpu32|m68881, cpu32_ctrl, "68332", 1},
530 {cpu32|m68881, cpu32_ctrl, "68333", 1},
531 {cpu32|m68881, cpu32_ctrl, "68334", 1},
532 {cpu32|m68881, cpu32_ctrl, "68336", 1},
533 {cpu32|m68881, cpu32_ctrl, "68340", 1},
534 {cpu32|m68881, cpu32_ctrl, "68341", 1},
535 {cpu32|m68881, cpu32_ctrl, "68349", 1},
536 {cpu32|m68881, cpu32_ctrl, "68360", 1},
537
538 {mcfisa_a, mcf_ctrl, "5200", 0},
539 {mcfisa_a, mcf_ctrl, "5202", 1},
540 {mcfisa_a, mcf_ctrl, "5204", 1},
541 {mcfisa_a, mcf5206_ctrl, "5206", 1},
542
543 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
544
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
546 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
547
548 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
549 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
550
551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
552 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
554
555 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
558
559 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
562 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
563
564 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
565 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
566
567 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
568 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
569 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
572
573 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
574 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
578
579 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
580
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
583
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
588
589 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
590
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
595
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
599
600 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
601
602 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
603 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
604 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
605 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
606 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
607 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
608 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
609
610 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
611 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
612 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
613 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
614 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
615 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
616 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
617
618 {fido_a, fido_ctrl, "fidoa", 0},
619 {fido_a, fido_ctrl, "fido", 1},
620
621 {0,NULL,NULL, 0}
622 };
623
624 static const struct m68k_cpu *m68k_lookup_cpu
625 (const char *, const struct m68k_cpu *, int, int *);
626 static int m68k_set_arch (const char *, int, int);
627 static int m68k_set_cpu (const char *, int, int);
628 static int m68k_set_extension (const char *, int, int);
629 static void m68k_init_arch (void);
630
631 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
632 architecture and we have a lot of relaxation modes. */
633
634 /* Macros used in the relaxation code. */
635 #define TAB(x,y) (((x) << 2) + (y))
636 #define TABTYPE(x) ((x) >> 2)
637
638 /* Relaxation states. */
639 #define BYTE 0
640 #define SHORT 1
641 #define LONG 2
642 #define SZ_UNDEF 3
643
644 /* Here are all the relaxation modes we support. First we can relax ordinary
645 branches. On 68020 and higher and on CPU32 all branch instructions take
646 three forms, so on these CPUs all branches always remain as such. When we
647 have to expand to the LONG form on a 68000, though, we substitute an
648 absolute jump instead. This is a direct replacement for unconditional
649 branches and a branch over a jump for conditional branches. However, if the
650 user requires PIC and disables this with --pcrel, we can only relax between
651 BYTE and SHORT forms, punting if that isn't enough. This gives us four
652 different relaxation modes for branches: */
653
654 #define BRANCHBWL 0 /* Branch byte, word, or long. */
655 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
656 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
657 #define BRANCHBW 3 /* Branch byte or word. */
658
659 /* We also relax coprocessor branches and DBcc's. All CPUs that support
660 coprocessor branches support them in word and long forms, so we have only
661 one relaxation mode for them. DBcc's are word only on all CPUs. We can
662 relax them to the LONG form with a branch-around sequence. This sequence
663 can use a long branch (if available) or an absolute jump (if acceptable).
664 This gives us two relaxation modes. If long branches are not available and
665 absolute jumps are not acceptable, we don't relax DBcc's. */
666
667 #define FBRANCH 4 /* Coprocessor branch. */
668 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
669 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
670
671 /* That's all for instruction relaxation. However, we also relax PC-relative
672 operands. Specifically, we have three operand relaxation modes. On the
673 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
674 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
675 two. Also PC+displacement+index operands in their simple form (with a non-
676 suppressed index without memory indirection) are supported on all CPUs, but
677 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
678 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
679 form of the PC+displacement+index operand. Finally, some absolute operands
680 can be relaxed down to 16-bit PC-relative. */
681
682 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
683 #define PCINDEX 8 /* PC + displacement + index. */
684 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
685
686 /* Note that calls to frag_var need to specify the maximum expansion
687 needed; this is currently 10 bytes for DBCC. */
688
689 /* The fields are:
690 How far Forward this mode will reach:
691 How far Backward this mode will reach:
692 How many bytes this mode will add to the size of the frag
693 Which mode to go to if the offset won't fit in this one
694
695 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
696 relax_typeS md_relax_table[] =
697 {
698 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
699 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
700 { 0, 0, 4, 0 },
701 { 1, 1, 0, 0 },
702
703 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
704 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
705 { 0, 0, 4, 0 },
706 { 1, 1, 0, 0 },
707
708 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
709 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
710 { 0, 0, 6, 0 },
711 { 1, 1, 0, 0 },
712
713 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
714 { 0, 0, 2, 0 },
715 { 1, 1, 0, 0 },
716 { 1, 1, 0, 0 },
717
718 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
719 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
720 { 0, 0, 4, 0 },
721 { 1, 1, 0, 0 },
722
723 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
724 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
725 { 0, 0, 10, 0 },
726 { 1, 1, 0, 0 },
727
728 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
729 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
730 { 0, 0, 10, 0 },
731 { 1, 1, 0, 0 },
732
733 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
734 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
735 { 0, 0, 6, 0 },
736 { 1, 1, 0, 0 },
737
738 { 125, -130, 0, TAB (PCINDEX, SHORT) },
739 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
740 { 0, 0, 4, 0 },
741 { 1, 1, 0, 0 },
742
743 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
744 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
745 { 0, 0, 4, 0 },
746 { 1, 1, 0, 0 },
747 };
748
749 /* These are the machine dependent pseudo-ops. These are included so
750 the assembler can work on the output from the SUN C compiler, which
751 generates these. */
752
753 /* This table describes all the machine specific pseudo-ops the assembler
754 has to support. The fields are:
755 pseudo-op name without dot
756 function to call to execute this pseudo-op
757 Integer arg to pass to the function. */
758 const pseudo_typeS md_pseudo_table[] =
759 {
760 {"data1", s_data1, 0},
761 {"data2", s_data2, 0},
762 {"bss", s_bss, 0},
763 {"even", s_even, 0},
764 {"skip", s_space, 0},
765 {"proc", s_proc, 0},
766 #if defined (TE_SUN3) || defined (OBJ_ELF)
767 {"align", s_align_bytes, 0},
768 #endif
769 #ifdef OBJ_ELF
770 {"swbeg", s_ignore, 0},
771 #endif
772 {"extend", float_cons, 'x'},
773 {"ldouble", float_cons, 'x'},
774
775 {"arch", s_m68k_arch, 0},
776 {"cpu", s_m68k_cpu, 0},
777
778 /* The following pseudo-ops are supported for MRI compatibility. */
779 {"chip", s_chip, 0},
780 {"comline", s_space, 1},
781 {"fopt", s_fopt, 0},
782 {"mask2", s_ignore, 0},
783 {"opt", s_opt, 0},
784 {"reg", s_reg, 0},
785 {"restore", s_restore, 0},
786 {"save", s_save, 0},
787
788 {"if", s_mri_if, 0},
789 {"if.b", s_mri_if, 'b'},
790 {"if.w", s_mri_if, 'w'},
791 {"if.l", s_mri_if, 'l'},
792 {"else", s_mri_else, 0},
793 {"else.s", s_mri_else, 's'},
794 {"else.l", s_mri_else, 'l'},
795 {"endi", s_mri_endi, 0},
796 {"break", s_mri_break, 0},
797 {"break.s", s_mri_break, 's'},
798 {"break.l", s_mri_break, 'l'},
799 {"next", s_mri_next, 0},
800 {"next.s", s_mri_next, 's'},
801 {"next.l", s_mri_next, 'l'},
802 {"for", s_mri_for, 0},
803 {"for.b", s_mri_for, 'b'},
804 {"for.w", s_mri_for, 'w'},
805 {"for.l", s_mri_for, 'l'},
806 {"endf", s_mri_endf, 0},
807 {"repeat", s_mri_repeat, 0},
808 {"until", s_mri_until, 0},
809 {"until.b", s_mri_until, 'b'},
810 {"until.w", s_mri_until, 'w'},
811 {"until.l", s_mri_until, 'l'},
812 {"while", s_mri_while, 0},
813 {"while.b", s_mri_while, 'b'},
814 {"while.w", s_mri_while, 'w'},
815 {"while.l", s_mri_while, 'l'},
816 {"endw", s_mri_endw, 0},
817
818 {0, 0, 0}
819 };
820
821 /* The mote pseudo ops are put into the opcode table, since they
822 don't start with a . they look like opcodes to gas. */
823
824 const pseudo_typeS mote_pseudo_table[] =
825 {
826
827 {"dcl", cons, 4},
828 {"dc", cons, 2},
829 {"dcw", cons, 2},
830 {"dcb", cons, 1},
831
832 {"dsl", s_space, 4},
833 {"ds", s_space, 2},
834 {"dsw", s_space, 2},
835 {"dsb", s_space, 1},
836
837 {"xdef", s_globl, 0},
838 #ifdef OBJ_ELF
839 {"align", s_align_bytes, 0},
840 #else
841 {"align", s_align_ptwo, 0},
842 #endif
843 #ifdef M68KCOFF
844 {"sect", obj_coff_section, 0},
845 {"section", obj_coff_section, 0},
846 #endif
847 {0, 0, 0}
848 };
849
850 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
851 gives identical results to a 32-bit host. */
852 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
853 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
854
855 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
856 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
857 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
858 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
859
860 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
861 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
862 #define islong(x) (1)
863
864 static char notend_table[256];
865 static char alt_notend_table[256];
866 #define notend(s) \
867 (! (notend_table[(unsigned char) *s] \
868 || (*s == ':' \
869 && alt_notend_table[(unsigned char) s[1]])))
870
871 #ifdef OBJ_ELF
872
873 /* Return zero if the reference to SYMBOL from within the same segment may
874 be relaxed. */
875
876 /* On an ELF system, we can't relax an externally visible symbol,
877 because it may be overridden by a shared library. However, if
878 TARGET_OS is "elf", then we presume that we are assembling for an
879 embedded system, in which case we don't have to worry about shared
880 libraries, and we can relax any external sym. */
881
882 #define relaxable_symbol(symbol) \
883 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
884 || S_IS_WEAK (symbol)))
885
886 /* Compute the relocation code for a fixup of SIZE bytes, using pc
887 relative relocation if PCREL is non-zero. PIC says whether a special
888 pic relocation was requested. */
889
890 static bfd_reloc_code_real_type
891 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
892 {
893 switch (pic)
894 {
895 case pic_got_pcrel:
896 switch (size)
897 {
898 case 1:
899 return BFD_RELOC_8_GOT_PCREL;
900 case 2:
901 return BFD_RELOC_16_GOT_PCREL;
902 case 4:
903 return BFD_RELOC_32_GOT_PCREL;
904 }
905 break;
906
907 case pic_got_off:
908 switch (size)
909 {
910 case 1:
911 return BFD_RELOC_8_GOTOFF;
912 case 2:
913 return BFD_RELOC_16_GOTOFF;
914 case 4:
915 return BFD_RELOC_32_GOTOFF;
916 }
917 break;
918
919 case pic_plt_pcrel:
920 switch (size)
921 {
922 case 1:
923 return BFD_RELOC_8_PLT_PCREL;
924 case 2:
925 return BFD_RELOC_16_PLT_PCREL;
926 case 4:
927 return BFD_RELOC_32_PLT_PCREL;
928 }
929 break;
930
931 case pic_plt_off:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_PLTOFF;
936 case 2:
937 return BFD_RELOC_16_PLTOFF;
938 case 4:
939 return BFD_RELOC_32_PLTOFF;
940 }
941 break;
942
943 case pic_none:
944 if (pcrel)
945 {
946 switch (size)
947 {
948 case 1:
949 return BFD_RELOC_8_PCREL;
950 case 2:
951 return BFD_RELOC_16_PCREL;
952 case 4:
953 return BFD_RELOC_32_PCREL;
954 }
955 }
956 else
957 {
958 switch (size)
959 {
960 case 1:
961 return BFD_RELOC_8;
962 case 2:
963 return BFD_RELOC_16;
964 case 4:
965 return BFD_RELOC_32;
966 }
967 }
968 }
969
970 if (pcrel)
971 {
972 if (pic == pic_none)
973 as_bad (_("Can not do %d byte pc-relative relocation"), size);
974 else
975 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
976 }
977 else
978 {
979 if (pic == pic_none)
980 as_bad (_("Can not do %d byte relocation"), size);
981 else
982 as_bad (_("Can not do %d byte pic relocation"), size);
983 }
984
985 return BFD_RELOC_NONE;
986 }
987
988 /* Here we decide which fixups can be adjusted to make them relative
989 to the beginning of the section instead of the symbol. Basically
990 we need to make sure that the dynamic relocations are done
991 correctly, so in some cases we force the original symbol to be
992 used. */
993 int
994 tc_m68k_fix_adjustable (fixS *fixP)
995 {
996 /* Adjust_reloc_syms doesn't know about the GOT. */
997 switch (fixP->fx_r_type)
998 {
999 case BFD_RELOC_8_GOT_PCREL:
1000 case BFD_RELOC_16_GOT_PCREL:
1001 case BFD_RELOC_32_GOT_PCREL:
1002 case BFD_RELOC_8_GOTOFF:
1003 case BFD_RELOC_16_GOTOFF:
1004 case BFD_RELOC_32_GOTOFF:
1005 case BFD_RELOC_8_PLT_PCREL:
1006 case BFD_RELOC_16_PLT_PCREL:
1007 case BFD_RELOC_32_PLT_PCREL:
1008 case BFD_RELOC_8_PLTOFF:
1009 case BFD_RELOC_16_PLTOFF:
1010 case BFD_RELOC_32_PLTOFF:
1011 return 0;
1012
1013 case BFD_RELOC_VTABLE_INHERIT:
1014 case BFD_RELOC_VTABLE_ENTRY:
1015 return 0;
1016
1017 default:
1018 return 1;
1019 }
1020 }
1021
1022 #else /* !OBJ_ELF */
1023
1024 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1025
1026 #define relaxable_symbol(symbol) 1
1027
1028 #endif /* OBJ_ELF */
1029
1030 arelent *
1031 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1032 {
1033 arelent *reloc;
1034 bfd_reloc_code_real_type code;
1035
1036 /* If the tcbit is set, then this was a fixup of a negative value
1037 that was never resolved. We do not have a reloc to handle this,
1038 so just return. We assume that other code will have detected this
1039 situation and produced a helpful error message, so we just tell the
1040 user that the reloc cannot be produced. */
1041 if (fixp->fx_tcbit)
1042 {
1043 if (fixp->fx_addsy)
1044 as_bad_where (fixp->fx_file, fixp->fx_line,
1045 _("Unable to produce reloc against symbol '%s'"),
1046 S_GET_NAME (fixp->fx_addsy));
1047 return NULL;
1048 }
1049
1050 if (fixp->fx_r_type != BFD_RELOC_NONE)
1051 {
1052 code = fixp->fx_r_type;
1053
1054 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1055 that fixup_segment converted a non-PC relative reloc into a
1056 PC relative reloc. In such a case, we need to convert the
1057 reloc code. */
1058 if (fixp->fx_pcrel)
1059 {
1060 switch (code)
1061 {
1062 case BFD_RELOC_8:
1063 code = BFD_RELOC_8_PCREL;
1064 break;
1065 case BFD_RELOC_16:
1066 code = BFD_RELOC_16_PCREL;
1067 break;
1068 case BFD_RELOC_32:
1069 code = BFD_RELOC_32_PCREL;
1070 break;
1071 case BFD_RELOC_8_PCREL:
1072 case BFD_RELOC_16_PCREL:
1073 case BFD_RELOC_32_PCREL:
1074 case BFD_RELOC_8_GOT_PCREL:
1075 case BFD_RELOC_16_GOT_PCREL:
1076 case BFD_RELOC_32_GOT_PCREL:
1077 case BFD_RELOC_8_GOTOFF:
1078 case BFD_RELOC_16_GOTOFF:
1079 case BFD_RELOC_32_GOTOFF:
1080 case BFD_RELOC_8_PLT_PCREL:
1081 case BFD_RELOC_16_PLT_PCREL:
1082 case BFD_RELOC_32_PLT_PCREL:
1083 case BFD_RELOC_8_PLTOFF:
1084 case BFD_RELOC_16_PLTOFF:
1085 case BFD_RELOC_32_PLTOFF:
1086 break;
1087 default:
1088 as_bad_where (fixp->fx_file, fixp->fx_line,
1089 _("Cannot make %s relocation PC relative"),
1090 bfd_get_reloc_code_name (code));
1091 }
1092 }
1093 }
1094 else
1095 {
1096 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1097 switch (F (fixp->fx_size, fixp->fx_pcrel))
1098 {
1099 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1100 MAP (1, 0, BFD_RELOC_8);
1101 MAP (2, 0, BFD_RELOC_16);
1102 MAP (4, 0, BFD_RELOC_32);
1103 MAP (1, 1, BFD_RELOC_8_PCREL);
1104 MAP (2, 1, BFD_RELOC_16_PCREL);
1105 MAP (4, 1, BFD_RELOC_32_PCREL);
1106 default:
1107 abort ();
1108 }
1109 }
1110 #undef F
1111 #undef MAP
1112
1113 reloc = (arelent *) xmalloc (sizeof (arelent));
1114 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1115 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1116 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1117 #ifndef OBJ_ELF
1118 if (fixp->fx_pcrel)
1119 reloc->addend = fixp->fx_addnumber;
1120 else
1121 reloc->addend = 0;
1122 #else
1123 if (!fixp->fx_pcrel)
1124 reloc->addend = fixp->fx_addnumber;
1125 else
1126 reloc->addend = (section->vma
1127 /* Explicit sign extension in case char is
1128 unsigned. */
1129 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1130 + fixp->fx_addnumber
1131 + md_pcrel_from (fixp));
1132 #endif
1133
1134 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1135 assert (reloc->howto != 0);
1136
1137 return reloc;
1138 }
1139
1140 /* Handle of the OPCODE hash table. NULL means any use before
1141 m68k_ip_begin() will crash. */
1142 static struct hash_control *op_hash;
1143 \f
1144 /* Assemble an m68k instruction. */
1145
1146 static void
1147 m68k_ip (char *instring)
1148 {
1149 register char *p;
1150 register struct m68k_op *opP;
1151 register const struct m68k_incant *opcode;
1152 register const char *s;
1153 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1154 char *pdot, *pdotmove;
1155 enum m68k_size siz1, siz2;
1156 char c;
1157 int losing;
1158 int opsfound;
1159 struct m68k_op operands_backup[6];
1160 LITTLENUM_TYPE words[6];
1161 LITTLENUM_TYPE *wordp;
1162 unsigned long ok_arch = 0;
1163
1164 if (*instring == ' ')
1165 instring++; /* Skip leading whitespace. */
1166
1167 /* Scan up to end of operation-code, which MUST end in end-of-string
1168 or exactly 1 space. */
1169 pdot = 0;
1170 for (p = instring; *p != '\0'; p++)
1171 {
1172 if (*p == ' ')
1173 break;
1174 if (*p == '.')
1175 pdot = p;
1176 }
1177
1178 if (p == instring)
1179 {
1180 the_ins.error = _("No operator");
1181 return;
1182 }
1183
1184 /* p now points to the end of the opcode name, probably whitespace.
1185 Make sure the name is null terminated by clobbering the
1186 whitespace, look it up in the hash table, then fix it back.
1187 Remove a dot, first, since the opcode tables have none. */
1188 if (pdot != NULL)
1189 {
1190 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1191 *pdotmove = pdotmove[1];
1192 p--;
1193 }
1194
1195 c = *p;
1196 *p = '\0';
1197 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1198 *p = c;
1199
1200 if (pdot != NULL)
1201 {
1202 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1203 *pdotmove = pdotmove[-1];
1204 *pdot = '.';
1205 ++p;
1206 }
1207
1208 if (opcode == NULL)
1209 {
1210 the_ins.error = _("Unknown operator");
1211 return;
1212 }
1213
1214 /* Found a legitimate opcode, start matching operands. */
1215 while (*p == ' ')
1216 ++p;
1217
1218 if (opcode->m_operands == 0)
1219 {
1220 char *old = input_line_pointer;
1221 *old = '\n';
1222 input_line_pointer = p;
1223 /* Ahh - it's a motorola style psuedo op. */
1224 mote_pseudo_table[opcode->m_opnum].poc_handler
1225 (mote_pseudo_table[opcode->m_opnum].poc_val);
1226 input_line_pointer = old;
1227 *old = 0;
1228
1229 return;
1230 }
1231
1232 if (flag_mri && opcode->m_opnum == 0)
1233 {
1234 /* In MRI mode, random garbage is allowed after an instruction
1235 which accepts no operands. */
1236 the_ins.args = opcode->m_operands;
1237 the_ins.numargs = opcode->m_opnum;
1238 the_ins.numo = opcode->m_codenum;
1239 the_ins.opcode[0] = getone (opcode);
1240 the_ins.opcode[1] = gettwo (opcode);
1241 return;
1242 }
1243
1244 for (opP = &the_ins.operands[0]; *p; opP++)
1245 {
1246 p = crack_operand (p, opP);
1247
1248 if (opP->error)
1249 {
1250 the_ins.error = opP->error;
1251 return;
1252 }
1253 }
1254
1255 opsfound = opP - &the_ins.operands[0];
1256
1257 /* This ugly hack is to support the floating pt opcodes in their
1258 standard form. Essentially, we fake a first enty of type COP#1 */
1259 if (opcode->m_operands[0] == 'I')
1260 {
1261 int n;
1262
1263 for (n = opsfound; n > 0; --n)
1264 the_ins.operands[n] = the_ins.operands[n - 1];
1265
1266 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1267 the_ins.operands[0].mode = CONTROL;
1268 the_ins.operands[0].reg = m68k_float_copnum;
1269 opsfound++;
1270 }
1271
1272 /* We've got the operands. Find an opcode that'll accept them. */
1273 for (losing = 0;;)
1274 {
1275 /* If we didn't get the right number of ops, or we have no
1276 common model with this pattern then reject this pattern. */
1277
1278 ok_arch |= opcode->m_arch;
1279 if (opsfound != opcode->m_opnum
1280 || ((opcode->m_arch & current_architecture) == 0))
1281 ++losing;
1282 else
1283 {
1284 int i;
1285
1286 /* Make a copy of the operands of this insn so that
1287 we can modify them safely, should we want to. */
1288 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1289 for (i = 0; i < opsfound; i++)
1290 operands_backup[i] = the_ins.operands[i];
1291
1292 for (s = opcode->m_operands, opP = &operands_backup[0];
1293 *s && !losing;
1294 s += 2, opP++)
1295 {
1296 /* Warning: this switch is huge! */
1297 /* I've tried to organize the cases into this order:
1298 non-alpha first, then alpha by letter. Lower-case
1299 goes directly before uppercase counterpart. */
1300 /* Code with multiple case ...: gets sorted by the lowest
1301 case ... it belongs to. I hope this makes sense. */
1302 switch (*s)
1303 {
1304 case '!':
1305 switch (opP->mode)
1306 {
1307 case IMMED:
1308 case DREG:
1309 case AREG:
1310 case FPREG:
1311 case CONTROL:
1312 case AINC:
1313 case ADEC:
1314 case REGLST:
1315 losing++;
1316 break;
1317 default:
1318 break;
1319 }
1320 break;
1321
1322 case '<':
1323 switch (opP->mode)
1324 {
1325 case DREG:
1326 case AREG:
1327 case FPREG:
1328 case CONTROL:
1329 case IMMED:
1330 case ADEC:
1331 case REGLST:
1332 losing++;
1333 break;
1334 default:
1335 break;
1336 }
1337 break;
1338
1339 case '>':
1340 switch (opP->mode)
1341 {
1342 case DREG:
1343 case AREG:
1344 case FPREG:
1345 case CONTROL:
1346 case IMMED:
1347 case AINC:
1348 case REGLST:
1349 losing++;
1350 break;
1351 case ABSL:
1352 break;
1353 default:
1354 if (opP->reg == PC
1355 || opP->reg == ZPC)
1356 losing++;
1357 break;
1358 }
1359 break;
1360
1361 case 'm':
1362 switch (opP->mode)
1363 {
1364 case DREG:
1365 case AREG:
1366 case AINDR:
1367 case AINC:
1368 case ADEC:
1369 break;
1370 default:
1371 losing++;
1372 }
1373 break;
1374
1375 case 'n':
1376 switch (opP->mode)
1377 {
1378 case DISP:
1379 break;
1380 default:
1381 losing++;
1382 }
1383 break;
1384
1385 case 'o':
1386 switch (opP->mode)
1387 {
1388 case BASE:
1389 case ABSL:
1390 case IMMED:
1391 break;
1392 default:
1393 losing++;
1394 }
1395 break;
1396
1397 case 'p':
1398 switch (opP->mode)
1399 {
1400 case DREG:
1401 case AREG:
1402 case AINDR:
1403 case AINC:
1404 case ADEC:
1405 break;
1406 case DISP:
1407 if (opP->reg == PC || opP->reg == ZPC)
1408 losing++;
1409 break;
1410 default:
1411 losing++;
1412 }
1413 break;
1414
1415 case 'q':
1416 switch (opP->mode)
1417 {
1418 case DREG:
1419 case AINDR:
1420 case AINC:
1421 case ADEC:
1422 break;
1423 case DISP:
1424 if (opP->reg == PC || opP->reg == ZPC)
1425 losing++;
1426 break;
1427 default:
1428 losing++;
1429 break;
1430 }
1431 break;
1432
1433 case 'v':
1434 switch (opP->mode)
1435 {
1436 case DREG:
1437 case AINDR:
1438 case AINC:
1439 case ADEC:
1440 case ABSL:
1441 break;
1442 case DISP:
1443 if (opP->reg == PC || opP->reg == ZPC)
1444 losing++;
1445 break;
1446 default:
1447 losing++;
1448 break;
1449 }
1450 break;
1451
1452 case '#':
1453 if (opP->mode != IMMED)
1454 losing++;
1455 else if (s[1] == 'b'
1456 && ! isvar (&opP->disp)
1457 && (opP->disp.exp.X_op != O_constant
1458 || ! isbyte (opP->disp.exp.X_add_number)))
1459 losing++;
1460 else if (s[1] == 'B'
1461 && ! isvar (&opP->disp)
1462 && (opP->disp.exp.X_op != O_constant
1463 || ! issbyte (opP->disp.exp.X_add_number)))
1464 losing++;
1465 else if (s[1] == 'w'
1466 && ! isvar (&opP->disp)
1467 && (opP->disp.exp.X_op != O_constant
1468 || ! isword (opP->disp.exp.X_add_number)))
1469 losing++;
1470 else if (s[1] == 'W'
1471 && ! isvar (&opP->disp)
1472 && (opP->disp.exp.X_op != O_constant
1473 || ! issword (opP->disp.exp.X_add_number)))
1474 losing++;
1475 break;
1476
1477 case '^':
1478 case 'T':
1479 if (opP->mode != IMMED)
1480 losing++;
1481 break;
1482
1483 case '$':
1484 if (opP->mode == AREG
1485 || opP->mode == CONTROL
1486 || opP->mode == FPREG
1487 || opP->mode == IMMED
1488 || opP->mode == REGLST
1489 || (opP->mode != ABSL
1490 && (opP->reg == PC
1491 || opP->reg == ZPC)))
1492 losing++;
1493 break;
1494
1495 case '%':
1496 if (opP->mode == CONTROL
1497 || opP->mode == FPREG
1498 || opP->mode == REGLST
1499 || opP->mode == IMMED
1500 || (opP->mode != ABSL
1501 && (opP->reg == PC
1502 || opP->reg == ZPC)))
1503 losing++;
1504 break;
1505
1506 case '&':
1507 switch (opP->mode)
1508 {
1509 case DREG:
1510 case AREG:
1511 case FPREG:
1512 case CONTROL:
1513 case IMMED:
1514 case AINC:
1515 case ADEC:
1516 case REGLST:
1517 losing++;
1518 break;
1519 case ABSL:
1520 break;
1521 default:
1522 if (opP->reg == PC
1523 || opP->reg == ZPC)
1524 losing++;
1525 break;
1526 }
1527 break;
1528
1529 case '*':
1530 if (opP->mode == CONTROL
1531 || opP->mode == FPREG
1532 || opP->mode == REGLST)
1533 losing++;
1534 break;
1535
1536 case '+':
1537 if (opP->mode != AINC)
1538 losing++;
1539 break;
1540
1541 case '-':
1542 if (opP->mode != ADEC)
1543 losing++;
1544 break;
1545
1546 case '/':
1547 switch (opP->mode)
1548 {
1549 case AREG:
1550 case CONTROL:
1551 case FPREG:
1552 case AINC:
1553 case ADEC:
1554 case IMMED:
1555 case REGLST:
1556 losing++;
1557 break;
1558 default:
1559 break;
1560 }
1561 break;
1562
1563 case ';':
1564 switch (opP->mode)
1565 {
1566 case AREG:
1567 case CONTROL:
1568 case FPREG:
1569 case REGLST:
1570 losing++;
1571 break;
1572 default:
1573 break;
1574 }
1575 break;
1576
1577 case '?':
1578 switch (opP->mode)
1579 {
1580 case AREG:
1581 case CONTROL:
1582 case FPREG:
1583 case AINC:
1584 case ADEC:
1585 case IMMED:
1586 case REGLST:
1587 losing++;
1588 break;
1589 case ABSL:
1590 break;
1591 default:
1592 if (opP->reg == PC || opP->reg == ZPC)
1593 losing++;
1594 break;
1595 }
1596 break;
1597
1598 case '@':
1599 switch (opP->mode)
1600 {
1601 case AREG:
1602 case CONTROL:
1603 case FPREG:
1604 case IMMED:
1605 case REGLST:
1606 losing++;
1607 break;
1608 default:
1609 break;
1610 }
1611 break;
1612
1613 case '~': /* For now! (JF FOO is this right?) */
1614 switch (opP->mode)
1615 {
1616 case DREG:
1617 case AREG:
1618 case CONTROL:
1619 case FPREG:
1620 case IMMED:
1621 case REGLST:
1622 losing++;
1623 break;
1624 case ABSL:
1625 break;
1626 default:
1627 if (opP->reg == PC
1628 || opP->reg == ZPC)
1629 losing++;
1630 break;
1631 }
1632 break;
1633
1634 case '3':
1635 if (opP->mode != CONTROL
1636 || (opP->reg != TT0 && opP->reg != TT1))
1637 losing++;
1638 break;
1639
1640 case 'A':
1641 if (opP->mode != AREG)
1642 losing++;
1643 break;
1644
1645 case 'a':
1646 if (opP->mode != AINDR)
1647 ++losing;
1648 break;
1649
1650 case '4':
1651 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1652 && (opP->mode != DISP
1653 || opP->reg < ADDR0
1654 || opP->reg > ADDR7))
1655 ++losing;
1656 break;
1657
1658 case 'B': /* FOO */
1659 if (opP->mode != ABSL
1660 || (flag_long_jumps
1661 && strncmp (instring, "jbsr", 4) == 0))
1662 losing++;
1663 break;
1664
1665 case 'b':
1666 switch (opP->mode)
1667 {
1668 case IMMED:
1669 case ABSL:
1670 case AREG:
1671 case FPREG:
1672 case CONTROL:
1673 case POST:
1674 case PRE:
1675 case REGLST:
1676 losing++;
1677 break;
1678 default:
1679 break;
1680 }
1681 break;
1682
1683 case 'C':
1684 if (opP->mode != CONTROL || opP->reg != CCR)
1685 losing++;
1686 break;
1687
1688 case 'd':
1689 if (opP->mode != DISP
1690 || opP->reg < ADDR0
1691 || opP->reg > ADDR7)
1692 losing++;
1693 break;
1694
1695 case 'D':
1696 if (opP->mode != DREG)
1697 losing++;
1698 break;
1699
1700 case 'E':
1701 if (opP->reg != ACC)
1702 losing++;
1703 break;
1704
1705 case 'e':
1706 if (opP->reg != ACC && opP->reg != ACC1
1707 && opP->reg != ACC2 && opP->reg != ACC3)
1708 losing++;
1709 break;
1710
1711 case 'F':
1712 if (opP->mode != FPREG)
1713 losing++;
1714 break;
1715
1716 case 'G':
1717 if (opP->reg != MACSR)
1718 losing++;
1719 break;
1720
1721 case 'g':
1722 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1723 losing++;
1724 break;
1725
1726 case 'H':
1727 if (opP->reg != MASK)
1728 losing++;
1729 break;
1730
1731 case 'I':
1732 if (opP->mode != CONTROL
1733 || opP->reg < COP0
1734 || opP->reg > COP7)
1735 losing++;
1736 break;
1737
1738 case 'i':
1739 if (opP->mode != LSH && opP->mode != RSH)
1740 losing++;
1741 break;
1742
1743 case 'J':
1744 if (opP->mode != CONTROL
1745 || opP->reg < USP
1746 || opP->reg > last_movec_reg
1747 || !control_regs)
1748 losing++;
1749 else
1750 {
1751 const enum m68k_register *rp;
1752
1753 for (rp = control_regs; *rp; rp++)
1754 {
1755 if (*rp == opP->reg)
1756 break;
1757 /* In most CPUs RAMBAR refers to control reg
1758 c05 (RAMBAR1), but a few CPUs have it
1759 refer to c04 (RAMBAR0). */
1760 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1761 {
1762 opP->reg = RAMBAR_ALT;
1763 break;
1764 }
1765 }
1766 if (*rp == 0)
1767 losing++;
1768 }
1769 break;
1770
1771 case 'k':
1772 if (opP->mode != IMMED)
1773 losing++;
1774 break;
1775
1776 case 'l':
1777 case 'L':
1778 if (opP->mode == DREG
1779 || opP->mode == AREG
1780 || opP->mode == FPREG)
1781 {
1782 if (s[1] == '8')
1783 losing++;
1784 else
1785 {
1786 switch (opP->mode)
1787 {
1788 case DREG:
1789 opP->mask = 1 << (opP->reg - DATA0);
1790 break;
1791 case AREG:
1792 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1793 break;
1794 case FPREG:
1795 opP->mask = 1 << (opP->reg - FP0 + 16);
1796 break;
1797 default:
1798 abort ();
1799 }
1800 opP->mode = REGLST;
1801 }
1802 }
1803 else if (opP->mode == CONTROL)
1804 {
1805 if (s[1] != '8')
1806 losing++;
1807 else
1808 {
1809 switch (opP->reg)
1810 {
1811 case FPI:
1812 opP->mask = 1 << 24;
1813 break;
1814 case FPS:
1815 opP->mask = 1 << 25;
1816 break;
1817 case FPC:
1818 opP->mask = 1 << 26;
1819 break;
1820 default:
1821 losing++;
1822 break;
1823 }
1824 opP->mode = REGLST;
1825 }
1826 }
1827 else if (opP->mode != REGLST)
1828 losing++;
1829 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1830 losing++;
1831 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1832 losing++;
1833 break;
1834
1835 case 'M':
1836 if (opP->mode != IMMED)
1837 losing++;
1838 else if (opP->disp.exp.X_op != O_constant
1839 || ! issbyte (opP->disp.exp.X_add_number))
1840 losing++;
1841 else if (! m68k_quick
1842 && instring[3] != 'q'
1843 && instring[4] != 'q')
1844 losing++;
1845 break;
1846
1847 case 'O':
1848 if (opP->mode != DREG
1849 && opP->mode != IMMED
1850 && opP->mode != ABSL)
1851 losing++;
1852 break;
1853
1854 case 'Q':
1855 if (opP->mode != IMMED)
1856 losing++;
1857 else if (opP->disp.exp.X_op != O_constant
1858 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1859 losing++;
1860 else if (! m68k_quick
1861 && (strncmp (instring, "add", 3) == 0
1862 || strncmp (instring, "sub", 3) == 0)
1863 && instring[3] != 'q')
1864 losing++;
1865 break;
1866
1867 case 'R':
1868 if (opP->mode != DREG && opP->mode != AREG)
1869 losing++;
1870 break;
1871
1872 case 'r':
1873 if (opP->mode != AINDR
1874 && (opP->mode != BASE
1875 || (opP->reg != 0
1876 && opP->reg != ZADDR0)
1877 || opP->disp.exp.X_op != O_absent
1878 || ((opP->index.reg < DATA0
1879 || opP->index.reg > DATA7)
1880 && (opP->index.reg < ADDR0
1881 || opP->index.reg > ADDR7))
1882 || opP->index.size != SIZE_UNSPEC
1883 || opP->index.scale != 1))
1884 losing++;
1885 break;
1886
1887 case 's':
1888 if (opP->mode != CONTROL
1889 || ! (opP->reg == FPI
1890 || opP->reg == FPS
1891 || opP->reg == FPC))
1892 losing++;
1893 break;
1894
1895 case 'S':
1896 if (opP->mode != CONTROL || opP->reg != SR)
1897 losing++;
1898 break;
1899
1900 case 't':
1901 if (opP->mode != IMMED)
1902 losing++;
1903 else if (opP->disp.exp.X_op != O_constant
1904 || TRUNC (opP->disp.exp.X_add_number) > 7)
1905 losing++;
1906 break;
1907
1908 case 'U':
1909 if (opP->mode != CONTROL || opP->reg != USP)
1910 losing++;
1911 break;
1912
1913 case 'x':
1914 if (opP->mode != IMMED)
1915 losing++;
1916 else if (opP->disp.exp.X_op != O_constant
1917 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1918 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1919 losing++;
1920 break;
1921
1922 /* JF these are out of order. We could put them
1923 in order if we were willing to put up with
1924 bunches of #ifdef m68851s in the code.
1925
1926 Don't forget that you need these operands
1927 to use 68030 MMU instructions. */
1928 #ifndef NO_68851
1929 /* Memory addressing mode used by pflushr. */
1930 case '|':
1931 if (opP->mode == CONTROL
1932 || opP->mode == FPREG
1933 || opP->mode == DREG
1934 || opP->mode == AREG
1935 || opP->mode == REGLST)
1936 losing++;
1937 /* We should accept immediate operands, but they
1938 supposedly have to be quad word, and we don't
1939 handle that. I would like to see what a Motorola
1940 assembler does before doing something here. */
1941 if (opP->mode == IMMED)
1942 losing++;
1943 break;
1944
1945 case 'f':
1946 if (opP->mode != CONTROL
1947 || (opP->reg != SFC && opP->reg != DFC))
1948 losing++;
1949 break;
1950
1951 case '0':
1952 if (opP->mode != CONTROL || opP->reg != TC)
1953 losing++;
1954 break;
1955
1956 case '1':
1957 if (opP->mode != CONTROL || opP->reg != AC)
1958 losing++;
1959 break;
1960
1961 case '2':
1962 if (opP->mode != CONTROL
1963 || (opP->reg != CAL
1964 && opP->reg != VAL
1965 && opP->reg != SCC))
1966 losing++;
1967 break;
1968
1969 case 'V':
1970 if (opP->mode != CONTROL
1971 || opP->reg != VAL)
1972 losing++;
1973 break;
1974
1975 case 'W':
1976 if (opP->mode != CONTROL
1977 || (opP->reg != DRP
1978 && opP->reg != SRP
1979 && opP->reg != CRP))
1980 losing++;
1981 break;
1982
1983 case 'w':
1984 switch (opP->mode)
1985 {
1986 case IMMED:
1987 case ABSL:
1988 case AREG:
1989 case DREG:
1990 case FPREG:
1991 case CONTROL:
1992 case POST:
1993 case PRE:
1994 case REGLST:
1995 losing++;
1996 break;
1997 default:
1998 break;
1999 }
2000 break;
2001
2002 case 'X':
2003 if (opP->mode != CONTROL
2004 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2005 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2006 losing++;
2007 break;
2008
2009 case 'Y':
2010 if (opP->mode != CONTROL || opP->reg != PSR)
2011 losing++;
2012 break;
2013
2014 case 'Z':
2015 if (opP->mode != CONTROL || opP->reg != PCSR)
2016 losing++;
2017 break;
2018 #endif
2019 case 'c':
2020 if (opP->mode != CONTROL
2021 || (opP->reg != NC
2022 && opP->reg != IC
2023 && opP->reg != DC
2024 && opP->reg != BC))
2025 losing++;
2026 break;
2027
2028 case '_':
2029 if (opP->mode != ABSL)
2030 ++losing;
2031 break;
2032
2033 case 'u':
2034 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2035 losing++;
2036 /* FIXME: kludge instead of fixing parser:
2037 upper/lower registers are *not* CONTROL
2038 registers, but ordinary ones. */
2039 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2040 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2041 opP->mode = DREG;
2042 else
2043 opP->mode = AREG;
2044 break;
2045
2046 case 'y':
2047 if (!(opP->mode == AINDR
2048 || (opP->mode == DISP
2049 && !(opP->reg == PC || opP->reg == ZPC))))
2050 losing++;
2051 break;
2052
2053 case 'z':
2054 if (!(opP->mode == AINDR || opP->mode == DISP))
2055 losing++;
2056 break;
2057
2058 default:
2059 abort ();
2060 }
2061
2062 if (losing)
2063 break;
2064 }
2065
2066 /* Since we have found the correct instruction, copy
2067 in the modifications that we may have made. */
2068 if (!losing)
2069 for (i = 0; i < opsfound; i++)
2070 the_ins.operands[i] = operands_backup[i];
2071 }
2072
2073 if (!losing)
2074 break;
2075
2076 opcode = opcode->m_next;
2077
2078 if (!opcode)
2079 {
2080 if (ok_arch
2081 && !(ok_arch & current_architecture))
2082 {
2083 const struct m68k_cpu *cpu;
2084 int any = 0;
2085 size_t space = 400;
2086 char *buf = xmalloc (space + 1);
2087 size_t len;
2088 int paren = 1;
2089
2090 the_ins.error = buf;
2091 /* Make sure there's a NUL at the end of the buffer -- strncpy
2092 won't write one when it runs out of buffer */
2093 buf[space] = 0;
2094 #define APPEND(STRING) \
2095 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2096
2097 APPEND (_("invalid instruction for this architecture; needs "));
2098 switch (ok_arch)
2099 {
2100 case mcfisa_a:
2101 APPEND (_("ColdFire ISA_A"));
2102 break;
2103 case mcfhwdiv:
2104 APPEND (_("ColdFire hardware divide"));
2105 break;
2106 case mcfisa_aa:
2107 APPEND (_("ColdFire ISA_A+"));
2108 break;
2109 case mcfisa_b:
2110 APPEND (_("ColdFire ISA_B"));
2111 break;
2112 case cfloat:
2113 APPEND (_("ColdFire fpu"));
2114 break;
2115 case mfloat:
2116 APPEND (_("M68K fpu"));
2117 break;
2118 case mmmu:
2119 APPEND (_("M68K mmu"));
2120 break;
2121 case m68020up:
2122 APPEND (_("68020 or higher"));
2123 break;
2124 case m68000up:
2125 APPEND (_("68000 or higher"));
2126 break;
2127 case m68010up:
2128 APPEND (_("68010 or higher"));
2129 break;
2130 default:
2131 paren = 0;
2132 }
2133 if (paren)
2134 APPEND (" (");
2135
2136 for (cpu = m68k_cpus; cpu->name; cpu++)
2137 if (!cpu->alias && (cpu->arch & ok_arch))
2138 {
2139 const struct m68k_cpu *alias;
2140 int seen_master = 0;
2141
2142 if (any)
2143 APPEND (", ");
2144 any = 0;
2145 APPEND (cpu->name);
2146 for (alias = cpu; alias != m68k_cpus; alias--)
2147 if (alias[-1].alias >= 0)
2148 break;
2149 for (; !seen_master || alias->alias > 0; alias++)
2150 {
2151 if (!alias->alias)
2152 seen_master = 1;
2153 else
2154 {
2155 if (any)
2156 APPEND (", ");
2157 else
2158 APPEND (" [");
2159 APPEND (alias->name);
2160 any = 1;
2161 }
2162 }
2163 if (any)
2164 APPEND ("]");
2165 any = 1;
2166 }
2167 if (paren)
2168 APPEND (")");
2169 #undef APPEND
2170 if (!space)
2171 {
2172 /* we ran out of space, so replace the end of the list
2173 with ellipsis. */
2174 buf -= 4;
2175 while (*buf != ' ')
2176 buf--;
2177 strcpy (buf, " ...");
2178 }
2179 }
2180 else
2181 the_ins.error = _("operands mismatch");
2182 return;
2183 }
2184
2185 losing = 0;
2186 }
2187
2188 /* Now assemble it. */
2189 the_ins.args = opcode->m_operands;
2190 the_ins.numargs = opcode->m_opnum;
2191 the_ins.numo = opcode->m_codenum;
2192 the_ins.opcode[0] = getone (opcode);
2193 the_ins.opcode[1] = gettwo (opcode);
2194
2195 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2196 {
2197 /* This switch is a doozy.
2198 Watch the first step; its a big one! */
2199 switch (s[0])
2200 {
2201
2202 case '*':
2203 case '~':
2204 case '%':
2205 case ';':
2206 case '@':
2207 case '!':
2208 case '&':
2209 case '$':
2210 case '?':
2211 case '/':
2212 case '<':
2213 case '>':
2214 case 'b':
2215 case 'm':
2216 case 'n':
2217 case 'o':
2218 case 'p':
2219 case 'q':
2220 case 'v':
2221 case 'w':
2222 case 'y':
2223 case 'z':
2224 case '4':
2225 #ifndef NO_68851
2226 case '|':
2227 #endif
2228 switch (opP->mode)
2229 {
2230 case IMMED:
2231 tmpreg = 0x3c; /* 7.4 */
2232 if (strchr ("bwl", s[1]))
2233 nextword = get_num (&opP->disp, 90);
2234 else
2235 nextword = get_num (&opP->disp, 0);
2236 if (isvar (&opP->disp))
2237 add_fix (s[1], &opP->disp, 0, 0);
2238 switch (s[1])
2239 {
2240 case 'b':
2241 if (!isbyte (nextword))
2242 opP->error = _("operand out of range");
2243 addword (nextword);
2244 baseo = 0;
2245 break;
2246 case 'w':
2247 if (!isword (nextword))
2248 opP->error = _("operand out of range");
2249 addword (nextword);
2250 baseo = 0;
2251 break;
2252 case 'W':
2253 if (!issword (nextword))
2254 opP->error = _("operand out of range");
2255 addword (nextword);
2256 baseo = 0;
2257 break;
2258 case 'l':
2259 addword (nextword >> 16);
2260 addword (nextword);
2261 baseo = 0;
2262 break;
2263
2264 case 'f':
2265 baseo = 2;
2266 outro = 8;
2267 break;
2268 case 'F':
2269 baseo = 4;
2270 outro = 11;
2271 break;
2272 case 'x':
2273 baseo = 6;
2274 outro = 15;
2275 break;
2276 case 'p':
2277 baseo = 6;
2278 outro = -1;
2279 break;
2280 default:
2281 abort ();
2282 }
2283 if (!baseo)
2284 break;
2285
2286 /* We gotta put out some float. */
2287 if (op (&opP->disp) != O_big)
2288 {
2289 valueT val;
2290 int gencnt;
2291
2292 /* Can other cases happen here? */
2293 if (op (&opP->disp) != O_constant)
2294 abort ();
2295
2296 val = (valueT) offs (&opP->disp);
2297 gencnt = 0;
2298 do
2299 {
2300 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2301 val >>= LITTLENUM_NUMBER_OF_BITS;
2302 ++gencnt;
2303 }
2304 while (val != 0);
2305 offs (&opP->disp) = gencnt;
2306 }
2307 if (offs (&opP->disp) > 0)
2308 {
2309 if (offs (&opP->disp) > baseo)
2310 {
2311 as_warn (_("Bignum too big for %c format; truncated"),
2312 s[1]);
2313 offs (&opP->disp) = baseo;
2314 }
2315 baseo -= offs (&opP->disp);
2316 while (baseo--)
2317 addword (0);
2318 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2319 offs (&opP->disp)--;
2320 --wordp)
2321 addword (*wordp);
2322 break;
2323 }
2324 gen_to_words (words, baseo, (long) outro);
2325 for (wordp = words; baseo--; wordp++)
2326 addword (*wordp);
2327 break;
2328 case DREG:
2329 tmpreg = opP->reg - DATA; /* 0.dreg */
2330 break;
2331 case AREG:
2332 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2333 break;
2334 case AINDR:
2335 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2336 break;
2337 case ADEC:
2338 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2339 break;
2340 case AINC:
2341 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2342 break;
2343 case DISP:
2344
2345 nextword = get_num (&opP->disp, 90);
2346
2347 /* Convert mode 5 addressing with a zero offset into
2348 mode 2 addressing to reduce the instruction size by a
2349 word. */
2350 if (! isvar (&opP->disp)
2351 && (nextword == 0)
2352 && (opP->disp.size == SIZE_UNSPEC)
2353 && (opP->reg >= ADDR0)
2354 && (opP->reg <= ADDR7))
2355 {
2356 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2357 break;
2358 }
2359
2360 if (opP->reg == PC
2361 && ! isvar (&opP->disp)
2362 && m68k_abspcadd)
2363 {
2364 opP->disp.exp.X_op = O_symbol;
2365 opP->disp.exp.X_add_symbol =
2366 section_symbol (absolute_section);
2367 }
2368
2369 /* Force into index mode. Hope this works. */
2370
2371 /* We do the first bit for 32-bit displacements, and the
2372 second bit for 16 bit ones. It is possible that we
2373 should make the default be WORD instead of LONG, but
2374 I think that'd break GCC, so we put up with a little
2375 inefficiency for the sake of working output. */
2376
2377 if (!issword (nextword)
2378 || (isvar (&opP->disp)
2379 && ((opP->disp.size == SIZE_UNSPEC
2380 && flag_short_refs == 0
2381 && cpu_of_arch (current_architecture) >= m68020
2382 && ! arch_coldfire_p (current_architecture))
2383 || opP->disp.size == SIZE_LONG)))
2384 {
2385 if (cpu_of_arch (current_architecture) < m68020
2386 || arch_coldfire_p (current_architecture))
2387 opP->error =
2388 _("displacement too large for this architecture; needs 68020 or higher");
2389 if (opP->reg == PC)
2390 tmpreg = 0x3B; /* 7.3 */
2391 else
2392 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2393 if (isvar (&opP->disp))
2394 {
2395 if (opP->reg == PC)
2396 {
2397 if (opP->disp.size == SIZE_LONG
2398 #ifdef OBJ_ELF
2399 /* If the displacement needs pic
2400 relocation it cannot be relaxed. */
2401 || opP->disp.pic_reloc != pic_none
2402 #endif
2403 )
2404 {
2405 addword (0x0170);
2406 add_fix ('l', &opP->disp, 1, 2);
2407 }
2408 else
2409 {
2410 add_frag (adds (&opP->disp),
2411 SEXT (offs (&opP->disp)),
2412 TAB (PCREL1632, SZ_UNDEF));
2413 break;
2414 }
2415 }
2416 else
2417 {
2418 addword (0x0170);
2419 add_fix ('l', &opP->disp, 0, 0);
2420 }
2421 }
2422 else
2423 addword (0x0170);
2424 addword (nextword >> 16);
2425 }
2426 else
2427 {
2428 if (opP->reg == PC)
2429 tmpreg = 0x3A; /* 7.2 */
2430 else
2431 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2432
2433 if (isvar (&opP->disp))
2434 {
2435 if (opP->reg == PC)
2436 {
2437 add_fix ('w', &opP->disp, 1, 0);
2438 }
2439 else
2440 add_fix ('w', &opP->disp, 0, 0);
2441 }
2442 }
2443 addword (nextword);
2444 break;
2445
2446 case POST:
2447 case PRE:
2448 case BASE:
2449 nextword = 0;
2450 baseo = get_num (&opP->disp, 90);
2451 if (opP->mode == POST || opP->mode == PRE)
2452 outro = get_num (&opP->odisp, 90);
2453 /* Figure out the `addressing mode'.
2454 Also turn on the BASE_DISABLE bit, if needed. */
2455 if (opP->reg == PC || opP->reg == ZPC)
2456 {
2457 tmpreg = 0x3b; /* 7.3 */
2458 if (opP->reg == ZPC)
2459 nextword |= 0x80;
2460 }
2461 else if (opP->reg == 0)
2462 {
2463 nextword |= 0x80;
2464 tmpreg = 0x30; /* 6.garbage */
2465 }
2466 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2467 {
2468 nextword |= 0x80;
2469 tmpreg = 0x30 + opP->reg - ZADDR0;
2470 }
2471 else
2472 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2473
2474 siz1 = opP->disp.size;
2475 if (opP->mode == POST || opP->mode == PRE)
2476 siz2 = opP->odisp.size;
2477 else
2478 siz2 = SIZE_UNSPEC;
2479
2480 /* Index register stuff. */
2481 if (opP->index.reg != 0
2482 && opP->index.reg >= DATA
2483 && opP->index.reg <= ADDR7)
2484 {
2485 nextword |= (opP->index.reg - DATA) << 12;
2486
2487 if (opP->index.size == SIZE_LONG
2488 || (opP->index.size == SIZE_UNSPEC
2489 && m68k_index_width_default == SIZE_LONG))
2490 nextword |= 0x800;
2491
2492 if ((opP->index.scale != 1
2493 && cpu_of_arch (current_architecture) < m68020)
2494 || (opP->index.scale == 8
2495 && (arch_coldfire_p (current_architecture)
2496 && !arch_coldfire_fpu (current_architecture))))
2497 {
2498 opP->error =
2499 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2500 }
2501
2502 if (arch_coldfire_p (current_architecture)
2503 && opP->index.size == SIZE_WORD)
2504 opP->error = _("invalid index size for coldfire");
2505
2506 switch (opP->index.scale)
2507 {
2508 case 1:
2509 break;
2510 case 2:
2511 nextword |= 0x200;
2512 break;
2513 case 4:
2514 nextword |= 0x400;
2515 break;
2516 case 8:
2517 nextword |= 0x600;
2518 break;
2519 default:
2520 abort ();
2521 }
2522 /* IF its simple,
2523 GET US OUT OF HERE! */
2524
2525 /* Must be INDEX, with an index register. Address
2526 register cannot be ZERO-PC, and either :b was
2527 forced, or we know it will fit. For a 68000 or
2528 68010, force this mode anyways, because the
2529 larger modes aren't supported. */
2530 if (opP->mode == BASE
2531 && ((opP->reg >= ADDR0
2532 && opP->reg <= ADDR7)
2533 || opP->reg == PC))
2534 {
2535 if (siz1 == SIZE_BYTE
2536 || cpu_of_arch (current_architecture) < m68020
2537 || arch_coldfire_p (current_architecture)
2538 || (siz1 == SIZE_UNSPEC
2539 && ! isvar (&opP->disp)
2540 && issbyte (baseo)))
2541 {
2542 nextword += baseo & 0xff;
2543 addword (nextword);
2544 if (isvar (&opP->disp))
2545 {
2546 /* Do a byte relocation. If it doesn't
2547 fit (possible on m68000) let the
2548 fixup processing complain later. */
2549 if (opP->reg == PC)
2550 add_fix ('B', &opP->disp, 1, 1);
2551 else
2552 add_fix ('B', &opP->disp, 0, 0);
2553 }
2554 else if (siz1 != SIZE_BYTE)
2555 {
2556 if (siz1 != SIZE_UNSPEC)
2557 as_warn (_("Forcing byte displacement"));
2558 if (! issbyte (baseo))
2559 opP->error = _("byte displacement out of range");
2560 }
2561
2562 break;
2563 }
2564 else if (siz1 == SIZE_UNSPEC
2565 && opP->reg == PC
2566 && isvar (&opP->disp)
2567 && subs (&opP->disp) == NULL
2568 #ifdef OBJ_ELF
2569 /* If the displacement needs pic
2570 relocation it cannot be relaxed. */
2571 && opP->disp.pic_reloc == pic_none
2572 #endif
2573 )
2574 {
2575 /* The code in md_convert_frag_1 needs to be
2576 able to adjust nextword. Call frag_grow
2577 to ensure that we have enough space in
2578 the frag obstack to make all the bytes
2579 contiguous. */
2580 frag_grow (14);
2581 nextword += baseo & 0xff;
2582 addword (nextword);
2583 add_frag (adds (&opP->disp),
2584 SEXT (offs (&opP->disp)),
2585 TAB (PCINDEX, SZ_UNDEF));
2586
2587 break;
2588 }
2589 }
2590 }
2591 else
2592 {
2593 nextword |= 0x40; /* No index reg. */
2594 if (opP->index.reg >= ZDATA0
2595 && opP->index.reg <= ZDATA7)
2596 nextword |= (opP->index.reg - ZDATA0) << 12;
2597 else if (opP->index.reg >= ZADDR0
2598 || opP->index.reg <= ZADDR7)
2599 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2600 }
2601
2602 /* It isn't simple. */
2603
2604 if (cpu_of_arch (current_architecture) < m68020
2605 || arch_coldfire_p (current_architecture))
2606 opP->error =
2607 _("invalid operand mode for this architecture; needs 68020 or higher");
2608
2609 nextword |= 0x100;
2610 /* If the guy specified a width, we assume that it is
2611 wide enough. Maybe it isn't. If so, we lose. */
2612 switch (siz1)
2613 {
2614 case SIZE_UNSPEC:
2615 if (isvar (&opP->disp)
2616 ? m68k_rel32
2617 : ! issword (baseo))
2618 {
2619 siz1 = SIZE_LONG;
2620 nextword |= 0x30;
2621 }
2622 else if (! isvar (&opP->disp) && baseo == 0)
2623 nextword |= 0x10;
2624 else
2625 {
2626 nextword |= 0x20;
2627 siz1 = SIZE_WORD;
2628 }
2629 break;
2630 case SIZE_BYTE:
2631 as_warn (_(":b not permitted; defaulting to :w"));
2632 /* Fall through. */
2633 case SIZE_WORD:
2634 nextword |= 0x20;
2635 break;
2636 case SIZE_LONG:
2637 nextword |= 0x30;
2638 break;
2639 }
2640
2641 /* Figure out inner displacement stuff. */
2642 if (opP->mode == POST || opP->mode == PRE)
2643 {
2644 if (cpu_of_arch (current_architecture) & cpu32)
2645 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2646 switch (siz2)
2647 {
2648 case SIZE_UNSPEC:
2649 if (isvar (&opP->odisp)
2650 ? m68k_rel32
2651 : ! issword (outro))
2652 {
2653 siz2 = SIZE_LONG;
2654 nextword |= 0x3;
2655 }
2656 else if (! isvar (&opP->odisp) && outro == 0)
2657 nextword |= 0x1;
2658 else
2659 {
2660 nextword |= 0x2;
2661 siz2 = SIZE_WORD;
2662 }
2663 break;
2664 case 1:
2665 as_warn (_(":b not permitted; defaulting to :w"));
2666 /* Fall through. */
2667 case 2:
2668 nextword |= 0x2;
2669 break;
2670 case 3:
2671 nextword |= 0x3;
2672 break;
2673 }
2674 if (opP->mode == POST
2675 && (nextword & 0x40) == 0)
2676 nextword |= 0x04;
2677 }
2678 addword (nextword);
2679
2680 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2681 {
2682 if (opP->reg == PC || opP->reg == ZPC)
2683 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2684 else
2685 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2686 }
2687 if (siz1 == SIZE_LONG)
2688 addword (baseo >> 16);
2689 if (siz1 != SIZE_UNSPEC)
2690 addword (baseo);
2691
2692 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2693 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2694 if (siz2 == SIZE_LONG)
2695 addword (outro >> 16);
2696 if (siz2 != SIZE_UNSPEC)
2697 addword (outro);
2698
2699 break;
2700
2701 case ABSL:
2702 nextword = get_num (&opP->disp, 90);
2703 switch (opP->disp.size)
2704 {
2705 default:
2706 abort ();
2707 case SIZE_UNSPEC:
2708 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2709 {
2710 tmpreg = 0x38; /* 7.0 */
2711 addword (nextword);
2712 break;
2713 }
2714 if (isvar (&opP->disp)
2715 && !subs (&opP->disp)
2716 && adds (&opP->disp)
2717 #ifdef OBJ_ELF
2718 /* If the displacement needs pic relocation it
2719 cannot be relaxed. */
2720 && opP->disp.pic_reloc == pic_none
2721 #endif
2722 && !flag_long_jumps
2723 && !strchr ("~%&$?", s[0]))
2724 {
2725 tmpreg = 0x3A; /* 7.2 */
2726 add_frag (adds (&opP->disp),
2727 SEXT (offs (&opP->disp)),
2728 TAB (ABSTOPCREL, SZ_UNDEF));
2729 break;
2730 }
2731 /* Fall through into long. */
2732 case SIZE_LONG:
2733 if (isvar (&opP->disp))
2734 add_fix ('l', &opP->disp, 0, 0);
2735
2736 tmpreg = 0x39;/* 7.1 mode */
2737 addword (nextword >> 16);
2738 addword (nextword);
2739 break;
2740
2741 case SIZE_BYTE:
2742 as_bad (_("unsupported byte value; use a different suffix"));
2743 /* Fall through. */
2744
2745 case SIZE_WORD:
2746 if (isvar (&opP->disp))
2747 add_fix ('w', &opP->disp, 0, 0);
2748
2749 tmpreg = 0x38;/* 7.0 mode */
2750 addword (nextword);
2751 break;
2752 }
2753 break;
2754 case CONTROL:
2755 case FPREG:
2756 default:
2757 as_bad (_("unknown/incorrect operand"));
2758 /* abort (); */
2759 }
2760
2761 /* If s[0] is '4', then this is for the mac instructions
2762 that can have a trailing_ampersand set. If so, set 0x100
2763 bit on tmpreg so install_gen_operand can check for it and
2764 set the appropriate bit (word2, bit 5). */
2765 if (s[0] == '4')
2766 {
2767 if (opP->trailing_ampersand)
2768 tmpreg |= 0x100;
2769 }
2770 install_gen_operand (s[1], tmpreg);
2771 break;
2772
2773 case '#':
2774 case '^':
2775 switch (s[1])
2776 { /* JF: I hate floating point! */
2777 case 'j':
2778 tmpreg = 70;
2779 break;
2780 case '8':
2781 tmpreg = 20;
2782 break;
2783 case 'C':
2784 tmpreg = 50;
2785 break;
2786 case '3':
2787 default:
2788 tmpreg = 90;
2789 break;
2790 }
2791 tmpreg = get_num (&opP->disp, tmpreg);
2792 if (isvar (&opP->disp))
2793 add_fix (s[1], &opP->disp, 0, 0);
2794 switch (s[1])
2795 {
2796 case 'b': /* Danger: These do no check for
2797 certain types of overflow.
2798 user beware! */
2799 if (!isbyte (tmpreg))
2800 opP->error = _("out of range");
2801 insop (tmpreg, opcode);
2802 if (isvar (&opP->disp))
2803 the_ins.reloc[the_ins.nrel - 1].n =
2804 (opcode->m_codenum) * 2 + 1;
2805 break;
2806 case 'B':
2807 if (!issbyte (tmpreg))
2808 opP->error = _("out of range");
2809 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2810 if (isvar (&opP->disp))
2811 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2812 break;
2813 case 'w':
2814 if (!isword (tmpreg))
2815 opP->error = _("out of range");
2816 insop (tmpreg, opcode);
2817 if (isvar (&opP->disp))
2818 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2819 break;
2820 case 'W':
2821 if (!issword (tmpreg))
2822 opP->error = _("out of range");
2823 insop (tmpreg, opcode);
2824 if (isvar (&opP->disp))
2825 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2826 break;
2827 case 'l':
2828 /* Because of the way insop works, we put these two out
2829 backwards. */
2830 insop (tmpreg, opcode);
2831 insop (tmpreg >> 16, opcode);
2832 if (isvar (&opP->disp))
2833 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2834 break;
2835 case '3':
2836 tmpreg &= 0xFF;
2837 case '8':
2838 case 'C':
2839 case 'j':
2840 install_operand (s[1], tmpreg);
2841 break;
2842 default:
2843 abort ();
2844 }
2845 break;
2846
2847 case '+':
2848 case '-':
2849 case 'A':
2850 case 'a':
2851 install_operand (s[1], opP->reg - ADDR);
2852 break;
2853
2854 case 'B':
2855 tmpreg = get_num (&opP->disp, 90);
2856 switch (s[1])
2857 {
2858 case 'B':
2859 add_fix ('B', &opP->disp, 1, -1);
2860 break;
2861 case 'W':
2862 add_fix ('w', &opP->disp, 1, 0);
2863 addword (0);
2864 break;
2865 case 'L':
2866 long_branch:
2867 if (! HAVE_LONG_BRANCH (current_architecture))
2868 as_warn (_("Can't use long branches on 68000/68010/5200"));
2869 the_ins.opcode[0] |= 0xff;
2870 add_fix ('l', &opP->disp, 1, 0);
2871 addword (0);
2872 addword (0);
2873 break;
2874 case 'g':
2875 if (subs (&opP->disp)) /* We can't relax it. */
2876 goto long_branch;
2877
2878 #ifdef OBJ_ELF
2879 /* If the displacement needs pic relocation it cannot be
2880 relaxed. */
2881 if (opP->disp.pic_reloc != pic_none)
2882 goto long_branch;
2883 #endif
2884 /* This could either be a symbol, or an absolute
2885 address. If it's an absolute address, turn it into
2886 an absolute jump right here and keep it out of the
2887 relaxer. */
2888 if (adds (&opP->disp) == 0)
2889 {
2890 if (the_ins.opcode[0] == 0x6000) /* jbra */
2891 the_ins.opcode[0] = 0x4EF9;
2892 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2893 the_ins.opcode[0] = 0x4EB9;
2894 else /* jCC */
2895 {
2896 the_ins.opcode[0] ^= 0x0100;
2897 the_ins.opcode[0] |= 0x0006;
2898 addword (0x4EF9);
2899 }
2900 add_fix ('l', &opP->disp, 0, 0);
2901 addword (0);
2902 addword (0);
2903 break;
2904 }
2905
2906 /* Now we know it's going into the relaxer. Now figure
2907 out which mode. We try in this order of preference:
2908 long branch, absolute jump, byte/word branches only. */
2909 if (HAVE_LONG_BRANCH (current_architecture))
2910 add_frag (adds (&opP->disp),
2911 SEXT (offs (&opP->disp)),
2912 TAB (BRANCHBWL, SZ_UNDEF));
2913 else if (! flag_keep_pcrel)
2914 {
2915 if ((the_ins.opcode[0] == 0x6000)
2916 || (the_ins.opcode[0] == 0x6100))
2917 add_frag (adds (&opP->disp),
2918 SEXT (offs (&opP->disp)),
2919 TAB (BRABSJUNC, SZ_UNDEF));
2920 else
2921 add_frag (adds (&opP->disp),
2922 SEXT (offs (&opP->disp)),
2923 TAB (BRABSJCOND, SZ_UNDEF));
2924 }
2925 else
2926 add_frag (adds (&opP->disp),
2927 SEXT (offs (&opP->disp)),
2928 TAB (BRANCHBW, SZ_UNDEF));
2929 break;
2930 case 'w':
2931 if (isvar (&opP->disp))
2932 {
2933 /* Check for DBcc instructions. We can relax them,
2934 but only if we have long branches and/or absolute
2935 jumps. */
2936 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2937 && (HAVE_LONG_BRANCH (current_architecture)
2938 || (! flag_keep_pcrel)))
2939 {
2940 if (HAVE_LONG_BRANCH (current_architecture))
2941 add_frag (adds (&opP->disp),
2942 SEXT (offs (&opP->disp)),
2943 TAB (DBCCLBR, SZ_UNDEF));
2944 else
2945 add_frag (adds (&opP->disp),
2946 SEXT (offs (&opP->disp)),
2947 TAB (DBCCABSJ, SZ_UNDEF));
2948 break;
2949 }
2950 add_fix ('w', &opP->disp, 1, 0);
2951 }
2952 addword (0);
2953 break;
2954 case 'C': /* Fixed size LONG coproc branches. */
2955 add_fix ('l', &opP->disp, 1, 0);
2956 addword (0);
2957 addword (0);
2958 break;
2959 case 'c': /* Var size Coprocesssor branches. */
2960 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2961 {
2962 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2963 add_fix ('l', &opP->disp, 1, 0);
2964 addword (0);
2965 addword (0);
2966 }
2967 else
2968 add_frag (adds (&opP->disp),
2969 SEXT (offs (&opP->disp)),
2970 TAB (FBRANCH, SZ_UNDEF));
2971 break;
2972 default:
2973 abort ();
2974 }
2975 break;
2976
2977 case 'C': /* Ignore it. */
2978 break;
2979
2980 case 'd': /* JF this is a kludge. */
2981 install_operand ('s', opP->reg - ADDR);
2982 tmpreg = get_num (&opP->disp, 90);
2983 if (!issword (tmpreg))
2984 {
2985 as_warn (_("Expression out of range, using 0"));
2986 tmpreg = 0;
2987 }
2988 addword (tmpreg);
2989 break;
2990
2991 case 'D':
2992 install_operand (s[1], opP->reg - DATA);
2993 break;
2994
2995 case 'e': /* EMAC ACCx, reg/reg. */
2996 install_operand (s[1], opP->reg - ACC);
2997 break;
2998
2999 case 'E': /* Ignore it. */
3000 break;
3001
3002 case 'F':
3003 install_operand (s[1], opP->reg - FP0);
3004 break;
3005
3006 case 'g': /* EMAC ACCEXTx. */
3007 install_operand (s[1], opP->reg - ACCEXT01);
3008 break;
3009
3010 case 'G': /* Ignore it. */
3011 case 'H':
3012 break;
3013
3014 case 'I':
3015 tmpreg = opP->reg - COP0;
3016 install_operand (s[1], tmpreg);
3017 break;
3018
3019 case 'i': /* MAC/EMAC scale factor. */
3020 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3021 break;
3022
3023 case 'J': /* JF foo. */
3024 switch (opP->reg)
3025 {
3026 case SFC:
3027 tmpreg = 0x000;
3028 break;
3029 case DFC:
3030 tmpreg = 0x001;
3031 break;
3032 case CACR:
3033 tmpreg = 0x002;
3034 break;
3035 case TC:
3036 case ASID:
3037 tmpreg = 0x003;
3038 break;
3039 case ACR0:
3040 case ITT0:
3041 tmpreg = 0x004;
3042 break;
3043 case ACR1:
3044 case ITT1:
3045 tmpreg = 0x005;
3046 break;
3047 case ACR2:
3048 case DTT0:
3049 tmpreg = 0x006;
3050 break;
3051 case ACR3:
3052 case DTT1:
3053 tmpreg = 0x007;
3054 break;
3055 case BUSCR:
3056 case MMUBAR:
3057 tmpreg = 0x008;
3058 break;
3059
3060 case USP:
3061 tmpreg = 0x800;
3062 break;
3063 case VBR:
3064 tmpreg = 0x801;
3065 break;
3066 case CAAR:
3067 tmpreg = 0x802;
3068 break;
3069 case MSP:
3070 tmpreg = 0x803;
3071 break;
3072 case ISP:
3073 tmpreg = 0x804;
3074 break;
3075 case MMUSR:
3076 tmpreg = 0x805;
3077 break;
3078 case URP:
3079 tmpreg = 0x806;
3080 break;
3081 case SRP:
3082 tmpreg = 0x807;
3083 break;
3084 case PCR:
3085 tmpreg = 0x808;
3086 break;
3087 case ROMBAR:
3088 case ROMBAR0:
3089 tmpreg = 0xC00;
3090 break;
3091 case ROMBAR1:
3092 tmpreg = 0xC01;
3093 break;
3094 case FLASHBAR:
3095 case RAMBAR0:
3096 case RAMBAR_ALT:
3097 tmpreg = 0xC04;
3098 break;
3099 case RAMBAR:
3100 case RAMBAR1:
3101 tmpreg = 0xC05;
3102 break;
3103 case MPCR:
3104 tmpreg = 0xC0C;
3105 break;
3106 case EDRAMBAR:
3107 tmpreg = 0xC0D;
3108 break;
3109 case MBAR0:
3110 case MBAR2:
3111 case SECMBAR:
3112 tmpreg = 0xC0E;
3113 break;
3114 case MBAR1:
3115 case MBAR:
3116 tmpreg = 0xC0F;
3117 break;
3118 case PCR1U0:
3119 tmpreg = 0xD02;
3120 break;
3121 case PCR1L0:
3122 tmpreg = 0xD03;
3123 break;
3124 case PCR2U0:
3125 tmpreg = 0xD04;
3126 break;
3127 case PCR2L0:
3128 tmpreg = 0xD05;
3129 break;
3130 case PCR3U0:
3131 tmpreg = 0xD06;
3132 break;
3133 case PCR3L0:
3134 tmpreg = 0xD07;
3135 break;
3136 case PCR1L1:
3137 tmpreg = 0xD0A;
3138 break;
3139 case PCR1U1:
3140 tmpreg = 0xD0B;
3141 break;
3142 case PCR2L1:
3143 tmpreg = 0xD0C;
3144 break;
3145 case PCR2U1:
3146 tmpreg = 0xD0D;
3147 break;
3148 case PCR3L1:
3149 tmpreg = 0xD0E;
3150 break;
3151 case PCR3U1:
3152 tmpreg = 0xD0F;
3153 break;
3154 case CAC:
3155 tmpreg = 0xFFE;
3156 break;
3157 case MBB:
3158 tmpreg = 0xFFF;
3159 break;
3160 default:
3161 abort ();
3162 }
3163 install_operand (s[1], tmpreg);
3164 break;
3165
3166 case 'k':
3167 tmpreg = get_num (&opP->disp, 55);
3168 install_operand (s[1], tmpreg & 0x7f);
3169 break;
3170
3171 case 'l':
3172 tmpreg = opP->mask;
3173 if (s[1] == 'w')
3174 {
3175 if (tmpreg & 0x7FF0000)
3176 as_bad (_("Floating point register in register list"));
3177 insop (reverse_16_bits (tmpreg), opcode);
3178 }
3179 else
3180 {
3181 if (tmpreg & 0x700FFFF)
3182 as_bad (_("Wrong register in floating-point reglist"));
3183 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3184 }
3185 break;
3186
3187 case 'L':
3188 tmpreg = opP->mask;
3189 if (s[1] == 'w')
3190 {
3191 if (tmpreg & 0x7FF0000)
3192 as_bad (_("Floating point register in register list"));
3193 insop (tmpreg, opcode);
3194 }
3195 else if (s[1] == '8')
3196 {
3197 if (tmpreg & 0x0FFFFFF)
3198 as_bad (_("incorrect register in reglist"));
3199 install_operand (s[1], tmpreg >> 24);
3200 }
3201 else
3202 {
3203 if (tmpreg & 0x700FFFF)
3204 as_bad (_("wrong register in floating-point reglist"));
3205 else
3206 install_operand (s[1], tmpreg >> 16);
3207 }
3208 break;
3209
3210 case 'M':
3211 install_operand (s[1], get_num (&opP->disp, 60));
3212 break;
3213
3214 case 'O':
3215 tmpreg = ((opP->mode == DREG)
3216 ? 0x20 + (int) (opP->reg - DATA)
3217 : (get_num (&opP->disp, 40) & 0x1F));
3218 install_operand (s[1], tmpreg);
3219 break;
3220
3221 case 'Q':
3222 tmpreg = get_num (&opP->disp, 10);
3223 if (tmpreg == 8)
3224 tmpreg = 0;
3225 install_operand (s[1], tmpreg);
3226 break;
3227
3228 case 'R':
3229 /* This depends on the fact that ADDR registers are eight
3230 more than their corresponding DATA regs, so the result
3231 will have the ADDR_REG bit set. */
3232 install_operand (s[1], opP->reg - DATA);
3233 break;
3234
3235 case 'r':
3236 if (opP->mode == AINDR)
3237 install_operand (s[1], opP->reg - DATA);
3238 else
3239 install_operand (s[1], opP->index.reg - DATA);
3240 break;
3241
3242 case 's':
3243 if (opP->reg == FPI)
3244 tmpreg = 0x1;
3245 else if (opP->reg == FPS)
3246 tmpreg = 0x2;
3247 else if (opP->reg == FPC)
3248 tmpreg = 0x4;
3249 else
3250 abort ();
3251 install_operand (s[1], tmpreg);
3252 break;
3253
3254 case 'S': /* Ignore it. */
3255 break;
3256
3257 case 'T':
3258 install_operand (s[1], get_num (&opP->disp, 30));
3259 break;
3260
3261 case 'U': /* Ignore it. */
3262 break;
3263
3264 case 'c':
3265 switch (opP->reg)
3266 {
3267 case NC:
3268 tmpreg = 0;
3269 break;
3270 case DC:
3271 tmpreg = 1;
3272 break;
3273 case IC:
3274 tmpreg = 2;
3275 break;
3276 case BC:
3277 tmpreg = 3;
3278 break;
3279 default:
3280 as_fatal (_("failed sanity check"));
3281 } /* switch on cache token. */
3282 install_operand (s[1], tmpreg);
3283 break;
3284 #ifndef NO_68851
3285 /* JF: These are out of order, I fear. */
3286 case 'f':
3287 switch (opP->reg)
3288 {
3289 case SFC:
3290 tmpreg = 0;
3291 break;
3292 case DFC:
3293 tmpreg = 1;
3294 break;
3295 default:
3296 abort ();
3297 }
3298 install_operand (s[1], tmpreg);
3299 break;
3300
3301 case '0':
3302 case '1':
3303 case '2':
3304 switch (opP->reg)
3305 {
3306 case TC:
3307 tmpreg = 0;
3308 break;
3309 case CAL:
3310 tmpreg = 4;
3311 break;
3312 case VAL:
3313 tmpreg = 5;
3314 break;
3315 case SCC:
3316 tmpreg = 6;
3317 break;
3318 case AC:
3319 tmpreg = 7;
3320 break;
3321 default:
3322 abort ();
3323 }
3324 install_operand (s[1], tmpreg);
3325 break;
3326
3327 case 'V':
3328 if (opP->reg == VAL)
3329 break;
3330 abort ();
3331
3332 case 'W':
3333 switch (opP->reg)
3334 {
3335 case DRP:
3336 tmpreg = 1;
3337 break;
3338 case SRP:
3339 tmpreg = 2;
3340 break;
3341 case CRP:
3342 tmpreg = 3;
3343 break;
3344 default:
3345 abort ();
3346 }
3347 install_operand (s[1], tmpreg);
3348 break;
3349
3350 case 'X':
3351 switch (opP->reg)
3352 {
3353 case BAD:
3354 case BAD + 1:
3355 case BAD + 2:
3356 case BAD + 3:
3357 case BAD + 4:
3358 case BAD + 5:
3359 case BAD + 6:
3360 case BAD + 7:
3361 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3362 break;
3363
3364 case BAC:
3365 case BAC + 1:
3366 case BAC + 2:
3367 case BAC + 3:
3368 case BAC + 4:
3369 case BAC + 5:
3370 case BAC + 6:
3371 case BAC + 7:
3372 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3373 break;
3374
3375 default:
3376 abort ();
3377 }
3378 install_operand (s[1], tmpreg);
3379 break;
3380 case 'Y':
3381 know (opP->reg == PSR);
3382 break;
3383 case 'Z':
3384 know (opP->reg == PCSR);
3385 break;
3386 #endif /* m68851 */
3387 case '3':
3388 switch (opP->reg)
3389 {
3390 case TT0:
3391 tmpreg = 2;
3392 break;
3393 case TT1:
3394 tmpreg = 3;
3395 break;
3396 default:
3397 abort ();
3398 }
3399 install_operand (s[1], tmpreg);
3400 break;
3401 case 't':
3402 tmpreg = get_num (&opP->disp, 20);
3403 install_operand (s[1], tmpreg);
3404 break;
3405 case '_': /* used only for move16 absolute 32-bit address. */
3406 if (isvar (&opP->disp))
3407 add_fix ('l', &opP->disp, 0, 0);
3408 tmpreg = get_num (&opP->disp, 90);
3409 addword (tmpreg >> 16);
3410 addword (tmpreg & 0xFFFF);
3411 break;
3412 case 'u':
3413 install_operand (s[1], opP->reg - DATA0L);
3414 opP->reg -= (DATA0L);
3415 opP->reg &= 0x0F; /* remove upper/lower bit. */
3416 break;
3417 case 'x':
3418 tmpreg = get_num (&opP->disp, 80);
3419 if (tmpreg == -1)
3420 tmpreg = 0;
3421 install_operand (s[1], tmpreg);
3422 break;
3423 default:
3424 abort ();
3425 }
3426 }
3427
3428 /* By the time whe get here (FINALLY) the_ins contains the complete
3429 instruction, ready to be emitted. . . */
3430 }
3431
3432 static int
3433 reverse_16_bits (int in)
3434 {
3435 int out = 0;
3436 int n;
3437
3438 static int mask[16] =
3439 {
3440 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3441 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3442 };
3443 for (n = 0; n < 16; n++)
3444 {
3445 if (in & mask[n])
3446 out |= mask[15 - n];
3447 }
3448 return out;
3449 } /* reverse_16_bits() */
3450
3451 static int
3452 reverse_8_bits (int in)
3453 {
3454 int out = 0;
3455 int n;
3456
3457 static int mask[8] =
3458 {
3459 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3460 };
3461
3462 for (n = 0; n < 8; n++)
3463 {
3464 if (in & mask[n])
3465 out |= mask[7 - n];
3466 }
3467 return out;
3468 } /* reverse_8_bits() */
3469
3470 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3471 (that value is chosen in the frag_var call in md_assemble). TYPE
3472 is the subtype of the frag to be generated; its primary type is
3473 rs_machine_dependent.
3474
3475 The TYPE parameter is also used by md_convert_frag_1 and
3476 md_estimate_size_before_relax. The appropriate type of fixup will
3477 be emitted by md_convert_frag_1.
3478
3479 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3480 static void
3481 install_operand (int mode, int val)
3482 {
3483 switch (mode)
3484 {
3485 case 's':
3486 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3487 break;
3488 case 'd':
3489 the_ins.opcode[0] |= val << 9;
3490 break;
3491 case '1':
3492 the_ins.opcode[1] |= val << 12;
3493 break;
3494 case '2':
3495 the_ins.opcode[1] |= val << 6;
3496 break;
3497 case '3':
3498 the_ins.opcode[1] |= val;
3499 break;
3500 case '4':
3501 the_ins.opcode[2] |= val << 12;
3502 break;
3503 case '5':
3504 the_ins.opcode[2] |= val << 6;
3505 break;
3506 case '6':
3507 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3508 three words long! */
3509 the_ins.numo++;
3510 the_ins.opcode[2] |= val;
3511 break;
3512 case '7':
3513 the_ins.opcode[1] |= val << 7;
3514 break;
3515 case '8':
3516 the_ins.opcode[1] |= val << 10;
3517 break;
3518 #ifndef NO_68851
3519 case '9':
3520 the_ins.opcode[1] |= val << 5;
3521 break;
3522 #endif
3523
3524 case 't':
3525 the_ins.opcode[1] |= (val << 10) | (val << 7);
3526 break;
3527 case 'D':
3528 the_ins.opcode[1] |= (val << 12) | val;
3529 break;
3530 case 'g':
3531 the_ins.opcode[0] |= val = 0xff;
3532 break;
3533 case 'i':
3534 the_ins.opcode[0] |= val << 9;
3535 break;
3536 case 'C':
3537 the_ins.opcode[1] |= val;
3538 break;
3539 case 'j':
3540 the_ins.opcode[1] |= val;
3541 the_ins.numo++; /* What a hack. */
3542 break;
3543 case 'k':
3544 the_ins.opcode[1] |= val << 4;
3545 break;
3546 case 'b':
3547 case 'w':
3548 case 'W':
3549 case 'l':
3550 break;
3551 case 'e':
3552 the_ins.opcode[0] |= (val << 6);
3553 break;
3554 case 'L':
3555 the_ins.opcode[1] = (val >> 16);
3556 the_ins.opcode[2] = val & 0xffff;
3557 break;
3558 case 'm':
3559 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3560 the_ins.opcode[0] |= ((val & 0x7) << 9);
3561 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3562 break;
3563 case 'n': /* MAC/EMAC Rx on !load. */
3564 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3565 the_ins.opcode[0] |= ((val & 0x7) << 9);
3566 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3567 break;
3568 case 'o': /* MAC/EMAC Rx on load. */
3569 the_ins.opcode[1] |= val << 12;
3570 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3571 break;
3572 case 'M': /* MAC/EMAC Ry on !load. */
3573 the_ins.opcode[0] |= (val & 0xF);
3574 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3575 break;
3576 case 'N': /* MAC/EMAC Ry on load. */
3577 the_ins.opcode[1] |= (val & 0xF);
3578 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3579 break;
3580 case 'h':
3581 the_ins.opcode[1] |= ((val != 1) << 10);
3582 break;
3583 case 'F':
3584 the_ins.opcode[0] |= ((val & 0x3) << 9);
3585 break;
3586 case 'f':
3587 the_ins.opcode[0] |= ((val & 0x3) << 0);
3588 break;
3589 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3590 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3591 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3592 break;
3593 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3594 the_ins.opcode[0] |= ((val & 0x1) << 7);
3595 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3596 break;
3597 case 'I':
3598 the_ins.opcode[1] |= ((val & 0x3) << 9);
3599 break;
3600 case ']':
3601 the_ins.opcode[0] |= (val & 0x1) <<10;
3602 break;
3603 case 'c':
3604 default:
3605 as_fatal (_("failed sanity check."));
3606 }
3607 }
3608
3609 static void
3610 install_gen_operand (int mode, int val)
3611 {
3612 switch (mode)
3613 {
3614 case '/': /* Special for mask loads for mac/msac insns with
3615 possible mask; trailing_ampersend set in bit 8. */
3616 the_ins.opcode[0] |= (val & 0x3f);
3617 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3618 break;
3619 case 's':
3620 the_ins.opcode[0] |= val;
3621 break;
3622 case 'd':
3623 /* This is a kludge!!! */
3624 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3625 break;
3626 case 'b':
3627 case 'w':
3628 case 'l':
3629 case 'f':
3630 case 'F':
3631 case 'x':
3632 case 'p':
3633 the_ins.opcode[0] |= val;
3634 break;
3635 /* more stuff goes here. */
3636 default:
3637 as_fatal (_("failed sanity check."));
3638 }
3639 }
3640
3641 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3642 then deal with the bitfield hack. */
3643
3644 static char *
3645 crack_operand (char *str, struct m68k_op *opP)
3646 {
3647 register int parens;
3648 register int c;
3649 register char *beg_str;
3650 int inquote = 0;
3651
3652 if (!str)
3653 {
3654 return str;
3655 }
3656 beg_str = str;
3657 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3658 {
3659 if (! inquote)
3660 {
3661 if (*str == '(')
3662 parens++;
3663 else if (*str == ')')
3664 {
3665 if (!parens)
3666 { /* ERROR. */
3667 opP->error = _("Extra )");
3668 return str;
3669 }
3670 --parens;
3671 }
3672 }
3673 if (flag_mri && *str == '\'')
3674 inquote = ! inquote;
3675 }
3676 if (!*str && parens)
3677 { /* ERROR. */
3678 opP->error = _("Missing )");
3679 return str;
3680 }
3681 c = *str;
3682 *str = '\0';
3683 if (m68k_ip_op (beg_str, opP) != 0)
3684 {
3685 *str = c;
3686 return str;
3687 }
3688 *str = c;
3689 if (c == '}')
3690 c = *++str; /* JF bitfield hack. */
3691 if (c)
3692 {
3693 c = *++str;
3694 if (!c)
3695 as_bad (_("Missing operand"));
3696 }
3697
3698 /* Detect MRI REG symbols and convert them to REGLSTs. */
3699 if (opP->mode == CONTROL && (int)opP->reg < 0)
3700 {
3701 opP->mode = REGLST;
3702 opP->mask = ~(int)opP->reg;
3703 opP->reg = 0;
3704 }
3705
3706 return str;
3707 }
3708
3709 /* This is the guts of the machine-dependent assembler. STR points to a
3710 machine dependent instruction. This function is supposed to emit
3711 the frags/bytes it assembles to.
3712 */
3713
3714 static void
3715 insert_reg (const char *regname, int regnum)
3716 {
3717 char buf[100];
3718 int i;
3719
3720 #ifdef REGISTER_PREFIX
3721 if (!flag_reg_prefix_optional)
3722 {
3723 buf[0] = REGISTER_PREFIX;
3724 strcpy (buf + 1, regname);
3725 regname = buf;
3726 }
3727 #endif
3728
3729 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3730 &zero_address_frag));
3731
3732 for (i = 0; regname[i]; i++)
3733 buf[i] = TOUPPER (regname[i]);
3734 buf[i] = '\0';
3735
3736 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3737 &zero_address_frag));
3738 }
3739
3740 struct init_entry
3741 {
3742 const char *name;
3743 int number;
3744 };
3745
3746 static const struct init_entry init_table[] =
3747 {
3748 { "d0", DATA0 },
3749 { "d1", DATA1 },
3750 { "d2", DATA2 },
3751 { "d3", DATA3 },
3752 { "d4", DATA4 },
3753 { "d5", DATA5 },
3754 { "d6", DATA6 },
3755 { "d7", DATA7 },
3756 { "a0", ADDR0 },
3757 { "a1", ADDR1 },
3758 { "a2", ADDR2 },
3759 { "a3", ADDR3 },
3760 { "a4", ADDR4 },
3761 { "a5", ADDR5 },
3762 { "a6", ADDR6 },
3763 { "fp", ADDR6 },
3764 { "a7", ADDR7 },
3765 { "sp", ADDR7 },
3766 { "ssp", ADDR7 },
3767 { "fp0", FP0 },
3768 { "fp1", FP1 },
3769 { "fp2", FP2 },
3770 { "fp3", FP3 },
3771 { "fp4", FP4 },
3772 { "fp5", FP5 },
3773 { "fp6", FP6 },
3774 { "fp7", FP7 },
3775 { "fpi", FPI },
3776 { "fpiar", FPI },
3777 { "fpc", FPI },
3778 { "fps", FPS },
3779 { "fpsr", FPS },
3780 { "fpc", FPC },
3781 { "fpcr", FPC },
3782 { "control", FPC },
3783 { "status", FPS },
3784 { "iaddr", FPI },
3785
3786 { "cop0", COP0 },
3787 { "cop1", COP1 },
3788 { "cop2", COP2 },
3789 { "cop3", COP3 },
3790 { "cop4", COP4 },
3791 { "cop5", COP5 },
3792 { "cop6", COP6 },
3793 { "cop7", COP7 },
3794 { "pc", PC },
3795 { "zpc", ZPC },
3796 { "sr", SR },
3797
3798 { "ccr", CCR },
3799 { "cc", CCR },
3800
3801 { "acc", ACC },
3802 { "acc0", ACC },
3803 { "acc1", ACC1 },
3804 { "acc2", ACC2 },
3805 { "acc3", ACC3 },
3806 { "accext01", ACCEXT01 },
3807 { "accext23", ACCEXT23 },
3808 { "macsr", MACSR },
3809 { "mask", MASK },
3810
3811 /* Control registers. */
3812 { "sfc", SFC }, /* Source Function Code. */
3813 { "sfcr", SFC },
3814 { "dfc", DFC }, /* Destination Function Code. */
3815 { "dfcr", DFC },
3816 { "cacr", CACR }, /* Cache Control Register. */
3817 { "caar", CAAR }, /* Cache Address Register. */
3818
3819 { "usp", USP }, /* User Stack Pointer. */
3820 { "vbr", VBR }, /* Vector Base Register. */
3821 { "msp", MSP }, /* Master Stack Pointer. */
3822 { "isp", ISP }, /* Interrupt Stack Pointer. */
3823
3824 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3825 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3826 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3827 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3828
3829 /* 68ec040 versions of same */
3830 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3831 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3832 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3833 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3834
3835 /* Coldfire versions of same. The ColdFire programmer's reference
3836 manual indicated that the order is 2,3,0,1, but Ken Rose
3837 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3838 { "acr0", ACR0 }, /* Access Control Unit 0. */
3839 { "acr1", ACR1 }, /* Access Control Unit 1. */
3840 { "acr2", ACR2 }, /* Access Control Unit 2. */
3841 { "acr3", ACR3 }, /* Access Control Unit 3. */
3842
3843 { "tc", TC }, /* MMU Translation Control Register. */
3844 { "tcr", TC },
3845 { "asid", ASID },
3846
3847 { "mmusr", MMUSR }, /* MMU Status Register. */
3848 { "srp", SRP }, /* User Root Pointer. */
3849 { "urp", URP }, /* Supervisor Root Pointer. */
3850
3851 { "buscr", BUSCR },
3852 { "mmubar", MMUBAR },
3853 { "pcr", PCR },
3854
3855 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3856 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3857 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3858 { "mbar", MBAR }, /* Module Base Address Register. */
3859
3860 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3861 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3862 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3863 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3864 { "mpcr", MPCR }, /* mcfv4e registers. */
3865 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3866 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3867 { "asid", TC }, /* mcfv4e registers. */
3868 { "mmubar", BUSCR }, /* mcfv4e registers. */
3869 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3870 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3871 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3872 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3873 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3874 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3875 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3876 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3877 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3878 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3879 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3880 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3881
3882 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3883 { "rambar", RAMBAR }, /* mcf528x registers. */
3884
3885 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3886
3887 { "cac", CAC }, /* fido registers. */
3888 { "mbb", MBB }, /* fido registers. */
3889 /* End of control registers. */
3890
3891 { "ac", AC },
3892 { "bc", BC },
3893 { "cal", CAL },
3894 { "crp", CRP },
3895 { "drp", DRP },
3896 { "pcsr", PCSR },
3897 { "psr", PSR },
3898 { "scc", SCC },
3899 { "val", VAL },
3900 { "bad0", BAD0 },
3901 { "bad1", BAD1 },
3902 { "bad2", BAD2 },
3903 { "bad3", BAD3 },
3904 { "bad4", BAD4 },
3905 { "bad5", BAD5 },
3906 { "bad6", BAD6 },
3907 { "bad7", BAD7 },
3908 { "bac0", BAC0 },
3909 { "bac1", BAC1 },
3910 { "bac2", BAC2 },
3911 { "bac3", BAC3 },
3912 { "bac4", BAC4 },
3913 { "bac5", BAC5 },
3914 { "bac6", BAC6 },
3915 { "bac7", BAC7 },
3916
3917 { "ic", IC },
3918 { "dc", DC },
3919 { "nc", NC },
3920
3921 { "tt0", TT0 },
3922 { "tt1", TT1 },
3923 /* 68ec030 versions of same. */
3924 { "ac0", TT0 },
3925 { "ac1", TT1 },
3926 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3927 { "acusr", PSR },
3928
3929 /* Suppressed data and address registers. */
3930 { "zd0", ZDATA0 },
3931 { "zd1", ZDATA1 },
3932 { "zd2", ZDATA2 },
3933 { "zd3", ZDATA3 },
3934 { "zd4", ZDATA4 },
3935 { "zd5", ZDATA5 },
3936 { "zd6", ZDATA6 },
3937 { "zd7", ZDATA7 },
3938 { "za0", ZADDR0 },
3939 { "za1", ZADDR1 },
3940 { "za2", ZADDR2 },
3941 { "za3", ZADDR3 },
3942 { "za4", ZADDR4 },
3943 { "za5", ZADDR5 },
3944 { "za6", ZADDR6 },
3945 { "za7", ZADDR7 },
3946
3947 /* Upper and lower data and address registers, used by macw and msacw. */
3948 { "d0l", DATA0L },
3949 { "d1l", DATA1L },
3950 { "d2l", DATA2L },
3951 { "d3l", DATA3L },
3952 { "d4l", DATA4L },
3953 { "d5l", DATA5L },
3954 { "d6l", DATA6L },
3955 { "d7l", DATA7L },
3956
3957 { "a0l", ADDR0L },
3958 { "a1l", ADDR1L },
3959 { "a2l", ADDR2L },
3960 { "a3l", ADDR3L },
3961 { "a4l", ADDR4L },
3962 { "a5l", ADDR5L },
3963 { "a6l", ADDR6L },
3964 { "a7l", ADDR7L },
3965
3966 { "d0u", DATA0U },
3967 { "d1u", DATA1U },
3968 { "d2u", DATA2U },
3969 { "d3u", DATA3U },
3970 { "d4u", DATA4U },
3971 { "d5u", DATA5U },
3972 { "d6u", DATA6U },
3973 { "d7u", DATA7U },
3974
3975 { "a0u", ADDR0U },
3976 { "a1u", ADDR1U },
3977 { "a2u", ADDR2U },
3978 { "a3u", ADDR3U },
3979 { "a4u", ADDR4U },
3980 { "a5u", ADDR5U },
3981 { "a6u", ADDR6U },
3982 { "a7u", ADDR7U },
3983
3984 { 0, 0 }
3985 };
3986
3987 static void
3988 init_regtable (void)
3989 {
3990 int i;
3991 for (i = 0; init_table[i].name; i++)
3992 insert_reg (init_table[i].name, init_table[i].number);
3993 }
3994
3995 void
3996 md_assemble (char *str)
3997 {
3998 const char *er;
3999 short *fromP;
4000 char *toP = NULL;
4001 int m, n = 0;
4002 char *to_beg_P;
4003 int shorts_this_frag;
4004 fixS *fixP;
4005
4006 if (!selected_cpu && !selected_arch)
4007 {
4008 /* We've not selected an architecture yet. Set the default
4009 now. We do this lazily so that an initial .cpu or .arch directive
4010 can specify. */
4011 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4012 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4013 }
4014 if (!initialized)
4015 m68k_init_arch ();
4016
4017 /* In MRI mode, the instruction and operands are separated by a
4018 space. Anything following the operands is a comment. The label
4019 has already been removed. */
4020 if (flag_mri)
4021 {
4022 char *s;
4023 int fields = 0;
4024 int infield = 0;
4025 int inquote = 0;
4026
4027 for (s = str; *s != '\0'; s++)
4028 {
4029 if ((*s == ' ' || *s == '\t') && ! inquote)
4030 {
4031 if (infield)
4032 {
4033 ++fields;
4034 if (fields >= 2)
4035 {
4036 *s = '\0';
4037 break;
4038 }
4039 infield = 0;
4040 }
4041 }
4042 else
4043 {
4044 if (! infield)
4045 infield = 1;
4046 if (*s == '\'')
4047 inquote = ! inquote;
4048 }
4049 }
4050 }
4051
4052 memset (&the_ins, '\0', sizeof (the_ins));
4053 m68k_ip (str);
4054 er = the_ins.error;
4055 if (!er)
4056 {
4057 for (n = 0; n < the_ins.numargs; n++)
4058 if (the_ins.operands[n].error)
4059 {
4060 er = the_ins.operands[n].error;
4061 break;
4062 }
4063 }
4064 if (er)
4065 {
4066 as_bad (_("%s -- statement `%s' ignored"), er, str);
4067 return;
4068 }
4069
4070 /* If there is a current label, record that it marks an instruction. */
4071 if (current_label != NULL)
4072 {
4073 current_label->text = 1;
4074 current_label = NULL;
4075 }
4076
4077 #ifdef OBJ_ELF
4078 /* Tie dwarf2 debug info to the address at the start of the insn. */
4079 dwarf2_emit_insn (0);
4080 #endif
4081
4082 if (the_ins.nfrag == 0)
4083 {
4084 /* No frag hacking involved; just put it out. */
4085 toP = frag_more (2 * the_ins.numo);
4086 fromP = &the_ins.opcode[0];
4087 for (m = the_ins.numo; m; --m)
4088 {
4089 md_number_to_chars (toP, (long) (*fromP), 2);
4090 toP += 2;
4091 fromP++;
4092 }
4093 /* Put out symbol-dependent info. */
4094 for (m = 0; m < the_ins.nrel; m++)
4095 {
4096 switch (the_ins.reloc[m].wid)
4097 {
4098 case 'B':
4099 n = 1;
4100 break;
4101 case 'b':
4102 n = 1;
4103 break;
4104 case '3':
4105 n = 1;
4106 break;
4107 case 'w':
4108 case 'W':
4109 n = 2;
4110 break;
4111 case 'l':
4112 n = 4;
4113 break;
4114 default:
4115 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4116 the_ins.reloc[m].wid);
4117 }
4118
4119 fixP = fix_new_exp (frag_now,
4120 ((toP - frag_now->fr_literal)
4121 - the_ins.numo * 2 + the_ins.reloc[m].n),
4122 n,
4123 &the_ins.reloc[m].exp,
4124 the_ins.reloc[m].pcrel,
4125 get_reloc_code (n, the_ins.reloc[m].pcrel,
4126 the_ins.reloc[m].pic_reloc));
4127 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4128 if (the_ins.reloc[m].wid == 'B')
4129 fixP->fx_signed = 1;
4130 }
4131 return;
4132 }
4133
4134 /* There's some frag hacking. */
4135 {
4136 /* Calculate the max frag size. */
4137 int wid;
4138
4139 wid = 2 * the_ins.fragb[0].fragoff;
4140 for (n = 1; n < the_ins.nfrag; n++)
4141 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4142 /* frag_var part. */
4143 wid += 10;
4144 /* Make sure the whole insn fits in one chunk, in particular that
4145 the var part is attached, as we access one byte before the
4146 variable frag for byte branches. */
4147 frag_grow (wid);
4148 }
4149
4150 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4151 {
4152 int wid;
4153
4154 if (n == 0)
4155 wid = 2 * the_ins.fragb[n].fragoff;
4156 else
4157 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4158 toP = frag_more (wid);
4159 to_beg_P = toP;
4160 shorts_this_frag = 0;
4161 for (m = wid / 2; m; --m)
4162 {
4163 md_number_to_chars (toP, (long) (*fromP), 2);
4164 toP += 2;
4165 fromP++;
4166 shorts_this_frag++;
4167 }
4168 for (m = 0; m < the_ins.nrel; m++)
4169 {
4170 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4171 {
4172 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4173 break;
4174 }
4175 wid = the_ins.reloc[m].wid;
4176 if (wid == 0)
4177 continue;
4178 the_ins.reloc[m].wid = 0;
4179 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4180
4181 fixP = fix_new_exp (frag_now,
4182 ((toP - frag_now->fr_literal)
4183 - the_ins.numo * 2 + the_ins.reloc[m].n),
4184 wid,
4185 &the_ins.reloc[m].exp,
4186 the_ins.reloc[m].pcrel,
4187 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4188 the_ins.reloc[m].pic_reloc));
4189 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4190 }
4191 (void) frag_var (rs_machine_dependent, 10, 0,
4192 (relax_substateT) (the_ins.fragb[n].fragty),
4193 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4194 }
4195 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4196 shorts_this_frag = 0;
4197 if (n)
4198 {
4199 toP = frag_more (n * 2);
4200 while (n--)
4201 {
4202 md_number_to_chars (toP, (long) (*fromP), 2);
4203 toP += 2;
4204 fromP++;
4205 shorts_this_frag++;
4206 }
4207 }
4208 for (m = 0; m < the_ins.nrel; m++)
4209 {
4210 int wid;
4211
4212 wid = the_ins.reloc[m].wid;
4213 if (wid == 0)
4214 continue;
4215 the_ins.reloc[m].wid = 0;
4216 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4217
4218 fixP = fix_new_exp (frag_now,
4219 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4220 - shorts_this_frag * 2),
4221 wid,
4222 &the_ins.reloc[m].exp,
4223 the_ins.reloc[m].pcrel,
4224 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4225 the_ins.reloc[m].pic_reloc));
4226 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4227 }
4228 }
4229
4230 /* Comparison function used by qsort to rank the opcode entries by name. */
4231
4232 static int
4233 m68k_compare_opcode (const void * v1, const void * v2)
4234 {
4235 struct m68k_opcode * op1, * op2;
4236 int ret;
4237
4238 if (v1 == v2)
4239 return 0;
4240
4241 op1 = *(struct m68k_opcode **) v1;
4242 op2 = *(struct m68k_opcode **) v2;
4243
4244 /* Compare the two names. If different, return the comparison.
4245 If the same, return the order they are in the opcode table. */
4246 ret = strcmp (op1->name, op2->name);
4247 if (ret)
4248 return ret;
4249 if (op1 < op2)
4250 return -1;
4251 return 1;
4252 }
4253
4254 void
4255 md_begin (void)
4256 {
4257 const struct m68k_opcode *ins;
4258 struct m68k_incant *hack, *slak;
4259 const char *retval = 0; /* Empty string, or error msg text. */
4260 int i;
4261
4262 /* Set up hash tables with 68000 instructions.
4263 similar to what the vax assembler does. */
4264 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4265 a copy of it at runtime, adding in the information we want but isn't
4266 there. I think it'd be better to have an awk script hack the table
4267 at compile time. Or even just xstr the table and use it as-is. But
4268 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4269 names. */
4270
4271 if (flag_mri)
4272 {
4273 flag_reg_prefix_optional = 1;
4274 m68k_abspcadd = 1;
4275 if (! m68k_rel32_from_cmdline)
4276 m68k_rel32 = 0;
4277 }
4278
4279 /* First sort the opcode table into alphabetical order to seperate
4280 the order that the assembler wants to see the opcodes from the
4281 order that the disassembler wants to see them. */
4282 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4283 if (!m68k_sorted_opcodes)
4284 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4285 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4286
4287 for (i = m68k_numopcodes; i--;)
4288 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4289
4290 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4291 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4292
4293 op_hash = hash_new ();
4294
4295 obstack_begin (&robyn, 4000);
4296 for (i = 0; i < m68k_numopcodes; i++)
4297 {
4298 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4299 do
4300 {
4301 ins = m68k_sorted_opcodes[i];
4302
4303 /* We *could* ignore insns that don't match our
4304 arch here by just leaving them out of the hash. */
4305 slak->m_operands = ins->args;
4306 slak->m_opnum = strlen (slak->m_operands) / 2;
4307 slak->m_arch = ins->arch;
4308 slak->m_opcode = ins->opcode;
4309 /* This is kludgey. */
4310 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4311 if (i + 1 != m68k_numopcodes
4312 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4313 {
4314 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4315 i++;
4316 }
4317 else
4318 slak->m_next = 0;
4319 slak = slak->m_next;
4320 }
4321 while (slak);
4322
4323 retval = hash_insert (op_hash, ins->name, (char *) hack);
4324 if (retval)
4325 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4326 }
4327
4328 for (i = 0; i < m68k_numaliases; i++)
4329 {
4330 const char *name = m68k_opcode_aliases[i].primary;
4331 const char *alias = m68k_opcode_aliases[i].alias;
4332 PTR val = hash_find (op_hash, name);
4333
4334 if (!val)
4335 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4336 retval = hash_insert (op_hash, alias, val);
4337 if (retval)
4338 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4339 }
4340
4341 /* In MRI mode, all unsized branches are variable sized. Normally,
4342 they are word sized. */
4343 if (flag_mri)
4344 {
4345 static struct m68k_opcode_alias mri_aliases[] =
4346 {
4347 { "bhi", "jhi", },
4348 { "bls", "jls", },
4349 { "bcc", "jcc", },
4350 { "bcs", "jcs", },
4351 { "bne", "jne", },
4352 { "beq", "jeq", },
4353 { "bvc", "jvc", },
4354 { "bvs", "jvs", },
4355 { "bpl", "jpl", },
4356 { "bmi", "jmi", },
4357 { "bge", "jge", },
4358 { "blt", "jlt", },
4359 { "bgt", "jgt", },
4360 { "ble", "jle", },
4361 { "bra", "jra", },
4362 { "bsr", "jbsr", },
4363 };
4364
4365 for (i = 0;
4366 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4367 i++)
4368 {
4369 const char *name = mri_aliases[i].primary;
4370 const char *alias = mri_aliases[i].alias;
4371 PTR val = hash_find (op_hash, name);
4372
4373 if (!val)
4374 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4375 retval = hash_jam (op_hash, alias, val);
4376 if (retval)
4377 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4378 }
4379 }
4380
4381 for (i = 0; i < (int) sizeof (notend_table); i++)
4382 {
4383 notend_table[i] = 0;
4384 alt_notend_table[i] = 0;
4385 }
4386
4387 notend_table[','] = 1;
4388 notend_table['{'] = 1;
4389 notend_table['}'] = 1;
4390 alt_notend_table['a'] = 1;
4391 alt_notend_table['A'] = 1;
4392 alt_notend_table['d'] = 1;
4393 alt_notend_table['D'] = 1;
4394 alt_notend_table['#'] = 1;
4395 alt_notend_table['&'] = 1;
4396 alt_notend_table['f'] = 1;
4397 alt_notend_table['F'] = 1;
4398 #ifdef REGISTER_PREFIX
4399 alt_notend_table[REGISTER_PREFIX] = 1;
4400 #endif
4401
4402 /* We need to put '(' in alt_notend_table to handle
4403 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4404 alt_notend_table['('] = 1;
4405
4406 /* We need to put '@' in alt_notend_table to handle
4407 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4408 alt_notend_table['@'] = 1;
4409
4410 /* We need to put digits in alt_notend_table to handle
4411 bfextu %d0{24:1},%d0 */
4412 alt_notend_table['0'] = 1;
4413 alt_notend_table['1'] = 1;
4414 alt_notend_table['2'] = 1;
4415 alt_notend_table['3'] = 1;
4416 alt_notend_table['4'] = 1;
4417 alt_notend_table['5'] = 1;
4418 alt_notend_table['6'] = 1;
4419 alt_notend_table['7'] = 1;
4420 alt_notend_table['8'] = 1;
4421 alt_notend_table['9'] = 1;
4422
4423 #ifndef MIT_SYNTAX_ONLY
4424 /* Insert pseudo ops, these have to go into the opcode table since
4425 gas expects pseudo ops to start with a dot. */
4426 {
4427 int n = 0;
4428
4429 while (mote_pseudo_table[n].poc_name)
4430 {
4431 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4432 hash_insert (op_hash,
4433 mote_pseudo_table[n].poc_name, (char *) hack);
4434 hack->m_operands = 0;
4435 hack->m_opnum = n;
4436 n++;
4437 }
4438 }
4439 #endif
4440
4441 init_regtable ();
4442
4443 #ifdef OBJ_ELF
4444 record_alignment (text_section, 2);
4445 record_alignment (data_section, 2);
4446 record_alignment (bss_section, 2);
4447 #endif
4448 }
4449
4450 \f
4451 /* This is called when a label is defined. */
4452
4453 void
4454 m68k_frob_label (symbolS *sym)
4455 {
4456 struct label_line *n;
4457
4458 n = (struct label_line *) xmalloc (sizeof *n);
4459 n->next = labels;
4460 n->label = sym;
4461 as_where (&n->file, &n->line);
4462 n->text = 0;
4463 labels = n;
4464 current_label = n;
4465
4466 #ifdef OBJ_ELF
4467 dwarf2_emit_label (sym);
4468 #endif
4469 }
4470
4471 /* This is called when a value that is not an instruction is emitted. */
4472
4473 void
4474 m68k_flush_pending_output (void)
4475 {
4476 current_label = NULL;
4477 }
4478
4479 /* This is called at the end of the assembly, when the final value of
4480 the label is known. We warn if this is a text symbol aligned at an
4481 odd location. */
4482
4483 void
4484 m68k_frob_symbol (symbolS *sym)
4485 {
4486 if (S_GET_SEGMENT (sym) == reg_section
4487 && (int) S_GET_VALUE (sym) < 0)
4488 {
4489 S_SET_SEGMENT (sym, absolute_section);
4490 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4491 }
4492 else if ((S_GET_VALUE (sym) & 1) != 0)
4493 {
4494 struct label_line *l;
4495
4496 for (l = labels; l != NULL; l = l->next)
4497 {
4498 if (l->label == sym)
4499 {
4500 if (l->text)
4501 as_warn_where (l->file, l->line,
4502 _("text label `%s' aligned to odd boundary"),
4503 S_GET_NAME (sym));
4504 break;
4505 }
4506 }
4507 }
4508 }
4509 \f
4510 /* This is called if we go in or out of MRI mode because of the .mri
4511 pseudo-op. */
4512
4513 void
4514 m68k_mri_mode_change (int on)
4515 {
4516 if (on)
4517 {
4518 if (! flag_reg_prefix_optional)
4519 {
4520 flag_reg_prefix_optional = 1;
4521 #ifdef REGISTER_PREFIX
4522 init_regtable ();
4523 #endif
4524 }
4525 m68k_abspcadd = 1;
4526 if (! m68k_rel32_from_cmdline)
4527 m68k_rel32 = 0;
4528 }
4529 else
4530 {
4531 if (! reg_prefix_optional_seen)
4532 {
4533 #ifdef REGISTER_PREFIX_OPTIONAL
4534 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4535 #else
4536 flag_reg_prefix_optional = 0;
4537 #endif
4538 #ifdef REGISTER_PREFIX
4539 init_regtable ();
4540 #endif
4541 }
4542 m68k_abspcadd = 0;
4543 if (! m68k_rel32_from_cmdline)
4544 m68k_rel32 = 1;
4545 }
4546 }
4547
4548 /* Equal to MAX_PRECISION in atof-ieee.c. */
4549 #define MAX_LITTLENUMS 6
4550
4551 /* Turn a string in input_line_pointer into a floating point constant
4552 of type TYPE, and store the appropriate bytes in *LITP. The number
4553 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4554 returned, or NULL on OK. */
4555
4556 char *
4557 md_atof (int type, char *litP, int *sizeP)
4558 {
4559 int prec;
4560 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4561 LITTLENUM_TYPE *wordP;
4562 char *t;
4563
4564 switch (type)
4565 {
4566 case 'f':
4567 case 'F':
4568 case 's':
4569 case 'S':
4570 prec = 2;
4571 break;
4572
4573 case 'd':
4574 case 'D':
4575 case 'r':
4576 case 'R':
4577 prec = 4;
4578 break;
4579
4580 case 'x':
4581 case 'X':
4582 prec = 6;
4583 break;
4584
4585 case 'p':
4586 case 'P':
4587 prec = 6;
4588 break;
4589
4590 default:
4591 *sizeP = 0;
4592 return _("Bad call to MD_ATOF()");
4593 }
4594 t = atof_ieee (input_line_pointer, type, words);
4595 if (t)
4596 input_line_pointer = t;
4597
4598 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4599 for (wordP = words; prec--;)
4600 {
4601 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4602 litP += sizeof (LITTLENUM_TYPE);
4603 }
4604 return 0;
4605 }
4606
4607 void
4608 md_number_to_chars (char *buf, valueT val, int n)
4609 {
4610 number_to_chars_bigendian (buf, val, n);
4611 }
4612
4613 void
4614 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4615 {
4616 offsetT val = *valP;
4617 addressT upper_limit;
4618 offsetT lower_limit;
4619
4620 /* This is unnecessary but it convinces the native rs6000 compiler
4621 to generate the code we want. */
4622 char *buf = fixP->fx_frag->fr_literal;
4623 buf += fixP->fx_where;
4624 /* End ibm compiler workaround. */
4625
4626 val = SEXT (val);
4627
4628 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4629 fixP->fx_done = 1;
4630
4631 #ifdef OBJ_ELF
4632 if (fixP->fx_addsy)
4633 {
4634 memset (buf, 0, fixP->fx_size);
4635 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4636
4637 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4638 && !S_IS_DEFINED (fixP->fx_addsy)
4639 && !S_IS_WEAK (fixP->fx_addsy))
4640 S_SET_WEAK (fixP->fx_addsy);
4641 return;
4642 }
4643 #endif
4644
4645 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4646 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4647 return;
4648
4649 switch (fixP->fx_size)
4650 {
4651 /* The cast to offsetT below are necessary to make code
4652 correct for machines where ints are smaller than offsetT. */
4653 case 1:
4654 *buf++ = val;
4655 upper_limit = 0x7f;
4656 lower_limit = - (offsetT) 0x80;
4657 break;
4658 case 2:
4659 *buf++ = (val >> 8);
4660 *buf++ = val;
4661 upper_limit = 0x7fff;
4662 lower_limit = - (offsetT) 0x8000;
4663 break;
4664 case 4:
4665 *buf++ = (val >> 24);
4666 *buf++ = (val >> 16);
4667 *buf++ = (val >> 8);
4668 *buf++ = val;
4669 upper_limit = 0x7fffffff;
4670 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4671 break;
4672 default:
4673 BAD_CASE (fixP->fx_size);
4674 }
4675
4676 /* Fix up a negative reloc. */
4677 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4678 {
4679 fixP->fx_addsy = fixP->fx_subsy;
4680 fixP->fx_subsy = NULL;
4681 fixP->fx_tcbit = 1;
4682 }
4683
4684 /* For non-pc-relative values, it's conceivable we might get something
4685 like "0xff" for a byte field. So extend the upper part of the range
4686 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4687 so that we can do any range checking at all. */
4688 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4689 upper_limit = upper_limit * 2 + 1;
4690
4691 if ((addressT) val > upper_limit
4692 && (val > 0 || val < lower_limit))
4693 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4694
4695 /* A one byte PC-relative reloc means a short branch. We can't use
4696 a short branch with a value of 0 or -1, because those indicate
4697 different opcodes (branches with longer offsets). fixup_segment
4698 in write.c may have clobbered fx_pcrel, so we need to examine the
4699 reloc type. */
4700 if ((fixP->fx_pcrel
4701 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4702 && fixP->fx_size == 1
4703 && (fixP->fx_addsy == NULL
4704 || S_IS_DEFINED (fixP->fx_addsy))
4705 && (val == 0 || val == -1))
4706 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4707 }
4708
4709 /* *fragP has been relaxed to its final size, and now needs to have
4710 the bytes inside it modified to conform to the new size There is UGLY
4711 MAGIC here. ..
4712 */
4713 static void
4714 md_convert_frag_1 (fragS *fragP)
4715 {
4716 long disp;
4717 fixS *fixP;
4718
4719 /* Address in object code of the displacement. */
4720 register int object_address = fragP->fr_fix + fragP->fr_address;
4721
4722 /* Address in gas core of the place to store the displacement. */
4723 /* This convinces the native rs6000 compiler to generate the code we
4724 want. */
4725 register char *buffer_address = fragP->fr_literal;
4726 buffer_address += fragP->fr_fix;
4727 /* End ibm compiler workaround. */
4728
4729 /* The displacement of the address, from current location. */
4730 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4731 disp = (disp + fragP->fr_offset) - object_address;
4732
4733 switch (fragP->fr_subtype)
4734 {
4735 case TAB (BRANCHBWL, BYTE):
4736 case TAB (BRABSJUNC, BYTE):
4737 case TAB (BRABSJCOND, BYTE):
4738 case TAB (BRANCHBW, BYTE):
4739 know (issbyte (disp));
4740 if (disp == 0)
4741 as_bad_where (fragP->fr_file, fragP->fr_line,
4742 _("short branch with zero offset: use :w"));
4743 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4744 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4745 fixP->fx_pcrel_adjust = -1;
4746 break;
4747 case TAB (BRANCHBWL, SHORT):
4748 case TAB (BRABSJUNC, SHORT):
4749 case TAB (BRABSJCOND, SHORT):
4750 case TAB (BRANCHBW, SHORT):
4751 fragP->fr_opcode[1] = 0x00;
4752 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4753 1, RELAX_RELOC_PC16);
4754 fragP->fr_fix += 2;
4755 break;
4756 case TAB (BRANCHBWL, LONG):
4757 fragP->fr_opcode[1] = (char) 0xFF;
4758 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4759 1, RELAX_RELOC_PC32);
4760 fragP->fr_fix += 4;
4761 break;
4762 case TAB (BRABSJUNC, LONG):
4763 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4764 {
4765 if (flag_keep_pcrel)
4766 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4767 fragP->fr_opcode[0] = 0x4E;
4768 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4769 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4770 0, RELAX_RELOC_ABS32);
4771 fragP->fr_fix += 4;
4772 }
4773 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4774 {
4775 if (flag_keep_pcrel)
4776 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4777 fragP->fr_opcode[0] = 0x4E;
4778 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4779 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4780 0, RELAX_RELOC_ABS32);
4781 fragP->fr_fix += 4;
4782 }
4783 else
4784 {
4785 /* This cannot happen, because jbsr and jbra are the only two
4786 unconditional branches. */
4787 abort ();
4788 }
4789 break;
4790 case TAB (BRABSJCOND, LONG):
4791 if (flag_keep_pcrel)
4792 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4793
4794 /* Only Bcc 68000 instructions can come here
4795 Change bcc into b!cc/jmp absl long. */
4796 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4797 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4798
4799 /* JF: these used to be fr_opcode[2,3], but they may be in a
4800 different frag, in which case referring to them is a no-no.
4801 Only fr_opcode[0,1] are guaranteed to work. */
4802 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4803 *buffer_address++ = (char) 0xf9;
4804 fragP->fr_fix += 2; /* Account for jmp instruction. */
4805 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4806 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4807 fragP->fr_fix += 4;
4808 break;
4809 case TAB (FBRANCH, SHORT):
4810 know ((fragP->fr_opcode[1] & 0x40) == 0);
4811 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4812 1, RELAX_RELOC_PC16);
4813 fragP->fr_fix += 2;
4814 break;
4815 case TAB (FBRANCH, LONG):
4816 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4817 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4818 1, RELAX_RELOC_PC32);
4819 fragP->fr_fix += 4;
4820 break;
4821 case TAB (DBCCLBR, SHORT):
4822 case TAB (DBCCABSJ, SHORT):
4823 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4824 1, RELAX_RELOC_PC16);
4825 fragP->fr_fix += 2;
4826 break;
4827 case TAB (DBCCLBR, LONG):
4828 /* Only DBcc instructions can come here.
4829 Change dbcc into dbcc/bral.
4830 JF: these used to be fr_opcode[2-7], but that's wrong. */
4831 if (flag_keep_pcrel)
4832 as_fatal (_("Tried to convert DBcc to absolute jump"));
4833
4834 *buffer_address++ = 0x00; /* Branch offset = 4. */
4835 *buffer_address++ = 0x04;
4836 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4837 *buffer_address++ = 0x06;
4838 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4839 *buffer_address++ = (char) 0xff;
4840
4841 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4842 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4843 RELAX_RELOC_PC32);
4844 fragP->fr_fix += 4;
4845 break;
4846 case TAB (DBCCABSJ, LONG):
4847 /* Only DBcc instructions can come here.
4848 Change dbcc into dbcc/jmp.
4849 JF: these used to be fr_opcode[2-7], but that's wrong. */
4850 if (flag_keep_pcrel)
4851 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4852
4853 *buffer_address++ = 0x00; /* Branch offset = 4. */
4854 *buffer_address++ = 0x04;
4855 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4856 *buffer_address++ = 0x06;
4857 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4858 *buffer_address++ = (char) 0xf9;
4859
4860 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4861 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4862 RELAX_RELOC_ABS32);
4863 fragP->fr_fix += 4;
4864 break;
4865 case TAB (PCREL1632, SHORT):
4866 fragP->fr_opcode[1] &= ~0x3F;
4867 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4868 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4869 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4870 fragP->fr_fix += 2;
4871 break;
4872 case TAB (PCREL1632, LONG):
4873 /* Already set to mode 7.3; this indicates: PC indirect with
4874 suppressed index, 32-bit displacement. */
4875 *buffer_address++ = 0x01;
4876 *buffer_address++ = 0x70;
4877 fragP->fr_fix += 2;
4878 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4879 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4880 fixP->fx_pcrel_adjust = 2;
4881 fragP->fr_fix += 4;
4882 break;
4883 case TAB (PCINDEX, BYTE):
4884 assert (fragP->fr_fix >= 2);
4885 buffer_address[-2] &= ~1;
4886 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4887 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4888 fixP->fx_pcrel_adjust = 1;
4889 break;
4890 case TAB (PCINDEX, SHORT):
4891 assert (fragP->fr_fix >= 2);
4892 buffer_address[-2] |= 0x1;
4893 buffer_address[-1] = 0x20;
4894 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4895 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4896 fixP->fx_pcrel_adjust = 2;
4897 fragP->fr_fix += 2;
4898 break;
4899 case TAB (PCINDEX, LONG):
4900 assert (fragP->fr_fix >= 2);
4901 buffer_address[-2] |= 0x1;
4902 buffer_address[-1] = 0x30;
4903 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4904 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4905 fixP->fx_pcrel_adjust = 2;
4906 fragP->fr_fix += 4;
4907 break;
4908 case TAB (ABSTOPCREL, SHORT):
4909 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4910 1, RELAX_RELOC_PC16);
4911 fragP->fr_fix += 2;
4912 break;
4913 case TAB (ABSTOPCREL, LONG):
4914 if (flag_keep_pcrel)
4915 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4916 /* The thing to do here is force it to ABSOLUTE LONG, since
4917 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4918 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4919 abort ();
4920 fragP->fr_opcode[1] &= ~0x3F;
4921 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4922 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4923 0, RELAX_RELOC_ABS32);
4924 fragP->fr_fix += 4;
4925 break;
4926 }
4927 }
4928
4929 void
4930 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4931 segT sec ATTRIBUTE_UNUSED,
4932 fragS *fragP)
4933 {
4934 md_convert_frag_1 (fragP);
4935 }
4936
4937 /* Force truly undefined symbols to their maximum size, and generally set up
4938 the frag list to be relaxed
4939 */
4940 int
4941 md_estimate_size_before_relax (fragS *fragP, segT segment)
4942 {
4943 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4944 switch (fragP->fr_subtype)
4945 {
4946 case TAB (BRANCHBWL, SZ_UNDEF):
4947 case TAB (BRABSJUNC, SZ_UNDEF):
4948 case TAB (BRABSJCOND, SZ_UNDEF):
4949 {
4950 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4951 && relaxable_symbol (fragP->fr_symbol))
4952 {
4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4954 }
4955 else if (flag_short_refs)
4956 {
4957 /* Symbol is undefined and we want short ref. */
4958 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4959 }
4960 else
4961 {
4962 /* Symbol is still undefined. Make it LONG. */
4963 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4964 }
4965 break;
4966 }
4967
4968 case TAB (BRANCHBW, SZ_UNDEF):
4969 {
4970 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4971 && relaxable_symbol (fragP->fr_symbol))
4972 {
4973 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4974 }
4975 else
4976 {
4977 /* Symbol is undefined and we don't have long branches. */
4978 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4979 }
4980 break;
4981 }
4982
4983 case TAB (FBRANCH, SZ_UNDEF):
4984 case TAB (DBCCLBR, SZ_UNDEF):
4985 case TAB (DBCCABSJ, SZ_UNDEF):
4986 case TAB (PCREL1632, SZ_UNDEF):
4987 {
4988 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4989 && relaxable_symbol (fragP->fr_symbol))
4990 || flag_short_refs)
4991 {
4992 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4993 }
4994 else
4995 {
4996 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4997 }
4998 break;
4999 }
5000
5001 case TAB (PCINDEX, SZ_UNDEF):
5002 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5003 && relaxable_symbol (fragP->fr_symbol)))
5004 {
5005 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5006 }
5007 else
5008 {
5009 fragP->fr_subtype = TAB (PCINDEX, LONG);
5010 }
5011 break;
5012
5013 case TAB (ABSTOPCREL, SZ_UNDEF):
5014 {
5015 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5016 && relaxable_symbol (fragP->fr_symbol)))
5017 {
5018 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5019 }
5020 else
5021 {
5022 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5023 }
5024 break;
5025 }
5026
5027 default:
5028 break;
5029 }
5030
5031 /* Now that SZ_UNDEF are taken care of, check others. */
5032 switch (fragP->fr_subtype)
5033 {
5034 case TAB (BRANCHBWL, BYTE):
5035 case TAB (BRABSJUNC, BYTE):
5036 case TAB (BRABSJCOND, BYTE):
5037 case TAB (BRANCHBW, BYTE):
5038 /* We can't do a short jump to the next instruction, so in that
5039 case we force word mode. If the symbol is at the start of a
5040 frag, and it is the next frag with any data in it (usually
5041 this is just the next frag, but assembler listings may
5042 introduce empty frags), we must use word mode. */
5043 if (fragP->fr_symbol)
5044 {
5045 fragS *sym_frag;
5046
5047 sym_frag = symbol_get_frag (fragP->fr_symbol);
5048 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5049 {
5050 fragS *l;
5051
5052 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5053 if (l->fr_fix != 0)
5054 break;
5055 if (l == sym_frag)
5056 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5057 }
5058 }
5059 break;
5060 default:
5061 break;
5062 }
5063 return md_relax_table[fragP->fr_subtype].rlx_length;
5064 }
5065
5066 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5067 /* the bit-field entries in the relocation_info struct plays hell
5068 with the byte-order problems of cross-assembly. So as a hack,
5069 I added this mach. dependent ri twiddler. Ugly, but it gets
5070 you there. -KWK */
5071 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5072 are symbolnum, most sig. byte first. Last byte is broken up with
5073 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5074 nibble as nuthin. (on Sun 3 at least) */
5075 /* Translate the internal relocation information into target-specific
5076 format. */
5077 #ifdef comment
5078 void
5079 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5080 {
5081 /* This is easy. */
5082 md_number_to_chars (the_bytes, ri->r_address, 4);
5083 /* Now the fun stuff. */
5084 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5085 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5086 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5087 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5088 | ((ri->r_length << 5) & 0x60)
5089 | ((ri->r_extern << 4) & 0x10));
5090 }
5091
5092 #endif
5093
5094 #endif /* OBJ_AOUT or OBJ_BOUT */
5095
5096 #ifndef WORKING_DOT_WORD
5097 int md_short_jump_size = 4;
5098 int md_long_jump_size = 6;
5099
5100 void
5101 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5102 fragS *frag ATTRIBUTE_UNUSED,
5103 symbolS *to_symbol ATTRIBUTE_UNUSED)
5104 {
5105 valueT offset;
5106
5107 offset = to_addr - (from_addr + 2);
5108
5109 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5110 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5111 }
5112
5113 void
5114 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5115 fragS *frag, symbolS *to_symbol)
5116 {
5117 valueT offset;
5118
5119 if (!HAVE_LONG_BRANCH (current_architecture))
5120 {
5121 if (flag_keep_pcrel)
5122 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5123 offset = to_addr - S_GET_VALUE (to_symbol);
5124 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5125 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5126 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5127 0, NO_RELOC);
5128 }
5129 else
5130 {
5131 offset = to_addr - (from_addr + 2);
5132 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5133 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5134 }
5135 }
5136
5137 #endif
5138
5139 /* Different values of OK tell what its OK to return. Things that
5140 aren't OK are an error (what a shock, no?)
5141
5142 0: Everything is OK
5143 10: Absolute 1:8 only
5144 20: Absolute 0:7 only
5145 30: absolute 0:15 only
5146 40: Absolute 0:31 only
5147 50: absolute 0:127 only
5148 55: absolute -64:63 only
5149 60: absolute -128:127 only
5150 70: absolute 0:4095 only
5151 80: absolute -1, 1:7 only
5152 90: No bignums. */
5153
5154 static int
5155 get_num (struct m68k_exp *exp, int ok)
5156 {
5157 if (exp->exp.X_op == O_absent)
5158 {
5159 /* Do the same thing the VAX asm does. */
5160 op (exp) = O_constant;
5161 adds (exp) = 0;
5162 subs (exp) = 0;
5163 offs (exp) = 0;
5164 if (ok == 10)
5165 {
5166 as_warn (_("expression out of range: defaulting to 1"));
5167 offs (exp) = 1;
5168 }
5169 }
5170 else if (exp->exp.X_op == O_constant)
5171 {
5172 switch (ok)
5173 {
5174 case 10:
5175 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5176 {
5177 as_warn (_("expression out of range: defaulting to 1"));
5178 offs (exp) = 1;
5179 }
5180 break;
5181 case 20:
5182 if ((valueT) TRUNC (offs (exp)) > 7)
5183 goto outrange;
5184 break;
5185 case 30:
5186 if ((valueT) TRUNC (offs (exp)) > 15)
5187 goto outrange;
5188 break;
5189 case 40:
5190 if ((valueT) TRUNC (offs (exp)) > 32)
5191 goto outrange;
5192 break;
5193 case 50:
5194 if ((valueT) TRUNC (offs (exp)) > 127)
5195 goto outrange;
5196 break;
5197 case 55:
5198 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5199 goto outrange;
5200 break;
5201 case 60:
5202 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5203 goto outrange;
5204 break;
5205 case 70:
5206 if ((valueT) TRUNC (offs (exp)) > 4095)
5207 {
5208 outrange:
5209 as_warn (_("expression out of range: defaulting to 0"));
5210 offs (exp) = 0;
5211 }
5212 break;
5213 case 80:
5214 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5215 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5216 {
5217 as_warn (_("expression out of range: defaulting to 1"));
5218 offs (exp) = 1;
5219 }
5220 break;
5221 default:
5222 break;
5223 }
5224 }
5225 else if (exp->exp.X_op == O_big)
5226 {
5227 if (offs (exp) <= 0 /* flonum. */
5228 && (ok == 90 /* no bignums */
5229 || (ok > 10 /* Small-int ranges including 0 ok. */
5230 /* If we have a flonum zero, a zero integer should
5231 do as well (e.g., in moveq). */
5232 && generic_floating_point_number.exponent == 0
5233 && generic_floating_point_number.low[0] == 0)))
5234 {
5235 /* HACK! Turn it into a long. */
5236 LITTLENUM_TYPE words[6];
5237
5238 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5239 op (exp) = O_constant;
5240 adds (exp) = 0;
5241 subs (exp) = 0;
5242 offs (exp) = words[1] | (words[0] << 16);
5243 }
5244 else if (ok != 0)
5245 {
5246 op (exp) = O_constant;
5247 adds (exp) = 0;
5248 subs (exp) = 0;
5249 offs (exp) = (ok == 10) ? 1 : 0;
5250 as_warn (_("Can't deal with expression; defaulting to %ld"),
5251 (long) offs (exp));
5252 }
5253 }
5254 else
5255 {
5256 if (ok >= 10 && ok <= 80)
5257 {
5258 op (exp) = O_constant;
5259 adds (exp) = 0;
5260 subs (exp) = 0;
5261 offs (exp) = (ok == 10) ? 1 : 0;
5262 as_warn (_("Can't deal with expression; defaulting to %ld"),
5263 (long) offs (exp));
5264 }
5265 }
5266
5267 if (exp->size != SIZE_UNSPEC)
5268 {
5269 switch (exp->size)
5270 {
5271 case SIZE_UNSPEC:
5272 case SIZE_LONG:
5273 break;
5274 case SIZE_BYTE:
5275 if (!isbyte (offs (exp)))
5276 as_warn (_("expression doesn't fit in BYTE"));
5277 break;
5278 case SIZE_WORD:
5279 if (!isword (offs (exp)))
5280 as_warn (_("expression doesn't fit in WORD"));
5281 break;
5282 }
5283 }
5284
5285 return offs (exp);
5286 }
5287
5288 /* These are the back-ends for the various machine dependent pseudo-ops. */
5289
5290 static void
5291 s_data1 (int ignore ATTRIBUTE_UNUSED)
5292 {
5293 subseg_set (data_section, 1);
5294 demand_empty_rest_of_line ();
5295 }
5296
5297 static void
5298 s_data2 (int ignore ATTRIBUTE_UNUSED)
5299 {
5300 subseg_set (data_section, 2);
5301 demand_empty_rest_of_line ();
5302 }
5303
5304 static void
5305 s_bss (int ignore ATTRIBUTE_UNUSED)
5306 {
5307 /* We don't support putting frags in the BSS segment, we fake it
5308 by marking in_bss, then looking at s_skip for clues. */
5309
5310 subseg_set (bss_section, 0);
5311 demand_empty_rest_of_line ();
5312 }
5313
5314 static void
5315 s_even (int ignore ATTRIBUTE_UNUSED)
5316 {
5317 register int temp;
5318 register long temp_fill;
5319
5320 temp = 1; /* JF should be 2? */
5321 temp_fill = get_absolute_expression ();
5322 if (!need_pass_2) /* Never make frag if expect extra pass. */
5323 frag_align (temp, (int) temp_fill, 0);
5324 demand_empty_rest_of_line ();
5325 record_alignment (now_seg, temp);
5326 }
5327
5328 static void
5329 s_proc (int ignore ATTRIBUTE_UNUSED)
5330 {
5331 demand_empty_rest_of_line ();
5332 }
5333 \f
5334 /* Pseudo-ops handled for MRI compatibility. */
5335
5336 /* This function returns non-zero if the argument is a conditional
5337 pseudo-op. This is called when checking whether a pending
5338 alignment is needed. */
5339
5340 int
5341 m68k_conditional_pseudoop (pseudo_typeS *pop)
5342 {
5343 return (pop->poc_handler == s_mri_if
5344 || pop->poc_handler == s_mri_else);
5345 }
5346
5347 /* Handle an MRI style chip specification. */
5348
5349 static void
5350 mri_chip (void)
5351 {
5352 char *s;
5353 char c;
5354 int i;
5355
5356 s = input_line_pointer;
5357 /* We can't use get_symbol_end since the processor names are not proper
5358 symbols. */
5359 while (is_part_of_name (c = *input_line_pointer++))
5360 ;
5361 *--input_line_pointer = 0;
5362 for (i = 0; m68k_cpus[i].name; i++)
5363 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5364 break;
5365 if (!m68k_cpus[i].name)
5366 {
5367 as_bad (_("%s: unrecognized processor name"), s);
5368 *input_line_pointer = c;
5369 ignore_rest_of_line ();
5370 return;
5371 }
5372 *input_line_pointer = c;
5373
5374 if (*input_line_pointer == '/')
5375 current_architecture = 0;
5376 else
5377 current_architecture &= m68881 | m68851;
5378 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5379 control_regs = m68k_cpus[i].control_regs;
5380
5381 while (*input_line_pointer == '/')
5382 {
5383 ++input_line_pointer;
5384 s = input_line_pointer;
5385 /* We can't use get_symbol_end since the processor names are not
5386 proper symbols. */
5387 while (is_part_of_name (c = *input_line_pointer++))
5388 ;
5389 *--input_line_pointer = 0;
5390 if (strcmp (s, "68881") == 0)
5391 current_architecture |= m68881;
5392 else if (strcmp (s, "68851") == 0)
5393 current_architecture |= m68851;
5394 *input_line_pointer = c;
5395 }
5396 }
5397
5398 /* The MRI CHIP pseudo-op. */
5399
5400 static void
5401 s_chip (int ignore ATTRIBUTE_UNUSED)
5402 {
5403 char *stop = NULL;
5404 char stopc;
5405
5406 if (flag_mri)
5407 stop = mri_comment_field (&stopc);
5408 mri_chip ();
5409 if (flag_mri)
5410 mri_comment_end (stop, stopc);
5411 demand_empty_rest_of_line ();
5412 }
5413
5414 /* The MRI FOPT pseudo-op. */
5415
5416 static void
5417 s_fopt (int ignore ATTRIBUTE_UNUSED)
5418 {
5419 SKIP_WHITESPACE ();
5420
5421 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5422 {
5423 int temp;
5424
5425 input_line_pointer += 3;
5426 temp = get_absolute_expression ();
5427 if (temp < 0 || temp > 7)
5428 as_bad (_("bad coprocessor id"));
5429 else
5430 m68k_float_copnum = COP0 + temp;
5431 }
5432 else
5433 {
5434 as_bad (_("unrecognized fopt option"));
5435 ignore_rest_of_line ();
5436 return;
5437 }
5438
5439 demand_empty_rest_of_line ();
5440 }
5441
5442 /* The structure used to handle the MRI OPT pseudo-op. */
5443
5444 struct opt_action
5445 {
5446 /* The name of the option. */
5447 const char *name;
5448
5449 /* If this is not NULL, just call this function. The first argument
5450 is the ARG field of this structure, the second argument is
5451 whether the option was negated. */
5452 void (*pfn) (int arg, int on);
5453
5454 /* If this is not NULL, and the PFN field is NULL, set the variable
5455 this points to. Set it to the ARG field if the option was not
5456 negated, and the NOTARG field otherwise. */
5457 int *pvar;
5458
5459 /* The value to pass to PFN or to assign to *PVAR. */
5460 int arg;
5461
5462 /* The value to assign to *PVAR if the option is negated. If PFN is
5463 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5464 the option may not be negated. */
5465 int notarg;
5466 };
5467
5468 /* The table used to handle the MRI OPT pseudo-op. */
5469
5470 static void skip_to_comma (int, int);
5471 static void opt_nest (int, int);
5472 static void opt_chip (int, int);
5473 static void opt_list (int, int);
5474 static void opt_list_symbols (int, int);
5475
5476 static const struct opt_action opt_table[] =
5477 {
5478 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5479
5480 /* We do relaxing, so there is little use for these options. */
5481 { "b", 0, 0, 0, 0 },
5482 { "brs", 0, 0, 0, 0 },
5483 { "brb", 0, 0, 0, 0 },
5484 { "brl", 0, 0, 0, 0 },
5485 { "brw", 0, 0, 0, 0 },
5486
5487 { "c", 0, 0, 0, 0 },
5488 { "cex", 0, 0, 0, 0 },
5489 { "case", 0, &symbols_case_sensitive, 1, 0 },
5490 { "cl", 0, 0, 0, 0 },
5491 { "cre", 0, 0, 0, 0 },
5492 { "d", 0, &flag_keep_locals, 1, 0 },
5493 { "e", 0, 0, 0, 0 },
5494 { "f", 0, &flag_short_refs, 1, 0 },
5495 { "frs", 0, &flag_short_refs, 1, 0 },
5496 { "frl", 0, &flag_short_refs, 0, 1 },
5497 { "g", 0, 0, 0, 0 },
5498 { "i", 0, 0, 0, 0 },
5499 { "m", 0, 0, 0, 0 },
5500 { "mex", 0, 0, 0, 0 },
5501 { "mc", 0, 0, 0, 0 },
5502 { "md", 0, 0, 0, 0 },
5503 { "nest", opt_nest, 0, 0, 0 },
5504 { "next", skip_to_comma, 0, 0, 0 },
5505 { "o", 0, 0, 0, 0 },
5506 { "old", 0, 0, 0, 0 },
5507 { "op", skip_to_comma, 0, 0, 0 },
5508 { "pco", 0, 0, 0, 0 },
5509 { "p", opt_chip, 0, 0, 0 },
5510 { "pcr", 0, 0, 0, 0 },
5511 { "pcs", 0, 0, 0, 0 },
5512 { "r", 0, 0, 0, 0 },
5513 { "quick", 0, &m68k_quick, 1, 0 },
5514 { "rel32", 0, &m68k_rel32, 1, 0 },
5515 { "s", opt_list, 0, 0, 0 },
5516 { "t", opt_list_symbols, 0, 0, 0 },
5517 { "w", 0, &flag_no_warnings, 0, 1 },
5518 { "x", 0, 0, 0, 0 }
5519 };
5520
5521 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5522
5523 /* The MRI OPT pseudo-op. */
5524
5525 static void
5526 s_opt (int ignore ATTRIBUTE_UNUSED)
5527 {
5528 do
5529 {
5530 int t;
5531 char *s;
5532 char c;
5533 int i;
5534 const struct opt_action *o;
5535
5536 SKIP_WHITESPACE ();
5537
5538 t = 1;
5539 if (*input_line_pointer == '-')
5540 {
5541 ++input_line_pointer;
5542 t = 0;
5543 }
5544 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5545 {
5546 input_line_pointer += 2;
5547 t = 0;
5548 }
5549
5550 s = input_line_pointer;
5551 c = get_symbol_end ();
5552
5553 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5554 {
5555 if (strcasecmp (s, o->name) == 0)
5556 {
5557 if (o->pfn)
5558 {
5559 /* Restore input_line_pointer now in case the option
5560 takes arguments. */
5561 *input_line_pointer = c;
5562 (*o->pfn) (o->arg, t);
5563 }
5564 else if (o->pvar != NULL)
5565 {
5566 if (! t && o->arg == o->notarg)
5567 as_bad (_("option `%s' may not be negated"), s);
5568 *input_line_pointer = c;
5569 *o->pvar = t ? o->arg : o->notarg;
5570 }
5571 else
5572 *input_line_pointer = c;
5573 break;
5574 }
5575 }
5576 if (i >= OPTCOUNT)
5577 {
5578 as_bad (_("option `%s' not recognized"), s);
5579 *input_line_pointer = c;
5580 }
5581 }
5582 while (*input_line_pointer++ == ',');
5583
5584 /* Move back to terminating character. */
5585 --input_line_pointer;
5586 demand_empty_rest_of_line ();
5587 }
5588
5589 /* Skip ahead to a comma. This is used for OPT options which we do
5590 not support and which take arguments. */
5591
5592 static void
5593 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5594 {
5595 while (*input_line_pointer != ','
5596 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5597 ++input_line_pointer;
5598 }
5599
5600 /* Handle the OPT NEST=depth option. */
5601
5602 static void
5603 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5604 {
5605 if (*input_line_pointer != '=')
5606 {
5607 as_bad (_("bad format of OPT NEST=depth"));
5608 return;
5609 }
5610
5611 ++input_line_pointer;
5612 max_macro_nest = get_absolute_expression ();
5613 }
5614
5615 /* Handle the OPT P=chip option. */
5616
5617 static void
5618 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5619 {
5620 if (*input_line_pointer != '=')
5621 {
5622 /* This is just OPT P, which we do not support. */
5623 return;
5624 }
5625
5626 ++input_line_pointer;
5627 mri_chip ();
5628 }
5629
5630 /* Handle the OPT S option. */
5631
5632 static void
5633 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5634 {
5635 listing_list (on);
5636 }
5637
5638 /* Handle the OPT T option. */
5639
5640 static void
5641 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5642 {
5643 if (on)
5644 listing |= LISTING_SYMBOLS;
5645 else
5646 listing &= ~LISTING_SYMBOLS;
5647 }
5648
5649 /* Handle the MRI REG pseudo-op. */
5650
5651 static void
5652 s_reg (int ignore ATTRIBUTE_UNUSED)
5653 {
5654 char *s;
5655 int c;
5656 struct m68k_op rop;
5657 int mask;
5658 char *stop = NULL;
5659 char stopc;
5660
5661 if (line_label == NULL)
5662 {
5663 as_bad (_("missing label"));
5664 ignore_rest_of_line ();
5665 return;
5666 }
5667
5668 if (flag_mri)
5669 stop = mri_comment_field (&stopc);
5670
5671 SKIP_WHITESPACE ();
5672
5673 s = input_line_pointer;
5674 while (ISALNUM (*input_line_pointer)
5675 #ifdef REGISTER_PREFIX
5676 || *input_line_pointer == REGISTER_PREFIX
5677 #endif
5678 || *input_line_pointer == '/'
5679 || *input_line_pointer == '-')
5680 ++input_line_pointer;
5681 c = *input_line_pointer;
5682 *input_line_pointer = '\0';
5683
5684 if (m68k_ip_op (s, &rop) != 0)
5685 {
5686 if (rop.error == NULL)
5687 as_bad (_("bad register list"));
5688 else
5689 as_bad (_("bad register list: %s"), rop.error);
5690 *input_line_pointer = c;
5691 ignore_rest_of_line ();
5692 return;
5693 }
5694
5695 *input_line_pointer = c;
5696
5697 if (rop.mode == REGLST)
5698 mask = rop.mask;
5699 else if (rop.mode == DREG)
5700 mask = 1 << (rop.reg - DATA0);
5701 else if (rop.mode == AREG)
5702 mask = 1 << (rop.reg - ADDR0 + 8);
5703 else if (rop.mode == FPREG)
5704 mask = 1 << (rop.reg - FP0 + 16);
5705 else if (rop.mode == CONTROL
5706 && rop.reg == FPI)
5707 mask = 1 << 24;
5708 else if (rop.mode == CONTROL
5709 && rop.reg == FPS)
5710 mask = 1 << 25;
5711 else if (rop.mode == CONTROL
5712 && rop.reg == FPC)
5713 mask = 1 << 26;
5714 else
5715 {
5716 as_bad (_("bad register list"));
5717 ignore_rest_of_line ();
5718 return;
5719 }
5720
5721 S_SET_SEGMENT (line_label, reg_section);
5722 S_SET_VALUE (line_label, ~mask);
5723 symbol_set_frag (line_label, &zero_address_frag);
5724
5725 if (flag_mri)
5726 mri_comment_end (stop, stopc);
5727
5728 demand_empty_rest_of_line ();
5729 }
5730
5731 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5732
5733 struct save_opts
5734 {
5735 struct save_opts *next;
5736 int abspcadd;
5737 int symbols_case_sensitive;
5738 int keep_locals;
5739 int short_refs;
5740 int architecture;
5741 const enum m68k_register *control_regs;
5742 int quick;
5743 int rel32;
5744 int listing;
5745 int no_warnings;
5746 /* FIXME: We don't save OPT S. */
5747 };
5748
5749 /* This variable holds the stack of saved options. */
5750
5751 static struct save_opts *save_stack;
5752
5753 /* The MRI SAVE pseudo-op. */
5754
5755 static void
5756 s_save (int ignore ATTRIBUTE_UNUSED)
5757 {
5758 struct save_opts *s;
5759
5760 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5761 s->abspcadd = m68k_abspcadd;
5762 s->symbols_case_sensitive = symbols_case_sensitive;
5763 s->keep_locals = flag_keep_locals;
5764 s->short_refs = flag_short_refs;
5765 s->architecture = current_architecture;
5766 s->control_regs = control_regs;
5767 s->quick = m68k_quick;
5768 s->rel32 = m68k_rel32;
5769 s->listing = listing;
5770 s->no_warnings = flag_no_warnings;
5771
5772 s->next = save_stack;
5773 save_stack = s;
5774
5775 demand_empty_rest_of_line ();
5776 }
5777
5778 /* The MRI RESTORE pseudo-op. */
5779
5780 static void
5781 s_restore (int ignore ATTRIBUTE_UNUSED)
5782 {
5783 struct save_opts *s;
5784
5785 if (save_stack == NULL)
5786 {
5787 as_bad (_("restore without save"));
5788 ignore_rest_of_line ();
5789 return;
5790 }
5791
5792 s = save_stack;
5793 save_stack = s->next;
5794
5795 m68k_abspcadd = s->abspcadd;
5796 symbols_case_sensitive = s->symbols_case_sensitive;
5797 flag_keep_locals = s->keep_locals;
5798 flag_short_refs = s->short_refs;
5799 current_architecture = s->architecture;
5800 control_regs = s->control_regs;
5801 m68k_quick = s->quick;
5802 m68k_rel32 = s->rel32;
5803 listing = s->listing;
5804 flag_no_warnings = s->no_warnings;
5805
5806 free (s);
5807
5808 demand_empty_rest_of_line ();
5809 }
5810
5811 /* Types of MRI structured control directives. */
5812
5813 enum mri_control_type
5814 {
5815 mri_for,
5816 mri_if,
5817 mri_repeat,
5818 mri_while
5819 };
5820
5821 /* This structure is used to stack the MRI structured control
5822 directives. */
5823
5824 struct mri_control_info
5825 {
5826 /* The directive within which this one is enclosed. */
5827 struct mri_control_info *outer;
5828
5829 /* The type of directive. */
5830 enum mri_control_type type;
5831
5832 /* Whether an ELSE has been in an IF. */
5833 int else_seen;
5834
5835 /* The add or sub statement at the end of a FOR. */
5836 char *incr;
5837
5838 /* The label of the top of a FOR or REPEAT loop. */
5839 char *top;
5840
5841 /* The label to jump to for the next iteration, or the else
5842 expression of a conditional. */
5843 char *next;
5844
5845 /* The label to jump to to break out of the loop, or the label past
5846 the end of a conditional. */
5847 char *bottom;
5848 };
5849
5850 /* The stack of MRI structured control directives. */
5851
5852 static struct mri_control_info *mri_control_stack;
5853
5854 /* The current MRI structured control directive index number, used to
5855 generate label names. */
5856
5857 static int mri_control_index;
5858
5859 /* Assemble an instruction for an MRI structured control directive. */
5860
5861 static void
5862 mri_assemble (char *str)
5863 {
5864 char *s;
5865
5866 /* md_assemble expects the opcode to be in lower case. */
5867 for (s = str; *s != ' ' && *s != '\0'; s++)
5868 *s = TOLOWER (*s);
5869
5870 md_assemble (str);
5871 }
5872
5873 /* Generate a new MRI label structured control directive label name. */
5874
5875 static char *
5876 mri_control_label (void)
5877 {
5878 char *n;
5879
5880 n = (char *) xmalloc (20);
5881 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5882 ++mri_control_index;
5883 return n;
5884 }
5885
5886 /* Create a new MRI structured control directive. */
5887
5888 static struct mri_control_info *
5889 push_mri_control (enum mri_control_type type)
5890 {
5891 struct mri_control_info *n;
5892
5893 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5894
5895 n->type = type;
5896 n->else_seen = 0;
5897 if (type == mri_if || type == mri_while)
5898 n->top = NULL;
5899 else
5900 n->top = mri_control_label ();
5901 n->next = mri_control_label ();
5902 n->bottom = mri_control_label ();
5903
5904 n->outer = mri_control_stack;
5905 mri_control_stack = n;
5906
5907 return n;
5908 }
5909
5910 /* Pop off the stack of MRI structured control directives. */
5911
5912 static void
5913 pop_mri_control (void)
5914 {
5915 struct mri_control_info *n;
5916
5917 n = mri_control_stack;
5918 mri_control_stack = n->outer;
5919 if (n->top != NULL)
5920 free (n->top);
5921 free (n->next);
5922 free (n->bottom);
5923 free (n);
5924 }
5925
5926 /* Recognize a condition code in an MRI structured control expression. */
5927
5928 static int
5929 parse_mri_condition (int *pcc)
5930 {
5931 char c1, c2;
5932
5933 know (*input_line_pointer == '<');
5934
5935 ++input_line_pointer;
5936 c1 = *input_line_pointer++;
5937 c2 = *input_line_pointer++;
5938
5939 if (*input_line_pointer != '>')
5940 {
5941 as_bad (_("syntax error in structured control directive"));
5942 return 0;
5943 }
5944
5945 ++input_line_pointer;
5946 SKIP_WHITESPACE ();
5947
5948 c1 = TOLOWER (c1);
5949 c2 = TOLOWER (c2);
5950
5951 *pcc = (c1 << 8) | c2;
5952
5953 return 1;
5954 }
5955
5956 /* Parse a single operand in an MRI structured control expression. */
5957
5958 static int
5959 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5960 char **rightstart, char **rightstop)
5961 {
5962 char *s;
5963
5964 SKIP_WHITESPACE ();
5965
5966 *pcc = -1;
5967 *leftstart = NULL;
5968 *leftstop = NULL;
5969 *rightstart = NULL;
5970 *rightstop = NULL;
5971
5972 if (*input_line_pointer == '<')
5973 {
5974 /* It's just a condition code. */
5975 return parse_mri_condition (pcc);
5976 }
5977
5978 /* Look ahead for the condition code. */
5979 for (s = input_line_pointer; *s != '\0'; ++s)
5980 {
5981 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5982 break;
5983 }
5984 if (*s == '\0')
5985 {
5986 as_bad (_("missing condition code in structured control directive"));
5987 return 0;
5988 }
5989
5990 *leftstart = input_line_pointer;
5991 *leftstop = s;
5992 if (*leftstop > *leftstart
5993 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5994 --*leftstop;
5995
5996 input_line_pointer = s;
5997 if (! parse_mri_condition (pcc))
5998 return 0;
5999
6000 /* Look ahead for AND or OR or end of line. */
6001 for (s = input_line_pointer; *s != '\0'; ++s)
6002 {
6003 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6004 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6005 ^^^ ^^ */
6006 if ((s == input_line_pointer
6007 || *(s-1) == ' '
6008 || *(s-1) == '\t')
6009 && ((strncasecmp (s, "AND", 3) == 0
6010 && (s[3] == '.' || ! is_part_of_name (s[3])))
6011 || (strncasecmp (s, "OR", 2) == 0
6012 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6013 break;
6014 }
6015
6016 *rightstart = input_line_pointer;
6017 *rightstop = s;
6018 if (*rightstop > *rightstart
6019 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6020 --*rightstop;
6021
6022 input_line_pointer = s;
6023
6024 return 1;
6025 }
6026
6027 #define MCC(b1, b2) (((b1) << 8) | (b2))
6028
6029 /* Swap the sense of a condition. This changes the condition so that
6030 it generates the same result when the operands are swapped. */
6031
6032 static int
6033 swap_mri_condition (int cc)
6034 {
6035 switch (cc)
6036 {
6037 case MCC ('h', 'i'): return MCC ('c', 's');
6038 case MCC ('l', 's'): return MCC ('c', 'c');
6039 /* <HS> is an alias for <CC>. */
6040 case MCC ('h', 's'):
6041 case MCC ('c', 'c'): return MCC ('l', 's');
6042 /* <LO> is an alias for <CS>. */
6043 case MCC ('l', 'o'):
6044 case MCC ('c', 's'): return MCC ('h', 'i');
6045 case MCC ('p', 'l'): return MCC ('m', 'i');
6046 case MCC ('m', 'i'): return MCC ('p', 'l');
6047 case MCC ('g', 'e'): return MCC ('l', 'e');
6048 case MCC ('l', 't'): return MCC ('g', 't');
6049 case MCC ('g', 't'): return MCC ('l', 't');
6050 case MCC ('l', 'e'): return MCC ('g', 'e');
6051 /* Issue a warning for conditions we can not swap. */
6052 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6053 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6054 case MCC ('v', 'c'):
6055 case MCC ('v', 's'):
6056 default :
6057 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6058 (char) (cc >> 8), (char) (cc));
6059 break;
6060 }
6061 return cc;
6062 }
6063
6064 /* Reverse the sense of a condition. */
6065
6066 static int
6067 reverse_mri_condition (int cc)
6068 {
6069 switch (cc)
6070 {
6071 case MCC ('h', 'i'): return MCC ('l', 's');
6072 case MCC ('l', 's'): return MCC ('h', 'i');
6073 /* <HS> is an alias for <CC> */
6074 case MCC ('h', 's'): return MCC ('l', 'o');
6075 case MCC ('c', 'c'): return MCC ('c', 's');
6076 /* <LO> is an alias for <CS> */
6077 case MCC ('l', 'o'): return MCC ('h', 's');
6078 case MCC ('c', 's'): return MCC ('c', 'c');
6079 case MCC ('n', 'e'): return MCC ('e', 'q');
6080 case MCC ('e', 'q'): return MCC ('n', 'e');
6081 case MCC ('v', 'c'): return MCC ('v', 's');
6082 case MCC ('v', 's'): return MCC ('v', 'c');
6083 case MCC ('p', 'l'): return MCC ('m', 'i');
6084 case MCC ('m', 'i'): return MCC ('p', 'l');
6085 case MCC ('g', 'e'): return MCC ('l', 't');
6086 case MCC ('l', 't'): return MCC ('g', 'e');
6087 case MCC ('g', 't'): return MCC ('l', 'e');
6088 case MCC ('l', 'e'): return MCC ('g', 't');
6089 }
6090 return cc;
6091 }
6092
6093 /* Build an MRI structured control expression. This generates test
6094 and branch instructions. It goes to TRUELAB if the condition is
6095 true, and to FALSELAB if the condition is false. Exactly one of
6096 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6097 is the size qualifier for the expression. EXTENT is the size to
6098 use for the branch. */
6099
6100 static void
6101 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6102 char *rightstart, char *rightstop,
6103 const char *truelab, const char *falselab,
6104 int extent)
6105 {
6106 char *buf;
6107 char *s;
6108
6109 if (leftstart != NULL)
6110 {
6111 struct m68k_op leftop, rightop;
6112 char c;
6113
6114 /* Swap the compare operands, if necessary, to produce a legal
6115 m68k compare instruction. Comparing a register operand with
6116 a non-register operand requires the register to be on the
6117 right (cmp, cmpa). Comparing an immediate value with
6118 anything requires the immediate value to be on the left
6119 (cmpi). */
6120
6121 c = *leftstop;
6122 *leftstop = '\0';
6123 (void) m68k_ip_op (leftstart, &leftop);
6124 *leftstop = c;
6125
6126 c = *rightstop;
6127 *rightstop = '\0';
6128 (void) m68k_ip_op (rightstart, &rightop);
6129 *rightstop = c;
6130
6131 if (rightop.mode == IMMED
6132 || ((leftop.mode == DREG || leftop.mode == AREG)
6133 && (rightop.mode != DREG && rightop.mode != AREG)))
6134 {
6135 char *temp;
6136
6137 /* Correct conditional handling:
6138 if #1 <lt> d0 then ;means if (1 < d0)
6139 ...
6140 endi
6141
6142 should assemble to:
6143
6144 cmp #1,d0 if we do *not* swap the operands
6145 bgt true we need the swapped condition!
6146 ble false
6147 true:
6148 ...
6149 false:
6150 */
6151 temp = leftstart;
6152 leftstart = rightstart;
6153 rightstart = temp;
6154 temp = leftstop;
6155 leftstop = rightstop;
6156 rightstop = temp;
6157 }
6158 else
6159 {
6160 cc = swap_mri_condition (cc);
6161 }
6162 }
6163
6164 if (truelab == NULL)
6165 {
6166 cc = reverse_mri_condition (cc);
6167 truelab = falselab;
6168 }
6169
6170 if (leftstart != NULL)
6171 {
6172 buf = (char *) xmalloc (20
6173 + (leftstop - leftstart)
6174 + (rightstop - rightstart));
6175 s = buf;
6176 *s++ = 'c';
6177 *s++ = 'm';
6178 *s++ = 'p';
6179 if (qual != '\0')
6180 *s++ = TOLOWER (qual);
6181 *s++ = ' ';
6182 memcpy (s, leftstart, leftstop - leftstart);
6183 s += leftstop - leftstart;
6184 *s++ = ',';
6185 memcpy (s, rightstart, rightstop - rightstart);
6186 s += rightstop - rightstart;
6187 *s = '\0';
6188 mri_assemble (buf);
6189 free (buf);
6190 }
6191
6192 buf = (char *) xmalloc (20 + strlen (truelab));
6193 s = buf;
6194 *s++ = 'b';
6195 *s++ = cc >> 8;
6196 *s++ = cc & 0xff;
6197 if (extent != '\0')
6198 *s++ = TOLOWER (extent);
6199 *s++ = ' ';
6200 strcpy (s, truelab);
6201 mri_assemble (buf);
6202 free (buf);
6203 }
6204
6205 /* Parse an MRI structured control expression. This generates test
6206 and branch instructions. STOP is where the expression ends. It
6207 goes to TRUELAB if the condition is true, and to FALSELAB if the
6208 condition is false. Exactly one of TRUELAB and FALSELAB will be
6209 NULL, meaning to fall through. QUAL is the size qualifier for the
6210 expression. EXTENT is the size to use for the branch. */
6211
6212 static void
6213 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6214 const char *falselab, int extent)
6215 {
6216 int c;
6217 int cc;
6218 char *leftstart;
6219 char *leftstop;
6220 char *rightstart;
6221 char *rightstop;
6222
6223 c = *stop;
6224 *stop = '\0';
6225
6226 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6227 &rightstart, &rightstop))
6228 {
6229 *stop = c;
6230 return;
6231 }
6232
6233 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6234 {
6235 const char *flab;
6236
6237 if (falselab != NULL)
6238 flab = falselab;
6239 else
6240 flab = mri_control_label ();
6241
6242 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6243 rightstop, (const char *) NULL, flab, extent);
6244
6245 input_line_pointer += 3;
6246 if (*input_line_pointer != '.'
6247 || input_line_pointer[1] == '\0')
6248 qual = '\0';
6249 else
6250 {
6251 qual = input_line_pointer[1];
6252 input_line_pointer += 2;
6253 }
6254
6255 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6256 &rightstart, &rightstop))
6257 {
6258 *stop = c;
6259 return;
6260 }
6261
6262 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6263 rightstop, truelab, falselab, extent);
6264
6265 if (falselab == NULL)
6266 colon (flab);
6267 }
6268 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6269 {
6270 const char *tlab;
6271
6272 if (truelab != NULL)
6273 tlab = truelab;
6274 else
6275 tlab = mri_control_label ();
6276
6277 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6278 rightstop, tlab, (const char *) NULL, extent);
6279
6280 input_line_pointer += 2;
6281 if (*input_line_pointer != '.'
6282 || input_line_pointer[1] == '\0')
6283 qual = '\0';
6284 else
6285 {
6286 qual = input_line_pointer[1];
6287 input_line_pointer += 2;
6288 }
6289
6290 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6291 &rightstart, &rightstop))
6292 {
6293 *stop = c;
6294 return;
6295 }
6296
6297 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6298 rightstop, truelab, falselab, extent);
6299
6300 if (truelab == NULL)
6301 colon (tlab);
6302 }
6303 else
6304 {
6305 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6306 rightstop, truelab, falselab, extent);
6307 }
6308
6309 *stop = c;
6310 if (input_line_pointer != stop)
6311 as_bad (_("syntax error in structured control directive"));
6312 }
6313
6314 /* Handle the MRI IF pseudo-op. This may be a structured control
6315 directive, or it may be a regular assembler conditional, depending
6316 on its operands. */
6317
6318 static void
6319 s_mri_if (int qual)
6320 {
6321 char *s;
6322 int c;
6323 struct mri_control_info *n;
6324
6325 /* A structured control directive must end with THEN with an
6326 optional qualifier. */
6327 s = input_line_pointer;
6328 /* We only accept '*' as introduction of comments if preceded by white space
6329 or at first column of a line (I think this can't actually happen here?)
6330 This is important when assembling:
6331 if d0 <ne> 12(a0,d0*2) then
6332 if d0 <ne> #CONST*20 then. */
6333 while (! (is_end_of_line[(unsigned char) *s]
6334 || (flag_mri
6335 && *s == '*'
6336 && (s == input_line_pointer
6337 || *(s-1) == ' '
6338 || *(s-1) == '\t'))))
6339 ++s;
6340 --s;
6341 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6342 --s;
6343
6344 if (s - input_line_pointer > 1
6345 && s[-1] == '.')
6346 s -= 2;
6347
6348 if (s - input_line_pointer < 3
6349 || strncasecmp (s - 3, "THEN", 4) != 0)
6350 {
6351 if (qual != '\0')
6352 {
6353 as_bad (_("missing then"));
6354 ignore_rest_of_line ();
6355 return;
6356 }
6357
6358 /* It's a conditional. */
6359 s_if (O_ne);
6360 return;
6361 }
6362
6363 /* Since this might be a conditional if, this pseudo-op will be
6364 called even if we are supported to be ignoring input. Double
6365 check now. Clobber *input_line_pointer so that ignore_input
6366 thinks that this is not a special pseudo-op. */
6367 c = *input_line_pointer;
6368 *input_line_pointer = 0;
6369 if (ignore_input ())
6370 {
6371 *input_line_pointer = c;
6372 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6373 ++input_line_pointer;
6374 demand_empty_rest_of_line ();
6375 return;
6376 }
6377 *input_line_pointer = c;
6378
6379 n = push_mri_control (mri_if);
6380
6381 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6382 n->next, s[1] == '.' ? s[2] : '\0');
6383
6384 if (s[1] == '.')
6385 input_line_pointer = s + 3;
6386 else
6387 input_line_pointer = s + 1;
6388
6389 if (flag_mri)
6390 {
6391 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6392 ++input_line_pointer;
6393 }
6394
6395 demand_empty_rest_of_line ();
6396 }
6397
6398 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6399 structured IF, associate the ELSE with the IF. Otherwise, assume
6400 it is a conditional else. */
6401
6402 static void
6403 s_mri_else (int qual)
6404 {
6405 int c;
6406 char *buf;
6407 char q[2];
6408
6409 if (qual == '\0'
6410 && (mri_control_stack == NULL
6411 || mri_control_stack->type != mri_if
6412 || mri_control_stack->else_seen))
6413 {
6414 s_else (0);
6415 return;
6416 }
6417
6418 c = *input_line_pointer;
6419 *input_line_pointer = 0;
6420 if (ignore_input ())
6421 {
6422 *input_line_pointer = c;
6423 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6424 ++input_line_pointer;
6425 demand_empty_rest_of_line ();
6426 return;
6427 }
6428 *input_line_pointer = c;
6429
6430 if (mri_control_stack == NULL
6431 || mri_control_stack->type != mri_if
6432 || mri_control_stack->else_seen)
6433 {
6434 as_bad (_("else without matching if"));
6435 ignore_rest_of_line ();
6436 return;
6437 }
6438
6439 mri_control_stack->else_seen = 1;
6440
6441 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6442 q[0] = TOLOWER (qual);
6443 q[1] = '\0';
6444 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6445 mri_assemble (buf);
6446 free (buf);
6447
6448 colon (mri_control_stack->next);
6449
6450 if (flag_mri)
6451 {
6452 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6453 ++input_line_pointer;
6454 }
6455
6456 demand_empty_rest_of_line ();
6457 }
6458
6459 /* Handle the MRI ENDI pseudo-op. */
6460
6461 static void
6462 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6463 {
6464 if (mri_control_stack == NULL
6465 || mri_control_stack->type != mri_if)
6466 {
6467 as_bad (_("endi without matching if"));
6468 ignore_rest_of_line ();
6469 return;
6470 }
6471
6472 /* ignore_input will not return true for ENDI, so we don't need to
6473 worry about checking it again here. */
6474
6475 if (! mri_control_stack->else_seen)
6476 colon (mri_control_stack->next);
6477 colon (mri_control_stack->bottom);
6478
6479 pop_mri_control ();
6480
6481 if (flag_mri)
6482 {
6483 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6484 ++input_line_pointer;
6485 }
6486
6487 demand_empty_rest_of_line ();
6488 }
6489
6490 /* Handle the MRI BREAK pseudo-op. */
6491
6492 static void
6493 s_mri_break (int extent)
6494 {
6495 struct mri_control_info *n;
6496 char *buf;
6497 char ex[2];
6498
6499 n = mri_control_stack;
6500 while (n != NULL
6501 && n->type != mri_for
6502 && n->type != mri_repeat
6503 && n->type != mri_while)
6504 n = n->outer;
6505 if (n == NULL)
6506 {
6507 as_bad (_("break outside of structured loop"));
6508 ignore_rest_of_line ();
6509 return;
6510 }
6511
6512 buf = (char *) xmalloc (20 + strlen (n->bottom));
6513 ex[0] = TOLOWER (extent);
6514 ex[1] = '\0';
6515 sprintf (buf, "bra%s %s", ex, n->bottom);
6516 mri_assemble (buf);
6517 free (buf);
6518
6519 if (flag_mri)
6520 {
6521 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6522 ++input_line_pointer;
6523 }
6524
6525 demand_empty_rest_of_line ();
6526 }
6527
6528 /* Handle the MRI NEXT pseudo-op. */
6529
6530 static void
6531 s_mri_next (int extent)
6532 {
6533 struct mri_control_info *n;
6534 char *buf;
6535 char ex[2];
6536
6537 n = mri_control_stack;
6538 while (n != NULL
6539 && n->type != mri_for
6540 && n->type != mri_repeat
6541 && n->type != mri_while)
6542 n = n->outer;
6543 if (n == NULL)
6544 {
6545 as_bad (_("next outside of structured loop"));
6546 ignore_rest_of_line ();
6547 return;
6548 }
6549
6550 buf = (char *) xmalloc (20 + strlen (n->next));
6551 ex[0] = TOLOWER (extent);
6552 ex[1] = '\0';
6553 sprintf (buf, "bra%s %s", ex, n->next);
6554 mri_assemble (buf);
6555 free (buf);
6556
6557 if (flag_mri)
6558 {
6559 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6560 ++input_line_pointer;
6561 }
6562
6563 demand_empty_rest_of_line ();
6564 }
6565
6566 /* Handle the MRI FOR pseudo-op. */
6567
6568 static void
6569 s_mri_for (int qual)
6570 {
6571 const char *varstart, *varstop;
6572 const char *initstart, *initstop;
6573 const char *endstart, *endstop;
6574 const char *bystart, *bystop;
6575 int up;
6576 int by;
6577 int extent;
6578 struct mri_control_info *n;
6579 char *buf;
6580 char *s;
6581 char ex[2];
6582
6583 /* The syntax is
6584 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6585 */
6586
6587 SKIP_WHITESPACE ();
6588 varstart = input_line_pointer;
6589
6590 /* Look for the '='. */
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6592 && *input_line_pointer != '=')
6593 ++input_line_pointer;
6594 if (*input_line_pointer != '=')
6595 {
6596 as_bad (_("missing ="));
6597 ignore_rest_of_line ();
6598 return;
6599 }
6600
6601 varstop = input_line_pointer;
6602 if (varstop > varstart
6603 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6604 --varstop;
6605
6606 ++input_line_pointer;
6607
6608 initstart = input_line_pointer;
6609
6610 /* Look for TO or DOWNTO. */
6611 up = 1;
6612 initstop = NULL;
6613 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6614 {
6615 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6616 && ! is_part_of_name (input_line_pointer[2]))
6617 {
6618 initstop = input_line_pointer;
6619 input_line_pointer += 2;
6620 break;
6621 }
6622 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6623 && ! is_part_of_name (input_line_pointer[6]))
6624 {
6625 initstop = input_line_pointer;
6626 up = 0;
6627 input_line_pointer += 6;
6628 break;
6629 }
6630 ++input_line_pointer;
6631 }
6632 if (initstop == NULL)
6633 {
6634 as_bad (_("missing to or downto"));
6635 ignore_rest_of_line ();
6636 return;
6637 }
6638 if (initstop > initstart
6639 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6640 --initstop;
6641
6642 SKIP_WHITESPACE ();
6643 endstart = input_line_pointer;
6644
6645 /* Look for BY or DO. */
6646 by = 0;
6647 endstop = NULL;
6648 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6649 {
6650 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6651 && ! is_part_of_name (input_line_pointer[2]))
6652 {
6653 endstop = input_line_pointer;
6654 by = 1;
6655 input_line_pointer += 2;
6656 break;
6657 }
6658 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6659 && (input_line_pointer[2] == '.'
6660 || ! is_part_of_name (input_line_pointer[2])))
6661 {
6662 endstop = input_line_pointer;
6663 input_line_pointer += 2;
6664 break;
6665 }
6666 ++input_line_pointer;
6667 }
6668 if (endstop == NULL)
6669 {
6670 as_bad (_("missing do"));
6671 ignore_rest_of_line ();
6672 return;
6673 }
6674 if (endstop > endstart
6675 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6676 --endstop;
6677
6678 if (! by)
6679 {
6680 bystart = "#1";
6681 bystop = bystart + 2;
6682 }
6683 else
6684 {
6685 SKIP_WHITESPACE ();
6686 bystart = input_line_pointer;
6687
6688 /* Look for DO. */
6689 bystop = NULL;
6690 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6691 {
6692 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6693 && (input_line_pointer[2] == '.'
6694 || ! is_part_of_name (input_line_pointer[2])))
6695 {
6696 bystop = input_line_pointer;
6697 input_line_pointer += 2;
6698 break;
6699 }
6700 ++input_line_pointer;
6701 }
6702 if (bystop == NULL)
6703 {
6704 as_bad (_("missing do"));
6705 ignore_rest_of_line ();
6706 return;
6707 }
6708 if (bystop > bystart
6709 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6710 --bystop;
6711 }
6712
6713 if (*input_line_pointer != '.')
6714 extent = '\0';
6715 else
6716 {
6717 extent = input_line_pointer[1];
6718 input_line_pointer += 2;
6719 }
6720
6721 /* We have fully parsed the FOR operands. Now build the loop. */
6722 n = push_mri_control (mri_for);
6723
6724 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6725
6726 /* Move init,var. */
6727 s = buf;
6728 *s++ = 'm';
6729 *s++ = 'o';
6730 *s++ = 'v';
6731 *s++ = 'e';
6732 if (qual != '\0')
6733 *s++ = TOLOWER (qual);
6734 *s++ = ' ';
6735 memcpy (s, initstart, initstop - initstart);
6736 s += initstop - initstart;
6737 *s++ = ',';
6738 memcpy (s, varstart, varstop - varstart);
6739 s += varstop - varstart;
6740 *s = '\0';
6741 mri_assemble (buf);
6742
6743 colon (n->top);
6744
6745 /* cmp end,var. */
6746 s = buf;
6747 *s++ = 'c';
6748 *s++ = 'm';
6749 *s++ = 'p';
6750 if (qual != '\0')
6751 *s++ = TOLOWER (qual);
6752 *s++ = ' ';
6753 memcpy (s, endstart, endstop - endstart);
6754 s += endstop - endstart;
6755 *s++ = ',';
6756 memcpy (s, varstart, varstop - varstart);
6757 s += varstop - varstart;
6758 *s = '\0';
6759 mri_assemble (buf);
6760
6761 /* bcc bottom. */
6762 ex[0] = TOLOWER (extent);
6763 ex[1] = '\0';
6764 if (up)
6765 sprintf (buf, "blt%s %s", ex, n->bottom);
6766 else
6767 sprintf (buf, "bgt%s %s", ex, n->bottom);
6768 mri_assemble (buf);
6769
6770 /* Put together the add or sub instruction used by ENDF. */
6771 s = buf;
6772 if (up)
6773 strcpy (s, "add");
6774 else
6775 strcpy (s, "sub");
6776 s += 3;
6777 if (qual != '\0')
6778 *s++ = TOLOWER (qual);
6779 *s++ = ' ';
6780 memcpy (s, bystart, bystop - bystart);
6781 s += bystop - bystart;
6782 *s++ = ',';
6783 memcpy (s, varstart, varstop - varstart);
6784 s += varstop - varstart;
6785 *s = '\0';
6786 n->incr = buf;
6787
6788 if (flag_mri)
6789 {
6790 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6791 ++input_line_pointer;
6792 }
6793
6794 demand_empty_rest_of_line ();
6795 }
6796
6797 /* Handle the MRI ENDF pseudo-op. */
6798
6799 static void
6800 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6801 {
6802 if (mri_control_stack == NULL
6803 || mri_control_stack->type != mri_for)
6804 {
6805 as_bad (_("endf without for"));
6806 ignore_rest_of_line ();
6807 return;
6808 }
6809
6810 colon (mri_control_stack->next);
6811
6812 mri_assemble (mri_control_stack->incr);
6813
6814 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6815 mri_assemble (mri_control_stack->incr);
6816
6817 free (mri_control_stack->incr);
6818
6819 colon (mri_control_stack->bottom);
6820
6821 pop_mri_control ();
6822
6823 if (flag_mri)
6824 {
6825 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6826 ++input_line_pointer;
6827 }
6828
6829 demand_empty_rest_of_line ();
6830 }
6831
6832 /* Handle the MRI REPEAT pseudo-op. */
6833
6834 static void
6835 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6836 {
6837 struct mri_control_info *n;
6838
6839 n = push_mri_control (mri_repeat);
6840 colon (n->top);
6841 if (flag_mri)
6842 {
6843 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6844 ++input_line_pointer;
6845 }
6846 demand_empty_rest_of_line ();
6847 }
6848
6849 /* Handle the MRI UNTIL pseudo-op. */
6850
6851 static void
6852 s_mri_until (int qual)
6853 {
6854 char *s;
6855
6856 if (mri_control_stack == NULL
6857 || mri_control_stack->type != mri_repeat)
6858 {
6859 as_bad (_("until without repeat"));
6860 ignore_rest_of_line ();
6861 return;
6862 }
6863
6864 colon (mri_control_stack->next);
6865
6866 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6867 ;
6868
6869 parse_mri_control_expression (s, qual, (const char *) NULL,
6870 mri_control_stack->top, '\0');
6871
6872 colon (mri_control_stack->bottom);
6873
6874 input_line_pointer = s;
6875
6876 pop_mri_control ();
6877
6878 if (flag_mri)
6879 {
6880 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6881 ++input_line_pointer;
6882 }
6883
6884 demand_empty_rest_of_line ();
6885 }
6886
6887 /* Handle the MRI WHILE pseudo-op. */
6888
6889 static void
6890 s_mri_while (int qual)
6891 {
6892 char *s;
6893
6894 struct mri_control_info *n;
6895
6896 s = input_line_pointer;
6897 /* We only accept '*' as introduction of comments if preceded by white space
6898 or at first column of a line (I think this can't actually happen here?)
6899 This is important when assembling:
6900 while d0 <ne> 12(a0,d0*2) do
6901 while d0 <ne> #CONST*20 do. */
6902 while (! (is_end_of_line[(unsigned char) *s]
6903 || (flag_mri
6904 && *s == '*'
6905 && (s == input_line_pointer
6906 || *(s-1) == ' '
6907 || *(s-1) == '\t'))))
6908 s++;
6909 --s;
6910 while (*s == ' ' || *s == '\t')
6911 --s;
6912 if (s - input_line_pointer > 1
6913 && s[-1] == '.')
6914 s -= 2;
6915 if (s - input_line_pointer < 2
6916 || strncasecmp (s - 1, "DO", 2) != 0)
6917 {
6918 as_bad (_("missing do"));
6919 ignore_rest_of_line ();
6920 return;
6921 }
6922
6923 n = push_mri_control (mri_while);
6924
6925 colon (n->next);
6926
6927 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6928 s[1] == '.' ? s[2] : '\0');
6929
6930 input_line_pointer = s + 1;
6931 if (*input_line_pointer == '.')
6932 input_line_pointer += 2;
6933
6934 if (flag_mri)
6935 {
6936 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6937 ++input_line_pointer;
6938 }
6939
6940 demand_empty_rest_of_line ();
6941 }
6942
6943 /* Handle the MRI ENDW pseudo-op. */
6944
6945 static void
6946 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6947 {
6948 char *buf;
6949
6950 if (mri_control_stack == NULL
6951 || mri_control_stack->type != mri_while)
6952 {
6953 as_bad (_("endw without while"));
6954 ignore_rest_of_line ();
6955 return;
6956 }
6957
6958 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6959 sprintf (buf, "bra %s", mri_control_stack->next);
6960 mri_assemble (buf);
6961 free (buf);
6962
6963 colon (mri_control_stack->bottom);
6964
6965 pop_mri_control ();
6966
6967 if (flag_mri)
6968 {
6969 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6970 ++input_line_pointer;
6971 }
6972
6973 demand_empty_rest_of_line ();
6974 }
6975 \f
6976 /* Parse a .cpu directive. */
6977
6978 static void
6979 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6980 {
6981 char saved_char;
6982 char *name;
6983
6984 if (initialized)
6985 {
6986 as_bad (_("already assembled instructions"));
6987 ignore_rest_of_line ();
6988 return;
6989 }
6990
6991 name = input_line_pointer;
6992 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6993 input_line_pointer++;
6994 saved_char = *input_line_pointer;
6995 *input_line_pointer = 0;
6996
6997 m68k_set_cpu (name, 1, 0);
6998
6999 *input_line_pointer = saved_char;
7000 demand_empty_rest_of_line ();
7001 return;
7002 }
7003
7004 /* Parse a .arch directive. */
7005
7006 static void
7007 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7008 {
7009 char saved_char;
7010 char *name;
7011
7012 if (initialized)
7013 {
7014 as_bad (_("already assembled instructions"));
7015 ignore_rest_of_line ();
7016 return;
7017 }
7018
7019 name = input_line_pointer;
7020 while (*input_line_pointer && *input_line_pointer != ','
7021 && !ISSPACE (*input_line_pointer))
7022 input_line_pointer++;
7023 saved_char = *input_line_pointer;
7024 *input_line_pointer = 0;
7025
7026 if (m68k_set_arch (name, 1, 0))
7027 {
7028 /* Scan extensions. */
7029 do
7030 {
7031 *input_line_pointer++ = saved_char;
7032 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7033 break;
7034 name = input_line_pointer;
7035 while (*input_line_pointer && *input_line_pointer != ','
7036 && !ISSPACE (*input_line_pointer))
7037 input_line_pointer++;
7038 saved_char = *input_line_pointer;
7039 *input_line_pointer = 0;
7040 }
7041 while (m68k_set_extension (name, 1, 0));
7042 }
7043
7044 *input_line_pointer = saved_char;
7045 demand_empty_rest_of_line ();
7046 return;
7047 }
7048 \f
7049 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7050 if none is found, the caller is responsible for emitting an error
7051 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7052 cpu name, if it begins with a '6' (possibly skipping an intervening
7053 'c'. We also allow a 'c' in the same place. if NEGATED is
7054 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7055 the option is indeed negated. */
7056
7057 static const struct m68k_cpu *
7058 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7059 int allow_m, int *negated)
7060 {
7061 /* allow negated value? */
7062 if (negated)
7063 {
7064 *negated = 0;
7065
7066 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7067 {
7068 arg += 3;
7069 *negated = 1;
7070 }
7071 }
7072
7073 /* Remove 'm' or 'mc' prefix from 68k variants. */
7074 if (allow_m)
7075 {
7076 if (arg[0] == 'm')
7077 {
7078 if (arg[1] == '6')
7079 arg += 1;
7080 else if (arg[1] == 'c' && arg[2] == '6')
7081 arg += 2;
7082 }
7083 }
7084 else if (arg[0] == 'c' && arg[1] == '6')
7085 arg += 1;
7086
7087 for (; table->name; table++)
7088 if (!strcmp (arg, table->name))
7089 {
7090 if (table->alias < -1 || table->alias > 1)
7091 as_bad (_("`%s' is deprecated, use `%s'"),
7092 table->name, table[table->alias < 0 ? 1 : -1].name);
7093 return table;
7094 }
7095 return 0;
7096 }
7097
7098 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7099
7100 static int
7101 m68k_set_cpu (char const *name, int allow_m, int silent)
7102 {
7103 const struct m68k_cpu *cpu;
7104
7105 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7106
7107 if (!cpu)
7108 {
7109 if (!silent)
7110 as_bad (_("cpu `%s' unrecognized"), name);
7111 return 0;
7112 }
7113
7114 if (selected_cpu && selected_cpu != cpu)
7115 {
7116 as_bad (_("already selected `%s' processor"),
7117 selected_cpu->name);
7118 return 0;
7119 }
7120 selected_cpu = cpu;
7121 return 1;
7122 }
7123
7124 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7125
7126 static int
7127 m68k_set_arch (char const *name, int allow_m, int silent)
7128 {
7129 const struct m68k_cpu *arch;
7130
7131 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7132
7133 if (!arch)
7134 {
7135 if (!silent)
7136 as_bad (_("architecture `%s' unrecognized"), name);
7137 return 0;
7138 }
7139
7140 if (selected_arch && selected_arch != arch)
7141 {
7142 as_bad (_("already selected `%s' architecture"),
7143 selected_arch->name);
7144 return 0;
7145 }
7146
7147 selected_arch = arch;
7148 return 1;
7149 }
7150
7151 /* Set the architecture extension, issuing errors if it is
7152 unrecognized, or invalid */
7153
7154 static int
7155 m68k_set_extension (char const *name, int allow_m, int silent)
7156 {
7157 int negated;
7158 const struct m68k_cpu *ext;
7159
7160 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7161
7162 if (!ext)
7163 {
7164 if (!silent)
7165 as_bad (_("extension `%s' unrecognized"), name);
7166 return 0;
7167 }
7168
7169 if (negated)
7170 not_current_architecture |= ext->arch;
7171 else
7172 current_architecture |= ext->arch;
7173 return 1;
7174 }
7175
7176 /* md_parse_option
7177 Invocation line includes a switch not recognized by the base assembler.
7178 */
7179
7180 #ifdef OBJ_ELF
7181 const char *md_shortopts = "lSA:m:kQ:V";
7182 #else
7183 const char *md_shortopts = "lSA:m:k";
7184 #endif
7185
7186 struct option md_longopts[] = {
7187 #define OPTION_PIC (OPTION_MD_BASE)
7188 {"pic", no_argument, NULL, OPTION_PIC},
7189 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7190 {"register-prefix-optional", no_argument, NULL,
7191 OPTION_REGISTER_PREFIX_OPTIONAL},
7192 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7193 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7194 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7195 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7196 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7197 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7198 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7199 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7200 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7201 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7202 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7203 {"pcrel", no_argument, NULL, OPTION_PCREL},
7204 {NULL, no_argument, NULL, 0}
7205 };
7206 size_t md_longopts_size = sizeof (md_longopts);
7207
7208 int
7209 md_parse_option (int c, char *arg)
7210 {
7211 switch (c)
7212 {
7213 case 'l': /* -l means keep external to 2 bit offset
7214 rather than 16 bit one. */
7215 flag_short_refs = 1;
7216 break;
7217
7218 case 'S': /* -S means that jbsr's always turn into
7219 jsr's. */
7220 flag_long_jumps = 1;
7221 break;
7222
7223 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7224 branches into absolute jumps. */
7225 flag_keep_pcrel = 1;
7226 break;
7227
7228 case OPTION_PIC:
7229 case 'k':
7230 flag_want_pic = 1;
7231 break; /* -pic, Position Independent Code. */
7232
7233 case OPTION_REGISTER_PREFIX_OPTIONAL:
7234 flag_reg_prefix_optional = 1;
7235 reg_prefix_optional_seen = 1;
7236 break;
7237
7238 /* -V: SVR4 argument to print version ID. */
7239 case 'V':
7240 print_version_id ();
7241 break;
7242
7243 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7244 should be emitted or not. FIXME: Not implemented. */
7245 case 'Q':
7246 break;
7247
7248 case OPTION_BITWISE_OR:
7249 {
7250 char *n, *t;
7251 const char *s;
7252
7253 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7254 t = n;
7255 for (s = m68k_comment_chars; *s != '\0'; s++)
7256 if (*s != '|')
7257 *t++ = *s;
7258 *t = '\0';
7259 m68k_comment_chars = n;
7260 }
7261 break;
7262
7263 case OPTION_BASE_SIZE_DEFAULT_16:
7264 m68k_index_width_default = SIZE_WORD;
7265 break;
7266
7267 case OPTION_BASE_SIZE_DEFAULT_32:
7268 m68k_index_width_default = SIZE_LONG;
7269 break;
7270
7271 case OPTION_DISP_SIZE_DEFAULT_16:
7272 m68k_rel32 = 0;
7273 m68k_rel32_from_cmdline = 1;
7274 break;
7275
7276 case OPTION_DISP_SIZE_DEFAULT_32:
7277 m68k_rel32 = 1;
7278 m68k_rel32_from_cmdline = 1;
7279 break;
7280
7281 case 'A':
7282 #if WARN_DEPRECATED
7283 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7284 arg, arg));
7285 #endif
7286 /* Intentional fall-through. */
7287 case 'm':
7288 if (!strncmp (arg, "arch=", 5))
7289 m68k_set_arch (arg + 5, 1, 0);
7290 else if (!strncmp (arg, "cpu=", 4))
7291 m68k_set_cpu (arg + 4, 1, 0);
7292 else if (m68k_set_extension (arg, 0, 1))
7293 ;
7294 else if (m68k_set_arch (arg, 0, 1))
7295 ;
7296 else if (m68k_set_cpu (arg, 0, 1))
7297 ;
7298 else
7299 return 0;
7300 break;
7301
7302 default:
7303 return 0;
7304 }
7305
7306 return 1;
7307 }
7308
7309 /* Setup tables from the selected arch and/or cpu */
7310
7311 static void
7312 m68k_init_arch (void)
7313 {
7314 if (not_current_architecture & current_architecture)
7315 {
7316 as_bad (_("architecture features both enabled and disabled"));
7317 not_current_architecture &= ~current_architecture;
7318 }
7319 if (selected_arch)
7320 {
7321 current_architecture |= selected_arch->arch;
7322 control_regs = selected_arch->control_regs;
7323 }
7324 else
7325 current_architecture |= selected_cpu->arch;
7326
7327 current_architecture &= ~not_current_architecture;
7328
7329 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7330 {
7331 /* Determine which float is really meant. */
7332 if (current_architecture & (m68k_mask & ~m68881))
7333 current_architecture ^= cfloat;
7334 else
7335 current_architecture ^= m68881;
7336 }
7337
7338 if (selected_cpu)
7339 {
7340 control_regs = selected_cpu->control_regs;
7341 if (current_architecture & ~selected_cpu->arch)
7342 {
7343 as_bad (_("selected processor does not have all features of selected architecture"));
7344 current_architecture
7345 = selected_cpu->arch & ~not_current_architecture;
7346 }
7347 }
7348
7349 if ((current_architecture & m68k_mask)
7350 && (current_architecture & ~m68k_mask))
7351 {
7352 as_bad (_ ("m68k and cf features both selected"));
7353 if (current_architecture & m68k_mask)
7354 current_architecture &= m68k_mask;
7355 else
7356 current_architecture &= ~m68k_mask;
7357 }
7358
7359 /* Permit m68881 specification with all cpus; those that can't work
7360 with a coprocessor could be doing emulation. */
7361 if (current_architecture & m68851)
7362 {
7363 if (current_architecture & m68040)
7364 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7365 }
7366 /* What other incompatibilities could we check for? */
7367
7368 if (cpu_of_arch (current_architecture) < m68020
7369 || arch_coldfire_p (current_architecture))
7370 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7371
7372 initialized = 1;
7373 }
7374
7375 void
7376 md_show_usage (FILE *stream)
7377 {
7378 const char *default_cpu = TARGET_CPU;
7379 int i;
7380 unsigned int default_arch;
7381
7382 /* Get the canonical name for the default target CPU. */
7383 if (*default_cpu == 'm')
7384 default_cpu++;
7385 for (i = 0; m68k_cpus[i].name; i++)
7386 {
7387 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7388 {
7389 default_arch = m68k_cpus[i].arch;
7390 while (m68k_cpus[i].alias > 0)
7391 i--;
7392 while (m68k_cpus[i].alias < 0)
7393 i++;
7394 default_cpu = m68k_cpus[i].name;
7395 }
7396 }
7397
7398 fprintf (stream, _("\
7399 -march=<arch> set architecture\n\
7400 -mcpu=<cpu> set cpu [default %s]\n\
7401 "), default_cpu);
7402 for (i = 0; m68k_extensions[i].name; i++)
7403 fprintf (stream, _("\
7404 -m[no-]%-16s enable/disable%s architecture extension\n\
7405 "), m68k_extensions[i].name,
7406 m68k_extensions[i].alias > 0 ? " ColdFire"
7407 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7408
7409 fprintf (stream, _("\
7410 -l use 1 word for refs to undefined symbols [default 2]\n\
7411 -pic, -k generate position independent code\n\
7412 -S turn jbsr into jsr\n\
7413 --pcrel never turn PC-relative branches into absolute jumps\n\
7414 --register-prefix-optional\n\
7415 recognize register names without prefix character\n\
7416 --bitwise-or do not treat `|' as a comment character\n\
7417 --base-size-default-16 base reg without size is 16 bits\n\
7418 --base-size-default-32 base reg without size is 32 bits (default)\n\
7419 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7420 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7421 "));
7422
7423 fprintf (stream, _("Architecture variants are: "));
7424 for (i = 0; m68k_archs[i].name; i++)
7425 {
7426 if (i)
7427 fprintf (stream, " | ");
7428 fprintf (stream, m68k_archs[i].name);
7429 }
7430 fprintf (stream, "\n");
7431
7432 fprintf (stream, _("Processor variants are: "));
7433 for (i = 0; m68k_cpus[i].name; i++)
7434 {
7435 if (i)
7436 fprintf (stream, " | ");
7437 fprintf (stream, m68k_cpus[i].name);
7438 }
7439 fprintf (stream, _("\n"));
7440 }
7441 \f
7442 #ifdef TEST2
7443
7444 /* TEST2: Test md_assemble() */
7445 /* Warning, this routine probably doesn't work anymore. */
7446 int
7447 main (void)
7448 {
7449 struct m68k_it the_ins;
7450 char buf[120];
7451 char *cp;
7452 int n;
7453
7454 m68k_ip_begin ();
7455 for (;;)
7456 {
7457 if (!gets (buf) || !*buf)
7458 break;
7459 if (buf[0] == '|' || buf[1] == '.')
7460 continue;
7461 for (cp = buf; *cp; cp++)
7462 if (*cp == '\t')
7463 *cp = ' ';
7464 if (is_label (buf))
7465 continue;
7466 memset (&the_ins, '\0', sizeof (the_ins));
7467 m68k_ip (&the_ins, buf);
7468 if (the_ins.error)
7469 {
7470 printf (_("Error %s in %s\n"), the_ins.error, buf);
7471 }
7472 else
7473 {
7474 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7475 for (n = 0; n < the_ins.numo; n++)
7476 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7477 printf (" ");
7478 print_the_insn (&the_ins.opcode[0], stdout);
7479 (void) putchar ('\n');
7480 }
7481 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7482 {
7483 if (the_ins.operands[n].error)
7484 {
7485 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7486 continue;
7487 }
7488 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7489 the_ins.operands[n].reg);
7490 if (the_ins.operands[n].b_const)
7491 printf ("Constant: '%.*s', ",
7492 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7493 the_ins.operands[n].b_const);
7494 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7495 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7496 if (the_ins.operands[n].b_iadd)
7497 printf ("Iadd: '%.*s',",
7498 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7499 the_ins.operands[n].b_iadd);
7500 putchar ('\n');
7501 }
7502 }
7503 m68k_ip_end ();
7504 return 0;
7505 }
7506
7507 int
7508 is_label (char *str)
7509 {
7510 while (*str == ' ')
7511 str++;
7512 while (*str && *str != ' ')
7513 str++;
7514 if (str[-1] == ':' || str[1] == '=')
7515 return 1;
7516 return 0;
7517 }
7518
7519 #endif
7520
7521 /* Possible states for relaxation:
7522
7523 0 0 branch offset byte (bra, etc)
7524 0 1 word
7525 0 2 long
7526
7527 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7528 1 1 word
7529 1 2 long
7530
7531 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7532 2 1 word-long
7533 2 2 long-word
7534 2 3 long-long
7535
7536 */
7537
7538 /* We have no need to default values of symbols. */
7539
7540 symbolS *
7541 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7542 {
7543 return 0;
7544 }
7545
7546 /* Round up a section size to the appropriate boundary. */
7547 valueT
7548 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7549 {
7550 #ifdef OBJ_AOUT
7551 /* For a.out, force the section size to be aligned. If we don't do
7552 this, BFD will align it for us, but it will not write out the
7553 final bytes of the section. This may be a bug in BFD, but it is
7554 easier to fix it here since that is how the other a.out targets
7555 work. */
7556 int align;
7557
7558 align = bfd_get_section_alignment (stdoutput, segment);
7559 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7560 #endif
7561
7562 return size;
7563 }
7564
7565 /* Exactly what point is a PC-relative offset relative TO?
7566 On the 68k, it is relative to the address of the first extension
7567 word. The difference between the addresses of the offset and the
7568 first extension word is stored in fx_pcrel_adjust. */
7569 long
7570 md_pcrel_from (fixS *fixP)
7571 {
7572 int adjust;
7573
7574 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7575 sign extend the value here. */
7576 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7577 if (adjust == 64)
7578 adjust = -1;
7579 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7580 }
7581
7582 #ifdef OBJ_ELF
7583 void
7584 m68k_elf_final_processing (void)
7585 {
7586 unsigned flags = 0;
7587
7588 if (arch_coldfire_fpu (current_architecture))
7589 flags |= EF_M68K_CFV4E;
7590 /* Set file-specific flags if this is a cpu32 processor. */
7591 if (cpu_of_arch (current_architecture) & cpu32)
7592 flags |= EF_M68K_CPU32;
7593 else if (cpu_of_arch (current_architecture) & fido_a)
7594 flags |= EF_M68K_FIDO;
7595 else if ((cpu_of_arch (current_architecture) & m68000up)
7596 && !(cpu_of_arch (current_architecture) & m68020up))
7597 flags |= EF_M68K_M68000;
7598
7599 if (current_architecture & mcfisa_a)
7600 {
7601 static const unsigned isa_features[][2] =
7602 {
7603 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7604 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7605 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7606 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7607 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7608 {0,0},
7609 };
7610 static const unsigned mac_features[][2] =
7611 {
7612 {EF_M68K_CF_MAC, mcfmac},
7613 {EF_M68K_CF_EMAC, mcfemac},
7614 {0,0},
7615 };
7616 unsigned ix;
7617 unsigned pattern;
7618
7619 pattern = (current_architecture
7620 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7621 for (ix = 0; isa_features[ix][1]; ix++)
7622 {
7623 if (pattern == isa_features[ix][1])
7624 {
7625 flags |= isa_features[ix][0];
7626 break;
7627 }
7628 }
7629 if (!isa_features[ix][1])
7630 {
7631 cf_bad:
7632 as_warn (_("Not a defined coldfire architecture"));
7633 }
7634 else
7635 {
7636 if (current_architecture & cfloat)
7637 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7638
7639 pattern = current_architecture & (mcfmac|mcfemac);
7640 if (pattern)
7641 {
7642 for (ix = 0; mac_features[ix][1]; ix++)
7643 {
7644 if (pattern == mac_features[ix][1])
7645 {
7646 flags |= mac_features[ix][0];
7647 break;
7648 }
7649 }
7650 if (!mac_features[ix][1])
7651 goto cf_bad;
7652 }
7653 }
7654 }
7655 elf_elfheader (stdoutput)->e_flags |= flags;
7656 }
7657 #endif
7658
7659 int
7660 tc_m68k_regname_to_dw2regnum (char *regname)
7661 {
7662 unsigned int regnum;
7663 static const char *const regnames[] =
7664 {
7665 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7666 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7667 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7668 "pc"
7669 };
7670
7671 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7672 if (strcmp (regname, regnames[regnum]) == 0)
7673 return regnum;
7674
7675 return -1;
7676 }
7677
7678 void
7679 tc_m68k_frame_initial_instructions (void)
7680 {
7681 static int sp_regno = -1;
7682
7683 if (sp_regno < 0)
7684 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7685
7686 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7687 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7688 }
GDB Binutils - Deliverables
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