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* config/tc-m68k.c (m68k_ip): The coldfire does not support 8x
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #include "as.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This string holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful. The macro
31 tc_comment_chars points to this. We use this, rather than the
32 usual comment_chars, so that the --bitwise-or option will work. */
33 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
34 const char *m68k_comment_chars = "|#";
35 #else
36 const char *m68k_comment_chars = "|";
37 #endif
38
39 /* This array holds the chars that only start a comment at the beginning of
40 a line. If the line seems to have the form '# 123 filename'
41 .line and .file directives will appear in the pre-processed output */
42 /* Note that input_file.c hand checks for '#' at the beginning of the
43 first line of the input file. This is because the compiler outputs
44 #NO_APP at the beginning of its output. */
45 /* Also note that comments like this one will always work. */
46 const char line_comment_chars[] = "#";
47
48 const char line_separator_chars[] = "";
49
50 /* Chars that can be used to separate mant from exp in floating point nums */
51 CONST char EXP_CHARS[] = "eE";
52
53 /* Chars that mean this number is a floating point constant, as
54 in "0f12.456" or "0d1.2345e12". */
55
56 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
57
58 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
59 changed in read.c . Ideally it shouldn't have to know about it at all,
60 but nothing is ideal around here. */
61
62 const int md_reloc_size = 8; /* Size of relocation record */
63
64 /* Are we trying to generate PIC code? If so, absolute references
65 ought to be made into linkage table references or pc-relative
66 references. Not implemented. For ELF there are other means
67 to denote pic relocations. */
68 int flag_want_pic;
69
70 static int flag_short_refs; /* -l option */
71 static int flag_long_jumps; /* -S option */
72
73 #ifdef REGISTER_PREFIX_OPTIONAL
74 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
75 #else
76 int flag_reg_prefix_optional;
77 #endif
78
79 /* Whether --register-prefix-optional was used on the command line. */
80 static int reg_prefix_optional_seen;
81
82 /* The floating point coprocessor to use by default. */
83 static enum m68k_register m68k_float_copnum = COP1;
84
85 /* If this is non-zero, then references to number(%pc) will be taken
86 to refer to number, rather than to %pc + number. */
87 static int m68k_abspcadd;
88
89 /* If this is non-zero, then the quick forms of the move, add, and sub
90 instructions are used when possible. */
91 static int m68k_quick = 1;
92
93 /* If this is non-zero, then if the size is not specified for a base
94 or outer displacement, the assembler assumes that the size should
95 be 32 bits. */
96 static int m68k_rel32 = 1;
97
98 /* Its an arbitrary name: This means I don't approve of it */
99 /* See flames below */
100 static struct obstack robyn;
101
102 #define TAB(x,y) (((x)<<2)+(y))
103 #define TABTYPE(xy) ((xy) >> 2)
104 #define BYTE 0
105 #define SHORT 1
106 #define LONG 2
107 #define SZ_UNDEF 3
108 #undef BRANCH
109 /* Case `g' except when BCC68000 is applicable. */
110 #define ABRANCH 1
111 /* Coprocessor branches. */
112 #define FBRANCH 2
113 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
114 supported on all cpus. Widens to 32-bit absolute. */
115 #define PCREL 3
116 /* For inserting an extra jmp instruction with long offset on 68000,
117 for expanding conditional branches. (Not bsr or bra.) Since the
118 68000 doesn't support 32-bit displacements for conditional
119 branches, we fake it by reversing the condition and branching
120 around a jmp with an absolute long operand. */
121 #define BCC68000 4
122 /* For the DBcc "instructions". If the displacement requires 32 bits,
123 the branch-around-a-jump game is played here too. */
124 #define DBCC 5
125 /* Not currently used? */
126 #define PCLEA 6
127 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
128 in 16 or 8 bits. */
129 #define PCINDEX 7
130
131 struct m68k_incant
132 {
133 const char *m_operands;
134 unsigned long m_opcode;
135 short m_opnum;
136 short m_codenum;
137 int m_arch;
138 struct m68k_incant *m_next;
139 };
140
141 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
142 #define gettwo(x) (((x)->m_opcode)&0xffff)
143
144 static const enum m68k_register m68000_control_regs[] = { 0 };
145 static const enum m68k_register m68010_control_regs[] = {
146 SFC, DFC, USP, VBR,
147 0
148 };
149 static const enum m68k_register m68020_control_regs[] = {
150 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
151 0
152 };
153 static const enum m68k_register m68040_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
155 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
156 0
157 };
158 static const enum m68k_register m68060_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
160 USP, VBR, URP, SRP, PCR,
161 0
162 };
163 static const enum m68k_register mcf5200_control_regs[] = {
164 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
165 RAMBAR0, RAMBAR1, MBAR,
166 0
167 };
168 #define cpu32_control_regs m68010_control_regs
169
170 static const enum m68k_register *control_regs;
171
172 /* internal form of a 68020 instruction */
173 struct m68k_it
174 {
175 const char *error;
176 const char *args; /* list of opcode info */
177 int numargs;
178
179 int numo; /* Number of shorts in opcode */
180 short opcode[11];
181
182 struct m68k_op operands[6];
183
184 int nexp; /* number of exprs in use */
185 struct m68k_exp exprs[4];
186
187 int nfrag; /* Number of frags we have to produce */
188 struct
189 {
190 int fragoff; /* Where in the current opcode the frag ends */
191 symbolS *fadd;
192 long foff;
193 int fragty;
194 }
195 fragb[4];
196
197 int nrel; /* Num of reloc strucs in use */
198 struct
199 {
200 int n;
201 expressionS exp;
202 char wid;
203 char pcrel;
204 /* In a pc relative address the difference between the address
205 of the offset and the address that the offset is relative
206 to. This depends on the addressing mode. Basically this
207 is the value to put in the offset field to address the
208 first byte of the offset, without regarding the special
209 significance of some values (in the branch instruction, for
210 example). */
211 int pcrel_fix;
212 #ifdef OBJ_ELF
213 /* Whether this expression needs special pic relocation, and if
214 so, which. */
215 enum pic_relocation pic_reloc;
216 #endif
217 }
218 reloc[5]; /* Five is enough??? */
219 };
220
221 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
222 #define float_of_arch(x) ((x) & mfloat)
223 #define mmu_of_arch(x) ((x) & mmmu)
224
225 static struct m68k_it the_ins; /* the instruction being assembled */
226
227 #define op(ex) ((ex)->exp.X_op)
228 #define adds(ex) ((ex)->exp.X_add_symbol)
229 #define subs(ex) ((ex)->exp.X_op_symbol)
230 #define offs(ex) ((ex)->exp.X_add_number)
231
232 /* Macros for adding things to the m68k_it struct */
233
234 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
235
236 /* Like addword, but goes BEFORE general operands */
237 static void
238 insop (w, opcode)
239 int w;
240 struct m68k_incant *opcode;
241 {
242 int z;
243 for(z=the_ins.numo;z>opcode->m_codenum;--z)
244 the_ins.opcode[z]=the_ins.opcode[z-1];
245 for(z=0;z<the_ins.nrel;z++)
246 the_ins.reloc[z].n+=2;
247 for (z = 0; z < the_ins.nfrag; z++)
248 the_ins.fragb[z].fragoff++;
249 the_ins.opcode[opcode->m_codenum]=w;
250 the_ins.numo++;
251 }
252
253 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
254 Blecch. */
255 static void
256 add_fix (width, exp, pc_rel, pc_fix)
257 char width;
258 struct m68k_exp *exp;
259 int pc_rel;
260 int pc_fix;
261 {
262 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
263 ? (the_ins.numo*2-1)
264 : (((width)=='b')
265 ? (the_ins.numo*2+1)
266 : (the_ins.numo*2)));
267 the_ins.reloc[the_ins.nrel].exp = exp->exp;
268 the_ins.reloc[the_ins.nrel].wid = width;
269 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
270 #ifdef OBJ_ELF
271 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
272 #endif
273 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
274 }
275
276 /* Cause an extra frag to be generated here, inserting up to 10 bytes
277 (that value is chosen in the frag_var call in md_assemble). TYPE
278 is the subtype of the frag to be generated; its primary type is
279 rs_machine_dependent.
280
281 The TYPE parameter is also used by md_convert_frag_1 and
282 md_estimate_size_before_relax. The appropriate type of fixup will
283 be emitted by md_convert_frag_1.
284
285 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
286 static void
287 add_frag(add,off,type)
288 symbolS *add;
289 long off;
290 int type;
291 {
292 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
293 the_ins.fragb[the_ins.nfrag].fadd=add;
294 the_ins.fragb[the_ins.nfrag].foff=off;
295 the_ins.fragb[the_ins.nfrag++].fragty=type;
296 }
297
298 #define isvar(ex) \
299 (op (ex) != O_constant && op (ex) != O_big)
300
301 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
302 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
303 static int reverse_16_bits PARAMS ((int in));
304 static int reverse_8_bits PARAMS ((int in));
305 static void install_gen_operand PARAMS ((int mode, int val));
306 static void install_operand PARAMS ((int mode, int val));
307 static void s_bss PARAMS ((int));
308 static void s_data1 PARAMS ((int));
309 static void s_data2 PARAMS ((int));
310 static void s_even PARAMS ((int));
311 static void s_proc PARAMS ((int));
312 static void mri_chip PARAMS ((void));
313 static void s_chip PARAMS ((int));
314 static void s_fopt PARAMS ((int));
315 static void s_opt PARAMS ((int));
316 static void s_reg PARAMS ((int));
317 static void s_restore PARAMS ((int));
318 static void s_save PARAMS ((int));
319 static void s_mri_if PARAMS ((int));
320 static void s_mri_else PARAMS ((int));
321 static void s_mri_endi PARAMS ((int));
322 static void s_mri_break PARAMS ((int));
323 static void s_mri_next PARAMS ((int));
324 static void s_mri_for PARAMS ((int));
325 static void s_mri_endf PARAMS ((int));
326 static void s_mri_repeat PARAMS ((int));
327 static void s_mri_until PARAMS ((int));
328 static void s_mri_while PARAMS ((int));
329 static void s_mri_endw PARAMS ((int));
330
331 static int current_architecture;
332
333 struct m68k_cpu {
334 unsigned long arch;
335 const char *name;
336 int alias;
337 };
338
339 static const struct m68k_cpu archs[] = {
340 { m68000, "68000", 0 },
341 { m68010, "68010", 0 },
342 { m68020, "68020", 0 },
343 { m68030, "68030", 0 },
344 { m68040, "68040", 0 },
345 { m68060, "68060", 0 },
346 { cpu32, "cpu32", 0 },
347 { m68881, "68881", 0 },
348 { m68851, "68851", 0 },
349 { mcf5200, "5200", 0 },
350 /* Aliases (effectively, so far as gas is concerned) for the above
351 cpus. */
352 { m68020, "68k", 1 },
353 { m68000, "68302", 1 },
354 { m68000, "68008", 1 },
355 { m68000, "68ec000", 1 },
356 { m68000, "68hc000", 1 },
357 { m68000, "68hc001", 1 },
358 { m68020, "68ec020", 1 },
359 { m68030, "68ec030", 1 },
360 { m68040, "68ec040", 1 },
361 { m68060, "68ec060", 1 },
362 { cpu32, "68330", 1 },
363 { cpu32, "68331", 1 },
364 { cpu32, "68332", 1 },
365 { cpu32, "68333", 1 },
366 { cpu32, "68340", 1 },
367 { cpu32, "68360", 1 },
368 { m68881, "68882", 1 },
369 };
370
371 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
372
373 /* BCC68000 is for patching in an extra jmp instruction for long offsets
374 on the 68000. The 68000 doesn't support long branches with branchs */
375
376 /* This table desribes how you change sizes for the various types of variable
377 size expressions. This version only supports two kinds. */
378
379 /* Note that calls to frag_var need to specify the maximum expansion
380 needed; this is currently 10 bytes for DBCC. */
381
382 /* The fields are:
383 How far Forward this mode will reach:
384 How far Backward this mode will reach:
385 How many bytes this mode will add to the size of the frag
386 Which mode to go to if the offset won't fit in this one
387 */
388 relax_typeS md_relax_table[] =
389 {
390 {1, 1, 0, 0}, /* First entries aren't used */
391 {1, 1, 0, 0}, /* For no good reason except */
392 {1, 1, 0, 0}, /* that the VAX doesn't either */
393 {1, 1, 0, 0},
394
395 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
396 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
397 {0, 0, 4, 0},
398 {1, 1, 0, 0},
399
400 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
401 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
402 {0, 0, 4, 0},
403 {1, 1, 0, 0},
404
405 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
406 {(32767), (-32768), 2, TAB (PCREL, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409
410 {(127), (-128), 0, TAB (BCC68000, SHORT)},
411 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
412 {0, 0, 6, 0}, /* jmp long space */
413 {1, 1, 0, 0},
414
415 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
416 {(32767), (-32768), 2, TAB (DBCC, LONG)},
417 {0, 0, 10, 0}, /* bra/jmp long space */
418 {1, 1, 0, 0},
419
420 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
421 {32767, -32768, 2, TAB (PCLEA, LONG)},
422 {0, 0, 6, 0},
423 {1, 1, 0, 0},
424
425 /* For, e.g., jmp pcrel indexed. */
426 {125, -130, 0, TAB (PCINDEX, SHORT)},
427 {32765, -32770, 2, TAB (PCINDEX, LONG)},
428 {0, 0, 4, 0},
429 {1, 1, 0, 0},
430 };
431
432 /* These are the machine dependent pseudo-ops. These are included so
433 the assembler can work on the output from the SUN C compiler, which
434 generates these.
435 */
436
437 /* This table describes all the machine specific pseudo-ops the assembler
438 has to support. The fields are:
439 pseudo-op name without dot
440 function to call to execute this pseudo-op
441 Integer arg to pass to the function
442 */
443 const pseudo_typeS md_pseudo_table[] =
444 {
445 {"data1", s_data1, 0},
446 {"data2", s_data2, 0},
447 {"bss", s_bss, 0},
448 {"even", s_even, 0},
449 {"skip", s_space, 0},
450 {"proc", s_proc, 0},
451 #if defined (TE_SUN3) || defined (OBJ_ELF)
452 {"align", s_align_bytes, 0},
453 #endif
454 #ifdef OBJ_ELF
455 {"swbeg", s_ignore, 0},
456 #endif
457 {"extend", float_cons, 'x'},
458 {"ldouble", float_cons, 'x'},
459
460 /* The following pseudo-ops are supported for MRI compatibility. */
461 {"chip", s_chip, 0},
462 {"comline", s_space, 1},
463 {"fopt", s_fopt, 0},
464 {"mask2", s_ignore, 0},
465 {"opt", s_opt, 0},
466 {"reg", s_reg, 0},
467 {"restore", s_restore, 0},
468 {"save", s_save, 0},
469
470 {"if", s_mri_if, 0},
471 {"if.b", s_mri_if, 'b'},
472 {"if.w", s_mri_if, 'w'},
473 {"if.l", s_mri_if, 'l'},
474 {"else", s_mri_else, 0},
475 {"else.s", s_mri_else, 's'},
476 {"else.l", s_mri_else, 'l'},
477 {"endi", s_mri_endi, 0},
478 {"break", s_mri_break, 0},
479 {"break.s", s_mri_break, 's'},
480 {"break.l", s_mri_break, 'l'},
481 {"next", s_mri_next, 0},
482 {"next.s", s_mri_next, 's'},
483 {"next.l", s_mri_next, 'l'},
484 {"for", s_mri_for, 0},
485 {"for.b", s_mri_for, 'b'},
486 {"for.w", s_mri_for, 'w'},
487 {"for.l", s_mri_for, 'l'},
488 {"endf", s_mri_endf, 0},
489 {"repeat", s_mri_repeat, 0},
490 {"until", s_mri_until, 0},
491 {"until.b", s_mri_until, 'b'},
492 {"until.w", s_mri_until, 'w'},
493 {"until.l", s_mri_until, 'l'},
494 {"while", s_mri_while, 0},
495 {"while.b", s_mri_while, 'b'},
496 {"while.w", s_mri_while, 'w'},
497 {"while.l", s_mri_while, 'l'},
498 {"endw", s_mri_endw, 0},
499
500 {0, 0, 0}
501 };
502
503
504 /* The mote pseudo ops are put into the opcode table, since they
505 don't start with a . they look like opcodes to gas.
506 */
507 extern void obj_coff_section ();
508
509 CONST pseudo_typeS mote_pseudo_table[] =
510 {
511
512 {"dcl", cons, 4},
513 {"dc", cons, 2},
514 {"dcw", cons, 2},
515 {"dcb", cons, 1},
516
517 {"dsl", s_space, 4},
518 {"ds", s_space, 2},
519 {"dsw", s_space, 2},
520 {"dsb", s_space, 1},
521
522 {"xdef", s_globl, 0},
523 #ifdef OBJ_ELF
524 {"align", s_align_bytes, 0},
525 #else
526 {"align", s_align_ptwo, 0},
527 #endif
528 #ifdef M68KCOFF
529 {"sect", obj_coff_section, 0},
530 {"section", obj_coff_section, 0},
531 #endif
532 {0, 0, 0}
533 };
534
535 #define issbyte(x) ((x)>=-128 && (x)<=127)
536 #define isubyte(x) ((x)>=0 && (x)<=255)
537 #define issword(x) ((x)>=-32768 && (x)<=32767)
538 #define isuword(x) ((x)>=0 && (x)<=65535)
539
540 #define isbyte(x) ((x)>= -255 && (x)<=255)
541 #define isword(x) ((x)>=-65536 && (x)<=65535)
542 #define islong(x) (1)
543
544 extern char *input_line_pointer;
545
546 static char mklower_table[256];
547 #define mklower(c) (mklower_table[(unsigned char)(c)])
548 static char notend_table[256];
549 static char alt_notend_table[256];
550 #define notend(s) \
551 (! (notend_table[(unsigned char) *s] \
552 || (*s == ':' \
553 && alt_notend_table[(unsigned char) s[1]])))
554
555 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
556
557 #ifdef NO_PCREL_RELOCS
558
559 int
560 make_pcrel_absolute(fixP, add_number)
561 fixS *fixP;
562 long *add_number;
563 {
564 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
565
566 /* rewrite the PC relative instructions to absolute address ones.
567 * these are rumoured to be faster, and the apollo linker refuses
568 * to deal with the PC relative relocations.
569 */
570 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
571 {
572 opcode[0] = 0x4e;
573 opcode[1] = 0xf9;
574 }
575 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
576 {
577 opcode[0] = 0x4e;
578 opcode[1] = 0xb9;
579 }
580 else
581 as_fatal ("Unknown PC relative instruction");
582 *add_number -= 4;
583 return 0;
584 }
585
586 #endif /* NO_PCREL_RELOCS */
587
588 short
589 tc_coff_fix2rtype (fixP)
590 fixS *fixP;
591 {
592 if (fixP->fx_tcbit && fixP->fx_size == 4)
593 return R_RELLONG_NEG;
594 #ifdef NO_PCREL_RELOCS
595 know (fixP->fx_pcrel == 0);
596 return (fixP->fx_size == 1 ? R_RELBYTE
597 : fixP->fx_size == 2 ? R_DIR16
598 : R_DIR32);
599 #else
600 return (fixP->fx_pcrel ?
601 (fixP->fx_size == 1 ? R_PCRBYTE :
602 fixP->fx_size == 2 ? R_PCRWORD :
603 R_PCRLONG) :
604 (fixP->fx_size == 1 ? R_RELBYTE :
605 fixP->fx_size == 2 ? R_RELWORD :
606 R_RELLONG));
607 #endif
608 }
609
610 #endif
611
612 #ifdef OBJ_ELF
613
614 /* Compute the relocation code for a fixup of SIZE bytes, using pc
615 relative relocation if PCREL is non-zero. PIC says whether a special
616 pic relocation was requested. */
617
618 static bfd_reloc_code_real_type get_reloc_code
619 PARAMS ((int, int, enum pic_relocation));
620
621 static bfd_reloc_code_real_type
622 get_reloc_code (size, pcrel, pic)
623 int size;
624 int pcrel;
625 enum pic_relocation pic;
626 {
627 switch (pic)
628 {
629 case pic_got_pcrel:
630 switch (size)
631 {
632 case 1:
633 return BFD_RELOC_8_GOT_PCREL;
634 case 2:
635 return BFD_RELOC_16_GOT_PCREL;
636 case 4:
637 return BFD_RELOC_32_GOT_PCREL;
638 }
639 break;
640
641 case pic_got_off:
642 switch (size)
643 {
644 case 1:
645 return BFD_RELOC_8_GOTOFF;
646 case 2:
647 return BFD_RELOC_16_GOTOFF;
648 case 4:
649 return BFD_RELOC_32_GOTOFF;
650 }
651 break;
652
653 case pic_plt_pcrel:
654 switch (size)
655 {
656 case 1:
657 return BFD_RELOC_8_PLT_PCREL;
658 case 2:
659 return BFD_RELOC_16_PLT_PCREL;
660 case 4:
661 return BFD_RELOC_32_PLT_PCREL;
662 }
663 break;
664
665 case pic_plt_off:
666 switch (size)
667 {
668 case 1:
669 return BFD_RELOC_8_PLTOFF;
670 case 2:
671 return BFD_RELOC_16_PLTOFF;
672 case 4:
673 return BFD_RELOC_32_PLTOFF;
674 }
675 break;
676
677 case pic_none:
678 if (pcrel)
679 {
680 switch (size)
681 {
682 case 1:
683 return BFD_RELOC_8_PCREL;
684 case 2:
685 return BFD_RELOC_16_PCREL;
686 case 4:
687 return BFD_RELOC_32_PCREL;
688 }
689 }
690 else
691 {
692 switch (size)
693 {
694 case 1:
695 return BFD_RELOC_8;
696 case 2:
697 return BFD_RELOC_16;
698 case 4:
699 return BFD_RELOC_32;
700 }
701 }
702 }
703
704 as_bad ("Can not do %d byte %s%srelocation", size,
705 pcrel ? "pc-relative " : "",
706 pic == pic_none ? "" : "pic ");
707 return BFD_RELOC_NONE;
708 }
709
710 /* Here we decide which fixups can be adjusted to make them relative
711 to the beginning of the section instead of the symbol. Basically
712 we need to make sure that the dynamic relocations are done
713 correctly, so in some cases we force the original symbol to be
714 used. */
715 int
716 tc_m68k_fix_adjustable (fixP)
717 fixS *fixP;
718 {
719 /* Prevent all adjustments to global symbols. */
720 if (S_IS_EXTERNAL (fixP->fx_addsy))
721 return 0;
722
723 /* adjust_reloc_syms doesn't know about the GOT */
724 switch (fixP->fx_r_type)
725 {
726 case BFD_RELOC_8_GOT_PCREL:
727 case BFD_RELOC_16_GOT_PCREL:
728 case BFD_RELOC_32_GOT_PCREL:
729 case BFD_RELOC_8_GOTOFF:
730 case BFD_RELOC_16_GOTOFF:
731 case BFD_RELOC_32_GOTOFF:
732 case BFD_RELOC_8_PLT_PCREL:
733 case BFD_RELOC_16_PLT_PCREL:
734 case BFD_RELOC_32_PLT_PCREL:
735 case BFD_RELOC_8_PLTOFF:
736 case BFD_RELOC_16_PLTOFF:
737 case BFD_RELOC_32_PLTOFF:
738 return 0;
739
740 default:
741 return 1;
742 }
743 }
744
745 #else /* !OBJ_ELF */
746
747 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
748
749 #endif /* OBJ_ELF */
750
751 #ifdef BFD_ASSEMBLER
752
753 arelent *
754 tc_gen_reloc (section, fixp)
755 asection *section;
756 fixS *fixp;
757 {
758 arelent *reloc;
759 bfd_reloc_code_real_type code;
760
761 if (fixp->fx_tcbit)
762 abort ();
763
764 if (fixp->fx_r_type != BFD_RELOC_NONE)
765 code = fixp->fx_r_type;
766 else
767 {
768 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
769 switch (F (fixp->fx_size, fixp->fx_pcrel))
770 {
771 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
772 MAP (1, 0, BFD_RELOC_8);
773 MAP (2, 0, BFD_RELOC_16);
774 MAP (4, 0, BFD_RELOC_32);
775 MAP (1, 1, BFD_RELOC_8_PCREL);
776 MAP (2, 1, BFD_RELOC_16_PCREL);
777 MAP (4, 1, BFD_RELOC_32_PCREL);
778 default:
779 abort ();
780 }
781 }
782 #undef F
783 #undef MAP
784
785 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
786 assert (reloc != 0);
787 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
788 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
789 #ifndef OBJ_ELF
790 if (fixp->fx_pcrel)
791 reloc->addend = fixp->fx_addnumber;
792 else
793 reloc->addend = 0;
794 #else
795 if (!fixp->fx_pcrel)
796 reloc->addend = fixp->fx_addnumber;
797 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
798 reloc->addend = (section->vma
799 + (fixp->fx_pcrel_adjust == 64
800 ? -1 : fixp->fx_pcrel_adjust)
801 + fixp->fx_addnumber
802 + md_pcrel_from (fixp));
803 else
804 reloc->addend = (fixp->fx_offset
805 + (fixp->fx_pcrel_adjust == 64
806 ? -1 : fixp->fx_pcrel_adjust));
807 #endif
808
809 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
810 assert (reloc->howto != 0);
811
812 return reloc;
813 }
814
815 #endif /* BFD_ASSEMBLER */
816
817 /* Handle of the OPCODE hash table. NULL means any use before
818 m68k_ip_begin() will crash. */
819 static struct hash_control *op_hash;
820 \f
821 /* Assemble an m68k instruction. */
822
823 void
824 m68k_ip (instring)
825 char *instring;
826 {
827 register char *p;
828 register struct m68k_op *opP;
829 register struct m68k_incant *opcode;
830 register const char *s;
831 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
832 char *pdot, *pdotmove;
833 enum m68k_size siz1, siz2;
834 char c;
835 int losing;
836 int opsfound;
837 char *crack_operand ();
838 LITTLENUM_TYPE words[6];
839 LITTLENUM_TYPE *wordp;
840 unsigned long ok_arch = 0;
841
842 if (*instring == ' ')
843 instring++; /* skip leading whitespace */
844
845 /* Scan up to end of operation-code, which MUST end in end-of-string
846 or exactly 1 space. */
847 pdot = 0;
848 for (p = instring; *p != '\0'; p++)
849 {
850 if (*p == ' ')
851 break;
852 if (*p == '.')
853 pdot = p;
854 }
855
856 if (p == instring)
857 {
858 the_ins.error = "No operator";
859 return;
860 }
861
862 /* p now points to the end of the opcode name, probably whitespace.
863 Make sure the name is null terminated by clobbering the
864 whitespace, look it up in the hash table, then fix it back.
865 Remove a dot, first, since the opcode tables have none. */
866 if (pdot != NULL)
867 {
868 for (pdotmove = pdot; pdotmove < p; pdotmove++)
869 *pdotmove = pdotmove[1];
870 p--;
871 }
872
873 c = *p;
874 *p = '\0';
875 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
876 *p = c;
877
878 if (pdot != NULL)
879 {
880 for (pdotmove = p; pdotmove > pdot; pdotmove--)
881 *pdotmove = pdotmove[-1];
882 *pdot = '.';
883 ++p;
884 }
885
886 if (opcode == NULL)
887 {
888 the_ins.error = "Unknown operator";
889 return;
890 }
891
892 /* found a legitimate opcode, start matching operands */
893 while (*p == ' ')
894 ++p;
895
896 if (opcode->m_operands == 0)
897 {
898 char *old = input_line_pointer;
899 *old = '\n';
900 input_line_pointer = p;
901 /* Ahh - it's a motorola style psuedo op */
902 mote_pseudo_table[opcode->m_opnum].poc_handler
903 (mote_pseudo_table[opcode->m_opnum].poc_val);
904 input_line_pointer = old;
905 *old = 0;
906
907 return;
908 }
909
910 if (flag_mri && opcode->m_opnum == 0)
911 {
912 /* In MRI mode, random garbage is allowed after an instruction
913 which accepts no operands. */
914 the_ins.args = opcode->m_operands;
915 the_ins.numargs = opcode->m_opnum;
916 the_ins.numo = opcode->m_codenum;
917 the_ins.opcode[0] = getone (opcode);
918 the_ins.opcode[1] = gettwo (opcode);
919 return;
920 }
921
922 for (opP = &the_ins.operands[0]; *p; opP++)
923 {
924 p = crack_operand (p, opP);
925
926 if (opP->error)
927 {
928 the_ins.error = opP->error;
929 return;
930 }
931 }
932
933 opsfound = opP - &the_ins.operands[0];
934
935 /* This ugly hack is to support the floating pt opcodes in their
936 standard form. Essentially, we fake a first enty of type COP#1 */
937 if (opcode->m_operands[0] == 'I')
938 {
939 int n;
940
941 for (n = opsfound; n > 0; --n)
942 the_ins.operands[n] = the_ins.operands[n - 1];
943
944 memset ((char *) (&the_ins.operands[0]), '\0',
945 sizeof (the_ins.operands[0]));
946 the_ins.operands[0].mode = CONTROL;
947 the_ins.operands[0].reg = m68k_float_copnum;
948 opsfound++;
949 }
950
951 /* We've got the operands. Find an opcode that'll accept them */
952 for (losing = 0;;)
953 {
954 /* If we didn't get the right number of ops, or we have no
955 common model with this pattern then reject this pattern. */
956
957 if (opsfound != opcode->m_opnum
958 || ((opcode->m_arch & current_architecture) == 0))
959 {
960 ++losing;
961 ok_arch |= opcode->m_arch;
962 }
963 else
964 {
965 for (s = opcode->m_operands, opP = &the_ins.operands[0];
966 *s && !losing;
967 s += 2, opP++)
968 {
969 /* Warning: this switch is huge! */
970 /* I've tried to organize the cases into this order:
971 non-alpha first, then alpha by letter. Lower-case
972 goes directly before uppercase counterpart. */
973 /* Code with multiple case ...: gets sorted by the lowest
974 case ... it belongs to. I hope this makes sense. */
975 switch (*s)
976 {
977 case '!':
978 switch (opP->mode)
979 {
980 case IMMED:
981 case DREG:
982 case AREG:
983 case FPREG:
984 case CONTROL:
985 case AINC:
986 case ADEC:
987 case REGLST:
988 losing++;
989 break;
990 default:
991 break;
992 }
993 break;
994
995 case '`':
996 switch (opP->mode)
997 {
998 case IMMED:
999 case DREG:
1000 case AREG:
1001 case FPREG:
1002 case CONTROL:
1003 case AINC:
1004 case REGLST:
1005 case AINDR:
1006 losing++;
1007 break;
1008 default:
1009 break;
1010 }
1011 break;
1012
1013 case '#':
1014 if (opP->mode != IMMED)
1015 losing++;
1016 else if (s[1] == 'b'
1017 && ! isvar (&opP->disp)
1018 && (opP->disp.exp.X_op != O_constant
1019 || ! isbyte (opP->disp.exp.X_add_number)))
1020 losing++;
1021 else if (s[1] == 'w'
1022 && ! isvar (&opP->disp)
1023 && (opP->disp.exp.X_op != O_constant
1024 || ! isword (opP->disp.exp.X_add_number)))
1025 losing++;
1026 else if (s[1] == 'W'
1027 && ! isvar (&opP->disp)
1028 && (opP->disp.exp.X_op != O_constant
1029 || ! issword (opP->disp.exp.X_add_number)))
1030 losing++;
1031 break;
1032
1033 case '^':
1034 case 'T':
1035 if (opP->mode != IMMED)
1036 losing++;
1037 break;
1038
1039 case '$':
1040 if (opP->mode == AREG
1041 || opP->mode == CONTROL
1042 || opP->mode == FPREG
1043 || opP->mode == IMMED
1044 || opP->mode == REGLST
1045 || (opP->mode != ABSL
1046 && (opP->reg == PC
1047 || opP->reg == ZPC)))
1048 losing++;
1049 break;
1050
1051 case '%':
1052 if (opP->mode == CONTROL
1053 || opP->mode == FPREG
1054 || opP->mode == REGLST
1055 || opP->mode == IMMED
1056 || (opP->mode != ABSL
1057 && (opP->reg == PC
1058 || opP->reg == ZPC)))
1059 losing++;
1060 break;
1061
1062 case '&':
1063 switch (opP->mode)
1064 {
1065 case DREG:
1066 case AREG:
1067 case FPREG:
1068 case CONTROL:
1069 case IMMED:
1070 case AINC:
1071 case ADEC:
1072 case REGLST:
1073 losing++;
1074 break;
1075 case ABSL:
1076 break;
1077 default:
1078 if (opP->reg == PC
1079 || opP->reg == ZPC)
1080 losing++;
1081 break;
1082 }
1083 break;
1084
1085 case '*':
1086 if (opP->mode == CONTROL
1087 || opP->mode == FPREG
1088 || opP->mode == REGLST)
1089 losing++;
1090 break;
1091
1092 case '+':
1093 if (opP->mode != AINC)
1094 losing++;
1095 break;
1096
1097 case '-':
1098 if (opP->mode != ADEC)
1099 losing++;
1100 break;
1101
1102 case '/':
1103 switch (opP->mode)
1104 {
1105 case AREG:
1106 case CONTROL:
1107 case FPREG:
1108 case AINC:
1109 case ADEC:
1110 case IMMED:
1111 case REGLST:
1112 losing++;
1113 break;
1114 default:
1115 break;
1116 }
1117 break;
1118
1119 case ';':
1120 switch (opP->mode)
1121 {
1122 case AREG:
1123 case CONTROL:
1124 case FPREG:
1125 case REGLST:
1126 losing++;
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132
1133 case '?':
1134 switch (opP->mode)
1135 {
1136 case AREG:
1137 case CONTROL:
1138 case FPREG:
1139 case AINC:
1140 case ADEC:
1141 case IMMED:
1142 case REGLST:
1143 losing++;
1144 break;
1145 case ABSL:
1146 break;
1147 default:
1148 if (opP->reg == PC || opP->reg == ZPC)
1149 losing++;
1150 break;
1151 }
1152 break;
1153
1154 case '@':
1155 switch (opP->mode)
1156 {
1157 case AREG:
1158 case CONTROL:
1159 case FPREG:
1160 case IMMED:
1161 case REGLST:
1162 losing++;
1163 break;
1164 default:
1165 break;
1166 }
1167 break;
1168
1169 case '~': /* For now! (JF FOO is this right?) */
1170 switch (opP->mode)
1171 {
1172 case DREG:
1173 case AREG:
1174 case CONTROL:
1175 case FPREG:
1176 case IMMED:
1177 case REGLST:
1178 losing++;
1179 break;
1180 case ABSL:
1181 break;
1182 default:
1183 if (opP->reg == PC
1184 || opP->reg == ZPC)
1185 losing++;
1186 break;
1187 }
1188 break;
1189
1190 case '3':
1191 if (opP->mode != CONTROL
1192 || (opP->reg != TT0 && opP->reg != TT1))
1193 losing++;
1194 break;
1195
1196 case 'A':
1197 if (opP->mode != AREG)
1198 losing++;
1199 break;
1200
1201 case 'a':
1202 if (opP->mode != AINDR)
1203 ++losing;
1204 break;
1205
1206 case 'B': /* FOO */
1207 if (opP->mode != ABSL
1208 || (flag_long_jumps
1209 && strncmp (instring, "jbsr", 4) == 0))
1210 losing++;
1211 break;
1212
1213 case 'C':
1214 if (opP->mode != CONTROL || opP->reg != CCR)
1215 losing++;
1216 break;
1217
1218 case 'd':
1219 if (opP->mode != DISP
1220 || opP->reg < ADDR0
1221 || opP->reg > ADDR7)
1222 losing++;
1223 break;
1224
1225 case 'D':
1226 if (opP->mode != DREG)
1227 losing++;
1228 break;
1229
1230 case 'F':
1231 if (opP->mode != FPREG)
1232 losing++;
1233 break;
1234
1235 case 'I':
1236 if (opP->mode != CONTROL
1237 || opP->reg < COP0
1238 || opP->reg > COP7)
1239 losing++;
1240 break;
1241
1242 case 'J':
1243 if (opP->mode != CONTROL
1244 || opP->reg < USP
1245 || opP->reg > last_movec_reg)
1246 losing++;
1247 else
1248 {
1249 const enum m68k_register *rp;
1250 for (rp = control_regs; *rp; rp++)
1251 if (*rp == opP->reg)
1252 break;
1253 if (*rp == 0)
1254 losing++;
1255 }
1256 break;
1257
1258 case 'k':
1259 if (opP->mode != IMMED)
1260 losing++;
1261 break;
1262
1263 case 'l':
1264 case 'L':
1265 if (opP->mode == DREG
1266 || opP->mode == AREG
1267 || opP->mode == FPREG)
1268 {
1269 if (s[1] == '8')
1270 losing++;
1271 else
1272 {
1273 switch (opP->mode)
1274 {
1275 case DREG:
1276 opP->mask = 1 << (opP->reg - DATA0);
1277 break;
1278 case AREG:
1279 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1280 break;
1281 case FPREG:
1282 opP->mask = 1 << (opP->reg - FP0 + 16);
1283 break;
1284 default:
1285 abort ();
1286 }
1287 opP->mode = REGLST;
1288 }
1289 }
1290 else if (opP->mode == CONTROL)
1291 {
1292 if (s[1] != '8')
1293 losing++;
1294 else
1295 {
1296 switch (opP->reg)
1297 {
1298 case FPI:
1299 opP->mask = 1 << 24;
1300 break;
1301 case FPS:
1302 opP->mask = 1 << 25;
1303 break;
1304 case FPC:
1305 opP->mask = 1 << 26;
1306 break;
1307 default:
1308 losing++;
1309 break;
1310 }
1311 opP->mode = REGLST;
1312 }
1313 }
1314 else if (opP->mode == ABSL
1315 && opP->disp.size == SIZE_UNSPEC
1316 && opP->disp.exp.X_op == O_constant)
1317 {
1318 /* This is what the MRI REG pseudo-op generates. */
1319 opP->mode = REGLST;
1320 opP->mask = opP->disp.exp.X_add_number;
1321 }
1322 else if (opP->mode != REGLST)
1323 losing++;
1324 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1325 losing++;
1326 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1327 losing++;
1328 break;
1329
1330 case 'M':
1331 if (opP->mode != IMMED)
1332 losing++;
1333 else if (opP->disp.exp.X_op != O_constant
1334 || ! issbyte (opP->disp.exp.X_add_number))
1335 losing++;
1336 else if (! m68k_quick
1337 && instring[3] != 'q'
1338 && instring[4] != 'q')
1339 losing++;
1340 break;
1341
1342 case 'O':
1343 if (opP->mode != DREG
1344 && opP->mode != IMMED
1345 && opP->mode != ABSL)
1346 losing++;
1347 break;
1348
1349 case 'Q':
1350 if (opP->mode != IMMED)
1351 losing++;
1352 else if (opP->disp.exp.X_op != O_constant
1353 || opP->disp.exp.X_add_number < 1
1354 || opP->disp.exp.X_add_number > 8)
1355 losing++;
1356 else if (! m68k_quick
1357 && (strncmp (instring, "add", 3) == 0
1358 || strncmp (instring, "sub", 3) == 0)
1359 && instring[3] != 'q')
1360 losing++;
1361 break;
1362
1363 case 'R':
1364 if (opP->mode != DREG && opP->mode != AREG)
1365 losing++;
1366 break;
1367
1368 case 'r':
1369 if (opP->mode != AINDR
1370 && (opP->mode != BASE
1371 || (opP->reg != 0
1372 && opP->reg != ZADDR0)
1373 || opP->disp.exp.X_op != O_absent
1374 || ((opP->index.reg < DATA0
1375 || opP->index.reg > DATA7)
1376 && (opP->index.reg < ADDR0
1377 || opP->index.reg > ADDR7))
1378 || opP->index.size != SIZE_UNSPEC
1379 || opP->index.scale != 1))
1380 losing++;
1381 break;
1382
1383 case 's':
1384 if (opP->mode != CONTROL
1385 || ! (opP->reg == FPI
1386 || opP->reg == FPS
1387 || opP->reg == FPC))
1388 losing++;
1389 break;
1390
1391 case 'S':
1392 if (opP->mode != CONTROL || opP->reg != SR)
1393 losing++;
1394 break;
1395
1396 case 't':
1397 if (opP->mode != IMMED)
1398 losing++;
1399 else if (opP->disp.exp.X_op != O_constant
1400 || opP->disp.exp.X_add_number < 0
1401 || opP->disp.exp.X_add_number > 7)
1402 losing++;
1403 break;
1404
1405 case 'U':
1406 if (opP->mode != CONTROL || opP->reg != USP)
1407 losing++;
1408 break;
1409
1410 /* JF these are out of order. We could put them
1411 in order if we were willing to put up with
1412 bunches of #ifdef m68851s in the code.
1413
1414 Don't forget that you need these operands
1415 to use 68030 MMU instructions. */
1416 #ifndef NO_68851
1417 /* Memory addressing mode used by pflushr */
1418 case '|':
1419 if (opP->mode == CONTROL
1420 || opP->mode == FPREG
1421 || opP->mode == DREG
1422 || opP->mode == AREG
1423 || opP->mode == REGLST)
1424 losing++;
1425 /* We should accept immediate operands, but they
1426 supposedly have to be quad word, and we don't
1427 handle that. I would like to see what a Motorola
1428 assembler does before doing something here. */
1429 if (opP->mode == IMMED)
1430 losing++;
1431 break;
1432
1433 case 'f':
1434 if (opP->mode != CONTROL
1435 || (opP->reg != SFC && opP->reg != DFC))
1436 losing++;
1437 break;
1438
1439 case '0':
1440 if (opP->mode != CONTROL || opP->reg != TC)
1441 losing++;
1442 break;
1443
1444 case '1':
1445 if (opP->mode != CONTROL || opP->reg != AC)
1446 losing++;
1447 break;
1448
1449 case '2':
1450 if (opP->mode != CONTROL
1451 || (opP->reg != CAL
1452 && opP->reg != VAL
1453 && opP->reg != SCC))
1454 losing++;
1455 break;
1456
1457 case 'V':
1458 if (opP->mode != CONTROL
1459 || opP->reg != VAL)
1460 losing++;
1461 break;
1462
1463 case 'W':
1464 if (opP->mode != CONTROL
1465 || (opP->reg != DRP
1466 && opP->reg != SRP
1467 && opP->reg != CRP))
1468 losing++;
1469 break;
1470
1471 case 'X':
1472 if (opP->mode != CONTROL
1473 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1474 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1475 losing++;
1476 break;
1477
1478 case 'Y':
1479 if (opP->mode != CONTROL || opP->reg != PSR)
1480 losing++;
1481 break;
1482
1483 case 'Z':
1484 if (opP->mode != CONTROL || opP->reg != PCSR)
1485 losing++;
1486 break;
1487 #endif
1488 case 'c':
1489 if (opP->mode != CONTROL
1490 || (opP->reg != NC
1491 && opP->reg != IC
1492 && opP->reg != DC
1493 && opP->reg != BC))
1494 {
1495 losing++;
1496 } /* not a cache specifier. */
1497 break;
1498
1499 case '_':
1500 if (opP->mode != ABSL)
1501 ++losing;
1502 break;
1503
1504 default:
1505 abort ();
1506 } /* switch on type of operand */
1507
1508 if (losing)
1509 break;
1510 } /* for each operand */
1511 } /* if immediately wrong */
1512
1513 if (!losing)
1514 {
1515 break;
1516 } /* got it. */
1517
1518 opcode = opcode->m_next;
1519
1520 if (!opcode)
1521 {
1522 if (ok_arch
1523 && !(ok_arch & current_architecture))
1524 {
1525 char buf[200], *cp;
1526 int len;
1527 strcpy (buf,
1528 "invalid instruction for this architecture; needs ");
1529 cp = buf + strlen (buf);
1530 switch (ok_arch)
1531 {
1532 case mfloat:
1533 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1534 break;
1535 case mmmu:
1536 strcpy (cp, "mmu (68030 or 68851)");
1537 break;
1538 case m68020up:
1539 strcpy (cp, "68020 or higher");
1540 break;
1541 case m68000up:
1542 strcpy (cp, "68000 or higher");
1543 break;
1544 case m68010up:
1545 strcpy (cp, "68010 or higher");
1546 break;
1547 default:
1548 {
1549 int got_one = 0, idx;
1550 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1551 idx++)
1552 {
1553 if ((archs[idx].arch & ok_arch)
1554 && ! archs[idx].alias)
1555 {
1556 if (got_one)
1557 {
1558 strcpy (cp, " or ");
1559 cp += strlen (cp);
1560 }
1561 got_one = 1;
1562 strcpy (cp, archs[idx].name);
1563 cp += strlen (cp);
1564 }
1565 }
1566 }
1567 }
1568 len = cp - buf + 1;
1569 cp = malloc (len);
1570 strcpy (cp, buf);
1571 the_ins.error = cp;
1572 }
1573 else
1574 the_ins.error = "operands mismatch";
1575 return;
1576 } /* Fell off the end */
1577
1578 losing = 0;
1579 }
1580
1581 /* now assemble it */
1582
1583 the_ins.args = opcode->m_operands;
1584 the_ins.numargs = opcode->m_opnum;
1585 the_ins.numo = opcode->m_codenum;
1586 the_ins.opcode[0] = getone (opcode);
1587 the_ins.opcode[1] = gettwo (opcode);
1588
1589 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1590 {
1591 /* This switch is a doozy.
1592 Watch the first step; its a big one! */
1593 switch (s[0])
1594 {
1595
1596 case '*':
1597 case '~':
1598 case '%':
1599 case ';':
1600 case '@':
1601 case '!':
1602 case '&':
1603 case '$':
1604 case '?':
1605 case '/':
1606 case '`':
1607 #ifndef NO_68851
1608 case '|':
1609 #endif
1610 switch (opP->mode)
1611 {
1612 case IMMED:
1613 tmpreg = 0x3c; /* 7.4 */
1614 if (strchr ("bwl", s[1]))
1615 nextword = get_num (&opP->disp, 80);
1616 else
1617 nextword = get_num (&opP->disp, 0);
1618 if (isvar (&opP->disp))
1619 add_fix (s[1], &opP->disp, 0, 0);
1620 switch (s[1])
1621 {
1622 case 'b':
1623 if (!isbyte (nextword))
1624 opP->error = "operand out of range";
1625 addword (nextword);
1626 baseo = 0;
1627 break;
1628 case 'w':
1629 if (!isword (nextword))
1630 opP->error = "operand out of range";
1631 addword (nextword);
1632 baseo = 0;
1633 break;
1634 case 'W':
1635 if (!issword (nextword))
1636 opP->error = "operand out of range";
1637 addword (nextword);
1638 baseo = 0;
1639 break;
1640 case 'l':
1641 addword (nextword >> 16);
1642 addword (nextword);
1643 baseo = 0;
1644 break;
1645
1646 case 'f':
1647 baseo = 2;
1648 outro = 8;
1649 break;
1650 case 'F':
1651 baseo = 4;
1652 outro = 11;
1653 break;
1654 case 'x':
1655 baseo = 6;
1656 outro = 15;
1657 break;
1658 case 'p':
1659 baseo = 6;
1660 outro = -1;
1661 break;
1662 default:
1663 abort ();
1664 }
1665 if (!baseo)
1666 break;
1667
1668 /* We gotta put out some float */
1669 if (op (&opP->disp) != O_big)
1670 {
1671 valueT val;
1672 int gencnt;
1673
1674 /* Can other cases happen here? */
1675 if (op (&opP->disp) != O_constant)
1676 abort ();
1677
1678 val = (valueT) offs (&opP->disp);
1679 gencnt = 0;
1680 do
1681 {
1682 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1683 val >>= LITTLENUM_NUMBER_OF_BITS;
1684 ++gencnt;
1685 }
1686 while (val != 0);
1687 offs (&opP->disp) = gencnt;
1688 }
1689 if (offs (&opP->disp) > 0)
1690 {
1691 if (offs (&opP->disp) > baseo)
1692 {
1693 as_warn ("Bignum too big for %c format; truncated",
1694 s[1]);
1695 offs (&opP->disp) = baseo;
1696 }
1697 baseo -= offs (&opP->disp);
1698 while (baseo--)
1699 addword (0);
1700 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1701 offs (&opP->disp)--;
1702 --wordp)
1703 addword (*wordp);
1704 break;
1705 }
1706 gen_to_words (words, baseo, (long) outro);
1707 for (wordp = words; baseo--; wordp++)
1708 addword (*wordp);
1709 break;
1710 case DREG:
1711 tmpreg = opP->reg - DATA; /* 0.dreg */
1712 break;
1713 case AREG:
1714 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1715 break;
1716 case AINDR:
1717 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1718 break;
1719 case ADEC:
1720 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1721 break;
1722 case AINC:
1723 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1724 break;
1725 case DISP:
1726
1727 nextword = get_num (&opP->disp, 80);
1728
1729 if (opP->reg == PC
1730 && ! isvar (&opP->disp)
1731 && m68k_abspcadd)
1732 {
1733 opP->disp.exp.X_op = O_symbol;
1734 #ifndef BFD_ASSEMBLER
1735 opP->disp.exp.X_add_symbol = &abs_symbol;
1736 #else
1737 opP->disp.exp.X_add_symbol =
1738 section_symbol (absolute_section);
1739 #endif
1740 }
1741
1742 /* Force into index mode. Hope this works */
1743
1744 /* We do the first bit for 32-bit displacements, and the
1745 second bit for 16 bit ones. It is possible that we
1746 should make the default be WORD instead of LONG, but
1747 I think that'd break GCC, so we put up with a little
1748 inefficiency for the sake of working output. */
1749
1750 if (!issword (nextword)
1751 || (isvar (&opP->disp)
1752 && ((opP->disp.size == SIZE_UNSPEC
1753 && flag_short_refs == 0
1754 && cpu_of_arch (current_architecture) >= m68020)
1755 || opP->disp.size == SIZE_LONG)))
1756 {
1757 if (cpu_of_arch (current_architecture) < m68020)
1758 opP->error =
1759 "displacement too large for this architecture; needs 68020 or higher";
1760 if (opP->reg == PC)
1761 tmpreg = 0x3B; /* 7.3 */
1762 else
1763 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1764 if (isvar (&opP->disp))
1765 {
1766 if (opP->reg == PC)
1767 {
1768 if (opP->disp.size == SIZE_LONG
1769 #ifdef OBJ_ELF
1770 /* If the displacement needs pic
1771 relocation it cannot be relaxed. */
1772 || opP->disp.pic_reloc != pic_none
1773 #endif
1774 )
1775 {
1776 addword (0x0170);
1777 add_fix ('l', &opP->disp, 1, 2);
1778 }
1779 else
1780 {
1781 add_frag (adds (&opP->disp),
1782 offs (&opP->disp),
1783 TAB (PCLEA, SZ_UNDEF));
1784 break;
1785 }
1786 }
1787 else
1788 {
1789 addword (0x0170);
1790 add_fix ('l', &opP->disp, 0, 0);
1791 }
1792 }
1793 else
1794 addword (0x0170);
1795 addword (nextword >> 16);
1796 }
1797 else
1798 {
1799 if (opP->reg == PC)
1800 tmpreg = 0x3A; /* 7.2 */
1801 else
1802 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1803
1804 if (isvar (&opP->disp))
1805 {
1806 if (opP->reg == PC)
1807 {
1808 add_fix ('w', &opP->disp, 1, 0);
1809 }
1810 else
1811 add_fix ('w', &opP->disp, 0, 0);
1812 }
1813 }
1814 addword (nextword);
1815 break;
1816
1817 case POST:
1818 case PRE:
1819 case BASE:
1820 nextword = 0;
1821 baseo = get_num (&opP->disp, 80);
1822 if (opP->mode == POST || opP->mode == PRE)
1823 outro = get_num (&opP->odisp, 80);
1824 /* Figure out the `addressing mode'.
1825 Also turn on the BASE_DISABLE bit, if needed. */
1826 if (opP->reg == PC || opP->reg == ZPC)
1827 {
1828 tmpreg = 0x3b; /* 7.3 */
1829 if (opP->reg == ZPC)
1830 nextword |= 0x80;
1831 }
1832 else if (opP->reg == 0)
1833 {
1834 nextword |= 0x80;
1835 tmpreg = 0x30; /* 6.garbage */
1836 }
1837 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1838 {
1839 nextword |= 0x80;
1840 tmpreg = 0x30 + opP->reg - ZADDR0;
1841 }
1842 else
1843 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1844
1845 siz1 = opP->disp.size;
1846 if (opP->mode == POST || opP->mode == PRE)
1847 siz2 = opP->odisp.size;
1848 else
1849 siz2 = SIZE_UNSPEC;
1850
1851 /* Index register stuff */
1852 if (opP->index.reg != 0
1853 && opP->index.reg >= DATA
1854 && opP->index.reg <= ADDR7)
1855 {
1856 nextword |= (opP->index.reg - DATA) << 12;
1857
1858 if (opP->index.size == SIZE_UNSPEC
1859 || opP->index.size == SIZE_LONG)
1860 nextword |= 0x800;
1861
1862 if ((opP->index.scale != 1
1863 && cpu_of_arch (current_architecture) < m68020)
1864 || (opP->index.scale == 8
1865 && current_architecture == mcf5200))
1866 {
1867 opP->error =
1868 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
1869 }
1870
1871 switch (opP->index.scale)
1872 {
1873 case 1:
1874 break;
1875 case 2:
1876 nextword |= 0x200;
1877 break;
1878 case 4:
1879 nextword |= 0x400;
1880 break;
1881 case 8:
1882 nextword |= 0x600;
1883 break;
1884 default:
1885 abort ();
1886 }
1887 /* IF its simple,
1888 GET US OUT OF HERE! */
1889
1890 /* Must be INDEX, with an index register. Address
1891 register cannot be ZERO-PC, and either :b was
1892 forced, or we know it will fit. For a 68000 or
1893 68010, force this mode anyways, because the
1894 larger modes aren't supported. */
1895 if (opP->mode == BASE
1896 && ((opP->reg >= ADDR0
1897 && opP->reg <= ADDR7)
1898 || opP->reg == PC))
1899 {
1900 if (siz1 == SIZE_BYTE
1901 || cpu_of_arch (current_architecture) < m68020
1902 || (siz1 == SIZE_UNSPEC
1903 && ! isvar (&opP->disp)
1904 && issbyte (baseo)))
1905 {
1906 nextword += baseo & 0xff;
1907 addword (nextword);
1908 if (isvar (&opP->disp))
1909 {
1910 /* Do a byte relocation. If it doesn't
1911 fit (possible on m68000) let the
1912 fixup processing complain later. */
1913 if (opP->reg == PC)
1914 add_fix ('B', &opP->disp, 1, 1);
1915 else
1916 add_fix ('B', &opP->disp, 0, 0);
1917 }
1918 else if (siz1 != SIZE_BYTE)
1919 {
1920 if (siz1 != SIZE_UNSPEC)
1921 as_warn ("Forcing byte displacement");
1922 if (! issbyte (baseo))
1923 opP->error = "byte displacement out of range";
1924 }
1925
1926 break;
1927 }
1928 else if (siz1 == SIZE_UNSPEC
1929 && opP->reg == PC
1930 && isvar (&opP->disp)
1931 && subs (&opP->disp) == NULL
1932 #ifdef OBJ_ELF
1933 /* If the displacement needs pic
1934 relocation it cannot be relaxed. */
1935 && opP->disp.pic_reloc == pic_none
1936 #endif
1937 )
1938 {
1939 nextword += baseo & 0xff;
1940 addword (nextword);
1941 add_frag (adds (&opP->disp), offs (&opP->disp),
1942 TAB (PCINDEX, SZ_UNDEF));
1943
1944 break;
1945 }
1946 }
1947 }
1948 else
1949 {
1950 nextword |= 0x40; /* No index reg */
1951 if (opP->index.reg >= ZDATA0
1952 && opP->index.reg <= ZDATA7)
1953 nextword |= (opP->index.reg - ZDATA0) << 12;
1954 else if (opP->index.reg >= ZADDR0
1955 || opP->index.reg <= ZADDR7)
1956 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1957 }
1958
1959 /* It isn't simple. */
1960
1961 if (cpu_of_arch (current_architecture) < m68020)
1962 opP->error =
1963 "invalid operand mode for this architecture; needs 68020 or higher";
1964
1965 nextword |= 0x100;
1966 /* If the guy specified a width, we assume that it is
1967 wide enough. Maybe it isn't. If so, we lose. */
1968 switch (siz1)
1969 {
1970 case SIZE_UNSPEC:
1971 if (isvar (&opP->disp)
1972 ? m68k_rel32
1973 : ! issword (baseo))
1974 {
1975 siz1 = SIZE_LONG;
1976 nextword |= 0x30;
1977 }
1978 else if (! isvar (&opP->disp) && baseo == 0)
1979 nextword |= 0x10;
1980 else
1981 {
1982 nextword |= 0x20;
1983 siz1 = SIZE_WORD;
1984 }
1985 break;
1986 case SIZE_BYTE:
1987 as_warn (":b not permitted; defaulting to :w");
1988 /* Fall through. */
1989 case SIZE_WORD:
1990 nextword |= 0x20;
1991 break;
1992 case SIZE_LONG:
1993 nextword |= 0x30;
1994 break;
1995 }
1996
1997 /* Figure out innner displacement stuff */
1998 if (opP->mode == POST || opP->mode == PRE)
1999 {
2000 if (cpu_of_arch (current_architecture) & cpu32)
2001 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2002 switch (siz2)
2003 {
2004 case SIZE_UNSPEC:
2005 if (isvar (&opP->odisp)
2006 ? m68k_rel32
2007 : ! issword (outro))
2008 {
2009 siz2 = SIZE_LONG;
2010 nextword |= 0x3;
2011 }
2012 else if (! isvar (&opP->odisp) && outro == 0)
2013 nextword |= 0x1;
2014 else
2015 {
2016 nextword |= 0x2;
2017 siz2 = SIZE_WORD;
2018 }
2019 break;
2020 case 1:
2021 as_warn (":b not permitted; defaulting to :w");
2022 /* Fall through. */
2023 case 2:
2024 nextword |= 0x2;
2025 break;
2026 case 3:
2027 nextword |= 0x3;
2028 break;
2029 }
2030 if (opP->mode == POST
2031 && (nextword & 0x40) == 0)
2032 nextword |= 0x04;
2033 }
2034 addword (nextword);
2035
2036 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2037 {
2038 if (opP->reg == PC || opP->reg == ZPC)
2039 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2040 else
2041 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2042 }
2043 if (siz1 == SIZE_LONG)
2044 addword (baseo >> 16);
2045 if (siz1 != SIZE_UNSPEC)
2046 addword (baseo);
2047
2048 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2049 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2050 if (siz2 == SIZE_LONG)
2051 addword (outro >> 16);
2052 if (siz2 != SIZE_UNSPEC)
2053 addword (outro);
2054
2055 break;
2056
2057 case ABSL:
2058 nextword = get_num (&opP->disp, 80);
2059 switch (opP->disp.size)
2060 {
2061 default:
2062 abort ();
2063 case SIZE_UNSPEC:
2064 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2065 {
2066 tmpreg = 0x38; /* 7.0 */
2067 addword (nextword);
2068 break;
2069 }
2070 /* Don't generate pc relative code on 68010 and
2071 68000. */
2072 if (isvar (&opP->disp)
2073 && !subs (&opP->disp)
2074 && adds (&opP->disp)
2075 #ifdef OBJ_ELF
2076 /* If the displacement needs pic relocation it
2077 cannot be relaxed. */
2078 && opP->disp.pic_reloc == pic_none
2079 #endif
2080 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2081 && cpu_of_arch (current_architecture) >= m68020
2082 && !flag_long_jumps
2083 && !strchr ("~%&$?", s[0]))
2084 {
2085 tmpreg = 0x3A; /* 7.2 */
2086 add_frag (adds (&opP->disp),
2087 offs (&opP->disp),
2088 TAB (PCREL, SZ_UNDEF));
2089 break;
2090 }
2091 /* Fall through into long */
2092 case SIZE_LONG:
2093 if (isvar (&opP->disp))
2094 add_fix ('l', &opP->disp, 0, 0);
2095
2096 tmpreg = 0x39;/* 7.1 mode */
2097 addword (nextword >> 16);
2098 addword (nextword);
2099 break;
2100
2101 case SIZE_WORD: /* Word */
2102 if (isvar (&opP->disp))
2103 add_fix ('w', &opP->disp, 0, 0);
2104
2105 tmpreg = 0x38;/* 7.0 mode */
2106 addword (nextword);
2107 break;
2108 }
2109 break;
2110 case CONTROL:
2111 case FPREG:
2112 default:
2113 as_bad ("unknown/incorrect operand");
2114 /* abort(); */
2115 }
2116 install_gen_operand (s[1], tmpreg);
2117 break;
2118
2119 case '#':
2120 case '^':
2121 switch (s[1])
2122 { /* JF: I hate floating point! */
2123 case 'j':
2124 tmpreg = 70;
2125 break;
2126 case '8':
2127 tmpreg = 20;
2128 break;
2129 case 'C':
2130 tmpreg = 50;
2131 break;
2132 case '3':
2133 default:
2134 tmpreg = 80;
2135 break;
2136 }
2137 tmpreg = get_num (&opP->disp, tmpreg);
2138 if (isvar (&opP->disp))
2139 add_fix (s[1], &opP->disp, 0, 0);
2140 switch (s[1])
2141 {
2142 case 'b': /* Danger: These do no check for
2143 certain types of overflow.
2144 user beware! */
2145 if (!isbyte (tmpreg))
2146 opP->error = "out of range";
2147 insop (tmpreg, opcode);
2148 if (isvar (&opP->disp))
2149 the_ins.reloc[the_ins.nrel - 1].n =
2150 (opcode->m_codenum) * 2 + 1;
2151 break;
2152 case 'w':
2153 if (!isword (tmpreg))
2154 opP->error = "out of range";
2155 insop (tmpreg, opcode);
2156 if (isvar (&opP->disp))
2157 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2158 break;
2159 case 'W':
2160 if (!issword (tmpreg))
2161 opP->error = "out of range";
2162 insop (tmpreg, opcode);
2163 if (isvar (&opP->disp))
2164 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2165 break;
2166 case 'l':
2167 /* Because of the way insop works, we put these two out
2168 backwards. */
2169 insop (tmpreg, opcode);
2170 insop (tmpreg >> 16, opcode);
2171 if (isvar (&opP->disp))
2172 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2173 break;
2174 case '3':
2175 tmpreg &= 0xFF;
2176 case '8':
2177 case 'C':
2178 install_operand (s[1], tmpreg);
2179 break;
2180 default:
2181 abort ();
2182 }
2183 break;
2184
2185 case '+':
2186 case '-':
2187 case 'A':
2188 case 'a':
2189 install_operand (s[1], opP->reg - ADDR);
2190 break;
2191
2192 case 'B':
2193 tmpreg = get_num (&opP->disp, 80);
2194 switch (s[1])
2195 {
2196 case 'B':
2197 /* The pc_fix argument winds up in fx_pcrel_adjust,
2198 which is a char, and may therefore be unsigned. We
2199 want to pass -1, but we pass 64 instead, and convert
2200 back in md_pcrel_from. */
2201 add_fix ('B', &opP->disp, 1, 64);
2202 break;
2203 case 'W':
2204 add_fix ('w', &opP->disp, 1, 0);
2205 addword (0);
2206 break;
2207 case 'L':
2208 long_branch:
2209 if (cpu_of_arch (current_architecture) < m68020)
2210 as_warn ("Can't use long branches on 68000/68010");
2211 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2212 add_fix ('l', &opP->disp, 1, 0);
2213 addword (0);
2214 addword (0);
2215 break;
2216 case 'g':
2217 if (subs (&opP->disp)) /* We can't relax it */
2218 goto long_branch;
2219
2220 #ifdef OBJ_ELF
2221 /* If the displacement needs pic relocation it cannot be
2222 relaxed. */
2223 if (opP->disp.pic_reloc != pic_none)
2224 goto long_branch;
2225 #endif
2226
2227 /* This could either be a symbol, or an absolute
2228 address. No matter, the frag hacking will finger it
2229 out. Not quite: it can't switch from BRANCH to
2230 BCC68000 for the case where opnd is absolute (it
2231 needs to use the 68000 hack since no conditional abs
2232 jumps). */
2233 if (((cpu_of_arch (current_architecture) < m68020)
2234 || (0 == adds (&opP->disp)))
2235 && (the_ins.opcode[0] >= 0x6200)
2236 && (the_ins.opcode[0] <= 0x6f00))
2237 add_frag (adds (&opP->disp), offs (&opP->disp),
2238 TAB (BCC68000, SZ_UNDEF));
2239 else
2240 add_frag (adds (&opP->disp), offs (&opP->disp),
2241 TAB (ABRANCH, SZ_UNDEF));
2242 break;
2243 case 'w':
2244 if (isvar (&opP->disp))
2245 {
2246 #if 1
2247 /* check for DBcc instruction */
2248 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2249 {
2250 /* size varies if patch */
2251 /* needed for long form */
2252 add_frag (adds (&opP->disp), offs (&opP->disp),
2253 TAB (DBCC, SZ_UNDEF));
2254 break;
2255 }
2256 #endif
2257 add_fix ('w', &opP->disp, 1, 0);
2258 }
2259 addword (0);
2260 break;
2261 case 'C': /* Fixed size LONG coproc branches */
2262 add_fix ('l', &opP->disp, 1, 0);
2263 addword (0);
2264 addword (0);
2265 break;
2266 case 'c': /* Var size Coprocesssor branches */
2267 if (subs (&opP->disp))
2268 {
2269 add_fix ('l', &opP->disp, 1, 0);
2270 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2271 }
2272 else if (adds (&opP->disp))
2273 add_frag (adds (&opP->disp), offs (&opP->disp),
2274 TAB (FBRANCH, SZ_UNDEF));
2275 else
2276 {
2277 /* add_frag((symbolS *) 0, offs(&opP->disp),
2278 TAB(FBRANCH,SHORT)); */
2279 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2280 add_fix ('l', &opP->disp, 1, 0);
2281 addword (0);
2282 addword (0);
2283 }
2284 break;
2285 default:
2286 abort ();
2287 }
2288 break;
2289
2290 case 'C': /* Ignore it */
2291 break;
2292
2293 case 'd': /* JF this is a kludge */
2294 install_operand ('s', opP->reg - ADDR);
2295 tmpreg = get_num (&opP->disp, 80);
2296 if (!issword (tmpreg))
2297 {
2298 as_warn ("Expression out of range, using 0");
2299 tmpreg = 0;
2300 }
2301 addword (tmpreg);
2302 break;
2303
2304 case 'D':
2305 install_operand (s[1], opP->reg - DATA);
2306 break;
2307
2308 case 'F':
2309 install_operand (s[1], opP->reg - FP0);
2310 break;
2311
2312 case 'I':
2313 tmpreg = opP->reg - COP0;
2314 install_operand (s[1], tmpreg);
2315 break;
2316
2317 case 'J': /* JF foo */
2318 switch (opP->reg)
2319 {
2320 case SFC:
2321 tmpreg = 0x000;
2322 break;
2323 case DFC:
2324 tmpreg = 0x001;
2325 break;
2326 case CACR:
2327 tmpreg = 0x002;
2328 break;
2329 case TC:
2330 tmpreg = 0x003;
2331 break;
2332 case ITT0:
2333 tmpreg = 0x004;
2334 break;
2335 case ITT1:
2336 tmpreg = 0x005;
2337 break;
2338 case DTT0:
2339 tmpreg = 0x006;
2340 break;
2341 case DTT1:
2342 tmpreg = 0x007;
2343 break;
2344 case BUSCR:
2345 tmpreg = 0x008;
2346 break;
2347
2348 case USP:
2349 tmpreg = 0x800;
2350 break;
2351 case VBR:
2352 tmpreg = 0x801;
2353 break;
2354 case CAAR:
2355 tmpreg = 0x802;
2356 break;
2357 case MSP:
2358 tmpreg = 0x803;
2359 break;
2360 case ISP:
2361 tmpreg = 0x804;
2362 break;
2363 case MMUSR:
2364 tmpreg = 0x805;
2365 break;
2366 case URP:
2367 tmpreg = 0x806;
2368 break;
2369 case SRP:
2370 tmpreg = 0x807;
2371 break;
2372 case PCR:
2373 tmpreg = 0x808;
2374 break;
2375 case ROMBAR:
2376 tmpreg = 0xC00;
2377 break;
2378 case RAMBAR0:
2379 tmpreg = 0xC04;
2380 break;
2381 case RAMBAR1:
2382 tmpreg = 0xC05;
2383 break;
2384 case MBAR:
2385 tmpreg = 0xC0F;
2386 break;
2387 default:
2388 abort ();
2389 }
2390 install_operand (s[1], tmpreg);
2391 break;
2392
2393 case 'k':
2394 tmpreg = get_num (&opP->disp, 55);
2395 install_operand (s[1], tmpreg & 0x7f);
2396 break;
2397
2398 case 'l':
2399 tmpreg = opP->mask;
2400 if (s[1] == 'w')
2401 {
2402 if (tmpreg & 0x7FF0000)
2403 as_bad ("Floating point register in register list");
2404 insop (reverse_16_bits (tmpreg), opcode);
2405 }
2406 else
2407 {
2408 if (tmpreg & 0x700FFFF)
2409 as_bad ("Wrong register in floating-point reglist");
2410 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2411 }
2412 break;
2413
2414 case 'L':
2415 tmpreg = opP->mask;
2416 if (s[1] == 'w')
2417 {
2418 if (tmpreg & 0x7FF0000)
2419 as_bad ("Floating point register in register list");
2420 insop (tmpreg, opcode);
2421 }
2422 else if (s[1] == '8')
2423 {
2424 if (tmpreg & 0x0FFFFFF)
2425 as_bad ("incorrect register in reglist");
2426 install_operand (s[1], tmpreg >> 24);
2427 }
2428 else
2429 {
2430 if (tmpreg & 0x700FFFF)
2431 as_bad ("wrong register in floating-point reglist");
2432 else
2433 install_operand (s[1], tmpreg >> 16);
2434 }
2435 break;
2436
2437 case 'M':
2438 install_operand (s[1], get_num (&opP->disp, 60));
2439 break;
2440
2441 case 'O':
2442 tmpreg = ((opP->mode == DREG)
2443 ? 0x20 + opP->reg - DATA
2444 : (get_num (&opP->disp, 40) & 0x1F));
2445 install_operand (s[1], tmpreg);
2446 break;
2447
2448 case 'Q':
2449 tmpreg = get_num (&opP->disp, 10);
2450 if (tmpreg == 8)
2451 tmpreg = 0;
2452 install_operand (s[1], tmpreg);
2453 break;
2454
2455 case 'R':
2456 /* This depends on the fact that ADDR registers are eight
2457 more than their corresponding DATA regs, so the result
2458 will have the ADDR_REG bit set */
2459 install_operand (s[1], opP->reg - DATA);
2460 break;
2461
2462 case 'r':
2463 if (opP->mode == AINDR)
2464 install_operand (s[1], opP->reg - DATA);
2465 else
2466 install_operand (s[1], opP->index.reg - DATA);
2467 break;
2468
2469 case 's':
2470 if (opP->reg == FPI)
2471 tmpreg = 0x1;
2472 else if (opP->reg == FPS)
2473 tmpreg = 0x2;
2474 else if (opP->reg == FPC)
2475 tmpreg = 0x4;
2476 else
2477 abort ();
2478 install_operand (s[1], tmpreg);
2479 break;
2480
2481 case 'S': /* Ignore it */
2482 break;
2483
2484 case 'T':
2485 install_operand (s[1], get_num (&opP->disp, 30));
2486 break;
2487
2488 case 'U': /* Ignore it */
2489 break;
2490
2491 case 'c':
2492 switch (opP->reg)
2493 {
2494 case NC:
2495 tmpreg = 0;
2496 break;
2497 case DC:
2498 tmpreg = 1;
2499 break;
2500 case IC:
2501 tmpreg = 2;
2502 break;
2503 case BC:
2504 tmpreg = 3;
2505 break;
2506 default:
2507 as_fatal ("failed sanity check");
2508 } /* switch on cache token */
2509 install_operand (s[1], tmpreg);
2510 break;
2511 #ifndef NO_68851
2512 /* JF: These are out of order, I fear. */
2513 case 'f':
2514 switch (opP->reg)
2515 {
2516 case SFC:
2517 tmpreg = 0;
2518 break;
2519 case DFC:
2520 tmpreg = 1;
2521 break;
2522 default:
2523 abort ();
2524 }
2525 install_operand (s[1], tmpreg);
2526 break;
2527
2528 case '0':
2529 case '1':
2530 case '2':
2531 switch (opP->reg)
2532 {
2533 case TC:
2534 tmpreg = 0;
2535 break;
2536 case CAL:
2537 tmpreg = 4;
2538 break;
2539 case VAL:
2540 tmpreg = 5;
2541 break;
2542 case SCC:
2543 tmpreg = 6;
2544 break;
2545 case AC:
2546 tmpreg = 7;
2547 break;
2548 default:
2549 abort ();
2550 }
2551 install_operand (s[1], tmpreg);
2552 break;
2553
2554 case 'V':
2555 if (opP->reg == VAL)
2556 break;
2557 abort ();
2558
2559 case 'W':
2560 switch (opP->reg)
2561 {
2562 case DRP:
2563 tmpreg = 1;
2564 break;
2565 case SRP:
2566 tmpreg = 2;
2567 break;
2568 case CRP:
2569 tmpreg = 3;
2570 break;
2571 default:
2572 abort ();
2573 }
2574 install_operand (s[1], tmpreg);
2575 break;
2576
2577 case 'X':
2578 switch (opP->reg)
2579 {
2580 case BAD:
2581 case BAD + 1:
2582 case BAD + 2:
2583 case BAD + 3:
2584 case BAD + 4:
2585 case BAD + 5:
2586 case BAD + 6:
2587 case BAD + 7:
2588 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2589 break;
2590
2591 case BAC:
2592 case BAC + 1:
2593 case BAC + 2:
2594 case BAC + 3:
2595 case BAC + 4:
2596 case BAC + 5:
2597 case BAC + 6:
2598 case BAC + 7:
2599 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2600 break;
2601
2602 default:
2603 abort ();
2604 }
2605 install_operand (s[1], tmpreg);
2606 break;
2607 case 'Y':
2608 know (opP->reg == PSR);
2609 break;
2610 case 'Z':
2611 know (opP->reg == PCSR);
2612 break;
2613 #endif /* m68851 */
2614 case '3':
2615 switch (opP->reg)
2616 {
2617 case TT0:
2618 tmpreg = 2;
2619 break;
2620 case TT1:
2621 tmpreg = 3;
2622 break;
2623 default:
2624 abort ();
2625 }
2626 install_operand (s[1], tmpreg);
2627 break;
2628 case 't':
2629 tmpreg = get_num (&opP->disp, 20);
2630 install_operand (s[1], tmpreg);
2631 break;
2632 case '_': /* used only for move16 absolute 32-bit address */
2633 tmpreg = get_num (&opP->disp, 80);
2634 addword (tmpreg >> 16);
2635 addword (tmpreg & 0xFFFF);
2636 break;
2637 default:
2638 abort ();
2639 }
2640 }
2641
2642 /* By the time whe get here (FINALLY) the_ins contains the complete
2643 instruction, ready to be emitted. . . */
2644 }
2645
2646 static int
2647 reverse_16_bits (in)
2648 int in;
2649 {
2650 int out = 0;
2651 int n;
2652
2653 static int mask[16] =
2654 {
2655 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2656 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2657 };
2658 for (n = 0; n < 16; n++)
2659 {
2660 if (in & mask[n])
2661 out |= mask[15 - n];
2662 }
2663 return out;
2664 } /* reverse_16_bits() */
2665
2666 static int
2667 reverse_8_bits (in)
2668 int in;
2669 {
2670 int out = 0;
2671 int n;
2672
2673 static int mask[8] =
2674 {
2675 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2676 };
2677
2678 for (n = 0; n < 8; n++)
2679 {
2680 if (in & mask[n])
2681 out |= mask[7 - n];
2682 }
2683 return out;
2684 } /* reverse_8_bits() */
2685
2686 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2687 (that value is chosen in the frag_var call in md_assemble). TYPE
2688 is the subtype of the frag to be generated; its primary type is
2689 rs_machine_dependent.
2690
2691 The TYPE parameter is also used by md_convert_frag_1 and
2692 md_estimate_size_before_relax. The appropriate type of fixup will
2693 be emitted by md_convert_frag_1.
2694
2695 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2696 static void
2697 install_operand (mode, val)
2698 int mode;
2699 int val;
2700 {
2701 switch (mode)
2702 {
2703 case 's':
2704 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2705 break;
2706 case 'd':
2707 the_ins.opcode[0] |= val << 9;
2708 break;
2709 case '1':
2710 the_ins.opcode[1] |= val << 12;
2711 break;
2712 case '2':
2713 the_ins.opcode[1] |= val << 6;
2714 break;
2715 case '3':
2716 the_ins.opcode[1] |= val;
2717 break;
2718 case '4':
2719 the_ins.opcode[2] |= val << 12;
2720 break;
2721 case '5':
2722 the_ins.opcode[2] |= val << 6;
2723 break;
2724 case '6':
2725 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2726 three words long! */
2727 the_ins.numo++;
2728 the_ins.opcode[2] |= val;
2729 break;
2730 case '7':
2731 the_ins.opcode[1] |= val << 7;
2732 break;
2733 case '8':
2734 the_ins.opcode[1] |= val << 10;
2735 break;
2736 #ifndef NO_68851
2737 case '9':
2738 the_ins.opcode[1] |= val << 5;
2739 break;
2740 #endif
2741
2742 case 't':
2743 the_ins.opcode[1] |= (val << 10) | (val << 7);
2744 break;
2745 case 'D':
2746 the_ins.opcode[1] |= (val << 12) | val;
2747 break;
2748 case 'g':
2749 the_ins.opcode[0] |= val = 0xff;
2750 break;
2751 case 'i':
2752 the_ins.opcode[0] |= val << 9;
2753 break;
2754 case 'C':
2755 the_ins.opcode[1] |= val;
2756 break;
2757 case 'j':
2758 the_ins.opcode[1] |= val;
2759 the_ins.numo++; /* What a hack */
2760 break;
2761 case 'k':
2762 the_ins.opcode[1] |= val << 4;
2763 break;
2764 case 'b':
2765 case 'w':
2766 case 'W':
2767 case 'l':
2768 break;
2769 case 'e':
2770 the_ins.opcode[0] |= (val << 6);
2771 break;
2772 case 'L':
2773 the_ins.opcode[1] = (val >> 16);
2774 the_ins.opcode[2] = val & 0xffff;
2775 break;
2776 case 'c':
2777 default:
2778 as_fatal ("failed sanity check.");
2779 }
2780 } /* install_operand() */
2781
2782 static void
2783 install_gen_operand (mode, val)
2784 int mode;
2785 int val;
2786 {
2787 switch (mode)
2788 {
2789 case 's':
2790 the_ins.opcode[0] |= val;
2791 break;
2792 case 'd':
2793 /* This is a kludge!!! */
2794 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2795 break;
2796 case 'b':
2797 case 'w':
2798 case 'l':
2799 case 'f':
2800 case 'F':
2801 case 'x':
2802 case 'p':
2803 the_ins.opcode[0] |= val;
2804 break;
2805 /* more stuff goes here */
2806 default:
2807 as_fatal ("failed sanity check.");
2808 }
2809 } /* install_gen_operand() */
2810
2811 /*
2812 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2813 * then deal with the bitfield hack.
2814 */
2815
2816 static char *
2817 crack_operand (str, opP)
2818 register char *str;
2819 register struct m68k_op *opP;
2820 {
2821 register int parens;
2822 register int c;
2823 register char *beg_str;
2824 int inquote = 0;
2825
2826 if (!str)
2827 {
2828 return str;
2829 }
2830 beg_str = str;
2831 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2832 {
2833 if (! inquote)
2834 {
2835 if (*str == '(')
2836 parens++;
2837 else if (*str == ')')
2838 {
2839 if (!parens)
2840 { /* ERROR */
2841 opP->error = "Extra )";
2842 return str;
2843 }
2844 --parens;
2845 }
2846 }
2847 if (flag_mri && *str == '\'')
2848 inquote = ! inquote;
2849 }
2850 if (!*str && parens)
2851 { /* ERROR */
2852 opP->error = "Missing )";
2853 return str;
2854 }
2855 c = *str;
2856 *str = '\0';
2857 if (m68k_ip_op (beg_str, opP) != 0)
2858 {
2859 *str = c;
2860 return str;
2861 }
2862 *str = c;
2863 if (c == '}')
2864 c = *++str; /* JF bitfield hack */
2865 if (c)
2866 {
2867 c = *++str;
2868 if (!c)
2869 as_bad ("Missing operand");
2870 }
2871 return str;
2872 }
2873
2874 /* This is the guts of the machine-dependent assembler. STR points to a
2875 machine dependent instruction. This function is supposed to emit
2876 the frags/bytes it assembles to.
2877 */
2878
2879 void
2880 insert_reg (regname, regnum)
2881 char *regname;
2882 int regnum;
2883 {
2884 char buf[100];
2885 int i;
2886
2887 #ifdef REGISTER_PREFIX
2888 if (!flag_reg_prefix_optional)
2889 {
2890 buf[0] = REGISTER_PREFIX;
2891 strcpy (buf + 1, regname);
2892 regname = buf;
2893 }
2894 #endif
2895
2896 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2897 &zero_address_frag));
2898
2899 for (i = 0; regname[i]; i++)
2900 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2901 buf[i] = '\0';
2902
2903 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2904 &zero_address_frag));
2905 }
2906
2907 struct init_entry
2908 {
2909 const char *name;
2910 int number;
2911 };
2912
2913 static const struct init_entry init_table[] =
2914 {
2915 { "d0", DATA0 },
2916 { "d1", DATA1 },
2917 { "d2", DATA2 },
2918 { "d3", DATA3 },
2919 { "d4", DATA4 },
2920 { "d5", DATA5 },
2921 { "d6", DATA6 },
2922 { "d7", DATA7 },
2923 { "a0", ADDR0 },
2924 { "a1", ADDR1 },
2925 { "a2", ADDR2 },
2926 { "a3", ADDR3 },
2927 { "a4", ADDR4 },
2928 { "a5", ADDR5 },
2929 { "a6", ADDR6 },
2930 { "fp", ADDR6 },
2931 { "a7", ADDR7 },
2932 { "sp", ADDR7 },
2933 { "ssp", ADDR7 },
2934 { "fp0", FP0 },
2935 { "fp1", FP1 },
2936 { "fp2", FP2 },
2937 { "fp3", FP3 },
2938 { "fp4", FP4 },
2939 { "fp5", FP5 },
2940 { "fp6", FP6 },
2941 { "fp7", FP7 },
2942 { "fpi", FPI },
2943 { "fpiar", FPI },
2944 { "fpc", FPI },
2945 { "fps", FPS },
2946 { "fpsr", FPS },
2947 { "fpc", FPC },
2948 { "fpcr", FPC },
2949 { "control", FPC },
2950 { "status", FPS },
2951 { "iaddr", FPI },
2952
2953 { "cop0", COP0 },
2954 { "cop1", COP1 },
2955 { "cop2", COP2 },
2956 { "cop3", COP3 },
2957 { "cop4", COP4 },
2958 { "cop5", COP5 },
2959 { "cop6", COP6 },
2960 { "cop7", COP7 },
2961 { "pc", PC },
2962 { "zpc", ZPC },
2963 { "sr", SR },
2964
2965 { "ccr", CCR },
2966 { "cc", CCR },
2967
2968 /* control registers */
2969 { "sfc", SFC }, /* Source Function Code */
2970 { "sfcr", SFC },
2971 { "dfc", DFC }, /* Destination Function Code */
2972 { "dfcr", DFC },
2973 { "cacr", CACR }, /* Cache Control Register */
2974 { "caar", CAAR }, /* Cache Address Register */
2975
2976 { "usp", USP }, /* User Stack Pointer */
2977 { "vbr", VBR }, /* Vector Base Register */
2978 { "msp", MSP }, /* Master Stack Pointer */
2979 { "isp", ISP }, /* Interrupt Stack Pointer */
2980
2981 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
2982 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
2983 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
2984 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
2985
2986 /* 68ec040 versions of same */
2987 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
2988 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
2989 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
2990 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
2991
2992 /* mcf5200 versions of same */
2993 { "acr2", ITT0 }, /* Access Control Unit 2 */
2994 { "acr3", ITT1 }, /* Access Control Unit 3 */
2995 { "acr0", DTT0 }, /* Access Control Unit 0 */
2996 { "acr1", DTT1 }, /* Access Control Unit 1 */
2997
2998 { "tc", TC }, /* MMU Translation Control Register */
2999 { "tcr", TC },
3000
3001 { "mmusr", MMUSR }, /* MMU Status Register */
3002 { "srp", SRP }, /* User Root Pointer */
3003 { "urp", URP }, /* Supervisor Root Pointer */
3004
3005 { "buscr", BUSCR },
3006 { "pcr", PCR },
3007
3008 { "rombar", ROMBAR }, /* ROM Base Address Register */
3009 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3010 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3011 { "mbar", MBAR }, /* Module Base Address Register */
3012 /* end of control registers */
3013
3014 { "ac", AC },
3015 { "bc", BC },
3016 { "cal", CAL },
3017 { "crp", CRP },
3018 { "drp", DRP },
3019 { "pcsr", PCSR },
3020 { "psr", PSR },
3021 { "scc", SCC },
3022 { "val", VAL },
3023 { "bad0", BAD0 },
3024 { "bad1", BAD1 },
3025 { "bad2", BAD2 },
3026 { "bad3", BAD3 },
3027 { "bad4", BAD4 },
3028 { "bad5", BAD5 },
3029 { "bad6", BAD6 },
3030 { "bad7", BAD7 },
3031 { "bac0", BAC0 },
3032 { "bac1", BAC1 },
3033 { "bac2", BAC2 },
3034 { "bac3", BAC3 },
3035 { "bac4", BAC4 },
3036 { "bac5", BAC5 },
3037 { "bac6", BAC6 },
3038 { "bac7", BAC7 },
3039
3040 { "ic", IC },
3041 { "dc", DC },
3042 { "nc", NC },
3043
3044 { "tt0", TT0 },
3045 { "tt1", TT1 },
3046 /* 68ec030 versions of same */
3047 { "ac0", TT0 },
3048 { "ac1", TT1 },
3049 /* 68ec030 access control unit, identical to 030 MMU status reg */
3050 { "acusr", PSR },
3051
3052 /* Suppressed data and address registers. */
3053 { "zd0", ZDATA0 },
3054 { "zd1", ZDATA1 },
3055 { "zd2", ZDATA2 },
3056 { "zd3", ZDATA3 },
3057 { "zd4", ZDATA4 },
3058 { "zd5", ZDATA5 },
3059 { "zd6", ZDATA6 },
3060 { "zd7", ZDATA7 },
3061 { "za0", ZADDR0 },
3062 { "za1", ZADDR1 },
3063 { "za2", ZADDR2 },
3064 { "za3", ZADDR3 },
3065 { "za4", ZADDR4 },
3066 { "za5", ZADDR5 },
3067 { "za6", ZADDR6 },
3068 { "za7", ZADDR7 },
3069
3070 { 0, 0 }
3071 };
3072
3073 void
3074 init_regtable ()
3075 {
3076 int i;
3077 for (i = 0; init_table[i].name; i++)
3078 insert_reg (init_table[i].name, init_table[i].number);
3079 }
3080
3081 static int no_68851, no_68881;
3082
3083 #ifdef OBJ_AOUT
3084 /* a.out machine type. Default to 68020. */
3085 int m68k_aout_machtype = 2;
3086 #endif
3087
3088 void
3089 md_assemble (str)
3090 char *str;
3091 {
3092 const char *er;
3093 short *fromP;
3094 char *toP = NULL;
3095 int m, n = 0;
3096 char *to_beg_P;
3097 int shorts_this_frag;
3098 fixS *fixP;
3099
3100 /* In MRI mode, the instruction and operands are separated by a
3101 space. Anything following the operands is a comment. The label
3102 has already been removed. */
3103 if (flag_mri)
3104 {
3105 char *s;
3106 int fields = 0;
3107 int infield = 0;
3108 int inquote = 0;
3109
3110 for (s = str; *s != '\0'; s++)
3111 {
3112 if ((*s == ' ' || *s == '\t') && ! inquote)
3113 {
3114 if (infield)
3115 {
3116 ++fields;
3117 if (fields >= 2)
3118 {
3119 *s = '\0';
3120 break;
3121 }
3122 infield = 0;
3123 }
3124 }
3125 else
3126 {
3127 if (! infield)
3128 infield = 1;
3129 if (*s == '\'')
3130 inquote = ! inquote;
3131 }
3132 }
3133 }
3134
3135 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3136 m68k_ip (str);
3137 er = the_ins.error;
3138 if (!er)
3139 {
3140 for (n = 0; n < the_ins.numargs; n++)
3141 if (the_ins.operands[n].error)
3142 {
3143 er = the_ins.operands[n].error;
3144 break;
3145 }
3146 }
3147 if (er)
3148 {
3149 as_bad ("%s -- statement `%s' ignored", er, str);
3150 return;
3151 }
3152
3153 if (the_ins.nfrag == 0)
3154 {
3155 /* No frag hacking involved; just put it out */
3156 toP = frag_more (2 * the_ins.numo);
3157 fromP = &the_ins.opcode[0];
3158 for (m = the_ins.numo; m; --m)
3159 {
3160 md_number_to_chars (toP, (long) (*fromP), 2);
3161 toP += 2;
3162 fromP++;
3163 }
3164 /* put out symbol-dependent info */
3165 for (m = 0; m < the_ins.nrel; m++)
3166 {
3167 switch (the_ins.reloc[m].wid)
3168 {
3169 case 'B':
3170 n = 1;
3171 break;
3172 case 'b':
3173 n = 1;
3174 break;
3175 case '3':
3176 n = 2;
3177 break;
3178 case 'w':
3179 n = 2;
3180 break;
3181 case 'l':
3182 n = 4;
3183 break;
3184 default:
3185 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3186 the_ins.reloc[m].wid);
3187 }
3188
3189 fixP = fix_new_exp (frag_now,
3190 ((toP - frag_now->fr_literal)
3191 - the_ins.numo * 2 + the_ins.reloc[m].n),
3192 n,
3193 &the_ins.reloc[m].exp,
3194 the_ins.reloc[m].pcrel,
3195 get_reloc_code (n, the_ins.reloc[m].pcrel,
3196 the_ins.reloc[m].pic_reloc));
3197 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3198 }
3199 return;
3200 }
3201
3202 /* There's some frag hacking */
3203 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3204 {
3205 int wid;
3206
3207 if (n == 0)
3208 wid = 2 * the_ins.fragb[n].fragoff;
3209 else
3210 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3211 toP = frag_more (wid);
3212 to_beg_P = toP;
3213 shorts_this_frag = 0;
3214 for (m = wid / 2; m; --m)
3215 {
3216 md_number_to_chars (toP, (long) (*fromP), 2);
3217 toP += 2;
3218 fromP++;
3219 shorts_this_frag++;
3220 }
3221 for (m = 0; m < the_ins.nrel; m++)
3222 {
3223 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3224 {
3225 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3226 break;
3227 }
3228 wid = the_ins.reloc[m].wid;
3229 if (wid == 0)
3230 continue;
3231 the_ins.reloc[m].wid = 0;
3232 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3233
3234 fixP = fix_new_exp (frag_now,
3235 ((toP - frag_now->fr_literal)
3236 - the_ins.numo * 2 + the_ins.reloc[m].n),
3237 wid,
3238 &the_ins.reloc[m].exp,
3239 the_ins.reloc[m].pcrel,
3240 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3241 the_ins.reloc[m].pic_reloc));
3242 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3243 }
3244 (void) frag_var (rs_machine_dependent, 10, 0,
3245 (relax_substateT) (the_ins.fragb[n].fragty),
3246 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3247 }
3248 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3249 shorts_this_frag = 0;
3250 if (n)
3251 {
3252 toP = frag_more (n * sizeof (short));
3253 while (n--)
3254 {
3255 md_number_to_chars (toP, (long) (*fromP), 2);
3256 toP += 2;
3257 fromP++;
3258 shorts_this_frag++;
3259 }
3260 }
3261 for (m = 0; m < the_ins.nrel; m++)
3262 {
3263 int wid;
3264
3265 wid = the_ins.reloc[m].wid;
3266 if (wid == 0)
3267 continue;
3268 the_ins.reloc[m].wid = 0;
3269 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3270
3271 fixP = fix_new_exp (frag_now,
3272 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3273 - shorts_this_frag * 2),
3274 wid,
3275 &the_ins.reloc[m].exp,
3276 the_ins.reloc[m].pcrel,
3277 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3278 the_ins.reloc[m].pic_reloc));
3279 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3280 }
3281 }
3282
3283 void
3284 md_begin ()
3285 {
3286 /*
3287 * md_begin -- set up hash tables with 68000 instructions.
3288 * similar to what the vax assembler does. ---phr
3289 */
3290 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3291 a copy of it at runtime, adding in the information we want but isn't
3292 there. I think it'd be better to have an awk script hack the table
3293 at compile time. Or even just xstr the table and use it as-is. But
3294 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3295 names. */
3296
3297 register const struct m68k_opcode *ins;
3298 register struct m68k_incant *hack, *slak;
3299 register const char *retval = 0; /* empty string, or error msg text */
3300 register unsigned int i;
3301 register char c;
3302
3303 if (flag_mri)
3304 {
3305 flag_reg_prefix_optional = 1;
3306 m68k_abspcadd = 1;
3307 m68k_rel32 = 0;
3308 }
3309
3310 op_hash = hash_new ();
3311
3312 obstack_begin (&robyn, 4000);
3313 for (i = 0; i < m68k_numopcodes; i++)
3314 {
3315 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3316 do
3317 {
3318 ins = &m68k_opcodes[i];
3319 /* We *could* ignore insns that don't match our arch here
3320 but just leaving them out of the hash. */
3321 slak->m_operands = ins->args;
3322 slak->m_opnum = strlen (slak->m_operands) / 2;
3323 slak->m_arch = ins->arch;
3324 slak->m_opcode = ins->opcode;
3325 /* This is kludgey */
3326 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3327 if (i + 1 != m68k_numopcodes
3328 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3329 {
3330 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3331 i++;
3332 }
3333 else
3334 slak->m_next = 0;
3335 slak = slak->m_next;
3336 }
3337 while (slak);
3338
3339 retval = hash_insert (op_hash, ins->name, (char *) hack);
3340 if (retval)
3341 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3342 }
3343
3344 for (i = 0; i < m68k_numaliases; i++)
3345 {
3346 const char *name = m68k_opcode_aliases[i].primary;
3347 const char *alias = m68k_opcode_aliases[i].alias;
3348 PTR val = hash_find (op_hash, name);
3349 if (!val)
3350 as_fatal ("Internal Error: Can't find %s in hash table", name);
3351 retval = hash_insert (op_hash, alias, val);
3352 if (retval)
3353 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3354 }
3355
3356 /* In MRI mode, all unsized branches are variable sized. Normally,
3357 they are word sized. */
3358 if (flag_mri)
3359 {
3360 static struct m68k_opcode_alias mri_aliases[] =
3361 {
3362 { "bhi", "jhi", },
3363 { "bls", "jls", },
3364 { "bcc", "jcc", },
3365 { "bcs", "jcs", },
3366 { "bne", "jne", },
3367 { "beq", "jeq", },
3368 { "bvc", "jvc", },
3369 { "bvs", "jvs", },
3370 { "bpl", "jpl", },
3371 { "bmi", "jmi", },
3372 { "bge", "jge", },
3373 { "blt", "jlt", },
3374 { "bgt", "jgt", },
3375 { "ble", "jle", },
3376 { "bra", "jra", },
3377 { "bsr", "jbsr", },
3378 };
3379
3380 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3381 {
3382 const char *name = mri_aliases[i].primary;
3383 const char *alias = mri_aliases[i].alias;
3384 PTR val = hash_find (op_hash, name);
3385 if (!val)
3386 as_fatal ("Internal Error: Can't find %s in hash table", name);
3387 retval = hash_jam (op_hash, alias, val);
3388 if (retval)
3389 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3390 }
3391 }
3392
3393 for (i = 0; i < sizeof (mklower_table); i++)
3394 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3395
3396 for (i = 0; i < sizeof (notend_table); i++)
3397 {
3398 notend_table[i] = 0;
3399 alt_notend_table[i] = 0;
3400 }
3401 notend_table[','] = 1;
3402 notend_table['{'] = 1;
3403 notend_table['}'] = 1;
3404 alt_notend_table['a'] = 1;
3405 alt_notend_table['A'] = 1;
3406 alt_notend_table['d'] = 1;
3407 alt_notend_table['D'] = 1;
3408 alt_notend_table['#'] = 1;
3409 alt_notend_table['&'] = 1;
3410 alt_notend_table['f'] = 1;
3411 alt_notend_table['F'] = 1;
3412 #ifdef REGISTER_PREFIX
3413 alt_notend_table[REGISTER_PREFIX] = 1;
3414 #endif
3415
3416 /* We need to put '(' in alt_notend_table to handle
3417 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3418 */
3419 alt_notend_table['('] = 1;
3420
3421 /* We need to put '@' in alt_notend_table to handle
3422 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3423 */
3424 alt_notend_table['@'] = 1;
3425
3426 /* We need to put digits in alt_notend_table to handle
3427 bfextu %d0{24:1},%d0
3428 */
3429 alt_notend_table['0'] = 1;
3430 alt_notend_table['1'] = 1;
3431 alt_notend_table['2'] = 1;
3432 alt_notend_table['3'] = 1;
3433 alt_notend_table['4'] = 1;
3434 alt_notend_table['5'] = 1;
3435 alt_notend_table['6'] = 1;
3436 alt_notend_table['7'] = 1;
3437 alt_notend_table['8'] = 1;
3438 alt_notend_table['9'] = 1;
3439
3440 #ifndef MIT_SYNTAX_ONLY
3441 /* Insert pseudo ops, these have to go into the opcode table since
3442 gas expects pseudo ops to start with a dot */
3443 {
3444 int n = 0;
3445 while (mote_pseudo_table[n].poc_name)
3446 {
3447 hack = (struct m68k_incant *)
3448 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3449 hash_insert (op_hash,
3450 mote_pseudo_table[n].poc_name, (char *) hack);
3451 hack->m_operands = 0;
3452 hack->m_opnum = n;
3453 n++;
3454 }
3455 }
3456 #endif
3457
3458 init_regtable ();
3459
3460 #ifdef OBJ_ELF
3461 record_alignment (text_section, 2);
3462 record_alignment (data_section, 2);
3463 record_alignment (bss_section, 2);
3464 #endif
3465 }
3466
3467 void
3468 m68k_init_after_args ()
3469 {
3470 if (cpu_of_arch (current_architecture) == 0)
3471 {
3472 int i;
3473 const char *default_cpu = TARGET_CPU;
3474
3475 if (*default_cpu == 'm')
3476 default_cpu++;
3477 for (i = 0; i < n_archs; i++)
3478 if (strcasecmp (default_cpu, archs[i].name) == 0)
3479 break;
3480 if (i == n_archs)
3481 {
3482 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3483 current_architecture |= m68020;
3484 }
3485 else
3486 current_architecture |= archs[i].arch;
3487 }
3488 /* Permit m68881 specification with all cpus; those that can't work
3489 with a coprocessor could be doing emulation. */
3490 if (current_architecture & m68851)
3491 {
3492 if (current_architecture & m68040)
3493 {
3494 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3495 }
3496 }
3497 /* What other incompatibilities could we check for? */
3498
3499 /* Toss in some default assumptions about coprocessors. */
3500 if (!no_68881
3501 && (cpu_of_arch (current_architecture)
3502 /* Can CPU32 have a 68881 coprocessor?? */
3503 & (m68020 | m68030 | cpu32)))
3504 {
3505 current_architecture |= m68881;
3506 }
3507 if (!no_68851
3508 && (cpu_of_arch (current_architecture) & m68020up) != 0
3509 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3510 {
3511 current_architecture |= m68851;
3512 }
3513 if (no_68881 && (current_architecture & m68881))
3514 as_bad ("options for 68881 and no-68881 both given");
3515 if (no_68851 && (current_architecture & m68851))
3516 as_bad ("options for 68851 and no-68851 both given");
3517
3518 #ifdef OBJ_AOUT
3519 /* Work out the magic number. This isn't very general. */
3520 if (current_architecture & m68000)
3521 m68k_aout_machtype = 0;
3522 else if (current_architecture & m68010)
3523 m68k_aout_machtype = 1;
3524 else if (current_architecture & m68020)
3525 m68k_aout_machtype = 2;
3526 else
3527 m68k_aout_machtype = 2;
3528 #endif
3529
3530 /* Note which set of "movec" control registers is available. */
3531 switch (cpu_of_arch (current_architecture))
3532 {
3533 case m68000:
3534 control_regs = m68000_control_regs;
3535 break;
3536 case m68010:
3537 control_regs = m68010_control_regs;
3538 break;
3539 case m68020:
3540 case m68030:
3541 control_regs = m68020_control_regs;
3542 break;
3543 case m68040:
3544 control_regs = m68040_control_regs;
3545 break;
3546 case m68060:
3547 control_regs = m68060_control_regs;
3548 break;
3549 case cpu32:
3550 control_regs = cpu32_control_regs;
3551 break;
3552 case mcf5200:
3553 control_regs = mcf5200_control_regs;
3554 break;
3555 default:
3556 abort ();
3557 }
3558
3559 if (cpu_of_arch (current_architecture) < m68020)
3560 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3561 }
3562
3563 /* This is called if we go in or out of MRI mode because of the .mri
3564 pseudo-op. */
3565
3566 void
3567 m68k_mri_mode_change (on)
3568 int on;
3569 {
3570 if (on)
3571 {
3572 if (! flag_reg_prefix_optional)
3573 {
3574 flag_reg_prefix_optional = 1;
3575 #ifdef REGISTER_PREFIX
3576 init_regtable ();
3577 #endif
3578 }
3579 m68k_abspcadd = 1;
3580 m68k_rel32 = 0;
3581 }
3582 else
3583 {
3584 if (! reg_prefix_optional_seen)
3585 {
3586 #ifdef REGISTER_PREFIX_OPTIONAL
3587 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3588 #else
3589 flag_reg_prefix_optional = 0;
3590 #endif
3591 #ifdef REGISTER_PREFIX
3592 init_regtable ();
3593 #endif
3594 }
3595 m68k_abspcadd = 0;
3596 m68k_rel32 = 1;
3597 }
3598 }
3599
3600 /* Equal to MAX_PRECISION in atof-ieee.c */
3601 #define MAX_LITTLENUMS 6
3602
3603 /* Turn a string in input_line_pointer into a floating point constant
3604 of type type, and store the appropriate bytes in *litP. The number
3605 of LITTLENUMS emitted is stored in *sizeP . An error message is
3606 returned, or NULL on OK. */
3607
3608 char *
3609 md_atof (type, litP, sizeP)
3610 char type;
3611 char *litP;
3612 int *sizeP;
3613 {
3614 int prec;
3615 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3616 LITTLENUM_TYPE *wordP;
3617 char *t;
3618 char *atof_ieee ();
3619
3620 switch (type)
3621 {
3622 case 'f':
3623 case 'F':
3624 case 's':
3625 case 'S':
3626 prec = 2;
3627 break;
3628
3629 case 'd':
3630 case 'D':
3631 case 'r':
3632 case 'R':
3633 prec = 4;
3634 break;
3635
3636 case 'x':
3637 case 'X':
3638 prec = 6;
3639 break;
3640
3641 case 'p':
3642 case 'P':
3643 prec = 6;
3644 break;
3645
3646 default:
3647 *sizeP = 0;
3648 return "Bad call to MD_ATOF()";
3649 }
3650 t = atof_ieee (input_line_pointer, type, words);
3651 if (t)
3652 input_line_pointer = t;
3653
3654 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3655 for (wordP = words; prec--;)
3656 {
3657 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3658 litP += sizeof (LITTLENUM_TYPE);
3659 }
3660 return 0;
3661 }
3662
3663 void
3664 md_number_to_chars (buf, val, n)
3665 char *buf;
3666 valueT val;
3667 int n;
3668 {
3669 number_to_chars_bigendian (buf, val, n);
3670 }
3671
3672 static void
3673 md_apply_fix_2 (fixP, val)
3674 fixS *fixP;
3675 offsetT val;
3676 {
3677 addressT upper_limit;
3678 offsetT lower_limit;
3679
3680 /* This is unnecessary but it convinces the native rs6000 compiler
3681 to generate the code we want. */
3682 char *buf = fixP->fx_frag->fr_literal;
3683 buf += fixP->fx_where;
3684 /* end ibm compiler workaround */
3685
3686 if (val & 0x80000000)
3687 val |= ~(addressT)0x7fffffff;
3688 else
3689 val &= 0x7fffffff;
3690
3691 #ifdef OBJ_ELF
3692 if (fixP->fx_addsy)
3693 {
3694 memset (buf, 0, fixP->fx_size);
3695 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3696 return;
3697 }
3698 #endif
3699
3700 switch (fixP->fx_size)
3701 {
3702 /* The cast to offsetT below are necessary to make code correct for
3703 machines where ints are smaller than offsetT */
3704 case 1:
3705 *buf++ = val;
3706 upper_limit = 0x7f;
3707 lower_limit = - (offsetT) 0x80;
3708 break;
3709 case 2:
3710 *buf++ = (val >> 8);
3711 *buf++ = val;
3712 upper_limit = 0x7fff;
3713 lower_limit = - (offsetT) 0x8000;
3714 break;
3715 case 4:
3716 *buf++ = (val >> 24);
3717 *buf++ = (val >> 16);
3718 *buf++ = (val >> 8);
3719 *buf++ = val;
3720 upper_limit = 0x7fffffff;
3721 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3722 break;
3723 default:
3724 BAD_CASE (fixP->fx_size);
3725 }
3726
3727 /* Fix up a negative reloc. */
3728 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3729 {
3730 fixP->fx_addsy = fixP->fx_subsy;
3731 fixP->fx_subsy = NULL;
3732 fixP->fx_tcbit = 1;
3733 }
3734
3735 /* For non-pc-relative values, it's conceivable we might get something
3736 like "0xff" for a byte field. So extend the upper part of the range
3737 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3738 so that we can do any range checking at all. */
3739 if (!fixP->fx_pcrel)
3740 upper_limit = upper_limit * 2 + 1;
3741
3742 if ((addressT) val > upper_limit
3743 && (val > 0 || val < lower_limit))
3744 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3745
3746 /* A one byte PC-relative reloc means a short branch. We can't use
3747 a short branch with a value of 0 or -1, because those indicate
3748 different opcodes (branches with longer offsets). */
3749 if (fixP->fx_pcrel
3750 && fixP->fx_size == 1
3751 && (fixP->fx_addsy == NULL
3752 || S_IS_DEFINED (fixP->fx_addsy))
3753 && (val == 0 || val == -1))
3754 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3755 }
3756
3757 #ifdef BFD_ASSEMBLER
3758 int
3759 md_apply_fix (fixP, valp)
3760 fixS *fixP;
3761 valueT *valp;
3762 {
3763 md_apply_fix_2 (fixP, (addressT) *valp);
3764 return 1;
3765 }
3766 #else
3767 void md_apply_fix (fixP, val)
3768 fixS *fixP;
3769 long val;
3770 {
3771 md_apply_fix_2 (fixP, (addressT) val);
3772 }
3773 #endif
3774
3775 /* *fragP has been relaxed to its final size, and now needs to have
3776 the bytes inside it modified to conform to the new size There is UGLY
3777 MAGIC here. ..
3778 */
3779 void
3780 md_convert_frag_1 (fragP)
3781 register fragS *fragP;
3782 {
3783 long disp;
3784 long ext = 0;
3785 fixS *fixP;
3786
3787 /* Address in object code of the displacement. */
3788 register int object_address = fragP->fr_fix + fragP->fr_address;
3789
3790 /* Address in gas core of the place to store the displacement. */
3791 /* This convinces the native rs6000 compiler to generate the code we
3792 want. */
3793 register char *buffer_address = fragP->fr_literal;
3794 buffer_address += fragP->fr_fix;
3795 /* end ibm compiler workaround */
3796
3797 /* The displacement of the address, from current location. */
3798 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3799 disp = (disp + fragP->fr_offset) - object_address;
3800
3801 #ifdef BFD_ASSEMBLER
3802 disp += fragP->fr_symbol->sy_frag->fr_address;
3803 #endif
3804
3805 switch (fragP->fr_subtype)
3806 {
3807 case TAB (BCC68000, BYTE):
3808 case TAB (ABRANCH, BYTE):
3809 know (issbyte (disp));
3810 if (disp == 0)
3811 as_bad ("short branch with zero offset: use :w");
3812 fragP->fr_opcode[1] = disp;
3813 ext = 0;
3814 break;
3815 case TAB (DBCC, SHORT):
3816 know (issword (disp));
3817 ext = 2;
3818 break;
3819 case TAB (BCC68000, SHORT):
3820 case TAB (ABRANCH, SHORT):
3821 know (issword (disp));
3822 fragP->fr_opcode[1] = 0x00;
3823 ext = 2;
3824 break;
3825 case TAB (ABRANCH, LONG):
3826 if (cpu_of_arch (current_architecture) < m68020)
3827 {
3828 if (fragP->fr_opcode[0] == 0x61)
3829 /* BSR */
3830 {
3831 fragP->fr_opcode[0] = 0x4E;
3832 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3833
3834 fix_new (fragP,
3835 fragP->fr_fix,
3836 4,
3837 fragP->fr_symbol,
3838 fragP->fr_offset,
3839 0,
3840 NO_RELOC);
3841
3842 fragP->fr_fix += 4;
3843 ext = 0;
3844 }
3845 /* BRA */
3846 else if (fragP->fr_opcode[0] == 0x60)
3847 {
3848 fragP->fr_opcode[0] = 0x4E;
3849 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3850 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3851 fragP->fr_offset, 0, NO_RELOC);
3852 fragP->fr_fix += 4;
3853 ext = 0;
3854 }
3855 else
3856 {
3857 as_bad ("Long branch offset not supported.");
3858 }
3859 }
3860 else
3861 {
3862 fragP->fr_opcode[1] = (char) 0xff;
3863 ext = 4;
3864 }
3865 break;
3866 case TAB (BCC68000, LONG):
3867 /* only Bcc 68000 instructions can come here */
3868 /* change bcc into b!cc/jmp absl long */
3869 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3870 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3871
3872 /* JF: these used to be fr_opcode[2,3], but they may be in a
3873 different frag, in which case refering to them is a no-no.
3874 Only fr_opcode[0,1] are guaranteed to work. */
3875 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3876 *buffer_address++ = (char) 0xf9;
3877 fragP->fr_fix += 2; /* account for jmp instruction */
3878 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3879 fragP->fr_offset, 0, NO_RELOC);
3880 fragP->fr_fix += 4;
3881 ext = 0;
3882 break;
3883 case TAB (DBCC, LONG):
3884 /* only DBcc 68000 instructions can come here */
3885 /* change dbcc into dbcc/jmp absl long */
3886 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3887 *buffer_address++ = 0x00; /* branch offset = 4 */
3888 *buffer_address++ = 0x04;
3889 *buffer_address++ = 0x60; /* put in bra pc+6 */
3890 *buffer_address++ = 0x06;
3891 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3892 *buffer_address++ = (char) 0xf9;
3893
3894 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3895 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3896 fragP->fr_offset, 0, NO_RELOC);
3897 fragP->fr_fix += 4;
3898 ext = 0;
3899 break;
3900 case TAB (FBRANCH, SHORT):
3901 know ((fragP->fr_opcode[1] & 0x40) == 0);
3902 ext = 2;
3903 break;
3904 case TAB (FBRANCH, LONG):
3905 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3906 ext = 4;
3907 break;
3908 case TAB (PCREL, SHORT):
3909 ext = 2;
3910 break;
3911 case TAB (PCREL, LONG):
3912 /* The thing to do here is force it to ABSOLUTE LONG, since
3913 PCREL is really trying to shorten an ABSOLUTE address anyway */
3914 /* JF FOO This code has not been tested */
3915 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3916 0, NO_RELOC);
3917 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3918 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3919 (unsigned) fragP->fr_opcode[0],
3920 (unsigned long) fragP->fr_address);
3921 fragP->fr_opcode[1] &= ~0x3F;
3922 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3923 fragP->fr_fix += 4;
3924 ext = 0;
3925 break;
3926 case TAB (PCLEA, SHORT):
3927 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3928 fragP->fr_offset, 1, NO_RELOC);
3929 fragP->fr_opcode[1] &= ~0x3F;
3930 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3931 ext = 2;
3932 break;
3933 case TAB (PCLEA, LONG):
3934 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3935 fragP->fr_offset, 1, NO_RELOC);
3936 fixP->fx_pcrel_adjust = 2;
3937 /* Already set to mode 7.3; this indicates: PC indirect with
3938 suppressed index, 32-bit displacement. */
3939 *buffer_address++ = 0x01;
3940 *buffer_address++ = 0x70;
3941 fragP->fr_fix += 2;
3942 ext = 4;
3943 break;
3944
3945 case TAB (PCINDEX, BYTE):
3946 disp += 2;
3947 if (!issbyte (disp))
3948 {
3949 as_bad ("displacement doesn't fit in one byte");
3950 disp = 0;
3951 }
3952 assert (fragP->fr_fix >= 2);
3953 buffer_address[-2] &= ~1;
3954 buffer_address[-1] = disp;
3955 ext = 0;
3956 break;
3957 case TAB (PCINDEX, SHORT):
3958 disp += 2;
3959 assert (issword (disp));
3960 assert (fragP->fr_fix >= 2);
3961 buffer_address[-2] |= 0x1;
3962 buffer_address[-1] = 0x20;
3963 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3964 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3965 NO_RELOC);
3966 fixP->fx_pcrel_adjust = 2;
3967 ext = 2;
3968 break;
3969 case TAB (PCINDEX, LONG):
3970 disp += 2;
3971 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3972 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3973 NO_RELOC);
3974 fixP->fx_pcrel_adjust = 2;
3975 assert (fragP->fr_fix >= 2);
3976 buffer_address[-2] |= 0x1;
3977 buffer_address[-1] = 0x30;
3978 ext = 4;
3979 break;
3980 }
3981
3982 if (ext)
3983 {
3984 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3985 fragP->fr_fix += ext;
3986 }
3987 }
3988
3989 #ifndef BFD_ASSEMBLER
3990
3991 void
3992 md_convert_frag (headers, sec, fragP)
3993 object_headers *headers;
3994 segT sec;
3995 fragS *fragP;
3996 {
3997 md_convert_frag_1 (fragP);
3998 }
3999
4000 #else
4001
4002 void
4003 md_convert_frag (abfd, sec, fragP)
4004 bfd *abfd;
4005 segT sec;
4006 fragS *fragP;
4007 {
4008 md_convert_frag_1 (fragP);
4009 }
4010 #endif
4011
4012 /* Force truly undefined symbols to their maximum size, and generally set up
4013 the frag list to be relaxed
4014 */
4015 int
4016 md_estimate_size_before_relax (fragP, segment)
4017 register fragS *fragP;
4018 segT segment;
4019 {
4020 int old_fix;
4021 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4022
4023 old_fix = fragP->fr_fix;
4024
4025 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4026 switch (fragP->fr_subtype)
4027 {
4028
4029 case TAB (ABRANCH, SZ_UNDEF):
4030 {
4031 if ((fragP->fr_symbol != NULL) /* Not absolute */
4032 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4033 {
4034 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4035 break;
4036 }
4037 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4038 {
4039 /* On 68000, or for absolute value, switch to abs long */
4040 /* FIXME, we should check abs val, pick short or long */
4041 if (fragP->fr_opcode[0] == 0x61)
4042 {
4043 fragP->fr_opcode[0] = 0x4E;
4044 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4045 fix_new (fragP, fragP->fr_fix, 4,
4046 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4047 fragP->fr_fix += 4;
4048 frag_wane (fragP);
4049 }
4050 else if (fragP->fr_opcode[0] == 0x60)
4051 {
4052 fragP->fr_opcode[0] = 0x4E;
4053 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4054 fix_new (fragP, fragP->fr_fix, 4,
4055 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4056 fragP->fr_fix += 4;
4057 frag_wane (fragP);
4058 }
4059 else
4060 {
4061 as_warn ("Long branch offset to extern symbol not supported.");
4062 }
4063 }
4064 else
4065 { /* Symbol is still undefined. Make it simple */
4066 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4067 fragP->fr_offset, 1, NO_RELOC);
4068 fragP->fr_fix += 4;
4069 fragP->fr_opcode[1] = (char) 0xff;
4070 frag_wane (fragP);
4071 break;
4072 }
4073
4074 break;
4075 } /* case TAB(ABRANCH,SZ_UNDEF) */
4076
4077 case TAB (FBRANCH, SZ_UNDEF):
4078 {
4079 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4080 {
4081 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4082 fragP->fr_var += 2;
4083 }
4084 else
4085 {
4086 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4087 fragP->fr_offset, 1, NO_RELOC);
4088 fragP->fr_fix += 4;
4089 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4090 frag_wane (fragP);
4091 }
4092 break;
4093 } /* TAB(FBRANCH,SZ_UNDEF) */
4094
4095 case TAB (PCREL, SZ_UNDEF):
4096 {
4097 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4098 || flag_short_refs
4099 || cpu_of_arch (current_architecture) < m68020)
4100 {
4101 fragP->fr_subtype = TAB (PCREL, SHORT);
4102 fragP->fr_var += 2;
4103 }
4104 else
4105 {
4106 fragP->fr_subtype = TAB (PCREL, LONG);
4107 fragP->fr_var += 4;
4108 }
4109 break;
4110 } /* TAB(PCREL,SZ_UNDEF) */
4111
4112 case TAB (BCC68000, SZ_UNDEF):
4113 {
4114 if ((fragP->fr_symbol != NULL)
4115 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4116 {
4117 fragP->fr_subtype = TAB (BCC68000, BYTE);
4118 break;
4119 }
4120 /* only Bcc 68000 instructions can come here */
4121 /* change bcc into b!cc/jmp absl long */
4122 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4123 if (flag_short_refs)
4124 {
4125 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4126 /* JF: these were fr_opcode[2,3] */
4127 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4128 buffer_address[1] = (char) 0xf8;
4129 fragP->fr_fix += 2; /* account for jmp instruction */
4130 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4131 fragP->fr_offset, 0, NO_RELOC);
4132 fragP->fr_fix += 2;
4133 }
4134 else
4135 {
4136 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4137 /* JF: these were fr_opcode[2,3] */
4138 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4139 buffer_address[1] = (char) 0xf9;
4140 fragP->fr_fix += 2; /* account for jmp instruction */
4141 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4142 fragP->fr_offset, 0, NO_RELOC);
4143 fragP->fr_fix += 4;
4144 }
4145 frag_wane (fragP);
4146 break;
4147 } /* case TAB(BCC68000,SZ_UNDEF) */
4148
4149 case TAB (DBCC, SZ_UNDEF):
4150 {
4151 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4152 {
4153 fragP->fr_subtype = TAB (DBCC, SHORT);
4154 fragP->fr_var += 2;
4155 break;
4156 }
4157 /* only DBcc 68000 instructions can come here */
4158 /* change dbcc into dbcc/jmp absl long */
4159 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4160 buffer_address[0] = 0x00; /* branch offset = 4 */
4161 buffer_address[1] = 0x04;
4162 buffer_address[2] = 0x60; /* put in bra pc + ... */
4163
4164 if (flag_short_refs)
4165 {
4166 /* JF: these were fr_opcode[5-7] */
4167 buffer_address[3] = 0x04; /* plus 4 */
4168 buffer_address[4] = 0x4e; /* Put in Jump Word */
4169 buffer_address[5] = (char) 0xf8;
4170 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4171 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4172 fragP->fr_offset, 0, NO_RELOC);
4173 fragP->fr_fix += 2;
4174 }
4175 else
4176 {
4177 /* JF: these were fr_opcode[5-7] */
4178 buffer_address[3] = 0x06; /* Plus 6 */
4179 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4180 buffer_address[5] = (char) 0xf9;
4181 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4182 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4183 fragP->fr_offset, 0, NO_RELOC);
4184 fragP->fr_fix += 4;
4185 }
4186
4187 frag_wane (fragP);
4188 break;
4189 } /* case TAB(DBCC,SZ_UNDEF) */
4190
4191 case TAB (PCLEA, SZ_UNDEF):
4192 {
4193 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4194 || flag_short_refs
4195 || cpu_of_arch (current_architecture) < m68020)
4196 {
4197 fragP->fr_subtype = TAB (PCLEA, SHORT);
4198 fragP->fr_var += 2;
4199 }
4200 else
4201 {
4202 fragP->fr_subtype = TAB (PCLEA, LONG);
4203 fragP->fr_var += 6;
4204 }
4205 break;
4206 } /* TAB(PCLEA,SZ_UNDEF) */
4207
4208 case TAB (PCINDEX, SZ_UNDEF):
4209 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4210 || cpu_of_arch (current_architecture) < m68020)
4211 {
4212 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4213 }
4214 else
4215 {
4216 fragP->fr_subtype = TAB (PCINDEX, LONG);
4217 fragP->fr_var += 4;
4218 }
4219 break;
4220
4221 default:
4222 break;
4223 }
4224
4225 /* now that SZ_UNDEF are taken care of, check others */
4226 switch (fragP->fr_subtype)
4227 {
4228 case TAB (BCC68000, BYTE):
4229 case TAB (ABRANCH, BYTE):
4230 /* We can't do a short jump to the next instruction, so in that
4231 case we force word mode. At this point S_GET_VALUE should
4232 return the offset of the symbol within its frag. If the
4233 symbol is at the start of a frag, and it is the next frag
4234 with any data in it (usually this is just the next frag, but
4235 assembler listings may introduce empty frags), we must use
4236 word mode. */
4237 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4238 {
4239 fragS *l;
4240
4241 for (l = fragP->fr_next;
4242 l != fragP->fr_symbol->sy_frag;
4243 l = l->fr_next)
4244 if (l->fr_fix + l->fr_var != 0)
4245 break;
4246 if (l == fragP->fr_symbol->sy_frag)
4247 {
4248 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4249 fragP->fr_var += 2;
4250 }
4251 }
4252 break;
4253 default:
4254 break;
4255 }
4256 return fragP->fr_var + fragP->fr_fix - old_fix;
4257 }
4258
4259 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4260 /* the bit-field entries in the relocation_info struct plays hell
4261 with the byte-order problems of cross-assembly. So as a hack,
4262 I added this mach. dependent ri twiddler. Ugly, but it gets
4263 you there. -KWK */
4264 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4265 are symbolnum, most sig. byte first. Last byte is broken up with
4266 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4267 nibble as nuthin. (on Sun 3 at least) */
4268 /* Translate the internal relocation information into target-specific
4269 format. */
4270 #ifdef comment
4271 void
4272 md_ri_to_chars (the_bytes, ri)
4273 char *the_bytes;
4274 struct reloc_info_generic *ri;
4275 {
4276 /* this is easy */
4277 md_number_to_chars (the_bytes, ri->r_address, 4);
4278 /* now the fun stuff */
4279 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4280 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4281 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4282 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4283 ((ri->r_extern << 4) & 0x10));
4284 }
4285
4286 #endif /* comment */
4287
4288 #ifndef BFD_ASSEMBLER
4289 void
4290 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4291 char *where;
4292 fixS *fixP;
4293 relax_addressT segment_address_in_file;
4294 {
4295 /*
4296 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4297 * Out: GNU LD relocation length code: 0, 1, or 2.
4298 */
4299
4300 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4301 long r_symbolnum;
4302
4303 know (fixP->fx_addsy != NULL);
4304
4305 md_number_to_chars (where,
4306 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4307 4);
4308
4309 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4310 ? S_GET_TYPE (fixP->fx_addsy)
4311 : fixP->fx_addsy->sy_number);
4312
4313 where[4] = (r_symbolnum >> 16) & 0x0ff;
4314 where[5] = (r_symbolnum >> 8) & 0x0ff;
4315 where[6] = r_symbolnum & 0x0ff;
4316 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4317 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4318 }
4319 #endif
4320
4321 #endif /* OBJ_AOUT or OBJ_BOUT */
4322
4323 #ifndef WORKING_DOT_WORD
4324 CONST int md_short_jump_size = 4;
4325 CONST int md_long_jump_size = 6;
4326
4327 void
4328 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4329 char *ptr;
4330 addressT from_addr, to_addr;
4331 fragS *frag;
4332 symbolS *to_symbol;
4333 {
4334 valueT offset;
4335
4336 offset = to_addr - (from_addr + 2);
4337
4338 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4339 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4340 }
4341
4342 void
4343 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4344 char *ptr;
4345 addressT from_addr, to_addr;
4346 fragS *frag;
4347 symbolS *to_symbol;
4348 {
4349 valueT offset;
4350
4351 if (cpu_of_arch (current_architecture) < m68020)
4352 {
4353 offset = to_addr - S_GET_VALUE (to_symbol);
4354 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4355 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4356 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4357 0, NO_RELOC);
4358 }
4359 else
4360 {
4361 offset = to_addr - (from_addr + 2);
4362 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4363 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4364 }
4365 }
4366
4367 #endif
4368
4369 /* Different values of OK tell what its OK to return. Things that
4370 aren't OK are an error (what a shock, no?)
4371
4372 0: Everything is OK
4373 10: Absolute 1:8 only
4374 20: Absolute 0:7 only
4375 30: absolute 0:15 only
4376 40: Absolute 0:31 only
4377 50: absolute 0:127 only
4378 55: absolute -64:63 only
4379 60: absolute -128:127 only
4380 70: absolute 0:4095 only
4381 80: No bignums
4382
4383 */
4384
4385 static int
4386 get_num (exp, ok)
4387 struct m68k_exp *exp;
4388 int ok;
4389 {
4390 if (exp->exp.X_op == O_absent)
4391 {
4392 /* Do the same thing the VAX asm does */
4393 op (exp) = O_constant;
4394 adds (exp) = 0;
4395 subs (exp) = 0;
4396 offs (exp) = 0;
4397 if (ok == 10)
4398 {
4399 as_warn ("expression out of range: defaulting to 1");
4400 offs (exp) = 1;
4401 }
4402 }
4403 else if (exp->exp.X_op == O_constant)
4404 {
4405 switch (ok)
4406 {
4407 case 10:
4408 if (offs (exp) < 1 || offs (exp) > 8)
4409 {
4410 as_warn ("expression out of range: defaulting to 1");
4411 offs (exp) = 1;
4412 }
4413 break;
4414 case 20:
4415 if (offs (exp) < 0 || offs (exp) > 7)
4416 goto outrange;
4417 break;
4418 case 30:
4419 if (offs (exp) < 0 || offs (exp) > 15)
4420 goto outrange;
4421 break;
4422 case 40:
4423 if (offs (exp) < 0 || offs (exp) > 32)
4424 goto outrange;
4425 break;
4426 case 50:
4427 if (offs (exp) < 0 || offs (exp) > 127)
4428 goto outrange;
4429 break;
4430 case 55:
4431 if (offs (exp) < -64 || offs (exp) > 63)
4432 goto outrange;
4433 break;
4434 case 60:
4435 if (offs (exp) < -128 || offs (exp) > 127)
4436 goto outrange;
4437 break;
4438 case 70:
4439 if (offs (exp) < 0 || offs (exp) > 4095)
4440 {
4441 outrange:
4442 as_warn ("expression out of range: defaulting to 0");
4443 offs (exp) = 0;
4444 }
4445 break;
4446 default:
4447 break;
4448 }
4449 }
4450 else if (exp->exp.X_op == O_big)
4451 {
4452 if (offs (exp) <= 0 /* flonum */
4453 && (ok == 80 /* no bignums */
4454 || (ok > 10 /* small-int ranges including 0 ok */
4455 /* If we have a flonum zero, a zero integer should
4456 do as well (e.g., in moveq). */
4457 && generic_floating_point_number.exponent == 0
4458 && generic_floating_point_number.low[0] == 0)))
4459 {
4460 /* HACK! Turn it into a long */
4461 LITTLENUM_TYPE words[6];
4462
4463 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4464 op (exp) = O_constant;
4465 adds (exp) = 0;
4466 subs (exp) = 0;
4467 offs (exp) = words[1] | (words[0] << 16);
4468 }
4469 else if (ok != 0)
4470 {
4471 op (exp) = O_constant;
4472 adds (exp) = 0;
4473 subs (exp) = 0;
4474 offs (exp) = (ok == 10) ? 1 : 0;
4475 as_warn ("Can't deal with expression; defaulting to %ld",
4476 offs (exp));
4477 }
4478 }
4479 else
4480 {
4481 if (ok >= 10 && ok <= 70)
4482 {
4483 op (exp) = O_constant;
4484 adds (exp) = 0;
4485 subs (exp) = 0;
4486 offs (exp) = (ok == 10) ? 1 : 0;
4487 as_warn ("Can't deal with expression; defaulting to %ld",
4488 offs (exp));
4489 }
4490 }
4491
4492 if (exp->size != SIZE_UNSPEC)
4493 {
4494 switch (exp->size)
4495 {
4496 case SIZE_UNSPEC:
4497 case SIZE_LONG:
4498 break;
4499 case SIZE_BYTE:
4500 if (!isbyte (offs (exp)))
4501 as_warn ("expression doesn't fit in BYTE");
4502 break;
4503 case SIZE_WORD:
4504 if (!isword (offs (exp)))
4505 as_warn ("expression doesn't fit in WORD");
4506 break;
4507 }
4508 }
4509
4510 return offs (exp);
4511 }
4512
4513 /* These are the back-ends for the various machine dependent pseudo-ops. */
4514 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4515
4516 static void
4517 s_data1 (ignore)
4518 int ignore;
4519 {
4520 subseg_set (data_section, 1);
4521 demand_empty_rest_of_line ();
4522 }
4523
4524 static void
4525 s_data2 (ignore)
4526 int ignore;
4527 {
4528 subseg_set (data_section, 2);
4529 demand_empty_rest_of_line ();
4530 }
4531
4532 static void
4533 s_bss (ignore)
4534 int ignore;
4535 {
4536 /* We don't support putting frags in the BSS segment, we fake it
4537 by marking in_bss, then looking at s_skip for clues. */
4538
4539 subseg_set (bss_section, 0);
4540 demand_empty_rest_of_line ();
4541 }
4542
4543 static void
4544 s_even (ignore)
4545 int ignore;
4546 {
4547 register int temp;
4548 register long temp_fill;
4549
4550 temp = 1; /* JF should be 2? */
4551 temp_fill = get_absolute_expression ();
4552 if (!need_pass_2) /* Never make frag if expect extra pass. */
4553 frag_align (temp, (int) temp_fill);
4554 demand_empty_rest_of_line ();
4555 }
4556
4557 static void
4558 s_proc (ignore)
4559 int ignore;
4560 {
4561 demand_empty_rest_of_line ();
4562 }
4563 \f
4564 /* Pseudo-ops handled for MRI compatibility. */
4565
4566 /* Handle an MRI style chip specification. */
4567
4568 static void
4569 mri_chip ()
4570 {
4571 char *s;
4572 char c;
4573 int i;
4574
4575 s = input_line_pointer;
4576 c = get_symbol_end ();
4577 for (i = 0; i < n_archs; i++)
4578 if (strcasecmp (s, archs[i].name) == 0)
4579 break;
4580 if (i >= n_archs)
4581 {
4582 as_bad ("%s: unrecognized processor name", s);
4583 *input_line_pointer = c;
4584 ignore_rest_of_line ();
4585 return;
4586 }
4587 *input_line_pointer = c;
4588
4589 if (*input_line_pointer == '/')
4590 current_architecture = 0;
4591 else
4592 current_architecture &= m68881 | m68851;
4593 current_architecture |= archs[i].arch;
4594
4595 while (*input_line_pointer == '/')
4596 {
4597 ++input_line_pointer;
4598 s = input_line_pointer;
4599 c = get_symbol_end ();
4600 if (strcmp (s, "68881") == 0)
4601 current_architecture |= m68881;
4602 else if (strcmp (s, "68851") == 0)
4603 current_architecture |= m68851;
4604 *input_line_pointer = c;
4605 }
4606 }
4607
4608 /* The MRI CHIP pseudo-op. */
4609
4610 static void
4611 s_chip (ignore)
4612 int ignore;
4613 {
4614 char *stop = NULL;
4615 char stopc;
4616
4617 if (flag_mri)
4618 stop = mri_comment_field (&stopc);
4619 mri_chip ();
4620 if (flag_mri)
4621 mri_comment_end (stop, stopc);
4622 demand_empty_rest_of_line ();
4623 }
4624
4625 /* The MRI FOPT pseudo-op. */
4626
4627 static void
4628 s_fopt (ignore)
4629 int ignore;
4630 {
4631 SKIP_WHITESPACE ();
4632
4633 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4634 {
4635 int temp;
4636
4637 input_line_pointer += 3;
4638 temp = get_absolute_expression ();
4639 if (temp < 0 || temp > 7)
4640 as_bad ("bad coprocessor id");
4641 else
4642 m68k_float_copnum = COP0 + temp;
4643 }
4644 else
4645 {
4646 as_bad ("unrecognized fopt option");
4647 ignore_rest_of_line ();
4648 return;
4649 }
4650
4651 demand_empty_rest_of_line ();
4652 }
4653
4654 /* The structure used to handle the MRI OPT pseudo-op. */
4655
4656 struct opt_action
4657 {
4658 /* The name of the option. */
4659 const char *name;
4660
4661 /* If this is not NULL, just call this function. The first argument
4662 is the ARG field of this structure, the second argument is
4663 whether the option was negated. */
4664 void (*pfn) PARAMS ((int arg, int on));
4665
4666 /* If this is not NULL, and the PFN field is NULL, set the variable
4667 this points to. Set it to the ARG field if the option was not
4668 negated, and the NOTARG field otherwise. */
4669 int *pvar;
4670
4671 /* The value to pass to PFN or to assign to *PVAR. */
4672 int arg;
4673
4674 /* The value to assign to *PVAR if the option is negated. If PFN is
4675 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4676 the option may not be negated. */
4677 int notarg;
4678 };
4679
4680 /* The table used to handle the MRI OPT pseudo-op. */
4681
4682 static void skip_to_comma PARAMS ((int, int));
4683 static void opt_nest PARAMS ((int, int));
4684 static void opt_chip PARAMS ((int, int));
4685 static void opt_list PARAMS ((int, int));
4686 static void opt_list_symbols PARAMS ((int, int));
4687
4688 static const struct opt_action opt_table[] =
4689 {
4690 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4691
4692 /* We do relaxing, so there is little use for these options. */
4693 { "b", 0, 0, 0, 0 },
4694 { "brs", 0, 0, 0, 0 },
4695 { "brb", 0, 0, 0, 0 },
4696 { "brl", 0, 0, 0, 0 },
4697 { "brw", 0, 0, 0, 0 },
4698
4699 { "c", 0, 0, 0, 0 },
4700 { "cex", 0, 0, 0, 0 },
4701 { "case", 0, &symbols_case_sensitive, 1, 0 },
4702 { "cl", 0, 0, 0, 0 },
4703 { "cre", 0, 0, 0, 0 },
4704 { "d", 0, &flag_keep_locals, 1, 0 },
4705 { "e", 0, 0, 0, 0 },
4706 { "f", 0, &flag_short_refs, 1, 0 },
4707 { "frs", 0, &flag_short_refs, 1, 0 },
4708 { "frl", 0, &flag_short_refs, 0, 1 },
4709 { "g", 0, 0, 0, 0 },
4710 { "i", 0, 0, 0, 0 },
4711 { "m", 0, 0, 0, 0 },
4712 { "mex", 0, 0, 0, 0 },
4713 { "mc", 0, 0, 0, 0 },
4714 { "md", 0, 0, 0, 0 },
4715 { "nest", opt_nest, 0, 0, 0 },
4716 { "next", skip_to_comma, 0, 0, 0 },
4717 { "o", 0, 0, 0, 0 },
4718 { "old", 0, 0, 0, 0 },
4719 { "op", skip_to_comma, 0, 0, 0 },
4720 { "pco", 0, 0, 0, 0 },
4721 { "p", opt_chip, 0, 0, 0 },
4722 { "pcr", 0, 0, 0, 0 },
4723 { "pcs", 0, 0, 0, 0 },
4724 { "r", 0, 0, 0, 0 },
4725 { "quick", 0, &m68k_quick, 1, 0 },
4726 { "rel32", 0, &m68k_rel32, 1, 0 },
4727 { "s", opt_list, 0, 0, 0 },
4728 { "t", opt_list_symbols, 0, 0, 0 },
4729 { "w", 0, &flag_no_warnings, 0, 1 },
4730 { "x", 0, 0, 0, 0 }
4731 };
4732
4733 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4734
4735 /* The MRI OPT pseudo-op. */
4736
4737 static void
4738 s_opt (ignore)
4739 int ignore;
4740 {
4741 do
4742 {
4743 int t;
4744 char *s;
4745 char c;
4746 int i;
4747 const struct opt_action *o;
4748
4749 SKIP_WHITESPACE ();
4750
4751 t = 1;
4752 if (*input_line_pointer == '-')
4753 {
4754 ++input_line_pointer;
4755 t = 0;
4756 }
4757 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4758 {
4759 input_line_pointer += 2;
4760 t = 0;
4761 }
4762
4763 s = input_line_pointer;
4764 c = get_symbol_end ();
4765
4766 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4767 {
4768 if (strcasecmp (s, o->name) == 0)
4769 {
4770 if (o->pfn)
4771 {
4772 /* Restore input_line_pointer now in case the option
4773 takes arguments. */
4774 *input_line_pointer = c;
4775 (*o->pfn) (o->arg, t);
4776 }
4777 else if (o->pvar != NULL)
4778 {
4779 if (! t && o->arg == o->notarg)
4780 as_bad ("option `%s' may not be negated", s);
4781 *input_line_pointer = c;
4782 *o->pvar = t ? o->arg : o->notarg;
4783 }
4784 else
4785 *input_line_pointer = c;
4786 break;
4787 }
4788 }
4789 if (i >= OPTCOUNT)
4790 {
4791 as_bad ("option `%s' not recognized", s);
4792 *input_line_pointer = c;
4793 }
4794 }
4795 while (*input_line_pointer++ == ',');
4796
4797 /* Move back to terminating character. */
4798 --input_line_pointer;
4799 demand_empty_rest_of_line ();
4800 }
4801
4802 /* Skip ahead to a comma. This is used for OPT options which we do
4803 not suppor tand which take arguments. */
4804
4805 static void
4806 skip_to_comma (arg, on)
4807 int arg;
4808 int on;
4809 {
4810 while (*input_line_pointer != ','
4811 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4812 ++input_line_pointer;
4813 }
4814
4815 /* Handle the OPT NEST=depth option. */
4816
4817 static void
4818 opt_nest (arg, on)
4819 int arg;
4820 int on;
4821 {
4822 if (*input_line_pointer != '=')
4823 {
4824 as_bad ("bad format of OPT NEST=depth");
4825 return;
4826 }
4827
4828 ++input_line_pointer;
4829 max_macro_nest = get_absolute_expression ();
4830 }
4831
4832 /* Handle the OPT P=chip option. */
4833
4834 static void
4835 opt_chip (arg, on)
4836 int arg;
4837 int on;
4838 {
4839 if (*input_line_pointer != '=')
4840 {
4841 /* This is just OPT P, which we do not support. */
4842 return;
4843 }
4844
4845 ++input_line_pointer;
4846 mri_chip ();
4847 }
4848
4849 /* Handle the OPT S option. */
4850
4851 static void
4852 opt_list (arg, on)
4853 int arg;
4854 int on;
4855 {
4856 listing_list (on);
4857 }
4858
4859 /* Handle the OPT T option. */
4860
4861 static void
4862 opt_list_symbols (arg, on)
4863 int arg;
4864 int on;
4865 {
4866 if (on)
4867 listing |= LISTING_SYMBOLS;
4868 else
4869 listing &=~ LISTING_SYMBOLS;
4870 }
4871
4872 /* Handle the MRI REG pseudo-op. */
4873
4874 static void
4875 s_reg (ignore)
4876 int ignore;
4877 {
4878 char *s;
4879 int c;
4880 struct m68k_op rop;
4881 unsigned long mask;
4882 char *stop = NULL;
4883 char stopc;
4884
4885 if (line_label == NULL)
4886 {
4887 as_bad ("missing label");
4888 ignore_rest_of_line ();
4889 return;
4890 }
4891
4892 if (flag_mri)
4893 stop = mri_comment_field (&stopc);
4894
4895 SKIP_WHITESPACE ();
4896
4897 s = input_line_pointer;
4898 while (isalnum ((unsigned char) *input_line_pointer)
4899 #ifdef REGISTER_PREFIX
4900 || *input_line_pointer == REGISTER_PREFIX
4901 #endif
4902 || *input_line_pointer == '/'
4903 || *input_line_pointer == '-')
4904 ++input_line_pointer;
4905 c = *input_line_pointer;
4906 *input_line_pointer = '\0';
4907
4908 if (m68k_ip_op (s, &rop) != 0)
4909 {
4910 if (rop.error == NULL)
4911 as_bad ("bad register list");
4912 else
4913 as_bad ("bad register list: %s", rop.error);
4914 *input_line_pointer = c;
4915 ignore_rest_of_line ();
4916 return;
4917 }
4918
4919 *input_line_pointer = c;
4920
4921 if (rop.mode == REGLST)
4922 mask = rop.mask;
4923 else if (rop.mode == DREG)
4924 mask = 1 << (rop.reg - DATA0);
4925 else if (rop.mode == AREG)
4926 mask = 1 << (rop.reg - ADDR0 + 8);
4927 else if (rop.mode == FPREG)
4928 mask = 1 << (rop.reg - FP0 + 16);
4929 else if (rop.mode == CONTROL
4930 && rop.reg == FPI)
4931 mask = 1 << 24;
4932 else if (rop.mode == CONTROL
4933 && rop.reg == FPS)
4934 mask = 1 << 25;
4935 else if (rop.mode == CONTROL
4936 && rop.reg == FPC)
4937 mask = 1 << 26;
4938 else
4939 {
4940 as_bad ("bad register list");
4941 ignore_rest_of_line ();
4942 return;
4943 }
4944
4945 S_SET_SEGMENT (line_label, absolute_section);
4946 S_SET_VALUE (line_label, mask);
4947 line_label->sy_frag = &zero_address_frag;
4948
4949 if (flag_mri)
4950 mri_comment_end (stop, stopc);
4951
4952 demand_empty_rest_of_line ();
4953 }
4954
4955 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4956
4957 struct save_opts
4958 {
4959 struct save_opts *next;
4960 int abspcadd;
4961 int symbols_case_sensitive;
4962 int keep_locals;
4963 int short_refs;
4964 int architecture;
4965 int quick;
4966 int rel32;
4967 int listing;
4968 int no_warnings;
4969 /* FIXME: We don't save OPT S. */
4970 };
4971
4972 /* This variable holds the stack of saved options. */
4973
4974 static struct save_opts *save_stack;
4975
4976 /* The MRI SAVE pseudo-op. */
4977
4978 static void
4979 s_save (ignore)
4980 int ignore;
4981 {
4982 struct save_opts *s;
4983
4984 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4985 s->abspcadd = m68k_abspcadd;
4986 s->symbols_case_sensitive = symbols_case_sensitive;
4987 s->keep_locals = flag_keep_locals;
4988 s->short_refs = flag_short_refs;
4989 s->architecture = current_architecture;
4990 s->quick = m68k_quick;
4991 s->rel32 = m68k_rel32;
4992 s->listing = listing;
4993 s->no_warnings = flag_no_warnings;
4994
4995 s->next = save_stack;
4996 save_stack = s;
4997
4998 demand_empty_rest_of_line ();
4999 }
5000
5001 /* The MRI RESTORE pseudo-op. */
5002
5003 static void
5004 s_restore (ignore)
5005 int ignore;
5006 {
5007 struct save_opts *s;
5008
5009 if (save_stack == NULL)
5010 {
5011 as_bad ("restore without save");
5012 ignore_rest_of_line ();
5013 return;
5014 }
5015
5016 s = save_stack;
5017 save_stack = s->next;
5018
5019 m68k_abspcadd = s->abspcadd;
5020 symbols_case_sensitive = s->symbols_case_sensitive;
5021 flag_keep_locals = s->keep_locals;
5022 flag_short_refs = s->short_refs;
5023 current_architecture = s->architecture;
5024 m68k_quick = s->quick;
5025 m68k_rel32 = s->rel32;
5026 listing = s->listing;
5027 flag_no_warnings = s->no_warnings;
5028
5029 free (s);
5030
5031 demand_empty_rest_of_line ();
5032 }
5033
5034 /* Types of MRI structured control directives. */
5035
5036 enum mri_control_type
5037 {
5038 mri_for,
5039 mri_if,
5040 mri_repeat,
5041 mri_while
5042 };
5043
5044 /* This structure is used to stack the MRI structured control
5045 directives. */
5046
5047 struct mri_control_info
5048 {
5049 /* The directive within which this one is enclosed. */
5050 struct mri_control_info *outer;
5051
5052 /* The type of directive. */
5053 enum mri_control_type type;
5054
5055 /* Whether an ELSE has been in an IF. */
5056 int else_seen;
5057
5058 /* The add or sub statement at the end of a FOR. */
5059 char *incr;
5060
5061 /* The label of the top of a FOR or REPEAT loop. */
5062 char *top;
5063
5064 /* The label to jump to for the next iteration, or the else
5065 expression of a conditional. */
5066 char *next;
5067
5068 /* The label to jump to to break out of the loop, or the label past
5069 the end of a conditional. */
5070 char *bottom;
5071 };
5072
5073 /* The stack of MRI structured control directives. */
5074
5075 static struct mri_control_info *mri_control_stack;
5076
5077 /* The current MRI structured control directive index number, used to
5078 generate label names. */
5079
5080 static int mri_control_index;
5081
5082 /* Some function prototypes. */
5083
5084 static char *mri_control_label PARAMS ((void));
5085 static struct mri_control_info *push_mri_control
5086 PARAMS ((enum mri_control_type));
5087 static void pop_mri_control PARAMS ((void));
5088 static int parse_mri_condition PARAMS ((int *));
5089 static int parse_mri_control_operand
5090 PARAMS ((int *, char **, char **, char **, char **));
5091 static int swap_mri_condition PARAMS ((int));
5092 static int reverse_mri_condition PARAMS ((int));
5093 static void build_mri_control_operand
5094 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5095 const char *, int));
5096 static void parse_mri_control_expression
5097 PARAMS ((char *, int, const char *, const char *, int));
5098
5099 /* Generate a new MRI label structured control directive label name. */
5100
5101 static char *
5102 mri_control_label ()
5103 {
5104 char *n;
5105
5106 n = (char *) xmalloc (20);
5107 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5108 ++mri_control_index;
5109 return n;
5110 }
5111
5112 /* Create a new MRI structured control directive. */
5113
5114 static struct mri_control_info *
5115 push_mri_control (type)
5116 enum mri_control_type type;
5117 {
5118 struct mri_control_info *n;
5119
5120 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5121
5122 n->type = type;
5123 n->else_seen = 0;
5124 if (type == mri_if || type == mri_while)
5125 n->top = NULL;
5126 else
5127 n->top = mri_control_label ();
5128 n->next = mri_control_label ();
5129 n->bottom = mri_control_label ();
5130
5131 n->outer = mri_control_stack;
5132 mri_control_stack = n;
5133
5134 return n;
5135 }
5136
5137 /* Pop off the stack of MRI structured control directives. */
5138
5139 static void
5140 pop_mri_control ()
5141 {
5142 struct mri_control_info *n;
5143
5144 n = mri_control_stack;
5145 mri_control_stack = n->outer;
5146 if (n->top != NULL)
5147 free (n->top);
5148 free (n->next);
5149 free (n->bottom);
5150 free (n);
5151 }
5152
5153 /* Recognize a condition code in an MRI structured control expression. */
5154
5155 static int
5156 parse_mri_condition (pcc)
5157 int *pcc;
5158 {
5159 char c1, c2;
5160
5161 know (*input_line_pointer == '<');
5162
5163 ++input_line_pointer;
5164 c1 = *input_line_pointer++;
5165 c2 = *input_line_pointer++;
5166
5167 if (*input_line_pointer != '>')
5168 {
5169 as_bad ("syntax error in structured control directive");
5170 return 0;
5171 }
5172
5173 ++input_line_pointer;
5174 SKIP_WHITESPACE ();
5175
5176 if (isupper (c1))
5177 c1 = tolower (c1);
5178 if (isupper (c2))
5179 c2 = tolower (c2);
5180
5181 *pcc = (c1 << 8) | c2;
5182
5183 return 1;
5184 }
5185
5186 /* Parse a single operand in an MRI structured control expression. */
5187
5188 static int
5189 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5190 int *pcc;
5191 char **leftstart;
5192 char **leftstop;
5193 char **rightstart;
5194 char **rightstop;
5195 {
5196 char *s;
5197
5198 SKIP_WHITESPACE ();
5199
5200 *pcc = -1;
5201 *leftstart = NULL;
5202 *leftstop = NULL;
5203 *rightstart = NULL;
5204 *rightstop = NULL;
5205
5206 if (*input_line_pointer == '<')
5207 {
5208 /* It's just a condition code. */
5209 return parse_mri_condition (pcc);
5210 }
5211
5212 /* Look ahead for the condition code. */
5213 for (s = input_line_pointer; *s != '\0'; ++s)
5214 {
5215 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5216 break;
5217 }
5218 if (*s == '\0')
5219 {
5220 as_bad ("missing condition code in structured control directive");
5221 return 0;
5222 }
5223
5224 *leftstart = input_line_pointer;
5225 *leftstop = s;
5226 if (*leftstop > *leftstart
5227 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5228 --*leftstop;
5229
5230 input_line_pointer = s;
5231 if (! parse_mri_condition (pcc))
5232 return 0;
5233
5234 /* Look ahead for AND or OR or end of line. */
5235 for (s = input_line_pointer; *s != '\0'; ++s)
5236 {
5237 if ((strncasecmp (s, "AND", 3) == 0
5238 && (s[3] == '.' || ! is_part_of_name (s[3])))
5239 || (strncasecmp (s, "OR", 2) == 0
5240 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5241 break;
5242 }
5243
5244 *rightstart = input_line_pointer;
5245 *rightstop = s;
5246 if (*rightstop > *rightstart
5247 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5248 --*rightstop;
5249
5250 input_line_pointer = s;
5251
5252 return 1;
5253 }
5254
5255 #define MCC(b1, b2) (((b1) << 8) | (b2))
5256
5257 /* Swap the sense of a condition. This changes the condition so that
5258 it generates the same result when the operands are swapped. */
5259
5260 static int
5261 swap_mri_condition (cc)
5262 int cc;
5263 {
5264 switch (cc)
5265 {
5266 case MCC ('h', 'i'): return MCC ('c', 's');
5267 case MCC ('l', 's'): return MCC ('c', 'c');
5268 case MCC ('c', 'c'): return MCC ('l', 's');
5269 case MCC ('c', 's'): return MCC ('h', 'i');
5270 case MCC ('p', 'l'): return MCC ('m', 'i');
5271 case MCC ('m', 'i'): return MCC ('p', 'l');
5272 case MCC ('g', 'e'): return MCC ('l', 'e');
5273 case MCC ('l', 't'): return MCC ('g', 't');
5274 case MCC ('g', 't'): return MCC ('l', 't');
5275 case MCC ('l', 'e'): return MCC ('g', 'e');
5276 }
5277 return cc;
5278 }
5279
5280 /* Reverse the sense of a condition. */
5281
5282 static int
5283 reverse_mri_condition (cc)
5284 int cc;
5285 {
5286 switch (cc)
5287 {
5288 case MCC ('h', 'i'): return MCC ('l', 's');
5289 case MCC ('l', 's'): return MCC ('h', 'i');
5290 case MCC ('c', 'c'): return MCC ('c', 's');
5291 case MCC ('c', 's'): return MCC ('c', 'c');
5292 case MCC ('n', 'e'): return MCC ('e', 'q');
5293 case MCC ('e', 'q'): return MCC ('n', 'e');
5294 case MCC ('v', 'c'): return MCC ('v', 's');
5295 case MCC ('v', 's'): return MCC ('v', 'c');
5296 case MCC ('p', 'l'): return MCC ('m', 'i');
5297 case MCC ('m', 'i'): return MCC ('p', 'l');
5298 case MCC ('g', 'e'): return MCC ('l', 't');
5299 case MCC ('l', 't'): return MCC ('g', 'e');
5300 case MCC ('g', 't'): return MCC ('l', 'e');
5301 case MCC ('l', 'e'): return MCC ('g', 't');
5302 }
5303 return cc;
5304 }
5305
5306 /* Build an MRI structured control expression. This generates test
5307 and branch instructions. It goes to TRUELAB if the condition is
5308 true, and to FALSELAB if the condition is false. Exactly one of
5309 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5310 is the size qualifier for the expression. EXTENT is the size to
5311 use for the branch. */
5312
5313 static void
5314 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5315 rightstop, truelab, falselab, extent)
5316 int qual;
5317 int cc;
5318 char *leftstart;
5319 char *leftstop;
5320 char *rightstart;
5321 char *rightstop;
5322 const char *truelab;
5323 const char *falselab;
5324 int extent;
5325 {
5326 char *buf;
5327 char *s;
5328
5329 if (leftstart != NULL)
5330 {
5331 struct m68k_op leftop, rightop;
5332 char c;
5333
5334 /* Swap the compare operands, if necessary, to produce a legal
5335 m68k compare instruction. Comparing a register operand with
5336 a non-register operand requires the register to be on the
5337 right (cmp, cmpa). Comparing an immediate value with
5338 anything requires the immediate value to be on the left
5339 (cmpi). */
5340
5341 c = *leftstop;
5342 *leftstop = '\0';
5343 (void) m68k_ip_op (leftstart, &leftop);
5344 *leftstop = c;
5345
5346 c = *rightstop;
5347 *rightstop = '\0';
5348 (void) m68k_ip_op (rightstart, &rightop);
5349 *rightstop = c;
5350
5351 if (rightop.mode == IMMED
5352 || ((leftop.mode == DREG || leftop.mode == AREG)
5353 && (rightop.mode != DREG && rightop.mode != AREG)))
5354 {
5355 char *temp;
5356
5357 cc = swap_mri_condition (cc);
5358 temp = leftstart;
5359 leftstart = rightstart;
5360 rightstart = temp;
5361 temp = leftstop;
5362 leftstop = rightstop;
5363 rightstop = temp;
5364 }
5365 }
5366
5367 if (truelab == NULL)
5368 {
5369 cc = reverse_mri_condition (cc);
5370 truelab = falselab;
5371 }
5372
5373 if (leftstart != NULL)
5374 {
5375 buf = (char *) xmalloc (20
5376 + (leftstop - leftstart)
5377 + (rightstop - rightstart));
5378 s = buf;
5379 *s++ = 'c';
5380 *s++ = 'm';
5381 *s++ = 'p';
5382 if (qual != '\0')
5383 *s++ = qual;
5384 *s++ = ' ';
5385 memcpy (s, leftstart, leftstop - leftstart);
5386 s += leftstop - leftstart;
5387 *s++ = ',';
5388 memcpy (s, rightstart, rightstop - rightstart);
5389 s += rightstop - rightstart;
5390 *s = '\0';
5391 md_assemble (buf);
5392 free (buf);
5393 }
5394
5395 buf = (char *) xmalloc (20 + strlen (truelab));
5396 s = buf;
5397 *s++ = 'b';
5398 *s++ = cc >> 8;
5399 *s++ = cc & 0xff;
5400 if (extent != '\0')
5401 *s++ = extent;
5402 *s++ = ' ';
5403 strcpy (s, truelab);
5404 md_assemble (buf);
5405 free (buf);
5406 }
5407
5408 /* Parse an MRI structured control expression. This generates test
5409 and branch instructions. STOP is where the expression ends. It
5410 goes to TRUELAB if the condition is true, and to FALSELAB if the
5411 condition is false. Exactly one of TRUELAB and FALSELAB will be
5412 NULL, meaning to fall through. QUAL is the size qualifier for the
5413 expression. EXTENT is the size to use for the branch. */
5414
5415 static void
5416 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5417 char *stop;
5418 int qual;
5419 const char *truelab;
5420 const char *falselab;
5421 int extent;
5422 {
5423 int c;
5424 int cc;
5425 char *leftstart;
5426 char *leftstop;
5427 char *rightstart;
5428 char *rightstop;
5429
5430 c = *stop;
5431 *stop = '\0';
5432
5433 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5434 &rightstart, &rightstop))
5435 {
5436 *stop = c;
5437 return;
5438 }
5439
5440 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5441 {
5442 const char *flab;
5443
5444 if (falselab != NULL)
5445 flab = falselab;
5446 else
5447 flab = mri_control_label ();
5448
5449 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5450 rightstop, (const char *) NULL, flab, extent);
5451
5452 input_line_pointer += 3;
5453 if (*input_line_pointer != '.'
5454 || input_line_pointer[1] == '\0')
5455 qual = '\0';
5456 else
5457 {
5458 qual = input_line_pointer[1];
5459 input_line_pointer += 2;
5460 }
5461
5462 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5463 &rightstart, &rightstop))
5464 {
5465 *stop = c;
5466 return;
5467 }
5468
5469 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5470 rightstop, truelab, falselab, extent);
5471
5472 if (falselab == NULL)
5473 colon (flab);
5474 }
5475 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5476 {
5477 const char *tlab;
5478
5479 if (truelab != NULL)
5480 tlab = truelab;
5481 else
5482 tlab = mri_control_label ();
5483
5484 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5485 rightstop, tlab, (const char *) NULL, extent);
5486
5487 input_line_pointer += 2;
5488 if (*input_line_pointer != '.'
5489 || input_line_pointer[1] == '\0')
5490 qual = '\0';
5491 else
5492 {
5493 qual = input_line_pointer[1];
5494 input_line_pointer += 2;
5495 }
5496
5497 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5498 &rightstart, &rightstop))
5499 {
5500 *stop = c;
5501 return;
5502 }
5503
5504 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5505 rightstop, truelab, falselab, extent);
5506
5507 if (truelab == NULL)
5508 colon (tlab);
5509 }
5510 else
5511 {
5512 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5513 rightstop, truelab, falselab, extent);
5514 }
5515
5516 *stop = c;
5517 if (input_line_pointer != stop)
5518 as_bad ("syntax error in structured control directive");
5519 }
5520
5521 /* Handle the MRI IF pseudo-op. This may be a structured control
5522 directive, or it may be a regular assembler conditional, depending
5523 on its operands. */
5524
5525 static void
5526 s_mri_if (qual)
5527 int qual;
5528 {
5529 char *s;
5530 int c;
5531 struct mri_control_info *n;
5532
5533 /* A structured control directive must end with THEN with an
5534 optional qualifier. */
5535 s = input_line_pointer;
5536 while (! is_end_of_line[(unsigned char) *s]
5537 && (! flag_mri || *s != '*'))
5538 ++s;
5539 --s;
5540 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5541 --s;
5542
5543 if (s - input_line_pointer > 1
5544 && s[-1] == '.')
5545 s -= 2;
5546
5547 if (s - input_line_pointer < 3
5548 || strncasecmp (s - 3, "THEN", 4) != 0)
5549 {
5550 if (qual != '\0')
5551 {
5552 as_bad ("missing then");
5553 ignore_rest_of_line ();
5554 return;
5555 }
5556
5557 /* It's a conditional. */
5558 s_if (O_ne);
5559 return;
5560 }
5561
5562 /* Since this might be a conditional if, this pseudo-op will be
5563 called even if we are supported to be ignoring input. Double
5564 check now. Clobber *input_line_pointer so that ignore_input
5565 thinks that this is not a special pseudo-op. */
5566 c = *input_line_pointer;
5567 *input_line_pointer = 0;
5568 if (ignore_input ())
5569 {
5570 *input_line_pointer = c;
5571 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5572 ++input_line_pointer;
5573 demand_empty_rest_of_line ();
5574 return;
5575 }
5576 *input_line_pointer = c;
5577
5578 n = push_mri_control (mri_if);
5579
5580 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5581 n->next, s[1] == '.' ? s[2] : '\0');
5582
5583 if (s[1] == '.')
5584 input_line_pointer = s + 3;
5585 else
5586 input_line_pointer = s + 1;
5587
5588 if (flag_mri)
5589 {
5590 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5591 ++input_line_pointer;
5592 }
5593
5594 demand_empty_rest_of_line ();
5595 }
5596
5597 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5598 structured IF, associate the ELSE with the IF. Otherwise, assume
5599 it is a conditional else. */
5600
5601 static void
5602 s_mri_else (qual)
5603 int qual;
5604 {
5605 int c;
5606 char *buf;
5607 char q[2];
5608
5609 if (qual == '\0'
5610 && (mri_control_stack == NULL
5611 || mri_control_stack->type != mri_if
5612 || mri_control_stack->else_seen))
5613 {
5614 s_else (0);
5615 return;
5616 }
5617
5618 c = *input_line_pointer;
5619 *input_line_pointer = 0;
5620 if (ignore_input ())
5621 {
5622 *input_line_pointer = c;
5623 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5624 ++input_line_pointer;
5625 demand_empty_rest_of_line ();
5626 return;
5627 }
5628 *input_line_pointer = c;
5629
5630 if (mri_control_stack == NULL
5631 || mri_control_stack->type != mri_if
5632 || mri_control_stack->else_seen)
5633 {
5634 as_bad ("else without matching if");
5635 ignore_rest_of_line ();
5636 return;
5637 }
5638
5639 mri_control_stack->else_seen = 1;
5640
5641 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5642 q[0] = qual;
5643 q[1] = '\0';
5644 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5645 md_assemble (buf);
5646 free (buf);
5647
5648 colon (mri_control_stack->next);
5649
5650 if (flag_mri)
5651 {
5652 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5653 ++input_line_pointer;
5654 }
5655
5656 demand_empty_rest_of_line ();
5657 }
5658
5659 /* Handle the MRI ENDI pseudo-op. */
5660
5661 static void
5662 s_mri_endi (ignore)
5663 int ignore;
5664 {
5665 if (mri_control_stack == NULL
5666 || mri_control_stack->type != mri_if)
5667 {
5668 as_bad ("endi without matching if");
5669 ignore_rest_of_line ();
5670 return;
5671 }
5672
5673 /* ignore_input will not return true for ENDI, so we don't need to
5674 worry about checking it again here. */
5675
5676 if (! mri_control_stack->else_seen)
5677 colon (mri_control_stack->next);
5678 colon (mri_control_stack->bottom);
5679
5680 pop_mri_control ();
5681
5682 if (flag_mri)
5683 {
5684 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5685 ++input_line_pointer;
5686 }
5687
5688 demand_empty_rest_of_line ();
5689 }
5690
5691 /* Handle the MRI BREAK pseudo-op. */
5692
5693 static void
5694 s_mri_break (extent)
5695 int extent;
5696 {
5697 struct mri_control_info *n;
5698 char *buf;
5699 char ex[2];
5700
5701 n = mri_control_stack;
5702 while (n != NULL
5703 && n->type != mri_for
5704 && n->type != mri_repeat
5705 && n->type != mri_while)
5706 n = n->outer;
5707 if (n == NULL)
5708 {
5709 as_bad ("break outside of structured loop");
5710 ignore_rest_of_line ();
5711 return;
5712 }
5713
5714 buf = (char *) xmalloc (20 + strlen (n->bottom));
5715 ex[0] = extent;
5716 ex[1] = '\0';
5717 sprintf (buf, "bra%s %s", ex, n->bottom);
5718 md_assemble (buf);
5719 free (buf);
5720
5721 if (flag_mri)
5722 {
5723 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5724 ++input_line_pointer;
5725 }
5726
5727 demand_empty_rest_of_line ();
5728 }
5729
5730 /* Handle the MRI NEXT pseudo-op. */
5731
5732 static void
5733 s_mri_next (extent)
5734 int extent;
5735 {
5736 struct mri_control_info *n;
5737 char *buf;
5738 char ex[2];
5739
5740 n = mri_control_stack;
5741 while (n != NULL
5742 && n->type != mri_for
5743 && n->type != mri_repeat
5744 && n->type != mri_while)
5745 n = n->outer;
5746 if (n == NULL)
5747 {
5748 as_bad ("next outside of structured loop");
5749 ignore_rest_of_line ();
5750 return;
5751 }
5752
5753 buf = (char *) xmalloc (20 + strlen (n->next));
5754 ex[0] = extent;
5755 ex[1] = '\0';
5756 sprintf (buf, "bra%s %s", ex, n->next);
5757 md_assemble (buf);
5758 free (buf);
5759
5760 if (flag_mri)
5761 {
5762 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5763 ++input_line_pointer;
5764 }
5765
5766 demand_empty_rest_of_line ();
5767 }
5768
5769 /* Handle the MRI FOR pseudo-op. */
5770
5771 static void
5772 s_mri_for (qual)
5773 int qual;
5774 {
5775 const char *varstart, *varstop;
5776 const char *initstart, *initstop;
5777 const char *endstart, *endstop;
5778 const char *bystart, *bystop;
5779 int up;
5780 int by;
5781 int extent;
5782 struct mri_control_info *n;
5783 char *buf;
5784 char *s;
5785 char ex[2];
5786
5787 /* The syntax is
5788 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5789 */
5790
5791 SKIP_WHITESPACE ();
5792 varstart = input_line_pointer;
5793
5794 /* Look for the '='. */
5795 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5796 && *input_line_pointer != '=')
5797 ++input_line_pointer;
5798 if (*input_line_pointer != '=')
5799 {
5800 as_bad ("missing =");
5801 ignore_rest_of_line ();
5802 return;
5803 }
5804
5805 varstop = input_line_pointer;
5806 if (varstop > varstart
5807 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5808 --varstop;
5809
5810 ++input_line_pointer;
5811
5812 initstart = input_line_pointer;
5813
5814 /* Look for TO or DOWNTO. */
5815 up = 1;
5816 initstop = NULL;
5817 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5818 {
5819 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5820 && ! is_part_of_name (input_line_pointer[2]))
5821 {
5822 initstop = input_line_pointer;
5823 input_line_pointer += 2;
5824 break;
5825 }
5826 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5827 && ! is_part_of_name (input_line_pointer[6]))
5828 {
5829 initstop = input_line_pointer;
5830 up = 0;
5831 input_line_pointer += 6;
5832 break;
5833 }
5834 ++input_line_pointer;
5835 }
5836 if (initstop == NULL)
5837 {
5838 as_bad ("missing to or downto");
5839 ignore_rest_of_line ();
5840 return;
5841 }
5842 if (initstop > initstart
5843 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5844 --initstop;
5845
5846 SKIP_WHITESPACE ();
5847 endstart = input_line_pointer;
5848
5849 /* Look for BY or DO. */
5850 by = 0;
5851 endstop = NULL;
5852 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5853 {
5854 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5855 && ! is_part_of_name (input_line_pointer[2]))
5856 {
5857 endstop = input_line_pointer;
5858 by = 1;
5859 input_line_pointer += 2;
5860 break;
5861 }
5862 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5863 && (input_line_pointer[2] == '.'
5864 || ! is_part_of_name (input_line_pointer[2])))
5865 {
5866 endstop = input_line_pointer;
5867 input_line_pointer += 2;
5868 break;
5869 }
5870 ++input_line_pointer;
5871 }
5872 if (endstop == NULL)
5873 {
5874 as_bad ("missing do");
5875 ignore_rest_of_line ();
5876 return;
5877 }
5878 if (endstop > endstart
5879 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5880 --endstop;
5881
5882 if (! by)
5883 {
5884 bystart = "#1";
5885 bystop = bystart + 2;
5886 }
5887 else
5888 {
5889 SKIP_WHITESPACE ();
5890 bystart = input_line_pointer;
5891
5892 /* Look for DO. */
5893 bystop = NULL;
5894 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5895 {
5896 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5897 && (input_line_pointer[2] == '.'
5898 || ! is_part_of_name (input_line_pointer[2])))
5899 {
5900 bystop = input_line_pointer;
5901 input_line_pointer += 2;
5902 break;
5903 }
5904 ++input_line_pointer;
5905 }
5906 if (bystop == NULL)
5907 {
5908 as_bad ("missing do");
5909 ignore_rest_of_line ();
5910 return;
5911 }
5912 if (bystop > bystart
5913 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5914 --bystop;
5915 }
5916
5917 if (*input_line_pointer != '.')
5918 extent = '\0';
5919 else
5920 {
5921 extent = input_line_pointer[1];
5922 input_line_pointer += 2;
5923 }
5924
5925 /* We have fully parsed the FOR operands. Now build the loop. */
5926
5927 n = push_mri_control (mri_for);
5928
5929 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5930
5931 /* move init,var */
5932 s = buf;
5933 *s++ = 'm';
5934 *s++ = 'o';
5935 *s++ = 'v';
5936 *s++ = 'e';
5937 if (qual != '\0')
5938 *s++ = qual;
5939 *s++ = ' ';
5940 memcpy (s, initstart, initstop - initstart);
5941 s += initstop - initstart;
5942 *s++ = ',';
5943 memcpy (s, varstart, varstop - varstart);
5944 s += varstop - varstart;
5945 *s = '\0';
5946 md_assemble (buf);
5947
5948 colon (n->top);
5949
5950 /* cmp end,var */
5951 s = buf;
5952 *s++ = 'c';
5953 *s++ = 'm';
5954 *s++ = 'p';
5955 if (qual != '\0')
5956 *s++ = qual;
5957 *s++ = ' ';
5958 memcpy (s, endstart, endstop - endstart);
5959 s += endstop - endstart;
5960 *s++ = ',';
5961 memcpy (s, varstart, varstop - varstart);
5962 s += varstop - varstart;
5963 *s = '\0';
5964 md_assemble (buf);
5965
5966 /* bcc bottom */
5967 ex[0] = extent;
5968 ex[1] = '\0';
5969 if (up)
5970 sprintf (buf, "blt%s %s", ex, n->bottom);
5971 else
5972 sprintf (buf, "bgt%s %s", ex, n->bottom);
5973 md_assemble (buf);
5974
5975 /* Put together the add or sub instruction used by ENDF. */
5976 s = buf;
5977 if (up)
5978 strcpy (s, "add");
5979 else
5980 strcpy (s, "sub");
5981 s += 3;
5982 if (qual != '\0')
5983 *s++ = qual;
5984 *s++ = ' ';
5985 memcpy (s, bystart, bystop - bystart);
5986 s += bystop - bystart;
5987 *s++ = ',';
5988 memcpy (s, varstart, varstop - varstart);
5989 s += varstop - varstart;
5990 *s = '\0';
5991 n->incr = buf;
5992
5993 if (flag_mri)
5994 {
5995 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5996 ++input_line_pointer;
5997 }
5998
5999 demand_empty_rest_of_line ();
6000 }
6001
6002 /* Handle the MRI ENDF pseudo-op. */
6003
6004 static void
6005 s_mri_endf (ignore)
6006 int ignore;
6007 {
6008 if (mri_control_stack == NULL
6009 || mri_control_stack->type != mri_for)
6010 {
6011 as_bad ("endf without for");
6012 ignore_rest_of_line ();
6013 return;
6014 }
6015
6016 colon (mri_control_stack->next);
6017
6018 md_assemble (mri_control_stack->incr);
6019
6020 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6021 md_assemble (mri_control_stack->incr);
6022
6023 free (mri_control_stack->incr);
6024
6025 colon (mri_control_stack->bottom);
6026
6027 pop_mri_control ();
6028
6029 if (flag_mri)
6030 {
6031 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6032 ++input_line_pointer;
6033 }
6034
6035 demand_empty_rest_of_line ();
6036 }
6037
6038 /* Handle the MRI REPEAT pseudo-op. */
6039
6040 static void
6041 s_mri_repeat (ignore)
6042 int ignore;
6043 {
6044 struct mri_control_info *n;
6045
6046 n = push_mri_control (mri_repeat);
6047 colon (n->top);
6048 if (flag_mri)
6049 {
6050 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6051 ++input_line_pointer;
6052 }
6053 demand_empty_rest_of_line ();
6054 }
6055
6056 /* Handle the MRI UNTIL pseudo-op. */
6057
6058 static void
6059 s_mri_until (qual)
6060 int qual;
6061 {
6062 char *s;
6063
6064 if (mri_control_stack == NULL
6065 || mri_control_stack->type != mri_repeat)
6066 {
6067 as_bad ("until without repeat");
6068 ignore_rest_of_line ();
6069 return;
6070 }
6071
6072 colon (mri_control_stack->next);
6073
6074 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6075 ;
6076
6077 parse_mri_control_expression (s, qual, (const char *) NULL,
6078 mri_control_stack->top, '\0');
6079
6080 colon (mri_control_stack->bottom);
6081
6082 input_line_pointer = s;
6083
6084 pop_mri_control ();
6085
6086 if (flag_mri)
6087 {
6088 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6089 ++input_line_pointer;
6090 }
6091
6092 demand_empty_rest_of_line ();
6093 }
6094
6095 /* Handle the MRI WHILE pseudo-op. */
6096
6097 static void
6098 s_mri_while (qual)
6099 int qual;
6100 {
6101 char *s;
6102
6103 struct mri_control_info *n;
6104
6105 s = input_line_pointer;
6106 while (! is_end_of_line[(unsigned char) *s]
6107 && (! flag_mri || *s != '*'))
6108 s++;
6109 --s;
6110 while (*s == ' ' || *s == '\t')
6111 --s;
6112 if (s - input_line_pointer > 1
6113 && s[-1] == '.')
6114 s -= 2;
6115 if (s - input_line_pointer < 2
6116 || strncasecmp (s - 1, "DO", 2) != 0)
6117 {
6118 as_bad ("missing do");
6119 ignore_rest_of_line ();
6120 return;
6121 }
6122
6123 n = push_mri_control (mri_while);
6124
6125 colon (n->next);
6126
6127 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6128 s[1] == '.' ? s[2] : '\0');
6129
6130 input_line_pointer = s + 1;
6131 if (*input_line_pointer == '.')
6132 input_line_pointer += 2;
6133
6134 if (flag_mri)
6135 {
6136 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6137 ++input_line_pointer;
6138 }
6139
6140 demand_empty_rest_of_line ();
6141 }
6142
6143 /* Handle the MRI ENDW pseudo-op. */
6144
6145 static void
6146 s_mri_endw (ignore)
6147 int ignore;
6148 {
6149 char *buf;
6150
6151 if (mri_control_stack == NULL
6152 || mri_control_stack->type != mri_while)
6153 {
6154 as_bad ("endw without while");
6155 ignore_rest_of_line ();
6156 return;
6157 }
6158
6159 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6160 sprintf (buf, "bra %s", mri_control_stack->next);
6161 md_assemble (buf);
6162 free (buf);
6163
6164 colon (mri_control_stack->bottom);
6165
6166 pop_mri_control ();
6167
6168 if (flag_mri)
6169 {
6170 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6171 ++input_line_pointer;
6172 }
6173
6174 demand_empty_rest_of_line ();
6175 }
6176 \f
6177 /*
6178 * md_parse_option
6179 * Invocation line includes a switch not recognized by the base assembler.
6180 * See if it's a processor-specific option. These are:
6181 *
6182 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6183 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6184 * Select the architecture. Instructions or features not
6185 * supported by the selected architecture cause fatal
6186 * errors. More than one may be specified. The default is
6187 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6188 * for -m68000, and -m68882 is a synonym for -m68881.
6189 * -[A]m[c]no-68851, -[A]m[c]no-68881
6190 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6191 * so don't use or document it, but that's the way the parsing
6192 * works).
6193 *
6194 * -pic Indicates PIC.
6195 * -k Indicates PIC. (Sun 3 only.)
6196 *
6197 * --bitwise-or
6198 * Permit `|' to be used in expressions.
6199 *
6200 */
6201
6202 #ifdef OBJ_ELF
6203 CONST char *md_shortopts = "lSA:m:kQ:V";
6204 #else
6205 CONST char *md_shortopts = "lSA:m:k";
6206 #endif
6207
6208 struct option md_longopts[] = {
6209 #define OPTION_PIC (OPTION_MD_BASE)
6210 {"pic", no_argument, NULL, OPTION_PIC},
6211 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6212 {"register-prefix-optional", no_argument, NULL,
6213 OPTION_REGISTER_PREFIX_OPTIONAL},
6214 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6215 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6216 {NULL, no_argument, NULL, 0}
6217 };
6218 size_t md_longopts_size = sizeof(md_longopts);
6219
6220 int
6221 md_parse_option (c, arg)
6222 int c;
6223 char *arg;
6224 {
6225 switch (c)
6226 {
6227 case 'l': /* -l means keep external to 2 bit offset
6228 rather than 16 bit one */
6229 flag_short_refs = 1;
6230 break;
6231
6232 case 'S': /* -S means that jbsr's always turn into
6233 jsr's. */
6234 flag_long_jumps = 1;
6235 break;
6236
6237 case 'A':
6238 if (*arg == 'm')
6239 arg++;
6240 /* intentional fall-through */
6241 case 'm':
6242
6243 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6244 {
6245 int i;
6246 unsigned long arch;
6247 const char *oarg = arg;
6248
6249 arg += 3;
6250 if (*arg == 'm')
6251 {
6252 arg++;
6253 if (arg[0] == 'c' && arg[1] == '6')
6254 arg++;
6255 }
6256 for (i = 0; i < n_archs; i++)
6257 if (!strcmp (arg, archs[i].name))
6258 break;
6259 if (i == n_archs)
6260 {
6261 unknown:
6262 as_bad ("unrecognized option `%s'", oarg);
6263 return 0;
6264 }
6265 arch = archs[i].arch;
6266 if (arch == m68881)
6267 no_68881 = 1;
6268 else if (arch == m68851)
6269 no_68851 = 1;
6270 else
6271 goto unknown;
6272 }
6273 else
6274 {
6275 int i;
6276
6277 if (arg[0] == 'c' && arg[1] == '6')
6278 arg++;
6279
6280 for (i = 0; i < n_archs; i++)
6281 if (!strcmp (arg, archs[i].name))
6282 {
6283 unsigned long arch = archs[i].arch;
6284 if (cpu_of_arch (arch))
6285 /* It's a cpu spec. */
6286 {
6287 current_architecture &= ~m68000up;
6288 current_architecture |= arch;
6289 }
6290 else if (arch == m68881)
6291 {
6292 current_architecture |= m68881;
6293 no_68881 = 0;
6294 }
6295 else if (arch == m68851)
6296 {
6297 current_architecture |= m68851;
6298 no_68851 = 0;
6299 }
6300 else
6301 /* ??? */
6302 abort ();
6303 break;
6304 }
6305 if (i == n_archs)
6306 {
6307 as_bad ("unrecognized architecture specification `%s'", arg);
6308 return 0;
6309 }
6310 }
6311 break;
6312
6313 case OPTION_PIC:
6314 case 'k':
6315 flag_want_pic = 1;
6316 break; /* -pic, Position Independent Code */
6317
6318 case OPTION_REGISTER_PREFIX_OPTIONAL:
6319 flag_reg_prefix_optional = 1;
6320 reg_prefix_optional_seen = 1;
6321 break;
6322
6323 /* -V: SVR4 argument to print version ID. */
6324 case 'V':
6325 print_version_id ();
6326 break;
6327
6328 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6329 should be emitted or not. FIXME: Not implemented. */
6330 case 'Q':
6331 break;
6332
6333 case OPTION_BITWISE_OR:
6334 {
6335 char *n, *t;
6336 const char *s;
6337
6338 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6339 t = n;
6340 for (s = m68k_comment_chars; *s != '\0'; s++)
6341 if (*s != '|')
6342 *t++ = *s;
6343 *t = '\0';
6344 m68k_comment_chars = n;
6345 }
6346 break;
6347
6348 default:
6349 return 0;
6350 }
6351
6352 return 1;
6353 }
6354
6355 void
6356 md_show_usage (stream)
6357 FILE *stream;
6358 {
6359 fprintf(stream, "\
6360 680X0 options:\n\
6361 -l use 1 word for refs to undefined symbols [default 2]\n\
6362 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6363 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6364 | -mcpu32 | -mcf5200\n\
6365 specify variant of 680X0 architecture [default 68020]\n\
6366 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6367 target has/lacks floating-point coprocessor\n\
6368 [default yes for 68020, 68030, and cpu32]\n");
6369 fprintf(stream, "\
6370 -m68851 | -mno-68851\n\
6371 target has/lacks memory-management unit coprocessor\n\
6372 [default yes for 68020 and up]\n\
6373 -pic, -k generate position independent code\n\
6374 -S turn jbsr into jsr\n\
6375 --register-prefix-optional\n\
6376 recognize register names without prefix character\n\
6377 --bitwise-or do not treat `|' as a comment character\n");
6378 }
6379 \f
6380 #ifdef TEST2
6381
6382 /* TEST2: Test md_assemble() */
6383 /* Warning, this routine probably doesn't work anymore */
6384
6385 main ()
6386 {
6387 struct m68k_it the_ins;
6388 char buf[120];
6389 char *cp;
6390 int n;
6391
6392 m68k_ip_begin ();
6393 for (;;)
6394 {
6395 if (!gets (buf) || !*buf)
6396 break;
6397 if (buf[0] == '|' || buf[1] == '.')
6398 continue;
6399 for (cp = buf; *cp; cp++)
6400 if (*cp == '\t')
6401 *cp = ' ';
6402 if (is_label (buf))
6403 continue;
6404 memset (&the_ins, '\0', sizeof (the_ins));
6405 m68k_ip (&the_ins, buf);
6406 if (the_ins.error)
6407 {
6408 printf ("Error %s in %s\n", the_ins.error, buf);
6409 }
6410 else
6411 {
6412 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6413 for (n = 0; n < the_ins.numo; n++)
6414 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6415 printf (" ");
6416 print_the_insn (&the_ins.opcode[0], stdout);
6417 (void) putchar ('\n');
6418 }
6419 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6420 {
6421 if (the_ins.operands[n].error)
6422 {
6423 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6424 continue;
6425 }
6426 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6427 if (the_ins.operands[n].b_const)
6428 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6429 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6430 if (the_ins.operands[n].b_iadd)
6431 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6432 (void) putchar ('\n');
6433 }
6434 }
6435 m68k_ip_end ();
6436 return 0;
6437 }
6438
6439 is_label (str)
6440 char *str;
6441 {
6442 while (*str == ' ')
6443 str++;
6444 while (*str && *str != ' ')
6445 str++;
6446 if (str[-1] == ':' || str[1] == '=')
6447 return 1;
6448 return 0;
6449 }
6450
6451 #endif
6452
6453 /* Possible states for relaxation:
6454
6455 0 0 branch offset byte (bra, etc)
6456 0 1 word
6457 0 2 long
6458
6459 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6460 1 1 word
6461 1 2 long
6462
6463 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6464 2 1 word-long
6465 2 2 long-word
6466 2 3 long-long
6467
6468 */
6469
6470 /* We have no need to default values of symbols. */
6471
6472 /* ARGSUSED */
6473 symbolS *
6474 md_undefined_symbol (name)
6475 char *name;
6476 {
6477 return 0;
6478 }
6479
6480 /* Round up a section size to the appropriate boundary. */
6481 valueT
6482 md_section_align (segment, size)
6483 segT segment;
6484 valueT size;
6485 {
6486 return size; /* Byte alignment is fine */
6487 }
6488
6489 /* Exactly what point is a PC-relative offset relative TO?
6490 On the 68k, it is relative to the address of the first extension
6491 word. The difference between the addresses of the offset and the
6492 first extension word is stored in fx_pcrel_adjust. */
6493 long
6494 md_pcrel_from (fixP)
6495 fixS *fixP;
6496 {
6497 int adjust;
6498
6499 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6500 -1 as 64. */
6501 adjust = fixP->fx_pcrel_adjust;
6502 if (adjust == 64)
6503 adjust = -1;
6504 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6505 }
6506
6507 #ifndef BFD_ASSEMBLER
6508 /*ARGSUSED*/
6509 void
6510 tc_coff_symbol_emit_hook (ignore)
6511 symbolS *ignore;
6512 {
6513 }
6514
6515 int
6516 tc_coff_sizemachdep (frag)
6517 fragS *frag;
6518 {
6519 switch (frag->fr_subtype & 0x3)
6520 {
6521 case BYTE:
6522 return 1;
6523 case SHORT:
6524 return 2;
6525 case LONG:
6526 return 4;
6527 default:
6528 abort ();
6529 return 0;
6530 }
6531 }
6532 #endif
6533
6534 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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