projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
* config/tc-m68k.c (struct label_line): Define.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 long foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 static struct m68k_it the_ins; /* the instruction being assembled */
255
256 #define op(ex) ((ex)->exp.X_op)
257 #define adds(ex) ((ex)->exp.X_add_symbol)
258 #define subs(ex) ((ex)->exp.X_op_symbol)
259 #define offs(ex) ((ex)->exp.X_add_number)
260
261 /* Macros for adding things to the m68k_it struct */
262
263 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
264
265 /* Like addword, but goes BEFORE general operands */
266 static void
267 insop (w, opcode)
268 int w;
269 struct m68k_incant *opcode;
270 {
271 int z;
272 for(z=the_ins.numo;z>opcode->m_codenum;--z)
273 the_ins.opcode[z]=the_ins.opcode[z-1];
274 for(z=0;z<the_ins.nrel;z++)
275 the_ins.reloc[z].n+=2;
276 for (z = 0; z < the_ins.nfrag; z++)
277 the_ins.fragb[z].fragoff++;
278 the_ins.opcode[opcode->m_codenum]=w;
279 the_ins.numo++;
280 }
281
282 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
283 Blecch. */
284 static void
285 add_fix (width, exp, pc_rel, pc_fix)
286 char width;
287 struct m68k_exp *exp;
288 int pc_rel;
289 int pc_fix;
290 {
291 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
292 ? (the_ins.numo*2-1)
293 : (((width)=='b')
294 ? (the_ins.numo*2+1)
295 : (the_ins.numo*2)));
296 the_ins.reloc[the_ins.nrel].exp = exp->exp;
297 the_ins.reloc[the_ins.nrel].wid = width;
298 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
299 #ifdef OBJ_ELF
300 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
301 #endif
302 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
303 }
304
305 /* Cause an extra frag to be generated here, inserting up to 10 bytes
306 (that value is chosen in the frag_var call in md_assemble). TYPE
307 is the subtype of the frag to be generated; its primary type is
308 rs_machine_dependent.
309
310 The TYPE parameter is also used by md_convert_frag_1 and
311 md_estimate_size_before_relax. The appropriate type of fixup will
312 be emitted by md_convert_frag_1.
313
314 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
315 static void
316 add_frag(add,off,type)
317 symbolS *add;
318 long off;
319 int type;
320 {
321 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
322 the_ins.fragb[the_ins.nfrag].fadd=add;
323 the_ins.fragb[the_ins.nfrag].foff=off;
324 the_ins.fragb[the_ins.nfrag++].fragty=type;
325 }
326
327 #define isvar(ex) \
328 (op (ex) != O_constant && op (ex) != O_big)
329
330 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
331 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
332 static int reverse_16_bits PARAMS ((int in));
333 static int reverse_8_bits PARAMS ((int in));
334 static void install_gen_operand PARAMS ((int mode, int val));
335 static void install_operand PARAMS ((int mode, int val));
336 static void s_bss PARAMS ((int));
337 static void s_data1 PARAMS ((int));
338 static void s_data2 PARAMS ((int));
339 static void s_even PARAMS ((int));
340 static void s_proc PARAMS ((int));
341 static void mri_chip PARAMS ((void));
342 static void s_chip PARAMS ((int));
343 static void s_fopt PARAMS ((int));
344 static void s_opt PARAMS ((int));
345 static void s_reg PARAMS ((int));
346 static void s_restore PARAMS ((int));
347 static void s_save PARAMS ((int));
348 static void s_mri_if PARAMS ((int));
349 static void s_mri_else PARAMS ((int));
350 static void s_mri_endi PARAMS ((int));
351 static void s_mri_break PARAMS ((int));
352 static void s_mri_next PARAMS ((int));
353 static void s_mri_for PARAMS ((int));
354 static void s_mri_endf PARAMS ((int));
355 static void s_mri_repeat PARAMS ((int));
356 static void s_mri_until PARAMS ((int));
357 static void s_mri_while PARAMS ((int));
358 static void s_mri_endw PARAMS ((int));
359
360 static int current_architecture;
361
362 struct m68k_cpu {
363 unsigned long arch;
364 const char *name;
365 int alias;
366 };
367
368 static const struct m68k_cpu archs[] = {
369 { m68000, "68000", 0 },
370 { m68010, "68010", 0 },
371 { m68020, "68020", 0 },
372 { m68030, "68030", 0 },
373 { m68040, "68040", 0 },
374 { m68060, "68060", 0 },
375 { cpu32, "cpu32", 0 },
376 { m68881, "68881", 0 },
377 { m68851, "68851", 0 },
378 { mcf5200, "5200", 0 },
379 /* Aliases (effectively, so far as gas is concerned) for the above
380 cpus. */
381 { m68020, "68k", 1 },
382 { m68000, "68302", 1 },
383 { m68000, "68008", 1 },
384 { m68000, "68ec000", 1 },
385 { m68000, "68hc000", 1 },
386 { m68000, "68hc001", 1 },
387 { m68020, "68ec020", 1 },
388 { m68030, "68ec030", 1 },
389 { m68040, "68ec040", 1 },
390 { m68060, "68ec060", 1 },
391 { cpu32, "68330", 1 },
392 { cpu32, "68331", 1 },
393 { cpu32, "68332", 1 },
394 { cpu32, "68333", 1 },
395 { cpu32, "68340", 1 },
396 { cpu32, "68360", 1 },
397 { m68881, "68882", 1 },
398 };
399
400 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
401
402 /* BCC68000 is for patching in an extra jmp instruction for long offsets
403 on the 68000. The 68000 doesn't support long branches with branchs */
404
405 /* This table desribes how you change sizes for the various types of variable
406 size expressions. This version only supports two kinds. */
407
408 /* Note that calls to frag_var need to specify the maximum expansion
409 needed; this is currently 10 bytes for DBCC. */
410
411 /* The fields are:
412 How far Forward this mode will reach:
413 How far Backward this mode will reach:
414 How many bytes this mode will add to the size of the frag
415 Which mode to go to if the offset won't fit in this one
416 */
417 relax_typeS md_relax_table[] =
418 {
419 {1, 1, 0, 0}, /* First entries aren't used */
420 {1, 1, 0, 0}, /* For no good reason except */
421 {1, 1, 0, 0}, /* that the VAX doesn't either */
422 {1, 1, 0, 0},
423
424 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
425 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
426 {0, 0, 4, 0},
427 {1, 1, 0, 0},
428
429 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
430 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
431 {0, 0, 4, 0},
432 {1, 1, 0, 0},
433
434 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
435 {(32767), (-32768), 2, TAB (PCREL, LONG)},
436 {0, 0, 4, 0},
437 {1, 1, 0, 0},
438
439 {(127), (-128), 0, TAB (BCC68000, SHORT)},
440 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
441 {0, 0, 6, 0}, /* jmp long space */
442 {1, 1, 0, 0},
443
444 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
445 {(32767), (-32768), 2, TAB (DBCC, LONG)},
446 {0, 0, 10, 0}, /* bra/jmp long space */
447 {1, 1, 0, 0},
448
449 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
450 {32767, -32768, 2, TAB (PCLEA, LONG)},
451 {0, 0, 6, 0},
452 {1, 1, 0, 0},
453
454 /* For, e.g., jmp pcrel indexed. */
455 {125, -130, 0, TAB (PCINDEX, SHORT)},
456 {32765, -32770, 2, TAB (PCINDEX, LONG)},
457 {0, 0, 4, 0},
458 {1, 1, 0, 0},
459 };
460
461 /* These are the machine dependent pseudo-ops. These are included so
462 the assembler can work on the output from the SUN C compiler, which
463 generates these.
464 */
465
466 /* This table describes all the machine specific pseudo-ops the assembler
467 has to support. The fields are:
468 pseudo-op name without dot
469 function to call to execute this pseudo-op
470 Integer arg to pass to the function
471 */
472 const pseudo_typeS md_pseudo_table[] =
473 {
474 {"data1", s_data1, 0},
475 {"data2", s_data2, 0},
476 {"bss", s_bss, 0},
477 {"even", s_even, 0},
478 {"skip", s_space, 0},
479 {"proc", s_proc, 0},
480 #if defined (TE_SUN3) || defined (OBJ_ELF)
481 {"align", s_align_bytes, 0},
482 #endif
483 #ifdef OBJ_ELF
484 {"swbeg", s_ignore, 0},
485 #endif
486 {"extend", float_cons, 'x'},
487 {"ldouble", float_cons, 'x'},
488
489 /* The following pseudo-ops are supported for MRI compatibility. */
490 {"chip", s_chip, 0},
491 {"comline", s_space, 1},
492 {"fopt", s_fopt, 0},
493 {"mask2", s_ignore, 0},
494 {"opt", s_opt, 0},
495 {"reg", s_reg, 0},
496 {"restore", s_restore, 0},
497 {"save", s_save, 0},
498
499 {"if", s_mri_if, 0},
500 {"if.b", s_mri_if, 'b'},
501 {"if.w", s_mri_if, 'w'},
502 {"if.l", s_mri_if, 'l'},
503 {"else", s_mri_else, 0},
504 {"else.s", s_mri_else, 's'},
505 {"else.l", s_mri_else, 'l'},
506 {"endi", s_mri_endi, 0},
507 {"break", s_mri_break, 0},
508 {"break.s", s_mri_break, 's'},
509 {"break.l", s_mri_break, 'l'},
510 {"next", s_mri_next, 0},
511 {"next.s", s_mri_next, 's'},
512 {"next.l", s_mri_next, 'l'},
513 {"for", s_mri_for, 0},
514 {"for.b", s_mri_for, 'b'},
515 {"for.w", s_mri_for, 'w'},
516 {"for.l", s_mri_for, 'l'},
517 {"endf", s_mri_endf, 0},
518 {"repeat", s_mri_repeat, 0},
519 {"until", s_mri_until, 0},
520 {"until.b", s_mri_until, 'b'},
521 {"until.w", s_mri_until, 'w'},
522 {"until.l", s_mri_until, 'l'},
523 {"while", s_mri_while, 0},
524 {"while.b", s_mri_while, 'b'},
525 {"while.w", s_mri_while, 'w'},
526 {"while.l", s_mri_while, 'l'},
527 {"endw", s_mri_endw, 0},
528
529 {0, 0, 0}
530 };
531
532
533 /* The mote pseudo ops are put into the opcode table, since they
534 don't start with a . they look like opcodes to gas.
535 */
536 extern void obj_coff_section ();
537
538 CONST pseudo_typeS mote_pseudo_table[] =
539 {
540
541 {"dcl", cons, 4},
542 {"dc", cons, 2},
543 {"dcw", cons, 2},
544 {"dcb", cons, 1},
545
546 {"dsl", s_space, 4},
547 {"ds", s_space, 2},
548 {"dsw", s_space, 2},
549 {"dsb", s_space, 1},
550
551 {"xdef", s_globl, 0},
552 #ifdef OBJ_ELF
553 {"align", s_align_bytes, 0},
554 #else
555 {"align", s_align_ptwo, 0},
556 #endif
557 #ifdef M68KCOFF
558 {"sect", obj_coff_section, 0},
559 {"section", obj_coff_section, 0},
560 #endif
561 {0, 0, 0}
562 };
563
564 #define issbyte(x) ((x)>=-128 && (x)<=127)
565 #define isubyte(x) ((x)>=0 && (x)<=255)
566 #define issword(x) ((x)>=-32768 && (x)<=32767)
567 #define isuword(x) ((x)>=0 && (x)<=65535)
568
569 #define isbyte(x) ((x)>= -255 && (x)<=255)
570 #define isword(x) ((x)>=-65536 && (x)<=65535)
571 #define islong(x) (1)
572
573 extern char *input_line_pointer;
574
575 static char mklower_table[256];
576 #define mklower(c) (mklower_table[(unsigned char)(c)])
577 static char notend_table[256];
578 static char alt_notend_table[256];
579 #define notend(s) \
580 (! (notend_table[(unsigned char) *s] \
581 || (*s == ':' \
582 && alt_notend_table[(unsigned char) s[1]])))
583
584 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
585
586 #ifdef NO_PCREL_RELOCS
587
588 int
589 make_pcrel_absolute(fixP, add_number)
590 fixS *fixP;
591 long *add_number;
592 {
593 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
594
595 /* rewrite the PC relative instructions to absolute address ones.
596 * these are rumoured to be faster, and the apollo linker refuses
597 * to deal with the PC relative relocations.
598 */
599 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
600 {
601 opcode[0] = 0x4e;
602 opcode[1] = 0xf9;
603 }
604 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
605 {
606 opcode[0] = 0x4e;
607 opcode[1] = 0xb9;
608 }
609 else
610 as_fatal ("Unknown PC relative instruction");
611 *add_number -= 4;
612 return 0;
613 }
614
615 #endif /* NO_PCREL_RELOCS */
616
617 short
618 tc_coff_fix2rtype (fixP)
619 fixS *fixP;
620 {
621 if (fixP->fx_tcbit && fixP->fx_size == 4)
622 return R_RELLONG_NEG;
623 #ifdef NO_PCREL_RELOCS
624 know (fixP->fx_pcrel == 0);
625 return (fixP->fx_size == 1 ? R_RELBYTE
626 : fixP->fx_size == 2 ? R_DIR16
627 : R_DIR32);
628 #else
629 return (fixP->fx_pcrel ?
630 (fixP->fx_size == 1 ? R_PCRBYTE :
631 fixP->fx_size == 2 ? R_PCRWORD :
632 R_PCRLONG) :
633 (fixP->fx_size == 1 ? R_RELBYTE :
634 fixP->fx_size == 2 ? R_RELWORD :
635 R_RELLONG));
636 #endif
637 }
638
639 #endif
640
641 #ifdef OBJ_ELF
642
643 /* Compute the relocation code for a fixup of SIZE bytes, using pc
644 relative relocation if PCREL is non-zero. PIC says whether a special
645 pic relocation was requested. */
646
647 static bfd_reloc_code_real_type get_reloc_code
648 PARAMS ((int, int, enum pic_relocation));
649
650 static bfd_reloc_code_real_type
651 get_reloc_code (size, pcrel, pic)
652 int size;
653 int pcrel;
654 enum pic_relocation pic;
655 {
656 switch (pic)
657 {
658 case pic_got_pcrel:
659 switch (size)
660 {
661 case 1:
662 return BFD_RELOC_8_GOT_PCREL;
663 case 2:
664 return BFD_RELOC_16_GOT_PCREL;
665 case 4:
666 return BFD_RELOC_32_GOT_PCREL;
667 }
668 break;
669
670 case pic_got_off:
671 switch (size)
672 {
673 case 1:
674 return BFD_RELOC_8_GOTOFF;
675 case 2:
676 return BFD_RELOC_16_GOTOFF;
677 case 4:
678 return BFD_RELOC_32_GOTOFF;
679 }
680 break;
681
682 case pic_plt_pcrel:
683 switch (size)
684 {
685 case 1:
686 return BFD_RELOC_8_PLT_PCREL;
687 case 2:
688 return BFD_RELOC_16_PLT_PCREL;
689 case 4:
690 return BFD_RELOC_32_PLT_PCREL;
691 }
692 break;
693
694 case pic_plt_off:
695 switch (size)
696 {
697 case 1:
698 return BFD_RELOC_8_PLTOFF;
699 case 2:
700 return BFD_RELOC_16_PLTOFF;
701 case 4:
702 return BFD_RELOC_32_PLTOFF;
703 }
704 break;
705
706 case pic_none:
707 if (pcrel)
708 {
709 switch (size)
710 {
711 case 1:
712 return BFD_RELOC_8_PCREL;
713 case 2:
714 return BFD_RELOC_16_PCREL;
715 case 4:
716 return BFD_RELOC_32_PCREL;
717 }
718 }
719 else
720 {
721 switch (size)
722 {
723 case 1:
724 return BFD_RELOC_8;
725 case 2:
726 return BFD_RELOC_16;
727 case 4:
728 return BFD_RELOC_32;
729 }
730 }
731 }
732
733 as_bad ("Can not do %d byte %s%srelocation", size,
734 pcrel ? "pc-relative " : "",
735 pic == pic_none ? "" : "pic ");
736 return BFD_RELOC_NONE;
737 }
738
739 /* Here we decide which fixups can be adjusted to make them relative
740 to the beginning of the section instead of the symbol. Basically
741 we need to make sure that the dynamic relocations are done
742 correctly, so in some cases we force the original symbol to be
743 used. */
744 int
745 tc_m68k_fix_adjustable (fixP)
746 fixS *fixP;
747 {
748 /* Prevent all adjustments to global symbols. */
749 if (S_IS_EXTERNAL (fixP->fx_addsy))
750 return 0;
751
752 /* adjust_reloc_syms doesn't know about the GOT */
753 switch (fixP->fx_r_type)
754 {
755 case BFD_RELOC_8_GOT_PCREL:
756 case BFD_RELOC_16_GOT_PCREL:
757 case BFD_RELOC_32_GOT_PCREL:
758 case BFD_RELOC_8_GOTOFF:
759 case BFD_RELOC_16_GOTOFF:
760 case BFD_RELOC_32_GOTOFF:
761 case BFD_RELOC_8_PLT_PCREL:
762 case BFD_RELOC_16_PLT_PCREL:
763 case BFD_RELOC_32_PLT_PCREL:
764 case BFD_RELOC_8_PLTOFF:
765 case BFD_RELOC_16_PLTOFF:
766 case BFD_RELOC_32_PLTOFF:
767 return 0;
768
769 default:
770 return 1;
771 }
772 }
773
774 #else /* !OBJ_ELF */
775
776 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
777
778 #endif /* OBJ_ELF */
779
780 #ifdef BFD_ASSEMBLER
781
782 arelent *
783 tc_gen_reloc (section, fixp)
784 asection *section;
785 fixS *fixp;
786 {
787 arelent *reloc;
788 bfd_reloc_code_real_type code;
789
790 if (fixp->fx_tcbit)
791 abort ();
792
793 if (fixp->fx_r_type != BFD_RELOC_NONE)
794 {
795 code = fixp->fx_r_type;
796
797 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
798 that fixup_segment converted a non-PC relative reloc into a
799 PC relative reloc. In such a case, we need to convert the
800 reloc code. */
801 if (fixp->fx_pcrel)
802 {
803 switch (code)
804 {
805 case BFD_RELOC_8:
806 code = BFD_RELOC_8_PCREL;
807 break;
808 case BFD_RELOC_16:
809 code = BFD_RELOC_16_PCREL;
810 break;
811 case BFD_RELOC_32:
812 code = BFD_RELOC_32_PCREL;
813 break;
814 case BFD_RELOC_8_PCREL:
815 case BFD_RELOC_16_PCREL:
816 case BFD_RELOC_32_PCREL:
817 case BFD_RELOC_8_GOT_PCREL:
818 case BFD_RELOC_16_GOT_PCREL:
819 case BFD_RELOC_32_GOT_PCREL:
820 case BFD_RELOC_8_GOTOFF:
821 case BFD_RELOC_16_GOTOFF:
822 case BFD_RELOC_32_GOTOFF:
823 case BFD_RELOC_8_PLT_PCREL:
824 case BFD_RELOC_16_PLT_PCREL:
825 case BFD_RELOC_32_PLT_PCREL:
826 case BFD_RELOC_8_PLTOFF:
827 case BFD_RELOC_16_PLTOFF:
828 case BFD_RELOC_32_PLTOFF:
829 break;
830 default:
831 as_bad_where (fixp->fx_file, fixp->fx_line,
832 "Cannot make %s relocation PC relative",
833 bfd_get_reloc_code_name (code));
834 }
835 }
836 }
837 else
838 {
839 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
840 switch (F (fixp->fx_size, fixp->fx_pcrel))
841 {
842 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
843 MAP (1, 0, BFD_RELOC_8);
844 MAP (2, 0, BFD_RELOC_16);
845 MAP (4, 0, BFD_RELOC_32);
846 MAP (1, 1, BFD_RELOC_8_PCREL);
847 MAP (2, 1, BFD_RELOC_16_PCREL);
848 MAP (4, 1, BFD_RELOC_32_PCREL);
849 default:
850 abort ();
851 }
852 }
853 #undef F
854 #undef MAP
855
856 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
857 assert (reloc != 0);
858 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
859 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
860 #ifndef OBJ_ELF
861 if (fixp->fx_pcrel)
862 reloc->addend = fixp->fx_addnumber;
863 else
864 reloc->addend = 0;
865 #else
866 if (!fixp->fx_pcrel)
867 reloc->addend = fixp->fx_addnumber;
868 else
869 reloc->addend = (section->vma
870 + (fixp->fx_pcrel_adjust == 64
871 ? -1 : fixp->fx_pcrel_adjust)
872 + fixp->fx_addnumber
873 + md_pcrel_from (fixp));
874 #endif
875
876 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
877 assert (reloc->howto != 0);
878
879 return reloc;
880 }
881
882 #endif /* BFD_ASSEMBLER */
883
884 /* Handle of the OPCODE hash table. NULL means any use before
885 m68k_ip_begin() will crash. */
886 static struct hash_control *op_hash;
887 \f
888 /* Assemble an m68k instruction. */
889
890 void
891 m68k_ip (instring)
892 char *instring;
893 {
894 register char *p;
895 register struct m68k_op *opP;
896 register struct m68k_incant *opcode;
897 register const char *s;
898 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
899 char *pdot, *pdotmove;
900 enum m68k_size siz1, siz2;
901 char c;
902 int losing;
903 int opsfound;
904 char *crack_operand ();
905 LITTLENUM_TYPE words[6];
906 LITTLENUM_TYPE *wordp;
907 unsigned long ok_arch = 0;
908
909 if (*instring == ' ')
910 instring++; /* skip leading whitespace */
911
912 /* Scan up to end of operation-code, which MUST end in end-of-string
913 or exactly 1 space. */
914 pdot = 0;
915 for (p = instring; *p != '\0'; p++)
916 {
917 if (*p == ' ')
918 break;
919 if (*p == '.')
920 pdot = p;
921 }
922
923 if (p == instring)
924 {
925 the_ins.error = "No operator";
926 return;
927 }
928
929 /* p now points to the end of the opcode name, probably whitespace.
930 Make sure the name is null terminated by clobbering the
931 whitespace, look it up in the hash table, then fix it back.
932 Remove a dot, first, since the opcode tables have none. */
933 if (pdot != NULL)
934 {
935 for (pdotmove = pdot; pdotmove < p; pdotmove++)
936 *pdotmove = pdotmove[1];
937 p--;
938 }
939
940 c = *p;
941 *p = '\0';
942 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
943 *p = c;
944
945 if (pdot != NULL)
946 {
947 for (pdotmove = p; pdotmove > pdot; pdotmove--)
948 *pdotmove = pdotmove[-1];
949 *pdot = '.';
950 ++p;
951 }
952
953 if (opcode == NULL)
954 {
955 the_ins.error = "Unknown operator";
956 return;
957 }
958
959 /* found a legitimate opcode, start matching operands */
960 while (*p == ' ')
961 ++p;
962
963 if (opcode->m_operands == 0)
964 {
965 char *old = input_line_pointer;
966 *old = '\n';
967 input_line_pointer = p;
968 /* Ahh - it's a motorola style psuedo op */
969 mote_pseudo_table[opcode->m_opnum].poc_handler
970 (mote_pseudo_table[opcode->m_opnum].poc_val);
971 input_line_pointer = old;
972 *old = 0;
973
974 return;
975 }
976
977 if (flag_mri && opcode->m_opnum == 0)
978 {
979 /* In MRI mode, random garbage is allowed after an instruction
980 which accepts no operands. */
981 the_ins.args = opcode->m_operands;
982 the_ins.numargs = opcode->m_opnum;
983 the_ins.numo = opcode->m_codenum;
984 the_ins.opcode[0] = getone (opcode);
985 the_ins.opcode[1] = gettwo (opcode);
986 return;
987 }
988
989 for (opP = &the_ins.operands[0]; *p; opP++)
990 {
991 p = crack_operand (p, opP);
992
993 if (opP->error)
994 {
995 the_ins.error = opP->error;
996 return;
997 }
998 }
999
1000 opsfound = opP - &the_ins.operands[0];
1001
1002 /* This ugly hack is to support the floating pt opcodes in their
1003 standard form. Essentially, we fake a first enty of type COP#1 */
1004 if (opcode->m_operands[0] == 'I')
1005 {
1006 int n;
1007
1008 for (n = opsfound; n > 0; --n)
1009 the_ins.operands[n] = the_ins.operands[n - 1];
1010
1011 memset ((char *) (&the_ins.operands[0]), '\0',
1012 sizeof (the_ins.operands[0]));
1013 the_ins.operands[0].mode = CONTROL;
1014 the_ins.operands[0].reg = m68k_float_copnum;
1015 opsfound++;
1016 }
1017
1018 /* We've got the operands. Find an opcode that'll accept them */
1019 for (losing = 0;;)
1020 {
1021 /* If we didn't get the right number of ops, or we have no
1022 common model with this pattern then reject this pattern. */
1023
1024 ok_arch |= opcode->m_arch;
1025 if (opsfound != opcode->m_opnum
1026 || ((opcode->m_arch & current_architecture) == 0))
1027 ++losing;
1028 else
1029 {
1030 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1031 *s && !losing;
1032 s += 2, opP++)
1033 {
1034 /* Warning: this switch is huge! */
1035 /* I've tried to organize the cases into this order:
1036 non-alpha first, then alpha by letter. Lower-case
1037 goes directly before uppercase counterpart. */
1038 /* Code with multiple case ...: gets sorted by the lowest
1039 case ... it belongs to. I hope this makes sense. */
1040 switch (*s)
1041 {
1042 case '!':
1043 switch (opP->mode)
1044 {
1045 case IMMED:
1046 case DREG:
1047 case AREG:
1048 case FPREG:
1049 case CONTROL:
1050 case AINC:
1051 case ADEC:
1052 case REGLST:
1053 losing++;
1054 break;
1055 default:
1056 break;
1057 }
1058 break;
1059
1060 case '`':
1061 switch (opP->mode)
1062 {
1063 case IMMED:
1064 case DREG:
1065 case AREG:
1066 case FPREG:
1067 case CONTROL:
1068 case AINC:
1069 case REGLST:
1070 case AINDR:
1071 losing++;
1072 break;
1073 default:
1074 break;
1075 }
1076 break;
1077
1078 case '<':
1079 switch (opP->mode)
1080 {
1081 case DREG:
1082 case AREG:
1083 case FPREG:
1084 case CONTROL:
1085 case IMMED:
1086 case ADEC:
1087 case REGLST:
1088 losing++;
1089 break;
1090 default:
1091 break;
1092 }
1093 break;
1094
1095 case '>':
1096 switch (opP->mode)
1097 {
1098 case DREG:
1099 case AREG:
1100 case FPREG:
1101 case CONTROL:
1102 case IMMED:
1103 case AINC:
1104 case REGLST:
1105 losing++;
1106 break;
1107 case ABSL:
1108 break;
1109 default:
1110 if (opP->reg == PC
1111 || opP->reg == ZPC)
1112 losing++;
1113 break;
1114 }
1115 break;
1116
1117 case 'm':
1118 switch (opP->mode)
1119 {
1120 case DREG:
1121 case AREG:
1122 case AINDR:
1123 case AINC:
1124 case ADEC:
1125 break;
1126 default:
1127 losing++;
1128 }
1129 break;
1130
1131 case 'n':
1132 switch (opP->mode)
1133 {
1134 case DISP:
1135 break;
1136 default:
1137 losing++;
1138 }
1139 break;
1140
1141 case 'o':
1142 switch (opP->mode)
1143 {
1144 case BASE:
1145 case ABSL:
1146 case IMMED:
1147 break;
1148 default:
1149 losing++;
1150 }
1151 break;
1152
1153 case 'p':
1154 switch (opP->mode)
1155 {
1156 case DREG:
1157 case AREG:
1158 case AINDR:
1159 case AINC:
1160 case ADEC:
1161 case DISP:
1162 break;
1163 default:
1164 losing++;
1165 }
1166 break;
1167
1168 case '#':
1169 if (opP->mode != IMMED)
1170 losing++;
1171 else if (s[1] == 'b'
1172 && ! isvar (&opP->disp)
1173 && (opP->disp.exp.X_op != O_constant
1174 || ! isbyte (opP->disp.exp.X_add_number)))
1175 losing++;
1176 else if (s[1] == 'B'
1177 && ! isvar (&opP->disp)
1178 && (opP->disp.exp.X_op != O_constant
1179 || ! issbyte (opP->disp.exp.X_add_number)))
1180 losing++;
1181 else if (s[1] == 'w'
1182 && ! isvar (&opP->disp)
1183 && (opP->disp.exp.X_op != O_constant
1184 || ! isword (opP->disp.exp.X_add_number)))
1185 losing++;
1186 else if (s[1] == 'W'
1187 && ! isvar (&opP->disp)
1188 && (opP->disp.exp.X_op != O_constant
1189 || ! issword (opP->disp.exp.X_add_number)))
1190 losing++;
1191 break;
1192
1193 case '^':
1194 case 'T':
1195 if (opP->mode != IMMED)
1196 losing++;
1197 break;
1198
1199 case '$':
1200 if (opP->mode == AREG
1201 || opP->mode == CONTROL
1202 || opP->mode == FPREG
1203 || opP->mode == IMMED
1204 || opP->mode == REGLST
1205 || (opP->mode != ABSL
1206 && (opP->reg == PC
1207 || opP->reg == ZPC)))
1208 losing++;
1209 break;
1210
1211 case '%':
1212 if (opP->mode == CONTROL
1213 || opP->mode == FPREG
1214 || opP->mode == REGLST
1215 || opP->mode == IMMED
1216 || (opP->mode != ABSL
1217 && (opP->reg == PC
1218 || opP->reg == ZPC)))
1219 losing++;
1220 break;
1221
1222 case '&':
1223 switch (opP->mode)
1224 {
1225 case DREG:
1226 case AREG:
1227 case FPREG:
1228 case CONTROL:
1229 case IMMED:
1230 case AINC:
1231 case ADEC:
1232 case REGLST:
1233 losing++;
1234 break;
1235 case ABSL:
1236 break;
1237 default:
1238 if (opP->reg == PC
1239 || opP->reg == ZPC)
1240 losing++;
1241 break;
1242 }
1243 break;
1244
1245 case '*':
1246 if (opP->mode == CONTROL
1247 || opP->mode == FPREG
1248 || opP->mode == REGLST)
1249 losing++;
1250 break;
1251
1252 case '+':
1253 if (opP->mode != AINC)
1254 losing++;
1255 break;
1256
1257 case '-':
1258 if (opP->mode != ADEC)
1259 losing++;
1260 break;
1261
1262 case '/':
1263 switch (opP->mode)
1264 {
1265 case AREG:
1266 case CONTROL:
1267 case FPREG:
1268 case AINC:
1269 case ADEC:
1270 case IMMED:
1271 case REGLST:
1272 losing++;
1273 break;
1274 default:
1275 break;
1276 }
1277 break;
1278
1279 case ';':
1280 switch (opP->mode)
1281 {
1282 case AREG:
1283 case CONTROL:
1284 case FPREG:
1285 case REGLST:
1286 losing++;
1287 break;
1288 default:
1289 break;
1290 }
1291 break;
1292
1293 case '?':
1294 switch (opP->mode)
1295 {
1296 case AREG:
1297 case CONTROL:
1298 case FPREG:
1299 case AINC:
1300 case ADEC:
1301 case IMMED:
1302 case REGLST:
1303 losing++;
1304 break;
1305 case ABSL:
1306 break;
1307 default:
1308 if (opP->reg == PC || opP->reg == ZPC)
1309 losing++;
1310 break;
1311 }
1312 break;
1313
1314 case '@':
1315 switch (opP->mode)
1316 {
1317 case AREG:
1318 case CONTROL:
1319 case FPREG:
1320 case IMMED:
1321 case REGLST:
1322 losing++;
1323 break;
1324 default:
1325 break;
1326 }
1327 break;
1328
1329 case '~': /* For now! (JF FOO is this right?) */
1330 switch (opP->mode)
1331 {
1332 case DREG:
1333 case AREG:
1334 case CONTROL:
1335 case FPREG:
1336 case IMMED:
1337 case REGLST:
1338 losing++;
1339 break;
1340 case ABSL:
1341 break;
1342 default:
1343 if (opP->reg == PC
1344 || opP->reg == ZPC)
1345 losing++;
1346 break;
1347 }
1348 break;
1349
1350 case '3':
1351 if (opP->mode != CONTROL
1352 || (opP->reg != TT0 && opP->reg != TT1))
1353 losing++;
1354 break;
1355
1356 case 'A':
1357 if (opP->mode != AREG)
1358 losing++;
1359 break;
1360
1361 case 'a':
1362 if (opP->mode != AINDR)
1363 ++losing;
1364 break;
1365
1366 case 'B': /* FOO */
1367 if (opP->mode != ABSL
1368 || (flag_long_jumps
1369 && strncmp (instring, "jbsr", 4) == 0))
1370 losing++;
1371 break;
1372
1373 case 'C':
1374 if (opP->mode != CONTROL || opP->reg != CCR)
1375 losing++;
1376 break;
1377
1378 case 'd':
1379 if (opP->mode != DISP
1380 || opP->reg < ADDR0
1381 || opP->reg > ADDR7)
1382 losing++;
1383 break;
1384
1385 case 'D':
1386 if (opP->mode != DREG)
1387 losing++;
1388 break;
1389
1390 case 'F':
1391 if (opP->mode != FPREG)
1392 losing++;
1393 break;
1394
1395 case 'I':
1396 if (opP->mode != CONTROL
1397 || opP->reg < COP0
1398 || opP->reg > COP7)
1399 losing++;
1400 break;
1401
1402 case 'J':
1403 if (opP->mode != CONTROL
1404 || opP->reg < USP
1405 || opP->reg > last_movec_reg)
1406 losing++;
1407 else
1408 {
1409 const enum m68k_register *rp;
1410 for (rp = control_regs; *rp; rp++)
1411 if (*rp == opP->reg)
1412 break;
1413 if (*rp == 0)
1414 losing++;
1415 }
1416 break;
1417
1418 case 'k':
1419 if (opP->mode != IMMED)
1420 losing++;
1421 break;
1422
1423 case 'l':
1424 case 'L':
1425 if (opP->mode == DREG
1426 || opP->mode == AREG
1427 || opP->mode == FPREG)
1428 {
1429 if (s[1] == '8')
1430 losing++;
1431 else
1432 {
1433 switch (opP->mode)
1434 {
1435 case DREG:
1436 opP->mask = 1 << (opP->reg - DATA0);
1437 break;
1438 case AREG:
1439 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1440 break;
1441 case FPREG:
1442 opP->mask = 1 << (opP->reg - FP0 + 16);
1443 break;
1444 default:
1445 abort ();
1446 }
1447 opP->mode = REGLST;
1448 }
1449 }
1450 else if (opP->mode == CONTROL)
1451 {
1452 if (s[1] != '8')
1453 losing++;
1454 else
1455 {
1456 switch (opP->reg)
1457 {
1458 case FPI:
1459 opP->mask = 1 << 24;
1460 break;
1461 case FPS:
1462 opP->mask = 1 << 25;
1463 break;
1464 case FPC:
1465 opP->mask = 1 << 26;
1466 break;
1467 default:
1468 losing++;
1469 break;
1470 }
1471 opP->mode = REGLST;
1472 }
1473 }
1474 else if (opP->mode == ABSL
1475 && opP->disp.size == SIZE_UNSPEC
1476 && opP->disp.exp.X_op == O_constant)
1477 {
1478 /* This is what the MRI REG pseudo-op generates. */
1479 opP->mode = REGLST;
1480 opP->mask = opP->disp.exp.X_add_number;
1481 }
1482 else if (opP->mode != REGLST)
1483 losing++;
1484 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1485 losing++;
1486 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1487 losing++;
1488 break;
1489
1490 case 'M':
1491 if (opP->mode != IMMED)
1492 losing++;
1493 else if (opP->disp.exp.X_op != O_constant
1494 || ! issbyte (opP->disp.exp.X_add_number))
1495 losing++;
1496 else if (! m68k_quick
1497 && instring[3] != 'q'
1498 && instring[4] != 'q')
1499 losing++;
1500 break;
1501
1502 case 'O':
1503 if (opP->mode != DREG
1504 && opP->mode != IMMED
1505 && opP->mode != ABSL)
1506 losing++;
1507 break;
1508
1509 case 'Q':
1510 if (opP->mode != IMMED)
1511 losing++;
1512 else if (opP->disp.exp.X_op != O_constant
1513 || opP->disp.exp.X_add_number < 1
1514 || opP->disp.exp.X_add_number > 8)
1515 losing++;
1516 else if (! m68k_quick
1517 && (strncmp (instring, "add", 3) == 0
1518 || strncmp (instring, "sub", 3) == 0)
1519 && instring[3] != 'q')
1520 losing++;
1521 break;
1522
1523 case 'R':
1524 if (opP->mode != DREG && opP->mode != AREG)
1525 losing++;
1526 break;
1527
1528 case 'r':
1529 if (opP->mode != AINDR
1530 && (opP->mode != BASE
1531 || (opP->reg != 0
1532 && opP->reg != ZADDR0)
1533 || opP->disp.exp.X_op != O_absent
1534 || ((opP->index.reg < DATA0
1535 || opP->index.reg > DATA7)
1536 && (opP->index.reg < ADDR0
1537 || opP->index.reg > ADDR7))
1538 || opP->index.size != SIZE_UNSPEC
1539 || opP->index.scale != 1))
1540 losing++;
1541 break;
1542
1543 case 's':
1544 if (opP->mode != CONTROL
1545 || ! (opP->reg == FPI
1546 || opP->reg == FPS
1547 || opP->reg == FPC))
1548 losing++;
1549 break;
1550
1551 case 'S':
1552 if (opP->mode != CONTROL || opP->reg != SR)
1553 losing++;
1554 break;
1555
1556 case 't':
1557 if (opP->mode != IMMED)
1558 losing++;
1559 else if (opP->disp.exp.X_op != O_constant
1560 || opP->disp.exp.X_add_number < 0
1561 || opP->disp.exp.X_add_number > 7)
1562 losing++;
1563 break;
1564
1565 case 'U':
1566 if (opP->mode != CONTROL || opP->reg != USP)
1567 losing++;
1568 break;
1569
1570 /* JF these are out of order. We could put them
1571 in order if we were willing to put up with
1572 bunches of #ifdef m68851s in the code.
1573
1574 Don't forget that you need these operands
1575 to use 68030 MMU instructions. */
1576 #ifndef NO_68851
1577 /* Memory addressing mode used by pflushr */
1578 case '|':
1579 if (opP->mode == CONTROL
1580 || opP->mode == FPREG
1581 || opP->mode == DREG
1582 || opP->mode == AREG
1583 || opP->mode == REGLST)
1584 losing++;
1585 /* We should accept immediate operands, but they
1586 supposedly have to be quad word, and we don't
1587 handle that. I would like to see what a Motorola
1588 assembler does before doing something here. */
1589 if (opP->mode == IMMED)
1590 losing++;
1591 break;
1592
1593 case 'f':
1594 if (opP->mode != CONTROL
1595 || (opP->reg != SFC && opP->reg != DFC))
1596 losing++;
1597 break;
1598
1599 case '0':
1600 if (opP->mode != CONTROL || opP->reg != TC)
1601 losing++;
1602 break;
1603
1604 case '1':
1605 if (opP->mode != CONTROL || opP->reg != AC)
1606 losing++;
1607 break;
1608
1609 case '2':
1610 if (opP->mode != CONTROL
1611 || (opP->reg != CAL
1612 && opP->reg != VAL
1613 && opP->reg != SCC))
1614 losing++;
1615 break;
1616
1617 case 'V':
1618 if (opP->mode != CONTROL
1619 || opP->reg != VAL)
1620 losing++;
1621 break;
1622
1623 case 'W':
1624 if (opP->mode != CONTROL
1625 || (opP->reg != DRP
1626 && opP->reg != SRP
1627 && opP->reg != CRP))
1628 losing++;
1629 break;
1630
1631 case 'X':
1632 if (opP->mode != CONTROL
1633 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1634 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1635 losing++;
1636 break;
1637
1638 case 'Y':
1639 if (opP->mode != CONTROL || opP->reg != PSR)
1640 losing++;
1641 break;
1642
1643 case 'Z':
1644 if (opP->mode != CONTROL || opP->reg != PCSR)
1645 losing++;
1646 break;
1647 #endif
1648 case 'c':
1649 if (opP->mode != CONTROL
1650 || (opP->reg != NC
1651 && opP->reg != IC
1652 && opP->reg != DC
1653 && opP->reg != BC))
1654 {
1655 losing++;
1656 } /* not a cache specifier. */
1657 break;
1658
1659 case '_':
1660 if (opP->mode != ABSL)
1661 ++losing;
1662 break;
1663
1664 default:
1665 abort ();
1666 } /* switch on type of operand */
1667
1668 if (losing)
1669 break;
1670 } /* for each operand */
1671 } /* if immediately wrong */
1672
1673 if (!losing)
1674 {
1675 break;
1676 } /* got it. */
1677
1678 opcode = opcode->m_next;
1679
1680 if (!opcode)
1681 {
1682 if (ok_arch
1683 && !(ok_arch & current_architecture))
1684 {
1685 char buf[200], *cp;
1686
1687 strcpy (buf,
1688 "invalid instruction for this architecture; needs ");
1689 cp = buf + strlen (buf);
1690 switch (ok_arch)
1691 {
1692 case mfloat:
1693 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1694 break;
1695 case mmmu:
1696 strcpy (cp, "mmu (68030 or 68851)");
1697 break;
1698 case m68020up:
1699 strcpy (cp, "68020 or higher");
1700 break;
1701 case m68000up:
1702 strcpy (cp, "68000 or higher");
1703 break;
1704 case m68010up:
1705 strcpy (cp, "68010 or higher");
1706 break;
1707 default:
1708 {
1709 int got_one = 0, idx;
1710 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1711 idx++)
1712 {
1713 if ((archs[idx].arch & ok_arch)
1714 && ! archs[idx].alias)
1715 {
1716 if (got_one)
1717 {
1718 strcpy (cp, " or ");
1719 cp += strlen (cp);
1720 }
1721 got_one = 1;
1722 strcpy (cp, archs[idx].name);
1723 cp += strlen (cp);
1724 }
1725 }
1726 }
1727 }
1728 cp = xmalloc (strlen (buf) + 1);
1729 strcpy (cp, buf);
1730 the_ins.error = cp;
1731 }
1732 else
1733 the_ins.error = "operands mismatch";
1734 return;
1735 } /* Fell off the end */
1736
1737 losing = 0;
1738 }
1739
1740 /* now assemble it */
1741
1742 the_ins.args = opcode->m_operands;
1743 the_ins.numargs = opcode->m_opnum;
1744 the_ins.numo = opcode->m_codenum;
1745 the_ins.opcode[0] = getone (opcode);
1746 the_ins.opcode[1] = gettwo (opcode);
1747
1748 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1749 {
1750 /* This switch is a doozy.
1751 Watch the first step; its a big one! */
1752 switch (s[0])
1753 {
1754
1755 case '*':
1756 case '~':
1757 case '%':
1758 case ';':
1759 case '@':
1760 case '!':
1761 case '&':
1762 case '$':
1763 case '?':
1764 case '/':
1765 case '`':
1766 case '<':
1767 case '>':
1768 case 'm':
1769 case 'n':
1770 case 'o':
1771 case 'p':
1772 #ifndef NO_68851
1773 case '|':
1774 #endif
1775 switch (opP->mode)
1776 {
1777 case IMMED:
1778 tmpreg = 0x3c; /* 7.4 */
1779 if (strchr ("bwl", s[1]))
1780 nextword = get_num (&opP->disp, 80);
1781 else
1782 nextword = get_num (&opP->disp, 0);
1783 if (isvar (&opP->disp))
1784 add_fix (s[1], &opP->disp, 0, 0);
1785 switch (s[1])
1786 {
1787 case 'b':
1788 if (!isbyte (nextword))
1789 opP->error = "operand out of range";
1790 addword (nextword);
1791 baseo = 0;
1792 break;
1793 case 'w':
1794 if (!isword (nextword))
1795 opP->error = "operand out of range";
1796 addword (nextword);
1797 baseo = 0;
1798 break;
1799 case 'W':
1800 if (!issword (nextword))
1801 opP->error = "operand out of range";
1802 addword (nextword);
1803 baseo = 0;
1804 break;
1805 case 'l':
1806 addword (nextword >> 16);
1807 addword (nextword);
1808 baseo = 0;
1809 break;
1810
1811 case 'f':
1812 baseo = 2;
1813 outro = 8;
1814 break;
1815 case 'F':
1816 baseo = 4;
1817 outro = 11;
1818 break;
1819 case 'x':
1820 baseo = 6;
1821 outro = 15;
1822 break;
1823 case 'p':
1824 baseo = 6;
1825 outro = -1;
1826 break;
1827 default:
1828 abort ();
1829 }
1830 if (!baseo)
1831 break;
1832
1833 /* We gotta put out some float */
1834 if (op (&opP->disp) != O_big)
1835 {
1836 valueT val;
1837 int gencnt;
1838
1839 /* Can other cases happen here? */
1840 if (op (&opP->disp) != O_constant)
1841 abort ();
1842
1843 val = (valueT) offs (&opP->disp);
1844 gencnt = 0;
1845 do
1846 {
1847 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1848 val >>= LITTLENUM_NUMBER_OF_BITS;
1849 ++gencnt;
1850 }
1851 while (val != 0);
1852 offs (&opP->disp) = gencnt;
1853 }
1854 if (offs (&opP->disp) > 0)
1855 {
1856 if (offs (&opP->disp) > baseo)
1857 {
1858 as_warn ("Bignum too big for %c format; truncated",
1859 s[1]);
1860 offs (&opP->disp) = baseo;
1861 }
1862 baseo -= offs (&opP->disp);
1863 while (baseo--)
1864 addword (0);
1865 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1866 offs (&opP->disp)--;
1867 --wordp)
1868 addword (*wordp);
1869 break;
1870 }
1871 gen_to_words (words, baseo, (long) outro);
1872 for (wordp = words; baseo--; wordp++)
1873 addword (*wordp);
1874 break;
1875 case DREG:
1876 tmpreg = opP->reg - DATA; /* 0.dreg */
1877 break;
1878 case AREG:
1879 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1880 break;
1881 case AINDR:
1882 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1883 break;
1884 case ADEC:
1885 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1886 break;
1887 case AINC:
1888 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1889 break;
1890 case DISP:
1891
1892 nextword = get_num (&opP->disp, 80);
1893
1894 if (opP->reg == PC
1895 && ! isvar (&opP->disp)
1896 && m68k_abspcadd)
1897 {
1898 opP->disp.exp.X_op = O_symbol;
1899 #ifndef BFD_ASSEMBLER
1900 opP->disp.exp.X_add_symbol = &abs_symbol;
1901 #else
1902 opP->disp.exp.X_add_symbol =
1903 section_symbol (absolute_section);
1904 #endif
1905 }
1906
1907 /* Force into index mode. Hope this works */
1908
1909 /* We do the first bit for 32-bit displacements, and the
1910 second bit for 16 bit ones. It is possible that we
1911 should make the default be WORD instead of LONG, but
1912 I think that'd break GCC, so we put up with a little
1913 inefficiency for the sake of working output. */
1914
1915 if (!issword (nextword)
1916 || (isvar (&opP->disp)
1917 && ((opP->disp.size == SIZE_UNSPEC
1918 && flag_short_refs == 0
1919 && cpu_of_arch (current_architecture) >= m68020)
1920 || opP->disp.size == SIZE_LONG)))
1921 {
1922 if (cpu_of_arch (current_architecture) < m68020)
1923 opP->error =
1924 "displacement too large for this architecture; needs 68020 or higher";
1925 if (opP->reg == PC)
1926 tmpreg = 0x3B; /* 7.3 */
1927 else
1928 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1929 if (isvar (&opP->disp))
1930 {
1931 if (opP->reg == PC)
1932 {
1933 if (opP->disp.size == SIZE_LONG
1934 #ifdef OBJ_ELF
1935 /* If the displacement needs pic
1936 relocation it cannot be relaxed. */
1937 || opP->disp.pic_reloc != pic_none
1938 #endif
1939 )
1940 {
1941 addword (0x0170);
1942 add_fix ('l', &opP->disp, 1, 2);
1943 }
1944 else
1945 {
1946 add_frag (adds (&opP->disp),
1947 offs (&opP->disp),
1948 TAB (PCLEA, SZ_UNDEF));
1949 break;
1950 }
1951 }
1952 else
1953 {
1954 addword (0x0170);
1955 add_fix ('l', &opP->disp, 0, 0);
1956 }
1957 }
1958 else
1959 addword (0x0170);
1960 addword (nextword >> 16);
1961 }
1962 else
1963 {
1964 if (opP->reg == PC)
1965 tmpreg = 0x3A; /* 7.2 */
1966 else
1967 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1968
1969 if (isvar (&opP->disp))
1970 {
1971 if (opP->reg == PC)
1972 {
1973 add_fix ('w', &opP->disp, 1, 0);
1974 }
1975 else
1976 add_fix ('w', &opP->disp, 0, 0);
1977 }
1978 }
1979 addword (nextword);
1980 break;
1981
1982 case POST:
1983 case PRE:
1984 case BASE:
1985 nextword = 0;
1986 baseo = get_num (&opP->disp, 80);
1987 if (opP->mode == POST || opP->mode == PRE)
1988 outro = get_num (&opP->odisp, 80);
1989 /* Figure out the `addressing mode'.
1990 Also turn on the BASE_DISABLE bit, if needed. */
1991 if (opP->reg == PC || opP->reg == ZPC)
1992 {
1993 tmpreg = 0x3b; /* 7.3 */
1994 if (opP->reg == ZPC)
1995 nextword |= 0x80;
1996 }
1997 else if (opP->reg == 0)
1998 {
1999 nextword |= 0x80;
2000 tmpreg = 0x30; /* 6.garbage */
2001 }
2002 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2003 {
2004 nextword |= 0x80;
2005 tmpreg = 0x30 + opP->reg - ZADDR0;
2006 }
2007 else
2008 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2009
2010 siz1 = opP->disp.size;
2011 if (opP->mode == POST || opP->mode == PRE)
2012 siz2 = opP->odisp.size;
2013 else
2014 siz2 = SIZE_UNSPEC;
2015
2016 /* Index register stuff */
2017 if (opP->index.reg != 0
2018 && opP->index.reg >= DATA
2019 && opP->index.reg <= ADDR7)
2020 {
2021 nextword |= (opP->index.reg - DATA) << 12;
2022
2023 if (opP->index.size == SIZE_LONG
2024 || (opP->index.size == SIZE_UNSPEC
2025 && m68k_index_width_default == SIZE_LONG))
2026 nextword |= 0x800;
2027
2028 if ((opP->index.scale != 1
2029 && cpu_of_arch (current_architecture) < m68020)
2030 || (opP->index.scale == 8
2031 && current_architecture == mcf5200))
2032 {
2033 opP->error =
2034 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2035 }
2036
2037 switch (opP->index.scale)
2038 {
2039 case 1:
2040 break;
2041 case 2:
2042 nextword |= 0x200;
2043 break;
2044 case 4:
2045 nextword |= 0x400;
2046 break;
2047 case 8:
2048 nextword |= 0x600;
2049 break;
2050 default:
2051 abort ();
2052 }
2053 /* IF its simple,
2054 GET US OUT OF HERE! */
2055
2056 /* Must be INDEX, with an index register. Address
2057 register cannot be ZERO-PC, and either :b was
2058 forced, or we know it will fit. For a 68000 or
2059 68010, force this mode anyways, because the
2060 larger modes aren't supported. */
2061 if (opP->mode == BASE
2062 && ((opP->reg >= ADDR0
2063 && opP->reg <= ADDR7)
2064 || opP->reg == PC))
2065 {
2066 if (siz1 == SIZE_BYTE
2067 || cpu_of_arch (current_architecture) < m68020
2068 || (siz1 == SIZE_UNSPEC
2069 && ! isvar (&opP->disp)
2070 && issbyte (baseo)))
2071 {
2072 nextword += baseo & 0xff;
2073 addword (nextword);
2074 if (isvar (&opP->disp))
2075 {
2076 /* Do a byte relocation. If it doesn't
2077 fit (possible on m68000) let the
2078 fixup processing complain later. */
2079 if (opP->reg == PC)
2080 add_fix ('B', &opP->disp, 1, 1);
2081 else
2082 add_fix ('B', &opP->disp, 0, 0);
2083 }
2084 else if (siz1 != SIZE_BYTE)
2085 {
2086 if (siz1 != SIZE_UNSPEC)
2087 as_warn ("Forcing byte displacement");
2088 if (! issbyte (baseo))
2089 opP->error = "byte displacement out of range";
2090 }
2091
2092 break;
2093 }
2094 else if (siz1 == SIZE_UNSPEC
2095 && opP->reg == PC
2096 && isvar (&opP->disp)
2097 && subs (&opP->disp) == NULL
2098 #ifdef OBJ_ELF
2099 /* If the displacement needs pic
2100 relocation it cannot be relaxed. */
2101 && opP->disp.pic_reloc == pic_none
2102 #endif
2103 )
2104 {
2105 /* The code in md_convert_frag_1 needs to be
2106 able to adjust nextword. Call frag_grow
2107 to ensure that we have enough space in
2108 the frag obstack to make all the bytes
2109 contiguous. */
2110 frag_grow (14);
2111 nextword += baseo & 0xff;
2112 addword (nextword);
2113 add_frag (adds (&opP->disp), offs (&opP->disp),
2114 TAB (PCINDEX, SZ_UNDEF));
2115
2116 break;
2117 }
2118 }
2119 }
2120 else
2121 {
2122 nextword |= 0x40; /* No index reg */
2123 if (opP->index.reg >= ZDATA0
2124 && opP->index.reg <= ZDATA7)
2125 nextword |= (opP->index.reg - ZDATA0) << 12;
2126 else if (opP->index.reg >= ZADDR0
2127 || opP->index.reg <= ZADDR7)
2128 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2129 }
2130
2131 /* It isn't simple. */
2132
2133 if (cpu_of_arch (current_architecture) < m68020)
2134 opP->error =
2135 "invalid operand mode for this architecture; needs 68020 or higher";
2136
2137 nextword |= 0x100;
2138 /* If the guy specified a width, we assume that it is
2139 wide enough. Maybe it isn't. If so, we lose. */
2140 switch (siz1)
2141 {
2142 case SIZE_UNSPEC:
2143 if (isvar (&opP->disp)
2144 ? m68k_rel32
2145 : ! issword (baseo))
2146 {
2147 siz1 = SIZE_LONG;
2148 nextword |= 0x30;
2149 }
2150 else if (! isvar (&opP->disp) && baseo == 0)
2151 nextword |= 0x10;
2152 else
2153 {
2154 nextword |= 0x20;
2155 siz1 = SIZE_WORD;
2156 }
2157 break;
2158 case SIZE_BYTE:
2159 as_warn (":b not permitted; defaulting to :w");
2160 /* Fall through. */
2161 case SIZE_WORD:
2162 nextword |= 0x20;
2163 break;
2164 case SIZE_LONG:
2165 nextword |= 0x30;
2166 break;
2167 }
2168
2169 /* Figure out innner displacement stuff */
2170 if (opP->mode == POST || opP->mode == PRE)
2171 {
2172 if (cpu_of_arch (current_architecture) & cpu32)
2173 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2174 switch (siz2)
2175 {
2176 case SIZE_UNSPEC:
2177 if (isvar (&opP->odisp)
2178 ? m68k_rel32
2179 : ! issword (outro))
2180 {
2181 siz2 = SIZE_LONG;
2182 nextword |= 0x3;
2183 }
2184 else if (! isvar (&opP->odisp) && outro == 0)
2185 nextword |= 0x1;
2186 else
2187 {
2188 nextword |= 0x2;
2189 siz2 = SIZE_WORD;
2190 }
2191 break;
2192 case 1:
2193 as_warn (":b not permitted; defaulting to :w");
2194 /* Fall through. */
2195 case 2:
2196 nextword |= 0x2;
2197 break;
2198 case 3:
2199 nextword |= 0x3;
2200 break;
2201 }
2202 if (opP->mode == POST
2203 && (nextword & 0x40) == 0)
2204 nextword |= 0x04;
2205 }
2206 addword (nextword);
2207
2208 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2209 {
2210 if (opP->reg == PC || opP->reg == ZPC)
2211 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2212 else
2213 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2214 }
2215 if (siz1 == SIZE_LONG)
2216 addword (baseo >> 16);
2217 if (siz1 != SIZE_UNSPEC)
2218 addword (baseo);
2219
2220 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2221 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2222 if (siz2 == SIZE_LONG)
2223 addword (outro >> 16);
2224 if (siz2 != SIZE_UNSPEC)
2225 addword (outro);
2226
2227 break;
2228
2229 case ABSL:
2230 nextword = get_num (&opP->disp, 80);
2231 switch (opP->disp.size)
2232 {
2233 default:
2234 abort ();
2235 case SIZE_UNSPEC:
2236 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2237 {
2238 tmpreg = 0x38; /* 7.0 */
2239 addword (nextword);
2240 break;
2241 }
2242 /* Don't generate pc relative code on 68010 and
2243 68000. */
2244 if (isvar (&opP->disp)
2245 && !subs (&opP->disp)
2246 && adds (&opP->disp)
2247 #ifdef OBJ_ELF
2248 /* If the displacement needs pic relocation it
2249 cannot be relaxed. */
2250 && opP->disp.pic_reloc == pic_none
2251 #endif
2252 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2253 && cpu_of_arch (current_architecture) >= m68020
2254 && !flag_long_jumps
2255 && !strchr ("~%&$?", s[0]))
2256 {
2257 tmpreg = 0x3A; /* 7.2 */
2258 add_frag (adds (&opP->disp),
2259 offs (&opP->disp),
2260 TAB (PCREL, SZ_UNDEF));
2261 break;
2262 }
2263 /* Fall through into long */
2264 case SIZE_LONG:
2265 if (isvar (&opP->disp))
2266 add_fix ('l', &opP->disp, 0, 0);
2267
2268 tmpreg = 0x39;/* 7.1 mode */
2269 addword (nextword >> 16);
2270 addword (nextword);
2271 break;
2272
2273 case SIZE_WORD: /* Word */
2274 if (isvar (&opP->disp))
2275 add_fix ('w', &opP->disp, 0, 0);
2276
2277 tmpreg = 0x38;/* 7.0 mode */
2278 addword (nextword);
2279 break;
2280 }
2281 break;
2282 case CONTROL:
2283 case FPREG:
2284 default:
2285 as_bad ("unknown/incorrect operand");
2286 /* abort(); */
2287 }
2288 install_gen_operand (s[1], tmpreg);
2289 break;
2290
2291 case '#':
2292 case '^':
2293 switch (s[1])
2294 { /* JF: I hate floating point! */
2295 case 'j':
2296 tmpreg = 70;
2297 break;
2298 case '8':
2299 tmpreg = 20;
2300 break;
2301 case 'C':
2302 tmpreg = 50;
2303 break;
2304 case '3':
2305 default:
2306 tmpreg = 80;
2307 break;
2308 }
2309 tmpreg = get_num (&opP->disp, tmpreg);
2310 if (isvar (&opP->disp))
2311 add_fix (s[1], &opP->disp, 0, 0);
2312 switch (s[1])
2313 {
2314 case 'b': /* Danger: These do no check for
2315 certain types of overflow.
2316 user beware! */
2317 if (!isbyte (tmpreg))
2318 opP->error = "out of range";
2319 insop (tmpreg, opcode);
2320 if (isvar (&opP->disp))
2321 the_ins.reloc[the_ins.nrel - 1].n =
2322 (opcode->m_codenum) * 2 + 1;
2323 break;
2324 case 'B':
2325 if (!issbyte (tmpreg))
2326 opP->error = "out of range";
2327 opcode->m_opcode |= tmpreg;
2328 if (isvar (&opP->disp))
2329 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2330 break;
2331 case 'w':
2332 if (!isword (tmpreg))
2333 opP->error = "out of range";
2334 insop (tmpreg, opcode);
2335 if (isvar (&opP->disp))
2336 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2337 break;
2338 case 'W':
2339 if (!issword (tmpreg))
2340 opP->error = "out of range";
2341 insop (tmpreg, opcode);
2342 if (isvar (&opP->disp))
2343 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2344 break;
2345 case 'l':
2346 /* Because of the way insop works, we put these two out
2347 backwards. */
2348 insop (tmpreg, opcode);
2349 insop (tmpreg >> 16, opcode);
2350 if (isvar (&opP->disp))
2351 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2352 break;
2353 case '3':
2354 tmpreg &= 0xFF;
2355 case '8':
2356 case 'C':
2357 install_operand (s[1], tmpreg);
2358 break;
2359 default:
2360 abort ();
2361 }
2362 break;
2363
2364 case '+':
2365 case '-':
2366 case 'A':
2367 case 'a':
2368 install_operand (s[1], opP->reg - ADDR);
2369 break;
2370
2371 case 'B':
2372 tmpreg = get_num (&opP->disp, 80);
2373 switch (s[1])
2374 {
2375 case 'B':
2376 /* The pc_fix argument winds up in fx_pcrel_adjust,
2377 which is a char, and may therefore be unsigned. We
2378 want to pass -1, but we pass 64 instead, and convert
2379 back in md_pcrel_from. */
2380 add_fix ('B', &opP->disp, 1, 64);
2381 break;
2382 case 'W':
2383 add_fix ('w', &opP->disp, 1, 0);
2384 addword (0);
2385 break;
2386 case 'L':
2387 long_branch:
2388 if (cpu_of_arch (current_architecture) < m68020)
2389 as_warn ("Can't use long branches on 68000/68010");
2390 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2391 add_fix ('l', &opP->disp, 1, 0);
2392 addword (0);
2393 addword (0);
2394 break;
2395 case 'g':
2396 if (subs (&opP->disp)) /* We can't relax it */
2397 goto long_branch;
2398
2399 #ifdef OBJ_ELF
2400 /* If the displacement needs pic relocation it cannot be
2401 relaxed. */
2402 if (opP->disp.pic_reloc != pic_none)
2403 goto long_branch;
2404 #endif
2405
2406 /* This could either be a symbol, or an absolute
2407 address. No matter, the frag hacking will finger it
2408 out. Not quite: it can't switch from BRANCH to
2409 BCC68000 for the case where opnd is absolute (it
2410 needs to use the 68000 hack since no conditional abs
2411 jumps). */
2412 if (((cpu_of_arch (current_architecture) < m68020)
2413 || (0 == adds (&opP->disp)))
2414 && (the_ins.opcode[0] >= 0x6200)
2415 && (the_ins.opcode[0] <= 0x6f00))
2416 add_frag (adds (&opP->disp), offs (&opP->disp),
2417 TAB (BCC68000, SZ_UNDEF));
2418 else
2419 add_frag (adds (&opP->disp), offs (&opP->disp),
2420 TAB (ABRANCH, SZ_UNDEF));
2421 break;
2422 case 'w':
2423 if (isvar (&opP->disp))
2424 {
2425 #if 1
2426 /* check for DBcc instruction */
2427 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2428 {
2429 /* size varies if patch */
2430 /* needed for long form */
2431 add_frag (adds (&opP->disp), offs (&opP->disp),
2432 TAB (DBCC, SZ_UNDEF));
2433 break;
2434 }
2435 #endif
2436 add_fix ('w', &opP->disp, 1, 0);
2437 }
2438 addword (0);
2439 break;
2440 case 'C': /* Fixed size LONG coproc branches */
2441 add_fix ('l', &opP->disp, 1, 0);
2442 addword (0);
2443 addword (0);
2444 break;
2445 case 'c': /* Var size Coprocesssor branches */
2446 if (subs (&opP->disp))
2447 {
2448 add_fix ('l', &opP->disp, 1, 0);
2449 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2450 }
2451 else if (adds (&opP->disp))
2452 add_frag (adds (&opP->disp), offs (&opP->disp),
2453 TAB (FBRANCH, SZ_UNDEF));
2454 else
2455 {
2456 /* add_frag((symbolS *) 0, offs(&opP->disp),
2457 TAB(FBRANCH,SHORT)); */
2458 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2459 add_fix ('l', &opP->disp, 1, 0);
2460 addword (0);
2461 addword (0);
2462 }
2463 break;
2464 default:
2465 abort ();
2466 }
2467 break;
2468
2469 case 'C': /* Ignore it */
2470 break;
2471
2472 case 'd': /* JF this is a kludge */
2473 install_operand ('s', opP->reg - ADDR);
2474 tmpreg = get_num (&opP->disp, 80);
2475 if (!issword (tmpreg))
2476 {
2477 as_warn ("Expression out of range, using 0");
2478 tmpreg = 0;
2479 }
2480 addword (tmpreg);
2481 break;
2482
2483 case 'D':
2484 install_operand (s[1], opP->reg - DATA);
2485 break;
2486
2487 case 'F':
2488 install_operand (s[1], opP->reg - FP0);
2489 break;
2490
2491 case 'I':
2492 tmpreg = opP->reg - COP0;
2493 install_operand (s[1], tmpreg);
2494 break;
2495
2496 case 'J': /* JF foo */
2497 switch (opP->reg)
2498 {
2499 case SFC:
2500 tmpreg = 0x000;
2501 break;
2502 case DFC:
2503 tmpreg = 0x001;
2504 break;
2505 case CACR:
2506 tmpreg = 0x002;
2507 break;
2508 case TC:
2509 tmpreg = 0x003;
2510 break;
2511 case ITT0:
2512 tmpreg = 0x004;
2513 break;
2514 case ITT1:
2515 tmpreg = 0x005;
2516 break;
2517 case DTT0:
2518 tmpreg = 0x006;
2519 break;
2520 case DTT1:
2521 tmpreg = 0x007;
2522 break;
2523 case BUSCR:
2524 tmpreg = 0x008;
2525 break;
2526
2527 case USP:
2528 tmpreg = 0x800;
2529 break;
2530 case VBR:
2531 tmpreg = 0x801;
2532 break;
2533 case CAAR:
2534 tmpreg = 0x802;
2535 break;
2536 case MSP:
2537 tmpreg = 0x803;
2538 break;
2539 case ISP:
2540 tmpreg = 0x804;
2541 break;
2542 case MMUSR:
2543 tmpreg = 0x805;
2544 break;
2545 case URP:
2546 tmpreg = 0x806;
2547 break;
2548 case SRP:
2549 tmpreg = 0x807;
2550 break;
2551 case PCR:
2552 tmpreg = 0x808;
2553 break;
2554 case ROMBAR:
2555 tmpreg = 0xC00;
2556 break;
2557 case RAMBAR0:
2558 tmpreg = 0xC04;
2559 break;
2560 case RAMBAR1:
2561 tmpreg = 0xC05;
2562 break;
2563 case MBAR:
2564 tmpreg = 0xC0F;
2565 break;
2566 default:
2567 abort ();
2568 }
2569 install_operand (s[1], tmpreg);
2570 break;
2571
2572 case 'k':
2573 tmpreg = get_num (&opP->disp, 55);
2574 install_operand (s[1], tmpreg & 0x7f);
2575 break;
2576
2577 case 'l':
2578 tmpreg = opP->mask;
2579 if (s[1] == 'w')
2580 {
2581 if (tmpreg & 0x7FF0000)
2582 as_bad ("Floating point register in register list");
2583 insop (reverse_16_bits (tmpreg), opcode);
2584 }
2585 else
2586 {
2587 if (tmpreg & 0x700FFFF)
2588 as_bad ("Wrong register in floating-point reglist");
2589 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2590 }
2591 break;
2592
2593 case 'L':
2594 tmpreg = opP->mask;
2595 if (s[1] == 'w')
2596 {
2597 if (tmpreg & 0x7FF0000)
2598 as_bad ("Floating point register in register list");
2599 insop (tmpreg, opcode);
2600 }
2601 else if (s[1] == '8')
2602 {
2603 if (tmpreg & 0x0FFFFFF)
2604 as_bad ("incorrect register in reglist");
2605 install_operand (s[1], tmpreg >> 24);
2606 }
2607 else
2608 {
2609 if (tmpreg & 0x700FFFF)
2610 as_bad ("wrong register in floating-point reglist");
2611 else
2612 install_operand (s[1], tmpreg >> 16);
2613 }
2614 break;
2615
2616 case 'M':
2617 install_operand (s[1], get_num (&opP->disp, 60));
2618 break;
2619
2620 case 'O':
2621 tmpreg = ((opP->mode == DREG)
2622 ? 0x20 + opP->reg - DATA
2623 : (get_num (&opP->disp, 40) & 0x1F));
2624 install_operand (s[1], tmpreg);
2625 break;
2626
2627 case 'Q':
2628 tmpreg = get_num (&opP->disp, 10);
2629 if (tmpreg == 8)
2630 tmpreg = 0;
2631 install_operand (s[1], tmpreg);
2632 break;
2633
2634 case 'R':
2635 /* This depends on the fact that ADDR registers are eight
2636 more than their corresponding DATA regs, so the result
2637 will have the ADDR_REG bit set */
2638 install_operand (s[1], opP->reg - DATA);
2639 break;
2640
2641 case 'r':
2642 if (opP->mode == AINDR)
2643 install_operand (s[1], opP->reg - DATA);
2644 else
2645 install_operand (s[1], opP->index.reg - DATA);
2646 break;
2647
2648 case 's':
2649 if (opP->reg == FPI)
2650 tmpreg = 0x1;
2651 else if (opP->reg == FPS)
2652 tmpreg = 0x2;
2653 else if (opP->reg == FPC)
2654 tmpreg = 0x4;
2655 else
2656 abort ();
2657 install_operand (s[1], tmpreg);
2658 break;
2659
2660 case 'S': /* Ignore it */
2661 break;
2662
2663 case 'T':
2664 install_operand (s[1], get_num (&opP->disp, 30));
2665 break;
2666
2667 case 'U': /* Ignore it */
2668 break;
2669
2670 case 'c':
2671 switch (opP->reg)
2672 {
2673 case NC:
2674 tmpreg = 0;
2675 break;
2676 case DC:
2677 tmpreg = 1;
2678 break;
2679 case IC:
2680 tmpreg = 2;
2681 break;
2682 case BC:
2683 tmpreg = 3;
2684 break;
2685 default:
2686 as_fatal ("failed sanity check");
2687 } /* switch on cache token */
2688 install_operand (s[1], tmpreg);
2689 break;
2690 #ifndef NO_68851
2691 /* JF: These are out of order, I fear. */
2692 case 'f':
2693 switch (opP->reg)
2694 {
2695 case SFC:
2696 tmpreg = 0;
2697 break;
2698 case DFC:
2699 tmpreg = 1;
2700 break;
2701 default:
2702 abort ();
2703 }
2704 install_operand (s[1], tmpreg);
2705 break;
2706
2707 case '0':
2708 case '1':
2709 case '2':
2710 switch (opP->reg)
2711 {
2712 case TC:
2713 tmpreg = 0;
2714 break;
2715 case CAL:
2716 tmpreg = 4;
2717 break;
2718 case VAL:
2719 tmpreg = 5;
2720 break;
2721 case SCC:
2722 tmpreg = 6;
2723 break;
2724 case AC:
2725 tmpreg = 7;
2726 break;
2727 default:
2728 abort ();
2729 }
2730 install_operand (s[1], tmpreg);
2731 break;
2732
2733 case 'V':
2734 if (opP->reg == VAL)
2735 break;
2736 abort ();
2737
2738 case 'W':
2739 switch (opP->reg)
2740 {
2741 case DRP:
2742 tmpreg = 1;
2743 break;
2744 case SRP:
2745 tmpreg = 2;
2746 break;
2747 case CRP:
2748 tmpreg = 3;
2749 break;
2750 default:
2751 abort ();
2752 }
2753 install_operand (s[1], tmpreg);
2754 break;
2755
2756 case 'X':
2757 switch (opP->reg)
2758 {
2759 case BAD:
2760 case BAD + 1:
2761 case BAD + 2:
2762 case BAD + 3:
2763 case BAD + 4:
2764 case BAD + 5:
2765 case BAD + 6:
2766 case BAD + 7:
2767 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2768 break;
2769
2770 case BAC:
2771 case BAC + 1:
2772 case BAC + 2:
2773 case BAC + 3:
2774 case BAC + 4:
2775 case BAC + 5:
2776 case BAC + 6:
2777 case BAC + 7:
2778 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2779 break;
2780
2781 default:
2782 abort ();
2783 }
2784 install_operand (s[1], tmpreg);
2785 break;
2786 case 'Y':
2787 know (opP->reg == PSR);
2788 break;
2789 case 'Z':
2790 know (opP->reg == PCSR);
2791 break;
2792 #endif /* m68851 */
2793 case '3':
2794 switch (opP->reg)
2795 {
2796 case TT0:
2797 tmpreg = 2;
2798 break;
2799 case TT1:
2800 tmpreg = 3;
2801 break;
2802 default:
2803 abort ();
2804 }
2805 install_operand (s[1], tmpreg);
2806 break;
2807 case 't':
2808 tmpreg = get_num (&opP->disp, 20);
2809 install_operand (s[1], tmpreg);
2810 break;
2811 case '_': /* used only for move16 absolute 32-bit address */
2812 tmpreg = get_num (&opP->disp, 80);
2813 addword (tmpreg >> 16);
2814 addword (tmpreg & 0xFFFF);
2815 break;
2816 default:
2817 abort ();
2818 }
2819 }
2820
2821 /* By the time whe get here (FINALLY) the_ins contains the complete
2822 instruction, ready to be emitted. . . */
2823 }
2824
2825 static int
2826 reverse_16_bits (in)
2827 int in;
2828 {
2829 int out = 0;
2830 int n;
2831
2832 static int mask[16] =
2833 {
2834 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2835 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2836 };
2837 for (n = 0; n < 16; n++)
2838 {
2839 if (in & mask[n])
2840 out |= mask[15 - n];
2841 }
2842 return out;
2843 } /* reverse_16_bits() */
2844
2845 static int
2846 reverse_8_bits (in)
2847 int in;
2848 {
2849 int out = 0;
2850 int n;
2851
2852 static int mask[8] =
2853 {
2854 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2855 };
2856
2857 for (n = 0; n < 8; n++)
2858 {
2859 if (in & mask[n])
2860 out |= mask[7 - n];
2861 }
2862 return out;
2863 } /* reverse_8_bits() */
2864
2865 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2866 (that value is chosen in the frag_var call in md_assemble). TYPE
2867 is the subtype of the frag to be generated; its primary type is
2868 rs_machine_dependent.
2869
2870 The TYPE parameter is also used by md_convert_frag_1 and
2871 md_estimate_size_before_relax. The appropriate type of fixup will
2872 be emitted by md_convert_frag_1.
2873
2874 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2875 static void
2876 install_operand (mode, val)
2877 int mode;
2878 int val;
2879 {
2880 switch (mode)
2881 {
2882 case 's':
2883 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2884 break;
2885 case 'd':
2886 the_ins.opcode[0] |= val << 9;
2887 break;
2888 case '1':
2889 the_ins.opcode[1] |= val << 12;
2890 break;
2891 case '2':
2892 the_ins.opcode[1] |= val << 6;
2893 break;
2894 case '3':
2895 the_ins.opcode[1] |= val;
2896 break;
2897 case '4':
2898 the_ins.opcode[2] |= val << 12;
2899 break;
2900 case '5':
2901 the_ins.opcode[2] |= val << 6;
2902 break;
2903 case '6':
2904 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2905 three words long! */
2906 the_ins.numo++;
2907 the_ins.opcode[2] |= val;
2908 break;
2909 case '7':
2910 the_ins.opcode[1] |= val << 7;
2911 break;
2912 case '8':
2913 the_ins.opcode[1] |= val << 10;
2914 break;
2915 #ifndef NO_68851
2916 case '9':
2917 the_ins.opcode[1] |= val << 5;
2918 break;
2919 #endif
2920
2921 case 't':
2922 the_ins.opcode[1] |= (val << 10) | (val << 7);
2923 break;
2924 case 'D':
2925 the_ins.opcode[1] |= (val << 12) | val;
2926 break;
2927 case 'g':
2928 the_ins.opcode[0] |= val = 0xff;
2929 break;
2930 case 'i':
2931 the_ins.opcode[0] |= val << 9;
2932 break;
2933 case 'C':
2934 the_ins.opcode[1] |= val;
2935 break;
2936 case 'j':
2937 the_ins.opcode[1] |= val;
2938 the_ins.numo++; /* What a hack */
2939 break;
2940 case 'k':
2941 the_ins.opcode[1] |= val << 4;
2942 break;
2943 case 'b':
2944 case 'w':
2945 case 'W':
2946 case 'l':
2947 break;
2948 case 'e':
2949 the_ins.opcode[0] |= (val << 6);
2950 break;
2951 case 'L':
2952 the_ins.opcode[1] = (val >> 16);
2953 the_ins.opcode[2] = val & 0xffff;
2954 break;
2955 case 'c':
2956 default:
2957 as_fatal ("failed sanity check.");
2958 }
2959 } /* install_operand() */
2960
2961 static void
2962 install_gen_operand (mode, val)
2963 int mode;
2964 int val;
2965 {
2966 switch (mode)
2967 {
2968 case 's':
2969 the_ins.opcode[0] |= val;
2970 break;
2971 case 'd':
2972 /* This is a kludge!!! */
2973 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2974 break;
2975 case 'b':
2976 case 'w':
2977 case 'l':
2978 case 'f':
2979 case 'F':
2980 case 'x':
2981 case 'p':
2982 the_ins.opcode[0] |= val;
2983 break;
2984 /* more stuff goes here */
2985 default:
2986 as_fatal ("failed sanity check.");
2987 }
2988 } /* install_gen_operand() */
2989
2990 /*
2991 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2992 * then deal with the bitfield hack.
2993 */
2994
2995 static char *
2996 crack_operand (str, opP)
2997 register char *str;
2998 register struct m68k_op *opP;
2999 {
3000 register int parens;
3001 register int c;
3002 register char *beg_str;
3003 int inquote = 0;
3004
3005 if (!str)
3006 {
3007 return str;
3008 }
3009 beg_str = str;
3010 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3011 {
3012 if (! inquote)
3013 {
3014 if (*str == '(')
3015 parens++;
3016 else if (*str == ')')
3017 {
3018 if (!parens)
3019 { /* ERROR */
3020 opP->error = "Extra )";
3021 return str;
3022 }
3023 --parens;
3024 }
3025 }
3026 if (flag_mri && *str == '\'')
3027 inquote = ! inquote;
3028 }
3029 if (!*str && parens)
3030 { /* ERROR */
3031 opP->error = "Missing )";
3032 return str;
3033 }
3034 c = *str;
3035 *str = '\0';
3036 if (m68k_ip_op (beg_str, opP) != 0)
3037 {
3038 *str = c;
3039 return str;
3040 }
3041 *str = c;
3042 if (c == '}')
3043 c = *++str; /* JF bitfield hack */
3044 if (c)
3045 {
3046 c = *++str;
3047 if (!c)
3048 as_bad ("Missing operand");
3049 }
3050 return str;
3051 }
3052
3053 /* This is the guts of the machine-dependent assembler. STR points to a
3054 machine dependent instruction. This function is supposed to emit
3055 the frags/bytes it assembles to.
3056 */
3057
3058 void
3059 insert_reg (regname, regnum)
3060 char *regname;
3061 int regnum;
3062 {
3063 char buf[100];
3064 int i;
3065
3066 #ifdef REGISTER_PREFIX
3067 if (!flag_reg_prefix_optional)
3068 {
3069 buf[0] = REGISTER_PREFIX;
3070 strcpy (buf + 1, regname);
3071 regname = buf;
3072 }
3073 #endif
3074
3075 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3076 &zero_address_frag));
3077
3078 for (i = 0; regname[i]; i++)
3079 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3080 buf[i] = '\0';
3081
3082 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3083 &zero_address_frag));
3084 }
3085
3086 struct init_entry
3087 {
3088 const char *name;
3089 int number;
3090 };
3091
3092 static const struct init_entry init_table[] =
3093 {
3094 { "d0", DATA0 },
3095 { "d1", DATA1 },
3096 { "d2", DATA2 },
3097 { "d3", DATA3 },
3098 { "d4", DATA4 },
3099 { "d5", DATA5 },
3100 { "d6", DATA6 },
3101 { "d7", DATA7 },
3102 { "a0", ADDR0 },
3103 { "a1", ADDR1 },
3104 { "a2", ADDR2 },
3105 { "a3", ADDR3 },
3106 { "a4", ADDR4 },
3107 { "a5", ADDR5 },
3108 { "a6", ADDR6 },
3109 { "fp", ADDR6 },
3110 { "a7", ADDR7 },
3111 { "sp", ADDR7 },
3112 { "ssp", ADDR7 },
3113 { "fp0", FP0 },
3114 { "fp1", FP1 },
3115 { "fp2", FP2 },
3116 { "fp3", FP3 },
3117 { "fp4", FP4 },
3118 { "fp5", FP5 },
3119 { "fp6", FP6 },
3120 { "fp7", FP7 },
3121 { "fpi", FPI },
3122 { "fpiar", FPI },
3123 { "fpc", FPI },
3124 { "fps", FPS },
3125 { "fpsr", FPS },
3126 { "fpc", FPC },
3127 { "fpcr", FPC },
3128 { "control", FPC },
3129 { "status", FPS },
3130 { "iaddr", FPI },
3131
3132 { "cop0", COP0 },
3133 { "cop1", COP1 },
3134 { "cop2", COP2 },
3135 { "cop3", COP3 },
3136 { "cop4", COP4 },
3137 { "cop5", COP5 },
3138 { "cop6", COP6 },
3139 { "cop7", COP7 },
3140 { "pc", PC },
3141 { "zpc", ZPC },
3142 { "sr", SR },
3143
3144 { "ccr", CCR },
3145 { "cc", CCR },
3146
3147 /* control registers */
3148 { "sfc", SFC }, /* Source Function Code */
3149 { "sfcr", SFC },
3150 { "dfc", DFC }, /* Destination Function Code */
3151 { "dfcr", DFC },
3152 { "cacr", CACR }, /* Cache Control Register */
3153 { "caar", CAAR }, /* Cache Address Register */
3154
3155 { "usp", USP }, /* User Stack Pointer */
3156 { "vbr", VBR }, /* Vector Base Register */
3157 { "msp", MSP }, /* Master Stack Pointer */
3158 { "isp", ISP }, /* Interrupt Stack Pointer */
3159
3160 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3161 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3162 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3163 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3164
3165 /* 68ec040 versions of same */
3166 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3167 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3168 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3169 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3170
3171 /* mcf5200 versions of same. The ColdFire programmer's reference
3172 manual indicated that the order is 2,3,0,1, but Ken Rose
3173 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3174 { "acr0", ITT0 }, /* Access Control Unit 0 */
3175 { "acr1", ITT1 }, /* Access Control Unit 1 */
3176 { "acr2", DTT0 }, /* Access Control Unit 2 */
3177 { "acr3", DTT1 }, /* Access Control Unit 3 */
3178
3179 { "tc", TC }, /* MMU Translation Control Register */
3180 { "tcr", TC },
3181
3182 { "mmusr", MMUSR }, /* MMU Status Register */
3183 { "srp", SRP }, /* User Root Pointer */
3184 { "urp", URP }, /* Supervisor Root Pointer */
3185
3186 { "buscr", BUSCR },
3187 { "pcr", PCR },
3188
3189 { "rombar", ROMBAR }, /* ROM Base Address Register */
3190 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3191 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3192 { "mbar", MBAR }, /* Module Base Address Register */
3193 /* end of control registers */
3194
3195 { "ac", AC },
3196 { "bc", BC },
3197 { "cal", CAL },
3198 { "crp", CRP },
3199 { "drp", DRP },
3200 { "pcsr", PCSR },
3201 { "psr", PSR },
3202 { "scc", SCC },
3203 { "val", VAL },
3204 { "bad0", BAD0 },
3205 { "bad1", BAD1 },
3206 { "bad2", BAD2 },
3207 { "bad3", BAD3 },
3208 { "bad4", BAD4 },
3209 { "bad5", BAD5 },
3210 { "bad6", BAD6 },
3211 { "bad7", BAD7 },
3212 { "bac0", BAC0 },
3213 { "bac1", BAC1 },
3214 { "bac2", BAC2 },
3215 { "bac3", BAC3 },
3216 { "bac4", BAC4 },
3217 { "bac5", BAC5 },
3218 { "bac6", BAC6 },
3219 { "bac7", BAC7 },
3220
3221 { "ic", IC },
3222 { "dc", DC },
3223 { "nc", NC },
3224
3225 { "tt0", TT0 },
3226 { "tt1", TT1 },
3227 /* 68ec030 versions of same */
3228 { "ac0", TT0 },
3229 { "ac1", TT1 },
3230 /* 68ec030 access control unit, identical to 030 MMU status reg */
3231 { "acusr", PSR },
3232
3233 /* Suppressed data and address registers. */
3234 { "zd0", ZDATA0 },
3235 { "zd1", ZDATA1 },
3236 { "zd2", ZDATA2 },
3237 { "zd3", ZDATA3 },
3238 { "zd4", ZDATA4 },
3239 { "zd5", ZDATA5 },
3240 { "zd6", ZDATA6 },
3241 { "zd7", ZDATA7 },
3242 { "za0", ZADDR0 },
3243 { "za1", ZADDR1 },
3244 { "za2", ZADDR2 },
3245 { "za3", ZADDR3 },
3246 { "za4", ZADDR4 },
3247 { "za5", ZADDR5 },
3248 { "za6", ZADDR6 },
3249 { "za7", ZADDR7 },
3250
3251 { 0, 0 }
3252 };
3253
3254 void
3255 init_regtable ()
3256 {
3257 int i;
3258 for (i = 0; init_table[i].name; i++)
3259 insert_reg (init_table[i].name, init_table[i].number);
3260 }
3261
3262 static int no_68851, no_68881;
3263
3264 #ifdef OBJ_AOUT
3265 /* a.out machine type. Default to 68020. */
3266 int m68k_aout_machtype = 2;
3267 #endif
3268
3269 void
3270 md_assemble (str)
3271 char *str;
3272 {
3273 const char *er;
3274 short *fromP;
3275 char *toP = NULL;
3276 int m, n = 0;
3277 char *to_beg_P;
3278 int shorts_this_frag;
3279 fixS *fixP;
3280
3281 /* In MRI mode, the instruction and operands are separated by a
3282 space. Anything following the operands is a comment. The label
3283 has already been removed. */
3284 if (flag_mri)
3285 {
3286 char *s;
3287 int fields = 0;
3288 int infield = 0;
3289 int inquote = 0;
3290
3291 for (s = str; *s != '\0'; s++)
3292 {
3293 if ((*s == ' ' || *s == '\t') && ! inquote)
3294 {
3295 if (infield)
3296 {
3297 ++fields;
3298 if (fields >= 2)
3299 {
3300 *s = '\0';
3301 break;
3302 }
3303 infield = 0;
3304 }
3305 }
3306 else
3307 {
3308 if (! infield)
3309 infield = 1;
3310 if (*s == '\'')
3311 inquote = ! inquote;
3312 }
3313 }
3314 }
3315
3316 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3317 m68k_ip (str);
3318 er = the_ins.error;
3319 if (!er)
3320 {
3321 for (n = 0; n < the_ins.numargs; n++)
3322 if (the_ins.operands[n].error)
3323 {
3324 er = the_ins.operands[n].error;
3325 break;
3326 }
3327 }
3328 if (er)
3329 {
3330 as_bad ("%s -- statement `%s' ignored", er, str);
3331 return;
3332 }
3333
3334 /* If there is a current label, record that it marks an instruction. */
3335 if (current_label != NULL)
3336 {
3337 current_label->text = 1;
3338 current_label = NULL;
3339 }
3340
3341 if (the_ins.nfrag == 0)
3342 {
3343 /* No frag hacking involved; just put it out */
3344 toP = frag_more (2 * the_ins.numo);
3345 fromP = &the_ins.opcode[0];
3346 for (m = the_ins.numo; m; --m)
3347 {
3348 md_number_to_chars (toP, (long) (*fromP), 2);
3349 toP += 2;
3350 fromP++;
3351 }
3352 /* put out symbol-dependent info */
3353 for (m = 0; m < the_ins.nrel; m++)
3354 {
3355 switch (the_ins.reloc[m].wid)
3356 {
3357 case 'B':
3358 n = 1;
3359 break;
3360 case 'b':
3361 n = 1;
3362 break;
3363 case '3':
3364 n = 1;
3365 break;
3366 case 'w':
3367 n = 2;
3368 break;
3369 case 'l':
3370 n = 4;
3371 break;
3372 default:
3373 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3374 the_ins.reloc[m].wid);
3375 }
3376
3377 fixP = fix_new_exp (frag_now,
3378 ((toP - frag_now->fr_literal)
3379 - the_ins.numo * 2 + the_ins.reloc[m].n),
3380 n,
3381 &the_ins.reloc[m].exp,
3382 the_ins.reloc[m].pcrel,
3383 get_reloc_code (n, the_ins.reloc[m].pcrel,
3384 the_ins.reloc[m].pic_reloc));
3385 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3386 if (the_ins.reloc[m].wid == 'B')
3387 fixP->fx_signed = 1;
3388 }
3389 return;
3390 }
3391
3392 /* There's some frag hacking */
3393 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3394 {
3395 int wid;
3396
3397 if (n == 0)
3398 wid = 2 * the_ins.fragb[n].fragoff;
3399 else
3400 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3401 toP = frag_more (wid);
3402 to_beg_P = toP;
3403 shorts_this_frag = 0;
3404 for (m = wid / 2; m; --m)
3405 {
3406 md_number_to_chars (toP, (long) (*fromP), 2);
3407 toP += 2;
3408 fromP++;
3409 shorts_this_frag++;
3410 }
3411 for (m = 0; m < the_ins.nrel; m++)
3412 {
3413 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3414 {
3415 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3416 break;
3417 }
3418 wid = the_ins.reloc[m].wid;
3419 if (wid == 0)
3420 continue;
3421 the_ins.reloc[m].wid = 0;
3422 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3423
3424 fixP = fix_new_exp (frag_now,
3425 ((toP - frag_now->fr_literal)
3426 - the_ins.numo * 2 + the_ins.reloc[m].n),
3427 wid,
3428 &the_ins.reloc[m].exp,
3429 the_ins.reloc[m].pcrel,
3430 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3431 the_ins.reloc[m].pic_reloc));
3432 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3433 }
3434 (void) frag_var (rs_machine_dependent, 10, 0,
3435 (relax_substateT) (the_ins.fragb[n].fragty),
3436 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3437 }
3438 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3439 shorts_this_frag = 0;
3440 if (n)
3441 {
3442 toP = frag_more (n * sizeof (short));
3443 while (n--)
3444 {
3445 md_number_to_chars (toP, (long) (*fromP), 2);
3446 toP += 2;
3447 fromP++;
3448 shorts_this_frag++;
3449 }
3450 }
3451 for (m = 0; m < the_ins.nrel; m++)
3452 {
3453 int wid;
3454
3455 wid = the_ins.reloc[m].wid;
3456 if (wid == 0)
3457 continue;
3458 the_ins.reloc[m].wid = 0;
3459 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3460
3461 fixP = fix_new_exp (frag_now,
3462 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3463 - shorts_this_frag * 2),
3464 wid,
3465 &the_ins.reloc[m].exp,
3466 the_ins.reloc[m].pcrel,
3467 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3468 the_ins.reloc[m].pic_reloc));
3469 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3470 }
3471 }
3472
3473 void
3474 md_begin ()
3475 {
3476 /*
3477 * md_begin -- set up hash tables with 68000 instructions.
3478 * similar to what the vax assembler does. ---phr
3479 */
3480 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3481 a copy of it at runtime, adding in the information we want but isn't
3482 there. I think it'd be better to have an awk script hack the table
3483 at compile time. Or even just xstr the table and use it as-is. But
3484 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3485 names. */
3486
3487 register const struct m68k_opcode *ins;
3488 register struct m68k_incant *hack, *slak;
3489 register const char *retval = 0; /* empty string, or error msg text */
3490 register unsigned int i;
3491 register char c;
3492
3493 if (flag_mri)
3494 {
3495 flag_reg_prefix_optional = 1;
3496 m68k_abspcadd = 1;
3497 if (! m68k_rel32_from_cmdline)
3498 m68k_rel32 = 0;
3499 }
3500
3501 op_hash = hash_new ();
3502
3503 obstack_begin (&robyn, 4000);
3504 for (i = 0; i < m68k_numopcodes; i++)
3505 {
3506 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3507 do
3508 {
3509 ins = &m68k_opcodes[i];
3510 /* We *could* ignore insns that don't match our arch here
3511 but just leaving them out of the hash. */
3512 slak->m_operands = ins->args;
3513 slak->m_opnum = strlen (slak->m_operands) / 2;
3514 slak->m_arch = ins->arch;
3515 slak->m_opcode = ins->opcode;
3516 /* This is kludgey */
3517 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3518 if (i + 1 != m68k_numopcodes
3519 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3520 {
3521 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3522 i++;
3523 }
3524 else
3525 slak->m_next = 0;
3526 slak = slak->m_next;
3527 }
3528 while (slak);
3529
3530 retval = hash_insert (op_hash, ins->name, (char *) hack);
3531 if (retval)
3532 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3533 }
3534
3535 for (i = 0; i < m68k_numaliases; i++)
3536 {
3537 const char *name = m68k_opcode_aliases[i].primary;
3538 const char *alias = m68k_opcode_aliases[i].alias;
3539 PTR val = hash_find (op_hash, name);
3540 if (!val)
3541 as_fatal ("Internal Error: Can't find %s in hash table", name);
3542 retval = hash_insert (op_hash, alias, val);
3543 if (retval)
3544 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3545 }
3546
3547 /* In MRI mode, all unsized branches are variable sized. Normally,
3548 they are word sized. */
3549 if (flag_mri)
3550 {
3551 static struct m68k_opcode_alias mri_aliases[] =
3552 {
3553 { "bhi", "jhi", },
3554 { "bls", "jls", },
3555 { "bcc", "jcc", },
3556 { "bcs", "jcs", },
3557 { "bne", "jne", },
3558 { "beq", "jeq", },
3559 { "bvc", "jvc", },
3560 { "bvs", "jvs", },
3561 { "bpl", "jpl", },
3562 { "bmi", "jmi", },
3563 { "bge", "jge", },
3564 { "blt", "jlt", },
3565 { "bgt", "jgt", },
3566 { "ble", "jle", },
3567 { "bra", "jra", },
3568 { "bsr", "jbsr", },
3569 };
3570
3571 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3572 {
3573 const char *name = mri_aliases[i].primary;
3574 const char *alias = mri_aliases[i].alias;
3575 PTR val = hash_find (op_hash, name);
3576 if (!val)
3577 as_fatal ("Internal Error: Can't find %s in hash table", name);
3578 retval = hash_jam (op_hash, alias, val);
3579 if (retval)
3580 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3581 }
3582 }
3583
3584 for (i = 0; i < sizeof (mklower_table); i++)
3585 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3586
3587 for (i = 0; i < sizeof (notend_table); i++)
3588 {
3589 notend_table[i] = 0;
3590 alt_notend_table[i] = 0;
3591 }
3592 notend_table[','] = 1;
3593 notend_table['{'] = 1;
3594 notend_table['}'] = 1;
3595 alt_notend_table['a'] = 1;
3596 alt_notend_table['A'] = 1;
3597 alt_notend_table['d'] = 1;
3598 alt_notend_table['D'] = 1;
3599 alt_notend_table['#'] = 1;
3600 alt_notend_table['&'] = 1;
3601 alt_notend_table['f'] = 1;
3602 alt_notend_table['F'] = 1;
3603 #ifdef REGISTER_PREFIX
3604 alt_notend_table[REGISTER_PREFIX] = 1;
3605 #endif
3606
3607 /* We need to put '(' in alt_notend_table to handle
3608 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3609 */
3610 alt_notend_table['('] = 1;
3611
3612 /* We need to put '@' in alt_notend_table to handle
3613 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3614 */
3615 alt_notend_table['@'] = 1;
3616
3617 /* We need to put digits in alt_notend_table to handle
3618 bfextu %d0{24:1},%d0
3619 */
3620 alt_notend_table['0'] = 1;
3621 alt_notend_table['1'] = 1;
3622 alt_notend_table['2'] = 1;
3623 alt_notend_table['3'] = 1;
3624 alt_notend_table['4'] = 1;
3625 alt_notend_table['5'] = 1;
3626 alt_notend_table['6'] = 1;
3627 alt_notend_table['7'] = 1;
3628 alt_notend_table['8'] = 1;
3629 alt_notend_table['9'] = 1;
3630
3631 #ifndef MIT_SYNTAX_ONLY
3632 /* Insert pseudo ops, these have to go into the opcode table since
3633 gas expects pseudo ops to start with a dot */
3634 {
3635 int n = 0;
3636 while (mote_pseudo_table[n].poc_name)
3637 {
3638 hack = (struct m68k_incant *)
3639 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3640 hash_insert (op_hash,
3641 mote_pseudo_table[n].poc_name, (char *) hack);
3642 hack->m_operands = 0;
3643 hack->m_opnum = n;
3644 n++;
3645 }
3646 }
3647 #endif
3648
3649 init_regtable ();
3650
3651 #ifdef OBJ_ELF
3652 record_alignment (text_section, 2);
3653 record_alignment (data_section, 2);
3654 record_alignment (bss_section, 2);
3655 #endif
3656 }
3657
3658 static void
3659 select_control_regs ()
3660 {
3661 /* Note which set of "movec" control registers is available. */
3662 switch (cpu_of_arch (current_architecture))
3663 {
3664 case m68000:
3665 control_regs = m68000_control_regs;
3666 break;
3667 case m68010:
3668 control_regs = m68010_control_regs;
3669 break;
3670 case m68020:
3671 case m68030:
3672 control_regs = m68020_control_regs;
3673 break;
3674 case m68040:
3675 control_regs = m68040_control_regs;
3676 break;
3677 case m68060:
3678 control_regs = m68060_control_regs;
3679 break;
3680 case cpu32:
3681 control_regs = cpu32_control_regs;
3682 break;
3683 case mcf5200:
3684 control_regs = mcf5200_control_regs;
3685 break;
3686 default:
3687 abort ();
3688 }
3689 }
3690
3691 void
3692 m68k_init_after_args ()
3693 {
3694 if (cpu_of_arch (current_architecture) == 0)
3695 {
3696 int i;
3697 const char *default_cpu = TARGET_CPU;
3698
3699 if (*default_cpu == 'm')
3700 default_cpu++;
3701 for (i = 0; i < n_archs; i++)
3702 if (strcasecmp (default_cpu, archs[i].name) == 0)
3703 break;
3704 if (i == n_archs)
3705 {
3706 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3707 current_architecture |= m68020;
3708 }
3709 else
3710 current_architecture |= archs[i].arch;
3711 }
3712 /* Permit m68881 specification with all cpus; those that can't work
3713 with a coprocessor could be doing emulation. */
3714 if (current_architecture & m68851)
3715 {
3716 if (current_architecture & m68040)
3717 {
3718 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3719 }
3720 }
3721 /* What other incompatibilities could we check for? */
3722
3723 /* Toss in some default assumptions about coprocessors. */
3724 if (!no_68881
3725 && (cpu_of_arch (current_architecture)
3726 /* Can CPU32 have a 68881 coprocessor?? */
3727 & (m68020 | m68030 | cpu32)))
3728 {
3729 current_architecture |= m68881;
3730 }
3731 if (!no_68851
3732 && (cpu_of_arch (current_architecture) & m68020up) != 0
3733 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3734 {
3735 current_architecture |= m68851;
3736 }
3737 if (no_68881 && (current_architecture & m68881))
3738 as_bad ("options for 68881 and no-68881 both given");
3739 if (no_68851 && (current_architecture & m68851))
3740 as_bad ("options for 68851 and no-68851 both given");
3741
3742 #ifdef OBJ_AOUT
3743 /* Work out the magic number. This isn't very general. */
3744 if (current_architecture & m68000)
3745 m68k_aout_machtype = 0;
3746 else if (current_architecture & m68010)
3747 m68k_aout_machtype = 1;
3748 else if (current_architecture & m68020)
3749 m68k_aout_machtype = 2;
3750 else
3751 m68k_aout_machtype = 2;
3752 #endif
3753
3754 /* Note which set of "movec" control registers is available. */
3755 select_control_regs ();
3756
3757 if (cpu_of_arch (current_architecture) < m68020)
3758 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3759 }
3760 \f
3761 /* This is called when a label is defined. */
3762
3763 void
3764 m68k_frob_label (sym)
3765 symbolS *sym;
3766 {
3767 struct label_line *n;
3768
3769 n = (struct label_line *) xmalloc (sizeof *n);
3770 n->next = labels;
3771 n->label = sym;
3772 as_where (&n->file, &n->line);
3773 labels = n;
3774 current_label = n;
3775 }
3776
3777 /* This is called when a value that is not an instruction is emitted. */
3778
3779 void
3780 m68k_flush_pending_output ()
3781 {
3782 current_label = NULL;
3783 }
3784
3785 /* This is called at the end of the assembly, when the final value of
3786 the label is known. We warn if this is a text symbol aligned at an
3787 odd location. */
3788
3789 void
3790 m68k_frob_symbol (sym)
3791 symbolS *sym;
3792 {
3793 if ((S_GET_VALUE (sym) & 1) != 0)
3794 {
3795 struct label_line *l;
3796
3797 for (l = labels; l != NULL; l = l->next)
3798 {
3799 if (l->label == sym)
3800 {
3801 if (l->text)
3802 as_warn_where (l->file, l->line,
3803 "text label `%s' aligned to odd boundary",
3804 S_GET_NAME (sym));
3805 break;
3806 }
3807 }
3808 }
3809 }
3810 \f
3811 /* This is called if we go in or out of MRI mode because of the .mri
3812 pseudo-op. */
3813
3814 void
3815 m68k_mri_mode_change (on)
3816 int on;
3817 {
3818 if (on)
3819 {
3820 if (! flag_reg_prefix_optional)
3821 {
3822 flag_reg_prefix_optional = 1;
3823 #ifdef REGISTER_PREFIX
3824 init_regtable ();
3825 #endif
3826 }
3827 m68k_abspcadd = 1;
3828 if (! m68k_rel32_from_cmdline)
3829 m68k_rel32 = 0;
3830 }
3831 else
3832 {
3833 if (! reg_prefix_optional_seen)
3834 {
3835 #ifdef REGISTER_PREFIX_OPTIONAL
3836 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3837 #else
3838 flag_reg_prefix_optional = 0;
3839 #endif
3840 #ifdef REGISTER_PREFIX
3841 init_regtable ();
3842 #endif
3843 }
3844 m68k_abspcadd = 0;
3845 if (! m68k_rel32_from_cmdline)
3846 m68k_rel32 = 1;
3847 }
3848 }
3849
3850 /* Equal to MAX_PRECISION in atof-ieee.c */
3851 #define MAX_LITTLENUMS 6
3852
3853 /* Turn a string in input_line_pointer into a floating point constant
3854 of type type, and store the appropriate bytes in *litP. The number
3855 of LITTLENUMS emitted is stored in *sizeP . An error message is
3856 returned, or NULL on OK. */
3857
3858 char *
3859 md_atof (type, litP, sizeP)
3860 char type;
3861 char *litP;
3862 int *sizeP;
3863 {
3864 int prec;
3865 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3866 LITTLENUM_TYPE *wordP;
3867 char *t;
3868 char *atof_ieee ();
3869
3870 switch (type)
3871 {
3872 case 'f':
3873 case 'F':
3874 case 's':
3875 case 'S':
3876 prec = 2;
3877 break;
3878
3879 case 'd':
3880 case 'D':
3881 case 'r':
3882 case 'R':
3883 prec = 4;
3884 break;
3885
3886 case 'x':
3887 case 'X':
3888 prec = 6;
3889 break;
3890
3891 case 'p':
3892 case 'P':
3893 prec = 6;
3894 break;
3895
3896 default:
3897 *sizeP = 0;
3898 return "Bad call to MD_ATOF()";
3899 }
3900 t = atof_ieee (input_line_pointer, type, words);
3901 if (t)
3902 input_line_pointer = t;
3903
3904 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3905 for (wordP = words; prec--;)
3906 {
3907 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3908 litP += sizeof (LITTLENUM_TYPE);
3909 }
3910 return 0;
3911 }
3912
3913 void
3914 md_number_to_chars (buf, val, n)
3915 char *buf;
3916 valueT val;
3917 int n;
3918 {
3919 number_to_chars_bigendian (buf, val, n);
3920 }
3921
3922 static void
3923 md_apply_fix_2 (fixP, val)
3924 fixS *fixP;
3925 offsetT val;
3926 {
3927 addressT upper_limit;
3928 offsetT lower_limit;
3929
3930 /* This is unnecessary but it convinces the native rs6000 compiler
3931 to generate the code we want. */
3932 char *buf = fixP->fx_frag->fr_literal;
3933 buf += fixP->fx_where;
3934 /* end ibm compiler workaround */
3935
3936 if (val & 0x80000000)
3937 val |= ~(addressT)0x7fffffff;
3938 else
3939 val &= 0x7fffffff;
3940
3941 #ifdef OBJ_ELF
3942 if (fixP->fx_addsy)
3943 {
3944 memset (buf, 0, fixP->fx_size);
3945 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3946 return;
3947 }
3948 #endif
3949
3950 switch (fixP->fx_size)
3951 {
3952 /* The cast to offsetT below are necessary to make code correct for
3953 machines where ints are smaller than offsetT */
3954 case 1:
3955 *buf++ = val;
3956 upper_limit = 0x7f;
3957 lower_limit = - (offsetT) 0x80;
3958 break;
3959 case 2:
3960 *buf++ = (val >> 8);
3961 *buf++ = val;
3962 upper_limit = 0x7fff;
3963 lower_limit = - (offsetT) 0x8000;
3964 break;
3965 case 4:
3966 *buf++ = (val >> 24);
3967 *buf++ = (val >> 16);
3968 *buf++ = (val >> 8);
3969 *buf++ = val;
3970 upper_limit = 0x7fffffff;
3971 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3972 break;
3973 default:
3974 BAD_CASE (fixP->fx_size);
3975 }
3976
3977 /* Fix up a negative reloc. */
3978 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3979 {
3980 fixP->fx_addsy = fixP->fx_subsy;
3981 fixP->fx_subsy = NULL;
3982 fixP->fx_tcbit = 1;
3983 }
3984
3985 /* For non-pc-relative values, it's conceivable we might get something
3986 like "0xff" for a byte field. So extend the upper part of the range
3987 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3988 so that we can do any range checking at all. */
3989 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3990 upper_limit = upper_limit * 2 + 1;
3991
3992 if ((addressT) val > upper_limit
3993 && (val > 0 || val < lower_limit))
3994 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3995
3996 /* A one byte PC-relative reloc means a short branch. We can't use
3997 a short branch with a value of 0 or -1, because those indicate
3998 different opcodes (branches with longer offsets). */
3999 if (fixP->fx_pcrel
4000 && fixP->fx_size == 1
4001 && (fixP->fx_addsy == NULL
4002 || S_IS_DEFINED (fixP->fx_addsy))
4003 && (val == 0 || val == -1))
4004 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4005 }
4006
4007 #ifdef BFD_ASSEMBLER
4008 int
4009 md_apply_fix (fixP, valp)
4010 fixS *fixP;
4011 valueT *valp;
4012 {
4013 md_apply_fix_2 (fixP, (addressT) *valp);
4014 return 1;
4015 }
4016 #else
4017 void md_apply_fix (fixP, val)
4018 fixS *fixP;
4019 long val;
4020 {
4021 md_apply_fix_2 (fixP, (addressT) val);
4022 }
4023 #endif
4024
4025 /* *fragP has been relaxed to its final size, and now needs to have
4026 the bytes inside it modified to conform to the new size There is UGLY
4027 MAGIC here. ..
4028 */
4029 void
4030 md_convert_frag_1 (fragP)
4031 register fragS *fragP;
4032 {
4033 long disp;
4034 long ext = 0;
4035 fixS *fixP;
4036
4037 /* Address in object code of the displacement. */
4038 register int object_address = fragP->fr_fix + fragP->fr_address;
4039
4040 /* Address in gas core of the place to store the displacement. */
4041 /* This convinces the native rs6000 compiler to generate the code we
4042 want. */
4043 register char *buffer_address = fragP->fr_literal;
4044 buffer_address += fragP->fr_fix;
4045 /* end ibm compiler workaround */
4046
4047 /* The displacement of the address, from current location. */
4048 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4049 disp = (disp + fragP->fr_offset) - object_address;
4050
4051 #ifdef BFD_ASSEMBLER
4052 disp += fragP->fr_symbol->sy_frag->fr_address;
4053 #endif
4054
4055 switch (fragP->fr_subtype)
4056 {
4057 case TAB (BCC68000, BYTE):
4058 case TAB (ABRANCH, BYTE):
4059 know (issbyte (disp));
4060 if (disp == 0)
4061 as_bad ("short branch with zero offset: use :w");
4062 fragP->fr_opcode[1] = disp;
4063 ext = 0;
4064 break;
4065 case TAB (DBCC, SHORT):
4066 know (issword (disp));
4067 ext = 2;
4068 break;
4069 case TAB (BCC68000, SHORT):
4070 case TAB (ABRANCH, SHORT):
4071 know (issword (disp));
4072 fragP->fr_opcode[1] = 0x00;
4073 ext = 2;
4074 break;
4075 case TAB (ABRANCH, LONG):
4076 if (cpu_of_arch (current_architecture) < m68020)
4077 {
4078 if (fragP->fr_opcode[0] == 0x61)
4079 /* BSR */
4080 {
4081 fragP->fr_opcode[0] = 0x4E;
4082 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4083
4084 fix_new (fragP,
4085 fragP->fr_fix,
4086 4,
4087 fragP->fr_symbol,
4088 fragP->fr_offset,
4089 0,
4090 NO_RELOC);
4091
4092 fragP->fr_fix += 4;
4093 ext = 0;
4094 }
4095 /* BRA */
4096 else if (fragP->fr_opcode[0] == 0x60)
4097 {
4098 fragP->fr_opcode[0] = 0x4E;
4099 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4100 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4101 fragP->fr_offset, 0, NO_RELOC);
4102 fragP->fr_fix += 4;
4103 ext = 0;
4104 }
4105 else
4106 {
4107 as_bad ("Long branch offset not supported.");
4108 }
4109 }
4110 else
4111 {
4112 fragP->fr_opcode[1] = (char) 0xff;
4113 ext = 4;
4114 }
4115 break;
4116 case TAB (BCC68000, LONG):
4117 /* only Bcc 68000 instructions can come here */
4118 /* change bcc into b!cc/jmp absl long */
4119 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4120 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4121
4122 /* JF: these used to be fr_opcode[2,3], but they may be in a
4123 different frag, in which case refering to them is a no-no.
4124 Only fr_opcode[0,1] are guaranteed to work. */
4125 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4126 *buffer_address++ = (char) 0xf9;
4127 fragP->fr_fix += 2; /* account for jmp instruction */
4128 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4129 fragP->fr_offset, 0, NO_RELOC);
4130 fragP->fr_fix += 4;
4131 ext = 0;
4132 break;
4133 case TAB (DBCC, LONG):
4134 /* only DBcc 68000 instructions can come here */
4135 /* change dbcc into dbcc/jmp absl long */
4136 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4137 *buffer_address++ = 0x00; /* branch offset = 4 */
4138 *buffer_address++ = 0x04;
4139 *buffer_address++ = 0x60; /* put in bra pc+6 */
4140 *buffer_address++ = 0x06;
4141 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4142 *buffer_address++ = (char) 0xf9;
4143
4144 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4145 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4146 fragP->fr_offset, 0, NO_RELOC);
4147 fragP->fr_fix += 4;
4148 ext = 0;
4149 break;
4150 case TAB (FBRANCH, SHORT):
4151 know ((fragP->fr_opcode[1] & 0x40) == 0);
4152 ext = 2;
4153 break;
4154 case TAB (FBRANCH, LONG):
4155 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4156 ext = 4;
4157 break;
4158 case TAB (PCREL, SHORT):
4159 ext = 2;
4160 break;
4161 case TAB (PCREL, LONG):
4162 /* The thing to do here is force it to ABSOLUTE LONG, since
4163 PCREL is really trying to shorten an ABSOLUTE address anyway */
4164 /* JF FOO This code has not been tested */
4165 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4166 0, NO_RELOC);
4167 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4168 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4169 (unsigned) fragP->fr_opcode[0],
4170 (unsigned long) fragP->fr_address);
4171 fragP->fr_opcode[1] &= ~0x3F;
4172 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4173 fragP->fr_fix += 4;
4174 ext = 0;
4175 break;
4176 case TAB (PCLEA, SHORT):
4177 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4178 fragP->fr_offset, 1, NO_RELOC);
4179 fragP->fr_opcode[1] &= ~0x3F;
4180 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4181 ext = 2;
4182 break;
4183 case TAB (PCLEA, LONG):
4184 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4185 fragP->fr_offset, 1, NO_RELOC);
4186 fixP->fx_pcrel_adjust = 2;
4187 /* Already set to mode 7.3; this indicates: PC indirect with
4188 suppressed index, 32-bit displacement. */
4189 *buffer_address++ = 0x01;
4190 *buffer_address++ = 0x70;
4191 fragP->fr_fix += 2;
4192 ext = 4;
4193 break;
4194
4195 case TAB (PCINDEX, BYTE):
4196 disp += 2;
4197 if (!issbyte (disp))
4198 {
4199 as_bad ("displacement doesn't fit in one byte");
4200 disp = 0;
4201 }
4202 assert (fragP->fr_fix >= 2);
4203 buffer_address[-2] &= ~1;
4204 buffer_address[-1] = disp;
4205 ext = 0;
4206 break;
4207 case TAB (PCINDEX, SHORT):
4208 disp += 2;
4209 assert (issword (disp));
4210 assert (fragP->fr_fix >= 2);
4211 buffer_address[-2] |= 0x1;
4212 buffer_address[-1] = 0x20;
4213 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4214 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4215 NO_RELOC);
4216 fixP->fx_pcrel_adjust = 2;
4217 ext = 2;
4218 break;
4219 case TAB (PCINDEX, LONG):
4220 disp += 2;
4221 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4222 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4223 NO_RELOC);
4224 fixP->fx_pcrel_adjust = 2;
4225 assert (fragP->fr_fix >= 2);
4226 buffer_address[-2] |= 0x1;
4227 buffer_address[-1] = 0x30;
4228 ext = 4;
4229 break;
4230 }
4231
4232 if (ext)
4233 {
4234 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4235 fragP->fr_fix += ext;
4236 }
4237 }
4238
4239 #ifndef BFD_ASSEMBLER
4240
4241 void
4242 md_convert_frag (headers, sec, fragP)
4243 object_headers *headers;
4244 segT sec;
4245 fragS *fragP;
4246 {
4247 md_convert_frag_1 (fragP);
4248 }
4249
4250 #else
4251
4252 void
4253 md_convert_frag (abfd, sec, fragP)
4254 bfd *abfd;
4255 segT sec;
4256 fragS *fragP;
4257 {
4258 md_convert_frag_1 (fragP);
4259 }
4260 #endif
4261
4262 /* Force truly undefined symbols to their maximum size, and generally set up
4263 the frag list to be relaxed
4264 */
4265 int
4266 md_estimate_size_before_relax (fragP, segment)
4267 register fragS *fragP;
4268 segT segment;
4269 {
4270 int old_fix;
4271 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4272
4273 old_fix = fragP->fr_fix;
4274
4275 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4276 switch (fragP->fr_subtype)
4277 {
4278
4279 case TAB (ABRANCH, SZ_UNDEF):
4280 {
4281 if ((fragP->fr_symbol != NULL) /* Not absolute */
4282 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4283 {
4284 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4285 break;
4286 }
4287 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4288 {
4289 /* On 68000, or for absolute value, switch to abs long */
4290 /* FIXME, we should check abs val, pick short or long */
4291 if (fragP->fr_opcode[0] == 0x61)
4292 {
4293 fragP->fr_opcode[0] = 0x4E;
4294 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4295 fix_new (fragP, fragP->fr_fix, 4,
4296 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4297 fragP->fr_fix += 4;
4298 frag_wane (fragP);
4299 }
4300 else if (fragP->fr_opcode[0] == 0x60)
4301 {
4302 fragP->fr_opcode[0] = 0x4E;
4303 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4304 fix_new (fragP, fragP->fr_fix, 4,
4305 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4306 fragP->fr_fix += 4;
4307 frag_wane (fragP);
4308 }
4309 else
4310 {
4311 as_warn ("Long branch offset to extern symbol not supported.");
4312 }
4313 }
4314 else
4315 { /* Symbol is still undefined. Make it simple */
4316 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4317 fragP->fr_offset, 1, NO_RELOC);
4318 fragP->fr_fix += 4;
4319 fragP->fr_opcode[1] = (char) 0xff;
4320 frag_wane (fragP);
4321 break;
4322 }
4323
4324 break;
4325 } /* case TAB(ABRANCH,SZ_UNDEF) */
4326
4327 case TAB (FBRANCH, SZ_UNDEF):
4328 {
4329 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4330 {
4331 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4332 fragP->fr_var += 2;
4333 }
4334 else
4335 {
4336 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4337 fragP->fr_offset, 1, NO_RELOC);
4338 fragP->fr_fix += 4;
4339 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4340 frag_wane (fragP);
4341 }
4342 break;
4343 } /* TAB(FBRANCH,SZ_UNDEF) */
4344
4345 case TAB (PCREL, SZ_UNDEF):
4346 {
4347 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4348 || flag_short_refs
4349 || cpu_of_arch (current_architecture) < m68020)
4350 {
4351 fragP->fr_subtype = TAB (PCREL, SHORT);
4352 fragP->fr_var += 2;
4353 }
4354 else
4355 {
4356 fragP->fr_subtype = TAB (PCREL, LONG);
4357 fragP->fr_var += 4;
4358 }
4359 break;
4360 } /* TAB(PCREL,SZ_UNDEF) */
4361
4362 case TAB (BCC68000, SZ_UNDEF):
4363 {
4364 if ((fragP->fr_symbol != NULL)
4365 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4366 {
4367 fragP->fr_subtype = TAB (BCC68000, BYTE);
4368 break;
4369 }
4370 /* only Bcc 68000 instructions can come here */
4371 /* change bcc into b!cc/jmp absl long */
4372 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4373 if (flag_short_refs)
4374 {
4375 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4376 /* JF: these were fr_opcode[2,3] */
4377 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4378 buffer_address[1] = (char) 0xf8;
4379 fragP->fr_fix += 2; /* account for jmp instruction */
4380 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4381 fragP->fr_offset, 0, NO_RELOC);
4382 fragP->fr_fix += 2;
4383 }
4384 else
4385 {
4386 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4387 /* JF: these were fr_opcode[2,3] */
4388 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4389 buffer_address[1] = (char) 0xf9;
4390 fragP->fr_fix += 2; /* account for jmp instruction */
4391 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4392 fragP->fr_offset, 0, NO_RELOC);
4393 fragP->fr_fix += 4;
4394 }
4395 frag_wane (fragP);
4396 break;
4397 } /* case TAB(BCC68000,SZ_UNDEF) */
4398
4399 case TAB (DBCC, SZ_UNDEF):
4400 {
4401 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4402 {
4403 fragP->fr_subtype = TAB (DBCC, SHORT);
4404 fragP->fr_var += 2;
4405 break;
4406 }
4407 /* only DBcc 68000 instructions can come here */
4408 /* change dbcc into dbcc/jmp absl long */
4409 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4410 buffer_address[0] = 0x00; /* branch offset = 4 */
4411 buffer_address[1] = 0x04;
4412 buffer_address[2] = 0x60; /* put in bra pc + ... */
4413
4414 if (flag_short_refs)
4415 {
4416 /* JF: these were fr_opcode[5-7] */
4417 buffer_address[3] = 0x04; /* plus 4 */
4418 buffer_address[4] = 0x4e; /* Put in Jump Word */
4419 buffer_address[5] = (char) 0xf8;
4420 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4421 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4422 fragP->fr_offset, 0, NO_RELOC);
4423 fragP->fr_fix += 2;
4424 }
4425 else
4426 {
4427 /* JF: these were fr_opcode[5-7] */
4428 buffer_address[3] = 0x06; /* Plus 6 */
4429 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4430 buffer_address[5] = (char) 0xf9;
4431 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4432 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4433 fragP->fr_offset, 0, NO_RELOC);
4434 fragP->fr_fix += 4;
4435 }
4436
4437 frag_wane (fragP);
4438 break;
4439 } /* case TAB(DBCC,SZ_UNDEF) */
4440
4441 case TAB (PCLEA, SZ_UNDEF):
4442 {
4443 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4444 || flag_short_refs
4445 || cpu_of_arch (current_architecture) < m68020)
4446 {
4447 fragP->fr_subtype = TAB (PCLEA, SHORT);
4448 fragP->fr_var += 2;
4449 }
4450 else
4451 {
4452 fragP->fr_subtype = TAB (PCLEA, LONG);
4453 fragP->fr_var += 6;
4454 }
4455 break;
4456 } /* TAB(PCLEA,SZ_UNDEF) */
4457
4458 case TAB (PCINDEX, SZ_UNDEF):
4459 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4460 || cpu_of_arch (current_architecture) < m68020)
4461 {
4462 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4463 }
4464 else
4465 {
4466 fragP->fr_subtype = TAB (PCINDEX, LONG);
4467 fragP->fr_var += 4;
4468 }
4469 break;
4470
4471 default:
4472 break;
4473 }
4474
4475 /* now that SZ_UNDEF are taken care of, check others */
4476 switch (fragP->fr_subtype)
4477 {
4478 case TAB (BCC68000, BYTE):
4479 case TAB (ABRANCH, BYTE):
4480 /* We can't do a short jump to the next instruction, so in that
4481 case we force word mode. At this point S_GET_VALUE should
4482 return the offset of the symbol within its frag. If the
4483 symbol is at the start of a frag, and it is the next frag
4484 with any data in it (usually this is just the next frag, but
4485 assembler listings may introduce empty frags), we must use
4486 word mode. */
4487 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4488 {
4489 fragS *l;
4490
4491 for (l = fragP->fr_next;
4492 l != fragP->fr_symbol->sy_frag;
4493 l = l->fr_next)
4494 if (l->fr_fix + l->fr_var != 0)
4495 break;
4496 if (l == fragP->fr_symbol->sy_frag)
4497 {
4498 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4499 fragP->fr_var += 2;
4500 }
4501 }
4502 break;
4503 default:
4504 break;
4505 }
4506 return fragP->fr_var + fragP->fr_fix - old_fix;
4507 }
4508
4509 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4510 /* the bit-field entries in the relocation_info struct plays hell
4511 with the byte-order problems of cross-assembly. So as a hack,
4512 I added this mach. dependent ri twiddler. Ugly, but it gets
4513 you there. -KWK */
4514 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4515 are symbolnum, most sig. byte first. Last byte is broken up with
4516 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4517 nibble as nuthin. (on Sun 3 at least) */
4518 /* Translate the internal relocation information into target-specific
4519 format. */
4520 #ifdef comment
4521 void
4522 md_ri_to_chars (the_bytes, ri)
4523 char *the_bytes;
4524 struct reloc_info_generic *ri;
4525 {
4526 /* this is easy */
4527 md_number_to_chars (the_bytes, ri->r_address, 4);
4528 /* now the fun stuff */
4529 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4530 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4531 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4532 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4533 ((ri->r_extern << 4) & 0x10));
4534 }
4535
4536 #endif /* comment */
4537
4538 #ifndef BFD_ASSEMBLER
4539 void
4540 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4541 char *where;
4542 fixS *fixP;
4543 relax_addressT segment_address_in_file;
4544 {
4545 /*
4546 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4547 * Out: GNU LD relocation length code: 0, 1, or 2.
4548 */
4549
4550 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4551 long r_symbolnum;
4552
4553 know (fixP->fx_addsy != NULL);
4554
4555 md_number_to_chars (where,
4556 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4557 4);
4558
4559 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4560 ? S_GET_TYPE (fixP->fx_addsy)
4561 : fixP->fx_addsy->sy_number);
4562
4563 where[4] = (r_symbolnum >> 16) & 0x0ff;
4564 where[5] = (r_symbolnum >> 8) & 0x0ff;
4565 where[6] = r_symbolnum & 0x0ff;
4566 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4567 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4568 }
4569 #endif
4570
4571 #endif /* OBJ_AOUT or OBJ_BOUT */
4572
4573 #ifndef WORKING_DOT_WORD
4574 CONST int md_short_jump_size = 4;
4575 CONST int md_long_jump_size = 6;
4576
4577 void
4578 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4579 char *ptr;
4580 addressT from_addr, to_addr;
4581 fragS *frag;
4582 symbolS *to_symbol;
4583 {
4584 valueT offset;
4585
4586 offset = to_addr - (from_addr + 2);
4587
4588 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4589 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4590 }
4591
4592 void
4593 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4594 char *ptr;
4595 addressT from_addr, to_addr;
4596 fragS *frag;
4597 symbolS *to_symbol;
4598 {
4599 valueT offset;
4600
4601 if (cpu_of_arch (current_architecture) < m68020)
4602 {
4603 offset = to_addr - S_GET_VALUE (to_symbol);
4604 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4605 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4606 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4607 0, NO_RELOC);
4608 }
4609 else
4610 {
4611 offset = to_addr - (from_addr + 2);
4612 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4613 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4614 }
4615 }
4616
4617 #endif
4618
4619 /* Different values of OK tell what its OK to return. Things that
4620 aren't OK are an error (what a shock, no?)
4621
4622 0: Everything is OK
4623 10: Absolute 1:8 only
4624 20: Absolute 0:7 only
4625 30: absolute 0:15 only
4626 40: Absolute 0:31 only
4627 50: absolute 0:127 only
4628 55: absolute -64:63 only
4629 60: absolute -128:127 only
4630 70: absolute 0:4095 only
4631 80: No bignums
4632
4633 */
4634
4635 static int
4636 get_num (exp, ok)
4637 struct m68k_exp *exp;
4638 int ok;
4639 {
4640 if (exp->exp.X_op == O_absent)
4641 {
4642 /* Do the same thing the VAX asm does */
4643 op (exp) = O_constant;
4644 adds (exp) = 0;
4645 subs (exp) = 0;
4646 offs (exp) = 0;
4647 if (ok == 10)
4648 {
4649 as_warn ("expression out of range: defaulting to 1");
4650 offs (exp) = 1;
4651 }
4652 }
4653 else if (exp->exp.X_op == O_constant)
4654 {
4655 switch (ok)
4656 {
4657 case 10:
4658 if (offs (exp) < 1 || offs (exp) > 8)
4659 {
4660 as_warn ("expression out of range: defaulting to 1");
4661 offs (exp) = 1;
4662 }
4663 break;
4664 case 20:
4665 if (offs (exp) < 0 || offs (exp) > 7)
4666 goto outrange;
4667 break;
4668 case 30:
4669 if (offs (exp) < 0 || offs (exp) > 15)
4670 goto outrange;
4671 break;
4672 case 40:
4673 if (offs (exp) < 0 || offs (exp) > 32)
4674 goto outrange;
4675 break;
4676 case 50:
4677 if (offs (exp) < 0 || offs (exp) > 127)
4678 goto outrange;
4679 break;
4680 case 55:
4681 if (offs (exp) < -64 || offs (exp) > 63)
4682 goto outrange;
4683 break;
4684 case 60:
4685 if (offs (exp) < -128 || offs (exp) > 127)
4686 goto outrange;
4687 break;
4688 case 70:
4689 if (offs (exp) < 0 || offs (exp) > 4095)
4690 {
4691 outrange:
4692 as_warn ("expression out of range: defaulting to 0");
4693 offs (exp) = 0;
4694 }
4695 break;
4696 default:
4697 break;
4698 }
4699 }
4700 else if (exp->exp.X_op == O_big)
4701 {
4702 if (offs (exp) <= 0 /* flonum */
4703 && (ok == 80 /* no bignums */
4704 || (ok > 10 /* small-int ranges including 0 ok */
4705 /* If we have a flonum zero, a zero integer should
4706 do as well (e.g., in moveq). */
4707 && generic_floating_point_number.exponent == 0
4708 && generic_floating_point_number.low[0] == 0)))
4709 {
4710 /* HACK! Turn it into a long */
4711 LITTLENUM_TYPE words[6];
4712
4713 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4714 op (exp) = O_constant;
4715 adds (exp) = 0;
4716 subs (exp) = 0;
4717 offs (exp) = words[1] | (words[0] << 16);
4718 }
4719 else if (ok != 0)
4720 {
4721 op (exp) = O_constant;
4722 adds (exp) = 0;
4723 subs (exp) = 0;
4724 offs (exp) = (ok == 10) ? 1 : 0;
4725 as_warn ("Can't deal with expression; defaulting to %ld",
4726 offs (exp));
4727 }
4728 }
4729 else
4730 {
4731 if (ok >= 10 && ok <= 70)
4732 {
4733 op (exp) = O_constant;
4734 adds (exp) = 0;
4735 subs (exp) = 0;
4736 offs (exp) = (ok == 10) ? 1 : 0;
4737 as_warn ("Can't deal with expression; defaulting to %ld",
4738 offs (exp));
4739 }
4740 }
4741
4742 if (exp->size != SIZE_UNSPEC)
4743 {
4744 switch (exp->size)
4745 {
4746 case SIZE_UNSPEC:
4747 case SIZE_LONG:
4748 break;
4749 case SIZE_BYTE:
4750 if (!isbyte (offs (exp)))
4751 as_warn ("expression doesn't fit in BYTE");
4752 break;
4753 case SIZE_WORD:
4754 if (!isword (offs (exp)))
4755 as_warn ("expression doesn't fit in WORD");
4756 break;
4757 }
4758 }
4759
4760 return offs (exp);
4761 }
4762
4763 /* These are the back-ends for the various machine dependent pseudo-ops. */
4764 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4765
4766 static void
4767 s_data1 (ignore)
4768 int ignore;
4769 {
4770 subseg_set (data_section, 1);
4771 demand_empty_rest_of_line ();
4772 }
4773
4774 static void
4775 s_data2 (ignore)
4776 int ignore;
4777 {
4778 subseg_set (data_section, 2);
4779 demand_empty_rest_of_line ();
4780 }
4781
4782 static void
4783 s_bss (ignore)
4784 int ignore;
4785 {
4786 /* We don't support putting frags in the BSS segment, we fake it
4787 by marking in_bss, then looking at s_skip for clues. */
4788
4789 subseg_set (bss_section, 0);
4790 demand_empty_rest_of_line ();
4791 }
4792
4793 static void
4794 s_even (ignore)
4795 int ignore;
4796 {
4797 register int temp;
4798 register long temp_fill;
4799
4800 temp = 1; /* JF should be 2? */
4801 temp_fill = get_absolute_expression ();
4802 if (!need_pass_2) /* Never make frag if expect extra pass. */
4803 frag_align (temp, (int) temp_fill);
4804 demand_empty_rest_of_line ();
4805 record_alignment (now_seg, temp);
4806 }
4807
4808 static void
4809 s_proc (ignore)
4810 int ignore;
4811 {
4812 demand_empty_rest_of_line ();
4813 }
4814 \f
4815 /* Pseudo-ops handled for MRI compatibility. */
4816
4817 /* This function returns non-zero if the argument is a conditional
4818 pseudo-op. This is called when checking whether a pending
4819 alignment is needed. */
4820
4821 int
4822 m68k_conditional_pseudoop (pop)
4823 pseudo_typeS *pop;
4824 {
4825 return (pop->poc_handler == s_mri_if
4826 || pop->poc_handler == s_mri_else);
4827 }
4828
4829 /* Handle an MRI style chip specification. */
4830
4831 static void
4832 mri_chip ()
4833 {
4834 char *s;
4835 char c;
4836 int i;
4837
4838 s = input_line_pointer;
4839 c = get_symbol_end ();
4840 for (i = 0; i < n_archs; i++)
4841 if (strcasecmp (s, archs[i].name) == 0)
4842 break;
4843 if (i >= n_archs)
4844 {
4845 as_bad ("%s: unrecognized processor name", s);
4846 *input_line_pointer = c;
4847 ignore_rest_of_line ();
4848 return;
4849 }
4850 *input_line_pointer = c;
4851
4852 if (*input_line_pointer == '/')
4853 current_architecture = 0;
4854 else
4855 current_architecture &= m68881 | m68851;
4856 current_architecture |= archs[i].arch;
4857
4858 while (*input_line_pointer == '/')
4859 {
4860 ++input_line_pointer;
4861 s = input_line_pointer;
4862 c = get_symbol_end ();
4863 if (strcmp (s, "68881") == 0)
4864 current_architecture |= m68881;
4865 else if (strcmp (s, "68851") == 0)
4866 current_architecture |= m68851;
4867 *input_line_pointer = c;
4868 }
4869
4870 /* Update info about available control registers. */
4871 select_control_regs ();
4872 }
4873
4874 /* The MRI CHIP pseudo-op. */
4875
4876 static void
4877 s_chip (ignore)
4878 int ignore;
4879 {
4880 char *stop = NULL;
4881 char stopc;
4882
4883 if (flag_mri)
4884 stop = mri_comment_field (&stopc);
4885 mri_chip ();
4886 if (flag_mri)
4887 mri_comment_end (stop, stopc);
4888 demand_empty_rest_of_line ();
4889 }
4890
4891 /* The MRI FOPT pseudo-op. */
4892
4893 static void
4894 s_fopt (ignore)
4895 int ignore;
4896 {
4897 SKIP_WHITESPACE ();
4898
4899 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4900 {
4901 int temp;
4902
4903 input_line_pointer += 3;
4904 temp = get_absolute_expression ();
4905 if (temp < 0 || temp > 7)
4906 as_bad ("bad coprocessor id");
4907 else
4908 m68k_float_copnum = COP0 + temp;
4909 }
4910 else
4911 {
4912 as_bad ("unrecognized fopt option");
4913 ignore_rest_of_line ();
4914 return;
4915 }
4916
4917 demand_empty_rest_of_line ();
4918 }
4919
4920 /* The structure used to handle the MRI OPT pseudo-op. */
4921
4922 struct opt_action
4923 {
4924 /* The name of the option. */
4925 const char *name;
4926
4927 /* If this is not NULL, just call this function. The first argument
4928 is the ARG field of this structure, the second argument is
4929 whether the option was negated. */
4930 void (*pfn) PARAMS ((int arg, int on));
4931
4932 /* If this is not NULL, and the PFN field is NULL, set the variable
4933 this points to. Set it to the ARG field if the option was not
4934 negated, and the NOTARG field otherwise. */
4935 int *pvar;
4936
4937 /* The value to pass to PFN or to assign to *PVAR. */
4938 int arg;
4939
4940 /* The value to assign to *PVAR if the option is negated. If PFN is
4941 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4942 the option may not be negated. */
4943 int notarg;
4944 };
4945
4946 /* The table used to handle the MRI OPT pseudo-op. */
4947
4948 static void skip_to_comma PARAMS ((int, int));
4949 static void opt_nest PARAMS ((int, int));
4950 static void opt_chip PARAMS ((int, int));
4951 static void opt_list PARAMS ((int, int));
4952 static void opt_list_symbols PARAMS ((int, int));
4953
4954 static const struct opt_action opt_table[] =
4955 {
4956 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4957
4958 /* We do relaxing, so there is little use for these options. */
4959 { "b", 0, 0, 0, 0 },
4960 { "brs", 0, 0, 0, 0 },
4961 { "brb", 0, 0, 0, 0 },
4962 { "brl", 0, 0, 0, 0 },
4963 { "brw", 0, 0, 0, 0 },
4964
4965 { "c", 0, 0, 0, 0 },
4966 { "cex", 0, 0, 0, 0 },
4967 { "case", 0, &symbols_case_sensitive, 1, 0 },
4968 { "cl", 0, 0, 0, 0 },
4969 { "cre", 0, 0, 0, 0 },
4970 { "d", 0, &flag_keep_locals, 1, 0 },
4971 { "e", 0, 0, 0, 0 },
4972 { "f", 0, &flag_short_refs, 1, 0 },
4973 { "frs", 0, &flag_short_refs, 1, 0 },
4974 { "frl", 0, &flag_short_refs, 0, 1 },
4975 { "g", 0, 0, 0, 0 },
4976 { "i", 0, 0, 0, 0 },
4977 { "m", 0, 0, 0, 0 },
4978 { "mex", 0, 0, 0, 0 },
4979 { "mc", 0, 0, 0, 0 },
4980 { "md", 0, 0, 0, 0 },
4981 { "nest", opt_nest, 0, 0, 0 },
4982 { "next", skip_to_comma, 0, 0, 0 },
4983 { "o", 0, 0, 0, 0 },
4984 { "old", 0, 0, 0, 0 },
4985 { "op", skip_to_comma, 0, 0, 0 },
4986 { "pco", 0, 0, 0, 0 },
4987 { "p", opt_chip, 0, 0, 0 },
4988 { "pcr", 0, 0, 0, 0 },
4989 { "pcs", 0, 0, 0, 0 },
4990 { "r", 0, 0, 0, 0 },
4991 { "quick", 0, &m68k_quick, 1, 0 },
4992 { "rel32", 0, &m68k_rel32, 1, 0 },
4993 { "s", opt_list, 0, 0, 0 },
4994 { "t", opt_list_symbols, 0, 0, 0 },
4995 { "w", 0, &flag_no_warnings, 0, 1 },
4996 { "x", 0, 0, 0, 0 }
4997 };
4998
4999 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5000
5001 /* The MRI OPT pseudo-op. */
5002
5003 static void
5004 s_opt (ignore)
5005 int ignore;
5006 {
5007 do
5008 {
5009 int t;
5010 char *s;
5011 char c;
5012 int i;
5013 const struct opt_action *o;
5014
5015 SKIP_WHITESPACE ();
5016
5017 t = 1;
5018 if (*input_line_pointer == '-')
5019 {
5020 ++input_line_pointer;
5021 t = 0;
5022 }
5023 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5024 {
5025 input_line_pointer += 2;
5026 t = 0;
5027 }
5028
5029 s = input_line_pointer;
5030 c = get_symbol_end ();
5031
5032 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5033 {
5034 if (strcasecmp (s, o->name) == 0)
5035 {
5036 if (o->pfn)
5037 {
5038 /* Restore input_line_pointer now in case the option
5039 takes arguments. */
5040 *input_line_pointer = c;
5041 (*o->pfn) (o->arg, t);
5042 }
5043 else if (o->pvar != NULL)
5044 {
5045 if (! t && o->arg == o->notarg)
5046 as_bad ("option `%s' may not be negated", s);
5047 *input_line_pointer = c;
5048 *o->pvar = t ? o->arg : o->notarg;
5049 }
5050 else
5051 *input_line_pointer = c;
5052 break;
5053 }
5054 }
5055 if (i >= OPTCOUNT)
5056 {
5057 as_bad ("option `%s' not recognized", s);
5058 *input_line_pointer = c;
5059 }
5060 }
5061 while (*input_line_pointer++ == ',');
5062
5063 /* Move back to terminating character. */
5064 --input_line_pointer;
5065 demand_empty_rest_of_line ();
5066 }
5067
5068 /* Skip ahead to a comma. This is used for OPT options which we do
5069 not suppor tand which take arguments. */
5070
5071 static void
5072 skip_to_comma (arg, on)
5073 int arg;
5074 int on;
5075 {
5076 while (*input_line_pointer != ','
5077 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5078 ++input_line_pointer;
5079 }
5080
5081 /* Handle the OPT NEST=depth option. */
5082
5083 static void
5084 opt_nest (arg, on)
5085 int arg;
5086 int on;
5087 {
5088 if (*input_line_pointer != '=')
5089 {
5090 as_bad ("bad format of OPT NEST=depth");
5091 return;
5092 }
5093
5094 ++input_line_pointer;
5095 max_macro_nest = get_absolute_expression ();
5096 }
5097
5098 /* Handle the OPT P=chip option. */
5099
5100 static void
5101 opt_chip (arg, on)
5102 int arg;
5103 int on;
5104 {
5105 if (*input_line_pointer != '=')
5106 {
5107 /* This is just OPT P, which we do not support. */
5108 return;
5109 }
5110
5111 ++input_line_pointer;
5112 mri_chip ();
5113 }
5114
5115 /* Handle the OPT S option. */
5116
5117 static void
5118 opt_list (arg, on)
5119 int arg;
5120 int on;
5121 {
5122 listing_list (on);
5123 }
5124
5125 /* Handle the OPT T option. */
5126
5127 static void
5128 opt_list_symbols (arg, on)
5129 int arg;
5130 int on;
5131 {
5132 if (on)
5133 listing |= LISTING_SYMBOLS;
5134 else
5135 listing &=~ LISTING_SYMBOLS;
5136 }
5137
5138 /* Handle the MRI REG pseudo-op. */
5139
5140 static void
5141 s_reg (ignore)
5142 int ignore;
5143 {
5144 char *s;
5145 int c;
5146 struct m68k_op rop;
5147 unsigned long mask;
5148 char *stop = NULL;
5149 char stopc;
5150
5151 if (line_label == NULL)
5152 {
5153 as_bad ("missing label");
5154 ignore_rest_of_line ();
5155 return;
5156 }
5157
5158 if (flag_mri)
5159 stop = mri_comment_field (&stopc);
5160
5161 SKIP_WHITESPACE ();
5162
5163 s = input_line_pointer;
5164 while (isalnum ((unsigned char) *input_line_pointer)
5165 #ifdef REGISTER_PREFIX
5166 || *input_line_pointer == REGISTER_PREFIX
5167 #endif
5168 || *input_line_pointer == '/'
5169 || *input_line_pointer == '-')
5170 ++input_line_pointer;
5171 c = *input_line_pointer;
5172 *input_line_pointer = '\0';
5173
5174 if (m68k_ip_op (s, &rop) != 0)
5175 {
5176 if (rop.error == NULL)
5177 as_bad ("bad register list");
5178 else
5179 as_bad ("bad register list: %s", rop.error);
5180 *input_line_pointer = c;
5181 ignore_rest_of_line ();
5182 return;
5183 }
5184
5185 *input_line_pointer = c;
5186
5187 if (rop.mode == REGLST)
5188 mask = rop.mask;
5189 else if (rop.mode == DREG)
5190 mask = 1 << (rop.reg - DATA0);
5191 else if (rop.mode == AREG)
5192 mask = 1 << (rop.reg - ADDR0 + 8);
5193 else if (rop.mode == FPREG)
5194 mask = 1 << (rop.reg - FP0 + 16);
5195 else if (rop.mode == CONTROL
5196 && rop.reg == FPI)
5197 mask = 1 << 24;
5198 else if (rop.mode == CONTROL
5199 && rop.reg == FPS)
5200 mask = 1 << 25;
5201 else if (rop.mode == CONTROL
5202 && rop.reg == FPC)
5203 mask = 1 << 26;
5204 else
5205 {
5206 as_bad ("bad register list");
5207 ignore_rest_of_line ();
5208 return;
5209 }
5210
5211 S_SET_SEGMENT (line_label, absolute_section);
5212 S_SET_VALUE (line_label, mask);
5213 line_label->sy_frag = &zero_address_frag;
5214
5215 if (flag_mri)
5216 mri_comment_end (stop, stopc);
5217
5218 demand_empty_rest_of_line ();
5219 }
5220
5221 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5222
5223 struct save_opts
5224 {
5225 struct save_opts *next;
5226 int abspcadd;
5227 int symbols_case_sensitive;
5228 int keep_locals;
5229 int short_refs;
5230 int architecture;
5231 int quick;
5232 int rel32;
5233 int listing;
5234 int no_warnings;
5235 /* FIXME: We don't save OPT S. */
5236 };
5237
5238 /* This variable holds the stack of saved options. */
5239
5240 static struct save_opts *save_stack;
5241
5242 /* The MRI SAVE pseudo-op. */
5243
5244 static void
5245 s_save (ignore)
5246 int ignore;
5247 {
5248 struct save_opts *s;
5249
5250 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5251 s->abspcadd = m68k_abspcadd;
5252 s->symbols_case_sensitive = symbols_case_sensitive;
5253 s->keep_locals = flag_keep_locals;
5254 s->short_refs = flag_short_refs;
5255 s->architecture = current_architecture;
5256 s->quick = m68k_quick;
5257 s->rel32 = m68k_rel32;
5258 s->listing = listing;
5259 s->no_warnings = flag_no_warnings;
5260
5261 s->next = save_stack;
5262 save_stack = s;
5263
5264 demand_empty_rest_of_line ();
5265 }
5266
5267 /* The MRI RESTORE pseudo-op. */
5268
5269 static void
5270 s_restore (ignore)
5271 int ignore;
5272 {
5273 struct save_opts *s;
5274
5275 if (save_stack == NULL)
5276 {
5277 as_bad ("restore without save");
5278 ignore_rest_of_line ();
5279 return;
5280 }
5281
5282 s = save_stack;
5283 save_stack = s->next;
5284
5285 m68k_abspcadd = s->abspcadd;
5286 symbols_case_sensitive = s->symbols_case_sensitive;
5287 flag_keep_locals = s->keep_locals;
5288 flag_short_refs = s->short_refs;
5289 current_architecture = s->architecture;
5290 m68k_quick = s->quick;
5291 m68k_rel32 = s->rel32;
5292 listing = s->listing;
5293 flag_no_warnings = s->no_warnings;
5294
5295 free (s);
5296
5297 demand_empty_rest_of_line ();
5298 }
5299
5300 /* Types of MRI structured control directives. */
5301
5302 enum mri_control_type
5303 {
5304 mri_for,
5305 mri_if,
5306 mri_repeat,
5307 mri_while
5308 };
5309
5310 /* This structure is used to stack the MRI structured control
5311 directives. */
5312
5313 struct mri_control_info
5314 {
5315 /* The directive within which this one is enclosed. */
5316 struct mri_control_info *outer;
5317
5318 /* The type of directive. */
5319 enum mri_control_type type;
5320
5321 /* Whether an ELSE has been in an IF. */
5322 int else_seen;
5323
5324 /* The add or sub statement at the end of a FOR. */
5325 char *incr;
5326
5327 /* The label of the top of a FOR or REPEAT loop. */
5328 char *top;
5329
5330 /* The label to jump to for the next iteration, or the else
5331 expression of a conditional. */
5332 char *next;
5333
5334 /* The label to jump to to break out of the loop, or the label past
5335 the end of a conditional. */
5336 char *bottom;
5337 };
5338
5339 /* The stack of MRI structured control directives. */
5340
5341 static struct mri_control_info *mri_control_stack;
5342
5343 /* The current MRI structured control directive index number, used to
5344 generate label names. */
5345
5346 static int mri_control_index;
5347
5348 /* Some function prototypes. */
5349
5350 static char *mri_control_label PARAMS ((void));
5351 static struct mri_control_info *push_mri_control
5352 PARAMS ((enum mri_control_type));
5353 static void pop_mri_control PARAMS ((void));
5354 static int parse_mri_condition PARAMS ((int *));
5355 static int parse_mri_control_operand
5356 PARAMS ((int *, char **, char **, char **, char **));
5357 static int swap_mri_condition PARAMS ((int));
5358 static int reverse_mri_condition PARAMS ((int));
5359 static void build_mri_control_operand
5360 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5361 const char *, int));
5362 static void parse_mri_control_expression
5363 PARAMS ((char *, int, const char *, const char *, int));
5364
5365 /* Generate a new MRI label structured control directive label name. */
5366
5367 static char *
5368 mri_control_label ()
5369 {
5370 char *n;
5371
5372 n = (char *) xmalloc (20);
5373 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5374 ++mri_control_index;
5375 return n;
5376 }
5377
5378 /* Create a new MRI structured control directive. */
5379
5380 static struct mri_control_info *
5381 push_mri_control (type)
5382 enum mri_control_type type;
5383 {
5384 struct mri_control_info *n;
5385
5386 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5387
5388 n->type = type;
5389 n->else_seen = 0;
5390 if (type == mri_if || type == mri_while)
5391 n->top = NULL;
5392 else
5393 n->top = mri_control_label ();
5394 n->next = mri_control_label ();
5395 n->bottom = mri_control_label ();
5396
5397 n->outer = mri_control_stack;
5398 mri_control_stack = n;
5399
5400 return n;
5401 }
5402
5403 /* Pop off the stack of MRI structured control directives. */
5404
5405 static void
5406 pop_mri_control ()
5407 {
5408 struct mri_control_info *n;
5409
5410 n = mri_control_stack;
5411 mri_control_stack = n->outer;
5412 if (n->top != NULL)
5413 free (n->top);
5414 free (n->next);
5415 free (n->bottom);
5416 free (n);
5417 }
5418
5419 /* Recognize a condition code in an MRI structured control expression. */
5420
5421 static int
5422 parse_mri_condition (pcc)
5423 int *pcc;
5424 {
5425 char c1, c2;
5426
5427 know (*input_line_pointer == '<');
5428
5429 ++input_line_pointer;
5430 c1 = *input_line_pointer++;
5431 c2 = *input_line_pointer++;
5432
5433 if (*input_line_pointer != '>')
5434 {
5435 as_bad ("syntax error in structured control directive");
5436 return 0;
5437 }
5438
5439 ++input_line_pointer;
5440 SKIP_WHITESPACE ();
5441
5442 if (isupper (c1))
5443 c1 = tolower (c1);
5444 if (isupper (c2))
5445 c2 = tolower (c2);
5446
5447 *pcc = (c1 << 8) | c2;
5448
5449 return 1;
5450 }
5451
5452 /* Parse a single operand in an MRI structured control expression. */
5453
5454 static int
5455 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5456 int *pcc;
5457 char **leftstart;
5458 char **leftstop;
5459 char **rightstart;
5460 char **rightstop;
5461 {
5462 char *s;
5463
5464 SKIP_WHITESPACE ();
5465
5466 *pcc = -1;
5467 *leftstart = NULL;
5468 *leftstop = NULL;
5469 *rightstart = NULL;
5470 *rightstop = NULL;
5471
5472 if (*input_line_pointer == '<')
5473 {
5474 /* It's just a condition code. */
5475 return parse_mri_condition (pcc);
5476 }
5477
5478 /* Look ahead for the condition code. */
5479 for (s = input_line_pointer; *s != '\0'; ++s)
5480 {
5481 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5482 break;
5483 }
5484 if (*s == '\0')
5485 {
5486 as_bad ("missing condition code in structured control directive");
5487 return 0;
5488 }
5489
5490 *leftstart = input_line_pointer;
5491 *leftstop = s;
5492 if (*leftstop > *leftstart
5493 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5494 --*leftstop;
5495
5496 input_line_pointer = s;
5497 if (! parse_mri_condition (pcc))
5498 return 0;
5499
5500 /* Look ahead for AND or OR or end of line. */
5501 for (s = input_line_pointer; *s != '\0'; ++s)
5502 {
5503 if ((strncasecmp (s, "AND", 3) == 0
5504 && (s[3] == '.' || ! is_part_of_name (s[3])))
5505 || (strncasecmp (s, "OR", 2) == 0
5506 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5507 break;
5508 }
5509
5510 *rightstart = input_line_pointer;
5511 *rightstop = s;
5512 if (*rightstop > *rightstart
5513 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5514 --*rightstop;
5515
5516 input_line_pointer = s;
5517
5518 return 1;
5519 }
5520
5521 #define MCC(b1, b2) (((b1) << 8) | (b2))
5522
5523 /* Swap the sense of a condition. This changes the condition so that
5524 it generates the same result when the operands are swapped. */
5525
5526 static int
5527 swap_mri_condition (cc)
5528 int cc;
5529 {
5530 switch (cc)
5531 {
5532 case MCC ('h', 'i'): return MCC ('c', 's');
5533 case MCC ('l', 's'): return MCC ('c', 'c');
5534 case MCC ('c', 'c'): return MCC ('l', 's');
5535 case MCC ('c', 's'): return MCC ('h', 'i');
5536 case MCC ('p', 'l'): return MCC ('m', 'i');
5537 case MCC ('m', 'i'): return MCC ('p', 'l');
5538 case MCC ('g', 'e'): return MCC ('l', 'e');
5539 case MCC ('l', 't'): return MCC ('g', 't');
5540 case MCC ('g', 't'): return MCC ('l', 't');
5541 case MCC ('l', 'e'): return MCC ('g', 'e');
5542 }
5543 return cc;
5544 }
5545
5546 /* Reverse the sense of a condition. */
5547
5548 static int
5549 reverse_mri_condition (cc)
5550 int cc;
5551 {
5552 switch (cc)
5553 {
5554 case MCC ('h', 'i'): return MCC ('l', 's');
5555 case MCC ('l', 's'): return MCC ('h', 'i');
5556 case MCC ('c', 'c'): return MCC ('c', 's');
5557 case MCC ('c', 's'): return MCC ('c', 'c');
5558 case MCC ('n', 'e'): return MCC ('e', 'q');
5559 case MCC ('e', 'q'): return MCC ('n', 'e');
5560 case MCC ('v', 'c'): return MCC ('v', 's');
5561 case MCC ('v', 's'): return MCC ('v', 'c');
5562 case MCC ('p', 'l'): return MCC ('m', 'i');
5563 case MCC ('m', 'i'): return MCC ('p', 'l');
5564 case MCC ('g', 'e'): return MCC ('l', 't');
5565 case MCC ('l', 't'): return MCC ('g', 'e');
5566 case MCC ('g', 't'): return MCC ('l', 'e');
5567 case MCC ('l', 'e'): return MCC ('g', 't');
5568 }
5569 return cc;
5570 }
5571
5572 /* Build an MRI structured control expression. This generates test
5573 and branch instructions. It goes to TRUELAB if the condition is
5574 true, and to FALSELAB if the condition is false. Exactly one of
5575 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5576 is the size qualifier for the expression. EXTENT is the size to
5577 use for the branch. */
5578
5579 static void
5580 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5581 rightstop, truelab, falselab, extent)
5582 int qual;
5583 int cc;
5584 char *leftstart;
5585 char *leftstop;
5586 char *rightstart;
5587 char *rightstop;
5588 const char *truelab;
5589 const char *falselab;
5590 int extent;
5591 {
5592 char *buf;
5593 char *s;
5594
5595 if (leftstart != NULL)
5596 {
5597 struct m68k_op leftop, rightop;
5598 char c;
5599
5600 /* Swap the compare operands, if necessary, to produce a legal
5601 m68k compare instruction. Comparing a register operand with
5602 a non-register operand requires the register to be on the
5603 right (cmp, cmpa). Comparing an immediate value with
5604 anything requires the immediate value to be on the left
5605 (cmpi). */
5606
5607 c = *leftstop;
5608 *leftstop = '\0';
5609 (void) m68k_ip_op (leftstart, &leftop);
5610 *leftstop = c;
5611
5612 c = *rightstop;
5613 *rightstop = '\0';
5614 (void) m68k_ip_op (rightstart, &rightop);
5615 *rightstop = c;
5616
5617 if (rightop.mode == IMMED
5618 || ((leftop.mode == DREG || leftop.mode == AREG)
5619 && (rightop.mode != DREG && rightop.mode != AREG)))
5620 {
5621 char *temp;
5622
5623 cc = swap_mri_condition (cc);
5624 temp = leftstart;
5625 leftstart = rightstart;
5626 rightstart = temp;
5627 temp = leftstop;
5628 leftstop = rightstop;
5629 rightstop = temp;
5630 }
5631 }
5632
5633 if (truelab == NULL)
5634 {
5635 cc = reverse_mri_condition (cc);
5636 truelab = falselab;
5637 }
5638
5639 if (leftstart != NULL)
5640 {
5641 buf = (char *) xmalloc (20
5642 + (leftstop - leftstart)
5643 + (rightstop - rightstart));
5644 s = buf;
5645 *s++ = 'c';
5646 *s++ = 'm';
5647 *s++ = 'p';
5648 if (qual != '\0')
5649 *s++ = qual;
5650 *s++ = ' ';
5651 memcpy (s, leftstart, leftstop - leftstart);
5652 s += leftstop - leftstart;
5653 *s++ = ',';
5654 memcpy (s, rightstart, rightstop - rightstart);
5655 s += rightstop - rightstart;
5656 *s = '\0';
5657 md_assemble (buf);
5658 free (buf);
5659 }
5660
5661 buf = (char *) xmalloc (20 + strlen (truelab));
5662 s = buf;
5663 *s++ = 'b';
5664 *s++ = cc >> 8;
5665 *s++ = cc & 0xff;
5666 if (extent != '\0')
5667 *s++ = extent;
5668 *s++ = ' ';
5669 strcpy (s, truelab);
5670 md_assemble (buf);
5671 free (buf);
5672 }
5673
5674 /* Parse an MRI structured control expression. This generates test
5675 and branch instructions. STOP is where the expression ends. It
5676 goes to TRUELAB if the condition is true, and to FALSELAB if the
5677 condition is false. Exactly one of TRUELAB and FALSELAB will be
5678 NULL, meaning to fall through. QUAL is the size qualifier for the
5679 expression. EXTENT is the size to use for the branch. */
5680
5681 static void
5682 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5683 char *stop;
5684 int qual;
5685 const char *truelab;
5686 const char *falselab;
5687 int extent;
5688 {
5689 int c;
5690 int cc;
5691 char *leftstart;
5692 char *leftstop;
5693 char *rightstart;
5694 char *rightstop;
5695
5696 c = *stop;
5697 *stop = '\0';
5698
5699 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5700 &rightstart, &rightstop))
5701 {
5702 *stop = c;
5703 return;
5704 }
5705
5706 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5707 {
5708 const char *flab;
5709
5710 if (falselab != NULL)
5711 flab = falselab;
5712 else
5713 flab = mri_control_label ();
5714
5715 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5716 rightstop, (const char *) NULL, flab, extent);
5717
5718 input_line_pointer += 3;
5719 if (*input_line_pointer != '.'
5720 || input_line_pointer[1] == '\0')
5721 qual = '\0';
5722 else
5723 {
5724 qual = input_line_pointer[1];
5725 input_line_pointer += 2;
5726 }
5727
5728 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5729 &rightstart, &rightstop))
5730 {
5731 *stop = c;
5732 return;
5733 }
5734
5735 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5736 rightstop, truelab, falselab, extent);
5737
5738 if (falselab == NULL)
5739 colon (flab);
5740 }
5741 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5742 {
5743 const char *tlab;
5744
5745 if (truelab != NULL)
5746 tlab = truelab;
5747 else
5748 tlab = mri_control_label ();
5749
5750 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5751 rightstop, tlab, (const char *) NULL, extent);
5752
5753 input_line_pointer += 2;
5754 if (*input_line_pointer != '.'
5755 || input_line_pointer[1] == '\0')
5756 qual = '\0';
5757 else
5758 {
5759 qual = input_line_pointer[1];
5760 input_line_pointer += 2;
5761 }
5762
5763 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5764 &rightstart, &rightstop))
5765 {
5766 *stop = c;
5767 return;
5768 }
5769
5770 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5771 rightstop, truelab, falselab, extent);
5772
5773 if (truelab == NULL)
5774 colon (tlab);
5775 }
5776 else
5777 {
5778 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5779 rightstop, truelab, falselab, extent);
5780 }
5781
5782 *stop = c;
5783 if (input_line_pointer != stop)
5784 as_bad ("syntax error in structured control directive");
5785 }
5786
5787 /* Handle the MRI IF pseudo-op. This may be a structured control
5788 directive, or it may be a regular assembler conditional, depending
5789 on its operands. */
5790
5791 static void
5792 s_mri_if (qual)
5793 int qual;
5794 {
5795 char *s;
5796 int c;
5797 struct mri_control_info *n;
5798
5799 /* A structured control directive must end with THEN with an
5800 optional qualifier. */
5801 s = input_line_pointer;
5802 while (! is_end_of_line[(unsigned char) *s]
5803 && (! flag_mri || *s != '*'))
5804 ++s;
5805 --s;
5806 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5807 --s;
5808
5809 if (s - input_line_pointer > 1
5810 && s[-1] == '.')
5811 s -= 2;
5812
5813 if (s - input_line_pointer < 3
5814 || strncasecmp (s - 3, "THEN", 4) != 0)
5815 {
5816 if (qual != '\0')
5817 {
5818 as_bad ("missing then");
5819 ignore_rest_of_line ();
5820 return;
5821 }
5822
5823 /* It's a conditional. */
5824 s_if (O_ne);
5825 return;
5826 }
5827
5828 /* Since this might be a conditional if, this pseudo-op will be
5829 called even if we are supported to be ignoring input. Double
5830 check now. Clobber *input_line_pointer so that ignore_input
5831 thinks that this is not a special pseudo-op. */
5832 c = *input_line_pointer;
5833 *input_line_pointer = 0;
5834 if (ignore_input ())
5835 {
5836 *input_line_pointer = c;
5837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5838 ++input_line_pointer;
5839 demand_empty_rest_of_line ();
5840 return;
5841 }
5842 *input_line_pointer = c;
5843
5844 n = push_mri_control (mri_if);
5845
5846 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5847 n->next, s[1] == '.' ? s[2] : '\0');
5848
5849 if (s[1] == '.')
5850 input_line_pointer = s + 3;
5851 else
5852 input_line_pointer = s + 1;
5853
5854 if (flag_mri)
5855 {
5856 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5857 ++input_line_pointer;
5858 }
5859
5860 demand_empty_rest_of_line ();
5861 }
5862
5863 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5864 structured IF, associate the ELSE with the IF. Otherwise, assume
5865 it is a conditional else. */
5866
5867 static void
5868 s_mri_else (qual)
5869 int qual;
5870 {
5871 int c;
5872 char *buf;
5873 char q[2];
5874
5875 if (qual == '\0'
5876 && (mri_control_stack == NULL
5877 || mri_control_stack->type != mri_if
5878 || mri_control_stack->else_seen))
5879 {
5880 s_else (0);
5881 return;
5882 }
5883
5884 c = *input_line_pointer;
5885 *input_line_pointer = 0;
5886 if (ignore_input ())
5887 {
5888 *input_line_pointer = c;
5889 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5890 ++input_line_pointer;
5891 demand_empty_rest_of_line ();
5892 return;
5893 }
5894 *input_line_pointer = c;
5895
5896 if (mri_control_stack == NULL
5897 || mri_control_stack->type != mri_if
5898 || mri_control_stack->else_seen)
5899 {
5900 as_bad ("else without matching if");
5901 ignore_rest_of_line ();
5902 return;
5903 }
5904
5905 mri_control_stack->else_seen = 1;
5906
5907 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5908 q[0] = qual;
5909 q[1] = '\0';
5910 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5911 md_assemble (buf);
5912 free (buf);
5913
5914 colon (mri_control_stack->next);
5915
5916 if (flag_mri)
5917 {
5918 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5919 ++input_line_pointer;
5920 }
5921
5922 demand_empty_rest_of_line ();
5923 }
5924
5925 /* Handle the MRI ENDI pseudo-op. */
5926
5927 static void
5928 s_mri_endi (ignore)
5929 int ignore;
5930 {
5931 if (mri_control_stack == NULL
5932 || mri_control_stack->type != mri_if)
5933 {
5934 as_bad ("endi without matching if");
5935 ignore_rest_of_line ();
5936 return;
5937 }
5938
5939 /* ignore_input will not return true for ENDI, so we don't need to
5940 worry about checking it again here. */
5941
5942 if (! mri_control_stack->else_seen)
5943 colon (mri_control_stack->next);
5944 colon (mri_control_stack->bottom);
5945
5946 pop_mri_control ();
5947
5948 if (flag_mri)
5949 {
5950 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5951 ++input_line_pointer;
5952 }
5953
5954 demand_empty_rest_of_line ();
5955 }
5956
5957 /* Handle the MRI BREAK pseudo-op. */
5958
5959 static void
5960 s_mri_break (extent)
5961 int extent;
5962 {
5963 struct mri_control_info *n;
5964 char *buf;
5965 char ex[2];
5966
5967 n = mri_control_stack;
5968 while (n != NULL
5969 && n->type != mri_for
5970 && n->type != mri_repeat
5971 && n->type != mri_while)
5972 n = n->outer;
5973 if (n == NULL)
5974 {
5975 as_bad ("break outside of structured loop");
5976 ignore_rest_of_line ();
5977 return;
5978 }
5979
5980 buf = (char *) xmalloc (20 + strlen (n->bottom));
5981 ex[0] = extent;
5982 ex[1] = '\0';
5983 sprintf (buf, "bra%s %s", ex, n->bottom);
5984 md_assemble (buf);
5985 free (buf);
5986
5987 if (flag_mri)
5988 {
5989 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5990 ++input_line_pointer;
5991 }
5992
5993 demand_empty_rest_of_line ();
5994 }
5995
5996 /* Handle the MRI NEXT pseudo-op. */
5997
5998 static void
5999 s_mri_next (extent)
6000 int extent;
6001 {
6002 struct mri_control_info *n;
6003 char *buf;
6004 char ex[2];
6005
6006 n = mri_control_stack;
6007 while (n != NULL
6008 && n->type != mri_for
6009 && n->type != mri_repeat
6010 && n->type != mri_while)
6011 n = n->outer;
6012 if (n == NULL)
6013 {
6014 as_bad ("next outside of structured loop");
6015 ignore_rest_of_line ();
6016 return;
6017 }
6018
6019 buf = (char *) xmalloc (20 + strlen (n->next));
6020 ex[0] = extent;
6021 ex[1] = '\0';
6022 sprintf (buf, "bra%s %s", ex, n->next);
6023 md_assemble (buf);
6024 free (buf);
6025
6026 if (flag_mri)
6027 {
6028 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6029 ++input_line_pointer;
6030 }
6031
6032 demand_empty_rest_of_line ();
6033 }
6034
6035 /* Handle the MRI FOR pseudo-op. */
6036
6037 static void
6038 s_mri_for (qual)
6039 int qual;
6040 {
6041 const char *varstart, *varstop;
6042 const char *initstart, *initstop;
6043 const char *endstart, *endstop;
6044 const char *bystart, *bystop;
6045 int up;
6046 int by;
6047 int extent;
6048 struct mri_control_info *n;
6049 char *buf;
6050 char *s;
6051 char ex[2];
6052
6053 /* The syntax is
6054 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6055 */
6056
6057 SKIP_WHITESPACE ();
6058 varstart = input_line_pointer;
6059
6060 /* Look for the '='. */
6061 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6062 && *input_line_pointer != '=')
6063 ++input_line_pointer;
6064 if (*input_line_pointer != '=')
6065 {
6066 as_bad ("missing =");
6067 ignore_rest_of_line ();
6068 return;
6069 }
6070
6071 varstop = input_line_pointer;
6072 if (varstop > varstart
6073 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6074 --varstop;
6075
6076 ++input_line_pointer;
6077
6078 initstart = input_line_pointer;
6079
6080 /* Look for TO or DOWNTO. */
6081 up = 1;
6082 initstop = NULL;
6083 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6084 {
6085 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6086 && ! is_part_of_name (input_line_pointer[2]))
6087 {
6088 initstop = input_line_pointer;
6089 input_line_pointer += 2;
6090 break;
6091 }
6092 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6093 && ! is_part_of_name (input_line_pointer[6]))
6094 {
6095 initstop = input_line_pointer;
6096 up = 0;
6097 input_line_pointer += 6;
6098 break;
6099 }
6100 ++input_line_pointer;
6101 }
6102 if (initstop == NULL)
6103 {
6104 as_bad ("missing to or downto");
6105 ignore_rest_of_line ();
6106 return;
6107 }
6108 if (initstop > initstart
6109 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6110 --initstop;
6111
6112 SKIP_WHITESPACE ();
6113 endstart = input_line_pointer;
6114
6115 /* Look for BY or DO. */
6116 by = 0;
6117 endstop = NULL;
6118 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6119 {
6120 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6121 && ! is_part_of_name (input_line_pointer[2]))
6122 {
6123 endstop = input_line_pointer;
6124 by = 1;
6125 input_line_pointer += 2;
6126 break;
6127 }
6128 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6129 && (input_line_pointer[2] == '.'
6130 || ! is_part_of_name (input_line_pointer[2])))
6131 {
6132 endstop = input_line_pointer;
6133 input_line_pointer += 2;
6134 break;
6135 }
6136 ++input_line_pointer;
6137 }
6138 if (endstop == NULL)
6139 {
6140 as_bad ("missing do");
6141 ignore_rest_of_line ();
6142 return;
6143 }
6144 if (endstop > endstart
6145 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6146 --endstop;
6147
6148 if (! by)
6149 {
6150 bystart = "#1";
6151 bystop = bystart + 2;
6152 }
6153 else
6154 {
6155 SKIP_WHITESPACE ();
6156 bystart = input_line_pointer;
6157
6158 /* Look for DO. */
6159 bystop = NULL;
6160 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6161 {
6162 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6163 && (input_line_pointer[2] == '.'
6164 || ! is_part_of_name (input_line_pointer[2])))
6165 {
6166 bystop = input_line_pointer;
6167 input_line_pointer += 2;
6168 break;
6169 }
6170 ++input_line_pointer;
6171 }
6172 if (bystop == NULL)
6173 {
6174 as_bad ("missing do");
6175 ignore_rest_of_line ();
6176 return;
6177 }
6178 if (bystop > bystart
6179 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6180 --bystop;
6181 }
6182
6183 if (*input_line_pointer != '.')
6184 extent = '\0';
6185 else
6186 {
6187 extent = input_line_pointer[1];
6188 input_line_pointer += 2;
6189 }
6190
6191 /* We have fully parsed the FOR operands. Now build the loop. */
6192
6193 n = push_mri_control (mri_for);
6194
6195 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6196
6197 /* move init,var */
6198 s = buf;
6199 *s++ = 'm';
6200 *s++ = 'o';
6201 *s++ = 'v';
6202 *s++ = 'e';
6203 if (qual != '\0')
6204 *s++ = qual;
6205 *s++ = ' ';
6206 memcpy (s, initstart, initstop - initstart);
6207 s += initstop - initstart;
6208 *s++ = ',';
6209 memcpy (s, varstart, varstop - varstart);
6210 s += varstop - varstart;
6211 *s = '\0';
6212 md_assemble (buf);
6213
6214 colon (n->top);
6215
6216 /* cmp end,var */
6217 s = buf;
6218 *s++ = 'c';
6219 *s++ = 'm';
6220 *s++ = 'p';
6221 if (qual != '\0')
6222 *s++ = qual;
6223 *s++ = ' ';
6224 memcpy (s, endstart, endstop - endstart);
6225 s += endstop - endstart;
6226 *s++ = ',';
6227 memcpy (s, varstart, varstop - varstart);
6228 s += varstop - varstart;
6229 *s = '\0';
6230 md_assemble (buf);
6231
6232 /* bcc bottom */
6233 ex[0] = extent;
6234 ex[1] = '\0';
6235 if (up)
6236 sprintf (buf, "blt%s %s", ex, n->bottom);
6237 else
6238 sprintf (buf, "bgt%s %s", ex, n->bottom);
6239 md_assemble (buf);
6240
6241 /* Put together the add or sub instruction used by ENDF. */
6242 s = buf;
6243 if (up)
6244 strcpy (s, "add");
6245 else
6246 strcpy (s, "sub");
6247 s += 3;
6248 if (qual != '\0')
6249 *s++ = qual;
6250 *s++ = ' ';
6251 memcpy (s, bystart, bystop - bystart);
6252 s += bystop - bystart;
6253 *s++ = ',';
6254 memcpy (s, varstart, varstop - varstart);
6255 s += varstop - varstart;
6256 *s = '\0';
6257 n->incr = buf;
6258
6259 if (flag_mri)
6260 {
6261 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6262 ++input_line_pointer;
6263 }
6264
6265 demand_empty_rest_of_line ();
6266 }
6267
6268 /* Handle the MRI ENDF pseudo-op. */
6269
6270 static void
6271 s_mri_endf (ignore)
6272 int ignore;
6273 {
6274 if (mri_control_stack == NULL
6275 || mri_control_stack->type != mri_for)
6276 {
6277 as_bad ("endf without for");
6278 ignore_rest_of_line ();
6279 return;
6280 }
6281
6282 colon (mri_control_stack->next);
6283
6284 md_assemble (mri_control_stack->incr);
6285
6286 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6287 md_assemble (mri_control_stack->incr);
6288
6289 free (mri_control_stack->incr);
6290
6291 colon (mri_control_stack->bottom);
6292
6293 pop_mri_control ();
6294
6295 if (flag_mri)
6296 {
6297 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6298 ++input_line_pointer;
6299 }
6300
6301 demand_empty_rest_of_line ();
6302 }
6303
6304 /* Handle the MRI REPEAT pseudo-op. */
6305
6306 static void
6307 s_mri_repeat (ignore)
6308 int ignore;
6309 {
6310 struct mri_control_info *n;
6311
6312 n = push_mri_control (mri_repeat);
6313 colon (n->top);
6314 if (flag_mri)
6315 {
6316 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6317 ++input_line_pointer;
6318 }
6319 demand_empty_rest_of_line ();
6320 }
6321
6322 /* Handle the MRI UNTIL pseudo-op. */
6323
6324 static void
6325 s_mri_until (qual)
6326 int qual;
6327 {
6328 char *s;
6329
6330 if (mri_control_stack == NULL
6331 || mri_control_stack->type != mri_repeat)
6332 {
6333 as_bad ("until without repeat");
6334 ignore_rest_of_line ();
6335 return;
6336 }
6337
6338 colon (mri_control_stack->next);
6339
6340 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6341 ;
6342
6343 parse_mri_control_expression (s, qual, (const char *) NULL,
6344 mri_control_stack->top, '\0');
6345
6346 colon (mri_control_stack->bottom);
6347
6348 input_line_pointer = s;
6349
6350 pop_mri_control ();
6351
6352 if (flag_mri)
6353 {
6354 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6355 ++input_line_pointer;
6356 }
6357
6358 demand_empty_rest_of_line ();
6359 }
6360
6361 /* Handle the MRI WHILE pseudo-op. */
6362
6363 static void
6364 s_mri_while (qual)
6365 int qual;
6366 {
6367 char *s;
6368
6369 struct mri_control_info *n;
6370
6371 s = input_line_pointer;
6372 while (! is_end_of_line[(unsigned char) *s]
6373 && (! flag_mri || *s != '*'))
6374 s++;
6375 --s;
6376 while (*s == ' ' || *s == '\t')
6377 --s;
6378 if (s - input_line_pointer > 1
6379 && s[-1] == '.')
6380 s -= 2;
6381 if (s - input_line_pointer < 2
6382 || strncasecmp (s - 1, "DO", 2) != 0)
6383 {
6384 as_bad ("missing do");
6385 ignore_rest_of_line ();
6386 return;
6387 }
6388
6389 n = push_mri_control (mri_while);
6390
6391 colon (n->next);
6392
6393 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6394 s[1] == '.' ? s[2] : '\0');
6395
6396 input_line_pointer = s + 1;
6397 if (*input_line_pointer == '.')
6398 input_line_pointer += 2;
6399
6400 if (flag_mri)
6401 {
6402 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6403 ++input_line_pointer;
6404 }
6405
6406 demand_empty_rest_of_line ();
6407 }
6408
6409 /* Handle the MRI ENDW pseudo-op. */
6410
6411 static void
6412 s_mri_endw (ignore)
6413 int ignore;
6414 {
6415 char *buf;
6416
6417 if (mri_control_stack == NULL
6418 || mri_control_stack->type != mri_while)
6419 {
6420 as_bad ("endw without while");
6421 ignore_rest_of_line ();
6422 return;
6423 }
6424
6425 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6426 sprintf (buf, "bra %s", mri_control_stack->next);
6427 md_assemble (buf);
6428 free (buf);
6429
6430 colon (mri_control_stack->bottom);
6431
6432 pop_mri_control ();
6433
6434 if (flag_mri)
6435 {
6436 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6437 ++input_line_pointer;
6438 }
6439
6440 demand_empty_rest_of_line ();
6441 }
6442 \f
6443 /*
6444 * md_parse_option
6445 * Invocation line includes a switch not recognized by the base assembler.
6446 * See if it's a processor-specific option. These are:
6447 *
6448 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6449 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6450 * Select the architecture. Instructions or features not
6451 * supported by the selected architecture cause fatal
6452 * errors. More than one may be specified. The default is
6453 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6454 * for -m68000, and -m68882 is a synonym for -m68881.
6455 * -[A]m[c]no-68851, -[A]m[c]no-68881
6456 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6457 * so don't use or document it, but that's the way the parsing
6458 * works).
6459 *
6460 * -pic Indicates PIC.
6461 * -k Indicates PIC. (Sun 3 only.)
6462 *
6463 * --bitwise-or
6464 * Permit `|' to be used in expressions.
6465 *
6466 */
6467
6468 #ifdef OBJ_ELF
6469 CONST char *md_shortopts = "lSA:m:kQ:V";
6470 #else
6471 CONST char *md_shortopts = "lSA:m:k";
6472 #endif
6473
6474 struct option md_longopts[] = {
6475 #define OPTION_PIC (OPTION_MD_BASE)
6476 {"pic", no_argument, NULL, OPTION_PIC},
6477 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6478 {"register-prefix-optional", no_argument, NULL,
6479 OPTION_REGISTER_PREFIX_OPTIONAL},
6480 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6481 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6482 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6483 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6484 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6485 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6486 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6487 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6488 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6489 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6490 {NULL, no_argument, NULL, 0}
6491 };
6492 size_t md_longopts_size = sizeof(md_longopts);
6493
6494 int
6495 md_parse_option (c, arg)
6496 int c;
6497 char *arg;
6498 {
6499 switch (c)
6500 {
6501 case 'l': /* -l means keep external to 2 bit offset
6502 rather than 16 bit one */
6503 flag_short_refs = 1;
6504 break;
6505
6506 case 'S': /* -S means that jbsr's always turn into
6507 jsr's. */
6508 flag_long_jumps = 1;
6509 break;
6510
6511 case 'A':
6512 if (*arg == 'm')
6513 arg++;
6514 /* intentional fall-through */
6515 case 'm':
6516
6517 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6518 {
6519 int i;
6520 unsigned long arch;
6521 const char *oarg = arg;
6522
6523 arg += 3;
6524 if (*arg == 'm')
6525 {
6526 arg++;
6527 if (arg[0] == 'c' && arg[1] == '6')
6528 arg++;
6529 }
6530 for (i = 0; i < n_archs; i++)
6531 if (!strcmp (arg, archs[i].name))
6532 break;
6533 if (i == n_archs)
6534 {
6535 unknown:
6536 as_bad ("unrecognized option `%s'", oarg);
6537 return 0;
6538 }
6539 arch = archs[i].arch;
6540 if (arch == m68881)
6541 no_68881 = 1;
6542 else if (arch == m68851)
6543 no_68851 = 1;
6544 else
6545 goto unknown;
6546 }
6547 else
6548 {
6549 int i;
6550
6551 if (arg[0] == 'c' && arg[1] == '6')
6552 arg++;
6553
6554 for (i = 0; i < n_archs; i++)
6555 if (!strcmp (arg, archs[i].name))
6556 {
6557 unsigned long arch = archs[i].arch;
6558 if (cpu_of_arch (arch))
6559 /* It's a cpu spec. */
6560 {
6561 current_architecture &= ~m68000up;
6562 current_architecture |= arch;
6563 }
6564 else if (arch == m68881)
6565 {
6566 current_architecture |= m68881;
6567 no_68881 = 0;
6568 }
6569 else if (arch == m68851)
6570 {
6571 current_architecture |= m68851;
6572 no_68851 = 0;
6573 }
6574 else
6575 /* ??? */
6576 abort ();
6577 break;
6578 }
6579 if (i == n_archs)
6580 {
6581 as_bad ("unrecognized architecture specification `%s'", arg);
6582 return 0;
6583 }
6584 }
6585 break;
6586
6587 case OPTION_PIC:
6588 case 'k':
6589 flag_want_pic = 1;
6590 break; /* -pic, Position Independent Code */
6591
6592 case OPTION_REGISTER_PREFIX_OPTIONAL:
6593 flag_reg_prefix_optional = 1;
6594 reg_prefix_optional_seen = 1;
6595 break;
6596
6597 /* -V: SVR4 argument to print version ID. */
6598 case 'V':
6599 print_version_id ();
6600 break;
6601
6602 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6603 should be emitted or not. FIXME: Not implemented. */
6604 case 'Q':
6605 break;
6606
6607 case OPTION_BITWISE_OR:
6608 {
6609 char *n, *t;
6610 const char *s;
6611
6612 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6613 t = n;
6614 for (s = m68k_comment_chars; *s != '\0'; s++)
6615 if (*s != '|')
6616 *t++ = *s;
6617 *t = '\0';
6618 m68k_comment_chars = n;
6619 }
6620 break;
6621
6622 case OPTION_BASE_SIZE_DEFAULT_16:
6623 m68k_index_width_default = SIZE_WORD;
6624 break;
6625
6626 case OPTION_BASE_SIZE_DEFAULT_32:
6627 m68k_index_width_default = SIZE_LONG;
6628 break;
6629
6630 case OPTION_DISP_SIZE_DEFAULT_16:
6631 m68k_rel32 = 0;
6632 m68k_rel32_from_cmdline = 1;
6633 break;
6634
6635 case OPTION_DISP_SIZE_DEFAULT_32:
6636 m68k_rel32 = 1;
6637 m68k_rel32_from_cmdline = 1;
6638 break;
6639
6640 default:
6641 return 0;
6642 }
6643
6644 return 1;
6645 }
6646
6647 void
6648 md_show_usage (stream)
6649 FILE *stream;
6650 {
6651 fprintf(stream, "\
6652 680X0 options:\n\
6653 -l use 1 word for refs to undefined symbols [default 2]\n\
6654 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6655 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6656 | -mcpu32 | -m5200\n\
6657 specify variant of 680X0 architecture [default 68020]\n\
6658 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6659 target has/lacks floating-point coprocessor\n\
6660 [default yes for 68020, 68030, and cpu32]\n");
6661 fprintf(stream, "\
6662 -m68851 | -mno-68851\n\
6663 target has/lacks memory-management unit coprocessor\n\
6664 [default yes for 68020 and up]\n\
6665 -pic, -k generate position independent code\n\
6666 -S turn jbsr into jsr\n\
6667 --register-prefix-optional\n\
6668 recognize register names without prefix character\n\
6669 --bitwise-or do not treat `|' as a comment character\n");
6670 fprintf (stream, "\
6671 --base-size-default-16 base reg without size is 16 bits\n\
6672 --base-size-default-32 base reg without size is 32 bits (default)\n\
6673 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6674 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6675 }
6676 \f
6677 #ifdef TEST2
6678
6679 /* TEST2: Test md_assemble() */
6680 /* Warning, this routine probably doesn't work anymore */
6681
6682 main ()
6683 {
6684 struct m68k_it the_ins;
6685 char buf[120];
6686 char *cp;
6687 int n;
6688
6689 m68k_ip_begin ();
6690 for (;;)
6691 {
6692 if (!gets (buf) || !*buf)
6693 break;
6694 if (buf[0] == '|' || buf[1] == '.')
6695 continue;
6696 for (cp = buf; *cp; cp++)
6697 if (*cp == '\t')
6698 *cp = ' ';
6699 if (is_label (buf))
6700 continue;
6701 memset (&the_ins, '\0', sizeof (the_ins));
6702 m68k_ip (&the_ins, buf);
6703 if (the_ins.error)
6704 {
6705 printf ("Error %s in %s\n", the_ins.error, buf);
6706 }
6707 else
6708 {
6709 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6710 for (n = 0; n < the_ins.numo; n++)
6711 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6712 printf (" ");
6713 print_the_insn (&the_ins.opcode[0], stdout);
6714 (void) putchar ('\n');
6715 }
6716 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6717 {
6718 if (the_ins.operands[n].error)
6719 {
6720 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6721 continue;
6722 }
6723 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6724 if (the_ins.operands[n].b_const)
6725 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6726 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6727 if (the_ins.operands[n].b_iadd)
6728 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6729 (void) putchar ('\n');
6730 }
6731 }
6732 m68k_ip_end ();
6733 return 0;
6734 }
6735
6736 is_label (str)
6737 char *str;
6738 {
6739 while (*str == ' ')
6740 str++;
6741 while (*str && *str != ' ')
6742 str++;
6743 if (str[-1] == ':' || str[1] == '=')
6744 return 1;
6745 return 0;
6746 }
6747
6748 #endif
6749
6750 /* Possible states for relaxation:
6751
6752 0 0 branch offset byte (bra, etc)
6753 0 1 word
6754 0 2 long
6755
6756 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6757 1 1 word
6758 1 2 long
6759
6760 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6761 2 1 word-long
6762 2 2 long-word
6763 2 3 long-long
6764
6765 */
6766
6767 /* We have no need to default values of symbols. */
6768
6769 /* ARGSUSED */
6770 symbolS *
6771 md_undefined_symbol (name)
6772 char *name;
6773 {
6774 return 0;
6775 }
6776
6777 /* Round up a section size to the appropriate boundary. */
6778 valueT
6779 md_section_align (segment, size)
6780 segT segment;
6781 valueT size;
6782 {
6783 return size; /* Byte alignment is fine */
6784 }
6785
6786 /* Exactly what point is a PC-relative offset relative TO?
6787 On the 68k, it is relative to the address of the first extension
6788 word. The difference between the addresses of the offset and the
6789 first extension word is stored in fx_pcrel_adjust. */
6790 long
6791 md_pcrel_from (fixP)
6792 fixS *fixP;
6793 {
6794 int adjust;
6795
6796 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6797 -1 as 64. */
6798 adjust = fixP->fx_pcrel_adjust;
6799 if (adjust == 64)
6800 adjust = -1;
6801 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6802 }
6803
6804 #ifndef BFD_ASSEMBLER
6805 /*ARGSUSED*/
6806 void
6807 tc_coff_symbol_emit_hook (ignore)
6808 symbolS *ignore;
6809 {
6810 }
6811
6812 int
6813 tc_coff_sizemachdep (frag)
6814 fragS *frag;
6815 {
6816 switch (frag->fr_subtype & 0x3)
6817 {
6818 case BYTE:
6819 return 1;
6820 case SHORT:
6821 return 2;
6822 case LONG:
6823 return 4;
6824 default:
6825 abort ();
6826 return 0;
6827 }
6828 }
6829 #endif
6830
6831 /* end of tc-m68k.c */
GDB Binutils - Deliverables
This page took 0.168289 seconds and 5 git commands to generate.