1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define SKIP_SPACE_TABS(S) \
46 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor (void);
50 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 #define AT mips_opts.at
108 extern int target_big_endian
;
110 /* The name of the readonly data section. */
111 #define RDATA_SECTION_NAME ".rodata"
113 /* Ways in which an instruction can be "appended" to the output. */
115 /* Just add it normally. */
118 /* Add it normally and then add a nop. */
121 /* Turn an instruction with a delay slot into a "compact" version. */
124 /* Insert the instruction before the last one. */
128 /* Information about an instruction, including its format, operands
132 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
133 const struct mips_opcode
*insn_mo
;
135 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
136 a copy of INSN_MO->match with the operands filled in. If we have
137 decided to use an extended MIPS16 instruction, this includes the
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
159 /* True if this instruction is complete. */
160 unsigned int complete_p
: 1;
162 /* True if this instruction is cleared from history by unconditional
164 unsigned int cleared_p
: 1;
167 /* The ABI to use. */
178 /* MIPS ABI we are using for this output file. */
179 static enum mips_abi_level mips_abi
= NO_ABI
;
181 /* Whether or not we have code that can call pic code. */
182 int mips_abicalls
= FALSE
;
184 /* Whether or not we have code which can be put into a shared
186 static bfd_boolean mips_in_shared
= TRUE
;
188 /* This is the set of options which may be modified by the .set
189 pseudo-op. We use a struct so that .set push and .set pop are more
192 struct mips_set_options
194 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
195 if it has not been initialized. Changed by `.set mipsN', and the
196 -mipsN command line option, and the default CPU. */
198 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
199 <asename>', by command line options, and based on the default
202 /* Whether we are assembling for the mips16 processor. 0 if we are
203 not, 1 if we are, and -1 if the value has not been initialized.
204 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
205 -nomips16 command line options, and the default CPU. */
207 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
208 1 if we are, and -1 if the value has not been initialized. Changed
209 by `.set micromips' and `.set nomicromips', and the -mmicromips
210 and -mno-micromips command line options, and the default CPU. */
212 /* Non-zero if we should not reorder instructions. Changed by `.set
213 reorder' and `.set noreorder'. */
215 /* Non-zero if we should not permit the register designated "assembler
216 temporary" to be used in instructions. The value is the register
217 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
218 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
220 /* Non-zero if we should warn when a macro instruction expands into
221 more than one machine instruction. Changed by `.set nomacro' and
223 int warn_about_macros
;
224 /* Non-zero if we should not move instructions. Changed by `.set
225 move', `.set volatile', `.set nomove', and `.set novolatile'. */
227 /* Non-zero if we should not optimize branches by moving the target
228 of the branch into the delay slot. Actually, we don't perform
229 this optimization anyhow. Changed by `.set bopt' and `.set
232 /* Non-zero if we should not autoextend mips16 instructions.
233 Changed by `.set autoextend' and `.set noautoextend'. */
235 /* True if we should only emit 32-bit microMIPS instructions.
236 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
237 and -mno-insn32 command line options. */
239 /* Restrict general purpose registers and floating point registers
240 to 32 bit. This is initially determined when -mgp32 or -mfp32
241 is passed but can changed if the assembler code uses .set mipsN. */
244 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
245 command line option, and the default CPU. */
247 /* True if ".set sym32" is in effect. */
249 /* True if floating-point operations are not allowed. Changed by .set
250 softfloat or .set hardfloat, by command line options -msoft-float or
251 -mhard-float. The default is false. */
252 bfd_boolean soft_float
;
254 /* True if only single-precision floating-point operations are allowed.
255 Changed by .set singlefloat or .set doublefloat, command-line options
256 -msingle-float or -mdouble-float. The default is false. */
257 bfd_boolean single_float
;
260 /* This is the struct we use to hold the current set of options. Note
261 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
262 -1 to indicate that they have not been initialized. */
264 /* True if -mgp32 was passed. */
265 static int file_mips_gp32
= -1;
267 /* True if -mfp32 was passed. */
268 static int file_mips_fp32
= -1;
270 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
271 static int file_mips_soft_float
= 0;
273 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
274 static int file_mips_single_float
= 0;
276 /* True if -mnan=2008, false if -mnan=legacy. */
277 static bfd_boolean mips_flag_nan2008
= FALSE
;
279 static struct mips_set_options mips_opts
=
281 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
282 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
283 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
284 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
285 /* soft_float */ FALSE
, /* single_float */ FALSE
288 /* The set of ASEs that were selected on the command line, either
289 explicitly via ASE options or implicitly through things like -march. */
290 static unsigned int file_ase
;
292 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
293 static unsigned int file_ase_explicit
;
295 /* These variables are filled in with the masks of registers used.
296 The object format code reads them and puts them in the appropriate
298 unsigned long mips_gprmask
;
299 unsigned long mips_cprmask
[4];
301 /* MIPS ISA we are using for this output file. */
302 static int file_mips_isa
= ISA_UNKNOWN
;
304 /* True if any MIPS16 code was produced. */
305 static int file_ase_mips16
;
307 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
308 || mips_opts.isa == ISA_MIPS32R2 \
309 || mips_opts.isa == ISA_MIPS32R3 \
310 || mips_opts.isa == ISA_MIPS32R5 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2 \
313 || mips_opts.isa == ISA_MIPS64R3 \
314 || mips_opts.isa == ISA_MIPS64R5)
316 /* True if any microMIPS code was produced. */
317 static int file_ase_micromips
;
319 /* True if we want to create R_MIPS_JALR for jalr $25. */
321 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
323 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
324 because there's no place for any addend, the only acceptable
325 expression is a bare symbol. */
326 #define MIPS_JALR_HINT_P(EXPR) \
327 (!HAVE_IN_PLACE_ADDENDS \
328 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2 \
359 || (ISA) == ISA_MIPS64R3 \
360 || (ISA) == ISA_MIPS64R5)
362 /* Return true if ISA supports 64 bit wide float registers. */
363 #define ISA_HAS_64BIT_FPRS(ISA) \
364 ((ISA) == ISA_MIPS3 \
365 || (ISA) == ISA_MIPS4 \
366 || (ISA) == ISA_MIPS5 \
367 || (ISA) == ISA_MIPS32R2 \
368 || (ISA) == ISA_MIPS32R3 \
369 || (ISA) == ISA_MIPS32R5 \
370 || (ISA) == ISA_MIPS64 \
371 || (ISA) == ISA_MIPS64R2 \
372 || (ISA) == ISA_MIPS64R3 \
373 || (ISA) == ISA_MIPS64R5 )
375 /* Return true if ISA supports 64-bit right rotate (dror et al.)
377 #define ISA_HAS_DROR(ISA) \
378 ((ISA) == ISA_MIPS64R2 \
379 || (ISA) == ISA_MIPS64R3 \
380 || (ISA) == ISA_MIPS64R5 \
381 || (mips_opts.micromips \
382 && ISA_HAS_64BIT_REGS (ISA)) \
385 /* Return true if ISA supports 32-bit right rotate (ror et al.)
387 #define ISA_HAS_ROR(ISA) \
388 ((ISA) == ISA_MIPS32R2 \
389 || (ISA) == ISA_MIPS32R3 \
390 || (ISA) == ISA_MIPS32R5 \
391 || (ISA) == ISA_MIPS64R2 \
392 || (ISA) == ISA_MIPS64R3 \
393 || (ISA) == ISA_MIPS64R5 \
394 || (mips_opts.ase & ASE_SMARTMIPS) \
395 || mips_opts.micromips \
398 /* Return true if ISA supports single-precision floats in odd registers. */
399 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
400 ((ISA) == ISA_MIPS32 \
401 || (ISA) == ISA_MIPS32R2 \
402 || (ISA) == ISA_MIPS32R3 \
403 || (ISA) == ISA_MIPS32R5 \
404 || (ISA) == ISA_MIPS64 \
405 || (ISA) == ISA_MIPS64R2 \
406 || (ISA) == ISA_MIPS64R3 \
407 || (ISA) == ISA_MIPS64R5)
409 /* Return true if ISA supports move to/from high part of a 64-bit
410 floating-point register. */
411 #define ISA_HAS_MXHC1(ISA) \
412 ((ISA) == ISA_MIPS32R2 \
413 || (ISA) == ISA_MIPS32R3 \
414 || (ISA) == ISA_MIPS32R5 \
415 || (ISA) == ISA_MIPS64R2 \
416 || (ISA) == ISA_MIPS64R3 \
417 || (ISA) == ISA_MIPS64R5)
419 #define HAVE_32BIT_GPRS \
420 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
422 #define HAVE_32BIT_FPRS \
423 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
425 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
426 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
428 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
430 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
432 /* True if relocations are stored in-place. */
433 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
435 /* The ABI-derived address size. */
436 #define HAVE_64BIT_ADDRESSES \
437 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
438 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
440 /* The size of symbolic constants (i.e., expressions of the form
441 "SYMBOL" or "SYMBOL + OFFSET"). */
442 #define HAVE_32BIT_SYMBOLS \
443 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
444 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
446 /* Addresses are loaded in different ways, depending on the address size
447 in use. The n32 ABI Documentation also mandates the use of additions
448 with overflow checking, but existing implementations don't follow it. */
449 #define ADDRESS_ADD_INSN \
450 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
452 #define ADDRESS_ADDI_INSN \
453 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
455 #define ADDRESS_LOAD_INSN \
456 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
458 #define ADDRESS_STORE_INSN \
459 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
461 /* Return true if the given CPU supports the MIPS16 ASE. */
462 #define CPU_HAS_MIPS16(cpu) \
463 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
464 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
466 /* Return true if the given CPU supports the microMIPS ASE. */
467 #define CPU_HAS_MICROMIPS(cpu) 0
469 /* True if CPU has a dror instruction. */
470 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
472 /* True if CPU has a ror instruction. */
473 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
475 /* True if CPU is in the Octeon family */
476 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
478 /* True if CPU has seq/sne and seqi/snei instructions. */
479 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
481 /* True, if CPU has support for ldc1 and sdc1. */
482 #define CPU_HAS_LDC1_SDC1(CPU) \
483 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
485 /* True if mflo and mfhi can be immediately followed by instructions
486 which write to the HI and LO registers.
488 According to MIPS specifications, MIPS ISAs I, II, and III need
489 (at least) two instructions between the reads of HI/LO and
490 instructions which write them, and later ISAs do not. Contradicting
491 the MIPS specifications, some MIPS IV processor user manuals (e.g.
492 the UM for the NEC Vr5000) document needing the instructions between
493 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
494 MIPS64 and later ISAs to have the interlocks, plus any specific
495 earlier-ISA CPUs for which CPU documentation declares that the
496 instructions are really interlocked. */
497 #define hilo_interlocks \
498 (mips_opts.isa == ISA_MIPS32 \
499 || mips_opts.isa == ISA_MIPS32R2 \
500 || mips_opts.isa == ISA_MIPS32R3 \
501 || mips_opts.isa == ISA_MIPS32R5 \
502 || mips_opts.isa == ISA_MIPS64 \
503 || mips_opts.isa == ISA_MIPS64R2 \
504 || mips_opts.isa == ISA_MIPS64R3 \
505 || mips_opts.isa == ISA_MIPS64R5 \
506 || mips_opts.arch == CPU_R4010 \
507 || mips_opts.arch == CPU_R5900 \
508 || mips_opts.arch == CPU_R10000 \
509 || mips_opts.arch == CPU_R12000 \
510 || mips_opts.arch == CPU_R14000 \
511 || mips_opts.arch == CPU_R16000 \
512 || mips_opts.arch == CPU_RM7000 \
513 || mips_opts.arch == CPU_VR5500 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from the GPRs after they are loaded from memory, and thus does not
519 require nops to be inserted. This applies to instructions marked
520 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
521 level I and microMIPS mode instructions are always interlocked. */
522 #define gpr_interlocks \
523 (mips_opts.isa != ISA_MIPS1 \
524 || mips_opts.arch == CPU_R3900 \
525 || mips_opts.arch == CPU_R5900 \
526 || mips_opts.micromips \
529 /* Whether the processor uses hardware interlocks to avoid delays
530 required by coprocessor instructions, and thus does not require
531 nops to be inserted. This applies to instructions marked
532 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
533 between instructions marked INSN_WRITE_COND_CODE and ones marked
534 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
535 levels I, II, and III and microMIPS mode instructions are always
537 /* Itbl support may require additional care here. */
538 #define cop_interlocks \
539 ((mips_opts.isa != ISA_MIPS1 \
540 && mips_opts.isa != ISA_MIPS2 \
541 && mips_opts.isa != ISA_MIPS3) \
542 || mips_opts.arch == CPU_R4300 \
543 || mips_opts.micromips \
546 /* Whether the processor uses hardware interlocks to protect reads
547 from coprocessor registers after they are loaded from memory, and
548 thus does not require nops to be inserted. This applies to
549 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
550 requires at MIPS ISA level I and microMIPS mode instructions are
551 always interlocked. */
552 #define cop_mem_interlocks \
553 (mips_opts.isa != ISA_MIPS1 \
554 || mips_opts.micromips \
557 /* Is this a mfhi or mflo instruction? */
558 #define MF_HILO_INSN(PINFO) \
559 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
561 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
562 has been selected. This implies, in particular, that addresses of text
563 labels have their LSB set. */
564 #define HAVE_CODE_COMPRESSION \
565 ((mips_opts.mips16 | mips_opts.micromips) != 0)
567 /* The minimum and maximum signed values that can be stored in a GPR. */
568 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
569 #define GPR_SMIN (-GPR_SMAX - 1)
571 /* MIPS PIC level. */
573 enum mips_pic_level mips_pic
;
575 /* 1 if we should generate 32 bit offsets from the $gp register in
576 SVR4_PIC mode. Currently has no meaning in other modes. */
577 static int mips_big_got
= 0;
579 /* 1 if trap instructions should used for overflow rather than break
581 static int mips_trap
= 0;
583 /* 1 if double width floating point constants should not be constructed
584 by assembling two single width halves into two single width floating
585 point registers which just happen to alias the double width destination
586 register. On some architectures this aliasing can be disabled by a bit
587 in the status register, and the setting of this bit cannot be determined
588 automatically at assemble time. */
589 static int mips_disable_float_construction
;
591 /* Non-zero if any .set noreorder directives were used. */
593 static int mips_any_noreorder
;
595 /* Non-zero if nops should be inserted when the register referenced in
596 an mfhi/mflo instruction is read in the next two instructions. */
597 static int mips_7000_hilo_fix
;
599 /* The size of objects in the small data section. */
600 static unsigned int g_switch_value
= 8;
601 /* Whether the -G option was used. */
602 static int g_switch_seen
= 0;
607 /* If we can determine in advance that GP optimization won't be
608 possible, we can skip the relaxation stuff that tries to produce
609 GP-relative references. This makes delay slot optimization work
612 This function can only provide a guess, but it seems to work for
613 gcc output. It needs to guess right for gcc, otherwise gcc
614 will put what it thinks is a GP-relative instruction in a branch
617 I don't know if a fix is needed for the SVR4_PIC mode. I've only
618 fixed it for the non-PIC mode. KR 95/04/07 */
619 static int nopic_need_relax (symbolS
*, int);
621 /* handle of the OPCODE hash table */
622 static struct hash_control
*op_hash
= NULL
;
624 /* The opcode hash table we use for the mips16. */
625 static struct hash_control
*mips16_op_hash
= NULL
;
627 /* The opcode hash table we use for the microMIPS ASE. */
628 static struct hash_control
*micromips_op_hash
= NULL
;
630 /* This array holds the chars that always start a comment. If the
631 pre-processor is disabled, these aren't very useful */
632 const char comment_chars
[] = "#";
634 /* This array holds the chars that only start a comment at the beginning of
635 a line. If the line seems to have the form '# 123 filename'
636 .line and .file directives will appear in the pre-processed output */
637 /* Note that input_file.c hand checks for '#' at the beginning of the
638 first line of the input file. This is because the compiler outputs
639 #NO_APP at the beginning of its output. */
640 /* Also note that C style comments are always supported. */
641 const char line_comment_chars
[] = "#";
643 /* This array holds machine specific line separator characters. */
644 const char line_separator_chars
[] = ";";
646 /* Chars that can be used to separate mant from exp in floating point nums */
647 const char EXP_CHARS
[] = "eE";
649 /* Chars that mean this number is a floating point constant */
652 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
654 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
655 changed in read.c . Ideally it shouldn't have to know about it at all,
656 but nothing is ideal around here.
659 /* Types of printf format used for instruction-related error messages.
660 "I" means int ("%d") and "S" means string ("%s"). */
661 enum mips_insn_error_format
{
667 /* Information about an error that was found while assembling the current
669 struct mips_insn_error
{
670 /* We sometimes need to match an instruction against more than one
671 opcode table entry. Errors found during this matching are reported
672 against a particular syntactic argument rather than against the
673 instruction as a whole. We grade these messages so that errors
674 against argument N have a greater priority than an error against
675 any argument < N, since the former implies that arguments up to N
676 were acceptable and that the opcode entry was therefore a closer match.
677 If several matches report an error against the same argument,
678 we only use that error if it is the same in all cases.
680 min_argnum is the minimum argument number for which an error message
681 should be accepted. It is 0 if MSG is against the instruction as
685 /* The printf()-style message, including its format and arguments. */
686 enum mips_insn_error_format format
;
694 /* The error that should be reported for the current instruction. */
695 static struct mips_insn_error insn_error
;
697 static int auto_align
= 1;
699 /* When outputting SVR4 PIC code, the assembler needs to know the
700 offset in the stack frame from which to restore the $gp register.
701 This is set by the .cprestore pseudo-op, and saved in this
703 static offsetT mips_cprestore_offset
= -1;
705 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
706 more optimizations, it can use a register value instead of a memory-saved
707 offset and even an other register than $gp as global pointer. */
708 static offsetT mips_cpreturn_offset
= -1;
709 static int mips_cpreturn_register
= -1;
710 static int mips_gp_register
= GP
;
711 static int mips_gprel_offset
= 0;
713 /* Whether mips_cprestore_offset has been set in the current function
714 (or whether it has already been warned about, if not). */
715 static int mips_cprestore_valid
= 0;
717 /* This is the register which holds the stack frame, as set by the
718 .frame pseudo-op. This is needed to implement .cprestore. */
719 static int mips_frame_reg
= SP
;
721 /* Whether mips_frame_reg has been set in the current function
722 (or whether it has already been warned about, if not). */
723 static int mips_frame_reg_valid
= 0;
725 /* To output NOP instructions correctly, we need to keep information
726 about the previous two instructions. */
728 /* Whether we are optimizing. The default value of 2 means to remove
729 unneeded NOPs and swap branch instructions when possible. A value
730 of 1 means to not swap branches. A value of 0 means to always
732 static int mips_optimize
= 2;
734 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
735 equivalent to seeing no -g option at all. */
736 static int mips_debug
= 0;
738 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
739 #define MAX_VR4130_NOPS 4
741 /* The maximum number of NOPs needed to fill delay slots. */
742 #define MAX_DELAY_NOPS 2
744 /* The maximum number of NOPs needed for any purpose. */
747 /* A list of previous instructions, with index 0 being the most recent.
748 We need to look back MAX_NOPS instructions when filling delay slots
749 or working around processor errata. We need to look back one
750 instruction further if we're thinking about using history[0] to
751 fill a branch delay slot. */
752 static struct mips_cl_insn history
[1 + MAX_NOPS
];
754 /* Arrays of operands for each instruction. */
755 #define MAX_OPERANDS 6
756 struct mips_operand_array
{
757 const struct mips_operand
*operand
[MAX_OPERANDS
];
759 static struct mips_operand_array
*mips_operands
;
760 static struct mips_operand_array
*mips16_operands
;
761 static struct mips_operand_array
*micromips_operands
;
763 /* Nop instructions used by emit_nop. */
764 static struct mips_cl_insn nop_insn
;
765 static struct mips_cl_insn mips16_nop_insn
;
766 static struct mips_cl_insn micromips_nop16_insn
;
767 static struct mips_cl_insn micromips_nop32_insn
;
769 /* The appropriate nop for the current mode. */
770 #define NOP_INSN (mips_opts.mips16 \
772 : (mips_opts.micromips \
773 ? (mips_opts.insn32 \
774 ? µmips_nop32_insn \
775 : µmips_nop16_insn) \
778 /* The size of NOP_INSN in bytes. */
779 #define NOP_INSN_SIZE ((mips_opts.mips16 \
780 || (mips_opts.micromips && !mips_opts.insn32)) \
783 /* If this is set, it points to a frag holding nop instructions which
784 were inserted before the start of a noreorder section. If those
785 nops turn out to be unnecessary, the size of the frag can be
787 static fragS
*prev_nop_frag
;
789 /* The number of nop instructions we created in prev_nop_frag. */
790 static int prev_nop_frag_holds
;
792 /* The number of nop instructions that we know we need in
794 static int prev_nop_frag_required
;
796 /* The number of instructions we've seen since prev_nop_frag. */
797 static int prev_nop_frag_since
;
799 /* Relocations against symbols are sometimes done in two parts, with a HI
800 relocation and a LO relocation. Each relocation has only 16 bits of
801 space to store an addend. This means that in order for the linker to
802 handle carries correctly, it must be able to locate both the HI and
803 the LO relocation. This means that the relocations must appear in
804 order in the relocation table.
806 In order to implement this, we keep track of each unmatched HI
807 relocation. We then sort them so that they immediately precede the
808 corresponding LO relocation. */
813 struct mips_hi_fixup
*next
;
816 /* The section this fixup is in. */
820 /* The list of unmatched HI relocs. */
822 static struct mips_hi_fixup
*mips_hi_fixup_list
;
824 /* The frag containing the last explicit relocation operator.
825 Null if explicit relocations have not been used. */
827 static fragS
*prev_reloc_op_frag
;
829 /* Map mips16 register numbers to normal MIPS register numbers. */
831 static const unsigned int mips16_to_32_reg_map
[] =
833 16, 17, 2, 3, 4, 5, 6, 7
836 /* Map microMIPS register numbers to normal MIPS register numbers. */
838 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
840 /* The microMIPS registers with type h. */
841 static const unsigned int micromips_to_32_reg_h_map1
[] =
843 5, 5, 6, 4, 4, 4, 4, 4
845 static const unsigned int micromips_to_32_reg_h_map2
[] =
847 6, 7, 7, 21, 22, 5, 6, 7
850 /* The microMIPS registers with type m. */
851 static const unsigned int micromips_to_32_reg_m_map
[] =
853 0, 17, 2, 3, 16, 18, 19, 20
856 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
858 /* Classifies the kind of instructions we're interested in when
859 implementing -mfix-vr4120. */
860 enum fix_vr4120_class
868 NUM_FIX_VR4120_CLASSES
871 /* ...likewise -mfix-loongson2f-jump. */
872 static bfd_boolean mips_fix_loongson2f_jump
;
874 /* ...likewise -mfix-loongson2f-nop. */
875 static bfd_boolean mips_fix_loongson2f_nop
;
877 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
878 static bfd_boolean mips_fix_loongson2f
;
880 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
881 there must be at least one other instruction between an instruction
882 of type X and an instruction of type Y. */
883 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
885 /* True if -mfix-vr4120 is in force. */
886 static int mips_fix_vr4120
;
888 /* ...likewise -mfix-vr4130. */
889 static int mips_fix_vr4130
;
891 /* ...likewise -mfix-24k. */
892 static int mips_fix_24k
;
894 /* ...likewise -mfix-rm7000 */
895 static int mips_fix_rm7000
;
897 /* ...likewise -mfix-cn63xxp1 */
898 static bfd_boolean mips_fix_cn63xxp1
;
900 /* We don't relax branches by default, since this causes us to expand
901 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
902 fail to compute the offset before expanding the macro to the most
903 efficient expansion. */
905 static int mips_relax_branch
;
907 /* The expansion of many macros depends on the type of symbol that
908 they refer to. For example, when generating position-dependent code,
909 a macro that refers to a symbol may have two different expansions,
910 one which uses GP-relative addresses and one which uses absolute
911 addresses. When generating SVR4-style PIC, a macro may have
912 different expansions for local and global symbols.
914 We handle these situations by generating both sequences and putting
915 them in variant frags. In position-dependent code, the first sequence
916 will be the GP-relative one and the second sequence will be the
917 absolute one. In SVR4 PIC, the first sequence will be for global
918 symbols and the second will be for local symbols.
920 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
921 SECOND are the lengths of the two sequences in bytes. These fields
922 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
923 the subtype has the following flags:
926 Set if it has been decided that we should use the second
927 sequence instead of the first.
930 Set in the first variant frag if the macro's second implementation
931 is longer than its first. This refers to the macro as a whole,
932 not an individual relaxation.
935 Set in the first variant frag if the macro appeared in a .set nomacro
936 block and if one alternative requires a warning but the other does not.
939 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
942 RELAX_DELAY_SLOT_16BIT
943 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
946 RELAX_DELAY_SLOT_SIZE_FIRST
947 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
948 the macro is of the wrong size for the branch delay slot.
950 RELAX_DELAY_SLOT_SIZE_SECOND
951 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
952 the macro is of the wrong size for the branch delay slot.
954 The frag's "opcode" points to the first fixup for relaxable code.
956 Relaxable macros are generated using a sequence such as:
958 relax_start (SYMBOL);
959 ... generate first expansion ...
961 ... generate second expansion ...
964 The code and fixups for the unwanted alternative are discarded
965 by md_convert_frag. */
966 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
968 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
969 #define RELAX_SECOND(X) ((X) & 0xff)
970 #define RELAX_USE_SECOND 0x10000
971 #define RELAX_SECOND_LONGER 0x20000
972 #define RELAX_NOMACRO 0x40000
973 #define RELAX_DELAY_SLOT 0x80000
974 #define RELAX_DELAY_SLOT_16BIT 0x100000
975 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
976 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
978 /* Branch without likely bit. If label is out of range, we turn:
980 beq reg1, reg2, label
990 with the following opcode replacements:
997 bltzal <-> bgezal (with jal label instead of j label)
999 Even though keeping the delay slot instruction in the delay slot of
1000 the branch would be more efficient, it would be very tricky to do
1001 correctly, because we'd have to introduce a variable frag *after*
1002 the delay slot instruction, and expand that instead. Let's do it
1003 the easy way for now, even if the branch-not-taken case now costs
1004 one additional instruction. Out-of-range branches are not supposed
1005 to be common, anyway.
1007 Branch likely. If label is out of range, we turn:
1009 beql reg1, reg2, label
1010 delay slot (annulled if branch not taken)
1019 delay slot (executed only if branch taken)
1022 It would be possible to generate a shorter sequence by losing the
1023 likely bit, generating something like:
1028 delay slot (executed only if branch taken)
1040 bltzall -> bgezal (with jal label instead of j label)
1041 bgezall -> bltzal (ditto)
1044 but it's not clear that it would actually improve performance. */
1045 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1046 ((relax_substateT) \
1049 | ((toofar) ? 0x20 : 0) \
1050 | ((link) ? 0x40 : 0) \
1051 | ((likely) ? 0x80 : 0) \
1052 | ((uncond) ? 0x100 : 0)))
1053 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1054 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1055 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1056 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1057 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1058 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1060 /* For mips16 code, we use an entirely different form of relaxation.
1061 mips16 supports two versions of most instructions which take
1062 immediate values: a small one which takes some small value, and a
1063 larger one which takes a 16 bit value. Since branches also follow
1064 this pattern, relaxing these values is required.
1066 We can assemble both mips16 and normal MIPS code in a single
1067 object. Therefore, we need to support this type of relaxation at
1068 the same time that we support the relaxation described above. We
1069 use the high bit of the subtype field to distinguish these cases.
1071 The information we store for this type of relaxation is the
1072 argument code found in the opcode file for this relocation, whether
1073 the user explicitly requested a small or extended form, and whether
1074 the relocation is in a jump or jal delay slot. That tells us the
1075 size of the value, and how it should be stored. We also store
1076 whether the fragment is considered to be extended or not. We also
1077 store whether this is known to be a branch to a different section,
1078 whether we have tried to relax this frag yet, and whether we have
1079 ever extended a PC relative fragment because of a shift count. */
1080 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1083 | ((small) ? 0x100 : 0) \
1084 | ((ext) ? 0x200 : 0) \
1085 | ((dslot) ? 0x400 : 0) \
1086 | ((jal_dslot) ? 0x800 : 0))
1087 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1088 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1089 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1090 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1091 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1092 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1093 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1094 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1095 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1096 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1097 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1098 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1100 /* For microMIPS code, we use relaxation similar to one we use for
1101 MIPS16 code. Some instructions that take immediate values support
1102 two encodings: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. As some branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both microMIPS and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use one of the high bits of the subtype field to distinguish these
1112 The information we store for this type of relaxation is the argument
1113 code found in the opcode file for this relocation, the register
1114 selected as the assembler temporary, whether the branch is
1115 unconditional, whether it is compact, whether it stores the link
1116 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1117 branches to a sequence of instructions is enabled, and whether the
1118 displacement of a branch is too large to fit as an immediate argument
1119 of a 16-bit and a 32-bit branch, respectively. */
1120 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1121 relax32, toofar16, toofar32) \
1124 | (((at) & 0x1f) << 8) \
1125 | ((uncond) ? 0x2000 : 0) \
1126 | ((compact) ? 0x4000 : 0) \
1127 | ((link) ? 0x8000 : 0) \
1128 | ((relax32) ? 0x10000 : 0) \
1129 | ((toofar16) ? 0x20000 : 0) \
1130 | ((toofar32) ? 0x40000 : 0))
1131 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1132 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1133 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1134 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1135 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1136 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1137 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1139 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1140 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1141 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1142 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1143 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1144 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1146 /* Sign-extend 16-bit value X. */
1147 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1149 /* Is the given value a sign-extended 32-bit value? */
1150 #define IS_SEXT_32BIT_NUM(x) \
1151 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1152 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1154 /* Is the given value a sign-extended 16-bit value? */
1155 #define IS_SEXT_16BIT_NUM(x) \
1156 (((x) &~ (offsetT) 0x7fff) == 0 \
1157 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1159 /* Is the given value a sign-extended 12-bit value? */
1160 #define IS_SEXT_12BIT_NUM(x) \
1161 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1163 /* Is the given value a sign-extended 9-bit value? */
1164 #define IS_SEXT_9BIT_NUM(x) \
1165 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1167 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1168 #define IS_ZEXT_32BIT_NUM(x) \
1169 (((x) &~ (offsetT) 0xffffffff) == 0 \
1170 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1172 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1174 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1175 (((STRUCT) >> (SHIFT)) & (MASK))
1177 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1178 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1180 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1181 : EXTRACT_BITS ((INSN).insn_opcode, \
1182 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1183 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1184 EXTRACT_BITS ((INSN).insn_opcode, \
1185 MIPS16OP_MASK_##FIELD, \
1186 MIPS16OP_SH_##FIELD)
1188 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1189 #define MIPS16_EXTEND (0xf000U << 16)
1191 /* Whether or not we are emitting a branch-likely macro. */
1192 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1194 /* Global variables used when generating relaxable macros. See the
1195 comment above RELAX_ENCODE for more details about how relaxation
1198 /* 0 if we're not emitting a relaxable macro.
1199 1 if we're emitting the first of the two relaxation alternatives.
1200 2 if we're emitting the second alternative. */
1203 /* The first relaxable fixup in the current frag. (In other words,
1204 the first fixup that refers to relaxable code.) */
1207 /* sizes[0] says how many bytes of the first alternative are stored in
1208 the current frag. Likewise sizes[1] for the second alternative. */
1209 unsigned int sizes
[2];
1211 /* The symbol on which the choice of sequence depends. */
1215 /* Global variables used to decide whether a macro needs a warning. */
1217 /* True if the macro is in a branch delay slot. */
1218 bfd_boolean delay_slot_p
;
1220 /* Set to the length in bytes required if the macro is in a delay slot
1221 that requires a specific length of instruction, otherwise zero. */
1222 unsigned int delay_slot_length
;
1224 /* For relaxable macros, sizes[0] is the length of the first alternative
1225 in bytes and sizes[1] is the length of the second alternative.
1226 For non-relaxable macros, both elements give the length of the
1228 unsigned int sizes
[2];
1230 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1231 instruction of the first alternative in bytes and first_insn_sizes[1]
1232 is the length of the first instruction of the second alternative.
1233 For non-relaxable macros, both elements give the length of the first
1234 instruction in bytes.
1236 Set to zero if we haven't yet seen the first instruction. */
1237 unsigned int first_insn_sizes
[2];
1239 /* For relaxable macros, insns[0] is the number of instructions for the
1240 first alternative and insns[1] is the number of instructions for the
1243 For non-relaxable macros, both elements give the number of
1244 instructions for the macro. */
1245 unsigned int insns
[2];
1247 /* The first variant frag for this macro. */
1249 } mips_macro_warning
;
1251 /* Prototypes for static functions. */
1253 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1255 static void append_insn
1256 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1257 bfd_boolean expansionp
);
1258 static void mips_no_prev_insn (void);
1259 static void macro_build (expressionS
*, const char *, const char *, ...);
1260 static void mips16_macro_build
1261 (expressionS
*, const char *, const char *, va_list *);
1262 static void load_register (int, expressionS
*, int);
1263 static void macro_start (void);
1264 static void macro_end (void);
1265 static void macro (struct mips_cl_insn
*ip
, char *str
);
1266 static void mips16_macro (struct mips_cl_insn
* ip
);
1267 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1268 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1269 static void mips16_immed
1270 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1271 unsigned int, unsigned long *);
1272 static size_t my_getSmallExpression
1273 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1274 static void my_getExpression (expressionS
*, char *);
1275 static void s_align (int);
1276 static void s_change_sec (int);
1277 static void s_change_section (int);
1278 static void s_cons (int);
1279 static void s_float_cons (int);
1280 static void s_mips_globl (int);
1281 static void s_option (int);
1282 static void s_mipsset (int);
1283 static void s_abicalls (int);
1284 static void s_cpload (int);
1285 static void s_cpsetup (int);
1286 static void s_cplocal (int);
1287 static void s_cprestore (int);
1288 static void s_cpreturn (int);
1289 static void s_dtprelword (int);
1290 static void s_dtpreldword (int);
1291 static void s_tprelword (int);
1292 static void s_tpreldword (int);
1293 static void s_gpvalue (int);
1294 static void s_gpword (int);
1295 static void s_gpdword (int);
1296 static void s_ehword (int);
1297 static void s_cpadd (int);
1298 static void s_insn (int);
1299 static void s_nan (int);
1300 static void md_obj_begin (void);
1301 static void md_obj_end (void);
1302 static void s_mips_ent (int);
1303 static void s_mips_end (int);
1304 static void s_mips_frame (int);
1305 static void s_mips_mask (int reg_type
);
1306 static void s_mips_stab (int);
1307 static void s_mips_weakext (int);
1308 static void s_mips_file (int);
1309 static void s_mips_loc (int);
1310 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1311 static int relaxed_branch_length (fragS
*, asection
*, int);
1312 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1313 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1315 /* Table and functions used to map between CPU/ISA names, and
1316 ISA levels, and CPU numbers. */
1318 struct mips_cpu_info
1320 const char *name
; /* CPU or ISA name. */
1321 int flags
; /* MIPS_CPU_* flags. */
1322 int ase
; /* Set of ASEs implemented by the CPU. */
1323 int isa
; /* ISA level. */
1324 int cpu
; /* CPU number (default CPU if ISA). */
1327 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1329 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1330 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1331 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1333 /* Command-line options. */
1334 const char *md_shortopts
= "O::g::G:";
1338 OPTION_MARCH
= OPTION_MD_BASE
,
1368 OPTION_NO_SMARTMIPS
,
1376 OPTION_NO_MICROMIPS
,
1379 OPTION_COMPAT_ARCH_BASE
,
1388 OPTION_M7000_HILO_FIX
,
1389 OPTION_MNO_7000_HILO_FIX
,
1393 OPTION_NO_FIX_RM7000
,
1394 OPTION_FIX_LOONGSON2F_JUMP
,
1395 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1396 OPTION_FIX_LOONGSON2F_NOP
,
1397 OPTION_NO_FIX_LOONGSON2F_NOP
,
1399 OPTION_NO_FIX_VR4120
,
1401 OPTION_NO_FIX_VR4130
,
1402 OPTION_FIX_CN63XXP1
,
1403 OPTION_NO_FIX_CN63XXP1
,
1410 OPTION_CONSTRUCT_FLOATS
,
1411 OPTION_NO_CONSTRUCT_FLOATS
,
1414 OPTION_RELAX_BRANCH
,
1415 OPTION_NO_RELAX_BRANCH
,
1424 OPTION_SINGLE_FLOAT
,
1425 OPTION_DOUBLE_FLOAT
,
1438 OPTION_MVXWORKS_PIC
,
1443 struct option md_longopts
[] =
1445 /* Options which specify architecture. */
1446 {"march", required_argument
, NULL
, OPTION_MARCH
},
1447 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1448 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1449 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1450 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1451 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1452 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1453 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1454 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1455 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1456 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1457 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1458 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1459 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1460 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1461 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1463 /* Options which specify Application Specific Extensions (ASEs). */
1464 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1465 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1466 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1467 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1468 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1469 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1470 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1471 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1472 {"mmt", no_argument
, NULL
, OPTION_MT
},
1473 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1474 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1475 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1476 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1477 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1478 {"meva", no_argument
, NULL
, OPTION_EVA
},
1479 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1480 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1481 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1482 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1483 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1484 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1485 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1486 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1487 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1488 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1489 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1491 /* Old-style architecture options. Don't add more of these. */
1492 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1493 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1494 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1495 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1496 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1497 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1498 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1499 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1501 /* Options which enable bug fixes. */
1502 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1503 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1504 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1505 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1506 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1507 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1508 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1509 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1510 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1511 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1512 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1513 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1514 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1515 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1516 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1517 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1518 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1520 /* Miscellaneous options. */
1521 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1522 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1523 {"break", no_argument
, NULL
, OPTION_BREAK
},
1524 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1525 {"EB", no_argument
, NULL
, OPTION_EB
},
1526 {"EL", no_argument
, NULL
, OPTION_EL
},
1527 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1528 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1529 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1530 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1531 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1532 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1533 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1534 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1535 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1536 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1537 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1538 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1539 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1540 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1541 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1542 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1543 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1544 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1546 /* Strictly speaking this next option is ELF specific,
1547 but we allow it for other ports as well in order to
1548 make testing easier. */
1549 {"32", no_argument
, NULL
, OPTION_32
},
1551 /* ELF-specific options. */
1552 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1553 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1554 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1555 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1556 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1557 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1558 {"n32", no_argument
, NULL
, OPTION_N32
},
1559 {"64", no_argument
, NULL
, OPTION_64
},
1560 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1561 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1562 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1563 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1564 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1565 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1567 {NULL
, no_argument
, NULL
, 0}
1569 size_t md_longopts_size
= sizeof (md_longopts
);
1571 /* Information about either an Application Specific Extension or an
1572 optional architecture feature that, for simplicity, we treat in the
1573 same way as an ASE. */
1576 /* The name of the ASE, used in both the command-line and .set options. */
1579 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1580 and 64-bit architectures, the flags here refer to the subset that
1581 is available on both. */
1584 /* The ASE_* flag used for instructions that are available on 64-bit
1585 architectures but that are not included in FLAGS. */
1586 unsigned int flags64
;
1588 /* The command-line options that turn the ASE on and off. */
1592 /* The minimum required architecture revisions for MIPS32, MIPS64,
1593 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1596 int micromips32_rev
;
1597 int micromips64_rev
;
1600 /* A table of all supported ASEs. */
1601 static const struct mips_ase mips_ases
[] = {
1602 { "dsp", ASE_DSP
, ASE_DSP64
,
1603 OPTION_DSP
, OPTION_NO_DSP
,
1606 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1607 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1610 { "eva", ASE_EVA
, 0,
1611 OPTION_EVA
, OPTION_NO_EVA
,
1614 { "mcu", ASE_MCU
, 0,
1615 OPTION_MCU
, OPTION_NO_MCU
,
1618 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1619 { "mdmx", ASE_MDMX
, 0,
1620 OPTION_MDMX
, OPTION_NO_MDMX
,
1623 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1624 { "mips3d", ASE_MIPS3D
, 0,
1625 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1629 OPTION_MT
, OPTION_NO_MT
,
1632 { "smartmips", ASE_SMARTMIPS
, 0,
1633 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1636 { "virt", ASE_VIRT
, ASE_VIRT64
,
1637 OPTION_VIRT
, OPTION_NO_VIRT
,
1640 { "msa", ASE_MSA
, ASE_MSA64
,
1641 OPTION_MSA
, OPTION_NO_MSA
,
1644 { "xpa", ASE_XPA
, 0,
1645 OPTION_XPA
, OPTION_NO_XPA
,
1649 /* The set of ASEs that require -mfp64. */
1650 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1652 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1653 static const unsigned int mips_ase_groups
[] = {
1659 The following pseudo-ops from the Kane and Heinrich MIPS book
1660 should be defined here, but are currently unsupported: .alias,
1661 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1663 The following pseudo-ops from the Kane and Heinrich MIPS book are
1664 specific to the type of debugging information being generated, and
1665 should be defined by the object format: .aent, .begin, .bend,
1666 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1669 The following pseudo-ops from the Kane and Heinrich MIPS book are
1670 not MIPS CPU specific, but are also not specific to the object file
1671 format. This file is probably the best place to define them, but
1672 they are not currently supported: .asm0, .endr, .lab, .struct. */
1674 static const pseudo_typeS mips_pseudo_table
[] =
1676 /* MIPS specific pseudo-ops. */
1677 {"option", s_option
, 0},
1678 {"set", s_mipsset
, 0},
1679 {"rdata", s_change_sec
, 'r'},
1680 {"sdata", s_change_sec
, 's'},
1681 {"livereg", s_ignore
, 0},
1682 {"abicalls", s_abicalls
, 0},
1683 {"cpload", s_cpload
, 0},
1684 {"cpsetup", s_cpsetup
, 0},
1685 {"cplocal", s_cplocal
, 0},
1686 {"cprestore", s_cprestore
, 0},
1687 {"cpreturn", s_cpreturn
, 0},
1688 {"dtprelword", s_dtprelword
, 0},
1689 {"dtpreldword", s_dtpreldword
, 0},
1690 {"tprelword", s_tprelword
, 0},
1691 {"tpreldword", s_tpreldword
, 0},
1692 {"gpvalue", s_gpvalue
, 0},
1693 {"gpword", s_gpword
, 0},
1694 {"gpdword", s_gpdword
, 0},
1695 {"ehword", s_ehword
, 0},
1696 {"cpadd", s_cpadd
, 0},
1697 {"insn", s_insn
, 0},
1700 /* Relatively generic pseudo-ops that happen to be used on MIPS
1702 {"asciiz", stringer
, 8 + 1},
1703 {"bss", s_change_sec
, 'b'},
1705 {"half", s_cons
, 1},
1706 {"dword", s_cons
, 3},
1707 {"weakext", s_mips_weakext
, 0},
1708 {"origin", s_org
, 0},
1709 {"repeat", s_rept
, 0},
1711 /* For MIPS this is non-standard, but we define it for consistency. */
1712 {"sbss", s_change_sec
, 'B'},
1714 /* These pseudo-ops are defined in read.c, but must be overridden
1715 here for one reason or another. */
1716 {"align", s_align
, 0},
1717 {"byte", s_cons
, 0},
1718 {"data", s_change_sec
, 'd'},
1719 {"double", s_float_cons
, 'd'},
1720 {"float", s_float_cons
, 'f'},
1721 {"globl", s_mips_globl
, 0},
1722 {"global", s_mips_globl
, 0},
1723 {"hword", s_cons
, 1},
1725 {"long", s_cons
, 2},
1726 {"octa", s_cons
, 4},
1727 {"quad", s_cons
, 3},
1728 {"section", s_change_section
, 0},
1729 {"short", s_cons
, 1},
1730 {"single", s_float_cons
, 'f'},
1731 {"stabd", s_mips_stab
, 'd'},
1732 {"stabn", s_mips_stab
, 'n'},
1733 {"stabs", s_mips_stab
, 's'},
1734 {"text", s_change_sec
, 't'},
1735 {"word", s_cons
, 2},
1737 { "extern", ecoff_directive_extern
, 0},
1742 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1744 /* These pseudo-ops should be defined by the object file format.
1745 However, a.out doesn't support them, so we have versions here. */
1746 {"aent", s_mips_ent
, 1},
1747 {"bgnb", s_ignore
, 0},
1748 {"end", s_mips_end
, 0},
1749 {"endb", s_ignore
, 0},
1750 {"ent", s_mips_ent
, 0},
1751 {"file", s_mips_file
, 0},
1752 {"fmask", s_mips_mask
, 'F'},
1753 {"frame", s_mips_frame
, 0},
1754 {"loc", s_mips_loc
, 0},
1755 {"mask", s_mips_mask
, 'R'},
1756 {"verstamp", s_ignore
, 0},
1760 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1761 purpose of the `.dc.a' internal pseudo-op. */
1764 mips_address_bytes (void)
1766 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1769 extern void pop_insert (const pseudo_typeS
*);
1772 mips_pop_insert (void)
1774 pop_insert (mips_pseudo_table
);
1775 if (! ECOFF_DEBUGGING
)
1776 pop_insert (mips_nonecoff_pseudo_table
);
1779 /* Symbols labelling the current insn. */
1781 struct insn_label_list
1783 struct insn_label_list
*next
;
1787 static struct insn_label_list
*free_insn_labels
;
1788 #define label_list tc_segment_info_data.labels
1790 static void mips_clear_insn_labels (void);
1791 static void mips_mark_labels (void);
1792 static void mips_compressed_mark_labels (void);
1795 mips_clear_insn_labels (void)
1797 register struct insn_label_list
**pl
;
1798 segment_info_type
*si
;
1802 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1805 si
= seg_info (now_seg
);
1806 *pl
= si
->label_list
;
1807 si
->label_list
= NULL
;
1811 /* Mark instruction labels in MIPS16/microMIPS mode. */
1814 mips_mark_labels (void)
1816 if (HAVE_CODE_COMPRESSION
)
1817 mips_compressed_mark_labels ();
1820 static char *expr_end
;
1822 /* An expression in a macro instruction. This is set by mips_ip and
1823 mips16_ip and when populated is always an O_constant. */
1825 static expressionS imm_expr
;
1827 /* The relocatable field in an instruction and the relocs associated
1828 with it. These variables are used for instructions like LUI and
1829 JAL as well as true offsets. They are also used for address
1830 operands in macros. */
1832 static expressionS offset_expr
;
1833 static bfd_reloc_code_real_type offset_reloc
[3]
1834 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1836 /* This is set to the resulting size of the instruction to be produced
1837 by mips16_ip if an explicit extension is used or by mips_ip if an
1838 explicit size is supplied. */
1840 static unsigned int forced_insn_length
;
1842 /* True if we are assembling an instruction. All dot symbols defined during
1843 this time should be treated as code labels. */
1845 static bfd_boolean mips_assembling_insn
;
1847 /* The pdr segment for per procedure frame/regmask info. Not used for
1850 static segT pdr_seg
;
1852 /* The default target format to use. */
1854 #if defined (TE_FreeBSD)
1855 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1856 #elif defined (TE_TMIPS)
1857 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1859 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1863 mips_target_format (void)
1865 switch (OUTPUT_FLAVOR
)
1867 case bfd_target_elf_flavour
:
1869 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1870 return (target_big_endian
1871 ? "elf32-bigmips-vxworks"
1872 : "elf32-littlemips-vxworks");
1874 return (target_big_endian
1875 ? (HAVE_64BIT_OBJECTS
1876 ? ELF_TARGET ("elf64-", "big")
1878 ? ELF_TARGET ("elf32-n", "big")
1879 : ELF_TARGET ("elf32-", "big")))
1880 : (HAVE_64BIT_OBJECTS
1881 ? ELF_TARGET ("elf64-", "little")
1883 ? ELF_TARGET ("elf32-n", "little")
1884 : ELF_TARGET ("elf32-", "little"))));
1891 /* Return the ISA revision that is currently in use, or 0 if we are
1892 generating code for MIPS V or below. */
1897 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1900 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1903 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1906 /* microMIPS implies revision 2 or above. */
1907 if (mips_opts
.micromips
)
1910 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1916 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1919 mips_ase_mask (unsigned int flags
)
1923 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1924 if (flags
& mips_ase_groups
[i
])
1925 flags
|= mips_ase_groups
[i
];
1929 /* Check whether the current ISA supports ASE. Issue a warning if
1933 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1937 static unsigned int warned_isa
;
1938 static unsigned int warned_fp32
;
1940 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1941 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1943 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1944 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1945 && (warned_isa
& ase
->flags
) != ase
->flags
)
1947 warned_isa
|= ase
->flags
;
1948 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1949 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1951 as_warn (_("the %d-bit %s architecture does not support the"
1952 " `%s' extension"), size
, base
, ase
->name
);
1954 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
1955 ase
->name
, base
, size
, min_rev
);
1957 if ((ase
->flags
& FP64_ASES
)
1959 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1961 warned_fp32
|= ase
->flags
;
1962 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
1966 /* Check all enabled ASEs to see whether they are supported by the
1967 chosen architecture. */
1970 mips_check_isa_supports_ases (void)
1972 unsigned int i
, mask
;
1974 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1976 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1977 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1978 mips_check_isa_supports_ase (&mips_ases
[i
]);
1982 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1983 that were affected. */
1986 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1990 mask
= mips_ase_mask (ase
->flags
);
1991 mips_opts
.ase
&= ~mask
;
1993 mips_opts
.ase
|= ase
->flags
;
1997 /* Return the ASE called NAME, or null if none. */
1999 static const struct mips_ase
*
2000 mips_lookup_ase (const char *name
)
2004 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2005 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2006 return &mips_ases
[i
];
2010 /* Return the length of a microMIPS instruction in bytes. If bits of
2011 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2012 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2013 major opcode) will require further modifications to the opcode
2016 static inline unsigned int
2017 micromips_insn_length (const struct mips_opcode
*mo
)
2019 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2022 /* Return the length of MIPS16 instruction OPCODE. */
2024 static inline unsigned int
2025 mips16_opcode_length (unsigned long opcode
)
2027 return (opcode
>> 16) == 0 ? 2 : 4;
2030 /* Return the length of instruction INSN. */
2032 static inline unsigned int
2033 insn_length (const struct mips_cl_insn
*insn
)
2035 if (mips_opts
.micromips
)
2036 return micromips_insn_length (insn
->insn_mo
);
2037 else if (mips_opts
.mips16
)
2038 return mips16_opcode_length (insn
->insn_opcode
);
2043 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2046 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2051 insn
->insn_opcode
= mo
->match
;
2054 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2055 insn
->fixp
[i
] = NULL
;
2056 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2057 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2058 insn
->mips16_absolute_jump_p
= 0;
2059 insn
->complete_p
= 0;
2060 insn
->cleared_p
= 0;
2063 /* Get a list of all the operands in INSN. */
2065 static const struct mips_operand_array
*
2066 insn_operands (const struct mips_cl_insn
*insn
)
2068 if (insn
->insn_mo
>= &mips_opcodes
[0]
2069 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2070 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2072 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2073 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2074 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2076 if (insn
->insn_mo
>= µmips_opcodes
[0]
2077 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2078 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2083 /* Get a description of operand OPNO of INSN. */
2085 static const struct mips_operand
*
2086 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2088 const struct mips_operand_array
*operands
;
2090 operands
= insn_operands (insn
);
2091 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2093 return operands
->operand
[opno
];
2096 /* Install UVAL as the value of OPERAND in INSN. */
2099 insn_insert_operand (struct mips_cl_insn
*insn
,
2100 const struct mips_operand
*operand
, unsigned int uval
)
2102 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2105 /* Extract the value of OPERAND from INSN. */
2107 static inline unsigned
2108 insn_extract_operand (const struct mips_cl_insn
*insn
,
2109 const struct mips_operand
*operand
)
2111 return mips_extract_operand (operand
, insn
->insn_opcode
);
2114 /* Record the current MIPS16/microMIPS mode in now_seg. */
2117 mips_record_compressed_mode (void)
2119 segment_info_type
*si
;
2121 si
= seg_info (now_seg
);
2122 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2123 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2124 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2125 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2128 /* Read a standard MIPS instruction from BUF. */
2130 static unsigned long
2131 read_insn (char *buf
)
2133 if (target_big_endian
)
2134 return bfd_getb32 ((bfd_byte
*) buf
);
2136 return bfd_getl32 ((bfd_byte
*) buf
);
2139 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2143 write_insn (char *buf
, unsigned int insn
)
2145 md_number_to_chars (buf
, insn
, 4);
2149 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2150 has length LENGTH. */
2152 static unsigned long
2153 read_compressed_insn (char *buf
, unsigned int length
)
2159 for (i
= 0; i
< length
; i
+= 2)
2162 if (target_big_endian
)
2163 insn
|= bfd_getb16 ((char *) buf
);
2165 insn
|= bfd_getl16 ((char *) buf
);
2171 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2172 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2175 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2179 for (i
= 0; i
< length
; i
+= 2)
2180 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2181 return buf
+ length
;
2184 /* Install INSN at the location specified by its "frag" and "where" fields. */
2187 install_insn (const struct mips_cl_insn
*insn
)
2189 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2190 if (HAVE_CODE_COMPRESSION
)
2191 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2193 write_insn (f
, insn
->insn_opcode
);
2194 mips_record_compressed_mode ();
2197 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2198 and install the opcode in the new location. */
2201 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2206 insn
->where
= where
;
2207 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2208 if (insn
->fixp
[i
] != NULL
)
2210 insn
->fixp
[i
]->fx_frag
= frag
;
2211 insn
->fixp
[i
]->fx_where
= where
;
2213 install_insn (insn
);
2216 /* Add INSN to the end of the output. */
2219 add_fixed_insn (struct mips_cl_insn
*insn
)
2221 char *f
= frag_more (insn_length (insn
));
2222 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2225 /* Start a variant frag and move INSN to the start of the variant part,
2226 marking it as fixed. The other arguments are as for frag_var. */
2229 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2230 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2232 frag_grow (max_chars
);
2233 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2235 frag_var (rs_machine_dependent
, max_chars
, var
,
2236 subtype
, symbol
, offset
, NULL
);
2239 /* Insert N copies of INSN into the history buffer, starting at
2240 position FIRST. Neither FIRST nor N need to be clipped. */
2243 insert_into_history (unsigned int first
, unsigned int n
,
2244 const struct mips_cl_insn
*insn
)
2246 if (mips_relax
.sequence
!= 2)
2250 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2252 history
[i
] = history
[i
- n
];
2258 /* Clear the error in insn_error. */
2261 clear_insn_error (void)
2263 memset (&insn_error
, 0, sizeof (insn_error
));
2266 /* Possibly record error message MSG for the current instruction.
2267 If the error is about a particular argument, ARGNUM is the 1-based
2268 number of that argument, otherwise it is 0. FORMAT is the format
2269 of MSG. Return true if MSG was used, false if the current message
2273 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2278 /* Give priority to errors against specific arguments, and to
2279 the first whole-instruction message. */
2285 /* Keep insn_error if it is against a later argument. */
2286 if (argnum
< insn_error
.min_argnum
)
2289 /* If both errors are against the same argument but are different,
2290 give up on reporting a specific error for this argument.
2291 See the comment about mips_insn_error for details. */
2292 if (argnum
== insn_error
.min_argnum
2294 && strcmp (insn_error
.msg
, msg
) != 0)
2297 insn_error
.min_argnum
+= 1;
2301 insn_error
.min_argnum
= argnum
;
2302 insn_error
.format
= format
;
2303 insn_error
.msg
= msg
;
2307 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2308 as for set_insn_error_format. */
2311 set_insn_error (int argnum
, const char *msg
)
2313 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2316 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2317 as for set_insn_error_format. */
2320 set_insn_error_i (int argnum
, const char *msg
, int i
)
2322 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2326 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2327 are as for set_insn_error_format. */
2330 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2332 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2334 insn_error
.u
.ss
[0] = s1
;
2335 insn_error
.u
.ss
[1] = s2
;
2339 /* Report the error in insn_error, which is against assembly code STR. */
2342 report_insn_error (const char *str
)
2346 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2347 switch (insn_error
.format
)
2354 as_bad (msg
, insn_error
.u
.i
, str
);
2358 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2363 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2364 the idea is to make it obvious at a glance that each errata is
2368 init_vr4120_conflicts (void)
2370 #define CONFLICT(FIRST, SECOND) \
2371 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2373 /* Errata 21 - [D]DIV[U] after [D]MACC */
2374 CONFLICT (MACC
, DIV
);
2375 CONFLICT (DMACC
, DIV
);
2377 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2378 CONFLICT (DMULT
, DMULT
);
2379 CONFLICT (DMULT
, DMACC
);
2380 CONFLICT (DMACC
, DMULT
);
2381 CONFLICT (DMACC
, DMACC
);
2383 /* Errata 24 - MT{LO,HI} after [D]MACC */
2384 CONFLICT (MACC
, MTHILO
);
2385 CONFLICT (DMACC
, MTHILO
);
2387 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2388 instruction is executed immediately after a MACC or DMACC
2389 instruction, the result of [either instruction] is incorrect." */
2390 CONFLICT (MACC
, MULT
);
2391 CONFLICT (MACC
, DMULT
);
2392 CONFLICT (DMACC
, MULT
);
2393 CONFLICT (DMACC
, DMULT
);
2395 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2396 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2397 DDIV or DDIVU instruction, the result of the MACC or
2398 DMACC instruction is incorrect.". */
2399 CONFLICT (DMULT
, MACC
);
2400 CONFLICT (DMULT
, DMACC
);
2401 CONFLICT (DIV
, MACC
);
2402 CONFLICT (DIV
, DMACC
);
2412 #define RNUM_MASK 0x00000ff
2413 #define RTYPE_MASK 0x0ffff00
2414 #define RTYPE_NUM 0x0000100
2415 #define RTYPE_FPU 0x0000200
2416 #define RTYPE_FCC 0x0000400
2417 #define RTYPE_VEC 0x0000800
2418 #define RTYPE_GP 0x0001000
2419 #define RTYPE_CP0 0x0002000
2420 #define RTYPE_PC 0x0004000
2421 #define RTYPE_ACC 0x0008000
2422 #define RTYPE_CCC 0x0010000
2423 #define RTYPE_VI 0x0020000
2424 #define RTYPE_VF 0x0040000
2425 #define RTYPE_R5900_I 0x0080000
2426 #define RTYPE_R5900_Q 0x0100000
2427 #define RTYPE_R5900_R 0x0200000
2428 #define RTYPE_R5900_ACC 0x0400000
2429 #define RTYPE_MSA 0x0800000
2430 #define RWARN 0x8000000
2432 #define GENERIC_REGISTER_NUMBERS \
2433 {"$0", RTYPE_NUM | 0}, \
2434 {"$1", RTYPE_NUM | 1}, \
2435 {"$2", RTYPE_NUM | 2}, \
2436 {"$3", RTYPE_NUM | 3}, \
2437 {"$4", RTYPE_NUM | 4}, \
2438 {"$5", RTYPE_NUM | 5}, \
2439 {"$6", RTYPE_NUM | 6}, \
2440 {"$7", RTYPE_NUM | 7}, \
2441 {"$8", RTYPE_NUM | 8}, \
2442 {"$9", RTYPE_NUM | 9}, \
2443 {"$10", RTYPE_NUM | 10}, \
2444 {"$11", RTYPE_NUM | 11}, \
2445 {"$12", RTYPE_NUM | 12}, \
2446 {"$13", RTYPE_NUM | 13}, \
2447 {"$14", RTYPE_NUM | 14}, \
2448 {"$15", RTYPE_NUM | 15}, \
2449 {"$16", RTYPE_NUM | 16}, \
2450 {"$17", RTYPE_NUM | 17}, \
2451 {"$18", RTYPE_NUM | 18}, \
2452 {"$19", RTYPE_NUM | 19}, \
2453 {"$20", RTYPE_NUM | 20}, \
2454 {"$21", RTYPE_NUM | 21}, \
2455 {"$22", RTYPE_NUM | 22}, \
2456 {"$23", RTYPE_NUM | 23}, \
2457 {"$24", RTYPE_NUM | 24}, \
2458 {"$25", RTYPE_NUM | 25}, \
2459 {"$26", RTYPE_NUM | 26}, \
2460 {"$27", RTYPE_NUM | 27}, \
2461 {"$28", RTYPE_NUM | 28}, \
2462 {"$29", RTYPE_NUM | 29}, \
2463 {"$30", RTYPE_NUM | 30}, \
2464 {"$31", RTYPE_NUM | 31}
2466 #define FPU_REGISTER_NAMES \
2467 {"$f0", RTYPE_FPU | 0}, \
2468 {"$f1", RTYPE_FPU | 1}, \
2469 {"$f2", RTYPE_FPU | 2}, \
2470 {"$f3", RTYPE_FPU | 3}, \
2471 {"$f4", RTYPE_FPU | 4}, \
2472 {"$f5", RTYPE_FPU | 5}, \
2473 {"$f6", RTYPE_FPU | 6}, \
2474 {"$f7", RTYPE_FPU | 7}, \
2475 {"$f8", RTYPE_FPU | 8}, \
2476 {"$f9", RTYPE_FPU | 9}, \
2477 {"$f10", RTYPE_FPU | 10}, \
2478 {"$f11", RTYPE_FPU | 11}, \
2479 {"$f12", RTYPE_FPU | 12}, \
2480 {"$f13", RTYPE_FPU | 13}, \
2481 {"$f14", RTYPE_FPU | 14}, \
2482 {"$f15", RTYPE_FPU | 15}, \
2483 {"$f16", RTYPE_FPU | 16}, \
2484 {"$f17", RTYPE_FPU | 17}, \
2485 {"$f18", RTYPE_FPU | 18}, \
2486 {"$f19", RTYPE_FPU | 19}, \
2487 {"$f20", RTYPE_FPU | 20}, \
2488 {"$f21", RTYPE_FPU | 21}, \
2489 {"$f22", RTYPE_FPU | 22}, \
2490 {"$f23", RTYPE_FPU | 23}, \
2491 {"$f24", RTYPE_FPU | 24}, \
2492 {"$f25", RTYPE_FPU | 25}, \
2493 {"$f26", RTYPE_FPU | 26}, \
2494 {"$f27", RTYPE_FPU | 27}, \
2495 {"$f28", RTYPE_FPU | 28}, \
2496 {"$f29", RTYPE_FPU | 29}, \
2497 {"$f30", RTYPE_FPU | 30}, \
2498 {"$f31", RTYPE_FPU | 31}
2500 #define FPU_CONDITION_CODE_NAMES \
2501 {"$fcc0", RTYPE_FCC | 0}, \
2502 {"$fcc1", RTYPE_FCC | 1}, \
2503 {"$fcc2", RTYPE_FCC | 2}, \
2504 {"$fcc3", RTYPE_FCC | 3}, \
2505 {"$fcc4", RTYPE_FCC | 4}, \
2506 {"$fcc5", RTYPE_FCC | 5}, \
2507 {"$fcc6", RTYPE_FCC | 6}, \
2508 {"$fcc7", RTYPE_FCC | 7}
2510 #define COPROC_CONDITION_CODE_NAMES \
2511 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2512 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2513 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2514 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2515 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2516 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2517 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2518 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2520 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2521 {"$a4", RTYPE_GP | 8}, \
2522 {"$a5", RTYPE_GP | 9}, \
2523 {"$a6", RTYPE_GP | 10}, \
2524 {"$a7", RTYPE_GP | 11}, \
2525 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2526 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2527 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2528 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2529 {"$t0", RTYPE_GP | 12}, \
2530 {"$t1", RTYPE_GP | 13}, \
2531 {"$t2", RTYPE_GP | 14}, \
2532 {"$t3", RTYPE_GP | 15}
2534 #define O32_SYMBOLIC_REGISTER_NAMES \
2535 {"$t0", RTYPE_GP | 8}, \
2536 {"$t1", RTYPE_GP | 9}, \
2537 {"$t2", RTYPE_GP | 10}, \
2538 {"$t3", RTYPE_GP | 11}, \
2539 {"$t4", RTYPE_GP | 12}, \
2540 {"$t5", RTYPE_GP | 13}, \
2541 {"$t6", RTYPE_GP | 14}, \
2542 {"$t7", RTYPE_GP | 15}, \
2543 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2544 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2545 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2546 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2548 /* Remaining symbolic register names */
2549 #define SYMBOLIC_REGISTER_NAMES \
2550 {"$zero", RTYPE_GP | 0}, \
2551 {"$at", RTYPE_GP | 1}, \
2552 {"$AT", RTYPE_GP | 1}, \
2553 {"$v0", RTYPE_GP | 2}, \
2554 {"$v1", RTYPE_GP | 3}, \
2555 {"$a0", RTYPE_GP | 4}, \
2556 {"$a1", RTYPE_GP | 5}, \
2557 {"$a2", RTYPE_GP | 6}, \
2558 {"$a3", RTYPE_GP | 7}, \
2559 {"$s0", RTYPE_GP | 16}, \
2560 {"$s1", RTYPE_GP | 17}, \
2561 {"$s2", RTYPE_GP | 18}, \
2562 {"$s3", RTYPE_GP | 19}, \
2563 {"$s4", RTYPE_GP | 20}, \
2564 {"$s5", RTYPE_GP | 21}, \
2565 {"$s6", RTYPE_GP | 22}, \
2566 {"$s7", RTYPE_GP | 23}, \
2567 {"$t8", RTYPE_GP | 24}, \
2568 {"$t9", RTYPE_GP | 25}, \
2569 {"$k0", RTYPE_GP | 26}, \
2570 {"$kt0", RTYPE_GP | 26}, \
2571 {"$k1", RTYPE_GP | 27}, \
2572 {"$kt1", RTYPE_GP | 27}, \
2573 {"$gp", RTYPE_GP | 28}, \
2574 {"$sp", RTYPE_GP | 29}, \
2575 {"$s8", RTYPE_GP | 30}, \
2576 {"$fp", RTYPE_GP | 30}, \
2577 {"$ra", RTYPE_GP | 31}
2579 #define MIPS16_SPECIAL_REGISTER_NAMES \
2580 {"$pc", RTYPE_PC | 0}
2582 #define MDMX_VECTOR_REGISTER_NAMES \
2583 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2584 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2585 {"$v2", RTYPE_VEC | 2}, \
2586 {"$v3", RTYPE_VEC | 3}, \
2587 {"$v4", RTYPE_VEC | 4}, \
2588 {"$v5", RTYPE_VEC | 5}, \
2589 {"$v6", RTYPE_VEC | 6}, \
2590 {"$v7", RTYPE_VEC | 7}, \
2591 {"$v8", RTYPE_VEC | 8}, \
2592 {"$v9", RTYPE_VEC | 9}, \
2593 {"$v10", RTYPE_VEC | 10}, \
2594 {"$v11", RTYPE_VEC | 11}, \
2595 {"$v12", RTYPE_VEC | 12}, \
2596 {"$v13", RTYPE_VEC | 13}, \
2597 {"$v14", RTYPE_VEC | 14}, \
2598 {"$v15", RTYPE_VEC | 15}, \
2599 {"$v16", RTYPE_VEC | 16}, \
2600 {"$v17", RTYPE_VEC | 17}, \
2601 {"$v18", RTYPE_VEC | 18}, \
2602 {"$v19", RTYPE_VEC | 19}, \
2603 {"$v20", RTYPE_VEC | 20}, \
2604 {"$v21", RTYPE_VEC | 21}, \
2605 {"$v22", RTYPE_VEC | 22}, \
2606 {"$v23", RTYPE_VEC | 23}, \
2607 {"$v24", RTYPE_VEC | 24}, \
2608 {"$v25", RTYPE_VEC | 25}, \
2609 {"$v26", RTYPE_VEC | 26}, \
2610 {"$v27", RTYPE_VEC | 27}, \
2611 {"$v28", RTYPE_VEC | 28}, \
2612 {"$v29", RTYPE_VEC | 29}, \
2613 {"$v30", RTYPE_VEC | 30}, \
2614 {"$v31", RTYPE_VEC | 31}
2616 #define R5900_I_NAMES \
2617 {"$I", RTYPE_R5900_I | 0}
2619 #define R5900_Q_NAMES \
2620 {"$Q", RTYPE_R5900_Q | 0}
2622 #define R5900_R_NAMES \
2623 {"$R", RTYPE_R5900_R | 0}
2625 #define R5900_ACC_NAMES \
2626 {"$ACC", RTYPE_R5900_ACC | 0 }
2628 #define MIPS_DSP_ACCUMULATOR_NAMES \
2629 {"$ac0", RTYPE_ACC | 0}, \
2630 {"$ac1", RTYPE_ACC | 1}, \
2631 {"$ac2", RTYPE_ACC | 2}, \
2632 {"$ac3", RTYPE_ACC | 3}
2634 static const struct regname reg_names
[] = {
2635 GENERIC_REGISTER_NUMBERS
,
2637 FPU_CONDITION_CODE_NAMES
,
2638 COPROC_CONDITION_CODE_NAMES
,
2640 /* The $txx registers depends on the abi,
2641 these will be added later into the symbol table from
2642 one of the tables below once mips_abi is set after
2643 parsing of arguments from the command line. */
2644 SYMBOLIC_REGISTER_NAMES
,
2646 MIPS16_SPECIAL_REGISTER_NAMES
,
2647 MDMX_VECTOR_REGISTER_NAMES
,
2652 MIPS_DSP_ACCUMULATOR_NAMES
,
2656 static const struct regname reg_names_o32
[] = {
2657 O32_SYMBOLIC_REGISTER_NAMES
,
2661 static const struct regname reg_names_n32n64
[] = {
2662 N32N64_SYMBOLIC_REGISTER_NAMES
,
2666 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2667 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2668 of these register symbols, return the associated vector register,
2669 otherwise return SYMVAL itself. */
2672 mips_prefer_vec_regno (unsigned int symval
)
2674 if ((symval
& -2) == (RTYPE_GP
| 2))
2675 return RTYPE_VEC
| (symval
& 1);
2679 /* Return true if string [S, E) is a valid register name, storing its
2680 symbol value in *SYMVAL_PTR if so. */
2683 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2688 /* Terminate name. */
2692 /* Look up the name. */
2693 symbol
= symbol_find (s
);
2696 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2699 *symval_ptr
= S_GET_VALUE (symbol
);
2703 /* Return true if the string at *SPTR is a valid register name. Allow it
2704 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2707 When returning true, move *SPTR past the register, store the
2708 register's symbol value in *SYMVAL_PTR and the channel mask in
2709 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2710 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2711 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2714 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2715 unsigned int *channels_ptr
)
2719 unsigned int channels
, symval
, bit
;
2721 /* Find end of name. */
2723 if (is_name_beginner (*e
))
2725 while (is_part_of_name (*e
))
2729 if (!mips_parse_register_1 (s
, e
, &symval
))
2734 /* Eat characters from the end of the string that are valid
2735 channel suffixes. The preceding register must be $ACC or
2736 end with a digit, so there is no ambiguity. */
2739 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2740 if (m
> s
&& m
[-1] == *q
)
2747 || !mips_parse_register_1 (s
, m
, &symval
)
2748 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2753 *symval_ptr
= symval
;
2755 *channels_ptr
= channels
;
2759 /* Check if SPTR points at a valid register specifier according to TYPES.
2760 If so, then return 1, advance S to consume the specifier and store
2761 the register's number in REGNOP, otherwise return 0. */
2764 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2768 if (mips_parse_register (s
, ®no
, NULL
))
2770 if (types
& RTYPE_VEC
)
2771 regno
= mips_prefer_vec_regno (regno
);
2780 as_warn (_("unrecognized register name `%s'"), *s
);
2785 return regno
<= RNUM_MASK
;
2788 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2789 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2792 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2797 for (i
= 0; i
< 4; i
++)
2798 if (*s
== "xyzw"[i
])
2800 *channels
|= 1 << (3 - i
);
2806 /* Token types for parsed operand lists. */
2807 enum mips_operand_token_type
{
2808 /* A plain register, e.g. $f2. */
2811 /* A 4-bit XYZW channel mask. */
2814 /* A constant vector index, e.g. [1]. */
2817 /* A register vector index, e.g. [$2]. */
2820 /* A continuous range of registers, e.g. $s0-$s4. */
2823 /* A (possibly relocated) expression. */
2826 /* A floating-point value. */
2829 /* A single character. This can be '(', ')' or ',', but '(' only appears
2833 /* A doubled character, either "--" or "++". */
2836 /* The end of the operand list. */
2840 /* A parsed operand token. */
2841 struct mips_operand_token
2843 /* The type of token. */
2844 enum mips_operand_token_type type
;
2847 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2850 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2851 unsigned int channels
;
2853 /* The integer value of an OT_INTEGER_INDEX. */
2856 /* The two register symbol values involved in an OT_REG_RANGE. */
2858 unsigned int regno1
;
2859 unsigned int regno2
;
2862 /* The value of an OT_INTEGER. The value is represented as an
2863 expression and the relocation operators that were applied to
2864 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2865 relocation operators were used. */
2868 bfd_reloc_code_real_type relocs
[3];
2871 /* The binary data for an OT_FLOAT constant, and the number of bytes
2874 unsigned char data
[8];
2878 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2883 /* An obstack used to construct lists of mips_operand_tokens. */
2884 static struct obstack mips_operand_tokens
;
2886 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2889 mips_add_token (struct mips_operand_token
*token
,
2890 enum mips_operand_token_type type
)
2893 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2896 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2897 and OT_REG tokens for them if so, and return a pointer to the first
2898 unconsumed character. Return null otherwise. */
2901 mips_parse_base_start (char *s
)
2903 struct mips_operand_token token
;
2904 unsigned int regno
, channels
;
2905 bfd_boolean decrement_p
;
2911 SKIP_SPACE_TABS (s
);
2913 /* Only match "--" as part of a base expression. In other contexts "--X"
2914 is a double negative. */
2915 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2919 SKIP_SPACE_TABS (s
);
2922 /* Allow a channel specifier because that leads to better error messages
2923 than treating something like "$vf0x++" as an expression. */
2924 if (!mips_parse_register (&s
, ®no
, &channels
))
2928 mips_add_token (&token
, OT_CHAR
);
2933 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2936 token
.u
.regno
= regno
;
2937 mips_add_token (&token
, OT_REG
);
2941 token
.u
.channels
= channels
;
2942 mips_add_token (&token
, OT_CHANNELS
);
2945 /* For consistency, only match "++" as part of base expressions too. */
2946 SKIP_SPACE_TABS (s
);
2947 if (s
[0] == '+' && s
[1] == '+')
2951 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2957 /* Parse one or more tokens from S. Return a pointer to the first
2958 unconsumed character on success. Return null if an error was found
2959 and store the error text in insn_error. FLOAT_FORMAT is as for
2960 mips_parse_arguments. */
2963 mips_parse_argument_token (char *s
, char float_format
)
2965 char *end
, *save_in
, *err
;
2966 unsigned int regno1
, regno2
, channels
;
2967 struct mips_operand_token token
;
2969 /* First look for "($reg", since we want to treat that as an
2970 OT_CHAR and OT_REG rather than an expression. */
2971 end
= mips_parse_base_start (s
);
2975 /* Handle other characters that end up as OT_CHARs. */
2976 if (*s
== ')' || *s
== ',')
2979 mips_add_token (&token
, OT_CHAR
);
2984 /* Handle tokens that start with a register. */
2985 if (mips_parse_register (&s
, ®no1
, &channels
))
2989 /* A register and a VU0 channel suffix. */
2990 token
.u
.regno
= regno1
;
2991 mips_add_token (&token
, OT_REG
);
2993 token
.u
.channels
= channels
;
2994 mips_add_token (&token
, OT_CHANNELS
);
2998 SKIP_SPACE_TABS (s
);
3001 /* A register range. */
3003 SKIP_SPACE_TABS (s
);
3004 if (!mips_parse_register (&s
, ®no2
, NULL
))
3006 set_insn_error (0, _("invalid register range"));
3010 token
.u
.reg_range
.regno1
= regno1
;
3011 token
.u
.reg_range
.regno2
= regno2
;
3012 mips_add_token (&token
, OT_REG_RANGE
);
3016 /* Add the register itself. */
3017 token
.u
.regno
= regno1
;
3018 mips_add_token (&token
, OT_REG
);
3020 /* Check for a vector index. */
3024 SKIP_SPACE_TABS (s
);
3025 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3026 mips_add_token (&token
, OT_REG_INDEX
);
3029 expressionS element
;
3031 my_getExpression (&element
, s
);
3032 if (element
.X_op
!= O_constant
)
3034 set_insn_error (0, _("vector element must be constant"));
3038 token
.u
.index
= element
.X_add_number
;
3039 mips_add_token (&token
, OT_INTEGER_INDEX
);
3041 SKIP_SPACE_TABS (s
);
3044 set_insn_error (0, _("missing `]'"));
3054 /* First try to treat expressions as floats. */
3055 save_in
= input_line_pointer
;
3056 input_line_pointer
= s
;
3057 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3058 &token
.u
.flt
.length
);
3059 end
= input_line_pointer
;
3060 input_line_pointer
= save_in
;
3063 set_insn_error (0, err
);
3068 mips_add_token (&token
, OT_FLOAT
);
3073 /* Treat everything else as an integer expression. */
3074 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3075 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3076 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3077 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3079 mips_add_token (&token
, OT_INTEGER
);
3083 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3084 if expressions should be treated as 32-bit floating-point constants,
3085 'd' if they should be treated as 64-bit floating-point constants,
3086 or 0 if they should be treated as integer expressions (the usual case).
3088 Return a list of tokens on success, otherwise return 0. The caller
3089 must obstack_free the list after use. */
3091 static struct mips_operand_token
*
3092 mips_parse_arguments (char *s
, char float_format
)
3094 struct mips_operand_token token
;
3096 SKIP_SPACE_TABS (s
);
3099 s
= mips_parse_argument_token (s
, float_format
);
3102 obstack_free (&mips_operand_tokens
,
3103 obstack_finish (&mips_operand_tokens
));
3106 SKIP_SPACE_TABS (s
);
3108 mips_add_token (&token
, OT_END
);
3109 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3112 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3113 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3116 is_opcode_valid (const struct mips_opcode
*mo
)
3118 int isa
= mips_opts
.isa
;
3119 int ase
= mips_opts
.ase
;
3123 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3124 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3125 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3126 ase
|= mips_ases
[i
].flags64
;
3128 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3131 /* Check whether the instruction or macro requires single-precision or
3132 double-precision floating-point support. Note that this information is
3133 stored differently in the opcode table for insns and macros. */
3134 if (mo
->pinfo
== INSN_MACRO
)
3136 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3137 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3141 fp_s
= mo
->pinfo
& FP_S
;
3142 fp_d
= mo
->pinfo
& FP_D
;
3145 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3148 if (fp_s
&& mips_opts
.soft_float
)
3154 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3155 selected ISA and architecture. */
3158 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3160 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3163 /* Return TRUE if the size of the microMIPS opcode MO matches one
3164 explicitly requested. Always TRUE in the standard MIPS mode. */
3167 is_size_valid (const struct mips_opcode
*mo
)
3169 if (!mips_opts
.micromips
)
3172 if (mips_opts
.insn32
)
3174 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3176 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3179 if (!forced_insn_length
)
3181 if (mo
->pinfo
== INSN_MACRO
)
3183 return forced_insn_length
== micromips_insn_length (mo
);
3186 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3187 of the preceding instruction. Always TRUE in the standard MIPS mode.
3189 We don't accept macros in 16-bit delay slots to avoid a case where
3190 a macro expansion fails because it relies on a preceding 32-bit real
3191 instruction to have matched and does not handle the operands correctly.
3192 The only macros that may expand to 16-bit instructions are JAL that
3193 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3194 and BGT (that likewise cannot be placed in a delay slot) that decay to
3195 a NOP. In all these cases the macros precede any corresponding real
3196 instruction definitions in the opcode table, so they will match in the
3197 second pass where the size of the delay slot is ignored and therefore
3198 produce correct code. */
3201 is_delay_slot_valid (const struct mips_opcode
*mo
)
3203 if (!mips_opts
.micromips
)
3206 if (mo
->pinfo
== INSN_MACRO
)
3207 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3208 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3209 && micromips_insn_length (mo
) != 4)
3211 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3212 && micromips_insn_length (mo
) != 2)
3218 /* For consistency checking, verify that all bits of OPCODE are specified
3219 either by the match/mask part of the instruction definition, or by the
3220 operand list. Also build up a list of operands in OPERANDS.
3222 INSN_BITS says which bits of the instruction are significant.
3223 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3224 provides the mips_operand description of each operand. DECODE_OPERAND
3225 is null for MIPS16 instructions. */
3228 validate_mips_insn (const struct mips_opcode
*opcode
,
3229 unsigned long insn_bits
,
3230 const struct mips_operand
*(*decode_operand
) (const char *),
3231 struct mips_operand_array
*operands
)
3234 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3235 const struct mips_operand
*operand
;
3237 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3238 if ((mask
& opcode
->match
) != opcode
->match
)
3240 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3241 opcode
->name
, opcode
->args
);
3246 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3247 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3248 for (s
= opcode
->args
; *s
; ++s
)
3261 if (!decode_operand
)
3262 operand
= decode_mips16_operand (*s
, FALSE
);
3264 operand
= decode_operand (s
);
3265 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3267 as_bad (_("internal: unknown operand type: %s %s"),
3268 opcode
->name
, opcode
->args
);
3271 gas_assert (opno
< MAX_OPERANDS
);
3272 operands
->operand
[opno
] = operand
;
3273 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3275 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3276 if (operand
->type
== OP_MDMX_IMM_REG
)
3277 /* Bit 5 is the format selector (OB vs QH). The opcode table
3278 has separate entries for each format. */
3279 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3280 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3281 used_bits
&= ~(mask
& 0x700);
3283 /* Skip prefix characters. */
3284 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3289 doubled
= used_bits
& mask
& insn_bits
;
3292 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3293 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3297 undefined
= ~used_bits
& insn_bits
;
3298 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3300 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3301 undefined
, opcode
->name
, opcode
->args
);
3304 used_bits
&= ~insn_bits
;
3307 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3308 used_bits
, opcode
->name
, opcode
->args
);
3314 /* The MIPS16 version of validate_mips_insn. */
3317 validate_mips16_insn (const struct mips_opcode
*opcode
,
3318 struct mips_operand_array
*operands
)
3320 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3322 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3323 instruction. Use TMP to describe the full instruction. */
3324 struct mips_opcode tmp
;
3329 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3331 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3334 /* The microMIPS version of validate_mips_insn. */
3337 validate_micromips_insn (const struct mips_opcode
*opc
,
3338 struct mips_operand_array
*operands
)
3340 unsigned long insn_bits
;
3341 unsigned long major
;
3342 unsigned int length
;
3344 if (opc
->pinfo
== INSN_MACRO
)
3345 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3348 length
= micromips_insn_length (opc
);
3349 if (length
!= 2 && length
!= 4)
3351 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3352 "%s %s"), length
, opc
->name
, opc
->args
);
3355 major
= opc
->match
>> (10 + 8 * (length
- 2));
3356 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3357 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3359 as_bad (_("internal error: bad microMIPS opcode "
3360 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3364 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3365 insn_bits
= 1 << 4 * length
;
3366 insn_bits
<<= 4 * length
;
3368 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3372 /* This function is called once, at assembler startup time. It should set up
3373 all the tables, etc. that the MD part of the assembler will need. */
3378 const char *retval
= NULL
;
3382 if (mips_pic
!= NO_PIC
)
3384 if (g_switch_seen
&& g_switch_value
!= 0)
3385 as_bad (_("-G may not be used in position-independent code"));
3389 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3390 as_warn (_("could not set architecture and machine"));
3392 op_hash
= hash_new ();
3394 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3395 for (i
= 0; i
< NUMOPCODES
;)
3397 const char *name
= mips_opcodes
[i
].name
;
3399 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3402 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3403 mips_opcodes
[i
].name
, retval
);
3404 /* Probably a memory allocation problem? Give up now. */
3405 as_fatal (_("broken assembler, no assembly attempted"));
3409 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3410 decode_mips_operand
, &mips_operands
[i
]))
3412 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3414 create_insn (&nop_insn
, mips_opcodes
+ i
);
3415 if (mips_fix_loongson2f_nop
)
3416 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3417 nop_insn
.fixed_p
= 1;
3421 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3424 mips16_op_hash
= hash_new ();
3425 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3426 bfd_mips16_num_opcodes
);
3429 while (i
< bfd_mips16_num_opcodes
)
3431 const char *name
= mips16_opcodes
[i
].name
;
3433 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3435 as_fatal (_("internal: can't hash `%s': %s"),
3436 mips16_opcodes
[i
].name
, retval
);
3439 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3441 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3443 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3444 mips16_nop_insn
.fixed_p
= 1;
3448 while (i
< bfd_mips16_num_opcodes
3449 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3452 micromips_op_hash
= hash_new ();
3453 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3454 bfd_micromips_num_opcodes
);
3457 while (i
< bfd_micromips_num_opcodes
)
3459 const char *name
= micromips_opcodes
[i
].name
;
3461 retval
= hash_insert (micromips_op_hash
, name
,
3462 (void *) µmips_opcodes
[i
]);
3464 as_fatal (_("internal: can't hash `%s': %s"),
3465 micromips_opcodes
[i
].name
, retval
);
3468 struct mips_cl_insn
*micromips_nop_insn
;
3470 if (!validate_micromips_insn (µmips_opcodes
[i
],
3471 µmips_operands
[i
]))
3474 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3476 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3477 micromips_nop_insn
= µmips_nop16_insn
;
3478 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3479 micromips_nop_insn
= µmips_nop32_insn
;
3483 if (micromips_nop_insn
->insn_mo
== NULL
3484 && strcmp (name
, "nop") == 0)
3486 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3487 micromips_nop_insn
->fixed_p
= 1;
3491 while (++i
< bfd_micromips_num_opcodes
3492 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3496 as_fatal (_("broken assembler, no assembly attempted"));
3498 /* We add all the general register names to the symbol table. This
3499 helps us detect invalid uses of them. */
3500 for (i
= 0; reg_names
[i
].name
; i
++)
3501 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3502 reg_names
[i
].num
, /* & RNUM_MASK, */
3503 &zero_address_frag
));
3505 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3506 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3507 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3508 &zero_address_frag
));
3510 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3511 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3512 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3513 &zero_address_frag
));
3515 for (i
= 0; i
< 32; i
++)
3519 /* R5900 VU0 floating-point register. */
3520 regname
[sizeof (rename
) - 1] = 0;
3521 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3522 symbol_table_insert (symbol_new (regname
, reg_section
,
3523 RTYPE_VF
| i
, &zero_address_frag
));
3525 /* R5900 VU0 integer register. */
3526 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3527 symbol_table_insert (symbol_new (regname
, reg_section
,
3528 RTYPE_VI
| i
, &zero_address_frag
));
3531 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3532 symbol_table_insert (symbol_new (regname
, reg_section
,
3533 RTYPE_MSA
| i
, &zero_address_frag
));
3536 obstack_init (&mips_operand_tokens
);
3538 mips_no_prev_insn ();
3541 mips_cprmask
[0] = 0;
3542 mips_cprmask
[1] = 0;
3543 mips_cprmask
[2] = 0;
3544 mips_cprmask
[3] = 0;
3546 /* set the default alignment for the text section (2**2) */
3547 record_alignment (text_section
, 2);
3549 bfd_set_gp_size (stdoutput
, g_switch_value
);
3551 /* On a native system other than VxWorks, sections must be aligned
3552 to 16 byte boundaries. When configured for an embedded ELF
3553 target, we don't bother. */
3554 if (strncmp (TARGET_OS
, "elf", 3) != 0
3555 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3557 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3558 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3559 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3562 /* Create a .reginfo section for register masks and a .mdebug
3563 section for debugging information. */
3571 subseg
= now_subseg
;
3573 /* The ABI says this section should be loaded so that the
3574 running program can access it. However, we don't load it
3575 if we are configured for an embedded target */
3576 flags
= SEC_READONLY
| SEC_DATA
;
3577 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3578 flags
|= SEC_ALLOC
| SEC_LOAD
;
3580 if (mips_abi
!= N64_ABI
)
3582 sec
= subseg_new (".reginfo", (subsegT
) 0);
3584 bfd_set_section_flags (stdoutput
, sec
, flags
);
3585 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3587 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3591 /* The 64-bit ABI uses a .MIPS.options section rather than
3592 .reginfo section. */
3593 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3594 bfd_set_section_flags (stdoutput
, sec
, flags
);
3595 bfd_set_section_alignment (stdoutput
, sec
, 3);
3597 /* Set up the option header. */
3599 Elf_Internal_Options opthdr
;
3602 opthdr
.kind
= ODK_REGINFO
;
3603 opthdr
.size
= (sizeof (Elf_External_Options
)
3604 + sizeof (Elf64_External_RegInfo
));
3607 f
= frag_more (sizeof (Elf_External_Options
));
3608 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3609 (Elf_External_Options
*) f
);
3611 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3615 if (ECOFF_DEBUGGING
)
3617 sec
= subseg_new (".mdebug", (subsegT
) 0);
3618 (void) bfd_set_section_flags (stdoutput
, sec
,
3619 SEC_HAS_CONTENTS
| SEC_READONLY
);
3620 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3622 else if (mips_flag_pdr
)
3624 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3625 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3626 SEC_READONLY
| SEC_RELOC
3628 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3631 subseg_set (seg
, subseg
);
3634 if (! ECOFF_DEBUGGING
)
3637 if (mips_fix_vr4120
)
3638 init_vr4120_conflicts ();
3644 mips_emit_delays ();
3645 if (! ECOFF_DEBUGGING
)
3650 md_assemble (char *str
)
3652 struct mips_cl_insn insn
;
3653 bfd_reloc_code_real_type unused_reloc
[3]
3654 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3656 imm_expr
.X_op
= O_absent
;
3657 offset_expr
.X_op
= O_absent
;
3658 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3659 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3660 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3662 mips_mark_labels ();
3663 mips_assembling_insn
= TRUE
;
3664 clear_insn_error ();
3666 if (mips_opts
.mips16
)
3667 mips16_ip (str
, &insn
);
3670 mips_ip (str
, &insn
);
3671 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3672 str
, insn
.insn_opcode
));
3676 report_insn_error (str
);
3677 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3680 if (mips_opts
.mips16
)
3681 mips16_macro (&insn
);
3688 if (offset_expr
.X_op
!= O_absent
)
3689 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3691 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3694 mips_assembling_insn
= FALSE
;
3697 /* Convenience functions for abstracting away the differences between
3698 MIPS16 and non-MIPS16 relocations. */
3700 static inline bfd_boolean
3701 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3705 case BFD_RELOC_MIPS16_JMP
:
3706 case BFD_RELOC_MIPS16_GPREL
:
3707 case BFD_RELOC_MIPS16_GOT16
:
3708 case BFD_RELOC_MIPS16_CALL16
:
3709 case BFD_RELOC_MIPS16_HI16_S
:
3710 case BFD_RELOC_MIPS16_HI16
:
3711 case BFD_RELOC_MIPS16_LO16
:
3719 static inline bfd_boolean
3720 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3724 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3725 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3726 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3727 case BFD_RELOC_MICROMIPS_GPREL16
:
3728 case BFD_RELOC_MICROMIPS_JMP
:
3729 case BFD_RELOC_MICROMIPS_HI16
:
3730 case BFD_RELOC_MICROMIPS_HI16_S
:
3731 case BFD_RELOC_MICROMIPS_LO16
:
3732 case BFD_RELOC_MICROMIPS_LITERAL
:
3733 case BFD_RELOC_MICROMIPS_GOT16
:
3734 case BFD_RELOC_MICROMIPS_CALL16
:
3735 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3736 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3737 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3738 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3739 case BFD_RELOC_MICROMIPS_SUB
:
3740 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3741 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3742 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3743 case BFD_RELOC_MICROMIPS_HIGHEST
:
3744 case BFD_RELOC_MICROMIPS_HIGHER
:
3745 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3746 case BFD_RELOC_MICROMIPS_JALR
:
3754 static inline bfd_boolean
3755 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3757 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3760 static inline bfd_boolean
3761 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3763 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3764 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3767 static inline bfd_boolean
3768 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3770 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3771 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3774 static inline bfd_boolean
3775 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3777 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3778 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3781 static inline bfd_boolean
3782 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3784 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3787 static inline bfd_boolean
3788 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3790 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3791 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3794 /* Return true if RELOC is a PC-relative relocation that does not have
3795 full address range. */
3797 static inline bfd_boolean
3798 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3802 case BFD_RELOC_16_PCREL_S2
:
3803 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3804 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3805 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3808 case BFD_RELOC_32_PCREL
:
3809 return HAVE_64BIT_ADDRESSES
;
3816 /* Return true if the given relocation might need a matching %lo().
3817 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3818 need a matching %lo() when applied to local symbols. */
3820 static inline bfd_boolean
3821 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3823 return (HAVE_IN_PLACE_ADDENDS
3824 && (hi16_reloc_p (reloc
)
3825 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3826 all GOT16 relocations evaluate to "G". */
3827 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3830 /* Return the type of %lo() reloc needed by RELOC, given that
3831 reloc_needs_lo_p. */
3833 static inline bfd_reloc_code_real_type
3834 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3836 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3837 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3841 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3844 static inline bfd_boolean
3845 fixup_has_matching_lo_p (fixS
*fixp
)
3847 return (fixp
->fx_next
!= NULL
3848 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3849 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3850 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3853 /* Move all labels in LABELS to the current insertion point. TEXT_P
3854 says whether the labels refer to text or data. */
3857 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3859 struct insn_label_list
*l
;
3862 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3864 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3865 symbol_set_frag (l
->label
, frag_now
);
3866 val
= (valueT
) frag_now_fix ();
3867 /* MIPS16/microMIPS text labels are stored as odd. */
3868 if (text_p
&& HAVE_CODE_COMPRESSION
)
3870 S_SET_VALUE (l
->label
, val
);
3874 /* Move all labels in insn_labels to the current insertion point
3875 and treat them as text labels. */
3878 mips_move_text_labels (void)
3880 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3884 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3886 bfd_boolean linkonce
= FALSE
;
3887 segT symseg
= S_GET_SEGMENT (sym
);
3889 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3891 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3893 /* The GNU toolchain uses an extension for ELF: a section
3894 beginning with the magic string .gnu.linkonce is a
3895 linkonce section. */
3896 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3897 sizeof ".gnu.linkonce" - 1) == 0)
3903 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3904 linker to handle them specially, such as generating jalx instructions
3905 when needed. We also make them odd for the duration of the assembly,
3906 in order to generate the right sort of code. We will make them even
3907 in the adjust_symtab routine, while leaving them marked. This is
3908 convenient for the debugger and the disassembler. The linker knows
3909 to make them odd again. */
3912 mips_compressed_mark_label (symbolS
*label
)
3914 gas_assert (HAVE_CODE_COMPRESSION
);
3916 if (mips_opts
.mips16
)
3917 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3919 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3920 if ((S_GET_VALUE (label
) & 1) == 0
3921 /* Don't adjust the address if the label is global or weak, or
3922 in a link-once section, since we'll be emitting symbol reloc
3923 references to it which will be patched up by the linker, and
3924 the final value of the symbol may or may not be MIPS16/microMIPS. */
3925 && !S_IS_WEAK (label
)
3926 && !S_IS_EXTERNAL (label
)
3927 && !s_is_linkonce (label
, now_seg
))
3928 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3931 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3934 mips_compressed_mark_labels (void)
3936 struct insn_label_list
*l
;
3938 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3939 mips_compressed_mark_label (l
->label
);
3942 /* End the current frag. Make it a variant frag and record the
3946 relax_close_frag (void)
3948 mips_macro_warning
.first_frag
= frag_now
;
3949 frag_var (rs_machine_dependent
, 0, 0,
3950 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3951 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3953 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3954 mips_relax
.first_fixup
= 0;
3957 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3958 See the comment above RELAX_ENCODE for more details. */
3961 relax_start (symbolS
*symbol
)
3963 gas_assert (mips_relax
.sequence
== 0);
3964 mips_relax
.sequence
= 1;
3965 mips_relax
.symbol
= symbol
;
3968 /* Start generating the second version of a relaxable sequence.
3969 See the comment above RELAX_ENCODE for more details. */
3974 gas_assert (mips_relax
.sequence
== 1);
3975 mips_relax
.sequence
= 2;
3978 /* End the current relaxable sequence. */
3983 gas_assert (mips_relax
.sequence
== 2);
3984 relax_close_frag ();
3985 mips_relax
.sequence
= 0;
3988 /* Return true if IP is a delayed branch or jump. */
3990 static inline bfd_boolean
3991 delayed_branch_p (const struct mips_cl_insn
*ip
)
3993 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3994 | INSN_COND_BRANCH_DELAY
3995 | INSN_COND_BRANCH_LIKELY
)) != 0;
3998 /* Return true if IP is a compact branch or jump. */
4000 static inline bfd_boolean
4001 compact_branch_p (const struct mips_cl_insn
*ip
)
4003 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4004 | INSN2_COND_BRANCH
)) != 0;
4007 /* Return true if IP is an unconditional branch or jump. */
4009 static inline bfd_boolean
4010 uncond_branch_p (const struct mips_cl_insn
*ip
)
4012 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4013 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4016 /* Return true if IP is a branch-likely instruction. */
4018 static inline bfd_boolean
4019 branch_likely_p (const struct mips_cl_insn
*ip
)
4021 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4024 /* Return the type of nop that should be used to fill the delay slot
4025 of delayed branch IP. */
4027 static struct mips_cl_insn
*
4028 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4030 if (mips_opts
.micromips
4031 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4032 return µmips_nop32_insn
;
4036 /* Return a mask that has bit N set if OPCODE reads the register(s)
4040 insn_read_mask (const struct mips_opcode
*opcode
)
4042 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4045 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4049 insn_write_mask (const struct mips_opcode
*opcode
)
4051 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4054 /* Return a mask of the registers specified by operand OPERAND of INSN.
4055 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4059 operand_reg_mask (const struct mips_cl_insn
*insn
,
4060 const struct mips_operand
*operand
,
4061 unsigned int type_mask
)
4063 unsigned int uval
, vsel
;
4065 switch (operand
->type
)
4072 case OP_ADDIUSP_INT
:
4073 case OP_ENTRY_EXIT_LIST
:
4074 case OP_REPEAT_DEST_REG
:
4075 case OP_REPEAT_PREV_REG
:
4078 case OP_VU0_MATCH_SUFFIX
:
4083 case OP_OPTIONAL_REG
:
4085 const struct mips_reg_operand
*reg_op
;
4087 reg_op
= (const struct mips_reg_operand
*) operand
;
4088 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4090 uval
= insn_extract_operand (insn
, operand
);
4091 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4096 const struct mips_reg_pair_operand
*pair_op
;
4098 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4099 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4101 uval
= insn_extract_operand (insn
, operand
);
4102 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4105 case OP_CLO_CLZ_DEST
:
4106 if (!(type_mask
& (1 << OP_REG_GP
)))
4108 uval
= insn_extract_operand (insn
, operand
);
4109 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4111 case OP_LWM_SWM_LIST
:
4114 case OP_SAVE_RESTORE_LIST
:
4117 case OP_MDMX_IMM_REG
:
4118 if (!(type_mask
& (1 << OP_REG_VEC
)))
4120 uval
= insn_extract_operand (insn
, operand
);
4122 if ((vsel
& 0x18) == 0x18)
4124 return 1 << (uval
& 31);
4127 if (!(type_mask
& (1 << OP_REG_GP
)))
4129 return 1 << insn_extract_operand (insn
, operand
);
4134 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4135 where bit N of OPNO_MASK is set if operand N should be included.
4136 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4140 insn_reg_mask (const struct mips_cl_insn
*insn
,
4141 unsigned int type_mask
, unsigned int opno_mask
)
4143 unsigned int opno
, reg_mask
;
4147 while (opno_mask
!= 0)
4150 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4157 /* Return the mask of core registers that IP reads. */
4160 gpr_read_mask (const struct mips_cl_insn
*ip
)
4162 unsigned long pinfo
, pinfo2
;
4165 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4166 pinfo
= ip
->insn_mo
->pinfo
;
4167 pinfo2
= ip
->insn_mo
->pinfo2
;
4168 if (pinfo
& INSN_UDI
)
4170 /* UDI instructions have traditionally been assumed to read RS
4172 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4173 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4175 if (pinfo
& INSN_READ_GPR_24
)
4177 if (pinfo2
& INSN2_READ_GPR_16
)
4179 if (pinfo2
& INSN2_READ_SP
)
4181 if (pinfo2
& INSN2_READ_GPR_31
)
4183 /* Don't include register 0. */
4187 /* Return the mask of core registers that IP writes. */
4190 gpr_write_mask (const struct mips_cl_insn
*ip
)
4192 unsigned long pinfo
, pinfo2
;
4195 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4196 pinfo
= ip
->insn_mo
->pinfo
;
4197 pinfo2
= ip
->insn_mo
->pinfo2
;
4198 if (pinfo
& INSN_WRITE_GPR_24
)
4200 if (pinfo
& INSN_WRITE_GPR_31
)
4202 if (pinfo
& INSN_UDI
)
4203 /* UDI instructions have traditionally been assumed to write to RD. */
4204 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4205 if (pinfo2
& INSN2_WRITE_SP
)
4207 /* Don't include register 0. */
4211 /* Return the mask of floating-point registers that IP reads. */
4214 fpr_read_mask (const struct mips_cl_insn
*ip
)
4216 unsigned long pinfo
;
4219 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4220 | (1 << OP_REG_MSA
)),
4221 insn_read_mask (ip
->insn_mo
));
4222 pinfo
= ip
->insn_mo
->pinfo
;
4223 /* Conservatively treat all operands to an FP_D instruction are doubles.
4224 (This is overly pessimistic for things like cvt.d.s.) */
4225 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4230 /* Return the mask of floating-point registers that IP writes. */
4233 fpr_write_mask (const struct mips_cl_insn
*ip
)
4235 unsigned long pinfo
;
4238 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4239 | (1 << OP_REG_MSA
)),
4240 insn_write_mask (ip
->insn_mo
));
4241 pinfo
= ip
->insn_mo
->pinfo
;
4242 /* Conservatively treat all operands to an FP_D instruction are doubles.
4243 (This is overly pessimistic for things like cvt.s.d.) */
4244 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4249 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4250 Check whether that is allowed. */
4253 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4255 const char *s
= insn
->name
;
4257 if (insn
->pinfo
== INSN_MACRO
)
4258 /* Let a macro pass, we'll catch it later when it is expanded. */
4261 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4263 /* Allow odd registers for single-precision ops. */
4264 switch (insn
->pinfo
& (FP_S
| FP_D
))
4275 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4276 s
= strchr (insn
->name
, '.');
4277 if (s
!= NULL
&& opnum
== 2)
4278 s
= strchr (s
+ 1, '.');
4279 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4282 /* Single-precision coprocessor loads and moves are OK too. */
4283 if ((insn
->pinfo
& FP_S
)
4284 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4285 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4291 /* Information about an instruction argument that we're trying to match. */
4292 struct mips_arg_info
4294 /* The instruction so far. */
4295 struct mips_cl_insn
*insn
;
4297 /* The first unconsumed operand token. */
4298 struct mips_operand_token
*token
;
4300 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4303 /* The 1-based argument number, for error reporting. This does not
4304 count elided optional registers, etc.. */
4307 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4308 unsigned int last_regno
;
4310 /* If the first operand was an OP_REG, this is the register that it
4311 specified, otherwise it is ILLEGAL_REG. */
4312 unsigned int dest_regno
;
4314 /* The value of the last OP_INT operand. Only used for OP_MSB,
4315 where it gives the lsb position. */
4316 unsigned int last_op_int
;
4318 /* If true, match routines should assume that no later instruction
4319 alternative matches and should therefore be as accomodating as
4320 possible. Match routines should not report errors if something
4321 is only invalid for !LAX_MATCH. */
4322 bfd_boolean lax_match
;
4324 /* True if a reference to the current AT register was seen. */
4325 bfd_boolean seen_at
;
4328 /* Record that the argument is out of range. */
4331 match_out_of_range (struct mips_arg_info
*arg
)
4333 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4336 /* Record that the argument isn't constant but needs to be. */
4339 match_not_constant (struct mips_arg_info
*arg
)
4341 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4345 /* Try to match an OT_CHAR token for character CH. Consume the token
4346 and return true on success, otherwise return false. */
4349 match_char (struct mips_arg_info
*arg
, char ch
)
4351 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4361 /* Try to get an expression from the next tokens in ARG. Consume the
4362 tokens and return true on success, storing the expression value in
4363 VALUE and relocation types in R. */
4366 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4367 bfd_reloc_code_real_type
*r
)
4369 /* If the next token is a '(' that was parsed as being part of a base
4370 expression, assume we have an elided offset. The later match will fail
4371 if this turns out to be wrong. */
4372 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4374 value
->X_op
= O_constant
;
4375 value
->X_add_number
= 0;
4376 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4380 /* Reject register-based expressions such as "0+$2" and "(($2))".
4381 For plain registers the default error seems more appropriate. */
4382 if (arg
->token
->type
== OT_INTEGER
4383 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4385 set_insn_error (arg
->argnum
, _("register value used as expression"));
4389 if (arg
->token
->type
== OT_INTEGER
)
4391 *value
= arg
->token
->u
.integer
.value
;
4392 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4398 (arg
->argnum
, _("operand %d must be an immediate expression"),
4403 /* Try to get a constant expression from the next tokens in ARG. Consume
4404 the tokens and return return true on success, storing the constant value
4405 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4409 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4412 bfd_reloc_code_real_type r
[3];
4414 if (!match_expression (arg
, &ex
, r
))
4417 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4418 *value
= ex
.X_add_number
;
4421 match_not_constant (arg
);
4427 /* Return the RTYPE_* flags for a register operand of type TYPE that
4428 appears in instruction OPCODE. */
4431 convert_reg_type (const struct mips_opcode
*opcode
,
4432 enum mips_reg_operand_type type
)
4437 return RTYPE_NUM
| RTYPE_GP
;
4440 /* Allow vector register names for MDMX if the instruction is a 64-bit
4441 FPR load, store or move (including moves to and from GPRs). */
4442 if ((mips_opts
.ase
& ASE_MDMX
)
4443 && (opcode
->pinfo
& FP_D
)
4444 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4445 | INSN_COPROC_MEMORY_DELAY
4446 | INSN_LOAD_COPROC_DELAY
4448 | INSN_STORE_MEMORY
)))
4449 return RTYPE_FPU
| RTYPE_VEC
;
4453 if (opcode
->pinfo
& (FP_D
| FP_S
))
4454 return RTYPE_CCC
| RTYPE_FCC
;
4458 if (opcode
->membership
& INSN_5400
)
4460 return RTYPE_FPU
| RTYPE_VEC
;
4466 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4467 return RTYPE_NUM
| RTYPE_CP0
;
4474 return RTYPE_NUM
| RTYPE_VI
;
4477 return RTYPE_NUM
| RTYPE_VF
;
4479 case OP_REG_R5900_I
:
4480 return RTYPE_R5900_I
;
4482 case OP_REG_R5900_Q
:
4483 return RTYPE_R5900_Q
;
4485 case OP_REG_R5900_R
:
4486 return RTYPE_R5900_R
;
4488 case OP_REG_R5900_ACC
:
4489 return RTYPE_R5900_ACC
;
4494 case OP_REG_MSA_CTRL
:
4500 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4503 check_regno (struct mips_arg_info
*arg
,
4504 enum mips_reg_operand_type type
, unsigned int regno
)
4506 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4507 arg
->seen_at
= TRUE
;
4509 if (type
== OP_REG_FP
4512 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4513 as_warn (_("float register should be even, was %d"), regno
);
4515 if (type
== OP_REG_CCC
)
4520 name
= arg
->insn
->insn_mo
->name
;
4521 length
= strlen (name
);
4522 if ((regno
& 1) != 0
4523 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4524 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4525 as_warn (_("condition code register should be even for %s, was %d"),
4528 if ((regno
& 3) != 0
4529 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4530 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4535 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4536 a register of type TYPE. Return true on success, storing the register
4537 number in *REGNO and warning about any dubious uses. */
4540 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4541 unsigned int symval
, unsigned int *regno
)
4543 if (type
== OP_REG_VEC
)
4544 symval
= mips_prefer_vec_regno (symval
);
4545 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4548 *regno
= symval
& RNUM_MASK
;
4549 check_regno (arg
, type
, *regno
);
4553 /* Try to interpret the next token in ARG as a register of type TYPE.
4554 Consume the token and return true on success, storing the register
4555 number in *REGNO. Return false on failure. */
4558 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4559 unsigned int *regno
)
4561 if (arg
->token
->type
== OT_REG
4562 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4570 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4571 Consume the token and return true on success, storing the register numbers
4572 in *REGNO1 and *REGNO2. Return false on failure. */
4575 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4576 unsigned int *regno1
, unsigned int *regno2
)
4578 if (match_reg (arg
, type
, regno1
))
4583 if (arg
->token
->type
== OT_REG_RANGE
4584 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4585 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4586 && *regno1
<= *regno2
)
4594 /* OP_INT matcher. */
4597 match_int_operand (struct mips_arg_info
*arg
,
4598 const struct mips_operand
*operand_base
)
4600 const struct mips_int_operand
*operand
;
4602 int min_val
, max_val
, factor
;
4605 operand
= (const struct mips_int_operand
*) operand_base
;
4606 factor
= 1 << operand
->shift
;
4607 min_val
= mips_int_operand_min (operand
);
4608 max_val
= mips_int_operand_max (operand
);
4610 if (operand_base
->lsb
== 0
4611 && operand_base
->size
== 16
4612 && operand
->shift
== 0
4613 && operand
->bias
== 0
4614 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4616 /* The operand can be relocated. */
4617 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4620 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4621 /* Relocation operators were used. Accept the arguent and
4622 leave the relocation value in offset_expr and offset_relocs
4623 for the caller to process. */
4626 if (offset_expr
.X_op
!= O_constant
)
4628 /* Accept non-constant operands if no later alternative matches,
4629 leaving it for the caller to process. */
4630 if (!arg
->lax_match
)
4632 offset_reloc
[0] = BFD_RELOC_LO16
;
4636 /* Clear the global state; we're going to install the operand
4638 sval
= offset_expr
.X_add_number
;
4639 offset_expr
.X_op
= O_absent
;
4641 /* For compatibility with older assemblers, we accept
4642 0x8000-0xffff as signed 16-bit numbers when only
4643 signed numbers are allowed. */
4646 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4647 if (!arg
->lax_match
&& sval
<= max_val
)
4653 if (!match_const_int (arg
, &sval
))
4657 arg
->last_op_int
= sval
;
4659 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
4661 match_out_of_range (arg
);
4665 uval
= (unsigned int) sval
>> operand
->shift
;
4666 uval
-= operand
->bias
;
4668 /* Handle -mfix-cn63xxp1. */
4670 && mips_fix_cn63xxp1
4671 && !mips_opts
.micromips
4672 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4687 /* The rest must be changed to 28. */
4692 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4696 /* OP_MAPPED_INT matcher. */
4699 match_mapped_int_operand (struct mips_arg_info
*arg
,
4700 const struct mips_operand
*operand_base
)
4702 const struct mips_mapped_int_operand
*operand
;
4703 unsigned int uval
, num_vals
;
4706 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4707 if (!match_const_int (arg
, &sval
))
4710 num_vals
= 1 << operand_base
->size
;
4711 for (uval
= 0; uval
< num_vals
; uval
++)
4712 if (operand
->int_map
[uval
] == sval
)
4714 if (uval
== num_vals
)
4716 match_out_of_range (arg
);
4720 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4724 /* OP_MSB matcher. */
4727 match_msb_operand (struct mips_arg_info
*arg
,
4728 const struct mips_operand
*operand_base
)
4730 const struct mips_msb_operand
*operand
;
4731 int min_val
, max_val
, max_high
;
4732 offsetT size
, sval
, high
;
4734 operand
= (const struct mips_msb_operand
*) operand_base
;
4735 min_val
= operand
->bias
;
4736 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4737 max_high
= operand
->opsize
;
4739 if (!match_const_int (arg
, &size
))
4742 high
= size
+ arg
->last_op_int
;
4743 sval
= operand
->add_lsb
? high
: size
;
4745 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4747 match_out_of_range (arg
);
4750 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4754 /* OP_REG matcher. */
4757 match_reg_operand (struct mips_arg_info
*arg
,
4758 const struct mips_operand
*operand_base
)
4760 const struct mips_reg_operand
*operand
;
4761 unsigned int regno
, uval
, num_vals
;
4763 operand
= (const struct mips_reg_operand
*) operand_base
;
4764 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4767 if (operand
->reg_map
)
4769 num_vals
= 1 << operand
->root
.size
;
4770 for (uval
= 0; uval
< num_vals
; uval
++)
4771 if (operand
->reg_map
[uval
] == regno
)
4773 if (num_vals
== uval
)
4779 arg
->last_regno
= regno
;
4780 if (arg
->opnum
== 1)
4781 arg
->dest_regno
= regno
;
4782 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4786 /* OP_REG_PAIR matcher. */
4789 match_reg_pair_operand (struct mips_arg_info
*arg
,
4790 const struct mips_operand
*operand_base
)
4792 const struct mips_reg_pair_operand
*operand
;
4793 unsigned int regno1
, regno2
, uval
, num_vals
;
4795 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4796 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4797 || !match_char (arg
, ',')
4798 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4801 num_vals
= 1 << operand_base
->size
;
4802 for (uval
= 0; uval
< num_vals
; uval
++)
4803 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4805 if (uval
== num_vals
)
4808 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4812 /* OP_PCREL matcher. The caller chooses the relocation type. */
4815 match_pcrel_operand (struct mips_arg_info
*arg
)
4817 bfd_reloc_code_real_type r
[3];
4819 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4822 /* OP_PERF_REG matcher. */
4825 match_perf_reg_operand (struct mips_arg_info
*arg
,
4826 const struct mips_operand
*operand
)
4830 if (!match_const_int (arg
, &sval
))
4835 || (mips_opts
.arch
== CPU_R5900
4836 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4837 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4839 set_insn_error (arg
->argnum
, _("invalid performance register"));
4843 insn_insert_operand (arg
->insn
, operand
, sval
);
4847 /* OP_ADDIUSP matcher. */
4850 match_addiusp_operand (struct mips_arg_info
*arg
,
4851 const struct mips_operand
*operand
)
4856 if (!match_const_int (arg
, &sval
))
4861 match_out_of_range (arg
);
4866 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4868 match_out_of_range (arg
);
4872 uval
= (unsigned int) sval
;
4873 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4874 insn_insert_operand (arg
->insn
, operand
, uval
);
4878 /* OP_CLO_CLZ_DEST matcher. */
4881 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4882 const struct mips_operand
*operand
)
4886 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4889 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4893 /* OP_LWM_SWM_LIST matcher. */
4896 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4897 const struct mips_operand
*operand
)
4899 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4900 struct mips_arg_info reset
;
4903 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4907 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4912 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4915 while (match_char (arg
, ',')
4916 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4919 if (operand
->size
== 2)
4921 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4927 and any permutations of these. */
4928 if ((reglist
& 0xfff1ffff) != 0x80010000)
4931 sregs
= (reglist
>> 17) & 7;
4936 /* The list must include at least one of ra and s0-sN,
4937 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4938 which are $23 and $30 respectively.) E.g.:
4946 and any permutations of these. */
4947 if ((reglist
& 0x3f00ffff) != 0)
4950 ra
= (reglist
>> 27) & 0x10;
4951 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4954 if ((sregs
& -sregs
) != sregs
)
4957 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4961 /* OP_ENTRY_EXIT_LIST matcher. */
4964 match_entry_exit_operand (struct mips_arg_info
*arg
,
4965 const struct mips_operand
*operand
)
4968 bfd_boolean is_exit
;
4970 /* The format is the same for both ENTRY and EXIT, but the constraints
4972 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4973 mask
= (is_exit
? 7 << 3 : 0);
4976 unsigned int regno1
, regno2
;
4977 bfd_boolean is_freg
;
4979 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4981 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4986 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4989 mask
|= (5 + regno2
) << 3;
4991 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4992 mask
|= (regno2
- 3) << 3;
4993 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4994 mask
|= (regno2
- 15) << 1;
4995 else if (regno1
== RA
&& regno2
== RA
)
5000 while (match_char (arg
, ','));
5002 insn_insert_operand (arg
->insn
, operand
, mask
);
5006 /* OP_SAVE_RESTORE_LIST matcher. */
5009 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5011 unsigned int opcode
, args
, statics
, sregs
;
5012 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5015 opcode
= arg
->insn
->insn_opcode
;
5017 num_frame_sizes
= 0;
5023 unsigned int regno1
, regno2
;
5025 if (arg
->token
->type
== OT_INTEGER
)
5027 /* Handle the frame size. */
5028 if (!match_const_int (arg
, &frame_size
))
5030 num_frame_sizes
+= 1;
5034 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5037 while (regno1
<= regno2
)
5039 if (regno1
>= 4 && regno1
<= 7)
5041 if (num_frame_sizes
== 0)
5043 args
|= 1 << (regno1
- 4);
5045 /* statics $a0-$a3 */
5046 statics
|= 1 << (regno1
- 4);
5048 else if (regno1
>= 16 && regno1
<= 23)
5050 sregs
|= 1 << (regno1
- 16);
5051 else if (regno1
== 30)
5054 else if (regno1
== 31)
5055 /* Add $ra to insn. */
5065 while (match_char (arg
, ','));
5067 /* Encode args/statics combination. */
5070 else if (args
== 0xf)
5071 /* All $a0-$a3 are args. */
5072 opcode
|= MIPS16_ALL_ARGS
<< 16;
5073 else if (statics
== 0xf)
5074 /* All $a0-$a3 are statics. */
5075 opcode
|= MIPS16_ALL_STATICS
<< 16;
5078 /* Count arg registers. */
5088 /* Count static registers. */
5090 while (statics
& 0x8)
5092 statics
= (statics
<< 1) & 0xf;
5098 /* Encode args/statics. */
5099 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5102 /* Encode $s0/$s1. */
5103 if (sregs
& (1 << 0)) /* $s0 */
5105 if (sregs
& (1 << 1)) /* $s1 */
5109 /* Encode $s2-$s8. */
5118 opcode
|= num_sregs
<< 24;
5120 /* Encode frame size. */
5121 if (num_frame_sizes
== 0)
5123 set_insn_error (arg
->argnum
, _("missing frame size"));
5126 if (num_frame_sizes
> 1)
5128 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5131 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5133 set_insn_error (arg
->argnum
, _("invalid frame size"));
5136 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5139 opcode
|= (((frame_size
& 0xf0) << 16)
5140 | (frame_size
& 0x0f));
5143 /* Finally build the instruction. */
5144 if ((opcode
>> 16) != 0 || frame_size
== 0)
5145 opcode
|= MIPS16_EXTEND
;
5146 arg
->insn
->insn_opcode
= opcode
;
5150 /* OP_MDMX_IMM_REG matcher. */
5153 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5154 const struct mips_operand
*operand
)
5156 unsigned int regno
, uval
;
5158 const struct mips_opcode
*opcode
;
5160 /* The mips_opcode records whether this is an octobyte or quadhalf
5161 instruction. Start out with that bit in place. */
5162 opcode
= arg
->insn
->insn_mo
;
5163 uval
= mips_extract_operand (operand
, opcode
->match
);
5164 is_qh
= (uval
!= 0);
5166 if (arg
->token
->type
== OT_REG
)
5168 if ((opcode
->membership
& INSN_5400
)
5169 && strcmp (opcode
->name
, "rzu.ob") == 0)
5171 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5176 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5180 /* Check whether this is a vector register or a broadcast of
5181 a single element. */
5182 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5184 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5186 set_insn_error (arg
->argnum
, _("invalid element selector"));
5189 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5194 /* A full vector. */
5195 if ((opcode
->membership
& INSN_5400
)
5196 && (strcmp (opcode
->name
, "sll.ob") == 0
5197 || strcmp (opcode
->name
, "srl.ob") == 0))
5199 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5205 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5207 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5215 if (!match_const_int (arg
, &sval
))
5217 if (sval
< 0 || sval
> 31)
5219 match_out_of_range (arg
);
5222 uval
|= (sval
& 31);
5224 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5226 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5228 insn_insert_operand (arg
->insn
, operand
, uval
);
5232 /* OP_IMM_INDEX matcher. */
5235 match_imm_index_operand (struct mips_arg_info
*arg
,
5236 const struct mips_operand
*operand
)
5238 unsigned int max_val
;
5240 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5243 max_val
= (1 << operand
->size
) - 1;
5244 if (arg
->token
->u
.index
> max_val
)
5246 match_out_of_range (arg
);
5249 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5254 /* OP_REG_INDEX matcher. */
5257 match_reg_index_operand (struct mips_arg_info
*arg
,
5258 const struct mips_operand
*operand
)
5262 if (arg
->token
->type
!= OT_REG_INDEX
)
5265 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5268 insn_insert_operand (arg
->insn
, operand
, regno
);
5273 /* OP_PC matcher. */
5276 match_pc_operand (struct mips_arg_info
*arg
)
5278 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5286 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5287 register that we need to match. */
5290 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5294 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5297 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5298 the length of the value in bytes (4 for float, 8 for double) and
5299 USING_GPRS says whether the destination is a GPR rather than an FPR.
5301 Return the constant in IMM and OFFSET as follows:
5303 - If the constant should be loaded via memory, set IMM to O_absent and
5304 OFFSET to the memory address.
5306 - Otherwise, if the constant should be loaded into two 32-bit registers,
5307 set IMM to the O_constant to load into the high register and OFFSET
5308 to the corresponding value for the low register.
5310 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5312 These constants only appear as the last operand in an instruction,
5313 and every instruction that accepts them in any variant accepts them
5314 in all variants. This means we don't have to worry about backing out
5315 any changes if the instruction does not match. We just match
5316 unconditionally and report an error if the constant is invalid. */
5319 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5320 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5325 const char *newname
;
5326 unsigned char *data
;
5328 /* Where the constant is placed is based on how the MIPS assembler
5331 length == 4 && using_gprs -- immediate value only
5332 length == 8 && using_gprs -- .rdata or immediate value
5333 length == 4 && !using_gprs -- .lit4 or immediate value
5334 length == 8 && !using_gprs -- .lit8 or immediate value
5336 The .lit4 and .lit8 sections are only used if permitted by the
5338 if (arg
->token
->type
!= OT_FLOAT
)
5340 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5344 gas_assert (arg
->token
->u
.flt
.length
== length
);
5345 data
= arg
->token
->u
.flt
.data
;
5348 /* Handle 32-bit constants for which an immediate value is best. */
5351 || g_switch_value
< 4
5352 || (data
[0] == 0 && data
[1] == 0)
5353 || (data
[2] == 0 && data
[3] == 0)))
5355 imm
->X_op
= O_constant
;
5356 if (!target_big_endian
)
5357 imm
->X_add_number
= bfd_getl32 (data
);
5359 imm
->X_add_number
= bfd_getb32 (data
);
5360 offset
->X_op
= O_absent
;
5364 /* Handle 64-bit constants for which an immediate value is best. */
5366 && !mips_disable_float_construction
5367 /* Constants can only be constructed in GPRs and copied
5368 to FPRs if the GPRs are at least as wide as the FPRs.
5369 Force the constant into memory if we are using 64-bit FPRs
5370 but the GPRs are only 32 bits wide. */
5371 /* ??? No longer true with the addition of MTHC1, but this
5372 is legacy code... */
5373 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5374 && ((data
[0] == 0 && data
[1] == 0)
5375 || (data
[2] == 0 && data
[3] == 0))
5376 && ((data
[4] == 0 && data
[5] == 0)
5377 || (data
[6] == 0 && data
[7] == 0)))
5379 /* The value is simple enough to load with a couple of instructions.
5380 If using 32-bit registers, set IMM to the high order 32 bits and
5381 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5383 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5385 imm
->X_op
= O_constant
;
5386 offset
->X_op
= O_constant
;
5387 if (!target_big_endian
)
5389 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5390 offset
->X_add_number
= bfd_getl32 (data
);
5394 imm
->X_add_number
= bfd_getb32 (data
);
5395 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5397 if (offset
->X_add_number
== 0)
5398 offset
->X_op
= O_absent
;
5402 imm
->X_op
= O_constant
;
5403 if (!target_big_endian
)
5404 imm
->X_add_number
= bfd_getl64 (data
);
5406 imm
->X_add_number
= bfd_getb64 (data
);
5407 offset
->X_op
= O_absent
;
5412 /* Switch to the right section. */
5414 subseg
= now_subseg
;
5417 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5422 if (using_gprs
|| g_switch_value
< 8)
5423 newname
= RDATA_SECTION_NAME
;
5428 new_seg
= subseg_new (newname
, (subsegT
) 0);
5429 bfd_set_section_flags (stdoutput
, new_seg
,
5430 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5431 frag_align (length
== 4 ? 2 : 3, 0, 0);
5432 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5433 record_alignment (new_seg
, 4);
5435 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5437 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5439 /* Set the argument to the current address in the section. */
5440 imm
->X_op
= O_absent
;
5441 offset
->X_op
= O_symbol
;
5442 offset
->X_add_symbol
= symbol_temp_new_now ();
5443 offset
->X_add_number
= 0;
5445 /* Put the floating point number into the section. */
5446 p
= frag_more (length
);
5447 memcpy (p
, data
, length
);
5449 /* Switch back to the original section. */
5450 subseg_set (seg
, subseg
);
5454 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5458 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5459 const struct mips_operand
*operand
,
5460 bfd_boolean match_p
)
5464 /* The operand can be an XYZW mask or a single 2-bit channel index
5465 (with X being 0). */
5466 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5468 /* The suffix can be omitted when it is already part of the opcode. */
5469 if (arg
->token
->type
!= OT_CHANNELS
)
5472 uval
= arg
->token
->u
.channels
;
5473 if (operand
->size
== 2)
5475 /* Check that a single bit is set and convert it into a 2-bit index. */
5476 if ((uval
& -uval
) != uval
)
5478 uval
= 4 - ffs (uval
);
5481 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5486 insn_insert_operand (arg
->insn
, operand
, uval
);
5490 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5491 of the argument text if the match is successful, otherwise return null. */
5494 match_operand (struct mips_arg_info
*arg
,
5495 const struct mips_operand
*operand
)
5497 switch (operand
->type
)
5500 return match_int_operand (arg
, operand
);
5503 return match_mapped_int_operand (arg
, operand
);
5506 return match_msb_operand (arg
, operand
);
5509 case OP_OPTIONAL_REG
:
5510 return match_reg_operand (arg
, operand
);
5513 return match_reg_pair_operand (arg
, operand
);
5516 return match_pcrel_operand (arg
);
5519 return match_perf_reg_operand (arg
, operand
);
5521 case OP_ADDIUSP_INT
:
5522 return match_addiusp_operand (arg
, operand
);
5524 case OP_CLO_CLZ_DEST
:
5525 return match_clo_clz_dest_operand (arg
, operand
);
5527 case OP_LWM_SWM_LIST
:
5528 return match_lwm_swm_list_operand (arg
, operand
);
5530 case OP_ENTRY_EXIT_LIST
:
5531 return match_entry_exit_operand (arg
, operand
);
5533 case OP_SAVE_RESTORE_LIST
:
5534 return match_save_restore_list_operand (arg
);
5536 case OP_MDMX_IMM_REG
:
5537 return match_mdmx_imm_reg_operand (arg
, operand
);
5539 case OP_REPEAT_DEST_REG
:
5540 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5542 case OP_REPEAT_PREV_REG
:
5543 return match_tied_reg_operand (arg
, arg
->last_regno
);
5546 return match_pc_operand (arg
);
5549 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5551 case OP_VU0_MATCH_SUFFIX
:
5552 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5555 return match_imm_index_operand (arg
, operand
);
5558 return match_reg_index_operand (arg
, operand
);
5563 /* ARG is the state after successfully matching an instruction.
5564 Issue any queued-up warnings. */
5567 check_completed_insn (struct mips_arg_info
*arg
)
5572 as_warn (_("used $at without \".set noat\""));
5574 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
5578 /* Return true if modifying general-purpose register REG needs a delay. */
5581 reg_needs_delay (unsigned int reg
)
5583 unsigned long prev_pinfo
;
5585 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5586 if (!mips_opts
.noreorder
5587 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
5588 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5589 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5595 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5596 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5597 by VR4120 errata. */
5600 classify_vr4120_insn (const char *name
)
5602 if (strncmp (name
, "macc", 4) == 0)
5603 return FIX_VR4120_MACC
;
5604 if (strncmp (name
, "dmacc", 5) == 0)
5605 return FIX_VR4120_DMACC
;
5606 if (strncmp (name
, "mult", 4) == 0)
5607 return FIX_VR4120_MULT
;
5608 if (strncmp (name
, "dmult", 5) == 0)
5609 return FIX_VR4120_DMULT
;
5610 if (strstr (name
, "div"))
5611 return FIX_VR4120_DIV
;
5612 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5613 return FIX_VR4120_MTHILO
;
5614 return NUM_FIX_VR4120_CLASSES
;
5617 #define INSN_ERET 0x42000018
5618 #define INSN_DERET 0x4200001f
5619 #define INSN_DMULT 0x1c
5620 #define INSN_DMULTU 0x1d
5622 /* Return the number of instructions that must separate INSN1 and INSN2,
5623 where INSN1 is the earlier instruction. Return the worst-case value
5624 for any INSN2 if INSN2 is null. */
5627 insns_between (const struct mips_cl_insn
*insn1
,
5628 const struct mips_cl_insn
*insn2
)
5630 unsigned long pinfo1
, pinfo2
;
5633 /* If INFO2 is null, pessimistically assume that all flags are set for
5634 the second instruction. */
5635 pinfo1
= insn1
->insn_mo
->pinfo
;
5636 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5638 /* For most targets, write-after-read dependencies on the HI and LO
5639 registers must be separated by at least two instructions. */
5640 if (!hilo_interlocks
)
5642 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5644 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5648 /* If we're working around r7000 errata, there must be two instructions
5649 between an mfhi or mflo and any instruction that uses the result. */
5650 if (mips_7000_hilo_fix
5651 && !mips_opts
.micromips
5652 && MF_HILO_INSN (pinfo1
)
5653 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5656 /* If we're working around 24K errata, one instruction is required
5657 if an ERET or DERET is followed by a branch instruction. */
5658 if (mips_fix_24k
&& !mips_opts
.micromips
)
5660 if (insn1
->insn_opcode
== INSN_ERET
5661 || insn1
->insn_opcode
== INSN_DERET
)
5664 || insn2
->insn_opcode
== INSN_ERET
5665 || insn2
->insn_opcode
== INSN_DERET
5666 || delayed_branch_p (insn2
))
5671 /* If we're working around PMC RM7000 errata, there must be three
5672 nops between a dmult and a load instruction. */
5673 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
5675 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
5676 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
5678 if (pinfo2
& INSN_LOAD_MEMORY
)
5683 /* If working around VR4120 errata, check for combinations that need
5684 a single intervening instruction. */
5685 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5687 unsigned int class1
, class2
;
5689 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5690 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5694 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5695 if (vr4120_conflicts
[class1
] & (1 << class2
))
5700 if (!HAVE_CODE_COMPRESSION
)
5702 /* Check for GPR or coprocessor load delays. All such delays
5703 are on the RT register. */
5704 /* Itbl support may require additional care here. */
5705 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
5706 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5708 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5712 /* Check for generic coprocessor hazards.
5714 This case is not handled very well. There is no special
5715 knowledge of CP0 handling, and the coprocessors other than
5716 the floating point unit are not distinguished at all. */
5717 /* Itbl support may require additional care here. FIXME!
5718 Need to modify this to include knowledge about
5719 user specified delays! */
5720 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5721 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5723 /* Handle cases where INSN1 writes to a known general coprocessor
5724 register. There must be a one instruction delay before INSN2
5725 if INSN2 reads that register, otherwise no delay is needed. */
5726 mask
= fpr_write_mask (insn1
);
5729 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5734 /* Read-after-write dependencies on the control registers
5735 require a two-instruction gap. */
5736 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5737 && (pinfo2
& INSN_READ_COND_CODE
))
5740 /* We don't know exactly what INSN1 does. If INSN2 is
5741 also a coprocessor instruction, assume there must be
5742 a one instruction gap. */
5743 if (pinfo2
& INSN_COP
)
5748 /* Check for read-after-write dependencies on the coprocessor
5749 control registers in cases where INSN1 does not need a general
5750 coprocessor delay. This means that INSN1 is a floating point
5751 comparison instruction. */
5752 /* Itbl support may require additional care here. */
5753 else if (!cop_interlocks
5754 && (pinfo1
& INSN_WRITE_COND_CODE
)
5755 && (pinfo2
& INSN_READ_COND_CODE
))
5762 /* Return the number of nops that would be needed to work around the
5763 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5764 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5765 that are contained within the first IGNORE instructions of HIST. */
5768 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5769 const struct mips_cl_insn
*insn
)
5774 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5775 are not affected by the errata. */
5777 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5778 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5779 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5782 /* Search for the first MFLO or MFHI. */
5783 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5784 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5786 /* Extract the destination register. */
5787 mask
= gpr_write_mask (&hist
[i
]);
5789 /* No nops are needed if INSN reads that register. */
5790 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5793 /* ...or if any of the intervening instructions do. */
5794 for (j
= 0; j
< i
; j
++)
5795 if (gpr_read_mask (&hist
[j
]) & mask
)
5799 return MAX_VR4130_NOPS
- i
;
5804 #define BASE_REG_EQ(INSN1, INSN2) \
5805 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5806 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5808 /* Return the minimum alignment for this store instruction. */
5811 fix_24k_align_to (const struct mips_opcode
*mo
)
5813 if (strcmp (mo
->name
, "sh") == 0)
5816 if (strcmp (mo
->name
, "swc1") == 0
5817 || strcmp (mo
->name
, "swc2") == 0
5818 || strcmp (mo
->name
, "sw") == 0
5819 || strcmp (mo
->name
, "sc") == 0
5820 || strcmp (mo
->name
, "s.s") == 0)
5823 if (strcmp (mo
->name
, "sdc1") == 0
5824 || strcmp (mo
->name
, "sdc2") == 0
5825 || strcmp (mo
->name
, "s.d") == 0)
5832 struct fix_24k_store_info
5834 /* Immediate offset, if any, for this store instruction. */
5836 /* Alignment required by this store instruction. */
5838 /* True for register offsets. */
5839 int register_offset
;
5842 /* Comparison function used by qsort. */
5845 fix_24k_sort (const void *a
, const void *b
)
5847 const struct fix_24k_store_info
*pos1
= a
;
5848 const struct fix_24k_store_info
*pos2
= b
;
5850 return (pos1
->off
- pos2
->off
);
5853 /* INSN is a store instruction. Try to record the store information
5854 in STINFO. Return false if the information isn't known. */
5857 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5858 const struct mips_cl_insn
*insn
)
5860 /* The instruction must have a known offset. */
5861 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5864 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5865 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5869 /* Return the number of nops that would be needed to work around the 24k
5870 "lost data on stores during refill" errata if instruction INSN
5871 immediately followed the 2 instructions described by HIST.
5872 Ignore hazards that are contained within the first IGNORE
5873 instructions of HIST.
5875 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5876 for the data cache refills and store data. The following describes
5877 the scenario where the store data could be lost.
5879 * A data cache miss, due to either a load or a store, causing fill
5880 data to be supplied by the memory subsystem
5881 * The first three doublewords of fill data are returned and written
5883 * A sequence of four stores occurs in consecutive cycles around the
5884 final doubleword of the fill:
5888 * Zero, One or more instructions
5891 The four stores A-D must be to different doublewords of the line that
5892 is being filled. The fourth instruction in the sequence above permits
5893 the fill of the final doubleword to be transferred from the FSB into
5894 the cache. In the sequence above, the stores may be either integer
5895 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5896 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5897 different doublewords on the line. If the floating point unit is
5898 running in 1:2 mode, it is not possible to create the sequence above
5899 using only floating point store instructions.
5901 In this case, the cache line being filled is incorrectly marked
5902 invalid, thereby losing the data from any store to the line that
5903 occurs between the original miss and the completion of the five
5904 cycle sequence shown above.
5906 The workarounds are:
5908 * Run the data cache in write-through mode.
5909 * Insert a non-store instruction between
5910 Store A and Store B or Store B and Store C. */
5913 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5914 const struct mips_cl_insn
*insn
)
5916 struct fix_24k_store_info pos
[3];
5917 int align
, i
, base_offset
;
5922 /* If the previous instruction wasn't a store, there's nothing to
5924 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5927 /* If the instructions after the previous one are unknown, we have
5928 to assume the worst. */
5932 /* Check whether we are dealing with three consecutive stores. */
5933 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5934 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5937 /* If we don't know the relationship between the store addresses,
5938 assume the worst. */
5939 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5940 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5943 if (!fix_24k_record_store_info (&pos
[0], insn
)
5944 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5945 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5948 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5950 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5951 X bytes and such that the base register + X is known to be aligned
5954 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5958 align
= pos
[0].align_to
;
5959 base_offset
= pos
[0].off
;
5960 for (i
= 1; i
< 3; i
++)
5961 if (align
< pos
[i
].align_to
)
5963 align
= pos
[i
].align_to
;
5964 base_offset
= pos
[i
].off
;
5966 for (i
= 0; i
< 3; i
++)
5967 pos
[i
].off
-= base_offset
;
5970 pos
[0].off
&= ~align
+ 1;
5971 pos
[1].off
&= ~align
+ 1;
5972 pos
[2].off
&= ~align
+ 1;
5974 /* If any two stores write to the same chunk, they also write to the
5975 same doubleword. The offsets are still sorted at this point. */
5976 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5979 /* A range of at least 9 bytes is needed for the stores to be in
5980 non-overlapping doublewords. */
5981 if (pos
[2].off
- pos
[0].off
<= 8)
5984 if (pos
[2].off
- pos
[1].off
>= 24
5985 || pos
[1].off
- pos
[0].off
>= 24
5986 || pos
[2].off
- pos
[0].off
>= 32)
5992 /* Return the number of nops that would be needed if instruction INSN
5993 immediately followed the MAX_NOPS instructions given by HIST,
5994 where HIST[0] is the most recent instruction. Ignore hazards
5995 between INSN and the first IGNORE instructions in HIST.
5997 If INSN is null, return the worse-case number of nops for any
6001 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6002 const struct mips_cl_insn
*insn
)
6004 int i
, nops
, tmp_nops
;
6007 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6009 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6010 if (tmp_nops
> nops
)
6014 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6016 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6017 if (tmp_nops
> nops
)
6021 if (mips_fix_24k
&& !mips_opts
.micromips
)
6023 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6024 if (tmp_nops
> nops
)
6031 /* The variable arguments provide NUM_INSNS extra instructions that
6032 might be added to HIST. Return the largest number of nops that
6033 would be needed after the extended sequence, ignoring hazards
6034 in the first IGNORE instructions. */
6037 nops_for_sequence (int num_insns
, int ignore
,
6038 const struct mips_cl_insn
*hist
, ...)
6041 struct mips_cl_insn buffer
[MAX_NOPS
];
6042 struct mips_cl_insn
*cursor
;
6045 va_start (args
, hist
);
6046 cursor
= buffer
+ num_insns
;
6047 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6048 while (cursor
> buffer
)
6049 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6051 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6056 /* Like nops_for_insn, but if INSN is a branch, take into account the
6057 worst-case delay for the branch target. */
6060 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6061 const struct mips_cl_insn
*insn
)
6065 nops
= nops_for_insn (ignore
, hist
, insn
);
6066 if (delayed_branch_p (insn
))
6068 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6069 hist
, insn
, get_delay_slot_nop (insn
));
6070 if (tmp_nops
> nops
)
6073 else if (compact_branch_p (insn
))
6075 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6076 if (tmp_nops
> nops
)
6082 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6085 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6087 gas_assert (!HAVE_CODE_COMPRESSION
);
6088 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6089 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6092 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6093 jr target pc &= 'hffff_ffff_cfff_ffff. */
6096 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6098 gas_assert (!HAVE_CODE_COMPRESSION
);
6099 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6100 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6101 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6109 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6110 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6113 ep
.X_op
= O_constant
;
6114 ep
.X_add_number
= 0xcfff0000;
6115 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6116 ep
.X_add_number
= 0xffff;
6117 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6118 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6123 fix_loongson2f (struct mips_cl_insn
* ip
)
6125 if (mips_fix_loongson2f_nop
)
6126 fix_loongson2f_nop (ip
);
6128 if (mips_fix_loongson2f_jump
)
6129 fix_loongson2f_jump (ip
);
6132 /* IP is a branch that has a delay slot, and we need to fill it
6133 automatically. Return true if we can do that by swapping IP
6134 with the previous instruction.
6135 ADDRESS_EXPR is an operand of the instruction to be used with
6139 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6140 bfd_reloc_code_real_type
*reloc_type
)
6142 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6143 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6144 unsigned int fpr_read
, prev_fpr_write
;
6146 /* -O2 and above is required for this optimization. */
6147 if (mips_optimize
< 2)
6150 /* If we have seen .set volatile or .set nomove, don't optimize. */
6151 if (mips_opts
.nomove
)
6154 /* We can't swap if the previous instruction's position is fixed. */
6155 if (history
[0].fixed_p
)
6158 /* If the previous previous insn was in a .set noreorder, we can't
6159 swap. Actually, the MIPS assembler will swap in this situation.
6160 However, gcc configured -with-gnu-as will generate code like
6168 in which we can not swap the bne and INSN. If gcc is not configured
6169 -with-gnu-as, it does not output the .set pseudo-ops. */
6170 if (history
[1].noreorder_p
)
6173 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6174 This means that the previous instruction was a 4-byte one anyhow. */
6175 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6178 /* If the branch is itself the target of a branch, we can not swap.
6179 We cheat on this; all we check for is whether there is a label on
6180 this instruction. If there are any branches to anything other than
6181 a label, users must use .set noreorder. */
6182 if (seg_info (now_seg
)->label_list
)
6185 /* If the previous instruction is in a variant frag other than this
6186 branch's one, we cannot do the swap. This does not apply to
6187 MIPS16 code, which uses variant frags for different purposes. */
6188 if (!mips_opts
.mips16
6190 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6193 /* We do not swap with instructions that cannot architecturally
6194 be placed in a branch delay slot, such as SYNC or ERET. We
6195 also refrain from swapping with a trap instruction, since it
6196 complicates trap handlers to have the trap instruction be in
6198 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6199 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6202 /* Check for conflicts between the branch and the instructions
6203 before the candidate delay slot. */
6204 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6207 /* Check for conflicts between the swapped sequence and the
6208 target of the branch. */
6209 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6212 /* If the branch reads a register that the previous
6213 instruction sets, we can not swap. */
6214 gpr_read
= gpr_read_mask (ip
);
6215 prev_gpr_write
= gpr_write_mask (&history
[0]);
6216 if (gpr_read
& prev_gpr_write
)
6219 fpr_read
= fpr_read_mask (ip
);
6220 prev_fpr_write
= fpr_write_mask (&history
[0]);
6221 if (fpr_read
& prev_fpr_write
)
6224 /* If the branch writes a register that the previous
6225 instruction sets, we can not swap. */
6226 gpr_write
= gpr_write_mask (ip
);
6227 if (gpr_write
& prev_gpr_write
)
6230 /* If the branch writes a register that the previous
6231 instruction reads, we can not swap. */
6232 prev_gpr_read
= gpr_read_mask (&history
[0]);
6233 if (gpr_write
& prev_gpr_read
)
6236 /* If one instruction sets a condition code and the
6237 other one uses a condition code, we can not swap. */
6238 pinfo
= ip
->insn_mo
->pinfo
;
6239 if ((pinfo
& INSN_READ_COND_CODE
)
6240 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6242 if ((pinfo
& INSN_WRITE_COND_CODE
)
6243 && (prev_pinfo
& INSN_READ_COND_CODE
))
6246 /* If the previous instruction uses the PC, we can not swap. */
6247 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6248 if (prev_pinfo2
& INSN2_READ_PC
)
6251 /* If the previous instruction has an incorrect size for a fixed
6252 branch delay slot in microMIPS mode, we cannot swap. */
6253 pinfo2
= ip
->insn_mo
->pinfo2
;
6254 if (mips_opts
.micromips
6255 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6256 && insn_length (history
) != 2)
6258 if (mips_opts
.micromips
6259 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6260 && insn_length (history
) != 4)
6263 /* On R5900 short loops need to be fixed by inserting a nop in
6264 the branch delay slots.
6265 A short loop can be terminated too early. */
6266 if (mips_opts
.arch
== CPU_R5900
6267 /* Check if instruction has a parameter, ignore "j $31". */
6268 && (address_expr
!= NULL
)
6269 /* Parameter must be 16 bit. */
6270 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6271 /* Branch to same segment. */
6272 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6273 /* Branch to same code fragment. */
6274 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6275 /* Can only calculate branch offset if value is known. */
6276 && symbol_constant_p(address_expr
->X_add_symbol
)
6277 /* Check if branch is really conditional. */
6278 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6279 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6280 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6283 /* Check if loop is shorter than 6 instructions including
6284 branch and delay slot. */
6285 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6292 /* When the loop includes branches or jumps,
6293 it is not a short loop. */
6294 for (i
= 0; i
< (distance
/ 4); i
++)
6296 if ((history
[i
].cleared_p
)
6297 || delayed_branch_p(&history
[i
]))
6305 /* Insert nop after branch to fix short loop. */
6314 /* Decide how we should add IP to the instruction stream.
6315 ADDRESS_EXPR is an operand of the instruction to be used with
6318 static enum append_method
6319 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6320 bfd_reloc_code_real_type
*reloc_type
)
6322 /* The relaxed version of a macro sequence must be inherently
6324 if (mips_relax
.sequence
== 2)
6327 /* We must not dabble with instructions in a ".set norerorder" block. */
6328 if (mips_opts
.noreorder
)
6331 /* Otherwise, it's our responsibility to fill branch delay slots. */
6332 if (delayed_branch_p (ip
))
6334 if (!branch_likely_p (ip
)
6335 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6338 if (mips_opts
.mips16
6339 && ISA_SUPPORTS_MIPS16E
6340 && gpr_read_mask (ip
) != 0)
6341 return APPEND_ADD_COMPACT
;
6343 return APPEND_ADD_WITH_NOP
;
6349 /* IP is a MIPS16 instruction whose opcode we have just changed.
6350 Point IP->insn_mo to the new opcode's definition. */
6353 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6355 const struct mips_opcode
*mo
, *end
;
6357 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6358 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6359 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6367 /* For microMIPS macros, we need to generate a local number label
6368 as the target of branches. */
6369 #define MICROMIPS_LABEL_CHAR '\037'
6370 static unsigned long micromips_target_label
;
6371 static char micromips_target_name
[32];
6374 micromips_label_name (void)
6376 char *p
= micromips_target_name
;
6377 char symbol_name_temporary
[24];
6385 l
= micromips_target_label
;
6386 #ifdef LOCAL_LABEL_PREFIX
6387 *p
++ = LOCAL_LABEL_PREFIX
;
6390 *p
++ = MICROMIPS_LABEL_CHAR
;
6393 symbol_name_temporary
[i
++] = l
% 10 + '0';
6398 *p
++ = symbol_name_temporary
[--i
];
6401 return micromips_target_name
;
6405 micromips_label_expr (expressionS
*label_expr
)
6407 label_expr
->X_op
= O_symbol
;
6408 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6409 label_expr
->X_add_number
= 0;
6413 micromips_label_inc (void)
6415 micromips_target_label
++;
6416 *micromips_target_name
= '\0';
6420 micromips_add_label (void)
6424 s
= colon (micromips_label_name ());
6425 micromips_label_inc ();
6426 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6429 /* If assembling microMIPS code, then return the microMIPS reloc
6430 corresponding to the requested one if any. Otherwise return
6431 the reloc unchanged. */
6433 static bfd_reloc_code_real_type
6434 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6436 static const bfd_reloc_code_real_type relocs
[][2] =
6438 /* Keep sorted incrementally by the left-hand key. */
6439 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6440 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6441 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6442 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6443 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6444 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6445 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6446 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6447 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6448 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6449 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6450 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6451 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6452 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6453 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6454 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6455 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6456 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6457 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6458 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6459 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6460 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6461 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6462 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6463 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6464 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6465 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6467 bfd_reloc_code_real_type r
;
6470 if (!mips_opts
.micromips
)
6472 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6478 return relocs
[i
][1];
6483 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6484 Return true on success, storing the resolved value in RESULT. */
6487 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6492 case BFD_RELOC_MIPS_HIGHEST
:
6493 case BFD_RELOC_MICROMIPS_HIGHEST
:
6494 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6497 case BFD_RELOC_MIPS_HIGHER
:
6498 case BFD_RELOC_MICROMIPS_HIGHER
:
6499 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6502 case BFD_RELOC_HI16_S
:
6503 case BFD_RELOC_MICROMIPS_HI16_S
:
6504 case BFD_RELOC_MIPS16_HI16_S
:
6505 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6508 case BFD_RELOC_HI16
:
6509 case BFD_RELOC_MICROMIPS_HI16
:
6510 case BFD_RELOC_MIPS16_HI16
:
6511 *result
= (operand
>> 16) & 0xffff;
6514 case BFD_RELOC_LO16
:
6515 case BFD_RELOC_MICROMIPS_LO16
:
6516 case BFD_RELOC_MIPS16_LO16
:
6517 *result
= operand
& 0xffff;
6520 case BFD_RELOC_UNUSED
:
6529 /* Output an instruction. IP is the instruction information.
6530 ADDRESS_EXPR is an operand of the instruction to be used with
6531 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6532 a macro expansion. */
6535 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6536 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6538 unsigned long prev_pinfo2
, pinfo
;
6539 bfd_boolean relaxed_branch
= FALSE
;
6540 enum append_method method
;
6541 bfd_boolean relax32
;
6544 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6545 fix_loongson2f (ip
);
6547 file_ase_mips16
|= mips_opts
.mips16
;
6548 file_ase_micromips
|= mips_opts
.micromips
;
6550 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6551 pinfo
= ip
->insn_mo
->pinfo
;
6553 if (mips_opts
.micromips
6555 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6556 && micromips_insn_length (ip
->insn_mo
) != 2)
6557 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6558 && micromips_insn_length (ip
->insn_mo
) != 4)))
6559 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
6560 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6562 if (address_expr
== NULL
)
6564 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6565 && reloc_type
[1] == BFD_RELOC_UNUSED
6566 && reloc_type
[2] == BFD_RELOC_UNUSED
6567 && address_expr
->X_op
== O_constant
)
6569 switch (*reloc_type
)
6571 case BFD_RELOC_MIPS_JMP
:
6575 shift
= mips_opts
.micromips
? 1 : 2;
6576 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6577 as_bad (_("jump to misaligned address (0x%lx)"),
6578 (unsigned long) address_expr
->X_add_number
);
6579 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6585 case BFD_RELOC_MIPS16_JMP
:
6586 if ((address_expr
->X_add_number
& 3) != 0)
6587 as_bad (_("jump to misaligned address (0x%lx)"),
6588 (unsigned long) address_expr
->X_add_number
);
6590 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6591 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6592 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6596 case BFD_RELOC_16_PCREL_S2
:
6600 shift
= mips_opts
.micromips
? 1 : 2;
6601 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6602 as_bad (_("branch to misaligned address (0x%lx)"),
6603 (unsigned long) address_expr
->X_add_number
);
6604 if (!mips_relax_branch
)
6606 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6607 & ~((1 << (shift
+ 16)) - 1))
6608 as_bad (_("branch address range overflow (0x%lx)"),
6609 (unsigned long) address_expr
->X_add_number
);
6610 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6620 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6623 ip
->insn_opcode
|= value
& 0xffff;
6631 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6633 /* There are a lot of optimizations we could do that we don't.
6634 In particular, we do not, in general, reorder instructions.
6635 If you use gcc with optimization, it will reorder
6636 instructions and generally do much more optimization then we
6637 do here; repeating all that work in the assembler would only
6638 benefit hand written assembly code, and does not seem worth
6640 int nops
= (mips_optimize
== 0
6641 ? nops_for_insn (0, history
, NULL
)
6642 : nops_for_insn_or_target (0, history
, ip
));
6646 unsigned long old_frag_offset
;
6649 old_frag
= frag_now
;
6650 old_frag_offset
= frag_now_fix ();
6652 for (i
= 0; i
< nops
; i
++)
6653 add_fixed_insn (NOP_INSN
);
6654 insert_into_history (0, nops
, NOP_INSN
);
6658 listing_prev_line ();
6659 /* We may be at the start of a variant frag. In case we
6660 are, make sure there is enough space for the frag
6661 after the frags created by listing_prev_line. The
6662 argument to frag_grow here must be at least as large
6663 as the argument to all other calls to frag_grow in
6664 this file. We don't have to worry about being in the
6665 middle of a variant frag, because the variants insert
6666 all needed nop instructions themselves. */
6670 mips_move_text_labels ();
6672 #ifndef NO_ECOFF_DEBUGGING
6673 if (ECOFF_DEBUGGING
)
6674 ecoff_fix_loc (old_frag
, old_frag_offset
);
6678 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6682 /* Work out how many nops in prev_nop_frag are needed by IP,
6683 ignoring hazards generated by the first prev_nop_frag_since
6685 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6686 gas_assert (nops
<= prev_nop_frag_holds
);
6688 /* Enforce NOPS as a minimum. */
6689 if (nops
> prev_nop_frag_required
)
6690 prev_nop_frag_required
= nops
;
6692 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6694 /* Settle for the current number of nops. Update the history
6695 accordingly (for the benefit of any future .set reorder code). */
6696 prev_nop_frag
= NULL
;
6697 insert_into_history (prev_nop_frag_since
,
6698 prev_nop_frag_holds
, NOP_INSN
);
6702 /* Allow this instruction to replace one of the nops that was
6703 tentatively added to prev_nop_frag. */
6704 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6705 prev_nop_frag_holds
--;
6706 prev_nop_frag_since
++;
6710 method
= get_append_method (ip
, address_expr
, reloc_type
);
6711 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6713 dwarf2_emit_insn (0);
6714 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6715 so "move" the instruction address accordingly.
6717 Also, it doesn't seem appropriate for the assembler to reorder .loc
6718 entries. If this instruction is a branch that we are going to swap
6719 with the previous instruction, the two instructions should be
6720 treated as a unit, and the debug information for both instructions
6721 should refer to the start of the branch sequence. Using the
6722 current position is certainly wrong when swapping a 32-bit branch
6723 and a 16-bit delay slot, since the current position would then be
6724 in the middle of a branch. */
6725 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6727 relax32
= (mips_relax_branch
6728 /* Don't try branch relaxation within .set nomacro, or within
6729 .set noat if we use $at for PIC computations. If it turns
6730 out that the branch was out-of-range, we'll get an error. */
6731 && !mips_opts
.warn_about_macros
6732 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6733 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6734 as they have no complementing branches. */
6735 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6737 if (!HAVE_CODE_COMPRESSION
6740 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6741 && delayed_branch_p (ip
))
6743 relaxed_branch
= TRUE
;
6744 add_relaxed_insn (ip
, (relaxed_branch_length
6746 uncond_branch_p (ip
) ? -1
6747 : branch_likely_p (ip
) ? 1
6751 uncond_branch_p (ip
),
6752 branch_likely_p (ip
),
6753 pinfo
& INSN_WRITE_GPR_31
,
6755 address_expr
->X_add_symbol
,
6756 address_expr
->X_add_number
);
6757 *reloc_type
= BFD_RELOC_UNUSED
;
6759 else if (mips_opts
.micromips
6761 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6762 || *reloc_type
> BFD_RELOC_UNUSED
)
6763 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6764 /* Don't try branch relaxation when users specify
6765 16-bit/32-bit instructions. */
6766 && !forced_insn_length
)
6768 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6769 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6770 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6771 int compact
= compact_branch_p (ip
);
6772 int al
= pinfo
& INSN_WRITE_GPR_31
;
6775 gas_assert (address_expr
!= NULL
);
6776 gas_assert (!mips_relax
.sequence
);
6778 relaxed_branch
= TRUE
;
6779 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6780 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6781 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6783 address_expr
->X_add_symbol
,
6784 address_expr
->X_add_number
);
6785 *reloc_type
= BFD_RELOC_UNUSED
;
6787 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6789 /* We need to set up a variant frag. */
6790 gas_assert (address_expr
!= NULL
);
6791 add_relaxed_insn (ip
, 4, 0,
6793 (*reloc_type
- BFD_RELOC_UNUSED
,
6794 forced_insn_length
== 2, forced_insn_length
== 4,
6795 delayed_branch_p (&history
[0]),
6796 history
[0].mips16_absolute_jump_p
),
6797 make_expr_symbol (address_expr
), 0);
6799 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6801 if (!delayed_branch_p (ip
))
6802 /* Make sure there is enough room to swap this instruction with
6803 a following jump instruction. */
6805 add_fixed_insn (ip
);
6809 if (mips_opts
.mips16
6810 && mips_opts
.noreorder
6811 && delayed_branch_p (&history
[0]))
6812 as_warn (_("extended instruction in delay slot"));
6814 if (mips_relax
.sequence
)
6816 /* If we've reached the end of this frag, turn it into a variant
6817 frag and record the information for the instructions we've
6819 if (frag_room () < 4)
6820 relax_close_frag ();
6821 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6824 if (mips_relax
.sequence
!= 2)
6826 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6827 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6828 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6829 mips_macro_warning
.insns
[0]++;
6831 if (mips_relax
.sequence
!= 1)
6833 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6834 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6835 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6836 mips_macro_warning
.insns
[1]++;
6839 if (mips_opts
.mips16
)
6842 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6844 add_fixed_insn (ip
);
6847 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6849 bfd_reloc_code_real_type final_type
[3];
6850 reloc_howto_type
*howto0
;
6851 reloc_howto_type
*howto
;
6854 /* Perform any necessary conversion to microMIPS relocations
6855 and find out how many relocations there actually are. */
6856 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6857 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6859 /* In a compound relocation, it is the final (outermost)
6860 operator that determines the relocated field. */
6861 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6866 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6867 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6868 bfd_get_reloc_size (howto
),
6870 howto0
&& howto0
->pc_relative
,
6873 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6874 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6875 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6877 /* These relocations can have an addend that won't fit in
6878 4 octets for 64bit assembly. */
6880 && ! howto
->partial_inplace
6881 && (reloc_type
[0] == BFD_RELOC_16
6882 || reloc_type
[0] == BFD_RELOC_32
6883 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6884 || reloc_type
[0] == BFD_RELOC_GPREL16
6885 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6886 || reloc_type
[0] == BFD_RELOC_GPREL32
6887 || reloc_type
[0] == BFD_RELOC_64
6888 || reloc_type
[0] == BFD_RELOC_CTOR
6889 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6890 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6891 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6892 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6893 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6894 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6895 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6896 || hi16_reloc_p (reloc_type
[0])
6897 || lo16_reloc_p (reloc_type
[0])))
6898 ip
->fixp
[0]->fx_no_overflow
= 1;
6900 /* These relocations can have an addend that won't fit in 2 octets. */
6901 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6902 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6903 ip
->fixp
[0]->fx_no_overflow
= 1;
6905 if (mips_relax
.sequence
)
6907 if (mips_relax
.first_fixup
== 0)
6908 mips_relax
.first_fixup
= ip
->fixp
[0];
6910 else if (reloc_needs_lo_p (*reloc_type
))
6912 struct mips_hi_fixup
*hi_fixup
;
6914 /* Reuse the last entry if it already has a matching %lo. */
6915 hi_fixup
= mips_hi_fixup_list
;
6917 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6919 hi_fixup
= ((struct mips_hi_fixup
*)
6920 xmalloc (sizeof (struct mips_hi_fixup
)));
6921 hi_fixup
->next
= mips_hi_fixup_list
;
6922 mips_hi_fixup_list
= hi_fixup
;
6924 hi_fixup
->fixp
= ip
->fixp
[0];
6925 hi_fixup
->seg
= now_seg
;
6928 /* Add fixups for the second and third relocations, if given.
6929 Note that the ABI allows the second relocation to be
6930 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6931 moment we only use RSS_UNDEF, but we could add support
6932 for the others if it ever becomes necessary. */
6933 for (i
= 1; i
< 3; i
++)
6934 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6936 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6937 ip
->fixp
[0]->fx_size
, NULL
, 0,
6938 FALSE
, final_type
[i
]);
6940 /* Use fx_tcbit to mark compound relocs. */
6941 ip
->fixp
[0]->fx_tcbit
= 1;
6942 ip
->fixp
[i
]->fx_tcbit
= 1;
6947 /* Update the register mask information. */
6948 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6949 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6954 insert_into_history (0, 1, ip
);
6957 case APPEND_ADD_WITH_NOP
:
6959 struct mips_cl_insn
*nop
;
6961 insert_into_history (0, 1, ip
);
6962 nop
= get_delay_slot_nop (ip
);
6963 add_fixed_insn (nop
);
6964 insert_into_history (0, 1, nop
);
6965 if (mips_relax
.sequence
)
6966 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6970 case APPEND_ADD_COMPACT
:
6971 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6972 gas_assert (mips_opts
.mips16
);
6973 ip
->insn_opcode
|= 0x0080;
6974 find_altered_mips16_opcode (ip
);
6976 insert_into_history (0, 1, ip
);
6981 struct mips_cl_insn delay
= history
[0];
6982 if (mips_opts
.mips16
)
6984 know (delay
.frag
== ip
->frag
);
6985 move_insn (ip
, delay
.frag
, delay
.where
);
6986 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6988 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6990 /* Add the delay slot instruction to the end of the
6991 current frag and shrink the fixed part of the
6992 original frag. If the branch occupies the tail of
6993 the latter, move it backwards to cover the gap. */
6994 delay
.frag
->fr_fix
-= branch_disp
;
6995 if (delay
.frag
== ip
->frag
)
6996 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6997 add_fixed_insn (&delay
);
7001 move_insn (&delay
, ip
->frag
,
7002 ip
->where
- branch_disp
+ insn_length (ip
));
7003 move_insn (ip
, history
[0].frag
, history
[0].where
);
7007 insert_into_history (0, 1, &delay
);
7012 /* If we have just completed an unconditional branch, clear the history. */
7013 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7014 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7018 mips_no_prev_insn ();
7020 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7021 history
[i
].cleared_p
= 1;
7024 /* We need to emit a label at the end of branch-likely macros. */
7025 if (emit_branch_likely_macro
)
7027 emit_branch_likely_macro
= FALSE
;
7028 micromips_add_label ();
7031 /* We just output an insn, so the next one doesn't have a label. */
7032 mips_clear_insn_labels ();
7035 /* Forget that there was any previous instruction or label.
7036 When BRANCH is true, the branch history is also flushed. */
7039 mips_no_prev_insn (void)
7041 prev_nop_frag
= NULL
;
7042 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7043 mips_clear_insn_labels ();
7046 /* This function must be called before we emit something other than
7047 instructions. It is like mips_no_prev_insn except that it inserts
7048 any NOPS that might be needed by previous instructions. */
7051 mips_emit_delays (void)
7053 if (! mips_opts
.noreorder
)
7055 int nops
= nops_for_insn (0, history
, NULL
);
7059 add_fixed_insn (NOP_INSN
);
7060 mips_move_text_labels ();
7063 mips_no_prev_insn ();
7066 /* Start a (possibly nested) noreorder block. */
7069 start_noreorder (void)
7071 if (mips_opts
.noreorder
== 0)
7076 /* None of the instructions before the .set noreorder can be moved. */
7077 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7078 history
[i
].fixed_p
= 1;
7080 /* Insert any nops that might be needed between the .set noreorder
7081 block and the previous instructions. We will later remove any
7082 nops that turn out not to be needed. */
7083 nops
= nops_for_insn (0, history
, NULL
);
7086 if (mips_optimize
!= 0)
7088 /* Record the frag which holds the nop instructions, so
7089 that we can remove them if we don't need them. */
7090 frag_grow (nops
* NOP_INSN_SIZE
);
7091 prev_nop_frag
= frag_now
;
7092 prev_nop_frag_holds
= nops
;
7093 prev_nop_frag_required
= 0;
7094 prev_nop_frag_since
= 0;
7097 for (; nops
> 0; --nops
)
7098 add_fixed_insn (NOP_INSN
);
7100 /* Move on to a new frag, so that it is safe to simply
7101 decrease the size of prev_nop_frag. */
7102 frag_wane (frag_now
);
7104 mips_move_text_labels ();
7106 mips_mark_labels ();
7107 mips_clear_insn_labels ();
7109 mips_opts
.noreorder
++;
7110 mips_any_noreorder
= 1;
7113 /* End a nested noreorder block. */
7116 end_noreorder (void)
7118 mips_opts
.noreorder
--;
7119 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7121 /* Commit to inserting prev_nop_frag_required nops and go back to
7122 handling nop insertion the .set reorder way. */
7123 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7125 insert_into_history (prev_nop_frag_since
,
7126 prev_nop_frag_required
, NOP_INSN
);
7127 prev_nop_frag
= NULL
;
7131 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7132 higher bits unset. */
7135 normalize_constant_expr (expressionS
*ex
)
7137 if (ex
->X_op
== O_constant
7138 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7139 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7143 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7144 all higher bits unset. */
7147 normalize_address_expr (expressionS
*ex
)
7149 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7150 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7151 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7152 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7156 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7157 Return true if the match was successful.
7159 OPCODE_EXTRA is a value that should be ORed into the opcode
7160 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7161 there are more alternatives after OPCODE and SOFT_MATCH is
7162 as for mips_arg_info. */
7165 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7166 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7167 bfd_boolean lax_match
, bfd_boolean complete_p
)
7170 struct mips_arg_info arg
;
7171 const struct mips_operand
*operand
;
7174 imm_expr
.X_op
= O_absent
;
7175 offset_expr
.X_op
= O_absent
;
7176 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7177 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7178 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7180 create_insn (insn
, opcode
);
7181 /* When no opcode suffix is specified, assume ".xyzw". */
7182 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7183 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7185 insn
->insn_opcode
|= opcode_extra
;
7186 memset (&arg
, 0, sizeof (arg
));
7190 arg
.last_regno
= ILLEGAL_REG
;
7191 arg
.dest_regno
= ILLEGAL_REG
;
7192 arg
.lax_match
= lax_match
;
7193 for (args
= opcode
->args
;; ++args
)
7195 if (arg
.token
->type
== OT_END
)
7197 /* Handle unary instructions in which only one operand is given.
7198 The source is then the same as the destination. */
7199 if (arg
.opnum
== 1 && *args
== ',')
7201 operand
= (mips_opts
.micromips
7202 ? decode_micromips_operand (args
+ 1)
7203 : decode_mips_operand (args
+ 1));
7204 if (operand
&& mips_optional_operand_p (operand
))
7212 /* Treat elided base registers as $0. */
7213 if (strcmp (args
, "(b)") == 0)
7221 /* The register suffix is optional. */
7226 /* Fail the match if there were too few operands. */
7230 /* Successful match. */
7233 clear_insn_error ();
7234 if (arg
.dest_regno
== arg
.last_regno
7235 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7239 (0, _("source and destination must be different"));
7240 else if (arg
.last_regno
== 31)
7242 (0, _("a destination register must be supplied"));
7244 else if (arg
.last_regno
== 31
7245 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7246 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7247 set_insn_error (0, _("the source register must not be $31"));
7248 check_completed_insn (&arg
);
7252 /* Fail the match if the line has too many operands. */
7256 /* Handle characters that need to match exactly. */
7257 if (*args
== '(' || *args
== ')' || *args
== ',')
7259 if (match_char (&arg
, *args
))
7266 if (arg
.token
->type
== OT_DOUBLE_CHAR
7267 && arg
.token
->u
.ch
== *args
)
7275 /* Handle special macro operands. Work out the properties of
7284 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7290 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7292 imm_expr
.X_op
= O_constant
;
7293 if (HAVE_32BIT_GPRS
)
7294 normalize_constant_expr (&imm_expr
);
7298 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7300 /* Assume that the offset has been elided and that what
7301 we saw was a base register. The match will fail later
7302 if that assumption turns out to be wrong. */
7303 offset_expr
.X_op
= O_constant
;
7304 offset_expr
.X_add_number
= 0;
7308 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7310 normalize_address_expr (&offset_expr
);
7315 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7321 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7327 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7333 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7339 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7343 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7347 gas_assert (mips_opts
.micromips
);
7353 if (!forced_insn_length
)
7354 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7356 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7358 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7364 operand
= (mips_opts
.micromips
7365 ? decode_micromips_operand (args
)
7366 : decode_mips_operand (args
));
7370 /* Skip prefixes. */
7371 if (*args
== '+' || *args
== 'm')
7374 if (mips_optional_operand_p (operand
)
7376 && (arg
.token
[0].type
!= OT_REG
7377 || arg
.token
[1].type
== OT_END
))
7379 /* Assume that the register has been elided and is the
7380 same as the first operand. */
7385 if (!match_operand (&arg
, operand
))
7390 /* Like match_insn, but for MIPS16. */
7393 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7394 struct mips_operand_token
*tokens
)
7397 const struct mips_operand
*operand
;
7398 const struct mips_operand
*ext_operand
;
7399 struct mips_arg_info arg
;
7402 create_insn (insn
, opcode
);
7403 imm_expr
.X_op
= O_absent
;
7404 offset_expr
.X_op
= O_absent
;
7405 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7406 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7407 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7410 memset (&arg
, 0, sizeof (arg
));
7414 arg
.last_regno
= ILLEGAL_REG
;
7415 arg
.dest_regno
= ILLEGAL_REG
;
7417 for (args
= opcode
->args
;; ++args
)
7421 if (arg
.token
->type
== OT_END
)
7425 /* Handle unary instructions in which only one operand is given.
7426 The source is then the same as the destination. */
7427 if (arg
.opnum
== 1 && *args
== ',')
7429 operand
= decode_mips16_operand (args
[1], FALSE
);
7430 if (operand
&& mips_optional_operand_p (operand
))
7438 /* Fail the match if there were too few operands. */
7442 /* Successful match. Stuff the immediate value in now, if
7444 clear_insn_error ();
7445 if (opcode
->pinfo
== INSN_MACRO
)
7447 gas_assert (relax_char
== 0 || relax_char
== 'p');
7448 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7451 && offset_expr
.X_op
== O_constant
7452 && calculate_reloc (*offset_reloc
,
7453 offset_expr
.X_add_number
,
7456 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7457 forced_insn_length
, &insn
->insn_opcode
);
7458 offset_expr
.X_op
= O_absent
;
7459 *offset_reloc
= BFD_RELOC_UNUSED
;
7461 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7463 if (forced_insn_length
== 2)
7464 set_insn_error (0, _("invalid unextended operand value"));
7465 forced_insn_length
= 4;
7466 insn
->insn_opcode
|= MIPS16_EXTEND
;
7468 else if (relax_char
)
7469 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7471 check_completed_insn (&arg
);
7475 /* Fail the match if the line has too many operands. */
7479 /* Handle characters that need to match exactly. */
7480 if (*args
== '(' || *args
== ')' || *args
== ',')
7482 if (match_char (&arg
, *args
))
7500 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7502 imm_expr
.X_op
= O_constant
;
7503 if (HAVE_32BIT_GPRS
)
7504 normalize_constant_expr (&imm_expr
);
7509 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7510 insn
->insn_opcode
<<= 16;
7514 operand
= decode_mips16_operand (c
, FALSE
);
7518 /* '6' is a special case. It is used for BREAK and SDBBP,
7519 whose operands are only meaningful to the software that decodes
7520 them. This means that there is no architectural reason why
7521 they cannot be prefixed by EXTEND, but in practice,
7522 exception handlers will only look at the instruction
7523 itself. We therefore allow '6' to be extended when
7524 disassembling but not when assembling. */
7525 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7527 ext_operand
= decode_mips16_operand (c
, TRUE
);
7528 if (operand
!= ext_operand
)
7530 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7532 offset_expr
.X_op
= O_constant
;
7533 offset_expr
.X_add_number
= 0;
7538 /* We need the OT_INTEGER check because some MIPS16
7539 immediate variants are listed before the register ones. */
7540 if (arg
.token
->type
!= OT_INTEGER
7541 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7544 /* '8' is used for SLTI(U) and has traditionally not
7545 been allowed to take relocation operators. */
7546 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7547 && (ext_operand
->size
!= 16 || c
== '8'))
7555 if (mips_optional_operand_p (operand
)
7557 && (arg
.token
[0].type
!= OT_REG
7558 || arg
.token
[1].type
== OT_END
))
7560 /* Assume that the register has been elided and is the
7561 same as the first operand. */
7566 if (!match_operand (&arg
, operand
))
7571 /* Record that the current instruction is invalid for the current ISA. */
7574 match_invalid_for_isa (void)
7577 (0, _("opcode not supported on this processor: %s (%s)"),
7578 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7579 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7582 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7583 Return true if a definite match or failure was found, storing any match
7584 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7585 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7586 tried and failed to match under normal conditions and now want to try a
7587 more relaxed match. */
7590 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7591 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
7592 int opcode_extra
, bfd_boolean lax_match
)
7594 const struct mips_opcode
*opcode
;
7595 const struct mips_opcode
*invalid_delay_slot
;
7596 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
7598 /* Search for a match, ignoring alternatives that don't satisfy the
7599 current ISA or forced_length. */
7600 invalid_delay_slot
= 0;
7601 seen_valid_for_isa
= FALSE
;
7602 seen_valid_for_size
= FALSE
;
7606 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7607 if (is_opcode_valid (opcode
))
7609 seen_valid_for_isa
= TRUE
;
7610 if (is_size_valid (opcode
))
7612 bfd_boolean delay_slot_ok
;
7614 seen_valid_for_size
= TRUE
;
7615 delay_slot_ok
= is_delay_slot_valid (opcode
);
7616 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
7617 lax_match
, delay_slot_ok
))
7621 if (!invalid_delay_slot
)
7622 invalid_delay_slot
= opcode
;
7631 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
7633 /* If the only matches we found had the wrong length for the delay slot,
7634 pick the first such match. We'll issue an appropriate warning later. */
7635 if (invalid_delay_slot
)
7637 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
7643 /* Handle the case where we didn't try to match an instruction because
7644 all the alternatives were incompatible with the current ISA. */
7645 if (!seen_valid_for_isa
)
7647 match_invalid_for_isa ();
7651 /* Handle the case where we didn't try to match an instruction because
7652 all the alternatives were of the wrong size. */
7653 if (!seen_valid_for_size
)
7655 if (mips_opts
.insn32
)
7656 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
7659 (0, _("unrecognized %d-bit version of microMIPS opcode"),
7660 8 * forced_insn_length
);
7667 /* Like match_insns, but for MIPS16. */
7670 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7671 struct mips_operand_token
*tokens
)
7673 const struct mips_opcode
*opcode
;
7674 bfd_boolean seen_valid_for_isa
;
7676 /* Search for a match, ignoring alternatives that don't satisfy the
7677 current ISA. There are no separate entries for extended forms so
7678 we deal with forced_length later. */
7679 seen_valid_for_isa
= FALSE
;
7683 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7684 if (is_opcode_valid_16 (opcode
))
7686 seen_valid_for_isa
= TRUE
;
7687 if (match_mips16_insn (insn
, opcode
, tokens
))
7692 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
7693 && strcmp (opcode
->name
, first
->name
) == 0);
7695 /* Handle the case where we didn't try to match an instruction because
7696 all the alternatives were incompatible with the current ISA. */
7697 if (!seen_valid_for_isa
)
7699 match_invalid_for_isa ();
7706 /* Set up global variables for the start of a new macro. */
7711 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7712 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7713 sizeof (mips_macro_warning
.first_insn_sizes
));
7714 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7715 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7716 && delayed_branch_p (&history
[0]));
7717 switch (history
[0].insn_mo
->pinfo2
7718 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7720 case INSN2_BRANCH_DELAY_32BIT
:
7721 mips_macro_warning
.delay_slot_length
= 4;
7723 case INSN2_BRANCH_DELAY_16BIT
:
7724 mips_macro_warning
.delay_slot_length
= 2;
7727 mips_macro_warning
.delay_slot_length
= 0;
7730 mips_macro_warning
.first_frag
= NULL
;
7733 /* Given that a macro is longer than one instruction or of the wrong size,
7734 return the appropriate warning for it. Return null if no warning is
7735 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7736 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7737 and RELAX_NOMACRO. */
7740 macro_warning (relax_substateT subtype
)
7742 if (subtype
& RELAX_DELAY_SLOT
)
7743 return _("macro instruction expanded into multiple instructions"
7744 " in a branch delay slot");
7745 else if (subtype
& RELAX_NOMACRO
)
7746 return _("macro instruction expanded into multiple instructions");
7747 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7748 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7749 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7750 ? _("macro instruction expanded into a wrong size instruction"
7751 " in a 16-bit branch delay slot")
7752 : _("macro instruction expanded into a wrong size instruction"
7753 " in a 32-bit branch delay slot"));
7758 /* Finish up a macro. Emit warnings as appropriate. */
7763 /* Relaxation warning flags. */
7764 relax_substateT subtype
= 0;
7766 /* Check delay slot size requirements. */
7767 if (mips_macro_warning
.delay_slot_length
== 2)
7768 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7769 if (mips_macro_warning
.delay_slot_length
!= 0)
7771 if (mips_macro_warning
.delay_slot_length
7772 != mips_macro_warning
.first_insn_sizes
[0])
7773 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7774 if (mips_macro_warning
.delay_slot_length
7775 != mips_macro_warning
.first_insn_sizes
[1])
7776 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7779 /* Check instruction count requirements. */
7780 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7782 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7783 subtype
|= RELAX_SECOND_LONGER
;
7784 if (mips_opts
.warn_about_macros
)
7785 subtype
|= RELAX_NOMACRO
;
7786 if (mips_macro_warning
.delay_slot_p
)
7787 subtype
|= RELAX_DELAY_SLOT
;
7790 /* If both alternatives fail to fill a delay slot correctly,
7791 emit the warning now. */
7792 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7793 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7798 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7799 | RELAX_DELAY_SLOT_SIZE_FIRST
7800 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7801 msg
= macro_warning (s
);
7803 as_warn ("%s", msg
);
7807 /* If both implementations are longer than 1 instruction, then emit the
7809 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7814 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7815 msg
= macro_warning (s
);
7817 as_warn ("%s", msg
);
7821 /* If any flags still set, then one implementation might need a warning
7822 and the other either will need one of a different kind or none at all.
7823 Pass any remaining flags over to relaxation. */
7824 if (mips_macro_warning
.first_frag
!= NULL
)
7825 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7828 /* Instruction operand formats used in macros that vary between
7829 standard MIPS and microMIPS code. */
7831 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7832 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7833 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7834 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7835 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7836 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7837 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7838 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7840 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7841 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7842 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7843 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7844 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7845 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7846 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7847 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7849 /* Read a macro's relocation codes from *ARGS and store them in *R.
7850 The first argument in *ARGS will be either the code for a single
7851 relocation or -1 followed by the three codes that make up a
7852 composite relocation. */
7855 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7859 next
= va_arg (*args
, int);
7861 r
[0] = (bfd_reloc_code_real_type
) next
;
7864 for (i
= 0; i
< 3; i
++)
7865 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7866 /* This function is only used for 16-bit relocation fields.
7867 To make the macro code simpler, treat an unrelocated value
7868 in the same way as BFD_RELOC_LO16. */
7869 if (r
[0] == BFD_RELOC_UNUSED
)
7870 r
[0] = BFD_RELOC_LO16
;
7874 /* Build an instruction created by a macro expansion. This is passed
7875 a pointer to the count of instructions created so far, an
7876 expression, the name of the instruction to build, an operand format
7877 string, and corresponding arguments. */
7880 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7882 const struct mips_opcode
*mo
= NULL
;
7883 bfd_reloc_code_real_type r
[3];
7884 const struct mips_opcode
*amo
;
7885 const struct mips_operand
*operand
;
7886 struct hash_control
*hash
;
7887 struct mips_cl_insn insn
;
7891 va_start (args
, fmt
);
7893 if (mips_opts
.mips16
)
7895 mips16_macro_build (ep
, name
, fmt
, &args
);
7900 r
[0] = BFD_RELOC_UNUSED
;
7901 r
[1] = BFD_RELOC_UNUSED
;
7902 r
[2] = BFD_RELOC_UNUSED
;
7903 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7904 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7906 gas_assert (strcmp (name
, amo
->name
) == 0);
7910 /* Search until we get a match for NAME. It is assumed here that
7911 macros will never generate MDMX, MIPS-3D, or MT instructions.
7912 We try to match an instruction that fulfils the branch delay
7913 slot instruction length requirement (if any) of the previous
7914 instruction. While doing this we record the first instruction
7915 seen that matches all the other conditions and use it anyway
7916 if the requirement cannot be met; we will issue an appropriate
7917 warning later on. */
7918 if (strcmp (fmt
, amo
->args
) == 0
7919 && amo
->pinfo
!= INSN_MACRO
7920 && is_opcode_valid (amo
)
7921 && is_size_valid (amo
))
7923 if (is_delay_slot_valid (amo
))
7933 gas_assert (amo
->name
);
7935 while (strcmp (name
, amo
->name
) == 0);
7938 create_insn (&insn
, mo
);
7951 macro_read_relocs (&args
, r
);
7952 gas_assert (*r
== BFD_RELOC_GPREL16
7953 || *r
== BFD_RELOC_MIPS_HIGHER
7954 || *r
== BFD_RELOC_HI16_S
7955 || *r
== BFD_RELOC_LO16
7956 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7960 macro_read_relocs (&args
, r
);
7964 macro_read_relocs (&args
, r
);
7965 gas_assert (ep
!= NULL
7966 && (ep
->X_op
== O_constant
7967 || (ep
->X_op
== O_symbol
7968 && (*r
== BFD_RELOC_MIPS_HIGHEST
7969 || *r
== BFD_RELOC_HI16_S
7970 || *r
== BFD_RELOC_HI16
7971 || *r
== BFD_RELOC_GPREL16
7972 || *r
== BFD_RELOC_MIPS_GOT_HI16
7973 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7977 gas_assert (ep
!= NULL
);
7980 * This allows macro() to pass an immediate expression for
7981 * creating short branches without creating a symbol.
7983 * We don't allow branch relaxation for these branches, as
7984 * they should only appear in ".set nomacro" anyway.
7986 if (ep
->X_op
== O_constant
)
7988 /* For microMIPS we always use relocations for branches.
7989 So we should not resolve immediate values. */
7990 gas_assert (!mips_opts
.micromips
);
7992 if ((ep
->X_add_number
& 3) != 0)
7993 as_bad (_("branch to misaligned address (0x%lx)"),
7994 (unsigned long) ep
->X_add_number
);
7995 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7996 as_bad (_("branch address range overflow (0x%lx)"),
7997 (unsigned long) ep
->X_add_number
);
7998 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8002 *r
= BFD_RELOC_16_PCREL_S2
;
8006 gas_assert (ep
!= NULL
);
8007 *r
= BFD_RELOC_MIPS_JMP
;
8011 operand
= (mips_opts
.micromips
8012 ? decode_micromips_operand (fmt
)
8013 : decode_mips_operand (fmt
));
8017 uval
= va_arg (args
, int);
8018 if (operand
->type
== OP_CLO_CLZ_DEST
)
8019 uval
|= (uval
<< 5);
8020 insn_insert_operand (&insn
, operand
, uval
);
8022 if (*fmt
== '+' || *fmt
== 'm')
8028 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8030 append_insn (&insn
, ep
, r
, TRUE
);
8034 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8037 struct mips_opcode
*mo
;
8038 struct mips_cl_insn insn
;
8039 const struct mips_operand
*operand
;
8040 bfd_reloc_code_real_type r
[3]
8041 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8043 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8045 gas_assert (strcmp (name
, mo
->name
) == 0);
8047 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8050 gas_assert (mo
->name
);
8051 gas_assert (strcmp (name
, mo
->name
) == 0);
8054 create_insn (&insn
, mo
);
8092 gas_assert (ep
!= NULL
);
8094 if (ep
->X_op
!= O_constant
)
8095 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8096 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8098 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8100 *r
= BFD_RELOC_UNUSED
;
8106 operand
= decode_mips16_operand (c
, FALSE
);
8110 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8115 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8117 append_insn (&insn
, ep
, r
, TRUE
);
8121 * Generate a "jalr" instruction with a relocation hint to the called
8122 * function. This occurs in NewABI PIC code.
8125 macro_build_jalr (expressionS
*ep
, int cprestore
)
8127 static const bfd_reloc_code_real_type jalr_relocs
[2]
8128 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8129 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8133 if (MIPS_JALR_HINT_P (ep
))
8138 if (mips_opts
.micromips
)
8140 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8141 ? "jalr" : "jalrs");
8142 if (MIPS_JALR_HINT_P (ep
)
8144 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8145 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8147 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8150 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8151 if (MIPS_JALR_HINT_P (ep
))
8152 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8156 * Generate a "lui" instruction.
8159 macro_build_lui (expressionS
*ep
, int regnum
)
8161 gas_assert (! mips_opts
.mips16
);
8163 if (ep
->X_op
!= O_constant
)
8165 gas_assert (ep
->X_op
== O_symbol
);
8166 /* _gp_disp is a special case, used from s_cpload.
8167 __gnu_local_gp is used if mips_no_shared. */
8168 gas_assert (mips_pic
== NO_PIC
8170 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8171 || (! mips_in_shared
8172 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8173 "__gnu_local_gp") == 0));
8176 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8179 /* Generate a sequence of instructions to do a load or store from a constant
8180 offset off of a base register (breg) into/from a target register (treg),
8181 using AT if necessary. */
8183 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8184 int treg
, int breg
, int dbl
)
8186 gas_assert (ep
->X_op
== O_constant
);
8188 /* Sign-extending 32-bit constants makes their handling easier. */
8190 normalize_constant_expr (ep
);
8192 /* Right now, this routine can only handle signed 32-bit constants. */
8193 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8194 as_warn (_("operand overflow"));
8196 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8198 /* Signed 16-bit offset will fit in the op. Easy! */
8199 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8203 /* 32-bit offset, need multiple instructions and AT, like:
8204 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8205 addu $tempreg,$tempreg,$breg
8206 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8207 to handle the complete offset. */
8208 macro_build_lui (ep
, AT
);
8209 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8210 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8213 as_bad (_("macro used $at after \".set noat\""));
8218 * Generates code to set the $at register to true (one)
8219 * if reg is less than the immediate expression.
8222 set_at (int reg
, int unsignedp
)
8224 if (imm_expr
.X_add_number
>= -0x8000
8225 && imm_expr
.X_add_number
< 0x8000)
8226 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8227 AT
, reg
, BFD_RELOC_LO16
);
8230 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8231 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8235 /* Count the leading zeroes by performing a binary chop. This is a
8236 bulky bit of source, but performance is a LOT better for the
8237 majority of values than a simple loop to count the bits:
8238 for (lcnt = 0; (lcnt < 32); lcnt++)
8239 if ((v) & (1 << (31 - lcnt)))
8241 However it is not code size friendly, and the gain will drop a bit
8242 on certain cached systems.
8244 #define COUNT_TOP_ZEROES(v) \
8245 (((v) & ~0xffff) == 0 \
8246 ? ((v) & ~0xff) == 0 \
8247 ? ((v) & ~0xf) == 0 \
8248 ? ((v) & ~0x3) == 0 \
8249 ? ((v) & ~0x1) == 0 \
8254 : ((v) & ~0x7) == 0 \
8257 : ((v) & ~0x3f) == 0 \
8258 ? ((v) & ~0x1f) == 0 \
8261 : ((v) & ~0x7f) == 0 \
8264 : ((v) & ~0xfff) == 0 \
8265 ? ((v) & ~0x3ff) == 0 \
8266 ? ((v) & ~0x1ff) == 0 \
8269 : ((v) & ~0x7ff) == 0 \
8272 : ((v) & ~0x3fff) == 0 \
8273 ? ((v) & ~0x1fff) == 0 \
8276 : ((v) & ~0x7fff) == 0 \
8279 : ((v) & ~0xffffff) == 0 \
8280 ? ((v) & ~0xfffff) == 0 \
8281 ? ((v) & ~0x3ffff) == 0 \
8282 ? ((v) & ~0x1ffff) == 0 \
8285 : ((v) & ~0x7ffff) == 0 \
8288 : ((v) & ~0x3fffff) == 0 \
8289 ? ((v) & ~0x1fffff) == 0 \
8292 : ((v) & ~0x7fffff) == 0 \
8295 : ((v) & ~0xfffffff) == 0 \
8296 ? ((v) & ~0x3ffffff) == 0 \
8297 ? ((v) & ~0x1ffffff) == 0 \
8300 : ((v) & ~0x7ffffff) == 0 \
8303 : ((v) & ~0x3fffffff) == 0 \
8304 ? ((v) & ~0x1fffffff) == 0 \
8307 : ((v) & ~0x7fffffff) == 0 \
8312 * This routine generates the least number of instructions necessary to load
8313 * an absolute expression value into a register.
8316 load_register (int reg
, expressionS
*ep
, int dbl
)
8319 expressionS hi32
, lo32
;
8321 if (ep
->X_op
!= O_big
)
8323 gas_assert (ep
->X_op
== O_constant
);
8325 /* Sign-extending 32-bit constants makes their handling easier. */
8327 normalize_constant_expr (ep
);
8329 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8331 /* We can handle 16 bit signed values with an addiu to
8332 $zero. No need to ever use daddiu here, since $zero and
8333 the result are always correct in 32 bit mode. */
8334 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8337 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8339 /* We can handle 16 bit unsigned values with an ori to
8341 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8344 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8346 /* 32 bit values require an lui. */
8347 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8348 if ((ep
->X_add_number
& 0xffff) != 0)
8349 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8354 /* The value is larger than 32 bits. */
8356 if (!dbl
|| HAVE_32BIT_GPRS
)
8360 sprintf_vma (value
, ep
->X_add_number
);
8361 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8362 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8366 if (ep
->X_op
!= O_big
)
8369 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8370 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8371 hi32
.X_add_number
&= 0xffffffff;
8373 lo32
.X_add_number
&= 0xffffffff;
8377 gas_assert (ep
->X_add_number
> 2);
8378 if (ep
->X_add_number
== 3)
8379 generic_bignum
[3] = 0;
8380 else if (ep
->X_add_number
> 4)
8381 as_bad (_("number larger than 64 bits"));
8382 lo32
.X_op
= O_constant
;
8383 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8384 hi32
.X_op
= O_constant
;
8385 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8388 if (hi32
.X_add_number
== 0)
8393 unsigned long hi
, lo
;
8395 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8397 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8399 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8402 if (lo32
.X_add_number
& 0x80000000)
8404 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8405 if (lo32
.X_add_number
& 0xffff)
8406 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8411 /* Check for 16bit shifted constant. We know that hi32 is
8412 non-zero, so start the mask on the first bit of the hi32
8417 unsigned long himask
, lomask
;
8421 himask
= 0xffff >> (32 - shift
);
8422 lomask
= (0xffff << shift
) & 0xffffffff;
8426 himask
= 0xffff << (shift
- 32);
8429 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8430 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8434 tmp
.X_op
= O_constant
;
8436 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8437 | (lo32
.X_add_number
>> shift
));
8439 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8440 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8441 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8442 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8447 while (shift
<= (64 - 16));
8449 /* Find the bit number of the lowest one bit, and store the
8450 shifted value in hi/lo. */
8451 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8452 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8456 while ((lo
& 1) == 0)
8461 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8467 while ((hi
& 1) == 0)
8476 /* Optimize if the shifted value is a (power of 2) - 1. */
8477 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8478 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8480 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8485 /* This instruction will set the register to be all
8487 tmp
.X_op
= O_constant
;
8488 tmp
.X_add_number
= (offsetT
) -1;
8489 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8493 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8494 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8496 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8497 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8502 /* Sign extend hi32 before calling load_register, because we can
8503 generally get better code when we load a sign extended value. */
8504 if ((hi32
.X_add_number
& 0x80000000) != 0)
8505 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8506 load_register (reg
, &hi32
, 0);
8509 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8513 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8521 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8523 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8524 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8530 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8534 mid16
.X_add_number
>>= 16;
8535 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8536 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8539 if ((lo32
.X_add_number
& 0xffff) != 0)
8540 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8544 load_delay_nop (void)
8546 if (!gpr_interlocks
)
8547 macro_build (NULL
, "nop", "");
8550 /* Load an address into a register. */
8553 load_address (int reg
, expressionS
*ep
, int *used_at
)
8555 if (ep
->X_op
!= O_constant
8556 && ep
->X_op
!= O_symbol
)
8558 as_bad (_("expression too complex"));
8559 ep
->X_op
= O_constant
;
8562 if (ep
->X_op
== O_constant
)
8564 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8568 if (mips_pic
== NO_PIC
)
8570 /* If this is a reference to a GP relative symbol, we want
8571 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8573 lui $reg,<sym> (BFD_RELOC_HI16_S)
8574 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8575 If we have an addend, we always use the latter form.
8577 With 64bit address space and a usable $at we want
8578 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8579 lui $at,<sym> (BFD_RELOC_HI16_S)
8580 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8581 daddiu $at,<sym> (BFD_RELOC_LO16)
8585 If $at is already in use, we use a path which is suboptimal
8586 on superscalar processors.
8587 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8588 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8590 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8592 daddiu $reg,<sym> (BFD_RELOC_LO16)
8594 For GP relative symbols in 64bit address space we can use
8595 the same sequence as in 32bit address space. */
8596 if (HAVE_64BIT_SYMBOLS
)
8598 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8599 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8601 relax_start (ep
->X_add_symbol
);
8602 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8603 mips_gp_register
, BFD_RELOC_GPREL16
);
8607 if (*used_at
== 0 && mips_opts
.at
)
8609 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8610 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8611 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8612 BFD_RELOC_MIPS_HIGHER
);
8613 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8614 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8615 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8620 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8621 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8622 BFD_RELOC_MIPS_HIGHER
);
8623 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8624 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8625 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8626 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8629 if (mips_relax
.sequence
)
8634 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8635 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8637 relax_start (ep
->X_add_symbol
);
8638 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8639 mips_gp_register
, BFD_RELOC_GPREL16
);
8642 macro_build_lui (ep
, reg
);
8643 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8644 reg
, reg
, BFD_RELOC_LO16
);
8645 if (mips_relax
.sequence
)
8649 else if (!mips_big_got
)
8653 /* If this is a reference to an external symbol, we want
8654 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8656 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8658 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8659 If there is a constant, it must be added in after.
8661 If we have NewABI, we want
8662 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8663 unless we're referencing a global symbol with a non-zero
8664 offset, in which case cst must be added separately. */
8667 if (ep
->X_add_number
)
8669 ex
.X_add_number
= ep
->X_add_number
;
8670 ep
->X_add_number
= 0;
8671 relax_start (ep
->X_add_symbol
);
8672 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8673 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8674 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8675 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8676 ex
.X_op
= O_constant
;
8677 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8678 reg
, reg
, BFD_RELOC_LO16
);
8679 ep
->X_add_number
= ex
.X_add_number
;
8682 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8683 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8684 if (mips_relax
.sequence
)
8689 ex
.X_add_number
= ep
->X_add_number
;
8690 ep
->X_add_number
= 0;
8691 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8692 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8694 relax_start (ep
->X_add_symbol
);
8696 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8700 if (ex
.X_add_number
!= 0)
8702 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8703 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8704 ex
.X_op
= O_constant
;
8705 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8706 reg
, reg
, BFD_RELOC_LO16
);
8710 else if (mips_big_got
)
8714 /* This is the large GOT case. If this is a reference to an
8715 external symbol, we want
8716 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8718 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8720 Otherwise, for a reference to a local symbol in old ABI, we want
8721 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8723 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8724 If there is a constant, it must be added in after.
8726 In the NewABI, for local symbols, with or without offsets, we want:
8727 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8728 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8732 ex
.X_add_number
= ep
->X_add_number
;
8733 ep
->X_add_number
= 0;
8734 relax_start (ep
->X_add_symbol
);
8735 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8736 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8737 reg
, reg
, mips_gp_register
);
8738 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8739 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8740 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8741 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8742 else if (ex
.X_add_number
)
8744 ex
.X_op
= O_constant
;
8745 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8749 ep
->X_add_number
= ex
.X_add_number
;
8751 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8752 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8753 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8754 BFD_RELOC_MIPS_GOT_OFST
);
8759 ex
.X_add_number
= ep
->X_add_number
;
8760 ep
->X_add_number
= 0;
8761 relax_start (ep
->X_add_symbol
);
8762 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8763 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8764 reg
, reg
, mips_gp_register
);
8765 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8766 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8768 if (reg_needs_delay (mips_gp_register
))
8770 /* We need a nop before loading from $gp. This special
8771 check is required because the lui which starts the main
8772 instruction stream does not refer to $gp, and so will not
8773 insert the nop which may be required. */
8774 macro_build (NULL
, "nop", "");
8776 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8777 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8779 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8783 if (ex
.X_add_number
!= 0)
8785 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8786 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8787 ex
.X_op
= O_constant
;
8788 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8796 if (!mips_opts
.at
&& *used_at
== 1)
8797 as_bad (_("macro used $at after \".set noat\""));
8800 /* Move the contents of register SOURCE into register DEST. */
8803 move_register (int dest
, int source
)
8805 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8806 instruction specifically requires a 32-bit one. */
8807 if (mips_opts
.micromips
8808 && !mips_opts
.insn32
8809 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8810 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8812 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8816 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8817 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8818 The two alternatives are:
8820 Global symbol Local sybmol
8821 ------------- ------------
8822 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8824 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8826 load_got_offset emits the first instruction and add_got_offset
8827 emits the second for a 16-bit offset or add_got_offset_hilo emits
8828 a sequence to add a 32-bit offset using a scratch register. */
8831 load_got_offset (int dest
, expressionS
*local
)
8836 global
.X_add_number
= 0;
8838 relax_start (local
->X_add_symbol
);
8839 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8840 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8842 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8843 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8848 add_got_offset (int dest
, expressionS
*local
)
8852 global
.X_op
= O_constant
;
8853 global
.X_op_symbol
= NULL
;
8854 global
.X_add_symbol
= NULL
;
8855 global
.X_add_number
= local
->X_add_number
;
8857 relax_start (local
->X_add_symbol
);
8858 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8859 dest
, dest
, BFD_RELOC_LO16
);
8861 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8866 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8869 int hold_mips_optimize
;
8871 global
.X_op
= O_constant
;
8872 global
.X_op_symbol
= NULL
;
8873 global
.X_add_symbol
= NULL
;
8874 global
.X_add_number
= local
->X_add_number
;
8876 relax_start (local
->X_add_symbol
);
8877 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8879 /* Set mips_optimize around the lui instruction to avoid
8880 inserting an unnecessary nop after the lw. */
8881 hold_mips_optimize
= mips_optimize
;
8883 macro_build_lui (&global
, tmp
);
8884 mips_optimize
= hold_mips_optimize
;
8885 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8888 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8891 /* Emit a sequence of instructions to emulate a branch likely operation.
8892 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8893 is its complementing branch with the original condition negated.
8894 CALL is set if the original branch specified the link operation.
8895 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8897 Code like this is produced in the noreorder mode:
8902 delay slot (executed only if branch taken)
8910 delay slot (executed only if branch taken)
8913 In the reorder mode the delay slot would be filled with a nop anyway,
8914 so code produced is simply:
8919 This function is used when producing code for the microMIPS ASE that
8920 does not implement branch likely instructions in hardware. */
8923 macro_build_branch_likely (const char *br
, const char *brneg
,
8924 int call
, expressionS
*ep
, const char *fmt
,
8925 unsigned int sreg
, unsigned int treg
)
8927 int noreorder
= mips_opts
.noreorder
;
8930 gas_assert (mips_opts
.micromips
);
8934 micromips_label_expr (&expr1
);
8935 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8936 macro_build (NULL
, "nop", "");
8937 macro_build (ep
, call
? "bal" : "b", "p");
8939 /* Set to true so that append_insn adds a label. */
8940 emit_branch_likely_macro
= TRUE
;
8944 macro_build (ep
, br
, fmt
, sreg
, treg
);
8945 macro_build (NULL
, "nop", "");
8950 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8951 the condition code tested. EP specifies the branch target. */
8954 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8981 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8984 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8985 the register tested. EP specifies the branch target. */
8988 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8990 const char *brneg
= NULL
;
9000 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9004 gas_assert (mips_opts
.micromips
);
9005 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9013 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9020 br
= mips_opts
.micromips
? "blez" : "blezl";
9027 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9031 gas_assert (mips_opts
.micromips
);
9032 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9039 if (mips_opts
.micromips
&& brneg
)
9040 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9042 macro_build (ep
, br
, "s,p", sreg
);
9045 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9046 TREG as the registers tested. EP specifies the branch target. */
9049 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9050 unsigned int sreg
, unsigned int treg
)
9052 const char *brneg
= NULL
;
9064 br
= mips_opts
.micromips
? "beq" : "beql";
9073 br
= mips_opts
.micromips
? "bne" : "bnel";
9079 if (mips_opts
.micromips
&& brneg
)
9080 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9082 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9085 /* Return the high part that should be loaded in order to make the low
9086 part of VALUE accessible using an offset of OFFBITS bits. */
9089 offset_high_part (offsetT value
, unsigned int offbits
)
9096 bias
= 1 << (offbits
- 1);
9097 low_mask
= bias
* 2 - 1;
9098 return (value
+ bias
) & ~low_mask
;
9101 /* Return true if the value stored in offset_expr and offset_reloc
9102 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9103 amount that the caller wants to add without inducing overflow
9104 and ALIGN is the known alignment of the value in bytes. */
9107 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9111 /* Accept any relocation operator if overflow isn't a concern. */
9112 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9115 /* These relocations are guaranteed not to overflow in correct links. */
9116 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9117 || gprel16_reloc_p (*offset_reloc
))
9120 if (offset_expr
.X_op
== O_constant
9121 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9122 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9129 * This routine implements the seemingly endless macro or synthesized
9130 * instructions and addressing modes in the mips assembly language. Many
9131 * of these macros are simple and are similar to each other. These could
9132 * probably be handled by some kind of table or grammar approach instead of
9133 * this verbose method. Others are not simple macros but are more like
9134 * optimizing code generation.
9135 * One interesting optimization is when several store macros appear
9136 * consecutively that would load AT with the upper half of the same address.
9137 * The ensuing load upper instructions are ommited. This implies some kind
9138 * of global optimization. We currently only optimize within a single macro.
9139 * For many of the load and store macros if the address is specified as a
9140 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9141 * first load register 'at' with zero and use it as the base register. The
9142 * mips assembler simply uses register $zero. Just one tiny optimization
9146 macro (struct mips_cl_insn
*ip
, char *str
)
9148 const struct mips_operand_array
*operands
;
9149 unsigned int breg
, i
;
9150 unsigned int tempreg
;
9153 expressionS label_expr
;
9168 bfd_boolean large_offset
;
9170 int hold_mips_optimize
;
9172 unsigned int op
[MAX_OPERANDS
];
9174 gas_assert (! mips_opts
.mips16
);
9176 operands
= insn_operands (ip
);
9177 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9178 if (operands
->operand
[i
])
9179 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9183 mask
= ip
->insn_mo
->mask
;
9185 label_expr
.X_op
= O_constant
;
9186 label_expr
.X_op_symbol
= NULL
;
9187 label_expr
.X_add_symbol
= NULL
;
9188 label_expr
.X_add_number
= 0;
9190 expr1
.X_op
= O_constant
;
9191 expr1
.X_op_symbol
= NULL
;
9192 expr1
.X_add_symbol
= NULL
;
9193 expr1
.X_add_number
= 1;
9209 if (mips_opts
.micromips
)
9210 micromips_label_expr (&label_expr
);
9212 label_expr
.X_add_number
= 8;
9213 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9215 macro_build (NULL
, "nop", "");
9217 move_register (op
[0], op
[1]);
9218 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9219 if (mips_opts
.micromips
)
9220 micromips_add_label ();
9237 if (!mips_opts
.micromips
)
9239 if (imm_expr
.X_add_number
>= -0x200
9240 && imm_expr
.X_add_number
< 0x200)
9242 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9243 (int) imm_expr
.X_add_number
);
9252 if (imm_expr
.X_add_number
>= -0x8000
9253 && imm_expr
.X_add_number
< 0x8000)
9255 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9260 load_register (AT
, &imm_expr
, dbl
);
9261 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9280 if (imm_expr
.X_add_number
>= 0
9281 && imm_expr
.X_add_number
< 0x10000)
9283 if (mask
!= M_NOR_I
)
9284 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9287 macro_build (&imm_expr
, "ori", "t,r,i",
9288 op
[0], op
[1], BFD_RELOC_LO16
);
9289 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9295 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9296 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9300 switch (imm_expr
.X_add_number
)
9303 macro_build (NULL
, "nop", "");
9306 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9310 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9311 (int) imm_expr
.X_add_number
);
9314 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9315 (unsigned long) imm_expr
.X_add_number
);
9324 gas_assert (mips_opts
.micromips
);
9325 macro_build_branch_ccl (mask
, &offset_expr
,
9326 EXTRACT_OPERAND (1, BCC
, *ip
));
9333 if (imm_expr
.X_add_number
== 0)
9339 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9344 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9351 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9352 else if (op
[0] == 0)
9353 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9357 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9358 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9359 &offset_expr
, AT
, ZERO
);
9369 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9375 /* Check for > max integer. */
9376 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9379 /* Result is always false. */
9381 macro_build (NULL
, "nop", "");
9383 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9386 ++imm_expr
.X_add_number
;
9390 if (mask
== M_BGEL_I
)
9392 if (imm_expr
.X_add_number
== 0)
9394 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9395 &offset_expr
, op
[0]);
9398 if (imm_expr
.X_add_number
== 1)
9400 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9401 &offset_expr
, op
[0]);
9404 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9407 /* result is always true */
9408 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9409 macro_build (&offset_expr
, "b", "p");
9414 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9415 &offset_expr
, AT
, ZERO
);
9423 else if (op
[0] == 0)
9424 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9425 &offset_expr
, ZERO
, op
[1]);
9429 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9430 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9431 &offset_expr
, AT
, ZERO
);
9440 && imm_expr
.X_add_number
== -1))
9442 ++imm_expr
.X_add_number
;
9446 if (mask
== M_BGEUL_I
)
9448 if (imm_expr
.X_add_number
== 0)
9450 else if (imm_expr
.X_add_number
== 1)
9451 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9452 &offset_expr
, op
[0], ZERO
);
9457 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9458 &offset_expr
, AT
, ZERO
);
9466 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9467 else if (op
[0] == 0)
9468 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9472 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9473 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9474 &offset_expr
, AT
, ZERO
);
9482 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9483 &offset_expr
, op
[0], ZERO
);
9484 else if (op
[0] == 0)
9489 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9490 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9491 &offset_expr
, AT
, ZERO
);
9499 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9500 else if (op
[0] == 0)
9501 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9505 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9506 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9507 &offset_expr
, AT
, ZERO
);
9514 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9516 ++imm_expr
.X_add_number
;
9520 if (mask
== M_BLTL_I
)
9522 if (imm_expr
.X_add_number
== 0)
9523 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9524 else if (imm_expr
.X_add_number
== 1)
9525 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9530 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9531 &offset_expr
, AT
, ZERO
);
9539 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9540 &offset_expr
, op
[0], ZERO
);
9541 else if (op
[0] == 0)
9546 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9547 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9548 &offset_expr
, AT
, ZERO
);
9557 && imm_expr
.X_add_number
== -1))
9559 ++imm_expr
.X_add_number
;
9563 if (mask
== M_BLTUL_I
)
9565 if (imm_expr
.X_add_number
== 0)
9567 else if (imm_expr
.X_add_number
== 1)
9568 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9569 &offset_expr
, op
[0], ZERO
);
9574 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9575 &offset_expr
, AT
, ZERO
);
9583 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9584 else if (op
[0] == 0)
9585 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9589 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9590 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9591 &offset_expr
, AT
, ZERO
);
9600 else if (op
[0] == 0)
9601 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9602 &offset_expr
, ZERO
, op
[1]);
9606 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9607 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9608 &offset_expr
, AT
, ZERO
);
9624 as_warn (_("divide by zero"));
9626 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9628 macro_build (NULL
, "break", BRK_FMT
, 7);
9635 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9636 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9640 if (mips_opts
.micromips
)
9641 micromips_label_expr (&label_expr
);
9643 label_expr
.X_add_number
= 8;
9644 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9645 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9646 macro_build (NULL
, "break", BRK_FMT
, 7);
9647 if (mips_opts
.micromips
)
9648 micromips_add_label ();
9650 expr1
.X_add_number
= -1;
9652 load_register (AT
, &expr1
, dbl
);
9653 if (mips_opts
.micromips
)
9654 micromips_label_expr (&label_expr
);
9656 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9657 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9660 expr1
.X_add_number
= 1;
9661 load_register (AT
, &expr1
, dbl
);
9662 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9666 expr1
.X_add_number
= 0x80000000;
9667 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9671 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9672 /* We want to close the noreorder block as soon as possible, so
9673 that later insns are available for delay slot filling. */
9678 if (mips_opts
.micromips
)
9679 micromips_label_expr (&label_expr
);
9681 label_expr
.X_add_number
= 8;
9682 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9683 macro_build (NULL
, "nop", "");
9685 /* We want to close the noreorder block as soon as possible, so
9686 that later insns are available for delay slot filling. */
9689 macro_build (NULL
, "break", BRK_FMT
, 6);
9691 if (mips_opts
.micromips
)
9692 micromips_add_label ();
9693 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9732 if (imm_expr
.X_add_number
== 0)
9734 as_warn (_("divide by zero"));
9736 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9738 macro_build (NULL
, "break", BRK_FMT
, 7);
9741 if (imm_expr
.X_add_number
== 1)
9743 if (strcmp (s2
, "mflo") == 0)
9744 move_register (op
[0], op
[1]);
9746 move_register (op
[0], ZERO
);
9749 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
9751 if (strcmp (s2
, "mflo") == 0)
9752 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9754 move_register (op
[0], ZERO
);
9759 load_register (AT
, &imm_expr
, dbl
);
9760 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9761 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9783 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9784 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9785 /* We want to close the noreorder block as soon as possible, so
9786 that later insns are available for delay slot filling. */
9791 if (mips_opts
.micromips
)
9792 micromips_label_expr (&label_expr
);
9794 label_expr
.X_add_number
= 8;
9795 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9796 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9798 /* We want to close the noreorder block as soon as possible, so
9799 that later insns are available for delay slot filling. */
9801 macro_build (NULL
, "break", BRK_FMT
, 7);
9802 if (mips_opts
.micromips
)
9803 micromips_add_label ();
9805 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9817 /* Load the address of a symbol into a register. If breg is not
9818 zero, we then add a base register to it. */
9821 if (dbl
&& HAVE_32BIT_GPRS
)
9822 as_warn (_("dla used to load 32-bit register"));
9824 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9825 as_warn (_("la used to load 64-bit address"));
9827 if (small_offset_p (0, align
, 16))
9829 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9830 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9834 if (mips_opts
.at
&& (op
[0] == breg
))
9842 if (offset_expr
.X_op
!= O_symbol
9843 && offset_expr
.X_op
!= O_constant
)
9845 as_bad (_("expression too complex"));
9846 offset_expr
.X_op
= O_constant
;
9849 if (offset_expr
.X_op
== O_constant
)
9850 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9851 else if (mips_pic
== NO_PIC
)
9853 /* If this is a reference to a GP relative symbol, we want
9854 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9856 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9857 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9858 If we have a constant, we need two instructions anyhow,
9859 so we may as well always use the latter form.
9861 With 64bit address space and a usable $at we want
9862 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9863 lui $at,<sym> (BFD_RELOC_HI16_S)
9864 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9865 daddiu $at,<sym> (BFD_RELOC_LO16)
9867 daddu $tempreg,$tempreg,$at
9869 If $at is already in use, we use a path which is suboptimal
9870 on superscalar processors.
9871 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9872 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9874 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9876 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9878 For GP relative symbols in 64bit address space we can use
9879 the same sequence as in 32bit address space. */
9880 if (HAVE_64BIT_SYMBOLS
)
9882 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9883 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9885 relax_start (offset_expr
.X_add_symbol
);
9886 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9887 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9891 if (used_at
== 0 && mips_opts
.at
)
9893 macro_build (&offset_expr
, "lui", LUI_FMT
,
9894 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9895 macro_build (&offset_expr
, "lui", LUI_FMT
,
9896 AT
, BFD_RELOC_HI16_S
);
9897 macro_build (&offset_expr
, "daddiu", "t,r,j",
9898 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9899 macro_build (&offset_expr
, "daddiu", "t,r,j",
9900 AT
, AT
, BFD_RELOC_LO16
);
9901 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9902 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9907 macro_build (&offset_expr
, "lui", LUI_FMT
,
9908 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9909 macro_build (&offset_expr
, "daddiu", "t,r,j",
9910 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9911 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9912 macro_build (&offset_expr
, "daddiu", "t,r,j",
9913 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9914 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9915 macro_build (&offset_expr
, "daddiu", "t,r,j",
9916 tempreg
, tempreg
, BFD_RELOC_LO16
);
9919 if (mips_relax
.sequence
)
9924 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9925 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9927 relax_start (offset_expr
.X_add_symbol
);
9928 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9929 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9932 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9933 as_bad (_("offset too large"));
9934 macro_build_lui (&offset_expr
, tempreg
);
9935 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9936 tempreg
, tempreg
, BFD_RELOC_LO16
);
9937 if (mips_relax
.sequence
)
9941 else if (!mips_big_got
&& !HAVE_NEWABI
)
9943 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9945 /* If this is a reference to an external symbol, and there
9946 is no constant, we want
9947 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9948 or for lca or if tempreg is PIC_CALL_REG
9949 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9950 For a local symbol, we want
9951 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9953 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9955 If we have a small constant, and this is a reference to
9956 an external symbol, we want
9957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9959 addiu $tempreg,$tempreg,<constant>
9960 For a local symbol, we want the same instruction
9961 sequence, but we output a BFD_RELOC_LO16 reloc on the
9964 If we have a large constant, and this is a reference to
9965 an external symbol, we want
9966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9967 lui $at,<hiconstant>
9968 addiu $at,$at,<loconstant>
9969 addu $tempreg,$tempreg,$at
9970 For a local symbol, we want the same instruction
9971 sequence, but we output a BFD_RELOC_LO16 reloc on the
9975 if (offset_expr
.X_add_number
== 0)
9977 if (mips_pic
== SVR4_PIC
9979 && (call
|| tempreg
== PIC_CALL_REG
))
9980 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9982 relax_start (offset_expr
.X_add_symbol
);
9983 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9984 lw_reloc_type
, mips_gp_register
);
9987 /* We're going to put in an addu instruction using
9988 tempreg, so we may as well insert the nop right
9993 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9994 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9996 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9997 tempreg
, tempreg
, BFD_RELOC_LO16
);
9999 /* FIXME: If breg == 0, and the next instruction uses
10000 $tempreg, then if this variant case is used an extra
10001 nop will be generated. */
10003 else if (offset_expr
.X_add_number
>= -0x8000
10004 && offset_expr
.X_add_number
< 0x8000)
10006 load_got_offset (tempreg
, &offset_expr
);
10008 add_got_offset (tempreg
, &offset_expr
);
10012 expr1
.X_add_number
= offset_expr
.X_add_number
;
10013 offset_expr
.X_add_number
=
10014 SEXT_16BIT (offset_expr
.X_add_number
);
10015 load_got_offset (tempreg
, &offset_expr
);
10016 offset_expr
.X_add_number
= expr1
.X_add_number
;
10017 /* If we are going to add in a base register, and the
10018 target register and the base register are the same,
10019 then we are using AT as a temporary register. Since
10020 we want to load the constant into AT, we add our
10021 current AT (from the global offset table) and the
10022 register into the register now, and pretend we were
10023 not using a base register. */
10027 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10032 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10036 else if (!mips_big_got
&& HAVE_NEWABI
)
10038 int add_breg_early
= 0;
10040 /* If this is a reference to an external, and there is no
10041 constant, or local symbol (*), with or without a
10043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10044 or for lca or if tempreg is PIC_CALL_REG
10045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10047 If we have a small constant, and this is a reference to
10048 an external symbol, we want
10049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10050 addiu $tempreg,$tempreg,<constant>
10052 If we have a large constant, and this is a reference to
10053 an external symbol, we want
10054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10055 lui $at,<hiconstant>
10056 addiu $at,$at,<loconstant>
10057 addu $tempreg,$tempreg,$at
10059 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10060 local symbols, even though it introduces an additional
10063 if (offset_expr
.X_add_number
)
10065 expr1
.X_add_number
= offset_expr
.X_add_number
;
10066 offset_expr
.X_add_number
= 0;
10068 relax_start (offset_expr
.X_add_symbol
);
10069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10070 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10072 if (expr1
.X_add_number
>= -0x8000
10073 && expr1
.X_add_number
< 0x8000)
10075 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10076 tempreg
, tempreg
, BFD_RELOC_LO16
);
10078 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10082 /* If we are going to add in a base register, and the
10083 target register and the base register are the same,
10084 then we are using AT as a temporary register. Since
10085 we want to load the constant into AT, we add our
10086 current AT (from the global offset table) and the
10087 register into the register now, and pretend we were
10088 not using a base register. */
10093 gas_assert (tempreg
== AT
);
10094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10097 add_breg_early
= 1;
10100 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10101 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10107 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10110 offset_expr
.X_add_number
= expr1
.X_add_number
;
10112 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10113 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10114 if (add_breg_early
)
10116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10117 op
[0], tempreg
, breg
);
10123 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10125 relax_start (offset_expr
.X_add_symbol
);
10126 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10127 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10129 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10130 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10135 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10136 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10139 else if (mips_big_got
&& !HAVE_NEWABI
)
10142 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10143 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10144 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10146 /* This is the large GOT case. If this is a reference to an
10147 external symbol, and there is no constant, we want
10148 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10149 addu $tempreg,$tempreg,$gp
10150 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10151 or for lca or if tempreg is PIC_CALL_REG
10152 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10153 addu $tempreg,$tempreg,$gp
10154 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10155 For a local symbol, we want
10156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10158 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10160 If we have a small constant, and this is a reference to
10161 an external symbol, we want
10162 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10163 addu $tempreg,$tempreg,$gp
10164 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10166 addiu $tempreg,$tempreg,<constant>
10167 For a local symbol, we want
10168 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10170 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10172 If we have a large constant, and this is a reference to
10173 an external symbol, we want
10174 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10175 addu $tempreg,$tempreg,$gp
10176 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10177 lui $at,<hiconstant>
10178 addiu $at,$at,<loconstant>
10179 addu $tempreg,$tempreg,$at
10180 For a local symbol, we want
10181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10182 lui $at,<hiconstant>
10183 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10184 addu $tempreg,$tempreg,$at
10187 expr1
.X_add_number
= offset_expr
.X_add_number
;
10188 offset_expr
.X_add_number
= 0;
10189 relax_start (offset_expr
.X_add_symbol
);
10190 gpdelay
= reg_needs_delay (mips_gp_register
);
10191 if (expr1
.X_add_number
== 0 && breg
== 0
10192 && (call
|| tempreg
== PIC_CALL_REG
))
10194 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10195 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10197 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10198 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10199 tempreg
, tempreg
, mips_gp_register
);
10200 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10201 tempreg
, lw_reloc_type
, tempreg
);
10202 if (expr1
.X_add_number
== 0)
10206 /* We're going to put in an addu instruction using
10207 tempreg, so we may as well insert the nop right
10212 else if (expr1
.X_add_number
>= -0x8000
10213 && expr1
.X_add_number
< 0x8000)
10216 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10217 tempreg
, tempreg
, BFD_RELOC_LO16
);
10223 /* If we are going to add in a base register, and the
10224 target register and the base register are the same,
10225 then we are using AT as a temporary register. Since
10226 we want to load the constant into AT, we add our
10227 current AT (from the global offset table) and the
10228 register into the register now, and pretend we were
10229 not using a base register. */
10234 gas_assert (tempreg
== AT
);
10236 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10241 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10242 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10246 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10251 /* This is needed because this instruction uses $gp, but
10252 the first instruction on the main stream does not. */
10253 macro_build (NULL
, "nop", "");
10256 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10257 local_reloc_type
, mips_gp_register
);
10258 if (expr1
.X_add_number
>= -0x8000
10259 && expr1
.X_add_number
< 0x8000)
10262 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10263 tempreg
, tempreg
, BFD_RELOC_LO16
);
10264 /* FIXME: If add_number is 0, and there was no base
10265 register, the external symbol case ended with a load,
10266 so if the symbol turns out to not be external, and
10267 the next instruction uses tempreg, an unnecessary nop
10268 will be inserted. */
10274 /* We must add in the base register now, as in the
10275 external symbol case. */
10276 gas_assert (tempreg
== AT
);
10278 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10281 /* We set breg to 0 because we have arranged to add
10282 it in in both cases. */
10286 macro_build_lui (&expr1
, AT
);
10287 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10288 AT
, AT
, BFD_RELOC_LO16
);
10289 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10290 tempreg
, tempreg
, AT
);
10295 else if (mips_big_got
&& HAVE_NEWABI
)
10297 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10298 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10299 int add_breg_early
= 0;
10301 /* This is the large GOT case. If this is a reference to an
10302 external symbol, and there is no constant, we want
10303 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10304 add $tempreg,$tempreg,$gp
10305 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10306 or for lca or if tempreg is PIC_CALL_REG
10307 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10308 add $tempreg,$tempreg,$gp
10309 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10311 If we have a small constant, and this is a reference to
10312 an external symbol, we want
10313 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10314 add $tempreg,$tempreg,$gp
10315 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10316 addi $tempreg,$tempreg,<constant>
10318 If we have a large constant, and this is a reference to
10319 an external symbol, we want
10320 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10321 addu $tempreg,$tempreg,$gp
10322 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10323 lui $at,<hiconstant>
10324 addi $at,$at,<loconstant>
10325 add $tempreg,$tempreg,$at
10327 If we have NewABI, and we know it's a local symbol, we want
10328 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10329 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10330 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10332 relax_start (offset_expr
.X_add_symbol
);
10334 expr1
.X_add_number
= offset_expr
.X_add_number
;
10335 offset_expr
.X_add_number
= 0;
10337 if (expr1
.X_add_number
== 0 && breg
== 0
10338 && (call
|| tempreg
== PIC_CALL_REG
))
10340 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10341 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10343 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10344 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10345 tempreg
, tempreg
, mips_gp_register
);
10346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10347 tempreg
, lw_reloc_type
, tempreg
);
10349 if (expr1
.X_add_number
== 0)
10351 else if (expr1
.X_add_number
>= -0x8000
10352 && expr1
.X_add_number
< 0x8000)
10354 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10355 tempreg
, tempreg
, BFD_RELOC_LO16
);
10357 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10361 /* If we are going to add in a base register, and the
10362 target register and the base register are the same,
10363 then we are using AT as a temporary register. Since
10364 we want to load the constant into AT, we add our
10365 current AT (from the global offset table) and the
10366 register into the register now, and pretend we were
10367 not using a base register. */
10372 gas_assert (tempreg
== AT
);
10373 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10376 add_breg_early
= 1;
10379 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10380 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10385 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10388 offset_expr
.X_add_number
= expr1
.X_add_number
;
10389 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10390 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10391 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10392 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10393 if (add_breg_early
)
10395 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10396 op
[0], tempreg
, breg
);
10406 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10410 gas_assert (!mips_opts
.micromips
);
10411 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10415 gas_assert (!mips_opts
.micromips
);
10416 macro_build (NULL
, "c2", "C", 0x02);
10420 gas_assert (!mips_opts
.micromips
);
10421 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10425 gas_assert (!mips_opts
.micromips
);
10426 macro_build (NULL
, "c2", "C", 3);
10430 gas_assert (!mips_opts
.micromips
);
10431 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10435 /* The j instruction may not be used in PIC code, since it
10436 requires an absolute address. We convert it to a b
10438 if (mips_pic
== NO_PIC
)
10439 macro_build (&offset_expr
, "j", "a");
10441 macro_build (&offset_expr
, "b", "p");
10444 /* The jal instructions must be handled as macros because when
10445 generating PIC code they expand to multi-instruction
10446 sequences. Normally they are simple instructions. */
10450 /* Fall through. */
10452 gas_assert (mips_opts
.micromips
);
10453 if (mips_opts
.insn32
)
10455 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10463 /* Fall through. */
10466 if (mips_pic
== NO_PIC
)
10468 s
= jals
? "jalrs" : "jalr";
10469 if (mips_opts
.micromips
10470 && !mips_opts
.insn32
10472 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10473 macro_build (NULL
, s
, "mj", op
[1]);
10475 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10479 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10480 && mips_cprestore_offset
>= 0);
10482 if (op
[1] != PIC_CALL_REG
)
10483 as_warn (_("MIPS PIC call to register other than $25"));
10485 s
= ((mips_opts
.micromips
10486 && !mips_opts
.insn32
10487 && (!mips_opts
.noreorder
|| cprestore
))
10488 ? "jalrs" : "jalr");
10489 if (mips_opts
.micromips
10490 && !mips_opts
.insn32
10492 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10493 macro_build (NULL
, s
, "mj", op
[1]);
10495 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10496 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10498 if (mips_cprestore_offset
< 0)
10499 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10502 if (!mips_frame_reg_valid
)
10504 as_warn (_("no .frame pseudo-op used in PIC code"));
10505 /* Quiet this warning. */
10506 mips_frame_reg_valid
= 1;
10508 if (!mips_cprestore_valid
)
10510 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10511 /* Quiet this warning. */
10512 mips_cprestore_valid
= 1;
10514 if (mips_opts
.noreorder
)
10515 macro_build (NULL
, "nop", "");
10516 expr1
.X_add_number
= mips_cprestore_offset
;
10517 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10520 HAVE_64BIT_ADDRESSES
);
10528 gas_assert (mips_opts
.micromips
);
10529 if (mips_opts
.insn32
)
10531 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10535 /* Fall through. */
10537 if (mips_pic
== NO_PIC
)
10538 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10539 else if (mips_pic
== SVR4_PIC
)
10541 /* If this is a reference to an external symbol, and we are
10542 using a small GOT, we want
10543 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10547 lw $gp,cprestore($sp)
10548 The cprestore value is set using the .cprestore
10549 pseudo-op. If we are using a big GOT, we want
10550 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10552 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10556 lw $gp,cprestore($sp)
10557 If the symbol is not external, we want
10558 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10560 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10563 lw $gp,cprestore($sp)
10565 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10566 sequences above, minus nops, unless the symbol is local,
10567 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10573 relax_start (offset_expr
.X_add_symbol
);
10574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10575 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10578 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10579 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10585 relax_start (offset_expr
.X_add_symbol
);
10586 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10587 BFD_RELOC_MIPS_CALL_HI16
);
10588 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10589 PIC_CALL_REG
, mips_gp_register
);
10590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10591 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10594 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10595 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10597 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10598 PIC_CALL_REG
, PIC_CALL_REG
,
10599 BFD_RELOC_MIPS_GOT_OFST
);
10603 macro_build_jalr (&offset_expr
, 0);
10607 relax_start (offset_expr
.X_add_symbol
);
10610 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10611 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10620 gpdelay
= reg_needs_delay (mips_gp_register
);
10621 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10622 BFD_RELOC_MIPS_CALL_HI16
);
10623 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10624 PIC_CALL_REG
, mips_gp_register
);
10625 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10626 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10631 macro_build (NULL
, "nop", "");
10633 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10634 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10637 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10638 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10640 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10642 if (mips_cprestore_offset
< 0)
10643 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10646 if (!mips_frame_reg_valid
)
10648 as_warn (_("no .frame pseudo-op used in PIC code"));
10649 /* Quiet this warning. */
10650 mips_frame_reg_valid
= 1;
10652 if (!mips_cprestore_valid
)
10654 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10655 /* Quiet this warning. */
10656 mips_cprestore_valid
= 1;
10658 if (mips_opts
.noreorder
)
10659 macro_build (NULL
, "nop", "");
10660 expr1
.X_add_number
= mips_cprestore_offset
;
10661 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10664 HAVE_64BIT_ADDRESSES
);
10668 else if (mips_pic
== VXWORKS_PIC
)
10669 as_bad (_("non-PIC jump used in PIC library"));
10776 gas_assert (!mips_opts
.micromips
);
10779 /* Itbl support may require additional care here. */
10785 /* Itbl support may require additional care here. */
10791 offbits
= (mips_opts
.micromips
? 12 : 16);
10792 /* Itbl support may require additional care here. */
10796 gas_assert (!mips_opts
.micromips
);
10799 /* Itbl support may require additional care here. */
10805 offbits
= (mips_opts
.micromips
? 12 : 16);
10810 offbits
= (mips_opts
.micromips
? 12 : 16);
10815 /* Itbl support may require additional care here. */
10821 offbits
= (mips_opts
.micromips
? 12 : 16);
10822 /* Itbl support may require additional care here. */
10828 /* Itbl support may require additional care here. */
10834 /* Itbl support may require additional care here. */
10840 offbits
= (mips_opts
.micromips
? 12 : 16);
10845 offbits
= (mips_opts
.micromips
? 12 : 16);
10850 offbits
= (mips_opts
.micromips
? 12 : 16);
10855 offbits
= (mips_opts
.micromips
? 12 : 16);
10860 offbits
= (mips_opts
.micromips
? 12 : 16);
10863 gas_assert (mips_opts
.micromips
);
10870 gas_assert (mips_opts
.micromips
);
10877 gas_assert (mips_opts
.micromips
);
10883 gas_assert (mips_opts
.micromips
);
10890 /* We don't want to use $0 as tempreg. */
10891 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10894 tempreg
= op
[0] + lp
;
10910 gas_assert (!mips_opts
.micromips
);
10913 /* Itbl support may require additional care here. */
10919 /* Itbl support may require additional care here. */
10925 offbits
= (mips_opts
.micromips
? 12 : 16);
10926 /* Itbl support may require additional care here. */
10930 gas_assert (!mips_opts
.micromips
);
10933 /* Itbl support may require additional care here. */
10939 offbits
= (mips_opts
.micromips
? 12 : 16);
10944 offbits
= (mips_opts
.micromips
? 12 : 16);
10949 offbits
= (mips_opts
.micromips
? 12 : 16);
10954 offbits
= (mips_opts
.micromips
? 12 : 16);
10958 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10959 offbits
= (mips_opts
.micromips
? 12 : 16);
10968 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10969 offbits
= (mips_opts
.micromips
? 12 : 16);
10980 /* Itbl support may require additional care here. */
10985 offbits
= (mips_opts
.micromips
? 12 : 16);
10986 /* Itbl support may require additional care here. */
10992 /* Itbl support may require additional care here. */
10996 gas_assert (!mips_opts
.micromips
);
10999 /* Itbl support may require additional care here. */
11005 offbits
= (mips_opts
.micromips
? 12 : 16);
11010 offbits
= (mips_opts
.micromips
? 12 : 16);
11013 gas_assert (mips_opts
.micromips
);
11019 gas_assert (mips_opts
.micromips
);
11025 gas_assert (mips_opts
.micromips
);
11031 gas_assert (mips_opts
.micromips
);
11040 if (small_offset_p (0, align
, 16))
11042 /* The first case exists for M_LD_AB and M_SD_AB, which are
11043 macros for o32 but which should act like normal instructions
11046 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11047 offset_reloc
[1], offset_reloc
[2], breg
);
11048 else if (small_offset_p (0, align
, offbits
))
11051 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11053 macro_build (NULL
, s
, fmt
, op
[0],
11054 (int) offset_expr
.X_add_number
, breg
);
11060 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11061 tempreg
, breg
, -1, offset_reloc
[0],
11062 offset_reloc
[1], offset_reloc
[2]);
11064 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11066 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11074 if (offset_expr
.X_op
!= O_constant
11075 && offset_expr
.X_op
!= O_symbol
)
11077 as_bad (_("expression too complex"));
11078 offset_expr
.X_op
= O_constant
;
11081 if (HAVE_32BIT_ADDRESSES
11082 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11086 sprintf_vma (value
, offset_expr
.X_add_number
);
11087 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11090 /* A constant expression in PIC code can be handled just as it
11091 is in non PIC code. */
11092 if (offset_expr
.X_op
== O_constant
)
11094 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11095 offbits
== 0 ? 16 : offbits
);
11096 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11098 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11100 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11101 tempreg
, tempreg
, breg
);
11104 if (offset_expr
.X_add_number
!= 0)
11105 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11106 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11107 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11109 else if (offbits
== 16)
11110 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11112 macro_build (NULL
, s
, fmt
, op
[0],
11113 (int) offset_expr
.X_add_number
, tempreg
);
11115 else if (offbits
!= 16)
11117 /* The offset field is too narrow to be used for a low-part
11118 relocation, so load the whole address into the auxillary
11120 load_address (tempreg
, &offset_expr
, &used_at
);
11122 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11123 tempreg
, tempreg
, breg
);
11125 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11127 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11129 else if (mips_pic
== NO_PIC
)
11131 /* If this is a reference to a GP relative symbol, and there
11132 is no base register, we want
11133 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11134 Otherwise, if there is no base register, we want
11135 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11136 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11137 If we have a constant, we need two instructions anyhow,
11138 so we always use the latter form.
11140 If we have a base register, and this is a reference to a
11141 GP relative symbol, we want
11142 addu $tempreg,$breg,$gp
11143 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11145 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11146 addu $tempreg,$tempreg,$breg
11147 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11148 With a constant we always use the latter case.
11150 With 64bit address space and no base register and $at usable,
11152 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11153 lui $at,<sym> (BFD_RELOC_HI16_S)
11154 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11157 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11158 If we have a base register, we want
11159 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11160 lui $at,<sym> (BFD_RELOC_HI16_S)
11161 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11165 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11167 Without $at we can't generate the optimal path for superscalar
11168 processors here since this would require two temporary registers.
11169 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11170 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11172 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11174 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11175 If we have a base register, we want
11176 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11177 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11179 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11181 daddu $tempreg,$tempreg,$breg
11182 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11184 For GP relative symbols in 64bit address space we can use
11185 the same sequence as in 32bit address space. */
11186 if (HAVE_64BIT_SYMBOLS
)
11188 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11189 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11191 relax_start (offset_expr
.X_add_symbol
);
11194 macro_build (&offset_expr
, s
, fmt
, op
[0],
11195 BFD_RELOC_GPREL16
, mips_gp_register
);
11199 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11200 tempreg
, breg
, mips_gp_register
);
11201 macro_build (&offset_expr
, s
, fmt
, op
[0],
11202 BFD_RELOC_GPREL16
, tempreg
);
11207 if (used_at
== 0 && mips_opts
.at
)
11209 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11210 BFD_RELOC_MIPS_HIGHEST
);
11211 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11213 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11214 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11216 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11217 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11218 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11219 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11225 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11226 BFD_RELOC_MIPS_HIGHEST
);
11227 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11228 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11229 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11230 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11231 tempreg
, BFD_RELOC_HI16_S
);
11232 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11234 macro_build (NULL
, "daddu", "d,v,t",
11235 tempreg
, tempreg
, breg
);
11236 macro_build (&offset_expr
, s
, fmt
, op
[0],
11237 BFD_RELOC_LO16
, tempreg
);
11240 if (mips_relax
.sequence
)
11247 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11248 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11250 relax_start (offset_expr
.X_add_symbol
);
11251 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11255 macro_build_lui (&offset_expr
, tempreg
);
11256 macro_build (&offset_expr
, s
, fmt
, op
[0],
11257 BFD_RELOC_LO16
, tempreg
);
11258 if (mips_relax
.sequence
)
11263 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11264 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11266 relax_start (offset_expr
.X_add_symbol
);
11267 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11268 tempreg
, breg
, mips_gp_register
);
11269 macro_build (&offset_expr
, s
, fmt
, op
[0],
11270 BFD_RELOC_GPREL16
, tempreg
);
11273 macro_build_lui (&offset_expr
, tempreg
);
11274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11275 tempreg
, tempreg
, breg
);
11276 macro_build (&offset_expr
, s
, fmt
, op
[0],
11277 BFD_RELOC_LO16
, tempreg
);
11278 if (mips_relax
.sequence
)
11282 else if (!mips_big_got
)
11284 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11286 /* If this is a reference to an external symbol, we want
11287 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11289 <op> op[0],0($tempreg)
11291 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11293 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11294 <op> op[0],0($tempreg)
11296 For NewABI, we want
11297 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11298 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11300 If there is a base register, we add it to $tempreg before
11301 the <op>. If there is a constant, we stick it in the
11302 <op> instruction. We don't handle constants larger than
11303 16 bits, because we have no way to load the upper 16 bits
11304 (actually, we could handle them for the subset of cases
11305 in which we are not using $at). */
11306 gas_assert (offset_expr
.X_op
== O_symbol
);
11309 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11310 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11312 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11313 tempreg
, tempreg
, breg
);
11314 macro_build (&offset_expr
, s
, fmt
, op
[0],
11315 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11318 expr1
.X_add_number
= offset_expr
.X_add_number
;
11319 offset_expr
.X_add_number
= 0;
11320 if (expr1
.X_add_number
< -0x8000
11321 || expr1
.X_add_number
>= 0x8000)
11322 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11323 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11324 lw_reloc_type
, mips_gp_register
);
11326 relax_start (offset_expr
.X_add_symbol
);
11328 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11329 tempreg
, BFD_RELOC_LO16
);
11332 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11333 tempreg
, tempreg
, breg
);
11334 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11336 else if (mips_big_got
&& !HAVE_NEWABI
)
11340 /* If this is a reference to an external symbol, we want
11341 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11342 addu $tempreg,$tempreg,$gp
11343 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11344 <op> op[0],0($tempreg)
11346 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11348 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11349 <op> op[0],0($tempreg)
11350 If there is a base register, we add it to $tempreg before
11351 the <op>. If there is a constant, we stick it in the
11352 <op> instruction. We don't handle constants larger than
11353 16 bits, because we have no way to load the upper 16 bits
11354 (actually, we could handle them for the subset of cases
11355 in which we are not using $at). */
11356 gas_assert (offset_expr
.X_op
== O_symbol
);
11357 expr1
.X_add_number
= offset_expr
.X_add_number
;
11358 offset_expr
.X_add_number
= 0;
11359 if (expr1
.X_add_number
< -0x8000
11360 || expr1
.X_add_number
>= 0x8000)
11361 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11362 gpdelay
= reg_needs_delay (mips_gp_register
);
11363 relax_start (offset_expr
.X_add_symbol
);
11364 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11365 BFD_RELOC_MIPS_GOT_HI16
);
11366 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11368 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11369 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11372 macro_build (NULL
, "nop", "");
11373 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11374 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11376 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11377 tempreg
, BFD_RELOC_LO16
);
11381 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11382 tempreg
, tempreg
, breg
);
11383 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11385 else if (mips_big_got
&& HAVE_NEWABI
)
11387 /* If this is a reference to an external symbol, we want
11388 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11389 add $tempreg,$tempreg,$gp
11390 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11391 <op> op[0],<ofst>($tempreg)
11392 Otherwise, for local symbols, we want:
11393 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11394 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11395 gas_assert (offset_expr
.X_op
== O_symbol
);
11396 expr1
.X_add_number
= offset_expr
.X_add_number
;
11397 offset_expr
.X_add_number
= 0;
11398 if (expr1
.X_add_number
< -0x8000
11399 || expr1
.X_add_number
>= 0x8000)
11400 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11401 relax_start (offset_expr
.X_add_symbol
);
11402 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11403 BFD_RELOC_MIPS_GOT_HI16
);
11404 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11406 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11407 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11410 tempreg
, tempreg
, breg
);
11411 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11414 offset_expr
.X_add_number
= expr1
.X_add_number
;
11415 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11416 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11418 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11419 tempreg
, tempreg
, breg
);
11420 macro_build (&offset_expr
, s
, fmt
, op
[0],
11421 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11430 gas_assert (mips_opts
.micromips
);
11431 gas_assert (mips_opts
.insn32
);
11432 start_noreorder ();
11433 macro_build (NULL
, "jr", "s", RA
);
11434 expr1
.X_add_number
= op
[0] << 2;
11435 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11440 gas_assert (mips_opts
.micromips
);
11441 gas_assert (mips_opts
.insn32
);
11442 macro_build (NULL
, "jr", "s", op
[0]);
11443 if (mips_opts
.noreorder
)
11444 macro_build (NULL
, "nop", "");
11449 load_register (op
[0], &imm_expr
, 0);
11453 load_register (op
[0], &imm_expr
, 1);
11457 if (imm_expr
.X_op
== O_constant
)
11460 load_register (AT
, &imm_expr
, 0);
11461 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11466 gas_assert (imm_expr
.X_op
== O_absent
11467 && offset_expr
.X_op
== O_symbol
11468 && strcmp (segment_name (S_GET_SEGMENT
11469 (offset_expr
.X_add_symbol
)),
11471 && offset_expr
.X_add_number
== 0);
11472 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11473 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11478 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11479 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11480 order 32 bits of the value and the low order 32 bits are either
11481 zero or in OFFSET_EXPR. */
11482 if (imm_expr
.X_op
== O_constant
)
11484 if (HAVE_64BIT_GPRS
)
11485 load_register (op
[0], &imm_expr
, 1);
11490 if (target_big_endian
)
11502 load_register (hreg
, &imm_expr
, 0);
11505 if (offset_expr
.X_op
== O_absent
)
11506 move_register (lreg
, 0);
11509 gas_assert (offset_expr
.X_op
== O_constant
);
11510 load_register (lreg
, &offset_expr
, 0);
11516 gas_assert (imm_expr
.X_op
== O_absent
);
11518 /* We know that sym is in the .rdata section. First we get the
11519 upper 16 bits of the address. */
11520 if (mips_pic
== NO_PIC
)
11522 macro_build_lui (&offset_expr
, AT
);
11527 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11528 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11532 /* Now we load the register(s). */
11533 if (HAVE_64BIT_GPRS
)
11536 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11537 BFD_RELOC_LO16
, AT
);
11542 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11543 BFD_RELOC_LO16
, AT
);
11546 /* FIXME: How in the world do we deal with the possible
11548 offset_expr
.X_add_number
+= 4;
11549 macro_build (&offset_expr
, "lw", "t,o(b)",
11550 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11556 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11557 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11558 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11559 the value and the low order 32 bits are either zero or in
11561 if (imm_expr
.X_op
== O_constant
)
11564 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11565 if (HAVE_64BIT_FPRS
)
11567 gas_assert (HAVE_64BIT_GPRS
);
11568 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11572 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11573 if (offset_expr
.X_op
== O_absent
)
11574 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11577 gas_assert (offset_expr
.X_op
== O_constant
);
11578 load_register (AT
, &offset_expr
, 0);
11579 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11585 gas_assert (imm_expr
.X_op
== O_absent
11586 && offset_expr
.X_op
== O_symbol
11587 && offset_expr
.X_add_number
== 0);
11588 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11589 if (strcmp (s
, ".lit8") == 0)
11591 op
[2] = mips_gp_register
;
11592 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11593 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11594 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11598 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11600 if (mips_pic
!= NO_PIC
)
11601 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11602 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11605 /* FIXME: This won't work for a 64 bit address. */
11606 macro_build_lui (&offset_expr
, AT
);
11610 offset_reloc
[0] = BFD_RELOC_LO16
;
11611 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11612 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11619 * The MIPS assembler seems to check for X_add_number not
11620 * being double aligned and generating:
11621 * lui at,%hi(foo+1)
11623 * addiu at,at,%lo(foo+1)
11626 * But, the resulting address is the same after relocation so why
11627 * generate the extra instruction?
11629 /* Itbl support may require additional care here. */
11632 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11641 gas_assert (!mips_opts
.micromips
);
11642 /* Itbl support may require additional care here. */
11645 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11665 if (HAVE_64BIT_GPRS
)
11675 if (HAVE_64BIT_GPRS
)
11683 /* Even on a big endian machine $fn comes before $fn+1. We have
11684 to adjust when loading from memory. We set coproc if we must
11685 load $fn+1 first. */
11686 /* Itbl support may require additional care here. */
11687 if (!target_big_endian
)
11691 if (small_offset_p (0, align
, 16))
11694 if (!small_offset_p (4, align
, 16))
11696 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11697 -1, offset_reloc
[0], offset_reloc
[1],
11699 expr1
.X_add_number
= 0;
11703 offset_reloc
[0] = BFD_RELOC_LO16
;
11704 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11705 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11707 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11709 ep
->X_add_number
+= 4;
11710 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11711 offset_reloc
[1], offset_reloc
[2], breg
);
11712 ep
->X_add_number
-= 4;
11713 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11714 offset_reloc
[1], offset_reloc
[2], breg
);
11718 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11719 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11721 ep
->X_add_number
+= 4;
11722 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11723 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11729 if (offset_expr
.X_op
!= O_symbol
11730 && offset_expr
.X_op
!= O_constant
)
11732 as_bad (_("expression too complex"));
11733 offset_expr
.X_op
= O_constant
;
11736 if (HAVE_32BIT_ADDRESSES
11737 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11741 sprintf_vma (value
, offset_expr
.X_add_number
);
11742 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11745 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11747 /* If this is a reference to a GP relative symbol, we want
11748 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11749 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11750 If we have a base register, we use this
11752 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11753 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11754 If this is not a GP relative symbol, we want
11755 lui $at,<sym> (BFD_RELOC_HI16_S)
11756 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11757 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11758 If there is a base register, we add it to $at after the
11759 lui instruction. If there is a constant, we always use
11761 if (offset_expr
.X_op
== O_symbol
11762 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11763 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11765 relax_start (offset_expr
.X_add_symbol
);
11768 tempreg
= mips_gp_register
;
11772 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11773 AT
, breg
, mips_gp_register
);
11778 /* Itbl support may require additional care here. */
11779 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11780 BFD_RELOC_GPREL16
, tempreg
);
11781 offset_expr
.X_add_number
+= 4;
11783 /* Set mips_optimize to 2 to avoid inserting an
11785 hold_mips_optimize
= mips_optimize
;
11787 /* Itbl support may require additional care here. */
11788 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11789 BFD_RELOC_GPREL16
, tempreg
);
11790 mips_optimize
= hold_mips_optimize
;
11794 offset_expr
.X_add_number
-= 4;
11797 if (offset_high_part (offset_expr
.X_add_number
, 16)
11798 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11800 load_address (AT
, &offset_expr
, &used_at
);
11801 offset_expr
.X_op
= O_constant
;
11802 offset_expr
.X_add_number
= 0;
11805 macro_build_lui (&offset_expr
, AT
);
11807 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11808 /* Itbl support may require additional care here. */
11809 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11810 BFD_RELOC_LO16
, AT
);
11811 /* FIXME: How do we handle overflow here? */
11812 offset_expr
.X_add_number
+= 4;
11813 /* Itbl support may require additional care here. */
11814 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11815 BFD_RELOC_LO16
, AT
);
11816 if (mips_relax
.sequence
)
11819 else if (!mips_big_got
)
11821 /* If this is a reference to an external symbol, we want
11822 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11825 <op> op[0]+1,4($at)
11827 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11829 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11830 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11831 If there is a base register we add it to $at before the
11832 lwc1 instructions. If there is a constant we include it
11833 in the lwc1 instructions. */
11835 expr1
.X_add_number
= offset_expr
.X_add_number
;
11836 if (expr1
.X_add_number
< -0x8000
11837 || expr1
.X_add_number
>= 0x8000 - 4)
11838 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11839 load_got_offset (AT
, &offset_expr
);
11842 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11844 /* Set mips_optimize to 2 to avoid inserting an undesired
11846 hold_mips_optimize
= mips_optimize
;
11849 /* Itbl support may require additional care here. */
11850 relax_start (offset_expr
.X_add_symbol
);
11851 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11852 BFD_RELOC_LO16
, AT
);
11853 expr1
.X_add_number
+= 4;
11854 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11855 BFD_RELOC_LO16
, AT
);
11857 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11858 BFD_RELOC_LO16
, AT
);
11859 offset_expr
.X_add_number
+= 4;
11860 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11861 BFD_RELOC_LO16
, AT
);
11864 mips_optimize
= hold_mips_optimize
;
11866 else if (mips_big_got
)
11870 /* If this is a reference to an external symbol, we want
11871 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11873 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11876 <op> op[0]+1,4($at)
11878 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11880 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11881 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11882 If there is a base register we add it to $at before the
11883 lwc1 instructions. If there is a constant we include it
11884 in the lwc1 instructions. */
11886 expr1
.X_add_number
= offset_expr
.X_add_number
;
11887 offset_expr
.X_add_number
= 0;
11888 if (expr1
.X_add_number
< -0x8000
11889 || expr1
.X_add_number
>= 0x8000 - 4)
11890 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11891 gpdelay
= reg_needs_delay (mips_gp_register
);
11892 relax_start (offset_expr
.X_add_symbol
);
11893 macro_build (&offset_expr
, "lui", LUI_FMT
,
11894 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11895 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11896 AT
, AT
, mips_gp_register
);
11897 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11898 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11901 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11902 /* Itbl support may require additional care here. */
11903 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11904 BFD_RELOC_LO16
, AT
);
11905 expr1
.X_add_number
+= 4;
11907 /* Set mips_optimize to 2 to avoid inserting an undesired
11909 hold_mips_optimize
= mips_optimize
;
11911 /* Itbl support may require additional care here. */
11912 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11913 BFD_RELOC_LO16
, AT
);
11914 mips_optimize
= hold_mips_optimize
;
11915 expr1
.X_add_number
-= 4;
11918 offset_expr
.X_add_number
= expr1
.X_add_number
;
11920 macro_build (NULL
, "nop", "");
11921 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11922 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11926 /* Itbl support may require additional care here. */
11927 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11928 BFD_RELOC_LO16
, AT
);
11929 offset_expr
.X_add_number
+= 4;
11931 /* Set mips_optimize to 2 to avoid inserting an undesired
11933 hold_mips_optimize
= mips_optimize
;
11935 /* Itbl support may require additional care here. */
11936 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11937 BFD_RELOC_LO16
, AT
);
11938 mips_optimize
= hold_mips_optimize
;
11957 /* New code added to support COPZ instructions.
11958 This code builds table entries out of the macros in mip_opcodes.
11959 R4000 uses interlocks to handle coproc delays.
11960 Other chips (like the R3000) require nops to be inserted for delays.
11962 FIXME: Currently, we require that the user handle delays.
11963 In order to fill delay slots for non-interlocked chips,
11964 we must have a way to specify delays based on the coprocessor.
11965 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11966 What are the side-effects of the cop instruction?
11967 What cache support might we have and what are its effects?
11968 Both coprocessor & memory require delays. how long???
11969 What registers are read/set/modified?
11971 If an itbl is provided to interpret cop instructions,
11972 this knowledge can be encoded in the itbl spec. */
11986 gas_assert (!mips_opts
.micromips
);
11987 /* For now we just do C (same as Cz). The parameter will be
11988 stored in insn_opcode by mips_ip. */
11989 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11993 move_register (op
[0], op
[1]);
11997 gas_assert (mips_opts
.micromips
);
11998 gas_assert (mips_opts
.insn32
);
11999 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12000 micromips_to_32_reg_m_map
[op
[1]]);
12001 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12002 micromips_to_32_reg_n_map
[op
[2]]);
12008 if (mips_opts
.arch
== CPU_R5900
)
12009 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12013 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12014 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12021 /* The MIPS assembler some times generates shifts and adds. I'm
12022 not trying to be that fancy. GCC should do this for us
12025 load_register (AT
, &imm_expr
, dbl
);
12026 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12027 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12040 start_noreorder ();
12043 load_register (AT
, &imm_expr
, dbl
);
12044 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12045 op
[1], imm
? AT
: op
[2]);
12046 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12047 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12048 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12050 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12053 if (mips_opts
.micromips
)
12054 micromips_label_expr (&label_expr
);
12056 label_expr
.X_add_number
= 8;
12057 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12058 macro_build (NULL
, "nop", "");
12059 macro_build (NULL
, "break", BRK_FMT
, 6);
12060 if (mips_opts
.micromips
)
12061 micromips_add_label ();
12064 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12077 start_noreorder ();
12080 load_register (AT
, &imm_expr
, dbl
);
12081 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12082 op
[1], imm
? AT
: op
[2]);
12083 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12084 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12086 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12089 if (mips_opts
.micromips
)
12090 micromips_label_expr (&label_expr
);
12092 label_expr
.X_add_number
= 8;
12093 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12094 macro_build (NULL
, "nop", "");
12095 macro_build (NULL
, "break", BRK_FMT
, 6);
12096 if (mips_opts
.micromips
)
12097 micromips_add_label ();
12103 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12105 if (op
[0] == op
[1])
12112 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12113 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12117 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12118 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12119 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12120 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12124 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12126 if (op
[0] == op
[1])
12133 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12134 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12138 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12139 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12140 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12141 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12150 rot
= imm_expr
.X_add_number
& 0x3f;
12151 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12153 rot
= (64 - rot
) & 0x3f;
12155 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12157 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12162 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12165 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12166 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12169 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12170 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12171 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12179 rot
= imm_expr
.X_add_number
& 0x1f;
12180 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12182 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12183 (32 - rot
) & 0x1f);
12188 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12192 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12193 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12194 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12199 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12201 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12205 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12206 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12207 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12208 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12212 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12214 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12218 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12219 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12220 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12221 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12230 rot
= imm_expr
.X_add_number
& 0x3f;
12231 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12234 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12236 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12241 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12244 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12245 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12248 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12249 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12250 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12258 rot
= imm_expr
.X_add_number
& 0x1f;
12259 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12261 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12266 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12270 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12271 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12272 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12278 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12279 else if (op
[2] == 0)
12280 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12283 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12284 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12289 if (imm_expr
.X_add_number
== 0)
12291 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12296 as_warn (_("instruction %s: result is always false"),
12297 ip
->insn_mo
->name
);
12298 move_register (op
[0], 0);
12301 if (CPU_HAS_SEQ (mips_opts
.arch
)
12302 && -512 <= imm_expr
.X_add_number
12303 && imm_expr
.X_add_number
< 512)
12305 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12306 (int) imm_expr
.X_add_number
);
12309 if (imm_expr
.X_add_number
>= 0
12310 && imm_expr
.X_add_number
< 0x10000)
12311 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12312 else if (imm_expr
.X_add_number
> -0x8000
12313 && imm_expr
.X_add_number
< 0)
12315 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12316 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12317 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12319 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12322 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12323 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12328 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12329 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12332 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12335 case M_SGE
: /* X >= Y <==> not (X < Y) */
12341 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12342 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12345 case M_SGE_I
: /* X >= I <==> not (X < I) */
12347 if (imm_expr
.X_add_number
>= -0x8000
12348 && imm_expr
.X_add_number
< 0x8000)
12349 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12350 op
[0], op
[1], BFD_RELOC_LO16
);
12353 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12354 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12358 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12361 case M_SGT
: /* X > Y <==> Y < X */
12367 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12370 case M_SGT_I
: /* X > I <==> I < X */
12377 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12378 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12381 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12387 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12388 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12391 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12398 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12399 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12400 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12404 if (imm_expr
.X_add_number
>= -0x8000
12405 && imm_expr
.X_add_number
< 0x8000)
12407 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12412 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12413 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12417 if (imm_expr
.X_add_number
>= -0x8000
12418 && imm_expr
.X_add_number
< 0x8000)
12420 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12425 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12426 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12431 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12432 else if (op
[2] == 0)
12433 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12436 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12437 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12442 if (imm_expr
.X_add_number
== 0)
12444 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12449 as_warn (_("instruction %s: result is always true"),
12450 ip
->insn_mo
->name
);
12451 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12452 op
[0], 0, BFD_RELOC_LO16
);
12455 if (CPU_HAS_SEQ (mips_opts
.arch
)
12456 && -512 <= imm_expr
.X_add_number
12457 && imm_expr
.X_add_number
< 512)
12459 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12460 (int) imm_expr
.X_add_number
);
12463 if (imm_expr
.X_add_number
>= 0
12464 && imm_expr
.X_add_number
< 0x10000)
12466 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12469 else if (imm_expr
.X_add_number
> -0x8000
12470 && imm_expr
.X_add_number
< 0)
12472 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12473 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12474 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12476 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12479 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12480 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12485 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12486 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12489 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12504 if (!mips_opts
.micromips
)
12506 if (imm_expr
.X_add_number
> -0x200
12507 && imm_expr
.X_add_number
<= 0x200)
12509 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
12510 (int) -imm_expr
.X_add_number
);
12519 if (imm_expr
.X_add_number
> -0x8000
12520 && imm_expr
.X_add_number
<= 0x8000)
12522 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12523 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12528 load_register (AT
, &imm_expr
, dbl
);
12529 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12551 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12552 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12557 gas_assert (!mips_opts
.micromips
);
12558 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12562 * Is the double cfc1 instruction a bug in the mips assembler;
12563 * or is there a reason for it?
12565 start_noreorder ();
12566 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12567 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12568 macro_build (NULL
, "nop", "");
12569 expr1
.X_add_number
= 3;
12570 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12571 expr1
.X_add_number
= 2;
12572 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12573 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12574 macro_build (NULL
, "nop", "");
12575 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12577 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12578 macro_build (NULL
, "nop", "");
12595 offbits
= (mips_opts
.micromips
? 12 : 16);
12601 offbits
= (mips_opts
.micromips
? 12 : 16);
12613 offbits
= (mips_opts
.micromips
? 12 : 16);
12620 offbits
= (mips_opts
.micromips
? 12 : 16);
12626 large_offset
= !small_offset_p (off
, align
, offbits
);
12628 expr1
.X_add_number
= 0;
12633 if (small_offset_p (0, align
, 16))
12634 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12635 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12638 load_address (tempreg
, ep
, &used_at
);
12640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12641 tempreg
, tempreg
, breg
);
12643 offset_reloc
[0] = BFD_RELOC_LO16
;
12644 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12645 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12650 else if (!ust
&& op
[0] == breg
)
12661 if (!target_big_endian
)
12662 ep
->X_add_number
+= off
;
12664 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12666 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12667 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12669 if (!target_big_endian
)
12670 ep
->X_add_number
-= off
;
12672 ep
->X_add_number
+= off
;
12674 macro_build (NULL
, s2
, "t,~(b)",
12675 tempreg
, (int) ep
->X_add_number
, breg
);
12677 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12678 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12680 /* If necessary, move the result in tempreg to the final destination. */
12681 if (!ust
&& op
[0] != tempreg
)
12683 /* Protect second load's delay slot. */
12685 move_register (op
[0], tempreg
);
12691 if (target_big_endian
== ust
)
12692 ep
->X_add_number
+= off
;
12693 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12694 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12695 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12697 /* For halfword transfers we need a temporary register to shuffle
12698 bytes. Unfortunately for M_USH_A we have none available before
12699 the next store as AT holds the base address. We deal with this
12700 case by clobbering TREG and then restoring it as with ULH. */
12701 tempreg
= ust
== large_offset
? op
[0] : AT
;
12703 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12705 if (target_big_endian
== ust
)
12706 ep
->X_add_number
-= off
;
12708 ep
->X_add_number
+= off
;
12709 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12710 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12712 /* For M_USH_A re-retrieve the LSB. */
12713 if (ust
&& large_offset
)
12715 if (target_big_endian
)
12716 ep
->X_add_number
+= off
;
12718 ep
->X_add_number
-= off
;
12719 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12720 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12722 /* For ULH and M_USH_A OR the LSB in. */
12723 if (!ust
|| large_offset
)
12725 tempreg
= !large_offset
? AT
: op
[0];
12726 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12727 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12732 /* FIXME: Check if this is one of the itbl macros, since they
12733 are added dynamically. */
12734 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
12737 if (!mips_opts
.at
&& used_at
)
12738 as_bad (_("macro used $at after \".set noat\""));
12741 /* Implement macros in mips16 mode. */
12744 mips16_macro (struct mips_cl_insn
*ip
)
12746 const struct mips_operand_array
*operands
;
12751 const char *s
, *s2
, *s3
;
12752 unsigned int op
[MAX_OPERANDS
];
12755 mask
= ip
->insn_mo
->mask
;
12757 operands
= insn_operands (ip
);
12758 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12759 if (operands
->operand
[i
])
12760 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12764 expr1
.X_op
= O_constant
;
12765 expr1
.X_op_symbol
= NULL
;
12766 expr1
.X_add_symbol
= NULL
;
12767 expr1
.X_add_number
= 1;
12786 start_noreorder ();
12787 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12788 expr1
.X_add_number
= 2;
12789 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12790 macro_build (NULL
, "break", "6", 7);
12792 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12793 since that causes an overflow. We should do that as well,
12794 but I don't see how to do the comparisons without a temporary
12797 macro_build (NULL
, s
, "x", op
[0]);
12816 start_noreorder ();
12817 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12818 expr1
.X_add_number
= 2;
12819 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12820 macro_build (NULL
, "break", "6", 7);
12822 macro_build (NULL
, s2
, "x", op
[0]);
12828 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12829 macro_build (NULL
, "mflo", "x", op
[0]);
12837 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12838 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12842 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12843 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12847 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12848 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12870 goto do_reverse_branch
;
12874 goto do_reverse_branch
;
12886 goto do_reverse_branch
;
12897 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12898 macro_build (&offset_expr
, s2
, "p");
12925 goto do_addone_branch_i
;
12930 goto do_addone_branch_i
;
12945 goto do_addone_branch_i
;
12951 do_addone_branch_i
:
12952 ++imm_expr
.X_add_number
;
12955 macro_build (&imm_expr
, s
, s3
, op
[0]);
12956 macro_build (&offset_expr
, s2
, "p");
12960 expr1
.X_add_number
= 0;
12961 macro_build (&expr1
, "slti", "x,8", op
[1]);
12962 if (op
[0] != op
[1])
12963 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12964 expr1
.X_add_number
= 2;
12965 macro_build (&expr1
, "bteqz", "p");
12966 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12971 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12972 opcode bits in *OPCODE_EXTRA. */
12974 static struct mips_opcode
*
12975 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12976 ssize_t length
, unsigned int *opcode_extra
)
12978 char *name
, *dot
, *p
;
12979 unsigned int mask
, suffix
;
12981 struct mips_opcode
*insn
;
12983 /* Make a copy of the instruction so that we can fiddle with it. */
12984 name
= alloca (length
+ 1);
12985 memcpy (name
, start
, length
);
12986 name
[length
] = '\0';
12988 /* Look up the instruction as-is. */
12989 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12993 dot
= strchr (name
, '.');
12996 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12997 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12998 if (*p
== 0 && mask
!= 0)
13001 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13003 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13005 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13011 if (mips_opts
.micromips
)
13013 /* See if there's an instruction size override suffix,
13014 either `16' or `32', at the end of the mnemonic proper,
13015 that defines the operation, i.e. before the first `.'
13016 character if any. Strip it and retry. */
13017 opend
= dot
!= NULL
? dot
- name
: length
;
13018 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13020 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13026 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13027 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13030 forced_insn_length
= suffix
;
13039 /* Assemble an instruction into its binary format. If the instruction
13040 is a macro, set imm_expr and offset_expr to the values associated
13041 with "I" and "A" operands respectively. Otherwise store the value
13042 of the relocatable field (if any) in offset_expr. In both cases
13043 set offset_reloc to the relocation operators applied to offset_expr. */
13046 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13048 const struct mips_opcode
*first
, *past
;
13049 struct hash_control
*hash
;
13052 struct mips_operand_token
*tokens
;
13053 unsigned int opcode_extra
;
13055 if (mips_opts
.micromips
)
13057 hash
= micromips_op_hash
;
13058 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13063 past
= &mips_opcodes
[NUMOPCODES
];
13065 forced_insn_length
= 0;
13068 /* We first try to match an instruction up to a space or to the end. */
13069 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13072 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13075 set_insn_error (0, _("unrecognized opcode"));
13079 if (strcmp (first
->name
, "li.s") == 0)
13081 else if (strcmp (first
->name
, "li.d") == 0)
13085 tokens
= mips_parse_arguments (str
+ end
, format
);
13089 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13090 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13091 set_insn_error (0, _("invalid operands"));
13093 obstack_free (&mips_operand_tokens
, tokens
);
13096 /* As for mips_ip, but used when assembling MIPS16 code.
13097 Also set forced_insn_length to the resulting instruction size in
13098 bytes if the user explicitly requested a small or extended instruction. */
13101 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13104 struct mips_opcode
*first
;
13105 struct mips_operand_token
*tokens
;
13107 forced_insn_length
= 0;
13109 for (s
= str
; ISLOWER (*s
); ++s
)
13123 if (s
[1] == 't' && s
[2] == ' ')
13125 forced_insn_length
= 2;
13129 else if (s
[1] == 'e' && s
[2] == ' ')
13131 forced_insn_length
= 4;
13135 /* Fall through. */
13137 set_insn_error (0, _("unrecognized opcode"));
13141 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13142 forced_insn_length
= 2;
13145 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13150 set_insn_error (0, _("unrecognized opcode"));
13154 tokens
= mips_parse_arguments (s
, 0);
13158 if (!match_mips16_insns (insn
, first
, tokens
))
13159 set_insn_error (0, _("invalid operands"));
13161 obstack_free (&mips_operand_tokens
, tokens
);
13164 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13165 NBITS is the number of significant bits in VAL. */
13167 static unsigned long
13168 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13173 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13176 else if (nbits
== 15)
13178 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13183 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13186 return (extval
<< 16) | val
;
13189 /* Like decode_mips16_operand, but require the operand to be defined and
13190 require it to be an integer. */
13192 static const struct mips_int_operand
*
13193 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13195 const struct mips_operand
*operand
;
13197 operand
= decode_mips16_operand (type
, extended_p
);
13198 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13200 return (const struct mips_int_operand
*) operand
;
13203 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13206 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13207 bfd_reloc_code_real_type reloc
, offsetT sval
)
13209 int min_val
, max_val
;
13211 min_val
= mips_int_operand_min (operand
);
13212 max_val
= mips_int_operand_max (operand
);
13213 if (reloc
!= BFD_RELOC_UNUSED
)
13216 sval
= SEXT_16BIT (sval
);
13221 return (sval
>= min_val
13223 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13226 /* Install immediate value VAL into MIPS16 instruction *INSN,
13227 extending it if necessary. The instruction in *INSN may
13228 already be extended.
13230 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13231 if none. In the former case, VAL is a 16-bit number with no
13232 defined signedness.
13234 TYPE is the type of the immediate field. USER_INSN_LENGTH
13235 is the length that the user requested, or 0 if none. */
13238 mips16_immed (char *file
, unsigned int line
, int type
,
13239 bfd_reloc_code_real_type reloc
, offsetT val
,
13240 unsigned int user_insn_length
, unsigned long *insn
)
13242 const struct mips_int_operand
*operand
;
13243 unsigned int uval
, length
;
13245 operand
= mips16_immed_operand (type
, FALSE
);
13246 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13248 /* We need an extended instruction. */
13249 if (user_insn_length
== 2)
13250 as_bad_where (file
, line
, _("invalid unextended operand value"));
13252 *insn
|= MIPS16_EXTEND
;
13254 else if (user_insn_length
== 4)
13256 /* The operand doesn't force an unextended instruction to be extended.
13257 Warn if the user wanted an extended instruction anyway. */
13258 *insn
|= MIPS16_EXTEND
;
13259 as_warn_where (file
, line
,
13260 _("extended operand requested but not required"));
13263 length
= mips16_opcode_length (*insn
);
13266 operand
= mips16_immed_operand (type
, TRUE
);
13267 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13268 as_bad_where (file
, line
,
13269 _("operand value out of range for instruction"));
13271 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13273 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13275 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13278 struct percent_op_match
13281 bfd_reloc_code_real_type reloc
;
13284 static const struct percent_op_match mips_percent_op
[] =
13286 {"%lo", BFD_RELOC_LO16
},
13287 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13288 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13289 {"%call16", BFD_RELOC_MIPS_CALL16
},
13290 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13291 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13292 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13293 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13294 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13295 {"%got", BFD_RELOC_MIPS_GOT16
},
13296 {"%gp_rel", BFD_RELOC_GPREL16
},
13297 {"%half", BFD_RELOC_16
},
13298 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13299 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13300 {"%neg", BFD_RELOC_MIPS_SUB
},
13301 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13302 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13303 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13304 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13305 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13306 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13307 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13308 {"%hi", BFD_RELOC_HI16_S
}
13311 static const struct percent_op_match mips16_percent_op
[] =
13313 {"%lo", BFD_RELOC_MIPS16_LO16
},
13314 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13315 {"%got", BFD_RELOC_MIPS16_GOT16
},
13316 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13317 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13318 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13319 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13320 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13321 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13322 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13323 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13324 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13328 /* Return true if *STR points to a relocation operator. When returning true,
13329 move *STR over the operator and store its relocation code in *RELOC.
13330 Leave both *STR and *RELOC alone when returning false. */
13333 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13335 const struct percent_op_match
*percent_op
;
13338 if (mips_opts
.mips16
)
13340 percent_op
= mips16_percent_op
;
13341 limit
= ARRAY_SIZE (mips16_percent_op
);
13345 percent_op
= mips_percent_op
;
13346 limit
= ARRAY_SIZE (mips_percent_op
);
13349 for (i
= 0; i
< limit
; i
++)
13350 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13352 int len
= strlen (percent_op
[i
].str
);
13354 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13357 *str
+= strlen (percent_op
[i
].str
);
13358 *reloc
= percent_op
[i
].reloc
;
13360 /* Check whether the output BFD supports this relocation.
13361 If not, issue an error and fall back on something safe. */
13362 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13364 as_bad (_("relocation %s isn't supported by the current ABI"),
13365 percent_op
[i
].str
);
13366 *reloc
= BFD_RELOC_UNUSED
;
13374 /* Parse string STR as a 16-bit relocatable operand. Store the
13375 expression in *EP and the relocations in the array starting
13376 at RELOC. Return the number of relocation operators used.
13378 On exit, EXPR_END points to the first character after the expression. */
13381 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13384 bfd_reloc_code_real_type reversed_reloc
[3];
13385 size_t reloc_index
, i
;
13386 int crux_depth
, str_depth
;
13389 /* Search for the start of the main expression, recoding relocations
13390 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13391 of the main expression and with CRUX_DEPTH containing the number
13392 of open brackets at that point. */
13399 crux_depth
= str_depth
;
13401 /* Skip over whitespace and brackets, keeping count of the number
13403 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13408 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13409 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13411 my_getExpression (ep
, crux
);
13414 /* Match every open bracket. */
13415 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13419 if (crux_depth
> 0)
13420 as_bad (_("unclosed '('"));
13424 if (reloc_index
!= 0)
13426 prev_reloc_op_frag
= frag_now
;
13427 for (i
= 0; i
< reloc_index
; i
++)
13428 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13431 return reloc_index
;
13435 my_getExpression (expressionS
*ep
, char *str
)
13439 save_in
= input_line_pointer
;
13440 input_line_pointer
= str
;
13442 expr_end
= input_line_pointer
;
13443 input_line_pointer
= save_in
;
13447 md_atof (int type
, char *litP
, int *sizeP
)
13449 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13453 md_number_to_chars (char *buf
, valueT val
, int n
)
13455 if (target_big_endian
)
13456 number_to_chars_bigendian (buf
, val
, n
);
13458 number_to_chars_littleendian (buf
, val
, n
);
13461 static int support_64bit_objects(void)
13463 const char **list
, **l
;
13466 list
= bfd_target_list ();
13467 for (l
= list
; *l
!= NULL
; l
++)
13468 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13469 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13471 yes
= (*l
!= NULL
);
13476 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13477 NEW_VALUE. Warn if another value was already specified. Note:
13478 we have to defer parsing the -march and -mtune arguments in order
13479 to handle 'from-abi' correctly, since the ABI might be specified
13480 in a later argument. */
13483 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13485 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13486 as_warn (_("a different %s was already specified, is now %s"),
13487 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13490 *string_ptr
= new_value
;
13494 md_parse_option (int c
, char *arg
)
13498 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13499 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13501 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13502 c
== mips_ases
[i
].option_on
);
13508 case OPTION_CONSTRUCT_FLOATS
:
13509 mips_disable_float_construction
= 0;
13512 case OPTION_NO_CONSTRUCT_FLOATS
:
13513 mips_disable_float_construction
= 1;
13525 target_big_endian
= 1;
13529 target_big_endian
= 0;
13535 else if (arg
[0] == '0')
13537 else if (arg
[0] == '1')
13547 mips_debug
= atoi (arg
);
13551 file_mips_isa
= ISA_MIPS1
;
13555 file_mips_isa
= ISA_MIPS2
;
13559 file_mips_isa
= ISA_MIPS3
;
13563 file_mips_isa
= ISA_MIPS4
;
13567 file_mips_isa
= ISA_MIPS5
;
13570 case OPTION_MIPS32
:
13571 file_mips_isa
= ISA_MIPS32
;
13574 case OPTION_MIPS32R2
:
13575 file_mips_isa
= ISA_MIPS32R2
;
13578 case OPTION_MIPS32R3
:
13579 file_mips_isa
= ISA_MIPS32R3
;
13582 case OPTION_MIPS32R5
:
13583 file_mips_isa
= ISA_MIPS32R5
;
13586 case OPTION_MIPS64R2
:
13587 file_mips_isa
= ISA_MIPS64R2
;
13590 case OPTION_MIPS64R3
:
13591 file_mips_isa
= ISA_MIPS64R3
;
13594 case OPTION_MIPS64R5
:
13595 file_mips_isa
= ISA_MIPS64R5
;
13598 case OPTION_MIPS64
:
13599 file_mips_isa
= ISA_MIPS64
;
13603 mips_set_option_string (&mips_tune_string
, arg
);
13607 mips_set_option_string (&mips_arch_string
, arg
);
13611 mips_set_option_string (&mips_arch_string
, "4650");
13612 mips_set_option_string (&mips_tune_string
, "4650");
13615 case OPTION_NO_M4650
:
13619 mips_set_option_string (&mips_arch_string
, "4010");
13620 mips_set_option_string (&mips_tune_string
, "4010");
13623 case OPTION_NO_M4010
:
13627 mips_set_option_string (&mips_arch_string
, "4100");
13628 mips_set_option_string (&mips_tune_string
, "4100");
13631 case OPTION_NO_M4100
:
13635 mips_set_option_string (&mips_arch_string
, "3900");
13636 mips_set_option_string (&mips_tune_string
, "3900");
13639 case OPTION_NO_M3900
:
13642 case OPTION_MICROMIPS
:
13643 if (mips_opts
.mips16
== 1)
13645 as_bad (_("-mmicromips cannot be used with -mips16"));
13648 mips_opts
.micromips
= 1;
13649 mips_no_prev_insn ();
13652 case OPTION_NO_MICROMIPS
:
13653 mips_opts
.micromips
= 0;
13654 mips_no_prev_insn ();
13657 case OPTION_MIPS16
:
13658 if (mips_opts
.micromips
== 1)
13660 as_bad (_("-mips16 cannot be used with -micromips"));
13663 mips_opts
.mips16
= 1;
13664 mips_no_prev_insn ();
13667 case OPTION_NO_MIPS16
:
13668 mips_opts
.mips16
= 0;
13669 mips_no_prev_insn ();
13672 case OPTION_FIX_24K
:
13676 case OPTION_NO_FIX_24K
:
13680 case OPTION_FIX_RM7000
:
13681 mips_fix_rm7000
= 1;
13684 case OPTION_NO_FIX_RM7000
:
13685 mips_fix_rm7000
= 0;
13688 case OPTION_FIX_LOONGSON2F_JUMP
:
13689 mips_fix_loongson2f_jump
= TRUE
;
13692 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13693 mips_fix_loongson2f_jump
= FALSE
;
13696 case OPTION_FIX_LOONGSON2F_NOP
:
13697 mips_fix_loongson2f_nop
= TRUE
;
13700 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13701 mips_fix_loongson2f_nop
= FALSE
;
13704 case OPTION_FIX_VR4120
:
13705 mips_fix_vr4120
= 1;
13708 case OPTION_NO_FIX_VR4120
:
13709 mips_fix_vr4120
= 0;
13712 case OPTION_FIX_VR4130
:
13713 mips_fix_vr4130
= 1;
13716 case OPTION_NO_FIX_VR4130
:
13717 mips_fix_vr4130
= 0;
13720 case OPTION_FIX_CN63XXP1
:
13721 mips_fix_cn63xxp1
= TRUE
;
13724 case OPTION_NO_FIX_CN63XXP1
:
13725 mips_fix_cn63xxp1
= FALSE
;
13728 case OPTION_RELAX_BRANCH
:
13729 mips_relax_branch
= 1;
13732 case OPTION_NO_RELAX_BRANCH
:
13733 mips_relax_branch
= 0;
13736 case OPTION_INSN32
:
13737 mips_opts
.insn32
= TRUE
;
13740 case OPTION_NO_INSN32
:
13741 mips_opts
.insn32
= FALSE
;
13744 case OPTION_MSHARED
:
13745 mips_in_shared
= TRUE
;
13748 case OPTION_MNO_SHARED
:
13749 mips_in_shared
= FALSE
;
13752 case OPTION_MSYM32
:
13753 mips_opts
.sym32
= TRUE
;
13756 case OPTION_MNO_SYM32
:
13757 mips_opts
.sym32
= FALSE
;
13760 /* When generating ELF code, we permit -KPIC and -call_shared to
13761 select SVR4_PIC, and -non_shared to select no PIC. This is
13762 intended to be compatible with Irix 5. */
13763 case OPTION_CALL_SHARED
:
13764 mips_pic
= SVR4_PIC
;
13765 mips_abicalls
= TRUE
;
13768 case OPTION_CALL_NONPIC
:
13770 mips_abicalls
= TRUE
;
13773 case OPTION_NON_SHARED
:
13775 mips_abicalls
= FALSE
;
13778 /* The -xgot option tells the assembler to use 32 bit offsets
13779 when accessing the got in SVR4_PIC mode. It is for Irix
13786 g_switch_value
= atoi (arg
);
13790 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13793 mips_abi
= O32_ABI
;
13797 mips_abi
= N32_ABI
;
13801 mips_abi
= N64_ABI
;
13802 if (!support_64bit_objects())
13803 as_fatal (_("no compiled in support for 64 bit object file format"));
13807 file_mips_gp32
= 1;
13811 file_mips_gp32
= 0;
13815 file_mips_fp32
= 1;
13819 file_mips_fp32
= 0;
13822 case OPTION_SINGLE_FLOAT
:
13823 file_mips_single_float
= 1;
13826 case OPTION_DOUBLE_FLOAT
:
13827 file_mips_single_float
= 0;
13830 case OPTION_SOFT_FLOAT
:
13831 file_mips_soft_float
= 1;
13834 case OPTION_HARD_FLOAT
:
13835 file_mips_soft_float
= 0;
13839 if (strcmp (arg
, "32") == 0)
13840 mips_abi
= O32_ABI
;
13841 else if (strcmp (arg
, "o64") == 0)
13842 mips_abi
= O64_ABI
;
13843 else if (strcmp (arg
, "n32") == 0)
13844 mips_abi
= N32_ABI
;
13845 else if (strcmp (arg
, "64") == 0)
13847 mips_abi
= N64_ABI
;
13848 if (! support_64bit_objects())
13849 as_fatal (_("no compiled in support for 64 bit object file "
13852 else if (strcmp (arg
, "eabi") == 0)
13853 mips_abi
= EABI_ABI
;
13856 as_fatal (_("invalid abi -mabi=%s"), arg
);
13861 case OPTION_M7000_HILO_FIX
:
13862 mips_7000_hilo_fix
= TRUE
;
13865 case OPTION_MNO_7000_HILO_FIX
:
13866 mips_7000_hilo_fix
= FALSE
;
13869 case OPTION_MDEBUG
:
13870 mips_flag_mdebug
= TRUE
;
13873 case OPTION_NO_MDEBUG
:
13874 mips_flag_mdebug
= FALSE
;
13878 mips_flag_pdr
= TRUE
;
13881 case OPTION_NO_PDR
:
13882 mips_flag_pdr
= FALSE
;
13885 case OPTION_MVXWORKS_PIC
:
13886 mips_pic
= VXWORKS_PIC
;
13890 if (strcmp (arg
, "2008") == 0)
13891 mips_flag_nan2008
= TRUE
;
13892 else if (strcmp (arg
, "legacy") == 0)
13893 mips_flag_nan2008
= FALSE
;
13896 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
13905 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13910 /* Set up globals to generate code for the ISA or processor
13911 described by INFO. */
13914 mips_set_architecture (const struct mips_cpu_info
*info
)
13918 file_mips_arch
= info
->cpu
;
13919 mips_opts
.arch
= info
->cpu
;
13920 mips_opts
.isa
= info
->isa
;
13925 /* Likewise for tuning. */
13928 mips_set_tune (const struct mips_cpu_info
*info
)
13931 mips_tune
= info
->cpu
;
13936 mips_after_parse_args (void)
13938 const struct mips_cpu_info
*arch_info
= 0;
13939 const struct mips_cpu_info
*tune_info
= 0;
13941 /* GP relative stuff not working for PE */
13942 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13944 if (g_switch_seen
&& g_switch_value
!= 0)
13945 as_bad (_("-G not supported in this configuration"));
13946 g_switch_value
= 0;
13949 if (mips_abi
== NO_ABI
)
13950 mips_abi
= MIPS_DEFAULT_ABI
;
13952 /* The following code determines the architecture and register size.
13953 Similar code was added to GCC 3.3 (see override_options() in
13954 config/mips/mips.c). The GAS and GCC code should be kept in sync
13955 as much as possible. */
13957 if (mips_arch_string
!= 0)
13958 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13960 if (file_mips_isa
!= ISA_UNKNOWN
)
13962 /* Handle -mipsN. At this point, file_mips_isa contains the
13963 ISA level specified by -mipsN, while arch_info->isa contains
13964 the -march selection (if any). */
13965 if (arch_info
!= 0)
13967 /* -march takes precedence over -mipsN, since it is more descriptive.
13968 There's no harm in specifying both as long as the ISA levels
13970 if (file_mips_isa
!= arch_info
->isa
)
13971 as_bad (_("-%s conflicts with the other architecture options,"
13972 " which imply -%s"),
13973 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13974 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13977 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13980 if (arch_info
== 0)
13982 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13983 gas_assert (arch_info
);
13986 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13987 as_bad (_("-march=%s is not compatible with the selected ABI"),
13990 mips_set_architecture (arch_info
);
13992 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13993 if (mips_tune_string
!= 0)
13994 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13996 if (tune_info
== 0)
13997 mips_set_tune (arch_info
);
13999 mips_set_tune (tune_info
);
14001 if (file_mips_gp32
>= 0)
14003 /* The user specified the size of the integer registers. Make sure
14004 it agrees with the ABI and ISA. */
14005 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14006 as_bad (_("-mgp64 used with a 32-bit processor"));
14007 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
14008 as_bad (_("-mgp32 used with a 64-bit ABI"));
14009 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
14010 as_bad (_("-mgp64 used with a 32-bit ABI"));
14014 /* Infer the integer register size from the ABI and processor.
14015 Restrict ourselves to 32-bit registers if that's all the
14016 processor has, or if the ABI cannot handle 64-bit registers. */
14017 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
14018 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
14021 switch (file_mips_fp32
)
14025 /* No user specified float register size.
14026 ??? GAS treats single-float processors as though they had 64-bit
14027 float registers (although it complains when double-precision
14028 instructions are used). As things stand, saying they have 32-bit
14029 registers would lead to spurious "register must be even" messages.
14030 So here we assume float registers are never smaller than the
14032 if (file_mips_gp32
== 0)
14033 /* 64-bit integer registers implies 64-bit float registers. */
14034 file_mips_fp32
= 0;
14035 else if ((mips_opts
.ase
& FP64_ASES
)
14036 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14037 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14038 file_mips_fp32
= 0;
14040 /* 32-bit float registers. */
14041 file_mips_fp32
= 1;
14044 /* The user specified the size of the float registers. Check if it
14045 agrees with the ABI and ISA. */
14047 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14048 as_bad (_("-mfp64 used with a 32-bit fpu"));
14049 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
14050 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
14051 as_warn (_("-mfp64 used with a 32-bit ABI"));
14054 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14055 as_warn (_("-mfp32 used with a 64-bit ABI"));
14059 /* End of GCC-shared inference code. */
14061 /* This flag is set when we have a 64-bit capable CPU but use only
14062 32-bit wide registers. Note that EABI does not use it. */
14063 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14064 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
14065 || mips_abi
== O32_ABI
))
14066 mips_32bitmode
= 1;
14068 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14069 as_bad (_("trap exception not supported at ISA 1"));
14071 /* If the selected architecture includes support for ASEs, enable
14072 generation of code for them. */
14073 if (mips_opts
.mips16
== -1)
14074 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
14075 if (mips_opts
.micromips
== -1)
14076 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
14078 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14079 ASEs from being selected implicitly. */
14080 if (file_mips_fp32
== 1)
14081 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
14083 /* If the user didn't explicitly select or deselect a particular ASE,
14084 use the default setting for the CPU. */
14085 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
14087 file_mips_isa
= mips_opts
.isa
;
14088 file_ase
= mips_opts
.ase
;
14089 mips_opts
.gp32
= file_mips_gp32
;
14090 mips_opts
.fp32
= file_mips_fp32
;
14091 mips_opts
.soft_float
= file_mips_soft_float
;
14092 mips_opts
.single_float
= file_mips_single_float
;
14094 mips_check_isa_supports_ases ();
14096 if (mips_flag_mdebug
< 0)
14097 mips_flag_mdebug
= 0;
14101 mips_init_after_args (void)
14103 /* initialize opcodes */
14104 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14105 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14109 md_pcrel_from (fixS
*fixP
)
14111 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14112 switch (fixP
->fx_r_type
)
14114 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14115 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14116 /* Return the address of the delay slot. */
14119 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14120 case BFD_RELOC_MICROMIPS_JMP
:
14121 case BFD_RELOC_16_PCREL_S2
:
14122 case BFD_RELOC_MIPS_JMP
:
14123 /* Return the address of the delay slot. */
14131 /* This is called before the symbol table is processed. In order to
14132 work with gcc when using mips-tfile, we must keep all local labels.
14133 However, in other cases, we want to discard them. If we were
14134 called with -g, but we didn't see any debugging information, it may
14135 mean that gcc is smuggling debugging information through to
14136 mips-tfile, in which case we must generate all local labels. */
14139 mips_frob_file_before_adjust (void)
14141 #ifndef NO_ECOFF_DEBUGGING
14142 if (ECOFF_DEBUGGING
14144 && ! ecoff_debugging_seen
)
14145 flag_keep_locals
= 1;
14149 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14150 the corresponding LO16 reloc. This is called before md_apply_fix and
14151 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14152 relocation operators.
14154 For our purposes, a %lo() expression matches a %got() or %hi()
14157 (a) it refers to the same symbol; and
14158 (b) the offset applied in the %lo() expression is no lower than
14159 the offset applied in the %got() or %hi().
14161 (b) allows us to cope with code like:
14164 lh $4,%lo(foo+2)($4)
14166 ...which is legal on RELA targets, and has a well-defined behaviour
14167 if the user knows that adding 2 to "foo" will not induce a carry to
14170 When several %lo()s match a particular %got() or %hi(), we use the
14171 following rules to distinguish them:
14173 (1) %lo()s with smaller offsets are a better match than %lo()s with
14176 (2) %lo()s with no matching %got() or %hi() are better than those
14177 that already have a matching %got() or %hi().
14179 (3) later %lo()s are better than earlier %lo()s.
14181 These rules are applied in order.
14183 (1) means, among other things, that %lo()s with identical offsets are
14184 chosen if they exist.
14186 (2) means that we won't associate several high-part relocations with
14187 the same low-part relocation unless there's no alternative. Having
14188 several high parts for the same low part is a GNU extension; this rule
14189 allows careful users to avoid it.
14191 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14192 with the last high-part relocation being at the front of the list.
14193 It therefore makes sense to choose the last matching low-part
14194 relocation, all other things being equal. It's also easier
14195 to code that way. */
14198 mips_frob_file (void)
14200 struct mips_hi_fixup
*l
;
14201 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14203 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14205 segment_info_type
*seginfo
;
14206 bfd_boolean matched_lo_p
;
14207 fixS
**hi_pos
, **lo_pos
, **pos
;
14209 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14211 /* If a GOT16 relocation turns out to be against a global symbol,
14212 there isn't supposed to be a matching LO. Ignore %gots against
14213 constants; we'll report an error for those later. */
14214 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14215 && !(l
->fixp
->fx_addsy
14216 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14219 /* Check quickly whether the next fixup happens to be a matching %lo. */
14220 if (fixup_has_matching_lo_p (l
->fixp
))
14223 seginfo
= seg_info (l
->seg
);
14225 /* Set HI_POS to the position of this relocation in the chain.
14226 Set LO_POS to the position of the chosen low-part relocation.
14227 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14228 relocation that matches an immediately-preceding high-part
14232 matched_lo_p
= FALSE
;
14233 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14235 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14237 if (*pos
== l
->fixp
)
14240 if ((*pos
)->fx_r_type
== looking_for_rtype
14241 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14242 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14244 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14246 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14249 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14250 && fixup_has_matching_lo_p (*pos
));
14253 /* If we found a match, remove the high-part relocation from its
14254 current position and insert it before the low-part relocation.
14255 Make the offsets match so that fixup_has_matching_lo_p()
14258 We don't warn about unmatched high-part relocations since some
14259 versions of gcc have been known to emit dead "lui ...%hi(...)"
14261 if (lo_pos
!= NULL
)
14263 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14264 if (l
->fixp
->fx_next
!= *lo_pos
)
14266 *hi_pos
= l
->fixp
->fx_next
;
14267 l
->fixp
->fx_next
= *lo_pos
;
14275 mips_force_relocation (fixS
*fixp
)
14277 if (generic_force_reloc (fixp
))
14280 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14281 so that the linker relaxation can update targets. */
14282 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14283 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14284 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14290 /* Read the instruction associated with RELOC from BUF. */
14292 static unsigned int
14293 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14295 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14296 return read_compressed_insn (buf
, 4);
14298 return read_insn (buf
);
14301 /* Write instruction INSN to BUF, given that it has been relocated
14305 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14306 unsigned long insn
)
14308 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14309 write_compressed_insn (buf
, insn
, 4);
14311 write_insn (buf
, insn
);
14314 /* Apply a fixup to the object file. */
14317 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14320 unsigned long insn
;
14321 reloc_howto_type
*howto
;
14323 if (fixP
->fx_pcrel
)
14324 switch (fixP
->fx_r_type
)
14326 case BFD_RELOC_16_PCREL_S2
:
14327 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14328 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14329 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14330 case BFD_RELOC_32_PCREL
:
14334 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14339 _("PC-relative reference to a different section"));
14343 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14344 that have no MIPS ELF equivalent. */
14345 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14347 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14352 gas_assert (fixP
->fx_size
== 2
14353 || fixP
->fx_size
== 4
14354 || fixP
->fx_r_type
== BFD_RELOC_8
14355 || fixP
->fx_r_type
== BFD_RELOC_16
14356 || fixP
->fx_r_type
== BFD_RELOC_64
14357 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14358 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14359 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14360 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14361 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14362 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14364 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14366 /* Don't treat parts of a composite relocation as done. There are two
14369 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14370 should nevertheless be emitted if the first part is.
14372 (2) In normal usage, composite relocations are never assembly-time
14373 constants. The easiest way of dealing with the pathological
14374 exceptions is to generate a relocation against STN_UNDEF and
14375 leave everything up to the linker. */
14376 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14379 switch (fixP
->fx_r_type
)
14381 case BFD_RELOC_MIPS_TLS_GD
:
14382 case BFD_RELOC_MIPS_TLS_LDM
:
14383 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14384 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14385 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14386 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14387 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14388 case BFD_RELOC_MIPS_TLS_TPREL32
:
14389 case BFD_RELOC_MIPS_TLS_TPREL64
:
14390 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14391 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14392 case BFD_RELOC_MICROMIPS_TLS_GD
:
14393 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14394 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14395 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14396 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14397 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14398 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14399 case BFD_RELOC_MIPS16_TLS_GD
:
14400 case BFD_RELOC_MIPS16_TLS_LDM
:
14401 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14402 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14403 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14404 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14405 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14406 if (!fixP
->fx_addsy
)
14408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14409 _("TLS relocation against a constant"));
14412 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14415 case BFD_RELOC_MIPS_JMP
:
14416 case BFD_RELOC_MIPS_SHIFT5
:
14417 case BFD_RELOC_MIPS_SHIFT6
:
14418 case BFD_RELOC_MIPS_GOT_DISP
:
14419 case BFD_RELOC_MIPS_GOT_PAGE
:
14420 case BFD_RELOC_MIPS_GOT_OFST
:
14421 case BFD_RELOC_MIPS_SUB
:
14422 case BFD_RELOC_MIPS_INSERT_A
:
14423 case BFD_RELOC_MIPS_INSERT_B
:
14424 case BFD_RELOC_MIPS_DELETE
:
14425 case BFD_RELOC_MIPS_HIGHEST
:
14426 case BFD_RELOC_MIPS_HIGHER
:
14427 case BFD_RELOC_MIPS_SCN_DISP
:
14428 case BFD_RELOC_MIPS_REL16
:
14429 case BFD_RELOC_MIPS_RELGOT
:
14430 case BFD_RELOC_MIPS_JALR
:
14431 case BFD_RELOC_HI16
:
14432 case BFD_RELOC_HI16_S
:
14433 case BFD_RELOC_LO16
:
14434 case BFD_RELOC_GPREL16
:
14435 case BFD_RELOC_MIPS_LITERAL
:
14436 case BFD_RELOC_MIPS_CALL16
:
14437 case BFD_RELOC_MIPS_GOT16
:
14438 case BFD_RELOC_GPREL32
:
14439 case BFD_RELOC_MIPS_GOT_HI16
:
14440 case BFD_RELOC_MIPS_GOT_LO16
:
14441 case BFD_RELOC_MIPS_CALL_HI16
:
14442 case BFD_RELOC_MIPS_CALL_LO16
:
14443 case BFD_RELOC_MIPS16_GPREL
:
14444 case BFD_RELOC_MIPS16_GOT16
:
14445 case BFD_RELOC_MIPS16_CALL16
:
14446 case BFD_RELOC_MIPS16_HI16
:
14447 case BFD_RELOC_MIPS16_HI16_S
:
14448 case BFD_RELOC_MIPS16_LO16
:
14449 case BFD_RELOC_MIPS16_JMP
:
14450 case BFD_RELOC_MICROMIPS_JMP
:
14451 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14452 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14453 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14454 case BFD_RELOC_MICROMIPS_SUB
:
14455 case BFD_RELOC_MICROMIPS_HIGHEST
:
14456 case BFD_RELOC_MICROMIPS_HIGHER
:
14457 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14458 case BFD_RELOC_MICROMIPS_JALR
:
14459 case BFD_RELOC_MICROMIPS_HI16
:
14460 case BFD_RELOC_MICROMIPS_HI16_S
:
14461 case BFD_RELOC_MICROMIPS_LO16
:
14462 case BFD_RELOC_MICROMIPS_GPREL16
:
14463 case BFD_RELOC_MICROMIPS_LITERAL
:
14464 case BFD_RELOC_MICROMIPS_CALL16
:
14465 case BFD_RELOC_MICROMIPS_GOT16
:
14466 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14467 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14468 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14469 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14470 case BFD_RELOC_MIPS_EH
:
14475 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14477 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14478 if (mips16_reloc_p (fixP
->fx_r_type
))
14479 insn
|= mips16_immed_extend (value
, 16);
14481 insn
|= (value
& 0xffff);
14482 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14486 _("unsupported constant in relocation"));
14491 /* This is handled like BFD_RELOC_32, but we output a sign
14492 extended value if we are only 32 bits. */
14495 if (8 <= sizeof (valueT
))
14496 md_number_to_chars (buf
, *valP
, 8);
14501 if ((*valP
& 0x80000000) != 0)
14505 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14506 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14511 case BFD_RELOC_RVA
:
14513 case BFD_RELOC_32_PCREL
:
14516 /* If we are deleting this reloc entry, we must fill in the
14517 value now. This can happen if we have a .word which is not
14518 resolved when it appears but is later defined. */
14520 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14523 case BFD_RELOC_16_PCREL_S2
:
14524 if ((*valP
& 0x3) != 0)
14525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14526 _("branch to misaligned address (%lx)"), (long) *valP
);
14528 /* We need to save the bits in the instruction since fixup_segment()
14529 might be deleting the relocation entry (i.e., a branch within
14530 the current segment). */
14531 if (! fixP
->fx_done
)
14534 /* Update old instruction data. */
14535 insn
= read_insn (buf
);
14537 if (*valP
+ 0x20000 <= 0x3ffff)
14539 insn
|= (*valP
>> 2) & 0xffff;
14540 write_insn (buf
, insn
);
14542 else if (mips_pic
== NO_PIC
14544 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14545 && (fixP
->fx_frag
->fr_address
14546 < text_section
->vma
+ bfd_get_section_size (text_section
))
14547 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14548 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14549 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14551 /* The branch offset is too large. If this is an
14552 unconditional branch, and we are not generating PIC code,
14553 we can convert it to an absolute jump instruction. */
14554 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14555 insn
= 0x0c000000; /* jal */
14557 insn
= 0x08000000; /* j */
14558 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14560 fixP
->fx_addsy
= section_symbol (text_section
);
14561 *valP
+= md_pcrel_from (fixP
);
14562 write_insn (buf
, insn
);
14566 /* If we got here, we have branch-relaxation disabled,
14567 and there's nothing we can do to fix this instruction
14568 without turning it into a longer sequence. */
14569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14570 _("branch out of range"));
14574 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14575 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14576 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14577 /* We adjust the offset back to even. */
14578 if ((*valP
& 0x1) != 0)
14581 if (! fixP
->fx_done
)
14584 /* Should never visit here, because we keep the relocation. */
14588 case BFD_RELOC_VTABLE_INHERIT
:
14591 && !S_IS_DEFINED (fixP
->fx_addsy
)
14592 && !S_IS_WEAK (fixP
->fx_addsy
))
14593 S_SET_WEAK (fixP
->fx_addsy
);
14596 case BFD_RELOC_VTABLE_ENTRY
:
14604 /* Remember value for tc_gen_reloc. */
14605 fixP
->fx_addnumber
= *valP
;
14615 name
= input_line_pointer
;
14616 c
= get_symbol_end ();
14617 p
= (symbolS
*) symbol_find_or_make (name
);
14618 *input_line_pointer
= c
;
14622 /* Align the current frag to a given power of two. If a particular
14623 fill byte should be used, FILL points to an integer that contains
14624 that byte, otherwise FILL is null.
14626 This function used to have the comment:
14628 The MIPS assembler also automatically adjusts any preceding label.
14630 The implementation therefore applied the adjustment to a maximum of
14631 one label. However, other label adjustments are applied to batches
14632 of labels, and adjusting just one caused problems when new labels
14633 were added for the sake of debugging or unwind information.
14634 We therefore adjust all preceding labels (given as LABELS) instead. */
14637 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14639 mips_emit_delays ();
14640 mips_record_compressed_mode ();
14641 if (fill
== NULL
&& subseg_text_p (now_seg
))
14642 frag_align_code (to
, 0);
14644 frag_align (to
, fill
? *fill
: 0, 0);
14645 record_alignment (now_seg
, to
);
14646 mips_move_labels (labels
, FALSE
);
14649 /* Align to a given power of two. .align 0 turns off the automatic
14650 alignment used by the data creating pseudo-ops. */
14653 s_align (int x ATTRIBUTE_UNUSED
)
14655 int temp
, fill_value
, *fill_ptr
;
14656 long max_alignment
= 28;
14658 /* o Note that the assembler pulls down any immediately preceding label
14659 to the aligned address.
14660 o It's not documented but auto alignment is reinstated by
14661 a .align pseudo instruction.
14662 o Note also that after auto alignment is turned off the mips assembler
14663 issues an error on attempt to assemble an improperly aligned data item.
14666 temp
= get_absolute_expression ();
14667 if (temp
> max_alignment
)
14668 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
14671 as_warn (_("alignment negative, 0 assumed"));
14674 if (*input_line_pointer
== ',')
14676 ++input_line_pointer
;
14677 fill_value
= get_absolute_expression ();
14678 fill_ptr
= &fill_value
;
14684 segment_info_type
*si
= seg_info (now_seg
);
14685 struct insn_label_list
*l
= si
->label_list
;
14686 /* Auto alignment should be switched on by next section change. */
14688 mips_align (temp
, fill_ptr
, l
);
14695 demand_empty_rest_of_line ();
14699 s_change_sec (int sec
)
14703 /* The ELF backend needs to know that we are changing sections, so
14704 that .previous works correctly. We could do something like check
14705 for an obj_section_change_hook macro, but that might be confusing
14706 as it would not be appropriate to use it in the section changing
14707 functions in read.c, since obj-elf.c intercepts those. FIXME:
14708 This should be cleaner, somehow. */
14709 obj_elf_section_change_hook ();
14711 mips_emit_delays ();
14722 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14723 demand_empty_rest_of_line ();
14727 seg
= subseg_new (RDATA_SECTION_NAME
,
14728 (subsegT
) get_absolute_expression ());
14729 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14730 | SEC_READONLY
| SEC_RELOC
14732 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14733 record_alignment (seg
, 4);
14734 demand_empty_rest_of_line ();
14738 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14739 bfd_set_section_flags (stdoutput
, seg
,
14740 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14741 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14742 record_alignment (seg
, 4);
14743 demand_empty_rest_of_line ();
14747 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14748 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14749 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14750 record_alignment (seg
, 4);
14751 demand_empty_rest_of_line ();
14759 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14761 char *section_name
;
14766 int section_entry_size
;
14767 int section_alignment
;
14769 section_name
= input_line_pointer
;
14770 c
= get_symbol_end ();
14772 next_c
= *(input_line_pointer
+ 1);
14774 /* Do we have .section Name<,"flags">? */
14775 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14777 /* just after name is now '\0'. */
14778 *input_line_pointer
= c
;
14779 input_line_pointer
= section_name
;
14780 obj_elf_section (ignore
);
14783 input_line_pointer
++;
14785 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14787 section_type
= get_absolute_expression ();
14790 if (*input_line_pointer
++ == ',')
14791 section_flag
= get_absolute_expression ();
14794 if (*input_line_pointer
++ == ',')
14795 section_entry_size
= get_absolute_expression ();
14797 section_entry_size
= 0;
14798 if (*input_line_pointer
++ == ',')
14799 section_alignment
= get_absolute_expression ();
14801 section_alignment
= 0;
14802 /* FIXME: really ignore? */
14803 (void) section_alignment
;
14805 section_name
= xstrdup (section_name
);
14807 /* When using the generic form of .section (as implemented by obj-elf.c),
14808 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14809 traditionally had to fall back on the more common @progbits instead.
14811 There's nothing really harmful in this, since bfd will correct
14812 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14813 means that, for backwards compatibility, the special_section entries
14814 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14816 Even so, we shouldn't force users of the MIPS .section syntax to
14817 incorrectly label the sections as SHT_PROGBITS. The best compromise
14818 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14819 generic type-checking code. */
14820 if (section_type
== SHT_MIPS_DWARF
)
14821 section_type
= SHT_PROGBITS
;
14823 obj_elf_change_section (section_name
, section_type
, section_flag
,
14824 section_entry_size
, 0, 0, 0);
14826 if (now_seg
->name
!= section_name
)
14827 free (section_name
);
14831 mips_enable_auto_align (void)
14837 s_cons (int log_size
)
14839 segment_info_type
*si
= seg_info (now_seg
);
14840 struct insn_label_list
*l
= si
->label_list
;
14842 mips_emit_delays ();
14843 if (log_size
> 0 && auto_align
)
14844 mips_align (log_size
, 0, l
);
14845 cons (1 << log_size
);
14846 mips_clear_insn_labels ();
14850 s_float_cons (int type
)
14852 segment_info_type
*si
= seg_info (now_seg
);
14853 struct insn_label_list
*l
= si
->label_list
;
14855 mips_emit_delays ();
14860 mips_align (3, 0, l
);
14862 mips_align (2, 0, l
);
14866 mips_clear_insn_labels ();
14869 /* Handle .globl. We need to override it because on Irix 5 you are
14872 where foo is an undefined symbol, to mean that foo should be
14873 considered to be the address of a function. */
14876 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14885 name
= input_line_pointer
;
14886 c
= get_symbol_end ();
14887 symbolP
= symbol_find_or_make (name
);
14888 S_SET_EXTERNAL (symbolP
);
14890 *input_line_pointer
= c
;
14891 SKIP_WHITESPACE ();
14893 /* On Irix 5, every global symbol that is not explicitly labelled as
14894 being a function is apparently labelled as being an object. */
14897 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14898 && (*input_line_pointer
!= ','))
14903 secname
= input_line_pointer
;
14904 c
= get_symbol_end ();
14905 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14907 as_bad (_("%s: no such section"), secname
);
14908 *input_line_pointer
= c
;
14910 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14911 flag
= BSF_FUNCTION
;
14914 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14916 c
= *input_line_pointer
;
14919 input_line_pointer
++;
14920 SKIP_WHITESPACE ();
14921 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14927 demand_empty_rest_of_line ();
14931 s_option (int x ATTRIBUTE_UNUSED
)
14936 opt
= input_line_pointer
;
14937 c
= get_symbol_end ();
14941 /* FIXME: What does this mean? */
14943 else if (strncmp (opt
, "pic", 3) == 0)
14947 i
= atoi (opt
+ 3);
14952 mips_pic
= SVR4_PIC
;
14953 mips_abicalls
= TRUE
;
14956 as_bad (_(".option pic%d not supported"), i
);
14958 if (mips_pic
== SVR4_PIC
)
14960 if (g_switch_seen
&& g_switch_value
!= 0)
14961 as_warn (_("-G may not be used with SVR4 PIC code"));
14962 g_switch_value
= 0;
14963 bfd_set_gp_size (stdoutput
, 0);
14967 as_warn (_("unrecognized option \"%s\""), opt
);
14969 *input_line_pointer
= c
;
14970 demand_empty_rest_of_line ();
14973 /* This structure is used to hold a stack of .set values. */
14975 struct mips_option_stack
14977 struct mips_option_stack
*next
;
14978 struct mips_set_options options
;
14981 static struct mips_option_stack
*mips_opts_stack
;
14983 /* Handle the .set pseudo-op. */
14986 s_mipsset (int x ATTRIBUTE_UNUSED
)
14988 char *name
= input_line_pointer
, ch
;
14989 const struct mips_ase
*ase
;
14991 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14992 ++input_line_pointer
;
14993 ch
= *input_line_pointer
;
14994 *input_line_pointer
= '\0';
14996 if (strcmp (name
, "reorder") == 0)
14998 if (mips_opts
.noreorder
)
15001 else if (strcmp (name
, "noreorder") == 0)
15003 if (!mips_opts
.noreorder
)
15004 start_noreorder ();
15006 else if (strncmp (name
, "at=", 3) == 0)
15008 char *s
= name
+ 3;
15010 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15011 as_bad (_("unrecognized register name `%s'"), s
);
15013 else if (strcmp (name
, "at") == 0)
15015 mips_opts
.at
= ATREG
;
15017 else if (strcmp (name
, "noat") == 0)
15019 mips_opts
.at
= ZERO
;
15021 else if (strcmp (name
, "macro") == 0)
15023 mips_opts
.warn_about_macros
= 0;
15025 else if (strcmp (name
, "nomacro") == 0)
15027 if (mips_opts
.noreorder
== 0)
15028 as_bad (_("`noreorder' must be set before `nomacro'"));
15029 mips_opts
.warn_about_macros
= 1;
15031 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15033 mips_opts
.nomove
= 0;
15035 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15037 mips_opts
.nomove
= 1;
15039 else if (strcmp (name
, "bopt") == 0)
15041 mips_opts
.nobopt
= 0;
15043 else if (strcmp (name
, "nobopt") == 0)
15045 mips_opts
.nobopt
= 1;
15047 else if (strcmp (name
, "gp=default") == 0)
15048 mips_opts
.gp32
= file_mips_gp32
;
15049 else if (strcmp (name
, "gp=32") == 0)
15050 mips_opts
.gp32
= 1;
15051 else if (strcmp (name
, "gp=64") == 0)
15053 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15054 as_warn (_("%s isa does not support 64-bit registers"),
15055 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15056 mips_opts
.gp32
= 0;
15058 else if (strcmp (name
, "fp=default") == 0)
15059 mips_opts
.fp32
= file_mips_fp32
;
15060 else if (strcmp (name
, "fp=32") == 0)
15061 mips_opts
.fp32
= 1;
15062 else if (strcmp (name
, "fp=64") == 0)
15064 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15065 as_warn (_("%s isa does not support 64-bit floating point registers"),
15066 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15067 mips_opts
.fp32
= 0;
15069 else if (strcmp (name
, "softfloat") == 0)
15070 mips_opts
.soft_float
= 1;
15071 else if (strcmp (name
, "hardfloat") == 0)
15072 mips_opts
.soft_float
= 0;
15073 else if (strcmp (name
, "singlefloat") == 0)
15074 mips_opts
.single_float
= 1;
15075 else if (strcmp (name
, "doublefloat") == 0)
15076 mips_opts
.single_float
= 0;
15077 else if (strcmp (name
, "mips16") == 0
15078 || strcmp (name
, "MIPS-16") == 0)
15080 if (mips_opts
.micromips
== 1)
15081 as_fatal (_("`mips16' cannot be used with `micromips'"));
15082 mips_opts
.mips16
= 1;
15084 else if (strcmp (name
, "nomips16") == 0
15085 || strcmp (name
, "noMIPS-16") == 0)
15086 mips_opts
.mips16
= 0;
15087 else if (strcmp (name
, "micromips") == 0)
15089 if (mips_opts
.mips16
== 1)
15090 as_fatal (_("`micromips' cannot be used with `mips16'"));
15091 mips_opts
.micromips
= 1;
15093 else if (strcmp (name
, "nomicromips") == 0)
15094 mips_opts
.micromips
= 0;
15095 else if (name
[0] == 'n'
15097 && (ase
= mips_lookup_ase (name
+ 2)))
15098 mips_set_ase (ase
, FALSE
);
15099 else if ((ase
= mips_lookup_ase (name
)))
15100 mips_set_ase (ase
, TRUE
);
15101 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15105 /* Permit the user to change the ISA and architecture on the fly.
15106 Needless to say, misuse can cause serious problems. */
15107 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15110 mips_opts
.isa
= file_mips_isa
;
15111 mips_opts
.arch
= file_mips_arch
;
15113 else if (strncmp (name
, "arch=", 5) == 0)
15115 const struct mips_cpu_info
*p
;
15117 p
= mips_parse_cpu("internal use", name
+ 5);
15119 as_bad (_("unknown architecture %s"), name
+ 5);
15122 mips_opts
.arch
= p
->cpu
;
15123 mips_opts
.isa
= p
->isa
;
15126 else if (strncmp (name
, "mips", 4) == 0)
15128 const struct mips_cpu_info
*p
;
15130 p
= mips_parse_cpu("internal use", name
);
15132 as_bad (_("unknown ISA level %s"), name
+ 4);
15135 mips_opts
.arch
= p
->cpu
;
15136 mips_opts
.isa
= p
->isa
;
15140 as_bad (_("unknown ISA or architecture %s"), name
);
15142 switch (mips_opts
.isa
)
15152 mips_opts
.gp32
= 1;
15153 mips_opts
.fp32
= 1;
15162 mips_opts
.gp32
= 0;
15163 if (mips_opts
.arch
== CPU_R5900
)
15165 mips_opts
.fp32
= 1;
15169 mips_opts
.fp32
= 0;
15173 as_bad (_("unknown ISA level %s"), name
+ 4);
15178 mips_opts
.gp32
= file_mips_gp32
;
15179 mips_opts
.fp32
= file_mips_fp32
;
15182 else if (strcmp (name
, "autoextend") == 0)
15183 mips_opts
.noautoextend
= 0;
15184 else if (strcmp (name
, "noautoextend") == 0)
15185 mips_opts
.noautoextend
= 1;
15186 else if (strcmp (name
, "insn32") == 0)
15187 mips_opts
.insn32
= TRUE
;
15188 else if (strcmp (name
, "noinsn32") == 0)
15189 mips_opts
.insn32
= FALSE
;
15190 else if (strcmp (name
, "push") == 0)
15192 struct mips_option_stack
*s
;
15194 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15195 s
->next
= mips_opts_stack
;
15196 s
->options
= mips_opts
;
15197 mips_opts_stack
= s
;
15199 else if (strcmp (name
, "pop") == 0)
15201 struct mips_option_stack
*s
;
15203 s
= mips_opts_stack
;
15205 as_bad (_(".set pop with no .set push"));
15208 /* If we're changing the reorder mode we need to handle
15209 delay slots correctly. */
15210 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15211 start_noreorder ();
15212 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15215 mips_opts
= s
->options
;
15216 mips_opts_stack
= s
->next
;
15220 else if (strcmp (name
, "sym32") == 0)
15221 mips_opts
.sym32
= TRUE
;
15222 else if (strcmp (name
, "nosym32") == 0)
15223 mips_opts
.sym32
= FALSE
;
15224 else if (strchr (name
, ','))
15226 /* Generic ".set" directive; use the generic handler. */
15227 *input_line_pointer
= ch
;
15228 input_line_pointer
= name
;
15234 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15236 mips_check_isa_supports_ases ();
15237 *input_line_pointer
= ch
;
15238 demand_empty_rest_of_line ();
15241 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15242 .option pic2. It means to generate SVR4 PIC calls. */
15245 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15247 mips_pic
= SVR4_PIC
;
15248 mips_abicalls
= TRUE
;
15250 if (g_switch_seen
&& g_switch_value
!= 0)
15251 as_warn (_("-G may not be used with SVR4 PIC code"));
15252 g_switch_value
= 0;
15254 bfd_set_gp_size (stdoutput
, 0);
15255 demand_empty_rest_of_line ();
15258 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15259 PIC code. It sets the $gp register for the function based on the
15260 function address, which is in the register named in the argument.
15261 This uses a relocation against _gp_disp, which is handled specially
15262 by the linker. The result is:
15263 lui $gp,%hi(_gp_disp)
15264 addiu $gp,$gp,%lo(_gp_disp)
15265 addu $gp,$gp,.cpload argument
15266 The .cpload argument is normally $25 == $t9.
15268 The -mno-shared option changes this to:
15269 lui $gp,%hi(__gnu_local_gp)
15270 addiu $gp,$gp,%lo(__gnu_local_gp)
15271 and the argument is ignored. This saves an instruction, but the
15272 resulting code is not position independent; it uses an absolute
15273 address for __gnu_local_gp. Thus code assembled with -mno-shared
15274 can go into an ordinary executable, but not into a shared library. */
15277 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15283 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15284 .cpload is ignored. */
15285 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15291 if (mips_opts
.mips16
)
15293 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15294 ignore_rest_of_line ();
15298 /* .cpload should be in a .set noreorder section. */
15299 if (mips_opts
.noreorder
== 0)
15300 as_warn (_(".cpload not in noreorder section"));
15302 reg
= tc_get_register (0);
15304 /* If we need to produce a 64-bit address, we are better off using
15305 the default instruction sequence. */
15306 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15308 ex
.X_op
= O_symbol
;
15309 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15311 ex
.X_op_symbol
= NULL
;
15312 ex
.X_add_number
= 0;
15314 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15315 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15317 mips_mark_labels ();
15318 mips_assembling_insn
= TRUE
;
15321 macro_build_lui (&ex
, mips_gp_register
);
15322 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15323 mips_gp_register
, BFD_RELOC_LO16
);
15325 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15326 mips_gp_register
, reg
);
15329 mips_assembling_insn
= FALSE
;
15330 demand_empty_rest_of_line ();
15333 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15334 .cpsetup $reg1, offset|$reg2, label
15336 If offset is given, this results in:
15337 sd $gp, offset($sp)
15338 lui $gp, %hi(%neg(%gp_rel(label)))
15339 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15340 daddu $gp, $gp, $reg1
15342 If $reg2 is given, this results in:
15343 daddu $reg2, $gp, $0
15344 lui $gp, %hi(%neg(%gp_rel(label)))
15345 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15346 daddu $gp, $gp, $reg1
15347 $reg1 is normally $25 == $t9.
15349 The -mno-shared option replaces the last three instructions with
15351 addiu $gp,$gp,%lo(_gp) */
15354 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15356 expressionS ex_off
;
15357 expressionS ex_sym
;
15360 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15361 We also need NewABI support. */
15362 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15368 if (mips_opts
.mips16
)
15370 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15371 ignore_rest_of_line ();
15375 reg1
= tc_get_register (0);
15376 SKIP_WHITESPACE ();
15377 if (*input_line_pointer
!= ',')
15379 as_bad (_("missing argument separator ',' for .cpsetup"));
15383 ++input_line_pointer
;
15384 SKIP_WHITESPACE ();
15385 if (*input_line_pointer
== '$')
15387 mips_cpreturn_register
= tc_get_register (0);
15388 mips_cpreturn_offset
= -1;
15392 mips_cpreturn_offset
= get_absolute_expression ();
15393 mips_cpreturn_register
= -1;
15395 SKIP_WHITESPACE ();
15396 if (*input_line_pointer
!= ',')
15398 as_bad (_("missing argument separator ',' for .cpsetup"));
15402 ++input_line_pointer
;
15403 SKIP_WHITESPACE ();
15404 expression (&ex_sym
);
15406 mips_mark_labels ();
15407 mips_assembling_insn
= TRUE
;
15410 if (mips_cpreturn_register
== -1)
15412 ex_off
.X_op
= O_constant
;
15413 ex_off
.X_add_symbol
= NULL
;
15414 ex_off
.X_op_symbol
= NULL
;
15415 ex_off
.X_add_number
= mips_cpreturn_offset
;
15417 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15418 BFD_RELOC_LO16
, SP
);
15421 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15422 mips_gp_register
, 0);
15424 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15426 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15427 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15430 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15431 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15432 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15435 mips_gp_register
, reg1
);
15441 ex
.X_op
= O_symbol
;
15442 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15443 ex
.X_op_symbol
= NULL
;
15444 ex
.X_add_number
= 0;
15446 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15447 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15449 macro_build_lui (&ex
, mips_gp_register
);
15450 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15451 mips_gp_register
, BFD_RELOC_LO16
);
15456 mips_assembling_insn
= FALSE
;
15457 demand_empty_rest_of_line ();
15461 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15463 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15464 .cplocal is ignored. */
15465 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15471 if (mips_opts
.mips16
)
15473 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15474 ignore_rest_of_line ();
15478 mips_gp_register
= tc_get_register (0);
15479 demand_empty_rest_of_line ();
15482 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15483 offset from $sp. The offset is remembered, and after making a PIC
15484 call $gp is restored from that location. */
15487 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15491 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15492 .cprestore is ignored. */
15493 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15499 if (mips_opts
.mips16
)
15501 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15502 ignore_rest_of_line ();
15506 mips_cprestore_offset
= get_absolute_expression ();
15507 mips_cprestore_valid
= 1;
15509 ex
.X_op
= O_constant
;
15510 ex
.X_add_symbol
= NULL
;
15511 ex
.X_op_symbol
= NULL
;
15512 ex
.X_add_number
= mips_cprestore_offset
;
15514 mips_mark_labels ();
15515 mips_assembling_insn
= TRUE
;
15518 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15519 SP
, HAVE_64BIT_ADDRESSES
);
15522 mips_assembling_insn
= FALSE
;
15523 demand_empty_rest_of_line ();
15526 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15527 was given in the preceding .cpsetup, it results in:
15528 ld $gp, offset($sp)
15530 If a register $reg2 was given there, it results in:
15531 daddu $gp, $reg2, $0 */
15534 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15538 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15539 We also need NewABI support. */
15540 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15546 if (mips_opts
.mips16
)
15548 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15549 ignore_rest_of_line ();
15553 mips_mark_labels ();
15554 mips_assembling_insn
= TRUE
;
15557 if (mips_cpreturn_register
== -1)
15559 ex
.X_op
= O_constant
;
15560 ex
.X_add_symbol
= NULL
;
15561 ex
.X_op_symbol
= NULL
;
15562 ex
.X_add_number
= mips_cpreturn_offset
;
15564 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15567 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15568 mips_cpreturn_register
, 0);
15571 mips_assembling_insn
= FALSE
;
15572 demand_empty_rest_of_line ();
15575 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15576 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15577 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15578 debug information or MIPS16 TLS. */
15581 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15582 bfd_reloc_code_real_type rtype
)
15589 if (ex
.X_op
!= O_symbol
)
15591 as_bad (_("unsupported use of %s"), dirstr
);
15592 ignore_rest_of_line ();
15595 p
= frag_more (bytes
);
15596 md_number_to_chars (p
, 0, bytes
);
15597 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15598 demand_empty_rest_of_line ();
15599 mips_clear_insn_labels ();
15602 /* Handle .dtprelword. */
15605 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15607 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15610 /* Handle .dtpreldword. */
15613 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15615 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15618 /* Handle .tprelword. */
15621 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15623 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15626 /* Handle .tpreldword. */
15629 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15631 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15634 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15635 code. It sets the offset to use in gp_rel relocations. */
15638 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15640 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15641 We also need NewABI support. */
15642 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15648 mips_gprel_offset
= get_absolute_expression ();
15650 demand_empty_rest_of_line ();
15653 /* Handle the .gpword pseudo-op. This is used when generating PIC
15654 code. It generates a 32 bit GP relative reloc. */
15657 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15659 segment_info_type
*si
;
15660 struct insn_label_list
*l
;
15664 /* When not generating PIC code, this is treated as .word. */
15665 if (mips_pic
!= SVR4_PIC
)
15671 si
= seg_info (now_seg
);
15672 l
= si
->label_list
;
15673 mips_emit_delays ();
15675 mips_align (2, 0, l
);
15678 mips_clear_insn_labels ();
15680 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15682 as_bad (_("unsupported use of .gpword"));
15683 ignore_rest_of_line ();
15687 md_number_to_chars (p
, 0, 4);
15688 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15689 BFD_RELOC_GPREL32
);
15691 demand_empty_rest_of_line ();
15695 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15697 segment_info_type
*si
;
15698 struct insn_label_list
*l
;
15702 /* When not generating PIC code, this is treated as .dword. */
15703 if (mips_pic
!= SVR4_PIC
)
15709 si
= seg_info (now_seg
);
15710 l
= si
->label_list
;
15711 mips_emit_delays ();
15713 mips_align (3, 0, l
);
15716 mips_clear_insn_labels ();
15718 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15720 as_bad (_("unsupported use of .gpdword"));
15721 ignore_rest_of_line ();
15725 md_number_to_chars (p
, 0, 8);
15726 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15727 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15729 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15730 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15731 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15733 demand_empty_rest_of_line ();
15736 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15737 tables. It generates a R_MIPS_EH reloc. */
15740 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15745 mips_emit_delays ();
15748 mips_clear_insn_labels ();
15750 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15752 as_bad (_("unsupported use of .ehword"));
15753 ignore_rest_of_line ();
15757 md_number_to_chars (p
, 0, 4);
15758 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15759 BFD_RELOC_MIPS_EH
);
15761 demand_empty_rest_of_line ();
15764 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15765 tables in SVR4 PIC code. */
15768 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15772 /* This is ignored when not generating SVR4 PIC code. */
15773 if (mips_pic
!= SVR4_PIC
)
15779 mips_mark_labels ();
15780 mips_assembling_insn
= TRUE
;
15782 /* Add $gp to the register named as an argument. */
15784 reg
= tc_get_register (0);
15785 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15788 mips_assembling_insn
= FALSE
;
15789 demand_empty_rest_of_line ();
15792 /* Handle the .insn pseudo-op. This marks instruction labels in
15793 mips16/micromips mode. This permits the linker to handle them specially,
15794 such as generating jalx instructions when needed. We also make
15795 them odd for the duration of the assembly, in order to generate the
15796 right sort of code. We will make them even in the adjust_symtab
15797 routine, while leaving them marked. This is convenient for the
15798 debugger and the disassembler. The linker knows to make them odd
15802 s_insn (int ignore ATTRIBUTE_UNUSED
)
15804 mips_mark_labels ();
15806 demand_empty_rest_of_line ();
15809 /* Handle the .nan pseudo-op. */
15812 s_nan (int ignore ATTRIBUTE_UNUSED
)
15814 static const char str_legacy
[] = "legacy";
15815 static const char str_2008
[] = "2008";
15818 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15820 if (i
== sizeof (str_2008
) - 1
15821 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15822 mips_flag_nan2008
= TRUE
;
15823 else if (i
== sizeof (str_legacy
) - 1
15824 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15825 mips_flag_nan2008
= FALSE
;
15827 as_bad (_("bad .nan directive"));
15829 input_line_pointer
+= i
;
15830 demand_empty_rest_of_line ();
15833 /* Handle a .stab[snd] directive. Ideally these directives would be
15834 implemented in a transparent way, so that removing them would not
15835 have any effect on the generated instructions. However, s_stab
15836 internally changes the section, so in practice we need to decide
15837 now whether the preceding label marks compressed code. We do not
15838 support changing the compression mode of a label after a .stab*
15839 directive, such as in:
15845 so the current mode wins. */
15848 s_mips_stab (int type
)
15850 mips_mark_labels ();
15854 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15857 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15864 name
= input_line_pointer
;
15865 c
= get_symbol_end ();
15866 symbolP
= symbol_find_or_make (name
);
15867 S_SET_WEAK (symbolP
);
15868 *input_line_pointer
= c
;
15870 SKIP_WHITESPACE ();
15872 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15874 if (S_IS_DEFINED (symbolP
))
15876 as_bad (_("ignoring attempt to redefine symbol %s"),
15877 S_GET_NAME (symbolP
));
15878 ignore_rest_of_line ();
15882 if (*input_line_pointer
== ',')
15884 ++input_line_pointer
;
15885 SKIP_WHITESPACE ();
15889 if (exp
.X_op
!= O_symbol
)
15891 as_bad (_("bad .weakext directive"));
15892 ignore_rest_of_line ();
15895 symbol_set_value_expression (symbolP
, &exp
);
15898 demand_empty_rest_of_line ();
15901 /* Parse a register string into a number. Called from the ECOFF code
15902 to parse .frame. The argument is non-zero if this is the frame
15903 register, so that we can record it in mips_frame_reg. */
15906 tc_get_register (int frame
)
15910 SKIP_WHITESPACE ();
15911 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15915 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15916 mips_frame_reg_valid
= 1;
15917 mips_cprestore_valid
= 0;
15923 md_section_align (asection
*seg
, valueT addr
)
15925 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15927 /* We don't need to align ELF sections to the full alignment.
15928 However, Irix 5 may prefer that we align them at least to a 16
15929 byte boundary. We don't bother to align the sections if we
15930 are targeted for an embedded system. */
15931 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15936 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15939 /* Utility routine, called from above as well. If called while the
15940 input file is still being read, it's only an approximation. (For
15941 example, a symbol may later become defined which appeared to be
15942 undefined earlier.) */
15945 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15950 if (g_switch_value
> 0)
15952 const char *symname
;
15955 /* Find out whether this symbol can be referenced off the $gp
15956 register. It can be if it is smaller than the -G size or if
15957 it is in the .sdata or .sbss section. Certain symbols can
15958 not be referenced off the $gp, although it appears as though
15960 symname
= S_GET_NAME (sym
);
15961 if (symname
!= (const char *) NULL
15962 && (strcmp (symname
, "eprol") == 0
15963 || strcmp (symname
, "etext") == 0
15964 || strcmp (symname
, "_gp") == 0
15965 || strcmp (symname
, "edata") == 0
15966 || strcmp (symname
, "_fbss") == 0
15967 || strcmp (symname
, "_fdata") == 0
15968 || strcmp (symname
, "_ftext") == 0
15969 || strcmp (symname
, "end") == 0
15970 || strcmp (symname
, "_gp_disp") == 0))
15972 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15974 #ifndef NO_ECOFF_DEBUGGING
15975 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15976 && (symbol_get_obj (sym
)->ecoff_extern_size
15977 <= g_switch_value
))
15979 /* We must defer this decision until after the whole
15980 file has been read, since there might be a .extern
15981 after the first use of this symbol. */
15982 || (before_relaxing
15983 #ifndef NO_ECOFF_DEBUGGING
15984 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15986 && S_GET_VALUE (sym
) == 0)
15987 || (S_GET_VALUE (sym
) != 0
15988 && S_GET_VALUE (sym
) <= g_switch_value
)))
15992 const char *segname
;
15994 segname
= segment_name (S_GET_SEGMENT (sym
));
15995 gas_assert (strcmp (segname
, ".lit8") != 0
15996 && strcmp (segname
, ".lit4") != 0);
15997 change
= (strcmp (segname
, ".sdata") != 0
15998 && strcmp (segname
, ".sbss") != 0
15999 && strncmp (segname
, ".sdata.", 7) != 0
16000 && strncmp (segname
, ".sbss.", 6) != 0
16001 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16002 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16007 /* We are not optimizing for the $gp register. */
16012 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16015 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16019 /* Handle the case of a symbol equated to another symbol. */
16020 while (symbol_equated_reloc_p (sym
))
16024 /* It's possible to get a loop here in a badly written program. */
16025 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16031 if (symbol_section_p (sym
))
16034 symsec
= S_GET_SEGMENT (sym
);
16036 /* This must duplicate the test in adjust_reloc_syms. */
16037 return (!bfd_is_und_section (symsec
)
16038 && !bfd_is_abs_section (symsec
)
16039 && !bfd_is_com_section (symsec
)
16040 && !s_is_linkonce (sym
, segtype
)
16041 /* A global or weak symbol is treated as external. */
16042 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16046 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16047 extended opcode. SEC is the section the frag is in. */
16050 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16053 const struct mips_int_operand
*operand
;
16058 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16060 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16063 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16064 operand
= mips16_immed_operand (type
, FALSE
);
16066 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16067 val
= S_GET_VALUE (fragp
->fr_symbol
);
16068 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16070 if (operand
->root
.type
== OP_PCREL
)
16072 const struct mips_pcrel_operand
*pcrel_op
;
16076 /* We won't have the section when we are called from
16077 mips_relax_frag. However, we will always have been called
16078 from md_estimate_size_before_relax first. If this is a
16079 branch to a different section, we mark it as such. If SEC is
16080 NULL, and the frag is not marked, then it must be a branch to
16081 the same section. */
16082 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16085 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16090 /* Must have been called from md_estimate_size_before_relax. */
16093 fragp
->fr_subtype
=
16094 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16096 /* FIXME: We should support this, and let the linker
16097 catch branches and loads that are out of range. */
16098 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16099 _("unsupported PC relative reference to different section"));
16103 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16104 /* Assume non-extended on the first relaxation pass.
16105 The address we have calculated will be bogus if this is
16106 a forward branch to another frag, as the forward frag
16107 will have fr_address == 0. */
16111 /* In this case, we know for sure that the symbol fragment is in
16112 the same section. If the relax_marker of the symbol fragment
16113 differs from the relax_marker of this fragment, we have not
16114 yet adjusted the symbol fragment fr_address. We want to add
16115 in STRETCH in order to get a better estimate of the address.
16116 This particularly matters because of the shift bits. */
16118 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16122 /* Adjust stretch for any alignment frag. Note that if have
16123 been expanding the earlier code, the symbol may be
16124 defined in what appears to be an earlier frag. FIXME:
16125 This doesn't handle the fr_subtype field, which specifies
16126 a maximum number of bytes to skip when doing an
16128 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16130 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16133 stretch
= - ((- stretch
)
16134 & ~ ((1 << (int) f
->fr_offset
) - 1));
16136 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16145 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16147 /* The base address rules are complicated. The base address of
16148 a branch is the following instruction. The base address of a
16149 PC relative load or add is the instruction itself, but if it
16150 is in a delay slot (in which case it can not be extended) use
16151 the address of the instruction whose delay slot it is in. */
16152 if (pcrel_op
->include_isa_bit
)
16156 /* If we are currently assuming that this frag should be
16157 extended, then, the current address is two bytes
16159 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16162 /* Ignore the low bit in the target, since it will be set
16163 for a text label. */
16166 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16168 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16171 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16173 /* If any of the shifted bits are set, we must use an extended
16174 opcode. If the address depends on the size of this
16175 instruction, this can lead to a loop, so we arrange to always
16176 use an extended opcode. We only check this when we are in
16177 the main relaxation loop, when SEC is NULL. */
16178 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16180 fragp
->fr_subtype
=
16181 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16185 /* If we are about to mark a frag as extended because the value
16186 is precisely the next value above maxtiny, then there is a
16187 chance of an infinite loop as in the following code:
16192 In this case when the la is extended, foo is 0x3fc bytes
16193 away, so the la can be shrunk, but then foo is 0x400 away, so
16194 the la must be extended. To avoid this loop, we mark the
16195 frag as extended if it was small, and is about to become
16196 extended with the next value above maxtiny. */
16197 maxtiny
= mips_int_operand_max (operand
);
16198 if (val
== maxtiny
+ (1 << operand
->shift
)
16199 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16202 fragp
->fr_subtype
=
16203 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16207 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16208 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16210 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16213 /* Compute the length of a branch sequence, and adjust the
16214 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16215 worst-case length is computed, with UPDATE being used to indicate
16216 whether an unconditional (-1), branch-likely (+1) or regular (0)
16217 branch is to be computed. */
16219 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16221 bfd_boolean toofar
;
16225 && S_IS_DEFINED (fragp
->fr_symbol
)
16226 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16231 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16233 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16237 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16240 /* If the symbol is not defined or it's in a different segment,
16241 assume the user knows what's going on and emit a short
16247 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16249 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16250 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16251 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16252 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16258 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16261 if (mips_pic
!= NO_PIC
)
16263 /* Additional space for PIC loading of target address. */
16265 if (mips_opts
.isa
== ISA_MIPS1
)
16266 /* Additional space for $at-stabilizing nop. */
16270 /* If branch is conditional. */
16271 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16278 /* Compute the length of a branch sequence, and adjust the
16279 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16280 worst-case length is computed, with UPDATE being used to indicate
16281 whether an unconditional (-1), or regular (0) branch is to be
16285 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16287 bfd_boolean toofar
;
16291 && S_IS_DEFINED (fragp
->fr_symbol
)
16292 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16297 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16298 /* Ignore the low bit in the target, since it will be set
16299 for a text label. */
16300 if ((val
& 1) != 0)
16303 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16307 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16310 /* If the symbol is not defined or it's in a different segment,
16311 assume the user knows what's going on and emit a short
16317 if (fragp
&& update
16318 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16319 fragp
->fr_subtype
= (toofar
16320 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16321 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16326 bfd_boolean compact_known
= fragp
!= NULL
;
16327 bfd_boolean compact
= FALSE
;
16328 bfd_boolean uncond
;
16331 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16333 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16335 uncond
= update
< 0;
16337 /* If label is out of range, we turn branch <br>:
16339 <br> label # 4 bytes
16345 nop # 2 bytes if compact && !PIC
16348 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16351 /* If assembling PIC code, we further turn:
16357 lw/ld at, %got(label)(gp) # 4 bytes
16358 d/addiu at, %lo(label) # 4 bytes
16361 if (mips_pic
!= NO_PIC
)
16364 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16366 <brneg> 0f # 4 bytes
16367 nop # 2 bytes if !compact
16370 length
+= (compact_known
&& compact
) ? 4 : 6;
16376 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16377 bit accordingly. */
16380 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16382 bfd_boolean toofar
;
16385 && S_IS_DEFINED (fragp
->fr_symbol
)
16386 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16392 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16393 /* Ignore the low bit in the target, since it will be set
16394 for a text label. */
16395 if ((val
& 1) != 0)
16398 /* Assume this is a 2-byte branch. */
16399 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16401 /* We try to avoid the infinite loop by not adding 2 more bytes for
16406 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16408 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16409 else if (type
== 'E')
16410 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16415 /* If the symbol is not defined or it's in a different segment,
16416 we emit a normal 32-bit branch. */
16419 if (fragp
&& update
16420 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16422 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16423 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16431 /* Estimate the size of a frag before relaxing. Unless this is the
16432 mips16, we are not really relaxing here, and the final size is
16433 encoded in the subtype information. For the mips16, we have to
16434 decide whether we are using an extended opcode or not. */
16437 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16441 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16444 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16446 return fragp
->fr_var
;
16449 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16450 /* We don't want to modify the EXTENDED bit here; it might get us
16451 into infinite loops. We change it only in mips_relax_frag(). */
16452 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16454 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16458 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16459 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16460 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16461 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16462 fragp
->fr_var
= length
;
16467 if (mips_pic
== NO_PIC
)
16468 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16469 else if (mips_pic
== SVR4_PIC
)
16470 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16471 else if (mips_pic
== VXWORKS_PIC
)
16472 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16479 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16480 return -RELAX_FIRST (fragp
->fr_subtype
);
16483 return -RELAX_SECOND (fragp
->fr_subtype
);
16486 /* This is called to see whether a reloc against a defined symbol
16487 should be converted into a reloc against a section. */
16490 mips_fix_adjustable (fixS
*fixp
)
16492 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16493 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16496 if (fixp
->fx_addsy
== NULL
)
16499 /* If symbol SYM is in a mergeable section, relocations of the form
16500 SYM + 0 can usually be made section-relative. The mergeable data
16501 is then identified by the section offset rather than by the symbol.
16503 However, if we're generating REL LO16 relocations, the offset is split
16504 between the LO16 and parterning high part relocation. The linker will
16505 need to recalculate the complete offset in order to correctly identify
16508 The linker has traditionally not looked for the parterning high part
16509 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16510 placed anywhere. Rather than break backwards compatibility by changing
16511 this, it seems better not to force the issue, and instead keep the
16512 original symbol. This will work with either linker behavior. */
16513 if ((lo16_reloc_p (fixp
->fx_r_type
)
16514 || reloc_needs_lo_p (fixp
->fx_r_type
))
16515 && HAVE_IN_PLACE_ADDENDS
16516 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16519 /* There is no place to store an in-place offset for JALR relocations.
16520 Likewise an in-range offset of limited PC-relative relocations may
16521 overflow the in-place relocatable field if recalculated against the
16522 start address of the symbol's containing section. */
16523 if (HAVE_IN_PLACE_ADDENDS
16524 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16525 || jalr_reloc_p (fixp
->fx_r_type
)))
16528 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16529 to a floating-point stub. The same is true for non-R_MIPS16_26
16530 relocations against MIPS16 functions; in this case, the stub becomes
16531 the function's canonical address.
16533 Floating-point stubs are stored in unique .mips16.call.* or
16534 .mips16.fn.* sections. If a stub T for function F is in section S,
16535 the first relocation in section S must be against F; this is how the
16536 linker determines the target function. All relocations that might
16537 resolve to T must also be against F. We therefore have the following
16538 restrictions, which are given in an intentionally-redundant way:
16540 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16543 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16544 if that stub might be used.
16546 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16549 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16550 that stub might be used.
16552 There is a further restriction:
16554 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16555 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16556 targets with in-place addends; the relocation field cannot
16557 encode the low bit.
16559 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16560 against a MIPS16 symbol. We deal with (5) by by not reducing any
16561 such relocations on REL targets.
16563 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16564 relocation against some symbol R, no relocation against R may be
16565 reduced. (Note that this deals with (2) as well as (1) because
16566 relocations against global symbols will never be reduced on ELF
16567 targets.) This approach is a little simpler than trying to detect
16568 stub sections, and gives the "all or nothing" per-symbol consistency
16569 that we have for MIPS16 symbols. */
16570 if (fixp
->fx_subsy
== NULL
16571 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16572 || *symbol_get_tc (fixp
->fx_addsy
)
16573 || (HAVE_IN_PLACE_ADDENDS
16574 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16575 && jmp_reloc_p (fixp
->fx_r_type
))))
16581 /* Translate internal representation of relocation info to BFD target
16585 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16587 static arelent
*retval
[4];
16589 bfd_reloc_code_real_type code
;
16591 memset (retval
, 0, sizeof(retval
));
16592 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16593 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16594 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16595 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16597 if (fixp
->fx_pcrel
)
16599 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16600 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16601 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16602 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16603 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16605 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16606 Relocations want only the symbol offset. */
16607 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16610 reloc
->addend
= fixp
->fx_addnumber
;
16612 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16613 entry to be used in the relocation's section offset. */
16614 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16616 reloc
->address
= reloc
->addend
;
16620 code
= fixp
->fx_r_type
;
16622 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16623 if (reloc
->howto
== NULL
)
16625 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16626 _("cannot represent %s relocation in this object file"
16628 bfd_get_reloc_code_name (code
));
16635 /* Relax a machine dependent frag. This returns the amount by which
16636 the current size of the frag should change. */
16639 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16641 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16643 offsetT old_var
= fragp
->fr_var
;
16645 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16647 return fragp
->fr_var
- old_var
;
16650 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16652 offsetT old_var
= fragp
->fr_var
;
16653 offsetT new_var
= 4;
16655 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16656 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16657 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16658 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16659 fragp
->fr_var
= new_var
;
16661 return new_var
- old_var
;
16664 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16667 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16669 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16671 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16676 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16678 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16685 /* Convert a machine dependent frag. */
16688 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16690 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16693 unsigned long insn
;
16697 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16698 insn
= read_insn (buf
);
16700 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16702 /* We generate a fixup instead of applying it right now
16703 because, if there are linker relaxations, we're going to
16704 need the relocations. */
16705 exp
.X_op
= O_symbol
;
16706 exp
.X_add_symbol
= fragp
->fr_symbol
;
16707 exp
.X_add_number
= fragp
->fr_offset
;
16709 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16710 BFD_RELOC_16_PCREL_S2
);
16711 fixp
->fx_file
= fragp
->fr_file
;
16712 fixp
->fx_line
= fragp
->fr_line
;
16714 buf
= write_insn (buf
, insn
);
16720 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16721 _("relaxed out-of-range branch into a jump"));
16723 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16726 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16728 /* Reverse the branch. */
16729 switch ((insn
>> 28) & 0xf)
16732 if ((insn
& 0xff000000) == 0x47000000
16733 || (insn
& 0xff600000) == 0x45600000)
16735 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
16736 reversed by tweaking bit 23. */
16737 insn
^= 0x00800000;
16741 /* bc[0-3][tf]l? instructions can have the condition
16742 reversed by tweaking a single TF bit, and their
16743 opcodes all have 0x4???????. */
16744 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16745 insn
^= 0x00010000;
16750 /* bltz 0x04000000 bgez 0x04010000
16751 bltzal 0x04100000 bgezal 0x04110000 */
16752 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16753 insn
^= 0x00010000;
16757 /* beq 0x10000000 bne 0x14000000
16758 blez 0x18000000 bgtz 0x1c000000 */
16759 insn
^= 0x04000000;
16767 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16769 /* Clear the and-link bit. */
16770 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16772 /* bltzal 0x04100000 bgezal 0x04110000
16773 bltzall 0x04120000 bgezall 0x04130000 */
16774 insn
&= ~0x00100000;
16777 /* Branch over the branch (if the branch was likely) or the
16778 full jump (not likely case). Compute the offset from the
16779 current instruction to branch to. */
16780 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16784 /* How many bytes in instructions we've already emitted? */
16785 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16786 /* How many bytes in instructions from here to the end? */
16787 i
= fragp
->fr_var
- i
;
16789 /* Convert to instruction count. */
16791 /* Branch counts from the next instruction. */
16794 /* Branch over the jump. */
16795 buf
= write_insn (buf
, insn
);
16798 buf
= write_insn (buf
, 0);
16800 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16802 /* beql $0, $0, 2f */
16804 /* Compute the PC offset from the current instruction to
16805 the end of the variable frag. */
16806 /* How many bytes in instructions we've already emitted? */
16807 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16808 /* How many bytes in instructions from here to the end? */
16809 i
= fragp
->fr_var
- i
;
16810 /* Convert to instruction count. */
16812 /* Don't decrement i, because we want to branch over the
16816 buf
= write_insn (buf
, insn
);
16817 buf
= write_insn (buf
, 0);
16821 if (mips_pic
== NO_PIC
)
16824 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16825 ? 0x0c000000 : 0x08000000);
16826 exp
.X_op
= O_symbol
;
16827 exp
.X_add_symbol
= fragp
->fr_symbol
;
16828 exp
.X_add_number
= fragp
->fr_offset
;
16830 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16831 FALSE
, BFD_RELOC_MIPS_JMP
);
16832 fixp
->fx_file
= fragp
->fr_file
;
16833 fixp
->fx_line
= fragp
->fr_line
;
16835 buf
= write_insn (buf
, insn
);
16839 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16841 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16842 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16843 insn
|= at
<< OP_SH_RT
;
16844 exp
.X_op
= O_symbol
;
16845 exp
.X_add_symbol
= fragp
->fr_symbol
;
16846 exp
.X_add_number
= fragp
->fr_offset
;
16848 if (fragp
->fr_offset
)
16850 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16851 exp
.X_add_number
= 0;
16854 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16855 FALSE
, BFD_RELOC_MIPS_GOT16
);
16856 fixp
->fx_file
= fragp
->fr_file
;
16857 fixp
->fx_line
= fragp
->fr_line
;
16859 buf
= write_insn (buf
, insn
);
16861 if (mips_opts
.isa
== ISA_MIPS1
)
16863 buf
= write_insn (buf
, 0);
16865 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16866 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16867 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16869 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16870 FALSE
, BFD_RELOC_LO16
);
16871 fixp
->fx_file
= fragp
->fr_file
;
16872 fixp
->fx_line
= fragp
->fr_line
;
16874 buf
= write_insn (buf
, insn
);
16877 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16881 insn
|= at
<< OP_SH_RS
;
16883 buf
= write_insn (buf
, insn
);
16887 fragp
->fr_fix
+= fragp
->fr_var
;
16888 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16892 /* Relax microMIPS branches. */
16893 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16895 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16896 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16897 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16898 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16899 bfd_boolean short_ds
;
16900 unsigned long insn
;
16904 exp
.X_op
= O_symbol
;
16905 exp
.X_add_symbol
= fragp
->fr_symbol
;
16906 exp
.X_add_number
= fragp
->fr_offset
;
16908 fragp
->fr_fix
+= fragp
->fr_var
;
16910 /* Handle 16-bit branches that fit or are forced to fit. */
16911 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16913 /* We generate a fixup instead of applying it right now,
16914 because if there is linker relaxation, we're going to
16915 need the relocations. */
16917 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16918 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16919 else if (type
== 'E')
16920 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16921 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16925 fixp
->fx_file
= fragp
->fr_file
;
16926 fixp
->fx_line
= fragp
->fr_line
;
16928 /* These relocations can have an addend that won't fit in
16930 fixp
->fx_no_overflow
= 1;
16935 /* Handle 32-bit branches that fit or are forced to fit. */
16936 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16937 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16939 /* We generate a fixup instead of applying it right now,
16940 because if there is linker relaxation, we're going to
16941 need the relocations. */
16942 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16943 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16944 fixp
->fx_file
= fragp
->fr_file
;
16945 fixp
->fx_line
= fragp
->fr_line
;
16951 /* Relax 16-bit branches to 32-bit branches. */
16954 insn
= read_compressed_insn (buf
, 2);
16956 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16957 insn
= 0x94000000; /* beq */
16958 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16960 unsigned long regno
;
16962 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16963 regno
= micromips_to_32_reg_d_map
[regno
];
16964 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16965 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16970 /* Nothing else to do, just write it out. */
16971 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16972 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16974 buf
= write_compressed_insn (buf
, insn
, 4);
16975 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16980 insn
= read_compressed_insn (buf
, 4);
16982 /* Relax 32-bit branches to a sequence of instructions. */
16983 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16984 _("relaxed out-of-range branch into a jump"));
16986 /* Set the short-delay-slot bit. */
16987 short_ds
= al
&& (insn
& 0x02000000) != 0;
16989 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16993 /* Reverse the branch. */
16994 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16995 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16996 insn
^= 0x20000000;
16997 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16998 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16999 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17000 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17001 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17002 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17003 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17004 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17005 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17006 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17007 insn
^= 0x00400000;
17008 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17009 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17010 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17011 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17012 insn
^= 0x00200000;
17013 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17015 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17017 insn
^= 0x00800000;
17023 /* Clear the and-link and short-delay-slot bits. */
17024 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17026 /* bltzal 0x40200000 bgezal 0x40600000 */
17027 /* bltzals 0x42200000 bgezals 0x42600000 */
17028 insn
&= ~0x02200000;
17031 /* Make a label at the end for use with the branch. */
17032 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17033 micromips_label_inc ();
17034 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17037 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17038 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17039 fixp
->fx_file
= fragp
->fr_file
;
17040 fixp
->fx_line
= fragp
->fr_line
;
17042 /* Branch over the jump. */
17043 buf
= write_compressed_insn (buf
, insn
, 4);
17046 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17049 if (mips_pic
== NO_PIC
)
17051 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17053 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17054 insn
= al
? jal
: 0xd4000000;
17056 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17057 BFD_RELOC_MICROMIPS_JMP
);
17058 fixp
->fx_file
= fragp
->fr_file
;
17059 fixp
->fx_line
= fragp
->fr_line
;
17061 buf
= write_compressed_insn (buf
, insn
, 4);
17064 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17068 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17069 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17070 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17072 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17073 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17074 insn
|= at
<< MICROMIPSOP_SH_RT
;
17076 if (exp
.X_add_number
)
17078 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17079 exp
.X_add_number
= 0;
17082 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17083 BFD_RELOC_MICROMIPS_GOT16
);
17084 fixp
->fx_file
= fragp
->fr_file
;
17085 fixp
->fx_line
= fragp
->fr_line
;
17087 buf
= write_compressed_insn (buf
, insn
, 4);
17089 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17090 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17091 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17093 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17094 BFD_RELOC_MICROMIPS_LO16
);
17095 fixp
->fx_file
= fragp
->fr_file
;
17096 fixp
->fx_line
= fragp
->fr_line
;
17098 buf
= write_compressed_insn (buf
, insn
, 4);
17100 /* jr/jrc/jalr/jalrs $at */
17101 insn
= al
? jalr
: jr
;
17102 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17104 buf
= write_compressed_insn (buf
, insn
, 2);
17107 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17111 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17114 const struct mips_int_operand
*operand
;
17117 unsigned int user_length
, length
;
17118 unsigned long insn
;
17121 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17122 operand
= mips16_immed_operand (type
, FALSE
);
17124 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17125 val
= resolve_symbol_value (fragp
->fr_symbol
);
17126 if (operand
->root
.type
== OP_PCREL
)
17128 const struct mips_pcrel_operand
*pcrel_op
;
17131 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17132 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17134 /* The rules for the base address of a PC relative reloc are
17135 complicated; see mips16_extended_frag. */
17136 if (pcrel_op
->include_isa_bit
)
17141 /* Ignore the low bit in the target, since it will be
17142 set for a text label. */
17145 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17147 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17150 addr
&= -(1 << pcrel_op
->align_log2
);
17153 /* Make sure the section winds up with the alignment we have
17155 if (operand
->shift
> 0)
17156 record_alignment (asec
, operand
->shift
);
17160 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17161 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17162 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17163 _("extended instruction in delay slot"));
17165 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17167 insn
= read_compressed_insn (buf
, 2);
17169 insn
|= MIPS16_EXTEND
;
17171 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17173 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17178 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17179 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17181 length
= (ext
? 4 : 2);
17182 gas_assert (mips16_opcode_length (insn
) == length
);
17183 write_compressed_insn (buf
, insn
, length
);
17184 fragp
->fr_fix
+= length
;
17188 relax_substateT subtype
= fragp
->fr_subtype
;
17189 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17190 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17194 first
= RELAX_FIRST (subtype
);
17195 second
= RELAX_SECOND (subtype
);
17196 fixp
= (fixS
*) fragp
->fr_opcode
;
17198 /* If the delay slot chosen does not match the size of the instruction,
17199 then emit a warning. */
17200 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17201 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17206 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17207 | RELAX_DELAY_SLOT_SIZE_FIRST
17208 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17209 msg
= macro_warning (s
);
17211 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17215 /* Possibly emit a warning if we've chosen the longer option. */
17216 if (use_second
== second_longer
)
17222 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17223 msg
= macro_warning (s
);
17225 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17229 /* Go through all the fixups for the first sequence. Disable them
17230 (by marking them as done) if we're going to use the second
17231 sequence instead. */
17233 && fixp
->fx_frag
== fragp
17234 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17236 if (subtype
& RELAX_USE_SECOND
)
17238 fixp
= fixp
->fx_next
;
17241 /* Go through the fixups for the second sequence. Disable them if
17242 we're going to use the first sequence, otherwise adjust their
17243 addresses to account for the relaxation. */
17244 while (fixp
&& fixp
->fx_frag
== fragp
)
17246 if (subtype
& RELAX_USE_SECOND
)
17247 fixp
->fx_where
-= first
;
17250 fixp
= fixp
->fx_next
;
17253 /* Now modify the frag contents. */
17254 if (subtype
& RELAX_USE_SECOND
)
17258 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17259 memmove (start
, start
+ first
, second
);
17260 fragp
->fr_fix
-= first
;
17263 fragp
->fr_fix
-= second
;
17267 /* This function is called after the relocs have been generated.
17268 We've been storing mips16 text labels as odd. Here we convert them
17269 back to even for the convenience of the debugger. */
17272 mips_frob_file_after_relocs (void)
17275 unsigned int count
, i
;
17277 syms
= bfd_get_outsymbols (stdoutput
);
17278 count
= bfd_get_symcount (stdoutput
);
17279 for (i
= 0; i
< count
; i
++, syms
++)
17280 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17281 && ((*syms
)->value
& 1) != 0)
17283 (*syms
)->value
&= ~1;
17284 /* If the symbol has an odd size, it was probably computed
17285 incorrectly, so adjust that as well. */
17286 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17287 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17291 /* This function is called whenever a label is defined, including fake
17292 labels instantiated off the dot special symbol. It is used when
17293 handling branch delays; if a branch has a label, we assume we cannot
17294 move it. This also bumps the value of the symbol by 1 in compressed
17298 mips_record_label (symbolS
*sym
)
17300 segment_info_type
*si
= seg_info (now_seg
);
17301 struct insn_label_list
*l
;
17303 if (free_insn_labels
== NULL
)
17304 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17307 l
= free_insn_labels
;
17308 free_insn_labels
= l
->next
;
17312 l
->next
= si
->label_list
;
17313 si
->label_list
= l
;
17316 /* This function is called as tc_frob_label() whenever a label is defined
17317 and adds a DWARF-2 record we only want for true labels. */
17320 mips_define_label (symbolS
*sym
)
17322 mips_record_label (sym
);
17323 dwarf2_emit_label (sym
);
17326 /* This function is called by tc_new_dot_label whenever a new dot symbol
17330 mips_add_dot_label (symbolS
*sym
)
17332 mips_record_label (sym
);
17333 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17334 mips_compressed_mark_label (sym
);
17337 /* Some special processing for a MIPS ELF file. */
17340 mips_elf_final_processing (void)
17342 /* Write out the register information. */
17343 if (mips_abi
!= N64_ABI
)
17347 s
.ri_gprmask
= mips_gprmask
;
17348 s
.ri_cprmask
[0] = mips_cprmask
[0];
17349 s
.ri_cprmask
[1] = mips_cprmask
[1];
17350 s
.ri_cprmask
[2] = mips_cprmask
[2];
17351 s
.ri_cprmask
[3] = mips_cprmask
[3];
17352 /* The gp_value field is set by the MIPS ELF backend. */
17354 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17355 ((Elf32_External_RegInfo
*)
17356 mips_regmask_frag
));
17360 Elf64_Internal_RegInfo s
;
17362 s
.ri_gprmask
= mips_gprmask
;
17364 s
.ri_cprmask
[0] = mips_cprmask
[0];
17365 s
.ri_cprmask
[1] = mips_cprmask
[1];
17366 s
.ri_cprmask
[2] = mips_cprmask
[2];
17367 s
.ri_cprmask
[3] = mips_cprmask
[3];
17368 /* The gp_value field is set by the MIPS ELF backend. */
17370 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17371 ((Elf64_External_RegInfo
*)
17372 mips_regmask_frag
));
17375 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17376 sort of BFD interface for this. */
17377 if (mips_any_noreorder
)
17378 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17379 if (mips_pic
!= NO_PIC
)
17381 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17382 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17385 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17387 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17388 defined at present; this might need to change in future. */
17389 if (file_ase_mips16
)
17390 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17391 if (file_ase_micromips
)
17392 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17393 if (file_ase
& ASE_MDMX
)
17394 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17396 /* Set the MIPS ELF ABI flags. */
17397 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17398 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17399 else if (mips_abi
== O64_ABI
)
17400 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17401 else if (mips_abi
== EABI_ABI
)
17403 if (!file_mips_gp32
)
17404 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17406 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17408 else if (mips_abi
== N32_ABI
)
17409 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17411 /* Nothing to do for N64_ABI. */
17413 if (mips_32bitmode
)
17414 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17416 if (mips_flag_nan2008
)
17417 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17419 /* 32 bit code with 64 bit FP registers. */
17420 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17421 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
17424 typedef struct proc
{
17426 symbolS
*func_end_sym
;
17427 unsigned long reg_mask
;
17428 unsigned long reg_offset
;
17429 unsigned long fpreg_mask
;
17430 unsigned long fpreg_offset
;
17431 unsigned long frame_offset
;
17432 unsigned long frame_reg
;
17433 unsigned long pc_reg
;
17436 static procS cur_proc
;
17437 static procS
*cur_proc_ptr
;
17438 static int numprocs
;
17440 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17441 as "2", and a normal nop as "0". */
17443 #define NOP_OPCODE_MIPS 0
17444 #define NOP_OPCODE_MIPS16 1
17445 #define NOP_OPCODE_MICROMIPS 2
17448 mips_nop_opcode (void)
17450 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17451 return NOP_OPCODE_MICROMIPS
;
17452 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17453 return NOP_OPCODE_MIPS16
;
17455 return NOP_OPCODE_MIPS
;
17458 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17459 32-bit microMIPS NOPs here (if applicable). */
17462 mips_handle_align (fragS
*fragp
)
17466 int bytes
, size
, excess
;
17469 if (fragp
->fr_type
!= rs_align_code
)
17472 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17474 switch (nop_opcode
)
17476 case NOP_OPCODE_MICROMIPS
:
17477 opcode
= micromips_nop32_insn
.insn_opcode
;
17480 case NOP_OPCODE_MIPS16
:
17481 opcode
= mips16_nop_insn
.insn_opcode
;
17484 case NOP_OPCODE_MIPS
:
17486 opcode
= nop_insn
.insn_opcode
;
17491 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17492 excess
= bytes
% size
;
17494 /* Handle the leading part if we're not inserting a whole number of
17495 instructions, and make it the end of the fixed part of the frag.
17496 Try to fit in a short microMIPS NOP if applicable and possible,
17497 and use zeroes otherwise. */
17498 gas_assert (excess
< 4);
17499 fragp
->fr_fix
+= excess
;
17504 /* Fall through. */
17506 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17508 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17512 /* Fall through. */
17515 /* Fall through. */
17520 md_number_to_chars (p
, opcode
, size
);
17521 fragp
->fr_var
= size
;
17525 md_obj_begin (void)
17532 /* Check for premature end, nesting errors, etc. */
17534 as_warn (_("missing .end at end of assembly"));
17543 if (*input_line_pointer
== '-')
17545 ++input_line_pointer
;
17548 if (!ISDIGIT (*input_line_pointer
))
17549 as_bad (_("expected simple number"));
17550 if (input_line_pointer
[0] == '0')
17552 if (input_line_pointer
[1] == 'x')
17554 input_line_pointer
+= 2;
17555 while (ISXDIGIT (*input_line_pointer
))
17558 val
|= hex_value (*input_line_pointer
++);
17560 return negative
? -val
: val
;
17564 ++input_line_pointer
;
17565 while (ISDIGIT (*input_line_pointer
))
17568 val
|= *input_line_pointer
++ - '0';
17570 return negative
? -val
: val
;
17573 if (!ISDIGIT (*input_line_pointer
))
17575 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17576 *input_line_pointer
, *input_line_pointer
);
17577 as_warn (_("invalid number"));
17580 while (ISDIGIT (*input_line_pointer
))
17583 val
+= *input_line_pointer
++ - '0';
17585 return negative
? -val
: val
;
17588 /* The .file directive; just like the usual .file directive, but there
17589 is an initial number which is the ECOFF file index. In the non-ECOFF
17590 case .file implies DWARF-2. */
17593 s_mips_file (int x ATTRIBUTE_UNUSED
)
17595 static int first_file_directive
= 0;
17597 if (ECOFF_DEBUGGING
)
17606 filename
= dwarf2_directive_file (0);
17608 /* Versions of GCC up to 3.1 start files with a ".file"
17609 directive even for stabs output. Make sure that this
17610 ".file" is handled. Note that you need a version of GCC
17611 after 3.1 in order to support DWARF-2 on MIPS. */
17612 if (filename
!= NULL
&& ! first_file_directive
)
17614 (void) new_logical_line (filename
, -1);
17615 s_app_file_string (filename
, 0);
17617 first_file_directive
= 1;
17621 /* The .loc directive, implying DWARF-2. */
17624 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17626 if (!ECOFF_DEBUGGING
)
17627 dwarf2_directive_loc (0);
17630 /* The .end directive. */
17633 s_mips_end (int x ATTRIBUTE_UNUSED
)
17637 /* Following functions need their own .frame and .cprestore directives. */
17638 mips_frame_reg_valid
= 0;
17639 mips_cprestore_valid
= 0;
17641 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17644 demand_empty_rest_of_line ();
17649 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17650 as_warn (_(".end not in text section"));
17654 as_warn (_(".end directive without a preceding .ent directive"));
17655 demand_empty_rest_of_line ();
17661 gas_assert (S_GET_NAME (p
));
17662 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17663 as_warn (_(".end symbol does not match .ent symbol"));
17665 if (debug_type
== DEBUG_STABS
)
17666 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17670 as_warn (_(".end directive missing or unknown symbol"));
17672 /* Create an expression to calculate the size of the function. */
17673 if (p
&& cur_proc_ptr
)
17675 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17676 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17679 exp
->X_op
= O_subtract
;
17680 exp
->X_add_symbol
= symbol_temp_new_now ();
17681 exp
->X_op_symbol
= p
;
17682 exp
->X_add_number
= 0;
17684 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17687 /* Generate a .pdr section. */
17688 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17690 segT saved_seg
= now_seg
;
17691 subsegT saved_subseg
= now_subseg
;
17695 #ifdef md_flush_pending_output
17696 md_flush_pending_output ();
17699 gas_assert (pdr_seg
);
17700 subseg_set (pdr_seg
, 0);
17702 /* Write the symbol. */
17703 exp
.X_op
= O_symbol
;
17704 exp
.X_add_symbol
= p
;
17705 exp
.X_add_number
= 0;
17706 emit_expr (&exp
, 4);
17708 fragp
= frag_more (7 * 4);
17710 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17711 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17712 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17713 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17714 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17715 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17716 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17718 subseg_set (saved_seg
, saved_subseg
);
17721 cur_proc_ptr
= NULL
;
17724 /* The .aent and .ent directives. */
17727 s_mips_ent (int aent
)
17731 symbolP
= get_symbol ();
17732 if (*input_line_pointer
== ',')
17733 ++input_line_pointer
;
17734 SKIP_WHITESPACE ();
17735 if (ISDIGIT (*input_line_pointer
)
17736 || *input_line_pointer
== '-')
17739 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17740 as_warn (_(".ent or .aent not in text section"));
17742 if (!aent
&& cur_proc_ptr
)
17743 as_warn (_("missing .end"));
17747 /* This function needs its own .frame and .cprestore directives. */
17748 mips_frame_reg_valid
= 0;
17749 mips_cprestore_valid
= 0;
17751 cur_proc_ptr
= &cur_proc
;
17752 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17754 cur_proc_ptr
->func_sym
= symbolP
;
17758 if (debug_type
== DEBUG_STABS
)
17759 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17760 S_GET_NAME (symbolP
));
17763 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17765 demand_empty_rest_of_line ();
17768 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17769 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17770 s_mips_frame is used so that we can set the PDR information correctly.
17771 We can't use the ecoff routines because they make reference to the ecoff
17772 symbol table (in the mdebug section). */
17775 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17777 if (ECOFF_DEBUGGING
)
17783 if (cur_proc_ptr
== (procS
*) NULL
)
17785 as_warn (_(".frame outside of .ent"));
17786 demand_empty_rest_of_line ();
17790 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17792 SKIP_WHITESPACE ();
17793 if (*input_line_pointer
++ != ','
17794 || get_absolute_expression_and_terminator (&val
) != ',')
17796 as_warn (_("bad .frame directive"));
17797 --input_line_pointer
;
17798 demand_empty_rest_of_line ();
17802 cur_proc_ptr
->frame_offset
= val
;
17803 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17805 demand_empty_rest_of_line ();
17809 /* The .fmask and .mask directives. If the mdebug section is present
17810 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17811 embedded targets, s_mips_mask is used so that we can set the PDR
17812 information correctly. We can't use the ecoff routines because they
17813 make reference to the ecoff symbol table (in the mdebug section). */
17816 s_mips_mask (int reg_type
)
17818 if (ECOFF_DEBUGGING
)
17819 s_ignore (reg_type
);
17824 if (cur_proc_ptr
== (procS
*) NULL
)
17826 as_warn (_(".mask/.fmask outside of .ent"));
17827 demand_empty_rest_of_line ();
17831 if (get_absolute_expression_and_terminator (&mask
) != ',')
17833 as_warn (_("bad .mask/.fmask directive"));
17834 --input_line_pointer
;
17835 demand_empty_rest_of_line ();
17839 off
= get_absolute_expression ();
17841 if (reg_type
== 'F')
17843 cur_proc_ptr
->fpreg_mask
= mask
;
17844 cur_proc_ptr
->fpreg_offset
= off
;
17848 cur_proc_ptr
->reg_mask
= mask
;
17849 cur_proc_ptr
->reg_offset
= off
;
17852 demand_empty_rest_of_line ();
17856 /* A table describing all the processors gas knows about. Names are
17857 matched in the order listed.
17859 To ease comparison, please keep this table in the same order as
17860 gcc's mips_cpu_info_table[]. */
17861 static const struct mips_cpu_info mips_cpu_info_table
[] =
17863 /* Entries for generic ISAs */
17864 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17865 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17866 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17867 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17868 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17869 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17870 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17871 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
17872 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
17873 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17874 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17875 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
17876 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
17879 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17880 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17881 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17884 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17887 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17888 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17889 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17890 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17891 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17892 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17893 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17894 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17895 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17896 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17897 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17898 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17899 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17900 /* ST Microelectronics Loongson 2E and 2F cores */
17901 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17902 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17905 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17906 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17907 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17908 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17909 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17910 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17911 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17912 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17913 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17914 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17915 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17916 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17917 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17918 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17919 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17922 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17923 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17924 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17925 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17927 /* MIPS 32 Release 2 */
17928 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17929 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17930 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17931 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17932 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17933 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17934 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17935 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17936 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17937 ISA_MIPS32R2
, CPU_MIPS32R2
},
17938 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17939 ISA_MIPS32R2
, CPU_MIPS32R2
},
17940 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17941 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17942 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17943 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17944 /* Deprecated forms of the above. */
17945 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17946 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17947 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17948 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17949 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17950 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17951 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17952 /* Deprecated forms of the above. */
17953 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17954 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17955 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17956 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17957 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17958 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17959 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17960 /* Deprecated forms of the above. */
17961 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17962 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17963 /* 34Kn is a 34kc without DSP. */
17964 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17965 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17966 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17967 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17968 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17969 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17970 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17971 /* Deprecated forms of the above. */
17972 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17973 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17974 /* 1004K cores are multiprocessor versions of the 34K. */
17975 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17976 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17977 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17978 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17979 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
17980 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
17983 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17984 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17985 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17986 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17988 /* Broadcom SB-1 CPU core */
17989 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17990 /* Broadcom SB-1A CPU core */
17991 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17993 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
17995 /* MIPS 64 Release 2 */
17997 /* Cavium Networks Octeon CPU core */
17998 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17999 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18000 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18003 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18006 XLP is mostly like XLR, with the prominent exception that it is
18007 MIPS64R2 rather than MIPS64. */
18008 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18011 { NULL
, 0, 0, 0, 0 }
18015 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18016 with a final "000" replaced by "k". Ignore case.
18018 Note: this function is shared between GCC and GAS. */
18021 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18023 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18024 given
++, canonical
++;
18026 return ((*given
== 0 && *canonical
== 0)
18027 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18031 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18032 CPU name. We've traditionally allowed a lot of variation here.
18034 Note: this function is shared between GCC and GAS. */
18037 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18039 /* First see if the name matches exactly, or with a final "000"
18040 turned into "k". */
18041 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18044 /* If not, try comparing based on numerical designation alone.
18045 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18046 if (TOLOWER (*given
) == 'r')
18048 if (!ISDIGIT (*given
))
18051 /* Skip over some well-known prefixes in the canonical name,
18052 hoping to find a number there too. */
18053 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18055 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18057 else if (TOLOWER (canonical
[0]) == 'r')
18060 return mips_strict_matching_cpu_name_p (canonical
, given
);
18064 /* Parse an option that takes the name of a processor as its argument.
18065 OPTION is the name of the option and CPU_STRING is the argument.
18066 Return the corresponding processor enumeration if the CPU_STRING is
18067 recognized, otherwise report an error and return null.
18069 A similar function exists in GCC. */
18071 static const struct mips_cpu_info
*
18072 mips_parse_cpu (const char *option
, const char *cpu_string
)
18074 const struct mips_cpu_info
*p
;
18076 /* 'from-abi' selects the most compatible architecture for the given
18077 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18078 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18079 version. Look first at the -mgp options, if given, otherwise base
18080 the choice on MIPS_DEFAULT_64BIT.
18082 Treat NO_ABI like the EABIs. One reason to do this is that the
18083 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18084 architecture. This code picks MIPS I for 'mips' and MIPS III for
18085 'mips64', just as we did in the days before 'from-abi'. */
18086 if (strcasecmp (cpu_string
, "from-abi") == 0)
18088 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18089 return mips_cpu_info_from_isa (ISA_MIPS1
);
18091 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18092 return mips_cpu_info_from_isa (ISA_MIPS3
);
18094 if (file_mips_gp32
>= 0)
18095 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
18097 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18102 /* 'default' has traditionally been a no-op. Probably not very useful. */
18103 if (strcasecmp (cpu_string
, "default") == 0)
18106 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18107 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18110 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18114 /* Return the canonical processor information for ISA (a member of the
18115 ISA_MIPS* enumeration). */
18117 static const struct mips_cpu_info
*
18118 mips_cpu_info_from_isa (int isa
)
18122 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18123 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18124 && isa
== mips_cpu_info_table
[i
].isa
)
18125 return (&mips_cpu_info_table
[i
]);
18130 static const struct mips_cpu_info
*
18131 mips_cpu_info_from_arch (int arch
)
18135 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18136 if (arch
== mips_cpu_info_table
[i
].cpu
)
18137 return (&mips_cpu_info_table
[i
]);
18143 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18147 fprintf (stream
, "%24s", "");
18152 fprintf (stream
, ", ");
18156 if (*col_p
+ strlen (string
) > 72)
18158 fprintf (stream
, "\n%24s", "");
18162 fprintf (stream
, "%s", string
);
18163 *col_p
+= strlen (string
);
18169 md_show_usage (FILE *stream
)
18174 fprintf (stream
, _("\
18176 -EB generate big endian output\n\
18177 -EL generate little endian output\n\
18178 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18179 -G NUM allow referencing objects up to NUM bytes\n\
18180 implicitly with the gp register [default 8]\n"));
18181 fprintf (stream
, _("\
18182 -mips1 generate MIPS ISA I instructions\n\
18183 -mips2 generate MIPS ISA II instructions\n\
18184 -mips3 generate MIPS ISA III instructions\n\
18185 -mips4 generate MIPS ISA IV instructions\n\
18186 -mips5 generate MIPS ISA V instructions\n\
18187 -mips32 generate MIPS32 ISA instructions\n\
18188 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18189 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18190 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18191 -mips64 generate MIPS64 ISA instructions\n\
18192 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18193 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18194 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18195 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18199 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18200 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18201 show (stream
, "from-abi", &column
, &first
);
18202 fputc ('\n', stream
);
18204 fprintf (stream
, _("\
18205 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18206 -no-mCPU don't generate code specific to CPU.\n\
18207 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18211 show (stream
, "3900", &column
, &first
);
18212 show (stream
, "4010", &column
, &first
);
18213 show (stream
, "4100", &column
, &first
);
18214 show (stream
, "4650", &column
, &first
);
18215 fputc ('\n', stream
);
18217 fprintf (stream
, _("\
18218 -mips16 generate mips16 instructions\n\
18219 -no-mips16 do not generate mips16 instructions\n"));
18220 fprintf (stream
, _("\
18221 -mmicromips generate microMIPS instructions\n\
18222 -mno-micromips do not generate microMIPS instructions\n"));
18223 fprintf (stream
, _("\
18224 -msmartmips generate smartmips instructions\n\
18225 -mno-smartmips do not generate smartmips instructions\n"));
18226 fprintf (stream
, _("\
18227 -mdsp generate DSP instructions\n\
18228 -mno-dsp do not generate DSP instructions\n"));
18229 fprintf (stream
, _("\
18230 -mdspr2 generate DSP R2 instructions\n\
18231 -mno-dspr2 do not generate DSP R2 instructions\n"));
18232 fprintf (stream
, _("\
18233 -mmt generate MT instructions\n\
18234 -mno-mt do not generate MT instructions\n"));
18235 fprintf (stream
, _("\
18236 -mmcu generate MCU instructions\n\
18237 -mno-mcu do not generate MCU instructions\n"));
18238 fprintf (stream
, _("\
18239 -mmsa generate MSA instructions\n\
18240 -mno-msa do not generate MSA instructions\n"));
18241 fprintf (stream
, _("\
18242 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18243 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18244 fprintf (stream
, _("\
18245 -mvirt generate Virtualization instructions\n\
18246 -mno-virt do not generate Virtualization instructions\n"));
18247 fprintf (stream
, _("\
18248 -minsn32 only generate 32-bit microMIPS instructions\n\
18249 -mno-insn32 generate all microMIPS instructions\n"));
18250 fprintf (stream
, _("\
18251 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18252 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18253 -mfix-vr4120 work around certain VR4120 errata\n\
18254 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18255 -mfix-24k insert a nop after ERET and DERET instructions\n\
18256 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18257 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18258 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18259 -msym32 assume all symbols have 32-bit values\n\
18260 -O0 remove unneeded NOPs, do not swap branches\n\
18261 -O remove unneeded NOPs and swap branches\n\
18262 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18263 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18264 fprintf (stream
, _("\
18265 -mhard-float allow floating-point instructions\n\
18266 -msoft-float do not allow floating-point instructions\n\
18267 -msingle-float only allow 32-bit floating-point operations\n\
18268 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18269 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18270 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18271 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18275 show (stream
, "legacy", &column
, &first
);
18276 show (stream
, "2008", &column
, &first
);
18278 fputc ('\n', stream
);
18280 fprintf (stream
, _("\
18281 -KPIC, -call_shared generate SVR4 position independent code\n\
18282 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18283 -mvxworks-pic generate VxWorks position independent code\n\
18284 -non_shared do not generate code that can operate with DSOs\n\
18285 -xgot assume a 32 bit GOT\n\
18286 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18287 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18288 position dependent (non shared) code\n\
18289 -mabi=ABI create ABI conformant object file for:\n"));
18293 show (stream
, "32", &column
, &first
);
18294 show (stream
, "o64", &column
, &first
);
18295 show (stream
, "n32", &column
, &first
);
18296 show (stream
, "64", &column
, &first
);
18297 show (stream
, "eabi", &column
, &first
);
18299 fputc ('\n', stream
);
18301 fprintf (stream
, _("\
18302 -32 create o32 ABI object file (default)\n\
18303 -n32 create n32 ABI object file\n\
18304 -64 create 64 ABI object file\n"));
18309 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18311 if (HAVE_64BIT_SYMBOLS
)
18312 return dwarf2_format_64bit_irix
;
18314 return dwarf2_format_32bit
;
18319 mips_dwarf2_addr_size (void)
18321 if (HAVE_64BIT_OBJECTS
)
18327 /* Standard calling conventions leave the CFA at SP on entry. */
18329 mips_cfi_frame_initial_instructions (void)
18331 cfi_add_CFA_def_cfa_register (SP
);
18335 tc_mips_regname_to_dw2regnum (char *regname
)
18337 unsigned int regnum
= -1;
18340 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))