1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes
[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p
;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length
;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes
[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes
[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns
[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning
;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1332 static void append_insn
1333 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1334 bfd_boolean expansionp
);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS
*, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS
*, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS
*, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn
*ip
, char *str
);
1343 static void mips16_macro (struct mips_cl_insn
* ip
);
1344 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1345 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1346 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1352 static void my_getExpression (expressionS
*, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type
);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean
pic_need_relax (symbolS
*);
1388 static int relaxed_branch_length (fragS
*, asection
*, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name
; /* CPU or ISA name. */
1399 int flags
; /* MIPS_CPU_* flags. */
1400 int ase
; /* Set of ASEs implemented by the CPU. */
1401 int isa
; /* ISA level. */
1402 int cpu
; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts
= "O::g::G:";
1416 OPTION_MARCH
= OPTION_MD_BASE
,
1448 OPTION_NO_SMARTMIPS
,
1458 OPTION_NO_MICROMIPS
,
1473 OPTION_M7000_HILO_FIX
,
1474 OPTION_MNO_7000_HILO_FIX
,
1478 OPTION_NO_FIX_RM7000
,
1479 OPTION_FIX_LOONGSON2F_JUMP
,
1480 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1481 OPTION_FIX_LOONGSON2F_NOP
,
1482 OPTION_NO_FIX_LOONGSON2F_NOP
,
1484 OPTION_NO_FIX_VR4120
,
1486 OPTION_NO_FIX_VR4130
,
1487 OPTION_FIX_CN63XXP1
,
1488 OPTION_NO_FIX_CN63XXP1
,
1495 OPTION_CONSTRUCT_FLOATS
,
1496 OPTION_NO_CONSTRUCT_FLOATS
,
1500 OPTION_RELAX_BRANCH
,
1501 OPTION_NO_RELAX_BRANCH
,
1502 OPTION_IGNORE_BRANCH_ISA
,
1503 OPTION_NO_IGNORE_BRANCH_ISA
,
1512 OPTION_SINGLE_FLOAT
,
1513 OPTION_DOUBLE_FLOAT
,
1526 OPTION_MVXWORKS_PIC
,
1529 OPTION_NO_ODD_SPREG
,
1532 OPTION_LOONGSON_MMI
,
1533 OPTION_NO_LOONGSON_MMI
,
1534 OPTION_LOONGSON_CAM
,
1535 OPTION_NO_LOONGSON_CAM
,
1539 struct option md_longopts
[] =
1541 /* Options which specify architecture. */
1542 {"march", required_argument
, NULL
, OPTION_MARCH
},
1543 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1544 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1545 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1546 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1547 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1548 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1549 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1550 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1551 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1552 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1553 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1554 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1555 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1556 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1557 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1558 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1559 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1561 /* Options which specify Application Specific Extensions (ASEs). */
1562 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1563 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1564 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1565 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1566 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1567 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1568 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1569 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1570 {"mmt", no_argument
, NULL
, OPTION_MT
},
1571 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1572 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1573 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1574 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1575 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1576 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1577 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1578 {"meva", no_argument
, NULL
, OPTION_EVA
},
1579 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1580 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1581 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1582 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1583 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1584 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1585 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1586 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1587 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1588 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1589 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1590 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1591 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1592 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1593 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1594 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1595 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1596 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1597 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1598 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1599 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1601 /* Old-style architecture options. Don't add more of these. */
1602 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1603 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1604 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1605 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1606 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1607 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1608 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1609 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1611 /* Options which enable bug fixes. */
1612 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1613 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1614 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1615 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1616 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1617 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1618 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1619 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1620 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1621 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1622 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1623 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1624 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1625 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1626 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1627 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1628 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1630 /* Miscellaneous options. */
1631 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1632 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1633 {"break", no_argument
, NULL
, OPTION_BREAK
},
1634 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1635 {"EB", no_argument
, NULL
, OPTION_EB
},
1636 {"EL", no_argument
, NULL
, OPTION_EL
},
1637 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1638 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1639 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1640 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1641 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1642 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1643 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1644 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1645 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1646 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1647 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1648 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1649 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1650 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1651 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1652 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1653 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1654 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1655 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1656 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1657 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1658 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1659 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1661 /* Strictly speaking this next option is ELF specific,
1662 but we allow it for other ports as well in order to
1663 make testing easier. */
1664 {"32", no_argument
, NULL
, OPTION_32
},
1666 /* ELF-specific options. */
1667 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1668 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1669 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1670 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1671 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1672 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1673 {"n32", no_argument
, NULL
, OPTION_N32
},
1674 {"64", no_argument
, NULL
, OPTION_64
},
1675 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1676 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1677 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1678 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1679 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1680 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1682 {NULL
, no_argument
, NULL
, 0}
1684 size_t md_longopts_size
= sizeof (md_longopts
);
1686 /* Information about either an Application Specific Extension or an
1687 optional architecture feature that, for simplicity, we treat in the
1688 same way as an ASE. */
1691 /* The name of the ASE, used in both the command-line and .set options. */
1694 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1695 and 64-bit architectures, the flags here refer to the subset that
1696 is available on both. */
1699 /* The ASE_* flag used for instructions that are available on 64-bit
1700 architectures but that are not included in FLAGS. */
1701 unsigned int flags64
;
1703 /* The command-line options that turn the ASE on and off. */
1707 /* The minimum required architecture revisions for MIPS32, MIPS64,
1708 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1711 int micromips32_rev
;
1712 int micromips64_rev
;
1714 /* The architecture where the ASE was removed or -1 if the extension has not
1719 /* A table of all supported ASEs. */
1720 static const struct mips_ase mips_ases
[] = {
1721 { "dsp", ASE_DSP
, ASE_DSP64
,
1722 OPTION_DSP
, OPTION_NO_DSP
,
1726 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1727 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1731 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1732 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1736 { "eva", ASE_EVA
, 0,
1737 OPTION_EVA
, OPTION_NO_EVA
,
1741 { "mcu", ASE_MCU
, 0,
1742 OPTION_MCU
, OPTION_NO_MCU
,
1746 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1747 { "mdmx", ASE_MDMX
, 0,
1748 OPTION_MDMX
, OPTION_NO_MDMX
,
1752 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1753 { "mips3d", ASE_MIPS3D
, 0,
1754 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1759 OPTION_MT
, OPTION_NO_MT
,
1763 { "smartmips", ASE_SMARTMIPS
, 0,
1764 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1768 { "virt", ASE_VIRT
, ASE_VIRT64
,
1769 OPTION_VIRT
, OPTION_NO_VIRT
,
1773 { "msa", ASE_MSA
, ASE_MSA64
,
1774 OPTION_MSA
, OPTION_NO_MSA
,
1778 { "xpa", ASE_XPA
, 0,
1779 OPTION_XPA
, OPTION_NO_XPA
,
1783 { "mips16e2", ASE_MIPS16E2
, 0,
1784 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1788 { "crc", ASE_CRC
, ASE_CRC64
,
1789 OPTION_CRC
, OPTION_NO_CRC
,
1793 { "ginv", ASE_GINV
, 0,
1794 OPTION_GINV
, OPTION_NO_GINV
,
1798 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1799 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1803 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1804 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1809 /* The set of ASEs that require -mfp64. */
1810 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1812 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1813 static const unsigned int mips_ase_groups
[] = {
1814 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1819 The following pseudo-ops from the Kane and Heinrich MIPS book
1820 should be defined here, but are currently unsupported: .alias,
1821 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1823 The following pseudo-ops from the Kane and Heinrich MIPS book are
1824 specific to the type of debugging information being generated, and
1825 should be defined by the object format: .aent, .begin, .bend,
1826 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1829 The following pseudo-ops from the Kane and Heinrich MIPS book are
1830 not MIPS CPU specific, but are also not specific to the object file
1831 format. This file is probably the best place to define them, but
1832 they are not currently supported: .asm0, .endr, .lab, .struct. */
1834 static const pseudo_typeS mips_pseudo_table
[] =
1836 /* MIPS specific pseudo-ops. */
1837 {"option", s_option
, 0},
1838 {"set", s_mipsset
, 0},
1839 {"rdata", s_change_sec
, 'r'},
1840 {"sdata", s_change_sec
, 's'},
1841 {"livereg", s_ignore
, 0},
1842 {"abicalls", s_abicalls
, 0},
1843 {"cpload", s_cpload
, 0},
1844 {"cpsetup", s_cpsetup
, 0},
1845 {"cplocal", s_cplocal
, 0},
1846 {"cprestore", s_cprestore
, 0},
1847 {"cpreturn", s_cpreturn
, 0},
1848 {"dtprelword", s_dtprelword
, 0},
1849 {"dtpreldword", s_dtpreldword
, 0},
1850 {"tprelword", s_tprelword
, 0},
1851 {"tpreldword", s_tpreldword
, 0},
1852 {"gpvalue", s_gpvalue
, 0},
1853 {"gpword", s_gpword
, 0},
1854 {"gpdword", s_gpdword
, 0},
1855 {"ehword", s_ehword
, 0},
1856 {"cpadd", s_cpadd
, 0},
1857 {"insn", s_insn
, 0},
1859 {"module", s_module
, 0},
1861 /* Relatively generic pseudo-ops that happen to be used on MIPS
1863 {"asciiz", stringer
, 8 + 1},
1864 {"bss", s_change_sec
, 'b'},
1866 {"half", s_cons
, 1},
1867 {"dword", s_cons
, 3},
1868 {"weakext", s_mips_weakext
, 0},
1869 {"origin", s_org
, 0},
1870 {"repeat", s_rept
, 0},
1872 /* For MIPS this is non-standard, but we define it for consistency. */
1873 {"sbss", s_change_sec
, 'B'},
1875 /* These pseudo-ops are defined in read.c, but must be overridden
1876 here for one reason or another. */
1877 {"align", s_align
, 0},
1878 {"byte", s_cons
, 0},
1879 {"data", s_change_sec
, 'd'},
1880 {"double", s_float_cons
, 'd'},
1881 {"float", s_float_cons
, 'f'},
1882 {"globl", s_mips_globl
, 0},
1883 {"global", s_mips_globl
, 0},
1884 {"hword", s_cons
, 1},
1886 {"long", s_cons
, 2},
1887 {"octa", s_cons
, 4},
1888 {"quad", s_cons
, 3},
1889 {"section", s_change_section
, 0},
1890 {"short", s_cons
, 1},
1891 {"single", s_float_cons
, 'f'},
1892 {"stabd", s_mips_stab
, 'd'},
1893 {"stabn", s_mips_stab
, 'n'},
1894 {"stabs", s_mips_stab
, 's'},
1895 {"text", s_change_sec
, 't'},
1896 {"word", s_cons
, 2},
1898 { "extern", ecoff_directive_extern
, 0},
1903 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1905 /* These pseudo-ops should be defined by the object file format.
1906 However, a.out doesn't support them, so we have versions here. */
1907 {"aent", s_mips_ent
, 1},
1908 {"bgnb", s_ignore
, 0},
1909 {"end", s_mips_end
, 0},
1910 {"endb", s_ignore
, 0},
1911 {"ent", s_mips_ent
, 0},
1912 {"file", s_mips_file
, 0},
1913 {"fmask", s_mips_mask
, 'F'},
1914 {"frame", s_mips_frame
, 0},
1915 {"loc", s_mips_loc
, 0},
1916 {"mask", s_mips_mask
, 'R'},
1917 {"verstamp", s_ignore
, 0},
1921 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1922 purpose of the `.dc.a' internal pseudo-op. */
1925 mips_address_bytes (void)
1927 file_mips_check_options ();
1928 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1931 extern void pop_insert (const pseudo_typeS
*);
1934 mips_pop_insert (void)
1936 pop_insert (mips_pseudo_table
);
1937 if (! ECOFF_DEBUGGING
)
1938 pop_insert (mips_nonecoff_pseudo_table
);
1941 /* Symbols labelling the current insn. */
1943 struct insn_label_list
1945 struct insn_label_list
*next
;
1949 static struct insn_label_list
*free_insn_labels
;
1950 #define label_list tc_segment_info_data.labels
1952 static void mips_clear_insn_labels (void);
1953 static void mips_mark_labels (void);
1954 static void mips_compressed_mark_labels (void);
1957 mips_clear_insn_labels (void)
1959 struct insn_label_list
**pl
;
1960 segment_info_type
*si
;
1964 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1967 si
= seg_info (now_seg
);
1968 *pl
= si
->label_list
;
1969 si
->label_list
= NULL
;
1973 /* Mark instruction labels in MIPS16/microMIPS mode. */
1976 mips_mark_labels (void)
1978 if (HAVE_CODE_COMPRESSION
)
1979 mips_compressed_mark_labels ();
1982 static char *expr_end
;
1984 /* An expression in a macro instruction. This is set by mips_ip and
1985 mips16_ip and when populated is always an O_constant. */
1987 static expressionS imm_expr
;
1989 /* The relocatable field in an instruction and the relocs associated
1990 with it. These variables are used for instructions like LUI and
1991 JAL as well as true offsets. They are also used for address
1992 operands in macros. */
1994 static expressionS offset_expr
;
1995 static bfd_reloc_code_real_type offset_reloc
[3]
1996 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1998 /* This is set to the resulting size of the instruction to be produced
1999 by mips16_ip if an explicit extension is used or by mips_ip if an
2000 explicit size is supplied. */
2002 static unsigned int forced_insn_length
;
2004 /* True if we are assembling an instruction. All dot symbols defined during
2005 this time should be treated as code labels. */
2007 static bfd_boolean mips_assembling_insn
;
2009 /* The pdr segment for per procedure frame/regmask info. Not used for
2012 static segT pdr_seg
;
2014 /* The default target format to use. */
2016 #if defined (TE_FreeBSD)
2017 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2018 #elif defined (TE_TMIPS)
2019 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2021 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2025 mips_target_format (void)
2027 switch (OUTPUT_FLAVOR
)
2029 case bfd_target_elf_flavour
:
2031 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2032 return (target_big_endian
2033 ? "elf32-bigmips-vxworks"
2034 : "elf32-littlemips-vxworks");
2036 return (target_big_endian
2037 ? (HAVE_64BIT_OBJECTS
2038 ? ELF_TARGET ("elf64-", "big")
2040 ? ELF_TARGET ("elf32-n", "big")
2041 : ELF_TARGET ("elf32-", "big")))
2042 : (HAVE_64BIT_OBJECTS
2043 ? ELF_TARGET ("elf64-", "little")
2045 ? ELF_TARGET ("elf32-n", "little")
2046 : ELF_TARGET ("elf32-", "little"))));
2053 /* Return the ISA revision that is currently in use, or 0 if we are
2054 generating code for MIPS V or below. */
2059 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2062 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2065 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2068 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2071 /* microMIPS implies revision 2 or above. */
2072 if (mips_opts
.micromips
)
2075 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2081 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2084 mips_ase_mask (unsigned int flags
)
2088 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2089 if (flags
& mips_ase_groups
[i
])
2090 flags
|= mips_ase_groups
[i
];
2094 /* Check whether the current ISA supports ASE. Issue a warning if
2098 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2102 static unsigned int warned_isa
;
2103 static unsigned int warned_fp32
;
2105 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2106 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2108 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2109 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2110 && (warned_isa
& ase
->flags
) != ase
->flags
)
2112 warned_isa
|= ase
->flags
;
2113 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2114 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2116 as_warn (_("the %d-bit %s architecture does not support the"
2117 " `%s' extension"), size
, base
, ase
->name
);
2119 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2120 ase
->name
, base
, size
, min_rev
);
2122 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2123 && (warned_isa
& ase
->flags
) != ase
->flags
)
2125 warned_isa
|= ase
->flags
;
2126 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2127 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2128 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2129 ase
->name
, base
, size
, ase
->rem_rev
);
2132 if ((ase
->flags
& FP64_ASES
)
2133 && mips_opts
.fp
!= 64
2134 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2136 warned_fp32
|= ase
->flags
;
2137 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2141 /* Check all enabled ASEs to see whether they are supported by the
2142 chosen architecture. */
2145 mips_check_isa_supports_ases (void)
2147 unsigned int i
, mask
;
2149 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2151 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2152 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2153 mips_check_isa_supports_ase (&mips_ases
[i
]);
2157 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2158 that were affected. */
2161 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2162 bfd_boolean enabled_p
)
2166 mask
= mips_ase_mask (ase
->flags
);
2169 /* Clear combination ASE flags, which need to be recalculated based on
2170 updated regular ASE settings. */
2171 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2174 opts
->ase
|= ase
->flags
;
2176 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2177 instructions which are only valid when both ASEs are enabled.
2178 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2179 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2181 opts
->ase
|= ASE_XPA_VIRT
;
2182 mask
|= ASE_XPA_VIRT
;
2184 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2186 opts
->ase
|= ASE_MIPS16E2_MT
;
2187 mask
|= ASE_MIPS16E2_MT
;
2193 /* Return the ASE called NAME, or null if none. */
2195 static const struct mips_ase
*
2196 mips_lookup_ase (const char *name
)
2200 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2201 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2202 return &mips_ases
[i
];
2206 /* Return the length of a microMIPS instruction in bytes. If bits of
2207 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2208 otherwise it is a 32-bit instruction. */
2210 static inline unsigned int
2211 micromips_insn_length (const struct mips_opcode
*mo
)
2213 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2216 /* Return the length of MIPS16 instruction OPCODE. */
2218 static inline unsigned int
2219 mips16_opcode_length (unsigned long opcode
)
2221 return (opcode
>> 16) == 0 ? 2 : 4;
2224 /* Return the length of instruction INSN. */
2226 static inline unsigned int
2227 insn_length (const struct mips_cl_insn
*insn
)
2229 if (mips_opts
.micromips
)
2230 return micromips_insn_length (insn
->insn_mo
);
2231 else if (mips_opts
.mips16
)
2232 return mips16_opcode_length (insn
->insn_opcode
);
2237 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2240 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2245 insn
->insn_opcode
= mo
->match
;
2248 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2249 insn
->fixp
[i
] = NULL
;
2250 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2251 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2252 insn
->mips16_absolute_jump_p
= 0;
2253 insn
->complete_p
= 0;
2254 insn
->cleared_p
= 0;
2257 /* Get a list of all the operands in INSN. */
2259 static const struct mips_operand_array
*
2260 insn_operands (const struct mips_cl_insn
*insn
)
2262 if (insn
->insn_mo
>= &mips_opcodes
[0]
2263 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2264 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2266 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2267 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2268 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2270 if (insn
->insn_mo
>= µmips_opcodes
[0]
2271 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2272 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2277 /* Get a description of operand OPNO of INSN. */
2279 static const struct mips_operand
*
2280 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2282 const struct mips_operand_array
*operands
;
2284 operands
= insn_operands (insn
);
2285 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2287 return operands
->operand
[opno
];
2290 /* Install UVAL as the value of OPERAND in INSN. */
2293 insn_insert_operand (struct mips_cl_insn
*insn
,
2294 const struct mips_operand
*operand
, unsigned int uval
)
2296 if (mips_opts
.mips16
2297 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2298 && mips_opcode_32bit_p (insn
->insn_mo
))
2299 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2301 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2304 /* Extract the value of OPERAND from INSN. */
2306 static inline unsigned
2307 insn_extract_operand (const struct mips_cl_insn
*insn
,
2308 const struct mips_operand
*operand
)
2310 return mips_extract_operand (operand
, insn
->insn_opcode
);
2313 /* Record the current MIPS16/microMIPS mode in now_seg. */
2316 mips_record_compressed_mode (void)
2318 segment_info_type
*si
;
2320 si
= seg_info (now_seg
);
2321 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2322 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2323 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2324 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2327 /* Read a standard MIPS instruction from BUF. */
2329 static unsigned long
2330 read_insn (char *buf
)
2332 if (target_big_endian
)
2333 return bfd_getb32 ((bfd_byte
*) buf
);
2335 return bfd_getl32 ((bfd_byte
*) buf
);
2338 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2342 write_insn (char *buf
, unsigned int insn
)
2344 md_number_to_chars (buf
, insn
, 4);
2348 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2349 has length LENGTH. */
2351 static unsigned long
2352 read_compressed_insn (char *buf
, unsigned int length
)
2358 for (i
= 0; i
< length
; i
+= 2)
2361 if (target_big_endian
)
2362 insn
|= bfd_getb16 ((char *) buf
);
2364 insn
|= bfd_getl16 ((char *) buf
);
2370 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2371 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2374 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2378 for (i
= 0; i
< length
; i
+= 2)
2379 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2380 return buf
+ length
;
2383 /* Install INSN at the location specified by its "frag" and "where" fields. */
2386 install_insn (const struct mips_cl_insn
*insn
)
2388 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2389 if (HAVE_CODE_COMPRESSION
)
2390 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2392 write_insn (f
, insn
->insn_opcode
);
2393 mips_record_compressed_mode ();
2396 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2397 and install the opcode in the new location. */
2400 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2405 insn
->where
= where
;
2406 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2407 if (insn
->fixp
[i
] != NULL
)
2409 insn
->fixp
[i
]->fx_frag
= frag
;
2410 insn
->fixp
[i
]->fx_where
= where
;
2412 install_insn (insn
);
2415 /* Add INSN to the end of the output. */
2418 add_fixed_insn (struct mips_cl_insn
*insn
)
2420 char *f
= frag_more (insn_length (insn
));
2421 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2424 /* Start a variant frag and move INSN to the start of the variant part,
2425 marking it as fixed. The other arguments are as for frag_var. */
2428 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2429 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2431 frag_grow (max_chars
);
2432 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2434 frag_var (rs_machine_dependent
, max_chars
, var
,
2435 subtype
, symbol
, offset
, NULL
);
2438 /* Insert N copies of INSN into the history buffer, starting at
2439 position FIRST. Neither FIRST nor N need to be clipped. */
2442 insert_into_history (unsigned int first
, unsigned int n
,
2443 const struct mips_cl_insn
*insn
)
2445 if (mips_relax
.sequence
!= 2)
2449 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2451 history
[i
] = history
[i
- n
];
2457 /* Clear the error in insn_error. */
2460 clear_insn_error (void)
2462 memset (&insn_error
, 0, sizeof (insn_error
));
2465 /* Possibly record error message MSG for the current instruction.
2466 If the error is about a particular argument, ARGNUM is the 1-based
2467 number of that argument, otherwise it is 0. FORMAT is the format
2468 of MSG. Return true if MSG was used, false if the current message
2472 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2477 /* Give priority to errors against specific arguments, and to
2478 the first whole-instruction message. */
2484 /* Keep insn_error if it is against a later argument. */
2485 if (argnum
< insn_error
.min_argnum
)
2488 /* If both errors are against the same argument but are different,
2489 give up on reporting a specific error for this argument.
2490 See the comment about mips_insn_error for details. */
2491 if (argnum
== insn_error
.min_argnum
2493 && strcmp (insn_error
.msg
, msg
) != 0)
2496 insn_error
.min_argnum
+= 1;
2500 insn_error
.min_argnum
= argnum
;
2501 insn_error
.format
= format
;
2502 insn_error
.msg
= msg
;
2506 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2507 as for set_insn_error_format. */
2510 set_insn_error (int argnum
, const char *msg
)
2512 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2515 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2516 as for set_insn_error_format. */
2519 set_insn_error_i (int argnum
, const char *msg
, int i
)
2521 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2525 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2526 are as for set_insn_error_format. */
2529 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2531 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2533 insn_error
.u
.ss
[0] = s1
;
2534 insn_error
.u
.ss
[1] = s2
;
2538 /* Report the error in insn_error, which is against assembly code STR. */
2541 report_insn_error (const char *str
)
2543 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2545 switch (insn_error
.format
)
2552 as_bad (msg
, insn_error
.u
.i
, str
);
2556 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2560 free ((char *) msg
);
2563 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2564 the idea is to make it obvious at a glance that each errata is
2568 init_vr4120_conflicts (void)
2570 #define CONFLICT(FIRST, SECOND) \
2571 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2573 /* Errata 21 - [D]DIV[U] after [D]MACC */
2574 CONFLICT (MACC
, DIV
);
2575 CONFLICT (DMACC
, DIV
);
2577 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2578 CONFLICT (DMULT
, DMULT
);
2579 CONFLICT (DMULT
, DMACC
);
2580 CONFLICT (DMACC
, DMULT
);
2581 CONFLICT (DMACC
, DMACC
);
2583 /* Errata 24 - MT{LO,HI} after [D]MACC */
2584 CONFLICT (MACC
, MTHILO
);
2585 CONFLICT (DMACC
, MTHILO
);
2587 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2588 instruction is executed immediately after a MACC or DMACC
2589 instruction, the result of [either instruction] is incorrect." */
2590 CONFLICT (MACC
, MULT
);
2591 CONFLICT (MACC
, DMULT
);
2592 CONFLICT (DMACC
, MULT
);
2593 CONFLICT (DMACC
, DMULT
);
2595 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2596 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2597 DDIV or DDIVU instruction, the result of the MACC or
2598 DMACC instruction is incorrect.". */
2599 CONFLICT (DMULT
, MACC
);
2600 CONFLICT (DMULT
, DMACC
);
2601 CONFLICT (DIV
, MACC
);
2602 CONFLICT (DIV
, DMACC
);
2612 #define RNUM_MASK 0x00000ff
2613 #define RTYPE_MASK 0x0ffff00
2614 #define RTYPE_NUM 0x0000100
2615 #define RTYPE_FPU 0x0000200
2616 #define RTYPE_FCC 0x0000400
2617 #define RTYPE_VEC 0x0000800
2618 #define RTYPE_GP 0x0001000
2619 #define RTYPE_CP0 0x0002000
2620 #define RTYPE_PC 0x0004000
2621 #define RTYPE_ACC 0x0008000
2622 #define RTYPE_CCC 0x0010000
2623 #define RTYPE_VI 0x0020000
2624 #define RTYPE_VF 0x0040000
2625 #define RTYPE_R5900_I 0x0080000
2626 #define RTYPE_R5900_Q 0x0100000
2627 #define RTYPE_R5900_R 0x0200000
2628 #define RTYPE_R5900_ACC 0x0400000
2629 #define RTYPE_MSA 0x0800000
2630 #define RWARN 0x8000000
2632 #define GENERIC_REGISTER_NUMBERS \
2633 {"$0", RTYPE_NUM | 0}, \
2634 {"$1", RTYPE_NUM | 1}, \
2635 {"$2", RTYPE_NUM | 2}, \
2636 {"$3", RTYPE_NUM | 3}, \
2637 {"$4", RTYPE_NUM | 4}, \
2638 {"$5", RTYPE_NUM | 5}, \
2639 {"$6", RTYPE_NUM | 6}, \
2640 {"$7", RTYPE_NUM | 7}, \
2641 {"$8", RTYPE_NUM | 8}, \
2642 {"$9", RTYPE_NUM | 9}, \
2643 {"$10", RTYPE_NUM | 10}, \
2644 {"$11", RTYPE_NUM | 11}, \
2645 {"$12", RTYPE_NUM | 12}, \
2646 {"$13", RTYPE_NUM | 13}, \
2647 {"$14", RTYPE_NUM | 14}, \
2648 {"$15", RTYPE_NUM | 15}, \
2649 {"$16", RTYPE_NUM | 16}, \
2650 {"$17", RTYPE_NUM | 17}, \
2651 {"$18", RTYPE_NUM | 18}, \
2652 {"$19", RTYPE_NUM | 19}, \
2653 {"$20", RTYPE_NUM | 20}, \
2654 {"$21", RTYPE_NUM | 21}, \
2655 {"$22", RTYPE_NUM | 22}, \
2656 {"$23", RTYPE_NUM | 23}, \
2657 {"$24", RTYPE_NUM | 24}, \
2658 {"$25", RTYPE_NUM | 25}, \
2659 {"$26", RTYPE_NUM | 26}, \
2660 {"$27", RTYPE_NUM | 27}, \
2661 {"$28", RTYPE_NUM | 28}, \
2662 {"$29", RTYPE_NUM | 29}, \
2663 {"$30", RTYPE_NUM | 30}, \
2664 {"$31", RTYPE_NUM | 31}
2666 #define FPU_REGISTER_NAMES \
2667 {"$f0", RTYPE_FPU | 0}, \
2668 {"$f1", RTYPE_FPU | 1}, \
2669 {"$f2", RTYPE_FPU | 2}, \
2670 {"$f3", RTYPE_FPU | 3}, \
2671 {"$f4", RTYPE_FPU | 4}, \
2672 {"$f5", RTYPE_FPU | 5}, \
2673 {"$f6", RTYPE_FPU | 6}, \
2674 {"$f7", RTYPE_FPU | 7}, \
2675 {"$f8", RTYPE_FPU | 8}, \
2676 {"$f9", RTYPE_FPU | 9}, \
2677 {"$f10", RTYPE_FPU | 10}, \
2678 {"$f11", RTYPE_FPU | 11}, \
2679 {"$f12", RTYPE_FPU | 12}, \
2680 {"$f13", RTYPE_FPU | 13}, \
2681 {"$f14", RTYPE_FPU | 14}, \
2682 {"$f15", RTYPE_FPU | 15}, \
2683 {"$f16", RTYPE_FPU | 16}, \
2684 {"$f17", RTYPE_FPU | 17}, \
2685 {"$f18", RTYPE_FPU | 18}, \
2686 {"$f19", RTYPE_FPU | 19}, \
2687 {"$f20", RTYPE_FPU | 20}, \
2688 {"$f21", RTYPE_FPU | 21}, \
2689 {"$f22", RTYPE_FPU | 22}, \
2690 {"$f23", RTYPE_FPU | 23}, \
2691 {"$f24", RTYPE_FPU | 24}, \
2692 {"$f25", RTYPE_FPU | 25}, \
2693 {"$f26", RTYPE_FPU | 26}, \
2694 {"$f27", RTYPE_FPU | 27}, \
2695 {"$f28", RTYPE_FPU | 28}, \
2696 {"$f29", RTYPE_FPU | 29}, \
2697 {"$f30", RTYPE_FPU | 30}, \
2698 {"$f31", RTYPE_FPU | 31}
2700 #define FPU_CONDITION_CODE_NAMES \
2701 {"$fcc0", RTYPE_FCC | 0}, \
2702 {"$fcc1", RTYPE_FCC | 1}, \
2703 {"$fcc2", RTYPE_FCC | 2}, \
2704 {"$fcc3", RTYPE_FCC | 3}, \
2705 {"$fcc4", RTYPE_FCC | 4}, \
2706 {"$fcc5", RTYPE_FCC | 5}, \
2707 {"$fcc6", RTYPE_FCC | 6}, \
2708 {"$fcc7", RTYPE_FCC | 7}
2710 #define COPROC_CONDITION_CODE_NAMES \
2711 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2712 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2713 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2714 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2715 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2716 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2717 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2718 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2720 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2721 {"$a4", RTYPE_GP | 8}, \
2722 {"$a5", RTYPE_GP | 9}, \
2723 {"$a6", RTYPE_GP | 10}, \
2724 {"$a7", RTYPE_GP | 11}, \
2725 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2726 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2727 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2728 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2729 {"$t0", RTYPE_GP | 12}, \
2730 {"$t1", RTYPE_GP | 13}, \
2731 {"$t2", RTYPE_GP | 14}, \
2732 {"$t3", RTYPE_GP | 15}
2734 #define O32_SYMBOLIC_REGISTER_NAMES \
2735 {"$t0", RTYPE_GP | 8}, \
2736 {"$t1", RTYPE_GP | 9}, \
2737 {"$t2", RTYPE_GP | 10}, \
2738 {"$t3", RTYPE_GP | 11}, \
2739 {"$t4", RTYPE_GP | 12}, \
2740 {"$t5", RTYPE_GP | 13}, \
2741 {"$t6", RTYPE_GP | 14}, \
2742 {"$t7", RTYPE_GP | 15}, \
2743 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2744 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2745 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2746 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2748 /* Remaining symbolic register names */
2749 #define SYMBOLIC_REGISTER_NAMES \
2750 {"$zero", RTYPE_GP | 0}, \
2751 {"$at", RTYPE_GP | 1}, \
2752 {"$AT", RTYPE_GP | 1}, \
2753 {"$v0", RTYPE_GP | 2}, \
2754 {"$v1", RTYPE_GP | 3}, \
2755 {"$a0", RTYPE_GP | 4}, \
2756 {"$a1", RTYPE_GP | 5}, \
2757 {"$a2", RTYPE_GP | 6}, \
2758 {"$a3", RTYPE_GP | 7}, \
2759 {"$s0", RTYPE_GP | 16}, \
2760 {"$s1", RTYPE_GP | 17}, \
2761 {"$s2", RTYPE_GP | 18}, \
2762 {"$s3", RTYPE_GP | 19}, \
2763 {"$s4", RTYPE_GP | 20}, \
2764 {"$s5", RTYPE_GP | 21}, \
2765 {"$s6", RTYPE_GP | 22}, \
2766 {"$s7", RTYPE_GP | 23}, \
2767 {"$t8", RTYPE_GP | 24}, \
2768 {"$t9", RTYPE_GP | 25}, \
2769 {"$k0", RTYPE_GP | 26}, \
2770 {"$kt0", RTYPE_GP | 26}, \
2771 {"$k1", RTYPE_GP | 27}, \
2772 {"$kt1", RTYPE_GP | 27}, \
2773 {"$gp", RTYPE_GP | 28}, \
2774 {"$sp", RTYPE_GP | 29}, \
2775 {"$s8", RTYPE_GP | 30}, \
2776 {"$fp", RTYPE_GP | 30}, \
2777 {"$ra", RTYPE_GP | 31}
2779 #define MIPS16_SPECIAL_REGISTER_NAMES \
2780 {"$pc", RTYPE_PC | 0}
2782 #define MDMX_VECTOR_REGISTER_NAMES \
2783 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2784 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2785 {"$v2", RTYPE_VEC | 2}, \
2786 {"$v3", RTYPE_VEC | 3}, \
2787 {"$v4", RTYPE_VEC | 4}, \
2788 {"$v5", RTYPE_VEC | 5}, \
2789 {"$v6", RTYPE_VEC | 6}, \
2790 {"$v7", RTYPE_VEC | 7}, \
2791 {"$v8", RTYPE_VEC | 8}, \
2792 {"$v9", RTYPE_VEC | 9}, \
2793 {"$v10", RTYPE_VEC | 10}, \
2794 {"$v11", RTYPE_VEC | 11}, \
2795 {"$v12", RTYPE_VEC | 12}, \
2796 {"$v13", RTYPE_VEC | 13}, \
2797 {"$v14", RTYPE_VEC | 14}, \
2798 {"$v15", RTYPE_VEC | 15}, \
2799 {"$v16", RTYPE_VEC | 16}, \
2800 {"$v17", RTYPE_VEC | 17}, \
2801 {"$v18", RTYPE_VEC | 18}, \
2802 {"$v19", RTYPE_VEC | 19}, \
2803 {"$v20", RTYPE_VEC | 20}, \
2804 {"$v21", RTYPE_VEC | 21}, \
2805 {"$v22", RTYPE_VEC | 22}, \
2806 {"$v23", RTYPE_VEC | 23}, \
2807 {"$v24", RTYPE_VEC | 24}, \
2808 {"$v25", RTYPE_VEC | 25}, \
2809 {"$v26", RTYPE_VEC | 26}, \
2810 {"$v27", RTYPE_VEC | 27}, \
2811 {"$v28", RTYPE_VEC | 28}, \
2812 {"$v29", RTYPE_VEC | 29}, \
2813 {"$v30", RTYPE_VEC | 30}, \
2814 {"$v31", RTYPE_VEC | 31}
2816 #define R5900_I_NAMES \
2817 {"$I", RTYPE_R5900_I | 0}
2819 #define R5900_Q_NAMES \
2820 {"$Q", RTYPE_R5900_Q | 0}
2822 #define R5900_R_NAMES \
2823 {"$R", RTYPE_R5900_R | 0}
2825 #define R5900_ACC_NAMES \
2826 {"$ACC", RTYPE_R5900_ACC | 0 }
2828 #define MIPS_DSP_ACCUMULATOR_NAMES \
2829 {"$ac0", RTYPE_ACC | 0}, \
2830 {"$ac1", RTYPE_ACC | 1}, \
2831 {"$ac2", RTYPE_ACC | 2}, \
2832 {"$ac3", RTYPE_ACC | 3}
2834 static const struct regname reg_names
[] = {
2835 GENERIC_REGISTER_NUMBERS
,
2837 FPU_CONDITION_CODE_NAMES
,
2838 COPROC_CONDITION_CODE_NAMES
,
2840 /* The $txx registers depends on the abi,
2841 these will be added later into the symbol table from
2842 one of the tables below once mips_abi is set after
2843 parsing of arguments from the command line. */
2844 SYMBOLIC_REGISTER_NAMES
,
2846 MIPS16_SPECIAL_REGISTER_NAMES
,
2847 MDMX_VECTOR_REGISTER_NAMES
,
2852 MIPS_DSP_ACCUMULATOR_NAMES
,
2856 static const struct regname reg_names_o32
[] = {
2857 O32_SYMBOLIC_REGISTER_NAMES
,
2861 static const struct regname reg_names_n32n64
[] = {
2862 N32N64_SYMBOLIC_REGISTER_NAMES
,
2866 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2867 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2868 of these register symbols, return the associated vector register,
2869 otherwise return SYMVAL itself. */
2872 mips_prefer_vec_regno (unsigned int symval
)
2874 if ((symval
& -2) == (RTYPE_GP
| 2))
2875 return RTYPE_VEC
| (symval
& 1);
2879 /* Return true if string [S, E) is a valid register name, storing its
2880 symbol value in *SYMVAL_PTR if so. */
2883 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2888 /* Terminate name. */
2892 /* Look up the name. */
2893 symbol
= symbol_find (s
);
2896 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2899 *symval_ptr
= S_GET_VALUE (symbol
);
2903 /* Return true if the string at *SPTR is a valid register name. Allow it
2904 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2907 When returning true, move *SPTR past the register, store the
2908 register's symbol value in *SYMVAL_PTR and the channel mask in
2909 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2910 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2911 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2914 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2915 unsigned int *channels_ptr
)
2919 unsigned int channels
, symval
, bit
;
2921 /* Find end of name. */
2923 if (is_name_beginner (*e
))
2925 while (is_part_of_name (*e
))
2929 if (!mips_parse_register_1 (s
, e
, &symval
))
2934 /* Eat characters from the end of the string that are valid
2935 channel suffixes. The preceding register must be $ACC or
2936 end with a digit, so there is no ambiguity. */
2939 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2940 if (m
> s
&& m
[-1] == *q
)
2947 || !mips_parse_register_1 (s
, m
, &symval
)
2948 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2953 *symval_ptr
= symval
;
2955 *channels_ptr
= channels
;
2959 /* Check if SPTR points at a valid register specifier according to TYPES.
2960 If so, then return 1, advance S to consume the specifier and store
2961 the register's number in REGNOP, otherwise return 0. */
2964 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2968 if (mips_parse_register (s
, ®no
, NULL
))
2970 if (types
& RTYPE_VEC
)
2971 regno
= mips_prefer_vec_regno (regno
);
2980 as_warn (_("unrecognized register name `%s'"), *s
);
2985 return regno
<= RNUM_MASK
;
2988 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2989 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2992 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2997 for (i
= 0; i
< 4; i
++)
2998 if (*s
== "xyzw"[i
])
3000 *channels
|= 1 << (3 - i
);
3006 /* Token types for parsed operand lists. */
3007 enum mips_operand_token_type
{
3008 /* A plain register, e.g. $f2. */
3011 /* A 4-bit XYZW channel mask. */
3014 /* A constant vector index, e.g. [1]. */
3017 /* A register vector index, e.g. [$2]. */
3020 /* A continuous range of registers, e.g. $s0-$s4. */
3023 /* A (possibly relocated) expression. */
3026 /* A floating-point value. */
3029 /* A single character. This can be '(', ')' or ',', but '(' only appears
3033 /* A doubled character, either "--" or "++". */
3036 /* The end of the operand list. */
3040 /* A parsed operand token. */
3041 struct mips_operand_token
3043 /* The type of token. */
3044 enum mips_operand_token_type type
;
3047 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3050 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3051 unsigned int channels
;
3053 /* The integer value of an OT_INTEGER_INDEX. */
3056 /* The two register symbol values involved in an OT_REG_RANGE. */
3058 unsigned int regno1
;
3059 unsigned int regno2
;
3062 /* The value of an OT_INTEGER. The value is represented as an
3063 expression and the relocation operators that were applied to
3064 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3065 relocation operators were used. */
3068 bfd_reloc_code_real_type relocs
[3];
3071 /* The binary data for an OT_FLOAT constant, and the number of bytes
3074 unsigned char data
[8];
3078 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3083 /* An obstack used to construct lists of mips_operand_tokens. */
3084 static struct obstack mips_operand_tokens
;
3086 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3089 mips_add_token (struct mips_operand_token
*token
,
3090 enum mips_operand_token_type type
)
3093 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3096 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3097 and OT_REG tokens for them if so, and return a pointer to the first
3098 unconsumed character. Return null otherwise. */
3101 mips_parse_base_start (char *s
)
3103 struct mips_operand_token token
;
3104 unsigned int regno
, channels
;
3105 bfd_boolean decrement_p
;
3111 SKIP_SPACE_TABS (s
);
3113 /* Only match "--" as part of a base expression. In other contexts "--X"
3114 is a double negative. */
3115 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3119 SKIP_SPACE_TABS (s
);
3122 /* Allow a channel specifier because that leads to better error messages
3123 than treating something like "$vf0x++" as an expression. */
3124 if (!mips_parse_register (&s
, ®no
, &channels
))
3128 mips_add_token (&token
, OT_CHAR
);
3133 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3136 token
.u
.regno
= regno
;
3137 mips_add_token (&token
, OT_REG
);
3141 token
.u
.channels
= channels
;
3142 mips_add_token (&token
, OT_CHANNELS
);
3145 /* For consistency, only match "++" as part of base expressions too. */
3146 SKIP_SPACE_TABS (s
);
3147 if (s
[0] == '+' && s
[1] == '+')
3151 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3157 /* Parse one or more tokens from S. Return a pointer to the first
3158 unconsumed character on success. Return null if an error was found
3159 and store the error text in insn_error. FLOAT_FORMAT is as for
3160 mips_parse_arguments. */
3163 mips_parse_argument_token (char *s
, char float_format
)
3165 char *end
, *save_in
;
3167 unsigned int regno1
, regno2
, channels
;
3168 struct mips_operand_token token
;
3170 /* First look for "($reg", since we want to treat that as an
3171 OT_CHAR and OT_REG rather than an expression. */
3172 end
= mips_parse_base_start (s
);
3176 /* Handle other characters that end up as OT_CHARs. */
3177 if (*s
== ')' || *s
== ',')
3180 mips_add_token (&token
, OT_CHAR
);
3185 /* Handle tokens that start with a register. */
3186 if (mips_parse_register (&s
, ®no1
, &channels
))
3190 /* A register and a VU0 channel suffix. */
3191 token
.u
.regno
= regno1
;
3192 mips_add_token (&token
, OT_REG
);
3194 token
.u
.channels
= channels
;
3195 mips_add_token (&token
, OT_CHANNELS
);
3199 SKIP_SPACE_TABS (s
);
3202 /* A register range. */
3204 SKIP_SPACE_TABS (s
);
3205 if (!mips_parse_register (&s
, ®no2
, NULL
))
3207 set_insn_error (0, _("invalid register range"));
3211 token
.u
.reg_range
.regno1
= regno1
;
3212 token
.u
.reg_range
.regno2
= regno2
;
3213 mips_add_token (&token
, OT_REG_RANGE
);
3217 /* Add the register itself. */
3218 token
.u
.regno
= regno1
;
3219 mips_add_token (&token
, OT_REG
);
3221 /* Check for a vector index. */
3225 SKIP_SPACE_TABS (s
);
3226 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3227 mips_add_token (&token
, OT_REG_INDEX
);
3230 expressionS element
;
3232 my_getExpression (&element
, s
);
3233 if (element
.X_op
!= O_constant
)
3235 set_insn_error (0, _("vector element must be constant"));
3239 token
.u
.index
= element
.X_add_number
;
3240 mips_add_token (&token
, OT_INTEGER_INDEX
);
3242 SKIP_SPACE_TABS (s
);
3245 set_insn_error (0, _("missing `]'"));
3255 /* First try to treat expressions as floats. */
3256 save_in
= input_line_pointer
;
3257 input_line_pointer
= s
;
3258 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3259 &token
.u
.flt
.length
);
3260 end
= input_line_pointer
;
3261 input_line_pointer
= save_in
;
3264 set_insn_error (0, err
);
3269 mips_add_token (&token
, OT_FLOAT
);
3274 /* Treat everything else as an integer expression. */
3275 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3276 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3277 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3278 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3280 mips_add_token (&token
, OT_INTEGER
);
3284 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3285 if expressions should be treated as 32-bit floating-point constants,
3286 'd' if they should be treated as 64-bit floating-point constants,
3287 or 0 if they should be treated as integer expressions (the usual case).
3289 Return a list of tokens on success, otherwise return 0. The caller
3290 must obstack_free the list after use. */
3292 static struct mips_operand_token
*
3293 mips_parse_arguments (char *s
, char float_format
)
3295 struct mips_operand_token token
;
3297 SKIP_SPACE_TABS (s
);
3300 s
= mips_parse_argument_token (s
, float_format
);
3303 obstack_free (&mips_operand_tokens
,
3304 obstack_finish (&mips_operand_tokens
));
3307 SKIP_SPACE_TABS (s
);
3309 mips_add_token (&token
, OT_END
);
3310 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3313 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3314 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3317 is_opcode_valid (const struct mips_opcode
*mo
)
3319 int isa
= mips_opts
.isa
;
3320 int ase
= mips_opts
.ase
;
3324 if (ISA_HAS_64BIT_REGS (isa
))
3325 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3326 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3327 ase
|= mips_ases
[i
].flags64
;
3329 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3332 /* Check whether the instruction or macro requires single-precision or
3333 double-precision floating-point support. Note that this information is
3334 stored differently in the opcode table for insns and macros. */
3335 if (mo
->pinfo
== INSN_MACRO
)
3337 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3338 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3342 fp_s
= mo
->pinfo
& FP_S
;
3343 fp_d
= mo
->pinfo
& FP_D
;
3346 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3349 if (fp_s
&& mips_opts
.soft_float
)
3355 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3356 selected ISA and architecture. */
3359 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3361 int isa
= mips_opts
.isa
;
3362 int ase
= mips_opts
.ase
;
3365 if (ISA_HAS_64BIT_REGS (isa
))
3366 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3367 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3368 ase
|= mips_ases
[i
].flags64
;
3370 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3373 /* Return TRUE if the size of the microMIPS opcode MO matches one
3374 explicitly requested. Always TRUE in the standard MIPS mode.
3375 Use is_size_valid_16 for MIPS16 opcodes. */
3378 is_size_valid (const struct mips_opcode
*mo
)
3380 if (!mips_opts
.micromips
)
3383 if (mips_opts
.insn32
)
3385 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3387 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3390 if (!forced_insn_length
)
3392 if (mo
->pinfo
== INSN_MACRO
)
3394 return forced_insn_length
== micromips_insn_length (mo
);
3397 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3398 explicitly requested. */
3401 is_size_valid_16 (const struct mips_opcode
*mo
)
3403 if (!forced_insn_length
)
3405 if (mo
->pinfo
== INSN_MACRO
)
3407 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3409 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3414 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3415 of the preceding instruction. Always TRUE in the standard MIPS mode.
3417 We don't accept macros in 16-bit delay slots to avoid a case where
3418 a macro expansion fails because it relies on a preceding 32-bit real
3419 instruction to have matched and does not handle the operands correctly.
3420 The only macros that may expand to 16-bit instructions are JAL that
3421 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3422 and BGT (that likewise cannot be placed in a delay slot) that decay to
3423 a NOP. In all these cases the macros precede any corresponding real
3424 instruction definitions in the opcode table, so they will match in the
3425 second pass where the size of the delay slot is ignored and therefore
3426 produce correct code. */
3429 is_delay_slot_valid (const struct mips_opcode
*mo
)
3431 if (!mips_opts
.micromips
)
3434 if (mo
->pinfo
== INSN_MACRO
)
3435 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3436 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3437 && micromips_insn_length (mo
) != 4)
3439 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3440 && micromips_insn_length (mo
) != 2)
3446 /* For consistency checking, verify that all bits of OPCODE are specified
3447 either by the match/mask part of the instruction definition, or by the
3448 operand list. Also build up a list of operands in OPERANDS.
3450 INSN_BITS says which bits of the instruction are significant.
3451 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3452 provides the mips_operand description of each operand. DECODE_OPERAND
3453 is null for MIPS16 instructions. */
3456 validate_mips_insn (const struct mips_opcode
*opcode
,
3457 unsigned long insn_bits
,
3458 const struct mips_operand
*(*decode_operand
) (const char *),
3459 struct mips_operand_array
*operands
)
3462 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3463 const struct mips_operand
*operand
;
3465 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3466 if ((mask
& opcode
->match
) != opcode
->match
)
3468 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3469 opcode
->name
, opcode
->args
);
3474 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3475 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3476 for (s
= opcode
->args
; *s
; ++s
)
3489 if (!decode_operand
)
3490 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3492 operand
= decode_operand (s
);
3493 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3495 as_bad (_("internal: unknown operand type: %s %s"),
3496 opcode
->name
, opcode
->args
);
3499 gas_assert (opno
< MAX_OPERANDS
);
3500 operands
->operand
[opno
] = operand
;
3501 if (!decode_operand
&& operand
3502 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3503 && mips_opcode_32bit_p (opcode
))
3504 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3505 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3507 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3508 if (operand
->type
== OP_MDMX_IMM_REG
)
3509 /* Bit 5 is the format selector (OB vs QH). The opcode table
3510 has separate entries for each format. */
3511 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3512 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3513 used_bits
&= ~(mask
& 0x700);
3514 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3515 operand field that cannot be fully described with LSB/SIZE. */
3516 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3517 used_bits
&= ~0x6000;
3519 /* Skip prefix characters. */
3520 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3525 doubled
= used_bits
& mask
& insn_bits
;
3528 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3529 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3533 undefined
= ~used_bits
& insn_bits
;
3534 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3536 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3537 undefined
, opcode
->name
, opcode
->args
);
3540 used_bits
&= ~insn_bits
;
3543 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3544 used_bits
, opcode
->name
, opcode
->args
);
3550 /* The MIPS16 version of validate_mips_insn. */
3553 validate_mips16_insn (const struct mips_opcode
*opcode
,
3554 struct mips_operand_array
*operands
)
3556 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3558 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3561 /* The microMIPS version of validate_mips_insn. */
3564 validate_micromips_insn (const struct mips_opcode
*opc
,
3565 struct mips_operand_array
*operands
)
3567 unsigned long insn_bits
;
3568 unsigned long major
;
3569 unsigned int length
;
3571 if (opc
->pinfo
== INSN_MACRO
)
3572 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3575 length
= micromips_insn_length (opc
);
3576 if (length
!= 2 && length
!= 4)
3578 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3579 "%s %s"), length
, opc
->name
, opc
->args
);
3582 major
= opc
->match
>> (10 + 8 * (length
- 2));
3583 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3584 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3586 as_bad (_("internal error: bad microMIPS opcode "
3587 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3591 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3592 insn_bits
= 1 << 4 * length
;
3593 insn_bits
<<= 4 * length
;
3595 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3599 /* This function is called once, at assembler startup time. It should set up
3600 all the tables, etc. that the MD part of the assembler will need. */
3605 const char *retval
= NULL
;
3609 if (mips_pic
!= NO_PIC
)
3611 if (g_switch_seen
&& g_switch_value
!= 0)
3612 as_bad (_("-G may not be used in position-independent code"));
3615 else if (mips_abicalls
)
3617 if (g_switch_seen
&& g_switch_value
!= 0)
3618 as_bad (_("-G may not be used with abicalls"));
3622 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3623 as_warn (_("could not set architecture and machine"));
3625 op_hash
= hash_new ();
3627 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3628 for (i
= 0; i
< NUMOPCODES
;)
3630 const char *name
= mips_opcodes
[i
].name
;
3632 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3635 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3636 mips_opcodes
[i
].name
, retval
);
3637 /* Probably a memory allocation problem? Give up now. */
3638 as_fatal (_("broken assembler, no assembly attempted"));
3642 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3643 decode_mips_operand
, &mips_operands
[i
]))
3645 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3647 create_insn (&nop_insn
, mips_opcodes
+ i
);
3648 if (mips_fix_loongson2f_nop
)
3649 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3650 nop_insn
.fixed_p
= 1;
3654 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3657 mips16_op_hash
= hash_new ();
3658 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3659 bfd_mips16_num_opcodes
);
3662 while (i
< bfd_mips16_num_opcodes
)
3664 const char *name
= mips16_opcodes
[i
].name
;
3666 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3668 as_fatal (_("internal: can't hash `%s': %s"),
3669 mips16_opcodes
[i
].name
, retval
);
3672 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3674 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3676 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3677 mips16_nop_insn
.fixed_p
= 1;
3681 while (i
< bfd_mips16_num_opcodes
3682 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3685 micromips_op_hash
= hash_new ();
3686 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3687 bfd_micromips_num_opcodes
);
3690 while (i
< bfd_micromips_num_opcodes
)
3692 const char *name
= micromips_opcodes
[i
].name
;
3694 retval
= hash_insert (micromips_op_hash
, name
,
3695 (void *) µmips_opcodes
[i
]);
3697 as_fatal (_("internal: can't hash `%s': %s"),
3698 micromips_opcodes
[i
].name
, retval
);
3701 struct mips_cl_insn
*micromips_nop_insn
;
3703 if (!validate_micromips_insn (µmips_opcodes
[i
],
3704 µmips_operands
[i
]))
3707 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3709 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3710 micromips_nop_insn
= µmips_nop16_insn
;
3711 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3712 micromips_nop_insn
= µmips_nop32_insn
;
3716 if (micromips_nop_insn
->insn_mo
== NULL
3717 && strcmp (name
, "nop") == 0)
3719 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3720 micromips_nop_insn
->fixed_p
= 1;
3724 while (++i
< bfd_micromips_num_opcodes
3725 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3729 as_fatal (_("broken assembler, no assembly attempted"));
3731 /* We add all the general register names to the symbol table. This
3732 helps us detect invalid uses of them. */
3733 for (i
= 0; reg_names
[i
].name
; i
++)
3734 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3735 reg_names
[i
].num
, /* & RNUM_MASK, */
3736 &zero_address_frag
));
3738 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3739 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3740 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3741 &zero_address_frag
));
3743 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3744 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3745 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3746 &zero_address_frag
));
3748 for (i
= 0; i
< 32; i
++)
3752 /* R5900 VU0 floating-point register. */
3753 sprintf (regname
, "$vf%d", i
);
3754 symbol_table_insert (symbol_new (regname
, reg_section
,
3755 RTYPE_VF
| i
, &zero_address_frag
));
3757 /* R5900 VU0 integer register. */
3758 sprintf (regname
, "$vi%d", i
);
3759 symbol_table_insert (symbol_new (regname
, reg_section
,
3760 RTYPE_VI
| i
, &zero_address_frag
));
3763 sprintf (regname
, "$w%d", i
);
3764 symbol_table_insert (symbol_new (regname
, reg_section
,
3765 RTYPE_MSA
| i
, &zero_address_frag
));
3768 obstack_init (&mips_operand_tokens
);
3770 mips_no_prev_insn ();
3773 mips_cprmask
[0] = 0;
3774 mips_cprmask
[1] = 0;
3775 mips_cprmask
[2] = 0;
3776 mips_cprmask
[3] = 0;
3778 /* set the default alignment for the text section (2**2) */
3779 record_alignment (text_section
, 2);
3781 bfd_set_gp_size (stdoutput
, g_switch_value
);
3783 /* On a native system other than VxWorks, sections must be aligned
3784 to 16 byte boundaries. When configured for an embedded ELF
3785 target, we don't bother. */
3786 if (strncmp (TARGET_OS
, "elf", 3) != 0
3787 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3789 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3790 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3791 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3794 /* Create a .reginfo section for register masks and a .mdebug
3795 section for debugging information. */
3803 subseg
= now_subseg
;
3805 /* The ABI says this section should be loaded so that the
3806 running program can access it. However, we don't load it
3807 if we are configured for an embedded target */
3808 flags
= SEC_READONLY
| SEC_DATA
;
3809 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3810 flags
|= SEC_ALLOC
| SEC_LOAD
;
3812 if (mips_abi
!= N64_ABI
)
3814 sec
= subseg_new (".reginfo", (subsegT
) 0);
3816 bfd_set_section_flags (stdoutput
, sec
, flags
);
3817 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3819 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3823 /* The 64-bit ABI uses a .MIPS.options section rather than
3824 .reginfo section. */
3825 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3826 bfd_set_section_flags (stdoutput
, sec
, flags
);
3827 bfd_set_section_alignment (stdoutput
, sec
, 3);
3829 /* Set up the option header. */
3831 Elf_Internal_Options opthdr
;
3834 opthdr
.kind
= ODK_REGINFO
;
3835 opthdr
.size
= (sizeof (Elf_External_Options
)
3836 + sizeof (Elf64_External_RegInfo
));
3839 f
= frag_more (sizeof (Elf_External_Options
));
3840 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3841 (Elf_External_Options
*) f
);
3843 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3847 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3848 bfd_set_section_flags (stdoutput
, sec
,
3849 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3850 bfd_set_section_alignment (stdoutput
, sec
, 3);
3851 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3853 if (ECOFF_DEBUGGING
)
3855 sec
= subseg_new (".mdebug", (subsegT
) 0);
3856 (void) bfd_set_section_flags (stdoutput
, sec
,
3857 SEC_HAS_CONTENTS
| SEC_READONLY
);
3858 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3860 else if (mips_flag_pdr
)
3862 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3863 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3864 SEC_READONLY
| SEC_RELOC
3866 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3869 subseg_set (seg
, subseg
);
3872 if (mips_fix_vr4120
)
3873 init_vr4120_conflicts ();
3877 fpabi_incompatible_with (int fpabi
, const char *what
)
3879 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3880 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3884 fpabi_requires (int fpabi
, const char *what
)
3886 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3887 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3890 /* Check -mabi and register sizes against the specified FP ABI. */
3892 check_fpabi (int fpabi
)
3896 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3897 if (file_mips_opts
.soft_float
)
3898 fpabi_incompatible_with (fpabi
, "softfloat");
3899 else if (file_mips_opts
.single_float
)
3900 fpabi_incompatible_with (fpabi
, "singlefloat");
3901 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3902 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3903 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3904 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3907 case Val_GNU_MIPS_ABI_FP_XX
:
3908 if (mips_abi
!= O32_ABI
)
3909 fpabi_requires (fpabi
, "-mabi=32");
3910 else if (file_mips_opts
.soft_float
)
3911 fpabi_incompatible_with (fpabi
, "softfloat");
3912 else if (file_mips_opts
.single_float
)
3913 fpabi_incompatible_with (fpabi
, "singlefloat");
3914 else if (file_mips_opts
.fp
!= 0)
3915 fpabi_requires (fpabi
, "fp=xx");
3918 case Val_GNU_MIPS_ABI_FP_64A
:
3919 case Val_GNU_MIPS_ABI_FP_64
:
3920 if (mips_abi
!= O32_ABI
)
3921 fpabi_requires (fpabi
, "-mabi=32");
3922 else if (file_mips_opts
.soft_float
)
3923 fpabi_incompatible_with (fpabi
, "softfloat");
3924 else if (file_mips_opts
.single_float
)
3925 fpabi_incompatible_with (fpabi
, "singlefloat");
3926 else if (file_mips_opts
.fp
!= 64)
3927 fpabi_requires (fpabi
, "fp=64");
3928 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3929 fpabi_incompatible_with (fpabi
, "nooddspreg");
3930 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3931 fpabi_requires (fpabi
, "nooddspreg");
3934 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3935 if (file_mips_opts
.soft_float
)
3936 fpabi_incompatible_with (fpabi
, "softfloat");
3937 else if (!file_mips_opts
.single_float
)
3938 fpabi_requires (fpabi
, "singlefloat");
3941 case Val_GNU_MIPS_ABI_FP_SOFT
:
3942 if (!file_mips_opts
.soft_float
)
3943 fpabi_requires (fpabi
, "softfloat");
3946 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3947 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3948 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3951 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3952 /* Silently ignore compatibility value. */
3956 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3957 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3962 /* Perform consistency checks on the current options. */
3965 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3967 /* Check the size of integer registers agrees with the ABI and ISA. */
3968 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3969 as_bad (_("`gp=64' used with a 32-bit processor"));
3971 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3972 as_bad (_("`gp=32' used with a 64-bit ABI"));
3974 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3975 as_bad (_("`gp=64' used with a 32-bit ABI"));
3977 /* Check the size of the float registers agrees with the ABI and ISA. */
3981 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3982 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3983 else if (opts
->single_float
== 1)
3984 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3987 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3988 as_bad (_("`fp=64' used with a 32-bit fpu"));
3990 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3991 && !ISA_HAS_MXHC1 (opts
->isa
))
3992 as_warn (_("`fp=64' used with a 32-bit ABI"));
3996 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3997 as_warn (_("`fp=32' used with a 64-bit ABI"));
3998 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3999 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4002 as_bad (_("Unknown size of floating point registers"));
4006 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4007 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4009 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4010 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4011 else if (ISA_IS_R6 (opts
->isa
)
4012 && (opts
->micromips
== 1
4013 || opts
->mips16
== 1))
4014 as_fatal (_("`%s' cannot be used with `%s'"),
4015 opts
->micromips
? "micromips" : "mips16",
4016 mips_cpu_info_from_isa (opts
->isa
)->name
);
4018 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4019 as_fatal (_("branch relaxation is not supported in `%s'"),
4020 mips_cpu_info_from_isa (opts
->isa
)->name
);
4023 /* Perform consistency checks on the module level options exactly once.
4024 This is a deferred check that happens:
4025 at the first .set directive
4026 or, at the first pseudo op that generates code (inc .dc.a)
4027 or, at the first instruction
4031 file_mips_check_options (void)
4033 const struct mips_cpu_info
*arch_info
= 0;
4035 if (file_mips_opts_checked
)
4038 /* The following code determines the register size.
4039 Similar code was added to GCC 3.3 (see override_options() in
4040 config/mips/mips.c). The GAS and GCC code should be kept in sync
4041 as much as possible. */
4043 if (file_mips_opts
.gp
< 0)
4045 /* Infer the integer register size from the ABI and processor.
4046 Restrict ourselves to 32-bit registers if that's all the
4047 processor has, or if the ABI cannot handle 64-bit registers. */
4048 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4049 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4053 if (file_mips_opts
.fp
< 0)
4055 /* No user specified float register size.
4056 ??? GAS treats single-float processors as though they had 64-bit
4057 float registers (although it complains when double-precision
4058 instructions are used). As things stand, saying they have 32-bit
4059 registers would lead to spurious "register must be even" messages.
4060 So here we assume float registers are never smaller than the
4062 if (file_mips_opts
.gp
== 64)
4063 /* 64-bit integer registers implies 64-bit float registers. */
4064 file_mips_opts
.fp
= 64;
4065 else if ((file_mips_opts
.ase
& FP64_ASES
)
4066 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4067 /* Handle ASEs that require 64-bit float registers, if possible. */
4068 file_mips_opts
.fp
= 64;
4069 else if (ISA_IS_R6 (mips_opts
.isa
))
4070 /* R6 implies 64-bit float registers. */
4071 file_mips_opts
.fp
= 64;
4073 /* 32-bit float registers. */
4074 file_mips_opts
.fp
= 32;
4077 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4079 /* Disable operations on odd-numbered floating-point registers by default
4080 when using the FPXX ABI. */
4081 if (file_mips_opts
.oddspreg
< 0)
4083 if (file_mips_opts
.fp
== 0)
4084 file_mips_opts
.oddspreg
= 0;
4086 file_mips_opts
.oddspreg
= 1;
4089 /* End of GCC-shared inference code. */
4091 /* This flag is set when we have a 64-bit capable CPU but use only
4092 32-bit wide registers. Note that EABI does not use it. */
4093 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4094 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4095 || mips_abi
== O32_ABI
))
4098 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4099 as_bad (_("trap exception not supported at ISA 1"));
4101 /* If the selected architecture includes support for ASEs, enable
4102 generation of code for them. */
4103 if (file_mips_opts
.mips16
== -1)
4104 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4105 if (file_mips_opts
.micromips
== -1)
4106 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4109 if (mips_nan2008
== -1)
4110 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4111 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4112 as_fatal (_("`%s' does not support legacy NaN"),
4113 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4115 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4116 being selected implicitly. */
4117 if (file_mips_opts
.fp
!= 64)
4118 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4120 /* If the user didn't explicitly select or deselect a particular ASE,
4121 use the default setting for the CPU. */
4122 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4124 /* Set up the current options. These may change throughout assembly. */
4125 mips_opts
= file_mips_opts
;
4127 mips_check_isa_supports_ases ();
4128 mips_check_options (&file_mips_opts
, TRUE
);
4129 file_mips_opts_checked
= TRUE
;
4131 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4132 as_warn (_("could not set architecture and machine"));
4136 md_assemble (char *str
)
4138 struct mips_cl_insn insn
;
4139 bfd_reloc_code_real_type unused_reloc
[3]
4140 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4142 file_mips_check_options ();
4144 imm_expr
.X_op
= O_absent
;
4145 offset_expr
.X_op
= O_absent
;
4146 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4147 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4148 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4150 mips_mark_labels ();
4151 mips_assembling_insn
= TRUE
;
4152 clear_insn_error ();
4154 if (mips_opts
.mips16
)
4155 mips16_ip (str
, &insn
);
4158 mips_ip (str
, &insn
);
4159 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4160 str
, insn
.insn_opcode
));
4164 report_insn_error (str
);
4165 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4168 if (mips_opts
.mips16
)
4169 mips16_macro (&insn
);
4176 if (offset_expr
.X_op
!= O_absent
)
4177 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4179 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4182 mips_assembling_insn
= FALSE
;
4185 /* Convenience functions for abstracting away the differences between
4186 MIPS16 and non-MIPS16 relocations. */
4188 static inline bfd_boolean
4189 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4193 case BFD_RELOC_MIPS16_JMP
:
4194 case BFD_RELOC_MIPS16_GPREL
:
4195 case BFD_RELOC_MIPS16_GOT16
:
4196 case BFD_RELOC_MIPS16_CALL16
:
4197 case BFD_RELOC_MIPS16_HI16_S
:
4198 case BFD_RELOC_MIPS16_HI16
:
4199 case BFD_RELOC_MIPS16_LO16
:
4200 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4208 static inline bfd_boolean
4209 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4213 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4214 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4215 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4216 case BFD_RELOC_MICROMIPS_GPREL16
:
4217 case BFD_RELOC_MICROMIPS_JMP
:
4218 case BFD_RELOC_MICROMIPS_HI16
:
4219 case BFD_RELOC_MICROMIPS_HI16_S
:
4220 case BFD_RELOC_MICROMIPS_LO16
:
4221 case BFD_RELOC_MICROMIPS_LITERAL
:
4222 case BFD_RELOC_MICROMIPS_GOT16
:
4223 case BFD_RELOC_MICROMIPS_CALL16
:
4224 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4225 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4226 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4227 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4228 case BFD_RELOC_MICROMIPS_SUB
:
4229 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4230 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4231 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4232 case BFD_RELOC_MICROMIPS_HIGHEST
:
4233 case BFD_RELOC_MICROMIPS_HIGHER
:
4234 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4235 case BFD_RELOC_MICROMIPS_JALR
:
4243 static inline bfd_boolean
4244 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4246 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4249 static inline bfd_boolean
4250 b_reloc_p (bfd_reloc_code_real_type reloc
)
4252 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4253 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4254 || reloc
== BFD_RELOC_16_PCREL_S2
4255 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4256 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4257 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4258 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4261 static inline bfd_boolean
4262 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4264 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4265 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4268 static inline bfd_boolean
4269 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4271 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4272 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4275 static inline bfd_boolean
4276 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4278 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4279 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4282 static inline bfd_boolean
4283 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4285 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4288 static inline bfd_boolean
4289 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4291 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4292 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4295 /* Return true if RELOC is a PC-relative relocation that does not have
4296 full address range. */
4298 static inline bfd_boolean
4299 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4303 case BFD_RELOC_16_PCREL_S2
:
4304 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4305 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4306 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4307 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4308 case BFD_RELOC_MIPS_21_PCREL_S2
:
4309 case BFD_RELOC_MIPS_26_PCREL_S2
:
4310 case BFD_RELOC_MIPS_18_PCREL_S3
:
4311 case BFD_RELOC_MIPS_19_PCREL_S2
:
4314 case BFD_RELOC_32_PCREL
:
4315 case BFD_RELOC_HI16_S_PCREL
:
4316 case BFD_RELOC_LO16_PCREL
:
4317 return HAVE_64BIT_ADDRESSES
;
4324 /* Return true if the given relocation might need a matching %lo().
4325 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4326 need a matching %lo() when applied to local symbols. */
4328 static inline bfd_boolean
4329 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4331 return (HAVE_IN_PLACE_ADDENDS
4332 && (hi16_reloc_p (reloc
)
4333 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4334 all GOT16 relocations evaluate to "G". */
4335 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4338 /* Return the type of %lo() reloc needed by RELOC, given that
4339 reloc_needs_lo_p. */
4341 static inline bfd_reloc_code_real_type
4342 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4344 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4345 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4349 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4352 static inline bfd_boolean
4353 fixup_has_matching_lo_p (fixS
*fixp
)
4355 return (fixp
->fx_next
!= NULL
4356 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4357 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4358 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4361 /* Move all labels in LABELS to the current insertion point. TEXT_P
4362 says whether the labels refer to text or data. */
4365 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4367 struct insn_label_list
*l
;
4370 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4372 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4373 symbol_set_frag (l
->label
, frag_now
);
4374 val
= (valueT
) frag_now_fix ();
4375 /* MIPS16/microMIPS text labels are stored as odd. */
4376 if (text_p
&& HAVE_CODE_COMPRESSION
)
4378 S_SET_VALUE (l
->label
, val
);
4382 /* Move all labels in insn_labels to the current insertion point
4383 and treat them as text labels. */
4386 mips_move_text_labels (void)
4388 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4391 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4394 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4396 bfd_boolean linkonce
= FALSE
;
4397 segT symseg
= S_GET_SEGMENT (sym
);
4399 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4401 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4403 /* The GNU toolchain uses an extension for ELF: a section
4404 beginning with the magic string .gnu.linkonce is a
4405 linkonce section. */
4406 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4407 sizeof ".gnu.linkonce" - 1) == 0)
4413 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4414 linker to handle them specially, such as generating jalx instructions
4415 when needed. We also make them odd for the duration of the assembly,
4416 in order to generate the right sort of code. We will make them even
4417 in the adjust_symtab routine, while leaving them marked. This is
4418 convenient for the debugger and the disassembler. The linker knows
4419 to make them odd again. */
4422 mips_compressed_mark_label (symbolS
*label
)
4424 gas_assert (HAVE_CODE_COMPRESSION
);
4426 if (mips_opts
.mips16
)
4427 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4429 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4430 if ((S_GET_VALUE (label
) & 1) == 0
4431 /* Don't adjust the address if the label is global or weak, or
4432 in a link-once section, since we'll be emitting symbol reloc
4433 references to it which will be patched up by the linker, and
4434 the final value of the symbol may or may not be MIPS16/microMIPS. */
4435 && !S_IS_WEAK (label
)
4436 && !S_IS_EXTERNAL (label
)
4437 && !s_is_linkonce (label
, now_seg
))
4438 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4441 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4444 mips_compressed_mark_labels (void)
4446 struct insn_label_list
*l
;
4448 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4449 mips_compressed_mark_label (l
->label
);
4452 /* End the current frag. Make it a variant frag and record the
4456 relax_close_frag (void)
4458 mips_macro_warning
.first_frag
= frag_now
;
4459 frag_var (rs_machine_dependent
, 0, 0,
4460 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4461 mips_pic
!= NO_PIC
),
4462 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4464 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4465 mips_relax
.first_fixup
= 0;
4468 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4469 See the comment above RELAX_ENCODE for more details. */
4472 relax_start (symbolS
*symbol
)
4474 gas_assert (mips_relax
.sequence
== 0);
4475 mips_relax
.sequence
= 1;
4476 mips_relax
.symbol
= symbol
;
4479 /* Start generating the second version of a relaxable sequence.
4480 See the comment above RELAX_ENCODE for more details. */
4485 gas_assert (mips_relax
.sequence
== 1);
4486 mips_relax
.sequence
= 2;
4489 /* End the current relaxable sequence. */
4494 gas_assert (mips_relax
.sequence
== 2);
4495 relax_close_frag ();
4496 mips_relax
.sequence
= 0;
4499 /* Return true if IP is a delayed branch or jump. */
4501 static inline bfd_boolean
4502 delayed_branch_p (const struct mips_cl_insn
*ip
)
4504 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4505 | INSN_COND_BRANCH_DELAY
4506 | INSN_COND_BRANCH_LIKELY
)) != 0;
4509 /* Return true if IP is a compact branch or jump. */
4511 static inline bfd_boolean
4512 compact_branch_p (const struct mips_cl_insn
*ip
)
4514 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4515 | INSN2_COND_BRANCH
)) != 0;
4518 /* Return true if IP is an unconditional branch or jump. */
4520 static inline bfd_boolean
4521 uncond_branch_p (const struct mips_cl_insn
*ip
)
4523 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4524 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4527 /* Return true if IP is a branch-likely instruction. */
4529 static inline bfd_boolean
4530 branch_likely_p (const struct mips_cl_insn
*ip
)
4532 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4535 /* Return the type of nop that should be used to fill the delay slot
4536 of delayed branch IP. */
4538 static struct mips_cl_insn
*
4539 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4541 if (mips_opts
.micromips
4542 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4543 return µmips_nop32_insn
;
4547 /* Return a mask that has bit N set if OPCODE reads the register(s)
4551 insn_read_mask (const struct mips_opcode
*opcode
)
4553 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4556 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4560 insn_write_mask (const struct mips_opcode
*opcode
)
4562 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4565 /* Return a mask of the registers specified by operand OPERAND of INSN.
4566 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4570 operand_reg_mask (const struct mips_cl_insn
*insn
,
4571 const struct mips_operand
*operand
,
4572 unsigned int type_mask
)
4574 unsigned int uval
, vsel
;
4576 switch (operand
->type
)
4583 case OP_ADDIUSP_INT
:
4584 case OP_ENTRY_EXIT_LIST
:
4585 case OP_REPEAT_DEST_REG
:
4586 case OP_REPEAT_PREV_REG
:
4589 case OP_VU0_MATCH_SUFFIX
:
4597 case OP_OPTIONAL_REG
:
4599 const struct mips_reg_operand
*reg_op
;
4601 reg_op
= (const struct mips_reg_operand
*) operand
;
4602 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4604 uval
= insn_extract_operand (insn
, operand
);
4605 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4610 const struct mips_reg_pair_operand
*pair_op
;
4612 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4613 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4615 uval
= insn_extract_operand (insn
, operand
);
4616 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4619 case OP_CLO_CLZ_DEST
:
4620 if (!(type_mask
& (1 << OP_REG_GP
)))
4622 uval
= insn_extract_operand (insn
, operand
);
4623 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4626 if (!(type_mask
& (1 << OP_REG_GP
)))
4628 uval
= insn_extract_operand (insn
, operand
);
4629 gas_assert ((uval
& 31) == (uval
>> 5));
4630 return 1 << (uval
& 31);
4633 case OP_NON_ZERO_REG
:
4634 if (!(type_mask
& (1 << OP_REG_GP
)))
4636 uval
= insn_extract_operand (insn
, operand
);
4637 return 1 << (uval
& 31);
4639 case OP_LWM_SWM_LIST
:
4642 case OP_SAVE_RESTORE_LIST
:
4645 case OP_MDMX_IMM_REG
:
4646 if (!(type_mask
& (1 << OP_REG_VEC
)))
4648 uval
= insn_extract_operand (insn
, operand
);
4650 if ((vsel
& 0x18) == 0x18)
4652 return 1 << (uval
& 31);
4655 if (!(type_mask
& (1 << OP_REG_GP
)))
4657 return 1 << insn_extract_operand (insn
, operand
);
4662 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4663 where bit N of OPNO_MASK is set if operand N should be included.
4664 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4668 insn_reg_mask (const struct mips_cl_insn
*insn
,
4669 unsigned int type_mask
, unsigned int opno_mask
)
4671 unsigned int opno
, reg_mask
;
4675 while (opno_mask
!= 0)
4678 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4685 /* Return the mask of core registers that IP reads. */
4688 gpr_read_mask (const struct mips_cl_insn
*ip
)
4690 unsigned long pinfo
, pinfo2
;
4693 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4694 pinfo
= ip
->insn_mo
->pinfo
;
4695 pinfo2
= ip
->insn_mo
->pinfo2
;
4696 if (pinfo
& INSN_UDI
)
4698 /* UDI instructions have traditionally been assumed to read RS
4700 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4701 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4703 if (pinfo
& INSN_READ_GPR_24
)
4705 if (pinfo2
& INSN2_READ_GPR_16
)
4707 if (pinfo2
& INSN2_READ_SP
)
4709 if (pinfo2
& INSN2_READ_GPR_31
)
4711 /* Don't include register 0. */
4715 /* Return the mask of core registers that IP writes. */
4718 gpr_write_mask (const struct mips_cl_insn
*ip
)
4720 unsigned long pinfo
, pinfo2
;
4723 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4724 pinfo
= ip
->insn_mo
->pinfo
;
4725 pinfo2
= ip
->insn_mo
->pinfo2
;
4726 if (pinfo
& INSN_WRITE_GPR_24
)
4728 if (pinfo
& INSN_WRITE_GPR_31
)
4730 if (pinfo
& INSN_UDI
)
4731 /* UDI instructions have traditionally been assumed to write to RD. */
4732 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4733 if (pinfo2
& INSN2_WRITE_SP
)
4735 /* Don't include register 0. */
4739 /* Return the mask of floating-point registers that IP reads. */
4742 fpr_read_mask (const struct mips_cl_insn
*ip
)
4744 unsigned long pinfo
;
4747 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4748 | (1 << OP_REG_MSA
)),
4749 insn_read_mask (ip
->insn_mo
));
4750 pinfo
= ip
->insn_mo
->pinfo
;
4751 /* Conservatively treat all operands to an FP_D instruction are doubles.
4752 (This is overly pessimistic for things like cvt.d.s.) */
4753 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4758 /* Return the mask of floating-point registers that IP writes. */
4761 fpr_write_mask (const struct mips_cl_insn
*ip
)
4763 unsigned long pinfo
;
4766 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4767 | (1 << OP_REG_MSA
)),
4768 insn_write_mask (ip
->insn_mo
));
4769 pinfo
= ip
->insn_mo
->pinfo
;
4770 /* Conservatively treat all operands to an FP_D instruction are doubles.
4771 (This is overly pessimistic for things like cvt.s.d.) */
4772 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4777 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4778 Check whether that is allowed. */
4781 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4783 const char *s
= insn
->name
;
4784 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4786 && mips_opts
.oddspreg
;
4788 if (insn
->pinfo
== INSN_MACRO
)
4789 /* Let a macro pass, we'll catch it later when it is expanded. */
4792 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4793 otherwise it depends on oddspreg. */
4794 if ((insn
->pinfo
& FP_S
)
4795 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4796 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4797 return FPR_SIZE
== 32 || oddspreg
;
4799 /* Allow odd registers for single-precision ops and double-precision if the
4800 floating-point registers are 64-bit wide. */
4801 switch (insn
->pinfo
& (FP_S
| FP_D
))
4807 return FPR_SIZE
== 64;
4812 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4813 s
= strchr (insn
->name
, '.');
4814 if (s
!= NULL
&& opnum
== 2)
4815 s
= strchr (s
+ 1, '.');
4816 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4819 return FPR_SIZE
== 64;
4822 /* Information about an instruction argument that we're trying to match. */
4823 struct mips_arg_info
4825 /* The instruction so far. */
4826 struct mips_cl_insn
*insn
;
4828 /* The first unconsumed operand token. */
4829 struct mips_operand_token
*token
;
4831 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4834 /* The 1-based argument number, for error reporting. This does not
4835 count elided optional registers, etc.. */
4838 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4839 unsigned int last_regno
;
4841 /* If the first operand was an OP_REG, this is the register that it
4842 specified, otherwise it is ILLEGAL_REG. */
4843 unsigned int dest_regno
;
4845 /* The value of the last OP_INT operand. Only used for OP_MSB,
4846 where it gives the lsb position. */
4847 unsigned int last_op_int
;
4849 /* If true, match routines should assume that no later instruction
4850 alternative matches and should therefore be as accommodating as
4851 possible. Match routines should not report errors if something
4852 is only invalid for !LAX_MATCH. */
4853 bfd_boolean lax_match
;
4855 /* True if a reference to the current AT register was seen. */
4856 bfd_boolean seen_at
;
4859 /* Record that the argument is out of range. */
4862 match_out_of_range (struct mips_arg_info
*arg
)
4864 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4867 /* Record that the argument isn't constant but needs to be. */
4870 match_not_constant (struct mips_arg_info
*arg
)
4872 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4876 /* Try to match an OT_CHAR token for character CH. Consume the token
4877 and return true on success, otherwise return false. */
4880 match_char (struct mips_arg_info
*arg
, char ch
)
4882 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4892 /* Try to get an expression from the next tokens in ARG. Consume the
4893 tokens and return true on success, storing the expression value in
4894 VALUE and relocation types in R. */
4897 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4898 bfd_reloc_code_real_type
*r
)
4900 /* If the next token is a '(' that was parsed as being part of a base
4901 expression, assume we have an elided offset. The later match will fail
4902 if this turns out to be wrong. */
4903 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4905 value
->X_op
= O_constant
;
4906 value
->X_add_number
= 0;
4907 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4911 /* Reject register-based expressions such as "0+$2" and "(($2))".
4912 For plain registers the default error seems more appropriate. */
4913 if (arg
->token
->type
== OT_INTEGER
4914 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4916 set_insn_error (arg
->argnum
, _("register value used as expression"));
4920 if (arg
->token
->type
== OT_INTEGER
)
4922 *value
= arg
->token
->u
.integer
.value
;
4923 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4929 (arg
->argnum
, _("operand %d must be an immediate expression"),
4934 /* Try to get a constant expression from the next tokens in ARG. Consume
4935 the tokens and return true on success, storing the constant value
4939 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4942 bfd_reloc_code_real_type r
[3];
4944 if (!match_expression (arg
, &ex
, r
))
4947 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4948 *value
= ex
.X_add_number
;
4951 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4952 match_out_of_range (arg
);
4954 match_not_constant (arg
);
4960 /* Return the RTYPE_* flags for a register operand of type TYPE that
4961 appears in instruction OPCODE. */
4964 convert_reg_type (const struct mips_opcode
*opcode
,
4965 enum mips_reg_operand_type type
)
4970 return RTYPE_NUM
| RTYPE_GP
;
4973 /* Allow vector register names for MDMX if the instruction is a 64-bit
4974 FPR load, store or move (including moves to and from GPRs). */
4975 if ((mips_opts
.ase
& ASE_MDMX
)
4976 && (opcode
->pinfo
& FP_D
)
4977 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4978 | INSN_COPROC_MEMORY_DELAY
4981 | INSN_STORE_MEMORY
)))
4982 return RTYPE_FPU
| RTYPE_VEC
;
4986 if (opcode
->pinfo
& (FP_D
| FP_S
))
4987 return RTYPE_CCC
| RTYPE_FCC
;
4991 if (opcode
->membership
& INSN_5400
)
4993 return RTYPE_FPU
| RTYPE_VEC
;
4999 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5000 return RTYPE_NUM
| RTYPE_CP0
;
5007 return RTYPE_NUM
| RTYPE_VI
;
5010 return RTYPE_NUM
| RTYPE_VF
;
5012 case OP_REG_R5900_I
:
5013 return RTYPE_R5900_I
;
5015 case OP_REG_R5900_Q
:
5016 return RTYPE_R5900_Q
;
5018 case OP_REG_R5900_R
:
5019 return RTYPE_R5900_R
;
5021 case OP_REG_R5900_ACC
:
5022 return RTYPE_R5900_ACC
;
5027 case OP_REG_MSA_CTRL
:
5033 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5036 check_regno (struct mips_arg_info
*arg
,
5037 enum mips_reg_operand_type type
, unsigned int regno
)
5039 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5040 arg
->seen_at
= TRUE
;
5042 if (type
== OP_REG_FP
5044 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5046 /* This was a warning prior to introducing O32 FPXX and FP64 support
5047 so maintain a warning for FP32 but raise an error for the new
5050 as_warn (_("float register should be even, was %d"), regno
);
5052 as_bad (_("float register should be even, was %d"), regno
);
5055 if (type
== OP_REG_CCC
)
5060 name
= arg
->insn
->insn_mo
->name
;
5061 length
= strlen (name
);
5062 if ((regno
& 1) != 0
5063 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5064 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5065 as_warn (_("condition code register should be even for %s, was %d"),
5068 if ((regno
& 3) != 0
5069 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5070 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5075 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5076 a register of type TYPE. Return true on success, storing the register
5077 number in *REGNO and warning about any dubious uses. */
5080 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5081 unsigned int symval
, unsigned int *regno
)
5083 if (type
== OP_REG_VEC
)
5084 symval
= mips_prefer_vec_regno (symval
);
5085 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5088 *regno
= symval
& RNUM_MASK
;
5089 check_regno (arg
, type
, *regno
);
5093 /* Try to interpret the next token in ARG as a register of type TYPE.
5094 Consume the token and return true on success, storing the register
5095 number in *REGNO. Return false on failure. */
5098 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5099 unsigned int *regno
)
5101 if (arg
->token
->type
== OT_REG
5102 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5110 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5111 Consume the token and return true on success, storing the register numbers
5112 in *REGNO1 and *REGNO2. Return false on failure. */
5115 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5116 unsigned int *regno1
, unsigned int *regno2
)
5118 if (match_reg (arg
, type
, regno1
))
5123 if (arg
->token
->type
== OT_REG_RANGE
5124 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5125 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5126 && *regno1
<= *regno2
)
5134 /* OP_INT matcher. */
5137 match_int_operand (struct mips_arg_info
*arg
,
5138 const struct mips_operand
*operand_base
)
5140 const struct mips_int_operand
*operand
;
5142 int min_val
, max_val
, factor
;
5145 operand
= (const struct mips_int_operand
*) operand_base
;
5146 factor
= 1 << operand
->shift
;
5147 min_val
= mips_int_operand_min (operand
);
5148 max_val
= mips_int_operand_max (operand
);
5150 if (operand_base
->lsb
== 0
5151 && operand_base
->size
== 16
5152 && operand
->shift
== 0
5153 && operand
->bias
== 0
5154 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5156 /* The operand can be relocated. */
5157 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5160 if (offset_expr
.X_op
== O_big
)
5162 match_out_of_range (arg
);
5166 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5167 /* Relocation operators were used. Accept the argument and
5168 leave the relocation value in offset_expr and offset_relocs
5169 for the caller to process. */
5172 if (offset_expr
.X_op
!= O_constant
)
5174 /* Accept non-constant operands if no later alternative matches,
5175 leaving it for the caller to process. */
5176 if (!arg
->lax_match
)
5178 match_not_constant (arg
);
5181 offset_reloc
[0] = BFD_RELOC_LO16
;
5185 /* Clear the global state; we're going to install the operand
5187 sval
= offset_expr
.X_add_number
;
5188 offset_expr
.X_op
= O_absent
;
5190 /* For compatibility with older assemblers, we accept
5191 0x8000-0xffff as signed 16-bit numbers when only
5192 signed numbers are allowed. */
5195 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5196 if (!arg
->lax_match
&& sval
<= max_val
)
5198 match_out_of_range (arg
);
5205 if (!match_const_int (arg
, &sval
))
5209 arg
->last_op_int
= sval
;
5211 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5213 match_out_of_range (arg
);
5217 uval
= (unsigned int) sval
>> operand
->shift
;
5218 uval
-= operand
->bias
;
5220 /* Handle -mfix-cn63xxp1. */
5222 && mips_fix_cn63xxp1
5223 && !mips_opts
.micromips
5224 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5239 /* The rest must be changed to 28. */
5244 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5248 /* OP_MAPPED_INT matcher. */
5251 match_mapped_int_operand (struct mips_arg_info
*arg
,
5252 const struct mips_operand
*operand_base
)
5254 const struct mips_mapped_int_operand
*operand
;
5255 unsigned int uval
, num_vals
;
5258 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5259 if (!match_const_int (arg
, &sval
))
5262 num_vals
= 1 << operand_base
->size
;
5263 for (uval
= 0; uval
< num_vals
; uval
++)
5264 if (operand
->int_map
[uval
] == sval
)
5266 if (uval
== num_vals
)
5268 match_out_of_range (arg
);
5272 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5276 /* OP_MSB matcher. */
5279 match_msb_operand (struct mips_arg_info
*arg
,
5280 const struct mips_operand
*operand_base
)
5282 const struct mips_msb_operand
*operand
;
5283 int min_val
, max_val
, max_high
;
5284 offsetT size
, sval
, high
;
5286 operand
= (const struct mips_msb_operand
*) operand_base
;
5287 min_val
= operand
->bias
;
5288 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5289 max_high
= operand
->opsize
;
5291 if (!match_const_int (arg
, &size
))
5294 high
= size
+ arg
->last_op_int
;
5295 sval
= operand
->add_lsb
? high
: size
;
5297 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5299 match_out_of_range (arg
);
5302 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5306 /* OP_REG matcher. */
5309 match_reg_operand (struct mips_arg_info
*arg
,
5310 const struct mips_operand
*operand_base
)
5312 const struct mips_reg_operand
*operand
;
5313 unsigned int regno
, uval
, num_vals
;
5315 operand
= (const struct mips_reg_operand
*) operand_base
;
5316 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5319 if (operand
->reg_map
)
5321 num_vals
= 1 << operand
->root
.size
;
5322 for (uval
= 0; uval
< num_vals
; uval
++)
5323 if (operand
->reg_map
[uval
] == regno
)
5325 if (num_vals
== uval
)
5331 arg
->last_regno
= regno
;
5332 if (arg
->opnum
== 1)
5333 arg
->dest_regno
= regno
;
5334 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5338 /* OP_REG_PAIR matcher. */
5341 match_reg_pair_operand (struct mips_arg_info
*arg
,
5342 const struct mips_operand
*operand_base
)
5344 const struct mips_reg_pair_operand
*operand
;
5345 unsigned int regno1
, regno2
, uval
, num_vals
;
5347 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5348 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5349 || !match_char (arg
, ',')
5350 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5353 num_vals
= 1 << operand_base
->size
;
5354 for (uval
= 0; uval
< num_vals
; uval
++)
5355 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5357 if (uval
== num_vals
)
5360 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5364 /* OP_PCREL matcher. The caller chooses the relocation type. */
5367 match_pcrel_operand (struct mips_arg_info
*arg
)
5369 bfd_reloc_code_real_type r
[3];
5371 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5374 /* OP_PERF_REG matcher. */
5377 match_perf_reg_operand (struct mips_arg_info
*arg
,
5378 const struct mips_operand
*operand
)
5382 if (!match_const_int (arg
, &sval
))
5387 || (mips_opts
.arch
== CPU_R5900
5388 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5389 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5391 set_insn_error (arg
->argnum
, _("invalid performance register"));
5395 insn_insert_operand (arg
->insn
, operand
, sval
);
5399 /* OP_ADDIUSP matcher. */
5402 match_addiusp_operand (struct mips_arg_info
*arg
,
5403 const struct mips_operand
*operand
)
5408 if (!match_const_int (arg
, &sval
))
5413 match_out_of_range (arg
);
5418 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5420 match_out_of_range (arg
);
5424 uval
= (unsigned int) sval
;
5425 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5426 insn_insert_operand (arg
->insn
, operand
, uval
);
5430 /* OP_CLO_CLZ_DEST matcher. */
5433 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5434 const struct mips_operand
*operand
)
5438 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5441 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5445 /* OP_CHECK_PREV matcher. */
5448 match_check_prev_operand (struct mips_arg_info
*arg
,
5449 const struct mips_operand
*operand_base
)
5451 const struct mips_check_prev_operand
*operand
;
5454 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5456 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5459 if (!operand
->zero_ok
&& regno
== 0)
5462 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5463 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5464 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5466 arg
->last_regno
= regno
;
5467 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5474 /* OP_SAME_RS_RT matcher. */
5477 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5478 const struct mips_operand
*operand
)
5482 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5487 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5491 arg
->last_regno
= regno
;
5493 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5497 /* OP_LWM_SWM_LIST matcher. */
5500 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5501 const struct mips_operand
*operand
)
5503 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5504 struct mips_arg_info reset
;
5507 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5511 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5516 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5519 while (match_char (arg
, ',')
5520 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5523 if (operand
->size
== 2)
5525 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5531 and any permutations of these. */
5532 if ((reglist
& 0xfff1ffff) != 0x80010000)
5535 sregs
= (reglist
>> 17) & 7;
5540 /* The list must include at least one of ra and s0-sN,
5541 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5542 which are $23 and $30 respectively.) E.g.:
5550 and any permutations of these. */
5551 if ((reglist
& 0x3f00ffff) != 0)
5554 ra
= (reglist
>> 27) & 0x10;
5555 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5558 if ((sregs
& -sregs
) != sregs
)
5561 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5565 /* OP_ENTRY_EXIT_LIST matcher. */
5568 match_entry_exit_operand (struct mips_arg_info
*arg
,
5569 const struct mips_operand
*operand
)
5572 bfd_boolean is_exit
;
5574 /* The format is the same for both ENTRY and EXIT, but the constraints
5576 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5577 mask
= (is_exit
? 7 << 3 : 0);
5580 unsigned int regno1
, regno2
;
5581 bfd_boolean is_freg
;
5583 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5585 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5590 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5593 mask
|= (5 + regno2
) << 3;
5595 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5596 mask
|= (regno2
- 3) << 3;
5597 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5598 mask
|= (regno2
- 15) << 1;
5599 else if (regno1
== RA
&& regno2
== RA
)
5604 while (match_char (arg
, ','));
5606 insn_insert_operand (arg
->insn
, operand
, mask
);
5610 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5611 the argument register mask AMASK, the number of static registers
5612 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5613 respectively, and the frame size FRAME_SIZE. */
5616 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5617 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5618 unsigned int frame_size
)
5620 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5621 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5624 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5625 argument register mask AMASK, the number of static registers saved
5626 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5627 respectively, and the frame size FRAME_SIZE. */
5630 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5631 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5632 unsigned int frame_size
)
5636 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5637 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5638 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5639 | ((frame_size
& 0xf0) << 16));
5643 /* OP_SAVE_RESTORE_LIST matcher. */
5646 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5648 unsigned int opcode
, args
, statics
, sregs
;
5649 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5650 unsigned int arg_mask
, ra
, s0
, s1
;
5653 opcode
= arg
->insn
->insn_opcode
;
5655 num_frame_sizes
= 0;
5664 unsigned int regno1
, regno2
;
5666 if (arg
->token
->type
== OT_INTEGER
)
5668 /* Handle the frame size. */
5669 if (!match_const_int (arg
, &frame_size
))
5671 num_frame_sizes
+= 1;
5675 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5678 while (regno1
<= regno2
)
5680 if (regno1
>= 4 && regno1
<= 7)
5682 if (num_frame_sizes
== 0)
5684 args
|= 1 << (regno1
- 4);
5686 /* statics $a0-$a3 */
5687 statics
|= 1 << (regno1
- 4);
5689 else if (regno1
>= 16 && regno1
<= 23)
5691 sregs
|= 1 << (regno1
- 16);
5692 else if (regno1
== 30)
5695 else if (regno1
== 31)
5696 /* Add $ra to insn. */
5706 while (match_char (arg
, ','));
5708 /* Encode args/statics combination. */
5711 else if (args
== 0xf)
5712 /* All $a0-$a3 are args. */
5713 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5714 else if (statics
== 0xf)
5715 /* All $a0-$a3 are statics. */
5716 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5719 /* Count arg registers. */
5729 /* Count static registers. */
5731 while (statics
& 0x8)
5733 statics
= (statics
<< 1) & 0xf;
5739 /* Encode args/statics. */
5740 arg_mask
= (num_args
<< 2) | num_statics
;
5743 /* Encode $s0/$s1. */
5744 if (sregs
& (1 << 0)) /* $s0 */
5746 if (sregs
& (1 << 1)) /* $s1 */
5750 /* Encode $s2-$s8. */
5760 /* Encode frame size. */
5761 if (num_frame_sizes
== 0)
5763 set_insn_error (arg
->argnum
, _("missing frame size"));
5766 if (num_frame_sizes
> 1)
5768 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5771 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5773 set_insn_error (arg
->argnum
, _("invalid frame size"));
5778 /* Finally build the instruction. */
5779 if (mips_opts
.mips16
)
5780 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5782 else if (!mips_opts
.micromips
)
5783 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5788 arg
->insn
->insn_opcode
= opcode
;
5792 /* OP_MDMX_IMM_REG matcher. */
5795 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5796 const struct mips_operand
*operand
)
5798 unsigned int regno
, uval
;
5800 const struct mips_opcode
*opcode
;
5802 /* The mips_opcode records whether this is an octobyte or quadhalf
5803 instruction. Start out with that bit in place. */
5804 opcode
= arg
->insn
->insn_mo
;
5805 uval
= mips_extract_operand (operand
, opcode
->match
);
5806 is_qh
= (uval
!= 0);
5808 if (arg
->token
->type
== OT_REG
)
5810 if ((opcode
->membership
& INSN_5400
)
5811 && strcmp (opcode
->name
, "rzu.ob") == 0)
5813 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5818 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5822 /* Check whether this is a vector register or a broadcast of
5823 a single element. */
5824 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5826 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5828 set_insn_error (arg
->argnum
, _("invalid element selector"));
5831 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5836 /* A full vector. */
5837 if ((opcode
->membership
& INSN_5400
)
5838 && (strcmp (opcode
->name
, "sll.ob") == 0
5839 || strcmp (opcode
->name
, "srl.ob") == 0))
5841 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5847 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5849 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5857 if (!match_const_int (arg
, &sval
))
5859 if (sval
< 0 || sval
> 31)
5861 match_out_of_range (arg
);
5864 uval
|= (sval
& 31);
5866 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5868 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5870 insn_insert_operand (arg
->insn
, operand
, uval
);
5874 /* OP_IMM_INDEX matcher. */
5877 match_imm_index_operand (struct mips_arg_info
*arg
,
5878 const struct mips_operand
*operand
)
5880 unsigned int max_val
;
5882 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5885 max_val
= (1 << operand
->size
) - 1;
5886 if (arg
->token
->u
.index
> max_val
)
5888 match_out_of_range (arg
);
5891 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5896 /* OP_REG_INDEX matcher. */
5899 match_reg_index_operand (struct mips_arg_info
*arg
,
5900 const struct mips_operand
*operand
)
5904 if (arg
->token
->type
!= OT_REG_INDEX
)
5907 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5910 insn_insert_operand (arg
->insn
, operand
, regno
);
5915 /* OP_PC matcher. */
5918 match_pc_operand (struct mips_arg_info
*arg
)
5920 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5928 /* OP_REG28 matcher. */
5931 match_reg28_operand (struct mips_arg_info
*arg
)
5935 if (arg
->token
->type
== OT_REG
5936 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5945 /* OP_NON_ZERO_REG matcher. */
5948 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5949 const struct mips_operand
*operand
)
5953 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5959 arg
->last_regno
= regno
;
5960 insn_insert_operand (arg
->insn
, operand
, regno
);
5964 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5965 register that we need to match. */
5968 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5972 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5975 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5976 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5977 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5979 Return the constant in IMM and OFFSET as follows:
5981 - If the constant should be loaded via memory, set IMM to O_absent and
5982 OFFSET to the memory address.
5984 - Otherwise, if the constant should be loaded into two 32-bit registers,
5985 set IMM to the O_constant to load into the high register and OFFSET
5986 to the corresponding value for the low register.
5988 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5990 These constants only appear as the last operand in an instruction,
5991 and every instruction that accepts them in any variant accepts them
5992 in all variants. This means we don't have to worry about backing out
5993 any changes if the instruction does not match. We just match
5994 unconditionally and report an error if the constant is invalid. */
5997 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5998 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6003 const char *newname
;
6004 unsigned char *data
;
6006 /* Where the constant is placed is based on how the MIPS assembler
6009 length == 4 && using_gprs -- immediate value only
6010 length == 8 && using_gprs -- .rdata or immediate value
6011 length == 4 && !using_gprs -- .lit4 or immediate value
6012 length == 8 && !using_gprs -- .lit8 or immediate value
6014 The .lit4 and .lit8 sections are only used if permitted by the
6016 if (arg
->token
->type
!= OT_FLOAT
)
6018 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6022 gas_assert (arg
->token
->u
.flt
.length
== length
);
6023 data
= arg
->token
->u
.flt
.data
;
6026 /* Handle 32-bit constants for which an immediate value is best. */
6029 || g_switch_value
< 4
6030 || (data
[0] == 0 && data
[1] == 0)
6031 || (data
[2] == 0 && data
[3] == 0)))
6033 imm
->X_op
= O_constant
;
6034 if (!target_big_endian
)
6035 imm
->X_add_number
= bfd_getl32 (data
);
6037 imm
->X_add_number
= bfd_getb32 (data
);
6038 offset
->X_op
= O_absent
;
6042 /* Handle 64-bit constants for which an immediate value is best. */
6044 && !mips_disable_float_construction
6045 /* Constants can only be constructed in GPRs and copied to FPRs if the
6046 GPRs are at least as wide as the FPRs or MTHC1 is available.
6047 Unlike most tests for 32-bit floating-point registers this check
6048 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6049 permit 64-bit moves without MXHC1.
6050 Force the constant into memory otherwise. */
6053 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6055 && ((data
[0] == 0 && data
[1] == 0)
6056 || (data
[2] == 0 && data
[3] == 0))
6057 && ((data
[4] == 0 && data
[5] == 0)
6058 || (data
[6] == 0 && data
[7] == 0)))
6060 /* The value is simple enough to load with a couple of instructions.
6061 If using 32-bit registers, set IMM to the high order 32 bits and
6062 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6064 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6066 imm
->X_op
= O_constant
;
6067 offset
->X_op
= O_constant
;
6068 if (!target_big_endian
)
6070 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6071 offset
->X_add_number
= bfd_getl32 (data
);
6075 imm
->X_add_number
= bfd_getb32 (data
);
6076 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6078 if (offset
->X_add_number
== 0)
6079 offset
->X_op
= O_absent
;
6083 imm
->X_op
= O_constant
;
6084 if (!target_big_endian
)
6085 imm
->X_add_number
= bfd_getl64 (data
);
6087 imm
->X_add_number
= bfd_getb64 (data
);
6088 offset
->X_op
= O_absent
;
6093 /* Switch to the right section. */
6095 subseg
= now_subseg
;
6098 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6103 if (using_gprs
|| g_switch_value
< 8)
6104 newname
= RDATA_SECTION_NAME
;
6109 new_seg
= subseg_new (newname
, (subsegT
) 0);
6110 bfd_set_section_flags (stdoutput
, new_seg
,
6111 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6112 frag_align (length
== 4 ? 2 : 3, 0, 0);
6113 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6114 record_alignment (new_seg
, 4);
6116 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6118 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6120 /* Set the argument to the current address in the section. */
6121 imm
->X_op
= O_absent
;
6122 offset
->X_op
= O_symbol
;
6123 offset
->X_add_symbol
= symbol_temp_new_now ();
6124 offset
->X_add_number
= 0;
6126 /* Put the floating point number into the section. */
6127 p
= frag_more (length
);
6128 memcpy (p
, data
, length
);
6130 /* Switch back to the original section. */
6131 subseg_set (seg
, subseg
);
6135 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6139 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6140 const struct mips_operand
*operand
,
6141 bfd_boolean match_p
)
6145 /* The operand can be an XYZW mask or a single 2-bit channel index
6146 (with X being 0). */
6147 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6149 /* The suffix can be omitted when it is already part of the opcode. */
6150 if (arg
->token
->type
!= OT_CHANNELS
)
6153 uval
= arg
->token
->u
.channels
;
6154 if (operand
->size
== 2)
6156 /* Check that a single bit is set and convert it into a 2-bit index. */
6157 if ((uval
& -uval
) != uval
)
6159 uval
= 4 - ffs (uval
);
6162 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6167 insn_insert_operand (arg
->insn
, operand
, uval
);
6171 /* Try to match a token from ARG against OPERAND. Consume the token
6172 and return true on success, otherwise return false. */
6175 match_operand (struct mips_arg_info
*arg
,
6176 const struct mips_operand
*operand
)
6178 switch (operand
->type
)
6181 return match_int_operand (arg
, operand
);
6184 return match_mapped_int_operand (arg
, operand
);
6187 return match_msb_operand (arg
, operand
);
6190 case OP_OPTIONAL_REG
:
6191 return match_reg_operand (arg
, operand
);
6194 return match_reg_pair_operand (arg
, operand
);
6197 return match_pcrel_operand (arg
);
6200 return match_perf_reg_operand (arg
, operand
);
6202 case OP_ADDIUSP_INT
:
6203 return match_addiusp_operand (arg
, operand
);
6205 case OP_CLO_CLZ_DEST
:
6206 return match_clo_clz_dest_operand (arg
, operand
);
6208 case OP_LWM_SWM_LIST
:
6209 return match_lwm_swm_list_operand (arg
, operand
);
6211 case OP_ENTRY_EXIT_LIST
:
6212 return match_entry_exit_operand (arg
, operand
);
6214 case OP_SAVE_RESTORE_LIST
:
6215 return match_save_restore_list_operand (arg
);
6217 case OP_MDMX_IMM_REG
:
6218 return match_mdmx_imm_reg_operand (arg
, operand
);
6220 case OP_REPEAT_DEST_REG
:
6221 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6223 case OP_REPEAT_PREV_REG
:
6224 return match_tied_reg_operand (arg
, arg
->last_regno
);
6227 return match_pc_operand (arg
);
6230 return match_reg28_operand (arg
);
6233 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6235 case OP_VU0_MATCH_SUFFIX
:
6236 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6239 return match_imm_index_operand (arg
, operand
);
6242 return match_reg_index_operand (arg
, operand
);
6245 return match_same_rs_rt_operand (arg
, operand
);
6248 return match_check_prev_operand (arg
, operand
);
6250 case OP_NON_ZERO_REG
:
6251 return match_non_zero_reg_operand (arg
, operand
);
6256 /* ARG is the state after successfully matching an instruction.
6257 Issue any queued-up warnings. */
6260 check_completed_insn (struct mips_arg_info
*arg
)
6265 as_warn (_("used $at without \".set noat\""));
6267 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6271 /* Return true if modifying general-purpose register REG needs a delay. */
6274 reg_needs_delay (unsigned int reg
)
6276 unsigned long prev_pinfo
;
6278 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6279 if (!mips_opts
.noreorder
6280 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6281 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6282 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6288 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6289 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6290 by VR4120 errata. */
6293 classify_vr4120_insn (const char *name
)
6295 if (strncmp (name
, "macc", 4) == 0)
6296 return FIX_VR4120_MACC
;
6297 if (strncmp (name
, "dmacc", 5) == 0)
6298 return FIX_VR4120_DMACC
;
6299 if (strncmp (name
, "mult", 4) == 0)
6300 return FIX_VR4120_MULT
;
6301 if (strncmp (name
, "dmult", 5) == 0)
6302 return FIX_VR4120_DMULT
;
6303 if (strstr (name
, "div"))
6304 return FIX_VR4120_DIV
;
6305 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6306 return FIX_VR4120_MTHILO
;
6307 return NUM_FIX_VR4120_CLASSES
;
6310 #define INSN_ERET 0x42000018
6311 #define INSN_DERET 0x4200001f
6312 #define INSN_DMULT 0x1c
6313 #define INSN_DMULTU 0x1d
6315 /* Return the number of instructions that must separate INSN1 and INSN2,
6316 where INSN1 is the earlier instruction. Return the worst-case value
6317 for any INSN2 if INSN2 is null. */
6320 insns_between (const struct mips_cl_insn
*insn1
,
6321 const struct mips_cl_insn
*insn2
)
6323 unsigned long pinfo1
, pinfo2
;
6326 /* If INFO2 is null, pessimistically assume that all flags are set for
6327 the second instruction. */
6328 pinfo1
= insn1
->insn_mo
->pinfo
;
6329 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6331 /* For most targets, write-after-read dependencies on the HI and LO
6332 registers must be separated by at least two instructions. */
6333 if (!hilo_interlocks
)
6335 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6337 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6341 /* If we're working around r7000 errata, there must be two instructions
6342 between an mfhi or mflo and any instruction that uses the result. */
6343 if (mips_7000_hilo_fix
6344 && !mips_opts
.micromips
6345 && MF_HILO_INSN (pinfo1
)
6346 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6349 /* If we're working around 24K errata, one instruction is required
6350 if an ERET or DERET is followed by a branch instruction. */
6351 if (mips_fix_24k
&& !mips_opts
.micromips
)
6353 if (insn1
->insn_opcode
== INSN_ERET
6354 || insn1
->insn_opcode
== INSN_DERET
)
6357 || insn2
->insn_opcode
== INSN_ERET
6358 || insn2
->insn_opcode
== INSN_DERET
6359 || delayed_branch_p (insn2
))
6364 /* If we're working around PMC RM7000 errata, there must be three
6365 nops between a dmult and a load instruction. */
6366 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6368 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6369 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6371 if (pinfo2
& INSN_LOAD_MEMORY
)
6376 /* If working around VR4120 errata, check for combinations that need
6377 a single intervening instruction. */
6378 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6380 unsigned int class1
, class2
;
6382 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6383 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6387 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6388 if (vr4120_conflicts
[class1
] & (1 << class2
))
6393 if (!HAVE_CODE_COMPRESSION
)
6395 /* Check for GPR or coprocessor load delays. All such delays
6396 are on the RT register. */
6397 /* Itbl support may require additional care here. */
6398 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6399 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6401 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6405 /* Check for generic coprocessor hazards.
6407 This case is not handled very well. There is no special
6408 knowledge of CP0 handling, and the coprocessors other than
6409 the floating point unit are not distinguished at all. */
6410 /* Itbl support may require additional care here. FIXME!
6411 Need to modify this to include knowledge about
6412 user specified delays! */
6413 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6414 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6416 /* Handle cases where INSN1 writes to a known general coprocessor
6417 register. There must be a one instruction delay before INSN2
6418 if INSN2 reads that register, otherwise no delay is needed. */
6419 mask
= fpr_write_mask (insn1
);
6422 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6427 /* Read-after-write dependencies on the control registers
6428 require a two-instruction gap. */
6429 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6430 && (pinfo2
& INSN_READ_COND_CODE
))
6433 /* We don't know exactly what INSN1 does. If INSN2 is
6434 also a coprocessor instruction, assume there must be
6435 a one instruction gap. */
6436 if (pinfo2
& INSN_COP
)
6441 /* Check for read-after-write dependencies on the coprocessor
6442 control registers in cases where INSN1 does not need a general
6443 coprocessor delay. This means that INSN1 is a floating point
6444 comparison instruction. */
6445 /* Itbl support may require additional care here. */
6446 else if (!cop_interlocks
6447 && (pinfo1
& INSN_WRITE_COND_CODE
)
6448 && (pinfo2
& INSN_READ_COND_CODE
))
6452 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6453 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6455 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6456 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6457 || (insn2
&& delayed_branch_p (insn2
))))
6463 /* Return the number of nops that would be needed to work around the
6464 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6465 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6466 that are contained within the first IGNORE instructions of HIST. */
6469 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6470 const struct mips_cl_insn
*insn
)
6475 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6476 are not affected by the errata. */
6478 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6479 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6480 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6483 /* Search for the first MFLO or MFHI. */
6484 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6485 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6487 /* Extract the destination register. */
6488 mask
= gpr_write_mask (&hist
[i
]);
6490 /* No nops are needed if INSN reads that register. */
6491 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6494 /* ...or if any of the intervening instructions do. */
6495 for (j
= 0; j
< i
; j
++)
6496 if (gpr_read_mask (&hist
[j
]) & mask
)
6500 return MAX_VR4130_NOPS
- i
;
6505 #define BASE_REG_EQ(INSN1, INSN2) \
6506 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6507 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6509 /* Return the minimum alignment for this store instruction. */
6512 fix_24k_align_to (const struct mips_opcode
*mo
)
6514 if (strcmp (mo
->name
, "sh") == 0)
6517 if (strcmp (mo
->name
, "swc1") == 0
6518 || strcmp (mo
->name
, "swc2") == 0
6519 || strcmp (mo
->name
, "sw") == 0
6520 || strcmp (mo
->name
, "sc") == 0
6521 || strcmp (mo
->name
, "s.s") == 0)
6524 if (strcmp (mo
->name
, "sdc1") == 0
6525 || strcmp (mo
->name
, "sdc2") == 0
6526 || strcmp (mo
->name
, "s.d") == 0)
6533 struct fix_24k_store_info
6535 /* Immediate offset, if any, for this store instruction. */
6537 /* Alignment required by this store instruction. */
6539 /* True for register offsets. */
6540 int register_offset
;
6543 /* Comparison function used by qsort. */
6546 fix_24k_sort (const void *a
, const void *b
)
6548 const struct fix_24k_store_info
*pos1
= a
;
6549 const struct fix_24k_store_info
*pos2
= b
;
6551 return (pos1
->off
- pos2
->off
);
6554 /* INSN is a store instruction. Try to record the store information
6555 in STINFO. Return false if the information isn't known. */
6558 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6559 const struct mips_cl_insn
*insn
)
6561 /* The instruction must have a known offset. */
6562 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6565 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6566 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6570 /* Return the number of nops that would be needed to work around the 24k
6571 "lost data on stores during refill" errata if instruction INSN
6572 immediately followed the 2 instructions described by HIST.
6573 Ignore hazards that are contained within the first IGNORE
6574 instructions of HIST.
6576 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6577 for the data cache refills and store data. The following describes
6578 the scenario where the store data could be lost.
6580 * A data cache miss, due to either a load or a store, causing fill
6581 data to be supplied by the memory subsystem
6582 * The first three doublewords of fill data are returned and written
6584 * A sequence of four stores occurs in consecutive cycles around the
6585 final doubleword of the fill:
6589 * Zero, One or more instructions
6592 The four stores A-D must be to different doublewords of the line that
6593 is being filled. The fourth instruction in the sequence above permits
6594 the fill of the final doubleword to be transferred from the FSB into
6595 the cache. In the sequence above, the stores may be either integer
6596 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6597 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6598 different doublewords on the line. If the floating point unit is
6599 running in 1:2 mode, it is not possible to create the sequence above
6600 using only floating point store instructions.
6602 In this case, the cache line being filled is incorrectly marked
6603 invalid, thereby losing the data from any store to the line that
6604 occurs between the original miss and the completion of the five
6605 cycle sequence shown above.
6607 The workarounds are:
6609 * Run the data cache in write-through mode.
6610 * Insert a non-store instruction between
6611 Store A and Store B or Store B and Store C. */
6614 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6615 const struct mips_cl_insn
*insn
)
6617 struct fix_24k_store_info pos
[3];
6618 int align
, i
, base_offset
;
6623 /* If the previous instruction wasn't a store, there's nothing to
6625 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6628 /* If the instructions after the previous one are unknown, we have
6629 to assume the worst. */
6633 /* Check whether we are dealing with three consecutive stores. */
6634 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6635 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6638 /* If we don't know the relationship between the store addresses,
6639 assume the worst. */
6640 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6641 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6644 if (!fix_24k_record_store_info (&pos
[0], insn
)
6645 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6646 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6649 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6651 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6652 X bytes and such that the base register + X is known to be aligned
6655 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6659 align
= pos
[0].align_to
;
6660 base_offset
= pos
[0].off
;
6661 for (i
= 1; i
< 3; i
++)
6662 if (align
< pos
[i
].align_to
)
6664 align
= pos
[i
].align_to
;
6665 base_offset
= pos
[i
].off
;
6667 for (i
= 0; i
< 3; i
++)
6668 pos
[i
].off
-= base_offset
;
6671 pos
[0].off
&= ~align
+ 1;
6672 pos
[1].off
&= ~align
+ 1;
6673 pos
[2].off
&= ~align
+ 1;
6675 /* If any two stores write to the same chunk, they also write to the
6676 same doubleword. The offsets are still sorted at this point. */
6677 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6680 /* A range of at least 9 bytes is needed for the stores to be in
6681 non-overlapping doublewords. */
6682 if (pos
[2].off
- pos
[0].off
<= 8)
6685 if (pos
[2].off
- pos
[1].off
>= 24
6686 || pos
[1].off
- pos
[0].off
>= 24
6687 || pos
[2].off
- pos
[0].off
>= 32)
6693 /* Return the number of nops that would be needed if instruction INSN
6694 immediately followed the MAX_NOPS instructions given by HIST,
6695 where HIST[0] is the most recent instruction. Ignore hazards
6696 between INSN and the first IGNORE instructions in HIST.
6698 If INSN is null, return the worse-case number of nops for any
6702 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6703 const struct mips_cl_insn
*insn
)
6705 int i
, nops
, tmp_nops
;
6708 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6710 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6711 if (tmp_nops
> nops
)
6715 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6717 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6718 if (tmp_nops
> nops
)
6722 if (mips_fix_24k
&& !mips_opts
.micromips
)
6724 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6725 if (tmp_nops
> nops
)
6732 /* The variable arguments provide NUM_INSNS extra instructions that
6733 might be added to HIST. Return the largest number of nops that
6734 would be needed after the extended sequence, ignoring hazards
6735 in the first IGNORE instructions. */
6738 nops_for_sequence (int num_insns
, int ignore
,
6739 const struct mips_cl_insn
*hist
, ...)
6742 struct mips_cl_insn buffer
[MAX_NOPS
];
6743 struct mips_cl_insn
*cursor
;
6746 va_start (args
, hist
);
6747 cursor
= buffer
+ num_insns
;
6748 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6749 while (cursor
> buffer
)
6750 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6752 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6757 /* Like nops_for_insn, but if INSN is a branch, take into account the
6758 worst-case delay for the branch target. */
6761 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6762 const struct mips_cl_insn
*insn
)
6766 nops
= nops_for_insn (ignore
, hist
, insn
);
6767 if (delayed_branch_p (insn
))
6769 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6770 hist
, insn
, get_delay_slot_nop (insn
));
6771 if (tmp_nops
> nops
)
6774 else if (compact_branch_p (insn
))
6776 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6777 if (tmp_nops
> nops
)
6783 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6786 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6788 gas_assert (!HAVE_CODE_COMPRESSION
);
6789 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6790 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6793 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6794 jr target pc &= 'hffff_ffff_cfff_ffff. */
6797 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6799 gas_assert (!HAVE_CODE_COMPRESSION
);
6800 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6801 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6802 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6810 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6811 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6814 ep
.X_op
= O_constant
;
6815 ep
.X_add_number
= 0xcfff0000;
6816 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6817 ep
.X_add_number
= 0xffff;
6818 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6819 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6824 fix_loongson2f (struct mips_cl_insn
* ip
)
6826 if (mips_fix_loongson2f_nop
)
6827 fix_loongson2f_nop (ip
);
6829 if (mips_fix_loongson2f_jump
)
6830 fix_loongson2f_jump (ip
);
6833 /* IP is a branch that has a delay slot, and we need to fill it
6834 automatically. Return true if we can do that by swapping IP
6835 with the previous instruction.
6836 ADDRESS_EXPR is an operand of the instruction to be used with
6840 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6841 bfd_reloc_code_real_type
*reloc_type
)
6843 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6844 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6845 unsigned int fpr_read
, prev_fpr_write
;
6847 /* -O2 and above is required for this optimization. */
6848 if (mips_optimize
< 2)
6851 /* If we have seen .set volatile or .set nomove, don't optimize. */
6852 if (mips_opts
.nomove
)
6855 /* We can't swap if the previous instruction's position is fixed. */
6856 if (history
[0].fixed_p
)
6859 /* If the previous previous insn was in a .set noreorder, we can't
6860 swap. Actually, the MIPS assembler will swap in this situation.
6861 However, gcc configured -with-gnu-as will generate code like
6869 in which we can not swap the bne and INSN. If gcc is not configured
6870 -with-gnu-as, it does not output the .set pseudo-ops. */
6871 if (history
[1].noreorder_p
)
6874 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6875 This means that the previous instruction was a 4-byte one anyhow. */
6876 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6879 /* If the branch is itself the target of a branch, we can not swap.
6880 We cheat on this; all we check for is whether there is a label on
6881 this instruction. If there are any branches to anything other than
6882 a label, users must use .set noreorder. */
6883 if (seg_info (now_seg
)->label_list
)
6886 /* If the previous instruction is in a variant frag other than this
6887 branch's one, we cannot do the swap. This does not apply to
6888 MIPS16 code, which uses variant frags for different purposes. */
6889 if (!mips_opts
.mips16
6891 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6894 /* We do not swap with instructions that cannot architecturally
6895 be placed in a branch delay slot, such as SYNC or ERET. We
6896 also refrain from swapping with a trap instruction, since it
6897 complicates trap handlers to have the trap instruction be in
6899 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6900 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6903 /* Check for conflicts between the branch and the instructions
6904 before the candidate delay slot. */
6905 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6908 /* Check for conflicts between the swapped sequence and the
6909 target of the branch. */
6910 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6913 /* If the branch reads a register that the previous
6914 instruction sets, we can not swap. */
6915 gpr_read
= gpr_read_mask (ip
);
6916 prev_gpr_write
= gpr_write_mask (&history
[0]);
6917 if (gpr_read
& prev_gpr_write
)
6920 fpr_read
= fpr_read_mask (ip
);
6921 prev_fpr_write
= fpr_write_mask (&history
[0]);
6922 if (fpr_read
& prev_fpr_write
)
6925 /* If the branch writes a register that the previous
6926 instruction sets, we can not swap. */
6927 gpr_write
= gpr_write_mask (ip
);
6928 if (gpr_write
& prev_gpr_write
)
6931 /* If the branch writes a register that the previous
6932 instruction reads, we can not swap. */
6933 prev_gpr_read
= gpr_read_mask (&history
[0]);
6934 if (gpr_write
& prev_gpr_read
)
6937 /* If one instruction sets a condition code and the
6938 other one uses a condition code, we can not swap. */
6939 pinfo
= ip
->insn_mo
->pinfo
;
6940 if ((pinfo
& INSN_READ_COND_CODE
)
6941 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6943 if ((pinfo
& INSN_WRITE_COND_CODE
)
6944 && (prev_pinfo
& INSN_READ_COND_CODE
))
6947 /* If the previous instruction uses the PC, we can not swap. */
6948 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6949 if (prev_pinfo2
& INSN2_READ_PC
)
6952 /* If the previous instruction has an incorrect size for a fixed
6953 branch delay slot in microMIPS mode, we cannot swap. */
6954 pinfo2
= ip
->insn_mo
->pinfo2
;
6955 if (mips_opts
.micromips
6956 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6957 && insn_length (history
) != 2)
6959 if (mips_opts
.micromips
6960 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6961 && insn_length (history
) != 4)
6964 /* On R5900 short loops need to be fixed by inserting a nop in
6965 the branch delay slots.
6966 A short loop can be terminated too early. */
6967 if (mips_opts
.arch
== CPU_R5900
6968 /* Check if instruction has a parameter, ignore "j $31". */
6969 && (address_expr
!= NULL
)
6970 /* Parameter must be 16 bit. */
6971 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6972 /* Branch to same segment. */
6973 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6974 /* Branch to same code fragment. */
6975 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6976 /* Can only calculate branch offset if value is known. */
6977 && symbol_constant_p (address_expr
->X_add_symbol
)
6978 /* Check if branch is really conditional. */
6979 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6980 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6981 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6984 /* Check if loop is shorter than 6 instructions including
6985 branch and delay slot. */
6986 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6993 /* When the loop includes branches or jumps,
6994 it is not a short loop. */
6995 for (i
= 0; i
< (distance
/ 4); i
++)
6997 if ((history
[i
].cleared_p
)
6998 || delayed_branch_p (&history
[i
]))
7006 /* Insert nop after branch to fix short loop. */
7015 /* Decide how we should add IP to the instruction stream.
7016 ADDRESS_EXPR is an operand of the instruction to be used with
7019 static enum append_method
7020 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7021 bfd_reloc_code_real_type
*reloc_type
)
7023 /* The relaxed version of a macro sequence must be inherently
7025 if (mips_relax
.sequence
== 2)
7028 /* We must not dabble with instructions in a ".set noreorder" block. */
7029 if (mips_opts
.noreorder
)
7032 /* Otherwise, it's our responsibility to fill branch delay slots. */
7033 if (delayed_branch_p (ip
))
7035 if (!branch_likely_p (ip
)
7036 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7039 if (mips_opts
.mips16
7040 && ISA_SUPPORTS_MIPS16E
7041 && gpr_read_mask (ip
) != 0)
7042 return APPEND_ADD_COMPACT
;
7044 if (mips_opts
.micromips
7045 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7046 || (!forced_insn_length
7047 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7048 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7049 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7050 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7051 return APPEND_ADD_COMPACT
;
7053 return APPEND_ADD_WITH_NOP
;
7059 /* IP is an instruction whose opcode we have just changed, END points
7060 to the end of the opcode table processed. Point IP->insn_mo to the
7061 new opcode's definition. */
7064 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7066 const struct mips_opcode
*mo
;
7068 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7069 if (mo
->pinfo
!= INSN_MACRO
7070 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7078 /* IP is a MIPS16 instruction whose opcode we have just changed.
7079 Point IP->insn_mo to the new opcode's definition. */
7082 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7084 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7087 /* IP is a microMIPS instruction whose opcode we have just changed.
7088 Point IP->insn_mo to the new opcode's definition. */
7091 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7093 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7096 /* For microMIPS macros, we need to generate a local number label
7097 as the target of branches. */
7098 #define MICROMIPS_LABEL_CHAR '\037'
7099 static unsigned long micromips_target_label
;
7100 static char micromips_target_name
[32];
7103 micromips_label_name (void)
7105 char *p
= micromips_target_name
;
7106 char symbol_name_temporary
[24];
7114 l
= micromips_target_label
;
7115 #ifdef LOCAL_LABEL_PREFIX
7116 *p
++ = LOCAL_LABEL_PREFIX
;
7119 *p
++ = MICROMIPS_LABEL_CHAR
;
7122 symbol_name_temporary
[i
++] = l
% 10 + '0';
7127 *p
++ = symbol_name_temporary
[--i
];
7130 return micromips_target_name
;
7134 micromips_label_expr (expressionS
*label_expr
)
7136 label_expr
->X_op
= O_symbol
;
7137 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7138 label_expr
->X_add_number
= 0;
7142 micromips_label_inc (void)
7144 micromips_target_label
++;
7145 *micromips_target_name
= '\0';
7149 micromips_add_label (void)
7153 s
= colon (micromips_label_name ());
7154 micromips_label_inc ();
7155 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7158 /* If assembling microMIPS code, then return the microMIPS reloc
7159 corresponding to the requested one if any. Otherwise return
7160 the reloc unchanged. */
7162 static bfd_reloc_code_real_type
7163 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7165 static const bfd_reloc_code_real_type relocs
[][2] =
7167 /* Keep sorted incrementally by the left-hand key. */
7168 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7169 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7170 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7171 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7172 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7173 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7174 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7175 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7176 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7177 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7178 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7179 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7180 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7181 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7182 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7183 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7184 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7185 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7186 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7187 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7188 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7189 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7190 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7191 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7192 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7193 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7194 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7196 bfd_reloc_code_real_type r
;
7199 if (!mips_opts
.micromips
)
7201 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7207 return relocs
[i
][1];
7212 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7213 Return true on success, storing the resolved value in RESULT. */
7216 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7221 case BFD_RELOC_MIPS_HIGHEST
:
7222 case BFD_RELOC_MICROMIPS_HIGHEST
:
7223 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7226 case BFD_RELOC_MIPS_HIGHER
:
7227 case BFD_RELOC_MICROMIPS_HIGHER
:
7228 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7231 case BFD_RELOC_HI16_S
:
7232 case BFD_RELOC_HI16_S_PCREL
:
7233 case BFD_RELOC_MICROMIPS_HI16_S
:
7234 case BFD_RELOC_MIPS16_HI16_S
:
7235 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7238 case BFD_RELOC_HI16
:
7239 case BFD_RELOC_MICROMIPS_HI16
:
7240 case BFD_RELOC_MIPS16_HI16
:
7241 *result
= (operand
>> 16) & 0xffff;
7244 case BFD_RELOC_LO16
:
7245 case BFD_RELOC_LO16_PCREL
:
7246 case BFD_RELOC_MICROMIPS_LO16
:
7247 case BFD_RELOC_MIPS16_LO16
:
7248 *result
= operand
& 0xffff;
7251 case BFD_RELOC_UNUSED
:
7260 /* Output an instruction. IP is the instruction information.
7261 ADDRESS_EXPR is an operand of the instruction to be used with
7262 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7263 a macro expansion. */
7266 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7267 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7269 unsigned long prev_pinfo2
, pinfo
;
7270 bfd_boolean relaxed_branch
= FALSE
;
7271 enum append_method method
;
7272 bfd_boolean relax32
;
7275 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7276 fix_loongson2f (ip
);
7278 file_ase_mips16
|= mips_opts
.mips16
;
7279 file_ase_micromips
|= mips_opts
.micromips
;
7281 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7282 pinfo
= ip
->insn_mo
->pinfo
;
7284 /* Don't raise alarm about `nods' frags as they'll fill in the right
7285 kind of nop in relaxation if required. */
7286 if (mips_opts
.micromips
7288 && !(history
[0].frag
7289 && history
[0].frag
->fr_type
== rs_machine_dependent
7290 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7291 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7292 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7293 && micromips_insn_length (ip
->insn_mo
) != 2)
7294 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7295 && micromips_insn_length (ip
->insn_mo
) != 4)))
7296 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7297 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7299 if (address_expr
== NULL
)
7301 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7302 && reloc_type
[1] == BFD_RELOC_UNUSED
7303 && reloc_type
[2] == BFD_RELOC_UNUSED
7304 && address_expr
->X_op
== O_constant
)
7306 switch (*reloc_type
)
7308 case BFD_RELOC_MIPS_JMP
:
7312 /* Shift is 2, unusually, for microMIPS JALX. */
7313 shift
= (mips_opts
.micromips
7314 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7315 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7316 as_bad (_("jump to misaligned address (0x%lx)"),
7317 (unsigned long) address_expr
->X_add_number
);
7318 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7324 case BFD_RELOC_MIPS16_JMP
:
7325 if ((address_expr
->X_add_number
& 3) != 0)
7326 as_bad (_("jump to misaligned address (0x%lx)"),
7327 (unsigned long) address_expr
->X_add_number
);
7329 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7330 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7331 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7335 case BFD_RELOC_16_PCREL_S2
:
7339 shift
= mips_opts
.micromips
? 1 : 2;
7340 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7341 as_bad (_("branch to misaligned address (0x%lx)"),
7342 (unsigned long) address_expr
->X_add_number
);
7343 if (!mips_relax_branch
)
7345 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7346 & ~((1 << (shift
+ 16)) - 1))
7347 as_bad (_("branch address range overflow (0x%lx)"),
7348 (unsigned long) address_expr
->X_add_number
);
7349 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7355 case BFD_RELOC_MIPS_21_PCREL_S2
:
7360 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7361 as_bad (_("branch to misaligned address (0x%lx)"),
7362 (unsigned long) address_expr
->X_add_number
);
7363 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7364 & ~((1 << (shift
+ 21)) - 1))
7365 as_bad (_("branch address range overflow (0x%lx)"),
7366 (unsigned long) address_expr
->X_add_number
);
7367 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7372 case BFD_RELOC_MIPS_26_PCREL_S2
:
7377 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7378 as_bad (_("branch to misaligned address (0x%lx)"),
7379 (unsigned long) address_expr
->X_add_number
);
7380 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7381 & ~((1 << (shift
+ 26)) - 1))
7382 as_bad (_("branch address range overflow (0x%lx)"),
7383 (unsigned long) address_expr
->X_add_number
);
7384 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7393 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7396 ip
->insn_opcode
|= value
& 0xffff;
7404 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7406 /* There are a lot of optimizations we could do that we don't.
7407 In particular, we do not, in general, reorder instructions.
7408 If you use gcc with optimization, it will reorder
7409 instructions and generally do much more optimization then we
7410 do here; repeating all that work in the assembler would only
7411 benefit hand written assembly code, and does not seem worth
7413 int nops
= (mips_optimize
== 0
7414 ? nops_for_insn (0, history
, NULL
)
7415 : nops_for_insn_or_target (0, history
, ip
));
7419 unsigned long old_frag_offset
;
7422 old_frag
= frag_now
;
7423 old_frag_offset
= frag_now_fix ();
7425 for (i
= 0; i
< nops
; i
++)
7426 add_fixed_insn (NOP_INSN
);
7427 insert_into_history (0, nops
, NOP_INSN
);
7431 listing_prev_line ();
7432 /* We may be at the start of a variant frag. In case we
7433 are, make sure there is enough space for the frag
7434 after the frags created by listing_prev_line. The
7435 argument to frag_grow here must be at least as large
7436 as the argument to all other calls to frag_grow in
7437 this file. We don't have to worry about being in the
7438 middle of a variant frag, because the variants insert
7439 all needed nop instructions themselves. */
7443 mips_move_text_labels ();
7445 #ifndef NO_ECOFF_DEBUGGING
7446 if (ECOFF_DEBUGGING
)
7447 ecoff_fix_loc (old_frag
, old_frag_offset
);
7451 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7455 /* Work out how many nops in prev_nop_frag are needed by IP,
7456 ignoring hazards generated by the first prev_nop_frag_since
7458 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7459 gas_assert (nops
<= prev_nop_frag_holds
);
7461 /* Enforce NOPS as a minimum. */
7462 if (nops
> prev_nop_frag_required
)
7463 prev_nop_frag_required
= nops
;
7465 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7467 /* Settle for the current number of nops. Update the history
7468 accordingly (for the benefit of any future .set reorder code). */
7469 prev_nop_frag
= NULL
;
7470 insert_into_history (prev_nop_frag_since
,
7471 prev_nop_frag_holds
, NOP_INSN
);
7475 /* Allow this instruction to replace one of the nops that was
7476 tentatively added to prev_nop_frag. */
7477 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7478 prev_nop_frag_holds
--;
7479 prev_nop_frag_since
++;
7483 method
= get_append_method (ip
, address_expr
, reloc_type
);
7484 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7486 dwarf2_emit_insn (0);
7487 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7488 so "move" the instruction address accordingly.
7490 Also, it doesn't seem appropriate for the assembler to reorder .loc
7491 entries. If this instruction is a branch that we are going to swap
7492 with the previous instruction, the two instructions should be
7493 treated as a unit, and the debug information for both instructions
7494 should refer to the start of the branch sequence. Using the
7495 current position is certainly wrong when swapping a 32-bit branch
7496 and a 16-bit delay slot, since the current position would then be
7497 in the middle of a branch. */
7498 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7500 relax32
= (mips_relax_branch
7501 /* Don't try branch relaxation within .set nomacro, or within
7502 .set noat if we use $at for PIC computations. If it turns
7503 out that the branch was out-of-range, we'll get an error. */
7504 && !mips_opts
.warn_about_macros
7505 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7506 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7507 as they have no complementing branches. */
7508 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7510 if (!HAVE_CODE_COMPRESSION
7513 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7514 && delayed_branch_p (ip
))
7516 relaxed_branch
= TRUE
;
7517 add_relaxed_insn (ip
, (relaxed_branch_length
7519 uncond_branch_p (ip
) ? -1
7520 : branch_likely_p (ip
) ? 1
7523 (AT
, mips_pic
!= NO_PIC
,
7524 uncond_branch_p (ip
),
7525 branch_likely_p (ip
),
7526 pinfo
& INSN_WRITE_GPR_31
,
7528 address_expr
->X_add_symbol
,
7529 address_expr
->X_add_number
);
7530 *reloc_type
= BFD_RELOC_UNUSED
;
7532 else if (mips_opts
.micromips
7534 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7535 || *reloc_type
> BFD_RELOC_UNUSED
)
7536 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7537 /* Don't try branch relaxation when users specify
7538 16-bit/32-bit instructions. */
7539 && !forced_insn_length
)
7541 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7542 && *reloc_type
> BFD_RELOC_UNUSED
);
7543 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7544 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7545 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7546 int nods
= method
== APPEND_ADD_WITH_NOP
;
7547 int al
= pinfo
& INSN_WRITE_GPR_31
;
7548 int length32
= nods
? 8 : 4;
7550 gas_assert (address_expr
!= NULL
);
7551 gas_assert (!mips_relax
.sequence
);
7553 relaxed_branch
= TRUE
;
7555 method
= APPEND_ADD
;
7557 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7558 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7559 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7561 uncond
, compact
, al
, nods
,
7563 address_expr
->X_add_symbol
,
7564 address_expr
->X_add_number
);
7565 *reloc_type
= BFD_RELOC_UNUSED
;
7567 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7569 bfd_boolean require_unextended
;
7570 bfd_boolean require_extended
;
7574 if (forced_insn_length
!= 0)
7576 require_unextended
= forced_insn_length
== 2;
7577 require_extended
= forced_insn_length
== 4;
7581 require_unextended
= (mips_opts
.noautoextend
7582 && !mips_opcode_32bit_p (ip
->insn_mo
));
7583 require_extended
= 0;
7586 /* We need to set up a variant frag. */
7587 gas_assert (address_expr
!= NULL
);
7588 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7589 symbol created by `make_expr_symbol' may not get a necessary
7590 external relocation produced. */
7591 if (address_expr
->X_op
== O_symbol
)
7593 symbol
= address_expr
->X_add_symbol
;
7594 offset
= address_expr
->X_add_number
;
7598 symbol
= make_expr_symbol (address_expr
);
7599 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7602 add_relaxed_insn (ip
, 12, 0,
7604 (*reloc_type
- BFD_RELOC_UNUSED
,
7605 mips_opts
.ase
& ASE_MIPS16E2
,
7608 mips_opts
.warn_about_macros
,
7609 require_unextended
, require_extended
,
7610 delayed_branch_p (&history
[0]),
7611 history
[0].mips16_absolute_jump_p
),
7614 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7616 if (!delayed_branch_p (ip
))
7617 /* Make sure there is enough room to swap this instruction with
7618 a following jump instruction. */
7620 add_fixed_insn (ip
);
7624 if (mips_opts
.mips16
7625 && mips_opts
.noreorder
7626 && delayed_branch_p (&history
[0]))
7627 as_warn (_("extended instruction in delay slot"));
7629 if (mips_relax
.sequence
)
7631 /* If we've reached the end of this frag, turn it into a variant
7632 frag and record the information for the instructions we've
7634 if (frag_room () < 4)
7635 relax_close_frag ();
7636 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7639 if (mips_relax
.sequence
!= 2)
7641 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7642 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7643 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7644 mips_macro_warning
.insns
[0]++;
7646 if (mips_relax
.sequence
!= 1)
7648 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7649 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7650 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7651 mips_macro_warning
.insns
[1]++;
7654 if (mips_opts
.mips16
)
7657 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7659 add_fixed_insn (ip
);
7662 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7664 bfd_reloc_code_real_type final_type
[3];
7665 reloc_howto_type
*howto0
;
7666 reloc_howto_type
*howto
;
7669 /* Perform any necessary conversion to microMIPS relocations
7670 and find out how many relocations there actually are. */
7671 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7672 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7674 /* In a compound relocation, it is the final (outermost)
7675 operator that determines the relocated field. */
7676 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7681 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7682 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7683 bfd_get_reloc_size (howto
),
7685 howto0
&& howto0
->pc_relative
,
7687 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7688 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7690 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7691 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7692 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7694 /* These relocations can have an addend that won't fit in
7695 4 octets for 64bit assembly. */
7697 && ! howto
->partial_inplace
7698 && (reloc_type
[0] == BFD_RELOC_16
7699 || reloc_type
[0] == BFD_RELOC_32
7700 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7701 || reloc_type
[0] == BFD_RELOC_GPREL16
7702 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7703 || reloc_type
[0] == BFD_RELOC_GPREL32
7704 || reloc_type
[0] == BFD_RELOC_64
7705 || reloc_type
[0] == BFD_RELOC_CTOR
7706 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7707 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7708 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7709 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7710 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7711 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7712 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7713 || hi16_reloc_p (reloc_type
[0])
7714 || lo16_reloc_p (reloc_type
[0])))
7715 ip
->fixp
[0]->fx_no_overflow
= 1;
7717 /* These relocations can have an addend that won't fit in 2 octets. */
7718 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7719 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7720 ip
->fixp
[0]->fx_no_overflow
= 1;
7722 if (mips_relax
.sequence
)
7724 if (mips_relax
.first_fixup
== 0)
7725 mips_relax
.first_fixup
= ip
->fixp
[0];
7727 else if (reloc_needs_lo_p (*reloc_type
))
7729 struct mips_hi_fixup
*hi_fixup
;
7731 /* Reuse the last entry if it already has a matching %lo. */
7732 hi_fixup
= mips_hi_fixup_list
;
7734 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7736 hi_fixup
= XNEW (struct mips_hi_fixup
);
7737 hi_fixup
->next
= mips_hi_fixup_list
;
7738 mips_hi_fixup_list
= hi_fixup
;
7740 hi_fixup
->fixp
= ip
->fixp
[0];
7741 hi_fixup
->seg
= now_seg
;
7744 /* Add fixups for the second and third relocations, if given.
7745 Note that the ABI allows the second relocation to be
7746 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7747 moment we only use RSS_UNDEF, but we could add support
7748 for the others if it ever becomes necessary. */
7749 for (i
= 1; i
< 3; i
++)
7750 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7752 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7753 ip
->fixp
[0]->fx_size
, NULL
, 0,
7754 FALSE
, final_type
[i
]);
7756 /* Use fx_tcbit to mark compound relocs. */
7757 ip
->fixp
[0]->fx_tcbit
= 1;
7758 ip
->fixp
[i
]->fx_tcbit
= 1;
7762 /* Update the register mask information. */
7763 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7764 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7769 insert_into_history (0, 1, ip
);
7772 case APPEND_ADD_WITH_NOP
:
7774 struct mips_cl_insn
*nop
;
7776 insert_into_history (0, 1, ip
);
7777 nop
= get_delay_slot_nop (ip
);
7778 add_fixed_insn (nop
);
7779 insert_into_history (0, 1, nop
);
7780 if (mips_relax
.sequence
)
7781 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7785 case APPEND_ADD_COMPACT
:
7786 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7787 if (mips_opts
.mips16
)
7789 ip
->insn_opcode
|= 0x0080;
7790 find_altered_mips16_opcode (ip
);
7792 /* Convert microMIPS instructions. */
7793 else if (mips_opts
.micromips
)
7796 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7797 ip
->insn_opcode
|= 0x0020;
7799 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7800 ip
->insn_opcode
= 0x40e00000;
7801 /* beqz16->beqzc, bnez16->bnezc */
7802 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7804 unsigned long regno
;
7806 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7807 regno
&= MICROMIPSOP_MASK_MD
;
7808 regno
= micromips_to_32_reg_d_map
[regno
];
7809 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7810 | (regno
<< MICROMIPSOP_SH_RS
)
7811 | 0x40a00000) ^ 0x00400000;
7813 /* beqz->beqzc, bnez->bnezc */
7814 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7815 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7816 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7817 | 0x40a00000) ^ 0x00400000;
7818 /* beq $0->beqzc, bne $0->bnezc */
7819 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7820 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7821 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7822 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7823 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7824 | 0x40a00000) ^ 0x00400000;
7827 find_altered_micromips_opcode (ip
);
7832 insert_into_history (0, 1, ip
);
7837 struct mips_cl_insn delay
= history
[0];
7839 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7841 /* Add the delay slot instruction to the end of the
7842 current frag and shrink the fixed part of the
7843 original frag. If the branch occupies the tail of
7844 the latter, move it backwards to cover the gap. */
7845 delay
.frag
->fr_fix
-= branch_disp
;
7846 if (delay
.frag
== ip
->frag
)
7847 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7848 add_fixed_insn (&delay
);
7852 /* If this is not a relaxed branch and we are in the
7853 same frag, then just swap the instructions. */
7854 move_insn (ip
, delay
.frag
, delay
.where
);
7855 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7859 insert_into_history (0, 1, &delay
);
7864 /* If we have just completed an unconditional branch, clear the history. */
7865 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7866 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7870 mips_no_prev_insn ();
7872 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7873 history
[i
].cleared_p
= 1;
7876 /* We need to emit a label at the end of branch-likely macros. */
7877 if (emit_branch_likely_macro
)
7879 emit_branch_likely_macro
= FALSE
;
7880 micromips_add_label ();
7883 /* We just output an insn, so the next one doesn't have a label. */
7884 mips_clear_insn_labels ();
7887 /* Forget that there was any previous instruction or label.
7888 When BRANCH is true, the branch history is also flushed. */
7891 mips_no_prev_insn (void)
7893 prev_nop_frag
= NULL
;
7894 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7895 mips_clear_insn_labels ();
7898 /* This function must be called before we emit something other than
7899 instructions. It is like mips_no_prev_insn except that it inserts
7900 any NOPS that might be needed by previous instructions. */
7903 mips_emit_delays (void)
7905 if (! mips_opts
.noreorder
)
7907 int nops
= nops_for_insn (0, history
, NULL
);
7911 add_fixed_insn (NOP_INSN
);
7912 mips_move_text_labels ();
7915 mips_no_prev_insn ();
7918 /* Start a (possibly nested) noreorder block. */
7921 start_noreorder (void)
7923 if (mips_opts
.noreorder
== 0)
7928 /* None of the instructions before the .set noreorder can be moved. */
7929 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7930 history
[i
].fixed_p
= 1;
7932 /* Insert any nops that might be needed between the .set noreorder
7933 block and the previous instructions. We will later remove any
7934 nops that turn out not to be needed. */
7935 nops
= nops_for_insn (0, history
, NULL
);
7938 if (mips_optimize
!= 0)
7940 /* Record the frag which holds the nop instructions, so
7941 that we can remove them if we don't need them. */
7942 frag_grow (nops
* NOP_INSN_SIZE
);
7943 prev_nop_frag
= frag_now
;
7944 prev_nop_frag_holds
= nops
;
7945 prev_nop_frag_required
= 0;
7946 prev_nop_frag_since
= 0;
7949 for (; nops
> 0; --nops
)
7950 add_fixed_insn (NOP_INSN
);
7952 /* Move on to a new frag, so that it is safe to simply
7953 decrease the size of prev_nop_frag. */
7954 frag_wane (frag_now
);
7956 mips_move_text_labels ();
7958 mips_mark_labels ();
7959 mips_clear_insn_labels ();
7961 mips_opts
.noreorder
++;
7962 mips_any_noreorder
= 1;
7965 /* End a nested noreorder block. */
7968 end_noreorder (void)
7970 mips_opts
.noreorder
--;
7971 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7973 /* Commit to inserting prev_nop_frag_required nops and go back to
7974 handling nop insertion the .set reorder way. */
7975 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7977 insert_into_history (prev_nop_frag_since
,
7978 prev_nop_frag_required
, NOP_INSN
);
7979 prev_nop_frag
= NULL
;
7983 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7984 higher bits unset. */
7987 normalize_constant_expr (expressionS
*ex
)
7989 if (ex
->X_op
== O_constant
7990 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7991 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7995 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7996 all higher bits unset. */
7999 normalize_address_expr (expressionS
*ex
)
8001 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8002 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8003 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8004 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8008 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8009 Return true if the match was successful.
8011 OPCODE_EXTRA is a value that should be ORed into the opcode
8012 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8013 there are more alternatives after OPCODE and SOFT_MATCH is
8014 as for mips_arg_info. */
8017 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8018 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8019 bfd_boolean lax_match
, bfd_boolean complete_p
)
8022 struct mips_arg_info arg
;
8023 const struct mips_operand
*operand
;
8026 imm_expr
.X_op
= O_absent
;
8027 offset_expr
.X_op
= O_absent
;
8028 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8029 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8030 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8032 create_insn (insn
, opcode
);
8033 /* When no opcode suffix is specified, assume ".xyzw". */
8034 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8035 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8037 insn
->insn_opcode
|= opcode_extra
;
8038 memset (&arg
, 0, sizeof (arg
));
8042 arg
.last_regno
= ILLEGAL_REG
;
8043 arg
.dest_regno
= ILLEGAL_REG
;
8044 arg
.lax_match
= lax_match
;
8045 for (args
= opcode
->args
;; ++args
)
8047 if (arg
.token
->type
== OT_END
)
8049 /* Handle unary instructions in which only one operand is given.
8050 The source is then the same as the destination. */
8051 if (arg
.opnum
== 1 && *args
== ',')
8053 operand
= (mips_opts
.micromips
8054 ? decode_micromips_operand (args
+ 1)
8055 : decode_mips_operand (args
+ 1));
8056 if (operand
&& mips_optional_operand_p (operand
))
8064 /* Treat elided base registers as $0. */
8065 if (strcmp (args
, "(b)") == 0)
8073 /* The register suffix is optional. */
8078 /* Fail the match if there were too few operands. */
8082 /* Successful match. */
8085 clear_insn_error ();
8086 if (arg
.dest_regno
== arg
.last_regno
8087 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8091 (0, _("source and destination must be different"));
8092 else if (arg
.last_regno
== 31)
8094 (0, _("a destination register must be supplied"));
8096 else if (arg
.last_regno
== 31
8097 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8098 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8099 set_insn_error (0, _("the source register must not be $31"));
8100 check_completed_insn (&arg
);
8104 /* Fail the match if the line has too many operands. */
8108 /* Handle characters that need to match exactly. */
8109 if (*args
== '(' || *args
== ')' || *args
== ',')
8111 if (match_char (&arg
, *args
))
8118 if (arg
.token
->type
== OT_DOUBLE_CHAR
8119 && arg
.token
->u
.ch
== *args
)
8127 /* Handle special macro operands. Work out the properties of
8136 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8140 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8149 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8153 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8157 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8163 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8165 imm_expr
.X_op
= O_constant
;
8167 normalize_constant_expr (&imm_expr
);
8171 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8173 /* Assume that the offset has been elided and that what
8174 we saw was a base register. The match will fail later
8175 if that assumption turns out to be wrong. */
8176 offset_expr
.X_op
= O_constant
;
8177 offset_expr
.X_add_number
= 0;
8181 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8183 normalize_address_expr (&offset_expr
);
8188 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8194 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8200 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8206 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8212 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8216 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8220 gas_assert (mips_opts
.micromips
);
8226 if (!forced_insn_length
)
8227 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8229 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8231 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8237 operand
= (mips_opts
.micromips
8238 ? decode_micromips_operand (args
)
8239 : decode_mips_operand (args
));
8243 /* Skip prefixes. */
8244 if (*args
== '+' || *args
== 'm' || *args
== '-')
8247 if (mips_optional_operand_p (operand
)
8249 && (arg
.token
[0].type
!= OT_REG
8250 || arg
.token
[1].type
== OT_END
))
8252 /* Assume that the register has been elided and is the
8253 same as the first operand. */
8258 if (!match_operand (&arg
, operand
))
8263 /* Like match_insn, but for MIPS16. */
8266 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8267 struct mips_operand_token
*tokens
)
8270 const struct mips_operand
*operand
;
8271 const struct mips_operand
*ext_operand
;
8272 bfd_boolean pcrel
= FALSE
;
8273 int required_insn_length
;
8274 struct mips_arg_info arg
;
8277 if (forced_insn_length
)
8278 required_insn_length
= forced_insn_length
;
8279 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8280 required_insn_length
= 2;
8282 required_insn_length
= 0;
8284 create_insn (insn
, opcode
);
8285 imm_expr
.X_op
= O_absent
;
8286 offset_expr
.X_op
= O_absent
;
8287 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8288 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8289 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8292 memset (&arg
, 0, sizeof (arg
));
8296 arg
.last_regno
= ILLEGAL_REG
;
8297 arg
.dest_regno
= ILLEGAL_REG
;
8299 for (args
= opcode
->args
;; ++args
)
8303 if (arg
.token
->type
== OT_END
)
8307 /* Handle unary instructions in which only one operand is given.
8308 The source is then the same as the destination. */
8309 if (arg
.opnum
== 1 && *args
== ',')
8311 operand
= decode_mips16_operand (args
[1], FALSE
);
8312 if (operand
&& mips_optional_operand_p (operand
))
8320 /* Fail the match if there were too few operands. */
8324 /* Successful match. Stuff the immediate value in now, if
8326 clear_insn_error ();
8327 if (opcode
->pinfo
== INSN_MACRO
)
8329 gas_assert (relax_char
== 0 || relax_char
== 'p');
8330 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8333 && offset_expr
.X_op
== O_constant
8335 && calculate_reloc (*offset_reloc
,
8336 offset_expr
.X_add_number
,
8339 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8340 required_insn_length
, &insn
->insn_opcode
);
8341 offset_expr
.X_op
= O_absent
;
8342 *offset_reloc
= BFD_RELOC_UNUSED
;
8344 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8346 if (required_insn_length
== 2)
8347 set_insn_error (0, _("invalid unextended operand value"));
8348 else if (!mips_opcode_32bit_p (opcode
))
8350 forced_insn_length
= 4;
8351 insn
->insn_opcode
|= MIPS16_EXTEND
;
8354 else if (relax_char
)
8355 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8357 check_completed_insn (&arg
);
8361 /* Fail the match if the line has too many operands. */
8365 /* Handle characters that need to match exactly. */
8366 if (*args
== '(' || *args
== ')' || *args
== ',')
8368 if (match_char (&arg
, *args
))
8388 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8390 imm_expr
.X_op
= O_constant
;
8392 normalize_constant_expr (&imm_expr
);
8397 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8401 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8405 if (operand
->type
== OP_PCREL
)
8409 ext_operand
= decode_mips16_operand (c
, TRUE
);
8410 if (operand
!= ext_operand
)
8412 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8414 offset_expr
.X_op
= O_constant
;
8415 offset_expr
.X_add_number
= 0;
8420 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8423 /* '8' is used for SLTI(U) and has traditionally not
8424 been allowed to take relocation operators. */
8425 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8426 && (ext_operand
->size
!= 16 || c
== '8'))
8428 match_not_constant (&arg
);
8432 if (offset_expr
.X_op
== O_big
)
8434 match_out_of_range (&arg
);
8443 if (mips_optional_operand_p (operand
)
8445 && (arg
.token
[0].type
!= OT_REG
8446 || arg
.token
[1].type
== OT_END
))
8448 /* Assume that the register has been elided and is the
8449 same as the first operand. */
8454 if (!match_operand (&arg
, operand
))
8459 /* Record that the current instruction is invalid for the current ISA. */
8462 match_invalid_for_isa (void)
8465 (0, _("opcode not supported on this processor: %s (%s)"),
8466 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8467 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8470 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8471 Return true if a definite match or failure was found, storing any match
8472 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8473 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8474 tried and failed to match under normal conditions and now want to try a
8475 more relaxed match. */
8478 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8479 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8480 int opcode_extra
, bfd_boolean lax_match
)
8482 const struct mips_opcode
*opcode
;
8483 const struct mips_opcode
*invalid_delay_slot
;
8484 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8486 /* Search for a match, ignoring alternatives that don't satisfy the
8487 current ISA or forced_length. */
8488 invalid_delay_slot
= 0;
8489 seen_valid_for_isa
= FALSE
;
8490 seen_valid_for_size
= FALSE
;
8494 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8495 if (is_opcode_valid (opcode
))
8497 seen_valid_for_isa
= TRUE
;
8498 if (is_size_valid (opcode
))
8500 bfd_boolean delay_slot_ok
;
8502 seen_valid_for_size
= TRUE
;
8503 delay_slot_ok
= is_delay_slot_valid (opcode
);
8504 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8505 lax_match
, delay_slot_ok
))
8509 if (!invalid_delay_slot
)
8510 invalid_delay_slot
= opcode
;
8519 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8521 /* If the only matches we found had the wrong length for the delay slot,
8522 pick the first such match. We'll issue an appropriate warning later. */
8523 if (invalid_delay_slot
)
8525 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8531 /* Handle the case where we didn't try to match an instruction because
8532 all the alternatives were incompatible with the current ISA. */
8533 if (!seen_valid_for_isa
)
8535 match_invalid_for_isa ();
8539 /* Handle the case where we didn't try to match an instruction because
8540 all the alternatives were of the wrong size. */
8541 if (!seen_valid_for_size
)
8543 if (mips_opts
.insn32
)
8544 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8547 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8548 8 * forced_insn_length
);
8555 /* Like match_insns, but for MIPS16. */
8558 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8559 struct mips_operand_token
*tokens
)
8561 const struct mips_opcode
*opcode
;
8562 bfd_boolean seen_valid_for_isa
;
8563 bfd_boolean seen_valid_for_size
;
8565 /* Search for a match, ignoring alternatives that don't satisfy the
8566 current ISA. There are no separate entries for extended forms so
8567 we deal with forced_length later. */
8568 seen_valid_for_isa
= FALSE
;
8569 seen_valid_for_size
= FALSE
;
8573 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8574 if (is_opcode_valid_16 (opcode
))
8576 seen_valid_for_isa
= TRUE
;
8577 if (is_size_valid_16 (opcode
))
8579 seen_valid_for_size
= TRUE
;
8580 if (match_mips16_insn (insn
, opcode
, tokens
))
8586 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8587 && strcmp (opcode
->name
, first
->name
) == 0);
8589 /* Handle the case where we didn't try to match an instruction because
8590 all the alternatives were incompatible with the current ISA. */
8591 if (!seen_valid_for_isa
)
8593 match_invalid_for_isa ();
8597 /* Handle the case where we didn't try to match an instruction because
8598 all the alternatives were of the wrong size. */
8599 if (!seen_valid_for_size
)
8601 if (forced_insn_length
== 2)
8603 (0, _("unrecognized unextended version of MIPS16 opcode"));
8606 (0, _("unrecognized extended version of MIPS16 opcode"));
8613 /* Set up global variables for the start of a new macro. */
8618 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8619 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8620 sizeof (mips_macro_warning
.first_insn_sizes
));
8621 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8622 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8623 && delayed_branch_p (&history
[0]));
8625 && history
[0].frag
->fr_type
== rs_machine_dependent
8626 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8627 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8628 mips_macro_warning
.delay_slot_length
= 0;
8630 switch (history
[0].insn_mo
->pinfo2
8631 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8633 case INSN2_BRANCH_DELAY_32BIT
:
8634 mips_macro_warning
.delay_slot_length
= 4;
8636 case INSN2_BRANCH_DELAY_16BIT
:
8637 mips_macro_warning
.delay_slot_length
= 2;
8640 mips_macro_warning
.delay_slot_length
= 0;
8643 mips_macro_warning
.first_frag
= NULL
;
8646 /* Given that a macro is longer than one instruction or of the wrong size,
8647 return the appropriate warning for it. Return null if no warning is
8648 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8649 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8650 and RELAX_NOMACRO. */
8653 macro_warning (relax_substateT subtype
)
8655 if (subtype
& RELAX_DELAY_SLOT
)
8656 return _("macro instruction expanded into multiple instructions"
8657 " in a branch delay slot");
8658 else if (subtype
& RELAX_NOMACRO
)
8659 return _("macro instruction expanded into multiple instructions");
8660 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8661 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8662 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8663 ? _("macro instruction expanded into a wrong size instruction"
8664 " in a 16-bit branch delay slot")
8665 : _("macro instruction expanded into a wrong size instruction"
8666 " in a 32-bit branch delay slot"));
8671 /* Finish up a macro. Emit warnings as appropriate. */
8676 /* Relaxation warning flags. */
8677 relax_substateT subtype
= 0;
8679 /* Check delay slot size requirements. */
8680 if (mips_macro_warning
.delay_slot_length
== 2)
8681 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8682 if (mips_macro_warning
.delay_slot_length
!= 0)
8684 if (mips_macro_warning
.delay_slot_length
8685 != mips_macro_warning
.first_insn_sizes
[0])
8686 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8687 if (mips_macro_warning
.delay_slot_length
8688 != mips_macro_warning
.first_insn_sizes
[1])
8689 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8692 /* Check instruction count requirements. */
8693 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8695 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8696 subtype
|= RELAX_SECOND_LONGER
;
8697 if (mips_opts
.warn_about_macros
)
8698 subtype
|= RELAX_NOMACRO
;
8699 if (mips_macro_warning
.delay_slot_p
)
8700 subtype
|= RELAX_DELAY_SLOT
;
8703 /* If both alternatives fail to fill a delay slot correctly,
8704 emit the warning now. */
8705 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8706 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8711 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8712 | RELAX_DELAY_SLOT_SIZE_FIRST
8713 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8714 msg
= macro_warning (s
);
8716 as_warn ("%s", msg
);
8720 /* If both implementations are longer than 1 instruction, then emit the
8722 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8727 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8728 msg
= macro_warning (s
);
8730 as_warn ("%s", msg
);
8734 /* If any flags still set, then one implementation might need a warning
8735 and the other either will need one of a different kind or none at all.
8736 Pass any remaining flags over to relaxation. */
8737 if (mips_macro_warning
.first_frag
!= NULL
)
8738 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8741 /* Instruction operand formats used in macros that vary between
8742 standard MIPS and microMIPS code. */
8744 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8745 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8746 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8747 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8748 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8749 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8750 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8751 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8753 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8754 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8755 : cop12_fmt[mips_opts.micromips])
8756 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8757 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8758 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8759 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8760 : mem12_fmt[mips_opts.micromips])
8761 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8762 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8763 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8765 /* Read a macro's relocation codes from *ARGS and store them in *R.
8766 The first argument in *ARGS will be either the code for a single
8767 relocation or -1 followed by the three codes that make up a
8768 composite relocation. */
8771 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8775 next
= va_arg (*args
, int);
8777 r
[0] = (bfd_reloc_code_real_type
) next
;
8780 for (i
= 0; i
< 3; i
++)
8781 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8782 /* This function is only used for 16-bit relocation fields.
8783 To make the macro code simpler, treat an unrelocated value
8784 in the same way as BFD_RELOC_LO16. */
8785 if (r
[0] == BFD_RELOC_UNUSED
)
8786 r
[0] = BFD_RELOC_LO16
;
8790 /* Build an instruction created by a macro expansion. This is passed
8791 a pointer to the count of instructions created so far, an
8792 expression, the name of the instruction to build, an operand format
8793 string, and corresponding arguments. */
8796 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8798 const struct mips_opcode
*mo
= NULL
;
8799 bfd_reloc_code_real_type r
[3];
8800 const struct mips_opcode
*amo
;
8801 const struct mips_operand
*operand
;
8802 struct hash_control
*hash
;
8803 struct mips_cl_insn insn
;
8807 va_start (args
, fmt
);
8809 if (mips_opts
.mips16
)
8811 mips16_macro_build (ep
, name
, fmt
, &args
);
8816 r
[0] = BFD_RELOC_UNUSED
;
8817 r
[1] = BFD_RELOC_UNUSED
;
8818 r
[2] = BFD_RELOC_UNUSED
;
8819 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8820 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8822 gas_assert (strcmp (name
, amo
->name
) == 0);
8826 /* Search until we get a match for NAME. It is assumed here that
8827 macros will never generate MDMX, MIPS-3D, or MT instructions.
8828 We try to match an instruction that fulfills the branch delay
8829 slot instruction length requirement (if any) of the previous
8830 instruction. While doing this we record the first instruction
8831 seen that matches all the other conditions and use it anyway
8832 if the requirement cannot be met; we will issue an appropriate
8833 warning later on. */
8834 if (strcmp (fmt
, amo
->args
) == 0
8835 && amo
->pinfo
!= INSN_MACRO
8836 && is_opcode_valid (amo
)
8837 && is_size_valid (amo
))
8839 if (is_delay_slot_valid (amo
))
8849 gas_assert (amo
->name
);
8851 while (strcmp (name
, amo
->name
) == 0);
8854 create_insn (&insn
, mo
);
8867 macro_read_relocs (&args
, r
);
8868 gas_assert (*r
== BFD_RELOC_GPREL16
8869 || *r
== BFD_RELOC_MIPS_HIGHER
8870 || *r
== BFD_RELOC_HI16_S
8871 || *r
== BFD_RELOC_LO16
8872 || *r
== BFD_RELOC_MIPS_GOT_OFST
8873 || (mips_opts
.micromips
8874 && (*r
== BFD_RELOC_16
8875 || *r
== BFD_RELOC_MIPS_GOT16
8876 || *r
== BFD_RELOC_MIPS_CALL16
8877 || *r
== BFD_RELOC_MIPS_GOT_HI16
8878 || *r
== BFD_RELOC_MIPS_GOT_LO16
8879 || *r
== BFD_RELOC_MIPS_CALL_HI16
8880 || *r
== BFD_RELOC_MIPS_CALL_LO16
8881 || *r
== BFD_RELOC_MIPS_SUB
8882 || *r
== BFD_RELOC_MIPS_GOT_PAGE
8883 || *r
== BFD_RELOC_MIPS_HIGHEST
8884 || *r
== BFD_RELOC_MIPS_GOT_DISP
8885 || *r
== BFD_RELOC_MIPS_TLS_GD
8886 || *r
== BFD_RELOC_MIPS_TLS_LDM
8887 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
8888 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
8889 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
8890 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
8891 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
8895 macro_read_relocs (&args
, r
);
8899 macro_read_relocs (&args
, r
);
8900 gas_assert (ep
!= NULL
8901 && (ep
->X_op
== O_constant
8902 || (ep
->X_op
== O_symbol
8903 && (*r
== BFD_RELOC_MIPS_HIGHEST
8904 || *r
== BFD_RELOC_HI16_S
8905 || *r
== BFD_RELOC_HI16
8906 || *r
== BFD_RELOC_GPREL16
8907 || *r
== BFD_RELOC_MIPS_GOT_HI16
8908 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8912 gas_assert (ep
!= NULL
);
8915 * This allows macro() to pass an immediate expression for
8916 * creating short branches without creating a symbol.
8918 * We don't allow branch relaxation for these branches, as
8919 * they should only appear in ".set nomacro" anyway.
8921 if (ep
->X_op
== O_constant
)
8923 /* For microMIPS we always use relocations for branches.
8924 So we should not resolve immediate values. */
8925 gas_assert (!mips_opts
.micromips
);
8927 if ((ep
->X_add_number
& 3) != 0)
8928 as_bad (_("branch to misaligned address (0x%lx)"),
8929 (unsigned long) ep
->X_add_number
);
8930 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8931 as_bad (_("branch address range overflow (0x%lx)"),
8932 (unsigned long) ep
->X_add_number
);
8933 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8937 *r
= BFD_RELOC_16_PCREL_S2
;
8941 gas_assert (ep
!= NULL
);
8942 *r
= BFD_RELOC_MIPS_JMP
;
8946 operand
= (mips_opts
.micromips
8947 ? decode_micromips_operand (fmt
)
8948 : decode_mips_operand (fmt
));
8952 uval
= va_arg (args
, int);
8953 if (operand
->type
== OP_CLO_CLZ_DEST
)
8954 uval
|= (uval
<< 5);
8955 insn_insert_operand (&insn
, operand
, uval
);
8957 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8963 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8965 append_insn (&insn
, ep
, r
, TRUE
);
8969 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8972 struct mips_opcode
*mo
;
8973 struct mips_cl_insn insn
;
8974 const struct mips_operand
*operand
;
8975 bfd_reloc_code_real_type r
[3]
8976 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8978 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8980 gas_assert (strcmp (name
, mo
->name
) == 0);
8982 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8985 gas_assert (mo
->name
);
8986 gas_assert (strcmp (name
, mo
->name
) == 0);
8989 create_insn (&insn
, mo
);
9026 gas_assert (ep
!= NULL
);
9028 if (ep
->X_op
!= O_constant
)
9029 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9030 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9032 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9034 *r
= BFD_RELOC_UNUSED
;
9040 operand
= decode_mips16_operand (c
, FALSE
);
9044 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9049 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9051 append_insn (&insn
, ep
, r
, TRUE
);
9055 * Generate a "jalr" instruction with a relocation hint to the called
9056 * function. This occurs in NewABI PIC code.
9059 macro_build_jalr (expressionS
*ep
, int cprestore
)
9061 static const bfd_reloc_code_real_type jalr_relocs
[2]
9062 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9063 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9067 if (MIPS_JALR_HINT_P (ep
))
9072 if (mips_opts
.micromips
)
9074 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9075 ? "jalr" : "jalrs");
9076 if (MIPS_JALR_HINT_P (ep
)
9078 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9079 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9081 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9084 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9085 if (MIPS_JALR_HINT_P (ep
))
9086 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9090 * Generate a "lui" instruction.
9093 macro_build_lui (expressionS
*ep
, int regnum
)
9095 gas_assert (! mips_opts
.mips16
);
9097 if (ep
->X_op
!= O_constant
)
9099 gas_assert (ep
->X_op
== O_symbol
);
9100 /* _gp_disp is a special case, used from s_cpload.
9101 __gnu_local_gp is used if mips_no_shared. */
9102 gas_assert (mips_pic
== NO_PIC
9104 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9105 || (! mips_in_shared
9106 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9107 "__gnu_local_gp") == 0));
9110 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9113 /* Generate a sequence of instructions to do a load or store from a constant
9114 offset off of a base register (breg) into/from a target register (treg),
9115 using AT if necessary. */
9117 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9118 int treg
, int breg
, int dbl
)
9120 gas_assert (ep
->X_op
== O_constant
);
9122 /* Sign-extending 32-bit constants makes their handling easier. */
9124 normalize_constant_expr (ep
);
9126 /* Right now, this routine can only handle signed 32-bit constants. */
9127 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9128 as_warn (_("operand overflow"));
9130 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9132 /* Signed 16-bit offset will fit in the op. Easy! */
9133 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9137 /* 32-bit offset, need multiple instructions and AT, like:
9138 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9139 addu $tempreg,$tempreg,$breg
9140 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9141 to handle the complete offset. */
9142 macro_build_lui (ep
, AT
);
9143 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9144 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9147 as_bad (_("macro used $at after \".set noat\""));
9152 * Generates code to set the $at register to true (one)
9153 * if reg is less than the immediate expression.
9156 set_at (int reg
, int unsignedp
)
9158 if (imm_expr
.X_add_number
>= -0x8000
9159 && imm_expr
.X_add_number
< 0x8000)
9160 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9161 AT
, reg
, BFD_RELOC_LO16
);
9164 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9165 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9169 /* Count the leading zeroes by performing a binary chop. This is a
9170 bulky bit of source, but performance is a LOT better for the
9171 majority of values than a simple loop to count the bits:
9172 for (lcnt = 0; (lcnt < 32); lcnt++)
9173 if ((v) & (1 << (31 - lcnt)))
9175 However it is not code size friendly, and the gain will drop a bit
9176 on certain cached systems.
9178 #define COUNT_TOP_ZEROES(v) \
9179 (((v) & ~0xffff) == 0 \
9180 ? ((v) & ~0xff) == 0 \
9181 ? ((v) & ~0xf) == 0 \
9182 ? ((v) & ~0x3) == 0 \
9183 ? ((v) & ~0x1) == 0 \
9188 : ((v) & ~0x7) == 0 \
9191 : ((v) & ~0x3f) == 0 \
9192 ? ((v) & ~0x1f) == 0 \
9195 : ((v) & ~0x7f) == 0 \
9198 : ((v) & ~0xfff) == 0 \
9199 ? ((v) & ~0x3ff) == 0 \
9200 ? ((v) & ~0x1ff) == 0 \
9203 : ((v) & ~0x7ff) == 0 \
9206 : ((v) & ~0x3fff) == 0 \
9207 ? ((v) & ~0x1fff) == 0 \
9210 : ((v) & ~0x7fff) == 0 \
9213 : ((v) & ~0xffffff) == 0 \
9214 ? ((v) & ~0xfffff) == 0 \
9215 ? ((v) & ~0x3ffff) == 0 \
9216 ? ((v) & ~0x1ffff) == 0 \
9219 : ((v) & ~0x7ffff) == 0 \
9222 : ((v) & ~0x3fffff) == 0 \
9223 ? ((v) & ~0x1fffff) == 0 \
9226 : ((v) & ~0x7fffff) == 0 \
9229 : ((v) & ~0xfffffff) == 0 \
9230 ? ((v) & ~0x3ffffff) == 0 \
9231 ? ((v) & ~0x1ffffff) == 0 \
9234 : ((v) & ~0x7ffffff) == 0 \
9237 : ((v) & ~0x3fffffff) == 0 \
9238 ? ((v) & ~0x1fffffff) == 0 \
9241 : ((v) & ~0x7fffffff) == 0 \
9246 * This routine generates the least number of instructions necessary to load
9247 * an absolute expression value into a register.
9250 load_register (int reg
, expressionS
*ep
, int dbl
)
9253 expressionS hi32
, lo32
;
9255 if (ep
->X_op
!= O_big
)
9257 gas_assert (ep
->X_op
== O_constant
);
9259 /* Sign-extending 32-bit constants makes their handling easier. */
9261 normalize_constant_expr (ep
);
9263 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9265 /* We can handle 16 bit signed values with an addiu to
9266 $zero. No need to ever use daddiu here, since $zero and
9267 the result are always correct in 32 bit mode. */
9268 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9271 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9273 /* We can handle 16 bit unsigned values with an ori to
9275 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9278 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9280 /* 32 bit values require an lui. */
9281 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9282 if ((ep
->X_add_number
& 0xffff) != 0)
9283 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9288 /* The value is larger than 32 bits. */
9290 if (!dbl
|| GPR_SIZE
== 32)
9294 sprintf_vma (value
, ep
->X_add_number
);
9295 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9296 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9300 if (ep
->X_op
!= O_big
)
9303 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9304 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9305 hi32
.X_add_number
&= 0xffffffff;
9307 lo32
.X_add_number
&= 0xffffffff;
9311 gas_assert (ep
->X_add_number
> 2);
9312 if (ep
->X_add_number
== 3)
9313 generic_bignum
[3] = 0;
9314 else if (ep
->X_add_number
> 4)
9315 as_bad (_("number larger than 64 bits"));
9316 lo32
.X_op
= O_constant
;
9317 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9318 hi32
.X_op
= O_constant
;
9319 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9322 if (hi32
.X_add_number
== 0)
9327 unsigned long hi
, lo
;
9329 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9331 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9333 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9336 if (lo32
.X_add_number
& 0x80000000)
9338 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9339 if (lo32
.X_add_number
& 0xffff)
9340 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9345 /* Check for 16bit shifted constant. We know that hi32 is
9346 non-zero, so start the mask on the first bit of the hi32
9351 unsigned long himask
, lomask
;
9355 himask
= 0xffff >> (32 - shift
);
9356 lomask
= (0xffff << shift
) & 0xffffffff;
9360 himask
= 0xffff << (shift
- 32);
9363 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9364 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9368 tmp
.X_op
= O_constant
;
9370 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9371 | (lo32
.X_add_number
>> shift
));
9373 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9374 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9375 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9376 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9381 while (shift
<= (64 - 16));
9383 /* Find the bit number of the lowest one bit, and store the
9384 shifted value in hi/lo. */
9385 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9386 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9390 while ((lo
& 1) == 0)
9395 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9401 while ((hi
& 1) == 0)
9410 /* Optimize if the shifted value is a (power of 2) - 1. */
9411 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9412 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9414 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9419 /* This instruction will set the register to be all
9421 tmp
.X_op
= O_constant
;
9422 tmp
.X_add_number
= (offsetT
) -1;
9423 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9427 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9428 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9430 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9431 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9436 /* Sign extend hi32 before calling load_register, because we can
9437 generally get better code when we load a sign extended value. */
9438 if ((hi32
.X_add_number
& 0x80000000) != 0)
9439 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9440 load_register (reg
, &hi32
, 0);
9443 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9447 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9455 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9457 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9458 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9464 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9468 mid16
.X_add_number
>>= 16;
9469 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9470 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9473 if ((lo32
.X_add_number
& 0xffff) != 0)
9474 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9478 load_delay_nop (void)
9480 if (!gpr_interlocks
)
9481 macro_build (NULL
, "nop", "");
9484 /* Load an address into a register. */
9487 load_address (int reg
, expressionS
*ep
, int *used_at
)
9489 if (ep
->X_op
!= O_constant
9490 && ep
->X_op
!= O_symbol
)
9492 as_bad (_("expression too complex"));
9493 ep
->X_op
= O_constant
;
9496 if (ep
->X_op
== O_constant
)
9498 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9502 if (mips_pic
== NO_PIC
)
9504 /* If this is a reference to a GP relative symbol, we want
9505 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9507 lui $reg,<sym> (BFD_RELOC_HI16_S)
9508 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9509 If we have an addend, we always use the latter form.
9511 With 64bit address space and a usable $at we want
9512 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9513 lui $at,<sym> (BFD_RELOC_HI16_S)
9514 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9515 daddiu $at,<sym> (BFD_RELOC_LO16)
9519 If $at is already in use, we use a path which is suboptimal
9520 on superscalar processors.
9521 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9522 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9524 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9526 daddiu $reg,<sym> (BFD_RELOC_LO16)
9528 For GP relative symbols in 64bit address space we can use
9529 the same sequence as in 32bit address space. */
9530 if (HAVE_64BIT_SYMBOLS
)
9532 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9533 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9535 relax_start (ep
->X_add_symbol
);
9536 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9537 mips_gp_register
, BFD_RELOC_GPREL16
);
9541 if (*used_at
== 0 && mips_opts
.at
)
9543 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9544 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9545 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9546 BFD_RELOC_MIPS_HIGHER
);
9547 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9548 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9549 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9554 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9555 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9556 BFD_RELOC_MIPS_HIGHER
);
9557 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9558 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9559 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9560 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9563 if (mips_relax
.sequence
)
9568 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9569 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9571 relax_start (ep
->X_add_symbol
);
9572 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9573 mips_gp_register
, BFD_RELOC_GPREL16
);
9576 macro_build_lui (ep
, reg
);
9577 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9578 reg
, reg
, BFD_RELOC_LO16
);
9579 if (mips_relax
.sequence
)
9583 else if (!mips_big_got
)
9587 /* If this is a reference to an external symbol, we want
9588 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9590 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9592 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9593 If there is a constant, it must be added in after.
9595 If we have NewABI, we want
9596 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9597 unless we're referencing a global symbol with a non-zero
9598 offset, in which case cst must be added separately. */
9601 if (ep
->X_add_number
)
9603 ex
.X_add_number
= ep
->X_add_number
;
9604 ep
->X_add_number
= 0;
9605 relax_start (ep
->X_add_symbol
);
9606 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9607 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9608 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9609 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9610 ex
.X_op
= O_constant
;
9611 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9612 reg
, reg
, BFD_RELOC_LO16
);
9613 ep
->X_add_number
= ex
.X_add_number
;
9616 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9617 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9618 if (mips_relax
.sequence
)
9623 ex
.X_add_number
= ep
->X_add_number
;
9624 ep
->X_add_number
= 0;
9625 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9626 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9628 relax_start (ep
->X_add_symbol
);
9630 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9634 if (ex
.X_add_number
!= 0)
9636 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9637 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9638 ex
.X_op
= O_constant
;
9639 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9640 reg
, reg
, BFD_RELOC_LO16
);
9644 else if (mips_big_got
)
9648 /* This is the large GOT case. If this is a reference to an
9649 external symbol, we want
9650 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9652 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9654 Otherwise, for a reference to a local symbol in old ABI, we want
9655 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9657 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9658 If there is a constant, it must be added in after.
9660 In the NewABI, for local symbols, with or without offsets, we want:
9661 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9662 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9666 ex
.X_add_number
= ep
->X_add_number
;
9667 ep
->X_add_number
= 0;
9668 relax_start (ep
->X_add_symbol
);
9669 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9670 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9671 reg
, reg
, mips_gp_register
);
9672 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9673 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9674 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9675 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9676 else if (ex
.X_add_number
)
9678 ex
.X_op
= O_constant
;
9679 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9683 ep
->X_add_number
= ex
.X_add_number
;
9685 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9686 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9687 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9688 BFD_RELOC_MIPS_GOT_OFST
);
9693 ex
.X_add_number
= ep
->X_add_number
;
9694 ep
->X_add_number
= 0;
9695 relax_start (ep
->X_add_symbol
);
9696 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9697 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9698 reg
, reg
, mips_gp_register
);
9699 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9700 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9702 if (reg_needs_delay (mips_gp_register
))
9704 /* We need a nop before loading from $gp. This special
9705 check is required because the lui which starts the main
9706 instruction stream does not refer to $gp, and so will not
9707 insert the nop which may be required. */
9708 macro_build (NULL
, "nop", "");
9710 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9711 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9713 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9717 if (ex
.X_add_number
!= 0)
9719 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9720 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9721 ex
.X_op
= O_constant
;
9722 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9730 if (!mips_opts
.at
&& *used_at
== 1)
9731 as_bad (_("macro used $at after \".set noat\""));
9734 /* Move the contents of register SOURCE into register DEST. */
9737 move_register (int dest
, int source
)
9739 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9740 instruction specifically requires a 32-bit one. */
9741 if (mips_opts
.micromips
9742 && !mips_opts
.insn32
9743 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9744 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9746 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9749 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9750 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9751 The two alternatives are:
9753 Global symbol Local symbol
9754 ------------- ------------
9755 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9757 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9759 load_got_offset emits the first instruction and add_got_offset
9760 emits the second for a 16-bit offset or add_got_offset_hilo emits
9761 a sequence to add a 32-bit offset using a scratch register. */
9764 load_got_offset (int dest
, expressionS
*local
)
9769 global
.X_add_number
= 0;
9771 relax_start (local
->X_add_symbol
);
9772 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9773 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9775 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9776 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9781 add_got_offset (int dest
, expressionS
*local
)
9785 global
.X_op
= O_constant
;
9786 global
.X_op_symbol
= NULL
;
9787 global
.X_add_symbol
= NULL
;
9788 global
.X_add_number
= local
->X_add_number
;
9790 relax_start (local
->X_add_symbol
);
9791 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9792 dest
, dest
, BFD_RELOC_LO16
);
9794 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9799 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9802 int hold_mips_optimize
;
9804 global
.X_op
= O_constant
;
9805 global
.X_op_symbol
= NULL
;
9806 global
.X_add_symbol
= NULL
;
9807 global
.X_add_number
= local
->X_add_number
;
9809 relax_start (local
->X_add_symbol
);
9810 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9812 /* Set mips_optimize around the lui instruction to avoid
9813 inserting an unnecessary nop after the lw. */
9814 hold_mips_optimize
= mips_optimize
;
9816 macro_build_lui (&global
, tmp
);
9817 mips_optimize
= hold_mips_optimize
;
9818 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9821 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9824 /* Emit a sequence of instructions to emulate a branch likely operation.
9825 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9826 is its complementing branch with the original condition negated.
9827 CALL is set if the original branch specified the link operation.
9828 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9830 Code like this is produced in the noreorder mode:
9835 delay slot (executed only if branch taken)
9843 delay slot (executed only if branch taken)
9846 In the reorder mode the delay slot would be filled with a nop anyway,
9847 so code produced is simply:
9852 This function is used when producing code for the microMIPS ASE that
9853 does not implement branch likely instructions in hardware. */
9856 macro_build_branch_likely (const char *br
, const char *brneg
,
9857 int call
, expressionS
*ep
, const char *fmt
,
9858 unsigned int sreg
, unsigned int treg
)
9860 int noreorder
= mips_opts
.noreorder
;
9863 gas_assert (mips_opts
.micromips
);
9867 micromips_label_expr (&expr1
);
9868 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9869 macro_build (NULL
, "nop", "");
9870 macro_build (ep
, call
? "bal" : "b", "p");
9872 /* Set to true so that append_insn adds a label. */
9873 emit_branch_likely_macro
= TRUE
;
9877 macro_build (ep
, br
, fmt
, sreg
, treg
);
9878 macro_build (NULL
, "nop", "");
9883 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9884 the condition code tested. EP specifies the branch target. */
9887 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9914 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9917 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9918 the register tested. EP specifies the branch target. */
9921 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9923 const char *brneg
= NULL
;
9933 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9937 gas_assert (mips_opts
.micromips
);
9938 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9946 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9953 br
= mips_opts
.micromips
? "blez" : "blezl";
9960 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9964 gas_assert (mips_opts
.micromips
);
9965 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9972 if (mips_opts
.micromips
&& brneg
)
9973 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9975 macro_build (ep
, br
, "s,p", sreg
);
9978 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9979 TREG as the registers tested. EP specifies the branch target. */
9982 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9983 unsigned int sreg
, unsigned int treg
)
9985 const char *brneg
= NULL
;
9997 br
= mips_opts
.micromips
? "beq" : "beql";
10006 br
= mips_opts
.micromips
? "bne" : "bnel";
10012 if (mips_opts
.micromips
&& brneg
)
10013 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10015 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10018 /* Return the high part that should be loaded in order to make the low
10019 part of VALUE accessible using an offset of OFFBITS bits. */
10022 offset_high_part (offsetT value
, unsigned int offbits
)
10029 bias
= 1 << (offbits
- 1);
10030 low_mask
= bias
* 2 - 1;
10031 return (value
+ bias
) & ~low_mask
;
10034 /* Return true if the value stored in offset_expr and offset_reloc
10035 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10036 amount that the caller wants to add without inducing overflow
10037 and ALIGN is the known alignment of the value in bytes. */
10040 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10044 /* Accept any relocation operator if overflow isn't a concern. */
10045 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10048 /* These relocations are guaranteed not to overflow in correct links. */
10049 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10050 || gprel16_reloc_p (*offset_reloc
))
10053 if (offset_expr
.X_op
== O_constant
10054 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10055 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10062 * This routine implements the seemingly endless macro or synthesized
10063 * instructions and addressing modes in the mips assembly language. Many
10064 * of these macros are simple and are similar to each other. These could
10065 * probably be handled by some kind of table or grammar approach instead of
10066 * this verbose method. Others are not simple macros but are more like
10067 * optimizing code generation.
10068 * One interesting optimization is when several store macros appear
10069 * consecutively that would load AT with the upper half of the same address.
10070 * The ensuing load upper instructions are omitted. This implies some kind
10071 * of global optimization. We currently only optimize within a single macro.
10072 * For many of the load and store macros if the address is specified as a
10073 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10074 * first load register 'at' with zero and use it as the base register. The
10075 * mips assembler simply uses register $zero. Just one tiny optimization
10079 macro (struct mips_cl_insn
*ip
, char *str
)
10081 const struct mips_operand_array
*operands
;
10082 unsigned int breg
, i
;
10083 unsigned int tempreg
;
10086 expressionS label_expr
;
10101 bfd_boolean large_offset
;
10103 int hold_mips_optimize
;
10104 unsigned int align
;
10105 unsigned int op
[MAX_OPERANDS
];
10107 gas_assert (! mips_opts
.mips16
);
10109 operands
= insn_operands (ip
);
10110 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10111 if (operands
->operand
[i
])
10112 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10116 mask
= ip
->insn_mo
->mask
;
10118 label_expr
.X_op
= O_constant
;
10119 label_expr
.X_op_symbol
= NULL
;
10120 label_expr
.X_add_symbol
= NULL
;
10121 label_expr
.X_add_number
= 0;
10123 expr1
.X_op
= O_constant
;
10124 expr1
.X_op_symbol
= NULL
;
10125 expr1
.X_add_symbol
= NULL
;
10126 expr1
.X_add_number
= 1;
10133 /* Fall through. */
10141 start_noreorder ();
10143 if (mips_opts
.micromips
)
10144 micromips_label_expr (&label_expr
);
10146 label_expr
.X_add_number
= 8;
10147 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10148 if (op
[0] == op
[1])
10149 macro_build (NULL
, "nop", "");
10151 move_register (op
[0], op
[1]);
10152 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10153 if (mips_opts
.micromips
)
10154 micromips_add_label ();
10171 if (!mips_opts
.micromips
)
10173 if (imm_expr
.X_add_number
>= -0x200
10174 && imm_expr
.X_add_number
< 0x200)
10176 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10177 (int) imm_expr
.X_add_number
);
10186 if (imm_expr
.X_add_number
>= -0x8000
10187 && imm_expr
.X_add_number
< 0x8000)
10189 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10194 load_register (AT
, &imm_expr
, dbl
);
10195 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10214 if (imm_expr
.X_add_number
>= 0
10215 && imm_expr
.X_add_number
< 0x10000)
10217 if (mask
!= M_NOR_I
)
10218 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10221 macro_build (&imm_expr
, "ori", "t,r,i",
10222 op
[0], op
[1], BFD_RELOC_LO16
);
10223 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10229 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10230 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10234 switch (imm_expr
.X_add_number
)
10237 macro_build (NULL
, "nop", "");
10240 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10244 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10245 (int) imm_expr
.X_add_number
);
10248 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10249 (unsigned long) imm_expr
.X_add_number
);
10258 gas_assert (mips_opts
.micromips
);
10259 macro_build_branch_ccl (mask
, &offset_expr
,
10260 EXTRACT_OPERAND (1, BCC
, *ip
));
10267 if (imm_expr
.X_add_number
== 0)
10273 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10275 /* Fall through. */
10278 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10283 /* Fall through. */
10286 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10287 else if (op
[0] == 0)
10288 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10292 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10293 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10294 &offset_expr
, AT
, ZERO
);
10304 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10309 /* Fall through. */
10311 /* Check for > max integer. */
10312 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10315 /* Result is always false. */
10317 macro_build (NULL
, "nop", "");
10319 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10322 ++imm_expr
.X_add_number
;
10326 if (mask
== M_BGEL_I
)
10328 if (imm_expr
.X_add_number
== 0)
10330 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10331 &offset_expr
, op
[0]);
10334 if (imm_expr
.X_add_number
== 1)
10336 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10337 &offset_expr
, op
[0]);
10340 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10343 /* result is always true */
10344 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10345 macro_build (&offset_expr
, "b", "p");
10350 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10351 &offset_expr
, AT
, ZERO
);
10356 /* Fall through. */
10360 else if (op
[0] == 0)
10361 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10362 &offset_expr
, ZERO
, op
[1]);
10366 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10367 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10368 &offset_expr
, AT
, ZERO
);
10374 /* Fall through. */
10378 && imm_expr
.X_add_number
== -1))
10380 ++imm_expr
.X_add_number
;
10384 if (mask
== M_BGEUL_I
)
10386 if (imm_expr
.X_add_number
== 0)
10388 else if (imm_expr
.X_add_number
== 1)
10389 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10390 &offset_expr
, op
[0], ZERO
);
10395 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10396 &offset_expr
, AT
, ZERO
);
10402 /* Fall through. */
10405 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10406 else if (op
[0] == 0)
10407 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10411 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10412 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10413 &offset_expr
, AT
, ZERO
);
10419 /* Fall through. */
10422 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10423 &offset_expr
, op
[0], ZERO
);
10424 else if (op
[0] == 0)
10429 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10430 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10431 &offset_expr
, AT
, ZERO
);
10437 /* Fall through. */
10440 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10441 else if (op
[0] == 0)
10442 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10446 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10447 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10448 &offset_expr
, AT
, ZERO
);
10454 /* Fall through. */
10456 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10458 ++imm_expr
.X_add_number
;
10462 if (mask
== M_BLTL_I
)
10464 if (imm_expr
.X_add_number
== 0)
10465 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10466 else if (imm_expr
.X_add_number
== 1)
10467 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10472 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10473 &offset_expr
, AT
, ZERO
);
10479 /* Fall through. */
10482 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10483 &offset_expr
, op
[0], ZERO
);
10484 else if (op
[0] == 0)
10489 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10490 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10491 &offset_expr
, AT
, ZERO
);
10497 /* Fall through. */
10501 && imm_expr
.X_add_number
== -1))
10503 ++imm_expr
.X_add_number
;
10507 if (mask
== M_BLTUL_I
)
10509 if (imm_expr
.X_add_number
== 0)
10511 else if (imm_expr
.X_add_number
== 1)
10512 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10513 &offset_expr
, op
[0], ZERO
);
10518 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10519 &offset_expr
, AT
, ZERO
);
10525 /* Fall through. */
10528 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10529 else if (op
[0] == 0)
10530 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10534 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10535 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10536 &offset_expr
, AT
, ZERO
);
10542 /* Fall through. */
10546 else if (op
[0] == 0)
10547 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10548 &offset_expr
, ZERO
, op
[1]);
10552 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10553 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10554 &offset_expr
, AT
, ZERO
);
10560 /* Fall through. */
10566 /* Fall through. */
10572 as_warn (_("divide by zero"));
10574 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10576 macro_build (NULL
, "break", BRK_FMT
, 7);
10580 start_noreorder ();
10583 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10584 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10588 if (mips_opts
.micromips
)
10589 micromips_label_expr (&label_expr
);
10591 label_expr
.X_add_number
= 8;
10592 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10593 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10594 macro_build (NULL
, "break", BRK_FMT
, 7);
10595 if (mips_opts
.micromips
)
10596 micromips_add_label ();
10598 expr1
.X_add_number
= -1;
10600 load_register (AT
, &expr1
, dbl
);
10601 if (mips_opts
.micromips
)
10602 micromips_label_expr (&label_expr
);
10604 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10605 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10608 expr1
.X_add_number
= 1;
10609 load_register (AT
, &expr1
, dbl
);
10610 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10614 expr1
.X_add_number
= 0x80000000;
10615 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10619 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10620 /* We want to close the noreorder block as soon as possible, so
10621 that later insns are available for delay slot filling. */
10626 if (mips_opts
.micromips
)
10627 micromips_label_expr (&label_expr
);
10629 label_expr
.X_add_number
= 8;
10630 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10631 macro_build (NULL
, "nop", "");
10633 /* We want to close the noreorder block as soon as possible, so
10634 that later insns are available for delay slot filling. */
10637 macro_build (NULL
, "break", BRK_FMT
, 6);
10639 if (mips_opts
.micromips
)
10640 micromips_add_label ();
10641 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10680 if (imm_expr
.X_add_number
== 0)
10682 as_warn (_("divide by zero"));
10684 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10686 macro_build (NULL
, "break", BRK_FMT
, 7);
10689 if (imm_expr
.X_add_number
== 1)
10691 if (strcmp (s2
, "mflo") == 0)
10692 move_register (op
[0], op
[1]);
10694 move_register (op
[0], ZERO
);
10697 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10699 if (strcmp (s2
, "mflo") == 0)
10700 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10702 move_register (op
[0], ZERO
);
10707 load_register (AT
, &imm_expr
, dbl
);
10708 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10709 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10728 start_noreorder ();
10731 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10732 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10733 /* We want to close the noreorder block as soon as possible, so
10734 that later insns are available for delay slot filling. */
10739 if (mips_opts
.micromips
)
10740 micromips_label_expr (&label_expr
);
10742 label_expr
.X_add_number
= 8;
10743 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10744 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10746 /* We want to close the noreorder block as soon as possible, so
10747 that later insns are available for delay slot filling. */
10749 macro_build (NULL
, "break", BRK_FMT
, 7);
10750 if (mips_opts
.micromips
)
10751 micromips_add_label ();
10753 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10758 /* Fall through. */
10764 /* Fall through. */
10767 /* Load the address of a symbol into a register. If breg is not
10768 zero, we then add a base register to it. */
10771 if (dbl
&& GPR_SIZE
== 32)
10772 as_warn (_("dla used to load 32-bit register; recommend using la "
10775 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10776 as_warn (_("la used to load 64-bit address; recommend using dla "
10779 if (small_offset_p (0, align
, 16))
10781 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10782 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10786 if (mips_opts
.at
&& (op
[0] == breg
))
10794 if (offset_expr
.X_op
!= O_symbol
10795 && offset_expr
.X_op
!= O_constant
)
10797 as_bad (_("expression too complex"));
10798 offset_expr
.X_op
= O_constant
;
10801 if (offset_expr
.X_op
== O_constant
)
10802 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10803 else if (mips_pic
== NO_PIC
)
10805 /* If this is a reference to a GP relative symbol, we want
10806 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10808 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10809 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10810 If we have a constant, we need two instructions anyhow,
10811 so we may as well always use the latter form.
10813 With 64bit address space and a usable $at we want
10814 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10815 lui $at,<sym> (BFD_RELOC_HI16_S)
10816 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10817 daddiu $at,<sym> (BFD_RELOC_LO16)
10819 daddu $tempreg,$tempreg,$at
10821 If $at is already in use, we use a path which is suboptimal
10822 on superscalar processors.
10823 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10824 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10826 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10828 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10830 For GP relative symbols in 64bit address space we can use
10831 the same sequence as in 32bit address space. */
10832 if (HAVE_64BIT_SYMBOLS
)
10834 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10835 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10837 relax_start (offset_expr
.X_add_symbol
);
10838 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10839 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10843 if (used_at
== 0 && mips_opts
.at
)
10845 macro_build (&offset_expr
, "lui", LUI_FMT
,
10846 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10847 macro_build (&offset_expr
, "lui", LUI_FMT
,
10848 AT
, BFD_RELOC_HI16_S
);
10849 macro_build (&offset_expr
, "daddiu", "t,r,j",
10850 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10851 macro_build (&offset_expr
, "daddiu", "t,r,j",
10852 AT
, AT
, BFD_RELOC_LO16
);
10853 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10854 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10859 macro_build (&offset_expr
, "lui", LUI_FMT
,
10860 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10861 macro_build (&offset_expr
, "daddiu", "t,r,j",
10862 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10863 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10864 macro_build (&offset_expr
, "daddiu", "t,r,j",
10865 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10866 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10867 macro_build (&offset_expr
, "daddiu", "t,r,j",
10868 tempreg
, tempreg
, BFD_RELOC_LO16
);
10871 if (mips_relax
.sequence
)
10876 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10877 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10879 relax_start (offset_expr
.X_add_symbol
);
10880 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10881 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10884 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10885 as_bad (_("offset too large"));
10886 macro_build_lui (&offset_expr
, tempreg
);
10887 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10888 tempreg
, tempreg
, BFD_RELOC_LO16
);
10889 if (mips_relax
.sequence
)
10893 else if (!mips_big_got
&& !HAVE_NEWABI
)
10895 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10897 /* If this is a reference to an external symbol, and there
10898 is no constant, we want
10899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10900 or for lca or if tempreg is PIC_CALL_REG
10901 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10902 For a local symbol, we want
10903 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10905 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10907 If we have a small constant, and this is a reference to
10908 an external symbol, we want
10909 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10911 addiu $tempreg,$tempreg,<constant>
10912 For a local symbol, we want the same instruction
10913 sequence, but we output a BFD_RELOC_LO16 reloc on the
10916 If we have a large constant, and this is a reference to
10917 an external symbol, we want
10918 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10919 lui $at,<hiconstant>
10920 addiu $at,$at,<loconstant>
10921 addu $tempreg,$tempreg,$at
10922 For a local symbol, we want the same instruction
10923 sequence, but we output a BFD_RELOC_LO16 reloc on the
10927 if (offset_expr
.X_add_number
== 0)
10929 if (mips_pic
== SVR4_PIC
10931 && (call
|| tempreg
== PIC_CALL_REG
))
10932 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10934 relax_start (offset_expr
.X_add_symbol
);
10935 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10936 lw_reloc_type
, mips_gp_register
);
10939 /* We're going to put in an addu instruction using
10940 tempreg, so we may as well insert the nop right
10945 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10946 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10948 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10949 tempreg
, tempreg
, BFD_RELOC_LO16
);
10951 /* FIXME: If breg == 0, and the next instruction uses
10952 $tempreg, then if this variant case is used an extra
10953 nop will be generated. */
10955 else if (offset_expr
.X_add_number
>= -0x8000
10956 && offset_expr
.X_add_number
< 0x8000)
10958 load_got_offset (tempreg
, &offset_expr
);
10960 add_got_offset (tempreg
, &offset_expr
);
10964 expr1
.X_add_number
= offset_expr
.X_add_number
;
10965 offset_expr
.X_add_number
=
10966 SEXT_16BIT (offset_expr
.X_add_number
);
10967 load_got_offset (tempreg
, &offset_expr
);
10968 offset_expr
.X_add_number
= expr1
.X_add_number
;
10969 /* If we are going to add in a base register, and the
10970 target register and the base register are the same,
10971 then we are using AT as a temporary register. Since
10972 we want to load the constant into AT, we add our
10973 current AT (from the global offset table) and the
10974 register into the register now, and pretend we were
10975 not using a base register. */
10979 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10984 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10988 else if (!mips_big_got
&& HAVE_NEWABI
)
10990 int add_breg_early
= 0;
10992 /* If this is a reference to an external, and there is no
10993 constant, or local symbol (*), with or without a
10995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10996 or for lca or if tempreg is PIC_CALL_REG
10997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10999 If we have a small constant, and this is a reference to
11000 an external symbol, we want
11001 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11002 addiu $tempreg,$tempreg,<constant>
11004 If we have a large constant, and this is a reference to
11005 an external symbol, we want
11006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11007 lui $at,<hiconstant>
11008 addiu $at,$at,<loconstant>
11009 addu $tempreg,$tempreg,$at
11011 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11012 local symbols, even though it introduces an additional
11015 if (offset_expr
.X_add_number
)
11017 expr1
.X_add_number
= offset_expr
.X_add_number
;
11018 offset_expr
.X_add_number
= 0;
11020 relax_start (offset_expr
.X_add_symbol
);
11021 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11022 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11024 if (expr1
.X_add_number
>= -0x8000
11025 && expr1
.X_add_number
< 0x8000)
11027 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11028 tempreg
, tempreg
, BFD_RELOC_LO16
);
11030 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11034 /* If we are going to add in a base register, and the
11035 target register and the base register are the same,
11036 then we are using AT as a temporary register. Since
11037 we want to load the constant into AT, we add our
11038 current AT (from the global offset table) and the
11039 register into the register now, and pretend we were
11040 not using a base register. */
11045 gas_assert (tempreg
== AT
);
11046 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11049 add_breg_early
= 1;
11052 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11053 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11059 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11062 offset_expr
.X_add_number
= expr1
.X_add_number
;
11064 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11065 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11066 if (add_breg_early
)
11068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11069 op
[0], tempreg
, breg
);
11075 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11077 relax_start (offset_expr
.X_add_symbol
);
11078 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11079 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11081 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11082 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11087 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11088 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11091 else if (mips_big_got
&& !HAVE_NEWABI
)
11094 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11095 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11096 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11098 /* This is the large GOT case. If this is a reference to an
11099 external symbol, and there is no constant, we want
11100 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11101 addu $tempreg,$tempreg,$gp
11102 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11103 or for lca or if tempreg is PIC_CALL_REG
11104 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11105 addu $tempreg,$tempreg,$gp
11106 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11107 For a local symbol, we want
11108 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11110 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11112 If we have a small constant, and this is a reference to
11113 an external symbol, we want
11114 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11115 addu $tempreg,$tempreg,$gp
11116 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11118 addiu $tempreg,$tempreg,<constant>
11119 For a local symbol, we want
11120 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11122 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11124 If we have a large constant, and this is a reference to
11125 an external symbol, we want
11126 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11127 addu $tempreg,$tempreg,$gp
11128 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11129 lui $at,<hiconstant>
11130 addiu $at,$at,<loconstant>
11131 addu $tempreg,$tempreg,$at
11132 For a local symbol, we want
11133 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11134 lui $at,<hiconstant>
11135 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11136 addu $tempreg,$tempreg,$at
11139 expr1
.X_add_number
= offset_expr
.X_add_number
;
11140 offset_expr
.X_add_number
= 0;
11141 relax_start (offset_expr
.X_add_symbol
);
11142 gpdelay
= reg_needs_delay (mips_gp_register
);
11143 if (expr1
.X_add_number
== 0 && breg
== 0
11144 && (call
|| tempreg
== PIC_CALL_REG
))
11146 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11147 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11149 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11150 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11151 tempreg
, tempreg
, mips_gp_register
);
11152 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11153 tempreg
, lw_reloc_type
, tempreg
);
11154 if (expr1
.X_add_number
== 0)
11158 /* We're going to put in an addu instruction using
11159 tempreg, so we may as well insert the nop right
11164 else if (expr1
.X_add_number
>= -0x8000
11165 && expr1
.X_add_number
< 0x8000)
11168 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11169 tempreg
, tempreg
, BFD_RELOC_LO16
);
11175 /* If we are going to add in a base register, and the
11176 target register and the base register are the same,
11177 then we are using AT as a temporary register. Since
11178 we want to load the constant into AT, we add our
11179 current AT (from the global offset table) and the
11180 register into the register now, and pretend we were
11181 not using a base register. */
11186 gas_assert (tempreg
== AT
);
11188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11193 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11194 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11198 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11203 /* This is needed because this instruction uses $gp, but
11204 the first instruction on the main stream does not. */
11205 macro_build (NULL
, "nop", "");
11208 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11209 local_reloc_type
, mips_gp_register
);
11210 if (expr1
.X_add_number
>= -0x8000
11211 && expr1
.X_add_number
< 0x8000)
11214 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11215 tempreg
, tempreg
, BFD_RELOC_LO16
);
11216 /* FIXME: If add_number is 0, and there was no base
11217 register, the external symbol case ended with a load,
11218 so if the symbol turns out to not be external, and
11219 the next instruction uses tempreg, an unnecessary nop
11220 will be inserted. */
11226 /* We must add in the base register now, as in the
11227 external symbol case. */
11228 gas_assert (tempreg
== AT
);
11230 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11233 /* We set breg to 0 because we have arranged to add
11234 it in in both cases. */
11238 macro_build_lui (&expr1
, AT
);
11239 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11240 AT
, AT
, BFD_RELOC_LO16
);
11241 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11242 tempreg
, tempreg
, AT
);
11247 else if (mips_big_got
&& HAVE_NEWABI
)
11249 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11250 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11251 int add_breg_early
= 0;
11253 /* This is the large GOT case. If this is a reference to an
11254 external symbol, and there is no constant, we want
11255 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11256 add $tempreg,$tempreg,$gp
11257 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11258 or for lca or if tempreg is PIC_CALL_REG
11259 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11260 add $tempreg,$tempreg,$gp
11261 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11263 If we have a small constant, and this is a reference to
11264 an external symbol, we want
11265 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11266 add $tempreg,$tempreg,$gp
11267 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11268 addi $tempreg,$tempreg,<constant>
11270 If we have a large constant, and this is a reference to
11271 an external symbol, we want
11272 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11273 addu $tempreg,$tempreg,$gp
11274 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11275 lui $at,<hiconstant>
11276 addi $at,$at,<loconstant>
11277 add $tempreg,$tempreg,$at
11279 If we have NewABI, and we know it's a local symbol, we want
11280 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11281 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11282 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11284 relax_start (offset_expr
.X_add_symbol
);
11286 expr1
.X_add_number
= offset_expr
.X_add_number
;
11287 offset_expr
.X_add_number
= 0;
11289 if (expr1
.X_add_number
== 0 && breg
== 0
11290 && (call
|| tempreg
== PIC_CALL_REG
))
11292 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11293 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11295 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11296 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11297 tempreg
, tempreg
, mips_gp_register
);
11298 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11299 tempreg
, lw_reloc_type
, tempreg
);
11301 if (expr1
.X_add_number
== 0)
11303 else if (expr1
.X_add_number
>= -0x8000
11304 && expr1
.X_add_number
< 0x8000)
11306 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11307 tempreg
, tempreg
, BFD_RELOC_LO16
);
11309 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11313 /* If we are going to add in a base register, and the
11314 target register and the base register are the same,
11315 then we are using AT as a temporary register. Since
11316 we want to load the constant into AT, we add our
11317 current AT (from the global offset table) and the
11318 register into the register now, and pretend we were
11319 not using a base register. */
11324 gas_assert (tempreg
== AT
);
11325 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11328 add_breg_early
= 1;
11331 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11332 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11337 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11340 offset_expr
.X_add_number
= expr1
.X_add_number
;
11341 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11342 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11343 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11344 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11345 if (add_breg_early
)
11347 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11348 op
[0], tempreg
, breg
);
11358 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11362 gas_assert (!mips_opts
.micromips
);
11363 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11367 gas_assert (!mips_opts
.micromips
);
11368 macro_build (NULL
, "c2", "C", 0x02);
11372 gas_assert (!mips_opts
.micromips
);
11373 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11377 gas_assert (!mips_opts
.micromips
);
11378 macro_build (NULL
, "c2", "C", 3);
11382 gas_assert (!mips_opts
.micromips
);
11383 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11387 /* The j instruction may not be used in PIC code, since it
11388 requires an absolute address. We convert it to a b
11390 if (mips_pic
== NO_PIC
)
11391 macro_build (&offset_expr
, "j", "a");
11393 macro_build (&offset_expr
, "b", "p");
11396 /* The jal instructions must be handled as macros because when
11397 generating PIC code they expand to multi-instruction
11398 sequences. Normally they are simple instructions. */
11402 /* Fall through. */
11404 gas_assert (mips_opts
.micromips
);
11405 if (mips_opts
.insn32
)
11407 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11415 /* Fall through. */
11418 if (mips_pic
== NO_PIC
)
11420 s
= jals
? "jalrs" : "jalr";
11421 if (mips_opts
.micromips
11422 && !mips_opts
.insn32
11424 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11425 macro_build (NULL
, s
, "mj", op
[1]);
11427 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11431 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11432 && mips_cprestore_offset
>= 0);
11434 if (op
[1] != PIC_CALL_REG
)
11435 as_warn (_("MIPS PIC call to register other than $25"));
11437 s
= ((mips_opts
.micromips
11438 && !mips_opts
.insn32
11439 && (!mips_opts
.noreorder
|| cprestore
))
11440 ? "jalrs" : "jalr");
11441 if (mips_opts
.micromips
11442 && !mips_opts
.insn32
11444 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11445 macro_build (NULL
, s
, "mj", op
[1]);
11447 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11448 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11450 if (mips_cprestore_offset
< 0)
11451 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11454 if (!mips_frame_reg_valid
)
11456 as_warn (_("no .frame pseudo-op used in PIC code"));
11457 /* Quiet this warning. */
11458 mips_frame_reg_valid
= 1;
11460 if (!mips_cprestore_valid
)
11462 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11463 /* Quiet this warning. */
11464 mips_cprestore_valid
= 1;
11466 if (mips_opts
.noreorder
)
11467 macro_build (NULL
, "nop", "");
11468 expr1
.X_add_number
= mips_cprestore_offset
;
11469 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11472 HAVE_64BIT_ADDRESSES
);
11480 gas_assert (mips_opts
.micromips
);
11481 if (mips_opts
.insn32
)
11483 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11487 /* Fall through. */
11489 if (mips_pic
== NO_PIC
)
11490 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11491 else if (mips_pic
== SVR4_PIC
)
11493 /* If this is a reference to an external symbol, and we are
11494 using a small GOT, we want
11495 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11499 lw $gp,cprestore($sp)
11500 The cprestore value is set using the .cprestore
11501 pseudo-op. If we are using a big GOT, we want
11502 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11504 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11508 lw $gp,cprestore($sp)
11509 If the symbol is not external, we want
11510 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11512 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11515 lw $gp,cprestore($sp)
11517 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11518 sequences above, minus nops, unless the symbol is local,
11519 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11525 relax_start (offset_expr
.X_add_symbol
);
11526 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11527 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11530 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11531 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11537 relax_start (offset_expr
.X_add_symbol
);
11538 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11539 BFD_RELOC_MIPS_CALL_HI16
);
11540 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11541 PIC_CALL_REG
, mips_gp_register
);
11542 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11543 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11546 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11547 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11549 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11550 PIC_CALL_REG
, PIC_CALL_REG
,
11551 BFD_RELOC_MIPS_GOT_OFST
);
11555 macro_build_jalr (&offset_expr
, 0);
11559 relax_start (offset_expr
.X_add_symbol
);
11562 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11563 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11572 gpdelay
= reg_needs_delay (mips_gp_register
);
11573 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11574 BFD_RELOC_MIPS_CALL_HI16
);
11575 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11576 PIC_CALL_REG
, mips_gp_register
);
11577 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11578 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11583 macro_build (NULL
, "nop", "");
11585 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11586 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11589 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11590 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11592 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11594 if (mips_cprestore_offset
< 0)
11595 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11598 if (!mips_frame_reg_valid
)
11600 as_warn (_("no .frame pseudo-op used in PIC code"));
11601 /* Quiet this warning. */
11602 mips_frame_reg_valid
= 1;
11604 if (!mips_cprestore_valid
)
11606 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11607 /* Quiet this warning. */
11608 mips_cprestore_valid
= 1;
11610 if (mips_opts
.noreorder
)
11611 macro_build (NULL
, "nop", "");
11612 expr1
.X_add_number
= mips_cprestore_offset
;
11613 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11616 HAVE_64BIT_ADDRESSES
);
11620 else if (mips_pic
== VXWORKS_PIC
)
11621 as_bad (_("non-PIC jump used in PIC library"));
11728 gas_assert (!mips_opts
.micromips
);
11731 /* Itbl support may require additional care here. */
11737 /* Itbl support may require additional care here. */
11743 offbits
= (mips_opts
.micromips
? 12
11744 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11746 /* Itbl support may require additional care here. */
11750 gas_assert (!mips_opts
.micromips
);
11753 /* Itbl support may require additional care here. */
11759 offbits
= (mips_opts
.micromips
? 12 : 16);
11764 offbits
= (mips_opts
.micromips
? 12 : 16);
11769 /* Itbl support may require additional care here. */
11775 offbits
= (mips_opts
.micromips
? 12
11776 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11778 /* Itbl support may require additional care here. */
11784 /* Itbl support may require additional care here. */
11790 /* Itbl support may require additional care here. */
11796 offbits
= (mips_opts
.micromips
? 12 : 16);
11801 offbits
= (mips_opts
.micromips
? 12 : 16);
11806 offbits
= (mips_opts
.micromips
? 12
11807 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11813 offbits
= (mips_opts
.micromips
? 12
11814 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11820 offbits
= (mips_opts
.micromips
? 12 : 16);
11823 gas_assert (mips_opts
.micromips
);
11830 gas_assert (mips_opts
.micromips
);
11837 gas_assert (mips_opts
.micromips
);
11843 gas_assert (mips_opts
.micromips
);
11850 /* We don't want to use $0 as tempreg. */
11851 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11854 tempreg
= op
[0] + lp
;
11870 gas_assert (!mips_opts
.micromips
);
11873 /* Itbl support may require additional care here. */
11879 /* Itbl support may require additional care here. */
11885 offbits
= (mips_opts
.micromips
? 12
11886 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11888 /* Itbl support may require additional care here. */
11892 gas_assert (!mips_opts
.micromips
);
11895 /* Itbl support may require additional care here. */
11901 offbits
= (mips_opts
.micromips
? 12 : 16);
11906 offbits
= (mips_opts
.micromips
? 12 : 16);
11911 offbits
= (mips_opts
.micromips
? 12
11912 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11918 offbits
= (mips_opts
.micromips
? 12
11919 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11924 fmt
= (mips_opts
.micromips
? "k,~(b)"
11925 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11927 offbits
= (mips_opts
.micromips
? 12
11928 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11938 fmt
= (mips_opts
.micromips
? "k,~(b)"
11939 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11941 offbits
= (mips_opts
.micromips
? 12
11942 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11954 /* Itbl support may require additional care here. */
11959 offbits
= (mips_opts
.micromips
? 12
11960 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11962 /* Itbl support may require additional care here. */
11968 /* Itbl support may require additional care here. */
11972 gas_assert (!mips_opts
.micromips
);
11975 /* Itbl support may require additional care here. */
11981 offbits
= (mips_opts
.micromips
? 12 : 16);
11986 offbits
= (mips_opts
.micromips
? 12 : 16);
11989 gas_assert (mips_opts
.micromips
);
11995 gas_assert (mips_opts
.micromips
);
12001 gas_assert (mips_opts
.micromips
);
12007 gas_assert (mips_opts
.micromips
);
12016 if (small_offset_p (0, align
, 16))
12018 /* The first case exists for M_LD_AB and M_SD_AB, which are
12019 macros for o32 but which should act like normal instructions
12022 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12023 offset_reloc
[1], offset_reloc
[2], breg
);
12024 else if (small_offset_p (0, align
, offbits
))
12027 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12029 macro_build (NULL
, s
, fmt
, op
[0],
12030 (int) offset_expr
.X_add_number
, breg
);
12036 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12037 tempreg
, breg
, -1, offset_reloc
[0],
12038 offset_reloc
[1], offset_reloc
[2]);
12040 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12042 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12050 if (offset_expr
.X_op
!= O_constant
12051 && offset_expr
.X_op
!= O_symbol
)
12053 as_bad (_("expression too complex"));
12054 offset_expr
.X_op
= O_constant
;
12057 if (HAVE_32BIT_ADDRESSES
12058 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12062 sprintf_vma (value
, offset_expr
.X_add_number
);
12063 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12066 /* A constant expression in PIC code can be handled just as it
12067 is in non PIC code. */
12068 if (offset_expr
.X_op
== O_constant
)
12070 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12071 offbits
== 0 ? 16 : offbits
);
12072 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12074 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12076 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12077 tempreg
, tempreg
, breg
);
12080 if (offset_expr
.X_add_number
!= 0)
12081 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12082 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12083 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12085 else if (offbits
== 16)
12086 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12088 macro_build (NULL
, s
, fmt
, op
[0],
12089 (int) offset_expr
.X_add_number
, tempreg
);
12091 else if (offbits
!= 16)
12093 /* The offset field is too narrow to be used for a low-part
12094 relocation, so load the whole address into the auxiliary
12096 load_address (tempreg
, &offset_expr
, &used_at
);
12098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12099 tempreg
, tempreg
, breg
);
12101 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12103 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12105 else if (mips_pic
== NO_PIC
)
12107 /* If this is a reference to a GP relative symbol, and there
12108 is no base register, we want
12109 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12110 Otherwise, if there is no base register, we want
12111 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12112 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12113 If we have a constant, we need two instructions anyhow,
12114 so we always use the latter form.
12116 If we have a base register, and this is a reference to a
12117 GP relative symbol, we want
12118 addu $tempreg,$breg,$gp
12119 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12121 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12122 addu $tempreg,$tempreg,$breg
12123 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12124 With a constant we always use the latter case.
12126 With 64bit address space and no base register and $at usable,
12128 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12129 lui $at,<sym> (BFD_RELOC_HI16_S)
12130 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12133 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12134 If we have a base register, we want
12135 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12136 lui $at,<sym> (BFD_RELOC_HI16_S)
12137 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12141 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12143 Without $at we can't generate the optimal path for superscalar
12144 processors here since this would require two temporary registers.
12145 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12146 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12148 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12150 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12151 If we have a base register, we want
12152 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12153 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12155 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12157 daddu $tempreg,$tempreg,$breg
12158 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12160 For GP relative symbols in 64bit address space we can use
12161 the same sequence as in 32bit address space. */
12162 if (HAVE_64BIT_SYMBOLS
)
12164 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12165 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12167 relax_start (offset_expr
.X_add_symbol
);
12170 macro_build (&offset_expr
, s
, fmt
, op
[0],
12171 BFD_RELOC_GPREL16
, mips_gp_register
);
12175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12176 tempreg
, breg
, mips_gp_register
);
12177 macro_build (&offset_expr
, s
, fmt
, op
[0],
12178 BFD_RELOC_GPREL16
, tempreg
);
12183 if (used_at
== 0 && mips_opts
.at
)
12185 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12186 BFD_RELOC_MIPS_HIGHEST
);
12187 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12189 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12190 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12192 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12193 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12194 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12195 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12201 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12202 BFD_RELOC_MIPS_HIGHEST
);
12203 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12204 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12205 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12206 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12207 tempreg
, BFD_RELOC_HI16_S
);
12208 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12210 macro_build (NULL
, "daddu", "d,v,t",
12211 tempreg
, tempreg
, breg
);
12212 macro_build (&offset_expr
, s
, fmt
, op
[0],
12213 BFD_RELOC_LO16
, tempreg
);
12216 if (mips_relax
.sequence
)
12223 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12224 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12226 relax_start (offset_expr
.X_add_symbol
);
12227 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12231 macro_build_lui (&offset_expr
, tempreg
);
12232 macro_build (&offset_expr
, s
, fmt
, op
[0],
12233 BFD_RELOC_LO16
, tempreg
);
12234 if (mips_relax
.sequence
)
12239 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12240 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12242 relax_start (offset_expr
.X_add_symbol
);
12243 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12244 tempreg
, breg
, mips_gp_register
);
12245 macro_build (&offset_expr
, s
, fmt
, op
[0],
12246 BFD_RELOC_GPREL16
, tempreg
);
12249 macro_build_lui (&offset_expr
, tempreg
);
12250 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12251 tempreg
, tempreg
, breg
);
12252 macro_build (&offset_expr
, s
, fmt
, op
[0],
12253 BFD_RELOC_LO16
, tempreg
);
12254 if (mips_relax
.sequence
)
12258 else if (!mips_big_got
)
12260 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12262 /* If this is a reference to an external symbol, we want
12263 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12265 <op> op[0],0($tempreg)
12267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12269 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12270 <op> op[0],0($tempreg)
12272 For NewABI, we want
12273 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12274 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12276 If there is a base register, we add it to $tempreg before
12277 the <op>. If there is a constant, we stick it in the
12278 <op> instruction. We don't handle constants larger than
12279 16 bits, because we have no way to load the upper 16 bits
12280 (actually, we could handle them for the subset of cases
12281 in which we are not using $at). */
12282 gas_assert (offset_expr
.X_op
== O_symbol
);
12285 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12286 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12288 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12289 tempreg
, tempreg
, breg
);
12290 macro_build (&offset_expr
, s
, fmt
, op
[0],
12291 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12294 expr1
.X_add_number
= offset_expr
.X_add_number
;
12295 offset_expr
.X_add_number
= 0;
12296 if (expr1
.X_add_number
< -0x8000
12297 || expr1
.X_add_number
>= 0x8000)
12298 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12299 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12300 lw_reloc_type
, mips_gp_register
);
12302 relax_start (offset_expr
.X_add_symbol
);
12304 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12305 tempreg
, BFD_RELOC_LO16
);
12308 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12309 tempreg
, tempreg
, breg
);
12310 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12312 else if (mips_big_got
&& !HAVE_NEWABI
)
12316 /* If this is a reference to an external symbol, we want
12317 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12318 addu $tempreg,$tempreg,$gp
12319 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12320 <op> op[0],0($tempreg)
12322 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12324 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12325 <op> op[0],0($tempreg)
12326 If there is a base register, we add it to $tempreg before
12327 the <op>. If there is a constant, we stick it in the
12328 <op> instruction. We don't handle constants larger than
12329 16 bits, because we have no way to load the upper 16 bits
12330 (actually, we could handle them for the subset of cases
12331 in which we are not using $at). */
12332 gas_assert (offset_expr
.X_op
== O_symbol
);
12333 expr1
.X_add_number
= offset_expr
.X_add_number
;
12334 offset_expr
.X_add_number
= 0;
12335 if (expr1
.X_add_number
< -0x8000
12336 || expr1
.X_add_number
>= 0x8000)
12337 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12338 gpdelay
= reg_needs_delay (mips_gp_register
);
12339 relax_start (offset_expr
.X_add_symbol
);
12340 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12341 BFD_RELOC_MIPS_GOT_HI16
);
12342 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12344 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12345 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12348 macro_build (NULL
, "nop", "");
12349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12350 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12352 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12353 tempreg
, BFD_RELOC_LO16
);
12357 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12358 tempreg
, tempreg
, breg
);
12359 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12361 else if (mips_big_got
&& HAVE_NEWABI
)
12363 /* If this is a reference to an external symbol, we want
12364 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12365 add $tempreg,$tempreg,$gp
12366 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12367 <op> op[0],<ofst>($tempreg)
12368 Otherwise, for local symbols, we want:
12369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12370 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12371 gas_assert (offset_expr
.X_op
== O_symbol
);
12372 expr1
.X_add_number
= offset_expr
.X_add_number
;
12373 offset_expr
.X_add_number
= 0;
12374 if (expr1
.X_add_number
< -0x8000
12375 || expr1
.X_add_number
>= 0x8000)
12376 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12377 relax_start (offset_expr
.X_add_symbol
);
12378 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12379 BFD_RELOC_MIPS_GOT_HI16
);
12380 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12383 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12386 tempreg
, tempreg
, breg
);
12387 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12390 offset_expr
.X_add_number
= expr1
.X_add_number
;
12391 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12392 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12394 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12395 tempreg
, tempreg
, breg
);
12396 macro_build (&offset_expr
, s
, fmt
, op
[0],
12397 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12406 gas_assert (mips_opts
.micromips
);
12407 gas_assert (mips_opts
.insn32
);
12408 start_noreorder ();
12409 macro_build (NULL
, "jr", "s", RA
);
12410 expr1
.X_add_number
= op
[0] << 2;
12411 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12416 gas_assert (mips_opts
.micromips
);
12417 gas_assert (mips_opts
.insn32
);
12418 macro_build (NULL
, "jr", "s", op
[0]);
12419 if (mips_opts
.noreorder
)
12420 macro_build (NULL
, "nop", "");
12425 load_register (op
[0], &imm_expr
, 0);
12429 load_register (op
[0], &imm_expr
, 1);
12433 if (imm_expr
.X_op
== O_constant
)
12436 load_register (AT
, &imm_expr
, 0);
12437 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12442 gas_assert (imm_expr
.X_op
== O_absent
12443 && offset_expr
.X_op
== O_symbol
12444 && strcmp (segment_name (S_GET_SEGMENT
12445 (offset_expr
.X_add_symbol
)),
12447 && offset_expr
.X_add_number
== 0);
12448 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12449 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12454 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12455 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12456 order 32 bits of the value and the low order 32 bits are either
12457 zero or in OFFSET_EXPR. */
12458 if (imm_expr
.X_op
== O_constant
)
12460 if (GPR_SIZE
== 64)
12461 load_register (op
[0], &imm_expr
, 1);
12466 if (target_big_endian
)
12478 load_register (hreg
, &imm_expr
, 0);
12481 if (offset_expr
.X_op
== O_absent
)
12482 move_register (lreg
, 0);
12485 gas_assert (offset_expr
.X_op
== O_constant
);
12486 load_register (lreg
, &offset_expr
, 0);
12492 gas_assert (imm_expr
.X_op
== O_absent
);
12494 /* We know that sym is in the .rdata section. First we get the
12495 upper 16 bits of the address. */
12496 if (mips_pic
== NO_PIC
)
12498 macro_build_lui (&offset_expr
, AT
);
12503 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12504 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12508 /* Now we load the register(s). */
12509 if (GPR_SIZE
== 64)
12512 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12513 BFD_RELOC_LO16
, AT
);
12518 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12519 BFD_RELOC_LO16
, AT
);
12522 /* FIXME: How in the world do we deal with the possible
12524 offset_expr
.X_add_number
+= 4;
12525 macro_build (&offset_expr
, "lw", "t,o(b)",
12526 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12532 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12533 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12534 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12535 the value and the low order 32 bits are either zero or in
12537 if (imm_expr
.X_op
== O_constant
)
12540 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12541 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12542 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12545 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12546 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12547 else if (FPR_SIZE
!= 32)
12548 as_bad (_("Unable to generate `%s' compliant code "
12550 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12552 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12553 if (offset_expr
.X_op
== O_absent
)
12554 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12557 gas_assert (offset_expr
.X_op
== O_constant
);
12558 load_register (AT
, &offset_expr
, 0);
12559 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12565 gas_assert (imm_expr
.X_op
== O_absent
12566 && offset_expr
.X_op
== O_symbol
12567 && offset_expr
.X_add_number
== 0);
12568 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12569 if (strcmp (s
, ".lit8") == 0)
12571 op
[2] = mips_gp_register
;
12572 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12573 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12574 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12578 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12580 if (mips_pic
!= NO_PIC
)
12581 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12582 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12585 /* FIXME: This won't work for a 64 bit address. */
12586 macro_build_lui (&offset_expr
, AT
);
12590 offset_reloc
[0] = BFD_RELOC_LO16
;
12591 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12592 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12599 * The MIPS assembler seems to check for X_add_number not
12600 * being double aligned and generating:
12601 * lui at,%hi(foo+1)
12603 * addiu at,at,%lo(foo+1)
12606 * But, the resulting address is the same after relocation so why
12607 * generate the extra instruction?
12609 /* Itbl support may require additional care here. */
12612 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12621 gas_assert (!mips_opts
.micromips
);
12622 /* Itbl support may require additional care here. */
12625 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12645 if (GPR_SIZE
== 64)
12655 if (GPR_SIZE
== 64)
12663 /* Even on a big endian machine $fn comes before $fn+1. We have
12664 to adjust when loading from memory. We set coproc if we must
12665 load $fn+1 first. */
12666 /* Itbl support may require additional care here. */
12667 if (!target_big_endian
)
12671 if (small_offset_p (0, align
, 16))
12674 if (!small_offset_p (4, align
, 16))
12676 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12677 -1, offset_reloc
[0], offset_reloc
[1],
12679 expr1
.X_add_number
= 0;
12683 offset_reloc
[0] = BFD_RELOC_LO16
;
12684 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12685 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12687 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12689 ep
->X_add_number
+= 4;
12690 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12691 offset_reloc
[1], offset_reloc
[2], breg
);
12692 ep
->X_add_number
-= 4;
12693 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12694 offset_reloc
[1], offset_reloc
[2], breg
);
12698 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12699 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12701 ep
->X_add_number
+= 4;
12702 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12703 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12709 if (offset_expr
.X_op
!= O_symbol
12710 && offset_expr
.X_op
!= O_constant
)
12712 as_bad (_("expression too complex"));
12713 offset_expr
.X_op
= O_constant
;
12716 if (HAVE_32BIT_ADDRESSES
12717 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12721 sprintf_vma (value
, offset_expr
.X_add_number
);
12722 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12725 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12727 /* If this is a reference to a GP relative symbol, we want
12728 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12729 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12730 If we have a base register, we use this
12732 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12733 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12734 If this is not a GP relative symbol, we want
12735 lui $at,<sym> (BFD_RELOC_HI16_S)
12736 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12737 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12738 If there is a base register, we add it to $at after the
12739 lui instruction. If there is a constant, we always use
12741 if (offset_expr
.X_op
== O_symbol
12742 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12743 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12745 relax_start (offset_expr
.X_add_symbol
);
12748 tempreg
= mips_gp_register
;
12752 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12753 AT
, breg
, mips_gp_register
);
12758 /* Itbl support may require additional care here. */
12759 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12760 BFD_RELOC_GPREL16
, tempreg
);
12761 offset_expr
.X_add_number
+= 4;
12763 /* Set mips_optimize to 2 to avoid inserting an
12765 hold_mips_optimize
= mips_optimize
;
12767 /* Itbl support may require additional care here. */
12768 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12769 BFD_RELOC_GPREL16
, tempreg
);
12770 mips_optimize
= hold_mips_optimize
;
12774 offset_expr
.X_add_number
-= 4;
12777 if (offset_high_part (offset_expr
.X_add_number
, 16)
12778 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12780 load_address (AT
, &offset_expr
, &used_at
);
12781 offset_expr
.X_op
= O_constant
;
12782 offset_expr
.X_add_number
= 0;
12785 macro_build_lui (&offset_expr
, AT
);
12787 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12788 /* Itbl support may require additional care here. */
12789 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12790 BFD_RELOC_LO16
, AT
);
12791 /* FIXME: How do we handle overflow here? */
12792 offset_expr
.X_add_number
+= 4;
12793 /* Itbl support may require additional care here. */
12794 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12795 BFD_RELOC_LO16
, AT
);
12796 if (mips_relax
.sequence
)
12799 else if (!mips_big_got
)
12801 /* If this is a reference to an external symbol, we want
12802 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12805 <op> op[0]+1,4($at)
12807 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12809 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12810 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12811 If there is a base register we add it to $at before the
12812 lwc1 instructions. If there is a constant we include it
12813 in the lwc1 instructions. */
12815 expr1
.X_add_number
= offset_expr
.X_add_number
;
12816 if (expr1
.X_add_number
< -0x8000
12817 || expr1
.X_add_number
>= 0x8000 - 4)
12818 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12819 load_got_offset (AT
, &offset_expr
);
12822 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12824 /* Set mips_optimize to 2 to avoid inserting an undesired
12826 hold_mips_optimize
= mips_optimize
;
12829 /* Itbl support may require additional care here. */
12830 relax_start (offset_expr
.X_add_symbol
);
12831 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12832 BFD_RELOC_LO16
, AT
);
12833 expr1
.X_add_number
+= 4;
12834 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12835 BFD_RELOC_LO16
, AT
);
12837 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12838 BFD_RELOC_LO16
, AT
);
12839 offset_expr
.X_add_number
+= 4;
12840 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12841 BFD_RELOC_LO16
, AT
);
12844 mips_optimize
= hold_mips_optimize
;
12846 else if (mips_big_got
)
12850 /* If this is a reference to an external symbol, we want
12851 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12853 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12856 <op> op[0]+1,4($at)
12858 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12860 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12861 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12862 If there is a base register we add it to $at before the
12863 lwc1 instructions. If there is a constant we include it
12864 in the lwc1 instructions. */
12866 expr1
.X_add_number
= offset_expr
.X_add_number
;
12867 offset_expr
.X_add_number
= 0;
12868 if (expr1
.X_add_number
< -0x8000
12869 || expr1
.X_add_number
>= 0x8000 - 4)
12870 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12871 gpdelay
= reg_needs_delay (mips_gp_register
);
12872 relax_start (offset_expr
.X_add_symbol
);
12873 macro_build (&offset_expr
, "lui", LUI_FMT
,
12874 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12875 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12876 AT
, AT
, mips_gp_register
);
12877 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12878 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12881 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12882 /* Itbl support may require additional care here. */
12883 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12884 BFD_RELOC_LO16
, AT
);
12885 expr1
.X_add_number
+= 4;
12887 /* Set mips_optimize to 2 to avoid inserting an undesired
12889 hold_mips_optimize
= mips_optimize
;
12891 /* Itbl support may require additional care here. */
12892 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12893 BFD_RELOC_LO16
, AT
);
12894 mips_optimize
= hold_mips_optimize
;
12895 expr1
.X_add_number
-= 4;
12898 offset_expr
.X_add_number
= expr1
.X_add_number
;
12900 macro_build (NULL
, "nop", "");
12901 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12902 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12905 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12906 /* Itbl support may require additional care here. */
12907 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12908 BFD_RELOC_LO16
, AT
);
12909 offset_expr
.X_add_number
+= 4;
12911 /* Set mips_optimize to 2 to avoid inserting an undesired
12913 hold_mips_optimize
= mips_optimize
;
12915 /* Itbl support may require additional care here. */
12916 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12917 BFD_RELOC_LO16
, AT
);
12918 mips_optimize
= hold_mips_optimize
;
12932 gas_assert (!mips_opts
.micromips
);
12937 /* New code added to support COPZ instructions.
12938 This code builds table entries out of the macros in mip_opcodes.
12939 R4000 uses interlocks to handle coproc delays.
12940 Other chips (like the R3000) require nops to be inserted for delays.
12942 FIXME: Currently, we require that the user handle delays.
12943 In order to fill delay slots for non-interlocked chips,
12944 we must have a way to specify delays based on the coprocessor.
12945 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12946 What are the side-effects of the cop instruction?
12947 What cache support might we have and what are its effects?
12948 Both coprocessor & memory require delays. how long???
12949 What registers are read/set/modified?
12951 If an itbl is provided to interpret cop instructions,
12952 this knowledge can be encoded in the itbl spec. */
12966 gas_assert (!mips_opts
.micromips
);
12967 /* For now we just do C (same as Cz). The parameter will be
12968 stored in insn_opcode by mips_ip. */
12969 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12973 move_register (op
[0], op
[1]);
12977 gas_assert (mips_opts
.micromips
);
12978 gas_assert (mips_opts
.insn32
);
12979 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12980 micromips_to_32_reg_m_map
[op
[1]]);
12981 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12982 micromips_to_32_reg_n_map
[op
[2]]);
12987 /* Fall through. */
12989 if (mips_opts
.arch
== CPU_R5900
)
12990 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12994 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12995 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13001 /* Fall through. */
13003 /* The MIPS assembler some times generates shifts and adds. I'm
13004 not trying to be that fancy. GCC should do this for us
13007 load_register (AT
, &imm_expr
, dbl
);
13008 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13009 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13014 /* Fall through. */
13021 /* Fall through. */
13024 start_noreorder ();
13027 load_register (AT
, &imm_expr
, dbl
);
13028 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13029 op
[1], imm
? AT
: op
[2]);
13030 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13031 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13032 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13034 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13037 if (mips_opts
.micromips
)
13038 micromips_label_expr (&label_expr
);
13040 label_expr
.X_add_number
= 8;
13041 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13042 macro_build (NULL
, "nop", "");
13043 macro_build (NULL
, "break", BRK_FMT
, 6);
13044 if (mips_opts
.micromips
)
13045 micromips_add_label ();
13048 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13053 /* Fall through. */
13060 /* Fall through. */
13063 start_noreorder ();
13066 load_register (AT
, &imm_expr
, dbl
);
13067 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13068 op
[1], imm
? AT
: op
[2]);
13069 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13070 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13072 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13075 if (mips_opts
.micromips
)
13076 micromips_label_expr (&label_expr
);
13078 label_expr
.X_add_number
= 8;
13079 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13080 macro_build (NULL
, "nop", "");
13081 macro_build (NULL
, "break", BRK_FMT
, 6);
13082 if (mips_opts
.micromips
)
13083 micromips_add_label ();
13089 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13091 if (op
[0] == op
[1])
13098 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13099 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13103 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13104 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13105 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13106 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13110 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13112 if (op
[0] == op
[1])
13119 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13120 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13124 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13125 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13126 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13127 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13136 rot
= imm_expr
.X_add_number
& 0x3f;
13137 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13139 rot
= (64 - rot
) & 0x3f;
13141 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13143 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13148 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13151 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13152 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13155 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13156 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13157 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13165 rot
= imm_expr
.X_add_number
& 0x1f;
13166 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13168 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13169 (32 - rot
) & 0x1f);
13174 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13178 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13179 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13180 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13185 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13187 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13191 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13192 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13193 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13194 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13198 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13200 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13204 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13205 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13206 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13207 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13216 rot
= imm_expr
.X_add_number
& 0x3f;
13217 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13220 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13222 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13227 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13230 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13231 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13234 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13235 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13236 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13244 rot
= imm_expr
.X_add_number
& 0x1f;
13245 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13247 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13252 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13256 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13257 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13258 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13264 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13265 else if (op
[2] == 0)
13266 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13269 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13270 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13275 if (imm_expr
.X_add_number
== 0)
13277 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13282 as_warn (_("instruction %s: result is always false"),
13283 ip
->insn_mo
->name
);
13284 move_register (op
[0], 0);
13287 if (CPU_HAS_SEQ (mips_opts
.arch
)
13288 && -512 <= imm_expr
.X_add_number
13289 && imm_expr
.X_add_number
< 512)
13291 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13292 (int) imm_expr
.X_add_number
);
13295 if (imm_expr
.X_add_number
>= 0
13296 && imm_expr
.X_add_number
< 0x10000)
13297 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13298 else if (imm_expr
.X_add_number
> -0x8000
13299 && imm_expr
.X_add_number
< 0)
13301 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13302 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13303 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13305 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13308 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13309 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13314 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13315 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13318 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13321 case M_SGE
: /* X >= Y <==> not (X < Y) */
13327 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13328 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13331 case M_SGE_I
: /* X >= I <==> not (X < I) */
13333 if (imm_expr
.X_add_number
>= -0x8000
13334 && imm_expr
.X_add_number
< 0x8000)
13335 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13336 op
[0], op
[1], BFD_RELOC_LO16
);
13339 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13340 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13344 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13347 case M_SGT
: /* X > Y <==> Y < X */
13353 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13356 case M_SGT_I
: /* X > I <==> I < X */
13363 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13364 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13367 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13373 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13374 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13377 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13384 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13385 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13386 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13390 if (imm_expr
.X_add_number
>= -0x8000
13391 && imm_expr
.X_add_number
< 0x8000)
13393 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13398 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13399 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13403 if (imm_expr
.X_add_number
>= -0x8000
13404 && imm_expr
.X_add_number
< 0x8000)
13406 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13411 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13412 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13417 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13418 else if (op
[2] == 0)
13419 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13422 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13423 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13428 if (imm_expr
.X_add_number
== 0)
13430 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13435 as_warn (_("instruction %s: result is always true"),
13436 ip
->insn_mo
->name
);
13437 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13438 op
[0], 0, BFD_RELOC_LO16
);
13441 if (CPU_HAS_SEQ (mips_opts
.arch
)
13442 && -512 <= imm_expr
.X_add_number
13443 && imm_expr
.X_add_number
< 512)
13445 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13446 (int) imm_expr
.X_add_number
);
13449 if (imm_expr
.X_add_number
>= 0
13450 && imm_expr
.X_add_number
< 0x10000)
13452 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13455 else if (imm_expr
.X_add_number
> -0x8000
13456 && imm_expr
.X_add_number
< 0)
13458 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13459 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13460 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13462 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13465 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13466 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13471 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13472 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13475 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13490 if (!mips_opts
.micromips
)
13492 if (imm_expr
.X_add_number
> -0x200
13493 && imm_expr
.X_add_number
<= 0x200)
13495 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13496 (int) -imm_expr
.X_add_number
);
13505 if (imm_expr
.X_add_number
> -0x8000
13506 && imm_expr
.X_add_number
<= 0x8000)
13508 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13509 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13514 load_register (AT
, &imm_expr
, dbl
);
13515 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13537 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13538 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13543 gas_assert (!mips_opts
.micromips
);
13544 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13548 * Is the double cfc1 instruction a bug in the mips assembler;
13549 * or is there a reason for it?
13551 start_noreorder ();
13552 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13553 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13554 macro_build (NULL
, "nop", "");
13555 expr1
.X_add_number
= 3;
13556 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13557 expr1
.X_add_number
= 2;
13558 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13559 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13560 macro_build (NULL
, "nop", "");
13561 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13563 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13564 macro_build (NULL
, "nop", "");
13581 offbits
= (mips_opts
.micromips
? 12 : 16);
13587 offbits
= (mips_opts
.micromips
? 12 : 16);
13599 offbits
= (mips_opts
.micromips
? 12 : 16);
13606 offbits
= (mips_opts
.micromips
? 12 : 16);
13612 large_offset
= !small_offset_p (off
, align
, offbits
);
13614 expr1
.X_add_number
= 0;
13619 if (small_offset_p (0, align
, 16))
13620 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13621 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13624 load_address (tempreg
, ep
, &used_at
);
13626 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13627 tempreg
, tempreg
, breg
);
13629 offset_reloc
[0] = BFD_RELOC_LO16
;
13630 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13631 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13636 else if (!ust
&& op
[0] == breg
)
13647 if (!target_big_endian
)
13648 ep
->X_add_number
+= off
;
13650 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13652 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13653 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13655 if (!target_big_endian
)
13656 ep
->X_add_number
-= off
;
13658 ep
->X_add_number
+= off
;
13660 macro_build (NULL
, s2
, "t,~(b)",
13661 tempreg
, (int) ep
->X_add_number
, breg
);
13663 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13664 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13666 /* If necessary, move the result in tempreg to the final destination. */
13667 if (!ust
&& op
[0] != tempreg
)
13669 /* Protect second load's delay slot. */
13671 move_register (op
[0], tempreg
);
13677 if (target_big_endian
== ust
)
13678 ep
->X_add_number
+= off
;
13679 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13680 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13681 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13683 /* For halfword transfers we need a temporary register to shuffle
13684 bytes. Unfortunately for M_USH_A we have none available before
13685 the next store as AT holds the base address. We deal with this
13686 case by clobbering TREG and then restoring it as with ULH. */
13687 tempreg
= ust
== large_offset
? op
[0] : AT
;
13689 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13691 if (target_big_endian
== ust
)
13692 ep
->X_add_number
-= off
;
13694 ep
->X_add_number
+= off
;
13695 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13696 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13698 /* For M_USH_A re-retrieve the LSB. */
13699 if (ust
&& large_offset
)
13701 if (target_big_endian
)
13702 ep
->X_add_number
+= off
;
13704 ep
->X_add_number
-= off
;
13705 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13706 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13708 /* For ULH and M_USH_A OR the LSB in. */
13709 if (!ust
|| large_offset
)
13711 tempreg
= !large_offset
? AT
: op
[0];
13712 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13713 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13718 /* FIXME: Check if this is one of the itbl macros, since they
13719 are added dynamically. */
13720 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13723 if (!mips_opts
.at
&& used_at
)
13724 as_bad (_("macro used $at after \".set noat\""));
13727 /* Implement macros in mips16 mode. */
13730 mips16_macro (struct mips_cl_insn
*ip
)
13732 const struct mips_operand_array
*operands
;
13737 const char *s
, *s2
, *s3
;
13738 unsigned int op
[MAX_OPERANDS
];
13741 mask
= ip
->insn_mo
->mask
;
13743 operands
= insn_operands (ip
);
13744 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13745 if (operands
->operand
[i
])
13746 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13750 expr1
.X_op
= O_constant
;
13751 expr1
.X_op_symbol
= NULL
;
13752 expr1
.X_add_symbol
= NULL
;
13753 expr1
.X_add_number
= 1;
13764 /* Fall through. */
13770 /* Fall through. */
13774 start_noreorder ();
13775 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13776 expr1
.X_add_number
= 2;
13777 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13778 macro_build (NULL
, "break", "6", 7);
13780 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13781 since that causes an overflow. We should do that as well,
13782 but I don't see how to do the comparisons without a temporary
13785 macro_build (NULL
, s
, "x", op
[0]);
13804 start_noreorder ();
13805 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13806 expr1
.X_add_number
= 2;
13807 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13808 macro_build (NULL
, "break", "6", 7);
13810 macro_build (NULL
, s2
, "x", op
[0]);
13815 /* Fall through. */
13817 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13818 macro_build (NULL
, "mflo", "x", op
[0]);
13826 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13827 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13831 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13832 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13836 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13837 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13859 goto do_reverse_branch
;
13863 goto do_reverse_branch
;
13875 goto do_reverse_branch
;
13886 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13887 macro_build (&offset_expr
, s2
, "p");
13914 goto do_addone_branch_i
;
13919 goto do_addone_branch_i
;
13934 goto do_addone_branch_i
;
13940 do_addone_branch_i
:
13941 ++imm_expr
.X_add_number
;
13944 macro_build (&imm_expr
, s
, s3
, op
[0]);
13945 macro_build (&offset_expr
, s2
, "p");
13949 expr1
.X_add_number
= 0;
13950 macro_build (&expr1
, "slti", "x,8", op
[1]);
13951 if (op
[0] != op
[1])
13952 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13953 expr1
.X_add_number
= 2;
13954 macro_build (&expr1
, "bteqz", "p");
13955 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13960 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13961 opcode bits in *OPCODE_EXTRA. */
13963 static struct mips_opcode
*
13964 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13965 ssize_t length
, unsigned int *opcode_extra
)
13967 char *name
, *dot
, *p
;
13968 unsigned int mask
, suffix
;
13970 struct mips_opcode
*insn
;
13972 /* Make a copy of the instruction so that we can fiddle with it. */
13973 name
= xstrndup (start
, length
);
13975 /* Look up the instruction as-is. */
13976 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13980 dot
= strchr (name
, '.');
13983 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13984 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13985 if (*p
== 0 && mask
!= 0)
13988 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13990 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13992 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13998 if (mips_opts
.micromips
)
14000 /* See if there's an instruction size override suffix,
14001 either `16' or `32', at the end of the mnemonic proper,
14002 that defines the operation, i.e. before the first `.'
14003 character if any. Strip it and retry. */
14004 opend
= dot
!= NULL
? dot
- name
: length
;
14005 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14007 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14013 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14014 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14017 forced_insn_length
= suffix
;
14029 /* Assemble an instruction into its binary format. If the instruction
14030 is a macro, set imm_expr and offset_expr to the values associated
14031 with "I" and "A" operands respectively. Otherwise store the value
14032 of the relocatable field (if any) in offset_expr. In both cases
14033 set offset_reloc to the relocation operators applied to offset_expr. */
14036 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14038 const struct mips_opcode
*first
, *past
;
14039 struct hash_control
*hash
;
14042 struct mips_operand_token
*tokens
;
14043 unsigned int opcode_extra
;
14045 if (mips_opts
.micromips
)
14047 hash
= micromips_op_hash
;
14048 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14053 past
= &mips_opcodes
[NUMOPCODES
];
14055 forced_insn_length
= 0;
14058 /* We first try to match an instruction up to a space or to the end. */
14059 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14062 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14065 set_insn_error (0, _("unrecognized opcode"));
14069 if (strcmp (first
->name
, "li.s") == 0)
14071 else if (strcmp (first
->name
, "li.d") == 0)
14075 tokens
= mips_parse_arguments (str
+ end
, format
);
14079 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14080 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14081 set_insn_error (0, _("invalid operands"));
14083 obstack_free (&mips_operand_tokens
, tokens
);
14086 /* As for mips_ip, but used when assembling MIPS16 code.
14087 Also set forced_insn_length to the resulting instruction size in
14088 bytes if the user explicitly requested a small or extended instruction. */
14091 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14094 struct mips_opcode
*first
;
14095 struct mips_operand_token
*tokens
;
14098 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14120 else if (*s
== 'e')
14127 else if (*s
++ == ' ')
14129 set_insn_error (0, _("unrecognized opcode"));
14132 forced_insn_length
= l
;
14135 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14140 set_insn_error (0, _("unrecognized opcode"));
14144 tokens
= mips_parse_arguments (s
, 0);
14148 if (!match_mips16_insns (insn
, first
, tokens
))
14149 set_insn_error (0, _("invalid operands"));
14151 obstack_free (&mips_operand_tokens
, tokens
);
14154 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14155 NBITS is the number of significant bits in VAL. */
14157 static unsigned long
14158 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14163 val
&= (1U << nbits
) - 1;
14164 if (nbits
== 16 || nbits
== 9)
14166 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14169 else if (nbits
== 15)
14171 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14174 else if (nbits
== 6)
14176 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14179 return (extval
<< 16) | val
;
14182 /* Like decode_mips16_operand, but require the operand to be defined and
14183 require it to be an integer. */
14185 static const struct mips_int_operand
*
14186 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14188 const struct mips_operand
*operand
;
14190 operand
= decode_mips16_operand (type
, extended_p
);
14191 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14193 return (const struct mips_int_operand
*) operand
;
14196 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14199 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14200 bfd_reloc_code_real_type reloc
, offsetT sval
)
14202 int min_val
, max_val
;
14204 min_val
= mips_int_operand_min (operand
);
14205 max_val
= mips_int_operand_max (operand
);
14206 if (reloc
!= BFD_RELOC_UNUSED
)
14209 sval
= SEXT_16BIT (sval
);
14214 return (sval
>= min_val
14216 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14219 /* Install immediate value VAL into MIPS16 instruction *INSN,
14220 extending it if necessary. The instruction in *INSN may
14221 already be extended.
14223 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14224 if none. In the former case, VAL is a 16-bit number with no
14225 defined signedness.
14227 TYPE is the type of the immediate field. USER_INSN_LENGTH
14228 is the length that the user requested, or 0 if none. */
14231 mips16_immed (const char *file
, unsigned int line
, int type
,
14232 bfd_reloc_code_real_type reloc
, offsetT val
,
14233 unsigned int user_insn_length
, unsigned long *insn
)
14235 const struct mips_int_operand
*operand
;
14236 unsigned int uval
, length
;
14238 operand
= mips16_immed_operand (type
, FALSE
);
14239 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14241 /* We need an extended instruction. */
14242 if (user_insn_length
== 2)
14243 as_bad_where (file
, line
, _("invalid unextended operand value"));
14245 *insn
|= MIPS16_EXTEND
;
14247 else if (user_insn_length
== 4)
14249 /* The operand doesn't force an unextended instruction to be extended.
14250 Warn if the user wanted an extended instruction anyway. */
14251 *insn
|= MIPS16_EXTEND
;
14252 as_warn_where (file
, line
,
14253 _("extended operand requested but not required"));
14256 length
= mips16_opcode_length (*insn
);
14259 operand
= mips16_immed_operand (type
, TRUE
);
14260 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14261 as_bad_where (file
, line
,
14262 _("operand value out of range for instruction"));
14264 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14265 if (length
== 2 || operand
->root
.lsb
!= 0)
14266 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14268 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14271 struct percent_op_match
14274 bfd_reloc_code_real_type reloc
;
14277 static const struct percent_op_match mips_percent_op
[] =
14279 {"%lo", BFD_RELOC_LO16
},
14280 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14281 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14282 {"%call16", BFD_RELOC_MIPS_CALL16
},
14283 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14284 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14285 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14286 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14287 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14288 {"%got", BFD_RELOC_MIPS_GOT16
},
14289 {"%gp_rel", BFD_RELOC_GPREL16
},
14290 {"%gprel", BFD_RELOC_GPREL16
},
14291 {"%half", BFD_RELOC_16
},
14292 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14293 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14294 {"%neg", BFD_RELOC_MIPS_SUB
},
14295 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14296 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14297 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14298 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14299 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14300 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14301 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14302 {"%hi", BFD_RELOC_HI16_S
},
14303 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14304 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14307 static const struct percent_op_match mips16_percent_op
[] =
14309 {"%lo", BFD_RELOC_MIPS16_LO16
},
14310 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14311 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14312 {"%got", BFD_RELOC_MIPS16_GOT16
},
14313 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14314 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14315 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14316 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14317 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14318 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14319 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14320 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14321 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14325 /* Return true if *STR points to a relocation operator. When returning true,
14326 move *STR over the operator and store its relocation code in *RELOC.
14327 Leave both *STR and *RELOC alone when returning false. */
14330 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14332 const struct percent_op_match
*percent_op
;
14335 if (mips_opts
.mips16
)
14337 percent_op
= mips16_percent_op
;
14338 limit
= ARRAY_SIZE (mips16_percent_op
);
14342 percent_op
= mips_percent_op
;
14343 limit
= ARRAY_SIZE (mips_percent_op
);
14346 for (i
= 0; i
< limit
; i
++)
14347 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14349 int len
= strlen (percent_op
[i
].str
);
14351 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14354 *str
+= strlen (percent_op
[i
].str
);
14355 *reloc
= percent_op
[i
].reloc
;
14357 /* Check whether the output BFD supports this relocation.
14358 If not, issue an error and fall back on something safe. */
14359 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14361 as_bad (_("relocation %s isn't supported by the current ABI"),
14362 percent_op
[i
].str
);
14363 *reloc
= BFD_RELOC_UNUSED
;
14371 /* Parse string STR as a 16-bit relocatable operand. Store the
14372 expression in *EP and the relocations in the array starting
14373 at RELOC. Return the number of relocation operators used.
14375 On exit, EXPR_END points to the first character after the expression. */
14378 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14381 bfd_reloc_code_real_type reversed_reloc
[3];
14382 size_t reloc_index
, i
;
14383 int crux_depth
, str_depth
;
14386 /* Search for the start of the main expression, recoding relocations
14387 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14388 of the main expression and with CRUX_DEPTH containing the number
14389 of open brackets at that point. */
14396 crux_depth
= str_depth
;
14398 /* Skip over whitespace and brackets, keeping count of the number
14400 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14405 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14406 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14408 my_getExpression (ep
, crux
);
14411 /* Match every open bracket. */
14412 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14416 if (crux_depth
> 0)
14417 as_bad (_("unclosed '('"));
14421 if (reloc_index
!= 0)
14423 prev_reloc_op_frag
= frag_now
;
14424 for (i
= 0; i
< reloc_index
; i
++)
14425 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14428 return reloc_index
;
14432 my_getExpression (expressionS
*ep
, char *str
)
14436 save_in
= input_line_pointer
;
14437 input_line_pointer
= str
;
14439 expr_end
= input_line_pointer
;
14440 input_line_pointer
= save_in
;
14444 md_atof (int type
, char *litP
, int *sizeP
)
14446 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14450 md_number_to_chars (char *buf
, valueT val
, int n
)
14452 if (target_big_endian
)
14453 number_to_chars_bigendian (buf
, val
, n
);
14455 number_to_chars_littleendian (buf
, val
, n
);
14458 static int support_64bit_objects(void)
14460 const char **list
, **l
;
14463 list
= bfd_target_list ();
14464 for (l
= list
; *l
!= NULL
; l
++)
14465 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14466 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14468 yes
= (*l
!= NULL
);
14473 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14474 NEW_VALUE. Warn if another value was already specified. Note:
14475 we have to defer parsing the -march and -mtune arguments in order
14476 to handle 'from-abi' correctly, since the ABI might be specified
14477 in a later argument. */
14480 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14482 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14483 as_warn (_("a different %s was already specified, is now %s"),
14484 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14487 *string_ptr
= new_value
;
14491 md_parse_option (int c
, const char *arg
)
14495 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14496 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14498 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14499 c
== mips_ases
[i
].option_on
);
14505 case OPTION_CONSTRUCT_FLOATS
:
14506 mips_disable_float_construction
= 0;
14509 case OPTION_NO_CONSTRUCT_FLOATS
:
14510 mips_disable_float_construction
= 1;
14522 target_big_endian
= 1;
14526 target_big_endian
= 0;
14532 else if (arg
[0] == '0')
14534 else if (arg
[0] == '1')
14544 mips_debug
= atoi (arg
);
14548 file_mips_opts
.isa
= ISA_MIPS1
;
14552 file_mips_opts
.isa
= ISA_MIPS2
;
14556 file_mips_opts
.isa
= ISA_MIPS3
;
14560 file_mips_opts
.isa
= ISA_MIPS4
;
14564 file_mips_opts
.isa
= ISA_MIPS5
;
14567 case OPTION_MIPS32
:
14568 file_mips_opts
.isa
= ISA_MIPS32
;
14571 case OPTION_MIPS32R2
:
14572 file_mips_opts
.isa
= ISA_MIPS32R2
;
14575 case OPTION_MIPS32R3
:
14576 file_mips_opts
.isa
= ISA_MIPS32R3
;
14579 case OPTION_MIPS32R5
:
14580 file_mips_opts
.isa
= ISA_MIPS32R5
;
14583 case OPTION_MIPS32R6
:
14584 file_mips_opts
.isa
= ISA_MIPS32R6
;
14587 case OPTION_MIPS64R2
:
14588 file_mips_opts
.isa
= ISA_MIPS64R2
;
14591 case OPTION_MIPS64R3
:
14592 file_mips_opts
.isa
= ISA_MIPS64R3
;
14595 case OPTION_MIPS64R5
:
14596 file_mips_opts
.isa
= ISA_MIPS64R5
;
14599 case OPTION_MIPS64R6
:
14600 file_mips_opts
.isa
= ISA_MIPS64R6
;
14603 case OPTION_MIPS64
:
14604 file_mips_opts
.isa
= ISA_MIPS64
;
14608 mips_set_option_string (&mips_tune_string
, arg
);
14612 mips_set_option_string (&mips_arch_string
, arg
);
14616 mips_set_option_string (&mips_arch_string
, "4650");
14617 mips_set_option_string (&mips_tune_string
, "4650");
14620 case OPTION_NO_M4650
:
14624 mips_set_option_string (&mips_arch_string
, "4010");
14625 mips_set_option_string (&mips_tune_string
, "4010");
14628 case OPTION_NO_M4010
:
14632 mips_set_option_string (&mips_arch_string
, "4100");
14633 mips_set_option_string (&mips_tune_string
, "4100");
14636 case OPTION_NO_M4100
:
14640 mips_set_option_string (&mips_arch_string
, "3900");
14641 mips_set_option_string (&mips_tune_string
, "3900");
14644 case OPTION_NO_M3900
:
14647 case OPTION_MICROMIPS
:
14648 if (file_mips_opts
.mips16
== 1)
14650 as_bad (_("-mmicromips cannot be used with -mips16"));
14653 file_mips_opts
.micromips
= 1;
14654 mips_no_prev_insn ();
14657 case OPTION_NO_MICROMIPS
:
14658 file_mips_opts
.micromips
= 0;
14659 mips_no_prev_insn ();
14662 case OPTION_MIPS16
:
14663 if (file_mips_opts
.micromips
== 1)
14665 as_bad (_("-mips16 cannot be used with -micromips"));
14668 file_mips_opts
.mips16
= 1;
14669 mips_no_prev_insn ();
14672 case OPTION_NO_MIPS16
:
14673 file_mips_opts
.mips16
= 0;
14674 mips_no_prev_insn ();
14677 case OPTION_FIX_24K
:
14681 case OPTION_NO_FIX_24K
:
14685 case OPTION_FIX_RM7000
:
14686 mips_fix_rm7000
= 1;
14689 case OPTION_NO_FIX_RM7000
:
14690 mips_fix_rm7000
= 0;
14693 case OPTION_FIX_LOONGSON2F_JUMP
:
14694 mips_fix_loongson2f_jump
= TRUE
;
14697 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14698 mips_fix_loongson2f_jump
= FALSE
;
14701 case OPTION_FIX_LOONGSON2F_NOP
:
14702 mips_fix_loongson2f_nop
= TRUE
;
14705 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14706 mips_fix_loongson2f_nop
= FALSE
;
14709 case OPTION_FIX_VR4120
:
14710 mips_fix_vr4120
= 1;
14713 case OPTION_NO_FIX_VR4120
:
14714 mips_fix_vr4120
= 0;
14717 case OPTION_FIX_VR4130
:
14718 mips_fix_vr4130
= 1;
14721 case OPTION_NO_FIX_VR4130
:
14722 mips_fix_vr4130
= 0;
14725 case OPTION_FIX_CN63XXP1
:
14726 mips_fix_cn63xxp1
= TRUE
;
14729 case OPTION_NO_FIX_CN63XXP1
:
14730 mips_fix_cn63xxp1
= FALSE
;
14733 case OPTION_RELAX_BRANCH
:
14734 mips_relax_branch
= 1;
14737 case OPTION_NO_RELAX_BRANCH
:
14738 mips_relax_branch
= 0;
14741 case OPTION_IGNORE_BRANCH_ISA
:
14742 mips_ignore_branch_isa
= TRUE
;
14745 case OPTION_NO_IGNORE_BRANCH_ISA
:
14746 mips_ignore_branch_isa
= FALSE
;
14749 case OPTION_INSN32
:
14750 file_mips_opts
.insn32
= TRUE
;
14753 case OPTION_NO_INSN32
:
14754 file_mips_opts
.insn32
= FALSE
;
14757 case OPTION_MSHARED
:
14758 mips_in_shared
= TRUE
;
14761 case OPTION_MNO_SHARED
:
14762 mips_in_shared
= FALSE
;
14765 case OPTION_MSYM32
:
14766 file_mips_opts
.sym32
= TRUE
;
14769 case OPTION_MNO_SYM32
:
14770 file_mips_opts
.sym32
= FALSE
;
14773 /* When generating ELF code, we permit -KPIC and -call_shared to
14774 select SVR4_PIC, and -non_shared to select no PIC. This is
14775 intended to be compatible with Irix 5. */
14776 case OPTION_CALL_SHARED
:
14777 mips_pic
= SVR4_PIC
;
14778 mips_abicalls
= TRUE
;
14781 case OPTION_CALL_NONPIC
:
14783 mips_abicalls
= TRUE
;
14786 case OPTION_NON_SHARED
:
14788 mips_abicalls
= FALSE
;
14791 /* The -xgot option tells the assembler to use 32 bit offsets
14792 when accessing the got in SVR4_PIC mode. It is for Irix
14799 g_switch_value
= atoi (arg
);
14803 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14806 mips_abi
= O32_ABI
;
14810 mips_abi
= N32_ABI
;
14814 mips_abi
= N64_ABI
;
14815 if (!support_64bit_objects())
14816 as_fatal (_("no compiled in support for 64 bit object file format"));
14820 file_mips_opts
.gp
= 32;
14824 file_mips_opts
.gp
= 64;
14828 file_mips_opts
.fp
= 32;
14832 file_mips_opts
.fp
= 0;
14836 file_mips_opts
.fp
= 64;
14839 case OPTION_ODD_SPREG
:
14840 file_mips_opts
.oddspreg
= 1;
14843 case OPTION_NO_ODD_SPREG
:
14844 file_mips_opts
.oddspreg
= 0;
14847 case OPTION_SINGLE_FLOAT
:
14848 file_mips_opts
.single_float
= 1;
14851 case OPTION_DOUBLE_FLOAT
:
14852 file_mips_opts
.single_float
= 0;
14855 case OPTION_SOFT_FLOAT
:
14856 file_mips_opts
.soft_float
= 1;
14859 case OPTION_HARD_FLOAT
:
14860 file_mips_opts
.soft_float
= 0;
14864 if (strcmp (arg
, "32") == 0)
14865 mips_abi
= O32_ABI
;
14866 else if (strcmp (arg
, "o64") == 0)
14867 mips_abi
= O64_ABI
;
14868 else if (strcmp (arg
, "n32") == 0)
14869 mips_abi
= N32_ABI
;
14870 else if (strcmp (arg
, "64") == 0)
14872 mips_abi
= N64_ABI
;
14873 if (! support_64bit_objects())
14874 as_fatal (_("no compiled in support for 64 bit object file "
14877 else if (strcmp (arg
, "eabi") == 0)
14878 mips_abi
= EABI_ABI
;
14881 as_fatal (_("invalid abi -mabi=%s"), arg
);
14886 case OPTION_M7000_HILO_FIX
:
14887 mips_7000_hilo_fix
= TRUE
;
14890 case OPTION_MNO_7000_HILO_FIX
:
14891 mips_7000_hilo_fix
= FALSE
;
14894 case OPTION_MDEBUG
:
14895 mips_flag_mdebug
= TRUE
;
14898 case OPTION_NO_MDEBUG
:
14899 mips_flag_mdebug
= FALSE
;
14903 mips_flag_pdr
= TRUE
;
14906 case OPTION_NO_PDR
:
14907 mips_flag_pdr
= FALSE
;
14910 case OPTION_MVXWORKS_PIC
:
14911 mips_pic
= VXWORKS_PIC
;
14915 if (strcmp (arg
, "2008") == 0)
14917 else if (strcmp (arg
, "legacy") == 0)
14921 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14930 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14935 /* Set up globals to tune for the ISA or processor described by INFO. */
14938 mips_set_tune (const struct mips_cpu_info
*info
)
14941 mips_tune
= info
->cpu
;
14946 mips_after_parse_args (void)
14948 const struct mips_cpu_info
*arch_info
= 0;
14949 const struct mips_cpu_info
*tune_info
= 0;
14951 /* GP relative stuff not working for PE */
14952 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14954 if (g_switch_seen
&& g_switch_value
!= 0)
14955 as_bad (_("-G not supported in this configuration"));
14956 g_switch_value
= 0;
14959 if (mips_abi
== NO_ABI
)
14960 mips_abi
= MIPS_DEFAULT_ABI
;
14962 /* The following code determines the architecture.
14963 Similar code was added to GCC 3.3 (see override_options() in
14964 config/mips/mips.c). The GAS and GCC code should be kept in sync
14965 as much as possible. */
14967 if (mips_arch_string
!= 0)
14968 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14970 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14972 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14973 ISA level specified by -mipsN, while arch_info->isa contains
14974 the -march selection (if any). */
14975 if (arch_info
!= 0)
14977 /* -march takes precedence over -mipsN, since it is more descriptive.
14978 There's no harm in specifying both as long as the ISA levels
14980 if (file_mips_opts
.isa
!= arch_info
->isa
)
14981 as_bad (_("-%s conflicts with the other architecture options,"
14982 " which imply -%s"),
14983 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14984 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14987 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14990 if (arch_info
== 0)
14992 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14993 gas_assert (arch_info
);
14996 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14997 as_bad (_("-march=%s is not compatible with the selected ABI"),
15000 file_mips_opts
.arch
= arch_info
->cpu
;
15001 file_mips_opts
.isa
= arch_info
->isa
;
15003 /* Set up initial mips_opts state. */
15004 mips_opts
= file_mips_opts
;
15006 /* The register size inference code is now placed in
15007 file_mips_check_options. */
15009 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15011 if (mips_tune_string
!= 0)
15012 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15014 if (tune_info
== 0)
15015 mips_set_tune (arch_info
);
15017 mips_set_tune (tune_info
);
15019 if (mips_flag_mdebug
< 0)
15020 mips_flag_mdebug
= 0;
15024 mips_init_after_args (void)
15026 /* initialize opcodes */
15027 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15028 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15032 md_pcrel_from (fixS
*fixP
)
15034 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15035 switch (fixP
->fx_r_type
)
15037 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15038 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15039 /* Return the address of the delay slot. */
15042 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15043 case BFD_RELOC_MICROMIPS_JMP
:
15044 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15045 case BFD_RELOC_16_PCREL_S2
:
15046 case BFD_RELOC_MIPS_21_PCREL_S2
:
15047 case BFD_RELOC_MIPS_26_PCREL_S2
:
15048 case BFD_RELOC_MIPS_JMP
:
15049 /* Return the address of the delay slot. */
15052 case BFD_RELOC_MIPS_18_PCREL_S3
:
15053 /* Return the aligned address of the doubleword containing
15054 the instruction. */
15062 /* This is called before the symbol table is processed. In order to
15063 work with gcc when using mips-tfile, we must keep all local labels.
15064 However, in other cases, we want to discard them. If we were
15065 called with -g, but we didn't see any debugging information, it may
15066 mean that gcc is smuggling debugging information through to
15067 mips-tfile, in which case we must generate all local labels. */
15070 mips_frob_file_before_adjust (void)
15072 #ifndef NO_ECOFF_DEBUGGING
15073 if (ECOFF_DEBUGGING
15075 && ! ecoff_debugging_seen
)
15076 flag_keep_locals
= 1;
15080 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15081 the corresponding LO16 reloc. This is called before md_apply_fix and
15082 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15083 relocation operators.
15085 For our purposes, a %lo() expression matches a %got() or %hi()
15088 (a) it refers to the same symbol; and
15089 (b) the offset applied in the %lo() expression is no lower than
15090 the offset applied in the %got() or %hi().
15092 (b) allows us to cope with code like:
15095 lh $4,%lo(foo+2)($4)
15097 ...which is legal on RELA targets, and has a well-defined behaviour
15098 if the user knows that adding 2 to "foo" will not induce a carry to
15101 When several %lo()s match a particular %got() or %hi(), we use the
15102 following rules to distinguish them:
15104 (1) %lo()s with smaller offsets are a better match than %lo()s with
15107 (2) %lo()s with no matching %got() or %hi() are better than those
15108 that already have a matching %got() or %hi().
15110 (3) later %lo()s are better than earlier %lo()s.
15112 These rules are applied in order.
15114 (1) means, among other things, that %lo()s with identical offsets are
15115 chosen if they exist.
15117 (2) means that we won't associate several high-part relocations with
15118 the same low-part relocation unless there's no alternative. Having
15119 several high parts for the same low part is a GNU extension; this rule
15120 allows careful users to avoid it.
15122 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15123 with the last high-part relocation being at the front of the list.
15124 It therefore makes sense to choose the last matching low-part
15125 relocation, all other things being equal. It's also easier
15126 to code that way. */
15129 mips_frob_file (void)
15131 struct mips_hi_fixup
*l
;
15132 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15134 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15136 segment_info_type
*seginfo
;
15137 bfd_boolean matched_lo_p
;
15138 fixS
**hi_pos
, **lo_pos
, **pos
;
15140 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15142 /* If a GOT16 relocation turns out to be against a global symbol,
15143 there isn't supposed to be a matching LO. Ignore %gots against
15144 constants; we'll report an error for those later. */
15145 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15146 && !(l
->fixp
->fx_addsy
15147 && pic_need_relax (l
->fixp
->fx_addsy
)))
15150 /* Check quickly whether the next fixup happens to be a matching %lo. */
15151 if (fixup_has_matching_lo_p (l
->fixp
))
15154 seginfo
= seg_info (l
->seg
);
15156 /* Set HI_POS to the position of this relocation in the chain.
15157 Set LO_POS to the position of the chosen low-part relocation.
15158 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15159 relocation that matches an immediately-preceding high-part
15163 matched_lo_p
= FALSE
;
15164 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15166 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15168 if (*pos
== l
->fixp
)
15171 if ((*pos
)->fx_r_type
== looking_for_rtype
15172 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15173 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15175 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15177 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15180 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15181 && fixup_has_matching_lo_p (*pos
));
15184 /* If we found a match, remove the high-part relocation from its
15185 current position and insert it before the low-part relocation.
15186 Make the offsets match so that fixup_has_matching_lo_p()
15189 We don't warn about unmatched high-part relocations since some
15190 versions of gcc have been known to emit dead "lui ...%hi(...)"
15192 if (lo_pos
!= NULL
)
15194 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15195 if (l
->fixp
->fx_next
!= *lo_pos
)
15197 *hi_pos
= l
->fixp
->fx_next
;
15198 l
->fixp
->fx_next
= *lo_pos
;
15206 mips_force_relocation (fixS
*fixp
)
15208 if (generic_force_reloc (fixp
))
15211 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15212 so that the linker relaxation can update targets. */
15213 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15214 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15215 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15218 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15219 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15220 microMIPS symbols so that we can do cross-mode branch diagnostics
15221 and BAL to JALX conversion by the linker. */
15222 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15223 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15224 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15226 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15229 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15230 if (ISA_IS_R6 (file_mips_opts
.isa
)
15231 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15232 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15233 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15234 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15235 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15236 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15237 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15243 /* Implement TC_FORCE_RELOCATION_ABS. */
15246 mips_force_relocation_abs (fixS
*fixp
)
15248 if (generic_force_reloc (fixp
))
15251 /* These relocations do not have enough bits in the in-place addend
15252 to hold an arbitrary absolute section's offset. */
15253 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15259 /* Read the instruction associated with RELOC from BUF. */
15261 static unsigned int
15262 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15264 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15265 return read_compressed_insn (buf
, 4);
15267 return read_insn (buf
);
15270 /* Write instruction INSN to BUF, given that it has been relocated
15274 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15275 unsigned long insn
)
15277 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15278 write_compressed_insn (buf
, insn
, 4);
15280 write_insn (buf
, insn
);
15283 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15284 to a symbol in another ISA mode, which cannot be converted to JALX. */
15287 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15289 unsigned long opcode
;
15293 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15296 other
= S_GET_OTHER (fixP
->fx_addsy
);
15297 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15298 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15299 switch (fixP
->fx_r_type
)
15301 case BFD_RELOC_MIPS_JMP
:
15302 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15303 case BFD_RELOC_MICROMIPS_JMP
:
15304 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15310 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15311 jump to a symbol in the same ISA mode. */
15314 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15316 unsigned long opcode
;
15320 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15323 other
= S_GET_OTHER (fixP
->fx_addsy
);
15324 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15325 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15326 switch (fixP
->fx_r_type
)
15328 case BFD_RELOC_MIPS_JMP
:
15329 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15330 case BFD_RELOC_MIPS16_JMP
:
15331 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15332 case BFD_RELOC_MICROMIPS_JMP
:
15333 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15339 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15340 to a symbol whose value plus addend is not aligned according to the
15341 ultimate (after linker relaxation) jump instruction's immediate field
15342 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15343 regular MIPS code, to (1 << 2). */
15346 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15348 bfd_boolean micro_to_mips_p
;
15352 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15355 other
= S_GET_OTHER (fixP
->fx_addsy
);
15356 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15357 val
+= fixP
->fx_offset
;
15358 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15359 && !ELF_ST_IS_MICROMIPS (other
));
15360 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15361 != ELF_ST_IS_COMPRESSED (other
));
15364 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15365 to a symbol whose annotation indicates another ISA mode. For absolute
15366 symbols check the ISA bit instead.
15368 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15369 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15370 MIPS symbols and associated with BAL instructions as these instructions
15371 may be converted to JALX by the linker. */
15374 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15376 bfd_boolean absolute_p
;
15377 unsigned long opcode
;
15383 if (mips_ignore_branch_isa
)
15386 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15389 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15390 absolute_p
= bfd_is_abs_section (symsec
);
15392 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15393 other
= S_GET_OTHER (fixP
->fx_addsy
);
15395 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15396 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15397 switch (fixP
->fx_r_type
)
15399 case BFD_RELOC_16_PCREL_S2
:
15400 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15401 && opcode
!= 0x0411);
15402 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15403 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15404 && opcode
!= 0x4060);
15405 case BFD_RELOC_MIPS_21_PCREL_S2
:
15406 case BFD_RELOC_MIPS_26_PCREL_S2
:
15407 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15408 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15409 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15410 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15411 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15412 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15418 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15419 branch instruction pointed to by FIXP is not aligned according to the
15420 branch instruction's immediate field requirement. We need the addend
15421 to preserve the ISA bit and also the sum must not have bit 2 set. We
15422 must explicitly OR in the ISA bit from symbol annotation as the bit
15423 won't be set in the symbol's value then. */
15426 fix_bad_misaligned_branch_p (fixS
*fixP
)
15428 bfd_boolean absolute_p
;
15435 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15438 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15439 absolute_p
= bfd_is_abs_section (symsec
);
15441 val
= S_GET_VALUE (fixP
->fx_addsy
);
15442 other
= S_GET_OTHER (fixP
->fx_addsy
);
15443 off
= fixP
->fx_offset
;
15445 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15446 val
|= ELF_ST_IS_COMPRESSED (other
);
15448 return (val
& 0x3) != isa_bit
;
15451 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15452 and its calculated value VAL. */
15455 fix_validate_branch (fixS
*fixP
, valueT val
)
15457 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15459 _("branch to misaligned address (0x%lx)"),
15460 (long) (val
+ md_pcrel_from (fixP
)));
15461 else if (fix_bad_cross_mode_branch_p (fixP
))
15462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15463 _("branch to a symbol in another ISA mode"));
15464 else if (fix_bad_misaligned_branch_p (fixP
))
15465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15466 _("branch to misaligned address (0x%lx)"),
15467 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15468 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15470 _("cannot encode misaligned addend "
15471 "in the relocatable field (0x%lx)"),
15472 (long) fixP
->fx_offset
);
15475 /* Apply a fixup to the object file. */
15478 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15481 unsigned long insn
;
15482 reloc_howto_type
*howto
;
15484 if (fixP
->fx_pcrel
)
15485 switch (fixP
->fx_r_type
)
15487 case BFD_RELOC_16_PCREL_S2
:
15488 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15489 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15490 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15491 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15492 case BFD_RELOC_32_PCREL
:
15493 case BFD_RELOC_MIPS_21_PCREL_S2
:
15494 case BFD_RELOC_MIPS_26_PCREL_S2
:
15495 case BFD_RELOC_MIPS_18_PCREL_S3
:
15496 case BFD_RELOC_MIPS_19_PCREL_S2
:
15497 case BFD_RELOC_HI16_S_PCREL
:
15498 case BFD_RELOC_LO16_PCREL
:
15502 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15507 _("PC-relative reference to a different section"));
15511 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15512 that have no MIPS ELF equivalent. */
15513 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15515 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15520 gas_assert (fixP
->fx_size
== 2
15521 || fixP
->fx_size
== 4
15522 || fixP
->fx_r_type
== BFD_RELOC_8
15523 || fixP
->fx_r_type
== BFD_RELOC_16
15524 || fixP
->fx_r_type
== BFD_RELOC_64
15525 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15526 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15527 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15528 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15529 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15530 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15531 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15533 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15535 /* Don't treat parts of a composite relocation as done. There are two
15538 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15539 should nevertheless be emitted if the first part is.
15541 (2) In normal usage, composite relocations are never assembly-time
15542 constants. The easiest way of dealing with the pathological
15543 exceptions is to generate a relocation against STN_UNDEF and
15544 leave everything up to the linker. */
15545 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15548 switch (fixP
->fx_r_type
)
15550 case BFD_RELOC_MIPS_TLS_GD
:
15551 case BFD_RELOC_MIPS_TLS_LDM
:
15552 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15553 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15554 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15555 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15556 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15557 case BFD_RELOC_MIPS_TLS_TPREL32
:
15558 case BFD_RELOC_MIPS_TLS_TPREL64
:
15559 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15560 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15561 case BFD_RELOC_MICROMIPS_TLS_GD
:
15562 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15563 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15564 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15565 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15566 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15567 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15568 case BFD_RELOC_MIPS16_TLS_GD
:
15569 case BFD_RELOC_MIPS16_TLS_LDM
:
15570 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15571 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15572 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15573 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15574 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15575 if (fixP
->fx_addsy
)
15576 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15579 _("TLS relocation against a constant"));
15582 case BFD_RELOC_MIPS_JMP
:
15583 case BFD_RELOC_MIPS16_JMP
:
15584 case BFD_RELOC_MICROMIPS_JMP
:
15588 gas_assert (!fixP
->fx_done
);
15590 /* Shift is 2, unusually, for microMIPS JALX. */
15591 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15592 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15597 if (fix_bad_cross_mode_jump_p (fixP
))
15598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15599 _("jump to a symbol in another ISA mode"));
15600 else if (fix_bad_same_mode_jalx_p (fixP
))
15601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15602 _("JALX to a symbol in the same ISA mode"));
15603 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15605 _("jump to misaligned address (0x%lx)"),
15606 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15607 + fixP
->fx_offset
));
15608 else if (HAVE_IN_PLACE_ADDENDS
15609 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15611 _("cannot encode misaligned addend "
15612 "in the relocatable field (0x%lx)"),
15613 (long) fixP
->fx_offset
);
15615 /* Fall through. */
15617 case BFD_RELOC_MIPS_SHIFT5
:
15618 case BFD_RELOC_MIPS_SHIFT6
:
15619 case BFD_RELOC_MIPS_GOT_DISP
:
15620 case BFD_RELOC_MIPS_GOT_PAGE
:
15621 case BFD_RELOC_MIPS_GOT_OFST
:
15622 case BFD_RELOC_MIPS_SUB
:
15623 case BFD_RELOC_MIPS_INSERT_A
:
15624 case BFD_RELOC_MIPS_INSERT_B
:
15625 case BFD_RELOC_MIPS_DELETE
:
15626 case BFD_RELOC_MIPS_HIGHEST
:
15627 case BFD_RELOC_MIPS_HIGHER
:
15628 case BFD_RELOC_MIPS_SCN_DISP
:
15629 case BFD_RELOC_MIPS_REL16
:
15630 case BFD_RELOC_MIPS_RELGOT
:
15631 case BFD_RELOC_MIPS_JALR
:
15632 case BFD_RELOC_HI16
:
15633 case BFD_RELOC_HI16_S
:
15634 case BFD_RELOC_LO16
:
15635 case BFD_RELOC_GPREL16
:
15636 case BFD_RELOC_MIPS_LITERAL
:
15637 case BFD_RELOC_MIPS_CALL16
:
15638 case BFD_RELOC_MIPS_GOT16
:
15639 case BFD_RELOC_GPREL32
:
15640 case BFD_RELOC_MIPS_GOT_HI16
:
15641 case BFD_RELOC_MIPS_GOT_LO16
:
15642 case BFD_RELOC_MIPS_CALL_HI16
:
15643 case BFD_RELOC_MIPS_CALL_LO16
:
15644 case BFD_RELOC_HI16_S_PCREL
:
15645 case BFD_RELOC_LO16_PCREL
:
15646 case BFD_RELOC_MIPS16_GPREL
:
15647 case BFD_RELOC_MIPS16_GOT16
:
15648 case BFD_RELOC_MIPS16_CALL16
:
15649 case BFD_RELOC_MIPS16_HI16
:
15650 case BFD_RELOC_MIPS16_HI16_S
:
15651 case BFD_RELOC_MIPS16_LO16
:
15652 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15653 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15654 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15655 case BFD_RELOC_MICROMIPS_SUB
:
15656 case BFD_RELOC_MICROMIPS_HIGHEST
:
15657 case BFD_RELOC_MICROMIPS_HIGHER
:
15658 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15659 case BFD_RELOC_MICROMIPS_JALR
:
15660 case BFD_RELOC_MICROMIPS_HI16
:
15661 case BFD_RELOC_MICROMIPS_HI16_S
:
15662 case BFD_RELOC_MICROMIPS_LO16
:
15663 case BFD_RELOC_MICROMIPS_GPREL16
:
15664 case BFD_RELOC_MICROMIPS_LITERAL
:
15665 case BFD_RELOC_MICROMIPS_CALL16
:
15666 case BFD_RELOC_MICROMIPS_GOT16
:
15667 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15668 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15669 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15670 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15671 case BFD_RELOC_MIPS_EH
:
15676 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15678 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15679 if (mips16_reloc_p (fixP
->fx_r_type
))
15680 insn
|= mips16_immed_extend (value
, 16);
15682 insn
|= (value
& 0xffff);
15683 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15687 _("unsupported constant in relocation"));
15692 /* This is handled like BFD_RELOC_32, but we output a sign
15693 extended value if we are only 32 bits. */
15696 if (8 <= sizeof (valueT
))
15697 md_number_to_chars (buf
, *valP
, 8);
15702 if ((*valP
& 0x80000000) != 0)
15706 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15707 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15712 case BFD_RELOC_RVA
:
15714 case BFD_RELOC_32_PCREL
:
15717 /* If we are deleting this reloc entry, we must fill in the
15718 value now. This can happen if we have a .word which is not
15719 resolved when it appears but is later defined. */
15721 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15724 case BFD_RELOC_MIPS_21_PCREL_S2
:
15725 fix_validate_branch (fixP
, *valP
);
15726 if (!fixP
->fx_done
)
15729 if (*valP
+ 0x400000 <= 0x7fffff)
15731 insn
= read_insn (buf
);
15732 insn
|= (*valP
>> 2) & 0x1fffff;
15733 write_insn (buf
, insn
);
15736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15737 _("branch out of range"));
15740 case BFD_RELOC_MIPS_26_PCREL_S2
:
15741 fix_validate_branch (fixP
, *valP
);
15742 if (!fixP
->fx_done
)
15745 if (*valP
+ 0x8000000 <= 0xfffffff)
15747 insn
= read_insn (buf
);
15748 insn
|= (*valP
>> 2) & 0x3ffffff;
15749 write_insn (buf
, insn
);
15752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15753 _("branch out of range"));
15756 case BFD_RELOC_MIPS_18_PCREL_S3
:
15757 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15759 _("PC-relative access using misaligned symbol (%lx)"),
15760 (long) S_GET_VALUE (fixP
->fx_addsy
));
15761 if ((fixP
->fx_offset
& 0x7) != 0)
15762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15763 _("PC-relative access using misaligned offset (%lx)"),
15764 (long) fixP
->fx_offset
);
15765 if (!fixP
->fx_done
)
15768 if (*valP
+ 0x100000 <= 0x1fffff)
15770 insn
= read_insn (buf
);
15771 insn
|= (*valP
>> 3) & 0x3ffff;
15772 write_insn (buf
, insn
);
15775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15776 _("PC-relative access out of range"));
15779 case BFD_RELOC_MIPS_19_PCREL_S2
:
15780 if ((*valP
& 0x3) != 0)
15781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15782 _("PC-relative access to misaligned address (%lx)"),
15784 if (!fixP
->fx_done
)
15787 if (*valP
+ 0x100000 <= 0x1fffff)
15789 insn
= read_insn (buf
);
15790 insn
|= (*valP
>> 2) & 0x7ffff;
15791 write_insn (buf
, insn
);
15794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15795 _("PC-relative access out of range"));
15798 case BFD_RELOC_16_PCREL_S2
:
15799 fix_validate_branch (fixP
, *valP
);
15801 /* We need to save the bits in the instruction since fixup_segment()
15802 might be deleting the relocation entry (i.e., a branch within
15803 the current segment). */
15804 if (! fixP
->fx_done
)
15807 /* Update old instruction data. */
15808 insn
= read_insn (buf
);
15810 if (*valP
+ 0x20000 <= 0x3ffff)
15812 insn
|= (*valP
>> 2) & 0xffff;
15813 write_insn (buf
, insn
);
15815 else if (fixP
->fx_tcbit2
15817 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15818 && (fixP
->fx_frag
->fr_address
15819 < text_section
->vma
+ bfd_get_section_size (text_section
))
15820 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15821 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15822 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15824 /* The branch offset is too large. If this is an
15825 unconditional branch, and we are not generating PIC code,
15826 we can convert it to an absolute jump instruction. */
15827 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15828 insn
= 0x0c000000; /* jal */
15830 insn
= 0x08000000; /* j */
15831 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15833 fixP
->fx_addsy
= section_symbol (text_section
);
15834 *valP
+= md_pcrel_from (fixP
);
15835 write_insn (buf
, insn
);
15839 /* If we got here, we have branch-relaxation disabled,
15840 and there's nothing we can do to fix this instruction
15841 without turning it into a longer sequence. */
15842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15843 _("branch out of range"));
15847 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15848 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15849 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15850 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15851 gas_assert (!fixP
->fx_done
);
15852 if (fix_bad_cross_mode_branch_p (fixP
))
15853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15854 _("branch to a symbol in another ISA mode"));
15855 else if (fixP
->fx_addsy
15856 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15857 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15858 && (fixP
->fx_offset
& 0x1) != 0)
15859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15860 _("branch to misaligned address (0x%lx)"),
15861 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15862 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15864 _("cannot encode misaligned addend "
15865 "in the relocatable field (0x%lx)"),
15866 (long) fixP
->fx_offset
);
15869 case BFD_RELOC_VTABLE_INHERIT
:
15872 && !S_IS_DEFINED (fixP
->fx_addsy
)
15873 && !S_IS_WEAK (fixP
->fx_addsy
))
15874 S_SET_WEAK (fixP
->fx_addsy
);
15877 case BFD_RELOC_NONE
:
15878 case BFD_RELOC_VTABLE_ENTRY
:
15886 /* Remember value for tc_gen_reloc. */
15887 fixP
->fx_addnumber
= *valP
;
15897 c
= get_symbol_name (&name
);
15898 p
= (symbolS
*) symbol_find_or_make (name
);
15899 (void) restore_line_pointer (c
);
15903 /* Align the current frag to a given power of two. If a particular
15904 fill byte should be used, FILL points to an integer that contains
15905 that byte, otherwise FILL is null.
15907 This function used to have the comment:
15909 The MIPS assembler also automatically adjusts any preceding label.
15911 The implementation therefore applied the adjustment to a maximum of
15912 one label. However, other label adjustments are applied to batches
15913 of labels, and adjusting just one caused problems when new labels
15914 were added for the sake of debugging or unwind information.
15915 We therefore adjust all preceding labels (given as LABELS) instead. */
15918 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15920 mips_emit_delays ();
15921 mips_record_compressed_mode ();
15922 if (fill
== NULL
&& subseg_text_p (now_seg
))
15923 frag_align_code (to
, 0);
15925 frag_align (to
, fill
? *fill
: 0, 0);
15926 record_alignment (now_seg
, to
);
15927 mips_move_labels (labels
, FALSE
);
15930 /* Align to a given power of two. .align 0 turns off the automatic
15931 alignment used by the data creating pseudo-ops. */
15934 s_align (int x ATTRIBUTE_UNUSED
)
15936 int temp
, fill_value
, *fill_ptr
;
15937 long max_alignment
= 28;
15939 /* o Note that the assembler pulls down any immediately preceding label
15940 to the aligned address.
15941 o It's not documented but auto alignment is reinstated by
15942 a .align pseudo instruction.
15943 o Note also that after auto alignment is turned off the mips assembler
15944 issues an error on attempt to assemble an improperly aligned data item.
15947 temp
= get_absolute_expression ();
15948 if (temp
> max_alignment
)
15949 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15952 as_warn (_("alignment negative, 0 assumed"));
15955 if (*input_line_pointer
== ',')
15957 ++input_line_pointer
;
15958 fill_value
= get_absolute_expression ();
15959 fill_ptr
= &fill_value
;
15965 segment_info_type
*si
= seg_info (now_seg
);
15966 struct insn_label_list
*l
= si
->label_list
;
15967 /* Auto alignment should be switched on by next section change. */
15969 mips_align (temp
, fill_ptr
, l
);
15976 demand_empty_rest_of_line ();
15980 s_change_sec (int sec
)
15984 /* The ELF backend needs to know that we are changing sections, so
15985 that .previous works correctly. We could do something like check
15986 for an obj_section_change_hook macro, but that might be confusing
15987 as it would not be appropriate to use it in the section changing
15988 functions in read.c, since obj-elf.c intercepts those. FIXME:
15989 This should be cleaner, somehow. */
15990 obj_elf_section_change_hook ();
15992 mips_emit_delays ();
16003 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16004 demand_empty_rest_of_line ();
16008 seg
= subseg_new (RDATA_SECTION_NAME
,
16009 (subsegT
) get_absolute_expression ());
16010 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16011 | SEC_READONLY
| SEC_RELOC
16013 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16014 record_alignment (seg
, 4);
16015 demand_empty_rest_of_line ();
16019 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16020 bfd_set_section_flags (stdoutput
, seg
,
16021 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16022 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16023 record_alignment (seg
, 4);
16024 demand_empty_rest_of_line ();
16028 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16029 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16030 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16031 record_alignment (seg
, 4);
16032 demand_empty_rest_of_line ();
16040 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16043 char *section_name
;
16048 int section_entry_size
;
16049 int section_alignment
;
16051 saved_ilp
= input_line_pointer
;
16052 endc
= get_symbol_name (§ion_name
);
16053 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16055 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16057 /* Do we have .section Name<,"flags">? */
16058 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16060 /* Just after name is now '\0'. */
16061 (void) restore_line_pointer (endc
);
16062 input_line_pointer
= saved_ilp
;
16063 obj_elf_section (ignore
);
16067 section_name
= xstrdup (section_name
);
16068 c
= restore_line_pointer (endc
);
16070 input_line_pointer
++;
16072 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16074 section_type
= get_absolute_expression ();
16078 if (*input_line_pointer
++ == ',')
16079 section_flag
= get_absolute_expression ();
16083 if (*input_line_pointer
++ == ',')
16084 section_entry_size
= get_absolute_expression ();
16086 section_entry_size
= 0;
16088 if (*input_line_pointer
++ == ',')
16089 section_alignment
= get_absolute_expression ();
16091 section_alignment
= 0;
16093 /* FIXME: really ignore? */
16094 (void) section_alignment
;
16096 /* When using the generic form of .section (as implemented by obj-elf.c),
16097 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16098 traditionally had to fall back on the more common @progbits instead.
16100 There's nothing really harmful in this, since bfd will correct
16101 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16102 means that, for backwards compatibility, the special_section entries
16103 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16105 Even so, we shouldn't force users of the MIPS .section syntax to
16106 incorrectly label the sections as SHT_PROGBITS. The best compromise
16107 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16108 generic type-checking code. */
16109 if (section_type
== SHT_MIPS_DWARF
)
16110 section_type
= SHT_PROGBITS
;
16112 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16113 section_entry_size
, 0, 0, 0);
16115 if (now_seg
->name
!= section_name
)
16116 free (section_name
);
16120 mips_enable_auto_align (void)
16126 s_cons (int log_size
)
16128 segment_info_type
*si
= seg_info (now_seg
);
16129 struct insn_label_list
*l
= si
->label_list
;
16131 mips_emit_delays ();
16132 if (log_size
> 0 && auto_align
)
16133 mips_align (log_size
, 0, l
);
16134 cons (1 << log_size
);
16135 mips_clear_insn_labels ();
16139 s_float_cons (int type
)
16141 segment_info_type
*si
= seg_info (now_seg
);
16142 struct insn_label_list
*l
= si
->label_list
;
16144 mips_emit_delays ();
16149 mips_align (3, 0, l
);
16151 mips_align (2, 0, l
);
16155 mips_clear_insn_labels ();
16158 /* Handle .globl. We need to override it because on Irix 5 you are
16161 where foo is an undefined symbol, to mean that foo should be
16162 considered to be the address of a function. */
16165 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16174 c
= get_symbol_name (&name
);
16175 symbolP
= symbol_find_or_make (name
);
16176 S_SET_EXTERNAL (symbolP
);
16178 *input_line_pointer
= c
;
16179 SKIP_WHITESPACE_AFTER_NAME ();
16181 /* On Irix 5, every global symbol that is not explicitly labelled as
16182 being a function is apparently labelled as being an object. */
16185 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16186 && (*input_line_pointer
!= ','))
16191 c
= get_symbol_name (&secname
);
16192 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16194 as_bad (_("%s: no such section"), secname
);
16195 (void) restore_line_pointer (c
);
16197 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16198 flag
= BSF_FUNCTION
;
16201 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16203 c
= *input_line_pointer
;
16206 input_line_pointer
++;
16207 SKIP_WHITESPACE ();
16208 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16214 demand_empty_rest_of_line ();
16218 s_option (int x ATTRIBUTE_UNUSED
)
16223 c
= get_symbol_name (&opt
);
16227 /* FIXME: What does this mean? */
16229 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16233 i
= atoi (opt
+ 3);
16234 if (i
!= 0 && i
!= 2)
16235 as_bad (_(".option pic%d not supported"), i
);
16236 else if (mips_pic
== VXWORKS_PIC
)
16237 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16242 mips_pic
= SVR4_PIC
;
16243 mips_abicalls
= TRUE
;
16246 if (mips_pic
== SVR4_PIC
)
16248 if (g_switch_seen
&& g_switch_value
!= 0)
16249 as_warn (_("-G may not be used with SVR4 PIC code"));
16250 g_switch_value
= 0;
16251 bfd_set_gp_size (stdoutput
, 0);
16255 as_warn (_("unrecognized option \"%s\""), opt
);
16257 (void) restore_line_pointer (c
);
16258 demand_empty_rest_of_line ();
16261 /* This structure is used to hold a stack of .set values. */
16263 struct mips_option_stack
16265 struct mips_option_stack
*next
;
16266 struct mips_set_options options
;
16269 static struct mips_option_stack
*mips_opts_stack
;
16271 /* Return status for .set/.module option handling. */
16273 enum code_option_type
16275 /* Unrecognized option. */
16276 OPTION_TYPE_BAD
= -1,
16278 /* Ordinary option. */
16279 OPTION_TYPE_NORMAL
,
16281 /* ISA changing option. */
16285 /* Handle common .set/.module options. Return status indicating option
16288 static enum code_option_type
16289 parse_code_option (char * name
)
16291 bfd_boolean isa_set
= FALSE
;
16292 const struct mips_ase
*ase
;
16294 if (strncmp (name
, "at=", 3) == 0)
16296 char *s
= name
+ 3;
16298 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16299 as_bad (_("unrecognized register name `%s'"), s
);
16301 else if (strcmp (name
, "at") == 0)
16302 mips_opts
.at
= ATREG
;
16303 else if (strcmp (name
, "noat") == 0)
16304 mips_opts
.at
= ZERO
;
16305 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16306 mips_opts
.nomove
= 0;
16307 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16308 mips_opts
.nomove
= 1;
16309 else if (strcmp (name
, "bopt") == 0)
16310 mips_opts
.nobopt
= 0;
16311 else if (strcmp (name
, "nobopt") == 0)
16312 mips_opts
.nobopt
= 1;
16313 else if (strcmp (name
, "gp=32") == 0)
16315 else if (strcmp (name
, "gp=64") == 0)
16317 else if (strcmp (name
, "fp=32") == 0)
16319 else if (strcmp (name
, "fp=xx") == 0)
16321 else if (strcmp (name
, "fp=64") == 0)
16323 else if (strcmp (name
, "softfloat") == 0)
16324 mips_opts
.soft_float
= 1;
16325 else if (strcmp (name
, "hardfloat") == 0)
16326 mips_opts
.soft_float
= 0;
16327 else if (strcmp (name
, "singlefloat") == 0)
16328 mips_opts
.single_float
= 1;
16329 else if (strcmp (name
, "doublefloat") == 0)
16330 mips_opts
.single_float
= 0;
16331 else if (strcmp (name
, "nooddspreg") == 0)
16332 mips_opts
.oddspreg
= 0;
16333 else if (strcmp (name
, "oddspreg") == 0)
16334 mips_opts
.oddspreg
= 1;
16335 else if (strcmp (name
, "mips16") == 0
16336 || strcmp (name
, "MIPS-16") == 0)
16337 mips_opts
.mips16
= 1;
16338 else if (strcmp (name
, "nomips16") == 0
16339 || strcmp (name
, "noMIPS-16") == 0)
16340 mips_opts
.mips16
= 0;
16341 else if (strcmp (name
, "micromips") == 0)
16342 mips_opts
.micromips
= 1;
16343 else if (strcmp (name
, "nomicromips") == 0)
16344 mips_opts
.micromips
= 0;
16345 else if (name
[0] == 'n'
16347 && (ase
= mips_lookup_ase (name
+ 2)))
16348 mips_set_ase (ase
, &mips_opts
, FALSE
);
16349 else if ((ase
= mips_lookup_ase (name
)))
16350 mips_set_ase (ase
, &mips_opts
, TRUE
);
16351 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16353 /* Permit the user to change the ISA and architecture on the fly.
16354 Needless to say, misuse can cause serious problems. */
16355 if (strncmp (name
, "arch=", 5) == 0)
16357 const struct mips_cpu_info
*p
;
16359 p
= mips_parse_cpu ("internal use", name
+ 5);
16361 as_bad (_("unknown architecture %s"), name
+ 5);
16364 mips_opts
.arch
= p
->cpu
;
16365 mips_opts
.isa
= p
->isa
;
16369 else if (strncmp (name
, "mips", 4) == 0)
16371 const struct mips_cpu_info
*p
;
16373 p
= mips_parse_cpu ("internal use", name
);
16375 as_bad (_("unknown ISA level %s"), name
+ 4);
16378 mips_opts
.arch
= p
->cpu
;
16379 mips_opts
.isa
= p
->isa
;
16384 as_bad (_("unknown ISA or architecture %s"), name
);
16386 else if (strcmp (name
, "autoextend") == 0)
16387 mips_opts
.noautoextend
= 0;
16388 else if (strcmp (name
, "noautoextend") == 0)
16389 mips_opts
.noautoextend
= 1;
16390 else if (strcmp (name
, "insn32") == 0)
16391 mips_opts
.insn32
= TRUE
;
16392 else if (strcmp (name
, "noinsn32") == 0)
16393 mips_opts
.insn32
= FALSE
;
16394 else if (strcmp (name
, "sym32") == 0)
16395 mips_opts
.sym32
= TRUE
;
16396 else if (strcmp (name
, "nosym32") == 0)
16397 mips_opts
.sym32
= FALSE
;
16399 return OPTION_TYPE_BAD
;
16401 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16404 /* Handle the .set pseudo-op. */
16407 s_mipsset (int x ATTRIBUTE_UNUSED
)
16409 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16410 char *name
= input_line_pointer
, ch
;
16412 file_mips_check_options ();
16414 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16415 ++input_line_pointer
;
16416 ch
= *input_line_pointer
;
16417 *input_line_pointer
= '\0';
16419 if (strchr (name
, ','))
16421 /* Generic ".set" directive; use the generic handler. */
16422 *input_line_pointer
= ch
;
16423 input_line_pointer
= name
;
16428 if (strcmp (name
, "reorder") == 0)
16430 if (mips_opts
.noreorder
)
16433 else if (strcmp (name
, "noreorder") == 0)
16435 if (!mips_opts
.noreorder
)
16436 start_noreorder ();
16438 else if (strcmp (name
, "macro") == 0)
16439 mips_opts
.warn_about_macros
= 0;
16440 else if (strcmp (name
, "nomacro") == 0)
16442 if (mips_opts
.noreorder
== 0)
16443 as_bad (_("`noreorder' must be set before `nomacro'"));
16444 mips_opts
.warn_about_macros
= 1;
16446 else if (strcmp (name
, "gp=default") == 0)
16447 mips_opts
.gp
= file_mips_opts
.gp
;
16448 else if (strcmp (name
, "fp=default") == 0)
16449 mips_opts
.fp
= file_mips_opts
.fp
;
16450 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16452 mips_opts
.isa
= file_mips_opts
.isa
;
16453 mips_opts
.arch
= file_mips_opts
.arch
;
16454 mips_opts
.gp
= file_mips_opts
.gp
;
16455 mips_opts
.fp
= file_mips_opts
.fp
;
16457 else if (strcmp (name
, "push") == 0)
16459 struct mips_option_stack
*s
;
16461 s
= XNEW (struct mips_option_stack
);
16462 s
->next
= mips_opts_stack
;
16463 s
->options
= mips_opts
;
16464 mips_opts_stack
= s
;
16466 else if (strcmp (name
, "pop") == 0)
16468 struct mips_option_stack
*s
;
16470 s
= mips_opts_stack
;
16472 as_bad (_(".set pop with no .set push"));
16475 /* If we're changing the reorder mode we need to handle
16476 delay slots correctly. */
16477 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16478 start_noreorder ();
16479 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16482 mips_opts
= s
->options
;
16483 mips_opts_stack
= s
->next
;
16489 type
= parse_code_option (name
);
16490 if (type
== OPTION_TYPE_BAD
)
16491 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16494 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16495 registers based on what is supported by the arch/cpu. */
16496 if (type
== OPTION_TYPE_ISA
)
16498 switch (mips_opts
.isa
)
16503 /* MIPS I cannot support FPXX. */
16505 /* fall-through. */
16512 if (mips_opts
.fp
!= 0)
16528 if (mips_opts
.fp
!= 0)
16530 if (mips_opts
.arch
== CPU_R5900
)
16537 as_bad (_("unknown ISA level %s"), name
+ 4);
16542 mips_check_options (&mips_opts
, FALSE
);
16544 mips_check_isa_supports_ases ();
16545 *input_line_pointer
= ch
;
16546 demand_empty_rest_of_line ();
16549 /* Handle the .module pseudo-op. */
16552 s_module (int ignore ATTRIBUTE_UNUSED
)
16554 char *name
= input_line_pointer
, ch
;
16556 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16557 ++input_line_pointer
;
16558 ch
= *input_line_pointer
;
16559 *input_line_pointer
= '\0';
16561 if (!file_mips_opts_checked
)
16563 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16564 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16566 /* Update module level settings from mips_opts. */
16567 file_mips_opts
= mips_opts
;
16570 as_bad (_(".module is not permitted after generating code"));
16572 *input_line_pointer
= ch
;
16573 demand_empty_rest_of_line ();
16576 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16577 .option pic2. It means to generate SVR4 PIC calls. */
16580 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16582 mips_pic
= SVR4_PIC
;
16583 mips_abicalls
= TRUE
;
16585 if (g_switch_seen
&& g_switch_value
!= 0)
16586 as_warn (_("-G may not be used with SVR4 PIC code"));
16587 g_switch_value
= 0;
16589 bfd_set_gp_size (stdoutput
, 0);
16590 demand_empty_rest_of_line ();
16593 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16594 PIC code. It sets the $gp register for the function based on the
16595 function address, which is in the register named in the argument.
16596 This uses a relocation against _gp_disp, which is handled specially
16597 by the linker. The result is:
16598 lui $gp,%hi(_gp_disp)
16599 addiu $gp,$gp,%lo(_gp_disp)
16600 addu $gp,$gp,.cpload argument
16601 The .cpload argument is normally $25 == $t9.
16603 The -mno-shared option changes this to:
16604 lui $gp,%hi(__gnu_local_gp)
16605 addiu $gp,$gp,%lo(__gnu_local_gp)
16606 and the argument is ignored. This saves an instruction, but the
16607 resulting code is not position independent; it uses an absolute
16608 address for __gnu_local_gp. Thus code assembled with -mno-shared
16609 can go into an ordinary executable, but not into a shared library. */
16612 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16618 file_mips_check_options ();
16620 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16621 .cpload is ignored. */
16622 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16628 if (mips_opts
.mips16
)
16630 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16631 ignore_rest_of_line ();
16635 /* .cpload should be in a .set noreorder section. */
16636 if (mips_opts
.noreorder
== 0)
16637 as_warn (_(".cpload not in noreorder section"));
16639 reg
= tc_get_register (0);
16641 /* If we need to produce a 64-bit address, we are better off using
16642 the default instruction sequence. */
16643 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16645 ex
.X_op
= O_symbol
;
16646 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16648 ex
.X_op_symbol
= NULL
;
16649 ex
.X_add_number
= 0;
16651 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16652 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16654 mips_mark_labels ();
16655 mips_assembling_insn
= TRUE
;
16658 macro_build_lui (&ex
, mips_gp_register
);
16659 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16660 mips_gp_register
, BFD_RELOC_LO16
);
16662 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16663 mips_gp_register
, reg
);
16666 mips_assembling_insn
= FALSE
;
16667 demand_empty_rest_of_line ();
16670 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16671 .cpsetup $reg1, offset|$reg2, label
16673 If offset is given, this results in:
16674 sd $gp, offset($sp)
16675 lui $gp, %hi(%neg(%gp_rel(label)))
16676 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16677 daddu $gp, $gp, $reg1
16679 If $reg2 is given, this results in:
16681 lui $gp, %hi(%neg(%gp_rel(label)))
16682 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16683 daddu $gp, $gp, $reg1
16684 $reg1 is normally $25 == $t9.
16686 The -mno-shared option replaces the last three instructions with
16688 addiu $gp,$gp,%lo(_gp) */
16691 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16693 expressionS ex_off
;
16694 expressionS ex_sym
;
16697 file_mips_check_options ();
16699 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16700 We also need NewABI support. */
16701 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16707 if (mips_opts
.mips16
)
16709 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16710 ignore_rest_of_line ();
16714 reg1
= tc_get_register (0);
16715 SKIP_WHITESPACE ();
16716 if (*input_line_pointer
!= ',')
16718 as_bad (_("missing argument separator ',' for .cpsetup"));
16722 ++input_line_pointer
;
16723 SKIP_WHITESPACE ();
16724 if (*input_line_pointer
== '$')
16726 mips_cpreturn_register
= tc_get_register (0);
16727 mips_cpreturn_offset
= -1;
16731 mips_cpreturn_offset
= get_absolute_expression ();
16732 mips_cpreturn_register
= -1;
16734 SKIP_WHITESPACE ();
16735 if (*input_line_pointer
!= ',')
16737 as_bad (_("missing argument separator ',' for .cpsetup"));
16741 ++input_line_pointer
;
16742 SKIP_WHITESPACE ();
16743 expression (&ex_sym
);
16745 mips_mark_labels ();
16746 mips_assembling_insn
= TRUE
;
16749 if (mips_cpreturn_register
== -1)
16751 ex_off
.X_op
= O_constant
;
16752 ex_off
.X_add_symbol
= NULL
;
16753 ex_off
.X_op_symbol
= NULL
;
16754 ex_off
.X_add_number
= mips_cpreturn_offset
;
16756 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16757 BFD_RELOC_LO16
, SP
);
16760 move_register (mips_cpreturn_register
, mips_gp_register
);
16762 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16764 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16765 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16768 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16769 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16770 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16772 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16773 mips_gp_register
, reg1
);
16779 ex
.X_op
= O_symbol
;
16780 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16781 ex
.X_op_symbol
= NULL
;
16782 ex
.X_add_number
= 0;
16784 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16785 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16787 macro_build_lui (&ex
, mips_gp_register
);
16788 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16789 mips_gp_register
, BFD_RELOC_LO16
);
16794 mips_assembling_insn
= FALSE
;
16795 demand_empty_rest_of_line ();
16799 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16801 file_mips_check_options ();
16803 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16804 .cplocal is ignored. */
16805 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16811 if (mips_opts
.mips16
)
16813 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16814 ignore_rest_of_line ();
16818 mips_gp_register
= tc_get_register (0);
16819 demand_empty_rest_of_line ();
16822 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16823 offset from $sp. The offset is remembered, and after making a PIC
16824 call $gp is restored from that location. */
16827 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16831 file_mips_check_options ();
16833 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16834 .cprestore is ignored. */
16835 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16841 if (mips_opts
.mips16
)
16843 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16844 ignore_rest_of_line ();
16848 mips_cprestore_offset
= get_absolute_expression ();
16849 mips_cprestore_valid
= 1;
16851 ex
.X_op
= O_constant
;
16852 ex
.X_add_symbol
= NULL
;
16853 ex
.X_op_symbol
= NULL
;
16854 ex
.X_add_number
= mips_cprestore_offset
;
16856 mips_mark_labels ();
16857 mips_assembling_insn
= TRUE
;
16860 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16861 SP
, HAVE_64BIT_ADDRESSES
);
16864 mips_assembling_insn
= FALSE
;
16865 demand_empty_rest_of_line ();
16868 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16869 was given in the preceding .cpsetup, it results in:
16870 ld $gp, offset($sp)
16872 If a register $reg2 was given there, it results in:
16873 or $gp, $reg2, $0 */
16876 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16880 file_mips_check_options ();
16882 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16883 We also need NewABI support. */
16884 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16890 if (mips_opts
.mips16
)
16892 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16893 ignore_rest_of_line ();
16897 mips_mark_labels ();
16898 mips_assembling_insn
= TRUE
;
16901 if (mips_cpreturn_register
== -1)
16903 ex
.X_op
= O_constant
;
16904 ex
.X_add_symbol
= NULL
;
16905 ex
.X_op_symbol
= NULL
;
16906 ex
.X_add_number
= mips_cpreturn_offset
;
16908 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16911 move_register (mips_gp_register
, mips_cpreturn_register
);
16915 mips_assembling_insn
= FALSE
;
16916 demand_empty_rest_of_line ();
16919 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16920 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16921 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16922 debug information or MIPS16 TLS. */
16925 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16926 bfd_reloc_code_real_type rtype
)
16933 if (ex
.X_op
!= O_symbol
)
16935 as_bad (_("unsupported use of %s"), dirstr
);
16936 ignore_rest_of_line ();
16939 p
= frag_more (bytes
);
16940 md_number_to_chars (p
, 0, bytes
);
16941 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16942 demand_empty_rest_of_line ();
16943 mips_clear_insn_labels ();
16946 /* Handle .dtprelword. */
16949 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16951 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16954 /* Handle .dtpreldword. */
16957 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16959 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16962 /* Handle .tprelword. */
16965 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16967 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16970 /* Handle .tpreldword. */
16973 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16975 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16978 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16979 code. It sets the offset to use in gp_rel relocations. */
16982 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16984 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16985 We also need NewABI support. */
16986 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16992 mips_gprel_offset
= get_absolute_expression ();
16994 demand_empty_rest_of_line ();
16997 /* Handle the .gpword pseudo-op. This is used when generating PIC
16998 code. It generates a 32 bit GP relative reloc. */
17001 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17003 segment_info_type
*si
;
17004 struct insn_label_list
*l
;
17008 /* When not generating PIC code, this is treated as .word. */
17009 if (mips_pic
!= SVR4_PIC
)
17015 si
= seg_info (now_seg
);
17016 l
= si
->label_list
;
17017 mips_emit_delays ();
17019 mips_align (2, 0, l
);
17022 mips_clear_insn_labels ();
17024 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17026 as_bad (_("unsupported use of .gpword"));
17027 ignore_rest_of_line ();
17031 md_number_to_chars (p
, 0, 4);
17032 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17033 BFD_RELOC_GPREL32
);
17035 demand_empty_rest_of_line ();
17039 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17041 segment_info_type
*si
;
17042 struct insn_label_list
*l
;
17046 /* When not generating PIC code, this is treated as .dword. */
17047 if (mips_pic
!= SVR4_PIC
)
17053 si
= seg_info (now_seg
);
17054 l
= si
->label_list
;
17055 mips_emit_delays ();
17057 mips_align (3, 0, l
);
17060 mips_clear_insn_labels ();
17062 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17064 as_bad (_("unsupported use of .gpdword"));
17065 ignore_rest_of_line ();
17069 md_number_to_chars (p
, 0, 8);
17070 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17071 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17073 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17074 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17075 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17077 demand_empty_rest_of_line ();
17080 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17081 tables. It generates a R_MIPS_EH reloc. */
17084 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17089 mips_emit_delays ();
17092 mips_clear_insn_labels ();
17094 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17096 as_bad (_("unsupported use of .ehword"));
17097 ignore_rest_of_line ();
17101 md_number_to_chars (p
, 0, 4);
17102 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17103 BFD_RELOC_32_PCREL
);
17105 demand_empty_rest_of_line ();
17108 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17109 tables in SVR4 PIC code. */
17112 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17116 file_mips_check_options ();
17118 /* This is ignored when not generating SVR4 PIC code. */
17119 if (mips_pic
!= SVR4_PIC
)
17125 mips_mark_labels ();
17126 mips_assembling_insn
= TRUE
;
17128 /* Add $gp to the register named as an argument. */
17130 reg
= tc_get_register (0);
17131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17134 mips_assembling_insn
= FALSE
;
17135 demand_empty_rest_of_line ();
17138 /* Handle the .insn pseudo-op. This marks instruction labels in
17139 mips16/micromips mode. This permits the linker to handle them specially,
17140 such as generating jalx instructions when needed. We also make
17141 them odd for the duration of the assembly, in order to generate the
17142 right sort of code. We will make them even in the adjust_symtab
17143 routine, while leaving them marked. This is convenient for the
17144 debugger and the disassembler. The linker knows to make them odd
17148 s_insn (int ignore ATTRIBUTE_UNUSED
)
17150 file_mips_check_options ();
17151 file_ase_mips16
|= mips_opts
.mips16
;
17152 file_ase_micromips
|= mips_opts
.micromips
;
17154 mips_mark_labels ();
17156 demand_empty_rest_of_line ();
17159 /* Handle the .nan pseudo-op. */
17162 s_nan (int ignore ATTRIBUTE_UNUSED
)
17164 static const char str_legacy
[] = "legacy";
17165 static const char str_2008
[] = "2008";
17168 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17170 if (i
== sizeof (str_2008
) - 1
17171 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17173 else if (i
== sizeof (str_legacy
) - 1
17174 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17176 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17179 as_bad (_("`%s' does not support legacy NaN"),
17180 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17183 as_bad (_("bad .nan directive"));
17185 input_line_pointer
+= i
;
17186 demand_empty_rest_of_line ();
17189 /* Handle a .stab[snd] directive. Ideally these directives would be
17190 implemented in a transparent way, so that removing them would not
17191 have any effect on the generated instructions. However, s_stab
17192 internally changes the section, so in practice we need to decide
17193 now whether the preceding label marks compressed code. We do not
17194 support changing the compression mode of a label after a .stab*
17195 directive, such as in:
17201 so the current mode wins. */
17204 s_mips_stab (int type
)
17206 file_mips_check_options ();
17207 mips_mark_labels ();
17211 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17214 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17221 c
= get_symbol_name (&name
);
17222 symbolP
= symbol_find_or_make (name
);
17223 S_SET_WEAK (symbolP
);
17224 *input_line_pointer
= c
;
17226 SKIP_WHITESPACE_AFTER_NAME ();
17228 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17230 if (S_IS_DEFINED (symbolP
))
17232 as_bad (_("ignoring attempt to redefine symbol %s"),
17233 S_GET_NAME (symbolP
));
17234 ignore_rest_of_line ();
17238 if (*input_line_pointer
== ',')
17240 ++input_line_pointer
;
17241 SKIP_WHITESPACE ();
17245 if (exp
.X_op
!= O_symbol
)
17247 as_bad (_("bad .weakext directive"));
17248 ignore_rest_of_line ();
17251 symbol_set_value_expression (symbolP
, &exp
);
17254 demand_empty_rest_of_line ();
17257 /* Parse a register string into a number. Called from the ECOFF code
17258 to parse .frame. The argument is non-zero if this is the frame
17259 register, so that we can record it in mips_frame_reg. */
17262 tc_get_register (int frame
)
17266 SKIP_WHITESPACE ();
17267 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17271 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17272 mips_frame_reg_valid
= 1;
17273 mips_cprestore_valid
= 0;
17279 md_section_align (asection
*seg
, valueT addr
)
17281 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17283 /* We don't need to align ELF sections to the full alignment.
17284 However, Irix 5 may prefer that we align them at least to a 16
17285 byte boundary. We don't bother to align the sections if we
17286 are targeted for an embedded system. */
17287 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17292 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17295 /* Utility routine, called from above as well. If called while the
17296 input file is still being read, it's only an approximation. (For
17297 example, a symbol may later become defined which appeared to be
17298 undefined earlier.) */
17301 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17306 if (g_switch_value
> 0)
17308 const char *symname
;
17311 /* Find out whether this symbol can be referenced off the $gp
17312 register. It can be if it is smaller than the -G size or if
17313 it is in the .sdata or .sbss section. Certain symbols can
17314 not be referenced off the $gp, although it appears as though
17316 symname
= S_GET_NAME (sym
);
17317 if (symname
!= (const char *) NULL
17318 && (strcmp (symname
, "eprol") == 0
17319 || strcmp (symname
, "etext") == 0
17320 || strcmp (symname
, "_gp") == 0
17321 || strcmp (symname
, "edata") == 0
17322 || strcmp (symname
, "_fbss") == 0
17323 || strcmp (symname
, "_fdata") == 0
17324 || strcmp (symname
, "_ftext") == 0
17325 || strcmp (symname
, "end") == 0
17326 || strcmp (symname
, "_gp_disp") == 0))
17328 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17330 #ifndef NO_ECOFF_DEBUGGING
17331 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17332 && (symbol_get_obj (sym
)->ecoff_extern_size
17333 <= g_switch_value
))
17335 /* We must defer this decision until after the whole
17336 file has been read, since there might be a .extern
17337 after the first use of this symbol. */
17338 || (before_relaxing
17339 #ifndef NO_ECOFF_DEBUGGING
17340 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17342 && S_GET_VALUE (sym
) == 0)
17343 || (S_GET_VALUE (sym
) != 0
17344 && S_GET_VALUE (sym
) <= g_switch_value
)))
17348 const char *segname
;
17350 segname
= segment_name (S_GET_SEGMENT (sym
));
17351 gas_assert (strcmp (segname
, ".lit8") != 0
17352 && strcmp (segname
, ".lit4") != 0);
17353 change
= (strcmp (segname
, ".sdata") != 0
17354 && strcmp (segname
, ".sbss") != 0
17355 && strncmp (segname
, ".sdata.", 7) != 0
17356 && strncmp (segname
, ".sbss.", 6) != 0
17357 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17358 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17363 /* We are not optimizing for the $gp register. */
17368 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17371 pic_need_relax (symbolS
*sym
)
17375 /* Handle the case of a symbol equated to another symbol. */
17376 while (symbol_equated_reloc_p (sym
))
17380 /* It's possible to get a loop here in a badly written program. */
17381 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17387 if (symbol_section_p (sym
))
17390 symsec
= S_GET_SEGMENT (sym
);
17392 /* This must duplicate the test in adjust_reloc_syms. */
17393 return (!bfd_is_und_section (symsec
)
17394 && !bfd_is_abs_section (symsec
)
17395 && !bfd_is_com_section (symsec
)
17396 /* A global or weak symbol is treated as external. */
17397 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17400 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17401 convert a section-relative value VAL to the equivalent PC-relative
17405 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17406 offsetT val
, long stretch
)
17411 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17413 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17415 /* If the relax_marker of the symbol fragment differs from the
17416 relax_marker of this fragment, we have not yet adjusted the
17417 symbol fragment fr_address. We want to add in STRETCH in
17418 order to get a better estimate of the address. This
17419 particularly matters because of the shift bits. */
17420 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17424 /* Adjust stretch for any alignment frag. Note that if have
17425 been expanding the earlier code, the symbol may be
17426 defined in what appears to be an earlier frag. FIXME:
17427 This doesn't handle the fr_subtype field, which specifies
17428 a maximum number of bytes to skip when doing an
17430 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17432 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17435 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17437 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17446 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17448 /* The base address rules are complicated. The base address of
17449 a branch is the following instruction. The base address of a
17450 PC relative load or add is the instruction itself, but if it
17451 is in a delay slot (in which case it can not be extended) use
17452 the address of the instruction whose delay slot it is in. */
17453 if (pcrel_op
->include_isa_bit
)
17457 /* If we are currently assuming that this frag should be
17458 extended, then the current address is two bytes higher. */
17459 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17462 /* Ignore the low bit in the target, since it will be set
17463 for a text label. */
17466 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17468 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17471 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17476 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17477 extended opcode. SEC is the section the frag is in. */
17480 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17482 const struct mips_int_operand
*operand
;
17487 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17489 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17492 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17493 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17494 operand
= mips16_immed_operand (type
, FALSE
);
17495 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17496 || (operand
->root
.type
== OP_PCREL
17498 : !bfd_is_abs_section (symsec
)))
17501 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17503 if (operand
->root
.type
== OP_PCREL
)
17505 const struct mips_pcrel_operand
*pcrel_op
;
17508 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17511 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17512 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17514 /* If any of the shifted bits are set, we must use an extended
17515 opcode. If the address depends on the size of this
17516 instruction, this can lead to a loop, so we arrange to always
17517 use an extended opcode. */
17518 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17520 fragp
->fr_subtype
=
17521 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17525 /* If we are about to mark a frag as extended because the value
17526 is precisely the next value above maxtiny, then there is a
17527 chance of an infinite loop as in the following code:
17532 In this case when the la is extended, foo is 0x3fc bytes
17533 away, so the la can be shrunk, but then foo is 0x400 away, so
17534 the la must be extended. To avoid this loop, we mark the
17535 frag as extended if it was small, and is about to become
17536 extended with the next value above maxtiny. */
17537 maxtiny
= mips_int_operand_max (operand
);
17538 if (val
== maxtiny
+ (1 << operand
->shift
)
17539 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17541 fragp
->fr_subtype
=
17542 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17547 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17550 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17551 macro expansion. SEC is the section the frag is in. We only
17552 support PC-relative instructions (LA, DLA, LW, LD) here, in
17553 non-PIC code using 32-bit addressing. */
17556 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17558 const struct mips_pcrel_operand
*pcrel_op
;
17559 const struct mips_int_operand
*operand
;
17564 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17566 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17568 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17571 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17577 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17578 if (bfd_is_abs_section (symsec
))
17580 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17582 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17585 operand
= mips16_immed_operand (type
, TRUE
);
17586 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17587 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17588 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17590 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17597 /* Compute the length of a branch sequence, and adjust the
17598 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17599 worst-case length is computed, with UPDATE being used to indicate
17600 whether an unconditional (-1), branch-likely (+1) or regular (0)
17601 branch is to be computed. */
17603 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17605 bfd_boolean toofar
;
17609 && S_IS_DEFINED (fragp
->fr_symbol
)
17610 && !S_IS_WEAK (fragp
->fr_symbol
)
17611 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17616 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17618 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17622 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17625 /* If the symbol is not defined or it's in a different segment,
17626 we emit the long sequence. */
17629 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17631 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17632 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17633 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17634 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17635 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17641 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17644 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17646 /* Additional space for PIC loading of target address. */
17648 if (mips_opts
.isa
== ISA_MIPS1
)
17649 /* Additional space for $at-stabilizing nop. */
17653 /* If branch is conditional. */
17654 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17661 /* Get a FRAG's branch instruction delay slot size, either from the
17662 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17663 or SHORT_INSN_SIZE otherwise. */
17666 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17668 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17671 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17673 return short_insn_size
;
17676 /* Compute the length of a branch sequence, and adjust the
17677 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17678 worst-case length is computed, with UPDATE being used to indicate
17679 whether an unconditional (-1), or regular (0) branch is to be
17683 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17685 bfd_boolean insn32
= TRUE
;
17686 bfd_boolean nods
= TRUE
;
17687 bfd_boolean pic
= TRUE
;
17688 bfd_boolean al
= TRUE
;
17689 int short_insn_size
;
17690 bfd_boolean toofar
;
17695 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17696 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17697 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17698 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17700 short_insn_size
= insn32
? 4 : 2;
17703 && S_IS_DEFINED (fragp
->fr_symbol
)
17704 && !S_IS_WEAK (fragp
->fr_symbol
)
17705 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17710 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17711 /* Ignore the low bit in the target, since it will be set
17712 for a text label. */
17713 if ((val
& 1) != 0)
17716 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17720 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17723 /* If the symbol is not defined or it's in a different segment,
17724 we emit the long sequence. */
17727 if (fragp
&& update
17728 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17729 fragp
->fr_subtype
= (toofar
17730 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17731 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17736 bfd_boolean compact_known
= fragp
!= NULL
;
17737 bfd_boolean compact
= FALSE
;
17738 bfd_boolean uncond
;
17742 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17743 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17746 uncond
= update
< 0;
17748 /* If label is out of range, we turn branch <br>:
17750 <br> label # 4 bytes
17757 # compact && (!PIC || insn32)
17760 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17761 length
+= short_insn_size
;
17763 /* If assembling PIC code, we further turn:
17769 lw/ld at, %got(label)(gp) # 4 bytes
17770 d/addiu at, %lo(label) # 4 bytes
17771 jr/c at # 2/4 bytes
17774 length
+= 4 + short_insn_size
;
17776 /* Add an extra nop if the jump has no compact form and we need
17777 to fill the delay slot. */
17778 if ((!pic
|| al
) && nods
)
17780 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17781 : short_insn_size
);
17783 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17785 <brneg> 0f # 4 bytes
17786 nop # 2/4 bytes if !compact
17789 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17793 /* Add an extra nop to fill the delay slot. */
17794 gas_assert (fragp
);
17795 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17801 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17802 bit accordingly. */
17805 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17807 bfd_boolean toofar
;
17810 && S_IS_DEFINED (fragp
->fr_symbol
)
17811 && !S_IS_WEAK (fragp
->fr_symbol
)
17812 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17818 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17819 /* Ignore the low bit in the target, since it will be set
17820 for a text label. */
17821 if ((val
& 1) != 0)
17824 /* Assume this is a 2-byte branch. */
17825 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17827 /* We try to avoid the infinite loop by not adding 2 more bytes for
17832 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17834 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17835 else if (type
== 'E')
17836 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17841 /* If the symbol is not defined or it's in a different segment,
17842 we emit a normal 32-bit branch. */
17845 if (fragp
&& update
17846 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17848 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17849 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17857 /* Estimate the size of a frag before relaxing. Unless this is the
17858 mips16, we are not really relaxing here, and the final size is
17859 encoded in the subtype information. For the mips16, we have to
17860 decide whether we are using an extended opcode or not. */
17863 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17867 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17870 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17872 return fragp
->fr_var
;
17875 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17877 /* We don't want to modify the EXTENDED bit here; it might get us
17878 into infinite loops. We change it only in mips_relax_frag(). */
17879 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17880 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
17882 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17885 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17889 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17890 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17891 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17892 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17893 fragp
->fr_var
= length
;
17898 if (mips_pic
== VXWORKS_PIC
)
17899 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17901 else if (RELAX_PIC (fragp
->fr_subtype
))
17902 change
= pic_need_relax (fragp
->fr_symbol
);
17904 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17908 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17909 return -RELAX_FIRST (fragp
->fr_subtype
);
17912 return -RELAX_SECOND (fragp
->fr_subtype
);
17915 /* This is called to see whether a reloc against a defined symbol
17916 should be converted into a reloc against a section. */
17919 mips_fix_adjustable (fixS
*fixp
)
17921 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17922 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17925 if (fixp
->fx_addsy
== NULL
)
17928 /* Allow relocs used for EH tables. */
17929 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17932 /* If symbol SYM is in a mergeable section, relocations of the form
17933 SYM + 0 can usually be made section-relative. The mergeable data
17934 is then identified by the section offset rather than by the symbol.
17936 However, if we're generating REL LO16 relocations, the offset is split
17937 between the LO16 and partnering high part relocation. The linker will
17938 need to recalculate the complete offset in order to correctly identify
17941 The linker has traditionally not looked for the partnering high part
17942 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17943 placed anywhere. Rather than break backwards compatibility by changing
17944 this, it seems better not to force the issue, and instead keep the
17945 original symbol. This will work with either linker behavior. */
17946 if ((lo16_reloc_p (fixp
->fx_r_type
)
17947 || reloc_needs_lo_p (fixp
->fx_r_type
))
17948 && HAVE_IN_PLACE_ADDENDS
17949 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17952 /* There is no place to store an in-place offset for JALR relocations. */
17953 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17956 /* Likewise an in-range offset of limited PC-relative relocations may
17957 overflow the in-place relocatable field if recalculated against the
17958 start address of the symbol's containing section.
17960 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17961 section relative to allow linker relaxations to be performed later on. */
17962 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17963 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17966 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17967 to a floating-point stub. The same is true for non-R_MIPS16_26
17968 relocations against MIPS16 functions; in this case, the stub becomes
17969 the function's canonical address.
17971 Floating-point stubs are stored in unique .mips16.call.* or
17972 .mips16.fn.* sections. If a stub T for function F is in section S,
17973 the first relocation in section S must be against F; this is how the
17974 linker determines the target function. All relocations that might
17975 resolve to T must also be against F. We therefore have the following
17976 restrictions, which are given in an intentionally-redundant way:
17978 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17981 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17982 if that stub might be used.
17984 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17987 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17988 that stub might be used.
17990 There is a further restriction:
17992 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17993 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17994 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17995 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17996 against MIPS16 or microMIPS symbols because we need to keep the
17997 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17998 detection and JAL or BAL to JALX instruction conversion in the
18001 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18002 against a MIPS16 symbol. We deal with (5) by additionally leaving
18003 alone any jump and branch relocations against a microMIPS symbol.
18005 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18006 relocation against some symbol R, no relocation against R may be
18007 reduced. (Note that this deals with (2) as well as (1) because
18008 relocations against global symbols will never be reduced on ELF
18009 targets.) This approach is a little simpler than trying to detect
18010 stub sections, and gives the "all or nothing" per-symbol consistency
18011 that we have for MIPS16 symbols. */
18012 if (fixp
->fx_subsy
== NULL
18013 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18014 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18015 && (jmp_reloc_p (fixp
->fx_r_type
)
18016 || b_reloc_p (fixp
->fx_r_type
)))
18017 || *symbol_get_tc (fixp
->fx_addsy
)))
18023 /* Translate internal representation of relocation info to BFD target
18027 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18029 static arelent
*retval
[4];
18031 bfd_reloc_code_real_type code
;
18033 memset (retval
, 0, sizeof(retval
));
18034 reloc
= retval
[0] = XCNEW (arelent
);
18035 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18036 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18037 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18039 if (fixp
->fx_pcrel
)
18041 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18042 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18043 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18044 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18045 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18046 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18047 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18048 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18049 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18050 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18051 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18052 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18054 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18055 Relocations want only the symbol offset. */
18056 switch (fixp
->fx_r_type
)
18058 case BFD_RELOC_MIPS_18_PCREL_S3
:
18059 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18062 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18066 else if (HAVE_IN_PLACE_ADDENDS
18067 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18068 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18069 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18071 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18072 addend accordingly. */
18073 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18076 reloc
->addend
= fixp
->fx_addnumber
;
18078 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18079 entry to be used in the relocation's section offset. */
18080 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18082 reloc
->address
= reloc
->addend
;
18086 code
= fixp
->fx_r_type
;
18088 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18089 if (reloc
->howto
== NULL
)
18091 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18092 _("cannot represent %s relocation in this object file"
18094 bfd_get_reloc_code_name (code
));
18101 /* Relax a machine dependent frag. This returns the amount by which
18102 the current size of the frag should change. */
18105 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18107 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18109 offsetT old_var
= fragp
->fr_var
;
18111 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18113 return fragp
->fr_var
- old_var
;
18116 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18118 offsetT old_var
= fragp
->fr_var
;
18119 offsetT new_var
= 4;
18121 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18122 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18123 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18124 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18125 fragp
->fr_var
= new_var
;
18127 return new_var
- old_var
;
18130 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18133 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18135 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18137 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18138 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18140 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18142 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18148 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18150 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18152 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18153 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18154 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18156 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18158 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18166 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18168 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18170 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18171 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18172 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18176 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18177 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18184 /* Convert a machine dependent frag. */
18187 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18189 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18192 unsigned long insn
;
18195 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18196 insn
= read_insn (buf
);
18198 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18200 /* We generate a fixup instead of applying it right now
18201 because, if there are linker relaxations, we're going to
18202 need the relocations. */
18203 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18204 fragp
->fr_symbol
, fragp
->fr_offset
,
18205 TRUE
, BFD_RELOC_16_PCREL_S2
);
18206 fixp
->fx_file
= fragp
->fr_file
;
18207 fixp
->fx_line
= fragp
->fr_line
;
18209 buf
= write_insn (buf
, insn
);
18215 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18216 _("relaxed out-of-range branch into a jump"));
18218 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18221 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18223 /* Reverse the branch. */
18224 switch ((insn
>> 28) & 0xf)
18227 if ((insn
& 0xff000000) == 0x47000000
18228 || (insn
& 0xff600000) == 0x45600000)
18230 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18231 reversed by tweaking bit 23. */
18232 insn
^= 0x00800000;
18236 /* bc[0-3][tf]l? instructions can have the condition
18237 reversed by tweaking a single TF bit, and their
18238 opcodes all have 0x4???????. */
18239 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18240 insn
^= 0x00010000;
18245 /* bltz 0x04000000 bgez 0x04010000
18246 bltzal 0x04100000 bgezal 0x04110000 */
18247 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18248 insn
^= 0x00010000;
18252 /* beq 0x10000000 bne 0x14000000
18253 blez 0x18000000 bgtz 0x1c000000 */
18254 insn
^= 0x04000000;
18262 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18264 /* Clear the and-link bit. */
18265 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18267 /* bltzal 0x04100000 bgezal 0x04110000
18268 bltzall 0x04120000 bgezall 0x04130000 */
18269 insn
&= ~0x00100000;
18272 /* Branch over the branch (if the branch was likely) or the
18273 full jump (not likely case). Compute the offset from the
18274 current instruction to branch to. */
18275 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18279 /* How many bytes in instructions we've already emitted? */
18280 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18281 /* How many bytes in instructions from here to the end? */
18282 i
= fragp
->fr_var
- i
;
18284 /* Convert to instruction count. */
18286 /* Branch counts from the next instruction. */
18289 /* Branch over the jump. */
18290 buf
= write_insn (buf
, insn
);
18293 buf
= write_insn (buf
, 0);
18295 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18297 /* beql $0, $0, 2f */
18299 /* Compute the PC offset from the current instruction to
18300 the end of the variable frag. */
18301 /* How many bytes in instructions we've already emitted? */
18302 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18303 /* How many bytes in instructions from here to the end? */
18304 i
= fragp
->fr_var
- i
;
18305 /* Convert to instruction count. */
18307 /* Don't decrement i, because we want to branch over the
18311 buf
= write_insn (buf
, insn
);
18312 buf
= write_insn (buf
, 0);
18316 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18319 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18320 ? 0x0c000000 : 0x08000000);
18322 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18323 fragp
->fr_symbol
, fragp
->fr_offset
,
18324 FALSE
, BFD_RELOC_MIPS_JMP
);
18325 fixp
->fx_file
= fragp
->fr_file
;
18326 fixp
->fx_line
= fragp
->fr_line
;
18328 buf
= write_insn (buf
, insn
);
18332 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18334 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18335 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18336 insn
|= at
<< OP_SH_RT
;
18338 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18339 fragp
->fr_symbol
, fragp
->fr_offset
,
18340 FALSE
, BFD_RELOC_MIPS_GOT16
);
18341 fixp
->fx_file
= fragp
->fr_file
;
18342 fixp
->fx_line
= fragp
->fr_line
;
18344 buf
= write_insn (buf
, insn
);
18346 if (mips_opts
.isa
== ISA_MIPS1
)
18348 buf
= write_insn (buf
, 0);
18350 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18351 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18352 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18354 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18355 fragp
->fr_symbol
, fragp
->fr_offset
,
18356 FALSE
, BFD_RELOC_LO16
);
18357 fixp
->fx_file
= fragp
->fr_file
;
18358 fixp
->fx_line
= fragp
->fr_line
;
18360 buf
= write_insn (buf
, insn
);
18363 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18367 insn
|= at
<< OP_SH_RS
;
18369 buf
= write_insn (buf
, insn
);
18373 fragp
->fr_fix
+= fragp
->fr_var
;
18374 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18378 /* Relax microMIPS branches. */
18379 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18381 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18382 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18383 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18384 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18385 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18386 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18387 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18388 bfd_boolean short_ds
;
18389 unsigned long insn
;
18392 fragp
->fr_fix
+= fragp
->fr_var
;
18394 /* Handle 16-bit branches that fit or are forced to fit. */
18395 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18397 /* We generate a fixup instead of applying it right now,
18398 because if there is linker relaxation, we're going to
18399 need the relocations. */
18403 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18404 fragp
->fr_symbol
, fragp
->fr_offset
,
18405 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18408 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18409 fragp
->fr_symbol
, fragp
->fr_offset
,
18410 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18416 fixp
->fx_file
= fragp
->fr_file
;
18417 fixp
->fx_line
= fragp
->fr_line
;
18419 /* These relocations can have an addend that won't fit in
18421 fixp
->fx_no_overflow
= 1;
18426 /* Handle 32-bit branches that fit or are forced to fit. */
18427 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18428 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18430 /* We generate a fixup instead of applying it right now,
18431 because if there is linker relaxation, we're going to
18432 need the relocations. */
18433 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18434 fragp
->fr_symbol
, fragp
->fr_offset
,
18435 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18436 fixp
->fx_file
= fragp
->fr_file
;
18437 fixp
->fx_line
= fragp
->fr_line
;
18441 insn
= read_compressed_insn (buf
, 4);
18446 /* Check the short-delay-slot bit. */
18447 if (!al
|| (insn
& 0x02000000) != 0)
18448 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18450 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18453 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18458 /* Relax 16-bit branches to 32-bit branches. */
18461 insn
= read_compressed_insn (buf
, 2);
18463 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18464 insn
= 0x94000000; /* beq */
18465 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18467 unsigned long regno
;
18469 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18470 regno
= micromips_to_32_reg_d_map
[regno
];
18471 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18472 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18477 /* Nothing else to do, just write it out. */
18478 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18479 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18481 buf
= write_compressed_insn (buf
, insn
, 4);
18483 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18484 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18489 insn
= read_compressed_insn (buf
, 4);
18491 /* Relax 32-bit branches to a sequence of instructions. */
18492 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18493 _("relaxed out-of-range branch into a jump"));
18495 /* Set the short-delay-slot bit. */
18496 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18498 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18502 /* Reverse the branch. */
18503 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18504 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18505 insn
^= 0x20000000;
18506 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18507 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18508 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18509 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18510 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18511 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18512 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18513 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18514 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18515 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18516 insn
^= 0x00400000;
18517 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18518 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18519 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18520 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18521 insn
^= 0x00200000;
18522 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18524 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18526 insn
^= 0x00800000;
18532 /* Clear the and-link and short-delay-slot bits. */
18533 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18535 /* bltzal 0x40200000 bgezal 0x40600000 */
18536 /* bltzals 0x42200000 bgezals 0x42600000 */
18537 insn
&= ~0x02200000;
18540 /* Make a label at the end for use with the branch. */
18541 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18542 micromips_label_inc ();
18543 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18546 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18547 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18548 fixp
->fx_file
= fragp
->fr_file
;
18549 fixp
->fx_line
= fragp
->fr_line
;
18551 /* Branch over the jump. */
18552 buf
= write_compressed_insn (buf
, insn
, 4);
18558 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18560 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18566 unsigned long jal
= (short_ds
|| nods
18567 ? 0x74000000 : 0xf4000000); /* jal/s */
18569 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18570 insn
= al
? jal
: 0xd4000000;
18572 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18573 fragp
->fr_symbol
, fragp
->fr_offset
,
18574 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18575 fixp
->fx_file
= fragp
->fr_file
;
18576 fixp
->fx_line
= fragp
->fr_line
;
18578 buf
= write_compressed_insn (buf
, insn
, 4);
18580 if (compact
|| nods
)
18584 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18586 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18591 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18593 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18594 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18595 insn
|= at
<< MICROMIPSOP_SH_RT
;
18597 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18598 fragp
->fr_symbol
, fragp
->fr_offset
,
18599 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18600 fixp
->fx_file
= fragp
->fr_file
;
18601 fixp
->fx_line
= fragp
->fr_line
;
18603 buf
= write_compressed_insn (buf
, insn
, 4);
18605 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18606 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18607 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18609 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18610 fragp
->fr_symbol
, fragp
->fr_offset
,
18611 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18612 fixp
->fx_file
= fragp
->fr_file
;
18613 fixp
->fx_line
= fragp
->fr_line
;
18615 buf
= write_compressed_insn (buf
, insn
, 4);
18620 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18621 insn
|= at
<< MICROMIPSOP_SH_RS
;
18623 buf
= write_compressed_insn (buf
, insn
, 4);
18625 if (compact
|| nods
)
18627 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18631 /* jr/jrc/jalr/jalrs $at */
18632 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18633 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18635 insn
= al
? jalr
: jr
;
18636 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18638 buf
= write_compressed_insn (buf
, insn
, 2);
18643 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18645 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18650 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18654 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18657 const struct mips_int_operand
*operand
;
18660 unsigned int user_length
;
18661 bfd_boolean need_reloc
;
18662 unsigned long insn
;
18667 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18668 operand
= mips16_immed_operand (type
, FALSE
);
18670 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18671 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18672 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18674 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18675 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18676 || (operand
->root
.type
== OP_PCREL
&& !mac
18678 : !bfd_is_abs_section (symsec
)));
18680 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18682 const struct mips_pcrel_operand
*pcrel_op
;
18684 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18686 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18688 if (!mips_ignore_branch_isa
18689 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18690 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18691 _("branch to a symbol in another ISA mode"));
18692 else if ((fragp
->fr_offset
& 0x1) != 0)
18693 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18694 _("branch to misaligned address (0x%lx)"),
18698 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18700 /* Make sure the section winds up with the alignment we have
18702 if (operand
->shift
> 0)
18703 record_alignment (asec
, operand
->shift
);
18706 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18707 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18710 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18711 _("macro instruction expanded into multiple "
18712 "instructions in a branch delay slot"));
18714 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18715 _("extended instruction in a branch delay slot"));
18717 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18718 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18719 _("macro instruction expanded into multiple "
18722 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18724 insn
= read_compressed_insn (buf
, 2);
18726 insn
|= MIPS16_EXTEND
;
18728 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18730 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18742 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18743 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18745 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18751 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18753 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18754 fragp
->fr_symbol
, fragp
->fr_offset
,
18755 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18756 fixp
->fx_file
= fragp
->fr_file
;
18757 fixp
->fx_line
= fragp
->fr_line
;
18759 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18760 fragp
->fr_symbol
, fragp
->fr_offset
,
18761 FALSE
, BFD_RELOC_MIPS16_LO16
);
18762 fixp
->fx_file
= fragp
->fr_file
;
18763 fixp
->fx_line
= fragp
->fr_line
;
18768 switch (insn
& 0xf800)
18770 case 0x0800: /* ADDIU */
18771 reg
= (insn
>> 8) & 0x7;
18772 op
= 0xf0004800 | (reg
<< 8);
18774 case 0xb000: /* LW */
18775 reg
= (insn
>> 8) & 0x7;
18776 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18778 case 0xf800: /* I64 */
18779 reg
= (insn
>> 5) & 0x7;
18780 switch (insn
& 0x0700)
18782 case 0x0400: /* LD */
18783 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18785 case 0x0600: /* DADDIU */
18786 op
= 0xf000fd00 | (reg
<< 5);
18796 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18797 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18798 buf
= write_compressed_insn (buf
, new, 4);
18801 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18802 buf
= write_compressed_insn (buf
, new, 4);
18804 op
|= mips16_immed_extend (val
, 16);
18805 buf
= write_compressed_insn (buf
, op
, 4);
18807 fragp
->fr_fix
+= e2
? 8 : 12;
18811 unsigned int length
= ext
? 4 : 2;
18815 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18822 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18827 if (mac
|| reloc
== BFD_RELOC_NONE
)
18828 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18829 _("unsupported relocation"));
18832 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18833 fragp
->fr_symbol
, fragp
->fr_offset
,
18835 fixp
->fx_file
= fragp
->fr_file
;
18836 fixp
->fx_line
= fragp
->fr_line
;
18839 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18840 _("invalid unextended operand value"));
18843 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18844 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18846 gas_assert (mips16_opcode_length (insn
) == length
);
18847 write_compressed_insn (buf
, insn
, length
);
18848 fragp
->fr_fix
+= length
;
18853 relax_substateT subtype
= fragp
->fr_subtype
;
18854 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18855 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18859 first
= RELAX_FIRST (subtype
);
18860 second
= RELAX_SECOND (subtype
);
18861 fixp
= (fixS
*) fragp
->fr_opcode
;
18863 /* If the delay slot chosen does not match the size of the instruction,
18864 then emit a warning. */
18865 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18866 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18871 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18872 | RELAX_DELAY_SLOT_SIZE_FIRST
18873 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18874 msg
= macro_warning (s
);
18876 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18880 /* Possibly emit a warning if we've chosen the longer option. */
18881 if (use_second
== second_longer
)
18887 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18888 msg
= macro_warning (s
);
18890 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18894 /* Go through all the fixups for the first sequence. Disable them
18895 (by marking them as done) if we're going to use the second
18896 sequence instead. */
18898 && fixp
->fx_frag
== fragp
18899 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18901 if (subtype
& RELAX_USE_SECOND
)
18903 fixp
= fixp
->fx_next
;
18906 /* Go through the fixups for the second sequence. Disable them if
18907 we're going to use the first sequence, otherwise adjust their
18908 addresses to account for the relaxation. */
18909 while (fixp
&& fixp
->fx_frag
== fragp
)
18911 if (subtype
& RELAX_USE_SECOND
)
18912 fixp
->fx_where
-= first
;
18915 fixp
= fixp
->fx_next
;
18918 /* Now modify the frag contents. */
18919 if (subtype
& RELAX_USE_SECOND
)
18923 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18924 memmove (start
, start
+ first
, second
);
18925 fragp
->fr_fix
-= first
;
18928 fragp
->fr_fix
-= second
;
18932 /* This function is called after the relocs have been generated.
18933 We've been storing mips16 text labels as odd. Here we convert them
18934 back to even for the convenience of the debugger. */
18937 mips_frob_file_after_relocs (void)
18940 unsigned int count
, i
;
18942 syms
= bfd_get_outsymbols (stdoutput
);
18943 count
= bfd_get_symcount (stdoutput
);
18944 for (i
= 0; i
< count
; i
++, syms
++)
18945 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18946 && ((*syms
)->value
& 1) != 0)
18948 (*syms
)->value
&= ~1;
18949 /* If the symbol has an odd size, it was probably computed
18950 incorrectly, so adjust that as well. */
18951 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18952 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18956 /* This function is called whenever a label is defined, including fake
18957 labels instantiated off the dot special symbol. It is used when
18958 handling branch delays; if a branch has a label, we assume we cannot
18959 move it. This also bumps the value of the symbol by 1 in compressed
18963 mips_record_label (symbolS
*sym
)
18965 segment_info_type
*si
= seg_info (now_seg
);
18966 struct insn_label_list
*l
;
18968 if (free_insn_labels
== NULL
)
18969 l
= XNEW (struct insn_label_list
);
18972 l
= free_insn_labels
;
18973 free_insn_labels
= l
->next
;
18977 l
->next
= si
->label_list
;
18978 si
->label_list
= l
;
18981 /* This function is called as tc_frob_label() whenever a label is defined
18982 and adds a DWARF-2 record we only want for true labels. */
18985 mips_define_label (symbolS
*sym
)
18987 mips_record_label (sym
);
18988 dwarf2_emit_label (sym
);
18991 /* This function is called by tc_new_dot_label whenever a new dot symbol
18995 mips_add_dot_label (symbolS
*sym
)
18997 mips_record_label (sym
);
18998 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18999 mips_compressed_mark_label (sym
);
19002 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19003 static unsigned int
19004 mips_convert_ase_flags (int ase
)
19006 unsigned int ext_ases
= 0;
19009 ext_ases
|= AFL_ASE_DSP
;
19010 if (ase
& ASE_DSPR2
)
19011 ext_ases
|= AFL_ASE_DSPR2
;
19012 if (ase
& ASE_DSPR3
)
19013 ext_ases
|= AFL_ASE_DSPR3
;
19015 ext_ases
|= AFL_ASE_EVA
;
19017 ext_ases
|= AFL_ASE_MCU
;
19018 if (ase
& ASE_MDMX
)
19019 ext_ases
|= AFL_ASE_MDMX
;
19020 if (ase
& ASE_MIPS3D
)
19021 ext_ases
|= AFL_ASE_MIPS3D
;
19023 ext_ases
|= AFL_ASE_MT
;
19024 if (ase
& ASE_SMARTMIPS
)
19025 ext_ases
|= AFL_ASE_SMARTMIPS
;
19026 if (ase
& ASE_VIRT
)
19027 ext_ases
|= AFL_ASE_VIRT
;
19029 ext_ases
|= AFL_ASE_MSA
;
19031 ext_ases
|= AFL_ASE_XPA
;
19032 if (ase
& ASE_MIPS16E2
)
19033 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19035 ext_ases
|= AFL_ASE_CRC
;
19036 if (ase
& ASE_GINV
)
19037 ext_ases
|= AFL_ASE_GINV
;
19038 if (ase
& ASE_LOONGSON_MMI
)
19039 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19040 if (ase
& ASE_LOONGSON_CAM
)
19041 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19045 /* Some special processing for a MIPS ELF file. */
19048 mips_elf_final_processing (void)
19051 Elf_Internal_ABIFlags_v0 flags
;
19055 switch (file_mips_opts
.isa
)
19058 flags
.isa_level
= 1;
19061 flags
.isa_level
= 2;
19064 flags
.isa_level
= 3;
19067 flags
.isa_level
= 4;
19070 flags
.isa_level
= 5;
19073 flags
.isa_level
= 32;
19077 flags
.isa_level
= 32;
19081 flags
.isa_level
= 32;
19085 flags
.isa_level
= 32;
19089 flags
.isa_level
= 32;
19093 flags
.isa_level
= 64;
19097 flags
.isa_level
= 64;
19101 flags
.isa_level
= 64;
19105 flags
.isa_level
= 64;
19109 flags
.isa_level
= 64;
19114 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19115 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19116 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19117 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19119 flags
.cpr2_size
= AFL_REG_NONE
;
19120 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19121 Tag_GNU_MIPS_ABI_FP
);
19122 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19123 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19124 if (file_ase_mips16
)
19125 flags
.ases
|= AFL_ASE_MIPS16
;
19126 if (file_ase_micromips
)
19127 flags
.ases
|= AFL_ASE_MICROMIPS
;
19129 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19130 || file_mips_opts
.fp
== 64)
19131 && file_mips_opts
.oddspreg
)
19132 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19135 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19136 ((Elf_External_ABIFlags_v0
*)
19139 /* Write out the register information. */
19140 if (mips_abi
!= N64_ABI
)
19144 s
.ri_gprmask
= mips_gprmask
;
19145 s
.ri_cprmask
[0] = mips_cprmask
[0];
19146 s
.ri_cprmask
[1] = mips_cprmask
[1];
19147 s
.ri_cprmask
[2] = mips_cprmask
[2];
19148 s
.ri_cprmask
[3] = mips_cprmask
[3];
19149 /* The gp_value field is set by the MIPS ELF backend. */
19151 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19152 ((Elf32_External_RegInfo
*)
19153 mips_regmask_frag
));
19157 Elf64_Internal_RegInfo s
;
19159 s
.ri_gprmask
= mips_gprmask
;
19161 s
.ri_cprmask
[0] = mips_cprmask
[0];
19162 s
.ri_cprmask
[1] = mips_cprmask
[1];
19163 s
.ri_cprmask
[2] = mips_cprmask
[2];
19164 s
.ri_cprmask
[3] = mips_cprmask
[3];
19165 /* The gp_value field is set by the MIPS ELF backend. */
19167 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19168 ((Elf64_External_RegInfo
*)
19169 mips_regmask_frag
));
19172 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19173 sort of BFD interface for this. */
19174 if (mips_any_noreorder
)
19175 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19176 if (mips_pic
!= NO_PIC
)
19178 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19179 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19182 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19184 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19185 defined at present; this might need to change in future. */
19186 if (file_ase_mips16
)
19187 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19188 if (file_ase_micromips
)
19189 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19190 if (file_mips_opts
.ase
& ASE_MDMX
)
19191 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19193 /* Set the MIPS ELF ABI flags. */
19194 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19195 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19196 else if (mips_abi
== O64_ABI
)
19197 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19198 else if (mips_abi
== EABI_ABI
)
19200 if (file_mips_opts
.gp
== 64)
19201 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19203 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19206 /* Nothing to do for N32_ABI or N64_ABI. */
19208 if (mips_32bitmode
)
19209 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19211 if (mips_nan2008
== 1)
19212 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19214 /* 32 bit code with 64 bit FP registers. */
19215 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19216 Tag_GNU_MIPS_ABI_FP
);
19217 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19218 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19221 typedef struct proc
{
19223 symbolS
*func_end_sym
;
19224 unsigned long reg_mask
;
19225 unsigned long reg_offset
;
19226 unsigned long fpreg_mask
;
19227 unsigned long fpreg_offset
;
19228 unsigned long frame_offset
;
19229 unsigned long frame_reg
;
19230 unsigned long pc_reg
;
19233 static procS cur_proc
;
19234 static procS
*cur_proc_ptr
;
19235 static int numprocs
;
19237 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19238 as "2", and a normal nop as "0". */
19240 #define NOP_OPCODE_MIPS 0
19241 #define NOP_OPCODE_MIPS16 1
19242 #define NOP_OPCODE_MICROMIPS 2
19245 mips_nop_opcode (void)
19247 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19248 return NOP_OPCODE_MICROMIPS
;
19249 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19250 return NOP_OPCODE_MIPS16
;
19252 return NOP_OPCODE_MIPS
;
19255 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19256 32-bit microMIPS NOPs here (if applicable). */
19259 mips_handle_align (fragS
*fragp
)
19263 int bytes
, size
, excess
;
19266 if (fragp
->fr_type
!= rs_align_code
)
19269 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19271 switch (nop_opcode
)
19273 case NOP_OPCODE_MICROMIPS
:
19274 opcode
= micromips_nop32_insn
.insn_opcode
;
19277 case NOP_OPCODE_MIPS16
:
19278 opcode
= mips16_nop_insn
.insn_opcode
;
19281 case NOP_OPCODE_MIPS
:
19283 opcode
= nop_insn
.insn_opcode
;
19288 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19289 excess
= bytes
% size
;
19291 /* Handle the leading part if we're not inserting a whole number of
19292 instructions, and make it the end of the fixed part of the frag.
19293 Try to fit in a short microMIPS NOP if applicable and possible,
19294 and use zeroes otherwise. */
19295 gas_assert (excess
< 4);
19296 fragp
->fr_fix
+= excess
;
19301 /* Fall through. */
19303 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19305 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19309 /* Fall through. */
19312 /* Fall through. */
19317 md_number_to_chars (p
, opcode
, size
);
19318 fragp
->fr_var
= size
;
19327 if (*input_line_pointer
== '-')
19329 ++input_line_pointer
;
19332 if (!ISDIGIT (*input_line_pointer
))
19333 as_bad (_("expected simple number"));
19334 if (input_line_pointer
[0] == '0')
19336 if (input_line_pointer
[1] == 'x')
19338 input_line_pointer
+= 2;
19339 while (ISXDIGIT (*input_line_pointer
))
19342 val
|= hex_value (*input_line_pointer
++);
19344 return negative
? -val
: val
;
19348 ++input_line_pointer
;
19349 while (ISDIGIT (*input_line_pointer
))
19352 val
|= *input_line_pointer
++ - '0';
19354 return negative
? -val
: val
;
19357 if (!ISDIGIT (*input_line_pointer
))
19359 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19360 *input_line_pointer
, *input_line_pointer
);
19361 as_warn (_("invalid number"));
19364 while (ISDIGIT (*input_line_pointer
))
19367 val
+= *input_line_pointer
++ - '0';
19369 return negative
? -val
: val
;
19372 /* The .file directive; just like the usual .file directive, but there
19373 is an initial number which is the ECOFF file index. In the non-ECOFF
19374 case .file implies DWARF-2. */
19377 s_mips_file (int x ATTRIBUTE_UNUSED
)
19379 static int first_file_directive
= 0;
19381 if (ECOFF_DEBUGGING
)
19390 filename
= dwarf2_directive_filename ();
19392 /* Versions of GCC up to 3.1 start files with a ".file"
19393 directive even for stabs output. Make sure that this
19394 ".file" is handled. Note that you need a version of GCC
19395 after 3.1 in order to support DWARF-2 on MIPS. */
19396 if (filename
!= NULL
&& ! first_file_directive
)
19398 (void) new_logical_line (filename
, -1);
19399 s_app_file_string (filename
, 0);
19401 first_file_directive
= 1;
19405 /* The .loc directive, implying DWARF-2. */
19408 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19410 if (!ECOFF_DEBUGGING
)
19411 dwarf2_directive_loc (0);
19414 /* The .end directive. */
19417 s_mips_end (int x ATTRIBUTE_UNUSED
)
19421 /* Following functions need their own .frame and .cprestore directives. */
19422 mips_frame_reg_valid
= 0;
19423 mips_cprestore_valid
= 0;
19425 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19428 demand_empty_rest_of_line ();
19433 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19434 as_warn (_(".end not in text section"));
19438 as_warn (_(".end directive without a preceding .ent directive"));
19439 demand_empty_rest_of_line ();
19445 gas_assert (S_GET_NAME (p
));
19446 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19447 as_warn (_(".end symbol does not match .ent symbol"));
19449 if (debug_type
== DEBUG_STABS
)
19450 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19454 as_warn (_(".end directive missing or unknown symbol"));
19456 /* Create an expression to calculate the size of the function. */
19457 if (p
&& cur_proc_ptr
)
19459 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19460 expressionS
*exp
= XNEW (expressionS
);
19463 exp
->X_op
= O_subtract
;
19464 exp
->X_add_symbol
= symbol_temp_new_now ();
19465 exp
->X_op_symbol
= p
;
19466 exp
->X_add_number
= 0;
19468 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19471 #ifdef md_flush_pending_output
19472 md_flush_pending_output ();
19475 /* Generate a .pdr section. */
19476 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19478 segT saved_seg
= now_seg
;
19479 subsegT saved_subseg
= now_subseg
;
19483 gas_assert (pdr_seg
);
19484 subseg_set (pdr_seg
, 0);
19486 /* Write the symbol. */
19487 exp
.X_op
= O_symbol
;
19488 exp
.X_add_symbol
= p
;
19489 exp
.X_add_number
= 0;
19490 emit_expr (&exp
, 4);
19492 fragp
= frag_more (7 * 4);
19494 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19495 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19496 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19497 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19498 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19499 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19500 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19502 subseg_set (saved_seg
, saved_subseg
);
19505 cur_proc_ptr
= NULL
;
19508 /* The .aent and .ent directives. */
19511 s_mips_ent (int aent
)
19515 symbolP
= get_symbol ();
19516 if (*input_line_pointer
== ',')
19517 ++input_line_pointer
;
19518 SKIP_WHITESPACE ();
19519 if (ISDIGIT (*input_line_pointer
)
19520 || *input_line_pointer
== '-')
19523 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19524 as_warn (_(".ent or .aent not in text section"));
19526 if (!aent
&& cur_proc_ptr
)
19527 as_warn (_("missing .end"));
19531 /* This function needs its own .frame and .cprestore directives. */
19532 mips_frame_reg_valid
= 0;
19533 mips_cprestore_valid
= 0;
19535 cur_proc_ptr
= &cur_proc
;
19536 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19538 cur_proc_ptr
->func_sym
= symbolP
;
19542 if (debug_type
== DEBUG_STABS
)
19543 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19544 S_GET_NAME (symbolP
));
19547 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19549 demand_empty_rest_of_line ();
19552 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19553 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19554 s_mips_frame is used so that we can set the PDR information correctly.
19555 We can't use the ecoff routines because they make reference to the ecoff
19556 symbol table (in the mdebug section). */
19559 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19561 if (ECOFF_DEBUGGING
)
19567 if (cur_proc_ptr
== (procS
*) NULL
)
19569 as_warn (_(".frame outside of .ent"));
19570 demand_empty_rest_of_line ();
19574 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19576 SKIP_WHITESPACE ();
19577 if (*input_line_pointer
++ != ','
19578 || get_absolute_expression_and_terminator (&val
) != ',')
19580 as_warn (_("bad .frame directive"));
19581 --input_line_pointer
;
19582 demand_empty_rest_of_line ();
19586 cur_proc_ptr
->frame_offset
= val
;
19587 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19589 demand_empty_rest_of_line ();
19593 /* The .fmask and .mask directives. If the mdebug section is present
19594 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19595 embedded targets, s_mips_mask is used so that we can set the PDR
19596 information correctly. We can't use the ecoff routines because they
19597 make reference to the ecoff symbol table (in the mdebug section). */
19600 s_mips_mask (int reg_type
)
19602 if (ECOFF_DEBUGGING
)
19603 s_ignore (reg_type
);
19608 if (cur_proc_ptr
== (procS
*) NULL
)
19610 as_warn (_(".mask/.fmask outside of .ent"));
19611 demand_empty_rest_of_line ();
19615 if (get_absolute_expression_and_terminator (&mask
) != ',')
19617 as_warn (_("bad .mask/.fmask directive"));
19618 --input_line_pointer
;
19619 demand_empty_rest_of_line ();
19623 off
= get_absolute_expression ();
19625 if (reg_type
== 'F')
19627 cur_proc_ptr
->fpreg_mask
= mask
;
19628 cur_proc_ptr
->fpreg_offset
= off
;
19632 cur_proc_ptr
->reg_mask
= mask
;
19633 cur_proc_ptr
->reg_offset
= off
;
19636 demand_empty_rest_of_line ();
19640 /* A table describing all the processors gas knows about. Names are
19641 matched in the order listed.
19643 To ease comparison, please keep this table in the same order as
19644 gcc's mips_cpu_info_table[]. */
19645 static const struct mips_cpu_info mips_cpu_info_table
[] =
19647 /* Entries for generic ISAs */
19648 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19649 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19650 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19651 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19652 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19653 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19654 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19655 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19656 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19657 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19658 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19659 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19660 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19661 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19662 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19665 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19666 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19667 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19670 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19673 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19674 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19675 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19676 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19677 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19678 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19679 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19680 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19681 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19682 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19683 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19684 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19685 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19686 /* ST Microelectronics Loongson 2E and 2F cores */
19687 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19688 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19691 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19692 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19693 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19694 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19695 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19696 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19697 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19698 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19699 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19700 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19701 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19702 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19703 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19704 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19705 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19708 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19709 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19710 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19711 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19713 /* MIPS 32 Release 2 */
19714 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19715 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19716 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19717 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19718 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19719 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19720 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19721 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19722 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19723 ISA_MIPS32R2
, CPU_MIPS32R2
},
19724 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19725 ISA_MIPS32R2
, CPU_MIPS32R2
},
19726 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19727 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19728 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19729 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19730 /* Deprecated forms of the above. */
19731 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19732 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19733 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19734 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19735 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19736 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19737 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19738 /* Deprecated forms of the above. */
19739 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19740 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19741 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19742 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19743 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19744 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19745 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19746 /* Deprecated forms of the above. */
19747 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19748 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19749 /* 34Kn is a 34kc without DSP. */
19750 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19751 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19752 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19753 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19754 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19755 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19756 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19757 /* Deprecated forms of the above. */
19758 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19759 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19760 /* 1004K cores are multiprocessor versions of the 34K. */
19761 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19762 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19763 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19764 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19765 /* interaptiv is the new name for 1004kf */
19766 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19767 { "interaptiv-mr2", 0,
19768 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19769 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19771 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19772 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19773 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19774 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19777 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19778 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19779 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19780 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19782 /* Broadcom SB-1 CPU core */
19783 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19784 /* Broadcom SB-1A CPU core */
19785 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19787 /* MIPS 64 Release 2 */
19788 /* Loongson CPU core */
19789 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
, ISA_MIPS64R2
,
19792 /* Cavium Networks Octeon CPU core */
19793 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19794 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19795 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19796 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19799 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19802 XLP is mostly like XLR, with the prominent exception that it is
19803 MIPS64R2 rather than MIPS64. */
19804 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19806 /* MIPS 64 Release 6 */
19807 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19808 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19811 { NULL
, 0, 0, 0, 0 }
19815 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19816 with a final "000" replaced by "k". Ignore case.
19818 Note: this function is shared between GCC and GAS. */
19821 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19823 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19824 given
++, canonical
++;
19826 return ((*given
== 0 && *canonical
== 0)
19827 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19831 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19832 CPU name. We've traditionally allowed a lot of variation here.
19834 Note: this function is shared between GCC and GAS. */
19837 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19839 /* First see if the name matches exactly, or with a final "000"
19840 turned into "k". */
19841 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19844 /* If not, try comparing based on numerical designation alone.
19845 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19846 if (TOLOWER (*given
) == 'r')
19848 if (!ISDIGIT (*given
))
19851 /* Skip over some well-known prefixes in the canonical name,
19852 hoping to find a number there too. */
19853 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19855 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19857 else if (TOLOWER (canonical
[0]) == 'r')
19860 return mips_strict_matching_cpu_name_p (canonical
, given
);
19864 /* Parse an option that takes the name of a processor as its argument.
19865 OPTION is the name of the option and CPU_STRING is the argument.
19866 Return the corresponding processor enumeration if the CPU_STRING is
19867 recognized, otherwise report an error and return null.
19869 A similar function exists in GCC. */
19871 static const struct mips_cpu_info
*
19872 mips_parse_cpu (const char *option
, const char *cpu_string
)
19874 const struct mips_cpu_info
*p
;
19876 /* 'from-abi' selects the most compatible architecture for the given
19877 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19878 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19879 version. Look first at the -mgp options, if given, otherwise base
19880 the choice on MIPS_DEFAULT_64BIT.
19882 Treat NO_ABI like the EABIs. One reason to do this is that the
19883 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19884 architecture. This code picks MIPS I for 'mips' and MIPS III for
19885 'mips64', just as we did in the days before 'from-abi'. */
19886 if (strcasecmp (cpu_string
, "from-abi") == 0)
19888 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19889 return mips_cpu_info_from_isa (ISA_MIPS1
);
19891 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19892 return mips_cpu_info_from_isa (ISA_MIPS3
);
19894 if (file_mips_opts
.gp
>= 0)
19895 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19896 ? ISA_MIPS1
: ISA_MIPS3
);
19898 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19903 /* 'default' has traditionally been a no-op. Probably not very useful. */
19904 if (strcasecmp (cpu_string
, "default") == 0)
19907 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19908 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19911 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19915 /* Return the canonical processor information for ISA (a member of the
19916 ISA_MIPS* enumeration). */
19918 static const struct mips_cpu_info
*
19919 mips_cpu_info_from_isa (int isa
)
19923 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19924 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19925 && isa
== mips_cpu_info_table
[i
].isa
)
19926 return (&mips_cpu_info_table
[i
]);
19931 static const struct mips_cpu_info
*
19932 mips_cpu_info_from_arch (int arch
)
19936 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19937 if (arch
== mips_cpu_info_table
[i
].cpu
)
19938 return (&mips_cpu_info_table
[i
]);
19944 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19948 fprintf (stream
, "%24s", "");
19953 fprintf (stream
, ", ");
19957 if (*col_p
+ strlen (string
) > 72)
19959 fprintf (stream
, "\n%24s", "");
19963 fprintf (stream
, "%s", string
);
19964 *col_p
+= strlen (string
);
19970 md_show_usage (FILE *stream
)
19975 fprintf (stream
, _("\
19977 -EB generate big endian output\n\
19978 -EL generate little endian output\n\
19979 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19980 -G NUM allow referencing objects up to NUM bytes\n\
19981 implicitly with the gp register [default 8]\n"));
19982 fprintf (stream
, _("\
19983 -mips1 generate MIPS ISA I instructions\n\
19984 -mips2 generate MIPS ISA II instructions\n\
19985 -mips3 generate MIPS ISA III instructions\n\
19986 -mips4 generate MIPS ISA IV instructions\n\
19987 -mips5 generate MIPS ISA V instructions\n\
19988 -mips32 generate MIPS32 ISA instructions\n\
19989 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19990 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19991 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19992 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19993 -mips64 generate MIPS64 ISA instructions\n\
19994 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19995 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19996 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19997 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19998 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20002 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20003 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20004 show (stream
, "from-abi", &column
, &first
);
20005 fputc ('\n', stream
);
20007 fprintf (stream
, _("\
20008 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20009 -no-mCPU don't generate code specific to CPU.\n\
20010 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20014 show (stream
, "3900", &column
, &first
);
20015 show (stream
, "4010", &column
, &first
);
20016 show (stream
, "4100", &column
, &first
);
20017 show (stream
, "4650", &column
, &first
);
20018 fputc ('\n', stream
);
20020 fprintf (stream
, _("\
20021 -mips16 generate mips16 instructions\n\
20022 -no-mips16 do not generate mips16 instructions\n"));
20023 fprintf (stream
, _("\
20024 -mmips16e2 generate MIPS16e2 instructions\n\
20025 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20026 fprintf (stream
, _("\
20027 -mmicromips generate microMIPS instructions\n\
20028 -mno-micromips do not generate microMIPS instructions\n"));
20029 fprintf (stream
, _("\
20030 -msmartmips generate smartmips instructions\n\
20031 -mno-smartmips do not generate smartmips instructions\n"));
20032 fprintf (stream
, _("\
20033 -mdsp generate DSP instructions\n\
20034 -mno-dsp do not generate DSP instructions\n"));
20035 fprintf (stream
, _("\
20036 -mdspr2 generate DSP R2 instructions\n\
20037 -mno-dspr2 do not generate DSP R2 instructions\n"));
20038 fprintf (stream
, _("\
20039 -mdspr3 generate DSP R3 instructions\n\
20040 -mno-dspr3 do not generate DSP R3 instructions\n"));
20041 fprintf (stream
, _("\
20042 -mmt generate MT instructions\n\
20043 -mno-mt do not generate MT instructions\n"));
20044 fprintf (stream
, _("\
20045 -mmcu generate MCU instructions\n\
20046 -mno-mcu do not generate MCU instructions\n"));
20047 fprintf (stream
, _("\
20048 -mmsa generate MSA instructions\n\
20049 -mno-msa do not generate MSA instructions\n"));
20050 fprintf (stream
, _("\
20051 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20052 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20053 fprintf (stream
, _("\
20054 -mvirt generate Virtualization instructions\n\
20055 -mno-virt do not generate Virtualization instructions\n"));
20056 fprintf (stream
, _("\
20057 -mcrc generate CRC instructions\n\
20058 -mno-crc do not generate CRC instructions\n"));
20059 fprintf (stream
, _("\
20060 -mginv generate Global INValidate (GINV) instructions\n\
20061 -mno-ginv do not generate Global INValidate instructions\n"));
20062 fprintf (stream
, _("\
20063 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20064 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20065 fprintf (stream
, _("\
20066 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20067 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20068 fprintf (stream
, _("\
20069 -minsn32 only generate 32-bit microMIPS instructions\n\
20070 -mno-insn32 generate all microMIPS instructions\n"));
20071 fprintf (stream
, _("\
20072 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20073 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20074 -mfix-vr4120 work around certain VR4120 errata\n\
20075 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20076 -mfix-24k insert a nop after ERET and DERET instructions\n\
20077 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20078 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20079 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20080 -msym32 assume all symbols have 32-bit values\n\
20081 -O0 do not remove unneeded NOPs, do not swap branches\n\
20082 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20083 -O2 remove unneeded NOPs and swap branches\n\
20084 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20085 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20086 fprintf (stream
, _("\
20087 -mhard-float allow floating-point instructions\n\
20088 -msoft-float do not allow floating-point instructions\n\
20089 -msingle-float only allow 32-bit floating-point operations\n\
20090 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20091 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20092 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20093 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20094 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20095 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20099 show (stream
, "legacy", &column
, &first
);
20100 show (stream
, "2008", &column
, &first
);
20102 fputc ('\n', stream
);
20104 fprintf (stream
, _("\
20105 -KPIC, -call_shared generate SVR4 position independent code\n\
20106 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20107 -mvxworks-pic generate VxWorks position independent code\n\
20108 -non_shared do not generate code that can operate with DSOs\n\
20109 -xgot assume a 32 bit GOT\n\
20110 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20111 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20112 position dependent (non shared) code\n\
20113 -mabi=ABI create ABI conformant object file for:\n"));
20117 show (stream
, "32", &column
, &first
);
20118 show (stream
, "o64", &column
, &first
);
20119 show (stream
, "n32", &column
, &first
);
20120 show (stream
, "64", &column
, &first
);
20121 show (stream
, "eabi", &column
, &first
);
20123 fputc ('\n', stream
);
20125 fprintf (stream
, _("\
20126 -32 create o32 ABI object file%s\n"),
20127 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20128 fprintf (stream
, _("\
20129 -n32 create n32 ABI object file%s\n"),
20130 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20131 fprintf (stream
, _("\
20132 -64 create 64 ABI object file%s\n"),
20133 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20138 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20140 if (HAVE_64BIT_SYMBOLS
)
20141 return dwarf2_format_64bit_irix
;
20143 return dwarf2_format_32bit
;
20148 mips_dwarf2_addr_size (void)
20150 if (HAVE_64BIT_OBJECTS
)
20156 /* Standard calling conventions leave the CFA at SP on entry. */
20158 mips_cfi_frame_initial_instructions (void)
20160 cfi_add_CFA_def_cfa_register (SP
);
20164 tc_mips_regname_to_dw2regnum (char *regname
)
20166 unsigned int regnum
= -1;
20169 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20175 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20176 Given a symbolic attribute NAME, return the proper integer value.
20177 Returns -1 if the attribute is not known. */
20180 mips_convert_symbolic_attribute (const char *name
)
20182 static const struct
20187 attribute_table
[] =
20189 #define T(tag) {#tag, tag}
20190 T (Tag_GNU_MIPS_ABI_FP
),
20191 T (Tag_GNU_MIPS_ABI_MSA
),
20199 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20200 if (streq (name
, attribute_table
[i
].name
))
20201 return attribute_table
[i
].tag
;
20209 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20211 mips_emit_delays ();
20213 as_warn (_("missing .end at end of assembly"));
20215 /* Just in case no code was emitted, do the consistency check. */
20216 file_mips_check_options ();
20218 /* Set a floating-point ABI if the user did not. */
20219 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20221 /* Perform consistency checks on the floating-point ABI. */
20222 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20223 Tag_GNU_MIPS_ABI_FP
);
20224 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20225 check_fpabi (fpabi
);
20229 /* Soft-float gets precedence over single-float, the two options should
20230 not be used together so this should not matter. */
20231 if (file_mips_opts
.soft_float
== 1)
20232 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20233 /* Single-float gets precedence over all double_float cases. */
20234 else if (file_mips_opts
.single_float
== 1)
20235 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20238 switch (file_mips_opts
.fp
)
20241 if (file_mips_opts
.gp
== 32)
20242 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20245 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20248 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20249 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20250 else if (file_mips_opts
.gp
== 32)
20251 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20253 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20258 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20259 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20263 /* Returns the relocation type required for a particular CFI encoding. */
20265 bfd_reloc_code_real_type
20266 mips_cfi_reloc_for_encoding (int encoding
)
20268 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20269 return BFD_RELOC_32_PCREL
;
20270 else return BFD_RELOC_NONE
;