1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
49 /* MIPS ISA (Instruction Set Architecture) level. */
50 static int mips_isa
= -1;
52 static int mips_warn_about_macros
;
53 static int mips_noreorder
;
54 static int mips_nomove
;
56 static int mips_nobopt
;
59 /* The size of the small data section. */
60 static int g_switch_value
= 8;
66 /* handle of the OPCODE hash table */
67 static struct hash_control
*op_hash
= NULL
;
69 /* This array holds the chars that always start a comment. If the
70 pre-processor is disabled, these aren't very useful */
71 const char comment_chars
[] = "#";
73 /* This array holds the chars that only start a comment at the beginning of
74 a line. If the line seems to have the form '# 123 filename'
75 .line and .file directives will appear in the pre-processed output */
76 /* Note that input_file.c hand checks for '#' at the beginning of the
77 first line of the input file. This is because the compiler outputs
78 #NO_APP at the beginning of its output. */
79 /* Also note that C style comments are always supported. */
80 const char line_comment_chars
[] = "#";
82 /* This array holds machine specific line separator characters. */
83 const char line_separator_chars
[] = "";
85 /* Chars that can be used to separate mant from exp in floating point nums */
86 const char EXP_CHARS
[] = "eE";
88 /* Chars that mean this number is a floating point constant */
91 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
93 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
94 changed in read.c . Ideally it shouldn't have to know about it at all,
95 but nothing is ideal around here.
98 static char *insn_error
;
100 static int byte_order
= BYTE_ORDER
;
102 static int auto_align
= 1;
104 /* Symbol labelling the current insn. */
105 static symbolS
*insn_label
;
107 /* To output NOP instructions correctly, we need to keep information
108 about the previous two instructions. */
110 /* Whether we are optimizing. The default value of 2 means to remove
111 unneeded NOPs and swap branch instructions when possible. A value
112 of 1 means to not swap branches. A value of 0 means to always
114 static int mips_optimize
= 2;
116 /* The previous instruction. */
117 static struct mips_cl_insn prev_insn
;
119 /* The instruction before prev_insn. */
120 static struct mips_cl_insn prev_prev_insn
;
122 /* If we don't want information for prev_insn or prev_prev_insn, we
123 point the insn_mo field at this dummy integer. */
124 static const struct mips_opcode dummy_opcode
= { 0 };
126 /* Non-zero if prev_insn is valid. */
127 static int prev_insn_valid
;
129 /* The frag for the previous instruction. */
130 static struct frag
*prev_insn_frag
;
132 /* The offset into prev_insn_frag for the previous instruction. */
133 static long prev_insn_where
;
135 /* The reloc for the previous instruction, if any. */
136 static fixS
*prev_insn_fixp
;
138 /* Non-zero if the previous instruction was in a delay slot. */
139 static int prev_insn_is_delay_slot
;
141 /* Non-zero if the previous instruction was in a .set noreorder. */
142 static int prev_insn_unreordered
;
144 /* Non-zero if the previous previous instruction was in a .set
146 static int prev_prev_insn_unreordered
;
148 /* Prototypes for static functions. */
151 #define internalError() \
152 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
154 #define internalError() as_fatal ("MIPS internal Error");
157 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
158 unsigned int reg
, int fpr
));
159 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
161 bfd_reloc_code_real_type r
));
162 static void mips_no_prev_insn
PARAMS ((void));
163 static void mips_emit_delays
PARAMS ((void));
164 static int gp_reference
PARAMS ((expressionS
* ep
));
165 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
166 const char *name
, const char *fmt
,
168 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
170 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
171 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
173 static void load_register
PARAMS ((int *counter
,
174 int reg
, expressionS
* ep
));
175 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
176 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
177 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
178 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
179 static symbolS
*get_symbol
PARAMS ((void));
180 static void mips_align
PARAMS ((int to
, int fill
));
181 static void s_align
PARAMS ((int));
182 static void s_stringer
PARAMS ((int));
183 static void s_change_sec
PARAMS ((int));
184 static void s_cons
PARAMS ((int));
185 static void s_err
PARAMS ((int));
186 static void s_extern
PARAMS ((int));
187 static void s_float_cons
PARAMS ((int));
188 static void s_option
PARAMS ((int));
189 static void s_mipsset
PARAMS ((int));
190 static void s_mips_space
PARAMS ((int));
192 static void md_obj_begin
PARAMS ((void));
193 static void md_obj_end
PARAMS ((void));
194 static long get_number
PARAMS ((void));
195 static void s_ent
PARAMS ((int));
196 static void s_mipsend
PARAMS ((int));
197 static void s_file
PARAMS ((int));
198 static void s_frame
PARAMS ((int));
199 static void s_loc
PARAMS ((int));
200 static void s_mask
PARAMS ((char));
205 The following pseudo-ops from the Kane and Heinrich MIPS book
206 should be defined here, but are currently unsupported: .alias,
207 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
209 The following pseudo-ops from the Kane and Heinrich MIPS book are
210 specific to the type of debugging information being generated, and
211 should be defined by the object format: .aent, .begin, .bend,
212 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
215 The following pseudo-ops from the Kane and Heinrich MIPS book are
216 not MIPS CPU specific, but are also not specific to the object file
217 format. This file is probably the best place to define them, but
218 they are not currently supported: .asm0, .endr, .lab, .repeat,
219 .struct, .weakext. */
221 const pseudo_typeS md_pseudo_table
[] =
223 /* MIPS specific pseudo-ops. */
224 {"option", s_option
, 0},
225 {"set", s_mipsset
, 0},
226 {"rdata", s_change_sec
, 'r',},
227 {"sdata", s_change_sec
, 's',},
229 /* Relatively generic pseudo-ops that happen to be used on MIPS
231 {"asciiz", s_stringer
, 1},
232 {"bss", s_change_sec
, 'b'},
236 /* These pseudo-ops are defined in read.c, but must be overridden
237 here for one reason or another. */
238 {"align", s_align
, 0},
239 {"ascii", s_stringer
, 0},
240 {"asciz", s_stringer
, 1},
242 {"data", s_change_sec
, 'd'},
243 {"double", s_float_cons
, 'd'},
244 {"extern", s_extern
, 0},
245 {"float", s_float_cons
, 'f'},
246 {"space", s_mips_space
, 0},
247 {"text", s_change_sec
, 't'},
251 /* These pseudo-ops should be defined by the object file format.
252 However, ECOFF is the only format which currently defines them,
253 so we have versions here for a.out. */
255 {"end", s_mipsend
, 0},
258 {"fmask", s_ignore
, 'F'},
259 {"frame", s_ignore
, 0},
260 {"loc", s_ignore
, 0},
261 {"mask", s_ignore
, 'R'},
262 {"verstamp", s_ignore
, 0},
269 const relax_typeS md_relax_table
[] =
275 static char *expr_end
;
277 static expressionS imm_expr
;
278 static expressionS offset_expr
;
279 static bfd_reloc_code_real_type imm_reloc
;
280 static bfd_reloc_code_real_type offset_reloc
;
283 * This function is called once, at assembler startup time. It should
284 * set up all the tables, etc. that the MD part of the assembler will need.
289 register const char *retval
= NULL
;
290 register unsigned int i
= 0;
294 if (strcmp (TARGET_CPU
, "mips") == 0)
296 else if (strcmp (TARGET_CPU
, "r6000") == 0
297 || strcmp (TARGET_CPU
, "mips2") == 0)
299 else if (strcmp (TARGET_CPU
, "mips64") == 0
300 || strcmp (TARGET_CPU
, "r4000") == 0
301 || strcmp (TARGET_CPU
, "mips3") == 0)
307 if ((op_hash
= hash_new ()) == NULL
)
309 as_fatal ("Virtual memory exhausted");
311 for (i
= 0; i
< NUMOPCODES
;)
313 const char *name
= mips_opcodes
[i
].name
;
315 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
316 if (retval
!= NULL
&& *retval
!= '\0')
318 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
319 mips_opcodes
[i
].name
, retval
);
320 as_fatal ("Broken assembler. No assembly attempted.");
324 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
325 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
326 != mips_opcodes
[i
].match
))
328 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
329 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
330 as_fatal ("Broken assembler. No assembly attempted.");
334 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
337 mips_no_prev_insn ();
339 /* set the default alignment for the text section (2**2) */
340 record_alignment (text_section
, 2);
343 bfd_set_gp_size (stdoutput
, g_switch_value
);
363 struct mips_cl_insn insn
;
365 imm_expr
.X_op
= O_absent
;
366 offset_expr
.X_op
= O_absent
;
368 mips_ip (str
, &insn
);
371 as_bad ("%s `%s'", insn_error
, str
);
374 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
380 if (imm_expr
.X_op
!= O_absent
)
381 append_insn (&insn
, &imm_expr
, imm_reloc
);
382 else if (offset_expr
.X_op
!= O_absent
)
383 append_insn (&insn
, &offset_expr
, offset_reloc
);
385 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
389 /* See whether instruction IP reads register REG. If FPR is non-zero,
390 REG is a floating point register. */
393 insn_uses_reg (ip
, reg
, fpr
)
394 struct mips_cl_insn
*ip
;
398 /* Don't report on general register 0, since it never changes. */
399 if (! fpr
&& reg
== 0)
404 /* If we are called with either $f0 or $f1, we must check $f0.
405 This is not optimal, because it will introduce an unnecessary
406 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
407 need to distinguish reading both $f0 and $f1 or just one of
408 them. Note that we don't have to check the other way,
409 because there is no instruction that sets both $f0 and $f1
410 and requires a delay. */
411 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
412 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
413 == (reg
&~ (unsigned) 1)))
415 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
416 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
417 == (reg
&~ (unsigned) 1)))
422 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
423 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
425 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
426 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
433 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
434 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
438 * Output an instruction.
441 append_insn (ip
, address_expr
, reloc_type
)
442 struct mips_cl_insn
*ip
;
443 expressionS
*address_expr
;
444 bfd_reloc_code_real_type reloc_type
;
450 if (! mips_noreorder
)
452 /* If the previous insn required any delay slots, see if we need
453 to insert a NOP or two. There are eight kinds of possible
454 hazards, of which an instruction can have at most one type.
455 (1) a load from memory delay
456 (2) a load from a coprocessor delay
457 (3) an unconditional branch delay
458 (4) a conditional branch delay
459 (5) a move to coprocessor register delay
460 (6) a load coprocessor register from memory delay
461 (7) a coprocessor condition code delay
462 (8) a HI/LO special register delay
464 There are a lot of optimizations we could do that we don't.
465 In particular, we do not, in general, reorder instructions.
466 If you use gcc with optimization, it will reorder
467 instructions and generally do much more optimization then we
468 do here; repeating all that work in the assembler would only
469 benefit hand written assembly code, and does not seem worth
472 /* This is how a NOP is emitted. */
473 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
475 /* The previous insn might require a delay slot, depending upon
476 the contents of the current insn. */
477 if ((prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
479 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)))
481 /* A load from a coprocessor or from memory. All load
482 delays delay the use of general register rt for one
483 instruction on the r3000. The r6000 and r4000 use
485 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
486 if (mips_optimize
== 0
487 || insn_uses_reg (ip
,
488 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
493 else if ((prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
495 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)))
497 /* A generic coprocessor delay. The previous instruction
498 modified a coprocessor general or control register. If
499 it modified a control register, we need to avoid any
500 coprocessor instruction (this is probably not always
501 required, but it sometimes is). If it modified a general
502 register, we avoid using that register.
504 On the r6000 and r4000 loading a coprocessor register
505 from memory is interlocked, and does not require a delay.
507 This case is not handled very well. There is no special
508 knowledge of CP0 handling, and the coprocessors other
509 than the floating point unit are not distinguished at
511 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
513 if (mips_optimize
== 0
514 || insn_uses_reg (ip
,
515 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
520 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_S
)
522 if (mips_optimize
== 0
523 || insn_uses_reg (ip
,
524 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
531 /* We don't know exactly what the previous instruction
532 does. If the current instruction uses a coprocessor
533 register, we must insert a NOP. If previous
534 instruction may set the condition codes, and the
535 current instruction uses them, we must insert two
537 if (mips_optimize
== 0
538 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
539 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)))
541 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
545 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
547 /* The previous instruction sets the coprocessor condition
548 codes, but does not require a general coprocessor delay
549 (this means it is a floating point comparison
550 instruction). If this instruction uses the condition
551 codes, we need to insert a single NOP. */
552 if (mips_optimize
== 0
553 || ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
556 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
558 /* The previous instruction reads the LO register; if the
559 current instruction writes to the LO register, we must
561 if (mips_optimize
== 0
562 || ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
565 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
567 /* The previous instruction reads the HI register; if the
568 current instruction writes to the HI register, we must
570 if (mips_optimize
== 0
571 || ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
575 /* There are two cases which require two intervening
576 instructions: 1) setting the condition codes using a move to
577 coprocessor instruction which requires a general coprocessor
578 delay and then reading the condition codes 2) reading the HI
579 or LO register and then writing to it. If we are not already
580 emitting a NOP instruction, we must check for these cases
581 compared to the instruction previous to the previous
584 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
585 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
586 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
587 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
588 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
589 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
590 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
593 /* Now emit the right number of NOP instructions. */
599 if (insn_label
!= NULL
)
601 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
602 insn_label
->sy_frag
= frag_now
;
603 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
610 /* This is testing the address of the frag, not the alignment of
611 the instruction in the current section. */
619 if (address_expr
!= NULL
)
621 if (address_expr
->X_op
== O_constant
)
626 ip
->insn_opcode
|= address_expr
->X_add_number
;
630 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
633 case BFD_RELOC_MIPS_JMP
:
634 case BFD_RELOC_16_PCREL_S2
:
643 assert (reloc_type
!= BFD_RELOC_UNUSED
);
645 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
647 reloc_type
== BFD_RELOC_16_PCREL_S2
,
652 md_number_to_chars (f
, ip
->insn_opcode
, 4);
654 if (! mips_noreorder
)
656 /* Filling the branch delay slot is more complex. We try to
657 switch the branch with the previous instruction, which we can
658 do if the previous instruction does not set up a condition
659 that the branch tests and if the branch is not itself the
660 target of any branch. */
661 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
662 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
664 if (mips_optimize
< 2
665 /* If we have seen .set nobopt, don't optimize. */
667 /* If we have seen .set volatile or .set nomove, don't
670 /* If we had to emit any NOP instructions, then we
671 already know we can not swap. */
673 /* If we don't even know the previous insn, we can not
676 /* If the previous insn is already in a branch delay
677 slot, then we can not swap. */
678 || prev_insn_is_delay_slot
679 /* If the previous previous insn was in a .set
680 noreorder, we can't swap. Actually, the MIPS
681 assembler will swap in this situation. However, gcc
682 configured -with-gnu-as will generate code like
688 in which we can not swap the bne and INSN. If gcc is
689 not configured -with-gnu-as, it does not output the
690 .set pseudo-ops. We don't have to check
691 prev_insn_unreordered, because prev_insn_valid will
692 be 0 in that case. We don't want to use
693 prev_prev_insn_valid, because we do want to be able
694 to swap at the start of a function. */
695 || prev_prev_insn_unreordered
696 /* If the branch is itself the target of a branch, we
697 can not swap. We cheat on this; all we check for is
698 whether there is a label on this instruction. If
699 there are any branches to anything other than a
700 label, users must use .set noreorder. */
701 || insn_label
!= NULL
702 /* If the branch reads the condition codes, we don't
703 even try to swap, because in the sequence
708 we can not swap, and I don't feel like handling that
710 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
711 /* We can not swap with an instruction that requires a
712 delay slot, becase the target of the branch might
713 interfere with that instruction. */
714 || (prev_insn
.insn_mo
->pinfo
715 & (INSN_LOAD_COPROC_DELAY
716 | INSN_COPROC_MOVE_DELAY
717 | INSN_WRITE_COND_CODE
721 && (prev_insn
.insn_mo
->pinfo
722 & (INSN_LOAD_MEMORY_DELAY
723 | INSN_COPROC_MEMORY_DELAY
)))
724 /* We can not swap with a branch instruction. */
725 || (prev_insn
.insn_mo
->pinfo
726 & (INSN_UNCOND_BRANCH_DELAY
727 | INSN_COND_BRANCH_DELAY
728 | INSN_COND_BRANCH_LIKELY
))
729 /* If the branch reads a register that the previous
730 instruction sets, we can not swap. */
731 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
732 && insn_uses_reg (ip
,
733 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
736 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
737 && insn_uses_reg (ip
,
738 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
741 /* If the branch writes a register that the previous
742 instruction sets, we can not swap (we know that
743 branches write only to RD or to $31). */
744 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
745 && (((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
746 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
747 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
748 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
749 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
752 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
753 && (((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
754 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
755 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
756 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
757 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
760 /* If the branch writes a register that the previous
761 instruction reads, we can not swap (we know that
762 branches only write to RD or to $31). */
763 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
764 && insn_uses_reg (&prev_insn
,
765 ((ip
->insn_opcode
>> OP_SH_RD
)
768 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
769 && insn_uses_reg (&prev_insn
, 31, 0))
770 /* If the previous previous instruction has a load
771 delay, and sets a register that the branch reads, we
773 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
775 && (prev_prev_insn
.insn_mo
->pinfo
776 & INSN_LOAD_MEMORY_DELAY
)))
777 && insn_uses_reg (ip
,
778 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
782 /* We could do even better for unconditional branches to
783 portions of this object file; we could pick up the
784 instruction at the destination, put it in the delay
785 slot, and bump the destination address. */
787 /* Update the previous insn information. */
788 prev_prev_insn
= *ip
;
789 prev_insn
.insn_mo
= &dummy_opcode
;
796 /* It looks like we can actually do the swap. */
797 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
798 memcpy (temp
, prev_f
, 4);
799 memcpy (prev_f
, f
, 4);
803 prev_insn_fixp
->fx_frag
= frag_now
;
804 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
808 fixp
->fx_frag
= prev_insn_frag
;
809 fixp
->fx_where
= prev_insn_where
;
811 /* Update the previous insn information; leave prev_insn
813 prev_prev_insn
= *ip
;
815 prev_insn_is_delay_slot
= 1;
817 /* If that was an unconditional branch, forget the previous
819 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
821 prev_prev_insn
.insn_mo
= &dummy_opcode
;
822 prev_insn
.insn_mo
= &dummy_opcode
;
825 else if (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
)
827 /* We don't yet optimize a branch likely. What we should do
828 is look at the target, copy the instruction found there
829 into the delay slot, and increment the branch to jump to
830 the next instruction. */
832 /* Update the previous insn information. */
833 prev_prev_insn
= *ip
;
834 prev_insn
.insn_mo
= &dummy_opcode
;
838 /* Update the previous insn information. */
840 prev_prev_insn
.insn_mo
= &dummy_opcode
;
842 prev_prev_insn
= prev_insn
;
845 /* Any time we see a branch, we always fill the delay slot
846 immediately; since this insn is not a branch, we know it
847 is not in a delay slot. */
848 prev_insn_is_delay_slot
= 0;
851 prev_prev_insn_unreordered
= prev_insn_unreordered
;
852 prev_insn_unreordered
= 0;
853 prev_insn_frag
= frag_now
;
854 prev_insn_where
= f
- frag_now
->fr_literal
;
855 prev_insn_fixp
= fixp
;
859 /* We just output an insn, so the next one doesn't have a label. */
863 /* This function forgets that there was any previous instruction or
869 prev_insn
.insn_mo
= &dummy_opcode
;
870 prev_prev_insn
.insn_mo
= &dummy_opcode
;
872 prev_insn_is_delay_slot
= 0;
873 prev_insn_unreordered
= 0;
874 prev_prev_insn_unreordered
= 0;
878 /* This function must be called whenever we turn on noreorder or emit
879 something other than instructions. It inserts any NOPS which might
880 be needed by the previous instruction, and clears the information
881 kept for the previous instructions. */
886 if (! mips_noreorder
)
891 if ((prev_insn
.insn_mo
->pinfo
892 & (INSN_LOAD_COPROC_DELAY
893 | INSN_COPROC_MOVE_DELAY
894 | INSN_WRITE_COND_CODE
898 && (prev_insn
.insn_mo
->pinfo
899 & (INSN_LOAD_MEMORY_DELAY
900 | INSN_COPROC_MEMORY_DELAY
))))
903 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
904 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
905 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
908 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
909 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
910 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
915 if (insn_label
!= NULL
)
917 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
918 insn_label
->sy_frag
= frag_now
;
919 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
922 mips_no_prev_insn ();
926 /* Return 1 if an expression can be accessed via the GP register. */
937 sym
= ep
->X_add_symbol
;
938 if (sym
== (symbolS
*) NULL
939 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
942 /* Certain symbols can not be referenced off the GP, although it
943 appears as though they can. */
944 symname
= S_GET_NAME (sym
);
945 if (symname
!= (const char *) NULL
946 && (strcmp (symname
, "eprol") == 0
947 || strcmp (symname
, "etext") == 0
948 || strcmp (symname
, "_gp") == 0
949 || strcmp (symname
, "edata") == 0
950 || strcmp (symname
, "_fbss") == 0
951 || strcmp (symname
, "_fdata") == 0
952 || strcmp (symname
, "_ftext") == 0
953 || strcmp (symname
, "end") == 0))
955 if (! S_IS_DEFINED (sym
)
956 && S_GET_VALUE (sym
) != 0
957 && S_GET_VALUE (sym
) <= g_switch_value
)
959 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
960 return (strcmp (segname
, ".sdata") == 0
961 || strcmp (segname
, ".sbss") == 0
962 || strcmp (segname
, ".lit8") == 0
963 || strcmp (segname
, ".lit4") == 0);
964 #else /* ! defined (OBJ_ECOFF) */
965 /* The GP register is only used for ECOFF. */
967 #endif /* ! defined (OBJ_ECOFF) */
970 /* Build an instruction created by a macro expansion. This is passed
971 a pointer to the count of instructions created so far, an
972 expression, the name of the instruction to build, an operand format
973 string, and corresponding arguments. */
977 macro_build (int *counter
,
982 #else /* ! defined (NO_STDARG) */
984 macro_build (counter
, ep
, name
, fmt
, va_alist
)
990 #endif /* ! defined (NO_STDARG) */
992 struct mips_cl_insn insn
;
993 bfd_reloc_code_real_type r
;
997 va_start (args
, fmt
);
1003 * If the macro is about to expand into a second instruction,
1004 * print a warning if needed. We need to pass ip as a parameter
1005 * to generate a better warning message here...
1007 if (mips_warn_about_macros
&& *counter
== 1)
1008 as_warn ("Macro instruction expanded into multiple instructions");
1010 *counter
+= 1; /* bump instruction counter */
1012 r
= BFD_RELOC_UNUSED
;
1013 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1014 assert (insn
.insn_mo
);
1015 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1017 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
1020 assert (insn
.insn_mo
->name
);
1021 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1023 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1024 insn
.insn_opcode
= insn
.insn_mo
->match
;
1040 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1046 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1051 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1056 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1063 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1067 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1071 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1078 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1088 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1089 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1094 assert (ep
!= NULL
);
1096 * This allows macro() to pass an immediate expression for
1097 * creating short branches without creating a symbol.
1098 * Note that the expression still might come from the assembly
1099 * input, in which case the value is not checked for range nor
1100 * is a relocation entry generated (yuck).
1102 if (ep
->X_op
== O_constant
)
1104 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1108 r
= BFD_RELOC_16_PCREL_S2
;
1117 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1119 /* Use GP relative addressing if possible. */
1120 if (r
== BFD_RELOC_LO16
1121 && gp_reference (ep
))
1122 r
= BFD_RELOC_MIPS_GPREL
;
1124 append_insn (&insn
, ep
, r
);
1128 * Generate a "lui" instruction.
1131 macro_build_lui (counter
, ep
, regnum
)
1136 expressionS high_expr
;
1137 struct mips_cl_insn insn
;
1138 bfd_reloc_code_real_type r
;
1139 CONST
char *name
= "lui";
1140 CONST
char *fmt
= "t,u";
1144 if (high_expr
.X_op
== O_constant
)
1146 /* we can compute the instruction now without a relocation entry */
1147 if (high_expr
.X_add_number
& 0x8000)
1148 high_expr
.X_add_number
+= 0x10000;
1149 high_expr
.X_add_number
=
1150 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1151 r
= BFD_RELOC_UNUSED
;
1154 r
= BFD_RELOC_HI16_S
;
1157 * If the macro is about to expand into a second instruction,
1158 * print a warning if needed. We need to pass ip as a parameter
1159 * to generate a better warning message here...
1161 if (mips_warn_about_macros
&& *counter
== 1)
1162 as_warn ("Macro instruction expanded into multiple instructions");
1164 *counter
+= 1; /* bump instruction counter */
1166 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1167 assert (insn
.insn_mo
);
1168 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1169 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1171 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1172 if (r
== BFD_RELOC_UNUSED
)
1174 insn
.insn_opcode
|= high_expr
.X_add_number
;
1175 append_insn (&insn
, NULL
, r
);
1178 append_insn (&insn
, &high_expr
, r
);
1182 * Generates code to set the $at register to true (one)
1183 * if reg is less than the immediate expression.
1186 set_at (counter
, reg
, unsignedp
)
1191 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1192 macro_build (counter
, &imm_expr
,
1193 unsignedp
? "sltiu" : "slti",
1197 load_register (counter
, AT
, &imm_expr
);
1198 macro_build (counter
, NULL
,
1199 unsignedp
? "sltu" : "slt",
1200 "d,v,t", AT
, reg
, AT
);
1204 /* Warn if an expression is not a constant. */
1207 check_absolute_expr (ip
, ex
)
1208 struct mips_cl_insn
*ip
;
1211 if (ex
->X_op
!= O_constant
)
1212 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1216 * This routine generates the least number of instructions neccessary to load
1217 * an absolute expression value into a register.
1220 load_register (counter
, reg
, ep
)
1225 assert (ep
->X_op
== O_constant
);
1226 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1227 macro_build (counter
, ep
,
1228 mips_isa
< 3 ? "addiu" : "daddiu",
1230 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1231 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1232 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1233 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1234 == ~ (offsetT
) 0x7fffffff))
1236 macro_build (counter
, ep
, "lui", "t,u", reg
);
1237 if ((ep
->X_add_number
& 0xffff) != 0)
1238 macro_build (counter
, ep
, "ori", "t,r,i", reg
, reg
);
1240 else if (mips_isa
< 3)
1242 as_bad ("Number larger than 32 bits");
1243 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1248 expressionS hi32
, lo32
;
1252 hi32
.X_add_number
>>= shift
;
1253 hi32
.X_add_number
&= 0xffffffff;
1254 if ((hi32
.X_add_number
& 0x80000000) != 0)
1255 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1256 load_register (counter
, reg
, &hi32
);
1258 lo32
.X_add_number
&= 0xffffffff;
1259 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1260 macro_build (counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
1265 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1267 mid16
.X_add_number
>>= 16;
1268 macro_build (counter
, &mid16
, "ori", "t,r,i", reg
, reg
);
1269 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1271 if ((lo32
.X_add_number
& 0xffff) != 0)
1272 macro_build (counter
, &lo32
, "ori", "t,r,i", reg
, reg
);
1278 * This routine implements the seemingly endless macro or synthesized
1279 * instructions and addressing modes in the mips assembly language. Many
1280 * of these macros are simple and are similar to each other. These could
1281 * probably be handled by some kind of table or grammer aproach instead of
1282 * this verbose method. Others are not simple macros but are more like
1283 * optimizing code generation.
1284 * One interesting optimization is when several store macros appear
1285 * consecutivly that would load AT with the upper half of the same address.
1286 * The ensuing load upper instructions are ommited. This implies some kind
1287 * of global optimization. We currently only optimize within a single macro.
1288 * For many of the load and store macros if the address is specified as a
1289 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1290 * first load register 'at' with zero and use it as the base register. The
1291 * mips assembler simply uses register $zero. Just one tiny optimization
1296 struct mips_cl_insn
*ip
;
1298 register int treg
, sreg
, dreg
, breg
;
1312 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1313 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1314 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1315 mask
= ip
->insn_mo
->mask
;
1317 expr1
.X_op
= O_constant
;
1318 expr1
.X_op_symbol
= NULL
;
1319 expr1
.X_add_symbol
= NULL
;
1320 expr1
.X_add_number
= 1;
1332 mips_emit_delays ();
1335 expr1
.X_add_number
= 8;
1336 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1338 macro_build (&icnt
, NULL
, "nop", "", 0);
1340 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1341 macro_build (&icnt
, NULL
,
1342 dbl
? "dsub" : "sub",
1343 "d,v,t", dreg
, 0, sreg
);
1366 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1368 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1371 load_register (&icnt
, AT
, &imm_expr
);
1372 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1391 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1393 if (mask
!= M_NOR_I
)
1394 macro_build (&icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
);
1397 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1398 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1403 load_register (&icnt
, AT
, &imm_expr
);
1404 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1421 if (imm_expr
.X_add_number
== 0)
1423 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1426 load_register (&icnt
, AT
, &imm_expr
);
1427 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1435 macro_build (&icnt
, &offset_expr
,
1436 likely
? "bgezl" : "bgez",
1442 macro_build (&icnt
, &offset_expr
,
1443 likely
? "blezl" : "blez",
1447 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1448 macro_build (&icnt
, &offset_expr
,
1449 likely
? "beql" : "beq",
1456 /* check for > max integer */
1457 maxnum
= 0x7fffffff;
1465 if (imm_expr
.X_add_number
>= maxnum
)
1468 /* result is always false */
1471 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1472 macro_build (&icnt
, NULL
, "nop", "", 0);
1476 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1477 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1481 imm_expr
.X_add_number
++;
1485 if (mask
== M_BGEL_I
)
1487 if (imm_expr
.X_add_number
== 0)
1489 macro_build (&icnt
, &offset_expr
,
1490 likely
? "bgezl" : "bgez",
1494 if (imm_expr
.X_add_number
== 1)
1496 macro_build (&icnt
, &offset_expr
,
1497 likely
? "bgtzl" : "bgtz",
1501 maxnum
= 0x7fffffff;
1509 maxnum
= - maxnum
- 1;
1510 if (imm_expr
.X_add_number
<= maxnum
)
1513 /* result is always true */
1514 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1515 macro_build (&icnt
, &offset_expr
, "b", "p");
1518 set_at (&icnt
, sreg
, 0);
1519 macro_build (&icnt
, &offset_expr
,
1520 likely
? "beql" : "beq",
1531 macro_build (&icnt
, &offset_expr
,
1532 likely
? "beql" : "beq",
1536 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1537 macro_build (&icnt
, &offset_expr
,
1538 likely
? "beql" : "beq",
1545 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1547 imm_expr
.X_add_number
++;
1551 if (mask
== M_BGEUL_I
)
1553 if (imm_expr
.X_add_number
== 0)
1555 if (imm_expr
.X_add_number
== 1)
1557 macro_build (&icnt
, &offset_expr
,
1558 likely
? "bnel" : "bne",
1562 set_at (&icnt
, sreg
, 1);
1563 macro_build (&icnt
, &offset_expr
,
1564 likely
? "beql" : "beq",
1573 macro_build (&icnt
, &offset_expr
,
1574 likely
? "bgtzl" : "bgtz",
1580 macro_build (&icnt
, &offset_expr
,
1581 likely
? "bltzl" : "bltz",
1585 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1586 macro_build (&icnt
, &offset_expr
,
1587 likely
? "bnel" : "bne",
1596 macro_build (&icnt
, &offset_expr
,
1597 likely
? "bnel" : "bne",
1603 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1604 macro_build (&icnt
, &offset_expr
,
1605 likely
? "bnel" : "bne",
1614 macro_build (&icnt
, &offset_expr
,
1615 likely
? "blezl" : "blez",
1621 macro_build (&icnt
, &offset_expr
,
1622 likely
? "bgezl" : "bgez",
1626 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1627 macro_build (&icnt
, &offset_expr
,
1628 likely
? "beql" : "beq",
1635 maxnum
= 0x7fffffff;
1643 if (imm_expr
.X_add_number
>= maxnum
)
1645 imm_expr
.X_add_number
++;
1649 if (mask
== M_BLTL_I
)
1651 if (imm_expr
.X_add_number
== 0)
1653 macro_build (&icnt
, &offset_expr
,
1654 likely
? "bltzl" : "bltz",
1658 if (imm_expr
.X_add_number
== 1)
1660 macro_build (&icnt
, &offset_expr
,
1661 likely
? "blezl" : "blez",
1665 set_at (&icnt
, sreg
, 0);
1666 macro_build (&icnt
, &offset_expr
,
1667 likely
? "bnel" : "bne",
1676 macro_build (&icnt
, &offset_expr
,
1677 likely
? "beql" : "beq",
1683 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1684 macro_build (&icnt
, &offset_expr
,
1685 likely
? "beql" : "beq",
1692 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1694 imm_expr
.X_add_number
++;
1698 if (mask
== M_BLTUL_I
)
1700 if (imm_expr
.X_add_number
== 0)
1702 if (imm_expr
.X_add_number
== 1)
1704 macro_build (&icnt
, &offset_expr
,
1705 likely
? "beql" : "beq",
1709 set_at (&icnt
, sreg
, 1);
1710 macro_build (&icnt
, &offset_expr
,
1711 likely
? "bnel" : "bne",
1720 macro_build (&icnt
, &offset_expr
,
1721 likely
? "bltzl" : "bltz",
1727 macro_build (&icnt
, &offset_expr
,
1728 likely
? "bgtzl" : "bgtz",
1732 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1733 macro_build (&icnt
, &offset_expr
,
1734 likely
? "bnel" : "bne",
1745 macro_build (&icnt
, &offset_expr
,
1746 likely
? "bnel" : "bne",
1750 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1751 macro_build (&icnt
, &offset_expr
,
1752 likely
? "bnel" : "bne",
1768 as_warn ("Divide by zero.");
1769 macro_build (&icnt
, NULL
, "break", "c", 7);
1773 mips_emit_delays ();
1775 macro_build (&icnt
, NULL
,
1776 dbl
? "ddiv" : "div",
1777 "z,s,t", sreg
, treg
);
1778 expr1
.X_add_number
= 8;
1779 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1780 macro_build (&icnt
, NULL
, "nop", "", 0);
1781 macro_build (&icnt
, NULL
, "break", "c", 7);
1782 expr1
.X_add_number
= -1;
1783 macro_build (&icnt
, &expr1
,
1784 dbl
? "daddiu" : "addiu",
1786 expr1
.X_add_number
= dbl
? 20 : 16;
1787 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1790 expr1
.X_add_number
= 1;
1791 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1792 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1796 expr1
.X_add_number
= 0x80000000;
1797 macro_build (&icnt
, &expr1
, "lui", "t,u", AT
);
1799 expr1
.X_add_number
= 8;
1800 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1801 macro_build (&icnt
, NULL
, "nop", "", 0);
1802 macro_build (&icnt
, NULL
, "break", "c", 6);
1804 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1843 if (imm_expr
.X_add_number
== 0)
1845 as_warn ("Divide by zero.");
1846 macro_build (&icnt
, NULL
, "break", "c", 7);
1849 if (imm_expr
.X_add_number
== 1)
1851 if (strcmp (s2
, "mflo") == 0)
1852 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1854 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1857 if (imm_expr
.X_add_number
== -1
1858 && s
[strlen (s
) - 1] != 'u')
1860 if (strcmp (s2
, "mflo") == 0)
1863 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1865 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1868 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1872 load_register (&icnt
, AT
, &imm_expr
);
1873 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
1874 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1893 mips_emit_delays ();
1895 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
1896 expr1
.X_add_number
= 8;
1897 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1898 macro_build (&icnt
, NULL
, "nop", "", 0);
1899 macro_build (&icnt
, NULL
, "break", "c", 7);
1901 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1905 if (offset_expr
.X_op
== O_constant
)
1907 load_register (&icnt
, treg
, &offset_expr
);
1910 if (gp_reference (&offset_expr
))
1911 macro_build (&icnt
, &offset_expr
,
1912 mips_isa
< 3 ? "addiu" : "daddiu",
1916 /* FIXME: This won't work for a 64 bit address. */
1917 macro_build_lui (&icnt
, &offset_expr
, treg
);
1918 macro_build (&icnt
, &offset_expr
,
1919 mips_isa
< 3 ? "addiu" : "daddiu",
1920 "t,r,j", treg
, treg
);
1925 tempreg
= (breg
== treg
) ? AT
: treg
;
1926 if (offset_expr
.X_op
== O_constant
)
1927 load_register (&icnt
, tempreg
, &offset_expr
);
1928 else if (gp_reference (&offset_expr
))
1929 macro_build (&icnt
, &offset_expr
,
1930 mips_isa
< 3 ? "addiu" : "daddiu",
1931 "t,r,j", tempreg
, GP
);
1934 /* FIXME: This won't work for a 64 bit address. */
1935 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1936 macro_build (&icnt
, &offset_expr
,
1937 mips_isa
< 3 ? "addiu" : "daddiu",
1938 "t,r,j", tempreg
, tempreg
);
1941 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
2011 if (breg
== treg
|| coproc
)
2080 if (mask
== M_LWC1_AB
2081 || mask
== M_SWC1_AB
2083 || mask
== M_LDC1_AB
2084 || mask
== M_SDC1_AB
)
2090 if (gp_reference (&offset_expr
))
2094 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2097 macro_build (&icnt
, (expressionS
*) NULL
,
2098 mips_isa
< 3 ? "addu" : "daddu",
2099 "d,v,t", tempreg
, breg
, GP
);
2103 /* FIXME: This won't work for a 64 bit address. */
2104 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2106 macro_build (&icnt
, NULL
,
2107 mips_isa
< 3 ? "addu" : "daddu",
2108 "d,v,t", tempreg
, tempreg
, breg
);
2110 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2117 load_register (&icnt
, treg
, &imm_expr
);
2122 lw $v0,%lo(foo)($at)
2123 lw $v1,%lo(foo+4)($at)
2128 /* FIXME: This won't work for a 64 bit address. */
2129 macro_build_lui (&icnt
, &offset_expr
, AT
);
2131 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2134 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2135 offset_expr
.X_add_number
+= 4;
2136 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2141 /* Load a floating point number from the .lit8 section. */
2144 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2150 /* Even on a big endian machine $fn comes before $fn+1. We have
2151 to adjust when loading from memory. */
2152 assert (mips_isa
< 2);
2153 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2154 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2156 offset_expr
.X_add_number
+= 4;
2157 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2158 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2164 * The MIPS assembler seems to check for X_add_number not
2165 * being double aligned and generating:
2168 * addiu at,at,%lo(foo+1)
2171 * But, the resulting address is the same after relocation so why
2172 * generate the extra instruction?
2174 if (gp_reference (&offset_expr
))
2180 macro_build (&icnt
, &offset_expr
,
2181 mips_isa
< 3 ? "addu" : "daddu",
2182 "d,v,t", AT
, breg
, GP
);
2188 /* FIXME: This won't work for a 64 bit address. */
2189 macro_build_lui (&icnt
, &offset_expr
, AT
);
2191 macro_build (&icnt
, NULL
,
2192 mips_isa
< 3 ? "addu" : "daddu",
2193 "d,v,t", AT
, AT
, breg
);
2197 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2200 /* Even on a big endian machine $fn comes before $fn+1. We
2201 have to adjust when loading from memory. */
2202 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2203 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2205 offset_expr
.X_add_number
+= 4;
2206 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2207 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2220 assert (mips_isa
< 3);
2221 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2222 offset_expr
.X_add_number
+= 4;
2223 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2246 if (gp_reference (&offset_expr
))
2254 macro_build (&icnt
, (expressionS
*) NULL
,
2255 mips_isa
< 3 ? "addu" : "daddu",
2256 "d,v,t", tempreg
, breg
, GP
);
2260 /* FIXME: This won't work for a 64 bit address. */
2261 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2263 macro_build (&icnt
, NULL
,
2264 mips_isa
< 3 ? "addu" : "daddu",
2265 "d,v,t", tempreg
, tempreg
, breg
);
2268 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2271 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2272 offset_expr
.X_add_number
+= 4;
2273 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2282 macro_build (&icnt
, NULL
,
2283 dbl
? "dmultu" : "multu",
2285 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2291 /* The MIPS assembler some times generates shifts and adds. I'm
2292 not trying to be that fancy. GCC should do this for us
2294 load_register (&icnt
, AT
, &imm_expr
);
2295 macro_build (&icnt
, NULL
,
2296 dbl
? "dmult" : "mult",
2298 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2304 mips_emit_delays ();
2306 macro_build (&icnt
, NULL
,
2307 dbl
? "dmult" : "mult",
2309 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2310 macro_build (&icnt
, NULL
,
2311 dbl
? "dsra32" : "sra",
2312 "d,w,<", dreg
, dreg
, 31);
2313 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2314 expr1
.X_add_number
= 8;
2315 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2316 macro_build (&icnt
, NULL
, "nop", "", 0);
2317 macro_build (&icnt
, NULL
, "break", "c", 6);
2319 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2325 mips_emit_delays ();
2327 macro_build (&icnt
, NULL
,
2328 dbl
? "dmultu" : "multu",
2330 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2331 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2332 expr1
.X_add_number
= 8;
2333 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2334 macro_build (&icnt
, NULL
, "nop", "", 0);
2335 macro_build (&icnt
, NULL
, "break", "c", 6);
2340 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2341 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2342 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2343 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2347 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2348 imm_expr
.X_add_number
& 0x1f);
2349 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2350 (0 - imm_expr
.X_add_number
) & 0x1f);
2351 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2355 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2356 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2357 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2358 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2362 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2363 imm_expr
.X_add_number
& 0x1f);
2364 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2365 (0 - imm_expr
.X_add_number
) & 0x1f);
2366 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2370 assert (mips_isa
< 2);
2371 /* Even on a big endian machine $fn comes before $fn+1. We have
2372 to adjust when storing to memory. */
2373 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2374 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2376 offset_expr
.X_add_number
+= 4;
2377 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2378 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2383 if (gp_reference (&offset_expr
))
2389 macro_build (&icnt
, (expressionS
*) NULL
,
2390 mips_isa
< 3 ? "addu" : "daddu",
2391 "d,v,t", AT
, breg
, GP
);
2397 /* FIXME: This won't work for a 64 bit address. */
2398 macro_build_lui (&icnt
, &offset_expr
, AT
);
2400 macro_build (&icnt
, NULL
,
2401 mips_isa
< 3 ? "addu" : "daddu",
2402 "d,v,t", AT
, AT
, breg
);
2406 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2409 /* Even on a big endian machine $fn comes before $fn+1. We
2410 have to adjust when storing to memory. */
2411 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2412 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2414 offset_expr
.X_add_number
+= 4;
2415 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2416 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2425 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2427 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2430 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2431 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2436 if (imm_expr
.X_add_number
== 0)
2438 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2443 as_warn ("Instruction %s: result is always false",
2445 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2448 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2450 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2453 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2455 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2456 macro_build (&icnt
, &imm_expr
,
2457 mips_isa
< 3 ? "addiu" : "daddiu",
2458 "t,r,j", dreg
, sreg
);
2463 load_register (&icnt
, AT
, &imm_expr
);
2464 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2467 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2472 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2478 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2479 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2482 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2484 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2486 macro_build (&icnt
, &expr1
,
2487 mask
== M_SGE_I
? "slti" : "sltiu",
2488 "t,r,j", dreg
, sreg
);
2493 load_register (&icnt
, AT
, &imm_expr
);
2494 macro_build (&icnt
, NULL
,
2495 mask
== M_SGE_I
? "slt" : "sltu",
2496 "d,v,t", dreg
, sreg
, AT
);
2499 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2504 case M_SGT
: /* sreg > treg <==> treg < sreg */
2510 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2513 case M_SGT_I
: /* sreg > I <==> I < sreg */
2519 load_register (&icnt
, AT
, &imm_expr
);
2520 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2523 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2529 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2530 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2533 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2539 load_register (&icnt
, AT
, &imm_expr
);
2540 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2541 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2545 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2547 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2550 load_register (&icnt
, AT
, &imm_expr
);
2551 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2555 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2557 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2560 load_register (&icnt
, AT
, &imm_expr
);
2561 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2566 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2568 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2571 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2572 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2577 if (imm_expr
.X_add_number
== 0)
2579 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2584 as_warn ("Instruction %s: result is always true",
2586 macro_build (&icnt
, &expr1
,
2587 mips_isa
< 3 ? "addiu" : "daddiu",
2591 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2593 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2596 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2598 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2599 macro_build (&icnt
, &imm_expr
,
2600 mips_isa
< 3 ? "addiu" : "daddiu",
2601 "t,r,j", dreg
, sreg
);
2606 load_register (&icnt
, AT
, &imm_expr
);
2607 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2610 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2618 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2620 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2621 macro_build (&icnt
, &imm_expr
,
2622 dbl
? "daddi" : "addi",
2623 "t,r,j", dreg
, sreg
);
2626 load_register (&icnt
, AT
, &imm_expr
);
2627 macro_build (&icnt
, NULL
,
2628 dbl
? "dsub" : "sub",
2629 "d,v,t", dreg
, sreg
, AT
);
2635 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2637 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2638 macro_build (&icnt
, &imm_expr
,
2639 dbl
? "daddiu" : "addiu",
2640 "t,r,j", dreg
, sreg
);
2643 load_register (&icnt
, AT
, &imm_expr
);
2644 macro_build (&icnt
, NULL
,
2645 dbl
? "dsubu" : "subu",
2646 "d,v,t", dreg
, sreg
, AT
);
2667 load_register (&icnt
, AT
, &imm_expr
);
2668 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2673 assert (mips_isa
< 2);
2674 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2675 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2678 * Is the double cfc1 instruction a bug in the mips assembler;
2679 * or is there a reason for it?
2681 mips_emit_delays ();
2683 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2684 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2685 macro_build (&icnt
, NULL
, "nop", "");
2686 expr1
.X_add_number
= 3;
2687 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2688 expr1
.X_add_number
= 2;
2689 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2690 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2691 macro_build (&icnt
, NULL
, "nop", "");
2692 macro_build (&icnt
, NULL
,
2693 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2694 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2695 macro_build (&icnt
, NULL
, "nop", "");
2705 /* avoid load delay */
2706 offset_expr
.X_add_number
+= 1;
2707 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2708 offset_expr
.X_add_number
-= 1;
2709 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2710 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2711 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2715 /* does this work on a big endian machine? */
2716 offset_expr
.X_add_number
+= 3;
2717 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2718 offset_expr
.X_add_number
-= 3;
2719 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2725 if (offset_expr
.X_op
== O_constant
)
2726 load_register (&icnt
, AT
, &offset_expr
);
2727 else if (gp_reference (&offset_expr
))
2728 macro_build (&icnt
, &offset_expr
,
2729 mips_isa
< 3 ? "addiu" : "daddiu",
2733 /* FIXME: This won't work for a 64 bit address. */
2734 macro_build_lui (&icnt
, &offset_expr
, AT
);
2735 macro_build (&icnt
, &offset_expr
,
2736 mips_isa
< 3 ? "addiu" : "daddiu",
2739 if (mask
== M_ULW_A
)
2741 expr1
.X_add_number
= 3;
2742 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2743 imm_expr
.X_add_number
= 0;
2744 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2748 macro_build (&icnt
, &expr1
,
2749 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2750 imm_expr
.X_add_number
= 0;
2751 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2752 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2753 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2758 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2759 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2760 offset_expr
.X_add_number
+= 1;
2761 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2765 offset_expr
.X_add_number
+= 3;
2766 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2767 offset_expr
.X_add_number
-= 3;
2768 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2773 if (offset_expr
.X_op
== O_constant
)
2774 load_register (&icnt
, AT
, &offset_expr
);
2775 else if (gp_reference (&offset_expr
))
2776 macro_build (&icnt
, &offset_expr
,
2777 mips_isa
< 3 ? "addiu" : "daddiu",
2781 /* FIXME: This won't work for a 64 bit address. */
2782 macro_build_lui (&icnt
, &offset_expr
, AT
);
2783 macro_build (&icnt
, &offset_expr
,
2784 mips_isa
< 3 ? "addiu" : "daddiu",
2787 if (mask
== M_USW_A
)
2789 expr1
.X_add_number
= 3;
2790 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2791 expr1
.X_add_number
= 0;
2792 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2796 expr1
.X_add_number
= 0;
2797 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2798 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2799 expr1
.X_add_number
= 1;
2800 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2801 expr1
.X_add_number
= 0;
2802 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2803 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2804 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2809 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2813 as_warn ("Macro used $at after \".set noat\"");
2818 This routine assembles an instruction into its binary format. As a side
2819 effect it sets one of the global variables imm_reloc or offset_reloc to the
2820 type of relocation to do if one of the operands is an address expression.
2825 struct mips_cl_insn
*ip
;
2830 struct mips_opcode
*insn
;
2833 unsigned int lastregno
= 0;
2838 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2850 as_warn ("Unknown opcode: `%s'", str
);
2853 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2855 as_warn ("`%s' not in hash table.", str
);
2856 insn_error
= "ERROR: Unrecognized opcode";
2864 assert (strcmp (insn
->name
, str
) == 0);
2866 if (insn
->pinfo
== INSN_MACRO
)
2867 insn_isa
= insn
->match
;
2868 else if (insn
->pinfo
& INSN_ISA2
)
2870 else if (insn
->pinfo
& INSN_ISA3
)
2875 if (insn_isa
> mips_isa
)
2877 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2878 && strcmp (insn
->name
, insn
[1].name
) == 0)
2883 insn_error
= "ERROR: instruction not supported on this processor";
2888 ip
->insn_opcode
= insn
->match
;
2889 for (args
= insn
->args
;; ++args
)
2895 case '\0': /* end of args */
2908 ip
->insn_opcode
|= lastregno
<< 21;
2913 ip
->insn_opcode
|= lastregno
<< 16;
2917 ip
->insn_opcode
|= lastregno
<< 11;
2923 /* handle optional base register.
2924 Either the base register is omitted or
2925 we must have a left paren. */
2926 /* this is dependent on the next operand specifier
2927 is a 'b' for base register */
2928 assert (args
[1] == 'b');
2932 case ')': /* these must match exactly */
2937 case '<': /* must be at least one digit */
2939 * According to the manual, if the shift amount is greater
2940 * than 31 or less than 0 the the shift amount should be
2941 * mod 32. In reality the mips assembler issues an error.
2942 * We issue a warning and do the mod.
2944 my_getExpression (&imm_expr
, s
);
2945 check_absolute_expr (ip
, &imm_expr
);
2946 if ((unsigned long) imm_expr
.X_add_number
> 31)
2948 as_warn ("Improper shift amount (%ld)",
2949 (long) imm_expr
.X_add_number
);
2950 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2952 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2953 imm_expr
.X_op
= O_absent
;
2957 case 'c': /* break code */
2958 my_getExpression (&imm_expr
, s
);
2959 check_absolute_expr (ip
, &imm_expr
);
2960 if ((unsigned) imm_expr
.X_add_number
> 1023)
2961 as_warn ("Illegal break code (%ld)",
2962 (long) imm_expr
.X_add_number
);
2963 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
2964 imm_expr
.X_op
= O_absent
;
2968 case 'B': /* syscall code */
2969 my_getExpression (&imm_expr
, s
);
2970 check_absolute_expr (ip
, &imm_expr
);
2971 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
2972 as_warn ("Illegal syscall code (%ld)",
2973 (long) imm_expr
.X_add_number
);
2974 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2975 imm_expr
.X_op
= O_absent
;
2979 case 'C': /* Coprocessor code */
2980 my_getExpression (&imm_expr
, s
);
2981 check_absolute_expr (ip
, &imm_expr
);
2982 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
2984 as_warn ("Coproccesor code > 25 bits (%ld)",
2985 (long) imm_expr
.X_add_number
);
2986 imm_expr
.X_add_number
&= ((1<<25) - 1);
2988 ip
->insn_opcode
|= imm_expr
.X_add_number
;
2989 imm_expr
.X_op
= O_absent
;
2993 case 'b': /* base register */
2994 case 'd': /* destination register */
2995 case 's': /* source register */
2996 case 't': /* target register */
2997 case 'r': /* both target and source */
2998 case 'v': /* both dest and source */
2999 case 'w': /* both dest and target */
3000 case 'E': /* coprocessor target register */
3001 case 'G': /* coprocessor destination register */
3002 case 'x': /* ignore register name */
3003 case 'z': /* must be zero register */
3017 while (isdigit (*s
));
3019 as_bad ("Invalid register number (%d)", regno
);
3021 else if (*args
!= 'E' && *args
!= 'G')
3023 if (s
[1] == 'f' && s
[2] == 'p')
3028 else if (s
[1] == 's' && s
[2] == 'p')
3033 else if (s
[1] == 'g' && s
[2] == 'p')
3038 else if (s
[1] == 'a' && s
[2] == 't')
3045 if (regno
== AT
&& ! mips_noat
)
3046 as_warn ("Used $at without \".set noat\"");
3053 if (c
== 'r' || c
== 'v' || c
== 'w')
3060 /* 'z' only matches $0. */
3061 if (c
== 'z' && regno
!= 0)
3069 ip
->insn_opcode
|= regno
<< 21;
3073 ip
->insn_opcode
|= regno
<< 11;
3078 ip
->insn_opcode
|= regno
<< 16;
3081 /* This case exists because on the r3000 trunc
3082 expands into a macro which requires a gp
3083 register. On the r6000 or r4000 it is
3084 assembled into a single instruction which
3085 ignores the register. Thus the insn version
3086 is MIPS_ISA2 and uses 'x', and the macro
3087 version is MIPS_ISA1 and uses 't'. */
3090 /* This case is for the div instruction, which
3091 acts differently if the destination argument
3092 is $0. This only matches $0, and is checked
3093 outside the switch. */
3104 ip
->insn_opcode
|= lastregno
<< 21;
3107 ip
->insn_opcode
|= lastregno
<< 16;
3112 case 'D': /* floating point destination register */
3113 case 'S': /* floating point source register */
3114 case 'T': /* floating point target register */
3118 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3128 while (isdigit (*s
));
3131 as_bad ("Invalid float register number (%d)", regno
);
3134 !(strcmp (str
, "mtc1") == 0 ||
3135 strcmp (str
, "mfc1") == 0 ||
3136 strcmp (str
, "lwc1") == 0 ||
3137 strcmp (str
, "swc1") == 0))
3138 as_warn ("Float register should be even, was %d",
3146 if (c
== 'V' || c
== 'W')
3156 ip
->insn_opcode
|= regno
<< 6;
3160 ip
->insn_opcode
|= regno
<< 11;
3164 ip
->insn_opcode
|= regno
<< 16;
3172 ip
->insn_opcode
|= lastregno
<< 11;
3175 ip
->insn_opcode
|= lastregno
<< 16;
3181 my_getExpression (&imm_expr
, s
);
3182 check_absolute_expr (ip
, &imm_expr
);
3187 my_getExpression (&offset_expr
, s
);
3188 imm_reloc
= BFD_RELOC_32
;
3200 unsigned char temp
[8];
3202 unsigned int length
;
3207 /* These only appear as the last operand in an
3208 instruction, and every instruction that accepts
3209 them in any variant accepts them in all variants.
3210 This means we don't have to worry about backing out
3211 any changes if the instruction does not match.
3213 The difference between them is the size of the
3214 floating point constant and where it goes. For 'F'
3215 and 'L' the constant is 64 bits; for 'f' and 'l' it
3216 is 32 bits. Where the constant is placed is based
3217 on how the MIPS assembler does things:
3220 f -- immediate value
3224 f64
= *args
== 'F' || *args
== 'L';
3226 save_in
= input_line_pointer
;
3227 input_line_pointer
= s
;
3228 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
3230 s
= input_line_pointer
;
3231 input_line_pointer
= save_in
;
3232 if (err
!= NULL
&& *err
!= '\0')
3234 as_bad ("Bad floating point constant: %s", err
);
3235 memset (temp
, '\0', sizeof temp
);
3236 length
= f64
? 8 : 4;
3239 assert (length
== (f64
? 8 : 4));
3243 imm_expr
.X_op
= O_constant
;
3244 if (byte_order
== LITTLE_ENDIAN
)
3245 imm_expr
.X_add_number
=
3246 (((((((int) temp
[3] << 8)
3251 imm_expr
.X_add_number
=
3252 (((((((int) temp
[0] << 8)
3259 /* Switch to the right section. */
3261 subseg
= now_subseg
;
3265 subseg_new (".rdata", (subsegT
) 0);
3268 subseg_new (".lit8", (subsegT
) 0);
3271 subseg_new (".lit4", (subsegT
) 0);
3275 as_bad ("Can't use floating point insn in this section");
3277 /* Set the argument to the current address in the
3279 offset_expr
.X_op
= O_symbol
;
3280 offset_expr
.X_add_symbol
=
3281 symbol_new ("L0\001", now_seg
,
3282 (valueT
) frag_now_fix (), frag_now
);
3283 offset_expr
.X_add_number
= 0;
3285 /* Put the floating point number into the section. */
3286 p
= frag_more ((int) length
);
3287 memcpy (p
, temp
, length
);
3289 /* Switch back to the original section. */
3290 subseg_set (seg
, subseg
);
3295 case 'i': /* 16 bit unsigned immediate */
3296 case 'j': /* 16 bit signed immediate */
3297 imm_reloc
= BFD_RELOC_LO16
;
3298 c
= my_getSmallExpression (&imm_expr
, s
);
3303 if (imm_expr
.X_op
== O_constant
)
3304 imm_expr
.X_add_number
=
3305 (imm_expr
.X_add_number
>> 16) & 0xffff;
3307 imm_reloc
= BFD_RELOC_HI16_S
;
3309 imm_reloc
= BFD_RELOC_HI16
;
3313 check_absolute_expr (ip
, &imm_expr
);
3316 if (imm_expr
.X_add_number
< 0
3317 || imm_expr
.X_add_number
>= 0x10000)
3319 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3320 !strcmp (insn
->name
, insn
[1].name
))
3322 as_bad ("16 bit expression not in range 0..65535");
3327 if (imm_expr
.X_add_number
< -0x8000 ||
3328 imm_expr
.X_add_number
>= 0x8000)
3330 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3331 !strcmp (insn
->name
, insn
[1].name
))
3333 as_bad ("16 bit expression not in range -32768..32767");
3339 case 'o': /* 16 bit offset */
3340 c
= my_getSmallExpression (&offset_expr
, s
);
3342 * If this value won't fit into a 16 bit offset, then
3343 * go find a macro that will generate the 32 bit offset
3346 if (offset_expr
.X_op
!= O_constant
3347 || offset_expr
.X_add_number
>= 0x8000
3348 || offset_expr
.X_add_number
< -0x8000)
3351 offset_reloc
= BFD_RELOC_LO16
;
3352 if (c
== 'h' || c
== 'H')
3354 assert (offset_expr
.X_op
== O_constant
);
3355 offset_expr
.X_add_number
=
3356 (offset_expr
.X_add_number
>> 16) & 0xffff;
3361 case 'p': /* pc relative offset */
3362 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3363 my_getExpression (&offset_expr
, s
);
3367 case 'u': /* upper 16 bits */
3368 c
= my_getSmallExpression (&imm_expr
, s
);
3369 if (imm_expr
.X_op
!= O_constant
3370 || imm_expr
.X_add_number
< 0
3371 || imm_expr
.X_add_number
>= 0x10000)
3372 as_bad ("lui expression not in range 0..65535");
3373 imm_reloc
= BFD_RELOC_LO16
;
3378 if (imm_expr
.X_op
== O_constant
)
3379 imm_expr
.X_add_number
=
3380 (imm_expr
.X_add_number
>> 16) & 0xffff;
3382 imm_reloc
= BFD_RELOC_HI16_S
;
3384 imm_reloc
= BFD_RELOC_HI16
;
3390 case 'a': /* 26 bit address */
3391 my_getExpression (&offset_expr
, s
);
3393 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3397 fprintf (stderr
, "bad char = '%c'\n", *args
);
3402 /* Args don't match. */
3403 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3404 !strcmp (insn
->name
, insn
[1].name
))
3410 insn_error
= "ERROR: Illegal operands";
3419 my_getSmallExpression (ep
, str
)
3430 ((str
[1] == 'h' && str
[2] == 'i')
3431 || (str
[1] == 'H' && str
[2] == 'I')
3432 || (str
[1] == 'l' && str
[2] == 'o'))
3444 * A small expression may be followed by a base register.
3445 * Scan to the end of this operand, and then back over a possible
3446 * base register. Then scan the small expression up to that
3447 * point. (Based on code in sparc.c...)
3449 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3451 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3453 if (isdigit (sp
[-2]))
3455 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3457 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3463 else if (sp
- 5 >= str
3466 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3467 || (sp
[-3] == 's' && sp
[-2] == 'p')
3468 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3469 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3475 /* no expression means zero offset */
3478 /* %xx(reg) is an error */
3479 ep
->X_op
= O_absent
;
3484 ep
->X_op
= O_absent
;
3487 ep
->X_add_symbol
= NULL
;
3488 ep
->X_op_symbol
= NULL
;
3489 ep
->X_add_number
= 0;
3494 my_getExpression (ep
, str
);
3501 my_getExpression (ep
, str
);
3502 return c
; /* => %hi or %lo encountered */
3506 my_getExpression (ep
, str
)
3512 save_in
= input_line_pointer
;
3513 input_line_pointer
= str
;
3515 expr_end
= input_line_pointer
;
3516 input_line_pointer
= save_in
;
3519 /* Turn a string in input_line_pointer into a floating point constant
3520 of type type, and store the appropriate bytes in *litP. The number
3521 of LITTLENUMS emitted is stored in *sizeP . An error message is
3522 returned, or NULL on OK. */
3525 md_atof (type
, litP
, sizeP
)
3531 LITTLENUM_TYPE words
[4];
3547 return "bad call to md_atof";
3550 t
= atof_ieee (input_line_pointer
, type
, words
);
3552 input_line_pointer
= t
;
3556 if (byte_order
== LITTLE_ENDIAN
)
3558 for (i
= prec
- 1; i
>= 0; i
--)
3560 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3566 for (i
= 0; i
< prec
; i
++)
3568 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3577 md_number_to_chars (buf
, val
, n
)
3625 md_number_to_chars (buf
, hi
, 4);
3650 md_parse_option (argP
, cntP
, vecP
)
3655 /* Accept -nocpp but ignore it. */
3656 if (strcmp (*argP
, "nocpp") == 0)
3662 if (strcmp (*argP
, "EL") == 0
3663 || strcmp (*argP
, "EB") == 0)
3665 /* FIXME: This breaks -L -EL. */
3673 if ((*argP
)[1] == '0')
3682 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3687 if (strncmp (*argP
, "mips", 4) == 0)
3689 mips_isa
= atol (*argP
+ 4);
3692 else if (mips_isa
< 1 || mips_isa
> 3)
3694 as_bad ("-mips%d not supported", mips_isa
);
3701 if (strncmp (*argP
, "mcpu=", 5) == 0)
3705 /* Identify the processor type */
3707 if (strcmp (p
, "default") == 0
3708 || strcmp (p
, "DEFAULT") == 0)
3712 if (*p
== 'r' || *p
== 'R')
3719 if (strcmp (p
, "2000") == 0
3720 || strcmp (p
, "2k") == 0
3721 || strcmp (p
, "2K") == 0)
3726 if (strcmp (p
, "3000") == 0
3727 || strcmp (p
, "3k") == 0
3728 || strcmp (p
, "3K") == 0)
3733 if (strcmp (p
, "4000") == 0
3734 || strcmp (p
, "4k") == 0
3735 || strcmp (p
, "4K") == 0)
3740 if (strcmp (p
, "6000") == 0
3741 || strcmp (p
, "6k") == 0
3742 || strcmp (p
, "6K") == 0)
3749 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3762 if ((*argP
)[1] != '\0')
3763 g_switch_value
= atoi (*argP
+ 1);
3766 **vecP
= (char *) NULL
;
3769 g_switch_value
= atoi (**vecP
);
3772 as_warn ("Number expected after -G");
3778 return 1; /* pretend you parsed the character */
3782 md_pcrel_from (fixP
)
3785 /* return the address of the delay slot */
3786 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3790 md_apply_fix (fixP
, valueP
)
3797 assert (fixP
->fx_size
== 4);
3800 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3802 switch (fixP
->fx_r_type
)
3805 case BFD_RELOC_MIPS_JMP
:
3806 case BFD_RELOC_HI16
:
3807 case BFD_RELOC_HI16_S
:
3808 case BFD_RELOC_LO16
:
3809 case BFD_RELOC_MIPS_GPREL
:
3810 /* Nothing needed to do. The value comes from the reloc entry */
3813 case BFD_RELOC_16_PCREL_S2
:
3815 * We need to save the bits in the instruction since fixup_segment()
3816 * might be deleting the relocation entry (i.e., a branch within
3817 * the current segment).
3820 as_warn ("Branch to odd address (%lx)", value
);
3822 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3823 as_bad ("Relocation overflow");
3825 /* update old instruction data */
3826 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3830 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3834 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3841 insn
|= value
& 0xFFFF;
3842 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
3856 const struct mips_opcode
*p
;
3857 int treg
, sreg
, dreg
, shamt
;
3862 for (i
= 0; i
< NUMOPCODES
; ++i
)
3864 p
= &mips_opcodes
[i
];
3865 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3867 printf ("%08lx %s\t", oc
, p
->name
);
3868 treg
= (oc
>> 16) & 0x1f;
3869 sreg
= (oc
>> 21) & 0x1f;
3870 dreg
= (oc
>> 11) & 0x1f;
3871 shamt
= (oc
>> 6) & 0x1f;
3873 for (args
= p
->args
;; ++args
)
3884 printf ("%c", *args
);
3888 assert (treg
== sreg
);
3889 printf ("$%d,$%d", treg
, sreg
);
3894 printf ("$%d", dreg
);
3899 printf ("$%d", treg
);
3904 printf ("$%d", sreg
);
3908 printf ("0x%08lx", oc
& 0x1ffffff);
3919 printf ("$%d", shamt
);
3930 printf ("%08lx UNDEFINED\n", oc
);
3941 name
= input_line_pointer
;
3942 c
= get_symbol_end ();
3943 p
= (symbolS
*) symbol_find_or_make (name
);
3944 *input_line_pointer
= c
;
3948 /* Align the current frag to a given power of two. The MIPS assembler
3949 also automatically adjusts any preceding label. */
3952 mips_align (to
, fill
)
3956 mips_emit_delays ();
3957 frag_align (to
, fill
);
3958 record_alignment (now_seg
, to
);
3959 if (insn_label
!= NULL
)
3961 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
3962 insn_label
->sy_frag
= frag_now
;
3963 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
3968 /* Align to a given power of two. .align 0 turns off the automatic
3969 alignment used by the data creating pseudo-ops. */
3976 register long temp_fill
;
3977 long max_alignment
= 15;
3981 o Note that the assembler pulls down any immediately preceeding label
3982 to the aligned address.
3983 o It's not documented but auto alignment is reinstated by
3984 a .align pseudo instruction.
3985 o Note also that after auto alignment is turned off the mips assembler
3986 issues an error on attempt to assemble an improperly aligned data item.
3991 temp
= get_absolute_expression ();
3992 if (temp
> max_alignment
)
3993 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
3996 as_warn ("Alignment negative: 0 assumed.");
3999 if (*input_line_pointer
== ',')
4001 input_line_pointer
++;
4002 temp_fill
= get_absolute_expression ();
4009 mips_align (temp
, (int) temp_fill
);
4016 demand_empty_rest_of_line ();
4019 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4020 that there was a previous instruction. */
4023 s_stringer (append_zero
)
4026 mips_emit_delays ();
4028 stringer (append_zero
);
4037 mips_emit_delays ();
4046 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4047 demand_empty_rest_of_line ();
4056 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4057 demand_empty_rest_of_line ();
4061 subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4062 demand_empty_rest_of_line ();
4065 as_bad ("Global pointers not supported; recompile -G 0");
4066 demand_empty_rest_of_line ();
4077 mips_emit_delays ();
4078 if (log_size
> 0 && auto_align
)
4079 mips_align (log_size
, 0);
4081 cons (1 << log_size
);
4088 as_fatal ("Encountered `.err', aborting assembly");
4098 symbolP
= get_symbol ();
4099 if (*input_line_pointer
== ',')
4100 input_line_pointer
++;
4101 size
= get_absolute_expression ();
4102 S_SET_VALUE (symbolP
, size
);
4103 S_SET_EXTERNAL (symbolP
);
4106 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4107 so we use an additional ECOFF specific field. */
4108 symbolP
->ecoff_undefined
= 1;
4116 mips_emit_delays ();
4133 if (strcmp (input_line_pointer
, "O1") != 0
4134 && strcmp (input_line_pointer
, "O2") != 0)
4135 as_warn ("Unrecognized option");
4136 demand_empty_rest_of_line ();
4143 char *name
= input_line_pointer
, ch
;
4145 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4146 input_line_pointer
++;
4147 ch
= *input_line_pointer
;
4148 *input_line_pointer
= '\0';
4150 if (strcmp (name
, "reorder") == 0)
4154 prev_insn_unreordered
= 1;
4155 prev_prev_insn_unreordered
= 1;
4159 else if (strcmp (name
, "noreorder") == 0)
4161 mips_emit_delays ();
4164 else if (strcmp (name
, "at") == 0)
4168 else if (strcmp (name
, "noat") == 0)
4172 else if (strcmp (name
, "macro") == 0)
4174 mips_warn_about_macros
= 0;
4176 else if (strcmp (name
, "nomacro") == 0)
4178 if (mips_noreorder
== 0)
4179 as_bad ("`noreorder' must be set before `nomacro'");
4180 mips_warn_about_macros
= 1;
4182 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4186 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4190 else if (strcmp (name
, "bopt") == 0)
4194 else if (strcmp (name
, "nobopt") == 0)
4200 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4202 *input_line_pointer
= ch
;
4203 demand_empty_rest_of_line ();
4206 /* The same as the usual .space directive, except that we have to
4207 forget about any previous instruction. */
4210 s_mips_space (param
)
4213 mips_emit_delays ();
4224 if (*input_line_pointer
++ != '$')
4226 as_warn ("expected `$'");
4229 if (isdigit ((unsigned char) *input_line_pointer
))
4231 reg
= get_absolute_expression ();
4232 if (reg
< 0 || reg
>= 32)
4234 as_warn ("Bad register number");
4240 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4242 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4244 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4246 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4250 as_warn ("Unrecognized register name");
4253 input_line_pointer
+= 2;
4259 * Translate internal representation of relocation info to BFD target format.
4262 tc_gen_reloc (section
, fixp
)
4268 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4269 assert (reloc
!= 0);
4271 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4272 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4273 if (fixp
->fx_pcrel
== 0)
4274 reloc
->addend
= fixp
->fx_addnumber
;
4279 reloc
->addend
= -reloc
->address
;
4281 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4282 assert (reloc
->howto
!= 0);
4287 /* should never be called */
4289 md_section_align (seg
, addr
)
4293 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4295 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4299 md_estimate_size_before_relax (fragP
, segtype
)
4303 as_fatal ("md_estimate_size_before_relax");
4305 } /* md_estimate_size_before_relax() */
4307 /* This function is called whenever a label is defined. It is used
4308 when handling branch delays; if a branch has a label, we assume we
4312 mips_define_label (sym
)
4320 /* These functions should really be defined by the object file format,
4321 since they are related to debugging information. However, this
4322 code has to work for the a.out format, which does not define them,
4323 so we provide simple versions here. These don't actually generate
4324 any debugging information, but they do simple checking and someday
4325 somebody may make them useful. */
4329 struct loc
*loc_next
;
4330 unsigned long loc_fileno
;
4331 unsigned long loc_lineno
;
4332 unsigned long loc_offset
;
4333 unsigned short loc_delta
;
4334 unsigned short loc_count
;
4343 struct proc
*proc_next
;
4344 struct symbol
*proc_isym
;
4345 struct symbol
*proc_end
;
4346 unsigned long proc_reg_mask
;
4347 unsigned long proc_reg_offset
;
4348 unsigned long proc_fpreg_mask
;
4349 unsigned long proc_fpreg_offset
;
4350 unsigned long proc_frameoffset
;
4351 unsigned long proc_framereg
;
4352 unsigned long proc_pcreg
;
4354 struct file
*proc_file
;
4361 struct file
*file_next
;
4362 unsigned long file_fileno
;
4363 struct symbol
*file_symbol
;
4364 struct symbol
*file_end
;
4365 struct proc
*file_proc
;
4370 static struct obstack proc_frags
;
4371 static procS
*proc_lastP
;
4372 static procS
*proc_rootP
;
4373 static int numprocs
;
4378 obstack_begin (&proc_frags
, 0x2000);
4384 /* check for premature end, nesting errors, etc */
4385 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4386 as_warn ("missing `.end' at end of assembly");
4389 extern char hex_value
[];
4397 if (*input_line_pointer
== '-')
4399 ++input_line_pointer
;
4402 if (!isdigit (*input_line_pointer
))
4403 as_bad ("Expected simple number.");
4404 if (input_line_pointer
[0] == '0')
4406 if (input_line_pointer
[1] == 'x')
4408 input_line_pointer
+= 2;
4409 while (isxdigit (*input_line_pointer
))
4412 val
|= hex_value
[(int) *input_line_pointer
++];
4414 return negative
? -val
: val
;
4418 ++input_line_pointer
;
4419 while (isdigit (*input_line_pointer
))
4422 val
|= *input_line_pointer
++ - '0';
4424 return negative
? -val
: val
;
4427 if (!isdigit (*input_line_pointer
))
4429 printf (" *input_line_pointer == '%c' 0x%02x\n",
4430 *input_line_pointer
, *input_line_pointer
);
4431 as_warn ("Invalid number");
4434 while (isdigit (*input_line_pointer
))
4437 val
+= *input_line_pointer
++ - '0';
4439 return negative
? -val
: val
;
4442 /* The .file directive; just like the usual .file directive, but there
4443 is an initial number which is the ECOFF file index. */
4451 line
= get_number ();
4456 /* The .end directive. */
4464 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4467 demand_empty_rest_of_line ();
4471 if (now_seg
!= text_section
)
4472 as_warn (".end not in text section");
4475 as_warn (".end and no .ent seen yet.");
4481 assert (S_GET_NAME (p
));
4482 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4483 as_warn (".end symbol does not match .ent symbol.");
4486 proc_lastP
->proc_end
= (symbolS
*) 1;
4489 /* The .aent and .ent directives. */
4499 symbolP
= get_symbol ();
4500 if (*input_line_pointer
== ',')
4501 input_line_pointer
++;
4502 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4503 number
= get_number ();
4504 if (now_seg
!= text_section
)
4505 as_warn (".ent or .aent not in text section.");
4507 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4508 as_warn ("missing `.end'");
4512 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4513 procP
->proc_isym
= symbolP
;
4514 procP
->proc_reg_mask
= 0;
4515 procP
->proc_reg_offset
= 0;
4516 procP
->proc_fpreg_mask
= 0;
4517 procP
->proc_fpreg_offset
= 0;
4518 procP
->proc_frameoffset
= 0;
4519 procP
->proc_framereg
= 0;
4520 procP
->proc_pcreg
= 0;
4521 procP
->proc_end
= NULL
;
4522 procP
->proc_next
= NULL
;
4524 proc_lastP
->proc_next
= procP
;
4530 demand_empty_rest_of_line ();
4533 /* The .frame directive. */
4546 frame_reg
= tc_get_register ();
4547 if (*input_line_pointer
== ',')
4548 input_line_pointer
++;
4549 frame_off
= get_absolute_expression ();
4550 if (*input_line_pointer
== ',')
4551 input_line_pointer
++;
4552 pcreg
= tc_get_register ();
4555 assert (proc_rootP
);
4556 proc_rootP
->proc_framereg
= frame_reg
;
4557 proc_rootP
->proc_frameoffset
= frame_off
;
4558 proc_rootP
->proc_pcreg
= pcreg
;
4559 /* bob macho .frame */
4561 /* We don't have to write out a frame stab for unoptimized code. */
4562 if (!(frame_reg
== 30 && frame_off
== 0))
4565 as_warn ("No .ent for .frame to use.");
4566 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4567 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4568 S_SET_TYPE (symP
, N_RMASK
);
4569 S_SET_OTHER (symP
, 0);
4570 S_SET_DESC (symP
, 0);
4571 symP
->sy_forward
= proc_lastP
->proc_isym
;
4572 /* bob perhaps I should have used pseudo set */
4574 demand_empty_rest_of_line ();
4578 /* The .fmask and .mask directives. */
4585 char str
[100], *strP
;
4591 mask
= get_number ();
4592 if (*input_line_pointer
== ',')
4593 input_line_pointer
++;
4594 off
= get_absolute_expression ();
4596 /* bob only for coff */
4597 assert (proc_rootP
);
4598 if (reg_type
== 'F')
4600 proc_rootP
->proc_fpreg_mask
= mask
;
4601 proc_rootP
->proc_fpreg_offset
= off
;
4605 proc_rootP
->proc_reg_mask
= mask
;
4606 proc_rootP
->proc_reg_offset
= off
;
4609 /* bob macho .mask + .fmask */
4611 /* We don't have to write out a mask stab if no saved regs. */
4615 as_warn ("No .ent for .mask to use.");
4617 for (i
= 0; i
< 32; i
++)
4621 sprintf (strP
, "%c%d,", reg_type
, i
);
4622 strP
+= strlen (strP
);
4626 sprintf (strP
, ";%d,", off
);
4627 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4628 S_SET_TYPE (symP
, N_RMASK
);
4629 S_SET_OTHER (symP
, 0);
4630 S_SET_DESC (symP
, 0);
4631 symP
->sy_forward
= proc_lastP
->proc_isym
;
4632 /* bob perhaps I should have used pseudo set */
4637 /* The .loc directive. */
4648 assert (now_seg
== text_section
);
4650 lineno
= get_number ();
4651 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4653 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4654 S_SET_TYPE (symbolP
, N_SLINE
);
4655 S_SET_OTHER (symbolP
, 0);
4656 S_SET_DESC (symbolP
, lineno
);
4657 symbolP
->sy_segment
= now_seg
;
4661 #endif /* ! defined (OBJ_ECOFF) */