1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static struct hash_control
*op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static struct hash_control
*mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static struct hash_control
*micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* Arrays of operands for each instruction. */
816 #define MAX_OPERANDS 6
817 struct mips_operand_array
819 const struct mips_operand
*operand
[MAX_OPERANDS
];
821 static struct mips_operand_array
*mips_operands
;
822 static struct mips_operand_array
*mips16_operands
;
823 static struct mips_operand_array
*micromips_operands
;
825 /* Nop instructions used by emit_nop. */
826 static struct mips_cl_insn nop_insn
;
827 static struct mips_cl_insn mips16_nop_insn
;
828 static struct mips_cl_insn micromips_nop16_insn
;
829 static struct mips_cl_insn micromips_nop32_insn
;
831 /* Sync instructions used by insert sync. */
832 static struct mips_cl_insn sync_insn
;
834 /* The appropriate nop for the current mode. */
835 #define NOP_INSN (mips_opts.mips16 \
837 : (mips_opts.micromips \
838 ? (mips_opts.insn32 \
839 ? µmips_nop32_insn \
840 : µmips_nop16_insn) \
843 /* The size of NOP_INSN in bytes. */
844 #define NOP_INSN_SIZE ((mips_opts.mips16 \
845 || (mips_opts.micromips && !mips_opts.insn32)) \
848 /* If this is set, it points to a frag holding nop instructions which
849 were inserted before the start of a noreorder section. If those
850 nops turn out to be unnecessary, the size of the frag can be
852 static fragS
*prev_nop_frag
;
854 /* The number of nop instructions we created in prev_nop_frag. */
855 static int prev_nop_frag_holds
;
857 /* The number of nop instructions that we know we need in
859 static int prev_nop_frag_required
;
861 /* The number of instructions we've seen since prev_nop_frag. */
862 static int prev_nop_frag_since
;
864 /* Relocations against symbols are sometimes done in two parts, with a HI
865 relocation and a LO relocation. Each relocation has only 16 bits of
866 space to store an addend. This means that in order for the linker to
867 handle carries correctly, it must be able to locate both the HI and
868 the LO relocation. This means that the relocations must appear in
869 order in the relocation table.
871 In order to implement this, we keep track of each unmatched HI
872 relocation. We then sort them so that they immediately precede the
873 corresponding LO relocation. */
878 struct mips_hi_fixup
*next
;
881 /* The section this fixup is in. */
885 /* The list of unmatched HI relocs. */
887 static struct mips_hi_fixup
*mips_hi_fixup_list
;
889 /* The frag containing the last explicit relocation operator.
890 Null if explicit relocations have not been used. */
892 static fragS
*prev_reloc_op_frag
;
894 /* Map mips16 register numbers to normal MIPS register numbers. */
896 static const unsigned int mips16_to_32_reg_map
[] =
898 16, 17, 2, 3, 4, 5, 6, 7
901 /* Map microMIPS register numbers to normal MIPS register numbers. */
903 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
905 /* The microMIPS registers with type h. */
906 static const unsigned int micromips_to_32_reg_h_map1
[] =
908 5, 5, 6, 4, 4, 4, 4, 4
910 static const unsigned int micromips_to_32_reg_h_map2
[] =
912 6, 7, 7, 21, 22, 5, 6, 7
915 /* The microMIPS registers with type m. */
916 static const unsigned int micromips_to_32_reg_m_map
[] =
918 0, 17, 2, 3, 16, 18, 19, 20
921 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
923 /* Classifies the kind of instructions we're interested in when
924 implementing -mfix-vr4120. */
925 enum fix_vr4120_class
933 NUM_FIX_VR4120_CLASSES
936 /* ...likewise -mfix-loongson2f-jump. */
937 static bfd_boolean mips_fix_loongson2f_jump
;
939 /* ...likewise -mfix-loongson2f-nop. */
940 static bfd_boolean mips_fix_loongson2f_nop
;
942 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
943 static bfd_boolean mips_fix_loongson2f
;
945 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
946 there must be at least one other instruction between an instruction
947 of type X and an instruction of type Y. */
948 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
950 /* True if -mfix-vr4120 is in force. */
951 static int mips_fix_vr4120
;
953 /* ...likewise -mfix-vr4130. */
954 static int mips_fix_vr4130
;
956 /* ...likewise -mfix-24k. */
957 static int mips_fix_24k
;
959 /* ...likewise -mfix-rm7000 */
960 static int mips_fix_rm7000
;
962 /* ...likewise -mfix-cn63xxp1 */
963 static bfd_boolean mips_fix_cn63xxp1
;
965 /* ...likewise -mfix-r5900 */
966 static bfd_boolean mips_fix_r5900
;
967 static bfd_boolean mips_fix_r5900_explicit
;
969 /* ...likewise -mfix-loongson3-llsc. */
970 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
972 /* We don't relax branches by default, since this causes us to expand
973 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
974 fail to compute the offset before expanding the macro to the most
975 efficient expansion. */
977 static int mips_relax_branch
;
979 /* TRUE if checks are suppressed for invalid branches between ISA modes.
980 Needed for broken assembly produced by some GCC versions and some
981 sloppy code out there, where branches to data labels are present. */
982 static bfd_boolean mips_ignore_branch_isa
;
984 /* The expansion of many macros depends on the type of symbol that
985 they refer to. For example, when generating position-dependent code,
986 a macro that refers to a symbol may have two different expansions,
987 one which uses GP-relative addresses and one which uses absolute
988 addresses. When generating SVR4-style PIC, a macro may have
989 different expansions for local and global symbols.
991 We handle these situations by generating both sequences and putting
992 them in variant frags. In position-dependent code, the first sequence
993 will be the GP-relative one and the second sequence will be the
994 absolute one. In SVR4 PIC, the first sequence will be for global
995 symbols and the second will be for local symbols.
997 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
998 SECOND are the lengths of the two sequences in bytes. These fields
999 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1000 the subtype has the following flags:
1003 Set if generating PIC code.
1006 Set if it has been decided that we should use the second
1007 sequence instead of the first.
1010 Set in the first variant frag if the macro's second implementation
1011 is longer than its first. This refers to the macro as a whole,
1012 not an individual relaxation.
1015 Set in the first variant frag if the macro appeared in a .set nomacro
1016 block and if one alternative requires a warning but the other does not.
1019 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1022 RELAX_DELAY_SLOT_16BIT
1023 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1026 RELAX_DELAY_SLOT_SIZE_FIRST
1027 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1028 the macro is of the wrong size for the branch delay slot.
1030 RELAX_DELAY_SLOT_SIZE_SECOND
1031 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1032 the macro is of the wrong size for the branch delay slot.
1034 The frag's "opcode" points to the first fixup for relaxable code.
1036 Relaxable macros are generated using a sequence such as:
1038 relax_start (SYMBOL);
1039 ... generate first expansion ...
1041 ... generate second expansion ...
1044 The code and fixups for the unwanted alternative are discarded
1045 by md_convert_frag. */
1046 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1047 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1049 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1050 #define RELAX_SECOND(X) ((X) & 0xff)
1051 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1052 #define RELAX_USE_SECOND 0x20000
1053 #define RELAX_SECOND_LONGER 0x40000
1054 #define RELAX_NOMACRO 0x80000
1055 #define RELAX_DELAY_SLOT 0x100000
1056 #define RELAX_DELAY_SLOT_16BIT 0x200000
1057 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1058 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1060 /* Branch without likely bit. If label is out of range, we turn:
1062 beq reg1, reg2, label
1072 with the following opcode replacements:
1079 bltzal <-> bgezal (with jal label instead of j label)
1081 Even though keeping the delay slot instruction in the delay slot of
1082 the branch would be more efficient, it would be very tricky to do
1083 correctly, because we'd have to introduce a variable frag *after*
1084 the delay slot instruction, and expand that instead. Let's do it
1085 the easy way for now, even if the branch-not-taken case now costs
1086 one additional instruction. Out-of-range branches are not supposed
1087 to be common, anyway.
1089 Branch likely. If label is out of range, we turn:
1091 beql reg1, reg2, label
1092 delay slot (annulled if branch not taken)
1101 delay slot (executed only if branch taken)
1104 It would be possible to generate a shorter sequence by losing the
1105 likely bit, generating something like:
1110 delay slot (executed only if branch taken)
1122 bltzall -> bgezal (with jal label instead of j label)
1123 bgezall -> bltzal (ditto)
1126 but it's not clear that it would actually improve performance. */
1127 #define RELAX_BRANCH_ENCODE(at, pic, \
1128 uncond, likely, link, toofar) \
1129 ((relax_substateT) \
1132 | ((pic) ? 0x20 : 0) \
1133 | ((toofar) ? 0x40 : 0) \
1134 | ((link) ? 0x80 : 0) \
1135 | ((likely) ? 0x100 : 0) \
1136 | ((uncond) ? 0x200 : 0)))
1137 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1138 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1139 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1140 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1141 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1142 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1143 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1145 /* For mips16 code, we use an entirely different form of relaxation.
1146 mips16 supports two versions of most instructions which take
1147 immediate values: a small one which takes some small value, and a
1148 larger one which takes a 16 bit value. Since branches also follow
1149 this pattern, relaxing these values is required.
1151 We can assemble both mips16 and normal MIPS code in a single
1152 object. Therefore, we need to support this type of relaxation at
1153 the same time that we support the relaxation described above. We
1154 use the high bit of the subtype field to distinguish these cases.
1156 The information we store for this type of relaxation is the
1157 argument code found in the opcode file for this relocation, whether
1158 the user explicitly requested a small or extended form, and whether
1159 the relocation is in a jump or jal delay slot. That tells us the
1160 size of the value, and how it should be stored. We also store
1161 whether the fragment is considered to be extended or not. We also
1162 store whether this is known to be a branch to a different section,
1163 whether we have tried to relax this frag yet, and whether we have
1164 ever extended a PC relative fragment because of a shift count. */
1165 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1170 | ((e2) ? 0x100 : 0) \
1171 | ((pic) ? 0x200 : 0) \
1172 | ((sym32) ? 0x400 : 0) \
1173 | ((nomacro) ? 0x800 : 0) \
1174 | ((small) ? 0x1000 : 0) \
1175 | ((ext) ? 0x2000 : 0) \
1176 | ((dslot) ? 0x4000 : 0) \
1177 | ((jal_dslot) ? 0x8000 : 0))
1179 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1180 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1181 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1182 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1183 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1184 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1185 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1186 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1187 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1188 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1190 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1191 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1192 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1193 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1195 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1196 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1198 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1200 /* For microMIPS code, we use relaxation similar to one we use for
1201 MIPS16 code. Some instructions that take immediate values support
1202 two encodings: a small one which takes some small value, and a
1203 larger one which takes a 16 bit value. As some branches also follow
1204 this pattern, relaxing these values is required.
1206 We can assemble both microMIPS and normal MIPS code in a single
1207 object. Therefore, we need to support this type of relaxation at
1208 the same time that we support the relaxation described above. We
1209 use one of the high bits of the subtype field to distinguish these
1212 The information we store for this type of relaxation is the argument
1213 code found in the opcode file for this relocation, the register
1214 selected as the assembler temporary, whether in the 32-bit
1215 instruction mode, whether the branch is unconditional, whether it is
1216 compact, whether there is no delay-slot instruction available to fill
1217 in, whether it stores the link address implicitly in $ra, whether
1218 relaxation of out-of-range 32-bit branches to a sequence of
1219 instructions is enabled, and whether the displacement of a branch is
1220 too large to fit as an immediate argument of a 16-bit and a 32-bit
1221 branch, respectively. */
1222 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1223 uncond, compact, link, nods, \
1224 relax32, toofar16, toofar32) \
1227 | (((at) & 0x1f) << 8) \
1228 | ((insn32) ? 0x2000 : 0) \
1229 | ((pic) ? 0x4000 : 0) \
1230 | ((uncond) ? 0x8000 : 0) \
1231 | ((compact) ? 0x10000 : 0) \
1232 | ((link) ? 0x20000 : 0) \
1233 | ((nods) ? 0x40000 : 0) \
1234 | ((relax32) ? 0x80000 : 0) \
1235 | ((toofar16) ? 0x100000 : 0) \
1236 | ((toofar32) ? 0x200000 : 0))
1237 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1238 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1239 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1240 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1241 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1242 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1243 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1244 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1245 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1246 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1248 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1249 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1250 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1251 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1252 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1253 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1255 /* Sign-extend 16-bit value X. */
1256 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1258 /* Is the given value a sign-extended 32-bit value? */
1259 #define IS_SEXT_32BIT_NUM(x) \
1260 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1261 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1263 /* Is the given value a sign-extended 16-bit value? */
1264 #define IS_SEXT_16BIT_NUM(x) \
1265 (((x) &~ (offsetT) 0x7fff) == 0 \
1266 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1268 /* Is the given value a sign-extended 12-bit value? */
1269 #define IS_SEXT_12BIT_NUM(x) \
1270 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1272 /* Is the given value a sign-extended 9-bit value? */
1273 #define IS_SEXT_9BIT_NUM(x) \
1274 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1276 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1277 #define IS_ZEXT_32BIT_NUM(x) \
1278 (((x) &~ (offsetT) 0xffffffff) == 0 \
1279 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1281 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1283 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1284 (((STRUCT) >> (SHIFT)) & (MASK))
1286 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1287 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1289 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1290 : EXTRACT_BITS ((INSN).insn_opcode, \
1291 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1292 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1293 EXTRACT_BITS ((INSN).insn_opcode, \
1294 MIPS16OP_MASK_##FIELD, \
1295 MIPS16OP_SH_##FIELD)
1297 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1298 #define MIPS16_EXTEND (0xf000U << 16)
1300 /* Whether or not we are emitting a branch-likely macro. */
1301 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1303 /* Global variables used when generating relaxable macros. See the
1304 comment above RELAX_ENCODE for more details about how relaxation
1307 /* 0 if we're not emitting a relaxable macro.
1308 1 if we're emitting the first of the two relaxation alternatives.
1309 2 if we're emitting the second alternative. */
1312 /* The first relaxable fixup in the current frag. (In other words,
1313 the first fixup that refers to relaxable code.) */
1316 /* sizes[0] says how many bytes of the first alternative are stored in
1317 the current frag. Likewise sizes[1] for the second alternative. */
1318 unsigned int sizes
[2];
1320 /* The symbol on which the choice of sequence depends. */
1324 /* Global variables used to decide whether a macro needs a warning. */
1326 /* True if the macro is in a branch delay slot. */
1327 bfd_boolean delay_slot_p
;
1329 /* Set to the length in bytes required if the macro is in a delay slot
1330 that requires a specific length of instruction, otherwise zero. */
1331 unsigned int delay_slot_length
;
1333 /* For relaxable macros, sizes[0] is the length of the first alternative
1334 in bytes and sizes[1] is the length of the second alternative.
1335 For non-relaxable macros, both elements give the length of the
1337 unsigned int sizes
[2];
1339 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1340 instruction of the first alternative in bytes and first_insn_sizes[1]
1341 is the length of the first instruction of the second alternative.
1342 For non-relaxable macros, both elements give the length of the first
1343 instruction in bytes.
1345 Set to zero if we haven't yet seen the first instruction. */
1346 unsigned int first_insn_sizes
[2];
1348 /* For relaxable macros, insns[0] is the number of instructions for the
1349 first alternative and insns[1] is the number of instructions for the
1352 For non-relaxable macros, both elements give the number of
1353 instructions for the macro. */
1354 unsigned int insns
[2];
1356 /* The first variant frag for this macro. */
1358 } mips_macro_warning
;
1360 /* Prototypes for static functions. */
1362 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1364 static void append_insn
1365 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1366 bfd_boolean expansionp
);
1367 static void mips_no_prev_insn (void);
1368 static void macro_build (expressionS
*, const char *, const char *, ...);
1369 static void mips16_macro_build
1370 (expressionS
*, const char *, const char *, va_list *);
1371 static void load_register (int, expressionS
*, int);
1372 static void macro_start (void);
1373 static void macro_end (void);
1374 static void macro (struct mips_cl_insn
*ip
, char *str
);
1375 static void mips16_macro (struct mips_cl_insn
* ip
);
1376 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1377 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1378 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1379 static void mips16_immed
1380 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1381 unsigned int, unsigned long *);
1382 static size_t my_getSmallExpression
1383 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1384 static void my_getExpression (expressionS
*, char *);
1385 static void s_align (int);
1386 static void s_change_sec (int);
1387 static void s_change_section (int);
1388 static void s_cons (int);
1389 static void s_float_cons (int);
1390 static void s_mips_globl (int);
1391 static void s_option (int);
1392 static void s_mipsset (int);
1393 static void s_abicalls (int);
1394 static void s_cpload (int);
1395 static void s_cpsetup (int);
1396 static void s_cplocal (int);
1397 static void s_cprestore (int);
1398 static void s_cpreturn (int);
1399 static void s_dtprelword (int);
1400 static void s_dtpreldword (int);
1401 static void s_tprelword (int);
1402 static void s_tpreldword (int);
1403 static void s_gpvalue (int);
1404 static void s_gpword (int);
1405 static void s_gpdword (int);
1406 static void s_ehword (int);
1407 static void s_cpadd (int);
1408 static void s_insn (int);
1409 static void s_nan (int);
1410 static void s_module (int);
1411 static void s_mips_ent (int);
1412 static void s_mips_end (int);
1413 static void s_mips_frame (int);
1414 static void s_mips_mask (int reg_type
);
1415 static void s_mips_stab (int);
1416 static void s_mips_weakext (int);
1417 static void s_mips_file (int);
1418 static void s_mips_loc (int);
1419 static bfd_boolean
pic_need_relax (symbolS
*);
1420 static int relaxed_branch_length (fragS
*, asection
*, int);
1421 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1422 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1423 static void file_mips_check_options (void);
1425 /* Table and functions used to map between CPU/ISA names, and
1426 ISA levels, and CPU numbers. */
1428 struct mips_cpu_info
1430 const char *name
; /* CPU or ISA name. */
1431 int flags
; /* MIPS_CPU_* flags. */
1432 int ase
; /* Set of ASEs implemented by the CPU. */
1433 int isa
; /* ISA level. */
1434 int cpu
; /* CPU number (default CPU if ISA). */
1437 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1439 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1440 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1441 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1443 /* Command-line options. */
1444 const char *md_shortopts
= "O::g::G:";
1448 OPTION_MARCH
= OPTION_MD_BASE
,
1480 OPTION_NO_SMARTMIPS
,
1490 OPTION_NO_MICROMIPS
,
1505 OPTION_M7000_HILO_FIX
,
1506 OPTION_MNO_7000_HILO_FIX
,
1510 OPTION_NO_FIX_RM7000
,
1511 OPTION_FIX_LOONGSON3_LLSC
,
1512 OPTION_NO_FIX_LOONGSON3_LLSC
,
1513 OPTION_FIX_LOONGSON2F_JUMP
,
1514 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1515 OPTION_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_LOONGSON2F_NOP
,
1518 OPTION_NO_FIX_VR4120
,
1520 OPTION_NO_FIX_VR4130
,
1521 OPTION_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_CN63XXP1
,
1524 OPTION_NO_FIX_R5900
,
1531 OPTION_CONSTRUCT_FLOATS
,
1532 OPTION_NO_CONSTRUCT_FLOATS
,
1536 OPTION_RELAX_BRANCH
,
1537 OPTION_NO_RELAX_BRANCH
,
1538 OPTION_IGNORE_BRANCH_ISA
,
1539 OPTION_NO_IGNORE_BRANCH_ISA
,
1548 OPTION_SINGLE_FLOAT
,
1549 OPTION_DOUBLE_FLOAT
,
1562 OPTION_MVXWORKS_PIC
,
1565 OPTION_NO_ODD_SPREG
,
1568 OPTION_LOONGSON_MMI
,
1569 OPTION_NO_LOONGSON_MMI
,
1570 OPTION_LOONGSON_CAM
,
1571 OPTION_NO_LOONGSON_CAM
,
1572 OPTION_LOONGSON_EXT
,
1573 OPTION_NO_LOONGSON_EXT
,
1574 OPTION_LOONGSON_EXT2
,
1575 OPTION_NO_LOONGSON_EXT2
,
1579 struct option md_longopts
[] =
1581 /* Options which specify architecture. */
1582 {"march", required_argument
, NULL
, OPTION_MARCH
},
1583 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1584 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1585 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1586 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1587 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1588 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1589 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1590 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1591 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1592 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1593 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1594 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1595 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1596 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1597 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1598 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1599 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1601 /* Options which specify Application Specific Extensions (ASEs). */
1602 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1603 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1604 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1605 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1606 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1607 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1608 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1609 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1610 {"mmt", no_argument
, NULL
, OPTION_MT
},
1611 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1612 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1613 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1614 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1615 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1616 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1617 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1618 {"meva", no_argument
, NULL
, OPTION_EVA
},
1619 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1620 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1621 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1622 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1623 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1624 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1625 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1626 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1627 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1628 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1629 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1630 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1631 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1632 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1633 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1634 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1635 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1636 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1637 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1638 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1639 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1640 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1641 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1642 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1643 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1645 /* Old-style architecture options. Don't add more of these. */
1646 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1647 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1648 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1649 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1650 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1651 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1652 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1653 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1655 /* Options which enable bug fixes. */
1656 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1657 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1658 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1659 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1660 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1661 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1662 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1663 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1664 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1665 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1666 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1667 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1668 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1669 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1670 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1671 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1672 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1673 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1674 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1675 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1676 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1678 /* Miscellaneous options. */
1679 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1680 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1681 {"break", no_argument
, NULL
, OPTION_BREAK
},
1682 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1683 {"EB", no_argument
, NULL
, OPTION_EB
},
1684 {"EL", no_argument
, NULL
, OPTION_EL
},
1685 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1686 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1687 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1688 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1689 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1690 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1691 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1692 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1693 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1694 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1695 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1696 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1697 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1698 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1699 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1700 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1701 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1702 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1703 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1704 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1705 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1706 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1707 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1709 /* Strictly speaking this next option is ELF specific,
1710 but we allow it for other ports as well in order to
1711 make testing easier. */
1712 {"32", no_argument
, NULL
, OPTION_32
},
1714 /* ELF-specific options. */
1715 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1716 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1717 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1718 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1719 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1720 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1721 {"n32", no_argument
, NULL
, OPTION_N32
},
1722 {"64", no_argument
, NULL
, OPTION_64
},
1723 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1724 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1725 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1726 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1727 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1728 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1730 {NULL
, no_argument
, NULL
, 0}
1732 size_t md_longopts_size
= sizeof (md_longopts
);
1734 /* Information about either an Application Specific Extension or an
1735 optional architecture feature that, for simplicity, we treat in the
1736 same way as an ASE. */
1739 /* The name of the ASE, used in both the command-line and .set options. */
1742 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1743 and 64-bit architectures, the flags here refer to the subset that
1744 is available on both. */
1747 /* The ASE_* flag used for instructions that are available on 64-bit
1748 architectures but that are not included in FLAGS. */
1749 unsigned int flags64
;
1751 /* The command-line options that turn the ASE on and off. */
1755 /* The minimum required architecture revisions for MIPS32, MIPS64,
1756 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1759 int micromips32_rev
;
1760 int micromips64_rev
;
1762 /* The architecture where the ASE was removed or -1 if the extension has not
1767 /* A table of all supported ASEs. */
1768 static const struct mips_ase mips_ases
[] = {
1769 { "dsp", ASE_DSP
, ASE_DSP64
,
1770 OPTION_DSP
, OPTION_NO_DSP
,
1774 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1775 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1779 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1780 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1784 { "eva", ASE_EVA
, 0,
1785 OPTION_EVA
, OPTION_NO_EVA
,
1789 { "mcu", ASE_MCU
, 0,
1790 OPTION_MCU
, OPTION_NO_MCU
,
1794 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1795 { "mdmx", ASE_MDMX
, 0,
1796 OPTION_MDMX
, OPTION_NO_MDMX
,
1800 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1801 { "mips3d", ASE_MIPS3D
, 0,
1802 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1807 OPTION_MT
, OPTION_NO_MT
,
1811 { "smartmips", ASE_SMARTMIPS
, 0,
1812 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1816 { "virt", ASE_VIRT
, ASE_VIRT64
,
1817 OPTION_VIRT
, OPTION_NO_VIRT
,
1821 { "msa", ASE_MSA
, ASE_MSA64
,
1822 OPTION_MSA
, OPTION_NO_MSA
,
1826 { "xpa", ASE_XPA
, 0,
1827 OPTION_XPA
, OPTION_NO_XPA
,
1831 { "mips16e2", ASE_MIPS16E2
, 0,
1832 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1836 { "crc", ASE_CRC
, ASE_CRC64
,
1837 OPTION_CRC
, OPTION_NO_CRC
,
1841 { "ginv", ASE_GINV
, 0,
1842 OPTION_GINV
, OPTION_NO_GINV
,
1846 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1847 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1851 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1852 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1856 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1857 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1861 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1862 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1867 /* The set of ASEs that require -mfp64. */
1868 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1870 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1871 static const unsigned int mips_ase_groups
[] = {
1872 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1873 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1878 The following pseudo-ops from the Kane and Heinrich MIPS book
1879 should be defined here, but are currently unsupported: .alias,
1880 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1882 The following pseudo-ops from the Kane and Heinrich MIPS book are
1883 specific to the type of debugging information being generated, and
1884 should be defined by the object format: .aent, .begin, .bend,
1885 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1888 The following pseudo-ops from the Kane and Heinrich MIPS book are
1889 not MIPS CPU specific, but are also not specific to the object file
1890 format. This file is probably the best place to define them, but
1891 they are not currently supported: .asm0, .endr, .lab, .struct. */
1893 static const pseudo_typeS mips_pseudo_table
[] =
1895 /* MIPS specific pseudo-ops. */
1896 {"option", s_option
, 0},
1897 {"set", s_mipsset
, 0},
1898 {"rdata", s_change_sec
, 'r'},
1899 {"sdata", s_change_sec
, 's'},
1900 {"livereg", s_ignore
, 0},
1901 {"abicalls", s_abicalls
, 0},
1902 {"cpload", s_cpload
, 0},
1903 {"cpsetup", s_cpsetup
, 0},
1904 {"cplocal", s_cplocal
, 0},
1905 {"cprestore", s_cprestore
, 0},
1906 {"cpreturn", s_cpreturn
, 0},
1907 {"dtprelword", s_dtprelword
, 0},
1908 {"dtpreldword", s_dtpreldword
, 0},
1909 {"tprelword", s_tprelword
, 0},
1910 {"tpreldword", s_tpreldword
, 0},
1911 {"gpvalue", s_gpvalue
, 0},
1912 {"gpword", s_gpword
, 0},
1913 {"gpdword", s_gpdword
, 0},
1914 {"ehword", s_ehword
, 0},
1915 {"cpadd", s_cpadd
, 0},
1916 {"insn", s_insn
, 0},
1918 {"module", s_module
, 0},
1920 /* Relatively generic pseudo-ops that happen to be used on MIPS
1922 {"asciiz", stringer
, 8 + 1},
1923 {"bss", s_change_sec
, 'b'},
1925 {"half", s_cons
, 1},
1926 {"dword", s_cons
, 3},
1927 {"weakext", s_mips_weakext
, 0},
1928 {"origin", s_org
, 0},
1929 {"repeat", s_rept
, 0},
1931 /* For MIPS this is non-standard, but we define it for consistency. */
1932 {"sbss", s_change_sec
, 'B'},
1934 /* These pseudo-ops are defined in read.c, but must be overridden
1935 here for one reason or another. */
1936 {"align", s_align
, 0},
1937 {"byte", s_cons
, 0},
1938 {"data", s_change_sec
, 'd'},
1939 {"double", s_float_cons
, 'd'},
1940 {"float", s_float_cons
, 'f'},
1941 {"globl", s_mips_globl
, 0},
1942 {"global", s_mips_globl
, 0},
1943 {"hword", s_cons
, 1},
1945 {"long", s_cons
, 2},
1946 {"octa", s_cons
, 4},
1947 {"quad", s_cons
, 3},
1948 {"section", s_change_section
, 0},
1949 {"short", s_cons
, 1},
1950 {"single", s_float_cons
, 'f'},
1951 {"stabd", s_mips_stab
, 'd'},
1952 {"stabn", s_mips_stab
, 'n'},
1953 {"stabs", s_mips_stab
, 's'},
1954 {"text", s_change_sec
, 't'},
1955 {"word", s_cons
, 2},
1957 { "extern", ecoff_directive_extern
, 0},
1962 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1964 /* These pseudo-ops should be defined by the object file format.
1965 However, a.out doesn't support them, so we have versions here. */
1966 {"aent", s_mips_ent
, 1},
1967 {"bgnb", s_ignore
, 0},
1968 {"end", s_mips_end
, 0},
1969 {"endb", s_ignore
, 0},
1970 {"ent", s_mips_ent
, 0},
1971 {"file", s_mips_file
, 0},
1972 {"fmask", s_mips_mask
, 'F'},
1973 {"frame", s_mips_frame
, 0},
1974 {"loc", s_mips_loc
, 0},
1975 {"mask", s_mips_mask
, 'R'},
1976 {"verstamp", s_ignore
, 0},
1980 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1981 purpose of the `.dc.a' internal pseudo-op. */
1984 mips_address_bytes (void)
1986 file_mips_check_options ();
1987 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1990 extern void pop_insert (const pseudo_typeS
*);
1993 mips_pop_insert (void)
1995 pop_insert (mips_pseudo_table
);
1996 if (! ECOFF_DEBUGGING
)
1997 pop_insert (mips_nonecoff_pseudo_table
);
2000 /* Symbols labelling the current insn. */
2002 struct insn_label_list
2004 struct insn_label_list
*next
;
2008 static struct insn_label_list
*free_insn_labels
;
2009 #define label_list tc_segment_info_data.labels
2011 static void mips_clear_insn_labels (void);
2012 static void mips_mark_labels (void);
2013 static void mips_compressed_mark_labels (void);
2016 mips_clear_insn_labels (void)
2018 struct insn_label_list
**pl
;
2019 segment_info_type
*si
;
2023 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2026 si
= seg_info (now_seg
);
2027 *pl
= si
->label_list
;
2028 si
->label_list
= NULL
;
2032 /* Mark instruction labels in MIPS16/microMIPS mode. */
2035 mips_mark_labels (void)
2037 if (HAVE_CODE_COMPRESSION
)
2038 mips_compressed_mark_labels ();
2041 static char *expr_end
;
2043 /* An expression in a macro instruction. This is set by mips_ip and
2044 mips16_ip and when populated is always an O_constant. */
2046 static expressionS imm_expr
;
2048 /* The relocatable field in an instruction and the relocs associated
2049 with it. These variables are used for instructions like LUI and
2050 JAL as well as true offsets. They are also used for address
2051 operands in macros. */
2053 static expressionS offset_expr
;
2054 static bfd_reloc_code_real_type offset_reloc
[3]
2055 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2057 /* This is set to the resulting size of the instruction to be produced
2058 by mips16_ip if an explicit extension is used or by mips_ip if an
2059 explicit size is supplied. */
2061 static unsigned int forced_insn_length
;
2063 /* True if we are assembling an instruction. All dot symbols defined during
2064 this time should be treated as code labels. */
2066 static bfd_boolean mips_assembling_insn
;
2068 /* The pdr segment for per procedure frame/regmask info. Not used for
2071 static segT pdr_seg
;
2073 /* The default target format to use. */
2075 #if defined (TE_FreeBSD)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2077 #elif defined (TE_TMIPS)
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2080 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2084 mips_target_format (void)
2086 switch (OUTPUT_FLAVOR
)
2088 case bfd_target_elf_flavour
:
2090 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2091 return (target_big_endian
2092 ? "elf32-bigmips-vxworks"
2093 : "elf32-littlemips-vxworks");
2095 return (target_big_endian
2096 ? (HAVE_64BIT_OBJECTS
2097 ? ELF_TARGET ("elf64-", "big")
2099 ? ELF_TARGET ("elf32-n", "big")
2100 : ELF_TARGET ("elf32-", "big")))
2101 : (HAVE_64BIT_OBJECTS
2102 ? ELF_TARGET ("elf64-", "little")
2104 ? ELF_TARGET ("elf32-n", "little")
2105 : ELF_TARGET ("elf32-", "little"))));
2112 /* Return the ISA revision that is currently in use, or 0 if we are
2113 generating code for MIPS V or below. */
2118 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2121 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2124 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2127 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2130 /* microMIPS implies revision 2 or above. */
2131 if (mips_opts
.micromips
)
2134 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2140 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2143 mips_ase_mask (unsigned int flags
)
2147 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2148 if (flags
& mips_ase_groups
[i
])
2149 flags
|= mips_ase_groups
[i
];
2153 /* Check whether the current ISA supports ASE. Issue a warning if
2157 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2161 static unsigned int warned_isa
;
2162 static unsigned int warned_fp32
;
2164 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2165 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2167 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2168 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2169 && (warned_isa
& ase
->flags
) != ase
->flags
)
2171 warned_isa
|= ase
->flags
;
2172 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2173 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2175 as_warn (_("the %d-bit %s architecture does not support the"
2176 " `%s' extension"), size
, base
, ase
->name
);
2178 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2179 ase
->name
, base
, size
, min_rev
);
2181 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2182 && (warned_isa
& ase
->flags
) != ase
->flags
)
2184 warned_isa
|= ase
->flags
;
2185 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2186 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2187 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2188 ase
->name
, base
, size
, ase
->rem_rev
);
2191 if ((ase
->flags
& FP64_ASES
)
2192 && mips_opts
.fp
!= 64
2193 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2195 warned_fp32
|= ase
->flags
;
2196 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2200 /* Check all enabled ASEs to see whether they are supported by the
2201 chosen architecture. */
2204 mips_check_isa_supports_ases (void)
2206 unsigned int i
, mask
;
2208 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2210 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2211 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2212 mips_check_isa_supports_ase (&mips_ases
[i
]);
2216 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2217 that were affected. */
2220 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2221 bfd_boolean enabled_p
)
2225 mask
= mips_ase_mask (ase
->flags
);
2228 /* Clear combination ASE flags, which need to be recalculated based on
2229 updated regular ASE settings. */
2230 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2233 opts
->ase
|= ase
->flags
;
2235 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2236 instructions which are only valid when both ASEs are enabled.
2237 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2238 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2240 opts
->ase
|= ASE_XPA_VIRT
;
2241 mask
|= ASE_XPA_VIRT
;
2243 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2245 opts
->ase
|= ASE_MIPS16E2_MT
;
2246 mask
|= ASE_MIPS16E2_MT
;
2249 /* The EVA Extension has instructions which are only valid when the R6 ISA
2250 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2252 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2254 opts
->ase
|= ASE_EVA_R6
;
2261 /* Return the ASE called NAME, or null if none. */
2263 static const struct mips_ase
*
2264 mips_lookup_ase (const char *name
)
2268 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2269 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2270 return &mips_ases
[i
];
2274 /* Return the length of a microMIPS instruction in bytes. If bits of
2275 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2276 otherwise it is a 32-bit instruction. */
2278 static inline unsigned int
2279 micromips_insn_length (const struct mips_opcode
*mo
)
2281 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2284 /* Return the length of MIPS16 instruction OPCODE. */
2286 static inline unsigned int
2287 mips16_opcode_length (unsigned long opcode
)
2289 return (opcode
>> 16) == 0 ? 2 : 4;
2292 /* Return the length of instruction INSN. */
2294 static inline unsigned int
2295 insn_length (const struct mips_cl_insn
*insn
)
2297 if (mips_opts
.micromips
)
2298 return micromips_insn_length (insn
->insn_mo
);
2299 else if (mips_opts
.mips16
)
2300 return mips16_opcode_length (insn
->insn_opcode
);
2305 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2308 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2313 insn
->insn_opcode
= mo
->match
;
2316 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2317 insn
->fixp
[i
] = NULL
;
2318 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2319 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2320 insn
->mips16_absolute_jump_p
= 0;
2321 insn
->complete_p
= 0;
2322 insn
->cleared_p
= 0;
2325 /* Get a list of all the operands in INSN. */
2327 static const struct mips_operand_array
*
2328 insn_operands (const struct mips_cl_insn
*insn
)
2330 if (insn
->insn_mo
>= &mips_opcodes
[0]
2331 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2332 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2334 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2335 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2336 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2338 if (insn
->insn_mo
>= µmips_opcodes
[0]
2339 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2340 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2345 /* Get a description of operand OPNO of INSN. */
2347 static const struct mips_operand
*
2348 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2350 const struct mips_operand_array
*operands
;
2352 operands
= insn_operands (insn
);
2353 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2355 return operands
->operand
[opno
];
2358 /* Install UVAL as the value of OPERAND in INSN. */
2361 insn_insert_operand (struct mips_cl_insn
*insn
,
2362 const struct mips_operand
*operand
, unsigned int uval
)
2364 if (mips_opts
.mips16
2365 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2366 && mips_opcode_32bit_p (insn
->insn_mo
))
2367 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2369 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2372 /* Extract the value of OPERAND from INSN. */
2374 static inline unsigned
2375 insn_extract_operand (const struct mips_cl_insn
*insn
,
2376 const struct mips_operand
*operand
)
2378 return mips_extract_operand (operand
, insn
->insn_opcode
);
2381 /* Record the current MIPS16/microMIPS mode in now_seg. */
2384 mips_record_compressed_mode (void)
2386 segment_info_type
*si
;
2388 si
= seg_info (now_seg
);
2389 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2390 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2391 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2392 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2395 /* Read a standard MIPS instruction from BUF. */
2397 static unsigned long
2398 read_insn (char *buf
)
2400 if (target_big_endian
)
2401 return bfd_getb32 ((bfd_byte
*) buf
);
2403 return bfd_getl32 ((bfd_byte
*) buf
);
2406 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2410 write_insn (char *buf
, unsigned int insn
)
2412 md_number_to_chars (buf
, insn
, 4);
2416 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2417 has length LENGTH. */
2419 static unsigned long
2420 read_compressed_insn (char *buf
, unsigned int length
)
2426 for (i
= 0; i
< length
; i
+= 2)
2429 if (target_big_endian
)
2430 insn
|= bfd_getb16 ((char *) buf
);
2432 insn
|= bfd_getl16 ((char *) buf
);
2438 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2439 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2442 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2446 for (i
= 0; i
< length
; i
+= 2)
2447 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2448 return buf
+ length
;
2451 /* Install INSN at the location specified by its "frag" and "where" fields. */
2454 install_insn (const struct mips_cl_insn
*insn
)
2456 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2457 if (HAVE_CODE_COMPRESSION
)
2458 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2460 write_insn (f
, insn
->insn_opcode
);
2461 mips_record_compressed_mode ();
2464 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2465 and install the opcode in the new location. */
2468 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2473 insn
->where
= where
;
2474 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2475 if (insn
->fixp
[i
] != NULL
)
2477 insn
->fixp
[i
]->fx_frag
= frag
;
2478 insn
->fixp
[i
]->fx_where
= where
;
2480 install_insn (insn
);
2483 /* Add INSN to the end of the output. */
2486 add_fixed_insn (struct mips_cl_insn
*insn
)
2488 char *f
= frag_more (insn_length (insn
));
2489 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2492 /* Start a variant frag and move INSN to the start of the variant part,
2493 marking it as fixed. The other arguments are as for frag_var. */
2496 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2497 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2499 frag_grow (max_chars
);
2500 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2502 frag_var (rs_machine_dependent
, max_chars
, var
,
2503 subtype
, symbol
, offset
, NULL
);
2506 /* Insert N copies of INSN into the history buffer, starting at
2507 position FIRST. Neither FIRST nor N need to be clipped. */
2510 insert_into_history (unsigned int first
, unsigned int n
,
2511 const struct mips_cl_insn
*insn
)
2513 if (mips_relax
.sequence
!= 2)
2517 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2519 history
[i
] = history
[i
- n
];
2525 /* Clear the error in insn_error. */
2528 clear_insn_error (void)
2530 memset (&insn_error
, 0, sizeof (insn_error
));
2533 /* Possibly record error message MSG for the current instruction.
2534 If the error is about a particular argument, ARGNUM is the 1-based
2535 number of that argument, otherwise it is 0. FORMAT is the format
2536 of MSG. Return true if MSG was used, false if the current message
2540 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2545 /* Give priority to errors against specific arguments, and to
2546 the first whole-instruction message. */
2552 /* Keep insn_error if it is against a later argument. */
2553 if (argnum
< insn_error
.min_argnum
)
2556 /* If both errors are against the same argument but are different,
2557 give up on reporting a specific error for this argument.
2558 See the comment about mips_insn_error for details. */
2559 if (argnum
== insn_error
.min_argnum
2561 && strcmp (insn_error
.msg
, msg
) != 0)
2564 insn_error
.min_argnum
+= 1;
2568 insn_error
.min_argnum
= argnum
;
2569 insn_error
.format
= format
;
2570 insn_error
.msg
= msg
;
2574 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2575 as for set_insn_error_format. */
2578 set_insn_error (int argnum
, const char *msg
)
2580 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2583 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2584 as for set_insn_error_format. */
2587 set_insn_error_i (int argnum
, const char *msg
, int i
)
2589 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2593 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2594 are as for set_insn_error_format. */
2597 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2599 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2601 insn_error
.u
.ss
[0] = s1
;
2602 insn_error
.u
.ss
[1] = s2
;
2606 /* Report the error in insn_error, which is against assembly code STR. */
2609 report_insn_error (const char *str
)
2611 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2613 switch (insn_error
.format
)
2620 as_bad (msg
, insn_error
.u
.i
, str
);
2624 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2628 free ((char *) msg
);
2631 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2632 the idea is to make it obvious at a glance that each errata is
2636 init_vr4120_conflicts (void)
2638 #define CONFLICT(FIRST, SECOND) \
2639 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2641 /* Errata 21 - [D]DIV[U] after [D]MACC */
2642 CONFLICT (MACC
, DIV
);
2643 CONFLICT (DMACC
, DIV
);
2645 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2646 CONFLICT (DMULT
, DMULT
);
2647 CONFLICT (DMULT
, DMACC
);
2648 CONFLICT (DMACC
, DMULT
);
2649 CONFLICT (DMACC
, DMACC
);
2651 /* Errata 24 - MT{LO,HI} after [D]MACC */
2652 CONFLICT (MACC
, MTHILO
);
2653 CONFLICT (DMACC
, MTHILO
);
2655 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2656 instruction is executed immediately after a MACC or DMACC
2657 instruction, the result of [either instruction] is incorrect." */
2658 CONFLICT (MACC
, MULT
);
2659 CONFLICT (MACC
, DMULT
);
2660 CONFLICT (DMACC
, MULT
);
2661 CONFLICT (DMACC
, DMULT
);
2663 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2664 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2665 DDIV or DDIVU instruction, the result of the MACC or
2666 DMACC instruction is incorrect.". */
2667 CONFLICT (DMULT
, MACC
);
2668 CONFLICT (DMULT
, DMACC
);
2669 CONFLICT (DIV
, MACC
);
2670 CONFLICT (DIV
, DMACC
);
2680 #define RNUM_MASK 0x00000ff
2681 #define RTYPE_MASK 0x0ffff00
2682 #define RTYPE_NUM 0x0000100
2683 #define RTYPE_FPU 0x0000200
2684 #define RTYPE_FCC 0x0000400
2685 #define RTYPE_VEC 0x0000800
2686 #define RTYPE_GP 0x0001000
2687 #define RTYPE_CP0 0x0002000
2688 #define RTYPE_PC 0x0004000
2689 #define RTYPE_ACC 0x0008000
2690 #define RTYPE_CCC 0x0010000
2691 #define RTYPE_VI 0x0020000
2692 #define RTYPE_VF 0x0040000
2693 #define RTYPE_R5900_I 0x0080000
2694 #define RTYPE_R5900_Q 0x0100000
2695 #define RTYPE_R5900_R 0x0200000
2696 #define RTYPE_R5900_ACC 0x0400000
2697 #define RTYPE_MSA 0x0800000
2698 #define RWARN 0x8000000
2700 #define GENERIC_REGISTER_NUMBERS \
2701 {"$0", RTYPE_NUM | 0}, \
2702 {"$1", RTYPE_NUM | 1}, \
2703 {"$2", RTYPE_NUM | 2}, \
2704 {"$3", RTYPE_NUM | 3}, \
2705 {"$4", RTYPE_NUM | 4}, \
2706 {"$5", RTYPE_NUM | 5}, \
2707 {"$6", RTYPE_NUM | 6}, \
2708 {"$7", RTYPE_NUM | 7}, \
2709 {"$8", RTYPE_NUM | 8}, \
2710 {"$9", RTYPE_NUM | 9}, \
2711 {"$10", RTYPE_NUM | 10}, \
2712 {"$11", RTYPE_NUM | 11}, \
2713 {"$12", RTYPE_NUM | 12}, \
2714 {"$13", RTYPE_NUM | 13}, \
2715 {"$14", RTYPE_NUM | 14}, \
2716 {"$15", RTYPE_NUM | 15}, \
2717 {"$16", RTYPE_NUM | 16}, \
2718 {"$17", RTYPE_NUM | 17}, \
2719 {"$18", RTYPE_NUM | 18}, \
2720 {"$19", RTYPE_NUM | 19}, \
2721 {"$20", RTYPE_NUM | 20}, \
2722 {"$21", RTYPE_NUM | 21}, \
2723 {"$22", RTYPE_NUM | 22}, \
2724 {"$23", RTYPE_NUM | 23}, \
2725 {"$24", RTYPE_NUM | 24}, \
2726 {"$25", RTYPE_NUM | 25}, \
2727 {"$26", RTYPE_NUM | 26}, \
2728 {"$27", RTYPE_NUM | 27}, \
2729 {"$28", RTYPE_NUM | 28}, \
2730 {"$29", RTYPE_NUM | 29}, \
2731 {"$30", RTYPE_NUM | 30}, \
2732 {"$31", RTYPE_NUM | 31}
2734 #define FPU_REGISTER_NAMES \
2735 {"$f0", RTYPE_FPU | 0}, \
2736 {"$f1", RTYPE_FPU | 1}, \
2737 {"$f2", RTYPE_FPU | 2}, \
2738 {"$f3", RTYPE_FPU | 3}, \
2739 {"$f4", RTYPE_FPU | 4}, \
2740 {"$f5", RTYPE_FPU | 5}, \
2741 {"$f6", RTYPE_FPU | 6}, \
2742 {"$f7", RTYPE_FPU | 7}, \
2743 {"$f8", RTYPE_FPU | 8}, \
2744 {"$f9", RTYPE_FPU | 9}, \
2745 {"$f10", RTYPE_FPU | 10}, \
2746 {"$f11", RTYPE_FPU | 11}, \
2747 {"$f12", RTYPE_FPU | 12}, \
2748 {"$f13", RTYPE_FPU | 13}, \
2749 {"$f14", RTYPE_FPU | 14}, \
2750 {"$f15", RTYPE_FPU | 15}, \
2751 {"$f16", RTYPE_FPU | 16}, \
2752 {"$f17", RTYPE_FPU | 17}, \
2753 {"$f18", RTYPE_FPU | 18}, \
2754 {"$f19", RTYPE_FPU | 19}, \
2755 {"$f20", RTYPE_FPU | 20}, \
2756 {"$f21", RTYPE_FPU | 21}, \
2757 {"$f22", RTYPE_FPU | 22}, \
2758 {"$f23", RTYPE_FPU | 23}, \
2759 {"$f24", RTYPE_FPU | 24}, \
2760 {"$f25", RTYPE_FPU | 25}, \
2761 {"$f26", RTYPE_FPU | 26}, \
2762 {"$f27", RTYPE_FPU | 27}, \
2763 {"$f28", RTYPE_FPU | 28}, \
2764 {"$f29", RTYPE_FPU | 29}, \
2765 {"$f30", RTYPE_FPU | 30}, \
2766 {"$f31", RTYPE_FPU | 31}
2768 #define FPU_CONDITION_CODE_NAMES \
2769 {"$fcc0", RTYPE_FCC | 0}, \
2770 {"$fcc1", RTYPE_FCC | 1}, \
2771 {"$fcc2", RTYPE_FCC | 2}, \
2772 {"$fcc3", RTYPE_FCC | 3}, \
2773 {"$fcc4", RTYPE_FCC | 4}, \
2774 {"$fcc5", RTYPE_FCC | 5}, \
2775 {"$fcc6", RTYPE_FCC | 6}, \
2776 {"$fcc7", RTYPE_FCC | 7}
2778 #define COPROC_CONDITION_CODE_NAMES \
2779 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2780 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2781 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2782 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2783 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2784 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2785 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2786 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2788 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2789 {"$a4", RTYPE_GP | 8}, \
2790 {"$a5", RTYPE_GP | 9}, \
2791 {"$a6", RTYPE_GP | 10}, \
2792 {"$a7", RTYPE_GP | 11}, \
2793 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2794 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2795 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2796 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2797 {"$t0", RTYPE_GP | 12}, \
2798 {"$t1", RTYPE_GP | 13}, \
2799 {"$t2", RTYPE_GP | 14}, \
2800 {"$t3", RTYPE_GP | 15}
2802 #define O32_SYMBOLIC_REGISTER_NAMES \
2803 {"$t0", RTYPE_GP | 8}, \
2804 {"$t1", RTYPE_GP | 9}, \
2805 {"$t2", RTYPE_GP | 10}, \
2806 {"$t3", RTYPE_GP | 11}, \
2807 {"$t4", RTYPE_GP | 12}, \
2808 {"$t5", RTYPE_GP | 13}, \
2809 {"$t6", RTYPE_GP | 14}, \
2810 {"$t7", RTYPE_GP | 15}, \
2811 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2812 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2813 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2814 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2816 /* Remaining symbolic register names. */
2817 #define SYMBOLIC_REGISTER_NAMES \
2818 {"$zero", RTYPE_GP | 0}, \
2819 {"$at", RTYPE_GP | 1}, \
2820 {"$AT", RTYPE_GP | 1}, \
2821 {"$v0", RTYPE_GP | 2}, \
2822 {"$v1", RTYPE_GP | 3}, \
2823 {"$a0", RTYPE_GP | 4}, \
2824 {"$a1", RTYPE_GP | 5}, \
2825 {"$a2", RTYPE_GP | 6}, \
2826 {"$a3", RTYPE_GP | 7}, \
2827 {"$s0", RTYPE_GP | 16}, \
2828 {"$s1", RTYPE_GP | 17}, \
2829 {"$s2", RTYPE_GP | 18}, \
2830 {"$s3", RTYPE_GP | 19}, \
2831 {"$s4", RTYPE_GP | 20}, \
2832 {"$s5", RTYPE_GP | 21}, \
2833 {"$s6", RTYPE_GP | 22}, \
2834 {"$s7", RTYPE_GP | 23}, \
2835 {"$t8", RTYPE_GP | 24}, \
2836 {"$t9", RTYPE_GP | 25}, \
2837 {"$k0", RTYPE_GP | 26}, \
2838 {"$kt0", RTYPE_GP | 26}, \
2839 {"$k1", RTYPE_GP | 27}, \
2840 {"$kt1", RTYPE_GP | 27}, \
2841 {"$gp", RTYPE_GP | 28}, \
2842 {"$sp", RTYPE_GP | 29}, \
2843 {"$s8", RTYPE_GP | 30}, \
2844 {"$fp", RTYPE_GP | 30}, \
2845 {"$ra", RTYPE_GP | 31}
2847 #define MIPS16_SPECIAL_REGISTER_NAMES \
2848 {"$pc", RTYPE_PC | 0}
2850 #define MDMX_VECTOR_REGISTER_NAMES \
2851 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2852 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2853 {"$v2", RTYPE_VEC | 2}, \
2854 {"$v3", RTYPE_VEC | 3}, \
2855 {"$v4", RTYPE_VEC | 4}, \
2856 {"$v5", RTYPE_VEC | 5}, \
2857 {"$v6", RTYPE_VEC | 6}, \
2858 {"$v7", RTYPE_VEC | 7}, \
2859 {"$v8", RTYPE_VEC | 8}, \
2860 {"$v9", RTYPE_VEC | 9}, \
2861 {"$v10", RTYPE_VEC | 10}, \
2862 {"$v11", RTYPE_VEC | 11}, \
2863 {"$v12", RTYPE_VEC | 12}, \
2864 {"$v13", RTYPE_VEC | 13}, \
2865 {"$v14", RTYPE_VEC | 14}, \
2866 {"$v15", RTYPE_VEC | 15}, \
2867 {"$v16", RTYPE_VEC | 16}, \
2868 {"$v17", RTYPE_VEC | 17}, \
2869 {"$v18", RTYPE_VEC | 18}, \
2870 {"$v19", RTYPE_VEC | 19}, \
2871 {"$v20", RTYPE_VEC | 20}, \
2872 {"$v21", RTYPE_VEC | 21}, \
2873 {"$v22", RTYPE_VEC | 22}, \
2874 {"$v23", RTYPE_VEC | 23}, \
2875 {"$v24", RTYPE_VEC | 24}, \
2876 {"$v25", RTYPE_VEC | 25}, \
2877 {"$v26", RTYPE_VEC | 26}, \
2878 {"$v27", RTYPE_VEC | 27}, \
2879 {"$v28", RTYPE_VEC | 28}, \
2880 {"$v29", RTYPE_VEC | 29}, \
2881 {"$v30", RTYPE_VEC | 30}, \
2882 {"$v31", RTYPE_VEC | 31}
2884 #define R5900_I_NAMES \
2885 {"$I", RTYPE_R5900_I | 0}
2887 #define R5900_Q_NAMES \
2888 {"$Q", RTYPE_R5900_Q | 0}
2890 #define R5900_R_NAMES \
2891 {"$R", RTYPE_R5900_R | 0}
2893 #define R5900_ACC_NAMES \
2894 {"$ACC", RTYPE_R5900_ACC | 0 }
2896 #define MIPS_DSP_ACCUMULATOR_NAMES \
2897 {"$ac0", RTYPE_ACC | 0}, \
2898 {"$ac1", RTYPE_ACC | 1}, \
2899 {"$ac2", RTYPE_ACC | 2}, \
2900 {"$ac3", RTYPE_ACC | 3}
2902 static const struct regname reg_names
[] = {
2903 GENERIC_REGISTER_NUMBERS
,
2905 FPU_CONDITION_CODE_NAMES
,
2906 COPROC_CONDITION_CODE_NAMES
,
2908 /* The $txx registers depends on the abi,
2909 these will be added later into the symbol table from
2910 one of the tables below once mips_abi is set after
2911 parsing of arguments from the command line. */
2912 SYMBOLIC_REGISTER_NAMES
,
2914 MIPS16_SPECIAL_REGISTER_NAMES
,
2915 MDMX_VECTOR_REGISTER_NAMES
,
2920 MIPS_DSP_ACCUMULATOR_NAMES
,
2924 static const struct regname reg_names_o32
[] = {
2925 O32_SYMBOLIC_REGISTER_NAMES
,
2929 static const struct regname reg_names_n32n64
[] = {
2930 N32N64_SYMBOLIC_REGISTER_NAMES
,
2934 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2935 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2936 of these register symbols, return the associated vector register,
2937 otherwise return SYMVAL itself. */
2940 mips_prefer_vec_regno (unsigned int symval
)
2942 if ((symval
& -2) == (RTYPE_GP
| 2))
2943 return RTYPE_VEC
| (symval
& 1);
2947 /* Return true if string [S, E) is a valid register name, storing its
2948 symbol value in *SYMVAL_PTR if so. */
2951 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2956 /* Terminate name. */
2960 /* Look up the name. */
2961 symbol
= symbol_find (s
);
2964 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2967 *symval_ptr
= S_GET_VALUE (symbol
);
2971 /* Return true if the string at *SPTR is a valid register name. Allow it
2972 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2975 When returning true, move *SPTR past the register, store the
2976 register's symbol value in *SYMVAL_PTR and the channel mask in
2977 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2978 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2979 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2982 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2983 unsigned int *channels_ptr
)
2987 unsigned int channels
, symval
, bit
;
2989 /* Find end of name. */
2991 if (is_name_beginner (*e
))
2993 while (is_part_of_name (*e
))
2997 if (!mips_parse_register_1 (s
, e
, &symval
))
3002 /* Eat characters from the end of the string that are valid
3003 channel suffixes. The preceding register must be $ACC or
3004 end with a digit, so there is no ambiguity. */
3007 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3008 if (m
> s
&& m
[-1] == *q
)
3015 || !mips_parse_register_1 (s
, m
, &symval
)
3016 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3021 *symval_ptr
= symval
;
3023 *channels_ptr
= channels
;
3027 /* Check if SPTR points at a valid register specifier according to TYPES.
3028 If so, then return 1, advance S to consume the specifier and store
3029 the register's number in REGNOP, otherwise return 0. */
3032 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3036 if (mips_parse_register (s
, ®no
, NULL
))
3038 if (types
& RTYPE_VEC
)
3039 regno
= mips_prefer_vec_regno (regno
);
3048 as_warn (_("unrecognized register name `%s'"), *s
);
3053 return regno
<= RNUM_MASK
;
3056 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3057 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3060 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3065 for (i
= 0; i
< 4; i
++)
3066 if (*s
== "xyzw"[i
])
3068 *channels
|= 1 << (3 - i
);
3074 /* Token types for parsed operand lists. */
3075 enum mips_operand_token_type
{
3076 /* A plain register, e.g. $f2. */
3079 /* A 4-bit XYZW channel mask. */
3082 /* A constant vector index, e.g. [1]. */
3085 /* A register vector index, e.g. [$2]. */
3088 /* A continuous range of registers, e.g. $s0-$s4. */
3091 /* A (possibly relocated) expression. */
3094 /* A floating-point value. */
3097 /* A single character. This can be '(', ')' or ',', but '(' only appears
3101 /* A doubled character, either "--" or "++". */
3104 /* The end of the operand list. */
3108 /* A parsed operand token. */
3109 struct mips_operand_token
3111 /* The type of token. */
3112 enum mips_operand_token_type type
;
3115 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3118 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3119 unsigned int channels
;
3121 /* The integer value of an OT_INTEGER_INDEX. */
3124 /* The two register symbol values involved in an OT_REG_RANGE. */
3126 unsigned int regno1
;
3127 unsigned int regno2
;
3130 /* The value of an OT_INTEGER. The value is represented as an
3131 expression and the relocation operators that were applied to
3132 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3133 relocation operators were used. */
3136 bfd_reloc_code_real_type relocs
[3];
3139 /* The binary data for an OT_FLOAT constant, and the number of bytes
3142 unsigned char data
[8];
3146 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3151 /* An obstack used to construct lists of mips_operand_tokens. */
3152 static struct obstack mips_operand_tokens
;
3154 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3157 mips_add_token (struct mips_operand_token
*token
,
3158 enum mips_operand_token_type type
)
3161 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3164 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3165 and OT_REG tokens for them if so, and return a pointer to the first
3166 unconsumed character. Return null otherwise. */
3169 mips_parse_base_start (char *s
)
3171 struct mips_operand_token token
;
3172 unsigned int regno
, channels
;
3173 bfd_boolean decrement_p
;
3179 SKIP_SPACE_TABS (s
);
3181 /* Only match "--" as part of a base expression. In other contexts "--X"
3182 is a double negative. */
3183 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3187 SKIP_SPACE_TABS (s
);
3190 /* Allow a channel specifier because that leads to better error messages
3191 than treating something like "$vf0x++" as an expression. */
3192 if (!mips_parse_register (&s
, ®no
, &channels
))
3196 mips_add_token (&token
, OT_CHAR
);
3201 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3204 token
.u
.regno
= regno
;
3205 mips_add_token (&token
, OT_REG
);
3209 token
.u
.channels
= channels
;
3210 mips_add_token (&token
, OT_CHANNELS
);
3213 /* For consistency, only match "++" as part of base expressions too. */
3214 SKIP_SPACE_TABS (s
);
3215 if (s
[0] == '+' && s
[1] == '+')
3219 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3225 /* Parse one or more tokens from S. Return a pointer to the first
3226 unconsumed character on success. Return null if an error was found
3227 and store the error text in insn_error. FLOAT_FORMAT is as for
3228 mips_parse_arguments. */
3231 mips_parse_argument_token (char *s
, char float_format
)
3233 char *end
, *save_in
;
3235 unsigned int regno1
, regno2
, channels
;
3236 struct mips_operand_token token
;
3238 /* First look for "($reg", since we want to treat that as an
3239 OT_CHAR and OT_REG rather than an expression. */
3240 end
= mips_parse_base_start (s
);
3244 /* Handle other characters that end up as OT_CHARs. */
3245 if (*s
== ')' || *s
== ',')
3248 mips_add_token (&token
, OT_CHAR
);
3253 /* Handle tokens that start with a register. */
3254 if (mips_parse_register (&s
, ®no1
, &channels
))
3258 /* A register and a VU0 channel suffix. */
3259 token
.u
.regno
= regno1
;
3260 mips_add_token (&token
, OT_REG
);
3262 token
.u
.channels
= channels
;
3263 mips_add_token (&token
, OT_CHANNELS
);
3267 SKIP_SPACE_TABS (s
);
3270 /* A register range. */
3272 SKIP_SPACE_TABS (s
);
3273 if (!mips_parse_register (&s
, ®no2
, NULL
))
3275 set_insn_error (0, _("invalid register range"));
3279 token
.u
.reg_range
.regno1
= regno1
;
3280 token
.u
.reg_range
.regno2
= regno2
;
3281 mips_add_token (&token
, OT_REG_RANGE
);
3285 /* Add the register itself. */
3286 token
.u
.regno
= regno1
;
3287 mips_add_token (&token
, OT_REG
);
3289 /* Check for a vector index. */
3293 SKIP_SPACE_TABS (s
);
3294 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3295 mips_add_token (&token
, OT_REG_INDEX
);
3298 expressionS element
;
3300 my_getExpression (&element
, s
);
3301 if (element
.X_op
!= O_constant
)
3303 set_insn_error (0, _("vector element must be constant"));
3307 token
.u
.index
= element
.X_add_number
;
3308 mips_add_token (&token
, OT_INTEGER_INDEX
);
3310 SKIP_SPACE_TABS (s
);
3313 set_insn_error (0, _("missing `]'"));
3323 /* First try to treat expressions as floats. */
3324 save_in
= input_line_pointer
;
3325 input_line_pointer
= s
;
3326 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3327 &token
.u
.flt
.length
);
3328 end
= input_line_pointer
;
3329 input_line_pointer
= save_in
;
3332 set_insn_error (0, err
);
3337 mips_add_token (&token
, OT_FLOAT
);
3342 /* Treat everything else as an integer expression. */
3343 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3344 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3345 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3346 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3348 mips_add_token (&token
, OT_INTEGER
);
3352 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3353 if expressions should be treated as 32-bit floating-point constants,
3354 'd' if they should be treated as 64-bit floating-point constants,
3355 or 0 if they should be treated as integer expressions (the usual case).
3357 Return a list of tokens on success, otherwise return 0. The caller
3358 must obstack_free the list after use. */
3360 static struct mips_operand_token
*
3361 mips_parse_arguments (char *s
, char float_format
)
3363 struct mips_operand_token token
;
3365 SKIP_SPACE_TABS (s
);
3368 s
= mips_parse_argument_token (s
, float_format
);
3371 obstack_free (&mips_operand_tokens
,
3372 obstack_finish (&mips_operand_tokens
));
3375 SKIP_SPACE_TABS (s
);
3377 mips_add_token (&token
, OT_END
);
3378 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3381 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3382 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3385 is_opcode_valid (const struct mips_opcode
*mo
)
3387 int isa
= mips_opts
.isa
;
3388 int ase
= mips_opts
.ase
;
3392 if (ISA_HAS_64BIT_REGS (isa
))
3393 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3394 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3395 ase
|= mips_ases
[i
].flags64
;
3397 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3400 /* Check whether the instruction or macro requires single-precision or
3401 double-precision floating-point support. Note that this information is
3402 stored differently in the opcode table for insns and macros. */
3403 if (mo
->pinfo
== INSN_MACRO
)
3405 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3406 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3410 fp_s
= mo
->pinfo
& FP_S
;
3411 fp_d
= mo
->pinfo
& FP_D
;
3414 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3417 if (fp_s
&& mips_opts
.soft_float
)
3423 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3424 selected ISA and architecture. */
3427 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3429 int isa
= mips_opts
.isa
;
3430 int ase
= mips_opts
.ase
;
3433 if (ISA_HAS_64BIT_REGS (isa
))
3434 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3435 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3436 ase
|= mips_ases
[i
].flags64
;
3438 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3441 /* Return TRUE if the size of the microMIPS opcode MO matches one
3442 explicitly requested. Always TRUE in the standard MIPS mode.
3443 Use is_size_valid_16 for MIPS16 opcodes. */
3446 is_size_valid (const struct mips_opcode
*mo
)
3448 if (!mips_opts
.micromips
)
3451 if (mips_opts
.insn32
)
3453 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3455 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3458 if (!forced_insn_length
)
3460 if (mo
->pinfo
== INSN_MACRO
)
3462 return forced_insn_length
== micromips_insn_length (mo
);
3465 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3466 explicitly requested. */
3469 is_size_valid_16 (const struct mips_opcode
*mo
)
3471 if (!forced_insn_length
)
3473 if (mo
->pinfo
== INSN_MACRO
)
3475 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3477 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3482 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3483 of the preceding instruction. Always TRUE in the standard MIPS mode.
3485 We don't accept macros in 16-bit delay slots to avoid a case where
3486 a macro expansion fails because it relies on a preceding 32-bit real
3487 instruction to have matched and does not handle the operands correctly.
3488 The only macros that may expand to 16-bit instructions are JAL that
3489 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3490 and BGT (that likewise cannot be placed in a delay slot) that decay to
3491 a NOP. In all these cases the macros precede any corresponding real
3492 instruction definitions in the opcode table, so they will match in the
3493 second pass where the size of the delay slot is ignored and therefore
3494 produce correct code. */
3497 is_delay_slot_valid (const struct mips_opcode
*mo
)
3499 if (!mips_opts
.micromips
)
3502 if (mo
->pinfo
== INSN_MACRO
)
3503 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3504 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3505 && micromips_insn_length (mo
) != 4)
3507 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3508 && micromips_insn_length (mo
) != 2)
3514 /* For consistency checking, verify that all bits of OPCODE are specified
3515 either by the match/mask part of the instruction definition, or by the
3516 operand list. Also build up a list of operands in OPERANDS.
3518 INSN_BITS says which bits of the instruction are significant.
3519 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3520 provides the mips_operand description of each operand. DECODE_OPERAND
3521 is null for MIPS16 instructions. */
3524 validate_mips_insn (const struct mips_opcode
*opcode
,
3525 unsigned long insn_bits
,
3526 const struct mips_operand
*(*decode_operand
) (const char *),
3527 struct mips_operand_array
*operands
)
3530 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3531 const struct mips_operand
*operand
;
3533 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3534 if ((mask
& opcode
->match
) != opcode
->match
)
3536 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3537 opcode
->name
, opcode
->args
);
3542 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3543 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3544 for (s
= opcode
->args
; *s
; ++s
)
3557 if (!decode_operand
)
3558 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3560 operand
= decode_operand (s
);
3561 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3563 as_bad (_("internal: unknown operand type: %s %s"),
3564 opcode
->name
, opcode
->args
);
3567 gas_assert (opno
< MAX_OPERANDS
);
3568 operands
->operand
[opno
] = operand
;
3569 if (!decode_operand
&& operand
3570 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3571 && mips_opcode_32bit_p (opcode
))
3572 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3573 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3575 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3576 if (operand
->type
== OP_MDMX_IMM_REG
)
3577 /* Bit 5 is the format selector (OB vs QH). The opcode table
3578 has separate entries for each format. */
3579 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3580 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3581 used_bits
&= ~(mask
& 0x700);
3582 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3583 operand field that cannot be fully described with LSB/SIZE. */
3584 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3585 used_bits
&= ~0x6000;
3587 /* Skip prefix characters. */
3588 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3593 doubled
= used_bits
& mask
& insn_bits
;
3596 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3597 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3601 undefined
= ~used_bits
& insn_bits
;
3602 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3604 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3605 undefined
, opcode
->name
, opcode
->args
);
3608 used_bits
&= ~insn_bits
;
3611 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3612 used_bits
, opcode
->name
, opcode
->args
);
3618 /* The MIPS16 version of validate_mips_insn. */
3621 validate_mips16_insn (const struct mips_opcode
*opcode
,
3622 struct mips_operand_array
*operands
)
3624 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3626 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3629 /* The microMIPS version of validate_mips_insn. */
3632 validate_micromips_insn (const struct mips_opcode
*opc
,
3633 struct mips_operand_array
*operands
)
3635 unsigned long insn_bits
;
3636 unsigned long major
;
3637 unsigned int length
;
3639 if (opc
->pinfo
== INSN_MACRO
)
3640 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3643 length
= micromips_insn_length (opc
);
3644 if (length
!= 2 && length
!= 4)
3646 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3647 "%s %s"), length
, opc
->name
, opc
->args
);
3650 major
= opc
->match
>> (10 + 8 * (length
- 2));
3651 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3652 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3654 as_bad (_("internal error: bad microMIPS opcode "
3655 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3659 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3660 insn_bits
= 1 << 4 * length
;
3661 insn_bits
<<= 4 * length
;
3663 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3667 /* This function is called once, at assembler startup time. It should set up
3668 all the tables, etc. that the MD part of the assembler will need. */
3673 const char *retval
= NULL
;
3677 if (mips_pic
!= NO_PIC
)
3679 if (g_switch_seen
&& g_switch_value
!= 0)
3680 as_bad (_("-G may not be used in position-independent code"));
3683 else if (mips_abicalls
)
3685 if (g_switch_seen
&& g_switch_value
!= 0)
3686 as_bad (_("-G may not be used with abicalls"));
3690 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3691 as_warn (_("could not set architecture and machine"));
3693 op_hash
= hash_new ();
3695 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3696 for (i
= 0; i
< NUMOPCODES
;)
3698 const char *name
= mips_opcodes
[i
].name
;
3700 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3703 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3704 mips_opcodes
[i
].name
, retval
);
3705 /* Probably a memory allocation problem? Give up now. */
3706 as_fatal (_("broken assembler, no assembly attempted"));
3710 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3711 decode_mips_operand
, &mips_operands
[i
]))
3714 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3716 create_insn (&nop_insn
, mips_opcodes
+ i
);
3717 if (mips_fix_loongson2f_nop
)
3718 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3719 nop_insn
.fixed_p
= 1;
3722 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3723 create_insn (&sync_insn
, mips_opcodes
+ i
);
3727 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3730 mips16_op_hash
= hash_new ();
3731 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3732 bfd_mips16_num_opcodes
);
3735 while (i
< bfd_mips16_num_opcodes
)
3737 const char *name
= mips16_opcodes
[i
].name
;
3739 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3741 as_fatal (_("internal: can't hash `%s': %s"),
3742 mips16_opcodes
[i
].name
, retval
);
3745 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3747 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3749 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3750 mips16_nop_insn
.fixed_p
= 1;
3754 while (i
< bfd_mips16_num_opcodes
3755 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3758 micromips_op_hash
= hash_new ();
3759 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3760 bfd_micromips_num_opcodes
);
3763 while (i
< bfd_micromips_num_opcodes
)
3765 const char *name
= micromips_opcodes
[i
].name
;
3767 retval
= hash_insert (micromips_op_hash
, name
,
3768 (void *) µmips_opcodes
[i
]);
3770 as_fatal (_("internal: can't hash `%s': %s"),
3771 micromips_opcodes
[i
].name
, retval
);
3774 struct mips_cl_insn
*micromips_nop_insn
;
3776 if (!validate_micromips_insn (µmips_opcodes
[i
],
3777 µmips_operands
[i
]))
3780 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3782 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3783 micromips_nop_insn
= µmips_nop16_insn
;
3784 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3785 micromips_nop_insn
= µmips_nop32_insn
;
3789 if (micromips_nop_insn
->insn_mo
== NULL
3790 && strcmp (name
, "nop") == 0)
3792 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3793 micromips_nop_insn
->fixed_p
= 1;
3797 while (++i
< bfd_micromips_num_opcodes
3798 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3802 as_fatal (_("broken assembler, no assembly attempted"));
3804 /* We add all the general register names to the symbol table. This
3805 helps us detect invalid uses of them. */
3806 for (i
= 0; reg_names
[i
].name
; i
++)
3807 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3808 reg_names
[i
].num
, /* & RNUM_MASK, */
3809 &zero_address_frag
));
3811 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3812 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3813 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3814 &zero_address_frag
));
3816 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3817 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3818 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3819 &zero_address_frag
));
3821 for (i
= 0; i
< 32; i
++)
3825 /* R5900 VU0 floating-point register. */
3826 sprintf (regname
, "$vf%d", i
);
3827 symbol_table_insert (symbol_new (regname
, reg_section
,
3828 RTYPE_VF
| i
, &zero_address_frag
));
3830 /* R5900 VU0 integer register. */
3831 sprintf (regname
, "$vi%d", i
);
3832 symbol_table_insert (symbol_new (regname
, reg_section
,
3833 RTYPE_VI
| i
, &zero_address_frag
));
3836 sprintf (regname
, "$w%d", i
);
3837 symbol_table_insert (symbol_new (regname
, reg_section
,
3838 RTYPE_MSA
| i
, &zero_address_frag
));
3841 obstack_init (&mips_operand_tokens
);
3843 mips_no_prev_insn ();
3846 mips_cprmask
[0] = 0;
3847 mips_cprmask
[1] = 0;
3848 mips_cprmask
[2] = 0;
3849 mips_cprmask
[3] = 0;
3851 /* set the default alignment for the text section (2**2) */
3852 record_alignment (text_section
, 2);
3854 bfd_set_gp_size (stdoutput
, g_switch_value
);
3856 /* On a native system other than VxWorks, sections must be aligned
3857 to 16 byte boundaries. When configured for an embedded ELF
3858 target, we don't bother. */
3859 if (strncmp (TARGET_OS
, "elf", 3) != 0
3860 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3862 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3863 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3864 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3867 /* Create a .reginfo section for register masks and a .mdebug
3868 section for debugging information. */
3876 subseg
= now_subseg
;
3878 /* The ABI says this section should be loaded so that the
3879 running program can access it. However, we don't load it
3880 if we are configured for an embedded target. */
3881 flags
= SEC_READONLY
| SEC_DATA
;
3882 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3883 flags
|= SEC_ALLOC
| SEC_LOAD
;
3885 if (mips_abi
!= N64_ABI
)
3887 sec
= subseg_new (".reginfo", (subsegT
) 0);
3889 bfd_set_section_flags (stdoutput
, sec
, flags
);
3890 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3892 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3896 /* The 64-bit ABI uses a .MIPS.options section rather than
3897 .reginfo section. */
3898 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3899 bfd_set_section_flags (stdoutput
, sec
, flags
);
3900 bfd_set_section_alignment (stdoutput
, sec
, 3);
3902 /* Set up the option header. */
3904 Elf_Internal_Options opthdr
;
3907 opthdr
.kind
= ODK_REGINFO
;
3908 opthdr
.size
= (sizeof (Elf_External_Options
)
3909 + sizeof (Elf64_External_RegInfo
));
3912 f
= frag_more (sizeof (Elf_External_Options
));
3913 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3914 (Elf_External_Options
*) f
);
3916 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3920 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3921 bfd_set_section_flags (stdoutput
, sec
,
3922 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3923 bfd_set_section_alignment (stdoutput
, sec
, 3);
3924 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3926 if (ECOFF_DEBUGGING
)
3928 sec
= subseg_new (".mdebug", (subsegT
) 0);
3929 (void) bfd_set_section_flags (stdoutput
, sec
,
3930 SEC_HAS_CONTENTS
| SEC_READONLY
);
3931 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3933 else if (mips_flag_pdr
)
3935 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3936 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3937 SEC_READONLY
| SEC_RELOC
3939 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3942 subseg_set (seg
, subseg
);
3945 if (mips_fix_vr4120
)
3946 init_vr4120_conflicts ();
3950 fpabi_incompatible_with (int fpabi
, const char *what
)
3952 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3953 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3957 fpabi_requires (int fpabi
, const char *what
)
3959 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3960 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3963 /* Check -mabi and register sizes against the specified FP ABI. */
3965 check_fpabi (int fpabi
)
3969 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3970 if (file_mips_opts
.soft_float
)
3971 fpabi_incompatible_with (fpabi
, "softfloat");
3972 else if (file_mips_opts
.single_float
)
3973 fpabi_incompatible_with (fpabi
, "singlefloat");
3974 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3975 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3976 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3977 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3980 case Val_GNU_MIPS_ABI_FP_XX
:
3981 if (mips_abi
!= O32_ABI
)
3982 fpabi_requires (fpabi
, "-mabi=32");
3983 else if (file_mips_opts
.soft_float
)
3984 fpabi_incompatible_with (fpabi
, "softfloat");
3985 else if (file_mips_opts
.single_float
)
3986 fpabi_incompatible_with (fpabi
, "singlefloat");
3987 else if (file_mips_opts
.fp
!= 0)
3988 fpabi_requires (fpabi
, "fp=xx");
3991 case Val_GNU_MIPS_ABI_FP_64A
:
3992 case Val_GNU_MIPS_ABI_FP_64
:
3993 if (mips_abi
!= O32_ABI
)
3994 fpabi_requires (fpabi
, "-mabi=32");
3995 else if (file_mips_opts
.soft_float
)
3996 fpabi_incompatible_with (fpabi
, "softfloat");
3997 else if (file_mips_opts
.single_float
)
3998 fpabi_incompatible_with (fpabi
, "singlefloat");
3999 else if (file_mips_opts
.fp
!= 64)
4000 fpabi_requires (fpabi
, "fp=64");
4001 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
4002 fpabi_incompatible_with (fpabi
, "nooddspreg");
4003 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
4004 fpabi_requires (fpabi
, "nooddspreg");
4007 case Val_GNU_MIPS_ABI_FP_SINGLE
:
4008 if (file_mips_opts
.soft_float
)
4009 fpabi_incompatible_with (fpabi
, "softfloat");
4010 else if (!file_mips_opts
.single_float
)
4011 fpabi_requires (fpabi
, "singlefloat");
4014 case Val_GNU_MIPS_ABI_FP_SOFT
:
4015 if (!file_mips_opts
.soft_float
)
4016 fpabi_requires (fpabi
, "softfloat");
4019 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4020 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4021 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4024 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4025 /* Silently ignore compatibility value. */
4029 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4030 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4035 /* Perform consistency checks on the current options. */
4038 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4040 /* Check the size of integer registers agrees with the ABI and ISA. */
4041 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4042 as_bad (_("`gp=64' used with a 32-bit processor"));
4044 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4045 as_bad (_("`gp=32' used with a 64-bit ABI"));
4047 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4048 as_bad (_("`gp=64' used with a 32-bit ABI"));
4050 /* Check the size of the float registers agrees with the ABI and ISA. */
4054 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4055 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4056 else if (opts
->single_float
== 1)
4057 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4060 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4061 as_bad (_("`fp=64' used with a 32-bit fpu"));
4063 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4064 && !ISA_HAS_MXHC1 (opts
->isa
))
4065 as_warn (_("`fp=64' used with a 32-bit ABI"));
4069 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4070 as_warn (_("`fp=32' used with a 64-bit ABI"));
4071 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4072 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4075 as_bad (_("Unknown size of floating point registers"));
4079 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4080 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4082 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4083 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4084 else if (ISA_IS_R6 (opts
->isa
)
4085 && (opts
->micromips
== 1
4086 || opts
->mips16
== 1))
4087 as_fatal (_("`%s' cannot be used with `%s'"),
4088 opts
->micromips
? "micromips" : "mips16",
4089 mips_cpu_info_from_isa (opts
->isa
)->name
);
4091 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4092 as_fatal (_("branch relaxation is not supported in `%s'"),
4093 mips_cpu_info_from_isa (opts
->isa
)->name
);
4096 /* Perform consistency checks on the module level options exactly once.
4097 This is a deferred check that happens:
4098 at the first .set directive
4099 or, at the first pseudo op that generates code (inc .dc.a)
4100 or, at the first instruction
4104 file_mips_check_options (void)
4106 if (file_mips_opts_checked
)
4109 /* The following code determines the register size.
4110 Similar code was added to GCC 3.3 (see override_options() in
4111 config/mips/mips.c). The GAS and GCC code should be kept in sync
4112 as much as possible. */
4114 if (file_mips_opts
.gp
< 0)
4116 /* Infer the integer register size from the ABI and processor.
4117 Restrict ourselves to 32-bit registers if that's all the
4118 processor has, or if the ABI cannot handle 64-bit registers. */
4119 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4120 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4124 if (file_mips_opts
.fp
< 0)
4126 /* No user specified float register size.
4127 ??? GAS treats single-float processors as though they had 64-bit
4128 float registers (although it complains when double-precision
4129 instructions are used). As things stand, saying they have 32-bit
4130 registers would lead to spurious "register must be even" messages.
4131 So here we assume float registers are never smaller than the
4133 if (file_mips_opts
.gp
== 64)
4134 /* 64-bit integer registers implies 64-bit float registers. */
4135 file_mips_opts
.fp
= 64;
4136 else if ((file_mips_opts
.ase
& FP64_ASES
)
4137 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4138 /* Handle ASEs that require 64-bit float registers, if possible. */
4139 file_mips_opts
.fp
= 64;
4140 else if (ISA_IS_R6 (mips_opts
.isa
))
4141 /* R6 implies 64-bit float registers. */
4142 file_mips_opts
.fp
= 64;
4144 /* 32-bit float registers. */
4145 file_mips_opts
.fp
= 32;
4148 /* Disable operations on odd-numbered floating-point registers by default
4149 when using the FPXX ABI. */
4150 if (file_mips_opts
.oddspreg
< 0)
4152 if (file_mips_opts
.fp
== 0)
4153 file_mips_opts
.oddspreg
= 0;
4155 file_mips_opts
.oddspreg
= 1;
4158 /* End of GCC-shared inference code. */
4160 /* This flag is set when we have a 64-bit capable CPU but use only
4161 32-bit wide registers. Note that EABI does not use it. */
4162 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4163 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4164 || mips_abi
== O32_ABI
))
4167 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4168 as_bad (_("trap exception not supported at ISA 1"));
4170 /* If the selected architecture includes support for ASEs, enable
4171 generation of code for them. */
4172 if (file_mips_opts
.mips16
== -1)
4173 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4174 if (file_mips_opts
.micromips
== -1)
4175 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4178 if (mips_nan2008
== -1)
4179 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4180 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4181 as_fatal (_("`%s' does not support legacy NaN"),
4182 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4184 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4185 being selected implicitly. */
4186 if (file_mips_opts
.fp
!= 64)
4187 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4189 /* If the user didn't explicitly select or deselect a particular ASE,
4190 use the default setting for the CPU. */
4191 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4193 /* Set up the current options. These may change throughout assembly. */
4194 mips_opts
= file_mips_opts
;
4196 mips_check_isa_supports_ases ();
4197 mips_check_options (&file_mips_opts
, TRUE
);
4198 file_mips_opts_checked
= TRUE
;
4200 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4201 as_warn (_("could not set architecture and machine"));
4205 md_assemble (char *str
)
4207 struct mips_cl_insn insn
;
4208 bfd_reloc_code_real_type unused_reloc
[3]
4209 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4211 file_mips_check_options ();
4213 imm_expr
.X_op
= O_absent
;
4214 offset_expr
.X_op
= O_absent
;
4215 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4216 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4217 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4219 mips_mark_labels ();
4220 mips_assembling_insn
= TRUE
;
4221 clear_insn_error ();
4223 if (mips_opts
.mips16
)
4224 mips16_ip (str
, &insn
);
4227 mips_ip (str
, &insn
);
4228 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4229 str
, insn
.insn_opcode
));
4233 report_insn_error (str
);
4234 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4237 if (mips_opts
.mips16
)
4238 mips16_macro (&insn
);
4245 if (offset_expr
.X_op
!= O_absent
)
4246 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4248 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4251 mips_assembling_insn
= FALSE
;
4254 /* Convenience functions for abstracting away the differences between
4255 MIPS16 and non-MIPS16 relocations. */
4257 static inline bfd_boolean
4258 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4262 case BFD_RELOC_MIPS16_JMP
:
4263 case BFD_RELOC_MIPS16_GPREL
:
4264 case BFD_RELOC_MIPS16_GOT16
:
4265 case BFD_RELOC_MIPS16_CALL16
:
4266 case BFD_RELOC_MIPS16_HI16_S
:
4267 case BFD_RELOC_MIPS16_HI16
:
4268 case BFD_RELOC_MIPS16_LO16
:
4269 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4277 static inline bfd_boolean
4278 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4282 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4283 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4284 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4285 case BFD_RELOC_MICROMIPS_GPREL16
:
4286 case BFD_RELOC_MICROMIPS_JMP
:
4287 case BFD_RELOC_MICROMIPS_HI16
:
4288 case BFD_RELOC_MICROMIPS_HI16_S
:
4289 case BFD_RELOC_MICROMIPS_LO16
:
4290 case BFD_RELOC_MICROMIPS_LITERAL
:
4291 case BFD_RELOC_MICROMIPS_GOT16
:
4292 case BFD_RELOC_MICROMIPS_CALL16
:
4293 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4294 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4295 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4296 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4297 case BFD_RELOC_MICROMIPS_SUB
:
4298 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4299 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4300 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4301 case BFD_RELOC_MICROMIPS_HIGHEST
:
4302 case BFD_RELOC_MICROMIPS_HIGHER
:
4303 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4304 case BFD_RELOC_MICROMIPS_JALR
:
4312 static inline bfd_boolean
4313 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4315 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4318 static inline bfd_boolean
4319 b_reloc_p (bfd_reloc_code_real_type reloc
)
4321 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4322 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4323 || reloc
== BFD_RELOC_16_PCREL_S2
4324 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4325 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4326 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4327 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4330 static inline bfd_boolean
4331 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4333 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4334 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4337 static inline bfd_boolean
4338 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4340 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4341 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4344 static inline bfd_boolean
4345 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4347 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4348 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4351 static inline bfd_boolean
4352 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4354 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4357 static inline bfd_boolean
4358 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4360 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4361 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4364 /* Return true if RELOC is a PC-relative relocation that does not have
4365 full address range. */
4367 static inline bfd_boolean
4368 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4372 case BFD_RELOC_16_PCREL_S2
:
4373 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4374 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4375 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4376 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4377 case BFD_RELOC_MIPS_21_PCREL_S2
:
4378 case BFD_RELOC_MIPS_26_PCREL_S2
:
4379 case BFD_RELOC_MIPS_18_PCREL_S3
:
4380 case BFD_RELOC_MIPS_19_PCREL_S2
:
4383 case BFD_RELOC_32_PCREL
:
4384 case BFD_RELOC_HI16_S_PCREL
:
4385 case BFD_RELOC_LO16_PCREL
:
4386 return HAVE_64BIT_ADDRESSES
;
4393 /* Return true if the given relocation might need a matching %lo().
4394 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4395 need a matching %lo() when applied to local symbols. */
4397 static inline bfd_boolean
4398 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4400 return (HAVE_IN_PLACE_ADDENDS
4401 && (hi16_reloc_p (reloc
)
4402 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4403 all GOT16 relocations evaluate to "G". */
4404 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4407 /* Return the type of %lo() reloc needed by RELOC, given that
4408 reloc_needs_lo_p. */
4410 static inline bfd_reloc_code_real_type
4411 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4413 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4414 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4418 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4421 static inline bfd_boolean
4422 fixup_has_matching_lo_p (fixS
*fixp
)
4424 return (fixp
->fx_next
!= NULL
4425 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4426 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4427 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4430 /* Move all labels in LABELS to the current insertion point. TEXT_P
4431 says whether the labels refer to text or data. */
4434 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4436 struct insn_label_list
*l
;
4439 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4441 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4442 symbol_set_frag (l
->label
, frag_now
);
4443 val
= (valueT
) frag_now_fix ();
4444 /* MIPS16/microMIPS text labels are stored as odd.
4445 We just carry the ISA mode bit forward. */
4446 if (text_p
&& HAVE_CODE_COMPRESSION
)
4447 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4448 S_SET_VALUE (l
->label
, val
);
4452 /* Move all labels in insn_labels to the current insertion point
4453 and treat them as text labels. */
4456 mips_move_text_labels (void)
4458 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4461 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4464 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4466 bfd_boolean linkonce
= FALSE
;
4467 segT symseg
= S_GET_SEGMENT (sym
);
4469 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4471 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4473 /* The GNU toolchain uses an extension for ELF: a section
4474 beginning with the magic string .gnu.linkonce is a
4475 linkonce section. */
4476 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4477 sizeof ".gnu.linkonce" - 1) == 0)
4483 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4484 linker to handle them specially, such as generating jalx instructions
4485 when needed. We also make them odd for the duration of the assembly,
4486 in order to generate the right sort of code. We will make them even
4487 in the adjust_symtab routine, while leaving them marked. This is
4488 convenient for the debugger and the disassembler. The linker knows
4489 to make them odd again. */
4492 mips_compressed_mark_label (symbolS
*label
)
4494 gas_assert (HAVE_CODE_COMPRESSION
);
4496 if (mips_opts
.mips16
)
4497 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4499 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4500 if ((S_GET_VALUE (label
) & 1) == 0
4501 /* Don't adjust the address if the label is global or weak, or
4502 in a link-once section, since we'll be emitting symbol reloc
4503 references to it which will be patched up by the linker, and
4504 the final value of the symbol may or may not be MIPS16/microMIPS. */
4505 && !S_IS_WEAK (label
)
4506 && !S_IS_EXTERNAL (label
)
4507 && !s_is_linkonce (label
, now_seg
))
4508 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4511 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4514 mips_compressed_mark_labels (void)
4516 struct insn_label_list
*l
;
4518 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4519 mips_compressed_mark_label (l
->label
);
4522 /* End the current frag. Make it a variant frag and record the
4526 relax_close_frag (void)
4528 mips_macro_warning
.first_frag
= frag_now
;
4529 frag_var (rs_machine_dependent
, 0, 0,
4530 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4531 mips_pic
!= NO_PIC
),
4532 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4534 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4535 mips_relax
.first_fixup
= 0;
4538 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4539 See the comment above RELAX_ENCODE for more details. */
4542 relax_start (symbolS
*symbol
)
4544 gas_assert (mips_relax
.sequence
== 0);
4545 mips_relax
.sequence
= 1;
4546 mips_relax
.symbol
= symbol
;
4549 /* Start generating the second version of a relaxable sequence.
4550 See the comment above RELAX_ENCODE for more details. */
4555 gas_assert (mips_relax
.sequence
== 1);
4556 mips_relax
.sequence
= 2;
4559 /* End the current relaxable sequence. */
4564 gas_assert (mips_relax
.sequence
== 2);
4565 relax_close_frag ();
4566 mips_relax
.sequence
= 0;
4569 /* Return true if IP is a delayed branch or jump. */
4571 static inline bfd_boolean
4572 delayed_branch_p (const struct mips_cl_insn
*ip
)
4574 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4575 | INSN_COND_BRANCH_DELAY
4576 | INSN_COND_BRANCH_LIKELY
)) != 0;
4579 /* Return true if IP is a compact branch or jump. */
4581 static inline bfd_boolean
4582 compact_branch_p (const struct mips_cl_insn
*ip
)
4584 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4585 | INSN2_COND_BRANCH
)) != 0;
4588 /* Return true if IP is an unconditional branch or jump. */
4590 static inline bfd_boolean
4591 uncond_branch_p (const struct mips_cl_insn
*ip
)
4593 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4594 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4597 /* Return true if IP is a branch-likely instruction. */
4599 static inline bfd_boolean
4600 branch_likely_p (const struct mips_cl_insn
*ip
)
4602 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4605 /* Return the type of nop that should be used to fill the delay slot
4606 of delayed branch IP. */
4608 static struct mips_cl_insn
*
4609 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4611 if (mips_opts
.micromips
4612 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4613 return µmips_nop32_insn
;
4617 /* Return a mask that has bit N set if OPCODE reads the register(s)
4621 insn_read_mask (const struct mips_opcode
*opcode
)
4623 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4626 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4630 insn_write_mask (const struct mips_opcode
*opcode
)
4632 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4635 /* Return a mask of the registers specified by operand OPERAND of INSN.
4636 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4640 operand_reg_mask (const struct mips_cl_insn
*insn
,
4641 const struct mips_operand
*operand
,
4642 unsigned int type_mask
)
4644 unsigned int uval
, vsel
;
4646 switch (operand
->type
)
4653 case OP_ADDIUSP_INT
:
4654 case OP_ENTRY_EXIT_LIST
:
4655 case OP_REPEAT_DEST_REG
:
4656 case OP_REPEAT_PREV_REG
:
4659 case OP_VU0_MATCH_SUFFIX
:
4667 case OP_OPTIONAL_REG
:
4669 const struct mips_reg_operand
*reg_op
;
4671 reg_op
= (const struct mips_reg_operand
*) operand
;
4672 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4674 uval
= insn_extract_operand (insn
, operand
);
4675 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4680 const struct mips_reg_pair_operand
*pair_op
;
4682 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4683 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4685 uval
= insn_extract_operand (insn
, operand
);
4686 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4689 case OP_CLO_CLZ_DEST
:
4690 if (!(type_mask
& (1 << OP_REG_GP
)))
4692 uval
= insn_extract_operand (insn
, operand
);
4693 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4696 if (!(type_mask
& (1 << OP_REG_GP
)))
4698 uval
= insn_extract_operand (insn
, operand
);
4699 gas_assert ((uval
& 31) == (uval
>> 5));
4700 return 1 << (uval
& 31);
4703 case OP_NON_ZERO_REG
:
4704 if (!(type_mask
& (1 << OP_REG_GP
)))
4706 uval
= insn_extract_operand (insn
, operand
);
4707 return 1 << (uval
& 31);
4709 case OP_LWM_SWM_LIST
:
4712 case OP_SAVE_RESTORE_LIST
:
4715 case OP_MDMX_IMM_REG
:
4716 if (!(type_mask
& (1 << OP_REG_VEC
)))
4718 uval
= insn_extract_operand (insn
, operand
);
4720 if ((vsel
& 0x18) == 0x18)
4722 return 1 << (uval
& 31);
4725 if (!(type_mask
& (1 << OP_REG_GP
)))
4727 return 1 << insn_extract_operand (insn
, operand
);
4732 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4733 where bit N of OPNO_MASK is set if operand N should be included.
4734 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4738 insn_reg_mask (const struct mips_cl_insn
*insn
,
4739 unsigned int type_mask
, unsigned int opno_mask
)
4741 unsigned int opno
, reg_mask
;
4745 while (opno_mask
!= 0)
4748 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4755 /* Return the mask of core registers that IP reads. */
4758 gpr_read_mask (const struct mips_cl_insn
*ip
)
4760 unsigned long pinfo
, pinfo2
;
4763 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4764 pinfo
= ip
->insn_mo
->pinfo
;
4765 pinfo2
= ip
->insn_mo
->pinfo2
;
4766 if (pinfo
& INSN_UDI
)
4768 /* UDI instructions have traditionally been assumed to read RS
4770 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4771 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4773 if (pinfo
& INSN_READ_GPR_24
)
4775 if (pinfo2
& INSN2_READ_GPR_16
)
4777 if (pinfo2
& INSN2_READ_SP
)
4779 if (pinfo2
& INSN2_READ_GPR_31
)
4781 /* Don't include register 0. */
4785 /* Return the mask of core registers that IP writes. */
4788 gpr_write_mask (const struct mips_cl_insn
*ip
)
4790 unsigned long pinfo
, pinfo2
;
4793 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4794 pinfo
= ip
->insn_mo
->pinfo
;
4795 pinfo2
= ip
->insn_mo
->pinfo2
;
4796 if (pinfo
& INSN_WRITE_GPR_24
)
4798 if (pinfo
& INSN_WRITE_GPR_31
)
4800 if (pinfo
& INSN_UDI
)
4801 /* UDI instructions have traditionally been assumed to write to RD. */
4802 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4803 if (pinfo2
& INSN2_WRITE_SP
)
4805 /* Don't include register 0. */
4809 /* Return the mask of floating-point registers that IP reads. */
4812 fpr_read_mask (const struct mips_cl_insn
*ip
)
4814 unsigned long pinfo
;
4817 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4818 | (1 << OP_REG_MSA
)),
4819 insn_read_mask (ip
->insn_mo
));
4820 pinfo
= ip
->insn_mo
->pinfo
;
4821 /* Conservatively treat all operands to an FP_D instruction are doubles.
4822 (This is overly pessimistic for things like cvt.d.s.) */
4823 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4828 /* Return the mask of floating-point registers that IP writes. */
4831 fpr_write_mask (const struct mips_cl_insn
*ip
)
4833 unsigned long pinfo
;
4836 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4837 | (1 << OP_REG_MSA
)),
4838 insn_write_mask (ip
->insn_mo
));
4839 pinfo
= ip
->insn_mo
->pinfo
;
4840 /* Conservatively treat all operands to an FP_D instruction are doubles.
4841 (This is overly pessimistic for things like cvt.s.d.) */
4842 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4847 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4848 Check whether that is allowed. */
4851 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4853 const char *s
= insn
->name
;
4854 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4856 && mips_opts
.oddspreg
;
4858 if (insn
->pinfo
== INSN_MACRO
)
4859 /* Let a macro pass, we'll catch it later when it is expanded. */
4862 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4863 otherwise it depends on oddspreg. */
4864 if ((insn
->pinfo
& FP_S
)
4865 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4866 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4867 return FPR_SIZE
== 32 || oddspreg
;
4869 /* Allow odd registers for single-precision ops and double-precision if the
4870 floating-point registers are 64-bit wide. */
4871 switch (insn
->pinfo
& (FP_S
| FP_D
))
4877 return FPR_SIZE
== 64;
4882 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4883 s
= strchr (insn
->name
, '.');
4884 if (s
!= NULL
&& opnum
== 2)
4885 s
= strchr (s
+ 1, '.');
4886 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4889 return FPR_SIZE
== 64;
4892 /* Information about an instruction argument that we're trying to match. */
4893 struct mips_arg_info
4895 /* The instruction so far. */
4896 struct mips_cl_insn
*insn
;
4898 /* The first unconsumed operand token. */
4899 struct mips_operand_token
*token
;
4901 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4904 /* The 1-based argument number, for error reporting. This does not
4905 count elided optional registers, etc.. */
4908 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4909 unsigned int last_regno
;
4911 /* If the first operand was an OP_REG, this is the register that it
4912 specified, otherwise it is ILLEGAL_REG. */
4913 unsigned int dest_regno
;
4915 /* The value of the last OP_INT operand. Only used for OP_MSB,
4916 where it gives the lsb position. */
4917 unsigned int last_op_int
;
4919 /* If true, match routines should assume that no later instruction
4920 alternative matches and should therefore be as accommodating as
4921 possible. Match routines should not report errors if something
4922 is only invalid for !LAX_MATCH. */
4923 bfd_boolean lax_match
;
4925 /* True if a reference to the current AT register was seen. */
4926 bfd_boolean seen_at
;
4929 /* Record that the argument is out of range. */
4932 match_out_of_range (struct mips_arg_info
*arg
)
4934 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4937 /* Record that the argument isn't constant but needs to be. */
4940 match_not_constant (struct mips_arg_info
*arg
)
4942 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4946 /* Try to match an OT_CHAR token for character CH. Consume the token
4947 and return true on success, otherwise return false. */
4950 match_char (struct mips_arg_info
*arg
, char ch
)
4952 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4962 /* Try to get an expression from the next tokens in ARG. Consume the
4963 tokens and return true on success, storing the expression value in
4964 VALUE and relocation types in R. */
4967 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4968 bfd_reloc_code_real_type
*r
)
4970 /* If the next token is a '(' that was parsed as being part of a base
4971 expression, assume we have an elided offset. The later match will fail
4972 if this turns out to be wrong. */
4973 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4975 value
->X_op
= O_constant
;
4976 value
->X_add_number
= 0;
4977 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4981 /* Reject register-based expressions such as "0+$2" and "(($2))".
4982 For plain registers the default error seems more appropriate. */
4983 if (arg
->token
->type
== OT_INTEGER
4984 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4986 set_insn_error (arg
->argnum
, _("register value used as expression"));
4990 if (arg
->token
->type
== OT_INTEGER
)
4992 *value
= arg
->token
->u
.integer
.value
;
4993 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4999 (arg
->argnum
, _("operand %d must be an immediate expression"),
5004 /* Try to get a constant expression from the next tokens in ARG. Consume
5005 the tokens and return true on success, storing the constant value
5009 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
5012 bfd_reloc_code_real_type r
[3];
5014 if (!match_expression (arg
, &ex
, r
))
5017 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5018 *value
= ex
.X_add_number
;
5021 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5022 match_out_of_range (arg
);
5024 match_not_constant (arg
);
5030 /* Return the RTYPE_* flags for a register operand of type TYPE that
5031 appears in instruction OPCODE. */
5034 convert_reg_type (const struct mips_opcode
*opcode
,
5035 enum mips_reg_operand_type type
)
5040 return RTYPE_NUM
| RTYPE_GP
;
5043 /* Allow vector register names for MDMX if the instruction is a 64-bit
5044 FPR load, store or move (including moves to and from GPRs). */
5045 if ((mips_opts
.ase
& ASE_MDMX
)
5046 && (opcode
->pinfo
& FP_D
)
5047 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5048 | INSN_COPROC_MEMORY_DELAY
5051 | INSN_STORE_MEMORY
)))
5052 return RTYPE_FPU
| RTYPE_VEC
;
5056 if (opcode
->pinfo
& (FP_D
| FP_S
))
5057 return RTYPE_CCC
| RTYPE_FCC
;
5061 if (opcode
->membership
& INSN_5400
)
5063 return RTYPE_FPU
| RTYPE_VEC
;
5069 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5070 return RTYPE_NUM
| RTYPE_CP0
;
5077 return RTYPE_NUM
| RTYPE_VI
;
5080 return RTYPE_NUM
| RTYPE_VF
;
5082 case OP_REG_R5900_I
:
5083 return RTYPE_R5900_I
;
5085 case OP_REG_R5900_Q
:
5086 return RTYPE_R5900_Q
;
5088 case OP_REG_R5900_R
:
5089 return RTYPE_R5900_R
;
5091 case OP_REG_R5900_ACC
:
5092 return RTYPE_R5900_ACC
;
5097 case OP_REG_MSA_CTRL
:
5103 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5106 check_regno (struct mips_arg_info
*arg
,
5107 enum mips_reg_operand_type type
, unsigned int regno
)
5109 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5110 arg
->seen_at
= TRUE
;
5112 if (type
== OP_REG_FP
5114 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5116 /* This was a warning prior to introducing O32 FPXX and FP64 support
5117 so maintain a warning for FP32 but raise an error for the new
5120 as_warn (_("float register should be even, was %d"), regno
);
5122 as_bad (_("float register should be even, was %d"), regno
);
5125 if (type
== OP_REG_CCC
)
5130 name
= arg
->insn
->insn_mo
->name
;
5131 length
= strlen (name
);
5132 if ((regno
& 1) != 0
5133 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5134 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5135 as_warn (_("condition code register should be even for %s, was %d"),
5138 if ((regno
& 3) != 0
5139 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5140 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5145 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5146 a register of type TYPE. Return true on success, storing the register
5147 number in *REGNO and warning about any dubious uses. */
5150 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5151 unsigned int symval
, unsigned int *regno
)
5153 if (type
== OP_REG_VEC
)
5154 symval
= mips_prefer_vec_regno (symval
);
5155 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5158 *regno
= symval
& RNUM_MASK
;
5159 check_regno (arg
, type
, *regno
);
5163 /* Try to interpret the next token in ARG as a register of type TYPE.
5164 Consume the token and return true on success, storing the register
5165 number in *REGNO. Return false on failure. */
5168 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5169 unsigned int *regno
)
5171 if (arg
->token
->type
== OT_REG
5172 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5180 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5181 Consume the token and return true on success, storing the register numbers
5182 in *REGNO1 and *REGNO2. Return false on failure. */
5185 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5186 unsigned int *regno1
, unsigned int *regno2
)
5188 if (match_reg (arg
, type
, regno1
))
5193 if (arg
->token
->type
== OT_REG_RANGE
5194 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5195 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5196 && *regno1
<= *regno2
)
5204 /* OP_INT matcher. */
5207 match_int_operand (struct mips_arg_info
*arg
,
5208 const struct mips_operand
*operand_base
)
5210 const struct mips_int_operand
*operand
;
5212 int min_val
, max_val
, factor
;
5215 operand
= (const struct mips_int_operand
*) operand_base
;
5216 factor
= 1 << operand
->shift
;
5217 min_val
= mips_int_operand_min (operand
);
5218 max_val
= mips_int_operand_max (operand
);
5220 if (operand_base
->lsb
== 0
5221 && operand_base
->size
== 16
5222 && operand
->shift
== 0
5223 && operand
->bias
== 0
5224 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5226 /* The operand can be relocated. */
5227 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5230 if (offset_expr
.X_op
== O_big
)
5232 match_out_of_range (arg
);
5236 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5237 /* Relocation operators were used. Accept the argument and
5238 leave the relocation value in offset_expr and offset_relocs
5239 for the caller to process. */
5242 if (offset_expr
.X_op
!= O_constant
)
5244 /* Accept non-constant operands if no later alternative matches,
5245 leaving it for the caller to process. */
5246 if (!arg
->lax_match
)
5248 match_not_constant (arg
);
5251 offset_reloc
[0] = BFD_RELOC_LO16
;
5255 /* Clear the global state; we're going to install the operand
5257 sval
= offset_expr
.X_add_number
;
5258 offset_expr
.X_op
= O_absent
;
5260 /* For compatibility with older assemblers, we accept
5261 0x8000-0xffff as signed 16-bit numbers when only
5262 signed numbers are allowed. */
5265 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5266 if (!arg
->lax_match
&& sval
<= max_val
)
5268 match_out_of_range (arg
);
5275 if (!match_const_int (arg
, &sval
))
5279 arg
->last_op_int
= sval
;
5281 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5283 match_out_of_range (arg
);
5287 uval
= (unsigned int) sval
>> operand
->shift
;
5288 uval
-= operand
->bias
;
5290 /* Handle -mfix-cn63xxp1. */
5292 && mips_fix_cn63xxp1
5293 && !mips_opts
.micromips
5294 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5309 /* The rest must be changed to 28. */
5314 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5318 /* OP_MAPPED_INT matcher. */
5321 match_mapped_int_operand (struct mips_arg_info
*arg
,
5322 const struct mips_operand
*operand_base
)
5324 const struct mips_mapped_int_operand
*operand
;
5325 unsigned int uval
, num_vals
;
5328 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5329 if (!match_const_int (arg
, &sval
))
5332 num_vals
= 1 << operand_base
->size
;
5333 for (uval
= 0; uval
< num_vals
; uval
++)
5334 if (operand
->int_map
[uval
] == sval
)
5336 if (uval
== num_vals
)
5338 match_out_of_range (arg
);
5342 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5346 /* OP_MSB matcher. */
5349 match_msb_operand (struct mips_arg_info
*arg
,
5350 const struct mips_operand
*operand_base
)
5352 const struct mips_msb_operand
*operand
;
5353 int min_val
, max_val
, max_high
;
5354 offsetT size
, sval
, high
;
5356 operand
= (const struct mips_msb_operand
*) operand_base
;
5357 min_val
= operand
->bias
;
5358 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5359 max_high
= operand
->opsize
;
5361 if (!match_const_int (arg
, &size
))
5364 high
= size
+ arg
->last_op_int
;
5365 sval
= operand
->add_lsb
? high
: size
;
5367 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5369 match_out_of_range (arg
);
5372 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5376 /* OP_REG matcher. */
5379 match_reg_operand (struct mips_arg_info
*arg
,
5380 const struct mips_operand
*operand_base
)
5382 const struct mips_reg_operand
*operand
;
5383 unsigned int regno
, uval
, num_vals
;
5385 operand
= (const struct mips_reg_operand
*) operand_base
;
5386 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5389 if (operand
->reg_map
)
5391 num_vals
= 1 << operand
->root
.size
;
5392 for (uval
= 0; uval
< num_vals
; uval
++)
5393 if (operand
->reg_map
[uval
] == regno
)
5395 if (num_vals
== uval
)
5401 arg
->last_regno
= regno
;
5402 if (arg
->opnum
== 1)
5403 arg
->dest_regno
= regno
;
5404 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5408 /* OP_REG_PAIR matcher. */
5411 match_reg_pair_operand (struct mips_arg_info
*arg
,
5412 const struct mips_operand
*operand_base
)
5414 const struct mips_reg_pair_operand
*operand
;
5415 unsigned int regno1
, regno2
, uval
, num_vals
;
5417 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5418 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5419 || !match_char (arg
, ',')
5420 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5423 num_vals
= 1 << operand_base
->size
;
5424 for (uval
= 0; uval
< num_vals
; uval
++)
5425 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5427 if (uval
== num_vals
)
5430 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5434 /* OP_PCREL matcher. The caller chooses the relocation type. */
5437 match_pcrel_operand (struct mips_arg_info
*arg
)
5439 bfd_reloc_code_real_type r
[3];
5441 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5444 /* OP_PERF_REG matcher. */
5447 match_perf_reg_operand (struct mips_arg_info
*arg
,
5448 const struct mips_operand
*operand
)
5452 if (!match_const_int (arg
, &sval
))
5457 || (mips_opts
.arch
== CPU_R5900
5458 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5459 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5461 set_insn_error (arg
->argnum
, _("invalid performance register"));
5465 insn_insert_operand (arg
->insn
, operand
, sval
);
5469 /* OP_ADDIUSP matcher. */
5472 match_addiusp_operand (struct mips_arg_info
*arg
,
5473 const struct mips_operand
*operand
)
5478 if (!match_const_int (arg
, &sval
))
5483 match_out_of_range (arg
);
5488 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5490 match_out_of_range (arg
);
5494 uval
= (unsigned int) sval
;
5495 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5496 insn_insert_operand (arg
->insn
, operand
, uval
);
5500 /* OP_CLO_CLZ_DEST matcher. */
5503 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5504 const struct mips_operand
*operand
)
5508 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5511 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5515 /* OP_CHECK_PREV matcher. */
5518 match_check_prev_operand (struct mips_arg_info
*arg
,
5519 const struct mips_operand
*operand_base
)
5521 const struct mips_check_prev_operand
*operand
;
5524 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5526 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5529 if (!operand
->zero_ok
&& regno
== 0)
5532 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5533 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5534 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5536 arg
->last_regno
= regno
;
5537 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5544 /* OP_SAME_RS_RT matcher. */
5547 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5548 const struct mips_operand
*operand
)
5552 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5557 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5561 arg
->last_regno
= regno
;
5563 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5567 /* OP_LWM_SWM_LIST matcher. */
5570 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5571 const struct mips_operand
*operand
)
5573 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5574 struct mips_arg_info reset
;
5577 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5581 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5586 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5589 while (match_char (arg
, ',')
5590 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5593 if (operand
->size
== 2)
5595 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5601 and any permutations of these. */
5602 if ((reglist
& 0xfff1ffff) != 0x80010000)
5605 sregs
= (reglist
>> 17) & 7;
5610 /* The list must include at least one of ra and s0-sN,
5611 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5612 which are $23 and $30 respectively.) E.g.:
5620 and any permutations of these. */
5621 if ((reglist
& 0x3f00ffff) != 0)
5624 ra
= (reglist
>> 27) & 0x10;
5625 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5628 if ((sregs
& -sregs
) != sregs
)
5631 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5635 /* OP_ENTRY_EXIT_LIST matcher. */
5638 match_entry_exit_operand (struct mips_arg_info
*arg
,
5639 const struct mips_operand
*operand
)
5642 bfd_boolean is_exit
;
5644 /* The format is the same for both ENTRY and EXIT, but the constraints
5646 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5647 mask
= (is_exit
? 7 << 3 : 0);
5650 unsigned int regno1
, regno2
;
5651 bfd_boolean is_freg
;
5653 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5655 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5660 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5663 mask
|= (5 + regno2
) << 3;
5665 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5666 mask
|= (regno2
- 3) << 3;
5667 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5668 mask
|= (regno2
- 15) << 1;
5669 else if (regno1
== RA
&& regno2
== RA
)
5674 while (match_char (arg
, ','));
5676 insn_insert_operand (arg
->insn
, operand
, mask
);
5680 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5681 the argument register mask AMASK, the number of static registers
5682 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5683 respectively, and the frame size FRAME_SIZE. */
5686 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5687 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5688 unsigned int frame_size
)
5690 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5691 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5694 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5695 argument register mask AMASK, the number of static registers saved
5696 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5697 respectively, and the frame size FRAME_SIZE. */
5700 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5701 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5702 unsigned int frame_size
)
5706 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5707 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5708 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5709 | ((frame_size
& 0xf0) << 16));
5713 /* OP_SAVE_RESTORE_LIST matcher. */
5716 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5718 unsigned int opcode
, args
, statics
, sregs
;
5719 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5720 unsigned int arg_mask
, ra
, s0
, s1
;
5723 opcode
= arg
->insn
->insn_opcode
;
5725 num_frame_sizes
= 0;
5734 unsigned int regno1
, regno2
;
5736 if (arg
->token
->type
== OT_INTEGER
)
5738 /* Handle the frame size. */
5739 if (!match_const_int (arg
, &frame_size
))
5741 num_frame_sizes
+= 1;
5745 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5748 while (regno1
<= regno2
)
5750 if (regno1
>= 4 && regno1
<= 7)
5752 if (num_frame_sizes
== 0)
5754 args
|= 1 << (regno1
- 4);
5756 /* statics $a0-$a3 */
5757 statics
|= 1 << (regno1
- 4);
5759 else if (regno1
>= 16 && regno1
<= 23)
5761 sregs
|= 1 << (regno1
- 16);
5762 else if (regno1
== 30)
5765 else if (regno1
== 31)
5766 /* Add $ra to insn. */
5776 while (match_char (arg
, ','));
5778 /* Encode args/statics combination. */
5781 else if (args
== 0xf)
5782 /* All $a0-$a3 are args. */
5783 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5784 else if (statics
== 0xf)
5785 /* All $a0-$a3 are statics. */
5786 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5789 /* Count arg registers. */
5799 /* Count static registers. */
5801 while (statics
& 0x8)
5803 statics
= (statics
<< 1) & 0xf;
5809 /* Encode args/statics. */
5810 arg_mask
= (num_args
<< 2) | num_statics
;
5813 /* Encode $s0/$s1. */
5814 if (sregs
& (1 << 0)) /* $s0 */
5816 if (sregs
& (1 << 1)) /* $s1 */
5820 /* Encode $s2-$s8. */
5830 /* Encode frame size. */
5831 if (num_frame_sizes
== 0)
5833 set_insn_error (arg
->argnum
, _("missing frame size"));
5836 if (num_frame_sizes
> 1)
5838 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5841 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5843 set_insn_error (arg
->argnum
, _("invalid frame size"));
5848 /* Finally build the instruction. */
5849 if (mips_opts
.mips16
)
5850 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5852 else if (!mips_opts
.micromips
)
5853 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5858 arg
->insn
->insn_opcode
= opcode
;
5862 /* OP_MDMX_IMM_REG matcher. */
5865 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5866 const struct mips_operand
*operand
)
5868 unsigned int regno
, uval
;
5870 const struct mips_opcode
*opcode
;
5872 /* The mips_opcode records whether this is an octobyte or quadhalf
5873 instruction. Start out with that bit in place. */
5874 opcode
= arg
->insn
->insn_mo
;
5875 uval
= mips_extract_operand (operand
, opcode
->match
);
5876 is_qh
= (uval
!= 0);
5878 if (arg
->token
->type
== OT_REG
)
5880 if ((opcode
->membership
& INSN_5400
)
5881 && strcmp (opcode
->name
, "rzu.ob") == 0)
5883 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5888 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5892 /* Check whether this is a vector register or a broadcast of
5893 a single element. */
5894 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5896 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5898 set_insn_error (arg
->argnum
, _("invalid element selector"));
5901 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5906 /* A full vector. */
5907 if ((opcode
->membership
& INSN_5400
)
5908 && (strcmp (opcode
->name
, "sll.ob") == 0
5909 || strcmp (opcode
->name
, "srl.ob") == 0))
5911 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5917 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5919 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5927 if (!match_const_int (arg
, &sval
))
5929 if (sval
< 0 || sval
> 31)
5931 match_out_of_range (arg
);
5934 uval
|= (sval
& 31);
5936 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5938 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5940 insn_insert_operand (arg
->insn
, operand
, uval
);
5944 /* OP_IMM_INDEX matcher. */
5947 match_imm_index_operand (struct mips_arg_info
*arg
,
5948 const struct mips_operand
*operand
)
5950 unsigned int max_val
;
5952 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5955 max_val
= (1 << operand
->size
) - 1;
5956 if (arg
->token
->u
.index
> max_val
)
5958 match_out_of_range (arg
);
5961 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5966 /* OP_REG_INDEX matcher. */
5969 match_reg_index_operand (struct mips_arg_info
*arg
,
5970 const struct mips_operand
*operand
)
5974 if (arg
->token
->type
!= OT_REG_INDEX
)
5977 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5980 insn_insert_operand (arg
->insn
, operand
, regno
);
5985 /* OP_PC matcher. */
5988 match_pc_operand (struct mips_arg_info
*arg
)
5990 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5998 /* OP_REG28 matcher. */
6001 match_reg28_operand (struct mips_arg_info
*arg
)
6005 if (arg
->token
->type
== OT_REG
6006 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6015 /* OP_NON_ZERO_REG matcher. */
6018 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6019 const struct mips_operand
*operand
)
6023 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6028 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6032 arg
->last_regno
= regno
;
6033 insn_insert_operand (arg
->insn
, operand
, regno
);
6037 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6038 register that we need to match. */
6041 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6045 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6048 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6049 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6050 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6052 Return the constant in IMM and OFFSET as follows:
6054 - If the constant should be loaded via memory, set IMM to O_absent and
6055 OFFSET to the memory address.
6057 - Otherwise, if the constant should be loaded into two 32-bit registers,
6058 set IMM to the O_constant to load into the high register and OFFSET
6059 to the corresponding value for the low register.
6061 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6063 These constants only appear as the last operand in an instruction,
6064 and every instruction that accepts them in any variant accepts them
6065 in all variants. This means we don't have to worry about backing out
6066 any changes if the instruction does not match. We just match
6067 unconditionally and report an error if the constant is invalid. */
6070 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6071 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6076 const char *newname
;
6077 unsigned char *data
;
6079 /* Where the constant is placed is based on how the MIPS assembler
6082 length == 4 && using_gprs -- immediate value only
6083 length == 8 && using_gprs -- .rdata or immediate value
6084 length == 4 && !using_gprs -- .lit4 or immediate value
6085 length == 8 && !using_gprs -- .lit8 or immediate value
6087 The .lit4 and .lit8 sections are only used if permitted by the
6089 if (arg
->token
->type
!= OT_FLOAT
)
6091 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6095 gas_assert (arg
->token
->u
.flt
.length
== length
);
6096 data
= arg
->token
->u
.flt
.data
;
6099 /* Handle 32-bit constants for which an immediate value is best. */
6102 || g_switch_value
< 4
6103 || (data
[0] == 0 && data
[1] == 0)
6104 || (data
[2] == 0 && data
[3] == 0)))
6106 imm
->X_op
= O_constant
;
6107 if (!target_big_endian
)
6108 imm
->X_add_number
= bfd_getl32 (data
);
6110 imm
->X_add_number
= bfd_getb32 (data
);
6111 offset
->X_op
= O_absent
;
6115 /* Handle 64-bit constants for which an immediate value is best. */
6117 && !mips_disable_float_construction
6118 /* Constants can only be constructed in GPRs and copied to FPRs if the
6119 GPRs are at least as wide as the FPRs or MTHC1 is available.
6120 Unlike most tests for 32-bit floating-point registers this check
6121 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6122 permit 64-bit moves without MXHC1.
6123 Force the constant into memory otherwise. */
6126 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6128 && ((data
[0] == 0 && data
[1] == 0)
6129 || (data
[2] == 0 && data
[3] == 0))
6130 && ((data
[4] == 0 && data
[5] == 0)
6131 || (data
[6] == 0 && data
[7] == 0)))
6133 /* The value is simple enough to load with a couple of instructions.
6134 If using 32-bit registers, set IMM to the high order 32 bits and
6135 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6137 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6139 imm
->X_op
= O_constant
;
6140 offset
->X_op
= O_constant
;
6141 if (!target_big_endian
)
6143 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6144 offset
->X_add_number
= bfd_getl32 (data
);
6148 imm
->X_add_number
= bfd_getb32 (data
);
6149 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6151 if (offset
->X_add_number
== 0)
6152 offset
->X_op
= O_absent
;
6156 imm
->X_op
= O_constant
;
6157 if (!target_big_endian
)
6158 imm
->X_add_number
= bfd_getl64 (data
);
6160 imm
->X_add_number
= bfd_getb64 (data
);
6161 offset
->X_op
= O_absent
;
6166 /* Switch to the right section. */
6168 subseg
= now_subseg
;
6171 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6176 if (using_gprs
|| g_switch_value
< 8)
6177 newname
= RDATA_SECTION_NAME
;
6182 new_seg
= subseg_new (newname
, (subsegT
) 0);
6183 bfd_set_section_flags (stdoutput
, new_seg
,
6184 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6185 frag_align (length
== 4 ? 2 : 3, 0, 0);
6186 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6187 record_alignment (new_seg
, 4);
6189 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6191 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6193 /* Set the argument to the current address in the section. */
6194 imm
->X_op
= O_absent
;
6195 offset
->X_op
= O_symbol
;
6196 offset
->X_add_symbol
= symbol_temp_new_now ();
6197 offset
->X_add_number
= 0;
6199 /* Put the floating point number into the section. */
6200 p
= frag_more (length
);
6201 memcpy (p
, data
, length
);
6203 /* Switch back to the original section. */
6204 subseg_set (seg
, subseg
);
6208 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6212 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6213 const struct mips_operand
*operand
,
6214 bfd_boolean match_p
)
6218 /* The operand can be an XYZW mask or a single 2-bit channel index
6219 (with X being 0). */
6220 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6222 /* The suffix can be omitted when it is already part of the opcode. */
6223 if (arg
->token
->type
!= OT_CHANNELS
)
6226 uval
= arg
->token
->u
.channels
;
6227 if (operand
->size
== 2)
6229 /* Check that a single bit is set and convert it into a 2-bit index. */
6230 if ((uval
& -uval
) != uval
)
6232 uval
= 4 - ffs (uval
);
6235 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6240 insn_insert_operand (arg
->insn
, operand
, uval
);
6244 /* Try to match a token from ARG against OPERAND. Consume the token
6245 and return true on success, otherwise return false. */
6248 match_operand (struct mips_arg_info
*arg
,
6249 const struct mips_operand
*operand
)
6251 switch (operand
->type
)
6254 return match_int_operand (arg
, operand
);
6257 return match_mapped_int_operand (arg
, operand
);
6260 return match_msb_operand (arg
, operand
);
6263 case OP_OPTIONAL_REG
:
6264 return match_reg_operand (arg
, operand
);
6267 return match_reg_pair_operand (arg
, operand
);
6270 return match_pcrel_operand (arg
);
6273 return match_perf_reg_operand (arg
, operand
);
6275 case OP_ADDIUSP_INT
:
6276 return match_addiusp_operand (arg
, operand
);
6278 case OP_CLO_CLZ_DEST
:
6279 return match_clo_clz_dest_operand (arg
, operand
);
6281 case OP_LWM_SWM_LIST
:
6282 return match_lwm_swm_list_operand (arg
, operand
);
6284 case OP_ENTRY_EXIT_LIST
:
6285 return match_entry_exit_operand (arg
, operand
);
6287 case OP_SAVE_RESTORE_LIST
:
6288 return match_save_restore_list_operand (arg
);
6290 case OP_MDMX_IMM_REG
:
6291 return match_mdmx_imm_reg_operand (arg
, operand
);
6293 case OP_REPEAT_DEST_REG
:
6294 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6296 case OP_REPEAT_PREV_REG
:
6297 return match_tied_reg_operand (arg
, arg
->last_regno
);
6300 return match_pc_operand (arg
);
6303 return match_reg28_operand (arg
);
6306 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6308 case OP_VU0_MATCH_SUFFIX
:
6309 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6312 return match_imm_index_operand (arg
, operand
);
6315 return match_reg_index_operand (arg
, operand
);
6318 return match_same_rs_rt_operand (arg
, operand
);
6321 return match_check_prev_operand (arg
, operand
);
6323 case OP_NON_ZERO_REG
:
6324 return match_non_zero_reg_operand (arg
, operand
);
6329 /* ARG is the state after successfully matching an instruction.
6330 Issue any queued-up warnings. */
6333 check_completed_insn (struct mips_arg_info
*arg
)
6338 as_warn (_("used $at without \".set noat\""));
6340 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6344 /* Return true if modifying general-purpose register REG needs a delay. */
6347 reg_needs_delay (unsigned int reg
)
6349 unsigned long prev_pinfo
;
6351 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6352 if (!mips_opts
.noreorder
6353 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6354 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6355 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6361 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6362 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6363 by VR4120 errata. */
6366 classify_vr4120_insn (const char *name
)
6368 if (strncmp (name
, "macc", 4) == 0)
6369 return FIX_VR4120_MACC
;
6370 if (strncmp (name
, "dmacc", 5) == 0)
6371 return FIX_VR4120_DMACC
;
6372 if (strncmp (name
, "mult", 4) == 0)
6373 return FIX_VR4120_MULT
;
6374 if (strncmp (name
, "dmult", 5) == 0)
6375 return FIX_VR4120_DMULT
;
6376 if (strstr (name
, "div"))
6377 return FIX_VR4120_DIV
;
6378 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6379 return FIX_VR4120_MTHILO
;
6380 return NUM_FIX_VR4120_CLASSES
;
6383 #define INSN_ERET 0x42000018
6384 #define INSN_DERET 0x4200001f
6385 #define INSN_DMULT 0x1c
6386 #define INSN_DMULTU 0x1d
6388 /* Return the number of instructions that must separate INSN1 and INSN2,
6389 where INSN1 is the earlier instruction. Return the worst-case value
6390 for any INSN2 if INSN2 is null. */
6393 insns_between (const struct mips_cl_insn
*insn1
,
6394 const struct mips_cl_insn
*insn2
)
6396 unsigned long pinfo1
, pinfo2
;
6399 /* If INFO2 is null, pessimistically assume that all flags are set for
6400 the second instruction. */
6401 pinfo1
= insn1
->insn_mo
->pinfo
;
6402 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6404 /* For most targets, write-after-read dependencies on the HI and LO
6405 registers must be separated by at least two instructions. */
6406 if (!hilo_interlocks
)
6408 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6410 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6414 /* If we're working around r7000 errata, there must be two instructions
6415 between an mfhi or mflo and any instruction that uses the result. */
6416 if (mips_7000_hilo_fix
6417 && !mips_opts
.micromips
6418 && MF_HILO_INSN (pinfo1
)
6419 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6422 /* If we're working around 24K errata, one instruction is required
6423 if an ERET or DERET is followed by a branch instruction. */
6424 if (mips_fix_24k
&& !mips_opts
.micromips
)
6426 if (insn1
->insn_opcode
== INSN_ERET
6427 || insn1
->insn_opcode
== INSN_DERET
)
6430 || insn2
->insn_opcode
== INSN_ERET
6431 || insn2
->insn_opcode
== INSN_DERET
6432 || delayed_branch_p (insn2
))
6437 /* If we're working around PMC RM7000 errata, there must be three
6438 nops between a dmult and a load instruction. */
6439 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6441 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6442 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6444 if (pinfo2
& INSN_LOAD_MEMORY
)
6449 /* If working around VR4120 errata, check for combinations that need
6450 a single intervening instruction. */
6451 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6453 unsigned int class1
, class2
;
6455 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6456 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6460 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6461 if (vr4120_conflicts
[class1
] & (1 << class2
))
6466 if (!HAVE_CODE_COMPRESSION
)
6468 /* Check for GPR or coprocessor load delays. All such delays
6469 are on the RT register. */
6470 /* Itbl support may require additional care here. */
6471 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6472 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6474 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6478 /* Check for generic coprocessor hazards.
6480 This case is not handled very well. There is no special
6481 knowledge of CP0 handling, and the coprocessors other than
6482 the floating point unit are not distinguished at all. */
6483 /* Itbl support may require additional care here. FIXME!
6484 Need to modify this to include knowledge about
6485 user specified delays! */
6486 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6487 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6489 /* Handle cases where INSN1 writes to a known general coprocessor
6490 register. There must be a one instruction delay before INSN2
6491 if INSN2 reads that register, otherwise no delay is needed. */
6492 mask
= fpr_write_mask (insn1
);
6495 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6500 /* Read-after-write dependencies on the control registers
6501 require a two-instruction gap. */
6502 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6503 && (pinfo2
& INSN_READ_COND_CODE
))
6506 /* We don't know exactly what INSN1 does. If INSN2 is
6507 also a coprocessor instruction, assume there must be
6508 a one instruction gap. */
6509 if (pinfo2
& INSN_COP
)
6514 /* Check for read-after-write dependencies on the coprocessor
6515 control registers in cases where INSN1 does not need a general
6516 coprocessor delay. This means that INSN1 is a floating point
6517 comparison instruction. */
6518 /* Itbl support may require additional care here. */
6519 else if (!cop_interlocks
6520 && (pinfo1
& INSN_WRITE_COND_CODE
)
6521 && (pinfo2
& INSN_READ_COND_CODE
))
6525 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6526 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6528 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6529 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6530 || (insn2
&& delayed_branch_p (insn2
))))
6536 /* Return the number of nops that would be needed to work around the
6537 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6538 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6539 that are contained within the first IGNORE instructions of HIST. */
6542 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6543 const struct mips_cl_insn
*insn
)
6548 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6549 are not affected by the errata. */
6551 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6552 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6553 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6556 /* Search for the first MFLO or MFHI. */
6557 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6558 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6560 /* Extract the destination register. */
6561 mask
= gpr_write_mask (&hist
[i
]);
6563 /* No nops are needed if INSN reads that register. */
6564 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6567 /* ...or if any of the intervening instructions do. */
6568 for (j
= 0; j
< i
; j
++)
6569 if (gpr_read_mask (&hist
[j
]) & mask
)
6573 return MAX_VR4130_NOPS
- i
;
6578 #define BASE_REG_EQ(INSN1, INSN2) \
6579 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6580 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6582 /* Return the minimum alignment for this store instruction. */
6585 fix_24k_align_to (const struct mips_opcode
*mo
)
6587 if (strcmp (mo
->name
, "sh") == 0)
6590 if (strcmp (mo
->name
, "swc1") == 0
6591 || strcmp (mo
->name
, "swc2") == 0
6592 || strcmp (mo
->name
, "sw") == 0
6593 || strcmp (mo
->name
, "sc") == 0
6594 || strcmp (mo
->name
, "s.s") == 0)
6597 if (strcmp (mo
->name
, "sdc1") == 0
6598 || strcmp (mo
->name
, "sdc2") == 0
6599 || strcmp (mo
->name
, "s.d") == 0)
6606 struct fix_24k_store_info
6608 /* Immediate offset, if any, for this store instruction. */
6610 /* Alignment required by this store instruction. */
6612 /* True for register offsets. */
6613 int register_offset
;
6616 /* Comparison function used by qsort. */
6619 fix_24k_sort (const void *a
, const void *b
)
6621 const struct fix_24k_store_info
*pos1
= a
;
6622 const struct fix_24k_store_info
*pos2
= b
;
6624 return (pos1
->off
- pos2
->off
);
6627 /* INSN is a store instruction. Try to record the store information
6628 in STINFO. Return false if the information isn't known. */
6631 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6632 const struct mips_cl_insn
*insn
)
6634 /* The instruction must have a known offset. */
6635 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6638 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6639 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6643 /* Return the number of nops that would be needed to work around the 24k
6644 "lost data on stores during refill" errata if instruction INSN
6645 immediately followed the 2 instructions described by HIST.
6646 Ignore hazards that are contained within the first IGNORE
6647 instructions of HIST.
6649 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6650 for the data cache refills and store data. The following describes
6651 the scenario where the store data could be lost.
6653 * A data cache miss, due to either a load or a store, causing fill
6654 data to be supplied by the memory subsystem
6655 * The first three doublewords of fill data are returned and written
6657 * A sequence of four stores occurs in consecutive cycles around the
6658 final doubleword of the fill:
6662 * Zero, One or more instructions
6665 The four stores A-D must be to different doublewords of the line that
6666 is being filled. The fourth instruction in the sequence above permits
6667 the fill of the final doubleword to be transferred from the FSB into
6668 the cache. In the sequence above, the stores may be either integer
6669 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6670 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6671 different doublewords on the line. If the floating point unit is
6672 running in 1:2 mode, it is not possible to create the sequence above
6673 using only floating point store instructions.
6675 In this case, the cache line being filled is incorrectly marked
6676 invalid, thereby losing the data from any store to the line that
6677 occurs between the original miss and the completion of the five
6678 cycle sequence shown above.
6680 The workarounds are:
6682 * Run the data cache in write-through mode.
6683 * Insert a non-store instruction between
6684 Store A and Store B or Store B and Store C. */
6687 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6688 const struct mips_cl_insn
*insn
)
6690 struct fix_24k_store_info pos
[3];
6691 int align
, i
, base_offset
;
6696 /* If the previous instruction wasn't a store, there's nothing to
6698 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6701 /* If the instructions after the previous one are unknown, we have
6702 to assume the worst. */
6706 /* Check whether we are dealing with three consecutive stores. */
6707 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6708 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6711 /* If we don't know the relationship between the store addresses,
6712 assume the worst. */
6713 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6714 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6717 if (!fix_24k_record_store_info (&pos
[0], insn
)
6718 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6719 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6722 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6724 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6725 X bytes and such that the base register + X is known to be aligned
6728 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6732 align
= pos
[0].align_to
;
6733 base_offset
= pos
[0].off
;
6734 for (i
= 1; i
< 3; i
++)
6735 if (align
< pos
[i
].align_to
)
6737 align
= pos
[i
].align_to
;
6738 base_offset
= pos
[i
].off
;
6740 for (i
= 0; i
< 3; i
++)
6741 pos
[i
].off
-= base_offset
;
6744 pos
[0].off
&= ~align
+ 1;
6745 pos
[1].off
&= ~align
+ 1;
6746 pos
[2].off
&= ~align
+ 1;
6748 /* If any two stores write to the same chunk, they also write to the
6749 same doubleword. The offsets are still sorted at this point. */
6750 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6753 /* A range of at least 9 bytes is needed for the stores to be in
6754 non-overlapping doublewords. */
6755 if (pos
[2].off
- pos
[0].off
<= 8)
6758 if (pos
[2].off
- pos
[1].off
>= 24
6759 || pos
[1].off
- pos
[0].off
>= 24
6760 || pos
[2].off
- pos
[0].off
>= 32)
6766 /* Return the number of nops that would be needed if instruction INSN
6767 immediately followed the MAX_NOPS instructions given by HIST,
6768 where HIST[0] is the most recent instruction. Ignore hazards
6769 between INSN and the first IGNORE instructions in HIST.
6771 If INSN is null, return the worse-case number of nops for any
6775 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6776 const struct mips_cl_insn
*insn
)
6778 int i
, nops
, tmp_nops
;
6781 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6783 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6784 if (tmp_nops
> nops
)
6788 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6790 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6791 if (tmp_nops
> nops
)
6795 if (mips_fix_24k
&& !mips_opts
.micromips
)
6797 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6798 if (tmp_nops
> nops
)
6805 /* The variable arguments provide NUM_INSNS extra instructions that
6806 might be added to HIST. Return the largest number of nops that
6807 would be needed after the extended sequence, ignoring hazards
6808 in the first IGNORE instructions. */
6811 nops_for_sequence (int num_insns
, int ignore
,
6812 const struct mips_cl_insn
*hist
, ...)
6815 struct mips_cl_insn buffer
[MAX_NOPS
];
6816 struct mips_cl_insn
*cursor
;
6819 va_start (args
, hist
);
6820 cursor
= buffer
+ num_insns
;
6821 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6822 while (cursor
> buffer
)
6823 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6825 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6830 /* Like nops_for_insn, but if INSN is a branch, take into account the
6831 worst-case delay for the branch target. */
6834 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6835 const struct mips_cl_insn
*insn
)
6839 nops
= nops_for_insn (ignore
, hist
, insn
);
6840 if (delayed_branch_p (insn
))
6842 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6843 hist
, insn
, get_delay_slot_nop (insn
));
6844 if (tmp_nops
> nops
)
6847 else if (compact_branch_p (insn
))
6849 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6850 if (tmp_nops
> nops
)
6856 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6859 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6861 gas_assert (!HAVE_CODE_COMPRESSION
);
6862 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6863 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6866 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6867 jr target pc &= 'hffff_ffff_cfff_ffff. */
6870 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6872 gas_assert (!HAVE_CODE_COMPRESSION
);
6873 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6874 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6875 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6883 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6884 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6887 ep
.X_op
= O_constant
;
6888 ep
.X_add_number
= 0xcfff0000;
6889 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6890 ep
.X_add_number
= 0xffff;
6891 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6892 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6897 fix_loongson2f (struct mips_cl_insn
* ip
)
6899 if (mips_fix_loongson2f_nop
)
6900 fix_loongson2f_nop (ip
);
6902 if (mips_fix_loongson2f_jump
)
6903 fix_loongson2f_jump (ip
);
6906 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6909 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6911 gas_assert (!HAVE_CODE_COMPRESSION
);
6913 /* If is an local label and the insn is not sync,
6914 look forward that whether an branch between ll/sc jump to here
6915 if so, insert a sync. */
6916 if (seg_info (now_seg
)->label_list
6917 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6918 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6920 const char *label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6921 unsigned long lookback
= ARRAY_SIZE (history
);
6924 for (i
= 0; i
< lookback
; i
++)
6926 if (streq (history
[i
].insn_mo
->name
, "ll")
6927 || streq (history
[i
].insn_mo
->name
, "lld"))
6930 if (streq (history
[i
].insn_mo
->name
, "sc")
6931 || streq (history
[i
].insn_mo
->name
, "scd"))
6935 for (j
= i
+ 1; j
< lookback
; j
++)
6937 if (streq (history
[i
].insn_mo
->name
, "ll")
6938 || streq (history
[i
].insn_mo
->name
, "lld"))
6941 if (delayed_branch_p (&history
[j
]))
6943 if (streq (history
[j
].target
, label_name
))
6945 add_fixed_insn (&sync_insn
);
6946 insert_into_history (0, 1, &sync_insn
);
6955 /* If we find a sc, we look forward to look for an branch insn,
6956 and see whether it jump back and out of ll/sc. */
6957 else if (streq(ip
->insn_mo
->name
, "sc") || streq(ip
->insn_mo
->name
, "scd"))
6959 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6962 for (i
= 0; i
< lookback
; i
++)
6964 if (streq (history
[i
].insn_mo
->name
, "ll")
6965 || streq (history
[i
].insn_mo
->name
, "lld"))
6968 if (delayed_branch_p (&history
[i
]))
6972 for (j
= i
+ 1; j
< lookback
; j
++)
6974 if (streq (history
[j
].insn_mo
->name
, "ll")
6975 || streq (history
[i
].insn_mo
->name
, "lld"))
6979 for (; j
< lookback
; j
++)
6981 if (history
[j
].label
[0] != '\0'
6982 && streq (history
[j
].label
, history
[i
].target
)
6983 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
6985 add_fixed_insn (&sync_insn
);
6986 insert_into_history (++j
, 1, &sync_insn
);
6993 /* Skip if there is a sync before ll/lld. */
6994 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
6995 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
6996 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
6998 add_fixed_insn (&sync_insn
);
6999 insert_into_history (0, 1, &sync_insn
);
7003 /* IP is a branch that has a delay slot, and we need to fill it
7004 automatically. Return true if we can do that by swapping IP
7005 with the previous instruction.
7006 ADDRESS_EXPR is an operand of the instruction to be used with
7010 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7011 bfd_reloc_code_real_type
*reloc_type
)
7013 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7014 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7015 unsigned int fpr_read
, prev_fpr_write
;
7017 /* -O2 and above is required for this optimization. */
7018 if (mips_optimize
< 2)
7021 /* If we have seen .set volatile or .set nomove, don't optimize. */
7022 if (mips_opts
.nomove
)
7025 /* We can't swap if the previous instruction's position is fixed. */
7026 if (history
[0].fixed_p
)
7029 /* If the previous previous insn was in a .set noreorder, we can't
7030 swap. Actually, the MIPS assembler will swap in this situation.
7031 However, gcc configured -with-gnu-as will generate code like
7039 in which we can not swap the bne and INSN. If gcc is not configured
7040 -with-gnu-as, it does not output the .set pseudo-ops. */
7041 if (history
[1].noreorder_p
)
7044 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7045 This means that the previous instruction was a 4-byte one anyhow. */
7046 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7049 /* If the branch is itself the target of a branch, we can not swap.
7050 We cheat on this; all we check for is whether there is a label on
7051 this instruction. If there are any branches to anything other than
7052 a label, users must use .set noreorder. */
7053 if (seg_info (now_seg
)->label_list
)
7056 /* If the previous instruction is in a variant frag other than this
7057 branch's one, we cannot do the swap. This does not apply to
7058 MIPS16 code, which uses variant frags for different purposes. */
7059 if (!mips_opts
.mips16
7061 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7064 /* We do not swap with instructions that cannot architecturally
7065 be placed in a branch delay slot, such as SYNC or ERET. We
7066 also refrain from swapping with a trap instruction, since it
7067 complicates trap handlers to have the trap instruction be in
7069 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7070 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7073 /* Check for conflicts between the branch and the instructions
7074 before the candidate delay slot. */
7075 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7078 /* Check for conflicts between the swapped sequence and the
7079 target of the branch. */
7080 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7083 /* If the branch reads a register that the previous
7084 instruction sets, we can not swap. */
7085 gpr_read
= gpr_read_mask (ip
);
7086 prev_gpr_write
= gpr_write_mask (&history
[0]);
7087 if (gpr_read
& prev_gpr_write
)
7090 fpr_read
= fpr_read_mask (ip
);
7091 prev_fpr_write
= fpr_write_mask (&history
[0]);
7092 if (fpr_read
& prev_fpr_write
)
7095 /* If the branch writes a register that the previous
7096 instruction sets, we can not swap. */
7097 gpr_write
= gpr_write_mask (ip
);
7098 if (gpr_write
& prev_gpr_write
)
7101 /* If the branch writes a register that the previous
7102 instruction reads, we can not swap. */
7103 prev_gpr_read
= gpr_read_mask (&history
[0]);
7104 if (gpr_write
& prev_gpr_read
)
7107 /* If one instruction sets a condition code and the
7108 other one uses a condition code, we can not swap. */
7109 pinfo
= ip
->insn_mo
->pinfo
;
7110 if ((pinfo
& INSN_READ_COND_CODE
)
7111 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7113 if ((pinfo
& INSN_WRITE_COND_CODE
)
7114 && (prev_pinfo
& INSN_READ_COND_CODE
))
7117 /* If the previous instruction uses the PC, we can not swap. */
7118 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7119 if (prev_pinfo2
& INSN2_READ_PC
)
7122 /* If the previous instruction has an incorrect size for a fixed
7123 branch delay slot in microMIPS mode, we cannot swap. */
7124 pinfo2
= ip
->insn_mo
->pinfo2
;
7125 if (mips_opts
.micromips
7126 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7127 && insn_length (history
) != 2)
7129 if (mips_opts
.micromips
7130 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7131 && insn_length (history
) != 4)
7134 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7137 The short loop bug under certain conditions causes loops to execute
7138 only once or twice. We must ensure that the assembler never
7139 generates loops that satisfy all of the following conditions:
7141 - a loop consists of less than or equal to six instructions
7142 (including the branch delay slot);
7143 - a loop contains only one conditional branch instruction at the end
7145 - a loop does not contain any other branch or jump instructions;
7146 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7148 We need to do this because of a hardware bug in the R5900 chip. */
7150 /* Check if instruction has a parameter, ignore "j $31". */
7151 && (address_expr
!= NULL
)
7152 /* Parameter must be 16 bit. */
7153 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7154 /* Branch to same segment. */
7155 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7156 /* Branch to same code fragment. */
7157 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7158 /* Can only calculate branch offset if value is known. */
7159 && symbol_constant_p (address_expr
->X_add_symbol
)
7160 /* Check if branch is really conditional. */
7161 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7162 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7163 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7166 /* Check if loop is shorter than or equal to 6 instructions
7167 including branch and delay slot. */
7168 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7175 /* When the loop includes branches or jumps,
7176 it is not a short loop. */
7177 for (i
= 0; i
< (distance
/ 4); i
++)
7179 if ((history
[i
].cleared_p
)
7180 || delayed_branch_p (&history
[i
]))
7188 /* Insert nop after branch to fix short loop. */
7197 /* Decide how we should add IP to the instruction stream.
7198 ADDRESS_EXPR is an operand of the instruction to be used with
7201 static enum append_method
7202 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7203 bfd_reloc_code_real_type
*reloc_type
)
7205 /* The relaxed version of a macro sequence must be inherently
7207 if (mips_relax
.sequence
== 2)
7210 /* We must not dabble with instructions in a ".set noreorder" block. */
7211 if (mips_opts
.noreorder
)
7214 /* Otherwise, it's our responsibility to fill branch delay slots. */
7215 if (delayed_branch_p (ip
))
7217 if (!branch_likely_p (ip
)
7218 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7221 if (mips_opts
.mips16
7222 && ISA_SUPPORTS_MIPS16E
7223 && gpr_read_mask (ip
) != 0)
7224 return APPEND_ADD_COMPACT
;
7226 if (mips_opts
.micromips
7227 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7228 || (!forced_insn_length
7229 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7230 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7231 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7232 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7233 return APPEND_ADD_COMPACT
;
7235 return APPEND_ADD_WITH_NOP
;
7241 /* IP is an instruction whose opcode we have just changed, END points
7242 to the end of the opcode table processed. Point IP->insn_mo to the
7243 new opcode's definition. */
7246 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7248 const struct mips_opcode
*mo
;
7250 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7251 if (mo
->pinfo
!= INSN_MACRO
7252 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7260 /* IP is a MIPS16 instruction whose opcode we have just changed.
7261 Point IP->insn_mo to the new opcode's definition. */
7264 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7266 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7269 /* IP is a microMIPS instruction whose opcode we have just changed.
7270 Point IP->insn_mo to the new opcode's definition. */
7273 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7275 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7278 /* For microMIPS macros, we need to generate a local number label
7279 as the target of branches. */
7280 #define MICROMIPS_LABEL_CHAR '\037'
7281 static unsigned long micromips_target_label
;
7282 static char micromips_target_name
[32];
7285 micromips_label_name (void)
7287 char *p
= micromips_target_name
;
7288 char symbol_name_temporary
[24];
7296 l
= micromips_target_label
;
7297 #ifdef LOCAL_LABEL_PREFIX
7298 *p
++ = LOCAL_LABEL_PREFIX
;
7301 *p
++ = MICROMIPS_LABEL_CHAR
;
7304 symbol_name_temporary
[i
++] = l
% 10 + '0';
7309 *p
++ = symbol_name_temporary
[--i
];
7312 return micromips_target_name
;
7316 micromips_label_expr (expressionS
*label_expr
)
7318 label_expr
->X_op
= O_symbol
;
7319 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7320 label_expr
->X_add_number
= 0;
7324 micromips_label_inc (void)
7326 micromips_target_label
++;
7327 *micromips_target_name
= '\0';
7331 micromips_add_label (void)
7335 s
= colon (micromips_label_name ());
7336 micromips_label_inc ();
7337 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7340 /* If assembling microMIPS code, then return the microMIPS reloc
7341 corresponding to the requested one if any. Otherwise return
7342 the reloc unchanged. */
7344 static bfd_reloc_code_real_type
7345 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7347 static const bfd_reloc_code_real_type relocs
[][2] =
7349 /* Keep sorted incrementally by the left-hand key. */
7350 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7351 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7352 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7353 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7354 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7355 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7356 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7357 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7358 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7359 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7360 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7361 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7362 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7363 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7364 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7365 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7366 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7367 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7368 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7369 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7370 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7371 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7372 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7373 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7374 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7375 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7376 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7378 bfd_reloc_code_real_type r
;
7381 if (!mips_opts
.micromips
)
7383 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7389 return relocs
[i
][1];
7394 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7395 Return true on success, storing the resolved value in RESULT. */
7398 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7403 case BFD_RELOC_MIPS_HIGHEST
:
7404 case BFD_RELOC_MICROMIPS_HIGHEST
:
7405 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7408 case BFD_RELOC_MIPS_HIGHER
:
7409 case BFD_RELOC_MICROMIPS_HIGHER
:
7410 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7413 case BFD_RELOC_HI16_S
:
7414 case BFD_RELOC_HI16_S_PCREL
:
7415 case BFD_RELOC_MICROMIPS_HI16_S
:
7416 case BFD_RELOC_MIPS16_HI16_S
:
7417 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7420 case BFD_RELOC_HI16
:
7421 case BFD_RELOC_MICROMIPS_HI16
:
7422 case BFD_RELOC_MIPS16_HI16
:
7423 *result
= (operand
>> 16) & 0xffff;
7426 case BFD_RELOC_LO16
:
7427 case BFD_RELOC_LO16_PCREL
:
7428 case BFD_RELOC_MICROMIPS_LO16
:
7429 case BFD_RELOC_MIPS16_LO16
:
7430 *result
= operand
& 0xffff;
7433 case BFD_RELOC_UNUSED
:
7442 /* Output an instruction. IP is the instruction information.
7443 ADDRESS_EXPR is an operand of the instruction to be used with
7444 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7445 a macro expansion. */
7448 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7449 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7451 unsigned long prev_pinfo2
, pinfo
;
7452 bfd_boolean relaxed_branch
= FALSE
;
7453 enum append_method method
;
7454 bfd_boolean relax32
;
7457 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7458 fix_loongson2f (ip
);
7460 ip
->target
[0] = '\0';
7461 if (offset_expr
.X_op
== O_symbol
)
7462 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7463 ip
->label
[0] = '\0';
7464 if (seg_info (now_seg
)->label_list
)
7465 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7466 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7467 fix_loongson3_llsc (ip
);
7469 file_ase_mips16
|= mips_opts
.mips16
;
7470 file_ase_micromips
|= mips_opts
.micromips
;
7472 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7473 pinfo
= ip
->insn_mo
->pinfo
;
7475 /* Don't raise alarm about `nods' frags as they'll fill in the right
7476 kind of nop in relaxation if required. */
7477 if (mips_opts
.micromips
7479 && !(history
[0].frag
7480 && history
[0].frag
->fr_type
== rs_machine_dependent
7481 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7482 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7483 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7484 && micromips_insn_length (ip
->insn_mo
) != 2)
7485 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7486 && micromips_insn_length (ip
->insn_mo
) != 4)))
7487 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7488 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7490 if (address_expr
== NULL
)
7492 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7493 && reloc_type
[1] == BFD_RELOC_UNUSED
7494 && reloc_type
[2] == BFD_RELOC_UNUSED
7495 && address_expr
->X_op
== O_constant
)
7497 switch (*reloc_type
)
7499 case BFD_RELOC_MIPS_JMP
:
7503 /* Shift is 2, unusually, for microMIPS JALX. */
7504 shift
= (mips_opts
.micromips
7505 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7506 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7507 as_bad (_("jump to misaligned address (0x%lx)"),
7508 (unsigned long) address_expr
->X_add_number
);
7509 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7515 case BFD_RELOC_MIPS16_JMP
:
7516 if ((address_expr
->X_add_number
& 3) != 0)
7517 as_bad (_("jump to misaligned address (0x%lx)"),
7518 (unsigned long) address_expr
->X_add_number
);
7520 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7521 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7522 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7526 case BFD_RELOC_16_PCREL_S2
:
7530 shift
= mips_opts
.micromips
? 1 : 2;
7531 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7532 as_bad (_("branch to misaligned address (0x%lx)"),
7533 (unsigned long) address_expr
->X_add_number
);
7534 if (!mips_relax_branch
)
7536 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7537 & ~((1 << (shift
+ 16)) - 1))
7538 as_bad (_("branch address range overflow (0x%lx)"),
7539 (unsigned long) address_expr
->X_add_number
);
7540 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7546 case BFD_RELOC_MIPS_21_PCREL_S2
:
7551 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7552 as_bad (_("branch to misaligned address (0x%lx)"),
7553 (unsigned long) address_expr
->X_add_number
);
7554 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7555 & ~((1 << (shift
+ 21)) - 1))
7556 as_bad (_("branch address range overflow (0x%lx)"),
7557 (unsigned long) address_expr
->X_add_number
);
7558 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7563 case BFD_RELOC_MIPS_26_PCREL_S2
:
7568 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7569 as_bad (_("branch to misaligned address (0x%lx)"),
7570 (unsigned long) address_expr
->X_add_number
);
7571 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7572 & ~((1 << (shift
+ 26)) - 1))
7573 as_bad (_("branch address range overflow (0x%lx)"),
7574 (unsigned long) address_expr
->X_add_number
);
7575 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7584 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7587 ip
->insn_opcode
|= value
& 0xffff;
7595 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7597 /* There are a lot of optimizations we could do that we don't.
7598 In particular, we do not, in general, reorder instructions.
7599 If you use gcc with optimization, it will reorder
7600 instructions and generally do much more optimization then we
7601 do here; repeating all that work in the assembler would only
7602 benefit hand written assembly code, and does not seem worth
7604 int nops
= (mips_optimize
== 0
7605 ? nops_for_insn (0, history
, NULL
)
7606 : nops_for_insn_or_target (0, history
, ip
));
7610 unsigned long old_frag_offset
;
7613 old_frag
= frag_now
;
7614 old_frag_offset
= frag_now_fix ();
7616 for (i
= 0; i
< nops
; i
++)
7617 add_fixed_insn (NOP_INSN
);
7618 insert_into_history (0, nops
, NOP_INSN
);
7622 listing_prev_line ();
7623 /* We may be at the start of a variant frag. In case we
7624 are, make sure there is enough space for the frag
7625 after the frags created by listing_prev_line. The
7626 argument to frag_grow here must be at least as large
7627 as the argument to all other calls to frag_grow in
7628 this file. We don't have to worry about being in the
7629 middle of a variant frag, because the variants insert
7630 all needed nop instructions themselves. */
7634 mips_move_text_labels ();
7636 #ifndef NO_ECOFF_DEBUGGING
7637 if (ECOFF_DEBUGGING
)
7638 ecoff_fix_loc (old_frag
, old_frag_offset
);
7642 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7646 /* Work out how many nops in prev_nop_frag are needed by IP,
7647 ignoring hazards generated by the first prev_nop_frag_since
7649 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7650 gas_assert (nops
<= prev_nop_frag_holds
);
7652 /* Enforce NOPS as a minimum. */
7653 if (nops
> prev_nop_frag_required
)
7654 prev_nop_frag_required
= nops
;
7656 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7658 /* Settle for the current number of nops. Update the history
7659 accordingly (for the benefit of any future .set reorder code). */
7660 prev_nop_frag
= NULL
;
7661 insert_into_history (prev_nop_frag_since
,
7662 prev_nop_frag_holds
, NOP_INSN
);
7666 /* Allow this instruction to replace one of the nops that was
7667 tentatively added to prev_nop_frag. */
7668 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7669 prev_nop_frag_holds
--;
7670 prev_nop_frag_since
++;
7674 method
= get_append_method (ip
, address_expr
, reloc_type
);
7675 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7677 dwarf2_emit_insn (0);
7678 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7679 so "move" the instruction address accordingly.
7681 Also, it doesn't seem appropriate for the assembler to reorder .loc
7682 entries. If this instruction is a branch that we are going to swap
7683 with the previous instruction, the two instructions should be
7684 treated as a unit, and the debug information for both instructions
7685 should refer to the start of the branch sequence. Using the
7686 current position is certainly wrong when swapping a 32-bit branch
7687 and a 16-bit delay slot, since the current position would then be
7688 in the middle of a branch. */
7689 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7691 relax32
= (mips_relax_branch
7692 /* Don't try branch relaxation within .set nomacro, or within
7693 .set noat if we use $at for PIC computations. If it turns
7694 out that the branch was out-of-range, we'll get an error. */
7695 && !mips_opts
.warn_about_macros
7696 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7697 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7698 as they have no complementing branches. */
7699 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7701 if (!HAVE_CODE_COMPRESSION
7704 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7705 && delayed_branch_p (ip
))
7707 relaxed_branch
= TRUE
;
7708 add_relaxed_insn (ip
, (relaxed_branch_length
7710 uncond_branch_p (ip
) ? -1
7711 : branch_likely_p (ip
) ? 1
7714 (AT
, mips_pic
!= NO_PIC
,
7715 uncond_branch_p (ip
),
7716 branch_likely_p (ip
),
7717 pinfo
& INSN_WRITE_GPR_31
,
7719 address_expr
->X_add_symbol
,
7720 address_expr
->X_add_number
);
7721 *reloc_type
= BFD_RELOC_UNUSED
;
7723 else if (mips_opts
.micromips
7725 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7726 || *reloc_type
> BFD_RELOC_UNUSED
)
7727 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7728 /* Don't try branch relaxation when users specify
7729 16-bit/32-bit instructions. */
7730 && !forced_insn_length
)
7732 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7733 && *reloc_type
> BFD_RELOC_UNUSED
);
7734 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7735 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7736 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7737 int nods
= method
== APPEND_ADD_WITH_NOP
;
7738 int al
= pinfo
& INSN_WRITE_GPR_31
;
7739 int length32
= nods
? 8 : 4;
7741 gas_assert (address_expr
!= NULL
);
7742 gas_assert (!mips_relax
.sequence
);
7744 relaxed_branch
= TRUE
;
7746 method
= APPEND_ADD
;
7748 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7749 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7750 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7752 uncond
, compact
, al
, nods
,
7754 address_expr
->X_add_symbol
,
7755 address_expr
->X_add_number
);
7756 *reloc_type
= BFD_RELOC_UNUSED
;
7758 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7760 bfd_boolean require_unextended
;
7761 bfd_boolean require_extended
;
7765 if (forced_insn_length
!= 0)
7767 require_unextended
= forced_insn_length
== 2;
7768 require_extended
= forced_insn_length
== 4;
7772 require_unextended
= (mips_opts
.noautoextend
7773 && !mips_opcode_32bit_p (ip
->insn_mo
));
7774 require_extended
= 0;
7777 /* We need to set up a variant frag. */
7778 gas_assert (address_expr
!= NULL
);
7779 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7780 symbol created by `make_expr_symbol' may not get a necessary
7781 external relocation produced. */
7782 if (address_expr
->X_op
== O_symbol
)
7784 symbol
= address_expr
->X_add_symbol
;
7785 offset
= address_expr
->X_add_number
;
7789 symbol
= make_expr_symbol (address_expr
);
7790 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7793 add_relaxed_insn (ip
, 12, 0,
7795 (*reloc_type
- BFD_RELOC_UNUSED
,
7796 mips_opts
.ase
& ASE_MIPS16E2
,
7799 mips_opts
.warn_about_macros
,
7800 require_unextended
, require_extended
,
7801 delayed_branch_p (&history
[0]),
7802 history
[0].mips16_absolute_jump_p
),
7805 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7807 if (!delayed_branch_p (ip
))
7808 /* Make sure there is enough room to swap this instruction with
7809 a following jump instruction. */
7811 add_fixed_insn (ip
);
7815 if (mips_opts
.mips16
7816 && mips_opts
.noreorder
7817 && delayed_branch_p (&history
[0]))
7818 as_warn (_("extended instruction in delay slot"));
7820 if (mips_relax
.sequence
)
7822 /* If we've reached the end of this frag, turn it into a variant
7823 frag and record the information for the instructions we've
7825 if (frag_room () < 4)
7826 relax_close_frag ();
7827 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7830 if (mips_relax
.sequence
!= 2)
7832 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7833 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7834 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7835 mips_macro_warning
.insns
[0]++;
7837 if (mips_relax
.sequence
!= 1)
7839 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7840 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7841 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7842 mips_macro_warning
.insns
[1]++;
7845 if (mips_opts
.mips16
)
7848 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7850 add_fixed_insn (ip
);
7853 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7855 bfd_reloc_code_real_type final_type
[3];
7856 reloc_howto_type
*howto0
;
7857 reloc_howto_type
*howto
;
7860 /* Perform any necessary conversion to microMIPS relocations
7861 and find out how many relocations there actually are. */
7862 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7863 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7865 /* In a compound relocation, it is the final (outermost)
7866 operator that determines the relocated field. */
7867 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7872 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7873 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7874 bfd_get_reloc_size (howto
),
7876 howto0
&& howto0
->pc_relative
,
7878 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7879 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7881 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7882 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7883 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7885 /* These relocations can have an addend that won't fit in
7886 4 octets for 64bit assembly. */
7888 && ! howto
->partial_inplace
7889 && (reloc_type
[0] == BFD_RELOC_16
7890 || reloc_type
[0] == BFD_RELOC_32
7891 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7892 || reloc_type
[0] == BFD_RELOC_GPREL16
7893 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7894 || reloc_type
[0] == BFD_RELOC_GPREL32
7895 || reloc_type
[0] == BFD_RELOC_64
7896 || reloc_type
[0] == BFD_RELOC_CTOR
7897 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7898 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7899 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7900 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7901 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7902 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7903 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7904 || hi16_reloc_p (reloc_type
[0])
7905 || lo16_reloc_p (reloc_type
[0])))
7906 ip
->fixp
[0]->fx_no_overflow
= 1;
7908 /* These relocations can have an addend that won't fit in 2 octets. */
7909 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7910 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7911 ip
->fixp
[0]->fx_no_overflow
= 1;
7913 if (mips_relax
.sequence
)
7915 if (mips_relax
.first_fixup
== 0)
7916 mips_relax
.first_fixup
= ip
->fixp
[0];
7918 else if (reloc_needs_lo_p (*reloc_type
))
7920 struct mips_hi_fixup
*hi_fixup
;
7922 /* Reuse the last entry if it already has a matching %lo. */
7923 hi_fixup
= mips_hi_fixup_list
;
7925 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7927 hi_fixup
= XNEW (struct mips_hi_fixup
);
7928 hi_fixup
->next
= mips_hi_fixup_list
;
7929 mips_hi_fixup_list
= hi_fixup
;
7931 hi_fixup
->fixp
= ip
->fixp
[0];
7932 hi_fixup
->seg
= now_seg
;
7935 /* Add fixups for the second and third relocations, if given.
7936 Note that the ABI allows the second relocation to be
7937 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7938 moment we only use RSS_UNDEF, but we could add support
7939 for the others if it ever becomes necessary. */
7940 for (i
= 1; i
< 3; i
++)
7941 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7943 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7944 ip
->fixp
[0]->fx_size
, NULL
, 0,
7945 FALSE
, final_type
[i
]);
7947 /* Use fx_tcbit to mark compound relocs. */
7948 ip
->fixp
[0]->fx_tcbit
= 1;
7949 ip
->fixp
[i
]->fx_tcbit
= 1;
7953 /* Update the register mask information. */
7954 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7955 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7960 insert_into_history (0, 1, ip
);
7963 case APPEND_ADD_WITH_NOP
:
7965 struct mips_cl_insn
*nop
;
7967 insert_into_history (0, 1, ip
);
7968 nop
= get_delay_slot_nop (ip
);
7969 add_fixed_insn (nop
);
7970 insert_into_history (0, 1, nop
);
7971 if (mips_relax
.sequence
)
7972 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7976 case APPEND_ADD_COMPACT
:
7977 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7978 if (mips_opts
.mips16
)
7980 ip
->insn_opcode
|= 0x0080;
7981 find_altered_mips16_opcode (ip
);
7983 /* Convert microMIPS instructions. */
7984 else if (mips_opts
.micromips
)
7987 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7988 ip
->insn_opcode
|= 0x0020;
7990 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7991 ip
->insn_opcode
= 0x40e00000;
7992 /* beqz16->beqzc, bnez16->bnezc */
7993 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7995 unsigned long regno
;
7997 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7998 regno
&= MICROMIPSOP_MASK_MD
;
7999 regno
= micromips_to_32_reg_d_map
[regno
];
8000 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
8001 | (regno
<< MICROMIPSOP_SH_RS
)
8002 | 0x40a00000) ^ 0x00400000;
8004 /* beqz->beqzc, bnez->bnezc */
8005 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8006 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8007 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8008 | 0x40a00000) ^ 0x00400000;
8009 /* beq $0->beqzc, bne $0->bnezc */
8010 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8011 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8012 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8013 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8014 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8015 | 0x40a00000) ^ 0x00400000;
8018 find_altered_micromips_opcode (ip
);
8023 insert_into_history (0, 1, ip
);
8028 struct mips_cl_insn delay
= history
[0];
8030 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8032 /* Add the delay slot instruction to the end of the
8033 current frag and shrink the fixed part of the
8034 original frag. If the branch occupies the tail of
8035 the latter, move it backwards to cover the gap. */
8036 delay
.frag
->fr_fix
-= branch_disp
;
8037 if (delay
.frag
== ip
->frag
)
8038 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8039 add_fixed_insn (&delay
);
8043 /* If this is not a relaxed branch and we are in the
8044 same frag, then just swap the instructions. */
8045 move_insn (ip
, delay
.frag
, delay
.where
);
8046 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8050 insert_into_history (0, 1, &delay
);
8055 /* If we have just completed an unconditional branch, clear the history. */
8056 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8057 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8061 mips_no_prev_insn ();
8063 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8064 history
[i
].cleared_p
= 1;
8067 /* We need to emit a label at the end of branch-likely macros. */
8068 if (emit_branch_likely_macro
)
8070 emit_branch_likely_macro
= FALSE
;
8071 micromips_add_label ();
8074 /* We just output an insn, so the next one doesn't have a label. */
8075 mips_clear_insn_labels ();
8078 /* Forget that there was any previous instruction or label.
8079 When BRANCH is true, the branch history is also flushed. */
8082 mips_no_prev_insn (void)
8084 prev_nop_frag
= NULL
;
8085 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8086 mips_clear_insn_labels ();
8089 /* This function must be called before we emit something other than
8090 instructions. It is like mips_no_prev_insn except that it inserts
8091 any NOPS that might be needed by previous instructions. */
8094 mips_emit_delays (void)
8096 if (! mips_opts
.noreorder
)
8098 int nops
= nops_for_insn (0, history
, NULL
);
8102 add_fixed_insn (NOP_INSN
);
8103 mips_move_text_labels ();
8106 mips_no_prev_insn ();
8109 /* Start a (possibly nested) noreorder block. */
8112 start_noreorder (void)
8114 if (mips_opts
.noreorder
== 0)
8119 /* None of the instructions before the .set noreorder can be moved. */
8120 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8121 history
[i
].fixed_p
= 1;
8123 /* Insert any nops that might be needed between the .set noreorder
8124 block and the previous instructions. We will later remove any
8125 nops that turn out not to be needed. */
8126 nops
= nops_for_insn (0, history
, NULL
);
8129 if (mips_optimize
!= 0)
8131 /* Record the frag which holds the nop instructions, so
8132 that we can remove them if we don't need them. */
8133 frag_grow (nops
* NOP_INSN_SIZE
);
8134 prev_nop_frag
= frag_now
;
8135 prev_nop_frag_holds
= nops
;
8136 prev_nop_frag_required
= 0;
8137 prev_nop_frag_since
= 0;
8140 for (; nops
> 0; --nops
)
8141 add_fixed_insn (NOP_INSN
);
8143 /* Move on to a new frag, so that it is safe to simply
8144 decrease the size of prev_nop_frag. */
8145 frag_wane (frag_now
);
8147 mips_move_text_labels ();
8149 mips_mark_labels ();
8150 mips_clear_insn_labels ();
8152 mips_opts
.noreorder
++;
8153 mips_any_noreorder
= 1;
8156 /* End a nested noreorder block. */
8159 end_noreorder (void)
8161 mips_opts
.noreorder
--;
8162 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8164 /* Commit to inserting prev_nop_frag_required nops and go back to
8165 handling nop insertion the .set reorder way. */
8166 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8168 insert_into_history (prev_nop_frag_since
,
8169 prev_nop_frag_required
, NOP_INSN
);
8170 prev_nop_frag
= NULL
;
8174 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8175 higher bits unset. */
8178 normalize_constant_expr (expressionS
*ex
)
8180 if (ex
->X_op
== O_constant
8181 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8182 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8186 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8187 all higher bits unset. */
8190 normalize_address_expr (expressionS
*ex
)
8192 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8193 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8194 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8195 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8199 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8200 Return true if the match was successful.
8202 OPCODE_EXTRA is a value that should be ORed into the opcode
8203 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8204 there are more alternatives after OPCODE and SOFT_MATCH is
8205 as for mips_arg_info. */
8208 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8209 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8210 bfd_boolean lax_match
, bfd_boolean complete_p
)
8213 struct mips_arg_info arg
;
8214 const struct mips_operand
*operand
;
8217 imm_expr
.X_op
= O_absent
;
8218 offset_expr
.X_op
= O_absent
;
8219 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8220 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8221 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8223 create_insn (insn
, opcode
);
8224 /* When no opcode suffix is specified, assume ".xyzw". */
8225 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8226 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8228 insn
->insn_opcode
|= opcode_extra
;
8229 memset (&arg
, 0, sizeof (arg
));
8233 arg
.last_regno
= ILLEGAL_REG
;
8234 arg
.dest_regno
= ILLEGAL_REG
;
8235 arg
.lax_match
= lax_match
;
8236 for (args
= opcode
->args
;; ++args
)
8238 if (arg
.token
->type
== OT_END
)
8240 /* Handle unary instructions in which only one operand is given.
8241 The source is then the same as the destination. */
8242 if (arg
.opnum
== 1 && *args
== ',')
8244 operand
= (mips_opts
.micromips
8245 ? decode_micromips_operand (args
+ 1)
8246 : decode_mips_operand (args
+ 1));
8247 if (operand
&& mips_optional_operand_p (operand
))
8255 /* Treat elided base registers as $0. */
8256 if (strcmp (args
, "(b)") == 0)
8264 /* The register suffix is optional. */
8269 /* Fail the match if there were too few operands. */
8273 /* Successful match. */
8276 clear_insn_error ();
8277 if (arg
.dest_regno
== arg
.last_regno
8278 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8282 (0, _("source and destination must be different"));
8283 else if (arg
.last_regno
== 31)
8285 (0, _("a destination register must be supplied"));
8287 else if (arg
.last_regno
== 31
8288 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8289 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8290 set_insn_error (0, _("the source register must not be $31"));
8291 check_completed_insn (&arg
);
8295 /* Fail the match if the line has too many operands. */
8299 /* Handle characters that need to match exactly. */
8300 if (*args
== '(' || *args
== ')' || *args
== ',')
8302 if (match_char (&arg
, *args
))
8309 if (arg
.token
->type
== OT_DOUBLE_CHAR
8310 && arg
.token
->u
.ch
== *args
)
8318 /* Handle special macro operands. Work out the properties of
8327 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8331 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8340 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8344 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8348 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8354 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8356 imm_expr
.X_op
= O_constant
;
8358 normalize_constant_expr (&imm_expr
);
8362 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8364 /* Assume that the offset has been elided and that what
8365 we saw was a base register. The match will fail later
8366 if that assumption turns out to be wrong. */
8367 offset_expr
.X_op
= O_constant
;
8368 offset_expr
.X_add_number
= 0;
8372 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8374 normalize_address_expr (&offset_expr
);
8379 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8385 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8391 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8397 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8403 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8407 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8411 gas_assert (mips_opts
.micromips
);
8417 if (!forced_insn_length
)
8418 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8420 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8422 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8428 operand
= (mips_opts
.micromips
8429 ? decode_micromips_operand (args
)
8430 : decode_mips_operand (args
));
8434 /* Skip prefixes. */
8435 if (*args
== '+' || *args
== 'm' || *args
== '-')
8438 if (mips_optional_operand_p (operand
)
8440 && (arg
.token
[0].type
!= OT_REG
8441 || arg
.token
[1].type
== OT_END
))
8443 /* Assume that the register has been elided and is the
8444 same as the first operand. */
8449 if (!match_operand (&arg
, operand
))
8454 /* Like match_insn, but for MIPS16. */
8457 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8458 struct mips_operand_token
*tokens
)
8461 const struct mips_operand
*operand
;
8462 const struct mips_operand
*ext_operand
;
8463 bfd_boolean pcrel
= FALSE
;
8464 int required_insn_length
;
8465 struct mips_arg_info arg
;
8468 if (forced_insn_length
)
8469 required_insn_length
= forced_insn_length
;
8470 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8471 required_insn_length
= 2;
8473 required_insn_length
= 0;
8475 create_insn (insn
, opcode
);
8476 imm_expr
.X_op
= O_absent
;
8477 offset_expr
.X_op
= O_absent
;
8478 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8479 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8480 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8483 memset (&arg
, 0, sizeof (arg
));
8487 arg
.last_regno
= ILLEGAL_REG
;
8488 arg
.dest_regno
= ILLEGAL_REG
;
8490 for (args
= opcode
->args
;; ++args
)
8494 if (arg
.token
->type
== OT_END
)
8498 /* Handle unary instructions in which only one operand is given.
8499 The source is then the same as the destination. */
8500 if (arg
.opnum
== 1 && *args
== ',')
8502 operand
= decode_mips16_operand (args
[1], FALSE
);
8503 if (operand
&& mips_optional_operand_p (operand
))
8511 /* Fail the match if there were too few operands. */
8515 /* Successful match. Stuff the immediate value in now, if
8517 clear_insn_error ();
8518 if (opcode
->pinfo
== INSN_MACRO
)
8520 gas_assert (relax_char
== 0 || relax_char
== 'p');
8521 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8524 && offset_expr
.X_op
== O_constant
8526 && calculate_reloc (*offset_reloc
,
8527 offset_expr
.X_add_number
,
8530 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8531 required_insn_length
, &insn
->insn_opcode
);
8532 offset_expr
.X_op
= O_absent
;
8533 *offset_reloc
= BFD_RELOC_UNUSED
;
8535 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8537 if (required_insn_length
== 2)
8538 set_insn_error (0, _("invalid unextended operand value"));
8539 else if (!mips_opcode_32bit_p (opcode
))
8541 forced_insn_length
= 4;
8542 insn
->insn_opcode
|= MIPS16_EXTEND
;
8545 else if (relax_char
)
8546 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8548 check_completed_insn (&arg
);
8552 /* Fail the match if the line has too many operands. */
8556 /* Handle characters that need to match exactly. */
8557 if (*args
== '(' || *args
== ')' || *args
== ',')
8559 if (match_char (&arg
, *args
))
8579 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8581 imm_expr
.X_op
= O_constant
;
8583 normalize_constant_expr (&imm_expr
);
8588 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8592 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8596 if (operand
->type
== OP_PCREL
)
8600 ext_operand
= decode_mips16_operand (c
, TRUE
);
8601 if (operand
!= ext_operand
)
8603 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8605 offset_expr
.X_op
= O_constant
;
8606 offset_expr
.X_add_number
= 0;
8611 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8614 /* '8' is used for SLTI(U) and has traditionally not
8615 been allowed to take relocation operators. */
8616 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8617 && (ext_operand
->size
!= 16 || c
== '8'))
8619 match_not_constant (&arg
);
8623 if (offset_expr
.X_op
== O_big
)
8625 match_out_of_range (&arg
);
8634 if (mips_optional_operand_p (operand
)
8636 && (arg
.token
[0].type
!= OT_REG
8637 || arg
.token
[1].type
== OT_END
))
8639 /* Assume that the register has been elided and is the
8640 same as the first operand. */
8645 if (!match_operand (&arg
, operand
))
8650 /* Record that the current instruction is invalid for the current ISA. */
8653 match_invalid_for_isa (void)
8656 (0, _("opcode not supported on this processor: %s (%s)"),
8657 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8658 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8661 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8662 Return true if a definite match or failure was found, storing any match
8663 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8664 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8665 tried and failed to match under normal conditions and now want to try a
8666 more relaxed match. */
8669 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8670 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8671 int opcode_extra
, bfd_boolean lax_match
)
8673 const struct mips_opcode
*opcode
;
8674 const struct mips_opcode
*invalid_delay_slot
;
8675 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8677 /* Search for a match, ignoring alternatives that don't satisfy the
8678 current ISA or forced_length. */
8679 invalid_delay_slot
= 0;
8680 seen_valid_for_isa
= FALSE
;
8681 seen_valid_for_size
= FALSE
;
8685 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8686 if (is_opcode_valid (opcode
))
8688 seen_valid_for_isa
= TRUE
;
8689 if (is_size_valid (opcode
))
8691 bfd_boolean delay_slot_ok
;
8693 seen_valid_for_size
= TRUE
;
8694 delay_slot_ok
= is_delay_slot_valid (opcode
);
8695 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8696 lax_match
, delay_slot_ok
))
8700 if (!invalid_delay_slot
)
8701 invalid_delay_slot
= opcode
;
8710 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8712 /* If the only matches we found had the wrong length for the delay slot,
8713 pick the first such match. We'll issue an appropriate warning later. */
8714 if (invalid_delay_slot
)
8716 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8722 /* Handle the case where we didn't try to match an instruction because
8723 all the alternatives were incompatible with the current ISA. */
8724 if (!seen_valid_for_isa
)
8726 match_invalid_for_isa ();
8730 /* Handle the case where we didn't try to match an instruction because
8731 all the alternatives were of the wrong size. */
8732 if (!seen_valid_for_size
)
8734 if (mips_opts
.insn32
)
8735 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8738 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8739 8 * forced_insn_length
);
8746 /* Like match_insns, but for MIPS16. */
8749 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8750 struct mips_operand_token
*tokens
)
8752 const struct mips_opcode
*opcode
;
8753 bfd_boolean seen_valid_for_isa
;
8754 bfd_boolean seen_valid_for_size
;
8756 /* Search for a match, ignoring alternatives that don't satisfy the
8757 current ISA. There are no separate entries for extended forms so
8758 we deal with forced_length later. */
8759 seen_valid_for_isa
= FALSE
;
8760 seen_valid_for_size
= FALSE
;
8764 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8765 if (is_opcode_valid_16 (opcode
))
8767 seen_valid_for_isa
= TRUE
;
8768 if (is_size_valid_16 (opcode
))
8770 seen_valid_for_size
= TRUE
;
8771 if (match_mips16_insn (insn
, opcode
, tokens
))
8777 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8778 && strcmp (opcode
->name
, first
->name
) == 0);
8780 /* Handle the case where we didn't try to match an instruction because
8781 all the alternatives were incompatible with the current ISA. */
8782 if (!seen_valid_for_isa
)
8784 match_invalid_for_isa ();
8788 /* Handle the case where we didn't try to match an instruction because
8789 all the alternatives were of the wrong size. */
8790 if (!seen_valid_for_size
)
8792 if (forced_insn_length
== 2)
8794 (0, _("unrecognized unextended version of MIPS16 opcode"));
8797 (0, _("unrecognized extended version of MIPS16 opcode"));
8804 /* Set up global variables for the start of a new macro. */
8809 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8810 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8811 sizeof (mips_macro_warning
.first_insn_sizes
));
8812 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8813 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8814 && delayed_branch_p (&history
[0]));
8816 && history
[0].frag
->fr_type
== rs_machine_dependent
8817 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8818 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8819 mips_macro_warning
.delay_slot_length
= 0;
8821 switch (history
[0].insn_mo
->pinfo2
8822 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8824 case INSN2_BRANCH_DELAY_32BIT
:
8825 mips_macro_warning
.delay_slot_length
= 4;
8827 case INSN2_BRANCH_DELAY_16BIT
:
8828 mips_macro_warning
.delay_slot_length
= 2;
8831 mips_macro_warning
.delay_slot_length
= 0;
8834 mips_macro_warning
.first_frag
= NULL
;
8837 /* Given that a macro is longer than one instruction or of the wrong size,
8838 return the appropriate warning for it. Return null if no warning is
8839 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8840 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8841 and RELAX_NOMACRO. */
8844 macro_warning (relax_substateT subtype
)
8846 if (subtype
& RELAX_DELAY_SLOT
)
8847 return _("macro instruction expanded into multiple instructions"
8848 " in a branch delay slot");
8849 else if (subtype
& RELAX_NOMACRO
)
8850 return _("macro instruction expanded into multiple instructions");
8851 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8852 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8853 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8854 ? _("macro instruction expanded into a wrong size instruction"
8855 " in a 16-bit branch delay slot")
8856 : _("macro instruction expanded into a wrong size instruction"
8857 " in a 32-bit branch delay slot"));
8862 /* Finish up a macro. Emit warnings as appropriate. */
8867 /* Relaxation warning flags. */
8868 relax_substateT subtype
= 0;
8870 /* Check delay slot size requirements. */
8871 if (mips_macro_warning
.delay_slot_length
== 2)
8872 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8873 if (mips_macro_warning
.delay_slot_length
!= 0)
8875 if (mips_macro_warning
.delay_slot_length
8876 != mips_macro_warning
.first_insn_sizes
[0])
8877 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8878 if (mips_macro_warning
.delay_slot_length
8879 != mips_macro_warning
.first_insn_sizes
[1])
8880 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8883 /* Check instruction count requirements. */
8884 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8886 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8887 subtype
|= RELAX_SECOND_LONGER
;
8888 if (mips_opts
.warn_about_macros
)
8889 subtype
|= RELAX_NOMACRO
;
8890 if (mips_macro_warning
.delay_slot_p
)
8891 subtype
|= RELAX_DELAY_SLOT
;
8894 /* If both alternatives fail to fill a delay slot correctly,
8895 emit the warning now. */
8896 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8897 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8902 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8903 | RELAX_DELAY_SLOT_SIZE_FIRST
8904 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8905 msg
= macro_warning (s
);
8907 as_warn ("%s", msg
);
8911 /* If both implementations are longer than 1 instruction, then emit the
8913 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8918 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8919 msg
= macro_warning (s
);
8921 as_warn ("%s", msg
);
8925 /* If any flags still set, then one implementation might need a warning
8926 and the other either will need one of a different kind or none at all.
8927 Pass any remaining flags over to relaxation. */
8928 if (mips_macro_warning
.first_frag
!= NULL
)
8929 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8932 /* Instruction operand formats used in macros that vary between
8933 standard MIPS and microMIPS code. */
8935 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8936 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8937 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8938 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8939 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8940 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8941 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8942 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8944 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8945 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8946 : cop12_fmt[mips_opts.micromips])
8947 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8948 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8949 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8950 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8951 : mem12_fmt[mips_opts.micromips])
8952 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8953 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8954 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8956 /* Read a macro's relocation codes from *ARGS and store them in *R.
8957 The first argument in *ARGS will be either the code for a single
8958 relocation or -1 followed by the three codes that make up a
8959 composite relocation. */
8962 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8966 next
= va_arg (*args
, int);
8968 r
[0] = (bfd_reloc_code_real_type
) next
;
8971 for (i
= 0; i
< 3; i
++)
8972 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8973 /* This function is only used for 16-bit relocation fields.
8974 To make the macro code simpler, treat an unrelocated value
8975 in the same way as BFD_RELOC_LO16. */
8976 if (r
[0] == BFD_RELOC_UNUSED
)
8977 r
[0] = BFD_RELOC_LO16
;
8981 /* Build an instruction created by a macro expansion. This is passed
8982 a pointer to the count of instructions created so far, an
8983 expression, the name of the instruction to build, an operand format
8984 string, and corresponding arguments. */
8987 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8989 const struct mips_opcode
*mo
= NULL
;
8990 bfd_reloc_code_real_type r
[3];
8991 const struct mips_opcode
*amo
;
8992 const struct mips_operand
*operand
;
8993 struct hash_control
*hash
;
8994 struct mips_cl_insn insn
;
8998 va_start (args
, fmt
);
9000 if (mips_opts
.mips16
)
9002 mips16_macro_build (ep
, name
, fmt
, &args
);
9007 r
[0] = BFD_RELOC_UNUSED
;
9008 r
[1] = BFD_RELOC_UNUSED
;
9009 r
[2] = BFD_RELOC_UNUSED
;
9010 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9011 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
9013 gas_assert (strcmp (name
, amo
->name
) == 0);
9017 /* Search until we get a match for NAME. It is assumed here that
9018 macros will never generate MDMX, MIPS-3D, or MT instructions.
9019 We try to match an instruction that fulfills the branch delay
9020 slot instruction length requirement (if any) of the previous
9021 instruction. While doing this we record the first instruction
9022 seen that matches all the other conditions and use it anyway
9023 if the requirement cannot be met; we will issue an appropriate
9024 warning later on. */
9025 if (strcmp (fmt
, amo
->args
) == 0
9026 && amo
->pinfo
!= INSN_MACRO
9027 && is_opcode_valid (amo
)
9028 && is_size_valid (amo
))
9030 if (is_delay_slot_valid (amo
))
9040 gas_assert (amo
->name
);
9042 while (strcmp (name
, amo
->name
) == 0);
9045 create_insn (&insn
, mo
);
9058 macro_read_relocs (&args
, r
);
9059 gas_assert (*r
== BFD_RELOC_GPREL16
9060 || *r
== BFD_RELOC_MIPS_HIGHER
9061 || *r
== BFD_RELOC_HI16_S
9062 || *r
== BFD_RELOC_LO16
9063 || *r
== BFD_RELOC_MIPS_GOT_OFST
9064 || (mips_opts
.micromips
9065 && (*r
== BFD_RELOC_16
9066 || *r
== BFD_RELOC_MIPS_GOT16
9067 || *r
== BFD_RELOC_MIPS_CALL16
9068 || *r
== BFD_RELOC_MIPS_GOT_HI16
9069 || *r
== BFD_RELOC_MIPS_GOT_LO16
9070 || *r
== BFD_RELOC_MIPS_CALL_HI16
9071 || *r
== BFD_RELOC_MIPS_CALL_LO16
9072 || *r
== BFD_RELOC_MIPS_SUB
9073 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9074 || *r
== BFD_RELOC_MIPS_HIGHEST
9075 || *r
== BFD_RELOC_MIPS_GOT_DISP
9076 || *r
== BFD_RELOC_MIPS_TLS_GD
9077 || *r
== BFD_RELOC_MIPS_TLS_LDM
9078 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9079 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9080 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9081 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9082 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9086 macro_read_relocs (&args
, r
);
9090 macro_read_relocs (&args
, r
);
9091 gas_assert (ep
!= NULL
9092 && (ep
->X_op
== O_constant
9093 || (ep
->X_op
== O_symbol
9094 && (*r
== BFD_RELOC_MIPS_HIGHEST
9095 || *r
== BFD_RELOC_HI16_S
9096 || *r
== BFD_RELOC_HI16
9097 || *r
== BFD_RELOC_GPREL16
9098 || *r
== BFD_RELOC_MIPS_GOT_HI16
9099 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9103 gas_assert (ep
!= NULL
);
9106 * This allows macro() to pass an immediate expression for
9107 * creating short branches without creating a symbol.
9109 * We don't allow branch relaxation for these branches, as
9110 * they should only appear in ".set nomacro" anyway.
9112 if (ep
->X_op
== O_constant
)
9114 /* For microMIPS we always use relocations for branches.
9115 So we should not resolve immediate values. */
9116 gas_assert (!mips_opts
.micromips
);
9118 if ((ep
->X_add_number
& 3) != 0)
9119 as_bad (_("branch to misaligned address (0x%lx)"),
9120 (unsigned long) ep
->X_add_number
);
9121 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9122 as_bad (_("branch address range overflow (0x%lx)"),
9123 (unsigned long) ep
->X_add_number
);
9124 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9128 *r
= BFD_RELOC_16_PCREL_S2
;
9132 gas_assert (ep
!= NULL
);
9133 *r
= BFD_RELOC_MIPS_JMP
;
9137 operand
= (mips_opts
.micromips
9138 ? decode_micromips_operand (fmt
)
9139 : decode_mips_operand (fmt
));
9143 uval
= va_arg (args
, int);
9144 if (operand
->type
== OP_CLO_CLZ_DEST
)
9145 uval
|= (uval
<< 5);
9146 insn_insert_operand (&insn
, operand
, uval
);
9148 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9154 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9156 append_insn (&insn
, ep
, r
, TRUE
);
9160 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9163 struct mips_opcode
*mo
;
9164 struct mips_cl_insn insn
;
9165 const struct mips_operand
*operand
;
9166 bfd_reloc_code_real_type r
[3]
9167 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9169 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9171 gas_assert (strcmp (name
, mo
->name
) == 0);
9173 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9176 gas_assert (mo
->name
);
9177 gas_assert (strcmp (name
, mo
->name
) == 0);
9180 create_insn (&insn
, mo
);
9217 gas_assert (ep
!= NULL
);
9219 if (ep
->X_op
!= O_constant
)
9220 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9221 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9223 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9225 *r
= BFD_RELOC_UNUSED
;
9231 operand
= decode_mips16_operand (c
, FALSE
);
9235 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9240 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9242 append_insn (&insn
, ep
, r
, TRUE
);
9246 * Generate a "jalr" instruction with a relocation hint to the called
9247 * function. This occurs in NewABI PIC code.
9250 macro_build_jalr (expressionS
*ep
, int cprestore
)
9252 static const bfd_reloc_code_real_type jalr_relocs
[2]
9253 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9254 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9258 if (MIPS_JALR_HINT_P (ep
))
9263 if (mips_opts
.micromips
)
9265 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9266 ? "jalr" : "jalrs");
9267 if (MIPS_JALR_HINT_P (ep
)
9269 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9270 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9272 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9275 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9276 if (MIPS_JALR_HINT_P (ep
))
9277 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9281 * Generate a "lui" instruction.
9284 macro_build_lui (expressionS
*ep
, int regnum
)
9286 gas_assert (! mips_opts
.mips16
);
9288 if (ep
->X_op
!= O_constant
)
9290 gas_assert (ep
->X_op
== O_symbol
);
9291 /* _gp_disp is a special case, used from s_cpload.
9292 __gnu_local_gp is used if mips_no_shared. */
9293 gas_assert (mips_pic
== NO_PIC
9295 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9296 || (! mips_in_shared
9297 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9298 "__gnu_local_gp") == 0));
9301 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9304 /* Generate a sequence of instructions to do a load or store from a constant
9305 offset off of a base register (breg) into/from a target register (treg),
9306 using AT if necessary. */
9308 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9309 int treg
, int breg
, int dbl
)
9311 gas_assert (ep
->X_op
== O_constant
);
9313 /* Sign-extending 32-bit constants makes their handling easier. */
9315 normalize_constant_expr (ep
);
9317 /* Right now, this routine can only handle signed 32-bit constants. */
9318 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9319 as_warn (_("operand overflow"));
9321 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9323 /* Signed 16-bit offset will fit in the op. Easy! */
9324 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9328 /* 32-bit offset, need multiple instructions and AT, like:
9329 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9330 addu $tempreg,$tempreg,$breg
9331 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9332 to handle the complete offset. */
9333 macro_build_lui (ep
, AT
);
9334 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9335 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9338 as_bad (_("macro used $at after \".set noat\""));
9343 * Generates code to set the $at register to true (one)
9344 * if reg is less than the immediate expression.
9347 set_at (int reg
, int unsignedp
)
9349 if (imm_expr
.X_add_number
>= -0x8000
9350 && imm_expr
.X_add_number
< 0x8000)
9351 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9352 AT
, reg
, BFD_RELOC_LO16
);
9355 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9356 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9360 /* Count the leading zeroes by performing a binary chop. This is a
9361 bulky bit of source, but performance is a LOT better for the
9362 majority of values than a simple loop to count the bits:
9363 for (lcnt = 0; (lcnt < 32); lcnt++)
9364 if ((v) & (1 << (31 - lcnt)))
9366 However it is not code size friendly, and the gain will drop a bit
9367 on certain cached systems.
9369 #define COUNT_TOP_ZEROES(v) \
9370 (((v) & ~0xffff) == 0 \
9371 ? ((v) & ~0xff) == 0 \
9372 ? ((v) & ~0xf) == 0 \
9373 ? ((v) & ~0x3) == 0 \
9374 ? ((v) & ~0x1) == 0 \
9379 : ((v) & ~0x7) == 0 \
9382 : ((v) & ~0x3f) == 0 \
9383 ? ((v) & ~0x1f) == 0 \
9386 : ((v) & ~0x7f) == 0 \
9389 : ((v) & ~0xfff) == 0 \
9390 ? ((v) & ~0x3ff) == 0 \
9391 ? ((v) & ~0x1ff) == 0 \
9394 : ((v) & ~0x7ff) == 0 \
9397 : ((v) & ~0x3fff) == 0 \
9398 ? ((v) & ~0x1fff) == 0 \
9401 : ((v) & ~0x7fff) == 0 \
9404 : ((v) & ~0xffffff) == 0 \
9405 ? ((v) & ~0xfffff) == 0 \
9406 ? ((v) & ~0x3ffff) == 0 \
9407 ? ((v) & ~0x1ffff) == 0 \
9410 : ((v) & ~0x7ffff) == 0 \
9413 : ((v) & ~0x3fffff) == 0 \
9414 ? ((v) & ~0x1fffff) == 0 \
9417 : ((v) & ~0x7fffff) == 0 \
9420 : ((v) & ~0xfffffff) == 0 \
9421 ? ((v) & ~0x3ffffff) == 0 \
9422 ? ((v) & ~0x1ffffff) == 0 \
9425 : ((v) & ~0x7ffffff) == 0 \
9428 : ((v) & ~0x3fffffff) == 0 \
9429 ? ((v) & ~0x1fffffff) == 0 \
9432 : ((v) & ~0x7fffffff) == 0 \
9437 * This routine generates the least number of instructions necessary to load
9438 * an absolute expression value into a register.
9441 load_register (int reg
, expressionS
*ep
, int dbl
)
9444 expressionS hi32
, lo32
;
9446 if (ep
->X_op
!= O_big
)
9448 gas_assert (ep
->X_op
== O_constant
);
9450 /* Sign-extending 32-bit constants makes their handling easier. */
9452 normalize_constant_expr (ep
);
9454 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9456 /* We can handle 16 bit signed values with an addiu to
9457 $zero. No need to ever use daddiu here, since $zero and
9458 the result are always correct in 32 bit mode. */
9459 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9462 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9464 /* We can handle 16 bit unsigned values with an ori to
9466 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9469 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9471 /* 32 bit values require an lui. */
9472 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9473 if ((ep
->X_add_number
& 0xffff) != 0)
9474 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9479 /* The value is larger than 32 bits. */
9481 if (!dbl
|| GPR_SIZE
== 32)
9485 sprintf_vma (value
, ep
->X_add_number
);
9486 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9487 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9491 if (ep
->X_op
!= O_big
)
9494 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9495 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9496 hi32
.X_add_number
&= 0xffffffff;
9498 lo32
.X_add_number
&= 0xffffffff;
9502 gas_assert (ep
->X_add_number
> 2);
9503 if (ep
->X_add_number
== 3)
9504 generic_bignum
[3] = 0;
9505 else if (ep
->X_add_number
> 4)
9506 as_bad (_("number larger than 64 bits"));
9507 lo32
.X_op
= O_constant
;
9508 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9509 hi32
.X_op
= O_constant
;
9510 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9513 if (hi32
.X_add_number
== 0)
9518 unsigned long hi
, lo
;
9520 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9522 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9524 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9527 if (lo32
.X_add_number
& 0x80000000)
9529 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9530 if (lo32
.X_add_number
& 0xffff)
9531 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9536 /* Check for 16bit shifted constant. We know that hi32 is
9537 non-zero, so start the mask on the first bit of the hi32
9542 unsigned long himask
, lomask
;
9546 himask
= 0xffff >> (32 - shift
);
9547 lomask
= (0xffff << shift
) & 0xffffffff;
9551 himask
= 0xffff << (shift
- 32);
9554 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9555 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9559 tmp
.X_op
= O_constant
;
9561 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9562 | (lo32
.X_add_number
>> shift
));
9564 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9565 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9566 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9567 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9572 while (shift
<= (64 - 16));
9574 /* Find the bit number of the lowest one bit, and store the
9575 shifted value in hi/lo. */
9576 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9577 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9581 while ((lo
& 1) == 0)
9586 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9592 while ((hi
& 1) == 0)
9601 /* Optimize if the shifted value is a (power of 2) - 1. */
9602 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9603 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9605 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9610 /* This instruction will set the register to be all
9612 tmp
.X_op
= O_constant
;
9613 tmp
.X_add_number
= (offsetT
) -1;
9614 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9618 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9619 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9621 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9622 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9627 /* Sign extend hi32 before calling load_register, because we can
9628 generally get better code when we load a sign extended value. */
9629 if ((hi32
.X_add_number
& 0x80000000) != 0)
9630 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9631 load_register (reg
, &hi32
, 0);
9634 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9638 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9646 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9648 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9649 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9655 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9659 mid16
.X_add_number
>>= 16;
9660 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9661 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9664 if ((lo32
.X_add_number
& 0xffff) != 0)
9665 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9669 load_delay_nop (void)
9671 if (!gpr_interlocks
)
9672 macro_build (NULL
, "nop", "");
9675 /* Load an address into a register. */
9678 load_address (int reg
, expressionS
*ep
, int *used_at
)
9680 if (ep
->X_op
!= O_constant
9681 && ep
->X_op
!= O_symbol
)
9683 as_bad (_("expression too complex"));
9684 ep
->X_op
= O_constant
;
9687 if (ep
->X_op
== O_constant
)
9689 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9693 if (mips_pic
== NO_PIC
)
9695 /* If this is a reference to a GP relative symbol, we want
9696 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9698 lui $reg,<sym> (BFD_RELOC_HI16_S)
9699 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9700 If we have an addend, we always use the latter form.
9702 With 64bit address space and a usable $at we want
9703 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9704 lui $at,<sym> (BFD_RELOC_HI16_S)
9705 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9706 daddiu $at,<sym> (BFD_RELOC_LO16)
9710 If $at is already in use, we use a path which is suboptimal
9711 on superscalar processors.
9712 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9713 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9715 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9717 daddiu $reg,<sym> (BFD_RELOC_LO16)
9719 For GP relative symbols in 64bit address space we can use
9720 the same sequence as in 32bit address space. */
9721 if (HAVE_64BIT_SYMBOLS
)
9723 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9724 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9726 relax_start (ep
->X_add_symbol
);
9727 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9728 mips_gp_register
, BFD_RELOC_GPREL16
);
9732 if (*used_at
== 0 && mips_opts
.at
)
9734 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9735 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9736 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9737 BFD_RELOC_MIPS_HIGHER
);
9738 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9739 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9740 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9745 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9746 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9747 BFD_RELOC_MIPS_HIGHER
);
9748 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9749 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9750 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9751 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9754 if (mips_relax
.sequence
)
9759 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9760 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9762 relax_start (ep
->X_add_symbol
);
9763 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9764 mips_gp_register
, BFD_RELOC_GPREL16
);
9767 macro_build_lui (ep
, reg
);
9768 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9769 reg
, reg
, BFD_RELOC_LO16
);
9770 if (mips_relax
.sequence
)
9774 else if (!mips_big_got
)
9778 /* If this is a reference to an external symbol, we want
9779 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9781 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9783 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9784 If there is a constant, it must be added in after.
9786 If we have NewABI, we want
9787 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9788 unless we're referencing a global symbol with a non-zero
9789 offset, in which case cst must be added separately. */
9792 if (ep
->X_add_number
)
9794 ex
.X_add_number
= ep
->X_add_number
;
9795 ep
->X_add_number
= 0;
9796 relax_start (ep
->X_add_symbol
);
9797 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9798 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9799 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9800 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9801 ex
.X_op
= O_constant
;
9802 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9803 reg
, reg
, BFD_RELOC_LO16
);
9804 ep
->X_add_number
= ex
.X_add_number
;
9807 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9808 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9809 if (mips_relax
.sequence
)
9814 ex
.X_add_number
= ep
->X_add_number
;
9815 ep
->X_add_number
= 0;
9816 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9817 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9819 relax_start (ep
->X_add_symbol
);
9821 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9825 if (ex
.X_add_number
!= 0)
9827 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9828 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9829 ex
.X_op
= O_constant
;
9830 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9831 reg
, reg
, BFD_RELOC_LO16
);
9835 else if (mips_big_got
)
9839 /* This is the large GOT case. If this is a reference to an
9840 external symbol, we want
9841 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9843 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9845 Otherwise, for a reference to a local symbol in old ABI, we want
9846 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9848 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9849 If there is a constant, it must be added in after.
9851 In the NewABI, for local symbols, with or without offsets, we want:
9852 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9853 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9857 ex
.X_add_number
= ep
->X_add_number
;
9858 ep
->X_add_number
= 0;
9859 relax_start (ep
->X_add_symbol
);
9860 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9861 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9862 reg
, reg
, mips_gp_register
);
9863 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9864 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9865 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9866 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9867 else if (ex
.X_add_number
)
9869 ex
.X_op
= O_constant
;
9870 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9874 ep
->X_add_number
= ex
.X_add_number
;
9876 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9877 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9878 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9879 BFD_RELOC_MIPS_GOT_OFST
);
9884 ex
.X_add_number
= ep
->X_add_number
;
9885 ep
->X_add_number
= 0;
9886 relax_start (ep
->X_add_symbol
);
9887 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9888 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9889 reg
, reg
, mips_gp_register
);
9890 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9891 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9893 if (reg_needs_delay (mips_gp_register
))
9895 /* We need a nop before loading from $gp. This special
9896 check is required because the lui which starts the main
9897 instruction stream does not refer to $gp, and so will not
9898 insert the nop which may be required. */
9899 macro_build (NULL
, "nop", "");
9901 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9902 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9904 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9908 if (ex
.X_add_number
!= 0)
9910 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9911 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9912 ex
.X_op
= O_constant
;
9913 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9921 if (!mips_opts
.at
&& *used_at
== 1)
9922 as_bad (_("macro used $at after \".set noat\""));
9925 /* Move the contents of register SOURCE into register DEST. */
9928 move_register (int dest
, int source
)
9930 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9931 instruction specifically requires a 32-bit one. */
9932 if (mips_opts
.micromips
9933 && !mips_opts
.insn32
9934 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9935 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9937 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9940 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9941 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9942 The two alternatives are:
9944 Global symbol Local symbol
9945 ------------- ------------
9946 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9948 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9950 load_got_offset emits the first instruction and add_got_offset
9951 emits the second for a 16-bit offset or add_got_offset_hilo emits
9952 a sequence to add a 32-bit offset using a scratch register. */
9955 load_got_offset (int dest
, expressionS
*local
)
9960 global
.X_add_number
= 0;
9962 relax_start (local
->X_add_symbol
);
9963 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9964 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9966 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9967 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9972 add_got_offset (int dest
, expressionS
*local
)
9976 global
.X_op
= O_constant
;
9977 global
.X_op_symbol
= NULL
;
9978 global
.X_add_symbol
= NULL
;
9979 global
.X_add_number
= local
->X_add_number
;
9981 relax_start (local
->X_add_symbol
);
9982 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9983 dest
, dest
, BFD_RELOC_LO16
);
9985 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9990 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9993 int hold_mips_optimize
;
9995 global
.X_op
= O_constant
;
9996 global
.X_op_symbol
= NULL
;
9997 global
.X_add_symbol
= NULL
;
9998 global
.X_add_number
= local
->X_add_number
;
10000 relax_start (local
->X_add_symbol
);
10001 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10003 /* Set mips_optimize around the lui instruction to avoid
10004 inserting an unnecessary nop after the lw. */
10005 hold_mips_optimize
= mips_optimize
;
10007 macro_build_lui (&global
, tmp
);
10008 mips_optimize
= hold_mips_optimize
;
10009 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10012 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10015 /* Emit a sequence of instructions to emulate a branch likely operation.
10016 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10017 is its complementing branch with the original condition negated.
10018 CALL is set if the original branch specified the link operation.
10019 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10021 Code like this is produced in the noreorder mode:
10026 delay slot (executed only if branch taken)
10029 or, if CALL is set:
10034 delay slot (executed only if branch taken)
10037 In the reorder mode the delay slot would be filled with a nop anyway,
10038 so code produced is simply:
10043 This function is used when producing code for the microMIPS ASE that
10044 does not implement branch likely instructions in hardware. */
10047 macro_build_branch_likely (const char *br
, const char *brneg
,
10048 int call
, expressionS
*ep
, const char *fmt
,
10049 unsigned int sreg
, unsigned int treg
)
10051 int noreorder
= mips_opts
.noreorder
;
10054 gas_assert (mips_opts
.micromips
);
10055 start_noreorder ();
10058 micromips_label_expr (&expr1
);
10059 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10060 macro_build (NULL
, "nop", "");
10061 macro_build (ep
, call
? "bal" : "b", "p");
10063 /* Set to true so that append_insn adds a label. */
10064 emit_branch_likely_macro
= TRUE
;
10068 macro_build (ep
, br
, fmt
, sreg
, treg
);
10069 macro_build (NULL
, "nop", "");
10074 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10075 the condition code tested. EP specifies the branch target. */
10078 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10080 const int call
= 0;
10105 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10108 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10109 the register tested. EP specifies the branch target. */
10112 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10114 const char *brneg
= NULL
;
10124 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10128 gas_assert (mips_opts
.micromips
);
10129 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10137 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10144 br
= mips_opts
.micromips
? "blez" : "blezl";
10151 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10155 gas_assert (mips_opts
.micromips
);
10156 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10163 if (mips_opts
.micromips
&& brneg
)
10164 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10166 macro_build (ep
, br
, "s,p", sreg
);
10169 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10170 TREG as the registers tested. EP specifies the branch target. */
10173 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10174 unsigned int sreg
, unsigned int treg
)
10176 const char *brneg
= NULL
;
10177 const int call
= 0;
10188 br
= mips_opts
.micromips
? "beq" : "beql";
10197 br
= mips_opts
.micromips
? "bne" : "bnel";
10203 if (mips_opts
.micromips
&& brneg
)
10204 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10206 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10209 /* Return the high part that should be loaded in order to make the low
10210 part of VALUE accessible using an offset of OFFBITS bits. */
10213 offset_high_part (offsetT value
, unsigned int offbits
)
10220 bias
= 1 << (offbits
- 1);
10221 low_mask
= bias
* 2 - 1;
10222 return (value
+ bias
) & ~low_mask
;
10225 /* Return true if the value stored in offset_expr and offset_reloc
10226 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10227 amount that the caller wants to add without inducing overflow
10228 and ALIGN is the known alignment of the value in bytes. */
10231 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10235 /* Accept any relocation operator if overflow isn't a concern. */
10236 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10239 /* These relocations are guaranteed not to overflow in correct links. */
10240 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10241 || gprel16_reloc_p (*offset_reloc
))
10244 if (offset_expr
.X_op
== O_constant
10245 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10246 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10253 * This routine implements the seemingly endless macro or synthesized
10254 * instructions and addressing modes in the mips assembly language. Many
10255 * of these macros are simple and are similar to each other. These could
10256 * probably be handled by some kind of table or grammar approach instead of
10257 * this verbose method. Others are not simple macros but are more like
10258 * optimizing code generation.
10259 * One interesting optimization is when several store macros appear
10260 * consecutively that would load AT with the upper half of the same address.
10261 * The ensuing load upper instructions are omitted. This implies some kind
10262 * of global optimization. We currently only optimize within a single macro.
10263 * For many of the load and store macros if the address is specified as a
10264 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10265 * first load register 'at' with zero and use it as the base register. The
10266 * mips assembler simply uses register $zero. Just one tiny optimization
10270 macro (struct mips_cl_insn
*ip
, char *str
)
10272 const struct mips_operand_array
*operands
;
10273 unsigned int breg
, i
;
10274 unsigned int tempreg
;
10277 expressionS label_expr
;
10292 int ll_sc_paired
= 0;
10293 bfd_boolean large_offset
;
10295 int hold_mips_optimize
;
10296 unsigned int align
;
10297 unsigned int op
[MAX_OPERANDS
];
10299 gas_assert (! mips_opts
.mips16
);
10301 operands
= insn_operands (ip
);
10302 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10303 if (operands
->operand
[i
])
10304 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10308 mask
= ip
->insn_mo
->mask
;
10310 label_expr
.X_op
= O_constant
;
10311 label_expr
.X_op_symbol
= NULL
;
10312 label_expr
.X_add_symbol
= NULL
;
10313 label_expr
.X_add_number
= 0;
10315 expr1
.X_op
= O_constant
;
10316 expr1
.X_op_symbol
= NULL
;
10317 expr1
.X_add_symbol
= NULL
;
10318 expr1
.X_add_number
= 1;
10325 /* Fall through. */
10333 start_noreorder ();
10335 if (mips_opts
.micromips
)
10336 micromips_label_expr (&label_expr
);
10338 label_expr
.X_add_number
= 8;
10339 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10340 if (op
[0] == op
[1])
10341 macro_build (NULL
, "nop", "");
10343 move_register (op
[0], op
[1]);
10344 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10345 if (mips_opts
.micromips
)
10346 micromips_add_label ();
10354 if (ISA_IS_R6 (mips_opts
.isa
))
10366 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10368 if (imm_expr
.X_add_number
>= -0x200
10369 && imm_expr
.X_add_number
< 0x200
10370 && !ISA_IS_R6 (mips_opts
.isa
))
10372 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10373 (int) imm_expr
.X_add_number
);
10382 if (imm_expr
.X_add_number
>= -0x8000
10383 && imm_expr
.X_add_number
< 0x8000)
10385 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10390 load_register (AT
, &imm_expr
, dbl
);
10391 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10410 if (imm_expr
.X_add_number
>= 0
10411 && imm_expr
.X_add_number
< 0x10000)
10413 if (mask
!= M_NOR_I
)
10414 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10417 macro_build (&imm_expr
, "ori", "t,r,i",
10418 op
[0], op
[1], BFD_RELOC_LO16
);
10419 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10425 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10426 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10430 switch (imm_expr
.X_add_number
)
10433 macro_build (NULL
, "nop", "");
10436 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10440 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10441 (int) imm_expr
.X_add_number
);
10444 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10445 (unsigned long) imm_expr
.X_add_number
);
10454 gas_assert (mips_opts
.micromips
);
10455 macro_build_branch_ccl (mask
, &offset_expr
,
10456 EXTRACT_OPERAND (1, BCC
, *ip
));
10463 if (imm_expr
.X_add_number
== 0)
10469 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10471 /* Fall through. */
10474 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10479 /* Fall through. */
10482 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10483 else if (op
[0] == 0)
10484 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10488 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10489 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10490 &offset_expr
, AT
, ZERO
);
10500 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10505 /* Fall through. */
10507 /* Check for > max integer. */
10508 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10511 /* Result is always false. */
10513 macro_build (NULL
, "nop", "");
10515 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10518 ++imm_expr
.X_add_number
;
10519 /* Fall through. */
10522 if (mask
== M_BGEL_I
)
10524 if (imm_expr
.X_add_number
== 0)
10526 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10527 &offset_expr
, op
[0]);
10530 if (imm_expr
.X_add_number
== 1)
10532 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10533 &offset_expr
, op
[0]);
10536 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10539 /* Result is always true. */
10540 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10541 macro_build (&offset_expr
, "b", "p");
10546 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10547 &offset_expr
, AT
, ZERO
);
10552 /* Fall through. */
10556 else if (op
[0] == 0)
10557 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10558 &offset_expr
, ZERO
, op
[1]);
10562 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10563 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10564 &offset_expr
, AT
, ZERO
);
10570 /* Fall through. */
10574 && imm_expr
.X_add_number
== -1))
10576 ++imm_expr
.X_add_number
;
10577 /* Fall through. */
10580 if (mask
== M_BGEUL_I
)
10582 if (imm_expr
.X_add_number
== 0)
10584 else if (imm_expr
.X_add_number
== 1)
10585 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10586 &offset_expr
, op
[0], ZERO
);
10591 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10592 &offset_expr
, AT
, ZERO
);
10598 /* Fall through. */
10601 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10602 else if (op
[0] == 0)
10603 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10607 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10608 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10609 &offset_expr
, AT
, ZERO
);
10615 /* Fall through. */
10618 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10619 &offset_expr
, op
[0], ZERO
);
10620 else if (op
[0] == 0)
10625 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10626 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10627 &offset_expr
, AT
, ZERO
);
10633 /* Fall through. */
10636 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10637 else if (op
[0] == 0)
10638 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10642 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10643 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10644 &offset_expr
, AT
, ZERO
);
10650 /* Fall through. */
10652 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10654 ++imm_expr
.X_add_number
;
10655 /* Fall through. */
10658 if (mask
== M_BLTL_I
)
10660 if (imm_expr
.X_add_number
== 0)
10661 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10662 else if (imm_expr
.X_add_number
== 1)
10663 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10668 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10669 &offset_expr
, AT
, ZERO
);
10675 /* Fall through. */
10678 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10679 &offset_expr
, op
[0], ZERO
);
10680 else if (op
[0] == 0)
10685 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10686 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10687 &offset_expr
, AT
, ZERO
);
10693 /* Fall through. */
10697 && imm_expr
.X_add_number
== -1))
10699 ++imm_expr
.X_add_number
;
10700 /* Fall through. */
10703 if (mask
== M_BLTUL_I
)
10705 if (imm_expr
.X_add_number
== 0)
10707 else if (imm_expr
.X_add_number
== 1)
10708 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10709 &offset_expr
, op
[0], ZERO
);
10714 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10715 &offset_expr
, AT
, ZERO
);
10721 /* Fall through. */
10724 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10725 else if (op
[0] == 0)
10726 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10730 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10731 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10732 &offset_expr
, AT
, ZERO
);
10738 /* Fall through. */
10742 else if (op
[0] == 0)
10743 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10744 &offset_expr
, ZERO
, op
[1]);
10748 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10749 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10750 &offset_expr
, AT
, ZERO
);
10756 /* Fall through. */
10762 /* Fall through. */
10768 as_warn (_("divide by zero"));
10770 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10772 macro_build (NULL
, "break", BRK_FMT
, 7);
10776 start_noreorder ();
10779 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10780 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10784 if (mips_opts
.micromips
)
10785 micromips_label_expr (&label_expr
);
10787 label_expr
.X_add_number
= 8;
10788 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10789 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10790 macro_build (NULL
, "break", BRK_FMT
, 7);
10791 if (mips_opts
.micromips
)
10792 micromips_add_label ();
10794 expr1
.X_add_number
= -1;
10796 load_register (AT
, &expr1
, dbl
);
10797 if (mips_opts
.micromips
)
10798 micromips_label_expr (&label_expr
);
10800 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10801 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10804 expr1
.X_add_number
= 1;
10805 load_register (AT
, &expr1
, dbl
);
10806 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10810 expr1
.X_add_number
= 0x80000000;
10811 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10815 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10816 /* We want to close the noreorder block as soon as possible, so
10817 that later insns are available for delay slot filling. */
10822 if (mips_opts
.micromips
)
10823 micromips_label_expr (&label_expr
);
10825 label_expr
.X_add_number
= 8;
10826 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10827 macro_build (NULL
, "nop", "");
10829 /* We want to close the noreorder block as soon as possible, so
10830 that later insns are available for delay slot filling. */
10833 macro_build (NULL
, "break", BRK_FMT
, 6);
10835 if (mips_opts
.micromips
)
10836 micromips_add_label ();
10837 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10876 if (imm_expr
.X_add_number
== 0)
10878 as_warn (_("divide by zero"));
10880 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10882 macro_build (NULL
, "break", BRK_FMT
, 7);
10885 if (imm_expr
.X_add_number
== 1)
10887 if (strcmp (s2
, "mflo") == 0)
10888 move_register (op
[0], op
[1]);
10890 move_register (op
[0], ZERO
);
10893 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10895 if (strcmp (s2
, "mflo") == 0)
10896 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10898 move_register (op
[0], ZERO
);
10903 load_register (AT
, &imm_expr
, dbl
);
10904 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10905 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10924 start_noreorder ();
10927 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10928 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10929 /* We want to close the noreorder block as soon as possible, so
10930 that later insns are available for delay slot filling. */
10935 if (mips_opts
.micromips
)
10936 micromips_label_expr (&label_expr
);
10938 label_expr
.X_add_number
= 8;
10939 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10940 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10942 /* We want to close the noreorder block as soon as possible, so
10943 that later insns are available for delay slot filling. */
10945 macro_build (NULL
, "break", BRK_FMT
, 7);
10946 if (mips_opts
.micromips
)
10947 micromips_add_label ();
10949 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10954 /* Fall through. */
10960 /* Fall through. */
10963 /* Load the address of a symbol into a register. If breg is not
10964 zero, we then add a base register to it. */
10967 if (dbl
&& GPR_SIZE
== 32)
10968 as_warn (_("dla used to load 32-bit register; recommend using la "
10971 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10972 as_warn (_("la used to load 64-bit address; recommend using dla "
10975 if (small_offset_p (0, align
, 16))
10977 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10978 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10982 if (mips_opts
.at
&& (op
[0] == breg
))
10990 if (offset_expr
.X_op
!= O_symbol
10991 && offset_expr
.X_op
!= O_constant
)
10993 as_bad (_("expression too complex"));
10994 offset_expr
.X_op
= O_constant
;
10997 if (offset_expr
.X_op
== O_constant
)
10998 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10999 else if (mips_pic
== NO_PIC
)
11001 /* If this is a reference to a GP relative symbol, we want
11002 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11004 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11005 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11006 If we have a constant, we need two instructions anyhow,
11007 so we may as well always use the latter form.
11009 With 64bit address space and a usable $at we want
11010 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11011 lui $at,<sym> (BFD_RELOC_HI16_S)
11012 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11013 daddiu $at,<sym> (BFD_RELOC_LO16)
11015 daddu $tempreg,$tempreg,$at
11017 If $at is already in use, we use a path which is suboptimal
11018 on superscalar processors.
11019 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11020 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11022 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11024 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11026 For GP relative symbols in 64bit address space we can use
11027 the same sequence as in 32bit address space. */
11028 if (HAVE_64BIT_SYMBOLS
)
11030 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11031 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11033 relax_start (offset_expr
.X_add_symbol
);
11034 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11035 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11039 if (used_at
== 0 && mips_opts
.at
)
11041 macro_build (&offset_expr
, "lui", LUI_FMT
,
11042 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11043 macro_build (&offset_expr
, "lui", LUI_FMT
,
11044 AT
, BFD_RELOC_HI16_S
);
11045 macro_build (&offset_expr
, "daddiu", "t,r,j",
11046 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11047 macro_build (&offset_expr
, "daddiu", "t,r,j",
11048 AT
, AT
, BFD_RELOC_LO16
);
11049 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11050 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11055 macro_build (&offset_expr
, "lui", LUI_FMT
,
11056 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11057 macro_build (&offset_expr
, "daddiu", "t,r,j",
11058 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11059 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11060 macro_build (&offset_expr
, "daddiu", "t,r,j",
11061 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11062 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11063 macro_build (&offset_expr
, "daddiu", "t,r,j",
11064 tempreg
, tempreg
, BFD_RELOC_LO16
);
11067 if (mips_relax
.sequence
)
11072 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11073 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11075 relax_start (offset_expr
.X_add_symbol
);
11076 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11077 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11080 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11081 as_bad (_("offset too large"));
11082 macro_build_lui (&offset_expr
, tempreg
);
11083 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11084 tempreg
, tempreg
, BFD_RELOC_LO16
);
11085 if (mips_relax
.sequence
)
11089 else if (!mips_big_got
&& !HAVE_NEWABI
)
11091 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11093 /* If this is a reference to an external symbol, and there
11094 is no constant, we want
11095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11096 or for lca or if tempreg is PIC_CALL_REG
11097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11098 For a local symbol, we want
11099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11101 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11103 If we have a small constant, and this is a reference to
11104 an external symbol, we want
11105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11107 addiu $tempreg,$tempreg,<constant>
11108 For a local symbol, we want the same instruction
11109 sequence, but we output a BFD_RELOC_LO16 reloc on the
11112 If we have a large constant, and this is a reference to
11113 an external symbol, we want
11114 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11115 lui $at,<hiconstant>
11116 addiu $at,$at,<loconstant>
11117 addu $tempreg,$tempreg,$at
11118 For a local symbol, we want the same instruction
11119 sequence, but we output a BFD_RELOC_LO16 reloc on the
11123 if (offset_expr
.X_add_number
== 0)
11125 if (mips_pic
== SVR4_PIC
11127 && (call
|| tempreg
== PIC_CALL_REG
))
11128 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11130 relax_start (offset_expr
.X_add_symbol
);
11131 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11132 lw_reloc_type
, mips_gp_register
);
11135 /* We're going to put in an addu instruction using
11136 tempreg, so we may as well insert the nop right
11141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11142 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11144 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11145 tempreg
, tempreg
, BFD_RELOC_LO16
);
11147 /* FIXME: If breg == 0, and the next instruction uses
11148 $tempreg, then if this variant case is used an extra
11149 nop will be generated. */
11151 else if (offset_expr
.X_add_number
>= -0x8000
11152 && offset_expr
.X_add_number
< 0x8000)
11154 load_got_offset (tempreg
, &offset_expr
);
11156 add_got_offset (tempreg
, &offset_expr
);
11160 expr1
.X_add_number
= offset_expr
.X_add_number
;
11161 offset_expr
.X_add_number
=
11162 SEXT_16BIT (offset_expr
.X_add_number
);
11163 load_got_offset (tempreg
, &offset_expr
);
11164 offset_expr
.X_add_number
= expr1
.X_add_number
;
11165 /* If we are going to add in a base register, and the
11166 target register and the base register are the same,
11167 then we are using AT as a temporary register. Since
11168 we want to load the constant into AT, we add our
11169 current AT (from the global offset table) and the
11170 register into the register now, and pretend we were
11171 not using a base register. */
11175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11180 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11184 else if (!mips_big_got
&& HAVE_NEWABI
)
11186 int add_breg_early
= 0;
11188 /* If this is a reference to an external, and there is no
11189 constant, or local symbol (*), with or without a
11191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11192 or for lca or if tempreg is PIC_CALL_REG
11193 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11195 If we have a small constant, and this is a reference to
11196 an external symbol, we want
11197 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11198 addiu $tempreg,$tempreg,<constant>
11200 If we have a large constant, and this is a reference to
11201 an external symbol, we want
11202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11203 lui $at,<hiconstant>
11204 addiu $at,$at,<loconstant>
11205 addu $tempreg,$tempreg,$at
11207 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11208 local symbols, even though it introduces an additional
11211 if (offset_expr
.X_add_number
)
11213 expr1
.X_add_number
= offset_expr
.X_add_number
;
11214 offset_expr
.X_add_number
= 0;
11216 relax_start (offset_expr
.X_add_symbol
);
11217 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11218 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11220 if (expr1
.X_add_number
>= -0x8000
11221 && expr1
.X_add_number
< 0x8000)
11223 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11224 tempreg
, tempreg
, BFD_RELOC_LO16
);
11226 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11230 /* If we are going to add in a base register, and the
11231 target register and the base register are the same,
11232 then we are using AT as a temporary register. Since
11233 we want to load the constant into AT, we add our
11234 current AT (from the global offset table) and the
11235 register into the register now, and pretend we were
11236 not using a base register. */
11241 gas_assert (tempreg
== AT
);
11242 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11245 add_breg_early
= 1;
11248 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11249 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11255 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11258 offset_expr
.X_add_number
= expr1
.X_add_number
;
11260 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11261 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11262 if (add_breg_early
)
11264 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11265 op
[0], tempreg
, breg
);
11271 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11273 relax_start (offset_expr
.X_add_symbol
);
11274 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11275 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11277 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11278 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11283 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11284 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11287 else if (mips_big_got
&& !HAVE_NEWABI
)
11290 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11291 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11292 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11294 /* This is the large GOT case. If this is a reference to an
11295 external symbol, and there is no constant, we want
11296 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11297 addu $tempreg,$tempreg,$gp
11298 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11299 or for lca or if tempreg is PIC_CALL_REG
11300 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11301 addu $tempreg,$tempreg,$gp
11302 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11303 For a local symbol, we want
11304 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11306 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11308 If we have a small constant, and this is a reference to
11309 an external symbol, we want
11310 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11311 addu $tempreg,$tempreg,$gp
11312 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11314 addiu $tempreg,$tempreg,<constant>
11315 For a local symbol, we want
11316 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11318 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11320 If we have a large constant, and this is a reference to
11321 an external symbol, we want
11322 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11323 addu $tempreg,$tempreg,$gp
11324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11325 lui $at,<hiconstant>
11326 addiu $at,$at,<loconstant>
11327 addu $tempreg,$tempreg,$at
11328 For a local symbol, we want
11329 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11330 lui $at,<hiconstant>
11331 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11332 addu $tempreg,$tempreg,$at
11335 expr1
.X_add_number
= offset_expr
.X_add_number
;
11336 offset_expr
.X_add_number
= 0;
11337 relax_start (offset_expr
.X_add_symbol
);
11338 gpdelay
= reg_needs_delay (mips_gp_register
);
11339 if (expr1
.X_add_number
== 0 && breg
== 0
11340 && (call
|| tempreg
== PIC_CALL_REG
))
11342 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11343 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11345 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11346 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11347 tempreg
, tempreg
, mips_gp_register
);
11348 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11349 tempreg
, lw_reloc_type
, tempreg
);
11350 if (expr1
.X_add_number
== 0)
11354 /* We're going to put in an addu instruction using
11355 tempreg, so we may as well insert the nop right
11360 else if (expr1
.X_add_number
>= -0x8000
11361 && expr1
.X_add_number
< 0x8000)
11364 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11365 tempreg
, tempreg
, BFD_RELOC_LO16
);
11371 /* If we are going to add in a base register, and the
11372 target register and the base register are the same,
11373 then we are using AT as a temporary register. Since
11374 we want to load the constant into AT, we add our
11375 current AT (from the global offset table) and the
11376 register into the register now, and pretend we were
11377 not using a base register. */
11382 gas_assert (tempreg
== AT
);
11384 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11389 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11390 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11394 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11399 /* This is needed because this instruction uses $gp, but
11400 the first instruction on the main stream does not. */
11401 macro_build (NULL
, "nop", "");
11404 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11405 local_reloc_type
, mips_gp_register
);
11406 if (expr1
.X_add_number
>= -0x8000
11407 && expr1
.X_add_number
< 0x8000)
11410 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11411 tempreg
, tempreg
, BFD_RELOC_LO16
);
11412 /* FIXME: If add_number is 0, and there was no base
11413 register, the external symbol case ended with a load,
11414 so if the symbol turns out to not be external, and
11415 the next instruction uses tempreg, an unnecessary nop
11416 will be inserted. */
11422 /* We must add in the base register now, as in the
11423 external symbol case. */
11424 gas_assert (tempreg
== AT
);
11426 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11429 /* We set breg to 0 because we have arranged to add
11430 it in in both cases. */
11434 macro_build_lui (&expr1
, AT
);
11435 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11436 AT
, AT
, BFD_RELOC_LO16
);
11437 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11438 tempreg
, tempreg
, AT
);
11443 else if (mips_big_got
&& HAVE_NEWABI
)
11445 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11446 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11447 int add_breg_early
= 0;
11449 /* This is the large GOT case. If this is a reference to an
11450 external symbol, and there is no constant, we want
11451 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11452 add $tempreg,$tempreg,$gp
11453 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11454 or for lca or if tempreg is PIC_CALL_REG
11455 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11456 add $tempreg,$tempreg,$gp
11457 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11459 If we have a small constant, and this is a reference to
11460 an external symbol, we want
11461 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11462 add $tempreg,$tempreg,$gp
11463 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11464 addi $tempreg,$tempreg,<constant>
11466 If we have a large constant, and this is a reference to
11467 an external symbol, we want
11468 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11469 addu $tempreg,$tempreg,$gp
11470 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11471 lui $at,<hiconstant>
11472 addi $at,$at,<loconstant>
11473 add $tempreg,$tempreg,$at
11475 If we have NewABI, and we know it's a local symbol, we want
11476 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11477 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11478 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11480 relax_start (offset_expr
.X_add_symbol
);
11482 expr1
.X_add_number
= offset_expr
.X_add_number
;
11483 offset_expr
.X_add_number
= 0;
11485 if (expr1
.X_add_number
== 0 && breg
== 0
11486 && (call
|| tempreg
== PIC_CALL_REG
))
11488 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11489 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11491 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11492 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11493 tempreg
, tempreg
, mips_gp_register
);
11494 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11495 tempreg
, lw_reloc_type
, tempreg
);
11497 if (expr1
.X_add_number
== 0)
11499 else if (expr1
.X_add_number
>= -0x8000
11500 && expr1
.X_add_number
< 0x8000)
11502 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11503 tempreg
, tempreg
, BFD_RELOC_LO16
);
11505 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11509 /* If we are going to add in a base register, and the
11510 target register and the base register are the same,
11511 then we are using AT as a temporary register. Since
11512 we want to load the constant into AT, we add our
11513 current AT (from the global offset table) and the
11514 register into the register now, and pretend we were
11515 not using a base register. */
11520 gas_assert (tempreg
== AT
);
11521 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11524 add_breg_early
= 1;
11527 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11528 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11533 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11536 offset_expr
.X_add_number
= expr1
.X_add_number
;
11537 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11538 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11539 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11540 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11541 if (add_breg_early
)
11543 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11544 op
[0], tempreg
, breg
);
11554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11558 gas_assert (!mips_opts
.micromips
);
11559 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11563 gas_assert (!mips_opts
.micromips
);
11564 macro_build (NULL
, "c2", "C", 0x02);
11568 gas_assert (!mips_opts
.micromips
);
11569 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11573 gas_assert (!mips_opts
.micromips
);
11574 macro_build (NULL
, "c2", "C", 3);
11578 gas_assert (!mips_opts
.micromips
);
11579 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11583 /* The j instruction may not be used in PIC code, since it
11584 requires an absolute address. We convert it to a b
11586 if (mips_pic
== NO_PIC
)
11587 macro_build (&offset_expr
, "j", "a");
11589 macro_build (&offset_expr
, "b", "p");
11592 /* The jal instructions must be handled as macros because when
11593 generating PIC code they expand to multi-instruction
11594 sequences. Normally they are simple instructions. */
11598 /* Fall through. */
11600 gas_assert (mips_opts
.micromips
);
11601 if (mips_opts
.insn32
)
11603 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11611 /* Fall through. */
11614 if (mips_pic
== NO_PIC
)
11616 s
= jals
? "jalrs" : "jalr";
11617 if (mips_opts
.micromips
11618 && !mips_opts
.insn32
11620 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11621 macro_build (NULL
, s
, "mj", op
[1]);
11623 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11627 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11628 && mips_cprestore_offset
>= 0);
11630 if (op
[1] != PIC_CALL_REG
)
11631 as_warn (_("MIPS PIC call to register other than $25"));
11633 s
= ((mips_opts
.micromips
11634 && !mips_opts
.insn32
11635 && (!mips_opts
.noreorder
|| cprestore
))
11636 ? "jalrs" : "jalr");
11637 if (mips_opts
.micromips
11638 && !mips_opts
.insn32
11640 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11641 macro_build (NULL
, s
, "mj", op
[1]);
11643 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11644 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11646 if (mips_cprestore_offset
< 0)
11647 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11650 if (!mips_frame_reg_valid
)
11652 as_warn (_("no .frame pseudo-op used in PIC code"));
11653 /* Quiet this warning. */
11654 mips_frame_reg_valid
= 1;
11656 if (!mips_cprestore_valid
)
11658 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11659 /* Quiet this warning. */
11660 mips_cprestore_valid
= 1;
11662 if (mips_opts
.noreorder
)
11663 macro_build (NULL
, "nop", "");
11664 expr1
.X_add_number
= mips_cprestore_offset
;
11665 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11668 HAVE_64BIT_ADDRESSES
);
11676 gas_assert (mips_opts
.micromips
);
11677 if (mips_opts
.insn32
)
11679 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11683 /* Fall through. */
11685 if (mips_pic
== NO_PIC
)
11686 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11687 else if (mips_pic
== SVR4_PIC
)
11689 /* If this is a reference to an external symbol, and we are
11690 using a small GOT, we want
11691 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11695 lw $gp,cprestore($sp)
11696 The cprestore value is set using the .cprestore
11697 pseudo-op. If we are using a big GOT, we want
11698 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11700 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11704 lw $gp,cprestore($sp)
11705 If the symbol is not external, we want
11706 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11708 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11711 lw $gp,cprestore($sp)
11713 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11714 sequences above, minus nops, unless the symbol is local,
11715 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11721 relax_start (offset_expr
.X_add_symbol
);
11722 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11723 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11726 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11727 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11733 relax_start (offset_expr
.X_add_symbol
);
11734 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11735 BFD_RELOC_MIPS_CALL_HI16
);
11736 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11737 PIC_CALL_REG
, mips_gp_register
);
11738 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11739 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11742 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11743 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11745 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11746 PIC_CALL_REG
, PIC_CALL_REG
,
11747 BFD_RELOC_MIPS_GOT_OFST
);
11751 macro_build_jalr (&offset_expr
, 0);
11755 relax_start (offset_expr
.X_add_symbol
);
11758 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11759 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11768 gpdelay
= reg_needs_delay (mips_gp_register
);
11769 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11770 BFD_RELOC_MIPS_CALL_HI16
);
11771 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11772 PIC_CALL_REG
, mips_gp_register
);
11773 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11774 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11779 macro_build (NULL
, "nop", "");
11781 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11782 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11785 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11786 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11788 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11790 if (mips_cprestore_offset
< 0)
11791 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11794 if (!mips_frame_reg_valid
)
11796 as_warn (_("no .frame pseudo-op used in PIC code"));
11797 /* Quiet this warning. */
11798 mips_frame_reg_valid
= 1;
11800 if (!mips_cprestore_valid
)
11802 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11803 /* Quiet this warning. */
11804 mips_cprestore_valid
= 1;
11806 if (mips_opts
.noreorder
)
11807 macro_build (NULL
, "nop", "");
11808 expr1
.X_add_number
= mips_cprestore_offset
;
11809 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11812 HAVE_64BIT_ADDRESSES
);
11816 else if (mips_pic
== VXWORKS_PIC
)
11817 as_bad (_("non-PIC jump used in PIC library"));
11924 gas_assert (!mips_opts
.micromips
);
11927 /* Itbl support may require additional care here. */
11933 /* Itbl support may require additional care here. */
11939 offbits
= (mips_opts
.micromips
? 12
11940 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11942 /* Itbl support may require additional care here. */
11946 gas_assert (!mips_opts
.micromips
);
11949 /* Itbl support may require additional care here. */
11955 offbits
= (mips_opts
.micromips
? 12 : 16);
11960 offbits
= (mips_opts
.micromips
? 12 : 16);
11965 /* Itbl support may require additional care here. */
11971 offbits
= (mips_opts
.micromips
? 12
11972 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11974 /* Itbl support may require additional care here. */
11980 /* Itbl support may require additional care here. */
11986 /* Itbl support may require additional care here. */
11992 offbits
= (mips_opts
.micromips
? 12 : 16);
11997 offbits
= (mips_opts
.micromips
? 12 : 16);
12002 offbits
= (mips_opts
.micromips
? 12
12003 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12009 offbits
= (mips_opts
.micromips
? 12
12010 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12016 offbits
= (mips_opts
.micromips
? 12 : 16);
12019 gas_assert (mips_opts
.micromips
);
12026 gas_assert (mips_opts
.micromips
);
12035 s
= ip
->insn_mo
->name
;
12041 gas_assert (mips_opts
.micromips
);
12047 gas_assert (mips_opts
.micromips
);
12054 /* Try to use one the the load registers to compute the base address.
12055 We don't want to use $0 as tempreg. */
12058 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12059 || (op
[1] == ZERO
&& op
[3] == op
[0])
12060 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12062 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12069 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12072 tempreg
= op
[0] + lp
;
12089 gas_assert (!mips_opts
.micromips
);
12092 /* Itbl support may require additional care here. */
12098 /* Itbl support may require additional care here. */
12104 offbits
= (mips_opts
.micromips
? 12
12105 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12107 /* Itbl support may require additional care here. */
12111 gas_assert (!mips_opts
.micromips
);
12114 /* Itbl support may require additional care here. */
12120 offbits
= (mips_opts
.micromips
? 12 : 16);
12125 offbits
= (mips_opts
.micromips
? 12 : 16);
12130 offbits
= (mips_opts
.micromips
? 12
12131 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12137 offbits
= (mips_opts
.micromips
? 12
12138 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12144 s
= ip
->insn_mo
->name
;
12151 fmt
= (mips_opts
.micromips
? "k,~(b)"
12152 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12154 offbits
= (mips_opts
.micromips
? 12
12155 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12165 fmt
= (mips_opts
.micromips
? "k,~(b)"
12166 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12168 offbits
= (mips_opts
.micromips
? 12
12169 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12181 /* Itbl support may require additional care here. */
12186 offbits
= (mips_opts
.micromips
? 12
12187 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12189 /* Itbl support may require additional care here. */
12195 /* Itbl support may require additional care here. */
12199 gas_assert (!mips_opts
.micromips
);
12202 /* Itbl support may require additional care here. */
12208 offbits
= (mips_opts
.micromips
? 12 : 16);
12213 offbits
= (mips_opts
.micromips
? 12 : 16);
12216 gas_assert (mips_opts
.micromips
);
12222 gas_assert (mips_opts
.micromips
);
12228 gas_assert (mips_opts
.micromips
);
12234 gas_assert (mips_opts
.micromips
);
12242 breg
= ll_sc_paired
? op
[3] : op
[2];
12243 if (small_offset_p (0, align
, 16))
12245 /* The first case exists for M_LD_AB and M_SD_AB, which are
12246 macros for o32 but which should act like normal instructions
12249 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12250 offset_reloc
[1], offset_reloc
[2], breg
);
12251 else if (small_offset_p (0, align
, offbits
))
12256 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12258 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12261 macro_build (NULL
, s
, fmt
, op
[0],
12262 (int) offset_expr
.X_add_number
, breg
);
12268 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12269 tempreg
, breg
, -1, offset_reloc
[0],
12270 offset_reloc
[1], offset_reloc
[2]);
12274 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12276 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12279 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12287 if (offset_expr
.X_op
!= O_constant
12288 && offset_expr
.X_op
!= O_symbol
)
12290 as_bad (_("expression too complex"));
12291 offset_expr
.X_op
= O_constant
;
12294 if (HAVE_32BIT_ADDRESSES
12295 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12299 sprintf_vma (value
, offset_expr
.X_add_number
);
12300 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12303 /* A constant expression in PIC code can be handled just as it
12304 is in non PIC code. */
12305 if (offset_expr
.X_op
== O_constant
)
12307 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12308 offbits
== 0 ? 16 : offbits
);
12309 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12311 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12313 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12314 tempreg
, tempreg
, breg
);
12317 if (offset_expr
.X_add_number
!= 0)
12318 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12319 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12321 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12323 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12325 else if (offbits
== 16)
12326 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12328 macro_build (NULL
, s
, fmt
, op
[0],
12329 (int) offset_expr
.X_add_number
, tempreg
);
12331 else if (offbits
!= 16)
12333 /* The offset field is too narrow to be used for a low-part
12334 relocation, so load the whole address into the auxiliary
12336 load_address (tempreg
, &offset_expr
, &used_at
);
12338 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12339 tempreg
, tempreg
, breg
);
12343 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12345 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12348 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12350 else if (mips_pic
== NO_PIC
)
12352 /* If this is a reference to a GP relative symbol, and there
12353 is no base register, we want
12354 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12355 Otherwise, if there is no base register, we want
12356 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12357 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12358 If we have a constant, we need two instructions anyhow,
12359 so we always use the latter form.
12361 If we have a base register, and this is a reference to a
12362 GP relative symbol, we want
12363 addu $tempreg,$breg,$gp
12364 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12366 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12367 addu $tempreg,$tempreg,$breg
12368 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12369 With a constant we always use the latter case.
12371 With 64bit address space and no base register and $at usable,
12373 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12374 lui $at,<sym> (BFD_RELOC_HI16_S)
12375 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12378 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12379 If we have a base register, we want
12380 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12381 lui $at,<sym> (BFD_RELOC_HI16_S)
12382 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12386 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12388 Without $at we can't generate the optimal path for superscalar
12389 processors here since this would require two temporary registers.
12390 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12391 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12393 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12395 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12396 If we have a base register, we want
12397 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12398 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12400 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12402 daddu $tempreg,$tempreg,$breg
12403 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12405 For GP relative symbols in 64bit address space we can use
12406 the same sequence as in 32bit address space. */
12407 if (HAVE_64BIT_SYMBOLS
)
12409 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12410 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12412 relax_start (offset_expr
.X_add_symbol
);
12415 macro_build (&offset_expr
, s
, fmt
, op
[0],
12416 BFD_RELOC_GPREL16
, mips_gp_register
);
12420 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12421 tempreg
, breg
, mips_gp_register
);
12422 macro_build (&offset_expr
, s
, fmt
, op
[0],
12423 BFD_RELOC_GPREL16
, tempreg
);
12428 if (used_at
== 0 && mips_opts
.at
)
12430 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12431 BFD_RELOC_MIPS_HIGHEST
);
12432 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12434 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12435 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12437 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12438 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12439 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12440 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12446 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12447 BFD_RELOC_MIPS_HIGHEST
);
12448 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12449 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12450 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12451 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12452 tempreg
, BFD_RELOC_HI16_S
);
12453 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12455 macro_build (NULL
, "daddu", "d,v,t",
12456 tempreg
, tempreg
, breg
);
12457 macro_build (&offset_expr
, s
, fmt
, op
[0],
12458 BFD_RELOC_LO16
, tempreg
);
12461 if (mips_relax
.sequence
)
12468 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12469 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12471 relax_start (offset_expr
.X_add_symbol
);
12472 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12476 macro_build_lui (&offset_expr
, tempreg
);
12477 macro_build (&offset_expr
, s
, fmt
, op
[0],
12478 BFD_RELOC_LO16
, tempreg
);
12479 if (mips_relax
.sequence
)
12484 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12485 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12487 relax_start (offset_expr
.X_add_symbol
);
12488 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12489 tempreg
, breg
, mips_gp_register
);
12490 macro_build (&offset_expr
, s
, fmt
, op
[0],
12491 BFD_RELOC_GPREL16
, tempreg
);
12494 macro_build_lui (&offset_expr
, tempreg
);
12495 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12496 tempreg
, tempreg
, breg
);
12497 macro_build (&offset_expr
, s
, fmt
, op
[0],
12498 BFD_RELOC_LO16
, tempreg
);
12499 if (mips_relax
.sequence
)
12503 else if (!mips_big_got
)
12505 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12507 /* If this is a reference to an external symbol, we want
12508 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12510 <op> op[0],0($tempreg)
12512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12514 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12515 <op> op[0],0($tempreg)
12517 For NewABI, we want
12518 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12519 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12521 If there is a base register, we add it to $tempreg before
12522 the <op>. If there is a constant, we stick it in the
12523 <op> instruction. We don't handle constants larger than
12524 16 bits, because we have no way to load the upper 16 bits
12525 (actually, we could handle them for the subset of cases
12526 in which we are not using $at). */
12527 gas_assert (offset_expr
.X_op
== O_symbol
);
12530 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12531 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12533 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12534 tempreg
, tempreg
, breg
);
12535 macro_build (&offset_expr
, s
, fmt
, op
[0],
12536 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12539 expr1
.X_add_number
= offset_expr
.X_add_number
;
12540 offset_expr
.X_add_number
= 0;
12541 if (expr1
.X_add_number
< -0x8000
12542 || expr1
.X_add_number
>= 0x8000)
12543 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12544 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12545 lw_reloc_type
, mips_gp_register
);
12547 relax_start (offset_expr
.X_add_symbol
);
12549 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12550 tempreg
, BFD_RELOC_LO16
);
12553 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12554 tempreg
, tempreg
, breg
);
12555 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12557 else if (mips_big_got
&& !HAVE_NEWABI
)
12561 /* If this is a reference to an external symbol, we want
12562 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12563 addu $tempreg,$tempreg,$gp
12564 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12565 <op> op[0],0($tempreg)
12567 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12569 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12570 <op> op[0],0($tempreg)
12571 If there is a base register, we add it to $tempreg before
12572 the <op>. If there is a constant, we stick it in the
12573 <op> instruction. We don't handle constants larger than
12574 16 bits, because we have no way to load the upper 16 bits
12575 (actually, we could handle them for the subset of cases
12576 in which we are not using $at). */
12577 gas_assert (offset_expr
.X_op
== O_symbol
);
12578 expr1
.X_add_number
= offset_expr
.X_add_number
;
12579 offset_expr
.X_add_number
= 0;
12580 if (expr1
.X_add_number
< -0x8000
12581 || expr1
.X_add_number
>= 0x8000)
12582 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12583 gpdelay
= reg_needs_delay (mips_gp_register
);
12584 relax_start (offset_expr
.X_add_symbol
);
12585 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12586 BFD_RELOC_MIPS_GOT_HI16
);
12587 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12589 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12590 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12593 macro_build (NULL
, "nop", "");
12594 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12595 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12597 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12598 tempreg
, BFD_RELOC_LO16
);
12602 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12603 tempreg
, tempreg
, breg
);
12604 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12606 else if (mips_big_got
&& HAVE_NEWABI
)
12608 /* If this is a reference to an external symbol, we want
12609 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12610 add $tempreg,$tempreg,$gp
12611 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12612 <op> op[0],<ofst>($tempreg)
12613 Otherwise, for local symbols, we want:
12614 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12615 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12616 gas_assert (offset_expr
.X_op
== O_symbol
);
12617 expr1
.X_add_number
= offset_expr
.X_add_number
;
12618 offset_expr
.X_add_number
= 0;
12619 if (expr1
.X_add_number
< -0x8000
12620 || expr1
.X_add_number
>= 0x8000)
12621 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12622 relax_start (offset_expr
.X_add_symbol
);
12623 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12624 BFD_RELOC_MIPS_GOT_HI16
);
12625 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12627 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12628 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12631 tempreg
, tempreg
, breg
);
12632 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12635 offset_expr
.X_add_number
= expr1
.X_add_number
;
12636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12637 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12639 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12640 tempreg
, tempreg
, breg
);
12641 macro_build (&offset_expr
, s
, fmt
, op
[0],
12642 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12651 gas_assert (mips_opts
.micromips
);
12652 gas_assert (mips_opts
.insn32
);
12653 start_noreorder ();
12654 macro_build (NULL
, "jr", "s", RA
);
12655 expr1
.X_add_number
= op
[0] << 2;
12656 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12661 gas_assert (mips_opts
.micromips
);
12662 gas_assert (mips_opts
.insn32
);
12663 macro_build (NULL
, "jr", "s", op
[0]);
12664 if (mips_opts
.noreorder
)
12665 macro_build (NULL
, "nop", "");
12670 load_register (op
[0], &imm_expr
, 0);
12674 load_register (op
[0], &imm_expr
, 1);
12678 if (imm_expr
.X_op
== O_constant
)
12681 load_register (AT
, &imm_expr
, 0);
12682 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12687 gas_assert (imm_expr
.X_op
== O_absent
12688 && offset_expr
.X_op
== O_symbol
12689 && strcmp (segment_name (S_GET_SEGMENT
12690 (offset_expr
.X_add_symbol
)),
12692 && offset_expr
.X_add_number
== 0);
12693 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12694 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12699 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12700 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12701 order 32 bits of the value and the low order 32 bits are either
12702 zero or in OFFSET_EXPR. */
12703 if (imm_expr
.X_op
== O_constant
)
12705 if (GPR_SIZE
== 64)
12706 load_register (op
[0], &imm_expr
, 1);
12711 if (target_big_endian
)
12723 load_register (hreg
, &imm_expr
, 0);
12726 if (offset_expr
.X_op
== O_absent
)
12727 move_register (lreg
, 0);
12730 gas_assert (offset_expr
.X_op
== O_constant
);
12731 load_register (lreg
, &offset_expr
, 0);
12737 gas_assert (imm_expr
.X_op
== O_absent
);
12739 /* We know that sym is in the .rdata section. First we get the
12740 upper 16 bits of the address. */
12741 if (mips_pic
== NO_PIC
)
12743 macro_build_lui (&offset_expr
, AT
);
12748 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12749 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12753 /* Now we load the register(s). */
12754 if (GPR_SIZE
== 64)
12757 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12758 BFD_RELOC_LO16
, AT
);
12763 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12764 BFD_RELOC_LO16
, AT
);
12767 /* FIXME: How in the world do we deal with the possible
12769 offset_expr
.X_add_number
+= 4;
12770 macro_build (&offset_expr
, "lw", "t,o(b)",
12771 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12777 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12778 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12779 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12780 the value and the low order 32 bits are either zero or in
12782 if (imm_expr
.X_op
== O_constant
)
12785 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12786 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12787 && imm_expr
.X_add_number
!= 0)
12791 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12793 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12794 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12797 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12799 if (FPR_SIZE
!= 32)
12800 as_bad (_("Unable to generate `%s' compliant code "
12802 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12804 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12806 if (offset_expr
.X_op
== O_absent
)
12807 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12810 gas_assert (offset_expr
.X_op
== O_constant
);
12811 load_register (AT
, &offset_expr
, 0);
12812 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12814 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12816 if (imm_expr
.X_add_number
!= 0)
12820 load_register (AT
, &imm_expr
, 0);
12822 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12828 gas_assert (imm_expr
.X_op
== O_absent
12829 && offset_expr
.X_op
== O_symbol
12830 && offset_expr
.X_add_number
== 0);
12831 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12832 if (strcmp (s
, ".lit8") == 0)
12834 op
[2] = mips_gp_register
;
12835 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12836 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12837 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12841 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12843 if (mips_pic
!= NO_PIC
)
12844 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12845 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12848 /* FIXME: This won't work for a 64 bit address. */
12849 macro_build_lui (&offset_expr
, AT
);
12853 offset_reloc
[0] = BFD_RELOC_LO16
;
12854 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12855 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12858 /* Fall through. */
12861 /* The MIPS assembler seems to check for X_add_number not
12862 being double aligned and generating:
12865 addiu at,at,%lo(foo+1)
12868 But, the resulting address is the same after relocation so why
12869 generate the extra instruction? */
12870 /* Itbl support may require additional care here. */
12873 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12882 gas_assert (!mips_opts
.micromips
);
12883 /* Itbl support may require additional care here. */
12886 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12906 if (GPR_SIZE
== 64)
12916 if (GPR_SIZE
== 64)
12924 /* Even on a big endian machine $fn comes before $fn+1. We have
12925 to adjust when loading from memory. We set coproc if we must
12926 load $fn+1 first. */
12927 /* Itbl support may require additional care here. */
12928 if (!target_big_endian
)
12932 if (small_offset_p (0, align
, 16))
12935 if (!small_offset_p (4, align
, 16))
12937 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12938 -1, offset_reloc
[0], offset_reloc
[1],
12940 expr1
.X_add_number
= 0;
12944 offset_reloc
[0] = BFD_RELOC_LO16
;
12945 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12946 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12948 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12950 ep
->X_add_number
+= 4;
12951 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12952 offset_reloc
[1], offset_reloc
[2], breg
);
12953 ep
->X_add_number
-= 4;
12954 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12955 offset_reloc
[1], offset_reloc
[2], breg
);
12959 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12960 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12962 ep
->X_add_number
+= 4;
12963 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12964 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12970 if (offset_expr
.X_op
!= O_symbol
12971 && offset_expr
.X_op
!= O_constant
)
12973 as_bad (_("expression too complex"));
12974 offset_expr
.X_op
= O_constant
;
12977 if (HAVE_32BIT_ADDRESSES
12978 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12982 sprintf_vma (value
, offset_expr
.X_add_number
);
12983 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12986 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12988 /* If this is a reference to a GP relative symbol, we want
12989 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12990 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12991 If we have a base register, we use this
12993 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12994 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12995 If this is not a GP relative symbol, we want
12996 lui $at,<sym> (BFD_RELOC_HI16_S)
12997 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12998 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12999 If there is a base register, we add it to $at after the
13000 lui instruction. If there is a constant, we always use
13002 if (offset_expr
.X_op
== O_symbol
13003 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13004 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13006 relax_start (offset_expr
.X_add_symbol
);
13009 tempreg
= mips_gp_register
;
13013 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13014 AT
, breg
, mips_gp_register
);
13019 /* Itbl support may require additional care here. */
13020 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13021 BFD_RELOC_GPREL16
, tempreg
);
13022 offset_expr
.X_add_number
+= 4;
13024 /* Set mips_optimize to 2 to avoid inserting an
13026 hold_mips_optimize
= mips_optimize
;
13028 /* Itbl support may require additional care here. */
13029 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13030 BFD_RELOC_GPREL16
, tempreg
);
13031 mips_optimize
= hold_mips_optimize
;
13035 offset_expr
.X_add_number
-= 4;
13038 if (offset_high_part (offset_expr
.X_add_number
, 16)
13039 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13041 load_address (AT
, &offset_expr
, &used_at
);
13042 offset_expr
.X_op
= O_constant
;
13043 offset_expr
.X_add_number
= 0;
13046 macro_build_lui (&offset_expr
, AT
);
13048 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13049 /* Itbl support may require additional care here. */
13050 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13051 BFD_RELOC_LO16
, AT
);
13052 /* FIXME: How do we handle overflow here? */
13053 offset_expr
.X_add_number
+= 4;
13054 /* Itbl support may require additional care here. */
13055 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13056 BFD_RELOC_LO16
, AT
);
13057 if (mips_relax
.sequence
)
13060 else if (!mips_big_got
)
13062 /* If this is a reference to an external symbol, we want
13063 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13066 <op> op[0]+1,4($at)
13068 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13070 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13071 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13072 If there is a base register we add it to $at before the
13073 lwc1 instructions. If there is a constant we include it
13074 in the lwc1 instructions. */
13076 expr1
.X_add_number
= offset_expr
.X_add_number
;
13077 if (expr1
.X_add_number
< -0x8000
13078 || expr1
.X_add_number
>= 0x8000 - 4)
13079 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13080 load_got_offset (AT
, &offset_expr
);
13083 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13085 /* Set mips_optimize to 2 to avoid inserting an undesired
13087 hold_mips_optimize
= mips_optimize
;
13090 /* Itbl support may require additional care here. */
13091 relax_start (offset_expr
.X_add_symbol
);
13092 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13093 BFD_RELOC_LO16
, AT
);
13094 expr1
.X_add_number
+= 4;
13095 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13096 BFD_RELOC_LO16
, AT
);
13098 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13099 BFD_RELOC_LO16
, AT
);
13100 offset_expr
.X_add_number
+= 4;
13101 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13102 BFD_RELOC_LO16
, AT
);
13105 mips_optimize
= hold_mips_optimize
;
13107 else if (mips_big_got
)
13111 /* If this is a reference to an external symbol, we want
13112 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13114 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13117 <op> op[0]+1,4($at)
13119 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13121 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13122 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13123 If there is a base register we add it to $at before the
13124 lwc1 instructions. If there is a constant we include it
13125 in the lwc1 instructions. */
13127 expr1
.X_add_number
= offset_expr
.X_add_number
;
13128 offset_expr
.X_add_number
= 0;
13129 if (expr1
.X_add_number
< -0x8000
13130 || expr1
.X_add_number
>= 0x8000 - 4)
13131 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13132 gpdelay
= reg_needs_delay (mips_gp_register
);
13133 relax_start (offset_expr
.X_add_symbol
);
13134 macro_build (&offset_expr
, "lui", LUI_FMT
,
13135 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13136 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13137 AT
, AT
, mips_gp_register
);
13138 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13139 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13142 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13143 /* Itbl support may require additional care here. */
13144 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13145 BFD_RELOC_LO16
, AT
);
13146 expr1
.X_add_number
+= 4;
13148 /* Set mips_optimize to 2 to avoid inserting an undesired
13150 hold_mips_optimize
= mips_optimize
;
13152 /* Itbl support may require additional care here. */
13153 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13154 BFD_RELOC_LO16
, AT
);
13155 mips_optimize
= hold_mips_optimize
;
13156 expr1
.X_add_number
-= 4;
13159 offset_expr
.X_add_number
= expr1
.X_add_number
;
13161 macro_build (NULL
, "nop", "");
13162 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13163 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13167 /* Itbl support may require additional care here. */
13168 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13169 BFD_RELOC_LO16
, AT
);
13170 offset_expr
.X_add_number
+= 4;
13172 /* Set mips_optimize to 2 to avoid inserting an undesired
13174 hold_mips_optimize
= mips_optimize
;
13176 /* Itbl support may require additional care here. */
13177 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13178 BFD_RELOC_LO16
, AT
);
13179 mips_optimize
= hold_mips_optimize
;
13193 gas_assert (!mips_opts
.micromips
);
13198 /* New code added to support COPZ instructions.
13199 This code builds table entries out of the macros in mip_opcodes.
13200 R4000 uses interlocks to handle coproc delays.
13201 Other chips (like the R3000) require nops to be inserted for delays.
13203 FIXME: Currently, we require that the user handle delays.
13204 In order to fill delay slots for non-interlocked chips,
13205 we must have a way to specify delays based on the coprocessor.
13206 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13207 What are the side-effects of the cop instruction?
13208 What cache support might we have and what are its effects?
13209 Both coprocessor & memory require delays. how long???
13210 What registers are read/set/modified?
13212 If an itbl is provided to interpret cop instructions,
13213 this knowledge can be encoded in the itbl spec. */
13227 gas_assert (!mips_opts
.micromips
);
13228 /* For now we just do C (same as Cz). The parameter will be
13229 stored in insn_opcode by mips_ip. */
13230 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13234 move_register (op
[0], op
[1]);
13238 gas_assert (mips_opts
.micromips
);
13239 gas_assert (mips_opts
.insn32
);
13240 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13241 micromips_to_32_reg_m_map
[op
[1]]);
13242 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13243 micromips_to_32_reg_n_map
[op
[2]]);
13248 /* Fall through. */
13250 if (mips_opts
.arch
== CPU_R5900
)
13251 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13255 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13256 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13262 /* Fall through. */
13264 /* The MIPS assembler some times generates shifts and adds. I'm
13265 not trying to be that fancy. GCC should do this for us
13268 load_register (AT
, &imm_expr
, dbl
);
13269 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13270 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13275 /* Fall through. */
13282 /* Fall through. */
13285 start_noreorder ();
13288 load_register (AT
, &imm_expr
, dbl
);
13289 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13290 op
[1], imm
? AT
: op
[2]);
13291 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13292 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13293 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13295 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13298 if (mips_opts
.micromips
)
13299 micromips_label_expr (&label_expr
);
13301 label_expr
.X_add_number
= 8;
13302 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13303 macro_build (NULL
, "nop", "");
13304 macro_build (NULL
, "break", BRK_FMT
, 6);
13305 if (mips_opts
.micromips
)
13306 micromips_add_label ();
13309 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13314 /* Fall through. */
13321 /* Fall through. */
13324 start_noreorder ();
13327 load_register (AT
, &imm_expr
, dbl
);
13328 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13329 op
[1], imm
? AT
: op
[2]);
13330 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13331 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13333 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13336 if (mips_opts
.micromips
)
13337 micromips_label_expr (&label_expr
);
13339 label_expr
.X_add_number
= 8;
13340 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13341 macro_build (NULL
, "nop", "");
13342 macro_build (NULL
, "break", BRK_FMT
, 6);
13343 if (mips_opts
.micromips
)
13344 micromips_add_label ();
13350 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13352 if (op
[0] == op
[1])
13359 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13360 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13364 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13365 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13366 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13367 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13371 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13373 if (op
[0] == op
[1])
13380 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13381 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13385 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13386 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13387 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13388 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13397 rot
= imm_expr
.X_add_number
& 0x3f;
13398 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13400 rot
= (64 - rot
) & 0x3f;
13402 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13404 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13409 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13412 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13413 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13416 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13417 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13418 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13426 rot
= imm_expr
.X_add_number
& 0x1f;
13427 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13429 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13430 (32 - rot
) & 0x1f);
13435 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13439 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13440 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13441 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13446 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13448 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13452 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13453 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13454 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13455 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13459 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13461 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13465 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13466 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13467 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13468 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13477 rot
= imm_expr
.X_add_number
& 0x3f;
13478 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13481 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13483 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13488 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13491 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13492 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13495 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13496 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13497 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13505 rot
= imm_expr
.X_add_number
& 0x1f;
13506 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13508 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13513 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13517 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13518 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13519 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13525 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13526 else if (op
[2] == 0)
13527 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13530 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13531 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13536 if (imm_expr
.X_add_number
== 0)
13538 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13543 as_warn (_("instruction %s: result is always false"),
13544 ip
->insn_mo
->name
);
13545 move_register (op
[0], 0);
13548 if (CPU_HAS_SEQ (mips_opts
.arch
)
13549 && -512 <= imm_expr
.X_add_number
13550 && imm_expr
.X_add_number
< 512)
13552 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13553 (int) imm_expr
.X_add_number
);
13556 if (imm_expr
.X_add_number
>= 0
13557 && imm_expr
.X_add_number
< 0x10000)
13558 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13559 else if (imm_expr
.X_add_number
> -0x8000
13560 && imm_expr
.X_add_number
< 0)
13562 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13563 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13564 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13566 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13569 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13570 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13575 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13576 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13579 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13582 case M_SGE
: /* X >= Y <==> not (X < Y) */
13588 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13589 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13592 case M_SGE_I
: /* X >= I <==> not (X < I). */
13594 if (imm_expr
.X_add_number
>= -0x8000
13595 && imm_expr
.X_add_number
< 0x8000)
13596 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13597 op
[0], op
[1], BFD_RELOC_LO16
);
13600 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13601 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13605 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13608 case M_SGT
: /* X > Y <==> Y < X. */
13614 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13617 case M_SGT_I
: /* X > I <==> I < X. */
13624 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13625 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13628 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13634 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13635 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13638 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13645 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13646 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13647 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13651 if (imm_expr
.X_add_number
>= -0x8000
13652 && imm_expr
.X_add_number
< 0x8000)
13654 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13659 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13660 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13664 if (imm_expr
.X_add_number
>= -0x8000
13665 && imm_expr
.X_add_number
< 0x8000)
13667 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13672 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13673 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13678 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13679 else if (op
[2] == 0)
13680 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13683 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13684 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13689 if (imm_expr
.X_add_number
== 0)
13691 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13696 as_warn (_("instruction %s: result is always true"),
13697 ip
->insn_mo
->name
);
13698 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13699 op
[0], 0, BFD_RELOC_LO16
);
13702 if (CPU_HAS_SEQ (mips_opts
.arch
)
13703 && -512 <= imm_expr
.X_add_number
13704 && imm_expr
.X_add_number
< 512)
13706 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13707 (int) imm_expr
.X_add_number
);
13710 if (imm_expr
.X_add_number
>= 0
13711 && imm_expr
.X_add_number
< 0x10000)
13713 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13716 else if (imm_expr
.X_add_number
> -0x8000
13717 && imm_expr
.X_add_number
< 0)
13719 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13720 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13721 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13723 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13726 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13727 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13732 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13733 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13736 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13742 if (ISA_IS_R6 (mips_opts
.isa
))
13754 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13756 if (imm_expr
.X_add_number
> -0x200
13757 && imm_expr
.X_add_number
<= 0x200
13758 && !ISA_IS_R6 (mips_opts
.isa
))
13760 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13761 (int) -imm_expr
.X_add_number
);
13770 if (imm_expr
.X_add_number
> -0x8000
13771 && imm_expr
.X_add_number
<= 0x8000)
13773 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13774 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13779 load_register (AT
, &imm_expr
, dbl
);
13780 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13802 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13803 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13808 gas_assert (!mips_opts
.micromips
);
13809 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13813 * Is the double cfc1 instruction a bug in the mips assembler;
13814 * or is there a reason for it?
13816 start_noreorder ();
13817 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13818 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13819 macro_build (NULL
, "nop", "");
13820 expr1
.X_add_number
= 3;
13821 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13822 expr1
.X_add_number
= 2;
13823 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13824 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13825 macro_build (NULL
, "nop", "");
13826 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13828 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13829 macro_build (NULL
, "nop", "");
13846 offbits
= (mips_opts
.micromips
? 12 : 16);
13852 offbits
= (mips_opts
.micromips
? 12 : 16);
13864 offbits
= (mips_opts
.micromips
? 12 : 16);
13871 offbits
= (mips_opts
.micromips
? 12 : 16);
13877 large_offset
= !small_offset_p (off
, align
, offbits
);
13879 expr1
.X_add_number
= 0;
13884 if (small_offset_p (0, align
, 16))
13885 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13886 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13889 load_address (tempreg
, ep
, &used_at
);
13891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13892 tempreg
, tempreg
, breg
);
13894 offset_reloc
[0] = BFD_RELOC_LO16
;
13895 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13896 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13901 else if (!ust
&& op
[0] == breg
)
13912 if (!target_big_endian
)
13913 ep
->X_add_number
+= off
;
13915 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13917 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13918 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13920 if (!target_big_endian
)
13921 ep
->X_add_number
-= off
;
13923 ep
->X_add_number
+= off
;
13925 macro_build (NULL
, s2
, "t,~(b)",
13926 tempreg
, (int) ep
->X_add_number
, breg
);
13928 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13929 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13931 /* If necessary, move the result in tempreg to the final destination. */
13932 if (!ust
&& op
[0] != tempreg
)
13934 /* Protect second load's delay slot. */
13936 move_register (op
[0], tempreg
);
13942 if (target_big_endian
== ust
)
13943 ep
->X_add_number
+= off
;
13944 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13945 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13946 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13948 /* For halfword transfers we need a temporary register to shuffle
13949 bytes. Unfortunately for M_USH_A we have none available before
13950 the next store as AT holds the base address. We deal with this
13951 case by clobbering TREG and then restoring it as with ULH. */
13952 tempreg
= ust
== large_offset
? op
[0] : AT
;
13954 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13956 if (target_big_endian
== ust
)
13957 ep
->X_add_number
-= off
;
13959 ep
->X_add_number
+= off
;
13960 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13961 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13963 /* For M_USH_A re-retrieve the LSB. */
13964 if (ust
&& large_offset
)
13966 if (target_big_endian
)
13967 ep
->X_add_number
+= off
;
13969 ep
->X_add_number
-= off
;
13970 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13971 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13973 /* For ULH and M_USH_A OR the LSB in. */
13974 if (!ust
|| large_offset
)
13976 tempreg
= !large_offset
? AT
: op
[0];
13977 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13978 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13983 /* FIXME: Check if this is one of the itbl macros, since they
13984 are added dynamically. */
13985 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13988 if (!mips_opts
.at
&& used_at
)
13989 as_bad (_("macro used $at after \".set noat\""));
13992 /* Implement macros in mips16 mode. */
13995 mips16_macro (struct mips_cl_insn
*ip
)
13997 const struct mips_operand_array
*operands
;
14002 const char *s
, *s2
, *s3
;
14003 unsigned int op
[MAX_OPERANDS
];
14006 mask
= ip
->insn_mo
->mask
;
14008 operands
= insn_operands (ip
);
14009 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14010 if (operands
->operand
[i
])
14011 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14015 expr1
.X_op
= O_constant
;
14016 expr1
.X_op_symbol
= NULL
;
14017 expr1
.X_add_symbol
= NULL
;
14018 expr1
.X_add_number
= 1;
14029 /* Fall through. */
14035 /* Fall through. */
14039 start_noreorder ();
14040 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14041 expr1
.X_add_number
= 2;
14042 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14043 macro_build (NULL
, "break", "6", 7);
14045 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14046 since that causes an overflow. We should do that as well,
14047 but I don't see how to do the comparisons without a temporary
14050 macro_build (NULL
, s
, "x", op
[0]);
14069 start_noreorder ();
14070 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14071 expr1
.X_add_number
= 2;
14072 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14073 macro_build (NULL
, "break", "6", 7);
14075 macro_build (NULL
, s2
, "x", op
[0]);
14080 /* Fall through. */
14082 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14083 macro_build (NULL
, "mflo", "x", op
[0]);
14091 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14092 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14096 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14097 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14101 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14102 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14124 goto do_reverse_branch
;
14128 goto do_reverse_branch
;
14140 goto do_reverse_branch
;
14151 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14152 macro_build (&offset_expr
, s2
, "p");
14179 goto do_addone_branch_i
;
14184 goto do_addone_branch_i
;
14199 goto do_addone_branch_i
;
14205 do_addone_branch_i
:
14206 ++imm_expr
.X_add_number
;
14209 macro_build (&imm_expr
, s
, s3
, op
[0]);
14210 macro_build (&offset_expr
, s2
, "p");
14214 expr1
.X_add_number
= 0;
14215 macro_build (&expr1
, "slti", "x,8", op
[1]);
14216 if (op
[0] != op
[1])
14217 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14218 expr1
.X_add_number
= 2;
14219 macro_build (&expr1
, "bteqz", "p");
14220 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14225 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14226 opcode bits in *OPCODE_EXTRA. */
14228 static struct mips_opcode
*
14229 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14230 ssize_t length
, unsigned int *opcode_extra
)
14232 char *name
, *dot
, *p
;
14233 unsigned int mask
, suffix
;
14235 struct mips_opcode
*insn
;
14237 /* Make a copy of the instruction so that we can fiddle with it. */
14238 name
= xstrndup (start
, length
);
14240 /* Look up the instruction as-is. */
14241 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14245 dot
= strchr (name
, '.');
14248 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14249 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14250 if (*p
== 0 && mask
!= 0)
14253 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14255 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14257 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14263 if (mips_opts
.micromips
)
14265 /* See if there's an instruction size override suffix,
14266 either `16' or `32', at the end of the mnemonic proper,
14267 that defines the operation, i.e. before the first `.'
14268 character if any. Strip it and retry. */
14269 opend
= dot
!= NULL
? dot
- name
: length
;
14270 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14272 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14278 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14279 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14282 forced_insn_length
= suffix
;
14294 /* Assemble an instruction into its binary format. If the instruction
14295 is a macro, set imm_expr and offset_expr to the values associated
14296 with "I" and "A" operands respectively. Otherwise store the value
14297 of the relocatable field (if any) in offset_expr. In both cases
14298 set offset_reloc to the relocation operators applied to offset_expr. */
14301 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14303 const struct mips_opcode
*first
, *past
;
14304 struct hash_control
*hash
;
14307 struct mips_operand_token
*tokens
;
14308 unsigned int opcode_extra
;
14310 if (mips_opts
.micromips
)
14312 hash
= micromips_op_hash
;
14313 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14318 past
= &mips_opcodes
[NUMOPCODES
];
14320 forced_insn_length
= 0;
14323 /* We first try to match an instruction up to a space or to the end. */
14324 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14327 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14330 set_insn_error (0, _("unrecognized opcode"));
14334 if (strcmp (first
->name
, "li.s") == 0)
14336 else if (strcmp (first
->name
, "li.d") == 0)
14340 tokens
= mips_parse_arguments (str
+ end
, format
);
14344 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14345 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14346 set_insn_error (0, _("invalid operands"));
14348 obstack_free (&mips_operand_tokens
, tokens
);
14351 /* As for mips_ip, but used when assembling MIPS16 code.
14352 Also set forced_insn_length to the resulting instruction size in
14353 bytes if the user explicitly requested a small or extended instruction. */
14356 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14359 struct mips_opcode
*first
;
14360 struct mips_operand_token
*tokens
;
14363 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14385 else if (*s
== 'e')
14392 else if (*s
++ == ' ')
14394 set_insn_error (0, _("unrecognized opcode"));
14397 forced_insn_length
= l
;
14400 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14405 set_insn_error (0, _("unrecognized opcode"));
14409 tokens
= mips_parse_arguments (s
, 0);
14413 if (!match_mips16_insns (insn
, first
, tokens
))
14414 set_insn_error (0, _("invalid operands"));
14416 obstack_free (&mips_operand_tokens
, tokens
);
14419 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14420 NBITS is the number of significant bits in VAL. */
14422 static unsigned long
14423 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14428 val
&= (1U << nbits
) - 1;
14429 if (nbits
== 16 || nbits
== 9)
14431 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14434 else if (nbits
== 15)
14436 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14439 else if (nbits
== 6)
14441 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14444 return (extval
<< 16) | val
;
14447 /* Like decode_mips16_operand, but require the operand to be defined and
14448 require it to be an integer. */
14450 static const struct mips_int_operand
*
14451 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14453 const struct mips_operand
*operand
;
14455 operand
= decode_mips16_operand (type
, extended_p
);
14456 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14458 return (const struct mips_int_operand
*) operand
;
14461 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14464 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14465 bfd_reloc_code_real_type reloc
, offsetT sval
)
14467 int min_val
, max_val
;
14469 min_val
= mips_int_operand_min (operand
);
14470 max_val
= mips_int_operand_max (operand
);
14471 if (reloc
!= BFD_RELOC_UNUSED
)
14474 sval
= SEXT_16BIT (sval
);
14479 return (sval
>= min_val
14481 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14484 /* Install immediate value VAL into MIPS16 instruction *INSN,
14485 extending it if necessary. The instruction in *INSN may
14486 already be extended.
14488 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14489 if none. In the former case, VAL is a 16-bit number with no
14490 defined signedness.
14492 TYPE is the type of the immediate field. USER_INSN_LENGTH
14493 is the length that the user requested, or 0 if none. */
14496 mips16_immed (const char *file
, unsigned int line
, int type
,
14497 bfd_reloc_code_real_type reloc
, offsetT val
,
14498 unsigned int user_insn_length
, unsigned long *insn
)
14500 const struct mips_int_operand
*operand
;
14501 unsigned int uval
, length
;
14503 operand
= mips16_immed_operand (type
, FALSE
);
14504 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14506 /* We need an extended instruction. */
14507 if (user_insn_length
== 2)
14508 as_bad_where (file
, line
, _("invalid unextended operand value"));
14510 *insn
|= MIPS16_EXTEND
;
14512 else if (user_insn_length
== 4)
14514 /* The operand doesn't force an unextended instruction to be extended.
14515 Warn if the user wanted an extended instruction anyway. */
14516 *insn
|= MIPS16_EXTEND
;
14517 as_warn_where (file
, line
,
14518 _("extended operand requested but not required"));
14521 length
= mips16_opcode_length (*insn
);
14524 operand
= mips16_immed_operand (type
, TRUE
);
14525 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14526 as_bad_where (file
, line
,
14527 _("operand value out of range for instruction"));
14529 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14530 if (length
== 2 || operand
->root
.lsb
!= 0)
14531 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14533 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14536 struct percent_op_match
14539 bfd_reloc_code_real_type reloc
;
14542 static const struct percent_op_match mips_percent_op
[] =
14544 {"%lo", BFD_RELOC_LO16
},
14545 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14546 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14547 {"%call16", BFD_RELOC_MIPS_CALL16
},
14548 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14549 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14550 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14551 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14552 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14553 {"%got", BFD_RELOC_MIPS_GOT16
},
14554 {"%gp_rel", BFD_RELOC_GPREL16
},
14555 {"%gprel", BFD_RELOC_GPREL16
},
14556 {"%half", BFD_RELOC_16
},
14557 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14558 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14559 {"%neg", BFD_RELOC_MIPS_SUB
},
14560 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14561 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14562 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14563 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14564 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14565 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14566 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14567 {"%hi", BFD_RELOC_HI16_S
},
14568 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14569 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14572 static const struct percent_op_match mips16_percent_op
[] =
14574 {"%lo", BFD_RELOC_MIPS16_LO16
},
14575 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14576 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14577 {"%got", BFD_RELOC_MIPS16_GOT16
},
14578 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14579 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14580 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14581 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14582 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14583 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14584 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14585 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14586 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14590 /* Return true if *STR points to a relocation operator. When returning true,
14591 move *STR over the operator and store its relocation code in *RELOC.
14592 Leave both *STR and *RELOC alone when returning false. */
14595 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14597 const struct percent_op_match
*percent_op
;
14600 if (mips_opts
.mips16
)
14602 percent_op
= mips16_percent_op
;
14603 limit
= ARRAY_SIZE (mips16_percent_op
);
14607 percent_op
= mips_percent_op
;
14608 limit
= ARRAY_SIZE (mips_percent_op
);
14611 for (i
= 0; i
< limit
; i
++)
14612 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14614 int len
= strlen (percent_op
[i
].str
);
14616 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14619 *str
+= strlen (percent_op
[i
].str
);
14620 *reloc
= percent_op
[i
].reloc
;
14622 /* Check whether the output BFD supports this relocation.
14623 If not, issue an error and fall back on something safe. */
14624 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14626 as_bad (_("relocation %s isn't supported by the current ABI"),
14627 percent_op
[i
].str
);
14628 *reloc
= BFD_RELOC_UNUSED
;
14636 /* Parse string STR as a 16-bit relocatable operand. Store the
14637 expression in *EP and the relocations in the array starting
14638 at RELOC. Return the number of relocation operators used.
14640 On exit, EXPR_END points to the first character after the expression. */
14643 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14646 bfd_reloc_code_real_type reversed_reloc
[3];
14647 size_t reloc_index
, i
;
14648 int crux_depth
, str_depth
;
14651 /* Search for the start of the main expression, recoding relocations
14652 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14653 of the main expression and with CRUX_DEPTH containing the number
14654 of open brackets at that point. */
14661 crux_depth
= str_depth
;
14663 /* Skip over whitespace and brackets, keeping count of the number
14665 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14670 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14671 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14673 my_getExpression (ep
, crux
);
14676 /* Match every open bracket. */
14677 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14681 if (crux_depth
> 0)
14682 as_bad (_("unclosed '('"));
14686 if (reloc_index
!= 0)
14688 prev_reloc_op_frag
= frag_now
;
14689 for (i
= 0; i
< reloc_index
; i
++)
14690 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14693 return reloc_index
;
14697 my_getExpression (expressionS
*ep
, char *str
)
14701 save_in
= input_line_pointer
;
14702 input_line_pointer
= str
;
14704 expr_end
= input_line_pointer
;
14705 input_line_pointer
= save_in
;
14709 md_atof (int type
, char *litP
, int *sizeP
)
14711 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14715 md_number_to_chars (char *buf
, valueT val
, int n
)
14717 if (target_big_endian
)
14718 number_to_chars_bigendian (buf
, val
, n
);
14720 number_to_chars_littleendian (buf
, val
, n
);
14723 static int support_64bit_objects(void)
14725 const char **list
, **l
;
14728 list
= bfd_target_list ();
14729 for (l
= list
; *l
!= NULL
; l
++)
14730 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14731 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14733 yes
= (*l
!= NULL
);
14738 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14739 NEW_VALUE. Warn if another value was already specified. Note:
14740 we have to defer parsing the -march and -mtune arguments in order
14741 to handle 'from-abi' correctly, since the ABI might be specified
14742 in a later argument. */
14745 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14747 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14748 as_warn (_("a different %s was already specified, is now %s"),
14749 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14752 *string_ptr
= new_value
;
14756 md_parse_option (int c
, const char *arg
)
14760 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14761 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14763 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14764 c
== mips_ases
[i
].option_on
);
14770 case OPTION_CONSTRUCT_FLOATS
:
14771 mips_disable_float_construction
= 0;
14774 case OPTION_NO_CONSTRUCT_FLOATS
:
14775 mips_disable_float_construction
= 1;
14787 target_big_endian
= 1;
14791 target_big_endian
= 0;
14797 else if (arg
[0] == '0')
14799 else if (arg
[0] == '1')
14809 mips_debug
= atoi (arg
);
14813 file_mips_opts
.isa
= ISA_MIPS1
;
14817 file_mips_opts
.isa
= ISA_MIPS2
;
14821 file_mips_opts
.isa
= ISA_MIPS3
;
14825 file_mips_opts
.isa
= ISA_MIPS4
;
14829 file_mips_opts
.isa
= ISA_MIPS5
;
14832 case OPTION_MIPS32
:
14833 file_mips_opts
.isa
= ISA_MIPS32
;
14836 case OPTION_MIPS32R2
:
14837 file_mips_opts
.isa
= ISA_MIPS32R2
;
14840 case OPTION_MIPS32R3
:
14841 file_mips_opts
.isa
= ISA_MIPS32R3
;
14844 case OPTION_MIPS32R5
:
14845 file_mips_opts
.isa
= ISA_MIPS32R5
;
14848 case OPTION_MIPS32R6
:
14849 file_mips_opts
.isa
= ISA_MIPS32R6
;
14852 case OPTION_MIPS64R2
:
14853 file_mips_opts
.isa
= ISA_MIPS64R2
;
14856 case OPTION_MIPS64R3
:
14857 file_mips_opts
.isa
= ISA_MIPS64R3
;
14860 case OPTION_MIPS64R5
:
14861 file_mips_opts
.isa
= ISA_MIPS64R5
;
14864 case OPTION_MIPS64R6
:
14865 file_mips_opts
.isa
= ISA_MIPS64R6
;
14868 case OPTION_MIPS64
:
14869 file_mips_opts
.isa
= ISA_MIPS64
;
14873 mips_set_option_string (&mips_tune_string
, arg
);
14877 mips_set_option_string (&mips_arch_string
, arg
);
14881 mips_set_option_string (&mips_arch_string
, "4650");
14882 mips_set_option_string (&mips_tune_string
, "4650");
14885 case OPTION_NO_M4650
:
14889 mips_set_option_string (&mips_arch_string
, "4010");
14890 mips_set_option_string (&mips_tune_string
, "4010");
14893 case OPTION_NO_M4010
:
14897 mips_set_option_string (&mips_arch_string
, "4100");
14898 mips_set_option_string (&mips_tune_string
, "4100");
14901 case OPTION_NO_M4100
:
14905 mips_set_option_string (&mips_arch_string
, "3900");
14906 mips_set_option_string (&mips_tune_string
, "3900");
14909 case OPTION_NO_M3900
:
14912 case OPTION_MICROMIPS
:
14913 if (file_mips_opts
.mips16
== 1)
14915 as_bad (_("-mmicromips cannot be used with -mips16"));
14918 file_mips_opts
.micromips
= 1;
14919 mips_no_prev_insn ();
14922 case OPTION_NO_MICROMIPS
:
14923 file_mips_opts
.micromips
= 0;
14924 mips_no_prev_insn ();
14927 case OPTION_MIPS16
:
14928 if (file_mips_opts
.micromips
== 1)
14930 as_bad (_("-mips16 cannot be used with -micromips"));
14933 file_mips_opts
.mips16
= 1;
14934 mips_no_prev_insn ();
14937 case OPTION_NO_MIPS16
:
14938 file_mips_opts
.mips16
= 0;
14939 mips_no_prev_insn ();
14942 case OPTION_FIX_24K
:
14946 case OPTION_NO_FIX_24K
:
14950 case OPTION_FIX_RM7000
:
14951 mips_fix_rm7000
= 1;
14954 case OPTION_NO_FIX_RM7000
:
14955 mips_fix_rm7000
= 0;
14958 case OPTION_FIX_LOONGSON3_LLSC
:
14959 mips_fix_loongson3_llsc
= TRUE
;
14962 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14963 mips_fix_loongson3_llsc
= FALSE
;
14966 case OPTION_FIX_LOONGSON2F_JUMP
:
14967 mips_fix_loongson2f_jump
= TRUE
;
14970 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14971 mips_fix_loongson2f_jump
= FALSE
;
14974 case OPTION_FIX_LOONGSON2F_NOP
:
14975 mips_fix_loongson2f_nop
= TRUE
;
14978 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14979 mips_fix_loongson2f_nop
= FALSE
;
14982 case OPTION_FIX_VR4120
:
14983 mips_fix_vr4120
= 1;
14986 case OPTION_NO_FIX_VR4120
:
14987 mips_fix_vr4120
= 0;
14990 case OPTION_FIX_VR4130
:
14991 mips_fix_vr4130
= 1;
14994 case OPTION_NO_FIX_VR4130
:
14995 mips_fix_vr4130
= 0;
14998 case OPTION_FIX_CN63XXP1
:
14999 mips_fix_cn63xxp1
= TRUE
;
15002 case OPTION_NO_FIX_CN63XXP1
:
15003 mips_fix_cn63xxp1
= FALSE
;
15006 case OPTION_FIX_R5900
:
15007 mips_fix_r5900
= TRUE
;
15008 mips_fix_r5900_explicit
= TRUE
;
15011 case OPTION_NO_FIX_R5900
:
15012 mips_fix_r5900
= FALSE
;
15013 mips_fix_r5900_explicit
= TRUE
;
15016 case OPTION_RELAX_BRANCH
:
15017 mips_relax_branch
= 1;
15020 case OPTION_NO_RELAX_BRANCH
:
15021 mips_relax_branch
= 0;
15024 case OPTION_IGNORE_BRANCH_ISA
:
15025 mips_ignore_branch_isa
= TRUE
;
15028 case OPTION_NO_IGNORE_BRANCH_ISA
:
15029 mips_ignore_branch_isa
= FALSE
;
15032 case OPTION_INSN32
:
15033 file_mips_opts
.insn32
= TRUE
;
15036 case OPTION_NO_INSN32
:
15037 file_mips_opts
.insn32
= FALSE
;
15040 case OPTION_MSHARED
:
15041 mips_in_shared
= TRUE
;
15044 case OPTION_MNO_SHARED
:
15045 mips_in_shared
= FALSE
;
15048 case OPTION_MSYM32
:
15049 file_mips_opts
.sym32
= TRUE
;
15052 case OPTION_MNO_SYM32
:
15053 file_mips_opts
.sym32
= FALSE
;
15056 /* When generating ELF code, we permit -KPIC and -call_shared to
15057 select SVR4_PIC, and -non_shared to select no PIC. This is
15058 intended to be compatible with Irix 5. */
15059 case OPTION_CALL_SHARED
:
15060 mips_pic
= SVR4_PIC
;
15061 mips_abicalls
= TRUE
;
15064 case OPTION_CALL_NONPIC
:
15066 mips_abicalls
= TRUE
;
15069 case OPTION_NON_SHARED
:
15071 mips_abicalls
= FALSE
;
15074 /* The -xgot option tells the assembler to use 32 bit offsets
15075 when accessing the got in SVR4_PIC mode. It is for Irix
15082 g_switch_value
= atoi (arg
);
15086 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15089 mips_abi
= O32_ABI
;
15093 mips_abi
= N32_ABI
;
15097 mips_abi
= N64_ABI
;
15098 if (!support_64bit_objects())
15099 as_fatal (_("no compiled in support for 64 bit object file format"));
15103 file_mips_opts
.gp
= 32;
15107 file_mips_opts
.gp
= 64;
15111 file_mips_opts
.fp
= 32;
15115 file_mips_opts
.fp
= 0;
15119 file_mips_opts
.fp
= 64;
15122 case OPTION_ODD_SPREG
:
15123 file_mips_opts
.oddspreg
= 1;
15126 case OPTION_NO_ODD_SPREG
:
15127 file_mips_opts
.oddspreg
= 0;
15130 case OPTION_SINGLE_FLOAT
:
15131 file_mips_opts
.single_float
= 1;
15134 case OPTION_DOUBLE_FLOAT
:
15135 file_mips_opts
.single_float
= 0;
15138 case OPTION_SOFT_FLOAT
:
15139 file_mips_opts
.soft_float
= 1;
15142 case OPTION_HARD_FLOAT
:
15143 file_mips_opts
.soft_float
= 0;
15147 if (strcmp (arg
, "32") == 0)
15148 mips_abi
= O32_ABI
;
15149 else if (strcmp (arg
, "o64") == 0)
15150 mips_abi
= O64_ABI
;
15151 else if (strcmp (arg
, "n32") == 0)
15152 mips_abi
= N32_ABI
;
15153 else if (strcmp (arg
, "64") == 0)
15155 mips_abi
= N64_ABI
;
15156 if (! support_64bit_objects())
15157 as_fatal (_("no compiled in support for 64 bit object file "
15160 else if (strcmp (arg
, "eabi") == 0)
15161 mips_abi
= EABI_ABI
;
15164 as_fatal (_("invalid abi -mabi=%s"), arg
);
15169 case OPTION_M7000_HILO_FIX
:
15170 mips_7000_hilo_fix
= TRUE
;
15173 case OPTION_MNO_7000_HILO_FIX
:
15174 mips_7000_hilo_fix
= FALSE
;
15177 case OPTION_MDEBUG
:
15178 mips_flag_mdebug
= TRUE
;
15181 case OPTION_NO_MDEBUG
:
15182 mips_flag_mdebug
= FALSE
;
15186 mips_flag_pdr
= TRUE
;
15189 case OPTION_NO_PDR
:
15190 mips_flag_pdr
= FALSE
;
15193 case OPTION_MVXWORKS_PIC
:
15194 mips_pic
= VXWORKS_PIC
;
15198 if (strcmp (arg
, "2008") == 0)
15200 else if (strcmp (arg
, "legacy") == 0)
15204 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15213 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15218 /* Set up globals to tune for the ISA or processor described by INFO. */
15221 mips_set_tune (const struct mips_cpu_info
*info
)
15224 mips_tune
= info
->cpu
;
15229 mips_after_parse_args (void)
15231 const struct mips_cpu_info
*arch_info
= 0;
15232 const struct mips_cpu_info
*tune_info
= 0;
15234 /* GP relative stuff not working for PE. */
15235 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15237 if (g_switch_seen
&& g_switch_value
!= 0)
15238 as_bad (_("-G not supported in this configuration"));
15239 g_switch_value
= 0;
15242 if (mips_abi
== NO_ABI
)
15243 mips_abi
= MIPS_DEFAULT_ABI
;
15245 /* The following code determines the architecture.
15246 Similar code was added to GCC 3.3 (see override_options() in
15247 config/mips/mips.c). The GAS and GCC code should be kept in sync
15248 as much as possible. */
15250 if (mips_arch_string
!= 0)
15251 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15253 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15255 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15256 ISA level specified by -mipsN, while arch_info->isa contains
15257 the -march selection (if any). */
15258 if (arch_info
!= 0)
15260 /* -march takes precedence over -mipsN, since it is more descriptive.
15261 There's no harm in specifying both as long as the ISA levels
15263 if (file_mips_opts
.isa
!= arch_info
->isa
)
15264 as_bad (_("-%s conflicts with the other architecture options,"
15265 " which imply -%s"),
15266 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15267 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15270 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15273 if (arch_info
== 0)
15275 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15276 gas_assert (arch_info
);
15279 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15280 as_bad (_("-march=%s is not compatible with the selected ABI"),
15283 file_mips_opts
.arch
= arch_info
->cpu
;
15284 file_mips_opts
.isa
= arch_info
->isa
;
15285 file_mips_opts
.init_ase
= arch_info
->ase
;
15287 /* The EVA Extension has instructions which are only valid when the R6 ISA
15288 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15290 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15291 file_mips_opts
.ase
|= ASE_EVA_R6
;
15293 /* Set up initial mips_opts state. */
15294 mips_opts
= file_mips_opts
;
15296 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15297 if (!mips_fix_r5900_explicit
)
15298 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15300 /* The register size inference code is now placed in
15301 file_mips_check_options. */
15303 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15305 if (mips_tune_string
!= 0)
15306 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15308 if (tune_info
== 0)
15309 mips_set_tune (arch_info
);
15311 mips_set_tune (tune_info
);
15313 if (mips_flag_mdebug
< 0)
15314 mips_flag_mdebug
= 0;
15318 mips_init_after_args (void)
15320 /* Initialize opcodes. */
15321 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15322 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15326 md_pcrel_from (fixS
*fixP
)
15328 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15330 switch (fixP
->fx_r_type
)
15332 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15333 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15334 /* Return the address of the delay slot. */
15337 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15338 case BFD_RELOC_MICROMIPS_JMP
:
15339 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15340 case BFD_RELOC_16_PCREL_S2
:
15341 case BFD_RELOC_MIPS_21_PCREL_S2
:
15342 case BFD_RELOC_MIPS_26_PCREL_S2
:
15343 case BFD_RELOC_MIPS_JMP
:
15344 /* Return the address of the delay slot. */
15347 case BFD_RELOC_MIPS_18_PCREL_S3
:
15348 /* Return the aligned address of the doubleword containing
15349 the instruction. */
15357 /* This is called before the symbol table is processed. In order to
15358 work with gcc when using mips-tfile, we must keep all local labels.
15359 However, in other cases, we want to discard them. If we were
15360 called with -g, but we didn't see any debugging information, it may
15361 mean that gcc is smuggling debugging information through to
15362 mips-tfile, in which case we must generate all local labels. */
15365 mips_frob_file_before_adjust (void)
15367 #ifndef NO_ECOFF_DEBUGGING
15368 if (ECOFF_DEBUGGING
15370 && ! ecoff_debugging_seen
)
15371 flag_keep_locals
= 1;
15375 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15376 the corresponding LO16 reloc. This is called before md_apply_fix and
15377 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15378 relocation operators.
15380 For our purposes, a %lo() expression matches a %got() or %hi()
15383 (a) it refers to the same symbol; and
15384 (b) the offset applied in the %lo() expression is no lower than
15385 the offset applied in the %got() or %hi().
15387 (b) allows us to cope with code like:
15390 lh $4,%lo(foo+2)($4)
15392 ...which is legal on RELA targets, and has a well-defined behaviour
15393 if the user knows that adding 2 to "foo" will not induce a carry to
15396 When several %lo()s match a particular %got() or %hi(), we use the
15397 following rules to distinguish them:
15399 (1) %lo()s with smaller offsets are a better match than %lo()s with
15402 (2) %lo()s with no matching %got() or %hi() are better than those
15403 that already have a matching %got() or %hi().
15405 (3) later %lo()s are better than earlier %lo()s.
15407 These rules are applied in order.
15409 (1) means, among other things, that %lo()s with identical offsets are
15410 chosen if they exist.
15412 (2) means that we won't associate several high-part relocations with
15413 the same low-part relocation unless there's no alternative. Having
15414 several high parts for the same low part is a GNU extension; this rule
15415 allows careful users to avoid it.
15417 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15418 with the last high-part relocation being at the front of the list.
15419 It therefore makes sense to choose the last matching low-part
15420 relocation, all other things being equal. It's also easier
15421 to code that way. */
15424 mips_frob_file (void)
15426 struct mips_hi_fixup
*l
;
15427 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15429 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15431 segment_info_type
*seginfo
;
15432 bfd_boolean matched_lo_p
;
15433 fixS
**hi_pos
, **lo_pos
, **pos
;
15435 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15437 /* If a GOT16 relocation turns out to be against a global symbol,
15438 there isn't supposed to be a matching LO. Ignore %gots against
15439 constants; we'll report an error for those later. */
15440 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15441 && !(l
->fixp
->fx_addsy
15442 && pic_need_relax (l
->fixp
->fx_addsy
)))
15445 /* Check quickly whether the next fixup happens to be a matching %lo. */
15446 if (fixup_has_matching_lo_p (l
->fixp
))
15449 seginfo
= seg_info (l
->seg
);
15451 /* Set HI_POS to the position of this relocation in the chain.
15452 Set LO_POS to the position of the chosen low-part relocation.
15453 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15454 relocation that matches an immediately-preceding high-part
15458 matched_lo_p
= FALSE
;
15459 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15461 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15463 if (*pos
== l
->fixp
)
15466 if ((*pos
)->fx_r_type
== looking_for_rtype
15467 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15468 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15470 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15472 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15475 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15476 && fixup_has_matching_lo_p (*pos
));
15479 /* If we found a match, remove the high-part relocation from its
15480 current position and insert it before the low-part relocation.
15481 Make the offsets match so that fixup_has_matching_lo_p()
15484 We don't warn about unmatched high-part relocations since some
15485 versions of gcc have been known to emit dead "lui ...%hi(...)"
15487 if (lo_pos
!= NULL
)
15489 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15490 if (l
->fixp
->fx_next
!= *lo_pos
)
15492 *hi_pos
= l
->fixp
->fx_next
;
15493 l
->fixp
->fx_next
= *lo_pos
;
15501 mips_force_relocation (fixS
*fixp
)
15503 if (generic_force_reloc (fixp
))
15506 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15507 so that the linker relaxation can update targets. */
15508 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15509 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15510 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15513 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15514 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15515 microMIPS symbols so that we can do cross-mode branch diagnostics
15516 and BAL to JALX conversion by the linker. */
15517 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15518 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15519 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15521 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15524 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15525 if (ISA_IS_R6 (file_mips_opts
.isa
)
15526 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15527 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15528 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15529 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15530 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15531 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15532 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15538 /* Implement TC_FORCE_RELOCATION_ABS. */
15541 mips_force_relocation_abs (fixS
*fixp
)
15543 if (generic_force_reloc (fixp
))
15546 /* These relocations do not have enough bits in the in-place addend
15547 to hold an arbitrary absolute section's offset. */
15548 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15554 /* Read the instruction associated with RELOC from BUF. */
15556 static unsigned int
15557 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15559 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15560 return read_compressed_insn (buf
, 4);
15562 return read_insn (buf
);
15565 /* Write instruction INSN to BUF, given that it has been relocated
15569 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15570 unsigned long insn
)
15572 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15573 write_compressed_insn (buf
, insn
, 4);
15575 write_insn (buf
, insn
);
15578 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15579 to a symbol in another ISA mode, which cannot be converted to JALX. */
15582 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15584 unsigned long opcode
;
15588 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15591 other
= S_GET_OTHER (fixP
->fx_addsy
);
15592 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15593 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15594 switch (fixP
->fx_r_type
)
15596 case BFD_RELOC_MIPS_JMP
:
15597 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15598 case BFD_RELOC_MICROMIPS_JMP
:
15599 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15605 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15606 jump to a symbol in the same ISA mode. */
15609 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15611 unsigned long opcode
;
15615 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15618 other
= S_GET_OTHER (fixP
->fx_addsy
);
15619 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15620 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15621 switch (fixP
->fx_r_type
)
15623 case BFD_RELOC_MIPS_JMP
:
15624 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15625 case BFD_RELOC_MIPS16_JMP
:
15626 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15627 case BFD_RELOC_MICROMIPS_JMP
:
15628 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15634 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15635 to a symbol whose value plus addend is not aligned according to the
15636 ultimate (after linker relaxation) jump instruction's immediate field
15637 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15638 regular MIPS code, to (1 << 2). */
15641 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15643 bfd_boolean micro_to_mips_p
;
15647 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15650 other
= S_GET_OTHER (fixP
->fx_addsy
);
15651 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15652 val
+= fixP
->fx_offset
;
15653 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15654 && !ELF_ST_IS_MICROMIPS (other
));
15655 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15656 != ELF_ST_IS_COMPRESSED (other
));
15659 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15660 to a symbol whose annotation indicates another ISA mode. For absolute
15661 symbols check the ISA bit instead.
15663 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15664 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15665 MIPS symbols and associated with BAL instructions as these instructions
15666 may be converted to JALX by the linker. */
15669 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15671 bfd_boolean absolute_p
;
15672 unsigned long opcode
;
15678 if (mips_ignore_branch_isa
)
15681 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15684 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15685 absolute_p
= bfd_is_abs_section (symsec
);
15687 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15688 other
= S_GET_OTHER (fixP
->fx_addsy
);
15690 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15691 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15692 switch (fixP
->fx_r_type
)
15694 case BFD_RELOC_16_PCREL_S2
:
15695 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15696 && opcode
!= 0x0411);
15697 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15698 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15699 && opcode
!= 0x4060);
15700 case BFD_RELOC_MIPS_21_PCREL_S2
:
15701 case BFD_RELOC_MIPS_26_PCREL_S2
:
15702 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15703 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15704 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15705 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15706 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15707 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15713 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15714 branch instruction pointed to by FIXP is not aligned according to the
15715 branch instruction's immediate field requirement. We need the addend
15716 to preserve the ISA bit and also the sum must not have bit 2 set. We
15717 must explicitly OR in the ISA bit from symbol annotation as the bit
15718 won't be set in the symbol's value then. */
15721 fix_bad_misaligned_branch_p (fixS
*fixP
)
15723 bfd_boolean absolute_p
;
15730 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15733 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15734 absolute_p
= bfd_is_abs_section (symsec
);
15736 val
= S_GET_VALUE (fixP
->fx_addsy
);
15737 other
= S_GET_OTHER (fixP
->fx_addsy
);
15738 off
= fixP
->fx_offset
;
15740 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15741 val
|= ELF_ST_IS_COMPRESSED (other
);
15743 return (val
& 0x3) != isa_bit
;
15746 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15747 and its calculated value VAL. */
15750 fix_validate_branch (fixS
*fixP
, valueT val
)
15752 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15754 _("branch to misaligned address (0x%lx)"),
15755 (long) (val
+ md_pcrel_from (fixP
)));
15756 else if (fix_bad_cross_mode_branch_p (fixP
))
15757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15758 _("branch to a symbol in another ISA mode"));
15759 else if (fix_bad_misaligned_branch_p (fixP
))
15760 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15761 _("branch to misaligned address (0x%lx)"),
15762 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15763 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15765 _("cannot encode misaligned addend "
15766 "in the relocatable field (0x%lx)"),
15767 (long) fixP
->fx_offset
);
15770 /* Apply a fixup to the object file. */
15773 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15776 unsigned long insn
;
15777 reloc_howto_type
*howto
;
15779 if (fixP
->fx_pcrel
)
15780 switch (fixP
->fx_r_type
)
15782 case BFD_RELOC_16_PCREL_S2
:
15783 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15784 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15785 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15786 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15787 case BFD_RELOC_32_PCREL
:
15788 case BFD_RELOC_MIPS_21_PCREL_S2
:
15789 case BFD_RELOC_MIPS_26_PCREL_S2
:
15790 case BFD_RELOC_MIPS_18_PCREL_S3
:
15791 case BFD_RELOC_MIPS_19_PCREL_S2
:
15792 case BFD_RELOC_HI16_S_PCREL
:
15793 case BFD_RELOC_LO16_PCREL
:
15797 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15802 _("PC-relative reference to a different section"));
15806 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15807 that have no MIPS ELF equivalent. */
15808 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15810 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15815 gas_assert (fixP
->fx_size
== 2
15816 || fixP
->fx_size
== 4
15817 || fixP
->fx_r_type
== BFD_RELOC_8
15818 || fixP
->fx_r_type
== BFD_RELOC_16
15819 || fixP
->fx_r_type
== BFD_RELOC_64
15820 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15821 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15822 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15823 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15824 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15825 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15826 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15828 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15830 /* Don't treat parts of a composite relocation as done. There are two
15833 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15834 should nevertheless be emitted if the first part is.
15836 (2) In normal usage, composite relocations are never assembly-time
15837 constants. The easiest way of dealing with the pathological
15838 exceptions is to generate a relocation against STN_UNDEF and
15839 leave everything up to the linker. */
15840 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15843 switch (fixP
->fx_r_type
)
15845 case BFD_RELOC_MIPS_TLS_GD
:
15846 case BFD_RELOC_MIPS_TLS_LDM
:
15847 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15848 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15849 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15850 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15851 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15852 case BFD_RELOC_MIPS_TLS_TPREL32
:
15853 case BFD_RELOC_MIPS_TLS_TPREL64
:
15854 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15855 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15856 case BFD_RELOC_MICROMIPS_TLS_GD
:
15857 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15858 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15859 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15860 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15861 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15862 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15863 case BFD_RELOC_MIPS16_TLS_GD
:
15864 case BFD_RELOC_MIPS16_TLS_LDM
:
15865 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15866 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15867 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15868 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15869 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15870 if (fixP
->fx_addsy
)
15871 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15874 _("TLS relocation against a constant"));
15877 case BFD_RELOC_MIPS_JMP
:
15878 case BFD_RELOC_MIPS16_JMP
:
15879 case BFD_RELOC_MICROMIPS_JMP
:
15883 gas_assert (!fixP
->fx_done
);
15885 /* Shift is 2, unusually, for microMIPS JALX. */
15886 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15887 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15892 if (fix_bad_cross_mode_jump_p (fixP
))
15893 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15894 _("jump to a symbol in another ISA mode"));
15895 else if (fix_bad_same_mode_jalx_p (fixP
))
15896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15897 _("JALX to a symbol in the same ISA mode"));
15898 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15900 _("jump to misaligned address (0x%lx)"),
15901 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15902 + fixP
->fx_offset
));
15903 else if (HAVE_IN_PLACE_ADDENDS
15904 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15906 _("cannot encode misaligned addend "
15907 "in the relocatable field (0x%lx)"),
15908 (long) fixP
->fx_offset
);
15910 /* Fall through. */
15912 case BFD_RELOC_MIPS_SHIFT5
:
15913 case BFD_RELOC_MIPS_SHIFT6
:
15914 case BFD_RELOC_MIPS_GOT_DISP
:
15915 case BFD_RELOC_MIPS_GOT_PAGE
:
15916 case BFD_RELOC_MIPS_GOT_OFST
:
15917 case BFD_RELOC_MIPS_SUB
:
15918 case BFD_RELOC_MIPS_INSERT_A
:
15919 case BFD_RELOC_MIPS_INSERT_B
:
15920 case BFD_RELOC_MIPS_DELETE
:
15921 case BFD_RELOC_MIPS_HIGHEST
:
15922 case BFD_RELOC_MIPS_HIGHER
:
15923 case BFD_RELOC_MIPS_SCN_DISP
:
15924 case BFD_RELOC_MIPS_REL16
:
15925 case BFD_RELOC_MIPS_RELGOT
:
15926 case BFD_RELOC_MIPS_JALR
:
15927 case BFD_RELOC_HI16
:
15928 case BFD_RELOC_HI16_S
:
15929 case BFD_RELOC_LO16
:
15930 case BFD_RELOC_GPREL16
:
15931 case BFD_RELOC_MIPS_LITERAL
:
15932 case BFD_RELOC_MIPS_CALL16
:
15933 case BFD_RELOC_MIPS_GOT16
:
15934 case BFD_RELOC_GPREL32
:
15935 case BFD_RELOC_MIPS_GOT_HI16
:
15936 case BFD_RELOC_MIPS_GOT_LO16
:
15937 case BFD_RELOC_MIPS_CALL_HI16
:
15938 case BFD_RELOC_MIPS_CALL_LO16
:
15939 case BFD_RELOC_HI16_S_PCREL
:
15940 case BFD_RELOC_LO16_PCREL
:
15941 case BFD_RELOC_MIPS16_GPREL
:
15942 case BFD_RELOC_MIPS16_GOT16
:
15943 case BFD_RELOC_MIPS16_CALL16
:
15944 case BFD_RELOC_MIPS16_HI16
:
15945 case BFD_RELOC_MIPS16_HI16_S
:
15946 case BFD_RELOC_MIPS16_LO16
:
15947 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15948 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15949 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15950 case BFD_RELOC_MICROMIPS_SUB
:
15951 case BFD_RELOC_MICROMIPS_HIGHEST
:
15952 case BFD_RELOC_MICROMIPS_HIGHER
:
15953 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15954 case BFD_RELOC_MICROMIPS_JALR
:
15955 case BFD_RELOC_MICROMIPS_HI16
:
15956 case BFD_RELOC_MICROMIPS_HI16_S
:
15957 case BFD_RELOC_MICROMIPS_LO16
:
15958 case BFD_RELOC_MICROMIPS_GPREL16
:
15959 case BFD_RELOC_MICROMIPS_LITERAL
:
15960 case BFD_RELOC_MICROMIPS_CALL16
:
15961 case BFD_RELOC_MICROMIPS_GOT16
:
15962 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15963 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15964 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15965 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15966 case BFD_RELOC_MIPS_EH
:
15971 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15973 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15974 if (mips16_reloc_p (fixP
->fx_r_type
))
15975 insn
|= mips16_immed_extend (value
, 16);
15977 insn
|= (value
& 0xffff);
15978 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15982 _("unsupported constant in relocation"));
15987 /* This is handled like BFD_RELOC_32, but we output a sign
15988 extended value if we are only 32 bits. */
15991 if (8 <= sizeof (valueT
))
15992 md_number_to_chars (buf
, *valP
, 8);
15997 if ((*valP
& 0x80000000) != 0)
16001 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16002 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16007 case BFD_RELOC_RVA
:
16009 case BFD_RELOC_32_PCREL
:
16012 /* If we are deleting this reloc entry, we must fill in the
16013 value now. This can happen if we have a .word which is not
16014 resolved when it appears but is later defined. */
16016 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16019 case BFD_RELOC_MIPS_21_PCREL_S2
:
16020 fix_validate_branch (fixP
, *valP
);
16021 if (!fixP
->fx_done
)
16024 if (*valP
+ 0x400000 <= 0x7fffff)
16026 insn
= read_insn (buf
);
16027 insn
|= (*valP
>> 2) & 0x1fffff;
16028 write_insn (buf
, insn
);
16031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16032 _("branch out of range"));
16035 case BFD_RELOC_MIPS_26_PCREL_S2
:
16036 fix_validate_branch (fixP
, *valP
);
16037 if (!fixP
->fx_done
)
16040 if (*valP
+ 0x8000000 <= 0xfffffff)
16042 insn
= read_insn (buf
);
16043 insn
|= (*valP
>> 2) & 0x3ffffff;
16044 write_insn (buf
, insn
);
16047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16048 _("branch out of range"));
16051 case BFD_RELOC_MIPS_18_PCREL_S3
:
16052 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16054 _("PC-relative access using misaligned symbol (%lx)"),
16055 (long) S_GET_VALUE (fixP
->fx_addsy
));
16056 if ((fixP
->fx_offset
& 0x7) != 0)
16057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16058 _("PC-relative access using misaligned offset (%lx)"),
16059 (long) fixP
->fx_offset
);
16060 if (!fixP
->fx_done
)
16063 if (*valP
+ 0x100000 <= 0x1fffff)
16065 insn
= read_insn (buf
);
16066 insn
|= (*valP
>> 3) & 0x3ffff;
16067 write_insn (buf
, insn
);
16070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16071 _("PC-relative access out of range"));
16074 case BFD_RELOC_MIPS_19_PCREL_S2
:
16075 if ((*valP
& 0x3) != 0)
16076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16077 _("PC-relative access to misaligned address (%lx)"),
16079 if (!fixP
->fx_done
)
16082 if (*valP
+ 0x100000 <= 0x1fffff)
16084 insn
= read_insn (buf
);
16085 insn
|= (*valP
>> 2) & 0x7ffff;
16086 write_insn (buf
, insn
);
16089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16090 _("PC-relative access out of range"));
16093 case BFD_RELOC_16_PCREL_S2
:
16094 fix_validate_branch (fixP
, *valP
);
16096 /* We need to save the bits in the instruction since fixup_segment()
16097 might be deleting the relocation entry (i.e., a branch within
16098 the current segment). */
16099 if (! fixP
->fx_done
)
16102 /* Update old instruction data. */
16103 insn
= read_insn (buf
);
16105 if (*valP
+ 0x20000 <= 0x3ffff)
16107 insn
|= (*valP
>> 2) & 0xffff;
16108 write_insn (buf
, insn
);
16110 else if (fixP
->fx_tcbit2
16112 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16113 && (fixP
->fx_frag
->fr_address
16114 < text_section
->vma
+ bfd_get_section_size (text_section
))
16115 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16116 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16117 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16119 /* The branch offset is too large. If this is an
16120 unconditional branch, and we are not generating PIC code,
16121 we can convert it to an absolute jump instruction. */
16122 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16123 insn
= 0x0c000000; /* jal */
16125 insn
= 0x08000000; /* j */
16126 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16128 fixP
->fx_addsy
= section_symbol (text_section
);
16129 *valP
+= md_pcrel_from (fixP
);
16130 write_insn (buf
, insn
);
16134 /* If we got here, we have branch-relaxation disabled,
16135 and there's nothing we can do to fix this instruction
16136 without turning it into a longer sequence. */
16137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16138 _("branch out of range"));
16142 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16143 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16144 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16145 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16146 gas_assert (!fixP
->fx_done
);
16147 if (fix_bad_cross_mode_branch_p (fixP
))
16148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16149 _("branch to a symbol in another ISA mode"));
16150 else if (fixP
->fx_addsy
16151 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16152 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16153 && (fixP
->fx_offset
& 0x1) != 0)
16154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16155 _("branch to misaligned address (0x%lx)"),
16156 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
16157 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16159 _("cannot encode misaligned addend "
16160 "in the relocatable field (0x%lx)"),
16161 (long) fixP
->fx_offset
);
16164 case BFD_RELOC_VTABLE_INHERIT
:
16167 && !S_IS_DEFINED (fixP
->fx_addsy
)
16168 && !S_IS_WEAK (fixP
->fx_addsy
))
16169 S_SET_WEAK (fixP
->fx_addsy
);
16172 case BFD_RELOC_NONE
:
16173 case BFD_RELOC_VTABLE_ENTRY
:
16181 /* Remember value for tc_gen_reloc. */
16182 fixP
->fx_addnumber
= *valP
;
16192 c
= get_symbol_name (&name
);
16193 p
= (symbolS
*) symbol_find_or_make (name
);
16194 (void) restore_line_pointer (c
);
16198 /* Align the current frag to a given power of two. If a particular
16199 fill byte should be used, FILL points to an integer that contains
16200 that byte, otherwise FILL is null.
16202 This function used to have the comment:
16204 The MIPS assembler also automatically adjusts any preceding label.
16206 The implementation therefore applied the adjustment to a maximum of
16207 one label. However, other label adjustments are applied to batches
16208 of labels, and adjusting just one caused problems when new labels
16209 were added for the sake of debugging or unwind information.
16210 We therefore adjust all preceding labels (given as LABELS) instead. */
16213 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16215 mips_emit_delays ();
16216 mips_record_compressed_mode ();
16217 if (fill
== NULL
&& subseg_text_p (now_seg
))
16218 frag_align_code (to
, 0);
16220 frag_align (to
, fill
? *fill
: 0, 0);
16221 record_alignment (now_seg
, to
);
16222 mips_move_labels (labels
, subseg_text_p (now_seg
));
16225 /* Align to a given power of two. .align 0 turns off the automatic
16226 alignment used by the data creating pseudo-ops. */
16229 s_align (int x ATTRIBUTE_UNUSED
)
16231 int temp
, fill_value
, *fill_ptr
;
16232 long max_alignment
= 28;
16234 /* o Note that the assembler pulls down any immediately preceding label
16235 to the aligned address.
16236 o It's not documented but auto alignment is reinstated by
16237 a .align pseudo instruction.
16238 o Note also that after auto alignment is turned off the mips assembler
16239 issues an error on attempt to assemble an improperly aligned data item.
16242 temp
= get_absolute_expression ();
16243 if (temp
> max_alignment
)
16244 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16247 as_warn (_("alignment negative, 0 assumed"));
16250 if (*input_line_pointer
== ',')
16252 ++input_line_pointer
;
16253 fill_value
= get_absolute_expression ();
16254 fill_ptr
= &fill_value
;
16260 segment_info_type
*si
= seg_info (now_seg
);
16261 struct insn_label_list
*l
= si
->label_list
;
16262 /* Auto alignment should be switched on by next section change. */
16264 mips_align (temp
, fill_ptr
, l
);
16271 demand_empty_rest_of_line ();
16275 s_change_sec (int sec
)
16279 /* The ELF backend needs to know that we are changing sections, so
16280 that .previous works correctly. We could do something like check
16281 for an obj_section_change_hook macro, but that might be confusing
16282 as it would not be appropriate to use it in the section changing
16283 functions in read.c, since obj-elf.c intercepts those. FIXME:
16284 This should be cleaner, somehow. */
16285 obj_elf_section_change_hook ();
16287 mips_emit_delays ();
16298 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16299 demand_empty_rest_of_line ();
16303 seg
= subseg_new (RDATA_SECTION_NAME
,
16304 (subsegT
) get_absolute_expression ());
16305 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16306 | SEC_READONLY
| SEC_RELOC
16308 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16309 record_alignment (seg
, 4);
16310 demand_empty_rest_of_line ();
16314 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16315 bfd_set_section_flags (stdoutput
, seg
,
16316 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16317 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16318 record_alignment (seg
, 4);
16319 demand_empty_rest_of_line ();
16323 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16324 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16325 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16326 record_alignment (seg
, 4);
16327 demand_empty_rest_of_line ();
16335 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16338 char *section_name
;
16343 int section_entry_size
;
16344 int section_alignment
;
16346 saved_ilp
= input_line_pointer
;
16347 endc
= get_symbol_name (§ion_name
);
16348 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16350 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16352 /* Do we have .section Name<,"flags">? */
16353 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16355 /* Just after name is now '\0'. */
16356 (void) restore_line_pointer (endc
);
16357 input_line_pointer
= saved_ilp
;
16358 obj_elf_section (ignore
);
16362 section_name
= xstrdup (section_name
);
16363 c
= restore_line_pointer (endc
);
16365 input_line_pointer
++;
16367 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16369 section_type
= get_absolute_expression ();
16373 if (*input_line_pointer
++ == ',')
16374 section_flag
= get_absolute_expression ();
16378 if (*input_line_pointer
++ == ',')
16379 section_entry_size
= get_absolute_expression ();
16381 section_entry_size
= 0;
16383 if (*input_line_pointer
++ == ',')
16384 section_alignment
= get_absolute_expression ();
16386 section_alignment
= 0;
16388 /* FIXME: really ignore? */
16389 (void) section_alignment
;
16391 /* When using the generic form of .section (as implemented by obj-elf.c),
16392 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16393 traditionally had to fall back on the more common @progbits instead.
16395 There's nothing really harmful in this, since bfd will correct
16396 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16397 means that, for backwards compatibility, the special_section entries
16398 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16400 Even so, we shouldn't force users of the MIPS .section syntax to
16401 incorrectly label the sections as SHT_PROGBITS. The best compromise
16402 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16403 generic type-checking code. */
16404 if (section_type
== SHT_MIPS_DWARF
)
16405 section_type
= SHT_PROGBITS
;
16407 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16408 section_entry_size
, 0, 0, 0);
16410 if (now_seg
->name
!= section_name
)
16411 free (section_name
);
16415 mips_enable_auto_align (void)
16421 s_cons (int log_size
)
16423 segment_info_type
*si
= seg_info (now_seg
);
16424 struct insn_label_list
*l
= si
->label_list
;
16426 mips_emit_delays ();
16427 if (log_size
> 0 && auto_align
)
16428 mips_align (log_size
, 0, l
);
16429 cons (1 << log_size
);
16430 mips_clear_insn_labels ();
16434 s_float_cons (int type
)
16436 segment_info_type
*si
= seg_info (now_seg
);
16437 struct insn_label_list
*l
= si
->label_list
;
16439 mips_emit_delays ();
16444 mips_align (3, 0, l
);
16446 mips_align (2, 0, l
);
16450 mips_clear_insn_labels ();
16453 /* Handle .globl. We need to override it because on Irix 5 you are
16456 where foo is an undefined symbol, to mean that foo should be
16457 considered to be the address of a function. */
16460 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16468 c
= get_symbol_name (&name
);
16469 symbolP
= symbol_find_or_make (name
);
16470 S_SET_EXTERNAL (symbolP
);
16472 *input_line_pointer
= c
;
16473 SKIP_WHITESPACE_AFTER_NAME ();
16475 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16476 && (*input_line_pointer
!= ','))
16481 c
= get_symbol_name (&secname
);
16482 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16484 as_bad (_("%s: no such section"), secname
);
16485 (void) restore_line_pointer (c
);
16487 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16488 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16491 c
= *input_line_pointer
;
16494 input_line_pointer
++;
16495 SKIP_WHITESPACE ();
16496 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16502 demand_empty_rest_of_line ();
16506 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16507 any undefined non-function symbol to STT_OBJECT. We try to be
16508 compatible, since newer Irix 5 and 6 linkers care. */
16511 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16513 /* This late in assembly we can set BSF_OBJECT indiscriminately
16514 and let elf.c:swap_out_syms sort out the symbol type. */
16515 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16516 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16517 || !S_IS_DEFINED (symp
))
16518 *flags
|= BSF_OBJECT
;
16523 s_option (int x ATTRIBUTE_UNUSED
)
16528 c
= get_symbol_name (&opt
);
16532 /* FIXME: What does this mean? */
16534 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16538 i
= atoi (opt
+ 3);
16539 if (i
!= 0 && i
!= 2)
16540 as_bad (_(".option pic%d not supported"), i
);
16541 else if (mips_pic
== VXWORKS_PIC
)
16542 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16547 mips_pic
= SVR4_PIC
;
16548 mips_abicalls
= TRUE
;
16551 if (mips_pic
== SVR4_PIC
)
16553 if (g_switch_seen
&& g_switch_value
!= 0)
16554 as_warn (_("-G may not be used with SVR4 PIC code"));
16555 g_switch_value
= 0;
16556 bfd_set_gp_size (stdoutput
, 0);
16560 as_warn (_("unrecognized option \"%s\""), opt
);
16562 (void) restore_line_pointer (c
);
16563 demand_empty_rest_of_line ();
16566 /* This structure is used to hold a stack of .set values. */
16568 struct mips_option_stack
16570 struct mips_option_stack
*next
;
16571 struct mips_set_options options
;
16574 static struct mips_option_stack
*mips_opts_stack
;
16576 /* Return status for .set/.module option handling. */
16578 enum code_option_type
16580 /* Unrecognized option. */
16581 OPTION_TYPE_BAD
= -1,
16583 /* Ordinary option. */
16584 OPTION_TYPE_NORMAL
,
16586 /* ISA changing option. */
16590 /* Handle common .set/.module options. Return status indicating option
16593 static enum code_option_type
16594 parse_code_option (char * name
)
16596 bfd_boolean isa_set
= FALSE
;
16597 const struct mips_ase
*ase
;
16599 if (strncmp (name
, "at=", 3) == 0)
16601 char *s
= name
+ 3;
16603 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16604 as_bad (_("unrecognized register name `%s'"), s
);
16606 else if (strcmp (name
, "at") == 0)
16607 mips_opts
.at
= ATREG
;
16608 else if (strcmp (name
, "noat") == 0)
16609 mips_opts
.at
= ZERO
;
16610 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16611 mips_opts
.nomove
= 0;
16612 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16613 mips_opts
.nomove
= 1;
16614 else if (strcmp (name
, "bopt") == 0)
16615 mips_opts
.nobopt
= 0;
16616 else if (strcmp (name
, "nobopt") == 0)
16617 mips_opts
.nobopt
= 1;
16618 else if (strcmp (name
, "gp=32") == 0)
16620 else if (strcmp (name
, "gp=64") == 0)
16622 else if (strcmp (name
, "fp=32") == 0)
16624 else if (strcmp (name
, "fp=xx") == 0)
16626 else if (strcmp (name
, "fp=64") == 0)
16628 else if (strcmp (name
, "softfloat") == 0)
16629 mips_opts
.soft_float
= 1;
16630 else if (strcmp (name
, "hardfloat") == 0)
16631 mips_opts
.soft_float
= 0;
16632 else if (strcmp (name
, "singlefloat") == 0)
16633 mips_opts
.single_float
= 1;
16634 else if (strcmp (name
, "doublefloat") == 0)
16635 mips_opts
.single_float
= 0;
16636 else if (strcmp (name
, "nooddspreg") == 0)
16637 mips_opts
.oddspreg
= 0;
16638 else if (strcmp (name
, "oddspreg") == 0)
16639 mips_opts
.oddspreg
= 1;
16640 else if (strcmp (name
, "mips16") == 0
16641 || strcmp (name
, "MIPS-16") == 0)
16642 mips_opts
.mips16
= 1;
16643 else if (strcmp (name
, "nomips16") == 0
16644 || strcmp (name
, "noMIPS-16") == 0)
16645 mips_opts
.mips16
= 0;
16646 else if (strcmp (name
, "micromips") == 0)
16647 mips_opts
.micromips
= 1;
16648 else if (strcmp (name
, "nomicromips") == 0)
16649 mips_opts
.micromips
= 0;
16650 else if (name
[0] == 'n'
16652 && (ase
= mips_lookup_ase (name
+ 2)))
16653 mips_set_ase (ase
, &mips_opts
, FALSE
);
16654 else if ((ase
= mips_lookup_ase (name
)))
16655 mips_set_ase (ase
, &mips_opts
, TRUE
);
16656 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16658 /* Permit the user to change the ISA and architecture on the fly.
16659 Needless to say, misuse can cause serious problems. */
16660 if (strncmp (name
, "arch=", 5) == 0)
16662 const struct mips_cpu_info
*p
;
16664 p
= mips_parse_cpu ("internal use", name
+ 5);
16666 as_bad (_("unknown architecture %s"), name
+ 5);
16669 mips_opts
.arch
= p
->cpu
;
16670 mips_opts
.isa
= p
->isa
;
16672 mips_opts
.init_ase
= p
->ase
;
16675 else if (strncmp (name
, "mips", 4) == 0)
16677 const struct mips_cpu_info
*p
;
16679 p
= mips_parse_cpu ("internal use", name
);
16681 as_bad (_("unknown ISA level %s"), name
+ 4);
16684 mips_opts
.arch
= p
->cpu
;
16685 mips_opts
.isa
= p
->isa
;
16687 mips_opts
.init_ase
= p
->ase
;
16691 as_bad (_("unknown ISA or architecture %s"), name
);
16693 else if (strcmp (name
, "autoextend") == 0)
16694 mips_opts
.noautoextend
= 0;
16695 else if (strcmp (name
, "noautoextend") == 0)
16696 mips_opts
.noautoextend
= 1;
16697 else if (strcmp (name
, "insn32") == 0)
16698 mips_opts
.insn32
= TRUE
;
16699 else if (strcmp (name
, "noinsn32") == 0)
16700 mips_opts
.insn32
= FALSE
;
16701 else if (strcmp (name
, "sym32") == 0)
16702 mips_opts
.sym32
= TRUE
;
16703 else if (strcmp (name
, "nosym32") == 0)
16704 mips_opts
.sym32
= FALSE
;
16706 return OPTION_TYPE_BAD
;
16708 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16711 /* Handle the .set pseudo-op. */
16714 s_mipsset (int x ATTRIBUTE_UNUSED
)
16716 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16717 char *name
= input_line_pointer
, ch
;
16719 file_mips_check_options ();
16721 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16722 ++input_line_pointer
;
16723 ch
= *input_line_pointer
;
16724 *input_line_pointer
= '\0';
16726 if (strchr (name
, ','))
16728 /* Generic ".set" directive; use the generic handler. */
16729 *input_line_pointer
= ch
;
16730 input_line_pointer
= name
;
16735 if (strcmp (name
, "reorder") == 0)
16737 if (mips_opts
.noreorder
)
16740 else if (strcmp (name
, "noreorder") == 0)
16742 if (!mips_opts
.noreorder
)
16743 start_noreorder ();
16745 else if (strcmp (name
, "macro") == 0)
16746 mips_opts
.warn_about_macros
= 0;
16747 else if (strcmp (name
, "nomacro") == 0)
16749 if (mips_opts
.noreorder
== 0)
16750 as_bad (_("`noreorder' must be set before `nomacro'"));
16751 mips_opts
.warn_about_macros
= 1;
16753 else if (strcmp (name
, "gp=default") == 0)
16754 mips_opts
.gp
= file_mips_opts
.gp
;
16755 else if (strcmp (name
, "fp=default") == 0)
16756 mips_opts
.fp
= file_mips_opts
.fp
;
16757 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16759 mips_opts
.isa
= file_mips_opts
.isa
;
16760 mips_opts
.arch
= file_mips_opts
.arch
;
16761 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16762 mips_opts
.gp
= file_mips_opts
.gp
;
16763 mips_opts
.fp
= file_mips_opts
.fp
;
16765 else if (strcmp (name
, "push") == 0)
16767 struct mips_option_stack
*s
;
16769 s
= XNEW (struct mips_option_stack
);
16770 s
->next
= mips_opts_stack
;
16771 s
->options
= mips_opts
;
16772 mips_opts_stack
= s
;
16774 else if (strcmp (name
, "pop") == 0)
16776 struct mips_option_stack
*s
;
16778 s
= mips_opts_stack
;
16780 as_bad (_(".set pop with no .set push"));
16783 /* If we're changing the reorder mode we need to handle
16784 delay slots correctly. */
16785 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16786 start_noreorder ();
16787 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16790 mips_opts
= s
->options
;
16791 mips_opts_stack
= s
->next
;
16797 type
= parse_code_option (name
);
16798 if (type
== OPTION_TYPE_BAD
)
16799 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16802 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16803 registers based on what is supported by the arch/cpu. */
16804 if (type
== OPTION_TYPE_ISA
)
16806 switch (mips_opts
.isa
)
16811 /* MIPS I cannot support FPXX. */
16813 /* fall-through. */
16820 if (mips_opts
.fp
!= 0)
16836 if (mips_opts
.fp
!= 0)
16838 if (mips_opts
.arch
== CPU_R5900
)
16845 as_bad (_("unknown ISA level %s"), name
+ 4);
16850 mips_check_options (&mips_opts
, FALSE
);
16852 mips_check_isa_supports_ases ();
16853 *input_line_pointer
= ch
;
16854 demand_empty_rest_of_line ();
16857 /* Handle the .module pseudo-op. */
16860 s_module (int ignore ATTRIBUTE_UNUSED
)
16862 char *name
= input_line_pointer
, ch
;
16864 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16865 ++input_line_pointer
;
16866 ch
= *input_line_pointer
;
16867 *input_line_pointer
= '\0';
16869 if (!file_mips_opts_checked
)
16871 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16872 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16874 /* Update module level settings from mips_opts. */
16875 file_mips_opts
= mips_opts
;
16878 as_bad (_(".module is not permitted after generating code"));
16880 *input_line_pointer
= ch
;
16881 demand_empty_rest_of_line ();
16884 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16885 .option pic2. It means to generate SVR4 PIC calls. */
16888 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16890 mips_pic
= SVR4_PIC
;
16891 mips_abicalls
= TRUE
;
16893 if (g_switch_seen
&& g_switch_value
!= 0)
16894 as_warn (_("-G may not be used with SVR4 PIC code"));
16895 g_switch_value
= 0;
16897 bfd_set_gp_size (stdoutput
, 0);
16898 demand_empty_rest_of_line ();
16901 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16902 PIC code. It sets the $gp register for the function based on the
16903 function address, which is in the register named in the argument.
16904 This uses a relocation against _gp_disp, which is handled specially
16905 by the linker. The result is:
16906 lui $gp,%hi(_gp_disp)
16907 addiu $gp,$gp,%lo(_gp_disp)
16908 addu $gp,$gp,.cpload argument
16909 The .cpload argument is normally $25 == $t9.
16911 The -mno-shared option changes this to:
16912 lui $gp,%hi(__gnu_local_gp)
16913 addiu $gp,$gp,%lo(__gnu_local_gp)
16914 and the argument is ignored. This saves an instruction, but the
16915 resulting code is not position independent; it uses an absolute
16916 address for __gnu_local_gp. Thus code assembled with -mno-shared
16917 can go into an ordinary executable, but not into a shared library. */
16920 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16926 file_mips_check_options ();
16928 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16929 .cpload is ignored. */
16930 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16936 if (mips_opts
.mips16
)
16938 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16939 ignore_rest_of_line ();
16943 /* .cpload should be in a .set noreorder section. */
16944 if (mips_opts
.noreorder
== 0)
16945 as_warn (_(".cpload not in noreorder section"));
16947 reg
= tc_get_register (0);
16949 /* If we need to produce a 64-bit address, we are better off using
16950 the default instruction sequence. */
16951 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16953 ex
.X_op
= O_symbol
;
16954 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16956 ex
.X_op_symbol
= NULL
;
16957 ex
.X_add_number
= 0;
16959 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16960 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16962 mips_mark_labels ();
16963 mips_assembling_insn
= TRUE
;
16966 macro_build_lui (&ex
, mips_gp_register
);
16967 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16968 mips_gp_register
, BFD_RELOC_LO16
);
16970 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16971 mips_gp_register
, reg
);
16974 mips_assembling_insn
= FALSE
;
16975 demand_empty_rest_of_line ();
16978 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16979 .cpsetup $reg1, offset|$reg2, label
16981 If offset is given, this results in:
16982 sd $gp, offset($sp)
16983 lui $gp, %hi(%neg(%gp_rel(label)))
16984 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16985 daddu $gp, $gp, $reg1
16987 If $reg2 is given, this results in:
16989 lui $gp, %hi(%neg(%gp_rel(label)))
16990 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16991 daddu $gp, $gp, $reg1
16992 $reg1 is normally $25 == $t9.
16994 The -mno-shared option replaces the last three instructions with
16996 addiu $gp,$gp,%lo(_gp) */
16999 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17001 expressionS ex_off
;
17002 expressionS ex_sym
;
17005 file_mips_check_options ();
17007 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17008 We also need NewABI support. */
17009 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17015 if (mips_opts
.mips16
)
17017 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17018 ignore_rest_of_line ();
17022 reg1
= tc_get_register (0);
17023 SKIP_WHITESPACE ();
17024 if (*input_line_pointer
!= ',')
17026 as_bad (_("missing argument separator ',' for .cpsetup"));
17030 ++input_line_pointer
;
17031 SKIP_WHITESPACE ();
17032 if (*input_line_pointer
== '$')
17034 mips_cpreturn_register
= tc_get_register (0);
17035 mips_cpreturn_offset
= -1;
17039 mips_cpreturn_offset
= get_absolute_expression ();
17040 mips_cpreturn_register
= -1;
17042 SKIP_WHITESPACE ();
17043 if (*input_line_pointer
!= ',')
17045 as_bad (_("missing argument separator ',' for .cpsetup"));
17049 ++input_line_pointer
;
17050 SKIP_WHITESPACE ();
17051 expression (&ex_sym
);
17053 mips_mark_labels ();
17054 mips_assembling_insn
= TRUE
;
17057 if (mips_cpreturn_register
== -1)
17059 ex_off
.X_op
= O_constant
;
17060 ex_off
.X_add_symbol
= NULL
;
17061 ex_off
.X_op_symbol
= NULL
;
17062 ex_off
.X_add_number
= mips_cpreturn_offset
;
17064 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17065 BFD_RELOC_LO16
, SP
);
17068 move_register (mips_cpreturn_register
, mips_gp_register
);
17070 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17072 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17073 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17076 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17077 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17078 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17080 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17081 mips_gp_register
, reg1
);
17087 ex
.X_op
= O_symbol
;
17088 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17089 ex
.X_op_symbol
= NULL
;
17090 ex
.X_add_number
= 0;
17092 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17093 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17095 macro_build_lui (&ex
, mips_gp_register
);
17096 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17097 mips_gp_register
, BFD_RELOC_LO16
);
17102 mips_assembling_insn
= FALSE
;
17103 demand_empty_rest_of_line ();
17107 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17109 file_mips_check_options ();
17111 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17112 .cplocal is ignored. */
17113 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17119 if (mips_opts
.mips16
)
17121 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17122 ignore_rest_of_line ();
17126 mips_gp_register
= tc_get_register (0);
17127 demand_empty_rest_of_line ();
17130 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17131 offset from $sp. The offset is remembered, and after making a PIC
17132 call $gp is restored from that location. */
17135 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17139 file_mips_check_options ();
17141 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17142 .cprestore is ignored. */
17143 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17149 if (mips_opts
.mips16
)
17151 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17152 ignore_rest_of_line ();
17156 mips_cprestore_offset
= get_absolute_expression ();
17157 mips_cprestore_valid
= 1;
17159 ex
.X_op
= O_constant
;
17160 ex
.X_add_symbol
= NULL
;
17161 ex
.X_op_symbol
= NULL
;
17162 ex
.X_add_number
= mips_cprestore_offset
;
17164 mips_mark_labels ();
17165 mips_assembling_insn
= TRUE
;
17168 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17169 SP
, HAVE_64BIT_ADDRESSES
);
17172 mips_assembling_insn
= FALSE
;
17173 demand_empty_rest_of_line ();
17176 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17177 was given in the preceding .cpsetup, it results in:
17178 ld $gp, offset($sp)
17180 If a register $reg2 was given there, it results in:
17181 or $gp, $reg2, $0 */
17184 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17188 file_mips_check_options ();
17190 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17191 We also need NewABI support. */
17192 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17198 if (mips_opts
.mips16
)
17200 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17201 ignore_rest_of_line ();
17205 mips_mark_labels ();
17206 mips_assembling_insn
= TRUE
;
17209 if (mips_cpreturn_register
== -1)
17211 ex
.X_op
= O_constant
;
17212 ex
.X_add_symbol
= NULL
;
17213 ex
.X_op_symbol
= NULL
;
17214 ex
.X_add_number
= mips_cpreturn_offset
;
17216 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17219 move_register (mips_gp_register
, mips_cpreturn_register
);
17223 mips_assembling_insn
= FALSE
;
17224 demand_empty_rest_of_line ();
17227 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17228 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17229 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17230 debug information or MIPS16 TLS. */
17233 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17234 bfd_reloc_code_real_type rtype
)
17241 if (ex
.X_op
!= O_symbol
)
17243 as_bad (_("unsupported use of %s"), dirstr
);
17244 ignore_rest_of_line ();
17247 p
= frag_more (bytes
);
17248 md_number_to_chars (p
, 0, bytes
);
17249 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17250 demand_empty_rest_of_line ();
17251 mips_clear_insn_labels ();
17254 /* Handle .dtprelword. */
17257 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17259 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17262 /* Handle .dtpreldword. */
17265 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17267 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17270 /* Handle .tprelword. */
17273 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17275 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17278 /* Handle .tpreldword. */
17281 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17283 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17286 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17287 code. It sets the offset to use in gp_rel relocations. */
17290 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17292 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17293 We also need NewABI support. */
17294 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17300 mips_gprel_offset
= get_absolute_expression ();
17302 demand_empty_rest_of_line ();
17305 /* Handle the .gpword pseudo-op. This is used when generating PIC
17306 code. It generates a 32 bit GP relative reloc. */
17309 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17311 segment_info_type
*si
;
17312 struct insn_label_list
*l
;
17316 /* When not generating PIC code, this is treated as .word. */
17317 if (mips_pic
!= SVR4_PIC
)
17323 si
= seg_info (now_seg
);
17324 l
= si
->label_list
;
17325 mips_emit_delays ();
17327 mips_align (2, 0, l
);
17330 mips_clear_insn_labels ();
17332 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17334 as_bad (_("unsupported use of .gpword"));
17335 ignore_rest_of_line ();
17339 md_number_to_chars (p
, 0, 4);
17340 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17341 BFD_RELOC_GPREL32
);
17343 demand_empty_rest_of_line ();
17347 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17349 segment_info_type
*si
;
17350 struct insn_label_list
*l
;
17354 /* When not generating PIC code, this is treated as .dword. */
17355 if (mips_pic
!= SVR4_PIC
)
17361 si
= seg_info (now_seg
);
17362 l
= si
->label_list
;
17363 mips_emit_delays ();
17365 mips_align (3, 0, l
);
17368 mips_clear_insn_labels ();
17370 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17372 as_bad (_("unsupported use of .gpdword"));
17373 ignore_rest_of_line ();
17377 md_number_to_chars (p
, 0, 8);
17378 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17379 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17381 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17382 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17383 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17385 demand_empty_rest_of_line ();
17388 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17389 tables. It generates a R_MIPS_EH reloc. */
17392 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17397 mips_emit_delays ();
17400 mips_clear_insn_labels ();
17402 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17404 as_bad (_("unsupported use of .ehword"));
17405 ignore_rest_of_line ();
17409 md_number_to_chars (p
, 0, 4);
17410 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17411 BFD_RELOC_32_PCREL
);
17413 demand_empty_rest_of_line ();
17416 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17417 tables in SVR4 PIC code. */
17420 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17424 file_mips_check_options ();
17426 /* This is ignored when not generating SVR4 PIC code. */
17427 if (mips_pic
!= SVR4_PIC
)
17433 mips_mark_labels ();
17434 mips_assembling_insn
= TRUE
;
17436 /* Add $gp to the register named as an argument. */
17438 reg
= tc_get_register (0);
17439 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17442 mips_assembling_insn
= FALSE
;
17443 demand_empty_rest_of_line ();
17446 /* Handle the .insn pseudo-op. This marks instruction labels in
17447 mips16/micromips mode. This permits the linker to handle them specially,
17448 such as generating jalx instructions when needed. We also make
17449 them odd for the duration of the assembly, in order to generate the
17450 right sort of code. We will make them even in the adjust_symtab
17451 routine, while leaving them marked. This is convenient for the
17452 debugger and the disassembler. The linker knows to make them odd
17456 s_insn (int ignore ATTRIBUTE_UNUSED
)
17458 file_mips_check_options ();
17459 file_ase_mips16
|= mips_opts
.mips16
;
17460 file_ase_micromips
|= mips_opts
.micromips
;
17462 mips_mark_labels ();
17464 demand_empty_rest_of_line ();
17467 /* Handle the .nan pseudo-op. */
17470 s_nan (int ignore ATTRIBUTE_UNUSED
)
17472 static const char str_legacy
[] = "legacy";
17473 static const char str_2008
[] = "2008";
17476 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17478 if (i
== sizeof (str_2008
) - 1
17479 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17481 else if (i
== sizeof (str_legacy
) - 1
17482 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17484 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17487 as_bad (_("`%s' does not support legacy NaN"),
17488 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17491 as_bad (_("bad .nan directive"));
17493 input_line_pointer
+= i
;
17494 demand_empty_rest_of_line ();
17497 /* Handle a .stab[snd] directive. Ideally these directives would be
17498 implemented in a transparent way, so that removing them would not
17499 have any effect on the generated instructions. However, s_stab
17500 internally changes the section, so in practice we need to decide
17501 now whether the preceding label marks compressed code. We do not
17502 support changing the compression mode of a label after a .stab*
17503 directive, such as in:
17509 so the current mode wins. */
17512 s_mips_stab (int type
)
17514 file_mips_check_options ();
17515 mips_mark_labels ();
17519 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17522 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17529 c
= get_symbol_name (&name
);
17530 symbolP
= symbol_find_or_make (name
);
17531 S_SET_WEAK (symbolP
);
17532 *input_line_pointer
= c
;
17534 SKIP_WHITESPACE_AFTER_NAME ();
17536 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17538 if (S_IS_DEFINED (symbolP
))
17540 as_bad (_("ignoring attempt to redefine symbol %s"),
17541 S_GET_NAME (symbolP
));
17542 ignore_rest_of_line ();
17546 if (*input_line_pointer
== ',')
17548 ++input_line_pointer
;
17549 SKIP_WHITESPACE ();
17553 if (exp
.X_op
!= O_symbol
)
17555 as_bad (_("bad .weakext directive"));
17556 ignore_rest_of_line ();
17559 symbol_set_value_expression (symbolP
, &exp
);
17562 demand_empty_rest_of_line ();
17565 /* Parse a register string into a number. Called from the ECOFF code
17566 to parse .frame. The argument is non-zero if this is the frame
17567 register, so that we can record it in mips_frame_reg. */
17570 tc_get_register (int frame
)
17574 SKIP_WHITESPACE ();
17575 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17579 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17580 mips_frame_reg_valid
= 1;
17581 mips_cprestore_valid
= 0;
17587 md_section_align (asection
*seg
, valueT addr
)
17589 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17591 /* We don't need to align ELF sections to the full alignment.
17592 However, Irix 5 may prefer that we align them at least to a 16
17593 byte boundary. We don't bother to align the sections if we
17594 are targeted for an embedded system. */
17595 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17600 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17603 /* Utility routine, called from above as well. If called while the
17604 input file is still being read, it's only an approximation. (For
17605 example, a symbol may later become defined which appeared to be
17606 undefined earlier.) */
17609 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17614 if (g_switch_value
> 0)
17616 const char *symname
;
17619 /* Find out whether this symbol can be referenced off the $gp
17620 register. It can be if it is smaller than the -G size or if
17621 it is in the .sdata or .sbss section. Certain symbols can
17622 not be referenced off the $gp, although it appears as though
17624 symname
= S_GET_NAME (sym
);
17625 if (symname
!= (const char *) NULL
17626 && (strcmp (symname
, "eprol") == 0
17627 || strcmp (symname
, "etext") == 0
17628 || strcmp (symname
, "_gp") == 0
17629 || strcmp (symname
, "edata") == 0
17630 || strcmp (symname
, "_fbss") == 0
17631 || strcmp (symname
, "_fdata") == 0
17632 || strcmp (symname
, "_ftext") == 0
17633 || strcmp (symname
, "end") == 0
17634 || strcmp (symname
, "_gp_disp") == 0))
17636 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17638 #ifndef NO_ECOFF_DEBUGGING
17639 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17640 && (symbol_get_obj (sym
)->ecoff_extern_size
17641 <= g_switch_value
))
17643 /* We must defer this decision until after the whole
17644 file has been read, since there might be a .extern
17645 after the first use of this symbol. */
17646 || (before_relaxing
17647 #ifndef NO_ECOFF_DEBUGGING
17648 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17650 && S_GET_VALUE (sym
) == 0)
17651 || (S_GET_VALUE (sym
) != 0
17652 && S_GET_VALUE (sym
) <= g_switch_value
)))
17656 const char *segname
;
17658 segname
= segment_name (S_GET_SEGMENT (sym
));
17659 gas_assert (strcmp (segname
, ".lit8") != 0
17660 && strcmp (segname
, ".lit4") != 0);
17661 change
= (strcmp (segname
, ".sdata") != 0
17662 && strcmp (segname
, ".sbss") != 0
17663 && strncmp (segname
, ".sdata.", 7) != 0
17664 && strncmp (segname
, ".sbss.", 6) != 0
17665 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17666 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17671 /* We are not optimizing for the $gp register. */
17676 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17679 pic_need_relax (symbolS
*sym
)
17683 /* Handle the case of a symbol equated to another symbol. */
17684 while (symbol_equated_reloc_p (sym
))
17688 /* It's possible to get a loop here in a badly written program. */
17689 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17695 if (symbol_section_p (sym
))
17698 symsec
= S_GET_SEGMENT (sym
);
17700 /* This must duplicate the test in adjust_reloc_syms. */
17701 return (!bfd_is_und_section (symsec
)
17702 && !bfd_is_abs_section (symsec
)
17703 && !bfd_is_com_section (symsec
)
17704 /* A global or weak symbol is treated as external. */
17705 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17708 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17709 convert a section-relative value VAL to the equivalent PC-relative
17713 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17714 offsetT val
, long stretch
)
17719 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17721 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17723 /* If the relax_marker of the symbol fragment differs from the
17724 relax_marker of this fragment, we have not yet adjusted the
17725 symbol fragment fr_address. We want to add in STRETCH in
17726 order to get a better estimate of the address. This
17727 particularly matters because of the shift bits. */
17728 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17732 /* Adjust stretch for any alignment frag. Note that if have
17733 been expanding the earlier code, the symbol may be
17734 defined in what appears to be an earlier frag. FIXME:
17735 This doesn't handle the fr_subtype field, which specifies
17736 a maximum number of bytes to skip when doing an
17738 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17740 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17743 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17745 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17754 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17756 /* The base address rules are complicated. The base address of
17757 a branch is the following instruction. The base address of a
17758 PC relative load or add is the instruction itself, but if it
17759 is in a delay slot (in which case it can not be extended) use
17760 the address of the instruction whose delay slot it is in. */
17761 if (pcrel_op
->include_isa_bit
)
17765 /* If we are currently assuming that this frag should be
17766 extended, then the current address is two bytes higher. */
17767 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17770 /* Ignore the low bit in the target, since it will be set
17771 for a text label. */
17774 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17776 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17779 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17784 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17785 extended opcode. SEC is the section the frag is in. */
17788 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17790 const struct mips_int_operand
*operand
;
17795 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17797 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17800 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17801 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17802 operand
= mips16_immed_operand (type
, FALSE
);
17803 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17804 || (operand
->root
.type
== OP_PCREL
17806 : !bfd_is_abs_section (symsec
)))
17809 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17811 if (operand
->root
.type
== OP_PCREL
)
17813 const struct mips_pcrel_operand
*pcrel_op
;
17816 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17819 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17820 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17822 /* If any of the shifted bits are set, we must use an extended
17823 opcode. If the address depends on the size of this
17824 instruction, this can lead to a loop, so we arrange to always
17825 use an extended opcode. */
17826 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17828 fragp
->fr_subtype
=
17829 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17833 /* If we are about to mark a frag as extended because the value
17834 is precisely the next value above maxtiny, then there is a
17835 chance of an infinite loop as in the following code:
17840 In this case when the la is extended, foo is 0x3fc bytes
17841 away, so the la can be shrunk, but then foo is 0x400 away, so
17842 the la must be extended. To avoid this loop, we mark the
17843 frag as extended if it was small, and is about to become
17844 extended with the next value above maxtiny. */
17845 maxtiny
= mips_int_operand_max (operand
);
17846 if (val
== maxtiny
+ (1 << operand
->shift
)
17847 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17849 fragp
->fr_subtype
=
17850 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17855 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17858 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17859 macro expansion. SEC is the section the frag is in. We only
17860 support PC-relative instructions (LA, DLA, LW, LD) here, in
17861 non-PIC code using 32-bit addressing. */
17864 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17866 const struct mips_pcrel_operand
*pcrel_op
;
17867 const struct mips_int_operand
*operand
;
17872 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17874 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17876 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17879 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17885 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17886 if (bfd_is_abs_section (symsec
))
17888 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17890 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17893 operand
= mips16_immed_operand (type
, TRUE
);
17894 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17895 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17896 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17898 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17905 /* Compute the length of a branch sequence, and adjust the
17906 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17907 worst-case length is computed, with UPDATE being used to indicate
17908 whether an unconditional (-1), branch-likely (+1) or regular (0)
17909 branch is to be computed. */
17911 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17913 bfd_boolean toofar
;
17917 && S_IS_DEFINED (fragp
->fr_symbol
)
17918 && !S_IS_WEAK (fragp
->fr_symbol
)
17919 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17924 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17926 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17930 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17933 /* If the symbol is not defined or it's in a different segment,
17934 we emit the long sequence. */
17937 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17939 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17940 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17941 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17942 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17943 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17949 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17952 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17954 /* Additional space for PIC loading of target address. */
17956 if (mips_opts
.isa
== ISA_MIPS1
)
17957 /* Additional space for $at-stabilizing nop. */
17961 /* If branch is conditional. */
17962 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17969 /* Get a FRAG's branch instruction delay slot size, either from the
17970 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17971 or SHORT_INSN_SIZE otherwise. */
17974 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17976 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17979 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17981 return short_insn_size
;
17984 /* Compute the length of a branch sequence, and adjust the
17985 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17986 worst-case length is computed, with UPDATE being used to indicate
17987 whether an unconditional (-1), or regular (0) branch is to be
17991 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17993 bfd_boolean insn32
= TRUE
;
17994 bfd_boolean nods
= TRUE
;
17995 bfd_boolean pic
= TRUE
;
17996 bfd_boolean al
= TRUE
;
17997 int short_insn_size
;
17998 bfd_boolean toofar
;
18003 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18004 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18005 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18006 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18008 short_insn_size
= insn32
? 4 : 2;
18011 && S_IS_DEFINED (fragp
->fr_symbol
)
18012 && !S_IS_WEAK (fragp
->fr_symbol
)
18013 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18018 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18019 /* Ignore the low bit in the target, since it will be set
18020 for a text label. */
18021 if ((val
& 1) != 0)
18024 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18028 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18031 /* If the symbol is not defined or it's in a different segment,
18032 we emit the long sequence. */
18035 if (fragp
&& update
18036 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18037 fragp
->fr_subtype
= (toofar
18038 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18039 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18044 bfd_boolean compact_known
= fragp
!= NULL
;
18045 bfd_boolean compact
= FALSE
;
18046 bfd_boolean uncond
;
18050 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18051 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18054 uncond
= update
< 0;
18056 /* If label is out of range, we turn branch <br>:
18058 <br> label # 4 bytes
18065 # compact && (!PIC || insn32)
18068 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18069 length
+= short_insn_size
;
18071 /* If assembling PIC code, we further turn:
18077 lw/ld at, %got(label)(gp) # 4 bytes
18078 d/addiu at, %lo(label) # 4 bytes
18079 jr/c at # 2/4 bytes
18082 length
+= 4 + short_insn_size
;
18084 /* Add an extra nop if the jump has no compact form and we need
18085 to fill the delay slot. */
18086 if ((!pic
|| al
) && nods
)
18088 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18089 : short_insn_size
);
18091 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18093 <brneg> 0f # 4 bytes
18094 nop # 2/4 bytes if !compact
18097 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18101 /* Add an extra nop to fill the delay slot. */
18102 gas_assert (fragp
);
18103 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18109 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18110 bit accordingly. */
18113 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18115 bfd_boolean toofar
;
18118 && S_IS_DEFINED (fragp
->fr_symbol
)
18119 && !S_IS_WEAK (fragp
->fr_symbol
)
18120 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18126 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18127 /* Ignore the low bit in the target, since it will be set
18128 for a text label. */
18129 if ((val
& 1) != 0)
18132 /* Assume this is a 2-byte branch. */
18133 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18135 /* We try to avoid the infinite loop by not adding 2 more bytes for
18140 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18142 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18143 else if (type
== 'E')
18144 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18149 /* If the symbol is not defined or it's in a different segment,
18150 we emit a normal 32-bit branch. */
18153 if (fragp
&& update
18154 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18156 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18157 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18165 /* Estimate the size of a frag before relaxing. Unless this is the
18166 mips16, we are not really relaxing here, and the final size is
18167 encoded in the subtype information. For the mips16, we have to
18168 decide whether we are using an extended opcode or not. */
18171 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18175 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18178 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18180 return fragp
->fr_var
;
18183 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18185 /* We don't want to modify the EXTENDED bit here; it might get us
18186 into infinite loops. We change it only in mips_relax_frag(). */
18187 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18188 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18190 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18193 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18197 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18198 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18199 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18200 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18201 fragp
->fr_var
= length
;
18206 if (mips_pic
== VXWORKS_PIC
)
18207 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18209 else if (RELAX_PIC (fragp
->fr_subtype
))
18210 change
= pic_need_relax (fragp
->fr_symbol
);
18212 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18216 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18217 return -RELAX_FIRST (fragp
->fr_subtype
);
18220 return -RELAX_SECOND (fragp
->fr_subtype
);
18223 /* This is called to see whether a reloc against a defined symbol
18224 should be converted into a reloc against a section. */
18227 mips_fix_adjustable (fixS
*fixp
)
18229 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18230 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18233 if (fixp
->fx_addsy
== NULL
)
18236 /* Allow relocs used for EH tables. */
18237 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18240 /* If symbol SYM is in a mergeable section, relocations of the form
18241 SYM + 0 can usually be made section-relative. The mergeable data
18242 is then identified by the section offset rather than by the symbol.
18244 However, if we're generating REL LO16 relocations, the offset is split
18245 between the LO16 and partnering high part relocation. The linker will
18246 need to recalculate the complete offset in order to correctly identify
18249 The linker has traditionally not looked for the partnering high part
18250 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18251 placed anywhere. Rather than break backwards compatibility by changing
18252 this, it seems better not to force the issue, and instead keep the
18253 original symbol. This will work with either linker behavior. */
18254 if ((lo16_reloc_p (fixp
->fx_r_type
)
18255 || reloc_needs_lo_p (fixp
->fx_r_type
))
18256 && HAVE_IN_PLACE_ADDENDS
18257 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18260 /* There is no place to store an in-place offset for JALR relocations. */
18261 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18264 /* Likewise an in-range offset of limited PC-relative relocations may
18265 overflow the in-place relocatable field if recalculated against the
18266 start address of the symbol's containing section.
18268 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18269 section relative to allow linker relaxations to be performed later on. */
18270 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18271 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18274 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18275 to a floating-point stub. The same is true for non-R_MIPS16_26
18276 relocations against MIPS16 functions; in this case, the stub becomes
18277 the function's canonical address.
18279 Floating-point stubs are stored in unique .mips16.call.* or
18280 .mips16.fn.* sections. If a stub T for function F is in section S,
18281 the first relocation in section S must be against F; this is how the
18282 linker determines the target function. All relocations that might
18283 resolve to T must also be against F. We therefore have the following
18284 restrictions, which are given in an intentionally-redundant way:
18286 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18289 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18290 if that stub might be used.
18292 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18295 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18296 that stub might be used.
18298 There is a further restriction:
18300 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18301 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18302 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18303 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18304 against MIPS16 or microMIPS symbols because we need to keep the
18305 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18306 detection and JAL or BAL to JALX instruction conversion in the
18309 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18310 against a MIPS16 symbol. We deal with (5) by additionally leaving
18311 alone any jump and branch relocations against a microMIPS symbol.
18313 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18314 relocation against some symbol R, no relocation against R may be
18315 reduced. (Note that this deals with (2) as well as (1) because
18316 relocations against global symbols will never be reduced on ELF
18317 targets.) This approach is a little simpler than trying to detect
18318 stub sections, and gives the "all or nothing" per-symbol consistency
18319 that we have for MIPS16 symbols. */
18320 if (fixp
->fx_subsy
== NULL
18321 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18322 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18323 && (jmp_reloc_p (fixp
->fx_r_type
)
18324 || b_reloc_p (fixp
->fx_r_type
)))
18325 || *symbol_get_tc (fixp
->fx_addsy
)))
18331 /* Translate internal representation of relocation info to BFD target
18335 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18337 static arelent
*retval
[4];
18339 bfd_reloc_code_real_type code
;
18341 memset (retval
, 0, sizeof(retval
));
18342 reloc
= retval
[0] = XCNEW (arelent
);
18343 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18344 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18345 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18347 if (fixp
->fx_pcrel
)
18349 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18350 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18351 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18352 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18353 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18354 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18355 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18356 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18357 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18358 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18359 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18360 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18362 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18363 Relocations want only the symbol offset. */
18364 switch (fixp
->fx_r_type
)
18366 case BFD_RELOC_MIPS_18_PCREL_S3
:
18367 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18370 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18374 else if (HAVE_IN_PLACE_ADDENDS
18375 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18376 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18377 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18379 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18380 addend accordingly. */
18381 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18384 reloc
->addend
= fixp
->fx_addnumber
;
18386 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18387 entry to be used in the relocation's section offset. */
18388 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18390 reloc
->address
= reloc
->addend
;
18394 code
= fixp
->fx_r_type
;
18396 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18397 if (reloc
->howto
== NULL
)
18399 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18400 _("cannot represent %s relocation in this object file"
18402 bfd_get_reloc_code_name (code
));
18409 /* Relax a machine dependent frag. This returns the amount by which
18410 the current size of the frag should change. */
18413 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18415 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18417 offsetT old_var
= fragp
->fr_var
;
18419 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18421 return fragp
->fr_var
- old_var
;
18424 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18426 offsetT old_var
= fragp
->fr_var
;
18427 offsetT new_var
= 4;
18429 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18430 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18431 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18432 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18433 fragp
->fr_var
= new_var
;
18435 return new_var
- old_var
;
18438 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18441 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18443 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18445 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18446 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18448 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18450 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18456 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18458 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18460 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18461 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18462 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18464 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18466 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18474 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18476 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18478 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18479 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18480 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18484 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18485 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18492 /* Convert a machine dependent frag. */
18495 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18497 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18500 unsigned long insn
;
18503 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18504 insn
= read_insn (buf
);
18506 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18508 /* We generate a fixup instead of applying it right now
18509 because, if there are linker relaxations, we're going to
18510 need the relocations. */
18511 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18512 fragp
->fr_symbol
, fragp
->fr_offset
,
18513 TRUE
, BFD_RELOC_16_PCREL_S2
);
18514 fixp
->fx_file
= fragp
->fr_file
;
18515 fixp
->fx_line
= fragp
->fr_line
;
18517 buf
= write_insn (buf
, insn
);
18523 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18524 _("relaxed out-of-range branch into a jump"));
18526 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18529 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18531 /* Reverse the branch. */
18532 switch ((insn
>> 28) & 0xf)
18535 if ((insn
& 0xff000000) == 0x47000000
18536 || (insn
& 0xff600000) == 0x45600000)
18538 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18539 reversed by tweaking bit 23. */
18540 insn
^= 0x00800000;
18544 /* bc[0-3][tf]l? instructions can have the condition
18545 reversed by tweaking a single TF bit, and their
18546 opcodes all have 0x4???????. */
18547 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18548 insn
^= 0x00010000;
18553 /* bltz 0x04000000 bgez 0x04010000
18554 bltzal 0x04100000 bgezal 0x04110000 */
18555 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18556 insn
^= 0x00010000;
18560 /* beq 0x10000000 bne 0x14000000
18561 blez 0x18000000 bgtz 0x1c000000 */
18562 insn
^= 0x04000000;
18570 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18572 /* Clear the and-link bit. */
18573 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18575 /* bltzal 0x04100000 bgezal 0x04110000
18576 bltzall 0x04120000 bgezall 0x04130000 */
18577 insn
&= ~0x00100000;
18580 /* Branch over the branch (if the branch was likely) or the
18581 full jump (not likely case). Compute the offset from the
18582 current instruction to branch to. */
18583 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18587 /* How many bytes in instructions we've already emitted? */
18588 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18589 /* How many bytes in instructions from here to the end? */
18590 i
= fragp
->fr_var
- i
;
18592 /* Convert to instruction count. */
18594 /* Branch counts from the next instruction. */
18597 /* Branch over the jump. */
18598 buf
= write_insn (buf
, insn
);
18601 buf
= write_insn (buf
, 0);
18603 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18605 /* beql $0, $0, 2f */
18607 /* Compute the PC offset from the current instruction to
18608 the end of the variable frag. */
18609 /* How many bytes in instructions we've already emitted? */
18610 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18611 /* How many bytes in instructions from here to the end? */
18612 i
= fragp
->fr_var
- i
;
18613 /* Convert to instruction count. */
18615 /* Don't decrement i, because we want to branch over the
18619 buf
= write_insn (buf
, insn
);
18620 buf
= write_insn (buf
, 0);
18624 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18627 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18628 ? 0x0c000000 : 0x08000000);
18630 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18631 fragp
->fr_symbol
, fragp
->fr_offset
,
18632 FALSE
, BFD_RELOC_MIPS_JMP
);
18633 fixp
->fx_file
= fragp
->fr_file
;
18634 fixp
->fx_line
= fragp
->fr_line
;
18636 buf
= write_insn (buf
, insn
);
18640 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18642 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18643 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18644 insn
|= at
<< OP_SH_RT
;
18646 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18647 fragp
->fr_symbol
, fragp
->fr_offset
,
18648 FALSE
, BFD_RELOC_MIPS_GOT16
);
18649 fixp
->fx_file
= fragp
->fr_file
;
18650 fixp
->fx_line
= fragp
->fr_line
;
18652 buf
= write_insn (buf
, insn
);
18654 if (mips_opts
.isa
== ISA_MIPS1
)
18656 buf
= write_insn (buf
, 0);
18658 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18659 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18660 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18662 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18663 fragp
->fr_symbol
, fragp
->fr_offset
,
18664 FALSE
, BFD_RELOC_LO16
);
18665 fixp
->fx_file
= fragp
->fr_file
;
18666 fixp
->fx_line
= fragp
->fr_line
;
18668 buf
= write_insn (buf
, insn
);
18671 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18675 insn
|= at
<< OP_SH_RS
;
18677 buf
= write_insn (buf
, insn
);
18681 fragp
->fr_fix
+= fragp
->fr_var
;
18682 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18686 /* Relax microMIPS branches. */
18687 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18689 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18690 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18691 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18692 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18693 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18694 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18695 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18696 bfd_boolean short_ds
;
18697 unsigned long insn
;
18700 fragp
->fr_fix
+= fragp
->fr_var
;
18702 /* Handle 16-bit branches that fit or are forced to fit. */
18703 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18705 /* We generate a fixup instead of applying it right now,
18706 because if there is linker relaxation, we're going to
18707 need the relocations. */
18711 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18712 fragp
->fr_symbol
, fragp
->fr_offset
,
18713 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18716 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18717 fragp
->fr_symbol
, fragp
->fr_offset
,
18718 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18724 fixp
->fx_file
= fragp
->fr_file
;
18725 fixp
->fx_line
= fragp
->fr_line
;
18727 /* These relocations can have an addend that won't fit in
18729 fixp
->fx_no_overflow
= 1;
18734 /* Handle 32-bit branches that fit or are forced to fit. */
18735 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18736 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18738 /* We generate a fixup instead of applying it right now,
18739 because if there is linker relaxation, we're going to
18740 need the relocations. */
18741 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18742 fragp
->fr_symbol
, fragp
->fr_offset
,
18743 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18744 fixp
->fx_file
= fragp
->fr_file
;
18745 fixp
->fx_line
= fragp
->fr_line
;
18749 insn
= read_compressed_insn (buf
, 4);
18754 /* Check the short-delay-slot bit. */
18755 if (!al
|| (insn
& 0x02000000) != 0)
18756 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18758 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18761 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18766 /* Relax 16-bit branches to 32-bit branches. */
18769 insn
= read_compressed_insn (buf
, 2);
18771 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18772 insn
= 0x94000000; /* beq */
18773 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18775 unsigned long regno
;
18777 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18778 regno
= micromips_to_32_reg_d_map
[regno
];
18779 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18780 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18785 /* Nothing else to do, just write it out. */
18786 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18787 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18789 buf
= write_compressed_insn (buf
, insn
, 4);
18791 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18792 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18797 insn
= read_compressed_insn (buf
, 4);
18799 /* Relax 32-bit branches to a sequence of instructions. */
18800 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18801 _("relaxed out-of-range branch into a jump"));
18803 /* Set the short-delay-slot bit. */
18804 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18806 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18810 /* Reverse the branch. */
18811 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18812 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18813 insn
^= 0x20000000;
18814 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18815 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18816 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18817 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18818 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18819 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18820 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18821 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18822 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18823 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18824 insn
^= 0x00400000;
18825 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18826 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18827 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18828 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18829 insn
^= 0x00200000;
18830 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18832 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18834 insn
^= 0x00800000;
18840 /* Clear the and-link and short-delay-slot bits. */
18841 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18843 /* bltzal 0x40200000 bgezal 0x40600000 */
18844 /* bltzals 0x42200000 bgezals 0x42600000 */
18845 insn
&= ~0x02200000;
18848 /* Make a label at the end for use with the branch. */
18849 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18850 micromips_label_inc ();
18851 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18854 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18855 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18856 fixp
->fx_file
= fragp
->fr_file
;
18857 fixp
->fx_line
= fragp
->fr_line
;
18859 /* Branch over the jump. */
18860 buf
= write_compressed_insn (buf
, insn
, 4);
18866 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18868 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18874 unsigned long jal
= (short_ds
|| nods
18875 ? 0x74000000 : 0xf4000000); /* jal/s */
18877 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18878 insn
= al
? jal
: 0xd4000000;
18880 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18881 fragp
->fr_symbol
, fragp
->fr_offset
,
18882 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18883 fixp
->fx_file
= fragp
->fr_file
;
18884 fixp
->fx_line
= fragp
->fr_line
;
18886 buf
= write_compressed_insn (buf
, insn
, 4);
18888 if (compact
|| nods
)
18892 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18894 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18899 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18901 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18902 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18903 insn
|= at
<< MICROMIPSOP_SH_RT
;
18905 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18906 fragp
->fr_symbol
, fragp
->fr_offset
,
18907 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18908 fixp
->fx_file
= fragp
->fr_file
;
18909 fixp
->fx_line
= fragp
->fr_line
;
18911 buf
= write_compressed_insn (buf
, insn
, 4);
18913 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18914 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18915 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18917 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18918 fragp
->fr_symbol
, fragp
->fr_offset
,
18919 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18920 fixp
->fx_file
= fragp
->fr_file
;
18921 fixp
->fx_line
= fragp
->fr_line
;
18923 buf
= write_compressed_insn (buf
, insn
, 4);
18928 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18929 insn
|= at
<< MICROMIPSOP_SH_RS
;
18931 buf
= write_compressed_insn (buf
, insn
, 4);
18933 if (compact
|| nods
)
18935 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18939 /* jr/jrc/jalr/jalrs $at */
18940 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18941 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18943 insn
= al
? jalr
: jr
;
18944 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18946 buf
= write_compressed_insn (buf
, insn
, 2);
18951 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18953 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18958 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18962 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18965 const struct mips_int_operand
*operand
;
18968 unsigned int user_length
;
18969 bfd_boolean need_reloc
;
18970 unsigned long insn
;
18975 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18976 operand
= mips16_immed_operand (type
, FALSE
);
18978 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18979 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18980 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18982 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18983 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18984 || (operand
->root
.type
== OP_PCREL
&& !mac
18986 : !bfd_is_abs_section (symsec
)));
18988 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18990 const struct mips_pcrel_operand
*pcrel_op
;
18992 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18994 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18996 if (!mips_ignore_branch_isa
18997 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18998 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18999 _("branch to a symbol in another ISA mode"));
19000 else if ((fragp
->fr_offset
& 0x1) != 0)
19001 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19002 _("branch to misaligned address (0x%lx)"),
19006 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19008 /* Make sure the section winds up with the alignment we have
19010 if (operand
->shift
> 0)
19011 record_alignment (asec
, operand
->shift
);
19014 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19015 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19018 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19019 _("macro instruction expanded into multiple "
19020 "instructions in a branch delay slot"));
19022 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19023 _("extended instruction in a branch delay slot"));
19025 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19026 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19027 _("macro instruction expanded into multiple "
19030 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19032 insn
= read_compressed_insn (buf
, 2);
19034 insn
|= MIPS16_EXTEND
;
19036 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19038 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19050 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19051 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19053 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19059 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19061 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19062 fragp
->fr_symbol
, fragp
->fr_offset
,
19063 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
19064 fixp
->fx_file
= fragp
->fr_file
;
19065 fixp
->fx_line
= fragp
->fr_line
;
19067 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19068 fragp
->fr_symbol
, fragp
->fr_offset
,
19069 FALSE
, BFD_RELOC_MIPS16_LO16
);
19070 fixp
->fx_file
= fragp
->fr_file
;
19071 fixp
->fx_line
= fragp
->fr_line
;
19076 switch (insn
& 0xf800)
19078 case 0x0800: /* ADDIU */
19079 reg
= (insn
>> 8) & 0x7;
19080 op
= 0xf0004800 | (reg
<< 8);
19082 case 0xb000: /* LW */
19083 reg
= (insn
>> 8) & 0x7;
19084 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19086 case 0xf800: /* I64 */
19087 reg
= (insn
>> 5) & 0x7;
19088 switch (insn
& 0x0700)
19090 case 0x0400: /* LD */
19091 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19093 case 0x0600: /* DADDIU */
19094 op
= 0xf000fd00 | (reg
<< 5);
19104 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19105 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19106 buf
= write_compressed_insn (buf
, new, 4);
19109 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19110 buf
= write_compressed_insn (buf
, new, 4);
19112 op
|= mips16_immed_extend (val
, 16);
19113 buf
= write_compressed_insn (buf
, op
, 4);
19115 fragp
->fr_fix
+= e2
? 8 : 12;
19119 unsigned int length
= ext
? 4 : 2;
19123 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19130 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19135 if (mac
|| reloc
== BFD_RELOC_NONE
)
19136 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19137 _("unsupported relocation"));
19140 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19141 fragp
->fr_symbol
, fragp
->fr_offset
,
19143 fixp
->fx_file
= fragp
->fr_file
;
19144 fixp
->fx_line
= fragp
->fr_line
;
19147 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19148 _("invalid unextended operand value"));
19151 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19152 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19154 gas_assert (mips16_opcode_length (insn
) == length
);
19155 write_compressed_insn (buf
, insn
, length
);
19156 fragp
->fr_fix
+= length
;
19161 relax_substateT subtype
= fragp
->fr_subtype
;
19162 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19163 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19164 unsigned int first
, second
;
19167 first
= RELAX_FIRST (subtype
);
19168 second
= RELAX_SECOND (subtype
);
19169 fixp
= (fixS
*) fragp
->fr_opcode
;
19171 /* If the delay slot chosen does not match the size of the instruction,
19172 then emit a warning. */
19173 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19174 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19179 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19180 | RELAX_DELAY_SLOT_SIZE_FIRST
19181 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19182 msg
= macro_warning (s
);
19184 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19188 /* Possibly emit a warning if we've chosen the longer option. */
19189 if (use_second
== second_longer
)
19195 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19196 msg
= macro_warning (s
);
19198 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19202 /* Go through all the fixups for the first sequence. Disable them
19203 (by marking them as done) if we're going to use the second
19204 sequence instead. */
19206 && fixp
->fx_frag
== fragp
19207 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19209 if (subtype
& RELAX_USE_SECOND
)
19211 fixp
= fixp
->fx_next
;
19214 /* Go through the fixups for the second sequence. Disable them if
19215 we're going to use the first sequence, otherwise adjust their
19216 addresses to account for the relaxation. */
19217 while (fixp
&& fixp
->fx_frag
== fragp
)
19219 if (subtype
& RELAX_USE_SECOND
)
19220 fixp
->fx_where
-= first
;
19223 fixp
= fixp
->fx_next
;
19226 /* Now modify the frag contents. */
19227 if (subtype
& RELAX_USE_SECOND
)
19231 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19232 memmove (start
, start
+ first
, second
);
19233 fragp
->fr_fix
-= first
;
19236 fragp
->fr_fix
-= second
;
19240 /* This function is called after the relocs have been generated.
19241 We've been storing mips16 text labels as odd. Here we convert them
19242 back to even for the convenience of the debugger. */
19245 mips_frob_file_after_relocs (void)
19248 unsigned int count
, i
;
19250 syms
= bfd_get_outsymbols (stdoutput
);
19251 count
= bfd_get_symcount (stdoutput
);
19252 for (i
= 0; i
< count
; i
++, syms
++)
19253 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19254 && ((*syms
)->value
& 1) != 0)
19256 (*syms
)->value
&= ~1;
19257 /* If the symbol has an odd size, it was probably computed
19258 incorrectly, so adjust that as well. */
19259 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19260 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19264 /* This function is called whenever a label is defined, including fake
19265 labels instantiated off the dot special symbol. It is used when
19266 handling branch delays; if a branch has a label, we assume we cannot
19267 move it. This also bumps the value of the symbol by 1 in compressed
19271 mips_record_label (symbolS
*sym
)
19273 segment_info_type
*si
= seg_info (now_seg
);
19274 struct insn_label_list
*l
;
19276 if (free_insn_labels
== NULL
)
19277 l
= XNEW (struct insn_label_list
);
19280 l
= free_insn_labels
;
19281 free_insn_labels
= l
->next
;
19285 l
->next
= si
->label_list
;
19286 si
->label_list
= l
;
19289 /* This function is called as tc_frob_label() whenever a label is defined
19290 and adds a DWARF-2 record we only want for true labels. */
19293 mips_define_label (symbolS
*sym
)
19295 mips_record_label (sym
);
19296 dwarf2_emit_label (sym
);
19299 /* This function is called by tc_new_dot_label whenever a new dot symbol
19303 mips_add_dot_label (symbolS
*sym
)
19305 mips_record_label (sym
);
19306 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19307 mips_compressed_mark_label (sym
);
19310 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19311 static unsigned int
19312 mips_convert_ase_flags (int ase
)
19314 unsigned int ext_ases
= 0;
19317 ext_ases
|= AFL_ASE_DSP
;
19318 if (ase
& ASE_DSPR2
)
19319 ext_ases
|= AFL_ASE_DSPR2
;
19320 if (ase
& ASE_DSPR3
)
19321 ext_ases
|= AFL_ASE_DSPR3
;
19323 ext_ases
|= AFL_ASE_EVA
;
19325 ext_ases
|= AFL_ASE_MCU
;
19326 if (ase
& ASE_MDMX
)
19327 ext_ases
|= AFL_ASE_MDMX
;
19328 if (ase
& ASE_MIPS3D
)
19329 ext_ases
|= AFL_ASE_MIPS3D
;
19331 ext_ases
|= AFL_ASE_MT
;
19332 if (ase
& ASE_SMARTMIPS
)
19333 ext_ases
|= AFL_ASE_SMARTMIPS
;
19334 if (ase
& ASE_VIRT
)
19335 ext_ases
|= AFL_ASE_VIRT
;
19337 ext_ases
|= AFL_ASE_MSA
;
19339 ext_ases
|= AFL_ASE_XPA
;
19340 if (ase
& ASE_MIPS16E2
)
19341 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19343 ext_ases
|= AFL_ASE_CRC
;
19344 if (ase
& ASE_GINV
)
19345 ext_ases
|= AFL_ASE_GINV
;
19346 if (ase
& ASE_LOONGSON_MMI
)
19347 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19348 if (ase
& ASE_LOONGSON_CAM
)
19349 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19350 if (ase
& ASE_LOONGSON_EXT
)
19351 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19352 if (ase
& ASE_LOONGSON_EXT2
)
19353 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19357 /* Some special processing for a MIPS ELF file. */
19360 mips_elf_final_processing (void)
19363 Elf_Internal_ABIFlags_v0 flags
;
19367 switch (file_mips_opts
.isa
)
19370 flags
.isa_level
= 1;
19373 flags
.isa_level
= 2;
19376 flags
.isa_level
= 3;
19379 flags
.isa_level
= 4;
19382 flags
.isa_level
= 5;
19385 flags
.isa_level
= 32;
19389 flags
.isa_level
= 32;
19393 flags
.isa_level
= 32;
19397 flags
.isa_level
= 32;
19401 flags
.isa_level
= 32;
19405 flags
.isa_level
= 64;
19409 flags
.isa_level
= 64;
19413 flags
.isa_level
= 64;
19417 flags
.isa_level
= 64;
19421 flags
.isa_level
= 64;
19426 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19427 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19428 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19429 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19431 flags
.cpr2_size
= AFL_REG_NONE
;
19432 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19433 Tag_GNU_MIPS_ABI_FP
);
19434 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19435 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19436 if (file_ase_mips16
)
19437 flags
.ases
|= AFL_ASE_MIPS16
;
19438 if (file_ase_micromips
)
19439 flags
.ases
|= AFL_ASE_MICROMIPS
;
19441 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19442 || file_mips_opts
.fp
== 64)
19443 && file_mips_opts
.oddspreg
)
19444 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19447 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19448 ((Elf_External_ABIFlags_v0
*)
19451 /* Write out the register information. */
19452 if (mips_abi
!= N64_ABI
)
19456 s
.ri_gprmask
= mips_gprmask
;
19457 s
.ri_cprmask
[0] = mips_cprmask
[0];
19458 s
.ri_cprmask
[1] = mips_cprmask
[1];
19459 s
.ri_cprmask
[2] = mips_cprmask
[2];
19460 s
.ri_cprmask
[3] = mips_cprmask
[3];
19461 /* The gp_value field is set by the MIPS ELF backend. */
19463 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19464 ((Elf32_External_RegInfo
*)
19465 mips_regmask_frag
));
19469 Elf64_Internal_RegInfo s
;
19471 s
.ri_gprmask
= mips_gprmask
;
19473 s
.ri_cprmask
[0] = mips_cprmask
[0];
19474 s
.ri_cprmask
[1] = mips_cprmask
[1];
19475 s
.ri_cprmask
[2] = mips_cprmask
[2];
19476 s
.ri_cprmask
[3] = mips_cprmask
[3];
19477 /* The gp_value field is set by the MIPS ELF backend. */
19479 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19480 ((Elf64_External_RegInfo
*)
19481 mips_regmask_frag
));
19484 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19485 sort of BFD interface for this. */
19486 if (mips_any_noreorder
)
19487 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19488 if (mips_pic
!= NO_PIC
)
19490 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19491 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19494 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19496 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19497 defined at present; this might need to change in future. */
19498 if (file_ase_mips16
)
19499 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19500 if (file_ase_micromips
)
19501 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19502 if (file_mips_opts
.ase
& ASE_MDMX
)
19503 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19505 /* Set the MIPS ELF ABI flags. */
19506 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19507 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19508 else if (mips_abi
== O64_ABI
)
19509 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19510 else if (mips_abi
== EABI_ABI
)
19512 if (file_mips_opts
.gp
== 64)
19513 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19515 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19518 /* Nothing to do for N32_ABI or N64_ABI. */
19520 if (mips_32bitmode
)
19521 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19523 if (mips_nan2008
== 1)
19524 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19526 /* 32 bit code with 64 bit FP registers. */
19527 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19528 Tag_GNU_MIPS_ABI_FP
);
19529 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19530 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19533 typedef struct proc
{
19535 symbolS
*func_end_sym
;
19536 unsigned long reg_mask
;
19537 unsigned long reg_offset
;
19538 unsigned long fpreg_mask
;
19539 unsigned long fpreg_offset
;
19540 unsigned long frame_offset
;
19541 unsigned long frame_reg
;
19542 unsigned long pc_reg
;
19545 static procS cur_proc
;
19546 static procS
*cur_proc_ptr
;
19547 static int numprocs
;
19549 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19550 as "2", and a normal nop as "0". */
19552 #define NOP_OPCODE_MIPS 0
19553 #define NOP_OPCODE_MIPS16 1
19554 #define NOP_OPCODE_MICROMIPS 2
19557 mips_nop_opcode (void)
19559 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19560 return NOP_OPCODE_MICROMIPS
;
19561 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19562 return NOP_OPCODE_MIPS16
;
19564 return NOP_OPCODE_MIPS
;
19567 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19568 32-bit microMIPS NOPs here (if applicable). */
19571 mips_handle_align (fragS
*fragp
)
19575 int bytes
, size
, excess
;
19578 if (fragp
->fr_type
!= rs_align_code
)
19581 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19583 switch (nop_opcode
)
19585 case NOP_OPCODE_MICROMIPS
:
19586 opcode
= micromips_nop32_insn
.insn_opcode
;
19589 case NOP_OPCODE_MIPS16
:
19590 opcode
= mips16_nop_insn
.insn_opcode
;
19593 case NOP_OPCODE_MIPS
:
19595 opcode
= nop_insn
.insn_opcode
;
19600 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19601 excess
= bytes
% size
;
19603 /* Handle the leading part if we're not inserting a whole number of
19604 instructions, and make it the end of the fixed part of the frag.
19605 Try to fit in a short microMIPS NOP if applicable and possible,
19606 and use zeroes otherwise. */
19607 gas_assert (excess
< 4);
19608 fragp
->fr_fix
+= excess
;
19613 /* Fall through. */
19615 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19617 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19621 /* Fall through. */
19624 /* Fall through. */
19629 md_number_to_chars (p
, opcode
, size
);
19630 fragp
->fr_var
= size
;
19639 if (*input_line_pointer
== '-')
19641 ++input_line_pointer
;
19644 if (!ISDIGIT (*input_line_pointer
))
19645 as_bad (_("expected simple number"));
19646 if (input_line_pointer
[0] == '0')
19648 if (input_line_pointer
[1] == 'x')
19650 input_line_pointer
+= 2;
19651 while (ISXDIGIT (*input_line_pointer
))
19654 val
|= hex_value (*input_line_pointer
++);
19656 return negative
? -val
: val
;
19660 ++input_line_pointer
;
19661 while (ISDIGIT (*input_line_pointer
))
19664 val
|= *input_line_pointer
++ - '0';
19666 return negative
? -val
: val
;
19669 if (!ISDIGIT (*input_line_pointer
))
19671 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19672 *input_line_pointer
, *input_line_pointer
);
19673 as_warn (_("invalid number"));
19676 while (ISDIGIT (*input_line_pointer
))
19679 val
+= *input_line_pointer
++ - '0';
19681 return negative
? -val
: val
;
19684 /* The .file directive; just like the usual .file directive, but there
19685 is an initial number which is the ECOFF file index. In the non-ECOFF
19686 case .file implies DWARF-2. */
19689 s_mips_file (int x ATTRIBUTE_UNUSED
)
19691 static int first_file_directive
= 0;
19693 if (ECOFF_DEBUGGING
)
19702 filename
= dwarf2_directive_filename ();
19704 /* Versions of GCC up to 3.1 start files with a ".file"
19705 directive even for stabs output. Make sure that this
19706 ".file" is handled. Note that you need a version of GCC
19707 after 3.1 in order to support DWARF-2 on MIPS. */
19708 if (filename
!= NULL
&& ! first_file_directive
)
19710 (void) new_logical_line (filename
, -1);
19711 s_app_file_string (filename
, 0);
19713 first_file_directive
= 1;
19717 /* The .loc directive, implying DWARF-2. */
19720 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19722 if (!ECOFF_DEBUGGING
)
19723 dwarf2_directive_loc (0);
19726 /* The .end directive. */
19729 s_mips_end (int x ATTRIBUTE_UNUSED
)
19733 /* Following functions need their own .frame and .cprestore directives. */
19734 mips_frame_reg_valid
= 0;
19735 mips_cprestore_valid
= 0;
19737 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19740 demand_empty_rest_of_line ();
19745 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19746 as_warn (_(".end not in text section"));
19750 as_warn (_(".end directive without a preceding .ent directive"));
19751 demand_empty_rest_of_line ();
19757 gas_assert (S_GET_NAME (p
));
19758 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19759 as_warn (_(".end symbol does not match .ent symbol"));
19761 if (debug_type
== DEBUG_STABS
)
19762 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19766 as_warn (_(".end directive missing or unknown symbol"));
19768 /* Create an expression to calculate the size of the function. */
19769 if (p
&& cur_proc_ptr
)
19771 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19772 expressionS
*exp
= XNEW (expressionS
);
19775 exp
->X_op
= O_subtract
;
19776 exp
->X_add_symbol
= symbol_temp_new_now ();
19777 exp
->X_op_symbol
= p
;
19778 exp
->X_add_number
= 0;
19780 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19783 #ifdef md_flush_pending_output
19784 md_flush_pending_output ();
19787 /* Generate a .pdr section. */
19788 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19790 segT saved_seg
= now_seg
;
19791 subsegT saved_subseg
= now_subseg
;
19795 gas_assert (pdr_seg
);
19796 subseg_set (pdr_seg
, 0);
19798 /* Write the symbol. */
19799 exp
.X_op
= O_symbol
;
19800 exp
.X_add_symbol
= p
;
19801 exp
.X_add_number
= 0;
19802 emit_expr (&exp
, 4);
19804 fragp
= frag_more (7 * 4);
19806 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19807 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19808 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19809 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19810 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19811 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19812 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19814 subseg_set (saved_seg
, saved_subseg
);
19817 cur_proc_ptr
= NULL
;
19820 /* The .aent and .ent directives. */
19823 s_mips_ent (int aent
)
19827 symbolP
= get_symbol ();
19828 if (*input_line_pointer
== ',')
19829 ++input_line_pointer
;
19830 SKIP_WHITESPACE ();
19831 if (ISDIGIT (*input_line_pointer
)
19832 || *input_line_pointer
== '-')
19835 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19836 as_warn (_(".ent or .aent not in text section"));
19838 if (!aent
&& cur_proc_ptr
)
19839 as_warn (_("missing .end"));
19843 /* This function needs its own .frame and .cprestore directives. */
19844 mips_frame_reg_valid
= 0;
19845 mips_cprestore_valid
= 0;
19847 cur_proc_ptr
= &cur_proc
;
19848 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19850 cur_proc_ptr
->func_sym
= symbolP
;
19854 if (debug_type
== DEBUG_STABS
)
19855 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19856 S_GET_NAME (symbolP
));
19859 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19861 demand_empty_rest_of_line ();
19864 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19865 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19866 s_mips_frame is used so that we can set the PDR information correctly.
19867 We can't use the ecoff routines because they make reference to the ecoff
19868 symbol table (in the mdebug section). */
19871 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19873 if (ECOFF_DEBUGGING
)
19879 if (cur_proc_ptr
== (procS
*) NULL
)
19881 as_warn (_(".frame outside of .ent"));
19882 demand_empty_rest_of_line ();
19886 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19888 SKIP_WHITESPACE ();
19889 if (*input_line_pointer
++ != ','
19890 || get_absolute_expression_and_terminator (&val
) != ',')
19892 as_warn (_("bad .frame directive"));
19893 --input_line_pointer
;
19894 demand_empty_rest_of_line ();
19898 cur_proc_ptr
->frame_offset
= val
;
19899 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19901 demand_empty_rest_of_line ();
19905 /* The .fmask and .mask directives. If the mdebug section is present
19906 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19907 embedded targets, s_mips_mask is used so that we can set the PDR
19908 information correctly. We can't use the ecoff routines because they
19909 make reference to the ecoff symbol table (in the mdebug section). */
19912 s_mips_mask (int reg_type
)
19914 if (ECOFF_DEBUGGING
)
19915 s_ignore (reg_type
);
19920 if (cur_proc_ptr
== (procS
*) NULL
)
19922 as_warn (_(".mask/.fmask outside of .ent"));
19923 demand_empty_rest_of_line ();
19927 if (get_absolute_expression_and_terminator (&mask
) != ',')
19929 as_warn (_("bad .mask/.fmask directive"));
19930 --input_line_pointer
;
19931 demand_empty_rest_of_line ();
19935 off
= get_absolute_expression ();
19937 if (reg_type
== 'F')
19939 cur_proc_ptr
->fpreg_mask
= mask
;
19940 cur_proc_ptr
->fpreg_offset
= off
;
19944 cur_proc_ptr
->reg_mask
= mask
;
19945 cur_proc_ptr
->reg_offset
= off
;
19948 demand_empty_rest_of_line ();
19952 /* A table describing all the processors gas knows about. Names are
19953 matched in the order listed.
19955 To ease comparison, please keep this table in the same order as
19956 gcc's mips_cpu_info_table[]. */
19957 static const struct mips_cpu_info mips_cpu_info_table
[] =
19959 /* Entries for generic ISAs. */
19960 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19961 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19962 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19963 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19964 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19965 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19966 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19967 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19968 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19969 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19970 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19971 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19972 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19973 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19974 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19977 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19978 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19979 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19982 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19985 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19986 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19987 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19988 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19989 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19990 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19991 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19992 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19993 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19994 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19995 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19996 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19997 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19998 /* ST Microelectronics Loongson 2E and 2F cores. */
19999 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20000 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20003 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20004 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20005 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20006 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20007 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20008 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20009 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20010 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20011 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20012 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20013 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20014 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20015 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20016 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20017 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20020 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20021 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20022 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20023 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20025 /* MIPS 32 Release 2 */
20026 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20027 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20028 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20029 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20030 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20031 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20032 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20033 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20034 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20035 ISA_MIPS32R2
, CPU_MIPS32R2
},
20036 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20037 ISA_MIPS32R2
, CPU_MIPS32R2
},
20038 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20039 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20040 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20041 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20042 /* Deprecated forms of the above. */
20043 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20044 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20045 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20046 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20047 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20048 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20049 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20050 /* Deprecated forms of the above. */
20051 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20052 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20053 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20054 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20055 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20056 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20057 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20058 /* Deprecated forms of the above. */
20059 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20060 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20061 /* 34Kn is a 34kc without DSP. */
20062 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20063 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20064 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20065 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20066 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20067 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20068 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20069 /* Deprecated forms of the above. */
20070 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20071 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20072 /* 1004K cores are multiprocessor versions of the 34K. */
20073 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20074 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20075 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20076 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20077 /* interaptiv is the new name for 1004kf. */
20078 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20079 { "interaptiv-mr2", 0,
20080 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20081 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20082 /* M5100 family. */
20083 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20084 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20085 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20086 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20089 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20090 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20091 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20092 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20094 /* Broadcom SB-1 CPU core. */
20095 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20096 /* Broadcom SB-1A CPU core. */
20097 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20099 /* MIPS 64 Release 2. */
20100 /* Loongson CPU core. */
20101 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20102 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20103 ISA_MIPS64R2
, CPU_GS464
},
20104 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20105 ISA_MIPS64R2
, CPU_GS464
},
20106 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20107 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20108 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20109 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20111 /* Cavium Networks Octeon CPU core. */
20112 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20113 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20114 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20115 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20118 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20121 XLP is mostly like XLR, with the prominent exception that it is
20122 MIPS64R2 rather than MIPS64. */
20123 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20125 /* MIPS 64 Release 6. */
20126 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20127 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20128 ISA_MIPS64R6
, CPU_MIPS64R6
},
20129 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20132 { NULL
, 0, 0, 0, 0 }
20136 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20137 with a final "000" replaced by "k". Ignore case.
20139 Note: this function is shared between GCC and GAS. */
20142 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20144 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20145 given
++, canonical
++;
20147 return ((*given
== 0 && *canonical
== 0)
20148 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20152 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20153 CPU name. We've traditionally allowed a lot of variation here.
20155 Note: this function is shared between GCC and GAS. */
20158 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20160 /* First see if the name matches exactly, or with a final "000"
20161 turned into "k". */
20162 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20165 /* If not, try comparing based on numerical designation alone.
20166 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20167 if (TOLOWER (*given
) == 'r')
20169 if (!ISDIGIT (*given
))
20172 /* Skip over some well-known prefixes in the canonical name,
20173 hoping to find a number there too. */
20174 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20176 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20178 else if (TOLOWER (canonical
[0]) == 'r')
20181 return mips_strict_matching_cpu_name_p (canonical
, given
);
20185 /* Parse an option that takes the name of a processor as its argument.
20186 OPTION is the name of the option and CPU_STRING is the argument.
20187 Return the corresponding processor enumeration if the CPU_STRING is
20188 recognized, otherwise report an error and return null.
20190 A similar function exists in GCC. */
20192 static const struct mips_cpu_info
*
20193 mips_parse_cpu (const char *option
, const char *cpu_string
)
20195 const struct mips_cpu_info
*p
;
20197 /* 'from-abi' selects the most compatible architecture for the given
20198 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20199 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20200 version. Look first at the -mgp options, if given, otherwise base
20201 the choice on MIPS_DEFAULT_64BIT.
20203 Treat NO_ABI like the EABIs. One reason to do this is that the
20204 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20205 architecture. This code picks MIPS I for 'mips' and MIPS III for
20206 'mips64', just as we did in the days before 'from-abi'. */
20207 if (strcasecmp (cpu_string
, "from-abi") == 0)
20209 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20210 return mips_cpu_info_from_isa (ISA_MIPS1
);
20212 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20213 return mips_cpu_info_from_isa (ISA_MIPS3
);
20215 if (file_mips_opts
.gp
>= 0)
20216 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20217 ? ISA_MIPS1
: ISA_MIPS3
);
20219 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20224 /* 'default' has traditionally been a no-op. Probably not very useful. */
20225 if (strcasecmp (cpu_string
, "default") == 0)
20228 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20229 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20232 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20236 /* Return the canonical processor information for ISA (a member of the
20237 ISA_MIPS* enumeration). */
20239 static const struct mips_cpu_info
*
20240 mips_cpu_info_from_isa (int isa
)
20244 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20245 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20246 && isa
== mips_cpu_info_table
[i
].isa
)
20247 return (&mips_cpu_info_table
[i
]);
20252 static const struct mips_cpu_info
*
20253 mips_cpu_info_from_arch (int arch
)
20257 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20258 if (arch
== mips_cpu_info_table
[i
].cpu
)
20259 return (&mips_cpu_info_table
[i
]);
20265 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20269 fprintf (stream
, "%24s", "");
20274 fprintf (stream
, ", ");
20278 if (*col_p
+ strlen (string
) > 72)
20280 fprintf (stream
, "\n%24s", "");
20284 fprintf (stream
, "%s", string
);
20285 *col_p
+= strlen (string
);
20291 md_show_usage (FILE *stream
)
20296 fprintf (stream
, _("\
20298 -EB generate big endian output\n\
20299 -EL generate little endian output\n\
20300 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20301 -G NUM allow referencing objects up to NUM bytes\n\
20302 implicitly with the gp register [default 8]\n"));
20303 fprintf (stream
, _("\
20304 -mips1 generate MIPS ISA I instructions\n\
20305 -mips2 generate MIPS ISA II instructions\n\
20306 -mips3 generate MIPS ISA III instructions\n\
20307 -mips4 generate MIPS ISA IV instructions\n\
20308 -mips5 generate MIPS ISA V instructions\n\
20309 -mips32 generate MIPS32 ISA instructions\n\
20310 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20311 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20312 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20313 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20314 -mips64 generate MIPS64 ISA instructions\n\
20315 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20316 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20317 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20318 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20319 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20323 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20324 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20325 show (stream
, "from-abi", &column
, &first
);
20326 fputc ('\n', stream
);
20328 fprintf (stream
, _("\
20329 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20330 -no-mCPU don't generate code specific to CPU.\n\
20331 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20335 show (stream
, "3900", &column
, &first
);
20336 show (stream
, "4010", &column
, &first
);
20337 show (stream
, "4100", &column
, &first
);
20338 show (stream
, "4650", &column
, &first
);
20339 fputc ('\n', stream
);
20341 fprintf (stream
, _("\
20342 -mips16 generate mips16 instructions\n\
20343 -no-mips16 do not generate mips16 instructions\n"));
20344 fprintf (stream
, _("\
20345 -mmips16e2 generate MIPS16e2 instructions\n\
20346 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20347 fprintf (stream
, _("\
20348 -mmicromips generate microMIPS instructions\n\
20349 -mno-micromips do not generate microMIPS instructions\n"));
20350 fprintf (stream
, _("\
20351 -msmartmips generate smartmips instructions\n\
20352 -mno-smartmips do not generate smartmips instructions\n"));
20353 fprintf (stream
, _("\
20354 -mdsp generate DSP instructions\n\
20355 -mno-dsp do not generate DSP instructions\n"));
20356 fprintf (stream
, _("\
20357 -mdspr2 generate DSP R2 instructions\n\
20358 -mno-dspr2 do not generate DSP R2 instructions\n"));
20359 fprintf (stream
, _("\
20360 -mdspr3 generate DSP R3 instructions\n\
20361 -mno-dspr3 do not generate DSP R3 instructions\n"));
20362 fprintf (stream
, _("\
20363 -mmt generate MT instructions\n\
20364 -mno-mt do not generate MT instructions\n"));
20365 fprintf (stream
, _("\
20366 -mmcu generate MCU instructions\n\
20367 -mno-mcu do not generate MCU instructions\n"));
20368 fprintf (stream
, _("\
20369 -mmsa generate MSA instructions\n\
20370 -mno-msa do not generate MSA instructions\n"));
20371 fprintf (stream
, _("\
20372 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20373 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20374 fprintf (stream
, _("\
20375 -mvirt generate Virtualization instructions\n\
20376 -mno-virt do not generate Virtualization instructions\n"));
20377 fprintf (stream
, _("\
20378 -mcrc generate CRC instructions\n\
20379 -mno-crc do not generate CRC instructions\n"));
20380 fprintf (stream
, _("\
20381 -mginv generate Global INValidate (GINV) instructions\n\
20382 -mno-ginv do not generate Global INValidate instructions\n"));
20383 fprintf (stream
, _("\
20384 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20385 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20386 fprintf (stream
, _("\
20387 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20388 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20389 fprintf (stream
, _("\
20390 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20391 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20392 fprintf (stream
, _("\
20393 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20394 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20395 fprintf (stream
, _("\
20396 -minsn32 only generate 32-bit microMIPS instructions\n\
20397 -mno-insn32 generate all microMIPS instructions\n"));
20398 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20399 fprintf (stream
, _("\
20400 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20401 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20403 fprintf (stream
, _("\
20404 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20405 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20407 fprintf (stream
, _("\
20408 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20409 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20410 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20411 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20412 -mfix-vr4120 work around certain VR4120 errata\n\
20413 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20414 -mfix-24k insert a nop after ERET and DERET instructions\n\
20415 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20416 -mfix-r5900 work around R5900 short loop errata\n\
20417 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20418 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20419 -msym32 assume all symbols have 32-bit values\n\
20420 -O0 do not remove unneeded NOPs, do not swap branches\n\
20421 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20422 -O2 remove unneeded NOPs and swap branches\n\
20423 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20424 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20425 fprintf (stream
, _("\
20426 -mhard-float allow floating-point instructions\n\
20427 -msoft-float do not allow floating-point instructions\n\
20428 -msingle-float only allow 32-bit floating-point operations\n\
20429 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20430 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20431 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20432 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20433 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20434 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20438 show (stream
, "legacy", &column
, &first
);
20439 show (stream
, "2008", &column
, &first
);
20441 fputc ('\n', stream
);
20443 fprintf (stream
, _("\
20444 -KPIC, -call_shared generate SVR4 position independent code\n\
20445 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20446 -mvxworks-pic generate VxWorks position independent code\n\
20447 -non_shared do not generate code that can operate with DSOs\n\
20448 -xgot assume a 32 bit GOT\n\
20449 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20450 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20451 position dependent (non shared) code\n\
20452 -mabi=ABI create ABI conformant object file for:\n"));
20456 show (stream
, "32", &column
, &first
);
20457 show (stream
, "o64", &column
, &first
);
20458 show (stream
, "n32", &column
, &first
);
20459 show (stream
, "64", &column
, &first
);
20460 show (stream
, "eabi", &column
, &first
);
20462 fputc ('\n', stream
);
20464 fprintf (stream
, _("\
20465 -32 create o32 ABI object file%s\n"),
20466 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20467 fprintf (stream
, _("\
20468 -n32 create n32 ABI object file%s\n"),
20469 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20470 fprintf (stream
, _("\
20471 -64 create 64 ABI object file%s\n"),
20472 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20477 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20479 if (HAVE_64BIT_SYMBOLS
)
20480 return dwarf2_format_64bit_irix
;
20482 return dwarf2_format_32bit
;
20487 mips_dwarf2_addr_size (void)
20489 if (HAVE_64BIT_OBJECTS
)
20495 /* Standard calling conventions leave the CFA at SP on entry. */
20497 mips_cfi_frame_initial_instructions (void)
20499 cfi_add_CFA_def_cfa_register (SP
);
20503 tc_mips_regname_to_dw2regnum (char *regname
)
20505 unsigned int regnum
= -1;
20508 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20514 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20515 Given a symbolic attribute NAME, return the proper integer value.
20516 Returns -1 if the attribute is not known. */
20519 mips_convert_symbolic_attribute (const char *name
)
20521 static const struct
20526 attribute_table
[] =
20528 #define T(tag) {#tag, tag}
20529 T (Tag_GNU_MIPS_ABI_FP
),
20530 T (Tag_GNU_MIPS_ABI_MSA
),
20538 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20539 if (streq (name
, attribute_table
[i
].name
))
20540 return attribute_table
[i
].tag
;
20548 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20550 mips_emit_delays ();
20552 as_warn (_("missing .end at end of assembly"));
20554 /* Just in case no code was emitted, do the consistency check. */
20555 file_mips_check_options ();
20557 /* Set a floating-point ABI if the user did not. */
20558 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20560 /* Perform consistency checks on the floating-point ABI. */
20561 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20562 Tag_GNU_MIPS_ABI_FP
);
20563 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20564 check_fpabi (fpabi
);
20568 /* Soft-float gets precedence over single-float, the two options should
20569 not be used together so this should not matter. */
20570 if (file_mips_opts
.soft_float
== 1)
20571 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20572 /* Single-float gets precedence over all double_float cases. */
20573 else if (file_mips_opts
.single_float
== 1)
20574 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20577 switch (file_mips_opts
.fp
)
20580 if (file_mips_opts
.gp
== 32)
20581 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20584 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20587 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20588 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20589 else if (file_mips_opts
.gp
== 32)
20590 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20592 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20597 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20598 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20602 /* Returns the relocation type required for a particular CFI encoding. */
20604 bfd_reloc_code_real_type
20605 mips_cfi_reloc_for_encoding (int encoding
)
20607 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20608 return BFD_RELOC_32_PCREL
;
20609 else return BFD_RELOC_NONE
;