1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* The name of the readonly data section. */
95 #define RDATA_SECTION_NAME ".data"
98 #define RDATA_SECTION_NAME ".rdata"
101 #define RDATA_SECTION_NAME ".rodata"
104 /* These variables are filled in with the masks of registers used.
105 The object format code reads them and puts them in the appropriate
107 unsigned long mips_gprmask
;
108 unsigned long mips_cprmask
[4];
110 /* MIPS ISA (Instruction Set Architecture) level (may be changed
111 temporarily using .set mipsN). */
112 static int mips_isa
= -1;
114 /* MIPS ISA we are using for this output file. */
115 static int file_mips_isa
;
117 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
120 /* MIPS PIC level. */
124 /* Do not generate PIC code. */
127 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
128 not sure what it is supposed to do. */
131 /* Generate PIC code as in the SVR4 MIPS ABI. */
134 /* Generate PIC code without using a global offset table: the data
135 segment has a maximum size of 64K, all data references are off
136 the $gp register, and all text references are PC relative. This
137 is used on some embedded systems. */
141 static enum mips_pic_level mips_pic
;
143 /* 1 if trap instructions should used for overflow rather than break
145 static int mips_trap
;
147 static int mips_warn_about_macros
;
148 static int mips_noreorder
;
149 static int mips_any_noreorder
;
150 static int mips_nomove
;
151 static int mips_noat
;
152 static int mips_nobopt
;
155 /* The size of the small data section. */
156 static int g_switch_value
= 8;
157 /* Whether the -G option was used. */
158 static int g_switch_seen
= 0;
164 /* handle of the OPCODE hash table */
165 static struct hash_control
*op_hash
= NULL
;
167 /* This array holds the chars that always start a comment. If the
168 pre-processor is disabled, these aren't very useful */
169 const char comment_chars
[] = "#";
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that C style comments are always supported. */
178 const char line_comment_chars
[] = "#";
180 /* This array holds machine specific line separator characters. */
181 const char line_separator_chars
[] = "";
183 /* Chars that can be used to separate mant from exp in floating point nums */
184 const char EXP_CHARS
[] = "eE";
186 /* Chars that mean this number is a floating point constant */
189 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
191 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
192 changed in read.c . Ideally it shouldn't have to know about it at all,
193 but nothing is ideal around here.
196 static char *insn_error
;
198 static int byte_order
= BYTE_ORDER
;
200 static int auto_align
= 1;
202 /* Symbol labelling the current insn. */
203 static symbolS
*insn_label
;
205 /* When outputting SVR4 PIC code, the assembler needs to know the
206 offset in the stack frame from which to restore the $gp register.
207 This is set by the .cprestore pseudo-op, and saved in this
209 static offsetT mips_cprestore_offset
= -1;
211 /* This is the register which holds the stack frame, as set by the
212 .frame pseudo-op. This is needed to implement .cprestore. */
213 static int mips_frame_reg
= SP
;
215 /* To output NOP instructions correctly, we need to keep information
216 about the previous two instructions. */
218 /* Whether we are optimizing. The default value of 2 means to remove
219 unneeded NOPs and swap branch instructions when possible. A value
220 of 1 means to not swap branches. A value of 0 means to always
222 static int mips_optimize
= 2;
224 /* The previous instruction. */
225 static struct mips_cl_insn prev_insn
;
227 /* The instruction before prev_insn. */
228 static struct mips_cl_insn prev_prev_insn
;
230 /* If we don't want information for prev_insn or prev_prev_insn, we
231 point the insn_mo field at this dummy integer. */
232 static const struct mips_opcode dummy_opcode
= { 0 };
234 /* Non-zero if prev_insn is valid. */
235 static int prev_insn_valid
;
237 /* The frag for the previous instruction. */
238 static struct frag
*prev_insn_frag
;
240 /* The offset into prev_insn_frag for the previous instruction. */
241 static long prev_insn_where
;
243 /* The reloc for the previous instruction, if any. */
244 static fixS
*prev_insn_fixp
;
246 /* Non-zero if the previous instruction was in a delay slot. */
247 static int prev_insn_is_delay_slot
;
249 /* Non-zero if the previous instruction was in a .set noreorder. */
250 static int prev_insn_unreordered
;
252 /* Non-zero if the previous previous instruction was in a .set
254 static int prev_prev_insn_unreordered
;
256 /* Since the MIPS does not have multiple forms of PC relative
257 instructions, we do not have to do relaxing as is done on other
258 platforms. However, we do have to handle GP relative addressing
259 correctly, which turns out to be a similar problem.
261 Every macro that refers to a symbol can occur in (at least) two
262 forms, one with GP relative addressing and one without. For
263 example, loading a global variable into a register generally uses
264 a macro instruction like this:
266 If i can be addressed off the GP register (this is true if it is in
267 the .sbss or .sdata section, or if it is known to be smaller than
268 the -G argument) this will generate the following instruction:
270 This instruction will use a GPREL reloc. If i can not be addressed
271 off the GP register, the following instruction sequence will be used:
274 In this case the first instruction will have a HI16 reloc, and the
275 second reloc will have a LO16 reloc. Both relocs will be against
278 The issue here is that we may not know whether i is GP addressable
279 until after we see the instruction that uses it. Therefore, we
280 want to be able to choose the final instruction sequence only at
281 the end of the assembly. This is similar to the way other
282 platforms choose the size of a PC relative instruction only at the
285 When generating position independent code we do not use GP
286 addressing in quite the same way, but the issue still arises as
287 external symbols and local symbols must be handled differently.
289 We handle these issues by actually generating both possible
290 instruction sequences. The longer one is put in a frag_var with
291 type rs_machine_dependent. We encode what to do with the frag in
292 the subtype field. We encode (1) the number of existing bytes to
293 replace, (2) the number of new bytes to use, (3) the offset from
294 the start of the existing bytes to the first reloc we must generate
295 (that is, the offset is applied from the start of the existing
296 bytes after they are replaced by the new bytes, if any), (4) the
297 offset from the start of the existing bytes to the second reloc,
298 (5) whether a third reloc is needed (the third reloc is always four
299 bytes after the second reloc), and (6) whether to warn if this
300 variant is used (this is sometimes needed if .set nomacro or .set
301 noat is in effect). All these numbers are reasonably small.
303 Generating two instruction sequences must be handled carefully to
304 ensure that delay slots are handled correctly. Fortunately, there
305 are a limited number of cases. When the second instruction
306 sequence is generated, append_insn is directed to maintain the
307 existing delay slot information, so it continues to apply to any
308 code after the second instruction sequence. This means that the
309 second instruction sequence must not impose any requirements not
310 required by the first instruction sequence.
312 These variant frags are then handled in functions called by the
313 machine independent code. md_estimate_size_before_relax returns
314 the final size of the frag. md_convert_frag sets up the final form
315 of the frag. tc_gen_reloc adjust the first reloc and adds a second
317 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
321 | (((reloc1) + 64) << 9) \
322 | (((reloc2) + 64) << 2) \
323 | ((reloc3) ? (1 << 1) : 0) \
325 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
326 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
327 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
328 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
329 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
330 #define RELAX_WARN(i) ((i) & 1)
332 /* Prototypes for static functions. */
335 #define internalError() \
336 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
338 #define internalError() as_fatal ("MIPS internal Error");
341 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
342 unsigned int reg
, int fpr
));
343 static void append_insn
PARAMS ((char *place
,
344 struct mips_cl_insn
* ip
,
346 bfd_reloc_code_real_type r
));
347 static void mips_no_prev_insn
PARAMS ((void));
348 static void mips_emit_delays
PARAMS ((void));
349 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
350 const char *name
, const char *fmt
,
352 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
353 expressionS
* ep
, int regnum
));
354 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
355 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
357 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
358 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
359 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
360 #ifdef LOSING_COMPILER
361 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
363 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
364 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
365 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
366 static symbolS
*get_symbol
PARAMS ((void));
367 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
368 static void s_align
PARAMS ((int));
369 static void s_stringer
PARAMS ((int));
370 static void s_change_sec
PARAMS ((int));
371 static void s_cons
PARAMS ((int));
372 static void s_err
PARAMS ((int));
373 static void s_extern
PARAMS ((int));
374 static void s_float_cons
PARAMS ((int));
375 static void s_mips_globl
PARAMS ((int));
376 static void s_option
PARAMS ((int));
377 static void s_mipsset
PARAMS ((int));
378 static void s_mips_space
PARAMS ((int));
379 static void s_abicalls
PARAMS ((int));
380 static void s_cpload
PARAMS ((int));
381 static void s_cprestore
PARAMS ((int));
382 static void s_gpword
PARAMS ((int));
383 static void s_cpadd
PARAMS ((int));
384 #ifndef ECOFF_DEBUGGING
385 static void md_obj_begin
PARAMS ((void));
386 static void md_obj_end
PARAMS ((void));
387 static long get_number
PARAMS ((void));
388 static void s_ent
PARAMS ((int));
389 static void s_mipsend
PARAMS ((int));
390 static void s_file
PARAMS ((int));
392 static void s_frame
PARAMS ((int));
393 static void s_loc
PARAMS ((int));
394 static void s_mask
PARAMS ((char));
400 The following pseudo-ops from the Kane and Heinrich MIPS book
401 should be defined here, but are currently unsupported: .alias,
402 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
404 The following pseudo-ops from the Kane and Heinrich MIPS book are
405 specific to the type of debugging information being generated, and
406 should be defined by the object format: .aent, .begin, .bend,
407 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
410 The following pseudo-ops from the Kane and Heinrich MIPS book are
411 not MIPS CPU specific, but are also not specific to the object file
412 format. This file is probably the best place to define them, but
413 they are not currently supported: .asm0, .endr, .lab, .repeat,
414 .struct, .weakext. */
416 const pseudo_typeS md_pseudo_table
[] =
418 /* MIPS specific pseudo-ops. */
419 {"option", s_option
, 0},
420 {"set", s_mipsset
, 0},
421 {"rdata", s_change_sec
, 'r'},
422 {"sdata", s_change_sec
, 's'},
423 {"livereg", s_ignore
, 0},
424 { "abicalls", s_abicalls
, 0},
425 { "cpload", s_cpload
, 0},
426 { "cprestore", s_cprestore
, 0},
427 { "gpword", s_gpword
, 0},
428 { "cpadd", s_cpadd
, 0},
430 /* Relatively generic pseudo-ops that happen to be used on MIPS
432 {"asciiz", s_stringer
, 1},
433 {"bss", s_change_sec
, 'b'},
436 {"dword", s_cons
, 3},
438 /* These pseudo-ops are defined in read.c, but must be overridden
439 here for one reason or another. */
440 {"align", s_align
, 0},
441 {"ascii", s_stringer
, 0},
442 {"asciz", s_stringer
, 1},
444 {"data", s_change_sec
, 'd'},
445 {"double", s_float_cons
, 'd'},
446 {"extern", s_extern
, 0},
447 {"float", s_float_cons
, 'f'},
448 {"globl", s_mips_globl
, 0},
449 {"global", s_mips_globl
, 0},
450 {"hword", s_cons
, 1},
455 {"short", s_cons
, 1},
456 {"single", s_float_cons
, 'f'},
457 {"space", s_mips_space
, 0},
458 {"text", s_change_sec
, 't'},
461 #ifndef ECOFF_DEBUGGING
462 /* These pseudo-ops should be defined by the object file format.
463 However, a.out doesn't support them, so we have versions here. */
465 {"bgnb", s_ignore
, 0},
466 {"end", s_mipsend
, 0},
467 {"endb", s_ignore
, 0},
470 {"fmask", s_ignore
, 'F'},
471 {"frame", s_ignore
, 0},
472 {"loc", s_ignore
, 0},
473 {"mask", s_ignore
, 'R'},
474 {"verstamp", s_ignore
, 0},
481 const relax_typeS md_relax_table
[] =
486 static char *expr_end
;
488 static expressionS imm_expr
;
489 static expressionS offset_expr
;
490 static bfd_reloc_code_real_type imm_reloc
;
491 static bfd_reloc_code_real_type offset_reloc
;
493 /* FIXME: This should be handled in a different way. */
494 extern int target_big_endian
;
497 * This function is called once, at assembler startup time. It should
498 * set up all the tables, etc. that the MD part of the assembler will need.
504 register const char *retval
= NULL
;
505 register unsigned int i
= 0;
513 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
515 a
= xmalloc (sizeof TARGET_CPU
);
516 strcpy (a
, TARGET_CPU
);
517 a
[(sizeof TARGET_CPU
) - 3] = '\0';
521 if (strcmp (cpu
, "mips") == 0)
526 else if (strcmp (cpu
, "r6000") == 0
527 || strcmp (cpu
, "mips2") == 0)
532 else if (strcmp (cpu
, "mips64") == 0
533 || strcmp (cpu
, "r4000") == 0
534 || strcmp (cpu
, "mips3") == 0)
539 else if (strcmp (cpu
, "r4400") == 0)
544 else if (strcmp (cpu
, "mips64orion") == 0
545 || strcmp (cpu
, "r4600") == 0)
560 if (mips_isa
< 2 && mips_trap
)
561 as_bad ("trap exception not supported at ISA 1");
566 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
569 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
572 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
576 as_warn ("Could not set architecture and machine");
578 file_mips_isa
= mips_isa
;
580 op_hash
= hash_new ();
582 for (i
= 0; i
< NUMOPCODES
;)
584 const char *name
= mips_opcodes
[i
].name
;
586 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
589 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
590 mips_opcodes
[i
].name
, retval
);
591 as_fatal ("Broken assembler. No assembly attempted.");
595 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
596 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
597 != mips_opcodes
[i
].match
))
599 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
600 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
601 as_fatal ("Broken assembler. No assembly attempted.");
605 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
608 mips_no_prev_insn ();
616 /* set the default alignment for the text section (2**2) */
617 record_alignment (text_section
, 2);
619 /* FIXME: This should be handled in a different way. */
620 target_big_endian
= byte_order
== BIG_ENDIAN
;
623 bfd_set_gp_size (stdoutput
, g_switch_value
);
627 /* Sections must be aligned to 16 byte boundaries. */
628 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
629 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
630 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
632 /* Create a .reginfo section for register masks and a .mdebug
633 section for debugging information. */
641 sec
= subseg_new (".reginfo", (subsegT
) 0);
643 /* The ABI says this section should be loaded so that the running
644 program can access it. */
645 (void) bfd_set_section_flags (stdoutput
, sec
,
646 (SEC_ALLOC
| SEC_LOAD
647 | SEC_READONLY
| SEC_DATA
));
648 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
650 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
652 #ifdef ECOFF_DEBUGGING
653 sec
= subseg_new (".mdebug", (subsegT
) 0);
654 (void) bfd_set_section_flags (stdoutput
, sec
,
655 SEC_HAS_CONTENTS
| SEC_READONLY
);
656 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
659 subseg_set (seg
, subseg
);
663 #ifndef ECOFF_DEBUGGING
671 #ifndef ECOFF_DEBUGGING
680 struct mips_cl_insn insn
;
682 imm_expr
.X_op
= O_absent
;
683 offset_expr
.X_op
= O_absent
;
685 mips_ip (str
, &insn
);
688 as_bad ("%s `%s'", insn_error
, str
);
691 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
697 if (imm_expr
.X_op
!= O_absent
)
698 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
699 else if (offset_expr
.X_op
!= O_absent
)
700 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
702 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
706 /* See whether instruction IP reads register REG. If FPR is non-zero,
707 REG is a floating point register. */
710 insn_uses_reg (ip
, reg
, fpr
)
711 struct mips_cl_insn
*ip
;
715 /* Don't report on general register 0, since it never changes. */
716 if (! fpr
&& reg
== 0)
721 /* If we are called with either $f0 or $f1, we must check $f0.
722 This is not optimal, because it will introduce an unnecessary
723 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
724 need to distinguish reading both $f0 and $f1 or just one of
725 them. Note that we don't have to check the other way,
726 because there is no instruction that sets both $f0 and $f1
727 and requires a delay. */
728 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
729 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
730 == (reg
&~ (unsigned) 1)))
732 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
733 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
734 == (reg
&~ (unsigned) 1)))
739 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
740 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
742 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
743 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
750 /* Output an instruction. PLACE is where to put the instruction; if
751 it is NULL, this uses frag_more to get room. IP is the instruction
752 information. ADDRESS_EXPR is an operand of the instruction to be
753 used with RELOC_TYPE. */
756 append_insn (place
, ip
, address_expr
, reloc_type
)
758 struct mips_cl_insn
*ip
;
759 expressionS
*address_expr
;
760 bfd_reloc_code_real_type reloc_type
;
762 register unsigned long prev_pinfo
, pinfo
;
767 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
768 pinfo
= ip
->insn_mo
->pinfo
;
770 if (place
== NULL
&& ! mips_noreorder
)
772 /* If the previous insn required any delay slots, see if we need
773 to insert a NOP or two. There are eight kinds of possible
774 hazards, of which an instruction can have at most one type.
775 (1) a load from memory delay
776 (2) a load from a coprocessor delay
777 (3) an unconditional branch delay
778 (4) a conditional branch delay
779 (5) a move to coprocessor register delay
780 (6) a load coprocessor register from memory delay
781 (7) a coprocessor condition code delay
782 (8) a HI/LO special register delay
784 There are a lot of optimizations we could do that we don't.
785 In particular, we do not, in general, reorder instructions.
786 If you use gcc with optimization, it will reorder
787 instructions and generally do much more optimization then we
788 do here; repeating all that work in the assembler would only
789 benefit hand written assembly code, and does not seem worth
792 /* This is how a NOP is emitted. */
793 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
795 /* The previous insn might require a delay slot, depending upon
796 the contents of the current insn. */
797 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
799 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
801 /* A load from a coprocessor or from memory. All load
802 delays delay the use of general register rt for one
803 instruction on the r3000. The r6000 and r4000 use
805 know (prev_pinfo
& INSN_WRITE_GPR_T
);
806 if (mips_optimize
== 0
807 || insn_uses_reg (ip
,
808 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
813 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
815 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
817 /* A generic coprocessor delay. The previous instruction
818 modified a coprocessor general or control register. If
819 it modified a control register, we need to avoid any
820 coprocessor instruction (this is probably not always
821 required, but it sometimes is). If it modified a general
822 register, we avoid using that register.
824 On the r6000 and r4000 loading a coprocessor register
825 from memory is interlocked, and does not require a delay.
827 This case is not handled very well. There is no special
828 knowledge of CP0 handling, and the coprocessors other
829 than the floating point unit are not distinguished at
831 if (prev_pinfo
& INSN_WRITE_FPR_T
)
833 if (mips_optimize
== 0
834 || insn_uses_reg (ip
,
835 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
840 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
842 if (mips_optimize
== 0
843 || insn_uses_reg (ip
,
844 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
851 /* We don't know exactly what the previous instruction
852 does. If the current instruction uses a coprocessor
853 register, we must insert a NOP. If previous
854 instruction may set the condition codes, and the
855 current instruction uses them, we must insert two
857 if (mips_optimize
== 0
858 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
859 && (pinfo
& INSN_READ_COND_CODE
)))
861 else if (pinfo
& INSN_COP
)
865 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
867 /* The previous instruction sets the coprocessor condition
868 codes, but does not require a general coprocessor delay
869 (this means it is a floating point comparison
870 instruction). If this instruction uses the condition
871 codes, we need to insert a single NOP. */
872 if (mips_optimize
== 0
873 || (pinfo
& INSN_READ_COND_CODE
))
876 else if (prev_pinfo
& INSN_READ_LO
)
878 /* The previous instruction reads the LO register; if the
879 current instruction writes to the LO register, we must
881 if (mips_optimize
== 0
882 || (pinfo
& INSN_WRITE_LO
))
885 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
887 /* The previous instruction reads the HI register; if the
888 current instruction writes to the HI register, we must
890 if (mips_optimize
== 0
891 || (pinfo
& INSN_WRITE_HI
))
895 /* There are two cases which require two intervening
896 instructions: 1) setting the condition codes using a move to
897 coprocessor instruction which requires a general coprocessor
898 delay and then reading the condition codes 2) reading the HI
899 or LO register and then writing to it. If we are not already
900 emitting a NOP instruction, we must check for these cases
901 compared to the instruction previous to the previous
904 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
905 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
906 && (pinfo
& INSN_READ_COND_CODE
))
907 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
908 && (pinfo
& INSN_WRITE_LO
))
909 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
910 && (pinfo
& INSN_WRITE_HI
))))
913 /* If we are being given a nop instruction, don't bother with
914 one of the nops we would otherwise output. This will only
915 happen when a nop instruction is used with mips_optimize set
917 if (nops
> 0 && ip
->insn_opcode
== 0)
920 /* Now emit the right number of NOP instructions. */
925 for (i
= 0; i
< nops
; i
++)
928 listing_prev_line ();
929 if (insn_label
!= NULL
)
931 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
932 insn_label
->sy_frag
= frag_now
;
933 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
943 if (address_expr
!= NULL
)
945 if (address_expr
->X_op
== O_constant
)
950 ip
->insn_opcode
|= address_expr
->X_add_number
;
954 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
957 case BFD_RELOC_MIPS_JMP
:
958 case BFD_RELOC_16_PCREL_S2
:
967 assert (reloc_type
!= BFD_RELOC_UNUSED
);
969 /* Don't generate a reloc if we are writing into a variant
972 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
974 reloc_type
== BFD_RELOC_16_PCREL_S2
,
979 md_number_to_chars (f
, ip
->insn_opcode
, 4);
981 /* Update the register mask information. */
982 if (pinfo
& INSN_WRITE_GPR_D
)
983 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
984 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
985 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
986 if (pinfo
& INSN_READ_GPR_S
)
987 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
988 if (pinfo
& INSN_WRITE_GPR_31
)
989 mips_gprmask
|= 1 << 31;
990 if (pinfo
& INSN_WRITE_FPR_D
)
991 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
992 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
993 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
994 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
995 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
996 if (pinfo
& INSN_COP
)
998 /* We don't keep enough information to sort these cases out. */
1000 /* Never set the bit for $0, which is always zero. */
1001 mips_gprmask
&=~ 1 << 0;
1003 if (place
== NULL
&& ! mips_noreorder
)
1005 /* Filling the branch delay slot is more complex. We try to
1006 switch the branch with the previous instruction, which we can
1007 do if the previous instruction does not set up a condition
1008 that the branch tests and if the branch is not itself the
1009 target of any branch. */
1010 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1011 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1013 if (mips_optimize
< 2
1014 /* If we have seen .set volatile or .set nomove, don't
1017 /* If we had to emit any NOP instructions, then we
1018 already know we can not swap. */
1020 /* If we don't even know the previous insn, we can not
1022 || ! prev_insn_valid
1023 /* If the previous insn is already in a branch delay
1024 slot, then we can not swap. */
1025 || prev_insn_is_delay_slot
1026 /* If the previous previous insn was in a .set
1027 noreorder, we can't swap. Actually, the MIPS
1028 assembler will swap in this situation. However, gcc
1029 configured -with-gnu-as will generate code like
1035 in which we can not swap the bne and INSN. If gcc is
1036 not configured -with-gnu-as, it does not output the
1037 .set pseudo-ops. We don't have to check
1038 prev_insn_unreordered, because prev_insn_valid will
1039 be 0 in that case. We don't want to use
1040 prev_prev_insn_valid, because we do want to be able
1041 to swap at the start of a function. */
1042 || prev_prev_insn_unreordered
1043 /* If the branch is itself the target of a branch, we
1044 can not swap. We cheat on this; all we check for is
1045 whether there is a label on this instruction. If
1046 there are any branches to anything other than a
1047 label, users must use .set noreorder. */
1048 || insn_label
!= NULL
1049 /* If the previous instruction is in a variant frag, we
1050 can not do the swap. */
1051 || prev_insn_frag
->fr_type
== rs_machine_dependent
1052 /* If the branch reads the condition codes, we don't
1053 even try to swap, because in the sequence
1058 we can not swap, and I don't feel like handling that
1060 || (pinfo
& INSN_READ_COND_CODE
)
1061 /* We can not swap with an instruction that requires a
1062 delay slot, becase the target of the branch might
1063 interfere with that instruction. */
1065 & (INSN_LOAD_COPROC_DELAY
1066 | INSN_COPROC_MOVE_DELAY
1067 | INSN_WRITE_COND_CODE
1072 & (INSN_LOAD_MEMORY_DELAY
1073 | INSN_COPROC_MEMORY_DELAY
)))
1074 /* We can not swap with a branch instruction. */
1076 & (INSN_UNCOND_BRANCH_DELAY
1077 | INSN_COND_BRANCH_DELAY
1078 | INSN_COND_BRANCH_LIKELY
))
1079 /* We do not swap with a trap instruction, since it
1080 complicates trap handlers to have the trap
1081 instruction be in a delay slot. */
1082 || (prev_pinfo
& INSN_TRAP
)
1083 /* If the branch reads a register that the previous
1084 instruction sets, we can not swap. */
1085 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1086 && insn_uses_reg (ip
,
1087 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1090 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1091 && insn_uses_reg (ip
,
1092 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1095 /* If the branch writes a register that the previous
1096 instruction sets, we can not swap (we know that
1097 branches write only to RD or to $31). */
1098 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1099 && (((pinfo
& INSN_WRITE_GPR_D
)
1100 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1101 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1102 || ((pinfo
& INSN_WRITE_GPR_31
)
1103 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1106 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1107 && (((pinfo
& INSN_WRITE_GPR_D
)
1108 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1109 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1110 || ((pinfo
& INSN_WRITE_GPR_31
)
1111 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1114 /* If the branch writes a register that the previous
1115 instruction reads, we can not swap (we know that
1116 branches only write to RD or to $31). */
1117 || ((pinfo
& INSN_WRITE_GPR_D
)
1118 && insn_uses_reg (&prev_insn
,
1119 ((ip
->insn_opcode
>> OP_SH_RD
)
1122 || ((pinfo
& INSN_WRITE_GPR_31
)
1123 && insn_uses_reg (&prev_insn
, 31, 0))
1124 /* If we are generating embedded PIC code, the branch
1125 might be expanded into a sequence which uses $at, so
1126 we can't swap with an instruction which reads it. */
1127 || (mips_pic
== EMBEDDED_PIC
1128 && insn_uses_reg (&prev_insn
, AT
, 0))
1129 /* If the previous previous instruction has a load
1130 delay, and sets a register that the branch reads, we
1132 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1134 && (prev_prev_insn
.insn_mo
->pinfo
1135 & INSN_LOAD_MEMORY_DELAY
)))
1136 && insn_uses_reg (ip
,
1137 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1141 /* We could do even better for unconditional branches to
1142 portions of this object file; we could pick up the
1143 instruction at the destination, put it in the delay
1144 slot, and bump the destination address. */
1146 /* Update the previous insn information. */
1147 prev_prev_insn
= *ip
;
1148 prev_insn
.insn_mo
= &dummy_opcode
;
1155 /* It looks like we can actually do the swap. */
1156 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1157 memcpy (temp
, prev_f
, 4);
1158 memcpy (prev_f
, f
, 4);
1159 memcpy (f
, temp
, 4);
1162 prev_insn_fixp
->fx_frag
= frag_now
;
1163 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1167 fixp
->fx_frag
= prev_insn_frag
;
1168 fixp
->fx_where
= prev_insn_where
;
1170 /* Update the previous insn information; leave prev_insn
1172 prev_prev_insn
= *ip
;
1174 prev_insn_is_delay_slot
= 1;
1176 /* If that was an unconditional branch, forget the previous
1177 insn information. */
1178 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1180 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1181 prev_insn
.insn_mo
= &dummy_opcode
;
1184 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1186 /* We don't yet optimize a branch likely. What we should do
1187 is look at the target, copy the instruction found there
1188 into the delay slot, and increment the branch to jump to
1189 the next instruction. */
1191 /* Update the previous insn information. */
1192 prev_prev_insn
= *ip
;
1193 prev_insn
.insn_mo
= &dummy_opcode
;
1197 /* Update the previous insn information. */
1199 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1201 prev_prev_insn
= prev_insn
;
1204 /* Any time we see a branch, we always fill the delay slot
1205 immediately; since this insn is not a branch, we know it
1206 is not in a delay slot. */
1207 prev_insn_is_delay_slot
= 0;
1210 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1211 prev_insn_unreordered
= 0;
1212 prev_insn_frag
= frag_now
;
1213 prev_insn_where
= f
- frag_now
->fr_literal
;
1214 prev_insn_fixp
= fixp
;
1215 prev_insn_valid
= 1;
1218 /* We just output an insn, so the next one doesn't have a label. */
1222 /* This function forgets that there was any previous instruction or
1226 mips_no_prev_insn ()
1228 prev_insn
.insn_mo
= &dummy_opcode
;
1229 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1230 prev_insn_valid
= 0;
1231 prev_insn_is_delay_slot
= 0;
1232 prev_insn_unreordered
= 0;
1233 prev_prev_insn_unreordered
= 0;
1237 /* This function must be called whenever we turn on noreorder or emit
1238 something other than instructions. It inserts any NOPS which might
1239 be needed by the previous instruction, and clears the information
1240 kept for the previous instructions. */
1245 if (! mips_noreorder
)
1250 if ((prev_insn
.insn_mo
->pinfo
1251 & (INSN_LOAD_COPROC_DELAY
1252 | INSN_COPROC_MOVE_DELAY
1253 | INSN_WRITE_COND_CODE
1257 && (prev_insn
.insn_mo
->pinfo
1258 & (INSN_LOAD_MEMORY_DELAY
1259 | INSN_COPROC_MEMORY_DELAY
))))
1262 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1263 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1264 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1267 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1268 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1269 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1274 if (insn_label
!= NULL
)
1276 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1277 insn_label
->sy_frag
= frag_now
;
1278 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1283 mips_no_prev_insn ();
1286 /* Build an instruction created by a macro expansion. This is passed
1287 a pointer to the count of instructions created so far, an
1288 expression, the name of the instruction to build, an operand format
1289 string, and corresponding arguments. */
1293 macro_build (char *place
,
1299 #else /* ! defined (NO_STDARG) */
1301 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1308 #endif /* ! defined (NO_STDARG) */
1310 struct mips_cl_insn insn
;
1311 bfd_reloc_code_real_type r
;
1315 va_start (args
, fmt
);
1321 * If the macro is about to expand into a second instruction,
1322 * print a warning if needed. We need to pass ip as a parameter
1323 * to generate a better warning message here...
1325 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1326 as_warn ("Macro instruction expanded into multiple instructions");
1329 *counter
+= 1; /* bump instruction counter */
1331 r
= BFD_RELOC_UNUSED
;
1332 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1333 assert (insn
.insn_mo
);
1334 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1336 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1337 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1340 assert (insn
.insn_mo
->name
);
1341 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1343 insn
.insn_opcode
= insn
.insn_mo
->match
;
1359 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1365 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1370 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1375 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1382 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1386 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1390 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1397 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1403 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1404 assert (r
== BFD_RELOC_MIPS_GPREL
1405 || r
== BFD_RELOC_MIPS_LITERAL
1406 || r
== BFD_RELOC_LO16
1407 || r
== BFD_RELOC_MIPS_GOT16
1408 || r
== BFD_RELOC_MIPS_CALL16
1409 || (ep
->X_op
== O_subtract
1410 && now_seg
== text_section
1411 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1412 && r
== BFD_RELOC_PCREL_LO16
));
1416 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1418 && (ep
->X_op
== O_constant
1419 || (ep
->X_op
== O_symbol
1420 && (r
== BFD_RELOC_HI16_S
1421 || r
== BFD_RELOC_HI16
))
1422 || (ep
->X_op
== O_subtract
1423 && now_seg
== text_section
1424 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1425 && r
== BFD_RELOC_PCREL_HI16_S
)));
1426 if (ep
->X_op
== O_constant
)
1428 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1430 r
= BFD_RELOC_UNUSED
;
1435 assert (ep
!= NULL
);
1437 * This allows macro() to pass an immediate expression for
1438 * creating short branches without creating a symbol.
1439 * Note that the expression still might come from the assembly
1440 * input, in which case the value is not checked for range nor
1441 * is a relocation entry generated (yuck).
1443 if (ep
->X_op
== O_constant
)
1445 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1449 r
= BFD_RELOC_16_PCREL_S2
;
1453 assert (ep
!= NULL
);
1454 r
= BFD_RELOC_MIPS_JMP
;
1463 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1465 append_insn (place
, &insn
, ep
, r
);
1469 * Generate a "lui" instruction.
1472 macro_build_lui (place
, counter
, ep
, regnum
)
1478 expressionS high_expr
;
1479 struct mips_cl_insn insn
;
1480 bfd_reloc_code_real_type r
;
1481 CONST
char *name
= "lui";
1482 CONST
char *fmt
= "t,u";
1488 high_expr
.X_op
= O_constant
;
1489 high_expr
.X_add_number
= 0;
1492 if (high_expr
.X_op
== O_constant
)
1494 /* we can compute the instruction now without a relocation entry */
1495 if (high_expr
.X_add_number
& 0x8000)
1496 high_expr
.X_add_number
+= 0x10000;
1497 high_expr
.X_add_number
=
1498 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1499 r
= BFD_RELOC_UNUSED
;
1503 assert (ep
->X_op
== O_symbol
);
1504 /* _gp_disp is a special case, used from s_cpload. */
1505 assert (mips_pic
== NO_PIC
1506 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1507 r
= BFD_RELOC_HI16_S
;
1511 * If the macro is about to expand into a second instruction,
1512 * print a warning if needed. We need to pass ip as a parameter
1513 * to generate a better warning message here...
1515 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1516 as_warn ("Macro instruction expanded into multiple instructions");
1519 *counter
+= 1; /* bump instruction counter */
1521 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1522 assert (insn
.insn_mo
);
1523 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1524 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1526 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1527 if (r
== BFD_RELOC_UNUSED
)
1529 insn
.insn_opcode
|= high_expr
.X_add_number
;
1530 append_insn (place
, &insn
, NULL
, r
);
1533 append_insn (place
, &insn
, &high_expr
, r
);
1537 * Generates code to set the $at register to true (one)
1538 * if reg is less than the immediate expression.
1541 set_at (counter
, reg
, unsignedp
)
1546 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1547 macro_build ((char *) NULL
, counter
, &imm_expr
,
1548 unsignedp
? "sltiu" : "slti",
1549 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1552 load_register (counter
, AT
, &imm_expr
);
1553 macro_build ((char *) NULL
, counter
, NULL
,
1554 unsignedp
? "sltu" : "slt",
1555 "d,v,t", AT
, reg
, AT
);
1559 /* Warn if an expression is not a constant. */
1562 check_absolute_expr (ip
, ex
)
1563 struct mips_cl_insn
*ip
;
1566 if (ex
->X_op
!= O_constant
)
1567 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1571 * This routine generates the least number of instructions neccessary to load
1572 * an absolute expression value into a register.
1575 load_register (counter
, reg
, ep
)
1580 assert (ep
->X_op
== O_constant
);
1581 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1583 /* No need to ever use daddiu here, since we are adding in
1585 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1586 (int) BFD_RELOC_LO16
);
1588 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1589 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1590 (int) BFD_RELOC_LO16
);
1591 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1592 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1593 == ~ (offsetT
) 0x7fffffff))
1595 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1596 (int) BFD_RELOC_HI16
);
1597 if ((ep
->X_add_number
& 0xffff) != 0)
1598 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1599 (int) BFD_RELOC_LO16
);
1601 else if (mips_isa
< 3)
1603 as_bad ("Number larger than 32 bits");
1604 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1605 (int) BFD_RELOC_LO16
);
1610 expressionS hi32
, lo32
;
1614 hi32
.X_add_number
>>= shift
;
1615 hi32
.X_add_number
&= 0xffffffff;
1616 if ((hi32
.X_add_number
& 0x80000000) != 0)
1617 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1618 load_register (counter
, reg
, &hi32
);
1620 lo32
.X_add_number
&= 0xffffffff;
1621 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1622 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1628 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1631 mid16
.X_add_number
>>= 16;
1632 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1633 reg
, (int) BFD_RELOC_LO16
);
1634 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1637 if ((lo32
.X_add_number
& 0xffff) != 0)
1638 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1639 (int) BFD_RELOC_LO16
);
1643 /* Load an address into a register. */
1646 load_address (counter
, reg
, ep
)
1653 if (ep
->X_op
!= O_constant
1654 && ep
->X_op
!= O_symbol
)
1656 as_bad ("expression too complex");
1657 ep
->X_op
= O_constant
;
1660 if (ep
->X_op
== O_constant
)
1662 load_register (counter
, reg
, ep
);
1666 if (mips_pic
== NO_PIC
)
1668 /* If this is a reference to a GP relative symbol, we want
1669 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1671 lui $reg,<sym> (BFD_RELOC_HI16_S)
1672 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1673 If we have an addend, we always use the latter form. */
1674 if (ep
->X_add_number
!= 0)
1679 macro_build ((char *) NULL
, counter
, ep
,
1680 mips_isa
< 3 ? "addiu" : "daddiu",
1681 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1682 p
= frag_var (rs_machine_dependent
, 8, 0,
1683 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1684 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1686 macro_build_lui (p
, counter
, ep
, reg
);
1689 macro_build (p
, counter
, ep
,
1690 mips_isa
< 3 ? "addiu" : "daddiu",
1691 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1693 else if (mips_pic
== SVR4_PIC
)
1697 /* If this is a reference to an external symbol, we want
1698 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1700 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1702 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1703 If there is a constant, it must be added in after. */
1704 ex
.X_add_number
= ep
->X_add_number
;
1705 ep
->X_add_number
= 0;
1707 macro_build ((char *) NULL
, counter
, ep
,
1708 mips_isa
< 3 ? "lw" : "ld",
1709 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1710 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1711 p
= frag_var (rs_machine_dependent
, 4, 0,
1712 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1713 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1714 macro_build (p
, counter
, ep
,
1715 mips_isa
< 3 ? "addiu" : "daddiu",
1716 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1717 if (ex
.X_add_number
!= 0)
1719 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1720 as_bad ("PIC code offset overflow (max 16 signed bits)");
1721 ex
.X_op
= O_constant
;
1722 macro_build (p
, counter
, &ex
,
1723 mips_isa
< 3 ? "addiu" : "daddiu",
1724 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1727 else if (mips_pic
== EMBEDDED_PIC
)
1730 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1732 macro_build ((char *) NULL
, counter
, ep
,
1733 mips_isa
< 3 ? "addiu" : "daddiu",
1734 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1742 * This routine implements the seemingly endless macro or synthesized
1743 * instructions and addressing modes in the mips assembly language. Many
1744 * of these macros are simple and are similar to each other. These could
1745 * probably be handled by some kind of table or grammer aproach instead of
1746 * this verbose method. Others are not simple macros but are more like
1747 * optimizing code generation.
1748 * One interesting optimization is when several store macros appear
1749 * consecutivly that would load AT with the upper half of the same address.
1750 * The ensuing load upper instructions are ommited. This implies some kind
1751 * of global optimization. We currently only optimize within a single macro.
1752 * For many of the load and store macros if the address is specified as a
1753 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1754 * first load register 'at' with zero and use it as the base register. The
1755 * mips assembler simply uses register $zero. Just one tiny optimization
1760 struct mips_cl_insn
*ip
;
1762 register int treg
, sreg
, dreg
, breg
;
1775 bfd_reloc_code_real_type r
;
1777 int hold_mips_optimize
;
1779 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1780 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1781 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1782 mask
= ip
->insn_mo
->mask
;
1784 expr1
.X_op
= O_constant
;
1785 expr1
.X_op_symbol
= NULL
;
1786 expr1
.X_add_symbol
= NULL
;
1787 expr1
.X_add_number
= 1;
1799 mips_emit_delays ();
1801 mips_any_noreorder
= 1;
1803 expr1
.X_add_number
= 8;
1804 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1806 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1808 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1809 macro_build ((char *) NULL
, &icnt
, NULL
,
1810 dbl
? "dsub" : "sub",
1811 "d,v,t", dreg
, 0, sreg
);
1834 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1836 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1837 (int) BFD_RELOC_LO16
);
1840 load_register (&icnt
, AT
, &imm_expr
);
1841 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1860 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1862 if (mask
!= M_NOR_I
)
1863 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1864 sreg
, (int) BFD_RELOC_LO16
);
1867 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1868 treg
, sreg
, (int) BFD_RELOC_LO16
);
1869 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1875 load_register (&icnt
, AT
, &imm_expr
);
1876 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1893 if (imm_expr
.X_add_number
== 0)
1895 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1899 load_register (&icnt
, AT
, &imm_expr
);
1900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1909 likely
? "bgezl" : "bgez",
1915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1916 likely
? "blezl" : "blez",
1920 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1921 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1922 likely
? "beql" : "beq",
1929 /* check for > max integer */
1930 maxnum
= 0x7fffffff;
1938 if (imm_expr
.X_add_number
>= maxnum
1939 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
1942 /* result is always false */
1945 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1946 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1950 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1951 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1956 imm_expr
.X_add_number
++;
1960 if (mask
== M_BGEL_I
)
1962 if (imm_expr
.X_add_number
== 0)
1964 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1965 likely
? "bgezl" : "bgez",
1969 if (imm_expr
.X_add_number
== 1)
1971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1972 likely
? "bgtzl" : "bgtz",
1976 maxnum
= 0x7fffffff;
1984 maxnum
= - maxnum
- 1;
1985 if (imm_expr
.X_add_number
<= maxnum
1986 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
1989 /* result is always true */
1990 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1991 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1994 set_at (&icnt
, sreg
, 0);
1995 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1996 likely
? "beql" : "beq",
2007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2008 likely
? "beql" : "beq",
2012 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2014 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2015 likely
? "beql" : "beq",
2022 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2024 imm_expr
.X_add_number
++;
2028 if (mask
== M_BGEUL_I
)
2030 if (imm_expr
.X_add_number
== 0)
2032 if (imm_expr
.X_add_number
== 1)
2034 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2035 likely
? "bnel" : "bne",
2039 set_at (&icnt
, sreg
, 1);
2040 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2041 likely
? "beql" : "beq",
2050 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2051 likely
? "bgtzl" : "bgtz",
2057 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2058 likely
? "bltzl" : "bltz",
2062 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2063 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2064 likely
? "bnel" : "bne",
2073 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2074 likely
? "bnel" : "bne",
2080 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2082 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2083 likely
? "bnel" : "bne",
2092 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2093 likely
? "blezl" : "blez",
2099 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2100 likely
? "bgezl" : "bgez",
2104 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2105 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2106 likely
? "beql" : "beq",
2113 maxnum
= 0x7fffffff;
2121 if (imm_expr
.X_add_number
>= maxnum
2122 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2124 imm_expr
.X_add_number
++;
2128 if (mask
== M_BLTL_I
)
2130 if (imm_expr
.X_add_number
== 0)
2132 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2133 likely
? "bltzl" : "bltz",
2137 if (imm_expr
.X_add_number
== 1)
2139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2140 likely
? "blezl" : "blez",
2144 set_at (&icnt
, sreg
, 0);
2145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2146 likely
? "bnel" : "bne",
2155 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2156 likely
? "beql" : "beq",
2162 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2164 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2165 likely
? "beql" : "beq",
2172 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2174 imm_expr
.X_add_number
++;
2178 if (mask
== M_BLTUL_I
)
2180 if (imm_expr
.X_add_number
== 0)
2182 if (imm_expr
.X_add_number
== 1)
2184 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2185 likely
? "beql" : "beq",
2189 set_at (&icnt
, sreg
, 1);
2190 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2191 likely
? "bnel" : "bne",
2200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2201 likely
? "bltzl" : "bltz",
2207 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2208 likely
? "bgtzl" : "bgtz",
2212 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2213 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2214 likely
? "bnel" : "bne",
2225 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2226 likely
? "bnel" : "bne",
2230 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2233 likely
? "bnel" : "bne",
2249 as_warn ("Divide by zero.");
2251 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2253 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2257 mips_emit_delays ();
2259 mips_any_noreorder
= 1;
2260 macro_build ((char *) NULL
, &icnt
, NULL
,
2261 dbl
? "ddiv" : "div",
2262 "z,s,t", sreg
, treg
);
2264 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2267 expr1
.X_add_number
= 8;
2268 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2269 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2270 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2272 expr1
.X_add_number
= -1;
2273 macro_build ((char *) NULL
, &icnt
, &expr1
,
2274 dbl
? "daddiu" : "addiu",
2275 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2276 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2277 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2280 expr1
.X_add_number
= 1;
2281 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2282 (int) BFD_RELOC_LO16
);
2283 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2288 expr1
.X_add_number
= 0x80000000;
2289 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2290 (int) BFD_RELOC_HI16
);
2293 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2296 expr1
.X_add_number
= 8;
2297 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2298 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2299 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2302 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2341 if (imm_expr
.X_add_number
== 0)
2343 as_warn ("Divide by zero.");
2345 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2347 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2350 if (imm_expr
.X_add_number
== 1)
2352 if (strcmp (s2
, "mflo") == 0)
2353 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2356 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2359 if (imm_expr
.X_add_number
== -1
2360 && s
[strlen (s
) - 1] != 'u')
2362 if (strcmp (s2
, "mflo") == 0)
2365 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2368 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2372 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2376 load_register (&icnt
, AT
, &imm_expr
);
2377 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2378 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2397 mips_emit_delays ();
2399 mips_any_noreorder
= 1;
2400 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2402 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2405 expr1
.X_add_number
= 8;
2406 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2407 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2408 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2411 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2415 /* Load the address of a symbol into a register. If breg is not
2416 zero, we then add a base register to it. */
2418 /* When generating embedded PIC code, we permit expressions of
2421 where bar is an address in the .text section. These are used
2422 when getting the addresses of functions. We don't permit
2423 X_add_number to be non-zero, because if the symbol is
2424 external the relaxing code needs to know that any addend is
2425 purely the offset to X_op_symbol. */
2426 if (mips_pic
== EMBEDDED_PIC
2427 && offset_expr
.X_op
== O_subtract
2428 && now_seg
== text_section
2429 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2431 && offset_expr
.X_add_number
== 0)
2433 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2434 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2435 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2436 mips_isa
< 3 ? "addiu" : "daddiu",
2437 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2441 if (offset_expr
.X_op
!= O_symbol
2442 && offset_expr
.X_op
!= O_constant
)
2444 as_bad ("expression too complex");
2445 offset_expr
.X_op
= O_constant
;
2459 if (offset_expr
.X_op
== O_constant
)
2460 load_register (&icnt
, tempreg
, &offset_expr
);
2461 else if (mips_pic
== NO_PIC
)
2463 /* If this is a reference to an GP relative symbol, we want
2464 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2466 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2467 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2468 If we have a constant, we need two instructions anyhow,
2469 so we may as well always use the latter form. */
2470 if (offset_expr
.X_add_number
!= 0)
2475 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2476 mips_isa
< 3 ? "addiu" : "daddiu",
2477 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2478 p
= frag_var (rs_machine_dependent
, 8, 0,
2479 RELAX_ENCODE (4, 8, 0, 4, 0,
2480 mips_warn_about_macros
),
2481 offset_expr
.X_add_symbol
, (long) 0,
2484 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2487 macro_build (p
, &icnt
, &offset_expr
,
2488 mips_isa
< 3 ? "addiu" : "daddiu",
2489 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2491 else if (mips_pic
== SVR4_PIC
)
2493 /* If this is a reference to an external symbol, and there
2494 is no constant, we want
2495 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2496 For a local symbol, we want
2497 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2499 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2501 If we have a small constant, and this is a reference to
2502 an external symbol, we want
2503 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2505 addiu $tempreg,$tempreg,<constant>
2506 For a local symbol, we want the same instruction
2507 sequence, but we output a BFD_RELOC_LO16 reloc on the
2510 If we have a large constant, and this is a reference to
2511 an external symbol, we want
2512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2513 lui $at,<hiconstant>
2514 addiu $at,$at,<loconstant>
2515 addu $tempreg,$tempreg,$at
2516 For a local symbol, we want the same instruction
2517 sequence, but we output a BFD_RELOC_LO16 reloc on the
2518 addiu instruction. */
2519 expr1
.X_add_number
= offset_expr
.X_add_number
;
2520 offset_expr
.X_add_number
= 0;
2522 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2523 mips_isa
< 3 ? "lw" : "ld",
2524 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2525 if (expr1
.X_add_number
== 0)
2533 /* We're going to put in an addu instruction using
2534 tempreg, so we may as well insert the nop right
2536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2540 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2541 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2543 ? mips_warn_about_macros
2545 offset_expr
.X_add_symbol
, (long) 0,
2549 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2552 macro_build (p
, &icnt
, &expr1
,
2553 mips_isa
< 3 ? "addiu" : "daddiu",
2554 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2555 /* FIXME: If breg == 0, and the next instruction uses
2556 $tempreg, then if this variant case is used an extra
2557 nop will be generated. */
2559 else if (expr1
.X_add_number
>= -0x8000
2560 && expr1
.X_add_number
< 0x8000)
2562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2564 macro_build ((char *) NULL
, &icnt
, &expr1
,
2565 mips_isa
< 3 ? "addiu" : "daddiu",
2566 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2567 (void) frag_var (rs_machine_dependent
, 0, 0,
2568 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2569 offset_expr
.X_add_symbol
, (long) 0,
2576 /* If we are going to add in a base register, and the
2577 target register and the base register are the same,
2578 then we are using AT as a temporary register. Since
2579 we want to load the constant into AT, we add our
2580 current AT (from the global offset table) and the
2581 register into the register now, and pretend we were
2582 not using a base register. */
2587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2589 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2590 mips_isa
< 3 ? "addu" : "daddu",
2591 "d,v,t", treg
, AT
, breg
);
2597 /* Set mips_optimize around the lui instruction to avoid
2598 inserting an unnecessary nop after the lw. */
2599 hold_mips_optimize
= mips_optimize
;
2601 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2602 mips_optimize
= hold_mips_optimize
;
2604 macro_build ((char *) NULL
, &icnt
, &expr1
,
2605 mips_isa
< 3 ? "addiu" : "daddiu",
2606 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2608 mips_isa
< 3 ? "addu" : "daddu",
2609 "d,v,t", tempreg
, tempreg
, AT
);
2610 (void) frag_var (rs_machine_dependent
, 0, 0,
2611 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2612 offset_expr
.X_add_symbol
, (long) 0,
2617 else if (mips_pic
== EMBEDDED_PIC
)
2620 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2622 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2623 mips_isa
< 3 ? "addiu" : "daddiu",
2624 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2631 mips_isa
< 3 ? "addu" : "daddu",
2632 "d,v,t", treg
, tempreg
, breg
);
2640 /* The j instruction may not be used in PIC code, since it
2641 requires an absolute address. We convert it to a b
2643 if (mips_pic
== NO_PIC
)
2644 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2646 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2649 /* The jal instructions must be handled as macros because when
2650 generating PIC code they expand to multi-instruction
2651 sequences. Normally they are simple instructions. */
2656 if (mips_pic
== NO_PIC
2657 || mips_pic
== EMBEDDED_PIC
)
2658 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2660 else if (mips_pic
== SVR4_PIC
)
2662 if (sreg
!= PIC_CALL_REG
)
2663 as_warn ("MIPS PIC call to register other than $25");
2665 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2667 if (mips_cprestore_offset
< 0)
2668 as_warn ("No .cprestore pseudo-op used in PIC code");
2671 expr1
.X_add_number
= mips_cprestore_offset
;
2672 macro_build ((char *) NULL
, &icnt
, &expr1
,
2673 mips_isa
< 3 ? "lw" : "ld",
2674 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2683 if (mips_pic
== NO_PIC
)
2684 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2685 else if (mips_pic
== SVR4_PIC
)
2687 /* If this is a reference to an external symbol, we want
2688 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2692 lw $gp,cprestore($sp)
2693 The cprestore value is set using the .cprestore
2694 pseudo-op. If the symbol is not external, we want
2695 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2697 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2700 lw $gp,cprestore($sp)
2703 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2704 mips_isa
< 3 ? "lw" : "ld",
2705 "t,o(b)", PIC_CALL_REG
,
2706 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2708 p
= frag_var (rs_machine_dependent
, 4, 0,
2709 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2710 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2711 macro_build (p
, &icnt
, &offset_expr
,
2712 mips_isa
< 3 ? "addiu" : "daddiu",
2713 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2714 (int) BFD_RELOC_LO16
);
2715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2716 "jalr", "s", PIC_CALL_REG
);
2717 if (mips_cprestore_offset
< 0)
2718 as_warn ("No .cprestore pseudo-op used in PIC code");
2722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2724 expr1
.X_add_number
= mips_cprestore_offset
;
2725 macro_build ((char *) NULL
, &icnt
, &expr1
,
2726 mips_isa
< 3 ? "lw" : "ld",
2727 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2731 else if (mips_pic
== EMBEDDED_PIC
)
2733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2734 /* The linker may expand the call to a longer sequence which
2735 uses $at, so we must break rather than return. */
2807 if (breg
== treg
|| coproc
)
2876 if (mask
== M_LWC1_AB
2877 || mask
== M_SWC1_AB
2878 || mask
== M_LDC1_AB
2879 || mask
== M_SDC1_AB
2888 if (offset_expr
.X_op
!= O_constant
2889 && offset_expr
.X_op
!= O_symbol
)
2891 as_bad ("expression too complex");
2892 offset_expr
.X_op
= O_constant
;
2895 /* A constant expression in PIC code can be handled just as it
2896 is in non PIC code. */
2897 if (mips_pic
== NO_PIC
2898 || offset_expr
.X_op
== O_constant
)
2900 /* If this is a reference to a GP relative symbol, and there
2901 is no base register, we want
2902 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2903 Otherwise, if there is no base register, we want
2904 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2905 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2906 If we have a constant, we need two instructions anyhow,
2907 so we always use the latter form.
2909 If we have a base register, and this is a reference to a
2910 GP relative symbol, we want
2911 addu $tempreg,$breg,$gp
2912 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2914 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2915 addu $tempreg,$tempreg,$breg
2916 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2917 With a constant we always use the latter case. */
2920 if (offset_expr
.X_add_number
!= 0)
2925 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2926 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2927 p
= frag_var (rs_machine_dependent
, 8, 0,
2928 RELAX_ENCODE (4, 8, 0, 4, 0,
2929 (mips_warn_about_macros
2930 || (used_at
&& mips_noat
))),
2931 offset_expr
.X_add_symbol
, (long) 0,
2935 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2938 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2939 (int) BFD_RELOC_LO16
, tempreg
);
2943 if (offset_expr
.X_add_number
!= 0)
2948 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2949 mips_isa
< 3 ? "addu" : "daddu",
2950 "d,v,t", tempreg
, breg
, GP
);
2951 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2952 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2953 p
= frag_var (rs_machine_dependent
, 12, 0,
2954 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2955 offset_expr
.X_add_symbol
, (long) 0,
2958 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2961 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2962 mips_isa
< 3 ? "addu" : "daddu",
2963 "d,v,t", tempreg
, tempreg
, breg
);
2966 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2967 (int) BFD_RELOC_LO16
, tempreg
);
2970 else if (mips_pic
== SVR4_PIC
)
2972 /* If this is a reference to an external symbol, we want
2973 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2975 <op> $treg,0($tempreg)
2977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2979 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2980 <op> $treg,0($tempreg)
2981 If there is a base register, we add it to $tempreg before
2982 the <op>. If there is a constant, we stick it in the
2983 <op> instruction. We don't handle constants larger than
2984 16 bits, because we have no way to load the upper 16 bits
2985 (actually, we could handle them for the subset of cases
2986 in which we are not using $at). */
2987 assert (offset_expr
.X_op
== O_symbol
);
2988 expr1
.X_add_number
= offset_expr
.X_add_number
;
2989 offset_expr
.X_add_number
= 0;
2990 if (expr1
.X_add_number
< -0x8000
2991 || expr1
.X_add_number
>= 0x8000)
2992 as_bad ("PIC code offset overflow (max 16 signed bits)");
2994 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2995 mips_isa
< 3 ? "lw" : "ld",
2996 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2997 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2998 p
= frag_var (rs_machine_dependent
, 4, 0,
2999 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3000 offset_expr
.X_add_symbol
, (long) 0,
3002 macro_build (p
, &icnt
, &offset_expr
,
3003 mips_isa
< 3 ? "addiu" : "daddiu",
3004 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3006 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3007 mips_isa
< 3 ? "addu" : "daddu",
3008 "d,v,t", tempreg
, tempreg
, breg
);
3009 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3010 (int) BFD_RELOC_LO16
, tempreg
);
3012 else if (mips_pic
== EMBEDDED_PIC
)
3014 /* If there is no base register, we want
3015 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3016 If there is a base register, we want
3017 addu $tempreg,$breg,$gp
3018 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3020 assert (offset_expr
.X_op
== O_symbol
);
3023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3024 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3030 mips_isa
< 3 ? "addu" : "daddu",
3031 "d,v,t", tempreg
, breg
, GP
);
3032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3033 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3046 load_register (&icnt
, treg
, &imm_expr
);
3050 if (imm_expr
.X_op
== O_constant
)
3052 load_register (&icnt
, AT
, &imm_expr
);
3053 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3054 "mtc1", "t,G", AT
, treg
);
3059 assert (offset_expr
.X_op
== O_symbol
3060 && strcmp (segment_name (S_GET_SEGMENT
3061 (offset_expr
.X_add_symbol
)),
3063 && offset_expr
.X_add_number
== 0);
3064 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3065 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3070 /* We know that sym is in the .rdata section. First we get the
3071 upper 16 bits of the address. */
3072 if (mips_pic
== NO_PIC
)
3074 /* FIXME: This won't work for a 64 bit address. */
3075 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3077 else if (mips_pic
== SVR4_PIC
)
3079 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3080 mips_isa
< 3 ? "lw" : "ld",
3081 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3083 else if (mips_pic
== EMBEDDED_PIC
)
3085 /* For embedded PIC we pick up the entire address off $gp in
3086 a single instruction. */
3087 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3088 mips_isa
< 3 ? "addiu" : "daddiu",
3089 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3090 offset_expr
.X_op
= O_constant
;
3091 offset_expr
.X_add_number
= 0;
3096 /* Now we load the register(s). */
3098 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3099 treg
, (int) BFD_RELOC_LO16
, AT
);
3102 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3103 treg
, (int) BFD_RELOC_LO16
, AT
);
3106 /* FIXME: How in the world do we deal with the possible
3108 offset_expr
.X_add_number
+= 4;
3109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3110 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3114 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3115 does not become a variant frag. */
3116 frag_wane (frag_now
);
3122 assert (offset_expr
.X_op
== O_symbol
3123 && offset_expr
.X_add_number
== 0);
3124 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3125 if (strcmp (s
, ".lit8") == 0)
3129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3130 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3134 r
= BFD_RELOC_MIPS_LITERAL
;
3139 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3140 if (mips_pic
== SVR4_PIC
)
3141 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3142 mips_isa
< 3 ? "lw" : "ld",
3143 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3146 /* FIXME: This won't work for a 64 bit address. */
3147 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3152 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3153 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3162 /* Even on a big endian machine $fn comes before $fn+1. We have
3163 to adjust when loading from memory. */
3166 assert (mips_isa
< 2);
3167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3168 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3170 /* FIXME: A possible overflow which I don't know how to deal
3172 offset_expr
.X_add_number
+= 4;
3173 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3174 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3177 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3178 does not become a variant frag. */
3179 frag_wane (frag_now
);
3188 * The MIPS assembler seems to check for X_add_number not
3189 * being double aligned and generating:
3192 * addiu at,at,%lo(foo+1)
3195 * But, the resulting address is the same after relocation so why
3196 * generate the extra instruction?
3243 if (offset_expr
.X_op
!= O_symbol
3244 && offset_expr
.X_op
!= O_constant
)
3246 as_bad ("expression too complex");
3247 offset_expr
.X_op
= O_constant
;
3250 /* Even on a big endian machine $fn comes before $fn+1. We have
3251 to adjust when loading from memory. We set coproc if we must
3252 load $fn+1 first. */
3253 if (byte_order
== LITTLE_ENDIAN
)
3256 if (mips_pic
== NO_PIC
3257 || offset_expr
.X_op
== O_constant
)
3259 /* If this is a reference to a GP relative symbol, we want
3260 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3261 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3262 If we have a base register, we use this
3264 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3265 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3266 If this is not a GP relative symbol, we want
3267 lui $at,<sym> (BFD_RELOC_HI16_S)
3268 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3269 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3270 If there is a base register, we add it to $at after the
3271 lui instruction. If there is a constant, we always use
3273 if (offset_expr
.X_add_number
!= 0)
3292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3293 mips_isa
< 3 ? "addu" : "daddu",
3294 "d,v,t", AT
, breg
, GP
);
3300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3301 coproc
? treg
+ 1 : treg
,
3302 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3303 offset_expr
.X_add_number
+= 4;
3305 /* Set mips_optimize to 2 to avoid inserting an
3307 hold_mips_optimize
= mips_optimize
;
3309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3310 coproc
? treg
: treg
+ 1,
3311 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3312 mips_optimize
= hold_mips_optimize
;
3314 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3315 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3316 used_at
&& mips_noat
),
3317 offset_expr
.X_add_symbol
, (long) 0,
3320 /* We just generated two relocs. When tc_gen_reloc
3321 handles this case, it will skip the first reloc and
3322 handle the second. The second reloc already has an
3323 extra addend of 4, which we added above. We must
3324 subtract it out, and then subtract another 4 to make
3325 the first reloc come out right. The second reloc
3326 will come out right because we are going to add 4 to
3327 offset_expr when we build its instruction below. */
3328 offset_expr
.X_add_number
-= 8;
3329 offset_expr
.X_op
= O_constant
;
3331 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3336 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3337 mips_isa
< 3 ? "addu" : "daddu",
3338 "d,v,t", AT
, breg
, AT
);
3342 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3343 coproc
? treg
+ 1 : treg
,
3344 (int) BFD_RELOC_LO16
, AT
);
3347 /* FIXME: How do we handle overflow here? */
3348 offset_expr
.X_add_number
+= 4;
3349 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3350 coproc
? treg
: treg
+ 1,
3351 (int) BFD_RELOC_LO16
, AT
);
3353 else if (mips_pic
== SVR4_PIC
)
3357 /* If this is a reference to an external symbol, we want
3358 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3363 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3365 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3366 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3367 If there is a base register we add it to $at before the
3368 lwc1 instructions. If there is a constant we include it
3369 in the lwc1 instructions. */
3371 expr1
.X_add_number
= offset_expr
.X_add_number
;
3372 offset_expr
.X_add_number
= 0;
3373 if (expr1
.X_add_number
< -0x8000
3374 || expr1
.X_add_number
>= 0x8000 - 4)
3375 as_bad ("PIC code offset overflow (max 16 signed bits)");
3380 frag_grow (24 + off
);
3381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3382 mips_isa
< 3 ? "lw" : "ld",
3383 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3387 mips_isa
< 3 ? "addu" : "daddu",
3388 "d,v,t", AT
, breg
, AT
);
3389 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3390 coproc
? treg
+ 1 : treg
,
3391 (int) BFD_RELOC_LO16
, AT
);
3392 expr1
.X_add_number
+= 4;
3394 /* Set mips_optimize to 2 to avoid inserting an undesired
3396 hold_mips_optimize
= mips_optimize
;
3398 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3399 coproc
? treg
: treg
+ 1,
3400 (int) BFD_RELOC_LO16
, AT
);
3401 mips_optimize
= hold_mips_optimize
;
3403 (void) frag_var (rs_machine_dependent
, 0, 0,
3404 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3405 offset_expr
.X_add_symbol
, (long) 0,
3408 else if (mips_pic
== EMBEDDED_PIC
)
3410 /* If there is no base register, we use
3411 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3412 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3413 If we have a base register, we use
3415 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3416 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3426 mips_isa
< 3 ? "addu" : "daddu",
3427 "d,v,t", AT
, breg
, GP
);
3432 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3433 coproc
? treg
+ 1 : treg
,
3434 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3435 offset_expr
.X_add_number
+= 4;
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3437 coproc
? treg
: treg
+ 1,
3438 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3454 assert (mips_isa
< 3);
3455 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3456 (int) BFD_RELOC_LO16
, breg
);
3457 offset_expr
.X_add_number
+= 4;
3458 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3459 (int) BFD_RELOC_LO16
, breg
);
3461 #ifdef LOSING_COMPILER
3467 as_warn ("Macro used $at after \".set noat\"");
3472 struct mips_cl_insn
*ip
;
3474 register int treg
, sreg
, dreg
, breg
;
3487 bfd_reloc_code_real_type r
;
3490 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3491 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3492 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3493 mask
= ip
->insn_mo
->mask
;
3495 expr1
.X_op
= O_constant
;
3496 expr1
.X_op_symbol
= NULL
;
3497 expr1
.X_add_symbol
= NULL
;
3498 expr1
.X_add_number
= 1;
3502 #endif /* LOSING_COMPILER */
3507 macro_build ((char *) NULL
, &icnt
, NULL
,
3508 dbl
? "dmultu" : "multu",
3510 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3516 /* The MIPS assembler some times generates shifts and adds. I'm
3517 not trying to be that fancy. GCC should do this for us
3519 load_register (&icnt
, AT
, &imm_expr
);
3520 macro_build ((char *) NULL
, &icnt
, NULL
,
3521 dbl
? "dmult" : "mult",
3523 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3529 mips_emit_delays ();
3531 mips_any_noreorder
= 1;
3532 macro_build ((char *) NULL
, &icnt
, NULL
,
3533 dbl
? "dmult" : "mult",
3535 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3536 macro_build ((char *) NULL
, &icnt
, NULL
,
3537 dbl
? "dsra32" : "sra",
3538 "d,w,<", dreg
, dreg
, 31);
3539 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3541 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3544 expr1
.X_add_number
= 8;
3545 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3546 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3547 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3550 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3556 mips_emit_delays ();
3558 mips_any_noreorder
= 1;
3559 macro_build ((char *) NULL
, &icnt
, NULL
,
3560 dbl
? "dmultu" : "multu",
3562 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3563 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3565 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3568 expr1
.X_add_number
= 8;
3569 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3570 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3571 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3577 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3578 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3581 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3585 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3586 imm_expr
.X_add_number
& 0x1f);
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3588 (0 - imm_expr
.X_add_number
) & 0x1f);
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3593 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3594 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3595 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3597 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3601 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3602 imm_expr
.X_add_number
& 0x1f);
3603 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3604 (0 - imm_expr
.X_add_number
) & 0x1f);
3605 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3609 assert (mips_isa
< 2);
3610 /* Even on a big endian machine $fn comes before $fn+1. We have
3611 to adjust when storing to memory. */
3612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3613 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3614 (int) BFD_RELOC_LO16
, breg
);
3615 offset_expr
.X_add_number
+= 4;
3616 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3617 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3618 (int) BFD_RELOC_LO16
, breg
);
3623 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3624 treg
, (int) BFD_RELOC_LO16
);
3626 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3627 sreg
, (int) BFD_RELOC_LO16
);
3630 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3632 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3633 dreg
, (int) BFD_RELOC_LO16
);
3638 if (imm_expr
.X_add_number
== 0)
3640 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3641 sreg
, (int) BFD_RELOC_LO16
);
3646 as_warn ("Instruction %s: result is always false",
3648 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3651 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3653 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3654 sreg
, (int) BFD_RELOC_LO16
);
3657 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3659 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3660 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3661 mips_isa
< 3 ? "addiu" : "daddiu",
3662 "t,r,j", dreg
, sreg
,
3663 (int) BFD_RELOC_LO16
);
3668 load_register (&icnt
, AT
, &imm_expr
);
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3673 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3674 (int) BFD_RELOC_LO16
);
3679 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3685 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3686 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3687 (int) BFD_RELOC_LO16
);
3690 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3692 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3694 macro_build ((char *) NULL
, &icnt
, &expr1
,
3695 mask
== M_SGE_I
? "slti" : "sltiu",
3696 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3701 load_register (&icnt
, AT
, &imm_expr
);
3702 macro_build ((char *) NULL
, &icnt
, NULL
,
3703 mask
== M_SGE_I
? "slt" : "sltu",
3704 "d,v,t", dreg
, sreg
, AT
);
3707 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3708 (int) BFD_RELOC_LO16
);
3713 case M_SGT
: /* sreg > treg <==> treg < sreg */
3719 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3722 case M_SGT_I
: /* sreg > I <==> I < sreg */
3728 load_register (&icnt
, AT
, &imm_expr
);
3729 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3732 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3738 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3739 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3740 (int) BFD_RELOC_LO16
);
3743 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3749 load_register (&icnt
, AT
, &imm_expr
);
3750 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3751 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3752 (int) BFD_RELOC_LO16
);
3756 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3758 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3759 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3762 load_register (&icnt
, AT
, &imm_expr
);
3763 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3767 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3769 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3770 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3773 load_register (&icnt
, AT
, &imm_expr
);
3774 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3783 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3787 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3789 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3795 if (imm_expr
.X_add_number
== 0)
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3803 as_warn ("Instruction %s: result is always true",
3805 macro_build ((char *) NULL
, &icnt
, &expr1
,
3806 mips_isa
< 3 ? "addiu" : "daddiu",
3807 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3810 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3812 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3813 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3816 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3818 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3819 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3820 mips_isa
< 3 ? "addiu" : "daddiu",
3821 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3826 load_register (&icnt
, AT
, &imm_expr
);
3827 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3831 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3839 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3841 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3842 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3843 dbl
? "daddi" : "addi",
3844 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3847 load_register (&icnt
, AT
, &imm_expr
);
3848 macro_build ((char *) NULL
, &icnt
, NULL
,
3849 dbl
? "dsub" : "sub",
3850 "d,v,t", dreg
, sreg
, AT
);
3856 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3858 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3859 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3860 dbl
? "daddiu" : "addiu",
3861 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3864 load_register (&icnt
, AT
, &imm_expr
);
3865 macro_build ((char *) NULL
, &icnt
, NULL
,
3866 dbl
? "dsubu" : "subu",
3867 "d,v,t", dreg
, sreg
, AT
);
3888 load_register (&icnt
, AT
, &imm_expr
);
3889 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3894 assert (mips_isa
< 2);
3895 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3896 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3899 * Is the double cfc1 instruction a bug in the mips assembler;
3900 * or is there a reason for it?
3902 mips_emit_delays ();
3904 mips_any_noreorder
= 1;
3905 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3906 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3907 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3908 expr1
.X_add_number
= 3;
3909 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3910 (int) BFD_RELOC_LO16
);
3911 expr1
.X_add_number
= 2;
3912 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3913 (int) BFD_RELOC_LO16
);
3914 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3915 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3916 macro_build ((char *) NULL
, &icnt
, NULL
,
3917 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3918 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3929 if (offset_expr
.X_add_number
>= 0x7fff)
3930 as_bad ("operand overflow");
3931 /* avoid load delay */
3932 if (byte_order
== LITTLE_ENDIAN
)
3933 offset_expr
.X_add_number
+= 1;
3934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3935 (int) BFD_RELOC_LO16
, breg
);
3936 if (byte_order
== LITTLE_ENDIAN
)
3937 offset_expr
.X_add_number
-= 1;
3939 offset_expr
.X_add_number
+= 1;
3940 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3941 (int) BFD_RELOC_LO16
, breg
);
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3943 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3947 if (offset_expr
.X_add_number
>= 0x7ffd)
3948 as_bad ("operand overflow");
3949 if (byte_order
== LITTLE_ENDIAN
)
3950 offset_expr
.X_add_number
+= 3;
3951 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3952 (int) BFD_RELOC_LO16
, breg
);
3953 if (byte_order
== LITTLE_ENDIAN
)
3954 offset_expr
.X_add_number
-= 3;
3956 offset_expr
.X_add_number
+= 3;
3957 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3958 (int) BFD_RELOC_LO16
, breg
);
3964 load_address (&icnt
, AT
, &offset_expr
);
3965 if (mask
== M_ULW_A
)
3967 if (byte_order
== LITTLE_ENDIAN
)
3968 expr1
.X_add_number
= 3;
3970 expr1
.X_add_number
= 0;
3971 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3972 (int) BFD_RELOC_LO16
, AT
);
3973 if (byte_order
== LITTLE_ENDIAN
)
3974 expr1
.X_add_number
= 0;
3976 expr1
.X_add_number
= 3;
3977 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3978 (int) BFD_RELOC_LO16
, AT
);
3982 if (byte_order
== BIG_ENDIAN
)
3983 expr1
.X_add_number
= 0;
3984 macro_build ((char *) NULL
, &icnt
, &expr1
,
3985 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3986 (int) BFD_RELOC_LO16
, AT
);
3987 if (byte_order
== BIG_ENDIAN
)
3988 expr1
.X_add_number
= 1;
3990 expr1
.X_add_number
= 0;
3991 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3992 (int) BFD_RELOC_LO16
, AT
);
3993 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3995 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4001 if (offset_expr
.X_add_number
>= 0x7fff)
4002 as_bad ("operand overflow");
4003 if (byte_order
== BIG_ENDIAN
)
4004 offset_expr
.X_add_number
+= 1;
4005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4006 (int) BFD_RELOC_LO16
, breg
);
4007 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4008 if (byte_order
== BIG_ENDIAN
)
4009 offset_expr
.X_add_number
-= 1;
4011 offset_expr
.X_add_number
+= 1;
4012 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4013 (int) BFD_RELOC_LO16
, breg
);
4017 if (offset_expr
.X_add_number
>= 0x7ffd)
4018 as_bad ("operand overflow");
4019 if (byte_order
== LITTLE_ENDIAN
)
4020 offset_expr
.X_add_number
+= 3;
4021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
4022 (int) BFD_RELOC_LO16
, breg
);
4023 if (byte_order
== LITTLE_ENDIAN
)
4024 offset_expr
.X_add_number
-= 3;
4026 offset_expr
.X_add_number
+= 3;
4027 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
4028 (int) BFD_RELOC_LO16
, breg
);
4033 load_address (&icnt
, AT
, &offset_expr
);
4034 if (mask
== M_USW_A
)
4036 if (byte_order
== LITTLE_ENDIAN
)
4037 expr1
.X_add_number
= 3;
4039 expr1
.X_add_number
= 0;
4040 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
4041 (int) BFD_RELOC_LO16
, AT
);
4042 if (byte_order
== LITTLE_ENDIAN
)
4043 expr1
.X_add_number
= 0;
4045 expr1
.X_add_number
= 3;
4046 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
4047 (int) BFD_RELOC_LO16
, AT
);
4051 if (byte_order
== LITTLE_ENDIAN
)
4052 expr1
.X_add_number
= 0;
4053 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4054 (int) BFD_RELOC_LO16
, AT
);
4055 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4057 if (byte_order
== LITTLE_ENDIAN
)
4058 expr1
.X_add_number
= 1;
4060 expr1
.X_add_number
= 0;
4061 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4062 (int) BFD_RELOC_LO16
, AT
);
4063 if (byte_order
== LITTLE_ENDIAN
)
4064 expr1
.X_add_number
= 0;
4066 expr1
.X_add_number
= 1;
4067 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4068 (int) BFD_RELOC_LO16
, AT
);
4069 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4071 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4077 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4081 as_warn ("Macro used $at after \".set noat\"");
4086 This routine assembles an instruction into its binary format. As a side
4087 effect it sets one of the global variables imm_reloc or offset_reloc to the
4088 type of relocation to do if one of the operands is an address expression.
4093 struct mips_cl_insn
*ip
;
4098 struct mips_opcode
*insn
;
4101 unsigned int lastregno
= 0;
4106 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4118 as_fatal ("Unknown opcode: `%s'", str
);
4120 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4122 as_warn ("`%s' not in hash table.", str
);
4123 insn_error
= "ERROR: Unrecognized opcode";
4131 assert (strcmp (insn
->name
, str
) == 0);
4133 if (insn
->pinfo
== INSN_MACRO
)
4134 insn_isa
= insn
->match
;
4135 else if (insn
->pinfo
& INSN_ISA2
)
4137 else if (insn
->pinfo
& INSN_ISA3
)
4142 if (insn_isa
> mips_isa
)
4144 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4145 && strcmp (insn
->name
, insn
[1].name
) == 0)
4150 as_warn ("Instruction not supported on this processor");
4154 ip
->insn_opcode
= insn
->match
;
4155 for (args
= insn
->args
;; ++args
)
4161 case '\0': /* end of args */
4174 ip
->insn_opcode
|= lastregno
<< 21;
4179 ip
->insn_opcode
|= lastregno
<< 16;
4183 ip
->insn_opcode
|= lastregno
<< 11;
4189 /* handle optional base register.
4190 Either the base register is omitted or
4191 we must have a left paren. */
4192 /* this is dependent on the next operand specifier
4193 is a 'b' for base register */
4194 assert (args
[1] == 'b');
4198 case ')': /* these must match exactly */
4203 case '<': /* must be at least one digit */
4205 * According to the manual, if the shift amount is greater
4206 * than 31 or less than 0 the the shift amount should be
4207 * mod 32. In reality the mips assembler issues an error.
4208 * We issue a warning and mask out all but the low 5 bits.
4210 my_getExpression (&imm_expr
, s
);
4211 check_absolute_expr (ip
, &imm_expr
);
4212 if ((unsigned long) imm_expr
.X_add_number
> 31)
4214 as_warn ("Improper shift amount (%ld)",
4215 (long) imm_expr
.X_add_number
);
4216 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4218 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4219 imm_expr
.X_op
= O_absent
;
4223 case '>': /* shift amount minus 32 */
4224 my_getExpression (&imm_expr
, s
);
4225 check_absolute_expr (ip
, &imm_expr
);
4226 if ((unsigned long) imm_expr
.X_add_number
< 32
4227 || (unsigned long) imm_expr
.X_add_number
> 63)
4229 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4230 imm_expr
.X_op
= O_absent
;
4234 case 'k': /* cache code */
4235 my_getExpression (&imm_expr
, s
);
4236 check_absolute_expr (ip
, &imm_expr
);
4237 if ((unsigned long) imm_expr
.X_add_number
> 31)
4239 as_warn ("Invalid cahce opcode (%lu)",
4240 (unsigned long) imm_expr
.X_add_number
);
4241 imm_expr
.X_add_number
&= 0x1f;
4243 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4244 imm_expr
.X_op
= O_absent
;
4248 case 'c': /* break code */
4249 my_getExpression (&imm_expr
, s
);
4250 check_absolute_expr (ip
, &imm_expr
);
4251 if ((unsigned) imm_expr
.X_add_number
> 1023)
4252 as_warn ("Illegal break code (%ld)",
4253 (long) imm_expr
.X_add_number
);
4254 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4255 imm_expr
.X_op
= O_absent
;
4259 case 'B': /* syscall code */
4260 my_getExpression (&imm_expr
, s
);
4261 check_absolute_expr (ip
, &imm_expr
);
4262 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4263 as_warn ("Illegal syscall code (%ld)",
4264 (long) imm_expr
.X_add_number
);
4265 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4266 imm_expr
.X_op
= O_absent
;
4270 case 'C': /* Coprocessor code */
4271 my_getExpression (&imm_expr
, s
);
4272 check_absolute_expr (ip
, &imm_expr
);
4273 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4275 as_warn ("Coproccesor code > 25 bits (%ld)",
4276 (long) imm_expr
.X_add_number
);
4277 imm_expr
.X_add_number
&= ((1<<25) - 1);
4279 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4280 imm_expr
.X_op
= O_absent
;
4284 case 'b': /* base register */
4285 case 'd': /* destination register */
4286 case 's': /* source register */
4287 case 't': /* target register */
4288 case 'r': /* both target and source */
4289 case 'v': /* both dest and source */
4290 case 'w': /* both dest and target */
4291 case 'E': /* coprocessor target register */
4292 case 'G': /* coprocessor destination register */
4293 case 'x': /* ignore register name */
4294 case 'z': /* must be zero register */
4308 while (isdigit (*s
));
4310 as_bad ("Invalid register number (%d)", regno
);
4312 else if (*args
== 'E' || *args
== 'G')
4316 if (s
[1] == 'f' && s
[2] == 'p')
4321 else if (s
[1] == 's' && s
[2] == 'p')
4326 else if (s
[1] == 'g' && s
[2] == 'p')
4331 else if (s
[1] == 'a' && s
[2] == 't')
4339 if (regno
== AT
&& ! mips_noat
)
4340 as_warn ("Used $at without \".set noat\"");
4346 if (c
== 'r' || c
== 'v' || c
== 'w')
4353 /* 'z' only matches $0. */
4354 if (c
== 'z' && regno
!= 0)
4362 ip
->insn_opcode
|= regno
<< 21;
4366 ip
->insn_opcode
|= regno
<< 11;
4371 ip
->insn_opcode
|= regno
<< 16;
4374 /* This case exists because on the r3000 trunc
4375 expands into a macro which requires a gp
4376 register. On the r6000 or r4000 it is
4377 assembled into a single instruction which
4378 ignores the register. Thus the insn version
4379 is MIPS_ISA2 and uses 'x', and the macro
4380 version is MIPS_ISA1 and uses 't'. */
4383 /* This case is for the div instruction, which
4384 acts differently if the destination argument
4385 is $0. This only matches $0, and is checked
4386 outside the switch. */
4397 ip
->insn_opcode
|= lastregno
<< 21;
4400 ip
->insn_opcode
|= lastregno
<< 16;
4405 case 'D': /* floating point destination register */
4406 case 'S': /* floating point source register */
4407 case 'T': /* floating point target register */
4411 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4421 while (isdigit (*s
));
4424 as_bad ("Invalid float register number (%d)", regno
);
4426 if ((regno
& 1) != 0
4428 && ! (strcmp (str
, "mtc1") == 0 ||
4429 strcmp (str
, "mfc1") == 0 ||
4430 strcmp (str
, "lwc1") == 0 ||
4431 strcmp (str
, "swc1") == 0))
4432 as_warn ("Float register should be even, was %d",
4440 if (c
== 'V' || c
== 'W')
4450 ip
->insn_opcode
|= regno
<< 6;
4454 ip
->insn_opcode
|= regno
<< 11;
4458 ip
->insn_opcode
|= regno
<< 16;
4466 ip
->insn_opcode
|= lastregno
<< 11;
4469 ip
->insn_opcode
|= lastregno
<< 16;
4475 my_getExpression (&imm_expr
, s
);
4476 check_absolute_expr (ip
, &imm_expr
);
4481 my_getExpression (&offset_expr
, s
);
4482 imm_reloc
= BFD_RELOC_32
;
4494 unsigned char temp
[8];
4496 unsigned int length
;
4501 /* These only appear as the last operand in an
4502 instruction, and every instruction that accepts
4503 them in any variant accepts them in all variants.
4504 This means we don't have to worry about backing out
4505 any changes if the instruction does not match.
4507 The difference between them is the size of the
4508 floating point constant and where it goes. For 'F'
4509 and 'L' the constant is 64 bits; for 'f' and 'l' it
4510 is 32 bits. Where the constant is placed is based
4511 on how the MIPS assembler does things:
4514 f -- immediate value
4517 The .lit4 and .lit8 sections are only used if
4518 permitted by the -G argument.
4520 When generating embedded PIC code, we use the
4521 .lit8 section but not the .lit4 section (we can do
4522 .lit4 inline easily; we need to put .lit8
4523 somewhere in the data segment, and using .lit8
4524 permits the linker to eventually combine identical
4527 f64
= *args
== 'F' || *args
== 'L';
4529 save_in
= input_line_pointer
;
4530 input_line_pointer
= s
;
4531 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4533 s
= input_line_pointer
;
4534 input_line_pointer
= save_in
;
4535 if (err
!= NULL
&& *err
!= '\0')
4537 as_bad ("Bad floating point constant: %s", err
);
4538 memset (temp
, '\0', sizeof temp
);
4539 length
= f64
? 8 : 4;
4542 assert (length
== (f64
? 8 : 4));
4546 && (mips_pic
== EMBEDDED_PIC
4548 || g_switch_value
< 4
4552 imm_expr
.X_op
= O_constant
;
4553 if (byte_order
== LITTLE_ENDIAN
)
4554 imm_expr
.X_add_number
=
4555 (((((((int) temp
[3] << 8)
4560 imm_expr
.X_add_number
=
4561 (((((((int) temp
[0] << 8)
4568 const char *newname
;
4571 /* Switch to the right section. */
4573 subseg
= now_subseg
;
4576 default: /* unused default case avoids warnings. */
4580 if (g_switch_value
< 8)
4581 newname
= RDATA_SECTION_NAME
;
4585 newname
= RDATA_SECTION_NAME
;
4589 assert (g_switch_value
>= 4);
4594 new_seg
= subseg_new (newname
, (subsegT
) 0);
4595 frag_align (*args
== 'l' ? 2 : 3, 0);
4597 record_alignment (new_seg
, 4);
4599 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4602 as_bad ("Can't use floating point insn in this section");
4604 /* Set the argument to the current address in the
4606 offset_expr
.X_op
= O_symbol
;
4607 offset_expr
.X_add_symbol
=
4608 symbol_new ("L0\001", now_seg
,
4609 (valueT
) frag_now_fix (), frag_now
);
4610 offset_expr
.X_add_number
= 0;
4612 /* Put the floating point number into the section. */
4613 p
= frag_more ((int) length
);
4614 memcpy (p
, temp
, length
);
4616 /* Switch back to the original section. */
4617 subseg_set (seg
, subseg
);
4622 case 'i': /* 16 bit unsigned immediate */
4623 case 'j': /* 16 bit signed immediate */
4624 imm_reloc
= BFD_RELOC_LO16
;
4625 c
= my_getSmallExpression (&imm_expr
, s
);
4630 if (imm_expr
.X_op
== O_constant
)
4631 imm_expr
.X_add_number
=
4632 (imm_expr
.X_add_number
>> 16) & 0xffff;
4634 imm_reloc
= BFD_RELOC_HI16_S
;
4636 imm_reloc
= BFD_RELOC_HI16
;
4640 check_absolute_expr (ip
, &imm_expr
);
4643 if (imm_expr
.X_add_number
< 0
4644 || imm_expr
.X_add_number
>= 0x10000)
4646 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4647 !strcmp (insn
->name
, insn
[1].name
))
4649 as_bad ("16 bit expression not in range 0..65535");
4657 /* The upper bound should be 0x8000, but
4658 unfortunately the MIPS assembler accepts numbers
4659 from 0x8000 to 0xffff and sign extends them, and
4660 we want to be compatible. We only permit this
4661 extended range for an instruction which does not
4662 provide any further alternates, since those
4663 alternates may handle other cases. People should
4664 use the numbers they mean, rather than relying on
4665 a mysterious sign extension. */
4666 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4667 strcmp (insn
->name
, insn
[1].name
) == 0);
4672 if (imm_expr
.X_add_number
< -0x8000 ||
4673 imm_expr
.X_add_number
>= max
)
4677 as_bad ("16 bit expression not in range -32768..32767");
4683 case 'o': /* 16 bit offset */
4684 c
= my_getSmallExpression (&offset_expr
, s
);
4686 /* If this value won't fit into a 16 bit offset, then go
4687 find a macro that will generate the 32 bit offset
4688 code pattern. As a special hack, we accept the
4689 difference of two local symbols as a constant. This
4690 is required to suppose embedded PIC switches, which
4691 use an instruction which looks like
4692 lw $4,$L12-$LS12($4)
4693 The problem with handling this in a more general
4694 fashion is that the macro function doesn't expect to
4695 see anything which can be handled in a single
4696 constant instruction. */
4698 && (offset_expr
.X_op
!= O_constant
4699 || offset_expr
.X_add_number
>= 0x8000
4700 || offset_expr
.X_add_number
< -0x8000)
4701 && (mips_pic
!= EMBEDDED_PIC
4702 || offset_expr
.X_op
!= O_subtract
4703 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4704 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4707 offset_reloc
= BFD_RELOC_LO16
;
4708 if (c
== 'h' || c
== 'H')
4710 assert (offset_expr
.X_op
== O_constant
);
4711 offset_expr
.X_add_number
=
4712 (offset_expr
.X_add_number
>> 16) & 0xffff;
4717 case 'p': /* pc relative offset */
4718 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4719 my_getExpression (&offset_expr
, s
);
4723 case 'u': /* upper 16 bits */
4724 c
= my_getSmallExpression (&imm_expr
, s
);
4725 if (imm_expr
.X_op
== O_constant
4726 && (imm_expr
.X_add_number
< 0
4727 || imm_expr
.X_add_number
>= 0x10000))
4728 as_bad ("lui expression not in range 0..65535");
4729 imm_reloc
= BFD_RELOC_LO16
;
4734 if (imm_expr
.X_op
== O_constant
)
4735 imm_expr
.X_add_number
=
4736 (imm_expr
.X_add_number
>> 16) & 0xffff;
4738 imm_reloc
= BFD_RELOC_HI16_S
;
4740 imm_reloc
= BFD_RELOC_HI16
;
4746 case 'a': /* 26 bit address */
4747 my_getExpression (&offset_expr
, s
);
4749 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4753 fprintf (stderr
, "bad char = '%c'\n", *args
);
4758 /* Args don't match. */
4759 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4760 !strcmp (insn
->name
, insn
[1].name
))
4766 insn_error
= "ERROR: Illegal operands";
4775 my_getSmallExpression (ep
, str
)
4786 ((str
[1] == 'h' && str
[2] == 'i')
4787 || (str
[1] == 'H' && str
[2] == 'I')
4788 || (str
[1] == 'l' && str
[2] == 'o'))
4800 * A small expression may be followed by a base register.
4801 * Scan to the end of this operand, and then back over a possible
4802 * base register. Then scan the small expression up to that
4803 * point. (Based on code in sparc.c...)
4805 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4807 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4809 if (isdigit (sp
[-2]))
4811 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4813 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4819 else if (sp
- 5 >= str
4822 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4823 || (sp
[-3] == 's' && sp
[-2] == 'p')
4824 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4825 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4831 /* no expression means zero offset */
4834 /* %xx(reg) is an error */
4835 ep
->X_op
= O_absent
;
4840 ep
->X_op
= O_constant
;
4843 ep
->X_add_symbol
= NULL
;
4844 ep
->X_op_symbol
= NULL
;
4845 ep
->X_add_number
= 0;
4850 my_getExpression (ep
, str
);
4857 my_getExpression (ep
, str
);
4858 return c
; /* => %hi or %lo encountered */
4862 my_getExpression (ep
, str
)
4868 save_in
= input_line_pointer
;
4869 input_line_pointer
= str
;
4871 expr_end
= input_line_pointer
;
4872 input_line_pointer
= save_in
;
4875 /* Turn a string in input_line_pointer into a floating point constant
4876 of type type, and store the appropriate bytes in *litP. The number
4877 of LITTLENUMS emitted is stored in *sizeP . An error message is
4878 returned, or NULL on OK. */
4881 md_atof (type
, litP
, sizeP
)
4887 LITTLENUM_TYPE words
[4];
4903 return "bad call to md_atof";
4906 t
= atof_ieee (input_line_pointer
, type
, words
);
4908 input_line_pointer
= t
;
4912 if (byte_order
== LITTLE_ENDIAN
)
4914 for (i
= prec
- 1; i
>= 0; i
--)
4916 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4922 for (i
= 0; i
< prec
; i
++)
4924 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4933 md_number_to_chars (buf
, val
, n
)
4941 number_to_chars_littleendian (buf
, val
, n
);
4945 number_to_chars_bigendian (buf
, val
, n
);
4954 CONST
char *md_shortopts
= "O::g::G:";
4956 CONST
char *md_shortopts
= "O::g::";
4958 struct option md_longopts
[] = {
4959 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4960 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4961 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4962 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4963 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4964 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4965 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4966 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4967 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4968 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4969 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4970 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4971 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4972 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4973 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4974 {"break", no_argument
, NULL
, OPTION_BREAK
},
4975 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4976 #define OPTION_EB (OPTION_MD_BASE + 10)
4977 {"EB", no_argument
, NULL
, OPTION_EB
},
4978 #define OPTION_EL (OPTION_MD_BASE + 11)
4979 {"EL", no_argument
, NULL
, OPTION_EL
},
4982 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
4983 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
4984 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
4985 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
4986 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
4989 {NULL
, no_argument
, NULL
, 0}
4991 size_t md_longopts_size
= sizeof(md_longopts
);
4994 md_parse_option (c
, arg
)
5009 byte_order
= BIG_ENDIAN
;
5011 mips_target_format
= "a.out-mips-big";
5014 mips_target_format
= "ecoff-bigmips";
5017 mips_target_format
= "elf32-bigmips";
5022 byte_order
= LITTLE_ENDIAN
;
5024 mips_target_format
= "a.out-mips-little";
5027 mips_target_format
= "ecoff-littlemips";
5030 mips_target_format
= "elf32-littlemips";
5035 if (arg
&& arg
[1] == '0')
5042 if (arg
== NULL
|| arg
[1] == '2')
5065 /* Identify the processor type */
5067 if (strcmp (p
, "default") == 0
5068 || strcmp (p
, "DEFAULT") == 0)
5072 if (*p
== 'r' || *p
== 'R')
5079 if (strcmp (p
, "2000") == 0
5080 || strcmp (p
, "2k") == 0
5081 || strcmp (p
, "2K") == 0)
5089 if (strcmp (p
, "3000") == 0
5090 || strcmp (p
, "3k") == 0
5091 || strcmp (p
, "3K") == 0)
5099 if (strcmp (p
, "4000") == 0
5100 || strcmp (p
, "4k") == 0
5101 || strcmp (p
, "4K") == 0)
5106 else if (strcmp (p
, "4400") == 0)
5111 else if (strcmp (p
, "4600") == 0)
5119 if (strcmp (p
, "6000") == 0
5120 || strcmp (p
, "6k") == 0
5121 || strcmp (p
, "6K") == 0)
5129 if (strcmp (p
, "orion") == 0)
5139 as_bad ("invalid architecture -mcpu=%s", arg
);
5146 case OPTION_MEMBEDDED_PIC
:
5147 mips_pic
= EMBEDDED_PIC
;
5151 as_bad ("-G may not be used with embedded PIC code");
5154 g_switch_value
= 0x7fffffff;
5159 /* When generating ELF code, we permit -KPIC and -call_shared to
5160 select SVR4_PIC, and -non_shared to select no PIC. This is
5161 intended to be compatible with Irix 5. */
5162 case OPTION_CALL_SHARED
:
5163 mips_pic
= SVR4_PIC
;
5164 if (g_switch_seen
&& g_switch_value
!= 0)
5166 as_bad ("-G may not be used with SVR4 PIC code");
5172 case OPTION_NON_SHARED
:
5175 #endif /* OBJ_ELF */
5179 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5181 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5185 g_switch_value
= atoi (arg
);
5198 md_show_usage (stream
)
5203 -membedded-pic generate embedded position independent code\n\
5204 -EB generate big endian output\n\
5205 -EL generate little endian output\n\
5206 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5207 -G NUM allow referencing objects up to NUM bytes\n\
5208 implicitly with the gp register [default 8]\n");
5210 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5211 -mips2, -mcpu=r6000 generate code for r6000\n\
5212 -mips3, -mcpu=r4000 generate code for r4000\n\
5213 -O0 remove unneeded NOPs, do not swap branches\n\
5214 -O remove unneeded NOPs and swap branches\n\
5215 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5216 --break, --no-trap break exception on div by 0 and mult overflow\n");
5219 -KPIC, -call_shared generate SVR4 position independent code\n\
5220 -non_shared do not generate position independent code\n");
5225 md_pcrel_from (fixP
)
5229 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5230 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5232 /* This makes a branch to an undefined symbol be a branch to the
5233 current location. */
5238 /* return the address of the delay slot */
5239 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5242 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5243 reloc for a cons. We could use the definition there, except that
5244 we want to handle 64 bit relocs specially. */
5247 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5250 unsigned int nbytes
;
5253 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5255 FIXME: There is no way to select anything but 32 bit mode right
5259 if (byte_order
== BIG_ENDIAN
)
5264 if (nbytes
!= 2 && nbytes
!= 4)
5265 as_bad ("Unsupported reloc size %d", nbytes
);
5267 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5268 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5271 /* When generating embedded PIC code we need to use a special
5272 relocation to represent the difference of two symbols in the .text
5273 section (switch tables use a difference of this sort). See
5274 include/coff/mips.h for details. This macro checks whether this
5275 fixup requires the special reloc. */
5276 #define SWITCH_TABLE(fixp) \
5277 ((fixp)->fx_r_type == BFD_RELOC_32 \
5278 && (fixp)->fx_addsy != NULL \
5279 && (fixp)->fx_subsy != NULL \
5280 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5281 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5283 /* When generating embedded PIC code we must keep all PC relative
5284 relocations, in case the linker has to relax a call. We also need
5285 to keep relocations for switch table entries. */
5289 mips_force_relocation (fixp
)
5292 return (mips_pic
== EMBEDDED_PIC
5294 || SWITCH_TABLE (fixp
)
5295 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5296 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5299 /* Apply a fixup to the object file. */
5302 md_apply_fix (fixP
, valueP
)
5309 assert (fixP
->fx_size
== 4);
5312 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5314 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5317 switch (fixP
->fx_r_type
)
5319 case BFD_RELOC_MIPS_JMP
:
5320 case BFD_RELOC_HI16
:
5321 case BFD_RELOC_HI16_S
:
5322 case BFD_RELOC_MIPS_GPREL
:
5323 case BFD_RELOC_MIPS_LITERAL
:
5324 case BFD_RELOC_MIPS_CALL16
:
5325 case BFD_RELOC_MIPS_GOT16
:
5326 case BFD_RELOC_MIPS_GPREL32
:
5328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5329 "Invalid PC relative reloc");
5330 /* Nothing needed to do. The value comes from the reloc entry */
5333 case BFD_RELOC_PCREL_HI16_S
:
5334 /* The addend for this is tricky if it is internal, so we just
5335 do everything here rather than in bfd_perform_relocation. */
5336 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5338 /* For an external symbol adjust by the address to make it
5339 pcrel_offset. We use the address of the RELLO reloc
5340 which follows this one. */
5341 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5342 + fixP
->fx_next
->fx_where
);
5347 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5348 if (byte_order
== BIG_ENDIAN
)
5350 md_number_to_chars (buf
, value
, 2);
5353 case BFD_RELOC_PCREL_LO16
:
5354 /* The addend for this is tricky if it is internal, so we just
5355 do everything here rather than in bfd_perform_relocation. */
5356 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5357 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5358 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5359 if (byte_order
== BIG_ENDIAN
)
5361 md_number_to_chars (buf
, value
, 2);
5365 /* If we are deleting this reloc entry, we must fill in the
5366 value now. This can happen if we have a .word which is not
5367 resolved when it appears but is later defined. We also need
5368 to fill in the value if this is an embedded PIC switch table
5371 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5372 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5376 case BFD_RELOC_LO16
:
5377 /* When handling an embedded PIC switch statement, we can wind
5378 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5381 if (value
< -0x8000 || value
> 0x7fff)
5382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5383 "relocation overflow");
5384 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5385 if (byte_order
== BIG_ENDIAN
)
5387 md_number_to_chars (buf
, value
, 2);
5391 case BFD_RELOC_16_PCREL_S2
:
5393 * We need to save the bits in the instruction since fixup_segment()
5394 * might be deleting the relocation entry (i.e., a branch within
5395 * the current segment).
5398 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5399 "Branch to odd address (%lx)", value
);
5401 if (value
< -0x8000 || value
>= 0x8000)
5402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "Relocation overflow");
5404 /* update old instruction data */
5405 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5409 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5413 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5420 insn
|= value
& 0xFFFF;
5421 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5436 const struct mips_opcode
*p
;
5437 int treg
, sreg
, dreg
, shamt
;
5442 for (i
= 0; i
< NUMOPCODES
; ++i
)
5444 p
= &mips_opcodes
[i
];
5445 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5447 printf ("%08lx %s\t", oc
, p
->name
);
5448 treg
= (oc
>> 16) & 0x1f;
5449 sreg
= (oc
>> 21) & 0x1f;
5450 dreg
= (oc
>> 11) & 0x1f;
5451 shamt
= (oc
>> 6) & 0x1f;
5453 for (args
= p
->args
;; ++args
)
5464 printf ("%c", *args
);
5468 assert (treg
== sreg
);
5469 printf ("$%d,$%d", treg
, sreg
);
5474 printf ("$%d", dreg
);
5479 printf ("$%d", treg
);
5483 printf ("0x%x", treg
);
5488 printf ("$%d", sreg
);
5492 printf ("0x%08lx", oc
& 0x1ffffff);
5504 printf ("$%d", shamt
);
5515 printf ("%08lx UNDEFINED\n", oc
);
5526 name
= input_line_pointer
;
5527 c
= get_symbol_end ();
5528 p
= (symbolS
*) symbol_find_or_make (name
);
5529 *input_line_pointer
= c
;
5533 /* Align the current frag to a given power of two. The MIPS assembler
5534 also automatically adjusts any preceding label. */
5537 mips_align (to
, fill
, label
)
5542 mips_emit_delays ();
5543 frag_align (to
, fill
);
5544 record_alignment (now_seg
, to
);
5547 assert (S_GET_SEGMENT (label
) == now_seg
);
5548 label
->sy_frag
= frag_now
;
5549 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5553 /* Align to a given power of two. .align 0 turns off the automatic
5554 alignment used by the data creating pseudo-ops. */
5561 register long temp_fill
;
5562 long max_alignment
= 15;
5566 o Note that the assembler pulls down any immediately preceeding label
5567 to the aligned address.
5568 o It's not documented but auto alignment is reinstated by
5569 a .align pseudo instruction.
5570 o Note also that after auto alignment is turned off the mips assembler
5571 issues an error on attempt to assemble an improperly aligned data item.
5576 temp
= get_absolute_expression ();
5577 if (temp
> max_alignment
)
5578 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5581 as_warn ("Alignment negative: 0 assumed.");
5584 if (*input_line_pointer
== ',')
5586 input_line_pointer
++;
5587 temp_fill
= get_absolute_expression ();
5594 mips_align (temp
, (int) temp_fill
, insn_label
);
5601 demand_empty_rest_of_line ();
5604 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5605 that there was a previous instruction. */
5608 s_stringer (append_zero
)
5611 mips_emit_delays ();
5613 stringer (append_zero
);
5624 /* When generating embedded PIC code, we only use the .text, .lit8,
5625 .sdata and .sbss sections. We change the .data and .rdata
5626 pseudo-ops to use .sdata. */
5627 if (mips_pic
== EMBEDDED_PIC
5628 && (sec
== 'd' || sec
== 'r'))
5631 mips_emit_delays ();
5641 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5642 demand_empty_rest_of_line ();
5646 seg
= subseg_new (RDATA_SECTION_NAME
,
5647 (subsegT
) get_absolute_expression ());
5649 bfd_set_section_flags (stdoutput
, seg
,
5655 bfd_set_section_alignment (stdoutput
, seg
, 4);
5657 demand_empty_rest_of_line ();
5662 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5664 bfd_set_section_flags (stdoutput
, seg
,
5665 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5666 bfd_set_section_alignment (stdoutput
, seg
, 4);
5668 demand_empty_rest_of_line ();
5670 #else /* ! defined (GPOPT) */
5671 as_bad ("Global pointers not supported; recompile -G 0");
5672 demand_empty_rest_of_line ();
5674 #endif /* ! defined (GPOPT) */
5687 mips_emit_delays ();
5688 if (log_size
> 0 && auto_align
)
5689 mips_align (log_size
, 0, label
);
5691 cons (1 << log_size
);
5698 as_fatal ("Encountered `.err', aborting assembly");
5708 symbolP
= get_symbol ();
5709 if (*input_line_pointer
== ',')
5710 input_line_pointer
++;
5711 size
= get_absolute_expression ();
5712 S_SET_EXTERNAL (symbolP
);
5714 #ifdef ECOFF_DEBUGGING
5715 symbolP
->ecoff_extern_size
= size
;
5727 mips_emit_delays ();
5731 mips_align (3, 0, label
);
5733 mips_align (2, 0, label
);
5740 /* Handle .globl. We need to override it because on Irix 5 you are
5743 where foo is an undefined symbol, to mean that foo should be
5744 considered to be the address of a function. */
5754 name
= input_line_pointer
;
5755 c
= get_symbol_end ();
5756 symbolP
= symbol_find_or_make (name
);
5757 *input_line_pointer
= c
;
5759 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5764 secname
= input_line_pointer
;
5765 c
= get_symbol_end ();
5766 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5768 as_bad ("%s: no such section", secname
);
5769 *input_line_pointer
= c
;
5771 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5772 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5775 S_SET_EXTERNAL (symbolP
);
5776 demand_empty_rest_of_line ();
5786 opt
= input_line_pointer
;
5787 c
= get_symbol_end ();
5791 /* FIXME: What does this mean? */
5793 else if (strncmp (opt
, "pic", 3) == 0)
5801 mips_pic
= SVR4_PIC
;
5803 as_bad (".option pic%d not supported", i
);
5806 if (mips_pic
== SVR4_PIC
)
5808 if (g_switch_seen
&& g_switch_value
!= 0)
5809 as_warn ("-G may not be used with SVR4 PIC code");
5811 bfd_set_gp_size (stdoutput
, 0);
5816 as_warn ("Unrecognized option \"%s\"", opt
);
5818 *input_line_pointer
= c
;
5819 demand_empty_rest_of_line ();
5826 char *name
= input_line_pointer
, ch
;
5828 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5829 input_line_pointer
++;
5830 ch
= *input_line_pointer
;
5831 *input_line_pointer
= '\0';
5833 if (strcmp (name
, "reorder") == 0)
5837 prev_insn_unreordered
= 1;
5838 prev_prev_insn_unreordered
= 1;
5842 else if (strcmp (name
, "noreorder") == 0)
5844 mips_emit_delays ();
5846 mips_any_noreorder
= 1;
5848 else if (strcmp (name
, "at") == 0)
5852 else if (strcmp (name
, "noat") == 0)
5856 else if (strcmp (name
, "macro") == 0)
5858 mips_warn_about_macros
= 0;
5860 else if (strcmp (name
, "nomacro") == 0)
5862 if (mips_noreorder
== 0)
5863 as_bad ("`noreorder' must be set before `nomacro'");
5864 mips_warn_about_macros
= 1;
5866 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5870 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5874 else if (strcmp (name
, "bopt") == 0)
5878 else if (strcmp (name
, "nobopt") == 0)
5882 else if (strncmp (name
, "mips", 4) == 0)
5886 /* Permit the user to change the ISA on the fly. Needless to
5887 say, misuse can cause serious problems. */
5888 isa
= atoi (name
+ 4);
5890 mips_isa
= file_mips_isa
;
5891 else if (isa
< 1 || isa
> 3)
5892 as_bad ("unknown ISA level");
5898 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5900 *input_line_pointer
= ch
;
5901 demand_empty_rest_of_line ();
5904 /* The same as the usual .space directive, except that we have to
5905 forget about any previous instruction. */
5908 s_mips_space (param
)
5911 mips_emit_delays ();
5916 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5917 .option pic2. It means to generate SVR4 PIC calls. */
5923 mips_pic
= SVR4_PIC
;
5925 if (g_switch_seen
&& g_switch_value
!= 0)
5926 as_warn ("-G may not be used with SVR4 PIC code");
5929 bfd_set_gp_size (stdoutput
, 0);
5930 demand_empty_rest_of_line ();
5933 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5934 PIC code. It sets the $gp register for the function based on the
5935 function address, which is in the register named in the argument.
5936 This uses a relocation against _gp_disp, which is handled specially
5937 by the linker. The result is:
5938 lui $gp,%hi(_gp_disp)
5939 addiu $gp,$gp,%lo(_gp_disp)
5940 addu $gp,$gp,.cpload argument
5941 The .cpload argument is normally $25 == $t9. */
5950 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5951 if (mips_pic
!= SVR4_PIC
)
5957 /* .cpload should be a in .set noreorder section. */
5958 if (mips_noreorder
== 0)
5959 as_warn (".cpload not in noreorder section");
5962 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5963 ex
.X_op_symbol
= NULL
;
5964 ex
.X_add_number
= 0;
5966 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5967 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5968 (int) BFD_RELOC_LO16
);
5970 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5971 GP
, GP
, tc_get_register (0));
5973 demand_empty_rest_of_line ();
5976 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5977 offset from $sp. The offset is remembered, and after making a PIC
5978 call $gp is restored from that location. */
5981 s_cprestore (ignore
)
5987 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5988 if (mips_pic
!= SVR4_PIC
)
5994 mips_cprestore_offset
= get_absolute_expression ();
5996 ex
.X_op
= O_constant
;
5997 ex
.X_add_symbol
= NULL
;
5998 ex
.X_op_symbol
= NULL
;
5999 ex
.X_add_number
= mips_cprestore_offset
;
6001 macro_build ((char *) NULL
, &icnt
, &ex
,
6002 mips_isa
< 3 ? "sw" : "sd",
6003 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6005 demand_empty_rest_of_line ();
6008 /* Handle the .gpword pseudo-op. This is used when generating PIC
6009 code. It generates a 32 bit GP relative reloc. */
6019 /* When not generating PIC code, this is treated as .word. */
6020 if (mips_pic
!= SVR4_PIC
)
6027 mips_emit_delays ();
6029 mips_align (2, 0, label
);
6034 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6036 as_bad ("Unsupported use of .gpword");
6037 ignore_rest_of_line ();
6041 md_number_to_chars (p
, (valueT
) 0, 4);
6042 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6043 BFD_RELOC_MIPS_GPREL32
);
6045 demand_empty_rest_of_line ();
6048 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6049 tables in SVR4 PIC code. */
6058 /* This is ignored when not generating SVR4 PIC code. */
6059 if (mips_pic
!= SVR4_PIC
)
6065 /* Add $gp to the register named as an argument. */
6066 reg
= tc_get_register (0);
6067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6068 mips_isa
< 3 ? "addu" : "daddu",
6069 "d,v,t", reg
, reg
, GP
);
6071 demand_empty_rest_of_line ();
6074 /* Parse a register string into a number. Called from the ECOFF code
6075 to parse .frame. The argument is non-zero if this is the frame
6076 register, so that we can record it in mips_frame_reg. */
6079 tc_get_register (frame
)
6085 if (*input_line_pointer
++ != '$')
6087 as_warn ("expected `$'");
6090 else if (isdigit ((unsigned char) *input_line_pointer
))
6092 reg
= get_absolute_expression ();
6093 if (reg
< 0 || reg
>= 32)
6095 as_warn ("Bad register number");
6101 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6103 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6105 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6107 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6111 as_warn ("Unrecognized register name");
6114 input_line_pointer
+= 2;
6117 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6122 md_section_align (seg
, addr
)
6126 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6128 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6131 /* Estimate the size of a frag before relaxing. We are not really
6132 relaxing here, and the final size is encoded in the subtype
6137 md_estimate_size_before_relax (fragp
, segtype
)
6143 if (mips_pic
== NO_PIC
)
6146 const char *symname
;
6148 /* Find out whether this symbol can be referenced off the GP
6149 register. It can be if it is smaller than the -G size or if
6150 it is in the .sdata or .sbss section. Certain symbols can
6151 not be referenced off the GP, although it appears as though
6153 symname
= S_GET_NAME (fragp
->fr_symbol
);
6154 if (symname
!= (const char *) NULL
6155 && (strcmp (symname
, "eprol") == 0
6156 || strcmp (symname
, "etext") == 0
6157 || strcmp (symname
, "_gp") == 0
6158 || strcmp (symname
, "edata") == 0
6159 || strcmp (symname
, "_fbss") == 0
6160 || strcmp (symname
, "_fdata") == 0
6161 || strcmp (symname
, "_ftext") == 0
6162 || strcmp (symname
, "end") == 0
6163 || strcmp (symname
, "_gp_disp") == 0))
6165 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6166 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6167 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6168 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6169 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6173 const char *segname
;
6175 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6176 assert (strcmp (segname
, ".lit8") != 0
6177 && strcmp (segname
, ".lit4") != 0);
6178 change
= (strcmp (segname
, ".sdata") != 0
6179 && strcmp (segname
, ".sbss") != 0);
6181 #else /* ! defined (GPOPT) */
6182 /* We are not optimizing for the GP register. */
6184 #endif /* ! defined (GPOPT) */
6186 else if (mips_pic
== SVR4_PIC
)
6188 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6190 /* This must duplicate the test in adjust_reloc_syms. */
6191 change
= (symsec
!= &bfd_und_section
6192 && symsec
!= &bfd_abs_section
6193 && ! bfd_is_com_section (symsec
));
6200 /* Record the offset to the first reloc in the fr_opcode field.
6201 This lets md_convert_frag and tc_gen_reloc know that the code
6202 must be expanded. */
6203 fragp
->fr_opcode
= (fragp
->fr_literal
6205 - RELAX_OLD (fragp
->fr_subtype
)
6206 + RELAX_RELOC1 (fragp
->fr_subtype
));
6207 /* FIXME: This really needs as_warn_where. */
6208 if (RELAX_WARN (fragp
->fr_subtype
))
6209 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6215 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6218 /* Translate internal representation of relocation info to BFD target
6222 tc_gen_reloc (section
, fixp
)
6226 static arelent
*retval
[4];
6229 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6232 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6233 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6235 if (mips_pic
== EMBEDDED_PIC
6236 && SWITCH_TABLE (fixp
))
6238 /* For a switch table entry we use a special reloc. The addend
6239 is actually the difference between the reloc address and the
6241 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6243 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6245 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6247 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6249 /* We use a special addend for an internal RELLO reloc. */
6250 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6251 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6253 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6255 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6257 assert (fixp
->fx_next
!= NULL
6258 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6259 /* We use a special addend for an internal RELHI reloc. The
6260 reloc is relative to the RELLO; adjust the addend
6262 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6263 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6264 + fixp
->fx_next
->fx_where
6265 - S_GET_VALUE (fixp
->fx_subsy
));
6267 reloc
->addend
= (fixp
->fx_addnumber
6268 + fixp
->fx_next
->fx_frag
->fr_address
6269 + fixp
->fx_next
->fx_where
);
6271 else if (fixp
->fx_pcrel
== 0)
6272 reloc
->addend
= fixp
->fx_addnumber
;
6276 /* A gruesome hack which is a result of the gruesome gas reloc
6278 reloc
->addend
= reloc
->address
;
6280 reloc
->addend
= -reloc
->address
;
6284 /* If this is a variant frag, we may need to adjust the existing
6285 reloc and generate a new one. */
6286 if (fixp
->fx_frag
->fr_opcode
!= NULL
6287 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6288 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6289 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6293 /* If this is not the last reloc in this frag, then we have two
6294 GPREL relocs, both of which are being replaced. Let the
6295 second one handle all of them. */
6296 if (fixp
->fx_next
!= NULL
6297 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6299 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6300 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6305 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6306 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6307 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6309 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6310 reloc2
->address
= (reloc
->address
6311 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6312 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6313 reloc2
->addend
= fixp
->fx_addnumber
;
6314 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6315 assert (reloc2
->howto
!= NULL
);
6317 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6321 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6324 reloc3
->address
+= 4;
6327 if (mips_pic
== NO_PIC
)
6329 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6330 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6332 else if (mips_pic
== SVR4_PIC
)
6334 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6336 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6337 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6344 /* To support a PC relative reloc when generating embedded PIC code
6345 for ECOFF, we use a Cygnus extension. We check for that here to
6346 make sure that we don't let such a reloc escape normally. */
6348 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6349 && mips_pic
!= EMBEDDED_PIC
)
6350 reloc
->howto
= NULL
;
6353 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6355 if (reloc
->howto
== NULL
)
6357 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6358 "Can not represent relocation in this object file format");
6365 /* Convert a machine dependent frag. */
6368 md_convert_frag (abfd
, asec
, fragp
)
6376 if (fragp
->fr_opcode
== NULL
)
6379 old
= RELAX_OLD (fragp
->fr_subtype
);
6380 new = RELAX_NEW (fragp
->fr_subtype
);
6381 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6384 memcpy (fixptr
- old
, fixptr
, new);
6386 fragp
->fr_fix
+= new - old
;
6389 /* This function is called whenever a label is defined. It is used
6390 when handling branch delays; if a branch has a label, we assume we
6394 mips_define_label (sym
)
6402 /* Some special processing for a MIPS ELF file. */
6405 mips_elf_final_processing ()
6409 /* Write out the .reginfo section. */
6410 s
.ri_gprmask
= mips_gprmask
;
6411 s
.ri_cprmask
[0] = mips_cprmask
[0];
6412 s
.ri_cprmask
[1] = mips_cprmask
[1];
6413 s
.ri_cprmask
[2] = mips_cprmask
[2];
6414 s
.ri_cprmask
[3] = mips_cprmask
[3];
6415 /* The gp_value field is set by the MIPS ELF backend. */
6417 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6418 ((Elf32_External_RegInfo
*)
6419 mips_regmask_frag
));
6421 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6422 sort of BFD interface for this. */
6423 if (mips_any_noreorder
)
6424 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6425 if (mips_pic
!= NO_PIC
)
6426 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6429 #endif /* OBJ_ELF */
6431 #ifndef ECOFF_DEBUGGING
6433 /* These functions should really be defined by the object file format,
6434 since they are related to debugging information. However, this
6435 code has to work for the a.out format, which does not define them,
6436 so we provide simple versions here. These don't actually generate
6437 any debugging information, but they do simple checking and someday
6438 somebody may make them useful. */
6442 struct loc
*loc_next
;
6443 unsigned long loc_fileno
;
6444 unsigned long loc_lineno
;
6445 unsigned long loc_offset
;
6446 unsigned short loc_delta
;
6447 unsigned short loc_count
;
6456 struct proc
*proc_next
;
6457 struct symbol
*proc_isym
;
6458 struct symbol
*proc_end
;
6459 unsigned long proc_reg_mask
;
6460 unsigned long proc_reg_offset
;
6461 unsigned long proc_fpreg_mask
;
6462 unsigned long proc_fpreg_offset
;
6463 unsigned long proc_frameoffset
;
6464 unsigned long proc_framereg
;
6465 unsigned long proc_pcreg
;
6467 struct file
*proc_file
;
6474 struct file
*file_next
;
6475 unsigned long file_fileno
;
6476 struct symbol
*file_symbol
;
6477 struct symbol
*file_end
;
6478 struct proc
*file_proc
;
6483 static struct obstack proc_frags
;
6484 static procS
*proc_lastP
;
6485 static procS
*proc_rootP
;
6486 static int numprocs
;
6491 obstack_begin (&proc_frags
, 0x2000);
6497 /* check for premature end, nesting errors, etc */
6498 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6499 as_warn ("missing `.end' at end of assembly");
6502 extern char hex_value
[];
6510 if (*input_line_pointer
== '-')
6512 ++input_line_pointer
;
6515 if (!isdigit (*input_line_pointer
))
6516 as_bad ("Expected simple number.");
6517 if (input_line_pointer
[0] == '0')
6519 if (input_line_pointer
[1] == 'x')
6521 input_line_pointer
+= 2;
6522 while (isxdigit (*input_line_pointer
))
6525 val
|= hex_value
[(int) *input_line_pointer
++];
6527 return negative
? -val
: val
;
6531 ++input_line_pointer
;
6532 while (isdigit (*input_line_pointer
))
6535 val
|= *input_line_pointer
++ - '0';
6537 return negative
? -val
: val
;
6540 if (!isdigit (*input_line_pointer
))
6542 printf (" *input_line_pointer == '%c' 0x%02x\n",
6543 *input_line_pointer
, *input_line_pointer
);
6544 as_warn ("Invalid number");
6547 while (isdigit (*input_line_pointer
))
6550 val
+= *input_line_pointer
++ - '0';
6552 return negative
? -val
: val
;
6555 /* The .file directive; just like the usual .file directive, but there
6556 is an initial number which is the ECOFF file index. */
6564 line
= get_number ();
6569 /* The .end directive. */
6577 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6580 demand_empty_rest_of_line ();
6584 if (now_seg
!= text_section
)
6585 as_warn (".end not in text section");
6588 as_warn (".end and no .ent seen yet.");
6594 assert (S_GET_NAME (p
));
6595 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6596 as_warn (".end symbol does not match .ent symbol.");
6599 proc_lastP
->proc_end
= (symbolS
*) 1;
6602 /* The .aent and .ent directives. */
6612 symbolP
= get_symbol ();
6613 if (*input_line_pointer
== ',')
6614 input_line_pointer
++;
6616 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6617 number
= get_number ();
6618 if (now_seg
!= text_section
)
6619 as_warn (".ent or .aent not in text section.");
6621 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6622 as_warn ("missing `.end'");
6626 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6627 procP
->proc_isym
= symbolP
;
6628 procP
->proc_reg_mask
= 0;
6629 procP
->proc_reg_offset
= 0;
6630 procP
->proc_fpreg_mask
= 0;
6631 procP
->proc_fpreg_offset
= 0;
6632 procP
->proc_frameoffset
= 0;
6633 procP
->proc_framereg
= 0;
6634 procP
->proc_pcreg
= 0;
6635 procP
->proc_end
= NULL
;
6636 procP
->proc_next
= NULL
;
6638 proc_lastP
->proc_next
= procP
;
6644 demand_empty_rest_of_line ();
6647 /* The .frame directive. */
6660 frame_reg
= tc_get_register (1);
6661 if (*input_line_pointer
== ',')
6662 input_line_pointer
++;
6663 frame_off
= get_absolute_expression ();
6664 if (*input_line_pointer
== ',')
6665 input_line_pointer
++;
6666 pcreg
= tc_get_register (0);
6669 assert (proc_rootP
);
6670 proc_rootP
->proc_framereg
= frame_reg
;
6671 proc_rootP
->proc_frameoffset
= frame_off
;
6672 proc_rootP
->proc_pcreg
= pcreg
;
6673 /* bob macho .frame */
6675 /* We don't have to write out a frame stab for unoptimized code. */
6676 if (!(frame_reg
== FP
&& frame_off
== 0))
6679 as_warn ("No .ent for .frame to use.");
6680 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6681 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6682 S_SET_TYPE (symP
, N_RMASK
);
6683 S_SET_OTHER (symP
, 0);
6684 S_SET_DESC (symP
, 0);
6685 symP
->sy_forward
= proc_lastP
->proc_isym
;
6686 /* bob perhaps I should have used pseudo set */
6688 demand_empty_rest_of_line ();
6692 /* The .fmask and .mask directives. */
6699 char str
[100], *strP
;
6705 mask
= get_number ();
6706 if (*input_line_pointer
== ',')
6707 input_line_pointer
++;
6708 off
= get_absolute_expression ();
6710 /* bob only for coff */
6711 assert (proc_rootP
);
6712 if (reg_type
== 'F')
6714 proc_rootP
->proc_fpreg_mask
= mask
;
6715 proc_rootP
->proc_fpreg_offset
= off
;
6719 proc_rootP
->proc_reg_mask
= mask
;
6720 proc_rootP
->proc_reg_offset
= off
;
6723 /* bob macho .mask + .fmask */
6725 /* We don't have to write out a mask stab if no saved regs. */
6729 as_warn ("No .ent for .mask to use.");
6731 for (i
= 0; i
< 32; i
++)
6735 sprintf (strP
, "%c%d,", reg_type
, i
);
6736 strP
+= strlen (strP
);
6740 sprintf (strP
, ";%d,", off
);
6741 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6742 S_SET_TYPE (symP
, N_RMASK
);
6743 S_SET_OTHER (symP
, 0);
6744 S_SET_DESC (symP
, 0);
6745 symP
->sy_forward
= proc_lastP
->proc_isym
;
6746 /* bob perhaps I should have used pseudo set */
6751 /* The .loc directive. */
6762 assert (now_seg
== text_section
);
6764 lineno
= get_number ();
6765 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6767 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6768 S_SET_TYPE (symbolP
, N_SLINE
);
6769 S_SET_OTHER (symbolP
, 0);
6770 S_SET_DESC (symbolP
, lineno
);
6771 symbolP
->sy_segment
= now_seg
;
6775 #endif /* ! defined (ECOFF_DEBUGGING) */