1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
115 mips_target_format ()
117 switch (OUTPUT_FLAVOR
)
119 case bfd_target_aout_flavour
:
120 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
121 case bfd_target_ecoff_flavour
:
122 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
123 case bfd_target_coff_flavour
:
125 case bfd_target_elf_flavour
:
127 /* This is traditional mips */
128 return (target_big_endian
129 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
131 return (target_big_endian
132 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
133 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
141 /* The name of the readonly data section. */
142 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
144 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
146 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
148 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
152 /* This is the set of options which may be modified by the .set
153 pseudo-op. We use a struct so that .set push and .set pop are more
156 struct mips_set_options
158 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
159 if it has not been initialized. Changed by `.set mipsN', and the
160 -mipsN command line option, and the default CPU. */
162 /* Whether we are assembling for the mips16 processor. 0 if we are
163 not, 1 if we are, and -1 if the value has not been initialized.
164 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
165 -nomips16 command line options, and the default CPU. */
167 /* Non-zero if we should not reorder instructions. Changed by `.set
168 reorder' and `.set noreorder'. */
170 /* Non-zero if we should not permit the $at ($1) register to be used
171 in instructions. Changed by `.set at' and `.set noat'. */
173 /* Non-zero if we should warn when a macro instruction expands into
174 more than one machine instruction. Changed by `.set nomacro' and
176 int warn_about_macros
;
177 /* Non-zero if we should not move instructions. Changed by `.set
178 move', `.set volatile', `.set nomove', and `.set novolatile'. */
180 /* Non-zero if we should not optimize branches by moving the target
181 of the branch into the delay slot. Actually, we don't perform
182 this optimization anyhow. Changed by `.set bopt' and `.set
185 /* Non-zero if we should not autoextend mips16 instructions.
186 Changed by `.set autoextend' and `.set noautoextend'. */
190 /* This is the struct we use to hold the current set of options. Note
191 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
192 -1 to indicate that they have not been initialized. */
194 static struct mips_set_options mips_opts
=
196 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
199 /* These variables are filled in with the masks of registers used.
200 The object format code reads them and puts them in the appropriate
202 unsigned long mips_gprmask
;
203 unsigned long mips_cprmask
[4];
205 /* MIPS ISA we are using for this output file. */
206 static int file_mips_isa
= ISA_UNKNOWN
;
208 /* The CPU type we are using for this output file. */
209 static int mips_cpu
= CPU_UNKNOWN
;
211 /* The argument of the -mabi= flag. */
212 static char * mips_abi_string
= 0;
214 /* Wether we should mark the file EABI64 or EABI32. */
215 static int mips_eabi64
= 0;
217 /* If they asked for mips1 or mips2 and a cpu that is
218 mips3 or greater, then mark the object file 32BITMODE. */
219 static int mips_32bitmode
= 0;
221 /* True if -mgp32 was passed. */
222 static int mips_gp32
= 0;
224 /* Some ISA's have delay slots for instructions which read or write
225 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
226 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
227 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
228 delay slot in this ISA. The uses of this macro assume that any
229 ISA that has delay slots for one of these, has them for all. They
230 also assume that ISAs which don't have delays for these insns, don't
231 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
232 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
234 || (ISA) == ISA_MIPS2 \
235 || (ISA) == ISA_MIPS3 \
238 /* Return true if ISA supports 64 bit gp register instructions. */
239 #define ISA_HAS_64BIT_REGS(ISA) ( \
241 || (ISA) == ISA_MIPS4 \
242 || (ISA) == ISA_MIPS5 \
243 || (ISA) == ISA_MIPS32 \
246 /* Whether the processor uses hardware interlocks to protect
247 reads from the HI and LO registers, and thus does not
248 require nops to be inserted.
250 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
251 -mcpu=FOO schedules for FOO, but still produces code that meets the
252 requirements of MIPS ISA I. For example, it won't generate any
253 FOO-specific instructions, and it will still assume that any
254 scheduling hazards described in MIPS ISA I are there, even if FOO
255 has interlocks. -mFOO gives GCC permission to generate code that
256 will only run on a FOO; it will generate FOO-specific instructions,
257 and assume interlocks provided by a FOO.
259 However, GAS currently doesn't make this distinction; before Jan 28
260 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
261 assumptions. The GCC driver passes these flags through to GAS, so
262 if GAS actually does anything that doesn't meet MIPS ISA I with
263 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
265 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
266 which seems senseless --- why generate code which will only run on
267 a FOO, but schedule for something else?
269 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
271 -- Jim Blandy <jimb@cygnus.com> */
273 #define hilo_interlocks (mips_cpu == CPU_R4010 \
276 /* Whether the processor uses hardware interlocks to protect reads
277 from the GPRs, and thus does not require nops to be inserted. */
278 #define gpr_interlocks \
279 (mips_opts.isa != ISA_MIPS1 \
280 || mips_cpu == CPU_R3900)
282 /* As with other "interlocks" this is used by hardware that has FP
283 (co-processor) interlocks. */
284 /* Itbl support may require additional care here. */
285 #define cop_interlocks (mips_cpu == CPU_R4300 \
288 /* Is this a mfhi or mflo instruction? */
289 #define MF_HILO_INSN(PINFO) \
290 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
292 /* MIPS PIC level. */
296 /* Do not generate PIC code. */
299 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
300 not sure what it is supposed to do. */
303 /* Generate PIC code as in the SVR4 MIPS ABI. */
306 /* Generate PIC code without using a global offset table: the data
307 segment has a maximum size of 64K, all data references are off
308 the $gp register, and all text references are PC relative. This
309 is used on some embedded systems. */
313 static enum mips_pic_level mips_pic
;
315 /* 1 if we should generate 32 bit offsets from the GP register in
316 SVR4_PIC mode. Currently has no meaning in other modes. */
317 static int mips_big_got
;
319 /* 1 if trap instructions should used for overflow rather than break
321 static int mips_trap
;
323 /* 1 if double width floating point constants should not be constructed
324 by a assembling two single width halves into two single width floating
325 point registers which just happen to alias the double width destination
326 register. On some architectures this aliasing can be disabled by a bit
327 in the status register, and the setting of this bit cannot be determined
328 automatically at assemble time. */
329 static int mips_disable_float_construction
;
331 /* Non-zero if any .set noreorder directives were used. */
333 static int mips_any_noreorder
;
335 /* Non-zero if nops should be inserted when the register referenced in
336 an mfhi/mflo instruction is read in the next two instructions. */
337 static int mips_7000_hilo_fix
;
339 /* The size of the small data section. */
340 static unsigned int g_switch_value
= 8;
341 /* Whether the -G option was used. */
342 static int g_switch_seen
= 0;
347 /* If we can determine in advance that GP optimization won't be
348 possible, we can skip the relaxation stuff that tries to produce
349 GP-relative references. This makes delay slot optimization work
352 This function can only provide a guess, but it seems to work for
353 gcc output. It needs to guess right for gcc, otherwise gcc
354 will put what it thinks is a GP-relative instruction in a branch
357 I don't know if a fix is needed for the SVR4_PIC mode. I've only
358 fixed it for the non-PIC mode. KR 95/04/07 */
359 static int nopic_need_relax
PARAMS ((symbolS
*, int));
361 /* handle of the OPCODE hash table */
362 static struct hash_control
*op_hash
= NULL
;
364 /* The opcode hash table we use for the mips16. */
365 static struct hash_control
*mips16_op_hash
= NULL
;
367 /* This array holds the chars that always start a comment. If the
368 pre-processor is disabled, these aren't very useful */
369 const char comment_chars
[] = "#";
371 /* This array holds the chars that only start a comment at the beginning of
372 a line. If the line seems to have the form '# 123 filename'
373 .line and .file directives will appear in the pre-processed output */
374 /* Note that input_file.c hand checks for '#' at the beginning of the
375 first line of the input file. This is because the compiler outputs
376 #NO_APP at the beginning of its output. */
377 /* Also note that C style comments are always supported. */
378 const char line_comment_chars
[] = "#";
380 /* This array holds machine specific line separator characters. */
381 const char line_separator_chars
[] = ";";
383 /* Chars that can be used to separate mant from exp in floating point nums */
384 const char EXP_CHARS
[] = "eE";
386 /* Chars that mean this number is a floating point constant */
389 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
391 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
392 changed in read.c . Ideally it shouldn't have to know about it at all,
393 but nothing is ideal around here.
396 static char *insn_error
;
398 static int auto_align
= 1;
400 /* When outputting SVR4 PIC code, the assembler needs to know the
401 offset in the stack frame from which to restore the $gp register.
402 This is set by the .cprestore pseudo-op, and saved in this
404 static offsetT mips_cprestore_offset
= -1;
406 /* This is the register which holds the stack frame, as set by the
407 .frame pseudo-op. This is needed to implement .cprestore. */
408 static int mips_frame_reg
= SP
;
410 /* To output NOP instructions correctly, we need to keep information
411 about the previous two instructions. */
413 /* Whether we are optimizing. The default value of 2 means to remove
414 unneeded NOPs and swap branch instructions when possible. A value
415 of 1 means to not swap branches. A value of 0 means to always
417 static int mips_optimize
= 2;
419 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
420 equivalent to seeing no -g option at all. */
421 static int mips_debug
= 0;
423 /* The previous instruction. */
424 static struct mips_cl_insn prev_insn
;
426 /* The instruction before prev_insn. */
427 static struct mips_cl_insn prev_prev_insn
;
429 /* If we don't want information for prev_insn or prev_prev_insn, we
430 point the insn_mo field at this dummy integer. */
431 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
433 /* Non-zero if prev_insn is valid. */
434 static int prev_insn_valid
;
436 /* The frag for the previous instruction. */
437 static struct frag
*prev_insn_frag
;
439 /* The offset into prev_insn_frag for the previous instruction. */
440 static long prev_insn_where
;
442 /* The reloc type for the previous instruction, if any. */
443 static bfd_reloc_code_real_type prev_insn_reloc_type
;
445 /* The reloc for the previous instruction, if any. */
446 static fixS
*prev_insn_fixp
;
448 /* Non-zero if the previous instruction was in a delay slot. */
449 static int prev_insn_is_delay_slot
;
451 /* Non-zero if the previous instruction was in a .set noreorder. */
452 static int prev_insn_unreordered
;
454 /* Non-zero if the previous instruction uses an extend opcode (if
456 static int prev_insn_extended
;
458 /* Non-zero if the previous previous instruction was in a .set
460 static int prev_prev_insn_unreordered
;
462 /* If this is set, it points to a frag holding nop instructions which
463 were inserted before the start of a noreorder section. If those
464 nops turn out to be unnecessary, the size of the frag can be
466 static fragS
*prev_nop_frag
;
468 /* The number of nop instructions we created in prev_nop_frag. */
469 static int prev_nop_frag_holds
;
471 /* The number of nop instructions that we know we need in
473 static int prev_nop_frag_required
;
475 /* The number of instructions we've seen since prev_nop_frag. */
476 static int prev_nop_frag_since
;
478 /* For ECOFF and ELF, relocations against symbols are done in two
479 parts, with a HI relocation and a LO relocation. Each relocation
480 has only 16 bits of space to store an addend. This means that in
481 order for the linker to handle carries correctly, it must be able
482 to locate both the HI and the LO relocation. This means that the
483 relocations must appear in order in the relocation table.
485 In order to implement this, we keep track of each unmatched HI
486 relocation. We then sort them so that they immediately precede the
487 corresponding LO relocation. */
492 struct mips_hi_fixup
*next
;
495 /* The section this fixup is in. */
499 /* The list of unmatched HI relocs. */
501 static struct mips_hi_fixup
*mips_hi_fixup_list
;
503 /* Map normal MIPS register numbers to mips16 register numbers. */
505 #define X ILLEGAL_REG
506 static const int mips32_to_16_reg_map
[] =
508 X
, X
, 2, 3, 4, 5, 6, 7,
509 X
, X
, X
, X
, X
, X
, X
, X
,
510 0, 1, X
, X
, X
, X
, X
, X
,
511 X
, X
, X
, X
, X
, X
, X
, X
515 /* Map mips16 register numbers to normal MIPS register numbers. */
517 static const unsigned int mips16_to_32_reg_map
[] =
519 16, 17, 2, 3, 4, 5, 6, 7
522 /* Since the MIPS does not have multiple forms of PC relative
523 instructions, we do not have to do relaxing as is done on other
524 platforms. However, we do have to handle GP relative addressing
525 correctly, which turns out to be a similar problem.
527 Every macro that refers to a symbol can occur in (at least) two
528 forms, one with GP relative addressing and one without. For
529 example, loading a global variable into a register generally uses
530 a macro instruction like this:
532 If i can be addressed off the GP register (this is true if it is in
533 the .sbss or .sdata section, or if it is known to be smaller than
534 the -G argument) this will generate the following instruction:
536 This instruction will use a GPREL reloc. If i can not be addressed
537 off the GP register, the following instruction sequence will be used:
540 In this case the first instruction will have a HI16 reloc, and the
541 second reloc will have a LO16 reloc. Both relocs will be against
544 The issue here is that we may not know whether i is GP addressable
545 until after we see the instruction that uses it. Therefore, we
546 want to be able to choose the final instruction sequence only at
547 the end of the assembly. This is similar to the way other
548 platforms choose the size of a PC relative instruction only at the
551 When generating position independent code we do not use GP
552 addressing in quite the same way, but the issue still arises as
553 external symbols and local symbols must be handled differently.
555 We handle these issues by actually generating both possible
556 instruction sequences. The longer one is put in a frag_var with
557 type rs_machine_dependent. We encode what to do with the frag in
558 the subtype field. We encode (1) the number of existing bytes to
559 replace, (2) the number of new bytes to use, (3) the offset from
560 the start of the existing bytes to the first reloc we must generate
561 (that is, the offset is applied from the start of the existing
562 bytes after they are replaced by the new bytes, if any), (4) the
563 offset from the start of the existing bytes to the second reloc,
564 (5) whether a third reloc is needed (the third reloc is always four
565 bytes after the second reloc), and (6) whether to warn if this
566 variant is used (this is sometimes needed if .set nomacro or .set
567 noat is in effect). All these numbers are reasonably small.
569 Generating two instruction sequences must be handled carefully to
570 ensure that delay slots are handled correctly. Fortunately, there
571 are a limited number of cases. When the second instruction
572 sequence is generated, append_insn is directed to maintain the
573 existing delay slot information, so it continues to apply to any
574 code after the second instruction sequence. This means that the
575 second instruction sequence must not impose any requirements not
576 required by the first instruction sequence.
578 These variant frags are then handled in functions called by the
579 machine independent code. md_estimate_size_before_relax returns
580 the final size of the frag. md_convert_frag sets up the final form
581 of the frag. tc_gen_reloc adjust the first reloc and adds a second
583 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
587 | (((reloc1) + 64) << 9) \
588 | (((reloc2) + 64) << 2) \
589 | ((reloc3) ? (1 << 1) : 0) \
591 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
592 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
593 #define RELAX_RELOC1(i) ((bfd_vma) (((i) >> 9) & 0x7f) - 64)
594 #define RELAX_RELOC2(i) ((bfd_vma) (((i) >> 2) & 0x7f) - 64)
595 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
596 #define RELAX_WARN(i) ((i) & 1)
598 /* For mips16 code, we use an entirely different form of relaxation.
599 mips16 supports two versions of most instructions which take
600 immediate values: a small one which takes some small value, and a
601 larger one which takes a 16 bit value. Since branches also follow
602 this pattern, relaxing these values is required.
604 We can assemble both mips16 and normal MIPS code in a single
605 object. Therefore, we need to support this type of relaxation at
606 the same time that we support the relaxation described above. We
607 use the high bit of the subtype field to distinguish these cases.
609 The information we store for this type of relaxation is the
610 argument code found in the opcode file for this relocation, whether
611 the user explicitly requested a small or extended form, and whether
612 the relocation is in a jump or jal delay slot. That tells us the
613 size of the value, and how it should be stored. We also store
614 whether the fragment is considered to be extended or not. We also
615 store whether this is known to be a branch to a different section,
616 whether we have tried to relax this frag yet, and whether we have
617 ever extended a PC relative fragment because of a shift count. */
618 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
621 | ((small) ? 0x100 : 0) \
622 | ((ext) ? 0x200 : 0) \
623 | ((dslot) ? 0x400 : 0) \
624 | ((jal_dslot) ? 0x800 : 0))
625 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
626 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
627 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
628 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
629 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
630 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
631 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
632 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
633 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
634 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
635 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
636 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
638 /* Prototypes for static functions. */
641 #define internalError() \
642 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
644 #define internalError() as_fatal (_("MIPS internal Error"));
647 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
649 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
650 unsigned int reg
, enum mips_regclass
class));
651 static int reg_needs_delay
PARAMS ((unsigned int));
652 static void mips16_mark_labels
PARAMS ((void));
653 static void append_insn
PARAMS ((char *place
,
654 struct mips_cl_insn
* ip
,
656 bfd_reloc_code_real_type r
,
658 static void mips_no_prev_insn
PARAMS ((int));
659 static void mips_emit_delays
PARAMS ((boolean
));
661 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
662 const char *name
, const char *fmt
,
665 static void macro_build ();
667 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
668 const char *, const char *,
670 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
671 expressionS
* ep
, int regnum
));
672 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
673 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
675 static void load_register
PARAMS ((int *, int, expressionS
*, int));
676 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
677 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
678 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
679 #ifdef LOSING_COMPILER
680 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
682 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
683 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
684 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
685 boolean
, boolean
, unsigned long *,
686 boolean
*, unsigned short *));
687 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
688 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
689 static symbolS
*get_symbol
PARAMS ((void));
690 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
691 static void s_align
PARAMS ((int));
692 static void s_change_sec
PARAMS ((int));
693 static void s_cons
PARAMS ((int));
694 static void s_float_cons
PARAMS ((int));
695 static void s_mips_globl
PARAMS ((int));
696 static void s_option
PARAMS ((int));
697 static void s_mipsset
PARAMS ((int));
698 static void s_abicalls
PARAMS ((int));
699 static void s_cpload
PARAMS ((int));
700 static void s_cprestore
PARAMS ((int));
701 static void s_gpword
PARAMS ((int));
702 static void s_cpadd
PARAMS ((int));
703 static void s_insn
PARAMS ((int));
704 static void md_obj_begin
PARAMS ((void));
705 static void md_obj_end
PARAMS ((void));
706 static long get_number
PARAMS ((void));
707 static void s_mips_ent
PARAMS ((int));
708 static void s_mips_end
PARAMS ((int));
709 static void s_mips_frame
PARAMS ((int));
710 static void s_mips_mask
PARAMS ((int));
711 static void s_mips_stab
PARAMS ((int));
712 static void s_mips_weakext
PARAMS ((int));
713 static void s_file
PARAMS ((int));
714 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
715 static const char *mips_isa_to_str
PARAMS ((int));
716 static const char *mips_cpu_to_str
PARAMS ((int));
717 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
719 /* Table and functions used to map between CPU/ISA names, and
720 ISA levels, and CPU numbers. */
724 const char *name
; /* CPU or ISA name. */
725 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
726 int isa
; /* ISA level. */
727 int cpu
; /* CPU number (default CPU if ISA). */
730 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
731 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
732 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
736 The following pseudo-ops from the Kane and Heinrich MIPS book
737 should be defined here, but are currently unsupported: .alias,
738 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
740 The following pseudo-ops from the Kane and Heinrich MIPS book are
741 specific to the type of debugging information being generated, and
742 should be defined by the object format: .aent, .begin, .bend,
743 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
746 The following pseudo-ops from the Kane and Heinrich MIPS book are
747 not MIPS CPU specific, but are also not specific to the object file
748 format. This file is probably the best place to define them, but
749 they are not currently supported: .asm0, .endr, .lab, .repeat,
752 static const pseudo_typeS mips_pseudo_table
[] =
754 /* MIPS specific pseudo-ops. */
755 {"option", s_option
, 0},
756 {"set", s_mipsset
, 0},
757 {"rdata", s_change_sec
, 'r'},
758 {"sdata", s_change_sec
, 's'},
759 {"livereg", s_ignore
, 0},
760 {"abicalls", s_abicalls
, 0},
761 {"cpload", s_cpload
, 0},
762 {"cprestore", s_cprestore
, 0},
763 {"gpword", s_gpword
, 0},
764 {"cpadd", s_cpadd
, 0},
767 /* Relatively generic pseudo-ops that happen to be used on MIPS
769 {"asciiz", stringer
, 1},
770 {"bss", s_change_sec
, 'b'},
773 {"dword", s_cons
, 3},
774 {"weakext", s_mips_weakext
, 0},
776 /* These pseudo-ops are defined in read.c, but must be overridden
777 here for one reason or another. */
778 {"align", s_align
, 0},
780 {"data", s_change_sec
, 'd'},
781 {"double", s_float_cons
, 'd'},
782 {"float", s_float_cons
, 'f'},
783 {"globl", s_mips_globl
, 0},
784 {"global", s_mips_globl
, 0},
785 {"hword", s_cons
, 1},
790 {"short", s_cons
, 1},
791 {"single", s_float_cons
, 'f'},
792 {"stabn", s_mips_stab
, 'n'},
793 {"text", s_change_sec
, 't'},
798 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
800 /* These pseudo-ops should be defined by the object file format.
801 However, a.out doesn't support them, so we have versions here. */
802 {"aent", s_mips_ent
, 1},
803 {"bgnb", s_ignore
, 0},
804 {"end", s_mips_end
, 0},
805 {"endb", s_ignore
, 0},
806 {"ent", s_mips_ent
, 0},
808 {"fmask", s_mips_mask
, 'F'},
809 {"frame", s_mips_frame
, 0},
810 {"loc", s_ignore
, 0},
811 {"mask", s_mips_mask
, 'R'},
812 {"verstamp", s_ignore
, 0},
816 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
821 pop_insert (mips_pseudo_table
);
822 if (! ECOFF_DEBUGGING
)
823 pop_insert (mips_nonecoff_pseudo_table
);
826 /* Symbols labelling the current insn. */
828 struct insn_label_list
830 struct insn_label_list
*next
;
834 static struct insn_label_list
*insn_labels
;
835 static struct insn_label_list
*free_insn_labels
;
837 static void mips_clear_insn_labels
PARAMS ((void));
840 mips_clear_insn_labels ()
842 register struct insn_label_list
**pl
;
844 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
850 static char *expr_end
;
852 /* Expressions which appear in instructions. These are set by
855 static expressionS imm_expr
;
856 static expressionS offset_expr
;
858 /* Relocs associated with imm_expr and offset_expr. */
860 static bfd_reloc_code_real_type imm_reloc
;
861 static bfd_reloc_code_real_type offset_reloc
;
863 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
865 static boolean imm_unmatched_hi
;
867 /* These are set by mips16_ip if an explicit extension is used. */
869 static boolean mips16_small
, mips16_ext
;
871 #ifdef MIPS_STABS_ELF
872 /* The pdr segment for per procedure frame/regmask info */
878 mips_isa_to_str (isa
)
881 const struct mips_cpu_info
*ci
;
884 ci
= mips_cpu_info_from_isa (isa
);
888 sprintf (s
, "ISA#%d", isa
);
893 mips_cpu_to_str (cpu
)
896 const struct mips_cpu_info
*ci
;
899 ci
= mips_cpu_info_from_cpu (cpu
);
903 sprintf (s
, "CPU#%d", cpu
);
907 /* This function is called once, at assembler startup time. It should
908 set up all the tables, etc. that the MD part of the assembler will need. */
913 register const char *retval
= NULL
;
918 int mips_isa_from_cpu
;
919 int target_cpu_had_mips16
= 0;
920 const struct mips_cpu_info
*ci
;
922 /* GP relative stuff not working for PE */
923 if (strncmp (TARGET_OS
, "pe", 2) == 0
924 && g_switch_value
!= 0)
927 as_bad (_("-G not supported in this configuration."));
932 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
934 a
= xmalloc (sizeof TARGET_CPU
);
935 strcpy (a
, TARGET_CPU
);
936 a
[(sizeof TARGET_CPU
) - 3] = '\0';
940 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
942 target_cpu_had_mips16
= 1;
943 cpu
+= sizeof "mips16" - 1;
946 if (mips_opts
.mips16
< 0)
947 mips_opts
.mips16
= target_cpu_had_mips16
;
949 /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was
950 specified on the command line, or some other value if one was.
951 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
952 the command line, or will be set otherwise if one was. */
953 if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
955 /* We have it all. There's nothing to do. */
957 else if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
959 /* We have CPU, we need ISA. */
960 ci
= mips_cpu_info_from_cpu (mips_cpu
);
962 mips_opts
.isa
= ci
->isa
;
964 else if (mips_cpu
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
966 /* We have ISA, we need default CPU. */
967 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
973 /* We need to set both ISA and CPU from target cpu. */
974 ci
= mips_cpu_info_from_name (cpu
);
976 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
978 mips_opts
.isa
= ci
->isa
;
982 ci
= mips_cpu_info_from_cpu (mips_cpu
);
984 mips_isa_from_cpu
= ci
->isa
;
986 /* End of TARGET_CPU processing, get rid of malloced memory
995 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
996 as_bad (_("trap exception not supported at ISA 1"));
998 /* Set the EABI kind based on the ISA before the user gets
999 to change the ISA with directives. This isn't really
1000 the best, but then neither is basing the abi on the isa. */
1001 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1003 && 0 == strcmp (mips_abi_string
, "eabi"))
1006 /* If they asked for mips1 or mips2 and a cpu that is
1007 mips3 or greater, then mark the object file 32BITMODE. */
1008 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1009 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1010 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1013 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
))
1014 as_warn (_("Could not set architecture and machine"));
1016 file_mips_isa
= mips_opts
.isa
;
1018 op_hash
= hash_new ();
1020 for (i
= 0; i
< NUMOPCODES
;)
1022 const char *name
= mips_opcodes
[i
].name
;
1024 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1027 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1028 mips_opcodes
[i
].name
, retval
);
1029 /* Probably a memory allocation problem? Give up now. */
1030 as_fatal (_("Broken assembler. No assembly attempted."));
1034 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1036 if (!validate_mips_insn (&mips_opcodes
[i
]))
1041 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1044 mips16_op_hash
= hash_new ();
1047 while (i
< bfd_mips16_num_opcodes
)
1049 const char *name
= mips16_opcodes
[i
].name
;
1051 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1053 as_fatal (_("internal: can't hash `%s': %s"),
1054 mips16_opcodes
[i
].name
, retval
);
1057 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1058 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1059 != mips16_opcodes
[i
].match
))
1061 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1062 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1067 while (i
< bfd_mips16_num_opcodes
1068 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1072 as_fatal (_("Broken assembler. No assembly attempted."));
1074 /* We add all the general register names to the symbol table. This
1075 helps us detect invalid uses of them. */
1076 for (i
= 0; i
< 32; i
++)
1080 sprintf (buf
, "$%d", i
);
1081 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1082 &zero_address_frag
));
1084 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1085 &zero_address_frag
));
1086 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1087 &zero_address_frag
));
1088 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1089 &zero_address_frag
));
1090 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1091 &zero_address_frag
));
1092 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1093 &zero_address_frag
));
1094 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1095 &zero_address_frag
));
1096 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1097 &zero_address_frag
));
1099 mips_no_prev_insn (false);
1102 mips_cprmask
[0] = 0;
1103 mips_cprmask
[1] = 0;
1104 mips_cprmask
[2] = 0;
1105 mips_cprmask
[3] = 0;
1107 /* set the default alignment for the text section (2**2) */
1108 record_alignment (text_section
, 2);
1110 if (USE_GLOBAL_POINTER_OPT
)
1111 bfd_set_gp_size (stdoutput
, g_switch_value
);
1113 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1115 /* On a native system, sections must be aligned to 16 byte
1116 boundaries. When configured for an embedded ELF target, we
1118 if (strcmp (TARGET_OS
, "elf") != 0)
1120 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1121 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1122 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1125 /* Create a .reginfo section for register masks and a .mdebug
1126 section for debugging information. */
1134 subseg
= now_subseg
;
1136 /* The ABI says this section should be loaded so that the
1137 running program can access it. However, we don't load it
1138 if we are configured for an embedded target */
1139 flags
= SEC_READONLY
| SEC_DATA
;
1140 if (strcmp (TARGET_OS
, "elf") != 0)
1141 flags
|= SEC_ALLOC
| SEC_LOAD
;
1145 sec
= subseg_new (".reginfo", (subsegT
) 0);
1147 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1148 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1151 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1156 /* The 64-bit ABI uses a .MIPS.options section rather than
1157 .reginfo section. */
1158 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1159 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1160 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1163 /* Set up the option header. */
1165 Elf_Internal_Options opthdr
;
1168 opthdr
.kind
= ODK_REGINFO
;
1169 opthdr
.size
= (sizeof (Elf_External_Options
)
1170 + sizeof (Elf64_External_RegInfo
));
1173 f
= frag_more (sizeof (Elf_External_Options
));
1174 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1175 (Elf_External_Options
*) f
);
1177 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1182 if (ECOFF_DEBUGGING
)
1184 sec
= subseg_new (".mdebug", (subsegT
) 0);
1185 (void) bfd_set_section_flags (stdoutput
, sec
,
1186 SEC_HAS_CONTENTS
| SEC_READONLY
);
1187 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1190 #ifdef MIPS_STABS_ELF
1191 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1192 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1193 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1194 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1197 subseg_set (seg
, subseg
);
1201 if (! ECOFF_DEBUGGING
)
1208 if (! ECOFF_DEBUGGING
)
1216 struct mips_cl_insn insn
;
1218 imm_expr
.X_op
= O_absent
;
1219 imm_reloc
= BFD_RELOC_UNUSED
;
1220 imm_unmatched_hi
= false;
1221 offset_expr
.X_op
= O_absent
;
1222 offset_reloc
= BFD_RELOC_UNUSED
;
1224 if (mips_opts
.mips16
)
1225 mips16_ip (str
, &insn
);
1228 mips_ip (str
, &insn
);
1229 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1230 str
, insn
.insn_opcode
));
1235 as_bad ("%s `%s'", insn_error
, str
);
1239 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1241 if (mips_opts
.mips16
)
1242 mips16_macro (&insn
);
1248 if (imm_expr
.X_op
!= O_absent
)
1249 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1251 else if (offset_expr
.X_op
!= O_absent
)
1252 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1254 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1258 /* See whether instruction IP reads register REG. CLASS is the type
1262 insn_uses_reg (ip
, reg
, class)
1263 struct mips_cl_insn
*ip
;
1265 enum mips_regclass
class;
1267 if (class == MIPS16_REG
)
1269 assert (mips_opts
.mips16
);
1270 reg
= mips16_to_32_reg_map
[reg
];
1271 class = MIPS_GR_REG
;
1274 /* Don't report on general register 0, since it never changes. */
1275 if (class == MIPS_GR_REG
&& reg
== 0)
1278 if (class == MIPS_FP_REG
)
1280 assert (! mips_opts
.mips16
);
1281 /* If we are called with either $f0 or $f1, we must check $f0.
1282 This is not optimal, because it will introduce an unnecessary
1283 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1284 need to distinguish reading both $f0 and $f1 or just one of
1285 them. Note that we don't have to check the other way,
1286 because there is no instruction that sets both $f0 and $f1
1287 and requires a delay. */
1288 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1289 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1290 == (reg
&~ (unsigned) 1)))
1292 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1293 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1294 == (reg
&~ (unsigned) 1)))
1297 else if (! mips_opts
.mips16
)
1299 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1300 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1302 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1303 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1308 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1309 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1310 & MIPS16OP_MASK_RX
)]
1313 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1314 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1315 & MIPS16OP_MASK_RY
)]
1318 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1319 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1320 & MIPS16OP_MASK_MOVE32Z
)]
1323 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1325 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1327 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1329 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1330 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1331 & MIPS16OP_MASK_REGR32
) == reg
)
1338 /* This function returns true if modifying a register requires a
1342 reg_needs_delay (reg
)
1345 unsigned long prev_pinfo
;
1347 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1348 if (! mips_opts
.noreorder
1349 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1350 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1351 || (! gpr_interlocks
1352 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1354 /* A load from a coprocessor or from memory. All load
1355 delays delay the use of general register rt for one
1356 instruction on the r3000. The r6000 and r4000 use
1358 /* Itbl support may require additional care here. */
1359 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1360 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1367 /* Mark instruction labels in mips16 mode. This permits the linker to
1368 handle them specially, such as generating jalx instructions when
1369 needed. We also make them odd for the duration of the assembly, in
1370 order to generate the right sort of code. We will make them even
1371 in the adjust_symtab routine, while leaving them marked. This is
1372 convenient for the debugger and the disassembler. The linker knows
1373 to make them odd again. */
1376 mips16_mark_labels ()
1378 if (mips_opts
.mips16
)
1380 struct insn_label_list
*l
;
1382 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1385 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1386 S_SET_OTHER (l
->label
, STO_MIPS16
);
1388 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1389 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1394 /* Output an instruction. PLACE is where to put the instruction; if
1395 it is NULL, this uses frag_more to get room. IP is the instruction
1396 information. ADDRESS_EXPR is an operand of the instruction to be
1397 used with RELOC_TYPE. */
1400 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1402 struct mips_cl_insn
*ip
;
1403 expressionS
*address_expr
;
1404 bfd_reloc_code_real_type reloc_type
;
1405 boolean unmatched_hi
;
1407 register unsigned long prev_pinfo
, pinfo
;
1412 /* Mark instruction labels in mips16 mode. */
1413 if (mips_opts
.mips16
)
1414 mips16_mark_labels ();
1416 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1417 pinfo
= ip
->insn_mo
->pinfo
;
1419 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1423 /* If the previous insn required any delay slots, see if we need
1424 to insert a NOP or two. There are eight kinds of possible
1425 hazards, of which an instruction can have at most one type.
1426 (1) a load from memory delay
1427 (2) a load from a coprocessor delay
1428 (3) an unconditional branch delay
1429 (4) a conditional branch delay
1430 (5) a move to coprocessor register delay
1431 (6) a load coprocessor register from memory delay
1432 (7) a coprocessor condition code delay
1433 (8) a HI/LO special register delay
1435 There are a lot of optimizations we could do that we don't.
1436 In particular, we do not, in general, reorder instructions.
1437 If you use gcc with optimization, it will reorder
1438 instructions and generally do much more optimization then we
1439 do here; repeating all that work in the assembler would only
1440 benefit hand written assembly code, and does not seem worth
1443 /* This is how a NOP is emitted. */
1444 #define emit_nop() \
1446 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1447 : md_number_to_chars (frag_more (4), 0, 4))
1449 /* The previous insn might require a delay slot, depending upon
1450 the contents of the current insn. */
1451 if (! mips_opts
.mips16
1452 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1453 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1454 && ! cop_interlocks
)
1455 || (! gpr_interlocks
1456 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1458 /* A load from a coprocessor or from memory. All load
1459 delays delay the use of general register rt for one
1460 instruction on the r3000. The r6000 and r4000 use
1462 /* Itbl support may require additional care here. */
1463 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1464 if (mips_optimize
== 0
1465 || insn_uses_reg (ip
,
1466 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1471 else if (! mips_opts
.mips16
1472 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1473 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1474 && ! cop_interlocks
)
1475 || (mips_opts
.isa
== ISA_MIPS1
1476 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1478 /* A generic coprocessor delay. The previous instruction
1479 modified a coprocessor general or control register. If
1480 it modified a control register, we need to avoid any
1481 coprocessor instruction (this is probably not always
1482 required, but it sometimes is). If it modified a general
1483 register, we avoid using that register.
1485 On the r6000 and r4000 loading a coprocessor register
1486 from memory is interlocked, and does not require a delay.
1488 This case is not handled very well. There is no special
1489 knowledge of CP0 handling, and the coprocessors other
1490 than the floating point unit are not distinguished at
1492 /* Itbl support may require additional care here. FIXME!
1493 Need to modify this to include knowledge about
1494 user specified delays! */
1495 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1497 if (mips_optimize
== 0
1498 || insn_uses_reg (ip
,
1499 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1504 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1506 if (mips_optimize
== 0
1507 || insn_uses_reg (ip
,
1508 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1515 /* We don't know exactly what the previous instruction
1516 does. If the current instruction uses a coprocessor
1517 register, we must insert a NOP. If previous
1518 instruction may set the condition codes, and the
1519 current instruction uses them, we must insert two
1521 /* Itbl support may require additional care here. */
1522 if (mips_optimize
== 0
1523 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1524 && (pinfo
& INSN_READ_COND_CODE
)))
1526 else if (pinfo
& INSN_COP
)
1530 else if (! mips_opts
.mips16
1531 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1532 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1533 && ! cop_interlocks
)
1535 /* The previous instruction sets the coprocessor condition
1536 codes, but does not require a general coprocessor delay
1537 (this means it is a floating point comparison
1538 instruction). If this instruction uses the condition
1539 codes, we need to insert a single NOP. */
1540 /* Itbl support may require additional care here. */
1541 if (mips_optimize
== 0
1542 || (pinfo
& INSN_READ_COND_CODE
))
1546 /* If we're fixing up mfhi/mflo for the r7000 and the
1547 previous insn was an mfhi/mflo and the current insn
1548 reads the register that the mfhi/mflo wrote to, then
1551 else if (mips_7000_hilo_fix
1552 && MF_HILO_INSN (prev_pinfo
)
1553 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1560 /* If we're fixing up mfhi/mflo for the r7000 and the
1561 2nd previous insn was an mfhi/mflo and the current insn
1562 reads the register that the mfhi/mflo wrote to, then
1565 else if (mips_7000_hilo_fix
1566 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1567 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1575 else if (prev_pinfo
& INSN_READ_LO
)
1577 /* The previous instruction reads the LO register; if the
1578 current instruction writes to the LO register, we must
1579 insert two NOPS. Some newer processors have interlocks.
1580 Also the tx39's multiply instructions can be exectuted
1581 immediatly after a read from HI/LO (without the delay),
1582 though the tx39's divide insns still do require the
1584 if (! (hilo_interlocks
1585 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1586 && (mips_optimize
== 0
1587 || (pinfo
& INSN_WRITE_LO
)))
1589 /* Most mips16 branch insns don't have a delay slot.
1590 If a read from LO is immediately followed by a branch
1591 to a write to LO we have a read followed by a write
1592 less than 2 insns away. We assume the target of
1593 a branch might be a write to LO, and insert a nop
1594 between a read and an immediately following branch. */
1595 else if (mips_opts
.mips16
1596 && (mips_optimize
== 0
1597 || (pinfo
& MIPS16_INSN_BRANCH
)))
1600 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1602 /* The previous instruction reads the HI register; if the
1603 current instruction writes to the HI register, we must
1604 insert a NOP. Some newer processors have interlocks.
1605 Also the note tx39's multiply above. */
1606 if (! (hilo_interlocks
1607 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1608 && (mips_optimize
== 0
1609 || (pinfo
& INSN_WRITE_HI
)))
1611 /* Most mips16 branch insns don't have a delay slot.
1612 If a read from HI is immediately followed by a branch
1613 to a write to HI we have a read followed by a write
1614 less than 2 insns away. We assume the target of
1615 a branch might be a write to HI, and insert a nop
1616 between a read and an immediately following branch. */
1617 else if (mips_opts
.mips16
1618 && (mips_optimize
== 0
1619 || (pinfo
& MIPS16_INSN_BRANCH
)))
1623 /* If the previous instruction was in a noreorder section, then
1624 we don't want to insert the nop after all. */
1625 /* Itbl support may require additional care here. */
1626 if (prev_insn_unreordered
)
1629 /* There are two cases which require two intervening
1630 instructions: 1) setting the condition codes using a move to
1631 coprocessor instruction which requires a general coprocessor
1632 delay and then reading the condition codes 2) reading the HI
1633 or LO register and then writing to it (except on processors
1634 which have interlocks). If we are not already emitting a NOP
1635 instruction, we must check for these cases compared to the
1636 instruction previous to the previous instruction. */
1637 if ((! mips_opts
.mips16
1638 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1639 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1640 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1641 && (pinfo
& INSN_READ_COND_CODE
)
1642 && ! cop_interlocks
)
1643 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1644 && (pinfo
& INSN_WRITE_LO
)
1645 && ! (hilo_interlocks
1646 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1647 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1648 && (pinfo
& INSN_WRITE_HI
)
1649 && ! (hilo_interlocks
1650 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1655 if (prev_prev_insn_unreordered
)
1658 if (prev_prev_nop
&& nops
== 0)
1661 /* If we are being given a nop instruction, don't bother with
1662 one of the nops we would otherwise output. This will only
1663 happen when a nop instruction is used with mips_optimize set
1666 && ! mips_opts
.noreorder
1667 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1670 /* Now emit the right number of NOP instructions. */
1671 if (nops
> 0 && ! mips_opts
.noreorder
)
1674 unsigned long old_frag_offset
;
1676 struct insn_label_list
*l
;
1678 old_frag
= frag_now
;
1679 old_frag_offset
= frag_now_fix ();
1681 for (i
= 0; i
< nops
; i
++)
1686 listing_prev_line ();
1687 /* We may be at the start of a variant frag. In case we
1688 are, make sure there is enough space for the frag
1689 after the frags created by listing_prev_line. The
1690 argument to frag_grow here must be at least as large
1691 as the argument to all other calls to frag_grow in
1692 this file. We don't have to worry about being in the
1693 middle of a variant frag, because the variants insert
1694 all needed nop instructions themselves. */
1698 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1700 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1701 symbol_set_frag (l
->label
, frag_now
);
1702 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1703 /* mips16 text labels are stored as odd. */
1704 if (mips_opts
.mips16
)
1705 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1708 #ifndef NO_ECOFF_DEBUGGING
1709 if (ECOFF_DEBUGGING
)
1710 ecoff_fix_loc (old_frag
, old_frag_offset
);
1713 else if (prev_nop_frag
!= NULL
)
1715 /* We have a frag holding nops we may be able to remove. If
1716 we don't need any nops, we can decrease the size of
1717 prev_nop_frag by the size of one instruction. If we do
1718 need some nops, we count them in prev_nops_required. */
1719 if (prev_nop_frag_since
== 0)
1723 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1724 --prev_nop_frag_holds
;
1727 prev_nop_frag_required
+= nops
;
1731 if (prev_prev_nop
== 0)
1733 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1734 --prev_nop_frag_holds
;
1737 ++prev_nop_frag_required
;
1740 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1741 prev_nop_frag
= NULL
;
1743 ++prev_nop_frag_since
;
1745 /* Sanity check: by the time we reach the second instruction
1746 after prev_nop_frag, we should have used up all the nops
1747 one way or another. */
1748 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1752 if (reloc_type
> BFD_RELOC_UNUSED
)
1754 /* We need to set up a variant frag. */
1755 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1756 f
= frag_var (rs_machine_dependent
, 4, 0,
1757 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1758 mips16_small
, mips16_ext
,
1760 & INSN_UNCOND_BRANCH_DELAY
),
1761 (prev_insn_reloc_type
1762 == BFD_RELOC_MIPS16_JMP
)),
1763 make_expr_symbol (address_expr
), (offsetT
) 0,
1766 else if (place
!= NULL
)
1768 else if (mips_opts
.mips16
1770 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1772 /* Make sure there is enough room to swap this instruction with
1773 a following jump instruction. */
1779 if (mips_opts
.mips16
1780 && mips_opts
.noreorder
1781 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1782 as_warn (_("extended instruction in delay slot"));
1788 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1790 if (address_expr
->X_op
== O_constant
)
1795 ip
->insn_opcode
|= address_expr
->X_add_number
;
1798 case BFD_RELOC_LO16
:
1799 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1802 case BFD_RELOC_MIPS_JMP
:
1803 if ((address_expr
->X_add_number
& 3) != 0)
1804 as_bad (_("jump to misaligned address (0x%lx)"),
1805 (unsigned long) address_expr
->X_add_number
);
1806 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1809 case BFD_RELOC_MIPS16_JMP
:
1810 if ((address_expr
->X_add_number
& 3) != 0)
1811 as_bad (_("jump to misaligned address (0x%lx)"),
1812 (unsigned long) address_expr
->X_add_number
);
1814 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1815 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1816 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1819 case BFD_RELOC_16_PCREL_S2
:
1829 /* Don't generate a reloc if we are writing into a variant
1833 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1835 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1839 struct mips_hi_fixup
*hi_fixup
;
1841 assert (reloc_type
== BFD_RELOC_HI16_S
);
1842 hi_fixup
= ((struct mips_hi_fixup
*)
1843 xmalloc (sizeof (struct mips_hi_fixup
)));
1844 hi_fixup
->fixp
= fixp
;
1845 hi_fixup
->seg
= now_seg
;
1846 hi_fixup
->next
= mips_hi_fixup_list
;
1847 mips_hi_fixup_list
= hi_fixup
;
1853 if (! mips_opts
.mips16
)
1854 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1855 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1857 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1858 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1864 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1867 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1870 /* Update the register mask information. */
1871 if (! mips_opts
.mips16
)
1873 if (pinfo
& INSN_WRITE_GPR_D
)
1874 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1875 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1876 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1877 if (pinfo
& INSN_READ_GPR_S
)
1878 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1879 if (pinfo
& INSN_WRITE_GPR_31
)
1880 mips_gprmask
|= 1 << 31;
1881 if (pinfo
& INSN_WRITE_FPR_D
)
1882 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1883 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1884 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1885 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1886 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1887 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1888 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1889 if (pinfo
& INSN_COP
)
1891 /* We don't keep enough information to sort these cases out.
1892 The itbl support does keep this information however, although
1893 we currently don't support itbl fprmats as part of the cop
1894 instruction. May want to add this support in the future. */
1896 /* Never set the bit for $0, which is always zero. */
1897 mips_gprmask
&= ~1 << 0;
1901 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1902 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1903 & MIPS16OP_MASK_RX
);
1904 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1905 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1906 & MIPS16OP_MASK_RY
);
1907 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1908 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1909 & MIPS16OP_MASK_RZ
);
1910 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1911 mips_gprmask
|= 1 << TREG
;
1912 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1913 mips_gprmask
|= 1 << SP
;
1914 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1915 mips_gprmask
|= 1 << RA
;
1916 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1917 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1918 if (pinfo
& MIPS16_INSN_READ_Z
)
1919 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1920 & MIPS16OP_MASK_MOVE32Z
);
1921 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1922 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1923 & MIPS16OP_MASK_REGR32
);
1926 if (place
== NULL
&& ! mips_opts
.noreorder
)
1928 /* Filling the branch delay slot is more complex. We try to
1929 switch the branch with the previous instruction, which we can
1930 do if the previous instruction does not set up a condition
1931 that the branch tests and if the branch is not itself the
1932 target of any branch. */
1933 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1934 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1936 if (mips_optimize
< 2
1937 /* If we have seen .set volatile or .set nomove, don't
1939 || mips_opts
.nomove
!= 0
1940 /* If we had to emit any NOP instructions, then we
1941 already know we can not swap. */
1943 /* If we don't even know the previous insn, we can not
1945 || ! prev_insn_valid
1946 /* If the previous insn is already in a branch delay
1947 slot, then we can not swap. */
1948 || prev_insn_is_delay_slot
1949 /* If the previous previous insn was in a .set
1950 noreorder, we can't swap. Actually, the MIPS
1951 assembler will swap in this situation. However, gcc
1952 configured -with-gnu-as will generate code like
1958 in which we can not swap the bne and INSN. If gcc is
1959 not configured -with-gnu-as, it does not output the
1960 .set pseudo-ops. We don't have to check
1961 prev_insn_unreordered, because prev_insn_valid will
1962 be 0 in that case. We don't want to use
1963 prev_prev_insn_valid, because we do want to be able
1964 to swap at the start of a function. */
1965 || prev_prev_insn_unreordered
1966 /* If the branch is itself the target of a branch, we
1967 can not swap. We cheat on this; all we check for is
1968 whether there is a label on this instruction. If
1969 there are any branches to anything other than a
1970 label, users must use .set noreorder. */
1971 || insn_labels
!= NULL
1972 /* If the previous instruction is in a variant frag, we
1973 can not do the swap. This does not apply to the
1974 mips16, which uses variant frags for different
1976 || (! mips_opts
.mips16
1977 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1978 /* If the branch reads the condition codes, we don't
1979 even try to swap, because in the sequence
1984 we can not swap, and I don't feel like handling that
1986 || (! mips_opts
.mips16
1987 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1988 && (pinfo
& INSN_READ_COND_CODE
))
1989 /* We can not swap with an instruction that requires a
1990 delay slot, becase the target of the branch might
1991 interfere with that instruction. */
1992 || (! mips_opts
.mips16
1993 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1995 /* Itbl support may require additional care here. */
1996 & (INSN_LOAD_COPROC_DELAY
1997 | INSN_COPROC_MOVE_DELAY
1998 | INSN_WRITE_COND_CODE
)))
1999 || (! (hilo_interlocks
2000 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2004 || (! mips_opts
.mips16
2006 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2007 || (! mips_opts
.mips16
2008 && mips_opts
.isa
== ISA_MIPS1
2009 /* Itbl support may require additional care here. */
2010 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2011 /* We can not swap with a branch instruction. */
2013 & (INSN_UNCOND_BRANCH_DELAY
2014 | INSN_COND_BRANCH_DELAY
2015 | INSN_COND_BRANCH_LIKELY
))
2016 /* We do not swap with a trap instruction, since it
2017 complicates trap handlers to have the trap
2018 instruction be in a delay slot. */
2019 || (prev_pinfo
& INSN_TRAP
)
2020 /* If the branch reads a register that the previous
2021 instruction sets, we can not swap. */
2022 || (! mips_opts
.mips16
2023 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2024 && insn_uses_reg (ip
,
2025 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2028 || (! mips_opts
.mips16
2029 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2030 && insn_uses_reg (ip
,
2031 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2034 || (mips_opts
.mips16
2035 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2036 && insn_uses_reg (ip
,
2037 ((prev_insn
.insn_opcode
2039 & MIPS16OP_MASK_RX
),
2041 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2042 && insn_uses_reg (ip
,
2043 ((prev_insn
.insn_opcode
2045 & MIPS16OP_MASK_RY
),
2047 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2048 && insn_uses_reg (ip
,
2049 ((prev_insn
.insn_opcode
2051 & MIPS16OP_MASK_RZ
),
2053 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2054 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2055 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2056 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2057 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2058 && insn_uses_reg (ip
,
2059 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2062 /* If the branch writes a register that the previous
2063 instruction sets, we can not swap (we know that
2064 branches write only to RD or to $31). */
2065 || (! mips_opts
.mips16
2066 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2067 && (((pinfo
& INSN_WRITE_GPR_D
)
2068 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2069 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2070 || ((pinfo
& INSN_WRITE_GPR_31
)
2071 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2074 || (! mips_opts
.mips16
2075 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2076 && (((pinfo
& INSN_WRITE_GPR_D
)
2077 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2078 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2079 || ((pinfo
& INSN_WRITE_GPR_31
)
2080 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2083 || (mips_opts
.mips16
2084 && (pinfo
& MIPS16_INSN_WRITE_31
)
2085 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2086 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2087 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2089 /* If the branch writes a register that the previous
2090 instruction reads, we can not swap (we know that
2091 branches only write to RD or to $31). */
2092 || (! mips_opts
.mips16
2093 && (pinfo
& INSN_WRITE_GPR_D
)
2094 && insn_uses_reg (&prev_insn
,
2095 ((ip
->insn_opcode
>> OP_SH_RD
)
2098 || (! mips_opts
.mips16
2099 && (pinfo
& INSN_WRITE_GPR_31
)
2100 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2101 || (mips_opts
.mips16
2102 && (pinfo
& MIPS16_INSN_WRITE_31
)
2103 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2104 /* If we are generating embedded PIC code, the branch
2105 might be expanded into a sequence which uses $at, so
2106 we can't swap with an instruction which reads it. */
2107 || (mips_pic
== EMBEDDED_PIC
2108 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2109 /* If the previous previous instruction has a load
2110 delay, and sets a register that the branch reads, we
2112 || (! mips_opts
.mips16
2113 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2114 /* Itbl support may require additional care here. */
2115 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2116 || (! gpr_interlocks
2117 && (prev_prev_insn
.insn_mo
->pinfo
2118 & INSN_LOAD_MEMORY_DELAY
)))
2119 && insn_uses_reg (ip
,
2120 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2123 /* If one instruction sets a condition code and the
2124 other one uses a condition code, we can not swap. */
2125 || ((pinfo
& INSN_READ_COND_CODE
)
2126 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2127 || ((pinfo
& INSN_WRITE_COND_CODE
)
2128 && (prev_pinfo
& INSN_READ_COND_CODE
))
2129 /* If the previous instruction uses the PC, we can not
2131 || (mips_opts
.mips16
2132 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2133 /* If the previous instruction was extended, we can not
2135 || (mips_opts
.mips16
&& prev_insn_extended
)
2136 /* If the previous instruction had a fixup in mips16
2137 mode, we can not swap. This normally means that the
2138 previous instruction was a 4 byte branch anyhow. */
2139 || (mips_opts
.mips16
&& prev_insn_fixp
)
2140 /* If the previous instruction is a sync, sync.l, or
2141 sync.p, we can not swap. */
2142 || (prev_pinfo
& INSN_SYNC
))
2144 /* We could do even better for unconditional branches to
2145 portions of this object file; we could pick up the
2146 instruction at the destination, put it in the delay
2147 slot, and bump the destination address. */
2149 /* Update the previous insn information. */
2150 prev_prev_insn
= *ip
;
2151 prev_insn
.insn_mo
= &dummy_opcode
;
2155 /* It looks like we can actually do the swap. */
2156 if (! mips_opts
.mips16
)
2161 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2162 memcpy (temp
, prev_f
, 4);
2163 memcpy (prev_f
, f
, 4);
2164 memcpy (f
, temp
, 4);
2167 prev_insn_fixp
->fx_frag
= frag_now
;
2168 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2172 fixp
->fx_frag
= prev_insn_frag
;
2173 fixp
->fx_where
= prev_insn_where
;
2181 assert (prev_insn_fixp
== NULL
);
2182 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2183 memcpy (temp
, prev_f
, 2);
2184 memcpy (prev_f
, f
, 2);
2185 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2187 assert (reloc_type
== BFD_RELOC_UNUSED
);
2188 memcpy (f
, temp
, 2);
2192 memcpy (f
, f
+ 2, 2);
2193 memcpy (f
+ 2, temp
, 2);
2197 fixp
->fx_frag
= prev_insn_frag
;
2198 fixp
->fx_where
= prev_insn_where
;
2202 /* Update the previous insn information; leave prev_insn
2204 prev_prev_insn
= *ip
;
2206 prev_insn_is_delay_slot
= 1;
2208 /* If that was an unconditional branch, forget the previous
2209 insn information. */
2210 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2212 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2213 prev_insn
.insn_mo
= &dummy_opcode
;
2216 prev_insn_fixp
= NULL
;
2217 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2218 prev_insn_extended
= 0;
2220 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2222 /* We don't yet optimize a branch likely. What we should do
2223 is look at the target, copy the instruction found there
2224 into the delay slot, and increment the branch to jump to
2225 the next instruction. */
2227 /* Update the previous insn information. */
2228 prev_prev_insn
= *ip
;
2229 prev_insn
.insn_mo
= &dummy_opcode
;
2230 prev_insn_fixp
= NULL
;
2231 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2232 prev_insn_extended
= 0;
2236 /* Update the previous insn information. */
2238 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2240 prev_prev_insn
= prev_insn
;
2243 /* Any time we see a branch, we always fill the delay slot
2244 immediately; since this insn is not a branch, we know it
2245 is not in a delay slot. */
2246 prev_insn_is_delay_slot
= 0;
2248 prev_insn_fixp
= fixp
;
2249 prev_insn_reloc_type
= reloc_type
;
2250 if (mips_opts
.mips16
)
2251 prev_insn_extended
= (ip
->use_extend
2252 || reloc_type
> BFD_RELOC_UNUSED
);
2255 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2256 prev_insn_unreordered
= 0;
2257 prev_insn_frag
= frag_now
;
2258 prev_insn_where
= f
- frag_now
->fr_literal
;
2259 prev_insn_valid
= 1;
2261 else if (place
== NULL
)
2263 /* We need to record a bit of information even when we are not
2264 reordering, in order to determine the base address for mips16
2265 PC relative relocs. */
2266 prev_prev_insn
= prev_insn
;
2268 prev_insn_reloc_type
= reloc_type
;
2269 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2270 prev_insn_unreordered
= 1;
2273 /* We just output an insn, so the next one doesn't have a label. */
2274 mips_clear_insn_labels ();
2276 /* We must ensure that a fixup associated with an unmatched %hi
2277 reloc does not become a variant frag. Otherwise, the
2278 rearrangement of %hi relocs in frob_file may confuse
2282 frag_wane (frag_now
);
2287 /* This function forgets that there was any previous instruction or
2288 label. If PRESERVE is non-zero, it remembers enough information to
2289 know whether nops are needed before a noreorder section. */
2292 mips_no_prev_insn (preserve
)
2297 prev_insn
.insn_mo
= &dummy_opcode
;
2298 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2299 prev_nop_frag
= NULL
;
2300 prev_nop_frag_holds
= 0;
2301 prev_nop_frag_required
= 0;
2302 prev_nop_frag_since
= 0;
2304 prev_insn_valid
= 0;
2305 prev_insn_is_delay_slot
= 0;
2306 prev_insn_unreordered
= 0;
2307 prev_insn_extended
= 0;
2308 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2309 prev_prev_insn_unreordered
= 0;
2310 mips_clear_insn_labels ();
2313 /* This function must be called whenever we turn on noreorder or emit
2314 something other than instructions. It inserts any NOPS which might
2315 be needed by the previous instruction, and clears the information
2316 kept for the previous instructions. The INSNS parameter is true if
2317 instructions are to follow. */
2320 mips_emit_delays (insns
)
2323 if (! mips_opts
.noreorder
)
2328 if ((! mips_opts
.mips16
2329 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2330 && (! cop_interlocks
2331 && (prev_insn
.insn_mo
->pinfo
2332 & (INSN_LOAD_COPROC_DELAY
2333 | INSN_COPROC_MOVE_DELAY
2334 | INSN_WRITE_COND_CODE
))))
2335 || (! hilo_interlocks
2336 && (prev_insn
.insn_mo
->pinfo
2339 || (! mips_opts
.mips16
2341 && (prev_insn
.insn_mo
->pinfo
2342 & INSN_LOAD_MEMORY_DELAY
))
2343 || (! mips_opts
.mips16
2344 && mips_opts
.isa
== ISA_MIPS1
2345 && (prev_insn
.insn_mo
->pinfo
2346 & INSN_COPROC_MEMORY_DELAY
)))
2348 /* Itbl support may require additional care here. */
2350 if ((! mips_opts
.mips16
2351 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2352 && (! cop_interlocks
2353 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2354 || (! hilo_interlocks
2355 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2356 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2359 if (prev_insn_unreordered
)
2362 else if ((! mips_opts
.mips16
2363 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2364 && (! cop_interlocks
2365 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2366 || (! hilo_interlocks
2367 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2368 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2370 /* Itbl support may require additional care here. */
2371 if (! prev_prev_insn_unreordered
)
2377 struct insn_label_list
*l
;
2381 /* Record the frag which holds the nop instructions, so
2382 that we can remove them if we don't need them. */
2383 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2384 prev_nop_frag
= frag_now
;
2385 prev_nop_frag_holds
= nops
;
2386 prev_nop_frag_required
= 0;
2387 prev_nop_frag_since
= 0;
2390 for (; nops
> 0; --nops
)
2395 /* Move on to a new frag, so that it is safe to simply
2396 decrease the size of prev_nop_frag. */
2397 frag_wane (frag_now
);
2401 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2403 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2404 symbol_set_frag (l
->label
, frag_now
);
2405 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2406 /* mips16 text labels are stored as odd. */
2407 if (mips_opts
.mips16
)
2408 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2413 /* Mark instruction labels in mips16 mode. */
2414 if (mips_opts
.mips16
&& insns
)
2415 mips16_mark_labels ();
2417 mips_no_prev_insn (insns
);
2420 /* Build an instruction created by a macro expansion. This is passed
2421 a pointer to the count of instructions created so far, an
2422 expression, the name of the instruction to build, an operand format
2423 string, and corresponding arguments. */
2427 macro_build (char *place
,
2435 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2444 struct mips_cl_insn insn
;
2445 bfd_reloc_code_real_type r
;
2449 va_start (args
, fmt
);
2455 * If the macro is about to expand into a second instruction,
2456 * print a warning if needed. We need to pass ip as a parameter
2457 * to generate a better warning message here...
2459 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2460 as_warn (_("Macro instruction expanded into multiple instructions"));
2463 *counter
+= 1; /* bump instruction counter */
2465 if (mips_opts
.mips16
)
2467 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2472 r
= BFD_RELOC_UNUSED
;
2473 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2474 assert (insn
.insn_mo
);
2475 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2477 /* Search until we get a match for NAME. */
2480 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2481 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2482 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2484 && (mips_cpu
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2488 assert (insn
.insn_mo
->name
);
2489 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2492 insn
.insn_opcode
= insn
.insn_mo
->match
;
2508 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2514 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2519 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2524 int tmp
= va_arg (args
, int);
2526 insn
.insn_opcode
|= tmp
<< 16;
2527 insn
.insn_opcode
|= tmp
<< 11;
2533 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2540 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2544 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2548 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2552 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2556 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2563 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2569 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2570 assert (r
== BFD_RELOC_MIPS_GPREL
2571 || r
== BFD_RELOC_MIPS_LITERAL
2572 || r
== BFD_RELOC_LO16
2573 || r
== BFD_RELOC_MIPS_GOT16
2574 || r
== BFD_RELOC_MIPS_CALL16
2575 || r
== BFD_RELOC_MIPS_GOT_LO16
2576 || r
== BFD_RELOC_MIPS_CALL_LO16
2577 || (ep
->X_op
== O_subtract
2578 && r
== BFD_RELOC_PCREL_LO16
));
2582 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2584 && (ep
->X_op
== O_constant
2585 || (ep
->X_op
== O_symbol
2586 && (r
== BFD_RELOC_HI16_S
2587 || r
== BFD_RELOC_HI16
2588 || r
== BFD_RELOC_MIPS_GOT_HI16
2589 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2590 || (ep
->X_op
== O_subtract
2591 && r
== BFD_RELOC_PCREL_HI16_S
)));
2592 if (ep
->X_op
== O_constant
)
2594 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2596 r
= BFD_RELOC_UNUSED
;
2601 assert (ep
!= NULL
);
2603 * This allows macro() to pass an immediate expression for
2604 * creating short branches without creating a symbol.
2605 * Note that the expression still might come from the assembly
2606 * input, in which case the value is not checked for range nor
2607 * is a relocation entry generated (yuck).
2609 if (ep
->X_op
== O_constant
)
2611 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2615 r
= BFD_RELOC_16_PCREL_S2
;
2619 assert (ep
!= NULL
);
2620 r
= BFD_RELOC_MIPS_JMP
;
2624 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2633 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2635 append_insn (place
, &insn
, ep
, r
, false);
2639 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2641 int *counter ATTRIBUTE_UNUSED
;
2647 struct mips_cl_insn insn
;
2648 bfd_reloc_code_real_type r
;
2650 r
= BFD_RELOC_UNUSED
;
2651 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2652 assert (insn
.insn_mo
);
2653 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2655 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2656 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2659 assert (insn
.insn_mo
->name
);
2660 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2663 insn
.insn_opcode
= insn
.insn_mo
->match
;
2664 insn
.use_extend
= false;
2683 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2688 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2692 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2696 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2706 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2713 regno
= va_arg (args
, int);
2714 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2715 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2736 assert (ep
!= NULL
);
2738 if (ep
->X_op
!= O_constant
)
2739 r
= BFD_RELOC_UNUSED
+ c
;
2742 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2743 false, false, &insn
.insn_opcode
,
2744 &insn
.use_extend
, &insn
.extend
);
2746 r
= BFD_RELOC_UNUSED
;
2752 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2759 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2761 append_insn (place
, &insn
, ep
, r
, false);
2765 * Generate a "lui" instruction.
2768 macro_build_lui (place
, counter
, ep
, regnum
)
2774 expressionS high_expr
;
2775 struct mips_cl_insn insn
;
2776 bfd_reloc_code_real_type r
;
2777 CONST
char *name
= "lui";
2778 CONST
char *fmt
= "t,u";
2780 assert (! mips_opts
.mips16
);
2786 high_expr
.X_op
= O_constant
;
2787 high_expr
.X_add_number
= ep
->X_add_number
;
2790 if (high_expr
.X_op
== O_constant
)
2792 /* we can compute the instruction now without a relocation entry */
2793 if (high_expr
.X_add_number
& 0x8000)
2794 high_expr
.X_add_number
+= 0x10000;
2795 high_expr
.X_add_number
=
2796 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2797 r
= BFD_RELOC_UNUSED
;
2801 assert (ep
->X_op
== O_symbol
);
2802 /* _gp_disp is a special case, used from s_cpload. */
2803 assert (mips_pic
== NO_PIC
2804 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2805 r
= BFD_RELOC_HI16_S
;
2809 * If the macro is about to expand into a second instruction,
2810 * print a warning if needed. We need to pass ip as a parameter
2811 * to generate a better warning message here...
2813 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2814 as_warn (_("Macro instruction expanded into multiple instructions"));
2817 *counter
+= 1; /* bump instruction counter */
2819 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2820 assert (insn
.insn_mo
);
2821 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2822 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2824 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2825 if (r
== BFD_RELOC_UNUSED
)
2827 insn
.insn_opcode
|= high_expr
.X_add_number
;
2828 append_insn (place
, &insn
, NULL
, r
, false);
2831 append_insn (place
, &insn
, &high_expr
, r
, false);
2835 * Generates code to set the $at register to true (one)
2836 * if reg is less than the immediate expression.
2839 set_at (counter
, reg
, unsignedp
)
2844 if (imm_expr
.X_op
== O_constant
2845 && imm_expr
.X_add_number
>= -0x8000
2846 && imm_expr
.X_add_number
< 0x8000)
2847 macro_build ((char *) NULL
, counter
, &imm_expr
,
2848 unsignedp
? "sltiu" : "slti",
2849 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2852 load_register (counter
, AT
, &imm_expr
, 0);
2853 macro_build ((char *) NULL
, counter
, NULL
,
2854 unsignedp
? "sltu" : "slt",
2855 "d,v,t", AT
, reg
, AT
);
2859 /* Warn if an expression is not a constant. */
2862 check_absolute_expr (ip
, ex
)
2863 struct mips_cl_insn
*ip
;
2866 if (ex
->X_op
== O_big
)
2867 as_bad (_("unsupported large constant"));
2868 else if (ex
->X_op
!= O_constant
)
2869 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2872 /* Count the leading zeroes by performing a binary chop. This is a
2873 bulky bit of source, but performance is a LOT better for the
2874 majority of values than a simple loop to count the bits:
2875 for (lcnt = 0; (lcnt < 32); lcnt++)
2876 if ((v) & (1 << (31 - lcnt)))
2878 However it is not code size friendly, and the gain will drop a bit
2879 on certain cached systems.
2881 #define COUNT_TOP_ZEROES(v) \
2882 (((v) & ~0xffff) == 0 \
2883 ? ((v) & ~0xff) == 0 \
2884 ? ((v) & ~0xf) == 0 \
2885 ? ((v) & ~0x3) == 0 \
2886 ? ((v) & ~0x1) == 0 \
2891 : ((v) & ~0x7) == 0 \
2894 : ((v) & ~0x3f) == 0 \
2895 ? ((v) & ~0x1f) == 0 \
2898 : ((v) & ~0x7f) == 0 \
2901 : ((v) & ~0xfff) == 0 \
2902 ? ((v) & ~0x3ff) == 0 \
2903 ? ((v) & ~0x1ff) == 0 \
2906 : ((v) & ~0x7ff) == 0 \
2909 : ((v) & ~0x3fff) == 0 \
2910 ? ((v) & ~0x1fff) == 0 \
2913 : ((v) & ~0x7fff) == 0 \
2916 : ((v) & ~0xffffff) == 0 \
2917 ? ((v) & ~0xfffff) == 0 \
2918 ? ((v) & ~0x3ffff) == 0 \
2919 ? ((v) & ~0x1ffff) == 0 \
2922 : ((v) & ~0x7ffff) == 0 \
2925 : ((v) & ~0x3fffff) == 0 \
2926 ? ((v) & ~0x1fffff) == 0 \
2929 : ((v) & ~0x7fffff) == 0 \
2932 : ((v) & ~0xfffffff) == 0 \
2933 ? ((v) & ~0x3ffffff) == 0 \
2934 ? ((v) & ~0x1ffffff) == 0 \
2937 : ((v) & ~0x7ffffff) == 0 \
2940 : ((v) & ~0x3fffffff) == 0 \
2941 ? ((v) & ~0x1fffffff) == 0 \
2944 : ((v) & ~0x7fffffff) == 0 \
2949 * This routine generates the least number of instructions neccessary to load
2950 * an absolute expression value into a register.
2953 load_register (counter
, reg
, ep
, dbl
)
2960 expressionS hi32
, lo32
;
2962 if (ep
->X_op
!= O_big
)
2964 assert (ep
->X_op
== O_constant
);
2965 if (ep
->X_add_number
< 0x8000
2966 && (ep
->X_add_number
>= 0
2967 || (ep
->X_add_number
>= -0x8000
2970 || sizeof (ep
->X_add_number
) > 4))))
2972 /* We can handle 16 bit signed values with an addiu to
2973 $zero. No need to ever use daddiu here, since $zero and
2974 the result are always correct in 32 bit mode. */
2975 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2976 (int) BFD_RELOC_LO16
);
2979 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2981 /* We can handle 16 bit unsigned values with an ori to
2983 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2984 (int) BFD_RELOC_LO16
);
2987 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2988 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2989 == ~ (offsetT
) 0x7fffffff))
2992 || sizeof (ep
->X_add_number
) > 4
2993 || (ep
->X_add_number
& 0x80000000) == 0))
2994 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
2995 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2996 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
2998 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2999 == ~ (offsetT
) 0xffffffff)))
3001 /* 32 bit values require an lui. */
3002 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3003 (int) BFD_RELOC_HI16
);
3004 if ((ep
->X_add_number
& 0xffff) != 0)
3005 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3006 (int) BFD_RELOC_LO16
);
3011 /* The value is larger than 32 bits. */
3013 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3015 as_bad (_("Number larger than 32 bits"));
3016 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3017 (int) BFD_RELOC_LO16
);
3021 if (ep
->X_op
!= O_big
)
3024 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3025 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3026 hi32
.X_add_number
&= 0xffffffff;
3028 lo32
.X_add_number
&= 0xffffffff;
3032 assert (ep
->X_add_number
> 2);
3033 if (ep
->X_add_number
== 3)
3034 generic_bignum
[3] = 0;
3035 else if (ep
->X_add_number
> 4)
3036 as_bad (_("Number larger than 64 bits"));
3037 lo32
.X_op
= O_constant
;
3038 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3039 hi32
.X_op
= O_constant
;
3040 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3043 if (hi32
.X_add_number
== 0)
3048 unsigned long hi
, lo
;
3050 if (hi32
.X_add_number
== 0xffffffff)
3052 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3054 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3055 reg
, 0, (int) BFD_RELOC_LO16
);
3058 if (lo32
.X_add_number
& 0x80000000)
3060 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3061 (int) BFD_RELOC_HI16
);
3062 if (lo32
.X_add_number
& 0xffff)
3063 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3064 reg
, reg
, (int) BFD_RELOC_LO16
);
3069 /* Check for 16bit shifted constant. We know that hi32 is
3070 non-zero, so start the mask on the first bit of the hi32
3075 unsigned long himask
, lomask
;
3079 himask
= 0xffff >> (32 - shift
);
3080 lomask
= (0xffff << shift
) & 0xffffffff;
3084 himask
= 0xffff << (shift
- 32);
3087 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3088 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3092 tmp
.X_op
= O_constant
;
3094 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3095 | (lo32
.X_add_number
>> shift
));
3097 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3098 macro_build ((char *) NULL
, counter
, &tmp
,
3099 "ori", "t,r,i", reg
, 0,
3100 (int) BFD_RELOC_LO16
);
3101 macro_build ((char *) NULL
, counter
, NULL
,
3102 (shift
>= 32) ? "dsll32" : "dsll",
3104 (shift
>= 32) ? shift
- 32 : shift
);
3109 while (shift
<= (64 - 16));
3111 /* Find the bit number of the lowest one bit, and store the
3112 shifted value in hi/lo. */
3113 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3114 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3118 while ((lo
& 1) == 0)
3123 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3129 while ((hi
& 1) == 0)
3138 /* Optimize if the shifted value is a (power of 2) - 1. */
3139 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3140 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3142 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3147 /* This instruction will set the register to be all
3149 tmp
.X_op
= O_constant
;
3150 tmp
.X_add_number
= (offsetT
) -1;
3151 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3152 reg
, 0, (int) BFD_RELOC_LO16
);
3156 macro_build ((char *) NULL
, counter
, NULL
,
3157 (bit
>= 32) ? "dsll32" : "dsll",
3159 (bit
>= 32) ? bit
- 32 : bit
);
3161 macro_build ((char *) NULL
, counter
, NULL
,
3162 (shift
>= 32) ? "dsrl32" : "dsrl",
3164 (shift
>= 32) ? shift
- 32 : shift
);
3169 /* Sign extend hi32 before calling load_register, because we can
3170 generally get better code when we load a sign extended value. */
3171 if ((hi32
.X_add_number
& 0x80000000) != 0)
3172 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3173 load_register (counter
, reg
, &hi32
, 0);
3176 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3180 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3189 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3191 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3192 (int) BFD_RELOC_HI16
);
3193 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3200 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3205 mid16
.X_add_number
>>= 16;
3206 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3207 freg
, (int) BFD_RELOC_LO16
);
3208 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3212 if ((lo32
.X_add_number
& 0xffff) != 0)
3213 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3214 (int) BFD_RELOC_LO16
);
3217 /* Load an address into a register. */
3220 load_address (counter
, reg
, ep
)
3227 if (ep
->X_op
!= O_constant
3228 && ep
->X_op
!= O_symbol
)
3230 as_bad (_("expression too complex"));
3231 ep
->X_op
= O_constant
;
3234 if (ep
->X_op
== O_constant
)
3236 load_register (counter
, reg
, ep
, 0);
3240 if (mips_pic
== NO_PIC
)
3242 /* If this is a reference to a GP relative symbol, we want
3243 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3245 lui $reg,<sym> (BFD_RELOC_HI16_S)
3246 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3247 If we have an addend, we always use the latter form. */
3248 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3249 || nopic_need_relax (ep
->X_add_symbol
, 1))
3254 macro_build ((char *) NULL
, counter
, ep
,
3255 ((bfd_arch_bits_per_address (stdoutput
) == 32
3256 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3257 ? "addiu" : "daddiu"),
3258 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3259 p
= frag_var (rs_machine_dependent
, 8, 0,
3260 RELAX_ENCODE (4, 8, 0, 4, 0,
3261 mips_opts
.warn_about_macros
),
3262 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3264 macro_build_lui (p
, counter
, ep
, reg
);
3267 macro_build (p
, counter
, ep
,
3268 ((bfd_arch_bits_per_address (stdoutput
) == 32
3269 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3270 ? "addiu" : "daddiu"),
3271 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3273 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3277 /* If this is a reference to an external symbol, we want
3278 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3280 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3282 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3283 If there is a constant, it must be added in after. */
3284 ex
.X_add_number
= ep
->X_add_number
;
3285 ep
->X_add_number
= 0;
3287 macro_build ((char *) NULL
, counter
, ep
,
3288 ((bfd_arch_bits_per_address (stdoutput
) == 32
3289 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3291 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3292 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3293 p
= frag_var (rs_machine_dependent
, 4, 0,
3294 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3295 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3296 macro_build (p
, counter
, ep
,
3297 ((bfd_arch_bits_per_address (stdoutput
) == 32
3298 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3299 ? "addiu" : "daddiu"),
3300 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3301 if (ex
.X_add_number
!= 0)
3303 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3304 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3305 ex
.X_op
= O_constant
;
3306 macro_build ((char *) NULL
, counter
, &ex
,
3307 ((bfd_arch_bits_per_address (stdoutput
) == 32
3308 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3309 ? "addiu" : "daddiu"),
3310 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3313 else if (mips_pic
== SVR4_PIC
)
3318 /* This is the large GOT case. If this is a reference to an
3319 external symbol, we want
3320 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3322 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3323 Otherwise, for a reference to a local symbol, we want
3324 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3326 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3327 If there is a constant, it must be added in after. */
3328 ex
.X_add_number
= ep
->X_add_number
;
3329 ep
->X_add_number
= 0;
3330 if (reg_needs_delay (GP
))
3335 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3336 (int) BFD_RELOC_MIPS_GOT_HI16
);
3337 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3338 ((bfd_arch_bits_per_address (stdoutput
) == 32
3339 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3340 ? "addu" : "daddu"),
3341 "d,v,t", reg
, reg
, GP
);
3342 macro_build ((char *) NULL
, counter
, ep
,
3343 ((bfd_arch_bits_per_address (stdoutput
) == 32
3344 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3346 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3347 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3348 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3349 mips_opts
.warn_about_macros
),
3350 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3353 /* We need a nop before loading from $gp. This special
3354 check is required because the lui which starts the main
3355 instruction stream does not refer to $gp, and so will not
3356 insert the nop which may be required. */
3357 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3360 macro_build (p
, counter
, ep
,
3361 ((bfd_arch_bits_per_address (stdoutput
) == 32
3362 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3364 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3366 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3368 macro_build (p
, counter
, ep
,
3369 ((bfd_arch_bits_per_address (stdoutput
) == 32
3370 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3371 ? "addiu" : "daddiu"),
3372 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3373 if (ex
.X_add_number
!= 0)
3375 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3376 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3377 ex
.X_op
= O_constant
;
3378 macro_build ((char *) NULL
, counter
, &ex
,
3379 ((bfd_arch_bits_per_address (stdoutput
) == 32
3380 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3381 ? "addiu" : "daddiu"),
3382 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3385 else if (mips_pic
== EMBEDDED_PIC
)
3388 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3390 macro_build ((char *) NULL
, counter
, ep
,
3391 ((bfd_arch_bits_per_address (stdoutput
) == 32
3392 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3393 ? "addiu" : "daddiu"),
3394 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3402 * This routine implements the seemingly endless macro or synthesized
3403 * instructions and addressing modes in the mips assembly language. Many
3404 * of these macros are simple and are similar to each other. These could
3405 * probably be handled by some kind of table or grammer aproach instead of
3406 * this verbose method. Others are not simple macros but are more like
3407 * optimizing code generation.
3408 * One interesting optimization is when several store macros appear
3409 * consecutivly that would load AT with the upper half of the same address.
3410 * The ensuing load upper instructions are ommited. This implies some kind
3411 * of global optimization. We currently only optimize within a single macro.
3412 * For many of the load and store macros if the address is specified as a
3413 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3414 * first load register 'at' with zero and use it as the base register. The
3415 * mips assembler simply uses register $zero. Just one tiny optimization
3420 struct mips_cl_insn
*ip
;
3422 register int treg
, sreg
, dreg
, breg
;
3438 bfd_reloc_code_real_type r
;
3440 int hold_mips_optimize
;
3442 assert (! mips_opts
.mips16
);
3444 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3445 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3446 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3447 mask
= ip
->insn_mo
->mask
;
3449 expr1
.X_op
= O_constant
;
3450 expr1
.X_op_symbol
= NULL
;
3451 expr1
.X_add_symbol
= NULL
;
3452 expr1
.X_add_number
= 1;
3464 mips_emit_delays (true);
3465 ++mips_opts
.noreorder
;
3466 mips_any_noreorder
= 1;
3468 expr1
.X_add_number
= 8;
3469 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3471 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3473 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3474 macro_build ((char *) NULL
, &icnt
, NULL
,
3475 dbl
? "dsub" : "sub",
3476 "d,v,t", dreg
, 0, sreg
);
3478 --mips_opts
.noreorder
;
3499 if (imm_expr
.X_op
== O_constant
3500 && imm_expr
.X_add_number
>= -0x8000
3501 && imm_expr
.X_add_number
< 0x8000)
3503 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3504 (int) BFD_RELOC_LO16
);
3507 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3508 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3527 if (imm_expr
.X_op
== O_constant
3528 && imm_expr
.X_add_number
>= 0
3529 && imm_expr
.X_add_number
< 0x10000)
3531 if (mask
!= M_NOR_I
)
3532 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3533 sreg
, (int) BFD_RELOC_LO16
);
3536 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3537 treg
, sreg
, (int) BFD_RELOC_LO16
);
3538 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3544 load_register (&icnt
, AT
, &imm_expr
, 0);
3545 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3562 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3564 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3568 load_register (&icnt
, AT
, &imm_expr
, 0);
3569 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3577 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3578 likely
? "bgezl" : "bgez",
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3585 likely
? "blezl" : "blez",
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3591 likely
? "beql" : "beq",
3598 /* check for > max integer */
3599 maxnum
= 0x7fffffff;
3600 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3607 if (imm_expr
.X_op
== O_constant
3608 && imm_expr
.X_add_number
>= maxnum
3609 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3612 /* result is always false */
3615 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3616 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3620 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3626 if (imm_expr
.X_op
!= O_constant
)
3627 as_bad (_("Unsupported large constant"));
3628 imm_expr
.X_add_number
++;
3632 if (mask
== M_BGEL_I
)
3634 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3637 likely
? "bgezl" : "bgez",
3641 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3643 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3644 likely
? "bgtzl" : "bgtz",
3648 maxnum
= 0x7fffffff;
3649 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3656 maxnum
= - maxnum
- 1;
3657 if (imm_expr
.X_op
== O_constant
3658 && imm_expr
.X_add_number
<= maxnum
3659 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3662 /* result is always true */
3663 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3664 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3667 set_at (&icnt
, sreg
, 0);
3668 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3669 likely
? "beql" : "beq",
3680 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3681 likely
? "beql" : "beq",
3685 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3687 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3688 likely
? "beql" : "beq",
3696 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3697 && imm_expr
.X_op
== O_constant
3698 && imm_expr
.X_add_number
== 0xffffffff))
3700 if (imm_expr
.X_op
!= O_constant
)
3701 as_bad (_("Unsupported large constant"));
3702 imm_expr
.X_add_number
++;
3706 if (mask
== M_BGEUL_I
)
3708 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3710 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3713 likely
? "bnel" : "bne",
3717 set_at (&icnt
, sreg
, 1);
3718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3719 likely
? "beql" : "beq",
3728 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3729 likely
? "bgtzl" : "bgtz",
3735 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3736 likely
? "bltzl" : "bltz",
3740 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3742 likely
? "bnel" : "bne",
3751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3752 likely
? "bnel" : "bne",
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3761 likely
? "bnel" : "bne",
3770 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3771 likely
? "blezl" : "blez",
3777 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3778 likely
? "bgezl" : "bgez",
3782 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3783 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3784 likely
? "beql" : "beq",
3791 maxnum
= 0x7fffffff;
3792 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3799 if (imm_expr
.X_op
== O_constant
3800 && imm_expr
.X_add_number
>= maxnum
3801 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3803 if (imm_expr
.X_op
!= O_constant
)
3804 as_bad (_("Unsupported large constant"));
3805 imm_expr
.X_add_number
++;
3809 if (mask
== M_BLTL_I
)
3811 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3814 likely
? "bltzl" : "bltz",
3818 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3820 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3821 likely
? "blezl" : "blez",
3825 set_at (&icnt
, sreg
, 0);
3826 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3827 likely
? "bnel" : "bne",
3836 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3837 likely
? "beql" : "beq",
3843 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3846 likely
? "beql" : "beq",
3854 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3855 && imm_expr
.X_op
== O_constant
3856 && imm_expr
.X_add_number
== 0xffffffff))
3858 if (imm_expr
.X_op
!= O_constant
)
3859 as_bad (_("Unsupported large constant"));
3860 imm_expr
.X_add_number
++;
3864 if (mask
== M_BLTUL_I
)
3866 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3868 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3871 likely
? "beql" : "beq",
3875 set_at (&icnt
, sreg
, 1);
3876 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3877 likely
? "bnel" : "bne",
3886 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3887 likely
? "bltzl" : "bltz",
3893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3894 likely
? "bgtzl" : "bgtz",
3898 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3899 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3900 likely
? "bnel" : "bne",
3911 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3912 likely
? "bnel" : "bne",
3916 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3918 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3919 likely
? "bnel" : "bne",
3935 as_warn (_("Divide by zero."));
3937 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3943 mips_emit_delays (true);
3944 ++mips_opts
.noreorder
;
3945 mips_any_noreorder
= 1;
3948 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3949 macro_build ((char *) NULL
, &icnt
, NULL
,
3950 dbl
? "ddiv" : "div",
3951 "z,s,t", sreg
, treg
);
3955 expr1
.X_add_number
= 8;
3956 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3957 macro_build ((char *) NULL
, &icnt
, NULL
,
3958 dbl
? "ddiv" : "div",
3959 "z,s,t", sreg
, treg
);
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3962 expr1
.X_add_number
= -1;
3963 macro_build ((char *) NULL
, &icnt
, &expr1
,
3964 dbl
? "daddiu" : "addiu",
3965 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3966 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3967 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3970 expr1
.X_add_number
= 1;
3971 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3972 (int) BFD_RELOC_LO16
);
3973 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3978 expr1
.X_add_number
= 0x80000000;
3979 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3980 (int) BFD_RELOC_HI16
);
3984 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3985 /* We want to close the noreorder block as soon as possible, so
3986 that later insns are available for delay slot filling. */
3987 --mips_opts
.noreorder
;
3991 expr1
.X_add_number
= 8;
3992 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3993 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3995 /* We want to close the noreorder block as soon as possible, so
3996 that later insns are available for delay slot filling. */
3997 --mips_opts
.noreorder
;
3999 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4001 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4040 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4042 as_warn (_("Divide by zero."));
4044 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4046 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4049 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4051 if (strcmp (s2
, "mflo") == 0)
4052 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4055 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4058 if (imm_expr
.X_op
== O_constant
4059 && imm_expr
.X_add_number
== -1
4060 && s
[strlen (s
) - 1] != 'u')
4062 if (strcmp (s2
, "mflo") == 0)
4065 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4068 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4072 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4076 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4077 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4078 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4097 mips_emit_delays (true);
4098 ++mips_opts
.noreorder
;
4099 mips_any_noreorder
= 1;
4102 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4104 /* We want to close the noreorder block as soon as possible, so
4105 that later insns are available for delay slot filling. */
4106 --mips_opts
.noreorder
;
4110 expr1
.X_add_number
= 8;
4111 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4112 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4114 /* We want to close the noreorder block as soon as possible, so
4115 that later insns are available for delay slot filling. */
4116 --mips_opts
.noreorder
;
4117 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4119 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4125 /* Load the address of a symbol into a register. If breg is not
4126 zero, we then add a base register to it. */
4128 /* When generating embedded PIC code, we permit expressions of
4131 where bar is an address in the current section. These are used
4132 when getting the addresses of functions. We don't permit
4133 X_add_number to be non-zero, because if the symbol is
4134 external the relaxing code needs to know that any addend is
4135 purely the offset to X_op_symbol. */
4136 if (mips_pic
== EMBEDDED_PIC
4137 && offset_expr
.X_op
== O_subtract
4138 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4139 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4140 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4142 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4146 && (offset_expr
.X_add_number
== 0
4147 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4149 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4150 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4151 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4152 ((bfd_arch_bits_per_address (stdoutput
) == 32
4153 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4154 ? "addiu" : "daddiu"),
4155 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4159 if (offset_expr
.X_op
!= O_symbol
4160 && offset_expr
.X_op
!= O_constant
)
4162 as_bad (_("expression too complex"));
4163 offset_expr
.X_op
= O_constant
;
4177 if (offset_expr
.X_op
== O_constant
)
4178 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4179 else if (mips_pic
== NO_PIC
)
4181 /* If this is a reference to an GP relative symbol, we want
4182 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4184 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4185 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4186 If we have a constant, we need two instructions anyhow,
4187 so we may as well always use the latter form. */
4188 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4189 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4194 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4195 ((bfd_arch_bits_per_address (stdoutput
) == 32
4196 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4197 ? "addiu" : "daddiu"),
4198 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4199 p
= frag_var (rs_machine_dependent
, 8, 0,
4200 RELAX_ENCODE (4, 8, 0, 4, 0,
4201 mips_opts
.warn_about_macros
),
4202 offset_expr
.X_add_symbol
, (offsetT
) 0,
4205 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4208 macro_build (p
, &icnt
, &offset_expr
,
4209 ((bfd_arch_bits_per_address (stdoutput
) == 32
4210 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4211 ? "addiu" : "daddiu"),
4212 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4214 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4216 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4218 /* If this is a reference to an external symbol, and there
4219 is no constant, we want
4220 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4221 or if tempreg is PIC_CALL_REG
4222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4223 For a local symbol, we want
4224 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4226 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4228 If we have a small constant, and this is a reference to
4229 an external symbol, we want
4230 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4232 addiu $tempreg,$tempreg,<constant>
4233 For a local symbol, we want the same instruction
4234 sequence, but we output a BFD_RELOC_LO16 reloc on the
4237 If we have a large constant, and this is a reference to
4238 an external symbol, we want
4239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4240 lui $at,<hiconstant>
4241 addiu $at,$at,<loconstant>
4242 addu $tempreg,$tempreg,$at
4243 For a local symbol, we want the same instruction
4244 sequence, but we output a BFD_RELOC_LO16 reloc on the
4245 addiu instruction. */
4246 expr1
.X_add_number
= offset_expr
.X_add_number
;
4247 offset_expr
.X_add_number
= 0;
4249 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4250 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4251 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4253 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4254 if (expr1
.X_add_number
== 0)
4262 /* We're going to put in an addu instruction using
4263 tempreg, so we may as well insert the nop right
4265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4269 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4270 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4272 ? mips_opts
.warn_about_macros
4274 offset_expr
.X_add_symbol
, (offsetT
) 0,
4278 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4281 macro_build (p
, &icnt
, &expr1
,
4282 ((bfd_arch_bits_per_address (stdoutput
) == 32
4283 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4284 ? "addiu" : "daddiu"),
4285 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4286 /* FIXME: If breg == 0, and the next instruction uses
4287 $tempreg, then if this variant case is used an extra
4288 nop will be generated. */
4290 else if (expr1
.X_add_number
>= -0x8000
4291 && expr1
.X_add_number
< 0x8000)
4293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4295 macro_build ((char *) NULL
, &icnt
, &expr1
,
4296 ((bfd_arch_bits_per_address (stdoutput
) == 32
4297 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4298 ? "addiu" : "daddiu"),
4299 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4300 (void) frag_var (rs_machine_dependent
, 0, 0,
4301 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4302 offset_expr
.X_add_symbol
, (offsetT
) 0,
4309 /* If we are going to add in a base register, and the
4310 target register and the base register are the same,
4311 then we are using AT as a temporary register. Since
4312 we want to load the constant into AT, we add our
4313 current AT (from the global offset table) and the
4314 register into the register now, and pretend we were
4315 not using a base register. */
4320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4323 ((bfd_arch_bits_per_address (stdoutput
) == 32
4324 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4325 ? "addu" : "daddu"),
4326 "d,v,t", treg
, AT
, breg
);
4332 /* Set mips_optimize around the lui instruction to avoid
4333 inserting an unnecessary nop after the lw. */
4334 hold_mips_optimize
= mips_optimize
;
4336 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4337 mips_optimize
= hold_mips_optimize
;
4339 macro_build ((char *) NULL
, &icnt
, &expr1
,
4340 ((bfd_arch_bits_per_address (stdoutput
) == 32
4341 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4342 ? "addiu" : "daddiu"),
4343 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4345 ((bfd_arch_bits_per_address (stdoutput
) == 32
4346 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4347 ? "addu" : "daddu"),
4348 "d,v,t", tempreg
, tempreg
, AT
);
4349 (void) frag_var (rs_machine_dependent
, 0, 0,
4350 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4351 offset_expr
.X_add_symbol
, (offsetT
) 0,
4356 else if (mips_pic
== SVR4_PIC
)
4359 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4360 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4362 /* This is the large GOT case. If this is a reference to an
4363 external symbol, and there is no constant, we want
4364 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4365 addu $tempreg,$tempreg,$gp
4366 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4367 or if tempreg is PIC_CALL_REG
4368 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4369 addu $tempreg,$tempreg,$gp
4370 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4371 For a local symbol, we want
4372 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4374 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4376 If we have a small constant, and this is a reference to
4377 an external symbol, we want
4378 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4379 addu $tempreg,$tempreg,$gp
4380 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4382 addiu $tempreg,$tempreg,<constant>
4383 For a local symbol, we want
4384 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4386 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4388 If we have a large constant, and this is a reference to
4389 an external symbol, we want
4390 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4391 addu $tempreg,$tempreg,$gp
4392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4393 lui $at,<hiconstant>
4394 addiu $at,$at,<loconstant>
4395 addu $tempreg,$tempreg,$at
4396 For a local symbol, we want
4397 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4398 lui $at,<hiconstant>
4399 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4400 addu $tempreg,$tempreg,$at
4402 expr1
.X_add_number
= offset_expr
.X_add_number
;
4403 offset_expr
.X_add_number
= 0;
4405 if (reg_needs_delay (GP
))
4409 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4411 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4412 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4414 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4415 tempreg
, lui_reloc_type
);
4416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4417 ((bfd_arch_bits_per_address (stdoutput
) == 32
4418 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4419 ? "addu" : "daddu"),
4420 "d,v,t", tempreg
, tempreg
, GP
);
4421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4423 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4424 if (expr1
.X_add_number
== 0)
4432 /* We're going to put in an addu instruction using
4433 tempreg, so we may as well insert the nop right
4435 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4440 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4441 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4444 ? mips_opts
.warn_about_macros
4446 offset_expr
.X_add_symbol
, (offsetT
) 0,
4449 else if (expr1
.X_add_number
>= -0x8000
4450 && expr1
.X_add_number
< 0x8000)
4452 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4454 macro_build ((char *) NULL
, &icnt
, &expr1
,
4455 ((bfd_arch_bits_per_address (stdoutput
) == 32
4456 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4457 ? "addiu" : "daddiu"),
4458 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4460 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4461 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4463 ? mips_opts
.warn_about_macros
4465 offset_expr
.X_add_symbol
, (offsetT
) 0,
4472 /* If we are going to add in a base register, and the
4473 target register and the base register are the same,
4474 then we are using AT as a temporary register. Since
4475 we want to load the constant into AT, we add our
4476 current AT (from the global offset table) and the
4477 register into the register now, and pretend we were
4478 not using a base register. */
4486 assert (tempreg
== AT
);
4487 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4489 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4490 ((bfd_arch_bits_per_address (stdoutput
) == 32
4491 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4492 ? "addu" : "daddu"),
4493 "d,v,t", treg
, AT
, breg
);
4498 /* Set mips_optimize around the lui instruction to avoid
4499 inserting an unnecessary nop after the lw. */
4500 hold_mips_optimize
= mips_optimize
;
4502 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4503 mips_optimize
= hold_mips_optimize
;
4505 macro_build ((char *) NULL
, &icnt
, &expr1
,
4506 ((bfd_arch_bits_per_address (stdoutput
) == 32
4507 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4508 ? "addiu" : "daddiu"),
4509 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4511 ((bfd_arch_bits_per_address (stdoutput
) == 32
4512 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4513 ? "addu" : "daddu"),
4514 "d,v,t", dreg
, dreg
, AT
);
4516 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4517 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4520 ? mips_opts
.warn_about_macros
4522 offset_expr
.X_add_symbol
, (offsetT
) 0,
4530 /* This is needed because this instruction uses $gp, but
4531 the first instruction on the main stream does not. */
4532 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4535 macro_build (p
, &icnt
, &offset_expr
,
4537 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4539 if (expr1
.X_add_number
>= -0x8000
4540 && expr1
.X_add_number
< 0x8000)
4542 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4544 macro_build (p
, &icnt
, &expr1
,
4545 ((bfd_arch_bits_per_address (stdoutput
) == 32
4546 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4547 ? "addiu" : "daddiu"),
4548 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4549 /* FIXME: If add_number is 0, and there was no base
4550 register, the external symbol case ended with a load,
4551 so if the symbol turns out to not be external, and
4552 the next instruction uses tempreg, an unnecessary nop
4553 will be inserted. */
4559 /* We must add in the base register now, as in the
4560 external symbol case. */
4561 assert (tempreg
== AT
);
4562 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4564 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4565 ((bfd_arch_bits_per_address (stdoutput
) == 32
4566 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4567 ? "addu" : "daddu"),
4568 "d,v,t", treg
, AT
, breg
);
4571 /* We set breg to 0 because we have arranged to add
4572 it in in both cases. */
4576 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4578 macro_build (p
, &icnt
, &expr1
,
4579 ((bfd_arch_bits_per_address (stdoutput
) == 32
4580 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4581 ? "addiu" : "daddiu"),
4582 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4584 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4585 ((bfd_arch_bits_per_address (stdoutput
) == 32
4586 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4587 ? "addu" : "daddu"),
4588 "d,v,t", tempreg
, tempreg
, AT
);
4592 else if (mips_pic
== EMBEDDED_PIC
)
4595 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4597 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4598 ((bfd_arch_bits_per_address (stdoutput
) == 32
4599 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4600 ? "addiu" : "daddiu"),
4601 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4608 ((bfd_arch_bits_per_address (stdoutput
) == 32
4609 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4610 ? "addu" : "daddu"),
4611 "d,v,t", treg
, tempreg
, breg
);
4619 /* The j instruction may not be used in PIC code, since it
4620 requires an absolute address. We convert it to a b
4622 if (mips_pic
== NO_PIC
)
4623 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4625 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4628 /* The jal instructions must be handled as macros because when
4629 generating PIC code they expand to multi-instruction
4630 sequences. Normally they are simple instructions. */
4635 if (mips_pic
== NO_PIC
4636 || mips_pic
== EMBEDDED_PIC
)
4637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4639 else if (mips_pic
== SVR4_PIC
)
4641 if (sreg
!= PIC_CALL_REG
)
4642 as_warn (_("MIPS PIC call to register other than $25"));
4644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4646 if (mips_cprestore_offset
< 0)
4647 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4650 expr1
.X_add_number
= mips_cprestore_offset
;
4651 macro_build ((char *) NULL
, &icnt
, &expr1
,
4652 ((bfd_arch_bits_per_address (stdoutput
) == 32
4653 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4655 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4664 if (mips_pic
== NO_PIC
)
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4666 else if (mips_pic
== SVR4_PIC
)
4668 /* If this is a reference to an external symbol, and we are
4669 using a small GOT, we want
4670 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4674 lw $gp,cprestore($sp)
4675 The cprestore value is set using the .cprestore
4676 pseudo-op. If we are using a big GOT, we want
4677 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4679 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4683 lw $gp,cprestore($sp)
4684 If the symbol is not external, we want
4685 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4687 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4690 lw $gp,cprestore($sp) */
4694 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4695 ((bfd_arch_bits_per_address (stdoutput
) == 32
4696 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4698 "t,o(b)", PIC_CALL_REG
,
4699 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4700 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4702 p
= frag_var (rs_machine_dependent
, 4, 0,
4703 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4704 offset_expr
.X_add_symbol
, (offsetT
) 0,
4711 if (reg_needs_delay (GP
))
4715 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4716 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4718 ((bfd_arch_bits_per_address (stdoutput
) == 32
4719 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4720 ? "addu" : "daddu"),
4721 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4722 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4723 ((bfd_arch_bits_per_address (stdoutput
) == 32
4724 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4726 "t,o(b)", PIC_CALL_REG
,
4727 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4730 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4731 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4733 offset_expr
.X_add_symbol
, (offsetT
) 0,
4737 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4740 macro_build (p
, &icnt
, &offset_expr
,
4741 ((bfd_arch_bits_per_address (stdoutput
) == 32
4742 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4744 "t,o(b)", PIC_CALL_REG
,
4745 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4747 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4750 macro_build (p
, &icnt
, &offset_expr
,
4751 ((bfd_arch_bits_per_address (stdoutput
) == 32
4752 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4753 ? "addiu" : "daddiu"),
4754 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4755 (int) BFD_RELOC_LO16
);
4756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4757 "jalr", "s", PIC_CALL_REG
);
4758 if (mips_cprestore_offset
< 0)
4759 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4762 if (mips_opts
.noreorder
)
4763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4765 expr1
.X_add_number
= mips_cprestore_offset
;
4766 macro_build ((char *) NULL
, &icnt
, &expr1
,
4767 ((bfd_arch_bits_per_address (stdoutput
) == 32
4768 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4770 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4774 else if (mips_pic
== EMBEDDED_PIC
)
4776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4777 /* The linker may expand the call to a longer sequence which
4778 uses $at, so we must break rather than return. */
4803 /* Itbl support may require additional care here. */
4808 /* Itbl support may require additional care here. */
4813 /* Itbl support may require additional care here. */
4818 /* Itbl support may require additional care here. */
4830 if (mips_cpu
== CPU_R4650
)
4832 as_bad (_("opcode not supported on this processor"));
4836 /* Itbl support may require additional care here. */
4841 /* Itbl support may require additional care here. */
4846 /* Itbl support may require additional care here. */
4866 if (breg
== treg
|| coproc
|| lr
)
4888 /* Itbl support may require additional care here. */
4893 /* Itbl support may require additional care here. */
4898 /* Itbl support may require additional care here. */
4903 /* Itbl support may require additional care here. */
4919 if (mips_cpu
== CPU_R4650
)
4921 as_bad (_("opcode not supported on this processor"));
4926 /* Itbl support may require additional care here. */
4930 /* Itbl support may require additional care here. */
4935 /* Itbl support may require additional care here. */
4947 /* Itbl support may require additional care here. */
4948 if (mask
== M_LWC1_AB
4949 || mask
== M_SWC1_AB
4950 || mask
== M_LDC1_AB
4951 || mask
== M_SDC1_AB
4960 if (offset_expr
.X_op
!= O_constant
4961 && offset_expr
.X_op
!= O_symbol
)
4963 as_bad (_("expression too complex"));
4964 offset_expr
.X_op
= O_constant
;
4967 /* A constant expression in PIC code can be handled just as it
4968 is in non PIC code. */
4969 if (mips_pic
== NO_PIC
4970 || offset_expr
.X_op
== O_constant
)
4972 /* If this is a reference to a GP relative symbol, and there
4973 is no base register, we want
4974 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4975 Otherwise, if there is no base register, we want
4976 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4977 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4978 If we have a constant, we need two instructions anyhow,
4979 so we always use the latter form.
4981 If we have a base register, and this is a reference to a
4982 GP relative symbol, we want
4983 addu $tempreg,$breg,$gp
4984 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4986 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4987 addu $tempreg,$tempreg,$breg
4988 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4989 With a constant we always use the latter case. */
4992 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4993 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4998 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4999 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5000 p
= frag_var (rs_machine_dependent
, 8, 0,
5001 RELAX_ENCODE (4, 8, 0, 4, 0,
5002 (mips_opts
.warn_about_macros
5004 && mips_opts
.noat
))),
5005 offset_expr
.X_add_symbol
, (offsetT
) 0,
5009 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5012 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5013 (int) BFD_RELOC_LO16
, tempreg
);
5017 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5018 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5024 ((bfd_arch_bits_per_address (stdoutput
) == 32
5025 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5026 ? "addu" : "daddu"),
5027 "d,v,t", tempreg
, breg
, GP
);
5028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5029 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5030 p
= frag_var (rs_machine_dependent
, 12, 0,
5031 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5032 offset_expr
.X_add_symbol
, (offsetT
) 0,
5035 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5038 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5039 ((bfd_arch_bits_per_address (stdoutput
) == 32
5040 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5041 ? "addu" : "daddu"),
5042 "d,v,t", tempreg
, tempreg
, breg
);
5045 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5046 (int) BFD_RELOC_LO16
, tempreg
);
5049 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5051 /* If this is a reference to an external symbol, we want
5052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5054 <op> $treg,0($tempreg)
5056 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5058 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5059 <op> $treg,0($tempreg)
5060 If there is a base register, we add it to $tempreg before
5061 the <op>. If there is a constant, we stick it in the
5062 <op> instruction. We don't handle constants larger than
5063 16 bits, because we have no way to load the upper 16 bits
5064 (actually, we could handle them for the subset of cases
5065 in which we are not using $at). */
5066 assert (offset_expr
.X_op
== O_symbol
);
5067 expr1
.X_add_number
= offset_expr
.X_add_number
;
5068 offset_expr
.X_add_number
= 0;
5069 if (expr1
.X_add_number
< -0x8000
5070 || expr1
.X_add_number
>= 0x8000)
5071 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5073 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5074 ((bfd_arch_bits_per_address (stdoutput
) == 32
5075 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5077 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5079 p
= frag_var (rs_machine_dependent
, 4, 0,
5080 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5081 offset_expr
.X_add_symbol
, (offsetT
) 0,
5083 macro_build (p
, &icnt
, &offset_expr
,
5084 ((bfd_arch_bits_per_address (stdoutput
) == 32
5085 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5086 ? "addiu" : "daddiu"),
5087 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5089 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5090 ((bfd_arch_bits_per_address (stdoutput
) == 32
5091 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5092 ? "addu" : "daddu"),
5093 "d,v,t", tempreg
, tempreg
, breg
);
5094 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5095 (int) BFD_RELOC_LO16
, tempreg
);
5097 else if (mips_pic
== SVR4_PIC
)
5101 /* If this is a reference to an external symbol, we want
5102 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5103 addu $tempreg,$tempreg,$gp
5104 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5105 <op> $treg,0($tempreg)
5107 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5109 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5110 <op> $treg,0($tempreg)
5111 If there is a base register, we add it to $tempreg before
5112 the <op>. If there is a constant, we stick it in the
5113 <op> instruction. We don't handle constants larger than
5114 16 bits, because we have no way to load the upper 16 bits
5115 (actually, we could handle them for the subset of cases
5116 in which we are not using $at). */
5117 assert (offset_expr
.X_op
== O_symbol
);
5118 expr1
.X_add_number
= offset_expr
.X_add_number
;
5119 offset_expr
.X_add_number
= 0;
5120 if (expr1
.X_add_number
< -0x8000
5121 || expr1
.X_add_number
>= 0x8000)
5122 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5123 if (reg_needs_delay (GP
))
5128 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5129 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5131 ((bfd_arch_bits_per_address (stdoutput
) == 32
5132 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5133 ? "addu" : "daddu"),
5134 "d,v,t", tempreg
, tempreg
, GP
);
5135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5136 ((bfd_arch_bits_per_address (stdoutput
) == 32
5137 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5139 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5141 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5142 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5143 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5146 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5149 macro_build (p
, &icnt
, &offset_expr
,
5150 ((bfd_arch_bits_per_address (stdoutput
) == 32
5151 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5153 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5155 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5157 macro_build (p
, &icnt
, &offset_expr
,
5158 ((bfd_arch_bits_per_address (stdoutput
) == 32
5159 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5160 ? "addiu" : "daddiu"),
5161 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5163 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5164 ((bfd_arch_bits_per_address (stdoutput
) == 32
5165 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5166 ? "addu" : "daddu"),
5167 "d,v,t", tempreg
, tempreg
, breg
);
5168 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5169 (int) BFD_RELOC_LO16
, tempreg
);
5171 else if (mips_pic
== EMBEDDED_PIC
)
5173 /* If there is no base register, we want
5174 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5175 If there is a base register, we want
5176 addu $tempreg,$breg,$gp
5177 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5179 assert (offset_expr
.X_op
== O_symbol
);
5182 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5183 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5189 ((bfd_arch_bits_per_address (stdoutput
) == 32
5190 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5191 ? "addu" : "daddu"),
5192 "d,v,t", tempreg
, breg
, GP
);
5193 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5194 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5207 load_register (&icnt
, treg
, &imm_expr
, 0);
5211 load_register (&icnt
, treg
, &imm_expr
, 1);
5215 if (imm_expr
.X_op
== O_constant
)
5217 load_register (&icnt
, AT
, &imm_expr
, 0);
5218 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5219 "mtc1", "t,G", AT
, treg
);
5224 assert (offset_expr
.X_op
== O_symbol
5225 && strcmp (segment_name (S_GET_SEGMENT
5226 (offset_expr
.X_add_symbol
)),
5228 && offset_expr
.X_add_number
== 0);
5229 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5230 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5235 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5236 the entire value, and in mips1 mode it is the high order 32
5237 bits of the value and the low order 32 bits are either zero
5238 or in offset_expr. */
5239 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5241 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5242 load_register (&icnt
, treg
, &imm_expr
, 1);
5247 if (target_big_endian
)
5259 load_register (&icnt
, hreg
, &imm_expr
, 0);
5262 if (offset_expr
.X_op
== O_absent
)
5263 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5267 assert (offset_expr
.X_op
== O_constant
);
5268 load_register (&icnt
, lreg
, &offset_expr
, 0);
5275 /* We know that sym is in the .rdata section. First we get the
5276 upper 16 bits of the address. */
5277 if (mips_pic
== NO_PIC
)
5279 /* FIXME: This won't work for a 64 bit address. */
5280 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5282 else if (mips_pic
== SVR4_PIC
)
5284 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5285 ((bfd_arch_bits_per_address (stdoutput
) == 32
5286 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5288 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5290 else if (mips_pic
== EMBEDDED_PIC
)
5292 /* For embedded PIC we pick up the entire address off $gp in
5293 a single instruction. */
5294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5295 ((bfd_arch_bits_per_address (stdoutput
) == 32
5296 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5297 ? "addiu" : "daddiu"),
5298 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5299 offset_expr
.X_op
= O_constant
;
5300 offset_expr
.X_add_number
= 0;
5305 /* Now we load the register(s). */
5306 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5307 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5308 treg
, (int) BFD_RELOC_LO16
, AT
);
5311 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5312 treg
, (int) BFD_RELOC_LO16
, AT
);
5315 /* FIXME: How in the world do we deal with the possible
5317 offset_expr
.X_add_number
+= 4;
5318 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5319 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5323 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5324 does not become a variant frag. */
5325 frag_wane (frag_now
);
5331 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5332 the entire value, and in mips1 mode it is the high order 32
5333 bits of the value and the low order 32 bits are either zero
5334 or in offset_expr. */
5335 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5337 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5338 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5339 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5340 "dmtc1", "t,S", AT
, treg
);
5343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5344 "mtc1", "t,G", AT
, treg
+ 1);
5345 if (offset_expr
.X_op
== O_absent
)
5346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5347 "mtc1", "t,G", 0, treg
);
5350 assert (offset_expr
.X_op
== O_constant
);
5351 load_register (&icnt
, AT
, &offset_expr
, 0);
5352 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5353 "mtc1", "t,G", AT
, treg
);
5359 assert (offset_expr
.X_op
== O_symbol
5360 && offset_expr
.X_add_number
== 0);
5361 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5362 if (strcmp (s
, ".lit8") == 0)
5364 if (mips_opts
.isa
!= ISA_MIPS1
)
5366 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5367 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5371 r
= BFD_RELOC_MIPS_LITERAL
;
5376 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5377 if (mips_pic
== SVR4_PIC
)
5378 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5379 ((bfd_arch_bits_per_address (stdoutput
) == 32
5380 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5382 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5385 /* FIXME: This won't work for a 64 bit address. */
5386 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5389 if (mips_opts
.isa
!= ISA_MIPS1
)
5391 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5392 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5394 /* To avoid confusion in tc_gen_reloc, we must ensure
5395 that this does not become a variant frag. */
5396 frag_wane (frag_now
);
5407 if (mips_cpu
== CPU_R4650
)
5409 as_bad (_("opcode not supported on this processor"));
5412 /* Even on a big endian machine $fn comes before $fn+1. We have
5413 to adjust when loading from memory. */
5416 assert (mips_opts
.isa
== ISA_MIPS1
);
5417 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5418 target_big_endian
? treg
+ 1 : treg
,
5420 /* FIXME: A possible overflow which I don't know how to deal
5422 offset_expr
.X_add_number
+= 4;
5423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5424 target_big_endian
? treg
: treg
+ 1,
5427 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5428 does not become a variant frag. */
5429 frag_wane (frag_now
);
5438 * The MIPS assembler seems to check for X_add_number not
5439 * being double aligned and generating:
5442 * addiu at,at,%lo(foo+1)
5445 * But, the resulting address is the same after relocation so why
5446 * generate the extra instruction?
5448 if (mips_cpu
== CPU_R4650
)
5450 as_bad (_("opcode not supported on this processor"));
5453 /* Itbl support may require additional care here. */
5455 if (mips_opts
.isa
!= ISA_MIPS1
)
5466 if (mips_cpu
== CPU_R4650
)
5468 as_bad (_("opcode not supported on this processor"));
5472 if (mips_opts
.isa
!= ISA_MIPS1
)
5480 /* Itbl support may require additional care here. */
5485 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5496 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5506 if (offset_expr
.X_op
!= O_symbol
5507 && offset_expr
.X_op
!= O_constant
)
5509 as_bad (_("expression too complex"));
5510 offset_expr
.X_op
= O_constant
;
5513 /* Even on a big endian machine $fn comes before $fn+1. We have
5514 to adjust when loading from memory. We set coproc if we must
5515 load $fn+1 first. */
5516 /* Itbl support may require additional care here. */
5517 if (! target_big_endian
)
5520 if (mips_pic
== NO_PIC
5521 || offset_expr
.X_op
== O_constant
)
5523 /* If this is a reference to a GP relative symbol, we want
5524 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5525 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5526 If we have a base register, we use this
5528 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5529 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5530 If this is not a GP relative symbol, we want
5531 lui $at,<sym> (BFD_RELOC_HI16_S)
5532 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5533 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5534 If there is a base register, we add it to $at after the
5535 lui instruction. If there is a constant, we always use
5537 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5538 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5557 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5558 ((bfd_arch_bits_per_address (stdoutput
) == 32
5559 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5560 ? "addu" : "daddu"),
5561 "d,v,t", AT
, breg
, GP
);
5567 /* Itbl support may require additional care here. */
5568 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5569 coproc
? treg
+ 1 : treg
,
5570 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5571 offset_expr
.X_add_number
+= 4;
5573 /* Set mips_optimize to 2 to avoid inserting an
5575 hold_mips_optimize
= mips_optimize
;
5577 /* Itbl support may require additional care here. */
5578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5579 coproc
? treg
: treg
+ 1,
5580 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5581 mips_optimize
= hold_mips_optimize
;
5583 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5584 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5585 used_at
&& mips_opts
.noat
),
5586 offset_expr
.X_add_symbol
, (offsetT
) 0,
5589 /* We just generated two relocs. When tc_gen_reloc
5590 handles this case, it will skip the first reloc and
5591 handle the second. The second reloc already has an
5592 extra addend of 4, which we added above. We must
5593 subtract it out, and then subtract another 4 to make
5594 the first reloc come out right. The second reloc
5595 will come out right because we are going to add 4 to
5596 offset_expr when we build its instruction below.
5598 If we have a symbol, then we don't want to include
5599 the offset, because it will wind up being included
5600 when we generate the reloc. */
5602 if (offset_expr
.X_op
== O_constant
)
5603 offset_expr
.X_add_number
-= 8;
5606 offset_expr
.X_add_number
= -4;
5607 offset_expr
.X_op
= O_constant
;
5610 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5615 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5616 ((bfd_arch_bits_per_address (stdoutput
) == 32
5617 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5618 ? "addu" : "daddu"),
5619 "d,v,t", AT
, breg
, AT
);
5623 /* Itbl support may require additional care here. */
5624 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5625 coproc
? treg
+ 1 : treg
,
5626 (int) BFD_RELOC_LO16
, AT
);
5629 /* FIXME: How do we handle overflow here? */
5630 offset_expr
.X_add_number
+= 4;
5631 /* Itbl support may require additional care here. */
5632 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5633 coproc
? treg
: treg
+ 1,
5634 (int) BFD_RELOC_LO16
, AT
);
5636 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5640 /* If this is a reference to an external symbol, we want
5641 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5646 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5648 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5649 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5650 If there is a base register we add it to $at before the
5651 lwc1 instructions. If there is a constant we include it
5652 in the lwc1 instructions. */
5654 expr1
.X_add_number
= offset_expr
.X_add_number
;
5655 offset_expr
.X_add_number
= 0;
5656 if (expr1
.X_add_number
< -0x8000
5657 || expr1
.X_add_number
>= 0x8000 - 4)
5658 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5663 frag_grow (24 + off
);
5664 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5665 ((bfd_arch_bits_per_address (stdoutput
) == 32
5666 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5668 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5669 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5672 ((bfd_arch_bits_per_address (stdoutput
) == 32
5673 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5674 ? "addu" : "daddu"),
5675 "d,v,t", AT
, breg
, AT
);
5676 /* Itbl support may require additional care here. */
5677 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5678 coproc
? treg
+ 1 : treg
,
5679 (int) BFD_RELOC_LO16
, AT
);
5680 expr1
.X_add_number
+= 4;
5682 /* Set mips_optimize to 2 to avoid inserting an undesired
5684 hold_mips_optimize
= mips_optimize
;
5686 /* Itbl support may require additional care here. */
5687 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5688 coproc
? treg
: treg
+ 1,
5689 (int) BFD_RELOC_LO16
, AT
);
5690 mips_optimize
= hold_mips_optimize
;
5692 (void) frag_var (rs_machine_dependent
, 0, 0,
5693 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5694 offset_expr
.X_add_symbol
, (offsetT
) 0,
5697 else if (mips_pic
== SVR4_PIC
)
5701 /* If this is a reference to an external symbol, we want
5702 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5704 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5709 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5711 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5712 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5713 If there is a base register we add it to $at before the
5714 lwc1 instructions. If there is a constant we include it
5715 in the lwc1 instructions. */
5717 expr1
.X_add_number
= offset_expr
.X_add_number
;
5718 offset_expr
.X_add_number
= 0;
5719 if (expr1
.X_add_number
< -0x8000
5720 || expr1
.X_add_number
>= 0x8000 - 4)
5721 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5722 if (reg_needs_delay (GP
))
5731 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5732 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5733 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5734 ((bfd_arch_bits_per_address (stdoutput
) == 32
5735 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5736 ? "addu" : "daddu"),
5737 "d,v,t", AT
, AT
, GP
);
5738 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5739 ((bfd_arch_bits_per_address (stdoutput
) == 32
5740 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5742 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5743 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5745 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5746 ((bfd_arch_bits_per_address (stdoutput
) == 32
5747 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5748 ? "addu" : "daddu"),
5749 "d,v,t", AT
, breg
, AT
);
5750 /* Itbl support may require additional care here. */
5751 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5752 coproc
? treg
+ 1 : treg
,
5753 (int) BFD_RELOC_LO16
, AT
);
5754 expr1
.X_add_number
+= 4;
5756 /* Set mips_optimize to 2 to avoid inserting an undesired
5758 hold_mips_optimize
= mips_optimize
;
5760 /* Itbl support may require additional care here. */
5761 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5762 coproc
? treg
: treg
+ 1,
5763 (int) BFD_RELOC_LO16
, AT
);
5764 mips_optimize
= hold_mips_optimize
;
5765 expr1
.X_add_number
-= 4;
5767 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5768 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5769 8 + gpdel
+ off
, 1, 0),
5770 offset_expr
.X_add_symbol
, (offsetT
) 0,
5774 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5777 macro_build (p
, &icnt
, &offset_expr
,
5778 ((bfd_arch_bits_per_address (stdoutput
) == 32
5779 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5781 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5783 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5787 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5788 ((bfd_arch_bits_per_address (stdoutput
) == 32
5789 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5790 ? "addu" : "daddu"),
5791 "d,v,t", AT
, breg
, AT
);
5794 /* Itbl support may require additional care here. */
5795 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5796 coproc
? treg
+ 1 : treg
,
5797 (int) BFD_RELOC_LO16
, AT
);
5799 expr1
.X_add_number
+= 4;
5801 /* Set mips_optimize to 2 to avoid inserting an undesired
5803 hold_mips_optimize
= mips_optimize
;
5805 /* Itbl support may require additional care here. */
5806 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5807 coproc
? treg
: treg
+ 1,
5808 (int) BFD_RELOC_LO16
, AT
);
5809 mips_optimize
= hold_mips_optimize
;
5811 else if (mips_pic
== EMBEDDED_PIC
)
5813 /* If there is no base register, we use
5814 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5815 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5816 If we have a base register, we use
5818 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5819 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5828 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5829 ((bfd_arch_bits_per_address (stdoutput
) == 32
5830 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5831 ? "addu" : "daddu"),
5832 "d,v,t", AT
, breg
, GP
);
5837 /* Itbl support may require additional care here. */
5838 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5839 coproc
? treg
+ 1 : treg
,
5840 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5841 offset_expr
.X_add_number
+= 4;
5842 /* Itbl support may require additional care here. */
5843 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5844 coproc
? treg
: treg
+ 1,
5845 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5861 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5862 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5863 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5864 (int) BFD_RELOC_LO16
, breg
);
5865 offset_expr
.X_add_number
+= 4;
5866 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5867 (int) BFD_RELOC_LO16
, breg
);
5870 /* New code added to support COPZ instructions.
5871 This code builds table entries out of the macros in mip_opcodes.
5872 R4000 uses interlocks to handle coproc delays.
5873 Other chips (like the R3000) require nops to be inserted for delays.
5875 FIXME: Currently, we require that the user handle delays.
5876 In order to fill delay slots for non-interlocked chips,
5877 we must have a way to specify delays based on the coprocessor.
5878 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5879 What are the side-effects of the cop instruction?
5880 What cache support might we have and what are its effects?
5881 Both coprocessor & memory require delays. how long???
5882 What registers are read/set/modified?
5884 If an itbl is provided to interpret cop instructions,
5885 this knowledge can be encoded in the itbl spec. */
5899 /* For now we just do C (same as Cz). The parameter will be
5900 stored in insn_opcode by mips_ip. */
5901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5905 #ifdef LOSING_COMPILER
5907 /* Try and see if this is a new itbl instruction.
5908 This code builds table entries out of the macros in mip_opcodes.
5909 FIXME: For now we just assemble the expression and pass it's
5910 value along as a 32-bit immediate.
5911 We may want to have the assembler assemble this value,
5912 so that we gain the assembler's knowledge of delay slots,
5914 Would it be more efficient to use mask (id) here? */
5915 if (itbl_have_entries
5916 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5918 s
= ip
->insn_mo
->name
;
5920 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5921 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5928 as_warn (_("Macro used $at after \".set noat\""));
5933 struct mips_cl_insn
*ip
;
5935 register int treg
, sreg
, dreg
, breg
;
5951 bfd_reloc_code_real_type r
;
5954 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5955 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5956 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5957 mask
= ip
->insn_mo
->mask
;
5959 expr1
.X_op
= O_constant
;
5960 expr1
.X_op_symbol
= NULL
;
5961 expr1
.X_add_symbol
= NULL
;
5962 expr1
.X_add_number
= 1;
5966 #endif /* LOSING_COMPILER */
5971 macro_build ((char *) NULL
, &icnt
, NULL
,
5972 dbl
? "dmultu" : "multu",
5974 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5980 /* The MIPS assembler some times generates shifts and adds. I'm
5981 not trying to be that fancy. GCC should do this for us
5983 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5984 macro_build ((char *) NULL
, &icnt
, NULL
,
5985 dbl
? "dmult" : "mult",
5987 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6000 mips_emit_delays (true);
6001 ++mips_opts
.noreorder
;
6002 mips_any_noreorder
= 1;
6004 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6005 macro_build ((char *) NULL
, &icnt
, NULL
,
6006 dbl
? "dmult" : "mult",
6007 "s,t", sreg
, imm
? AT
: treg
);
6008 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6009 macro_build ((char *) NULL
, &icnt
, NULL
,
6010 dbl
? "dsra32" : "sra",
6011 "d,w,<", dreg
, dreg
, 31);
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6014 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6017 expr1
.X_add_number
= 8;
6018 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6022 --mips_opts
.noreorder
;
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6036 mips_emit_delays (true);
6037 ++mips_opts
.noreorder
;
6038 mips_any_noreorder
= 1;
6040 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6041 macro_build ((char *) NULL
, &icnt
, NULL
,
6042 dbl
? "dmultu" : "multu",
6043 "s,t", sreg
, imm
? AT
: treg
);
6044 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6045 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6047 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6050 expr1
.X_add_number
= 8;
6051 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6052 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6053 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6055 --mips_opts
.noreorder
;
6059 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6060 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6061 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6067 if (imm_expr
.X_op
!= O_constant
)
6068 as_bad (_("rotate count too large"));
6069 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6070 (int) (imm_expr
.X_add_number
& 0x1f));
6071 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6072 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6073 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6078 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6079 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6085 if (imm_expr
.X_op
!= O_constant
)
6086 as_bad (_("rotate count too large"));
6087 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6088 (int) (imm_expr
.X_add_number
& 0x1f));
6089 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6090 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6095 if (mips_cpu
== CPU_R4650
)
6097 as_bad (_("opcode not supported on this processor"));
6100 assert (mips_opts
.isa
== ISA_MIPS1
);
6101 /* Even on a big endian machine $fn comes before $fn+1. We have
6102 to adjust when storing to memory. */
6103 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6104 target_big_endian
? treg
+ 1 : treg
,
6105 (int) BFD_RELOC_LO16
, breg
);
6106 offset_expr
.X_add_number
+= 4;
6107 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6108 target_big_endian
? treg
: treg
+ 1,
6109 (int) BFD_RELOC_LO16
, breg
);
6114 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6115 treg
, (int) BFD_RELOC_LO16
);
6117 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6118 sreg
, (int) BFD_RELOC_LO16
);
6121 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6123 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6124 dreg
, (int) BFD_RELOC_LO16
);
6129 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6131 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6132 sreg
, (int) BFD_RELOC_LO16
);
6137 as_warn (_("Instruction %s: result is always false"),
6139 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6142 if (imm_expr
.X_op
== O_constant
6143 && imm_expr
.X_add_number
>= 0
6144 && imm_expr
.X_add_number
< 0x10000)
6146 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6147 sreg
, (int) BFD_RELOC_LO16
);
6150 else if (imm_expr
.X_op
== O_constant
6151 && imm_expr
.X_add_number
> -0x8000
6152 && imm_expr
.X_add_number
< 0)
6154 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6155 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6156 ((bfd_arch_bits_per_address (stdoutput
) == 32
6157 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6158 ? "addiu" : "daddiu"),
6159 "t,r,j", dreg
, sreg
,
6160 (int) BFD_RELOC_LO16
);
6165 load_register (&icnt
, AT
, &imm_expr
, 0);
6166 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6170 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6171 (int) BFD_RELOC_LO16
);
6176 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6182 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6183 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6184 (int) BFD_RELOC_LO16
);
6187 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6189 if (imm_expr
.X_op
== O_constant
6190 && imm_expr
.X_add_number
>= -0x8000
6191 && imm_expr
.X_add_number
< 0x8000)
6193 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6194 mask
== M_SGE_I
? "slti" : "sltiu",
6195 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6200 load_register (&icnt
, AT
, &imm_expr
, 0);
6201 macro_build ((char *) NULL
, &icnt
, NULL
,
6202 mask
== M_SGE_I
? "slt" : "sltu",
6203 "d,v,t", dreg
, sreg
, AT
);
6206 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6207 (int) BFD_RELOC_LO16
);
6212 case M_SGT
: /* sreg > treg <==> treg < sreg */
6218 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6221 case M_SGT_I
: /* sreg > I <==> I < sreg */
6227 load_register (&icnt
, AT
, &imm_expr
, 0);
6228 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6231 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6237 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6238 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6239 (int) BFD_RELOC_LO16
);
6242 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6248 load_register (&icnt
, AT
, &imm_expr
, 0);
6249 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6250 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6251 (int) BFD_RELOC_LO16
);
6255 if (imm_expr
.X_op
== O_constant
6256 && imm_expr
.X_add_number
>= -0x8000
6257 && imm_expr
.X_add_number
< 0x8000)
6259 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6260 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6263 load_register (&icnt
, AT
, &imm_expr
, 0);
6264 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6268 if (imm_expr
.X_op
== O_constant
6269 && imm_expr
.X_add_number
>= -0x8000
6270 && imm_expr
.X_add_number
< 0x8000)
6272 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6273 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6276 load_register (&icnt
, AT
, &imm_expr
, 0);
6277 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6283 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6286 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6290 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6292 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6298 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6300 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6306 as_warn (_("Instruction %s: result is always true"),
6308 macro_build ((char *) NULL
, &icnt
, &expr1
,
6309 ((bfd_arch_bits_per_address (stdoutput
) == 32
6310 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6311 ? "addiu" : "daddiu"),
6312 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6315 if (imm_expr
.X_op
== O_constant
6316 && imm_expr
.X_add_number
>= 0
6317 && imm_expr
.X_add_number
< 0x10000)
6319 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6320 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6323 else if (imm_expr
.X_op
== O_constant
6324 && imm_expr
.X_add_number
> -0x8000
6325 && imm_expr
.X_add_number
< 0)
6327 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6328 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6329 ((bfd_arch_bits_per_address (stdoutput
) == 32
6330 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6331 ? "addiu" : "daddiu"),
6332 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6337 load_register (&icnt
, AT
, &imm_expr
, 0);
6338 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6342 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6350 if (imm_expr
.X_op
== O_constant
6351 && imm_expr
.X_add_number
> -0x8000
6352 && imm_expr
.X_add_number
<= 0x8000)
6354 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6355 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6356 dbl
? "daddi" : "addi",
6357 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6360 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6361 macro_build ((char *) NULL
, &icnt
, NULL
,
6362 dbl
? "dsub" : "sub",
6363 "d,v,t", dreg
, sreg
, AT
);
6369 if (imm_expr
.X_op
== O_constant
6370 && imm_expr
.X_add_number
> -0x8000
6371 && imm_expr
.X_add_number
<= 0x8000)
6373 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6374 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6375 dbl
? "daddiu" : "addiu",
6376 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6379 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6380 macro_build ((char *) NULL
, &icnt
, NULL
,
6381 dbl
? "dsubu" : "subu",
6382 "d,v,t", dreg
, sreg
, AT
);
6403 load_register (&icnt
, AT
, &imm_expr
, 0);
6404 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6409 assert (mips_opts
.isa
== ISA_MIPS1
);
6410 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6411 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6414 * Is the double cfc1 instruction a bug in the mips assembler;
6415 * or is there a reason for it?
6417 mips_emit_delays (true);
6418 ++mips_opts
.noreorder
;
6419 mips_any_noreorder
= 1;
6420 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6421 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6422 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6423 expr1
.X_add_number
= 3;
6424 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6425 (int) BFD_RELOC_LO16
);
6426 expr1
.X_add_number
= 2;
6427 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6428 (int) BFD_RELOC_LO16
);
6429 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6430 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6431 macro_build ((char *) NULL
, &icnt
, NULL
,
6432 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6433 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6434 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6435 --mips_opts
.noreorder
;
6444 if (offset_expr
.X_add_number
>= 0x7fff)
6445 as_bad (_("operand overflow"));
6446 /* avoid load delay */
6447 if (! target_big_endian
)
6448 offset_expr
.X_add_number
+= 1;
6449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6450 (int) BFD_RELOC_LO16
, breg
);
6451 if (! target_big_endian
)
6452 offset_expr
.X_add_number
-= 1;
6454 offset_expr
.X_add_number
+= 1;
6455 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6456 (int) BFD_RELOC_LO16
, breg
);
6457 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6458 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6471 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6472 as_bad (_("operand overflow"));
6473 if (! target_big_endian
)
6474 offset_expr
.X_add_number
+= off
;
6475 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6476 (int) BFD_RELOC_LO16
, breg
);
6477 if (! target_big_endian
)
6478 offset_expr
.X_add_number
-= off
;
6480 offset_expr
.X_add_number
+= off
;
6481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6482 (int) BFD_RELOC_LO16
, breg
);
6495 load_address (&icnt
, AT
, &offset_expr
);
6497 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6498 ((bfd_arch_bits_per_address (stdoutput
) == 32
6499 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6500 ? "addu" : "daddu"),
6501 "d,v,t", AT
, AT
, breg
);
6502 if (! target_big_endian
)
6503 expr1
.X_add_number
= off
;
6505 expr1
.X_add_number
= 0;
6506 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6507 (int) BFD_RELOC_LO16
, AT
);
6508 if (! target_big_endian
)
6509 expr1
.X_add_number
= 0;
6511 expr1
.X_add_number
= off
;
6512 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6513 (int) BFD_RELOC_LO16
, AT
);
6518 load_address (&icnt
, AT
, &offset_expr
);
6520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6521 ((bfd_arch_bits_per_address (stdoutput
) == 32
6522 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6523 ? "addu" : "daddu"),
6524 "d,v,t", AT
, AT
, breg
);
6525 if (target_big_endian
)
6526 expr1
.X_add_number
= 0;
6527 macro_build ((char *) NULL
, &icnt
, &expr1
,
6528 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6529 (int) BFD_RELOC_LO16
, AT
);
6530 if (target_big_endian
)
6531 expr1
.X_add_number
= 1;
6533 expr1
.X_add_number
= 0;
6534 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6535 (int) BFD_RELOC_LO16
, AT
);
6536 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6538 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6543 if (offset_expr
.X_add_number
>= 0x7fff)
6544 as_bad (_("operand overflow"));
6545 if (target_big_endian
)
6546 offset_expr
.X_add_number
+= 1;
6547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6548 (int) BFD_RELOC_LO16
, breg
);
6549 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6550 if (target_big_endian
)
6551 offset_expr
.X_add_number
-= 1;
6553 offset_expr
.X_add_number
+= 1;
6554 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6555 (int) BFD_RELOC_LO16
, breg
);
6568 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6569 as_bad (_("operand overflow"));
6570 if (! target_big_endian
)
6571 offset_expr
.X_add_number
+= off
;
6572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6573 (int) BFD_RELOC_LO16
, breg
);
6574 if (! target_big_endian
)
6575 offset_expr
.X_add_number
-= off
;
6577 offset_expr
.X_add_number
+= off
;
6578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6579 (int) BFD_RELOC_LO16
, breg
);
6592 load_address (&icnt
, AT
, &offset_expr
);
6594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6595 ((bfd_arch_bits_per_address (stdoutput
) == 32
6596 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6597 ? "addu" : "daddu"),
6598 "d,v,t", AT
, AT
, breg
);
6599 if (! target_big_endian
)
6600 expr1
.X_add_number
= off
;
6602 expr1
.X_add_number
= 0;
6603 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6604 (int) BFD_RELOC_LO16
, AT
);
6605 if (! target_big_endian
)
6606 expr1
.X_add_number
= 0;
6608 expr1
.X_add_number
= off
;
6609 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6610 (int) BFD_RELOC_LO16
, AT
);
6614 load_address (&icnt
, AT
, &offset_expr
);
6616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6617 ((bfd_arch_bits_per_address (stdoutput
) == 32
6618 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6619 ? "addu" : "daddu"),
6620 "d,v,t", AT
, AT
, breg
);
6621 if (! target_big_endian
)
6622 expr1
.X_add_number
= 0;
6623 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6624 (int) BFD_RELOC_LO16
, AT
);
6625 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6627 if (! target_big_endian
)
6628 expr1
.X_add_number
= 1;
6630 expr1
.X_add_number
= 0;
6631 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6632 (int) BFD_RELOC_LO16
, AT
);
6633 if (! target_big_endian
)
6634 expr1
.X_add_number
= 0;
6636 expr1
.X_add_number
= 1;
6637 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6638 (int) BFD_RELOC_LO16
, AT
);
6639 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6641 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6646 /* FIXME: Check if this is one of the itbl macros, since they
6647 are added dynamically. */
6648 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6652 as_warn (_("Macro used $at after \".set noat\""));
6655 /* Implement macros in mips16 mode. */
6659 struct mips_cl_insn
*ip
;
6662 int xreg
, yreg
, zreg
, tmp
;
6666 const char *s
, *s2
, *s3
;
6668 mask
= ip
->insn_mo
->mask
;
6670 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6671 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6672 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6676 expr1
.X_op
= O_constant
;
6677 expr1
.X_op_symbol
= NULL
;
6678 expr1
.X_add_symbol
= NULL
;
6679 expr1
.X_add_number
= 1;
6698 mips_emit_delays (true);
6699 ++mips_opts
.noreorder
;
6700 mips_any_noreorder
= 1;
6701 macro_build ((char *) NULL
, &icnt
, NULL
,
6702 dbl
? "ddiv" : "div",
6703 "0,x,y", xreg
, yreg
);
6704 expr1
.X_add_number
= 2;
6705 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6706 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6708 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6709 since that causes an overflow. We should do that as well,
6710 but I don't see how to do the comparisons without a temporary
6712 --mips_opts
.noreorder
;
6713 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6732 mips_emit_delays (true);
6733 ++mips_opts
.noreorder
;
6734 mips_any_noreorder
= 1;
6735 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6736 expr1
.X_add_number
= 2;
6737 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6738 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6739 --mips_opts
.noreorder
;
6740 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6746 macro_build ((char *) NULL
, &icnt
, NULL
,
6747 dbl
? "dmultu" : "multu",
6749 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6757 if (imm_expr
.X_op
!= O_constant
)
6758 as_bad (_("Unsupported large constant"));
6759 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6760 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6761 dbl
? "daddiu" : "addiu",
6762 "y,x,4", yreg
, xreg
);
6766 if (imm_expr
.X_op
!= O_constant
)
6767 as_bad (_("Unsupported large constant"));
6768 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6769 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6774 if (imm_expr
.X_op
!= O_constant
)
6775 as_bad (_("Unsupported large constant"));
6776 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6777 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6800 goto do_reverse_branch
;
6804 goto do_reverse_branch
;
6816 goto do_reverse_branch
;
6827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6829 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6856 goto do_addone_branch_i
;
6861 goto do_addone_branch_i
;
6876 goto do_addone_branch_i
;
6883 if (imm_expr
.X_op
!= O_constant
)
6884 as_bad (_("Unsupported large constant"));
6885 ++imm_expr
.X_add_number
;
6888 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6889 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6893 expr1
.X_add_number
= 0;
6894 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6897 "move", "y,X", xreg
, yreg
);
6898 expr1
.X_add_number
= 2;
6899 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6901 "neg", "x,w", xreg
, xreg
);
6905 /* For consistency checking, verify that all bits are specified either
6906 by the match/mask part of the instruction definition, or by the
6909 validate_mips_insn (opc
)
6910 const struct mips_opcode
*opc
;
6912 const char *p
= opc
->args
;
6914 unsigned long used_bits
= opc
->mask
;
6916 if ((used_bits
& opc
->match
) != opc
->match
)
6918 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6919 opc
->name
, opc
->args
);
6922 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6929 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6930 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6932 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6933 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6934 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6935 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6937 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6938 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6940 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6942 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6943 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6944 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6945 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6946 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6947 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6948 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6949 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6950 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6951 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6952 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6954 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6955 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6956 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6957 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6959 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6960 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6961 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6962 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6963 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6964 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6965 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6966 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6967 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6970 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6971 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6972 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6974 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6975 c
, opc
->name
, opc
->args
);
6979 if (used_bits
!= 0xffffffff)
6981 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6982 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6988 /* This routine assembles an instruction into its binary format. As a
6989 side effect, it sets one of the global variables imm_reloc or
6990 offset_reloc to the type of relocation to do if one of the operands
6991 is an address expression. */
6996 struct mips_cl_insn
*ip
;
7001 struct mips_opcode
*insn
;
7004 unsigned int lastregno
= 0;
7007 int full_opcode_match
= 1;
7011 /* If the instruction contains a '.', we first try to match an instruction
7012 including the '.'. Then we try again without the '.'. */
7014 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7017 /* If we stopped on whitespace, then replace the whitespace with null for
7018 the call to hash_find. Save the character we replaced just in case we
7019 have to re-parse the instruction. */
7020 if (isspace ((unsigned char) *s
))
7026 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7028 /* If we didn't find the instruction in the opcode table, try again, but
7029 this time with just the instruction up to, but not including the
7033 /* Restore the character we overwrite above (if any). */
7037 /* Scan up to the first '.' or whitespace. */
7038 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7041 /* If we did not find a '.', then we can quit now. */
7044 insn_error
= "unrecognized opcode";
7048 /* Lookup the instruction in the hash table. */
7050 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7052 insn_error
= "unrecognized opcode";
7056 full_opcode_match
= 0;
7064 assert (strcmp (insn
->name
, str
) == 0);
7066 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7071 if (insn
->pinfo
!= INSN_MACRO
)
7073 if (mips_cpu
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7079 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7080 && strcmp (insn
->name
, insn
[1].name
) == 0)
7087 static char buf
[100];
7089 _("opcode not supported on this processor: %s (%s)"),
7090 mips_cpu_to_str (mips_cpu
),
7091 mips_isa_to_str (mips_opts
.isa
));
7099 ip
->insn_opcode
= insn
->match
;
7100 for (args
= insn
->args
;; ++args
)
7106 case '\0': /* end of args */
7119 ip
->insn_opcode
|= lastregno
<< 21;
7124 ip
->insn_opcode
|= lastregno
<< 16;
7128 ip
->insn_opcode
|= lastregno
<< 11;
7134 /* Handle optional base register.
7135 Either the base register is omitted or
7136 we must have a left paren. */
7137 /* This is dependent on the next operand specifier
7138 is a base register specification. */
7139 assert (args
[1] == 'b' || args
[1] == '5'
7140 || args
[1] == '-' || args
[1] == '4');
7144 case ')': /* these must match exactly */
7149 case '<': /* must be at least one digit */
7151 * According to the manual, if the shift amount is greater
7152 * than 31 or less than 0 the the shift amount should be
7153 * mod 32. In reality the mips assembler issues an error.
7154 * We issue a warning and mask out all but the low 5 bits.
7156 my_getExpression (&imm_expr
, s
);
7157 check_absolute_expr (ip
, &imm_expr
);
7158 if ((unsigned long) imm_expr
.X_add_number
> 31)
7160 as_warn (_("Improper shift amount (%ld)"),
7161 (long) imm_expr
.X_add_number
);
7162 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7164 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7165 imm_expr
.X_op
= O_absent
;
7169 case '>': /* shift amount minus 32 */
7170 my_getExpression (&imm_expr
, s
);
7171 check_absolute_expr (ip
, &imm_expr
);
7172 if ((unsigned long) imm_expr
.X_add_number
< 32
7173 || (unsigned long) imm_expr
.X_add_number
> 63)
7175 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7176 imm_expr
.X_op
= O_absent
;
7180 case 'k': /* cache code */
7181 case 'h': /* prefx code */
7182 my_getExpression (&imm_expr
, s
);
7183 check_absolute_expr (ip
, &imm_expr
);
7184 if ((unsigned long) imm_expr
.X_add_number
> 31)
7186 as_warn (_("Invalid value for `%s' (%lu)"),
7188 (unsigned long) imm_expr
.X_add_number
);
7189 imm_expr
.X_add_number
&= 0x1f;
7192 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7194 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7195 imm_expr
.X_op
= O_absent
;
7199 case 'c': /* break code */
7200 my_getExpression (&imm_expr
, s
);
7201 check_absolute_expr (ip
, &imm_expr
);
7202 if ((unsigned) imm_expr
.X_add_number
> 1023)
7204 as_warn (_("Illegal break code (%ld)"),
7205 (long) imm_expr
.X_add_number
);
7206 imm_expr
.X_add_number
&= 0x3ff;
7208 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7209 imm_expr
.X_op
= O_absent
;
7213 case 'q': /* lower break code */
7214 my_getExpression (&imm_expr
, s
);
7215 check_absolute_expr (ip
, &imm_expr
);
7216 if ((unsigned) imm_expr
.X_add_number
> 1023)
7218 as_warn (_("Illegal lower break code (%ld)"),
7219 (long) imm_expr
.X_add_number
);
7220 imm_expr
.X_add_number
&= 0x3ff;
7222 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7223 imm_expr
.X_op
= O_absent
;
7227 case 'B': /* 20-bit syscall/break code. */
7228 my_getExpression (&imm_expr
, s
);
7229 check_absolute_expr (ip
, &imm_expr
);
7230 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7231 as_warn (_("Illegal 20-bit code (%ld)"),
7232 (long) imm_expr
.X_add_number
);
7233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7234 imm_expr
.X_op
= O_absent
;
7238 case 'C': /* Coprocessor code */
7239 my_getExpression (&imm_expr
, s
);
7240 check_absolute_expr (ip
, &imm_expr
);
7241 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7243 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7244 (long) imm_expr
.X_add_number
);
7245 imm_expr
.X_add_number
&= ((1<<25) - 1);
7247 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7248 imm_expr
.X_op
= O_absent
;
7252 case 'J': /* 19-bit wait code. */
7253 my_getExpression (&imm_expr
, s
);
7254 check_absolute_expr (ip
, &imm_expr
);
7255 if ((unsigned) imm_expr
.X_add_number
> 0x7ffff)
7256 as_warn (_("Illegal 19-bit code (%ld)"),
7257 (long) imm_expr
.X_add_number
);
7258 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7259 imm_expr
.X_op
= O_absent
;
7263 case 'P': /* Performance register */
7264 my_getExpression (&imm_expr
, s
);
7265 check_absolute_expr (ip
, &imm_expr
);
7266 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7268 as_warn (_("Invalidate performance regster (%ld)"),
7269 (long) imm_expr
.X_add_number
);
7270 imm_expr
.X_add_number
&= 1;
7272 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7273 imm_expr
.X_op
= O_absent
;
7277 case 'b': /* base register */
7278 case 'd': /* destination register */
7279 case 's': /* source register */
7280 case 't': /* target register */
7281 case 'r': /* both target and source */
7282 case 'v': /* both dest and source */
7283 case 'w': /* both dest and target */
7284 case 'E': /* coprocessor target register */
7285 case 'G': /* coprocessor destination register */
7286 case 'x': /* ignore register name */
7287 case 'z': /* must be zero register */
7288 case 'U': /* destination register (clo/clz). */
7293 if (isdigit ((unsigned char) s
[1]))
7303 while (isdigit ((unsigned char) *s
));
7305 as_bad (_("Invalid register number (%d)"), regno
);
7307 else if (*args
== 'E' || *args
== 'G')
7311 if (s
[1] == 'f' && s
[2] == 'p')
7316 else if (s
[1] == 's' && s
[2] == 'p')
7321 else if (s
[1] == 'g' && s
[2] == 'p')
7326 else if (s
[1] == 'a' && s
[2] == 't')
7331 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7336 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7341 else if (itbl_have_entries
)
7346 p
= s
+ 1; /* advance past '$' */
7347 n
= itbl_get_field (&p
); /* n is name */
7349 /* See if this is a register defined in an
7351 if (itbl_get_reg_val (n
, &r
))
7353 /* Get_field advances to the start of
7354 the next field, so we need to back
7355 rack to the end of the last field. */
7359 s
= strchr (s
, '\0');
7372 as_warn (_("Used $at without \".set noat\""));
7378 if (c
== 'r' || c
== 'v' || c
== 'w')
7385 /* 'z' only matches $0. */
7386 if (c
== 'z' && regno
!= 0)
7389 /* Now that we have assembled one operand, we use the args string
7390 * to figure out where it goes in the instruction. */
7397 ip
->insn_opcode
|= regno
<< 21;
7401 ip
->insn_opcode
|= regno
<< 11;
7404 ip
->insn_opcode
|= regno
<< 11;
7405 ip
->insn_opcode
|= regno
<< 16;
7410 ip
->insn_opcode
|= regno
<< 16;
7413 /* This case exists because on the r3000 trunc
7414 expands into a macro which requires a gp
7415 register. On the r6000 or r4000 it is
7416 assembled into a single instruction which
7417 ignores the register. Thus the insn version
7418 is MIPS_ISA2 and uses 'x', and the macro
7419 version is MIPS_ISA1 and uses 't'. */
7422 /* This case is for the div instruction, which
7423 acts differently if the destination argument
7424 is $0. This only matches $0, and is checked
7425 outside the switch. */
7428 /* Itbl operand; not yet implemented. FIXME ?? */
7430 /* What about all other operands like 'i', which
7431 can be specified in the opcode table? */
7441 ip
->insn_opcode
|= lastregno
<< 21;
7444 ip
->insn_opcode
|= lastregno
<< 16;
7449 case 'D': /* floating point destination register */
7450 case 'S': /* floating point source register */
7451 case 'T': /* floating point target register */
7452 case 'R': /* floating point source register */
7456 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7466 while (isdigit ((unsigned char) *s
));
7469 as_bad (_("Invalid float register number (%d)"), regno
);
7471 if ((regno
& 1) != 0
7472 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7473 && ! (strcmp (str
, "mtc1") == 0
7474 || strcmp (str
, "mfc1") == 0
7475 || strcmp (str
, "lwc1") == 0
7476 || strcmp (str
, "swc1") == 0
7477 || strcmp (str
, "l.s") == 0
7478 || strcmp (str
, "s.s") == 0))
7479 as_warn (_("Float register should be even, was %d"),
7487 if (c
== 'V' || c
== 'W')
7497 ip
->insn_opcode
|= regno
<< 6;
7501 ip
->insn_opcode
|= regno
<< 11;
7505 ip
->insn_opcode
|= regno
<< 16;
7508 ip
->insn_opcode
|= regno
<< 21;
7518 ip
->insn_opcode
|= lastregno
<< 11;
7521 ip
->insn_opcode
|= lastregno
<< 16;
7527 my_getExpression (&imm_expr
, s
);
7528 if (imm_expr
.X_op
!= O_big
7529 && imm_expr
.X_op
!= O_constant
)
7530 insn_error
= _("absolute expression required");
7535 my_getExpression (&offset_expr
, s
);
7536 imm_reloc
= BFD_RELOC_32
;
7548 unsigned char temp
[8];
7550 unsigned int length
;
7555 /* These only appear as the last operand in an
7556 instruction, and every instruction that accepts
7557 them in any variant accepts them in all variants.
7558 This means we don't have to worry about backing out
7559 any changes if the instruction does not match.
7561 The difference between them is the size of the
7562 floating point constant and where it goes. For 'F'
7563 and 'L' the constant is 64 bits; for 'f' and 'l' it
7564 is 32 bits. Where the constant is placed is based
7565 on how the MIPS assembler does things:
7568 f -- immediate value
7571 The .lit4 and .lit8 sections are only used if
7572 permitted by the -G argument.
7574 When generating embedded PIC code, we use the
7575 .lit8 section but not the .lit4 section (we can do
7576 .lit4 inline easily; we need to put .lit8
7577 somewhere in the data segment, and using .lit8
7578 permits the linker to eventually combine identical
7581 f64
= *args
== 'F' || *args
== 'L';
7583 save_in
= input_line_pointer
;
7584 input_line_pointer
= s
;
7585 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7587 s
= input_line_pointer
;
7588 input_line_pointer
= save_in
;
7589 if (err
!= NULL
&& *err
!= '\0')
7591 as_bad (_("Bad floating point constant: %s"), err
);
7592 memset (temp
, '\0', sizeof temp
);
7593 length
= f64
? 8 : 4;
7596 assert (length
== (unsigned) (f64
? 8 : 4));
7600 && (! USE_GLOBAL_POINTER_OPT
7601 || mips_pic
== EMBEDDED_PIC
7602 || g_switch_value
< 4
7603 || (temp
[0] == 0 && temp
[1] == 0)
7604 || (temp
[2] == 0 && temp
[3] == 0))))
7606 imm_expr
.X_op
= O_constant
;
7607 if (! target_big_endian
)
7608 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7610 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7613 && ! mips_disable_float_construction
7614 && ((temp
[0] == 0 && temp
[1] == 0)
7615 || (temp
[2] == 0 && temp
[3] == 0))
7616 && ((temp
[4] == 0 && temp
[5] == 0)
7617 || (temp
[6] == 0 && temp
[7] == 0)))
7619 /* The value is simple enough to load with a
7620 couple of instructions. In mips1 mode, set
7621 imm_expr to the high order 32 bits and
7622 offset_expr to the low order 32 bits.
7623 Otherwise, set imm_expr to the entire 64 bit
7625 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7627 imm_expr
.X_op
= O_constant
;
7628 offset_expr
.X_op
= O_constant
;
7629 if (! target_big_endian
)
7631 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7632 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7636 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7637 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7639 if (offset_expr
.X_add_number
== 0)
7640 offset_expr
.X_op
= O_absent
;
7642 else if (sizeof (imm_expr
.X_add_number
) > 4)
7644 imm_expr
.X_op
= O_constant
;
7645 if (! target_big_endian
)
7646 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7648 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7652 imm_expr
.X_op
= O_big
;
7653 imm_expr
.X_add_number
= 4;
7654 if (! target_big_endian
)
7656 generic_bignum
[0] = bfd_getl16 (temp
);
7657 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7658 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7659 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7663 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7664 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7665 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7666 generic_bignum
[3] = bfd_getb16 (temp
);
7672 const char *newname
;
7675 /* Switch to the right section. */
7677 subseg
= now_subseg
;
7680 default: /* unused default case avoids warnings. */
7682 newname
= RDATA_SECTION_NAME
;
7683 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7684 || mips_pic
== EMBEDDED_PIC
)
7688 if (mips_pic
== EMBEDDED_PIC
)
7691 newname
= RDATA_SECTION_NAME
;
7694 assert (!USE_GLOBAL_POINTER_OPT
7695 || g_switch_value
>= 4);
7699 new_seg
= subseg_new (newname
, (subsegT
) 0);
7700 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7701 bfd_set_section_flags (stdoutput
, new_seg
,
7706 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7707 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7708 && strcmp (TARGET_OS
, "elf") != 0)
7709 record_alignment (new_seg
, 4);
7711 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7713 as_bad (_("Can't use floating point insn in this section"));
7715 /* Set the argument to the current address in the
7717 offset_expr
.X_op
= O_symbol
;
7718 offset_expr
.X_add_symbol
=
7719 symbol_new ("L0\001", now_seg
,
7720 (valueT
) frag_now_fix (), frag_now
);
7721 offset_expr
.X_add_number
= 0;
7723 /* Put the floating point number into the section. */
7724 p
= frag_more ((int) length
);
7725 memcpy (p
, temp
, length
);
7727 /* Switch back to the original section. */
7728 subseg_set (seg
, subseg
);
7733 case 'i': /* 16 bit unsigned immediate */
7734 case 'j': /* 16 bit signed immediate */
7735 imm_reloc
= BFD_RELOC_LO16
;
7736 c
= my_getSmallExpression (&imm_expr
, s
);
7741 if (imm_expr
.X_op
== O_constant
)
7742 imm_expr
.X_add_number
=
7743 (imm_expr
.X_add_number
>> 16) & 0xffff;
7746 imm_reloc
= BFD_RELOC_HI16_S
;
7747 imm_unmatched_hi
= true;
7750 imm_reloc
= BFD_RELOC_HI16
;
7752 else if (imm_expr
.X_op
== O_constant
)
7753 imm_expr
.X_add_number
&= 0xffff;
7757 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7758 || ((imm_expr
.X_add_number
< 0
7759 || imm_expr
.X_add_number
>= 0x10000)
7760 && imm_expr
.X_op
== O_constant
))
7762 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7763 !strcmp (insn
->name
, insn
[1].name
))
7765 if (imm_expr
.X_op
== O_constant
7766 || imm_expr
.X_op
== O_big
)
7767 as_bad (_("16 bit expression not in range 0..65535"));
7775 /* The upper bound should be 0x8000, but
7776 unfortunately the MIPS assembler accepts numbers
7777 from 0x8000 to 0xffff and sign extends them, and
7778 we want to be compatible. We only permit this
7779 extended range for an instruction which does not
7780 provide any further alternates, since those
7781 alternates may handle other cases. People should
7782 use the numbers they mean, rather than relying on
7783 a mysterious sign extension. */
7784 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7785 strcmp (insn
->name
, insn
[1].name
) == 0);
7790 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7791 || ((imm_expr
.X_add_number
< -0x8000
7792 || imm_expr
.X_add_number
>= max
)
7793 && imm_expr
.X_op
== O_constant
)
7795 && imm_expr
.X_add_number
< 0
7796 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7797 && imm_expr
.X_unsigned
7798 && sizeof (imm_expr
.X_add_number
) <= 4))
7802 if (imm_expr
.X_op
== O_constant
7803 || imm_expr
.X_op
== O_big
)
7804 as_bad (_("16 bit expression not in range -32768..32767"));
7810 case 'o': /* 16 bit offset */
7811 c
= my_getSmallExpression (&offset_expr
, s
);
7813 /* If this value won't fit into a 16 bit offset, then go
7814 find a macro that will generate the 32 bit offset
7815 code pattern. As a special hack, we accept the
7816 difference of two local symbols as a constant. This
7817 is required to suppose embedded PIC switches, which
7818 use an instruction which looks like
7819 lw $4,$L12-$LS12($4)
7820 The problem with handling this in a more general
7821 fashion is that the macro function doesn't expect to
7822 see anything which can be handled in a single
7823 constant instruction. */
7825 && (offset_expr
.X_op
!= O_constant
7826 || offset_expr
.X_add_number
>= 0x8000
7827 || offset_expr
.X_add_number
< -0x8000)
7828 && (mips_pic
!= EMBEDDED_PIC
7829 || offset_expr
.X_op
!= O_subtract
7830 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7831 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7834 if (c
== 'h' || c
== 'H')
7836 if (offset_expr
.X_op
!= O_constant
)
7838 offset_expr
.X_add_number
=
7839 (offset_expr
.X_add_number
>> 16) & 0xffff;
7841 offset_reloc
= BFD_RELOC_LO16
;
7845 case 'p': /* pc relative offset */
7846 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7847 my_getExpression (&offset_expr
, s
);
7851 case 'u': /* upper 16 bits */
7852 c
= my_getSmallExpression (&imm_expr
, s
);
7853 imm_reloc
= BFD_RELOC_LO16
;
7858 if (imm_expr
.X_op
== O_constant
)
7859 imm_expr
.X_add_number
=
7860 (imm_expr
.X_add_number
>> 16) & 0xffff;
7863 imm_reloc
= BFD_RELOC_HI16_S
;
7864 imm_unmatched_hi
= true;
7867 imm_reloc
= BFD_RELOC_HI16
;
7869 else if (imm_expr
.X_op
== O_constant
)
7870 imm_expr
.X_add_number
&= 0xffff;
7872 if (imm_expr
.X_op
== O_constant
7873 && (imm_expr
.X_add_number
< 0
7874 || imm_expr
.X_add_number
>= 0x10000))
7875 as_bad (_("lui expression not in range 0..65535"));
7879 case 'a': /* 26 bit address */
7880 my_getExpression (&offset_expr
, s
);
7882 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7885 case 'N': /* 3 bit branch condition code */
7886 case 'M': /* 3 bit compare condition code */
7887 if (strncmp (s
, "$fcc", 4) != 0)
7897 while (isdigit ((unsigned char) *s
));
7899 as_bad (_("invalid condition code register $fcc%d"), regno
);
7901 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7903 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7907 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7909 if (isdigit ((unsigned char) *s
))
7918 while (isdigit ((unsigned char) *s
));
7921 c
= 8; /* Invalid sel value. */
7924 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7925 ip
->insn_opcode
|= c
;
7929 as_bad (_("bad char = '%c'\n"), *args
);
7934 /* Args don't match. */
7935 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7936 !strcmp (insn
->name
, insn
[1].name
))
7942 insn_error
= _("illegal operands");
7947 /* This routine assembles an instruction into its binary format when
7948 assembling for the mips16. As a side effect, it sets one of the
7949 global variables imm_reloc or offset_reloc to the type of
7950 relocation to do if one of the operands is an address expression.
7951 It also sets mips16_small and mips16_ext if the user explicitly
7952 requested a small or extended instruction. */
7957 struct mips_cl_insn
*ip
;
7961 struct mips_opcode
*insn
;
7964 unsigned int lastregno
= 0;
7969 mips16_small
= false;
7972 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7984 if (s
[1] == 't' && s
[2] == ' ')
7987 mips16_small
= true;
7991 else if (s
[1] == 'e' && s
[2] == ' ')
8000 insn_error
= _("unknown opcode");
8004 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8005 mips16_small
= true;
8007 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8009 insn_error
= _("unrecognized opcode");
8016 assert (strcmp (insn
->name
, str
) == 0);
8019 ip
->insn_opcode
= insn
->match
;
8020 ip
->use_extend
= false;
8021 imm_expr
.X_op
= O_absent
;
8022 imm_reloc
= BFD_RELOC_UNUSED
;
8023 offset_expr
.X_op
= O_absent
;
8024 offset_reloc
= BFD_RELOC_UNUSED
;
8025 for (args
= insn
->args
; 1; ++args
)
8032 /* In this switch statement we call break if we did not find
8033 a match, continue if we did find a match, or return if we
8042 /* Stuff the immediate value in now, if we can. */
8043 if (imm_expr
.X_op
== O_constant
8044 && imm_reloc
> BFD_RELOC_UNUSED
8045 && insn
->pinfo
!= INSN_MACRO
)
8047 mips16_immed ((char *) NULL
, 0,
8048 imm_reloc
- BFD_RELOC_UNUSED
,
8049 imm_expr
.X_add_number
, true, mips16_small
,
8050 mips16_ext
, &ip
->insn_opcode
,
8051 &ip
->use_extend
, &ip
->extend
);
8052 imm_expr
.X_op
= O_absent
;
8053 imm_reloc
= BFD_RELOC_UNUSED
;
8067 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8070 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8086 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8088 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8105 if (isdigit ((unsigned char) s
[1]))
8115 while (isdigit ((unsigned char) *s
));
8118 as_bad (_("invalid register number (%d)"), regno
);
8124 if (s
[1] == 'f' && s
[2] == 'p')
8129 else if (s
[1] == 's' && s
[2] == 'p')
8134 else if (s
[1] == 'g' && s
[2] == 'p')
8139 else if (s
[1] == 'a' && s
[2] == 't')
8144 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8149 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8162 if (c
== 'v' || c
== 'w')
8164 regno
= mips16_to_32_reg_map
[lastregno
];
8178 regno
= mips32_to_16_reg_map
[regno
];
8183 regno
= ILLEGAL_REG
;
8188 regno
= ILLEGAL_REG
;
8193 regno
= ILLEGAL_REG
;
8198 if (regno
== AT
&& ! mips_opts
.noat
)
8199 as_warn (_("used $at without \".set noat\""));
8206 if (regno
== ILLEGAL_REG
)
8213 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8217 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8220 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8223 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8229 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8232 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8233 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8243 if (strncmp (s
, "$pc", 3) == 0)
8267 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8269 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8270 and generate the appropriate reloc. If the text
8271 inside %gprel is not a symbol name with an
8272 optional offset, then we generate a normal reloc
8273 and will probably fail later. */
8274 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8275 if (imm_expr
.X_op
== O_symbol
)
8278 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8280 ip
->use_extend
= true;
8287 /* Just pick up a normal expression. */
8288 my_getExpression (&imm_expr
, s
);
8291 if (imm_expr
.X_op
== O_register
)
8293 /* What we thought was an expression turned out to
8296 if (s
[0] == '(' && args
[1] == '(')
8298 /* It looks like the expression was omitted
8299 before a register indirection, which means
8300 that the expression is implicitly zero. We
8301 still set up imm_expr, so that we handle
8302 explicit extensions correctly. */
8303 imm_expr
.X_op
= O_constant
;
8304 imm_expr
.X_add_number
= 0;
8305 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8312 /* We need to relax this instruction. */
8313 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8322 /* We use offset_reloc rather than imm_reloc for the PC
8323 relative operands. This lets macros with both
8324 immediate and address operands work correctly. */
8325 my_getExpression (&offset_expr
, s
);
8327 if (offset_expr
.X_op
== O_register
)
8330 /* We need to relax this instruction. */
8331 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8335 case '6': /* break code */
8336 my_getExpression (&imm_expr
, s
);
8337 check_absolute_expr (ip
, &imm_expr
);
8338 if ((unsigned long) imm_expr
.X_add_number
> 63)
8340 as_warn (_("Invalid value for `%s' (%lu)"),
8342 (unsigned long) imm_expr
.X_add_number
);
8343 imm_expr
.X_add_number
&= 0x3f;
8345 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8346 imm_expr
.X_op
= O_absent
;
8350 case 'a': /* 26 bit address */
8351 my_getExpression (&offset_expr
, s
);
8353 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8354 ip
->insn_opcode
<<= 16;
8357 case 'l': /* register list for entry macro */
8358 case 'L': /* register list for exit macro */
8368 int freg
, reg1
, reg2
;
8370 while (*s
== ' ' || *s
== ',')
8374 as_bad (_("can't parse register list"));
8386 while (isdigit ((unsigned char) *s
))
8408 as_bad (_("invalid register list"));
8413 while (isdigit ((unsigned char) *s
))
8420 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8425 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8430 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8431 mask
|= (reg2
- 3) << 3;
8432 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8433 mask
|= (reg2
- 15) << 1;
8434 else if (reg1
== 31 && reg2
== 31)
8438 as_bad (_("invalid register list"));
8442 /* The mask is filled in in the opcode table for the
8443 benefit of the disassembler. We remove it before
8444 applying the actual mask. */
8445 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8446 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8450 case 'e': /* extend code */
8451 my_getExpression (&imm_expr
, s
);
8452 check_absolute_expr (ip
, &imm_expr
);
8453 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8455 as_warn (_("Invalid value for `%s' (%lu)"),
8457 (unsigned long) imm_expr
.X_add_number
);
8458 imm_expr
.X_add_number
&= 0x7ff;
8460 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8461 imm_expr
.X_op
= O_absent
;
8471 /* Args don't match. */
8472 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8473 strcmp (insn
->name
, insn
[1].name
) == 0)
8480 insn_error
= _("illegal operands");
8486 /* This structure holds information we know about a mips16 immediate
8489 struct mips16_immed_operand
8491 /* The type code used in the argument string in the opcode table. */
8493 /* The number of bits in the short form of the opcode. */
8495 /* The number of bits in the extended form of the opcode. */
8497 /* The amount by which the short form is shifted when it is used;
8498 for example, the sw instruction has a shift count of 2. */
8500 /* The amount by which the short form is shifted when it is stored
8501 into the instruction code. */
8503 /* Non-zero if the short form is unsigned. */
8505 /* Non-zero if the extended form is unsigned. */
8507 /* Non-zero if the value is PC relative. */
8511 /* The mips16 immediate operand types. */
8513 static const struct mips16_immed_operand mips16_immed_operands
[] =
8515 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8516 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8517 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8518 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8519 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8520 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8521 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8522 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8523 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8524 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8525 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8526 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8527 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8528 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8529 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8530 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8531 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8532 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8533 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8534 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8535 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8538 #define MIPS16_NUM_IMMED \
8539 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8541 /* Handle a mips16 instruction with an immediate value. This or's the
8542 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8543 whether an extended value is needed; if one is needed, it sets
8544 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8545 If SMALL is true, an unextended opcode was explicitly requested.
8546 If EXT is true, an extended opcode was explicitly requested. If
8547 WARN is true, warn if EXT does not match reality. */
8550 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8559 unsigned long *insn
;
8560 boolean
*use_extend
;
8561 unsigned short *extend
;
8563 register const struct mips16_immed_operand
*op
;
8564 int mintiny
, maxtiny
;
8567 op
= mips16_immed_operands
;
8568 while (op
->type
!= type
)
8571 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8576 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8579 maxtiny
= 1 << op
->nbits
;
8584 maxtiny
= (1 << op
->nbits
) - 1;
8589 mintiny
= - (1 << (op
->nbits
- 1));
8590 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8593 /* Branch offsets have an implicit 0 in the lowest bit. */
8594 if (type
== 'p' || type
== 'q')
8597 if ((val
& ((1 << op
->shift
) - 1)) != 0
8598 || val
< (mintiny
<< op
->shift
)
8599 || val
> (maxtiny
<< op
->shift
))
8604 if (warn
&& ext
&& ! needext
)
8605 as_warn_where (file
, line
,
8606 _("extended operand requested but not required"));
8607 if (small
&& needext
)
8608 as_bad_where (file
, line
, _("invalid unextended operand value"));
8610 if (small
|| (! ext
&& ! needext
))
8614 *use_extend
= false;
8615 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8616 insnval
<<= op
->op_shift
;
8621 long minext
, maxext
;
8627 maxext
= (1 << op
->extbits
) - 1;
8631 minext
= - (1 << (op
->extbits
- 1));
8632 maxext
= (1 << (op
->extbits
- 1)) - 1;
8634 if (val
< minext
|| val
> maxext
)
8635 as_bad_where (file
, line
,
8636 _("operand value out of range for instruction"));
8639 if (op
->extbits
== 16)
8641 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8644 else if (op
->extbits
== 15)
8646 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8651 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8655 *extend
= (unsigned short) extval
;
8664 my_getSmallExpression (ep
, str
)
8675 ((str
[1] == 'h' && str
[2] == 'i')
8676 || (str
[1] == 'H' && str
[2] == 'I')
8677 || (str
[1] == 'l' && str
[2] == 'o'))
8689 * A small expression may be followed by a base register.
8690 * Scan to the end of this operand, and then back over a possible
8691 * base register. Then scan the small expression up to that
8692 * point. (Based on code in sparc.c...)
8694 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8696 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8698 if (isdigit ((unsigned char) sp
[-2]))
8700 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8702 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8708 else if (sp
- 5 >= str
8711 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8712 || (sp
[-3] == 's' && sp
[-2] == 'p')
8713 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8714 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8720 /* no expression means zero offset */
8723 /* %xx(reg) is an error */
8724 ep
->X_op
= O_absent
;
8729 ep
->X_op
= O_constant
;
8732 ep
->X_add_symbol
= NULL
;
8733 ep
->X_op_symbol
= NULL
;
8734 ep
->X_add_number
= 0;
8739 my_getExpression (ep
, str
);
8746 my_getExpression (ep
, str
);
8747 return c
; /* => %hi or %lo encountered */
8751 my_getExpression (ep
, str
)
8757 save_in
= input_line_pointer
;
8758 input_line_pointer
= str
;
8760 expr_end
= input_line_pointer
;
8761 input_line_pointer
= save_in
;
8763 /* If we are in mips16 mode, and this is an expression based on `.',
8764 then we bump the value of the symbol by 1 since that is how other
8765 text symbols are handled. We don't bother to handle complex
8766 expressions, just `.' plus or minus a constant. */
8767 if (mips_opts
.mips16
8768 && ep
->X_op
== O_symbol
8769 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8770 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8771 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8772 && symbol_constant_p (ep
->X_add_symbol
)
8773 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8774 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8777 /* Turn a string in input_line_pointer into a floating point constant
8778 of type TYPE, and store the appropriate bytes in *LITP. The number
8779 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8780 returned, or NULL on OK. */
8783 md_atof (type
, litP
, sizeP
)
8789 LITTLENUM_TYPE words
[4];
8805 return _("bad call to md_atof");
8808 t
= atof_ieee (input_line_pointer
, type
, words
);
8810 input_line_pointer
= t
;
8814 if (! target_big_endian
)
8816 for (i
= prec
- 1; i
>= 0; i
--)
8818 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8824 for (i
= 0; i
< prec
; i
++)
8826 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8835 md_number_to_chars (buf
, val
, n
)
8840 if (target_big_endian
)
8841 number_to_chars_bigendian (buf
, val
, n
);
8843 number_to_chars_littleendian (buf
, val
, n
);
8846 CONST
char *md_shortopts
= "O::g::G:";
8848 struct option md_longopts
[] =
8850 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8851 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8852 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8853 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8854 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8855 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8856 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8857 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8858 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8859 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8860 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8861 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8862 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8863 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8864 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8865 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8866 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8867 {"break", no_argument
, NULL
, OPTION_BREAK
},
8868 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8869 #define OPTION_EB (OPTION_MD_BASE + 9)
8870 {"EB", no_argument
, NULL
, OPTION_EB
},
8871 #define OPTION_EL (OPTION_MD_BASE + 10)
8872 {"EL", no_argument
, NULL
, OPTION_EL
},
8873 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8874 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8875 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8876 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8877 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8878 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8879 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8880 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8881 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8882 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8883 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8884 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8885 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8886 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8887 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8888 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8889 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8890 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8891 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8892 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8893 #define OPTION_MABI (OPTION_MD_BASE + 21)
8894 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8895 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8896 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8897 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8898 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8899 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8900 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8901 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8902 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8903 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8904 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8905 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8906 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8907 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8908 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8909 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8910 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8911 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8912 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8914 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8915 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8916 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8917 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8918 #define OPTION_32 (OPTION_ELF_BASE + 3)
8919 #define OPTION_64 (OPTION_ELF_BASE + 4)
8920 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8921 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8922 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8923 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8924 {"32", no_argument
, NULL
, OPTION_32
},
8925 {"64", no_argument
, NULL
, OPTION_64
},
8928 {NULL
, no_argument
, NULL
, 0}
8930 size_t md_longopts_size
= sizeof (md_longopts
);
8933 md_parse_option (c
, arg
)
8939 case OPTION_CONSTRUCT_FLOATS
:
8940 mips_disable_float_construction
= 0;
8943 case OPTION_NO_CONSTRUCT_FLOATS
:
8944 mips_disable_float_construction
= 1;
8956 target_big_endian
= 1;
8960 target_big_endian
= 0;
8964 if (arg
&& arg
[1] == '0')
8974 mips_debug
= atoi (arg
);
8975 /* When the MIPS assembler sees -g or -g2, it does not do
8976 optimizations which limit full symbolic debugging. We take
8977 that to be equivalent to -O0. */
8978 if (mips_debug
== 2)
8983 mips_opts
.isa
= ISA_MIPS1
;
8987 mips_opts
.isa
= ISA_MIPS2
;
8991 mips_opts
.isa
= ISA_MIPS3
;
8995 mips_opts
.isa
= ISA_MIPS4
;
8999 mips_opts
.isa
= ISA_MIPS5
;
9003 mips_opts
.isa
= ISA_MIPS32
;
9007 mips_opts
.isa
= ISA_MIPS64
;
9012 /* Identify the processor type. */
9013 if (strcasecmp (arg
, "default") == 0)
9014 mips_cpu
= CPU_UNKNOWN
;
9017 const struct mips_cpu_info
*ci
;
9019 ci
= mips_cpu_info_from_name (arg
);
9020 if (ci
== NULL
|| ci
->is_isa
)
9021 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9029 mips_cpu
= CPU_R4650
;
9032 case OPTION_NO_M4650
:
9036 mips_cpu
= CPU_R4010
;
9039 case OPTION_NO_M4010
:
9043 mips_cpu
= CPU_VR4100
;
9046 case OPTION_NO_M4100
:
9050 mips_cpu
= CPU_R3900
;
9053 case OPTION_NO_M3900
:
9057 mips_opts
.mips16
= 1;
9058 mips_no_prev_insn (false);
9061 case OPTION_NO_MIPS16
:
9062 mips_opts
.mips16
= 0;
9063 mips_no_prev_insn (false);
9066 case OPTION_MEMBEDDED_PIC
:
9067 mips_pic
= EMBEDDED_PIC
;
9068 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9070 as_bad (_("-G may not be used with embedded PIC code"));
9073 g_switch_value
= 0x7fffffff;
9077 /* When generating ELF code, we permit -KPIC and -call_shared to
9078 select SVR4_PIC, and -non_shared to select no PIC. This is
9079 intended to be compatible with Irix 5. */
9080 case OPTION_CALL_SHARED
:
9081 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9083 as_bad (_("-call_shared is supported only for ELF format"));
9086 mips_pic
= SVR4_PIC
;
9087 if (g_switch_seen
&& g_switch_value
!= 0)
9089 as_bad (_("-G may not be used with SVR4 PIC code"));
9095 case OPTION_NON_SHARED
:
9096 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9098 as_bad (_("-non_shared is supported only for ELF format"));
9104 /* The -xgot option tells the assembler to use 32 offsets when
9105 accessing the got in SVR4_PIC mode. It is for Irix
9110 #endif /* OBJ_ELF */
9113 if (! USE_GLOBAL_POINTER_OPT
)
9115 as_bad (_("-G is not supported for this configuration"));
9118 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9120 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9124 g_switch_value
= atoi (arg
);
9129 /* The -32 and -64 options tell the assembler to output the 32
9130 bit or the 64 bit MIPS ELF format. */
9137 const char **list
, **l
;
9139 list
= bfd_target_list ();
9140 for (l
= list
; *l
!= NULL
; l
++)
9141 if (strcmp (*l
, "elf64-bigmips") == 0
9142 || strcmp (*l
, "elf64-littlemips") == 0)
9145 as_fatal (_("No compiled in support for 64 bit object file format"));
9150 #endif /* OBJ_ELF */
9156 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9157 flag in object files because to do so would make it
9158 impossible to link with libraries compiled without "-gp32".
9159 This is unnecessarily restrictive.
9161 We could solve this problem by adding "-gp32" multilibs to
9162 gcc, but to set this flag before gcc is built with such
9163 multilibs will break too many systems. */
9179 if (strcmp (arg
, "32") == 0
9180 || strcmp (arg
, "n32") == 0
9181 || strcmp (arg
, "64") == 0
9182 || strcmp (arg
, "o64") == 0
9183 || strcmp (arg
, "eabi") == 0)
9184 mips_abi_string
= arg
;
9187 case OPTION_M7000_HILO_FIX
:
9188 mips_7000_hilo_fix
= true;
9191 case OPTION_NO_M7000_HILO_FIX
:
9192 mips_7000_hilo_fix
= false;
9203 show (stream
, string
, col_p
, first_p
)
9211 fprintf (stream
, "%24s", "");
9216 fprintf (stream
, ", ");
9220 if (*col_p
+ strlen (string
) > 72)
9222 fprintf (stream
, "\n%24s", "");
9226 fprintf (stream
, "%s", string
);
9227 *col_p
+= strlen (string
);
9233 md_show_usage (stream
)
9238 fprintf (stream
, _("\
9240 -membedded-pic generate embedded position independent code\n\
9241 -EB generate big endian output\n\
9242 -EL generate little endian output\n\
9243 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9244 -G NUM allow referencing objects up to NUM bytes\n\
9245 implicitly with the gp register [default 8]\n"));
9246 fprintf (stream
, _("\
9247 -mips1 generate MIPS ISA I instructions\n\
9248 -mips2 generate MIPS ISA II instructions\n\
9249 -mips3 generate MIPS ISA III instructions\n\
9250 -mips4 generate MIPS ISA IV instructions\n\
9251 -mips5 generate MIPS ISA V instructions\n\
9252 -mips32 generate MIPS32 ISA instructions\n\
9253 -mips64 generate MIPS64 ISA instructions\n\
9254 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9258 show (stream
, "2000", &column
, &first
);
9259 show (stream
, "3000", &column
, &first
);
9260 show (stream
, "3900", &column
, &first
);
9261 show (stream
, "4000", &column
, &first
);
9262 show (stream
, "4010", &column
, &first
);
9263 show (stream
, "4100", &column
, &first
);
9264 show (stream
, "4111", &column
, &first
);
9265 show (stream
, "4300", &column
, &first
);
9266 show (stream
, "4400", &column
, &first
);
9267 show (stream
, "4600", &column
, &first
);
9268 show (stream
, "4650", &column
, &first
);
9269 show (stream
, "5000", &column
, &first
);
9270 show (stream
, "6000", &column
, &first
);
9271 show (stream
, "8000", &column
, &first
);
9272 show (stream
, "10000", &column
, &first
);
9273 show (stream
, "mips32-4k", &column
, &first
);
9274 show (stream
, "sb-1", &column
, &first
);
9275 fputc ('\n', stream
);
9277 fprintf (stream
, _("\
9278 -mCPU equivalent to -mcpu=CPU.\n\
9279 -no-mCPU don't generate code specific to CPU.\n\
9280 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9284 show (stream
, "3900", &column
, &first
);
9285 show (stream
, "4010", &column
, &first
);
9286 show (stream
, "4100", &column
, &first
);
9287 show (stream
, "4650", &column
, &first
);
9288 fputc ('\n', stream
);
9290 fprintf (stream
, _("\
9291 -mips16 generate mips16 instructions\n\
9292 -no-mips16 do not generate mips16 instructions\n"));
9293 fprintf (stream
, _("\
9294 -O0 remove unneeded NOPs, do not swap branches\n\
9295 -O remove unneeded NOPs and swap branches\n\
9296 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9297 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9298 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9300 fprintf (stream
, _("\
9301 -KPIC, -call_shared generate SVR4 position independent code\n\
9302 -non_shared do not generate position independent code\n\
9303 -xgot assume a 32 bit GOT\n\
9304 -32 create 32 bit object file (default)\n\
9305 -64 create 64 bit object file\n"));
9310 mips_init_after_args ()
9312 /* initialize opcodes */
9313 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9314 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9318 md_pcrel_from (fixP
)
9321 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9322 && fixP
->fx_addsy
!= (symbolS
*) NULL
9323 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9325 /* This makes a branch to an undefined symbol be a branch to the
9326 current location. */
9330 /* return the address of the delay slot */
9331 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9334 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9335 reloc for a cons. We could use the definition there, except that
9336 we want to handle 64 bit relocs specially. */
9339 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9340 fragS
*frag ATTRIBUTE_UNUSED
;
9342 unsigned int nbytes
;
9346 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9348 if (nbytes
== 8 && ! mips_64
)
9350 if (target_big_endian
)
9356 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9357 as_bad (_("Unsupported reloc size %d"), nbytes
);
9359 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9362 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9365 /* This is called before the symbol table is processed. In order to
9366 work with gcc when using mips-tfile, we must keep all local labels.
9367 However, in other cases, we want to discard them. If we were
9368 called with -g, but we didn't see any debugging information, it may
9369 mean that gcc is smuggling debugging information through to
9370 mips-tfile, in which case we must generate all local labels. */
9373 mips_frob_file_before_adjust ()
9375 #ifndef NO_ECOFF_DEBUGGING
9378 && ! ecoff_debugging_seen
)
9379 flag_keep_locals
= 1;
9383 /* Sort any unmatched HI16_S relocs so that they immediately precede
9384 the corresponding LO reloc. This is called before md_apply_fix and
9385 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9386 explicit use of the %hi modifier. */
9391 struct mips_hi_fixup
*l
;
9393 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9395 segment_info_type
*seginfo
;
9398 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9400 /* Check quickly whether the next fixup happens to be a matching
9402 if (l
->fixp
->fx_next
!= NULL
9403 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9404 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9405 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9408 /* Look through the fixups for this segment for a matching %lo.
9409 When we find one, move the %hi just in front of it. We do
9410 this in two passes. In the first pass, we try to find a
9411 unique %lo. In the second pass, we permit multiple %hi
9412 relocs for a single %lo (this is a GNU extension). */
9413 seginfo
= seg_info (l
->seg
);
9414 for (pass
= 0; pass
< 2; pass
++)
9419 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9421 /* Check whether this is a %lo fixup which matches l->fixp. */
9422 if (f
->fx_r_type
== BFD_RELOC_LO16
9423 && f
->fx_addsy
== l
->fixp
->fx_addsy
9424 && f
->fx_offset
== l
->fixp
->fx_offset
9427 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9428 || prev
->fx_addsy
!= f
->fx_addsy
9429 || prev
->fx_offset
!= f
->fx_offset
))
9433 /* Move l->fixp before f. */
9434 for (pf
= &seginfo
->fix_root
;
9436 pf
= &(*pf
)->fx_next
)
9437 assert (*pf
!= NULL
);
9439 *pf
= l
->fixp
->fx_next
;
9441 l
->fixp
->fx_next
= f
;
9443 seginfo
->fix_root
= l
->fixp
;
9445 prev
->fx_next
= l
->fixp
;
9456 #if 0 /* GCC code motion plus incomplete dead code elimination
9457 can leave a %hi without a %lo. */
9459 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9460 _("Unmatched %%hi reloc"));
9466 /* When generating embedded PIC code we need to use a special
9467 relocation to represent the difference of two symbols in the .text
9468 section (switch tables use a difference of this sort). See
9469 include/coff/mips.h for details. This macro checks whether this
9470 fixup requires the special reloc. */
9471 #define SWITCH_TABLE(fixp) \
9472 ((fixp)->fx_r_type == BFD_RELOC_32 \
9473 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9474 && (fixp)->fx_addsy != NULL \
9475 && (fixp)->fx_subsy != NULL \
9476 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9477 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9479 /* When generating embedded PIC code we must keep all PC relative
9480 relocations, in case the linker has to relax a call. We also need
9481 to keep relocations for switch table entries. */
9484 mips_force_relocation (fixp
)
9487 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9488 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9491 return (mips_pic
== EMBEDDED_PIC
9493 || SWITCH_TABLE (fixp
)
9494 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9495 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9498 /* Apply a fixup to the object file. */
9501 md_apply_fix (fixP
, valueP
)
9508 assert (fixP
->fx_size
== 4
9509 || fixP
->fx_r_type
== BFD_RELOC_16
9510 || fixP
->fx_r_type
== BFD_RELOC_64
9511 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9512 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9516 /* If we aren't adjusting this fixup to be against the section
9517 symbol, we need to adjust the value. */
9519 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9521 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9522 || S_IS_WEAK (fixP
->fx_addsy
)
9523 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9524 && (((bfd_get_section_flags (stdoutput
,
9525 S_GET_SEGMENT (fixP
->fx_addsy
))
9526 & SEC_LINK_ONCE
) != 0)
9527 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9529 sizeof (".gnu.linkonce") - 1))))
9532 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9533 if (value
!= 0 && ! fixP
->fx_pcrel
)
9535 /* In this case, the bfd_install_relocation routine will
9536 incorrectly add the symbol value back in. We just want
9537 the addend to appear in the object file.
9538 FIXME: If this makes VALUE zero, we're toast. */
9539 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9543 /* This code was generated using trial and error and so is
9544 fragile and not trustworthy. If you change it, you should
9545 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9547 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9549 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9551 /* BFD's REL handling, for MIPS, is _very_ weird.
9552 This gives the right results, but it can't possibly
9553 be the way things are supposed to work. */
9554 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9555 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9556 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9561 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9563 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9566 switch (fixP
->fx_r_type
)
9568 case BFD_RELOC_MIPS_JMP
:
9569 case BFD_RELOC_HI16
:
9570 case BFD_RELOC_HI16_S
:
9571 case BFD_RELOC_MIPS_GPREL
:
9572 case BFD_RELOC_MIPS_LITERAL
:
9573 case BFD_RELOC_MIPS_CALL16
:
9574 case BFD_RELOC_MIPS_GOT16
:
9575 case BFD_RELOC_MIPS_GPREL32
:
9576 case BFD_RELOC_MIPS_GOT_HI16
:
9577 case BFD_RELOC_MIPS_GOT_LO16
:
9578 case BFD_RELOC_MIPS_CALL_HI16
:
9579 case BFD_RELOC_MIPS_CALL_LO16
:
9580 case BFD_RELOC_MIPS16_GPREL
:
9582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9583 _("Invalid PC relative reloc"));
9584 /* Nothing needed to do. The value comes from the reloc entry */
9587 case BFD_RELOC_MIPS16_JMP
:
9588 /* We currently always generate a reloc against a symbol, which
9589 means that we don't want an addend even if the symbol is
9591 fixP
->fx_addnumber
= 0;
9594 case BFD_RELOC_PCREL_HI16_S
:
9595 /* The addend for this is tricky if it is internal, so we just
9596 do everything here rather than in bfd_install_relocation. */
9597 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9602 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9604 /* For an external symbol adjust by the address to make it
9605 pcrel_offset. We use the address of the RELLO reloc
9606 which follows this one. */
9607 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9608 + fixP
->fx_next
->fx_where
);
9613 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9614 if (target_big_endian
)
9616 md_number_to_chars (buf
, value
, 2);
9619 case BFD_RELOC_PCREL_LO16
:
9620 /* The addend for this is tricky if it is internal, so we just
9621 do everything here rather than in bfd_install_relocation. */
9622 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9627 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9628 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9629 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9630 if (target_big_endian
)
9632 md_number_to_chars (buf
, value
, 2);
9636 /* This is handled like BFD_RELOC_32, but we output a sign
9637 extended value if we are only 32 bits. */
9639 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9641 if (8 <= sizeof (valueT
))
9642 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9649 w1
= w2
= fixP
->fx_where
;
9650 if (target_big_endian
)
9654 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9655 if ((value
& 0x80000000) != 0)
9659 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9666 /* If we are deleting this reloc entry, we must fill in the
9667 value now. This can happen if we have a .word which is not
9668 resolved when it appears but is later defined. We also need
9669 to fill in the value if this is an embedded PIC switch table
9672 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9673 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9678 /* If we are deleting this reloc entry, we must fill in the
9680 assert (fixP
->fx_size
== 2);
9682 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9686 case BFD_RELOC_LO16
:
9687 /* When handling an embedded PIC switch statement, we can wind
9688 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9691 if (value
< -0x8000 || value
> 0x7fff)
9692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9693 _("relocation overflow"));
9694 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9695 if (target_big_endian
)
9697 md_number_to_chars (buf
, value
, 2);
9701 case BFD_RELOC_16_PCREL_S2
:
9703 * We need to save the bits in the instruction since fixup_segment()
9704 * might be deleting the relocation entry (i.e., a branch within
9705 * the current segment).
9707 if ((value
& 0x3) != 0)
9708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9709 _("Branch to odd address (%lx)"), value
);
9711 if (!fixP
->fx_done
&& value
!= 0)
9713 /* If 'value' is zero, the remaining reloc code won't actually
9714 do the store, so it must be done here. This is probably
9717 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9721 /* update old instruction data */
9722 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9723 if (target_big_endian
)
9724 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9726 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9728 if (value
>= -0x8000 && value
< 0x8000)
9729 insn
|= value
& 0xffff;
9732 /* The branch offset is too large. If this is an
9733 unconditional branch, and we are not generating PIC code,
9734 we can convert it to an absolute jump instruction. */
9735 if (mips_pic
== NO_PIC
9737 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9738 && (fixP
->fx_frag
->fr_address
9739 < text_section
->vma
+ text_section
->_raw_size
)
9740 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9741 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9742 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9744 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9745 insn
= 0x0c000000; /* jal */
9747 insn
= 0x08000000; /* j */
9748 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9750 fixP
->fx_addsy
= section_symbol (text_section
);
9751 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9755 /* FIXME. It would be possible in principle to handle
9756 conditional branches which overflow. They could be
9757 transformed into a branch around a jump. This would
9758 require setting up variant frags for each different
9759 branch type. The native MIPS assembler attempts to
9760 handle these cases, but it appears to do it
9762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9763 _("Branch out of range"));
9767 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9770 case BFD_RELOC_VTABLE_INHERIT
:
9773 && !S_IS_DEFINED (fixP
->fx_addsy
)
9774 && !S_IS_WEAK (fixP
->fx_addsy
))
9775 S_SET_WEAK (fixP
->fx_addsy
);
9778 case BFD_RELOC_VTABLE_ENTRY
:
9794 const struct mips_opcode
*p
;
9795 int treg
, sreg
, dreg
, shamt
;
9800 for (i
= 0; i
< NUMOPCODES
; ++i
)
9802 p
= &mips_opcodes
[i
];
9803 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9805 printf ("%08lx %s\t", oc
, p
->name
);
9806 treg
= (oc
>> 16) & 0x1f;
9807 sreg
= (oc
>> 21) & 0x1f;
9808 dreg
= (oc
>> 11) & 0x1f;
9809 shamt
= (oc
>> 6) & 0x1f;
9811 for (args
= p
->args
;; ++args
)
9822 printf ("%c", *args
);
9826 assert (treg
== sreg
);
9827 printf ("$%d,$%d", treg
, sreg
);
9832 printf ("$%d", dreg
);
9837 printf ("$%d", treg
);
9841 printf ("0x%x", treg
);
9846 printf ("$%d", sreg
);
9850 printf ("0x%08lx", oc
& 0x1ffffff);
9862 printf ("$%d", shamt
);
9873 printf (_("%08lx UNDEFINED\n"), oc
);
9884 name
= input_line_pointer
;
9885 c
= get_symbol_end ();
9886 p
= (symbolS
*) symbol_find_or_make (name
);
9887 *input_line_pointer
= c
;
9891 /* Align the current frag to a given power of two. The MIPS assembler
9892 also automatically adjusts any preceding label. */
9895 mips_align (to
, fill
, label
)
9900 mips_emit_delays (false);
9901 frag_align (to
, fill
, 0);
9902 record_alignment (now_seg
, to
);
9905 assert (S_GET_SEGMENT (label
) == now_seg
);
9906 symbol_set_frag (label
, frag_now
);
9907 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9911 /* Align to a given power of two. .align 0 turns off the automatic
9912 alignment used by the data creating pseudo-ops. */
9916 int x ATTRIBUTE_UNUSED
;
9919 register long temp_fill
;
9920 long max_alignment
= 15;
9924 o Note that the assembler pulls down any immediately preceeding label
9925 to the aligned address.
9926 o It's not documented but auto alignment is reinstated by
9927 a .align pseudo instruction.
9928 o Note also that after auto alignment is turned off the mips assembler
9929 issues an error on attempt to assemble an improperly aligned data item.
9934 temp
= get_absolute_expression ();
9935 if (temp
> max_alignment
)
9936 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9939 as_warn (_("Alignment negative: 0 assumed."));
9942 if (*input_line_pointer
== ',')
9944 input_line_pointer
++;
9945 temp_fill
= get_absolute_expression ();
9952 mips_align (temp
, (int) temp_fill
,
9953 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9960 demand_empty_rest_of_line ();
9964 mips_flush_pending_output ()
9966 mips_emit_delays (false);
9967 mips_clear_insn_labels ();
9976 /* When generating embedded PIC code, we only use the .text, .lit8,
9977 .sdata and .sbss sections. We change the .data and .rdata
9978 pseudo-ops to use .sdata. */
9979 if (mips_pic
== EMBEDDED_PIC
9980 && (sec
== 'd' || sec
== 'r'))
9984 /* The ELF backend needs to know that we are changing sections, so
9985 that .previous works correctly. We could do something like check
9986 for a obj_section_change_hook macro, but that might be confusing
9987 as it would not be appropriate to use it in the section changing
9988 functions in read.c, since obj-elf.c intercepts those. FIXME:
9989 This should be cleaner, somehow. */
9990 obj_elf_section_change_hook ();
9993 mips_emit_delays (false);
10003 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10004 demand_empty_rest_of_line ();
10008 if (USE_GLOBAL_POINTER_OPT
)
10010 seg
= subseg_new (RDATA_SECTION_NAME
,
10011 (subsegT
) get_absolute_expression ());
10012 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10014 bfd_set_section_flags (stdoutput
, seg
,
10020 if (strcmp (TARGET_OS
, "elf") != 0)
10021 record_alignment (seg
, 4);
10023 demand_empty_rest_of_line ();
10027 as_bad (_("No read only data section in this object file format"));
10028 demand_empty_rest_of_line ();
10034 if (USE_GLOBAL_POINTER_OPT
)
10036 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10037 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10039 bfd_set_section_flags (stdoutput
, seg
,
10040 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10042 if (strcmp (TARGET_OS
, "elf") != 0)
10043 record_alignment (seg
, 4);
10045 demand_empty_rest_of_line ();
10050 as_bad (_("Global pointers not supported; recompile -G 0"));
10051 demand_empty_rest_of_line ();
10060 mips_enable_auto_align ()
10071 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10072 mips_emit_delays (false);
10073 if (log_size
> 0 && auto_align
)
10074 mips_align (log_size
, 0, label
);
10075 mips_clear_insn_labels ();
10076 cons (1 << log_size
);
10080 s_float_cons (type
)
10085 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10087 mips_emit_delays (false);
10092 mips_align (3, 0, label
);
10094 mips_align (2, 0, label
);
10097 mips_clear_insn_labels ();
10102 /* Handle .globl. We need to override it because on Irix 5 you are
10105 where foo is an undefined symbol, to mean that foo should be
10106 considered to be the address of a function. */
10110 int x ATTRIBUTE_UNUSED
;
10117 name
= input_line_pointer
;
10118 c
= get_symbol_end ();
10119 symbolP
= symbol_find_or_make (name
);
10120 *input_line_pointer
= c
;
10121 SKIP_WHITESPACE ();
10123 /* On Irix 5, every global symbol that is not explicitly labelled as
10124 being a function is apparently labelled as being an object. */
10127 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10132 secname
= input_line_pointer
;
10133 c
= get_symbol_end ();
10134 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10136 as_bad (_("%s: no such section"), secname
);
10137 *input_line_pointer
= c
;
10139 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10140 flag
= BSF_FUNCTION
;
10143 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10145 S_SET_EXTERNAL (symbolP
);
10146 demand_empty_rest_of_line ();
10151 int x ATTRIBUTE_UNUSED
;
10156 opt
= input_line_pointer
;
10157 c
= get_symbol_end ();
10161 /* FIXME: What does this mean? */
10163 else if (strncmp (opt
, "pic", 3) == 0)
10167 i
= atoi (opt
+ 3);
10171 mips_pic
= SVR4_PIC
;
10173 as_bad (_(".option pic%d not supported"), i
);
10175 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10177 if (g_switch_seen
&& g_switch_value
!= 0)
10178 as_warn (_("-G may not be used with SVR4 PIC code"));
10179 g_switch_value
= 0;
10180 bfd_set_gp_size (stdoutput
, 0);
10184 as_warn (_("Unrecognized option \"%s\""), opt
);
10186 *input_line_pointer
= c
;
10187 demand_empty_rest_of_line ();
10190 /* This structure is used to hold a stack of .set values. */
10192 struct mips_option_stack
10194 struct mips_option_stack
*next
;
10195 struct mips_set_options options
;
10198 static struct mips_option_stack
*mips_opts_stack
;
10200 /* Handle the .set pseudo-op. */
10204 int x ATTRIBUTE_UNUSED
;
10206 char *name
= input_line_pointer
, ch
;
10208 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10209 input_line_pointer
++;
10210 ch
= *input_line_pointer
;
10211 *input_line_pointer
= '\0';
10213 if (strcmp (name
, "reorder") == 0)
10215 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10217 /* If we still have pending nops, we can discard them. The
10218 usual nop handling will insert any that are still
10220 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10221 * (mips_opts
.mips16
? 2 : 4));
10222 prev_nop_frag
= NULL
;
10224 mips_opts
.noreorder
= 0;
10226 else if (strcmp (name
, "noreorder") == 0)
10228 mips_emit_delays (true);
10229 mips_opts
.noreorder
= 1;
10230 mips_any_noreorder
= 1;
10232 else if (strcmp (name
, "at") == 0)
10234 mips_opts
.noat
= 0;
10236 else if (strcmp (name
, "noat") == 0)
10238 mips_opts
.noat
= 1;
10240 else if (strcmp (name
, "macro") == 0)
10242 mips_opts
.warn_about_macros
= 0;
10244 else if (strcmp (name
, "nomacro") == 0)
10246 if (mips_opts
.noreorder
== 0)
10247 as_bad (_("`noreorder' must be set before `nomacro'"));
10248 mips_opts
.warn_about_macros
= 1;
10250 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10252 mips_opts
.nomove
= 0;
10254 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10256 mips_opts
.nomove
= 1;
10258 else if (strcmp (name
, "bopt") == 0)
10260 mips_opts
.nobopt
= 0;
10262 else if (strcmp (name
, "nobopt") == 0)
10264 mips_opts
.nobopt
= 1;
10266 else if (strcmp (name
, "mips16") == 0
10267 || strcmp (name
, "MIPS-16") == 0)
10268 mips_opts
.mips16
= 1;
10269 else if (strcmp (name
, "nomips16") == 0
10270 || strcmp (name
, "noMIPS-16") == 0)
10271 mips_opts
.mips16
= 0;
10272 else if (strncmp (name
, "mips", 4) == 0)
10276 /* Permit the user to change the ISA on the fly. Needless to
10277 say, misuse can cause serious problems. */
10278 isa
= atoi (name
+ 4);
10281 case 0: mips_opts
.isa
= file_mips_isa
; break;
10282 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10283 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10284 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10285 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10286 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10287 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10288 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10289 default: as_bad (_("unknown ISA level")); break;
10292 else if (strcmp (name
, "autoextend") == 0)
10293 mips_opts
.noautoextend
= 0;
10294 else if (strcmp (name
, "noautoextend") == 0)
10295 mips_opts
.noautoextend
= 1;
10296 else if (strcmp (name
, "push") == 0)
10298 struct mips_option_stack
*s
;
10300 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10301 s
->next
= mips_opts_stack
;
10302 s
->options
= mips_opts
;
10303 mips_opts_stack
= s
;
10305 else if (strcmp (name
, "pop") == 0)
10307 struct mips_option_stack
*s
;
10309 s
= mips_opts_stack
;
10311 as_bad (_(".set pop with no .set push"));
10314 /* If we're changing the reorder mode we need to handle
10315 delay slots correctly. */
10316 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10317 mips_emit_delays (true);
10318 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10320 if (prev_nop_frag
!= NULL
)
10322 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10323 * (mips_opts
.mips16
? 2 : 4));
10324 prev_nop_frag
= NULL
;
10328 mips_opts
= s
->options
;
10329 mips_opts_stack
= s
->next
;
10335 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10337 *input_line_pointer
= ch
;
10338 demand_empty_rest_of_line ();
10341 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10342 .option pic2. It means to generate SVR4 PIC calls. */
10345 s_abicalls (ignore
)
10346 int ignore ATTRIBUTE_UNUSED
;
10348 mips_pic
= SVR4_PIC
;
10349 if (USE_GLOBAL_POINTER_OPT
)
10351 if (g_switch_seen
&& g_switch_value
!= 0)
10352 as_warn (_("-G may not be used with SVR4 PIC code"));
10353 g_switch_value
= 0;
10355 bfd_set_gp_size (stdoutput
, 0);
10356 demand_empty_rest_of_line ();
10359 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10360 PIC code. It sets the $gp register for the function based on the
10361 function address, which is in the register named in the argument.
10362 This uses a relocation against _gp_disp, which is handled specially
10363 by the linker. The result is:
10364 lui $gp,%hi(_gp_disp)
10365 addiu $gp,$gp,%lo(_gp_disp)
10366 addu $gp,$gp,.cpload argument
10367 The .cpload argument is normally $25 == $t9. */
10371 int ignore ATTRIBUTE_UNUSED
;
10376 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10377 if (mips_pic
!= SVR4_PIC
)
10383 /* .cpload should be a in .set noreorder section. */
10384 if (mips_opts
.noreorder
== 0)
10385 as_warn (_(".cpload not in noreorder section"));
10387 ex
.X_op
= O_symbol
;
10388 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10389 ex
.X_op_symbol
= NULL
;
10390 ex
.X_add_number
= 0;
10392 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10393 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10395 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10396 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10397 (int) BFD_RELOC_LO16
);
10399 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10400 GP
, GP
, tc_get_register (0));
10402 demand_empty_rest_of_line ();
10405 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10406 offset from $sp. The offset is remembered, and after making a PIC
10407 call $gp is restored from that location. */
10410 s_cprestore (ignore
)
10411 int ignore ATTRIBUTE_UNUSED
;
10416 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10417 if (mips_pic
!= SVR4_PIC
)
10423 mips_cprestore_offset
= get_absolute_expression ();
10425 ex
.X_op
= O_constant
;
10426 ex
.X_add_symbol
= NULL
;
10427 ex
.X_op_symbol
= NULL
;
10428 ex
.X_add_number
= mips_cprestore_offset
;
10430 macro_build ((char *) NULL
, &icnt
, &ex
,
10431 ((bfd_arch_bits_per_address (stdoutput
) == 32
10432 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10434 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10436 demand_empty_rest_of_line ();
10439 /* Handle the .gpword pseudo-op. This is used when generating PIC
10440 code. It generates a 32 bit GP relative reloc. */
10444 int ignore ATTRIBUTE_UNUSED
;
10450 /* When not generating PIC code, this is treated as .word. */
10451 if (mips_pic
!= SVR4_PIC
)
10457 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10458 mips_emit_delays (true);
10460 mips_align (2, 0, label
);
10461 mips_clear_insn_labels ();
10465 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10467 as_bad (_("Unsupported use of .gpword"));
10468 ignore_rest_of_line ();
10472 md_number_to_chars (p
, (valueT
) 0, 4);
10473 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10474 BFD_RELOC_MIPS_GPREL32
);
10476 demand_empty_rest_of_line ();
10479 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10480 tables in SVR4 PIC code. */
10484 int ignore ATTRIBUTE_UNUSED
;
10489 /* This is ignored when not generating SVR4 PIC code. */
10490 if (mips_pic
!= SVR4_PIC
)
10496 /* Add $gp to the register named as an argument. */
10497 reg
= tc_get_register (0);
10498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10499 ((bfd_arch_bits_per_address (stdoutput
) == 32
10500 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10501 ? "addu" : "daddu"),
10502 "d,v,t", reg
, reg
, GP
);
10504 demand_empty_rest_of_line ();
10507 /* Handle the .insn pseudo-op. This marks instruction labels in
10508 mips16 mode. This permits the linker to handle them specially,
10509 such as generating jalx instructions when needed. We also make
10510 them odd for the duration of the assembly, in order to generate the
10511 right sort of code. We will make them even in the adjust_symtab
10512 routine, while leaving them marked. This is convenient for the
10513 debugger and the disassembler. The linker knows to make them odd
10518 int ignore ATTRIBUTE_UNUSED
;
10520 if (mips_opts
.mips16
)
10521 mips16_mark_labels ();
10523 demand_empty_rest_of_line ();
10526 /* Handle a .stabn directive. We need these in order to mark a label
10527 as being a mips16 text label correctly. Sometimes the compiler
10528 will emit a label, followed by a .stabn, and then switch sections.
10529 If the label and .stabn are in mips16 mode, then the label is
10530 really a mips16 text label. */
10536 if (type
== 'n' && mips_opts
.mips16
)
10537 mips16_mark_labels ();
10542 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10546 s_mips_weakext (ignore
)
10547 int ignore ATTRIBUTE_UNUSED
;
10554 name
= input_line_pointer
;
10555 c
= get_symbol_end ();
10556 symbolP
= symbol_find_or_make (name
);
10557 S_SET_WEAK (symbolP
);
10558 *input_line_pointer
= c
;
10560 SKIP_WHITESPACE ();
10562 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10564 if (S_IS_DEFINED (symbolP
))
10566 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10567 S_GET_NAME (symbolP
));
10568 ignore_rest_of_line ();
10572 if (*input_line_pointer
== ',')
10574 ++input_line_pointer
;
10575 SKIP_WHITESPACE ();
10579 if (exp
.X_op
!= O_symbol
)
10581 as_bad ("bad .weakext directive");
10582 ignore_rest_of_line();
10585 symbol_set_value_expression (symbolP
, &exp
);
10588 demand_empty_rest_of_line ();
10591 /* Parse a register string into a number. Called from the ECOFF code
10592 to parse .frame. The argument is non-zero if this is the frame
10593 register, so that we can record it in mips_frame_reg. */
10596 tc_get_register (frame
)
10601 SKIP_WHITESPACE ();
10602 if (*input_line_pointer
++ != '$')
10604 as_warn (_("expected `$'"));
10607 else if (isdigit ((unsigned char) *input_line_pointer
))
10609 reg
= get_absolute_expression ();
10610 if (reg
< 0 || reg
>= 32)
10612 as_warn (_("Bad register number"));
10618 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10620 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10622 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10624 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10628 as_warn (_("Unrecognized register name"));
10631 input_line_pointer
+= 2;
10634 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10639 md_section_align (seg
, addr
)
10643 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10646 /* We don't need to align ELF sections to the full alignment.
10647 However, Irix 5 may prefer that we align them at least to a 16
10648 byte boundary. We don't bother to align the sections if we are
10649 targeted for an embedded system. */
10650 if (strcmp (TARGET_OS
, "elf") == 0)
10656 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10659 /* Utility routine, called from above as well. If called while the
10660 input file is still being read, it's only an approximation. (For
10661 example, a symbol may later become defined which appeared to be
10662 undefined earlier.) */
10665 nopic_need_relax (sym
, before_relaxing
)
10667 int before_relaxing
;
10672 if (USE_GLOBAL_POINTER_OPT
)
10674 const char *symname
;
10677 /* Find out whether this symbol can be referenced off the GP
10678 register. It can be if it is smaller than the -G size or if
10679 it is in the .sdata or .sbss section. Certain symbols can
10680 not be referenced off the GP, although it appears as though
10682 symname
= S_GET_NAME (sym
);
10683 if (symname
!= (const char *) NULL
10684 && (strcmp (symname
, "eprol") == 0
10685 || strcmp (symname
, "etext") == 0
10686 || strcmp (symname
, "_gp") == 0
10687 || strcmp (symname
, "edata") == 0
10688 || strcmp (symname
, "_fbss") == 0
10689 || strcmp (symname
, "_fdata") == 0
10690 || strcmp (symname
, "_ftext") == 0
10691 || strcmp (symname
, "end") == 0
10692 || strcmp (symname
, "_gp_disp") == 0))
10694 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10696 #ifndef NO_ECOFF_DEBUGGING
10697 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10698 && (symbol_get_obj (sym
)->ecoff_extern_size
10699 <= g_switch_value
))
10701 /* We must defer this decision until after the whole
10702 file has been read, since there might be a .extern
10703 after the first use of this symbol. */
10704 || (before_relaxing
10705 #ifndef NO_ECOFF_DEBUGGING
10706 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10708 && S_GET_VALUE (sym
) == 0)
10709 || (S_GET_VALUE (sym
) != 0
10710 && S_GET_VALUE (sym
) <= g_switch_value
)))
10714 const char *segname
;
10716 segname
= segment_name (S_GET_SEGMENT (sym
));
10717 assert (strcmp (segname
, ".lit8") != 0
10718 && strcmp (segname
, ".lit4") != 0);
10719 change
= (strcmp (segname
, ".sdata") != 0
10720 && strcmp (segname
, ".sbss") != 0
10721 && strncmp (segname
, ".sdata.", 7) != 0
10722 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10727 /* We are not optimizing for the GP register. */
10731 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10732 extended opcode. SEC is the section the frag is in. */
10735 mips16_extended_frag (fragp
, sec
, stretch
)
10741 register const struct mips16_immed_operand
*op
;
10743 int mintiny
, maxtiny
;
10746 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10748 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10751 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10752 op
= mips16_immed_operands
;
10753 while (op
->type
!= type
)
10756 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10761 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10764 maxtiny
= 1 << op
->nbits
;
10769 maxtiny
= (1 << op
->nbits
) - 1;
10774 mintiny
= - (1 << (op
->nbits
- 1));
10775 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10778 /* We can't always call S_GET_VALUE here, because we don't want to
10779 lock in a particular frag address. */
10780 if (symbol_constant_p (fragp
->fr_symbol
))
10782 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10783 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10784 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10786 else if (symbol_equated_p (fragp
->fr_symbol
)
10787 && (symbol_constant_p
10788 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10792 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10793 val
= (S_GET_VALUE (eqsym
)
10794 + symbol_get_frag (eqsym
)->fr_address
10795 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10796 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10797 symsec
= S_GET_SEGMENT (eqsym
);
10806 /* We won't have the section when we are called from
10807 mips_relax_frag. However, we will always have been called
10808 from md_estimate_size_before_relax first. If this is a
10809 branch to a different section, we mark it as such. If SEC is
10810 NULL, and the frag is not marked, then it must be a branch to
10811 the same section. */
10814 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10821 fragp
->fr_subtype
=
10822 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10824 /* FIXME: We should support this, and let the linker
10825 catch branches and loads that are out of range. */
10826 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10827 _("unsupported PC relative reference to different section"));
10833 /* In this case, we know for sure that the symbol fragment is in
10834 the same section. If the fr_address of the symbol fragment
10835 is greater then the address of this fragment we want to add
10836 in STRETCH in order to get a better estimate of the address.
10837 This particularly matters because of the shift bits. */
10839 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10840 >= fragp
->fr_address
))
10844 /* Adjust stretch for any alignment frag. Note that if have
10845 been expanding the earlier code, the symbol may be
10846 defined in what appears to be an earlier frag. FIXME:
10847 This doesn't handle the fr_subtype field, which specifies
10848 a maximum number of bytes to skip when doing an
10851 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10854 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10857 stretch
= - ((- stretch
)
10858 & ~ ((1 << (int) f
->fr_offset
) - 1));
10860 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10869 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10871 /* The base address rules are complicated. The base address of
10872 a branch is the following instruction. The base address of a
10873 PC relative load or add is the instruction itself, but if it
10874 is in a delay slot (in which case it can not be extended) use
10875 the address of the instruction whose delay slot it is in. */
10876 if (type
== 'p' || type
== 'q')
10880 /* If we are currently assuming that this frag should be
10881 extended, then, the current address is two bytes
10883 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10886 /* Ignore the low bit in the target, since it will be set
10887 for a text label. */
10888 if ((val
& 1) != 0)
10891 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10893 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10896 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10898 /* Branch offsets have an implicit 0 in the lowest bit. */
10899 if (type
== 'p' || type
== 'q')
10902 /* If any of the shifted bits are set, we must use an extended
10903 opcode. If the address depends on the size of this
10904 instruction, this can lead to a loop, so we arrange to always
10905 use an extended opcode. We only check this when we are in
10906 the main relaxation loop, when SEC is NULL. */
10907 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10909 fragp
->fr_subtype
=
10910 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10914 /* If we are about to mark a frag as extended because the value
10915 is precisely maxtiny + 1, then there is a chance of an
10916 infinite loop as in the following code:
10921 In this case when the la is extended, foo is 0x3fc bytes
10922 away, so the la can be shrunk, but then foo is 0x400 away, so
10923 the la must be extended. To avoid this loop, we mark the
10924 frag as extended if it was small, and is about to become
10925 extended with a value of maxtiny + 1. */
10926 if (val
== ((maxtiny
+ 1) << op
->shift
)
10927 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10930 fragp
->fr_subtype
=
10931 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10935 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10936 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10938 if ((val
& ((1 << op
->shift
) - 1)) != 0
10939 || val
< (mintiny
<< op
->shift
)
10940 || val
> (maxtiny
<< op
->shift
))
10946 /* Estimate the size of a frag before relaxing. Unless this is the
10947 mips16, we are not really relaxing here, and the final size is
10948 encoded in the subtype information. For the mips16, we have to
10949 decide whether we are using an extended opcode or not. */
10952 md_estimate_size_before_relax (fragp
, segtype
)
10957 boolean linkonce
= false;
10959 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10961 if (mips16_extended_frag (fragp
, segtype
, 0))
10963 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10968 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10973 if (mips_pic
== NO_PIC
)
10975 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10977 else if (mips_pic
== SVR4_PIC
)
10982 sym
= fragp
->fr_symbol
;
10984 /* Handle the case of a symbol equated to another symbol. */
10985 while (symbol_equated_p (sym
)
10986 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10990 /* It's possible to get a loop here in a badly written
10992 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10998 symsec
= S_GET_SEGMENT (sym
);
11000 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11001 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11003 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11007 /* The GNU toolchain uses an extension for ELF: a section
11008 beginning with the magic string .gnu.linkonce is a linkonce
11010 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11011 sizeof ".gnu.linkonce" - 1) == 0)
11015 /* This must duplicate the test in adjust_reloc_syms. */
11016 change
= (symsec
!= &bfd_und_section
11017 && symsec
!= &bfd_abs_section
11018 && ! bfd_is_com_section (symsec
)
11021 /* A weak symbol is treated as external. */
11022 && ! S_IS_WEAK (sym
)
11031 /* Record the offset to the first reloc in the fr_opcode field.
11032 This lets md_convert_frag and tc_gen_reloc know that the code
11033 must be expanded. */
11034 fragp
->fr_opcode
= (fragp
->fr_literal
11036 - RELAX_OLD (fragp
->fr_subtype
)
11037 + RELAX_RELOC1 (fragp
->fr_subtype
));
11038 /* FIXME: This really needs as_warn_where. */
11039 if (RELAX_WARN (fragp
->fr_subtype
))
11040 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11046 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11049 /* This is called to see whether a reloc against a defined symbol
11050 should be converted into a reloc against a section. Don't adjust
11051 MIPS16 jump relocations, so we don't have to worry about the format
11052 of the offset in the .o file. Don't adjust relocations against
11053 mips16 symbols, so that the linker can find them if it needs to set
11057 mips_fix_adjustable (fixp
)
11060 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11062 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11063 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11065 if (fixp
->fx_addsy
== NULL
)
11068 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11069 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11070 && fixp
->fx_subsy
== NULL
)
11076 /* Translate internal representation of relocation info to BFD target
11080 tc_gen_reloc (section
, fixp
)
11081 asection
*section ATTRIBUTE_UNUSED
;
11084 static arelent
*retval
[4];
11086 bfd_reloc_code_real_type code
;
11088 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11091 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11092 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11093 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11095 if (mips_pic
== EMBEDDED_PIC
11096 && SWITCH_TABLE (fixp
))
11098 /* For a switch table entry we use a special reloc. The addend
11099 is actually the difference between the reloc address and the
11101 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11102 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11103 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11104 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11106 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11107 reloc
->addend
= fixp
->fx_addnumber
;
11108 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11110 /* We use a special addend for an internal RELLO reloc. */
11111 if (symbol_section_p (fixp
->fx_addsy
))
11112 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11114 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11116 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11118 assert (fixp
->fx_next
!= NULL
11119 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11120 /* We use a special addend for an internal RELHI reloc. The
11121 reloc is relative to the RELLO; adjust the addend
11123 if (symbol_section_p (fixp
->fx_addsy
))
11124 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11125 + fixp
->fx_next
->fx_where
11126 - S_GET_VALUE (fixp
->fx_subsy
));
11128 reloc
->addend
= (fixp
->fx_addnumber
11129 + fixp
->fx_next
->fx_frag
->fr_address
11130 + fixp
->fx_next
->fx_where
);
11134 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11135 /* A gruesome hack which is a result of the gruesome gas reloc
11137 reloc
->addend
= reloc
->address
;
11139 reloc
->addend
= -reloc
->address
;
11142 /* If this is a variant frag, we may need to adjust the existing
11143 reloc and generate a new one. */
11144 if (fixp
->fx_frag
->fr_opcode
!= NULL
11145 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11146 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11147 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11148 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11149 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11150 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11151 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11155 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11157 /* If this is not the last reloc in this frag, then we have two
11158 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11159 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11160 the second one handle all of them. */
11161 if (fixp
->fx_next
!= NULL
11162 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11164 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11165 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11166 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11167 && (fixp
->fx_next
->fx_r_type
11168 == BFD_RELOC_MIPS_GOT_LO16
))
11169 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11170 && (fixp
->fx_next
->fx_r_type
11171 == BFD_RELOC_MIPS_CALL_LO16
)));
11176 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11177 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11178 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11180 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11181 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11182 reloc2
->address
= (reloc
->address
11183 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11184 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11185 reloc2
->addend
= fixp
->fx_addnumber
;
11186 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11187 assert (reloc2
->howto
!= NULL
);
11189 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11193 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11196 reloc3
->address
+= 4;
11199 if (mips_pic
== NO_PIC
)
11201 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11202 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11204 else if (mips_pic
== SVR4_PIC
)
11206 switch (fixp
->fx_r_type
)
11210 case BFD_RELOC_MIPS_GOT16
:
11212 case BFD_RELOC_MIPS_CALL16
:
11213 case BFD_RELOC_MIPS_GOT_LO16
:
11214 case BFD_RELOC_MIPS_CALL_LO16
:
11215 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11223 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11224 to be used in the relocation's section offset. */
11225 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11227 reloc
->address
= reloc
->addend
;
11231 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11232 fixup_segment converted a non-PC relative reloc into a PC
11233 relative reloc. In such a case, we need to convert the reloc
11235 code
= fixp
->fx_r_type
;
11236 if (fixp
->fx_pcrel
)
11241 code
= BFD_RELOC_8_PCREL
;
11244 code
= BFD_RELOC_16_PCREL
;
11247 code
= BFD_RELOC_32_PCREL
;
11250 code
= BFD_RELOC_64_PCREL
;
11252 case BFD_RELOC_8_PCREL
:
11253 case BFD_RELOC_16_PCREL
:
11254 case BFD_RELOC_32_PCREL
:
11255 case BFD_RELOC_64_PCREL
:
11256 case BFD_RELOC_16_PCREL_S2
:
11257 case BFD_RELOC_PCREL_HI16_S
:
11258 case BFD_RELOC_PCREL_LO16
:
11261 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11262 _("Cannot make %s relocation PC relative"),
11263 bfd_get_reloc_code_name (code
));
11267 /* To support a PC relative reloc when generating embedded PIC code
11268 for ECOFF, we use a Cygnus extension. We check for that here to
11269 make sure that we don't let such a reloc escape normally. */
11270 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11271 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11272 && code
== BFD_RELOC_16_PCREL_S2
11273 && mips_pic
!= EMBEDDED_PIC
)
11274 reloc
->howto
= NULL
;
11276 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11278 if (reloc
->howto
== NULL
)
11280 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11281 _("Can not represent %s relocation in this object file format"),
11282 bfd_get_reloc_code_name (code
));
11289 /* Relax a machine dependent frag. This returns the amount by which
11290 the current size of the frag should change. */
11293 mips_relax_frag (fragp
, stretch
)
11297 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11300 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11302 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11304 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11309 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11311 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11318 /* Convert a machine dependent frag. */
11321 md_convert_frag (abfd
, asec
, fragp
)
11322 bfd
*abfd ATTRIBUTE_UNUSED
;
11329 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11332 register const struct mips16_immed_operand
*op
;
11333 boolean small
, ext
;
11336 unsigned long insn
;
11337 boolean use_extend
;
11338 unsigned short extend
;
11340 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11341 op
= mips16_immed_operands
;
11342 while (op
->type
!= type
)
11345 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11356 resolve_symbol_value (fragp
->fr_symbol
, finalize_syms
);
11357 val
= S_GET_VALUE (fragp
->fr_symbol
);
11362 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11364 /* The rules for the base address of a PC relative reloc are
11365 complicated; see mips16_extended_frag. */
11366 if (type
== 'p' || type
== 'q')
11371 /* Ignore the low bit in the target, since it will be
11372 set for a text label. */
11373 if ((val
& 1) != 0)
11376 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11378 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11381 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11384 /* Make sure the section winds up with the alignment we have
11387 record_alignment (asec
, op
->shift
);
11391 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11392 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11393 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11394 _("extended instruction in delay slot"));
11396 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11398 if (target_big_endian
)
11399 insn
= bfd_getb16 (buf
);
11401 insn
= bfd_getl16 (buf
);
11403 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11404 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11405 small
, ext
, &insn
, &use_extend
, &extend
);
11409 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11410 fragp
->fr_fix
+= 2;
11414 md_number_to_chars (buf
, insn
, 2);
11415 fragp
->fr_fix
+= 2;
11420 if (fragp
->fr_opcode
== NULL
)
11423 old
= RELAX_OLD (fragp
->fr_subtype
);
11424 new = RELAX_NEW (fragp
->fr_subtype
);
11425 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11428 memcpy (fixptr
- old
, fixptr
, new);
11430 fragp
->fr_fix
+= new - old
;
11436 /* This function is called after the relocs have been generated.
11437 We've been storing mips16 text labels as odd. Here we convert them
11438 back to even for the convenience of the debugger. */
11441 mips_frob_file_after_relocs ()
11444 unsigned int count
, i
;
11446 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11449 syms
= bfd_get_outsymbols (stdoutput
);
11450 count
= bfd_get_symcount (stdoutput
);
11451 for (i
= 0; i
< count
; i
++, syms
++)
11453 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11454 && ((*syms
)->value
& 1) != 0)
11456 (*syms
)->value
&= ~1;
11457 /* If the symbol has an odd size, it was probably computed
11458 incorrectly, so adjust that as well. */
11459 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11460 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11467 /* This function is called whenever a label is defined. It is used
11468 when handling branch delays; if a branch has a label, we assume we
11469 can not move it. */
11472 mips_define_label (sym
)
11475 struct insn_label_list
*l
;
11477 if (free_insn_labels
== NULL
)
11478 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11481 l
= free_insn_labels
;
11482 free_insn_labels
= l
->next
;
11486 l
->next
= insn_labels
;
11490 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11492 /* Some special processing for a MIPS ELF file. */
11495 mips_elf_final_processing ()
11497 /* Write out the register information. */
11502 s
.ri_gprmask
= mips_gprmask
;
11503 s
.ri_cprmask
[0] = mips_cprmask
[0];
11504 s
.ri_cprmask
[1] = mips_cprmask
[1];
11505 s
.ri_cprmask
[2] = mips_cprmask
[2];
11506 s
.ri_cprmask
[3] = mips_cprmask
[3];
11507 /* The gp_value field is set by the MIPS ELF backend. */
11509 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11510 ((Elf32_External_RegInfo
*)
11511 mips_regmask_frag
));
11515 Elf64_Internal_RegInfo s
;
11517 s
.ri_gprmask
= mips_gprmask
;
11519 s
.ri_cprmask
[0] = mips_cprmask
[0];
11520 s
.ri_cprmask
[1] = mips_cprmask
[1];
11521 s
.ri_cprmask
[2] = mips_cprmask
[2];
11522 s
.ri_cprmask
[3] = mips_cprmask
[3];
11523 /* The gp_value field is set by the MIPS ELF backend. */
11525 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11526 ((Elf64_External_RegInfo
*)
11527 mips_regmask_frag
));
11530 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11531 sort of BFD interface for this. */
11532 if (mips_any_noreorder
)
11533 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11534 if (mips_pic
!= NO_PIC
)
11535 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11537 /* Set the MIPS ELF ABI flags. */
11538 if (mips_abi_string
== 0)
11540 else if (strcmp (mips_abi_string
, "32") == 0)
11541 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11542 else if (strcmp (mips_abi_string
, "o64") == 0)
11543 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11544 else if (strcmp (mips_abi_string
, "eabi") == 0)
11547 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11549 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11552 if (mips_32bitmode
)
11553 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11556 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11558 typedef struct proc
{
11560 unsigned long reg_mask
;
11561 unsigned long reg_offset
;
11562 unsigned long fpreg_mask
;
11563 unsigned long fpreg_offset
;
11564 unsigned long frame_offset
;
11565 unsigned long frame_reg
;
11566 unsigned long pc_reg
;
11569 static procS cur_proc
;
11570 static procS
*cur_proc_ptr
;
11571 static int numprocs
;
11573 /* Fill in an rs_align_code fragment. */
11576 mips_handle_align (fragp
)
11579 if (fragp
->fr_type
!= rs_align_code
)
11582 if (mips_opts
.mips16
)
11584 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11585 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11590 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
11591 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
11596 fragp
->fr_fix
+= 1;
11599 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
11603 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
11614 /* check for premature end, nesting errors, etc */
11616 as_warn (_("missing `.end' at end of assembly"));
11625 if (*input_line_pointer
== '-')
11627 ++input_line_pointer
;
11630 if (!isdigit ((unsigned char) *input_line_pointer
))
11631 as_bad (_("Expected simple number."));
11632 if (input_line_pointer
[0] == '0')
11634 if (input_line_pointer
[1] == 'x')
11636 input_line_pointer
+= 2;
11637 while (isxdigit ((unsigned char) *input_line_pointer
))
11640 val
|= hex_value (*input_line_pointer
++);
11642 return negative
? -val
: val
;
11646 ++input_line_pointer
;
11647 while (isdigit ((unsigned char) *input_line_pointer
))
11650 val
|= *input_line_pointer
++ - '0';
11652 return negative
? -val
: val
;
11655 if (!isdigit ((unsigned char) *input_line_pointer
))
11657 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11658 *input_line_pointer
, *input_line_pointer
);
11659 as_warn (_("Invalid number"));
11662 while (isdigit ((unsigned char) *input_line_pointer
))
11665 val
+= *input_line_pointer
++ - '0';
11667 return negative
? -val
: val
;
11670 /* The .file directive; just like the usual .file directive, but there
11671 is an initial number which is the ECOFF file index. */
11675 int x ATTRIBUTE_UNUSED
;
11679 line
= get_number ();
11683 /* The .end directive. */
11687 int x ATTRIBUTE_UNUSED
;
11692 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11695 demand_empty_rest_of_line ();
11700 #ifdef BFD_ASSEMBLER
11701 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11706 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11713 as_warn (_(".end not in text section"));
11717 as_warn (_(".end directive without a preceding .ent directive."));
11718 demand_empty_rest_of_line ();
11724 assert (S_GET_NAME (p
));
11725 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11726 as_warn (_(".end symbol does not match .ent symbol."));
11729 as_warn (_(".end directive missing or unknown symbol"));
11731 #ifdef MIPS_STABS_ELF
11733 segT saved_seg
= now_seg
;
11734 subsegT saved_subseg
= now_subseg
;
11735 fragS
*saved_frag
= frag_now
;
11741 dot
= frag_now_fix ();
11743 #ifdef md_flush_pending_output
11744 md_flush_pending_output ();
11748 subseg_set (pdr_seg
, 0);
11750 /* Write the symbol. */
11751 exp
.X_op
= O_symbol
;
11752 exp
.X_add_symbol
= p
;
11753 exp
.X_add_number
= 0;
11754 emit_expr (&exp
, 4);
11756 fragp
= frag_more (7 * 4);
11758 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11759 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11760 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11761 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11762 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11763 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11764 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11766 subseg_set (saved_seg
, saved_subseg
);
11770 cur_proc_ptr
= NULL
;
11773 /* The .aent and .ent directives. */
11783 symbolP
= get_symbol ();
11784 if (*input_line_pointer
== ',')
11785 input_line_pointer
++;
11786 SKIP_WHITESPACE ();
11787 if (isdigit ((unsigned char) *input_line_pointer
)
11788 || *input_line_pointer
== '-')
11789 number
= get_number ();
11791 #ifdef BFD_ASSEMBLER
11792 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11797 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11804 as_warn (_(".ent or .aent not in text section."));
11806 if (!aent
&& cur_proc_ptr
)
11807 as_warn (_("missing `.end'"));
11811 cur_proc_ptr
= &cur_proc
;
11812 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11814 cur_proc_ptr
->isym
= symbolP
;
11816 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11821 demand_empty_rest_of_line ();
11824 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11825 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11826 s_mips_frame is used so that we can set the PDR information correctly.
11827 We can't use the ecoff routines because they make reference to the ecoff
11828 symbol table (in the mdebug section). */
11831 s_mips_frame (ignore
)
11834 #ifdef MIPS_STABS_ELF
11838 if (cur_proc_ptr
== (procS
*) NULL
)
11840 as_warn (_(".frame outside of .ent"));
11841 demand_empty_rest_of_line ();
11845 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11847 SKIP_WHITESPACE ();
11848 if (*input_line_pointer
++ != ','
11849 || get_absolute_expression_and_terminator (&val
) != ',')
11851 as_warn (_("Bad .frame directive"));
11852 --input_line_pointer
;
11853 demand_empty_rest_of_line ();
11857 cur_proc_ptr
->frame_offset
= val
;
11858 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11860 demand_empty_rest_of_line ();
11863 #endif /* MIPS_STABS_ELF */
11866 /* The .fmask and .mask directives. If the mdebug section is present
11867 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11868 embedded targets, s_mips_mask is used so that we can set the PDR
11869 information correctly. We can't use the ecoff routines because they
11870 make reference to the ecoff symbol table (in the mdebug section). */
11873 s_mips_mask (reg_type
)
11876 #ifdef MIPS_STABS_ELF
11879 if (cur_proc_ptr
== (procS
*) NULL
)
11881 as_warn (_(".mask/.fmask outside of .ent"));
11882 demand_empty_rest_of_line ();
11886 if (get_absolute_expression_and_terminator (&mask
) != ',')
11888 as_warn (_("Bad .mask/.fmask directive"));
11889 --input_line_pointer
;
11890 demand_empty_rest_of_line ();
11894 off
= get_absolute_expression ();
11896 if (reg_type
== 'F')
11898 cur_proc_ptr
->fpreg_mask
= mask
;
11899 cur_proc_ptr
->fpreg_offset
= off
;
11903 cur_proc_ptr
->reg_mask
= mask
;
11904 cur_proc_ptr
->reg_offset
= off
;
11907 demand_empty_rest_of_line ();
11909 s_ignore (reg_type
);
11910 #endif /* MIPS_STABS_ELF */
11913 /* The .loc directive. */
11924 assert (now_seg
== text_section
);
11926 lineno
= get_number ();
11927 addroff
= frag_now_fix ();
11929 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11930 S_SET_TYPE (symbolP
, N_SLINE
);
11931 S_SET_OTHER (symbolP
, 0);
11932 S_SET_DESC (symbolP
, lineno
);
11933 symbolP
->sy_segment
= now_seg
;
11937 /* CPU name/ISA/number mapping table.
11939 Entries are grouped by type. The first matching CPU or ISA entry
11940 gets chosen by CPU or ISA, so it should be the 'canonical' name
11941 for that type. Entries after that within the type are sorted
11944 Case is ignored in comparison, so put the canonical entry in the
11945 appropriate case but everything else in lower case to ease eye pain. */
11946 static const struct mips_cpu_info mips_cpu_info_table
[] =
11949 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
11950 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
11953 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
11956 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
11959 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
11962 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
11963 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
11966 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
11967 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
11970 /* XXX for now, MIPS64 -> MIPS3 because of history */
11971 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
}, /* XXX! */
11974 { "MIPS64", 1, ISA_MIPS64
, CPU_MIPS64
},
11976 { "mips64isa", 1, ISA_MIPS64
, CPU_MIPS64
},
11977 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
11980 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
11981 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
11982 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
11983 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
11986 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
11987 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
11988 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
11989 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
11992 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
11993 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
11994 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
11997 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
11998 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
11999 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12000 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12003 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12004 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12007 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12008 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12011 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12012 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12013 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12014 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12017 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12018 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12021 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12022 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12023 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12024 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12027 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12028 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12029 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12030 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12033 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12034 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12035 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12036 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12039 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12040 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12041 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12042 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12045 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12046 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12047 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12048 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12051 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12052 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12053 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12054 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12057 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12058 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12059 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12060 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12061 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12062 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12063 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12064 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12065 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12066 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12067 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12068 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12070 /* MIPS32 4K CPU */
12071 { "MIPS32-4K", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12072 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12073 { "4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12074 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12075 { "mips32-4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12076 { "mips32-4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12077 { "mips32-4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12079 /* SiByte SB-1 CPU */
12080 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12081 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12082 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12083 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12086 { NULL
, 0, 0, 0, },
12089 static const struct mips_cpu_info
*
12090 mips_cpu_info_from_name (name
)
12095 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12096 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12097 return (&mips_cpu_info_table
[i
]);
12102 static const struct mips_cpu_info
*
12103 mips_cpu_info_from_isa (isa
)
12108 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12109 if (mips_cpu_info_table
[i
].is_isa
12110 && isa
== mips_cpu_info_table
[i
].isa
)
12111 return (&mips_cpu_info_table
[i
]);
12116 static const struct mips_cpu_info
*
12117 mips_cpu_info_from_cpu (cpu
)
12122 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12123 if (!mips_cpu_info_table
[i
].is_isa
12124 && cpu
== mips_cpu_info_table
[i
].cpu
)
12125 return (&mips_cpu_info_table
[i
]);