1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 FIXME: The CPU specific variables (mips_4010, et. al.) should
146 probably be in here as well, and there should probably be some way
149 struct mips_set_options
151 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
152 if it has not been initialized. Changed by `.set mipsN', and the
153 -mipsN command line option, and the default CPU. */
155 /* Whether we are assembling for the mips16 processor. 0 if we are
156 not, 1 if we are, and -1 if the value has not been initialized.
157 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
158 -nomips16 command line options, and the default CPU. */
160 /* Non-zero if we should not reorder instructions. Changed by `.set
161 reorder' and `.set noreorder'. */
163 /* Non-zero if we should not permit the $at ($1) register to be used
164 in instructions. Changed by `.set at' and `.set noat'. */
166 /* Non-zero if we should warn when a macro instruction expands into
167 more than one machine instruction. Changed by `.set nomacro' and
169 int warn_about_macros
;
170 /* Non-zero if we should not move instructions. Changed by `.set
171 move', `.set volatile', `.set nomove', and `.set novolatile'. */
173 /* Non-zero if we should not optimize branches by moving the target
174 of the branch into the delay slot. Actually, we don't perform
175 this optimization anyhow. Changed by `.set bopt' and `.set
178 /* Non-zero if we should not autoextend mips16 instructions.
179 Changed by `.set autoextend' and `.set noautoextend'. */
183 /* This is the struct we use to hold the current set of options. Note
184 that we must set the isa and mips16 fields to -1 to indicate that
185 they have not been initialized. */
187 static struct mips_set_options mips_opts
= { -1, -1 };
189 /* These variables are filled in with the masks of registers used.
190 The object format code reads them and puts them in the appropriate
192 unsigned long mips_gprmask
;
193 unsigned long mips_cprmask
[4];
195 /* MIPS ISA we are using for this output file. */
196 static int file_mips_isa
;
198 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
199 static int mips_cpu
= -1;
201 /* The argument of the -mabi= flag. */
202 static char* mips_abi_string
= 0;
204 /* Wether we should mark the file EABI64 or EABI32. */
205 static int mips_eabi64
= 0;
207 /* Whether the 4650 instructions (mad/madu) are permitted. */
208 static int mips_4650
= -1;
210 /* Whether the 4010 instructions are permitted. */
211 static int mips_4010
= -1;
213 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
214 static int mips_4100
= -1;
216 /* start-sanitize-vr4xxx */
217 /* Whether NEC 4121 instructions are permitted. */
218 static int mips_4121
= -1;
220 /* end-sanitize-vr4xxx */
221 /* start-sanitize-vr4320 */
222 /* Whether NEC vr4320 instructions are permitted. */
223 static int mips_4320
= -1;
225 /* end-sanitize-vr4320 */
226 /* start-sanitize-cygnus */
227 /* Whether NEC vr5400 instructions are permitted. */
228 static int mips_5400
= -1;
230 /* end-sanitize-cygnus */
231 /* start-sanitize-r5900 */
232 /* Whether Toshiba r5900 instructions are permitted. */
233 static int mips_5900
= -1;
235 /* end-sanitize-r5900 */
236 /* Whether Toshiba r3900 instructions are permitted. */
237 static int mips_3900
= -1;
239 /* start-sanitize-tx49 */
240 /* Whether Toshiba r4900 instructions are permitted. */
241 static int mips_4900
= -1;
243 /* end-sanitize-tx49 */
244 /* start-sanitize-tx19 */
245 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
246 The tx19 related options and configuration bits are handled by
248 /* end-sanitize-tx19 */
250 /* Whether the processor uses hardware interlocks to protect
251 reads from the HI and LO registers, and thus does not
252 require nops to be inserted.
254 FIXME: We really should not be checking mips_cpu here. The -mcpu=
255 option is documented to not do anything special. In gcc, the
256 -mcpu= option only affects scheduling, and does not affect code
257 generation. Each test of -mcpu= here should actually be testing a
258 specific variable, such as mips_4010, and each such variable should
259 have a command line option to set it. The -mcpu= option may be
260 used to set the default value of these options, as is the case for
263 #define hilo_interlocks (mips_4010 \
264 /* start-sanitize-tx49 */ \
265 || mips_cpu == 4900 || mips_4900 \
266 /* end-sanitize-tx49 */ \
267 /* start-sanitize-vr4320 */ \
268 || mips_cpu == 4320 \
269 /* end-sanitize-vr4320 */ \
270 /* start-sanitize-r5900 */ \
272 /* end-sanitize-r5900 */ \
275 /* Whether the processor uses hardware interlocks to protect reads
276 from the GPRs, and thus does not require nops to be inserted. */
277 #define gpr_interlocks \
278 (mips_opts.isa >= 2 \
279 /* start-sanitize-cygnus */ \
281 /* end-sanitize-cygnus */ \
282 /* start-sanitize-r5900 */ \
284 /* end-sanitize-r5900 */ \
287 /* As with other "interlocks" this is used by hardware that has FP
288 (co-processor) interlocks. */
289 /* Itbl support may require additional care here. */
290 #define cop_interlocks (mips_cpu == 4300 \
291 /* start-sanitize-vr4320 */ \
292 || mips_cpu == 4320 \
293 /* end-sanitize-vr4320 */ \
294 /* start-sanitize-cygnus */ \
295 || mips_cpu == 5400 \
296 /* end-sanitize-cygnus */ \
299 /* MIPS PIC level. */
303 /* Do not generate PIC code. */
306 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
307 not sure what it is supposed to do. */
310 /* Generate PIC code as in the SVR4 MIPS ABI. */
313 /* Generate PIC code without using a global offset table: the data
314 segment has a maximum size of 64K, all data references are off
315 the $gp register, and all text references are PC relative. This
316 is used on some embedded systems. */
320 static enum mips_pic_level mips_pic
;
322 /* 1 if we should generate 32 bit offsets from the GP register in
323 SVR4_PIC mode. Currently has no meaning in other modes. */
324 static int mips_big_got
;
326 /* 1 if trap instructions should used for overflow rather than break
328 static int mips_trap
;
330 /* Non-zero if any .set noreorder directives were used. */
332 static int mips_any_noreorder
;
334 /* The size of the small data section. */
335 static int g_switch_value
= 8;
336 /* Whether the -G option was used. */
337 static int g_switch_seen
= 0;
342 /* If we can determine in advance that GP optimization won't be
343 possible, we can skip the relaxation stuff that tries to produce
344 GP-relative references. This makes delay slot optimization work
347 This function can only provide a guess, but it seems to work for
348 gcc output. If it guesses wrong, the only loss should be in
349 efficiency; it shouldn't introduce any bugs.
351 I don't know if a fix is needed for the SVR4_PIC mode. I've only
352 fixed it for the non-PIC mode. KR 95/04/07 */
353 static int nopic_need_relax
PARAMS ((symbolS
*, int));
355 /* handle of the OPCODE hash table */
356 static struct hash_control
*op_hash
= NULL
;
358 /* The opcode hash table we use for the mips16. */
359 static struct hash_control
*mips16_op_hash
= NULL
;
361 /* This array holds the chars that always start a comment. If the
362 pre-processor is disabled, these aren't very useful */
363 const char comment_chars
[] = "#";
365 /* This array holds the chars that only start a comment at the beginning of
366 a line. If the line seems to have the form '# 123 filename'
367 .line and .file directives will appear in the pre-processed output */
368 /* Note that input_file.c hand checks for '#' at the beginning of the
369 first line of the input file. This is because the compiler outputs
370 #NO_APP at the beginning of its output. */
371 /* Also note that C style comments are always supported. */
372 const char line_comment_chars
[] = "#";
374 /* This array holds machine specific line separator characters. */
375 const char line_separator_chars
[] = "";
377 /* Chars that can be used to separate mant from exp in floating point nums */
378 const char EXP_CHARS
[] = "eE";
380 /* Chars that mean this number is a floating point constant */
383 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
385 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
386 changed in read.c . Ideally it shouldn't have to know about it at all,
387 but nothing is ideal around here.
390 static char *insn_error
;
392 static int auto_align
= 1;
394 /* When outputting SVR4 PIC code, the assembler needs to know the
395 offset in the stack frame from which to restore the $gp register.
396 This is set by the .cprestore pseudo-op, and saved in this
398 static offsetT mips_cprestore_offset
= -1;
400 /* This is the register which holds the stack frame, as set by the
401 .frame pseudo-op. This is needed to implement .cprestore. */
402 static int mips_frame_reg
= SP
;
404 /* To output NOP instructions correctly, we need to keep information
405 about the previous two instructions. */
407 /* Whether we are optimizing. The default value of 2 means to remove
408 unneeded NOPs and swap branch instructions when possible. A value
409 of 1 means to not swap branches. A value of 0 means to always
411 static int mips_optimize
= 2;
413 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
414 equivalent to seeing no -g option at all. */
415 static int mips_debug
= 0;
417 /* The previous instruction. */
418 static struct mips_cl_insn prev_insn
;
420 /* The instruction before prev_insn. */
421 static struct mips_cl_insn prev_prev_insn
;
423 /* If we don't want information for prev_insn or prev_prev_insn, we
424 point the insn_mo field at this dummy integer. */
425 static const struct mips_opcode dummy_opcode
= { 0 };
427 /* Non-zero if prev_insn is valid. */
428 static int prev_insn_valid
;
430 /* The frag for the previous instruction. */
431 static struct frag
*prev_insn_frag
;
433 /* The offset into prev_insn_frag for the previous instruction. */
434 static long prev_insn_where
;
436 /* The reloc type for the previous instruction, if any. */
437 static bfd_reloc_code_real_type prev_insn_reloc_type
;
439 /* The reloc for the previous instruction, if any. */
440 static fixS
*prev_insn_fixp
;
442 /* Non-zero if the previous instruction was in a delay slot. */
443 static int prev_insn_is_delay_slot
;
445 /* Non-zero if the previous instruction was in a .set noreorder. */
446 static int prev_insn_unreordered
;
448 /* Non-zero if the previous instruction uses an extend opcode (if
450 static int prev_insn_extended
;
452 /* Non-zero if the previous previous instruction was in a .set
454 static int prev_prev_insn_unreordered
;
456 /* start-sanitize-branchbug4011 */
457 /* Non-zero if the previous insn had one or more labels */
458 static int prev_insn_labels
;
460 /* end-sanitize-branchbug4011 */
461 /* If this is set, it points to a frag holding nop instructions which
462 were inserted before the start of a noreorder section. If those
463 nops turn out to be unnecessary, the size of the frag can be
465 static fragS
*prev_nop_frag
;
467 /* The number of nop instructions we created in prev_nop_frag. */
468 static int prev_nop_frag_holds
;
470 /* The number of nop instructions that we know we need in
472 static int prev_nop_frag_required
;
474 /* The number of instructions we've seen since prev_nop_frag. */
475 static int prev_nop_frag_since
;
477 /* For ECOFF and ELF, relocations against symbols are done in two
478 parts, with a HI relocation and a LO relocation. Each relocation
479 has only 16 bits of space to store an addend. This means that in
480 order for the linker to handle carries correctly, it must be able
481 to locate both the HI and the LO relocation. This means that the
482 relocations must appear in order in the relocation table.
484 In order to implement this, we keep track of each unmatched HI
485 relocation. We then sort them so that they immediately precede the
486 corresponding LO relocation. */
491 struct mips_hi_fixup
*next
;
494 /* The section this fixup is in. */
498 /* The list of unmatched HI relocs. */
500 static struct mips_hi_fixup
*mips_hi_fixup_list
;
502 /* Map normal MIPS register numbers to mips16 register numbers. */
504 #define X ILLEGAL_REG
505 static const int mips32_to_16_reg_map
[] =
507 X
, X
, 2, 3, 4, 5, 6, 7,
508 X
, X
, X
, X
, X
, X
, X
, X
,
509 0, 1, X
, X
, X
, X
, X
, X
,
510 X
, X
, X
, X
, X
, X
, X
, X
514 /* Map mips16 register numbers to normal MIPS register numbers. */
516 static const int mips16_to_32_reg_map
[] =
518 16, 17, 2, 3, 4, 5, 6, 7
521 /* Since the MIPS does not have multiple forms of PC relative
522 instructions, we do not have to do relaxing as is done on other
523 platforms. However, we do have to handle GP relative addressing
524 correctly, which turns out to be a similar problem.
526 Every macro that refers to a symbol can occur in (at least) two
527 forms, one with GP relative addressing and one without. For
528 example, loading a global variable into a register generally uses
529 a macro instruction like this:
531 If i can be addressed off the GP register (this is true if it is in
532 the .sbss or .sdata section, or if it is known to be smaller than
533 the -G argument) this will generate the following instruction:
535 This instruction will use a GPREL reloc. If i can not be addressed
536 off the GP register, the following instruction sequence will be used:
539 In this case the first instruction will have a HI16 reloc, and the
540 second reloc will have a LO16 reloc. Both relocs will be against
543 The issue here is that we may not know whether i is GP addressable
544 until after we see the instruction that uses it. Therefore, we
545 want to be able to choose the final instruction sequence only at
546 the end of the assembly. This is similar to the way other
547 platforms choose the size of a PC relative instruction only at the
550 When generating position independent code we do not use GP
551 addressing in quite the same way, but the issue still arises as
552 external symbols and local symbols must be handled differently.
554 We handle these issues by actually generating both possible
555 instruction sequences. The longer one is put in a frag_var with
556 type rs_machine_dependent. We encode what to do with the frag in
557 the subtype field. We encode (1) the number of existing bytes to
558 replace, (2) the number of new bytes to use, (3) the offset from
559 the start of the existing bytes to the first reloc we must generate
560 (that is, the offset is applied from the start of the existing
561 bytes after they are replaced by the new bytes, if any), (4) the
562 offset from the start of the existing bytes to the second reloc,
563 (5) whether a third reloc is needed (the third reloc is always four
564 bytes after the second reloc), and (6) whether to warn if this
565 variant is used (this is sometimes needed if .set nomacro or .set
566 noat is in effect). All these numbers are reasonably small.
568 Generating two instruction sequences must be handled carefully to
569 ensure that delay slots are handled correctly. Fortunately, there
570 are a limited number of cases. When the second instruction
571 sequence is generated, append_insn is directed to maintain the
572 existing delay slot information, so it continues to apply to any
573 code after the second instruction sequence. This means that the
574 second instruction sequence must not impose any requirements not
575 required by the first instruction sequence.
577 These variant frags are then handled in functions called by the
578 machine independent code. md_estimate_size_before_relax returns
579 the final size of the frag. md_convert_frag sets up the final form
580 of the frag. tc_gen_reloc adjust the first reloc and adds a second
582 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
586 | (((reloc1) + 64) << 9) \
587 | (((reloc2) + 64) << 2) \
588 | ((reloc3) ? (1 << 1) : 0) \
590 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
591 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
592 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
593 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
594 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
595 #define RELAX_WARN(i) ((i) & 1)
597 /* For mips16 code, we use an entirely different form of relaxation.
598 mips16 supports two versions of most instructions which take
599 immediate values: a small one which takes some small value, and a
600 larger one which takes a 16 bit value. Since branches also follow
601 this pattern, relaxing these values is required.
603 We can assemble both mips16 and normal MIPS code in a single
604 object. Therefore, we need to support this type of relaxation at
605 the same time that we support the relaxation described above. We
606 use the high bit of the subtype field to distinguish these cases.
608 The information we store for this type of relaxation is the
609 argument code found in the opcode file for this relocation, whether
610 the user explicitly requested a small or extended form, and whether
611 the relocation is in a jump or jal delay slot. That tells us the
612 size of the value, and how it should be stored. We also store
613 whether the fragment is considered to be extended or not. We also
614 store whether this is known to be a branch to a different section,
615 whether we have tried to relax this frag yet, and whether we have
616 ever extended a PC relative fragment because of a shift count. */
617 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
620 | ((small) ? 0x100 : 0) \
621 | ((ext) ? 0x200 : 0) \
622 | ((dslot) ? 0x400 : 0) \
623 | ((jal_dslot) ? 0x800 : 0))
624 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
625 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
626 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
627 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
628 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
629 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
630 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
631 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
632 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
633 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
634 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
635 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
636 /* start-sanitize-branchbug4011 */
637 /* The 4011 core has a bug in it's branch processing that
638 an be avoided if branches never branches (where branches
639 are defined as those starting with 'b'). We do this here
640 by insuring that labels are not directly on branch instructions,
641 and if they are inserting a no-op between the label and the
643 static int mips_fix_4011_branch_bug
= 0;
644 /* end-sanitize-branchbug4011 */
646 /* Prototypes for static functions. */
649 #define internalError() \
650 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
652 #define internalError() as_fatal (_("MIPS internal Error"));
655 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
657 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
658 unsigned int reg
, enum mips_regclass
class));
659 static int reg_needs_delay
PARAMS ((int));
660 static void mips16_mark_labels
PARAMS ((void));
661 static void append_insn
PARAMS ((char *place
,
662 struct mips_cl_insn
* ip
,
664 bfd_reloc_code_real_type r
,
666 static void mips_no_prev_insn
PARAMS ((int));
667 static void mips_emit_delays
PARAMS ((boolean
));
669 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
670 const char *name
, const char *fmt
,
673 static void macro_build ();
675 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
676 const char *, const char *,
678 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
679 expressionS
* ep
, int regnum
));
680 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
681 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
683 static void load_register
PARAMS ((int *, int, expressionS
*, int));
684 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
685 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
686 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
687 #ifdef LOSING_COMPILER
688 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
690 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
691 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
692 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
693 boolean
, boolean
, unsigned long *,
694 boolean
*, unsigned short *));
695 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
696 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
697 static symbolS
*get_symbol
PARAMS ((void));
698 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
699 static void s_align
PARAMS ((int));
700 static void s_change_sec
PARAMS ((int));
701 static void s_cons
PARAMS ((int));
702 static void s_float_cons
PARAMS ((int));
703 static void s_mips_globl
PARAMS ((int));
704 static void s_option
PARAMS ((int));
705 static void s_mipsset
PARAMS ((int));
706 static void s_abicalls
PARAMS ((int));
707 static void s_cpload
PARAMS ((int));
708 static void s_cprestore
PARAMS ((int));
709 static void s_gpword
PARAMS ((int));
710 static void s_cpadd
PARAMS ((int));
711 static void s_insn
PARAMS ((int));
712 static void md_obj_begin
PARAMS ((void));
713 static void md_obj_end
PARAMS ((void));
714 static long get_number
PARAMS ((void));
715 static void s_mips_ent
PARAMS ((int));
716 static void s_mips_end
PARAMS ((int));
717 static void s_mips_frame
PARAMS ((int));
718 static void s_mips_mask
PARAMS ((int));
719 static void s_mips_stab
PARAMS ((int));
720 static void s_mips_weakext
PARAMS ((int));
721 static void s_file
PARAMS ((int));
722 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
725 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
729 The following pseudo-ops from the Kane and Heinrich MIPS book
730 should be defined here, but are currently unsupported: .alias,
731 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
733 The following pseudo-ops from the Kane and Heinrich MIPS book are
734 specific to the type of debugging information being generated, and
735 should be defined by the object format: .aent, .begin, .bend,
736 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
739 The following pseudo-ops from the Kane and Heinrich MIPS book are
740 not MIPS CPU specific, but are also not specific to the object file
741 format. This file is probably the best place to define them, but
742 they are not currently supported: .asm0, .endr, .lab, .repeat,
745 static const pseudo_typeS mips_pseudo_table
[] =
747 /* MIPS specific pseudo-ops. */
748 {"option", s_option
, 0},
749 {"set", s_mipsset
, 0},
750 {"rdata", s_change_sec
, 'r'},
751 {"sdata", s_change_sec
, 's'},
752 {"livereg", s_ignore
, 0},
753 {"abicalls", s_abicalls
, 0},
754 {"cpload", s_cpload
, 0},
755 {"cprestore", s_cprestore
, 0},
756 {"gpword", s_gpword
, 0},
757 {"cpadd", s_cpadd
, 0},
760 /* Relatively generic pseudo-ops that happen to be used on MIPS
762 {"asciiz", stringer
, 1},
763 {"bss", s_change_sec
, 'b'},
766 {"dword", s_cons
, 3},
767 {"weakext", s_mips_weakext
, 0},
769 /* These pseudo-ops are defined in read.c, but must be overridden
770 here for one reason or another. */
771 {"align", s_align
, 0},
773 {"data", s_change_sec
, 'd'},
774 {"double", s_float_cons
, 'd'},
775 {"float", s_float_cons
, 'f'},
776 {"globl", s_mips_globl
, 0},
777 {"global", s_mips_globl
, 0},
778 {"hword", s_cons
, 1},
783 {"short", s_cons
, 1},
784 {"single", s_float_cons
, 'f'},
785 {"stabn", s_mips_stab
, 'n'},
786 {"text", s_change_sec
, 't'},
791 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
792 /* These pseudo-ops should be defined by the object file format.
793 However, a.out doesn't support them, so we have versions here. */
794 {"aent", s_mips_ent
, 1},
795 {"bgnb", s_ignore
, 0},
796 {"end", s_mips_end
, 0},
797 {"endb", s_ignore
, 0},
798 {"ent", s_mips_ent
, 0},
800 {"fmask", s_mips_mask
, 'F'},
801 {"frame", s_mips_frame
, 0},
802 {"loc", s_ignore
, 0},
803 {"mask", s_mips_mask
, 'R'},
804 {"verstamp", s_ignore
, 0},
808 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
813 pop_insert (mips_pseudo_table
);
814 if (! ECOFF_DEBUGGING
)
815 pop_insert (mips_nonecoff_pseudo_table
);
818 /* Symbols labelling the current insn. */
820 struct insn_label_list
822 struct insn_label_list
*next
;
826 static struct insn_label_list
*insn_labels
;
827 static struct insn_label_list
*free_insn_labels
;
829 static void mips_clear_insn_labels
PARAMS ((void));
832 mips_clear_insn_labels ()
834 register struct insn_label_list
**pl
;
836 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
842 static char *expr_end
;
844 /* Expressions which appear in instructions. These are set by
847 static expressionS imm_expr
;
848 static expressionS offset_expr
;
850 /* Relocs associated with imm_expr and offset_expr. */
852 static bfd_reloc_code_real_type imm_reloc
;
853 static bfd_reloc_code_real_type offset_reloc
;
855 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
857 static boolean imm_unmatched_hi
;
859 /* These are set by mips16_ip if an explicit extension is used. */
861 static boolean mips16_small
, mips16_ext
;
863 #ifdef MIPS_STABS_ELF
864 /* The pdr segment for per procedure frame/regmask info */
870 * This function is called once, at assembler startup time. It should
871 * set up all the tables, etc. that the MD part of the assembler will need.
877 register const char *retval
= NULL
;
878 register unsigned int i
= 0;
884 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
886 a
= xmalloc (sizeof TARGET_CPU
);
887 strcpy (a
, TARGET_CPU
);
888 a
[(sizeof TARGET_CPU
) - 3] = '\0';
894 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
895 just the generic 'mips', in which case set mips_cpu based
896 on the given ISA, if any. */
898 if (strcmp (cpu
, "mips") == 0)
900 if (mips_opts
.isa
< 0)
903 else if (mips_opts
.isa
== 2)
906 else if (mips_opts
.isa
== 3)
909 else if (mips_opts
.isa
== 4)
916 else if (strcmp (cpu
, "r3900") == 0
917 || strcmp (cpu
, "mipstx39") == 0
918 /* start-sanitize-tx19 */
919 || strcmp (cpu
, "r1900") == 0
920 || strcmp (cpu
, "mipstx19") == 0
921 /* end-sanitize-tx19 */
925 else if (strcmp (cpu
, "r6000") == 0
926 || strcmp (cpu
, "mips2") == 0)
929 else if (strcmp (cpu
, "mips64") == 0
930 || strcmp (cpu
, "r4000") == 0
931 || strcmp (cpu
, "mips3") == 0)
934 else if (strcmp (cpu
, "r4400") == 0)
937 else if (strcmp (cpu
, "mips64orion") == 0
938 || strcmp (cpu
, "r4600") == 0)
941 else if (strcmp (cpu
, "r4650") == 0)
944 else if (strcmp (cpu
, "mips64vr4300") == 0)
947 /* start-sanitize-vr4xxx */
948 else if (strcmp (cpu
, "mips64vr4xxx") == 0)
951 /* end-sanitize-vr4xxx */
952 /* start-sanitize-vr4320 */
953 else if (strcmp (cpu
, "r4320") == 0
954 || strcmp (cpu
, "mips64vr4320") == 0)
957 /* end-sanitize-vr4320 */
958 else if (strcmp (cpu
, "mips64vr4100") == 0)
961 /* start-sanitize-vr4xxx */
962 else if (strcmp (cpu
, "vr4121") == 0
963 || strcmp (cpu
, "mips64vr4121") == 0)
966 /* end-sanitize-vr4xxx */
967 else if (strcmp (cpu
, "r4010") == 0)
970 /* start-sanitize-tx49 */
971 else if (strcmp (cpu
, "mips64tx49") == 0)
973 /* end-sanitize-tx49 */
975 else if (strcmp (cpu
, "r5000") == 0
976 || strcmp (cpu
, "mips64vr5000") == 0)
979 /* start-sanitize-cygnus */
980 else if (strcmp (cpu
, "r5400") == 0
981 || strcmp (cpu
, "mips64vr5400") == 0)
983 /* end-sanitize-cygnus */
985 /* start-sanitize-r5900 */
986 else if (strcmp (cpu
, "r5900") == 0
987 || strcmp (cpu
, "mips64r5900") == 0)
989 /* end-sanitize-r5900 */
991 else if (strcmp (cpu
, "r8000") == 0
992 || strcmp (cpu
, "mips4") == 0)
995 else if (strcmp (cpu
, "r10000") == 0)
998 else if (strcmp (cpu
, "mips16") == 0)
999 mips_cpu
= 0; /* FIXME */
1005 if (mips_opts
.isa
== -1)
1007 if (mips_cpu
== 3000
1008 || mips_cpu
== 3900)
1011 else if (mips_cpu
== 6000
1012 || mips_cpu
== 4010)
1015 else if (mips_cpu
== 4000
1017 /* start-sanitize-vr4xxx */
1020 /* end-sanitize-vr4xxx */
1023 /* start-sanitize-vr4320 */
1025 /* end-sanitize-vr4320 */
1027 /* start-sanitize-tx49 */
1029 /* end-sanitize-tx49 */
1030 /* start-sanitize-r5900 */
1032 /* end-sanitize-r5900 */
1033 || mips_cpu
== 4650)
1036 else if (mips_cpu
== 5000
1037 /* start-sanitize-cygnus */
1039 /* end-sanitize-cygnus */
1041 || mips_cpu
== 10000)
1048 if (mips_opts
.mips16
< 0)
1050 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1051 mips_opts
.mips16
= 1;
1053 mips_opts
.mips16
= 0;
1057 mips_4650
= (mips_cpu
== 4650);
1060 mips_4010
= (mips_cpu
== 4010);
1063 mips_4100
= (mips_cpu
== 4100
1064 /* start-sanitize-vr4xxx */
1066 /* end-sanitize-vr4xxx */
1069 /* start-sanitize-vr4xxx */
1071 mips_4121
= (mips_cpu
== 4121);
1073 /* end-sanitize-vr4xxx */
1074 /* start-sanitize-vr4320 */
1076 mips_4320
= (mips_cpu
== 4320);
1078 /* end-sanitize-vr4320 */
1079 /* start-sanitize-cygnus */
1081 mips_5400
= (mips_cpu
== 5400);
1082 /* end-sanitize-cygnus */
1084 /* start-sanitize-r5900 */
1086 mips_5900
= (mips_cpu
== 5900);
1087 /* end-sanitize-r5900 */
1090 mips_3900
= (mips_cpu
== 3900);
1092 /* start-sanitize-tx49 */
1094 mips_4900
= (mips_cpu
== 4900);
1096 /* end-sanitize-tx49 */
1098 /* End of TARGET_CPU processing, get rid of malloced memory
1107 if (mips_opts
.isa
< 2 && mips_trap
)
1108 as_bad (_("trap exception not supported at ISA 1"));
1110 /* Set the EABI kind based on the ISA before the user gets
1111 to change the ISA with directives. This isn't really
1112 the best, but then neither is basing the abi on the isa. */
1113 if (mips_opts
.isa
> 2 && 0 == strcmp (mips_abi_string
,"eabi"))
1116 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1118 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1122 switch (mips_opts
.isa
)
1125 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1128 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1131 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1134 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1140 as_warn (_("Could not set architecture and machine"));
1142 file_mips_isa
= mips_opts
.isa
;
1144 op_hash
= hash_new ();
1146 for (i
= 0; i
< NUMOPCODES
;)
1148 const char *name
= mips_opcodes
[i
].name
;
1150 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1153 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1154 mips_opcodes
[i
].name
, retval
);
1155 /* Probably a memory allocation problem? Give up now. */
1156 as_fatal (_("Broken assembler. No assembly attempted."));
1160 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1162 if (!validate_mips_insn (&mips_opcodes
[i
]))
1167 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1170 mips16_op_hash
= hash_new ();
1173 while (i
< bfd_mips16_num_opcodes
)
1175 const char *name
= mips16_opcodes
[i
].name
;
1177 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1179 as_fatal (_("internal: can't hash `%s': %s"),
1180 mips16_opcodes
[i
].name
, retval
);
1183 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1184 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1185 != mips16_opcodes
[i
].match
))
1187 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1188 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1193 while (i
< bfd_mips16_num_opcodes
1194 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1198 as_fatal (_("Broken assembler. No assembly attempted."));
1200 /* We add all the general register names to the symbol table. This
1201 helps us detect invalid uses of them. */
1202 for (i
= 0; i
< 32; i
++)
1206 sprintf (buf
, "$%d", i
);
1207 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1208 &zero_address_frag
));
1210 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1211 &zero_address_frag
));
1212 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1213 &zero_address_frag
));
1214 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1215 &zero_address_frag
));
1216 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1217 &zero_address_frag
));
1218 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1219 &zero_address_frag
));
1220 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1221 &zero_address_frag
));
1222 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1223 &zero_address_frag
));
1225 mips_no_prev_insn (false);
1228 mips_cprmask
[0] = 0;
1229 mips_cprmask
[1] = 0;
1230 mips_cprmask
[2] = 0;
1231 mips_cprmask
[3] = 0;
1233 /* set the default alignment for the text section (2**2) */
1234 record_alignment (text_section
, 2);
1236 if (USE_GLOBAL_POINTER_OPT
)
1237 bfd_set_gp_size (stdoutput
, g_switch_value
);
1239 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1241 /* On a native system, sections must be aligned to 16 byte
1242 boundaries. When configured for an embedded ELF target, we
1244 if (strcmp (TARGET_OS
, "elf") != 0)
1246 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1247 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1248 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1251 /* Create a .reginfo section for register masks and a .mdebug
1252 section for debugging information. */
1260 subseg
= now_subseg
;
1262 /* The ABI says this section should be loaded so that the
1263 running program can access it. However, we don't load it
1264 if we are configured for an embedded target */
1265 flags
= SEC_READONLY
| SEC_DATA
;
1266 if (strcmp (TARGET_OS
, "elf") != 0)
1267 flags
|= SEC_ALLOC
| SEC_LOAD
;
1271 sec
= subseg_new (".reginfo", (subsegT
) 0);
1274 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1275 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1278 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1283 /* The 64-bit ABI uses a .MIPS.options section rather than
1284 .reginfo section. */
1285 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1286 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1287 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1290 /* Set up the option header. */
1292 Elf_Internal_Options opthdr
;
1295 opthdr
.kind
= ODK_REGINFO
;
1296 opthdr
.size
= (sizeof (Elf_External_Options
)
1297 + sizeof (Elf64_External_RegInfo
));
1300 f
= frag_more (sizeof (Elf_External_Options
));
1301 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1302 (Elf_External_Options
*) f
);
1304 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1309 if (ECOFF_DEBUGGING
)
1311 sec
= subseg_new (".mdebug", (subsegT
) 0);
1312 (void) bfd_set_section_flags (stdoutput
, sec
,
1313 SEC_HAS_CONTENTS
| SEC_READONLY
);
1314 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1317 #ifdef MIPS_STABS_ELF
1318 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1320 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1321 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1324 subseg_set (seg
, subseg
);
1328 if (! ECOFF_DEBUGGING
)
1335 if (! ECOFF_DEBUGGING
)
1343 struct mips_cl_insn insn
;
1345 imm_expr
.X_op
= O_absent
;
1346 imm_reloc
= BFD_RELOC_UNUSED
;
1347 imm_unmatched_hi
= false;
1348 offset_expr
.X_op
= O_absent
;
1349 offset_reloc
= BFD_RELOC_UNUSED
;
1351 if (mips_opts
.mips16
)
1352 mips16_ip (str
, &insn
);
1355 mips_ip (str
, &insn
);
1356 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1357 str
, insn
.insn_opcode
));
1362 as_bad ("%s `%s'", insn_error
, str
);
1366 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1368 if (mips_opts
.mips16
)
1369 mips16_macro (&insn
);
1375 if (imm_expr
.X_op
!= O_absent
)
1376 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1378 else if (offset_expr
.X_op
!= O_absent
)
1379 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1381 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1385 /* See whether instruction IP reads register REG. CLASS is the type
1389 insn_uses_reg (ip
, reg
, class)
1390 struct mips_cl_insn
*ip
;
1392 enum mips_regclass
class;
1394 if (class == MIPS16_REG
)
1396 assert (mips_opts
.mips16
);
1397 reg
= mips16_to_32_reg_map
[reg
];
1398 class = MIPS_GR_REG
;
1401 /* Don't report on general register 0, since it never changes. */
1402 if (class == MIPS_GR_REG
&& reg
== 0)
1405 if (class == MIPS_FP_REG
)
1407 assert (! mips_opts
.mips16
);
1408 /* If we are called with either $f0 or $f1, we must check $f0.
1409 This is not optimal, because it will introduce an unnecessary
1410 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1411 need to distinguish reading both $f0 and $f1 or just one of
1412 them. Note that we don't have to check the other way,
1413 because there is no instruction that sets both $f0 and $f1
1414 and requires a delay. */
1415 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1416 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1417 == (reg
&~ (unsigned) 1)))
1419 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1420 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1421 == (reg
&~ (unsigned) 1)))
1424 else if (! mips_opts
.mips16
)
1426 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1427 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1429 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1430 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1435 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1436 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1437 & MIPS16OP_MASK_RX
)]
1440 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1441 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1442 & MIPS16OP_MASK_RY
)]
1445 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1446 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1447 & MIPS16OP_MASK_MOVE32Z
)]
1450 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1452 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1454 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1456 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1457 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1458 & MIPS16OP_MASK_REGR32
) == reg
)
1465 /* This function returns true if modifying a register requires a
1469 reg_needs_delay (reg
)
1472 unsigned long prev_pinfo
;
1474 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1475 if (! mips_opts
.noreorder
1476 && mips_opts
.isa
< 4
1477 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1478 || (! gpr_interlocks
1479 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1481 /* A load from a coprocessor or from memory. All load
1482 delays delay the use of general register rt for one
1483 instruction on the r3000. The r6000 and r4000 use
1485 /* Itbl support may require additional care here. */
1486 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1487 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1494 /* Mark instruction labels in mips16 mode. This permits the linker to
1495 handle them specially, such as generating jalx instructions when
1496 needed. We also make them odd for the duration of the assembly, in
1497 order to generate the right sort of code. We will make them even
1498 in the adjust_symtab routine, while leaving them marked. This is
1499 convenient for the debugger and the disassembler. The linker knows
1500 to make them odd again. */
1503 mips16_mark_labels ()
1505 if (mips_opts
.mips16
)
1507 struct insn_label_list
*l
;
1509 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1512 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1513 S_SET_OTHER (l
->label
, STO_MIPS16
);
1515 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1516 ++l
->label
->sy_value
.X_add_number
;
1521 /* Output an instruction. PLACE is where to put the instruction; if
1522 it is NULL, this uses frag_more to get room. IP is the instruction
1523 information. ADDRESS_EXPR is an operand of the instruction to be
1524 used with RELOC_TYPE. */
1527 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1529 struct mips_cl_insn
*ip
;
1530 expressionS
*address_expr
;
1531 bfd_reloc_code_real_type reloc_type
;
1532 boolean unmatched_hi
;
1534 register unsigned long prev_pinfo
, pinfo
;
1538 /* start-sanitize-branchbug4011 */
1539 int label_nop
= 0; /* True if a no-op needs to appear between
1540 the current insn and the current labels */
1541 /* end-sanitize-branchbug4011 */
1543 /* Mark instruction labels in mips16 mode. */
1544 if (mips_opts
.mips16
)
1545 mips16_mark_labels ();
1547 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1548 pinfo
= ip
->insn_mo
->pinfo
;
1550 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1554 /* If the previous insn required any delay slots, see if we need
1555 to insert a NOP or two. There are eight kinds of possible
1556 hazards, of which an instruction can have at most one type.
1557 (1) a load from memory delay
1558 (2) a load from a coprocessor delay
1559 (3) an unconditional branch delay
1560 (4) a conditional branch delay
1561 (5) a move to coprocessor register delay
1562 (6) a load coprocessor register from memory delay
1563 (7) a coprocessor condition code delay
1564 (8) a HI/LO special register delay
1566 There are a lot of optimizations we could do that we don't.
1567 In particular, we do not, in general, reorder instructions.
1568 If you use gcc with optimization, it will reorder
1569 instructions and generally do much more optimization then we
1570 do here; repeating all that work in the assembler would only
1571 benefit hand written assembly code, and does not seem worth
1574 /* This is how a NOP is emitted. */
1575 #define emit_nop() \
1577 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1578 : md_number_to_chars (frag_more (4), 0, 4))
1580 /* The previous insn might require a delay slot, depending upon
1581 the contents of the current insn. */
1582 if (! mips_opts
.mips16
1583 && mips_opts
.isa
< 4
1584 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1585 && ! cop_interlocks
)
1586 || (! gpr_interlocks
1587 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1589 /* A load from a coprocessor or from memory. All load
1590 delays delay the use of general register rt for one
1591 instruction on the r3000. The r6000 and r4000 use
1593 /* Itbl support may require additional care here. */
1594 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1595 if (mips_optimize
== 0
1596 || insn_uses_reg (ip
,
1597 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1602 else if (! mips_opts
.mips16
1603 && mips_opts
.isa
< 4
1604 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1605 && ! cop_interlocks
)
1606 || (mips_opts
.isa
< 2
1607 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1609 /* A generic coprocessor delay. The previous instruction
1610 modified a coprocessor general or control register. If
1611 it modified a control register, we need to avoid any
1612 coprocessor instruction (this is probably not always
1613 required, but it sometimes is). If it modified a general
1614 register, we avoid using that register.
1616 On the r6000 and r4000 loading a coprocessor register
1617 from memory is interlocked, and does not require a delay.
1619 This case is not handled very well. There is no special
1620 knowledge of CP0 handling, and the coprocessors other
1621 than the floating point unit are not distinguished at
1623 /* Itbl support may require additional care here. FIXME!
1624 Need to modify this to include knowledge about
1625 user specified delays! */
1626 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1628 if (mips_optimize
== 0
1629 || insn_uses_reg (ip
,
1630 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1635 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1637 if (mips_optimize
== 0
1638 || insn_uses_reg (ip
,
1639 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1646 /* We don't know exactly what the previous instruction
1647 does. If the current instruction uses a coprocessor
1648 register, we must insert a NOP. If previous
1649 instruction may set the condition codes, and the
1650 current instruction uses them, we must insert two
1652 /* Itbl support may require additional care here. */
1653 if (mips_optimize
== 0
1654 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1655 && (pinfo
& INSN_READ_COND_CODE
)))
1657 else if (pinfo
& INSN_COP
)
1661 else if (! mips_opts
.mips16
1662 && mips_opts
.isa
< 4
1663 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1664 && ! cop_interlocks
)
1666 /* The previous instruction sets the coprocessor condition
1667 codes, but does not require a general coprocessor delay
1668 (this means it is a floating point comparison
1669 instruction). If this instruction uses the condition
1670 codes, we need to insert a single NOP. */
1671 /* Itbl support may require additional care here. */
1672 if (mips_optimize
== 0
1673 || (pinfo
& INSN_READ_COND_CODE
))
1676 else if (prev_pinfo
& INSN_READ_LO
)
1678 /* The previous instruction reads the LO register; if the
1679 current instruction writes to the LO register, we must
1680 insert two NOPS. Some newer processors have interlocks.
1681 Also the tx39's multiply instructions can be exectuted
1682 immediatly after a read from HI/LO (without the delay),
1683 though the tx39's divide insns still do require the
1685 if (! (hilo_interlocks
1686 || (mips_3900
&& (pinfo
& INSN_MULT
)))
1687 && (mips_optimize
== 0
1688 || (pinfo
& INSN_WRITE_LO
)))
1691 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1693 /* The previous instruction reads the HI register; if the
1694 current instruction writes to the HI register, we must
1695 insert a NOP. Some newer processors have interlocks.
1696 Also the note tx39's multiply above. */
1697 if (! (hilo_interlocks
1698 || (mips_3900
&& (pinfo
& INSN_MULT
)))
1699 && (mips_optimize
== 0
1700 || (pinfo
& INSN_WRITE_HI
)))
1704 /* If the previous instruction was in a noreorder section, then
1705 we don't want to insert the nop after all. */
1706 /* Itbl support may require additional care here. */
1707 if (prev_insn_unreordered
)
1710 /* There are two cases which require two intervening
1711 instructions: 1) setting the condition codes using a move to
1712 coprocessor instruction which requires a general coprocessor
1713 delay and then reading the condition codes 2) reading the HI
1714 or LO register and then writing to it (except on processors
1715 which have interlocks). If we are not already emitting a NOP
1716 instruction, we must check for these cases compared to the
1717 instruction previous to the previous instruction. */
1718 if ((! mips_opts
.mips16
1719 && mips_opts
.isa
< 4
1720 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1721 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1722 && (pinfo
& INSN_READ_COND_CODE
)
1723 && ! cop_interlocks
)
1724 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1725 && (pinfo
& INSN_WRITE_LO
)
1726 && ! (hilo_interlocks
1727 || (mips_3900
&& (pinfo
& INSN_MULT
))))
1728 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1729 && (pinfo
& INSN_WRITE_HI
)
1730 && ! (hilo_interlocks
1731 || (mips_3900
&& (pinfo
& INSN_MULT
)))))
1736 if (prev_prev_insn_unreordered
)
1739 if (prev_prev_nop
&& nops
== 0)
1742 /* If we are being given a nop instruction, don't bother with
1743 one of the nops we would otherwise output. This will only
1744 happen when a nop instruction is used with mips_optimize set
1747 && ! mips_opts
.noreorder
1748 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1751 /* start-sanitize-branchbug4011 */
1752 /* If we have a label on a branch insn, we need at least one no-op
1753 between the label and the branch. The pinfo flags in this test
1754 must cover all the kinds of branches. */
1755 if (mips_fix_4011_branch_bug
1756 && insn_labels
!= NULL
1757 && (ip
->insn_mo
->pinfo
1758 & (INSN_UNCOND_BRANCH_DELAY
1759 |INSN_COND_BRANCH_DELAY
1760 |INSN_COND_BRANCH_LIKELY
)))
1764 /* Make sure we've got at least one nop. */
1769 /* end-sanitize-branchbug4011 */
1770 /* Now emit the right number of NOP instructions. */
1771 if (nops
> 0 && ! mips_opts
.noreorder
)
1774 unsigned long old_frag_offset
;
1776 struct insn_label_list
*l
;
1778 old_frag
= frag_now
;
1779 old_frag_offset
= frag_now_fix ();
1781 /* start-sanitize-branchbug4011 */
1782 /* Emit the nops that should be before the label. */
1786 /* end-sanitize-branchbug4011 */
1787 for (i
= 0; i
< nops
; i
++)
1792 listing_prev_line ();
1793 /* We may be at the start of a variant frag. In case we
1794 are, make sure there is enough space for the frag
1795 after the frags created by listing_prev_line. The
1796 argument to frag_grow here must be at least as large
1797 as the argument to all other calls to frag_grow in
1798 this file. We don't have to worry about being in the
1799 middle of a variant frag, because the variants insert
1800 all needed nop instructions themselves. */
1804 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1806 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1807 l
->label
->sy_frag
= frag_now
;
1808 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1809 /* mips16 text labels are stored as odd. */
1810 if (mips_opts
.mips16
)
1811 ++l
->label
->sy_value
.X_add_number
;
1814 #ifndef NO_ECOFF_DEBUGGING
1815 if (ECOFF_DEBUGGING
)
1816 ecoff_fix_loc (old_frag
, old_frag_offset
);
1818 /* start-sanitize-branchbug4011 */
1821 /* Emit the nop after the label, and return the
1822 nop count to it's proper value. */
1826 /* end-sanitize-branchbug4011 */
1828 else if (prev_nop_frag
!= NULL
)
1830 /* We have a frag holding nops we may be able to remove. If
1831 we don't need any nops, we can decrease the size of
1832 prev_nop_frag by the size of one instruction. If we do
1833 need some nops, we count them in prev_nops_required. */
1834 if (prev_nop_frag_since
== 0)
1838 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1839 --prev_nop_frag_holds
;
1842 prev_nop_frag_required
+= nops
;
1846 if (prev_prev_nop
== 0)
1848 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1849 --prev_nop_frag_holds
;
1852 ++prev_nop_frag_required
;
1855 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1856 prev_nop_frag
= NULL
;
1858 ++prev_nop_frag_since
;
1860 /* Sanity check: by the time we reach the second instruction
1861 after prev_nop_frag, we should have used up all the nops
1862 one way or another. */
1863 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1867 if (reloc_type
> BFD_RELOC_UNUSED
)
1869 /* We need to set up a variant frag. */
1870 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1871 f
= frag_var (rs_machine_dependent
, 4, 0,
1872 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1873 mips16_small
, mips16_ext
,
1875 & INSN_UNCOND_BRANCH_DELAY
),
1876 (prev_insn_reloc_type
1877 == BFD_RELOC_MIPS16_JMP
)),
1878 make_expr_symbol (address_expr
), (offsetT
) 0,
1881 else if (place
!= NULL
)
1883 else if (mips_opts
.mips16
1885 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1887 /* Make sure there is enough room to swap this instruction with
1888 a following jump instruction. */
1894 if (mips_opts
.mips16
1895 && mips_opts
.noreorder
1896 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1897 as_warn (_("extended instruction in delay slot"));
1903 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1905 if (address_expr
->X_op
== O_constant
)
1910 ip
->insn_opcode
|= address_expr
->X_add_number
;
1913 case BFD_RELOC_LO16
:
1914 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1917 case BFD_RELOC_MIPS_JMP
:
1918 if ((address_expr
->X_add_number
& 3) != 0)
1919 as_bad (_("jump to misaligned address (0x%lx)"),
1920 (unsigned long) address_expr
->X_add_number
);
1921 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1924 case BFD_RELOC_MIPS16_JMP
:
1925 if ((address_expr
->X_add_number
& 3) != 0)
1926 as_bad (_("jump to misaligned address (0x%lx)"),
1927 (unsigned long) address_expr
->X_add_number
);
1929 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1930 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1931 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1934 /* start-sanitize-r5900 */
1935 case BFD_RELOC_MIPS15_S3
:
1936 ip
->insn_opcode
|= ((imm_expr
.X_add_number
& 0x7fff) >> 3) << 6;
1938 /* end-sanitize-r5900 */
1940 case BFD_RELOC_16_PCREL_S2
:
1950 /* Don't generate a reloc if we are writing into a variant
1954 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1956 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1960 struct mips_hi_fixup
*hi_fixup
;
1962 assert (reloc_type
== BFD_RELOC_HI16_S
);
1963 hi_fixup
= ((struct mips_hi_fixup
*)
1964 xmalloc (sizeof (struct mips_hi_fixup
)));
1965 hi_fixup
->fixp
= fixp
;
1966 hi_fixup
->seg
= now_seg
;
1967 hi_fixup
->next
= mips_hi_fixup_list
;
1968 mips_hi_fixup_list
= hi_fixup
;
1974 if (! mips_opts
.mips16
)
1975 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1976 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1978 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1979 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1985 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1988 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1991 /* Update the register mask information. */
1992 if (! mips_opts
.mips16
)
1994 if (pinfo
& INSN_WRITE_GPR_D
)
1995 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1996 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1997 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1998 if (pinfo
& INSN_READ_GPR_S
)
1999 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2000 if (pinfo
& INSN_WRITE_GPR_31
)
2001 mips_gprmask
|= 1 << 31;
2002 if (pinfo
& INSN_WRITE_FPR_D
)
2003 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2004 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2005 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2006 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2007 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2008 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2009 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2010 if (pinfo
& INSN_COP
)
2012 /* We don't keep enough information to sort these cases out.
2013 The itbl support does keep this information however, although
2014 we currently don't support itbl fprmats as part of the cop
2015 instruction. May want to add this support in the future. */
2017 /* Never set the bit for $0, which is always zero. */
2018 mips_gprmask
&=~ 1 << 0;
2022 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2023 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2024 & MIPS16OP_MASK_RX
);
2025 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2026 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2027 & MIPS16OP_MASK_RY
);
2028 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2029 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2030 & MIPS16OP_MASK_RZ
);
2031 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2032 mips_gprmask
|= 1 << TREG
;
2033 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2034 mips_gprmask
|= 1 << SP
;
2035 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2036 mips_gprmask
|= 1 << RA
;
2037 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2038 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2039 if (pinfo
& MIPS16_INSN_READ_Z
)
2040 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2041 & MIPS16OP_MASK_MOVE32Z
);
2042 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2043 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2044 & MIPS16OP_MASK_REGR32
);
2047 if (place
== NULL
&& ! mips_opts
.noreorder
)
2049 /* Filling the branch delay slot is more complex. We try to
2050 switch the branch with the previous instruction, which we can
2051 do if the previous instruction does not set up a condition
2052 that the branch tests and if the branch is not itself the
2053 target of any branch. */
2054 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2055 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2057 if (mips_optimize
< 2
2058 /* If we have seen .set volatile or .set nomove, don't
2060 || mips_opts
.nomove
!= 0
2061 /* If we had to emit any NOP instructions, then we
2062 already know we can not swap. */
2064 /* If we don't even know the previous insn, we can not
2066 || ! prev_insn_valid
2067 /* If the previous insn is already in a branch delay
2068 slot, then we can not swap. */
2069 || prev_insn_is_delay_slot
2070 /* start-sanitize-branchbug4011 */
2071 /* We can't swap the branch back to a previous label */
2072 || (mips_fix_4011_branch_bug
&& prev_insn_labels
)
2073 /* end-sanitize-branchbug4011 */
2074 /* If the previous previous insn was in a .set
2075 noreorder, we can't swap. Actually, the MIPS
2076 assembler will swap in this situation. However, gcc
2077 configured -with-gnu-as will generate code like
2083 in which we can not swap the bne and INSN. If gcc is
2084 not configured -with-gnu-as, it does not output the
2085 .set pseudo-ops. We don't have to check
2086 prev_insn_unreordered, because prev_insn_valid will
2087 be 0 in that case. We don't want to use
2088 prev_prev_insn_valid, because we do want to be able
2089 to swap at the start of a function. */
2090 || prev_prev_insn_unreordered
2091 /* If the branch is itself the target of a branch, we
2092 can not swap. We cheat on this; all we check for is
2093 whether there is a label on this instruction. If
2094 there are any branches to anything other than a
2095 label, users must use .set noreorder. */
2096 || insn_labels
!= NULL
2097 /* If the previous instruction is in a variant frag, we
2098 can not do the swap. This does not apply to the
2099 mips16, which uses variant frags for different
2101 || (! mips_opts
.mips16
2102 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2103 /* If the branch reads the condition codes, we don't
2104 even try to swap, because in the sequence
2109 we can not swap, and I don't feel like handling that
2111 || (! mips_opts
.mips16
2112 && mips_opts
.isa
< 4
2113 && (pinfo
& INSN_READ_COND_CODE
))
2114 /* We can not swap with an instruction that requires a
2115 delay slot, becase the target of the branch might
2116 interfere with that instruction. */
2117 || (! mips_opts
.mips16
2118 && mips_opts
.isa
< 4
2120 /* Itbl support may require additional care here. */
2121 & (INSN_LOAD_COPROC_DELAY
2122 | INSN_COPROC_MOVE_DELAY
2123 | INSN_WRITE_COND_CODE
)))
2124 || (! (hilo_interlocks
|| (mips_3900
&& (pinfo
& INSN_MULT
)))
2128 || (! mips_opts
.mips16
2130 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2131 || (! mips_opts
.mips16
2132 && mips_opts
.isa
< 2
2133 /* Itbl support may require additional care here. */
2134 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2135 /* We can not swap with a branch instruction. */
2137 & (INSN_UNCOND_BRANCH_DELAY
2138 | INSN_COND_BRANCH_DELAY
2139 | INSN_COND_BRANCH_LIKELY
))
2140 /* We do not swap with a trap instruction, since it
2141 complicates trap handlers to have the trap
2142 instruction be in a delay slot. */
2143 || (prev_pinfo
& INSN_TRAP
)
2144 /* If the branch reads a register that the previous
2145 instruction sets, we can not swap. */
2146 || (! mips_opts
.mips16
2147 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2148 && insn_uses_reg (ip
,
2149 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2152 || (! mips_opts
.mips16
2153 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2154 && insn_uses_reg (ip
,
2155 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2158 || (mips_opts
.mips16
2159 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2160 && insn_uses_reg (ip
,
2161 ((prev_insn
.insn_opcode
2163 & MIPS16OP_MASK_RX
),
2165 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2166 && insn_uses_reg (ip
,
2167 ((prev_insn
.insn_opcode
2169 & MIPS16OP_MASK_RY
),
2171 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2172 && insn_uses_reg (ip
,
2173 ((prev_insn
.insn_opcode
2175 & MIPS16OP_MASK_RZ
),
2177 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2178 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2179 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2180 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2181 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2182 && insn_uses_reg (ip
,
2183 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2186 /* If the branch writes a register that the previous
2187 instruction sets, we can not swap (we know that
2188 branches write only to RD or to $31). */
2189 || (! mips_opts
.mips16
2190 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2191 && (((pinfo
& INSN_WRITE_GPR_D
)
2192 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2193 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2194 || ((pinfo
& INSN_WRITE_GPR_31
)
2195 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2198 || (! mips_opts
.mips16
2199 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2200 && (((pinfo
& INSN_WRITE_GPR_D
)
2201 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2202 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2203 || ((pinfo
& INSN_WRITE_GPR_31
)
2204 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2207 || (mips_opts
.mips16
2208 && (pinfo
& MIPS16_INSN_WRITE_31
)
2209 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2210 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2211 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2213 /* If the branch writes a register that the previous
2214 instruction reads, we can not swap (we know that
2215 branches only write to RD or to $31). */
2216 || (! mips_opts
.mips16
2217 && (pinfo
& INSN_WRITE_GPR_D
)
2218 && insn_uses_reg (&prev_insn
,
2219 ((ip
->insn_opcode
>> OP_SH_RD
)
2222 || (! mips_opts
.mips16
2223 && (pinfo
& INSN_WRITE_GPR_31
)
2224 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2225 || (mips_opts
.mips16
2226 && (pinfo
& MIPS16_INSN_WRITE_31
)
2227 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2228 /* If we are generating embedded PIC code, the branch
2229 might be expanded into a sequence which uses $at, so
2230 we can't swap with an instruction which reads it. */
2231 || (mips_pic
== EMBEDDED_PIC
2232 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2233 /* If the previous previous instruction has a load
2234 delay, and sets a register that the branch reads, we
2236 || (! mips_opts
.mips16
2237 && mips_opts
.isa
< 4
2238 /* Itbl support may require additional care here. */
2239 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2240 || (! gpr_interlocks
2241 && (prev_prev_insn
.insn_mo
->pinfo
2242 & INSN_LOAD_MEMORY_DELAY
)))
2243 && insn_uses_reg (ip
,
2244 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2247 /* If one instruction sets a condition code and the
2248 other one uses a condition code, we can not swap. */
2249 || ((pinfo
& INSN_READ_COND_CODE
)
2250 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2251 || ((pinfo
& INSN_WRITE_COND_CODE
)
2252 && (prev_pinfo
& INSN_READ_COND_CODE
))
2253 /* If the previous instruction uses the PC, we can not
2255 || (mips_opts
.mips16
2256 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2257 /* If the previous instruction was extended, we can not
2259 || (mips_opts
.mips16
&& prev_insn_extended
)
2260 /* If the previous instruction had a fixup in mips16
2261 mode, we can not swap. This normally means that the
2262 previous instruction was a 4 byte branch anyhow. */
2263 || (mips_opts
.mips16
&& prev_insn_fixp
)
2264 /* If the previous instruction is a sync, sync.l, or
2265 sync.p, we can not swap. */
2266 || (prev_pinfo
&& INSN_SYNC
))
2268 /* We could do even better for unconditional branches to
2269 portions of this object file; we could pick up the
2270 instruction at the destination, put it in the delay
2271 slot, and bump the destination address. */
2273 /* Update the previous insn information. */
2274 prev_prev_insn
= *ip
;
2275 prev_insn
.insn_mo
= &dummy_opcode
;
2279 /* It looks like we can actually do the swap. */
2280 if (! mips_opts
.mips16
)
2285 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2286 memcpy (temp
, prev_f
, 4);
2287 memcpy (prev_f
, f
, 4);
2288 memcpy (f
, temp
, 4);
2291 prev_insn_fixp
->fx_frag
= frag_now
;
2292 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2296 fixp
->fx_frag
= prev_insn_frag
;
2297 fixp
->fx_where
= prev_insn_where
;
2305 assert (prev_insn_fixp
== NULL
);
2306 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2307 memcpy (temp
, prev_f
, 2);
2308 memcpy (prev_f
, f
, 2);
2309 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2311 assert (reloc_type
== BFD_RELOC_UNUSED
);
2312 memcpy (f
, temp
, 2);
2316 memcpy (f
, f
+ 2, 2);
2317 memcpy (f
+ 2, temp
, 2);
2321 fixp
->fx_frag
= prev_insn_frag
;
2322 fixp
->fx_where
= prev_insn_where
;
2326 /* Update the previous insn information; leave prev_insn
2328 prev_prev_insn
= *ip
;
2330 prev_insn_is_delay_slot
= 1;
2332 /* If that was an unconditional branch, forget the previous
2333 insn information. */
2334 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2336 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2337 prev_insn
.insn_mo
= &dummy_opcode
;
2340 prev_insn_fixp
= NULL
;
2341 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2342 prev_insn_extended
= 0;
2344 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2346 /* We don't yet optimize a branch likely. What we should do
2347 is look at the target, copy the instruction found there
2348 into the delay slot, and increment the branch to jump to
2349 the next instruction. */
2351 /* Update the previous insn information. */
2352 prev_prev_insn
= *ip
;
2353 prev_insn
.insn_mo
= &dummy_opcode
;
2354 prev_insn_fixp
= NULL
;
2355 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2356 prev_insn_extended
= 0;
2360 /* Update the previous insn information. */
2362 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2364 prev_prev_insn
= prev_insn
;
2367 /* Any time we see a branch, we always fill the delay slot
2368 immediately; since this insn is not a branch, we know it
2369 is not in a delay slot. */
2370 prev_insn_is_delay_slot
= 0;
2372 prev_insn_fixp
= fixp
;
2373 prev_insn_reloc_type
= reloc_type
;
2374 if (mips_opts
.mips16
)
2375 prev_insn_extended
= (ip
->use_extend
2376 || reloc_type
> BFD_RELOC_UNUSED
);
2379 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2380 prev_insn_unreordered
= 0;
2381 prev_insn_frag
= frag_now
;
2382 prev_insn_where
= f
- frag_now
->fr_literal
;
2383 prev_insn_valid
= 1;
2384 /* start-sanitize-branchbug4011 */
2385 prev_insn_labels
= !! insn_labels
;
2386 /* end-sanitize-branchbug4011 */
2388 else if (place
== NULL
)
2390 /* We need to record a bit of information even when we are not
2391 reordering, in order to determine the base address for mips16
2392 PC relative relocs. */
2393 prev_prev_insn
= prev_insn
;
2395 prev_insn_reloc_type
= reloc_type
;
2396 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2397 prev_insn_unreordered
= 1;
2398 /* start-sanitize-branchbug4011 */
2399 prev_insn_labels
= !! insn_labels
;
2400 /* end-sanitize-branchbug4011 */
2403 /* We just output an insn, so the next one doesn't have a label. */
2404 mips_clear_insn_labels ();
2406 /* We must ensure that a fixup associated with an unmatched %hi
2407 reloc does not become a variant frag. Otherwise, the
2408 rearrangement of %hi relocs in frob_file may confuse
2412 frag_wane (frag_now
);
2417 /* This function forgets that there was any previous instruction or
2418 label. If PRESERVE is non-zero, it remembers enough information to
2419 know whether nops are needed before a noreorder section. */
2422 mips_no_prev_insn (preserve
)
2427 prev_insn
.insn_mo
= &dummy_opcode
;
2428 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2429 prev_nop_frag
= NULL
;
2430 prev_nop_frag_holds
= 0;
2431 prev_nop_frag_required
= 0;
2432 prev_nop_frag_since
= 0;
2434 prev_insn_valid
= 0;
2435 prev_insn_is_delay_slot
= 0;
2436 prev_insn_unreordered
= 0;
2437 prev_insn_extended
= 0;
2438 /* start-sanitize-branchbug4011 */
2439 prev_insn_labels
= 0;
2440 /* end-sanitize-branchbug4011 */
2441 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2442 prev_prev_insn_unreordered
= 0;
2443 mips_clear_insn_labels ();
2446 /* This function must be called whenever we turn on noreorder or emit
2447 something other than instructions. It inserts any NOPS which might
2448 be needed by the previous instruction, and clears the information
2449 kept for the previous instructions. The INSNS parameter is true if
2450 instructions are to follow. */
2453 mips_emit_delays (insns
)
2456 if (! mips_opts
.noreorder
)
2461 if ((! mips_opts
.mips16
2462 && mips_opts
.isa
< 4
2463 && (! cop_interlocks
2464 && (prev_insn
.insn_mo
->pinfo
2465 & (INSN_LOAD_COPROC_DELAY
2466 | INSN_COPROC_MOVE_DELAY
2467 | INSN_WRITE_COND_CODE
))))
2468 || (! hilo_interlocks
2469 && (prev_insn
.insn_mo
->pinfo
2472 || (! mips_opts
.mips16
2474 && (prev_insn
.insn_mo
->pinfo
2475 & INSN_LOAD_MEMORY_DELAY
))
2476 || (! mips_opts
.mips16
2477 && mips_opts
.isa
< 2
2478 && (prev_insn
.insn_mo
->pinfo
2479 & INSN_COPROC_MEMORY_DELAY
)))
2481 /* Itbl support may require additional care here. */
2483 if ((! mips_opts
.mips16
2484 && mips_opts
.isa
< 4
2485 && (! cop_interlocks
2486 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2487 || (! hilo_interlocks
2488 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2489 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2492 if (prev_insn_unreordered
)
2495 else if ((! mips_opts
.mips16
2496 && mips_opts
.isa
< 4
2497 && (! cop_interlocks
2498 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2499 || (! hilo_interlocks
2500 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2501 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2503 /* Itbl support may require additional care here. */
2504 if (! prev_prev_insn_unreordered
)
2510 struct insn_label_list
*l
;
2514 /* Record the frag which holds the nop instructions, so
2515 that we can remove them if we don't need them. */
2516 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2517 prev_nop_frag
= frag_now
;
2518 prev_nop_frag_holds
= nops
;
2519 prev_nop_frag_required
= 0;
2520 prev_nop_frag_since
= 0;
2523 for (; nops
> 0; --nops
)
2528 /* Move on to a new frag, so that it is safe to simply
2529 decrease the size of prev_nop_frag. */
2530 frag_wane (frag_now
);
2534 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2536 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2537 l
->label
->sy_frag
= frag_now
;
2538 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2539 /* mips16 text labels are stored as odd. */
2540 if (mips_opts
.mips16
)
2541 ++l
->label
->sy_value
.X_add_number
;
2546 /* Mark instruction labels in mips16 mode. */
2547 if (mips_opts
.mips16
&& insns
)
2548 mips16_mark_labels ();
2550 mips_no_prev_insn (insns
);
2553 /* Build an instruction created by a macro expansion. This is passed
2554 a pointer to the count of instructions created so far, an
2555 expression, the name of the instruction to build, an operand format
2556 string, and corresponding arguments. */
2560 macro_build (char *place
,
2568 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2577 struct mips_cl_insn insn
;
2578 bfd_reloc_code_real_type r
;
2583 va_start (args
, fmt
);
2589 * If the macro is about to expand into a second instruction,
2590 * print a warning if needed. We need to pass ip as a parameter
2591 * to generate a better warning message here...
2593 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2594 as_warn (_("Macro instruction expanded into multiple instructions"));
2597 *counter
+= 1; /* bump instruction counter */
2599 if (mips_opts
.mips16
)
2601 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2606 r
= BFD_RELOC_UNUSED
;
2607 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2608 assert (insn
.insn_mo
);
2609 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2611 /* Search until we get a match for NAME. */
2614 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2616 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2618 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2620 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2625 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2626 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2627 && (insn_isa
<= mips_opts
.isa
2629 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2631 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2633 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2634 /* start-sanitize-vr4xxx */
2636 && (insn
.insn_mo
->membership
& INSN_4121
) != 0)
2637 /* end-sanitize-vr4xxx */
2638 /* start-sanitize-vr4320 */
2640 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2641 /* end-sanitize-vr4320 */
2642 /* start-sanitize-tx49 */
2644 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2645 /* end-sanitize-tx49 */
2646 /* start-sanitize-r5900 */
2648 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2649 /* end-sanitize-r5900 */
2650 /* start-sanitize-cygnus */
2652 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2653 /* end-sanitize-cygnus */
2655 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2656 /* start-sanitize-r5900 */
2657 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2658 /* end-sanitize-r5900 */
2659 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2663 assert (insn
.insn_mo
->name
);
2664 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2667 insn
.insn_opcode
= insn
.insn_mo
->match
;
2683 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2689 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2694 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2699 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2706 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2710 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2714 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2718 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2725 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2731 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2732 assert (r
== BFD_RELOC_MIPS_GPREL
2733 || r
== BFD_RELOC_MIPS_LITERAL
2734 || r
== BFD_RELOC_LO16
2735 || r
== BFD_RELOC_MIPS_GOT16
2736 || r
== BFD_RELOC_MIPS_CALL16
2737 || r
== BFD_RELOC_MIPS_GOT_LO16
2738 || r
== BFD_RELOC_MIPS_CALL_LO16
2739 || (ep
->X_op
== O_subtract
2740 && now_seg
== text_section
2741 && r
== BFD_RELOC_PCREL_LO16
));
2745 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2747 && (ep
->X_op
== O_constant
2748 || (ep
->X_op
== O_symbol
2749 && (r
== BFD_RELOC_HI16_S
2750 || r
== BFD_RELOC_HI16
2751 || r
== BFD_RELOC_MIPS_GOT_HI16
2752 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2753 || (ep
->X_op
== O_subtract
2754 && now_seg
== text_section
2755 && r
== BFD_RELOC_PCREL_HI16_S
)));
2756 if (ep
->X_op
== O_constant
)
2758 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2760 r
= BFD_RELOC_UNUSED
;
2765 assert (ep
!= NULL
);
2767 * This allows macro() to pass an immediate expression for
2768 * creating short branches without creating a symbol.
2769 * Note that the expression still might come from the assembly
2770 * input, in which case the value is not checked for range nor
2771 * is a relocation entry generated (yuck).
2773 if (ep
->X_op
== O_constant
)
2775 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2779 r
= BFD_RELOC_16_PCREL_S2
;
2783 assert (ep
!= NULL
);
2784 r
= BFD_RELOC_MIPS_JMP
;
2788 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2797 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2799 append_insn (place
, &insn
, ep
, r
, false);
2803 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2811 struct mips_cl_insn insn
;
2812 bfd_reloc_code_real_type r
;
2814 r
= BFD_RELOC_UNUSED
;
2815 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2816 assert (insn
.insn_mo
);
2817 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2819 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2820 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2823 assert (insn
.insn_mo
->name
);
2824 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2827 insn
.insn_opcode
= insn
.insn_mo
->match
;
2828 insn
.use_extend
= false;
2847 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2852 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2856 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2860 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2870 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2877 regno
= va_arg (args
, int);
2878 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2879 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2900 assert (ep
!= NULL
);
2902 if (ep
->X_op
!= O_constant
)
2903 r
= BFD_RELOC_UNUSED
+ c
;
2906 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2907 false, false, &insn
.insn_opcode
,
2908 &insn
.use_extend
, &insn
.extend
);
2910 r
= BFD_RELOC_UNUSED
;
2916 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2923 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2925 append_insn (place
, &insn
, ep
, r
, false);
2929 * Generate a "lui" instruction.
2932 macro_build_lui (place
, counter
, ep
, regnum
)
2938 expressionS high_expr
;
2939 struct mips_cl_insn insn
;
2940 bfd_reloc_code_real_type r
;
2941 CONST
char *name
= "lui";
2942 CONST
char *fmt
= "t,u";
2944 assert (! mips_opts
.mips16
);
2950 high_expr
.X_op
= O_constant
;
2951 high_expr
.X_add_number
= ep
->X_add_number
;
2954 if (high_expr
.X_op
== O_constant
)
2956 /* we can compute the instruction now without a relocation entry */
2957 if (high_expr
.X_add_number
& 0x8000)
2958 high_expr
.X_add_number
+= 0x10000;
2959 high_expr
.X_add_number
=
2960 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2961 r
= BFD_RELOC_UNUSED
;
2965 assert (ep
->X_op
== O_symbol
);
2966 /* _gp_disp is a special case, used from s_cpload. */
2967 assert (mips_pic
== NO_PIC
2968 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2969 r
= BFD_RELOC_HI16_S
;
2973 * If the macro is about to expand into a second instruction,
2974 * print a warning if needed. We need to pass ip as a parameter
2975 * to generate a better warning message here...
2977 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2978 as_warn (_("Macro instruction expanded into multiple instructions"));
2981 *counter
+= 1; /* bump instruction counter */
2983 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2984 assert (insn
.insn_mo
);
2985 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2986 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2988 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2989 if (r
== BFD_RELOC_UNUSED
)
2991 insn
.insn_opcode
|= high_expr
.X_add_number
;
2992 append_insn (place
, &insn
, NULL
, r
, false);
2995 append_insn (place
, &insn
, &high_expr
, r
, false);
2999 * Generates code to set the $at register to true (one)
3000 * if reg is less than the immediate expression.
3003 set_at (counter
, reg
, unsignedp
)
3008 if (imm_expr
.X_op
== O_constant
3009 && imm_expr
.X_add_number
>= -0x8000
3010 && imm_expr
.X_add_number
< 0x8000)
3011 macro_build ((char *) NULL
, counter
, &imm_expr
,
3012 unsignedp
? "sltiu" : "slti",
3013 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3016 load_register (counter
, AT
, &imm_expr
, 0);
3017 macro_build ((char *) NULL
, counter
, NULL
,
3018 unsignedp
? "sltu" : "slt",
3019 "d,v,t", AT
, reg
, AT
);
3023 /* Warn if an expression is not a constant. */
3026 check_absolute_expr (ip
, ex
)
3027 struct mips_cl_insn
*ip
;
3030 if (ex
->X_op
== O_big
)
3031 as_bad (_("unsupported large constant"));
3032 else if (ex
->X_op
!= O_constant
)
3033 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3036 /* Count the leading zeroes by performing a binary chop. This is a
3037 bulky bit of source, but performance is a LOT better for the
3038 majority of values than a simple loop to count the bits:
3039 for (lcnt = 0; (lcnt < 32); lcnt++)
3040 if ((v) & (1 << (31 - lcnt)))
3042 However it is not code size friendly, and the gain will drop a bit
3043 on certain cached systems.
3045 #define COUNT_TOP_ZEROES(v) \
3046 (((v) & ~0xffff) == 0 \
3047 ? ((v) & ~0xff) == 0 \
3048 ? ((v) & ~0xf) == 0 \
3049 ? ((v) & ~0x3) == 0 \
3050 ? ((v) & ~0x1) == 0 \
3055 : ((v) & ~0x7) == 0 \
3058 : ((v) & ~0x3f) == 0 \
3059 ? ((v) & ~0x1f) == 0 \
3062 : ((v) & ~0x7f) == 0 \
3065 : ((v) & ~0xfff) == 0 \
3066 ? ((v) & ~0x3ff) == 0 \
3067 ? ((v) & ~0x1ff) == 0 \
3070 : ((v) & ~0x7ff) == 0 \
3073 : ((v) & ~0x3fff) == 0 \
3074 ? ((v) & ~0x1fff) == 0 \
3077 : ((v) & ~0x7fff) == 0 \
3080 : ((v) & ~0xffffff) == 0 \
3081 ? ((v) & ~0xfffff) == 0 \
3082 ? ((v) & ~0x3ffff) == 0 \
3083 ? ((v) & ~0x1ffff) == 0 \
3086 : ((v) & ~0x7ffff) == 0 \
3089 : ((v) & ~0x3fffff) == 0 \
3090 ? ((v) & ~0x1fffff) == 0 \
3093 : ((v) & ~0x7fffff) == 0 \
3096 : ((v) & ~0xfffffff) == 0 \
3097 ? ((v) & ~0x3ffffff) == 0 \
3098 ? ((v) & ~0x1ffffff) == 0 \
3101 : ((v) & ~0x7ffffff) == 0 \
3104 : ((v) & ~0x3fffffff) == 0 \
3105 ? ((v) & ~0x1fffffff) == 0 \
3108 : ((v) & ~0x7fffffff) == 0 \
3113 * This routine generates the least number of instructions neccessary to load
3114 * an absolute expression value into a register.
3117 load_register (counter
, reg
, ep
, dbl
)
3124 expressionS hi32
, lo32
;
3126 if (ep
->X_op
!= O_big
)
3128 assert (ep
->X_op
== O_constant
);
3129 if (ep
->X_add_number
< 0x8000
3130 && (ep
->X_add_number
>= 0
3131 || (ep
->X_add_number
>= -0x8000
3134 || sizeof (ep
->X_add_number
) > 4))))
3136 /* We can handle 16 bit signed values with an addiu to
3137 $zero. No need to ever use daddiu here, since $zero and
3138 the result are always correct in 32 bit mode. */
3139 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3140 (int) BFD_RELOC_LO16
);
3143 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3145 /* We can handle 16 bit unsigned values with an ori to
3147 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3148 (int) BFD_RELOC_LO16
);
3151 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3152 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3153 == ~ (offsetT
) 0x7fffffff))
3156 || sizeof (ep
->X_add_number
) > 4
3157 || (ep
->X_add_number
& 0x80000000) == 0))
3158 || ((mips_opts
.isa
< 3 || ! dbl
)
3159 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3160 || (mips_opts
.isa
< 3
3162 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3163 == ~ (offsetT
) 0xffffffff)))
3165 /* 32 bit values require an lui. */
3166 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3167 (int) BFD_RELOC_HI16
);
3168 if ((ep
->X_add_number
& 0xffff) != 0)
3169 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3170 (int) BFD_RELOC_LO16
);
3175 /* The value is larger than 32 bits. */
3177 if (mips_opts
.isa
< 3)
3179 as_bad (_("Number larger than 32 bits"));
3180 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3181 (int) BFD_RELOC_LO16
);
3185 if (ep
->X_op
!= O_big
)
3188 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3189 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3190 hi32
.X_add_number
&= 0xffffffff;
3192 lo32
.X_add_number
&= 0xffffffff;
3196 assert (ep
->X_add_number
> 2);
3197 if (ep
->X_add_number
== 3)
3198 generic_bignum
[3] = 0;
3199 else if (ep
->X_add_number
> 4)
3200 as_bad (_("Number larger than 64 bits"));
3201 lo32
.X_op
= O_constant
;
3202 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3203 hi32
.X_op
= O_constant
;
3204 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3207 if (hi32
.X_add_number
== 0)
3212 unsigned long hi
, lo
;
3214 if (hi32
.X_add_number
== 0xffffffff)
3216 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3218 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3219 reg
, 0, (int) BFD_RELOC_LO16
);
3222 if (lo32
.X_add_number
& 0x80000000)
3224 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3225 (int) BFD_RELOC_HI16
);
3226 if (lo32
.X_add_number
& 0xffff)
3227 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3228 reg
, reg
, (int) BFD_RELOC_LO16
);
3233 /* Check for 16bit shifted constant. We know that hi32 is
3234 non-zero, so start the mask on the first bit of the hi32
3239 unsigned long himask
, lomask
;
3243 himask
= 0xffff >> (32 - shift
);
3244 lomask
= (0xffff << shift
) & 0xffffffff;
3248 himask
= 0xffff << (shift
- 32);
3251 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3252 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3256 tmp
.X_op
= O_constant
;
3258 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3259 | (lo32
.X_add_number
>> shift
));
3261 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3262 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3263 (int) BFD_RELOC_LO16
);
3264 macro_build ((char *) NULL
, counter
, NULL
,
3265 (shift
>= 32) ? "dsll32" : "dsll",
3267 (shift
>= 32) ? shift
- 32 : shift
);
3271 } while (shift
<= (64 - 16));
3273 /* Find the bit number of the lowest one bit, and store the
3274 shifted value in hi/lo. */
3275 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3276 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3280 while ((lo
& 1) == 0)
3285 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3291 while ((hi
& 1) == 0)
3300 /* Optimize if the shifted value is a (power of 2) - 1. */
3301 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3302 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3304 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3309 /* This instruction will set the register to be all
3311 tmp
.X_op
= O_constant
;
3312 tmp
.X_add_number
= (offsetT
) -1;
3313 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3314 reg
, 0, (int) BFD_RELOC_LO16
);
3318 macro_build ((char *) NULL
, counter
, NULL
,
3319 (bit
>= 32) ? "dsll32" : "dsll",
3321 (bit
>= 32) ? bit
- 32 : bit
);
3323 macro_build ((char *) NULL
, counter
, NULL
,
3324 (shift
>= 32) ? "dsrl32" : "dsrl",
3326 (shift
>= 32) ? shift
- 32 : shift
);
3331 /* Sign extend hi32 before calling load_register, because we can
3332 generally get better code when we load a sign extended value. */
3333 if ((hi32
.X_add_number
& 0x80000000) != 0)
3334 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3335 load_register (counter
, reg
, &hi32
, 0);
3338 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3342 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3351 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3353 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3354 (int) BFD_RELOC_HI16
);
3355 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3362 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3367 mid16
.X_add_number
>>= 16;
3368 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3369 freg
, (int) BFD_RELOC_LO16
);
3370 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3374 if ((lo32
.X_add_number
& 0xffff) != 0)
3375 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3376 (int) BFD_RELOC_LO16
);
3379 /* Load an address into a register. */
3382 load_address (counter
, reg
, ep
)
3389 if (ep
->X_op
!= O_constant
3390 && ep
->X_op
!= O_symbol
)
3392 as_bad (_("expression too complex"));
3393 ep
->X_op
= O_constant
;
3396 if (ep
->X_op
== O_constant
)
3398 load_register (counter
, reg
, ep
, 0);
3402 if (mips_pic
== NO_PIC
)
3404 /* If this is a reference to a GP relative symbol, we want
3405 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3407 lui $reg,<sym> (BFD_RELOC_HI16_S)
3408 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3409 If we have an addend, we always use the latter form. */
3410 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3411 || nopic_need_relax (ep
->X_add_symbol
, 1))
3416 macro_build ((char *) NULL
, counter
, ep
,
3417 ((bfd_arch_bits_per_address (stdoutput
) == 32
3418 || mips_opts
.isa
< 3)
3419 ? "addiu" : "daddiu"),
3420 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3421 p
= frag_var (rs_machine_dependent
, 8, 0,
3422 RELAX_ENCODE (4, 8, 0, 4, 0,
3423 mips_opts
.warn_about_macros
),
3424 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3426 macro_build_lui (p
, counter
, ep
, reg
);
3429 macro_build (p
, counter
, ep
,
3430 ((bfd_arch_bits_per_address (stdoutput
) == 32
3431 || mips_opts
.isa
< 3)
3432 ? "addiu" : "daddiu"),
3433 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3435 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3439 /* If this is a reference to an external symbol, we want
3440 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3442 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3444 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3445 If there is a constant, it must be added in after. */
3446 ex
.X_add_number
= ep
->X_add_number
;
3447 ep
->X_add_number
= 0;
3449 macro_build ((char *) NULL
, counter
, ep
,
3450 ((bfd_arch_bits_per_address (stdoutput
) == 32
3451 || mips_opts
.isa
< 3)
3453 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3454 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3455 p
= frag_var (rs_machine_dependent
, 4, 0,
3456 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3457 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3458 macro_build (p
, counter
, ep
,
3459 ((bfd_arch_bits_per_address (stdoutput
) == 32
3460 || mips_opts
.isa
< 3)
3461 ? "addiu" : "daddiu"),
3462 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3463 if (ex
.X_add_number
!= 0)
3465 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3466 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3467 ex
.X_op
= O_constant
;
3468 macro_build ((char *) NULL
, counter
, &ex
,
3469 ((bfd_arch_bits_per_address (stdoutput
) == 32
3470 || mips_opts
.isa
< 3)
3471 ? "addiu" : "daddiu"),
3472 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3475 else if (mips_pic
== SVR4_PIC
)
3480 /* This is the large GOT case. If this is a reference to an
3481 external symbol, we want
3482 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3484 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3485 Otherwise, for a reference to a local symbol, we want
3486 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3488 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3489 If there is a constant, it must be added in after. */
3490 ex
.X_add_number
= ep
->X_add_number
;
3491 ep
->X_add_number
= 0;
3492 if (reg_needs_delay (GP
))
3497 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3498 (int) BFD_RELOC_MIPS_GOT_HI16
);
3499 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3500 ((bfd_arch_bits_per_address (stdoutput
) == 32
3501 || mips_opts
.isa
< 3)
3502 ? "addu" : "daddu"),
3503 "d,v,t", reg
, reg
, GP
);
3504 macro_build ((char *) NULL
, counter
, ep
,
3505 ((bfd_arch_bits_per_address (stdoutput
) == 32
3506 || mips_opts
.isa
< 3)
3508 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3509 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3510 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3511 mips_opts
.warn_about_macros
),
3512 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3515 /* We need a nop before loading from $gp. This special
3516 check is required because the lui which starts the main
3517 instruction stream does not refer to $gp, and so will not
3518 insert the nop which may be required. */
3519 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3522 macro_build (p
, counter
, ep
,
3523 ((bfd_arch_bits_per_address (stdoutput
) == 32
3524 || mips_opts
.isa
< 3)
3526 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3528 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3530 macro_build (p
, counter
, ep
,
3531 ((bfd_arch_bits_per_address (stdoutput
) == 32
3532 || mips_opts
.isa
< 3)
3533 ? "addiu" : "daddiu"),
3534 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3535 if (ex
.X_add_number
!= 0)
3537 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3538 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3539 ex
.X_op
= O_constant
;
3540 macro_build ((char *) NULL
, counter
, &ex
,
3541 ((bfd_arch_bits_per_address (stdoutput
) == 32
3542 || mips_opts
.isa
< 3)
3543 ? "addiu" : "daddiu"),
3544 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3547 else if (mips_pic
== EMBEDDED_PIC
)
3550 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3552 macro_build ((char *) NULL
, counter
, ep
,
3553 ((bfd_arch_bits_per_address (stdoutput
) == 32
3554 || mips_opts
.isa
< 3)
3555 ? "addiu" : "daddiu"),
3556 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3564 * This routine implements the seemingly endless macro or synthesized
3565 * instructions and addressing modes in the mips assembly language. Many
3566 * of these macros are simple and are similar to each other. These could
3567 * probably be handled by some kind of table or grammer aproach instead of
3568 * this verbose method. Others are not simple macros but are more like
3569 * optimizing code generation.
3570 * One interesting optimization is when several store macros appear
3571 * consecutivly that would load AT with the upper half of the same address.
3572 * The ensuing load upper instructions are ommited. This implies some kind
3573 * of global optimization. We currently only optimize within a single macro.
3574 * For many of the load and store macros if the address is specified as a
3575 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3576 * first load register 'at' with zero and use it as the base register. The
3577 * mips assembler simply uses register $zero. Just one tiny optimization
3582 struct mips_cl_insn
*ip
;
3584 register int treg
, sreg
, dreg
, breg
;
3600 bfd_reloc_code_real_type r
;
3602 int hold_mips_optimize
;
3604 assert (! mips_opts
.mips16
);
3606 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3607 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3608 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3609 mask
= ip
->insn_mo
->mask
;
3611 expr1
.X_op
= O_constant
;
3612 expr1
.X_op_symbol
= NULL
;
3613 expr1
.X_add_symbol
= NULL
;
3614 expr1
.X_add_number
= 1;
3626 mips_emit_delays (true);
3627 ++mips_opts
.noreorder
;
3628 mips_any_noreorder
= 1;
3630 expr1
.X_add_number
= 8;
3631 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3633 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3635 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3636 macro_build ((char *) NULL
, &icnt
, NULL
,
3637 dbl
? "dsub" : "sub",
3638 "d,v,t", dreg
, 0, sreg
);
3640 --mips_opts
.noreorder
;
3661 if (imm_expr
.X_op
== O_constant
3662 && imm_expr
.X_add_number
>= -0x8000
3663 && imm_expr
.X_add_number
< 0x8000)
3665 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3666 (int) BFD_RELOC_LO16
);
3669 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3670 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3689 if (imm_expr
.X_op
== O_constant
3690 && imm_expr
.X_add_number
>= 0
3691 && imm_expr
.X_add_number
< 0x10000)
3693 if (mask
!= M_NOR_I
)
3694 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3695 sreg
, (int) BFD_RELOC_LO16
);
3698 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3699 treg
, sreg
, (int) BFD_RELOC_LO16
);
3700 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3706 load_register (&icnt
, AT
, &imm_expr
, 0);
3707 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3724 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3730 load_register (&icnt
, AT
, &imm_expr
, 0);
3731 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3739 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3740 likely
? "bgezl" : "bgez",
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3747 likely
? "blezl" : "blez",
3751 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3752 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3753 likely
? "beql" : "beq",
3760 /* check for > max integer */
3761 maxnum
= 0x7fffffff;
3762 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3769 if (imm_expr
.X_op
== O_constant
3770 && imm_expr
.X_add_number
>= maxnum
3771 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3774 /* result is always false */
3777 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3778 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3782 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3788 if (imm_expr
.X_op
!= O_constant
)
3789 as_bad (_("Unsupported large constant"));
3790 imm_expr
.X_add_number
++;
3794 if (mask
== M_BGEL_I
)
3796 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3798 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3799 likely
? "bgezl" : "bgez",
3803 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3805 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3806 likely
? "bgtzl" : "bgtz",
3810 maxnum
= 0x7fffffff;
3811 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3818 maxnum
= - maxnum
- 1;
3819 if (imm_expr
.X_op
== O_constant
3820 && imm_expr
.X_add_number
<= maxnum
3821 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3824 /* result is always true */
3825 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3829 set_at (&icnt
, sreg
, 0);
3830 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3831 likely
? "beql" : "beq",
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 likely
? "beql" : "beq",
3847 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3849 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3850 likely
? "beql" : "beq",
3858 || (mips_opts
.isa
< 3
3859 && imm_expr
.X_op
== O_constant
3860 && imm_expr
.X_add_number
== 0xffffffff))
3862 if (imm_expr
.X_op
!= O_constant
)
3863 as_bad (_("Unsupported large constant"));
3864 imm_expr
.X_add_number
++;
3868 if (mask
== M_BGEUL_I
)
3870 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3872 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3875 likely
? "bnel" : "bne",
3879 set_at (&icnt
, sreg
, 1);
3880 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3881 likely
? "beql" : "beq",
3890 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3891 likely
? "bgtzl" : "bgtz",
3897 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3898 likely
? "bltzl" : "bltz",
3902 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3903 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3904 likely
? "bnel" : "bne",
3913 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3914 likely
? "bnel" : "bne",
3920 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3922 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3923 likely
? "bnel" : "bne",
3932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3933 likely
? "blezl" : "blez",
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3940 likely
? "bgezl" : "bgez",
3944 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3945 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3946 likely
? "beql" : "beq",
3953 maxnum
= 0x7fffffff;
3954 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3961 if (imm_expr
.X_op
== O_constant
3962 && imm_expr
.X_add_number
>= maxnum
3963 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3965 if (imm_expr
.X_op
!= O_constant
)
3966 as_bad (_("Unsupported large constant"));
3967 imm_expr
.X_add_number
++;
3971 if (mask
== M_BLTL_I
)
3973 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3975 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3976 likely
? "bltzl" : "bltz",
3980 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3982 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3983 likely
? "blezl" : "blez",
3987 set_at (&icnt
, sreg
, 0);
3988 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3989 likely
? "bnel" : "bne",
3998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3999 likely
? "beql" : "beq",
4005 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4008 likely
? "beql" : "beq",
4016 || (mips_opts
.isa
< 3
4017 && imm_expr
.X_op
== O_constant
4018 && imm_expr
.X_add_number
== 0xffffffff))
4020 if (imm_expr
.X_op
!= O_constant
)
4021 as_bad (_("Unsupported large constant"));
4022 imm_expr
.X_add_number
++;
4026 if (mask
== M_BLTUL_I
)
4028 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4030 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4033 likely
? "beql" : "beq",
4037 set_at (&icnt
, sreg
, 1);
4038 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4039 likely
? "bnel" : "bne",
4048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4049 likely
? "bltzl" : "bltz",
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4056 likely
? "bgtzl" : "bgtz",
4060 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4061 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4062 likely
? "bnel" : "bne",
4073 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4074 likely
? "bnel" : "bne",
4078 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4081 likely
? "bnel" : "bne",
4097 as_warn (_("Divide by zero."));
4099 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4101 /* start-sanitize-r5900 */
4103 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4105 /* end-sanitize-r5900 */
4106 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4110 mips_emit_delays (true);
4111 ++mips_opts
.noreorder
;
4112 mips_any_noreorder
= 1;
4115 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4116 macro_build ((char *) NULL
, &icnt
, NULL
,
4117 dbl
? "ddiv" : "div",
4118 "z,s,t", sreg
, treg
);
4122 expr1
.X_add_number
= 8;
4123 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4124 macro_build ((char *) NULL
, &icnt
, NULL
,
4125 dbl
? "ddiv" : "div",
4126 "z,s,t", sreg
, treg
);
4127 /* start-sanitize-r5900 */
4129 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4131 /* end-sanitize-r5900 */
4132 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4134 expr1
.X_add_number
= -1;
4135 macro_build ((char *) NULL
, &icnt
, &expr1
,
4136 dbl
? "daddiu" : "addiu",
4137 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4138 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4139 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4142 expr1
.X_add_number
= 1;
4143 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4144 (int) BFD_RELOC_LO16
);
4145 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4150 expr1
.X_add_number
= 0x80000000;
4151 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4152 (int) BFD_RELOC_HI16
);
4156 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4157 /* We want to close the noreorder block as soon as possible, so
4158 that later insns are available for delay slot filling. */
4159 --mips_opts
.noreorder
;
4163 expr1
.X_add_number
= 8;
4164 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4165 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4167 /* We want to close the noreorder block as soon as possible, so
4168 that later insns are available for delay slot filling. */
4169 --mips_opts
.noreorder
;
4171 /* start-sanitize-r5900 */
4173 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
4175 /* end-sanitize-r5900 */
4176 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4178 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4217 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4219 as_warn (_("Divide by zero."));
4221 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4223 /* start-sanitize-r5900 */
4225 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4227 /* end-sanitize-r5900 */
4228 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4231 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4233 if (strcmp (s2
, "mflo") == 0)
4234 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4237 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4240 if (imm_expr
.X_op
== O_constant
4241 && imm_expr
.X_add_number
== -1
4242 && s
[strlen (s
) - 1] != 'u')
4244 if (strcmp (s2
, "mflo") == 0)
4247 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4250 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4254 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4258 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4259 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4260 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4279 mips_emit_delays (true);
4280 ++mips_opts
.noreorder
;
4281 mips_any_noreorder
= 1;
4284 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4285 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4286 /* We want to close the noreorder block as soon as possible, so
4287 that later insns are available for delay slot filling. */
4288 --mips_opts
.noreorder
;
4292 expr1
.X_add_number
= 8;
4293 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4294 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4296 /* We want to close the noreorder block as soon as possible, so
4297 that later insns are available for delay slot filling. */
4298 --mips_opts
.noreorder
;
4299 /* start-sanitize-r5900 */
4301 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4303 /* end-sanitize-r5900 */
4304 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4306 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4312 /* Load the address of a symbol into a register. If breg is not
4313 zero, we then add a base register to it. */
4315 /* When generating embedded PIC code, we permit expressions of
4318 where bar is an address in the .text section. These are used
4319 when getting the addresses of functions. We don't permit
4320 X_add_number to be non-zero, because if the symbol is
4321 external the relaxing code needs to know that any addend is
4322 purely the offset to X_op_symbol. */
4323 if (mips_pic
== EMBEDDED_PIC
4324 && offset_expr
.X_op
== O_subtract
4325 && now_seg
== text_section
4326 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4327 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4328 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4329 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4330 ->sy_value
.X_add_symbol
)
4333 && offset_expr
.X_add_number
== 0)
4335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4336 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4337 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4338 ((bfd_arch_bits_per_address (stdoutput
) == 32
4339 || mips_opts
.isa
< 3)
4340 ? "addiu" : "daddiu"),
4341 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4345 if (offset_expr
.X_op
!= O_symbol
4346 && offset_expr
.X_op
!= O_constant
)
4348 as_bad (_("expression too complex"));
4349 offset_expr
.X_op
= O_constant
;
4363 if (offset_expr
.X_op
== O_constant
)
4364 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4365 else if (mips_pic
== NO_PIC
)
4367 /* If this is a reference to an GP relative symbol, we want
4368 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4370 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4371 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4372 If we have a constant, we need two instructions anyhow,
4373 so we may as well always use the latter form. */
4374 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4375 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4380 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4381 ((bfd_arch_bits_per_address (stdoutput
) == 32
4382 || mips_opts
.isa
< 3)
4383 ? "addiu" : "daddiu"),
4384 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4385 p
= frag_var (rs_machine_dependent
, 8, 0,
4386 RELAX_ENCODE (4, 8, 0, 4, 0,
4387 mips_opts
.warn_about_macros
),
4388 offset_expr
.X_add_symbol
, (offsetT
) 0,
4391 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4394 macro_build (p
, &icnt
, &offset_expr
,
4395 ((bfd_arch_bits_per_address (stdoutput
) == 32
4396 || mips_opts
.isa
< 3)
4397 ? "addiu" : "daddiu"),
4398 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4400 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4402 /* If this is a reference to an external symbol, and there
4403 is no constant, we want
4404 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4405 For a local symbol, we want
4406 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4408 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4410 If we have a small constant, and this is a reference to
4411 an external symbol, we want
4412 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4414 addiu $tempreg,$tempreg,<constant>
4415 For a local symbol, we want the same instruction
4416 sequence, but we output a BFD_RELOC_LO16 reloc on the
4419 If we have a large constant, and this is a reference to
4420 an external symbol, we want
4421 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4422 lui $at,<hiconstant>
4423 addiu $at,$at,<loconstant>
4424 addu $tempreg,$tempreg,$at
4425 For a local symbol, we want the same instruction
4426 sequence, but we output a BFD_RELOC_LO16 reloc on the
4427 addiu instruction. */
4428 expr1
.X_add_number
= offset_expr
.X_add_number
;
4429 offset_expr
.X_add_number
= 0;
4431 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4433 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4434 if (expr1
.X_add_number
== 0)
4442 /* We're going to put in an addu instruction using
4443 tempreg, so we may as well insert the nop right
4445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4449 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4450 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4452 ? mips_opts
.warn_about_macros
4454 offset_expr
.X_add_symbol
, (offsetT
) 0,
4458 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4461 macro_build (p
, &icnt
, &expr1
,
4462 ((bfd_arch_bits_per_address (stdoutput
) == 32
4463 || mips_opts
.isa
< 3)
4464 ? "addiu" : "daddiu"),
4465 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4466 /* FIXME: If breg == 0, and the next instruction uses
4467 $tempreg, then if this variant case is used an extra
4468 nop will be generated. */
4470 else if (expr1
.X_add_number
>= -0x8000
4471 && expr1
.X_add_number
< 0x8000)
4473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4475 macro_build ((char *) NULL
, &icnt
, &expr1
,
4476 ((bfd_arch_bits_per_address (stdoutput
) == 32
4477 || mips_opts
.isa
< 3)
4478 ? "addiu" : "daddiu"),
4479 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4480 (void) frag_var (rs_machine_dependent
, 0, 0,
4481 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4482 offset_expr
.X_add_symbol
, (offsetT
) 0,
4489 /* If we are going to add in a base register, and the
4490 target register and the base register are the same,
4491 then we are using AT as a temporary register. Since
4492 we want to load the constant into AT, we add our
4493 current AT (from the global offset table) and the
4494 register into the register now, and pretend we were
4495 not using a base register. */
4500 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4502 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4503 ((bfd_arch_bits_per_address (stdoutput
) == 32
4504 || mips_opts
.isa
< 3)
4505 ? "addu" : "daddu"),
4506 "d,v,t", treg
, AT
, breg
);
4512 /* Set mips_optimize around the lui instruction to avoid
4513 inserting an unnecessary nop after the lw. */
4514 hold_mips_optimize
= mips_optimize
;
4516 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4517 mips_optimize
= hold_mips_optimize
;
4519 macro_build ((char *) NULL
, &icnt
, &expr1
,
4520 ((bfd_arch_bits_per_address (stdoutput
) == 32
4521 || mips_opts
.isa
< 3)
4522 ? "addiu" : "daddiu"),
4523 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4525 ((bfd_arch_bits_per_address (stdoutput
) == 32
4526 || mips_opts
.isa
< 3)
4527 ? "addu" : "daddu"),
4528 "d,v,t", tempreg
, tempreg
, AT
);
4529 (void) frag_var (rs_machine_dependent
, 0, 0,
4530 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4531 offset_expr
.X_add_symbol
, (offsetT
) 0,
4536 else if (mips_pic
== SVR4_PIC
)
4540 /* This is the large GOT case. If this is a reference to an
4541 external symbol, and there is no constant, we want
4542 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4543 addu $tempreg,$tempreg,$gp
4544 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4545 For a local symbol, we want
4546 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4548 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4550 If we have a small constant, and this is a reference to
4551 an external symbol, we want
4552 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4553 addu $tempreg,$tempreg,$gp
4554 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4556 addiu $tempreg,$tempreg,<constant>
4557 For a local symbol, we want
4558 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4560 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4562 If we have a large constant, and this is a reference to
4563 an external symbol, we want
4564 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4565 addu $tempreg,$tempreg,$gp
4566 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4567 lui $at,<hiconstant>
4568 addiu $at,$at,<loconstant>
4569 addu $tempreg,$tempreg,$at
4570 For a local symbol, we want
4571 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4572 lui $at,<hiconstant>
4573 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4574 addu $tempreg,$tempreg,$at
4576 expr1
.X_add_number
= offset_expr
.X_add_number
;
4577 offset_expr
.X_add_number
= 0;
4579 if (reg_needs_delay (GP
))
4583 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4584 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4585 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4586 ((bfd_arch_bits_per_address (stdoutput
) == 32
4587 || mips_opts
.isa
< 3)
4588 ? "addu" : "daddu"),
4589 "d,v,t", tempreg
, tempreg
, GP
);
4590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4592 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4594 if (expr1
.X_add_number
== 0)
4602 /* We're going to put in an addu instruction using
4603 tempreg, so we may as well insert the nop right
4605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4610 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4611 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4614 ? mips_opts
.warn_about_macros
4616 offset_expr
.X_add_symbol
, (offsetT
) 0,
4619 else if (expr1
.X_add_number
>= -0x8000
4620 && expr1
.X_add_number
< 0x8000)
4622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4624 macro_build ((char *) NULL
, &icnt
, &expr1
,
4625 ((bfd_arch_bits_per_address (stdoutput
) == 32
4626 || mips_opts
.isa
< 3)
4627 ? "addiu" : "daddiu"),
4628 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4630 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4631 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4633 ? mips_opts
.warn_about_macros
4635 offset_expr
.X_add_symbol
, (offsetT
) 0,
4642 /* If we are going to add in a base register, and the
4643 target register and the base register are the same,
4644 then we are using AT as a temporary register. Since
4645 we want to load the constant into AT, we add our
4646 current AT (from the global offset table) and the
4647 register into the register now, and pretend we were
4648 not using a base register. */
4656 assert (tempreg
== AT
);
4657 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4659 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4660 ((bfd_arch_bits_per_address (stdoutput
) == 32
4661 || mips_opts
.isa
< 3)
4662 ? "addu" : "daddu"),
4663 "d,v,t", treg
, AT
, breg
);
4668 /* Set mips_optimize around the lui instruction to avoid
4669 inserting an unnecessary nop after the lw. */
4670 hold_mips_optimize
= mips_optimize
;
4672 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4673 mips_optimize
= hold_mips_optimize
;
4675 macro_build ((char *) NULL
, &icnt
, &expr1
,
4676 ((bfd_arch_bits_per_address (stdoutput
) == 32
4677 || mips_opts
.isa
< 3)
4678 ? "addiu" : "daddiu"),
4679 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4680 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4681 ((bfd_arch_bits_per_address (stdoutput
) == 32
4682 || mips_opts
.isa
< 3)
4683 ? "addu" : "daddu"),
4684 "d,v,t", dreg
, dreg
, AT
);
4686 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4687 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4690 ? mips_opts
.warn_about_macros
4692 offset_expr
.X_add_symbol
, (offsetT
) 0,
4700 /* This is needed because this instruction uses $gp, but
4701 the first instruction on the main stream does not. */
4702 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4705 macro_build (p
, &icnt
, &offset_expr
,
4707 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4709 if (expr1
.X_add_number
>= -0x8000
4710 && expr1
.X_add_number
< 0x8000)
4712 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4714 macro_build (p
, &icnt
, &expr1
,
4715 ((bfd_arch_bits_per_address (stdoutput
) == 32
4716 || mips_opts
.isa
< 3)
4717 ? "addiu" : "daddiu"),
4718 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4719 /* FIXME: If add_number is 0, and there was no base
4720 register, the external symbol case ended with a load,
4721 so if the symbol turns out to not be external, and
4722 the next instruction uses tempreg, an unnecessary nop
4723 will be inserted. */
4729 /* We must add in the base register now, as in the
4730 external symbol case. */
4731 assert (tempreg
== AT
);
4732 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4734 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4735 ((bfd_arch_bits_per_address (stdoutput
) == 32
4736 || mips_opts
.isa
< 3)
4737 ? "addu" : "daddu"),
4738 "d,v,t", treg
, AT
, breg
);
4741 /* We set breg to 0 because we have arranged to add
4742 it in in both cases. */
4746 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4748 macro_build (p
, &icnt
, &expr1
,
4749 ((bfd_arch_bits_per_address (stdoutput
) == 32
4750 || mips_opts
.isa
< 3)
4751 ? "addiu" : "daddiu"),
4752 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4754 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4755 ((bfd_arch_bits_per_address (stdoutput
) == 32
4756 || mips_opts
.isa
< 3)
4757 ? "addu" : "daddu"),
4758 "d,v,t", tempreg
, tempreg
, AT
);
4762 else if (mips_pic
== EMBEDDED_PIC
)
4765 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4767 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4768 ((bfd_arch_bits_per_address (stdoutput
) == 32
4769 || mips_opts
.isa
< 3)
4770 ? "addiu" : "daddiu"),
4771 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4778 ((bfd_arch_bits_per_address (stdoutput
) == 32
4779 || mips_opts
.isa
< 3)
4780 ? "addu" : "daddu"),
4781 "d,v,t", treg
, tempreg
, breg
);
4789 /* The j instruction may not be used in PIC code, since it
4790 requires an absolute address. We convert it to a b
4792 if (mips_pic
== NO_PIC
)
4793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4795 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4798 /* The jal instructions must be handled as macros because when
4799 generating PIC code they expand to multi-instruction
4800 sequences. Normally they are simple instructions. */
4805 if (mips_pic
== NO_PIC
4806 || mips_pic
== EMBEDDED_PIC
)
4807 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4809 else if (mips_pic
== SVR4_PIC
)
4811 if (sreg
!= PIC_CALL_REG
)
4812 as_warn (_("MIPS PIC call to register other than $25"));
4814 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4816 if (mips_cprestore_offset
< 0)
4817 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4820 expr1
.X_add_number
= mips_cprestore_offset
;
4821 macro_build ((char *) NULL
, &icnt
, &expr1
,
4822 ((bfd_arch_bits_per_address (stdoutput
) == 32
4823 || mips_opts
.isa
< 3)
4825 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4834 if (mips_pic
== NO_PIC
)
4835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4836 else if (mips_pic
== SVR4_PIC
)
4838 /* If this is a reference to an external symbol, and we are
4839 using a small GOT, we want
4840 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4844 lw $gp,cprestore($sp)
4845 The cprestore value is set using the .cprestore
4846 pseudo-op. If we are using a big GOT, we want
4847 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4849 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4853 lw $gp,cprestore($sp)
4854 If the symbol is not external, we want
4855 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4857 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4860 lw $gp,cprestore($sp) */
4864 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4865 ((bfd_arch_bits_per_address (stdoutput
) == 32
4866 || mips_opts
.isa
< 3)
4868 "t,o(b)", PIC_CALL_REG
,
4869 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4870 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4872 p
= frag_var (rs_machine_dependent
, 4, 0,
4873 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4874 offset_expr
.X_add_symbol
, (offsetT
) 0,
4881 if (reg_needs_delay (GP
))
4885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4886 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4888 ((bfd_arch_bits_per_address (stdoutput
) == 32
4889 || mips_opts
.isa
< 3)
4890 ? "addu" : "daddu"),
4891 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4892 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4893 ((bfd_arch_bits_per_address (stdoutput
) == 32
4894 || mips_opts
.isa
< 3)
4896 "t,o(b)", PIC_CALL_REG
,
4897 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4898 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4900 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4901 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4903 offset_expr
.X_add_symbol
, (offsetT
) 0,
4907 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4910 macro_build (p
, &icnt
, &offset_expr
,
4911 ((bfd_arch_bits_per_address (stdoutput
) == 32
4912 || mips_opts
.isa
< 3)
4914 "t,o(b)", PIC_CALL_REG
,
4915 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4917 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4920 macro_build (p
, &icnt
, &offset_expr
,
4921 ((bfd_arch_bits_per_address (stdoutput
) == 32
4922 || mips_opts
.isa
< 3)
4923 ? "addiu" : "daddiu"),
4924 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4925 (int) BFD_RELOC_LO16
);
4926 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4927 "jalr", "s", PIC_CALL_REG
);
4928 if (mips_cprestore_offset
< 0)
4929 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4932 if (mips_opts
.noreorder
)
4933 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4935 expr1
.X_add_number
= mips_cprestore_offset
;
4936 macro_build ((char *) NULL
, &icnt
, &expr1
,
4937 ((bfd_arch_bits_per_address (stdoutput
) == 32
4938 || mips_opts
.isa
< 3)
4940 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4944 else if (mips_pic
== EMBEDDED_PIC
)
4946 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4947 /* The linker may expand the call to a longer sequence which
4948 uses $at, so we must break rather than return. */
4973 /* Itbl support may require additional care here. */
4978 /* Itbl support may require additional care here. */
4983 /* Itbl support may require additional care here. */
4988 /* Itbl support may require additional care here. */
5002 as_bad (_("opcode not supported on this processor"));
5006 /* Itbl support may require additional care here. */
5011 /* Itbl support may require additional care here. */
5016 /* Itbl support may require additional care here. */
5036 if (breg
== treg
|| coproc
|| lr
)
5058 /* Itbl support may require additional care here. */
5063 /* Itbl support may require additional care here. */
5068 /* Itbl support may require additional care here. */
5073 /* Itbl support may require additional care here. */
5091 as_bad (_("opcode not supported on this processor"));
5096 /* Itbl support may require additional care here. */
5100 /* Itbl support may require additional care here. */
5105 /* Itbl support may require additional care here. */
5117 /* Itbl support may require additional care here. */
5118 if (mask
== M_LWC1_AB
5119 || mask
== M_SWC1_AB
5120 || mask
== M_LDC1_AB
5121 || mask
== M_SDC1_AB
5130 if (offset_expr
.X_op
!= O_constant
5131 && offset_expr
.X_op
!= O_symbol
)
5133 as_bad (_("expression too complex"));
5134 offset_expr
.X_op
= O_constant
;
5137 /* A constant expression in PIC code can be handled just as it
5138 is in non PIC code. */
5139 if (mips_pic
== NO_PIC
5140 || offset_expr
.X_op
== O_constant
)
5142 /* If this is a reference to a GP relative symbol, and there
5143 is no base register, we want
5144 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5145 Otherwise, if there is no base register, we want
5146 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5147 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5148 If we have a constant, we need two instructions anyhow,
5149 so we always use the latter form.
5151 If we have a base register, and this is a reference to a
5152 GP relative symbol, we want
5153 addu $tempreg,$breg,$gp
5154 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5156 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5157 addu $tempreg,$tempreg,$breg
5158 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5159 With a constant we always use the latter case. */
5162 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5163 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5168 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5169 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5170 p
= frag_var (rs_machine_dependent
, 8, 0,
5171 RELAX_ENCODE (4, 8, 0, 4, 0,
5172 (mips_opts
.warn_about_macros
5174 && mips_opts
.noat
))),
5175 offset_expr
.X_add_symbol
, (offsetT
) 0,
5179 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5182 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5183 (int) BFD_RELOC_LO16
, tempreg
);
5187 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5188 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5193 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5194 ((bfd_arch_bits_per_address (stdoutput
) == 32
5195 || mips_opts
.isa
< 3)
5196 ? "addu" : "daddu"),
5197 "d,v,t", tempreg
, breg
, GP
);
5198 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5199 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5200 p
= frag_var (rs_machine_dependent
, 12, 0,
5201 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5202 offset_expr
.X_add_symbol
, (offsetT
) 0,
5205 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5208 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5209 ((bfd_arch_bits_per_address (stdoutput
) == 32
5210 || mips_opts
.isa
< 3)
5211 ? "addu" : "daddu"),
5212 "d,v,t", tempreg
, tempreg
, breg
);
5215 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5216 (int) BFD_RELOC_LO16
, tempreg
);
5219 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5221 /* If this is a reference to an external symbol, we want
5222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5224 <op> $treg,0($tempreg)
5226 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5228 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5229 <op> $treg,0($tempreg)
5230 If there is a base register, we add it to $tempreg before
5231 the <op>. If there is a constant, we stick it in the
5232 <op> instruction. We don't handle constants larger than
5233 16 bits, because we have no way to load the upper 16 bits
5234 (actually, we could handle them for the subset of cases
5235 in which we are not using $at). */
5236 assert (offset_expr
.X_op
== O_symbol
);
5237 expr1
.X_add_number
= offset_expr
.X_add_number
;
5238 offset_expr
.X_add_number
= 0;
5239 if (expr1
.X_add_number
< -0x8000
5240 || expr1
.X_add_number
>= 0x8000)
5241 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5244 ((bfd_arch_bits_per_address (stdoutput
) == 32
5245 || mips_opts
.isa
< 3)
5247 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5249 p
= frag_var (rs_machine_dependent
, 4, 0,
5250 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5251 offset_expr
.X_add_symbol
, (offsetT
) 0,
5253 macro_build (p
, &icnt
, &offset_expr
,
5254 ((bfd_arch_bits_per_address (stdoutput
) == 32
5255 || mips_opts
.isa
< 3)
5256 ? "addiu" : "daddiu"),
5257 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5259 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5260 ((bfd_arch_bits_per_address (stdoutput
) == 32
5261 || mips_opts
.isa
< 3)
5262 ? "addu" : "daddu"),
5263 "d,v,t", tempreg
, tempreg
, breg
);
5264 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5265 (int) BFD_RELOC_LO16
, tempreg
);
5267 else if (mips_pic
== SVR4_PIC
)
5271 /* If this is a reference to an external symbol, we want
5272 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5273 addu $tempreg,$tempreg,$gp
5274 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5275 <op> $treg,0($tempreg)
5277 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5279 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5280 <op> $treg,0($tempreg)
5281 If there is a base register, we add it to $tempreg before
5282 the <op>. If there is a constant, we stick it in the
5283 <op> instruction. We don't handle constants larger than
5284 16 bits, because we have no way to load the upper 16 bits
5285 (actually, we could handle them for the subset of cases
5286 in which we are not using $at). */
5287 assert (offset_expr
.X_op
== O_symbol
);
5288 expr1
.X_add_number
= offset_expr
.X_add_number
;
5289 offset_expr
.X_add_number
= 0;
5290 if (expr1
.X_add_number
< -0x8000
5291 || expr1
.X_add_number
>= 0x8000)
5292 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5293 if (reg_needs_delay (GP
))
5298 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5299 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5301 ((bfd_arch_bits_per_address (stdoutput
) == 32
5302 || mips_opts
.isa
< 3)
5303 ? "addu" : "daddu"),
5304 "d,v,t", tempreg
, tempreg
, GP
);
5305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5306 ((bfd_arch_bits_per_address (stdoutput
) == 32
5307 || mips_opts
.isa
< 3)
5309 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5311 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5312 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5313 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5316 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5319 macro_build (p
, &icnt
, &offset_expr
,
5320 ((bfd_arch_bits_per_address (stdoutput
) == 32
5321 || mips_opts
.isa
< 3)
5323 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5325 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5327 macro_build (p
, &icnt
, &offset_expr
,
5328 ((bfd_arch_bits_per_address (stdoutput
) == 32
5329 || mips_opts
.isa
< 3)
5330 ? "addiu" : "daddiu"),
5331 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5334 ((bfd_arch_bits_per_address (stdoutput
) == 32
5335 || mips_opts
.isa
< 3)
5336 ? "addu" : "daddu"),
5337 "d,v,t", tempreg
, tempreg
, breg
);
5338 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5339 (int) BFD_RELOC_LO16
, tempreg
);
5341 else if (mips_pic
== EMBEDDED_PIC
)
5343 /* If there is no base register, we want
5344 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5345 If there is a base register, we want
5346 addu $tempreg,$breg,$gp
5347 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5349 assert (offset_expr
.X_op
== O_symbol
);
5352 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5353 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5359 ((bfd_arch_bits_per_address (stdoutput
) == 32
5360 || mips_opts
.isa
< 3)
5361 ? "addu" : "daddu"),
5362 "d,v,t", tempreg
, breg
, GP
);
5363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5364 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5377 load_register (&icnt
, treg
, &imm_expr
, 0);
5381 load_register (&icnt
, treg
, &imm_expr
, 1);
5385 if (imm_expr
.X_op
== O_constant
)
5387 load_register (&icnt
, AT
, &imm_expr
, 0);
5388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5389 "mtc1", "t,G", AT
, treg
);
5394 assert (offset_expr
.X_op
== O_symbol
5395 && strcmp (segment_name (S_GET_SEGMENT
5396 (offset_expr
.X_add_symbol
)),
5398 && offset_expr
.X_add_number
== 0);
5399 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5400 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5405 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5406 the entire value, and in mips1 mode it is the high order 32
5407 bits of the value and the low order 32 bits are either zero
5408 or in offset_expr. */
5409 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5411 if (mips_opts
.isa
>= 3)
5412 load_register (&icnt
, treg
, &imm_expr
, 1);
5417 if (target_big_endian
)
5429 load_register (&icnt
, hreg
, &imm_expr
, 0);
5432 if (offset_expr
.X_op
== O_absent
)
5433 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5437 assert (offset_expr
.X_op
== O_constant
);
5438 load_register (&icnt
, lreg
, &offset_expr
, 0);
5445 /* We know that sym is in the .rdata section. First we get the
5446 upper 16 bits of the address. */
5447 if (mips_pic
== NO_PIC
)
5449 /* FIXME: This won't work for a 64 bit address. */
5450 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5452 else if (mips_pic
== SVR4_PIC
)
5454 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5455 ((bfd_arch_bits_per_address (stdoutput
) == 32
5456 || mips_opts
.isa
< 3)
5458 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5460 else if (mips_pic
== EMBEDDED_PIC
)
5462 /* For embedded PIC we pick up the entire address off $gp in
5463 a single instruction. */
5464 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5465 ((bfd_arch_bits_per_address (stdoutput
) == 32
5466 || mips_opts
.isa
< 3)
5467 ? "addiu" : "daddiu"),
5468 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5469 offset_expr
.X_op
= O_constant
;
5470 offset_expr
.X_add_number
= 0;
5475 /* Now we load the register(s). */
5476 if (mips_opts
.isa
>= 3)
5477 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5478 treg
, (int) BFD_RELOC_LO16
, AT
);
5481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5482 treg
, (int) BFD_RELOC_LO16
, AT
);
5485 /* FIXME: How in the world do we deal with the possible
5487 offset_expr
.X_add_number
+= 4;
5488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5489 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5493 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5494 does not become a variant frag. */
5495 frag_wane (frag_now
);
5501 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5502 the entire value, and in mips1 mode it is the high order 32
5503 bits of the value and the low order 32 bits are either zero
5504 or in offset_expr. */
5505 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5507 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5508 if (mips_opts
.isa
>= 3)
5509 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5510 "dmtc1", "t,S", AT
, treg
);
5513 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5514 "mtc1", "t,G", AT
, treg
+ 1);
5515 if (offset_expr
.X_op
== O_absent
)
5516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5517 "mtc1", "t,G", 0, treg
);
5520 assert (offset_expr
.X_op
== O_constant
);
5521 load_register (&icnt
, AT
, &offset_expr
, 0);
5522 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5523 "mtc1", "t,G", AT
, treg
);
5529 assert (offset_expr
.X_op
== O_symbol
5530 && offset_expr
.X_add_number
== 0);
5531 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5532 if (strcmp (s
, ".lit8") == 0)
5534 if (mips_opts
.isa
>= 2)
5536 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5537 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5541 r
= BFD_RELOC_MIPS_LITERAL
;
5546 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5547 if (mips_pic
== SVR4_PIC
)
5548 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5549 ((bfd_arch_bits_per_address (stdoutput
) == 32
5550 || mips_opts
.isa
< 3)
5552 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5555 /* FIXME: This won't work for a 64 bit address. */
5556 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5559 if (mips_opts
.isa
>= 2)
5561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5562 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5564 /* To avoid confusion in tc_gen_reloc, we must ensure
5565 that this does not become a variant frag. */
5566 frag_wane (frag_now
);
5579 as_bad (_("opcode not supported on this processor"));
5582 /* Even on a big endian machine $fn comes before $fn+1. We have
5583 to adjust when loading from memory. */
5586 assert (mips_opts
.isa
< 2);
5587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5588 target_big_endian
? treg
+ 1 : treg
,
5590 /* FIXME: A possible overflow which I don't know how to deal
5592 offset_expr
.X_add_number
+= 4;
5593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5594 target_big_endian
? treg
: treg
+ 1,
5597 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5598 does not become a variant frag. */
5599 frag_wane (frag_now
);
5608 * The MIPS assembler seems to check for X_add_number not
5609 * being double aligned and generating:
5612 * addiu at,at,%lo(foo+1)
5615 * But, the resulting address is the same after relocation so why
5616 * generate the extra instruction?
5620 as_bad (_("opcode not supported on this processor"));
5623 /* Itbl support may require additional care here. */
5625 if (mips_opts
.isa
>= 2)
5638 as_bad (_("opcode not supported on this processor"));
5642 if (mips_opts
.isa
>= 2)
5650 /* Itbl support may require additional care here. */
5655 if (mips_opts
.isa
>= 3)
5666 if (mips_opts
.isa
>= 3)
5676 if (offset_expr
.X_op
!= O_symbol
5677 && offset_expr
.X_op
!= O_constant
)
5679 as_bad (_("expression too complex"));
5680 offset_expr
.X_op
= O_constant
;
5683 /* Even on a big endian machine $fn comes before $fn+1. We have
5684 to adjust when loading from memory. We set coproc if we must
5685 load $fn+1 first. */
5686 /* Itbl support may require additional care here. */
5687 if (! target_big_endian
)
5690 if (mips_pic
== NO_PIC
5691 || offset_expr
.X_op
== O_constant
)
5693 /* If this is a reference to a GP relative symbol, we want
5694 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5695 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5696 If we have a base register, we use this
5698 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5699 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5700 If this is not a GP relative symbol, we want
5701 lui $at,<sym> (BFD_RELOC_HI16_S)
5702 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5703 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5704 If there is a base register, we add it to $at after the
5705 lui instruction. If there is a constant, we always use
5707 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5708 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5728 ((bfd_arch_bits_per_address (stdoutput
) == 32
5729 || mips_opts
.isa
< 3)
5730 ? "addu" : "daddu"),
5731 "d,v,t", AT
, breg
, GP
);
5737 /* Itbl support may require additional care here. */
5738 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5739 coproc
? treg
+ 1 : treg
,
5740 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5741 offset_expr
.X_add_number
+= 4;
5743 /* Set mips_optimize to 2 to avoid inserting an
5745 hold_mips_optimize
= mips_optimize
;
5747 /* Itbl support may require additional care here. */
5748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5749 coproc
? treg
: treg
+ 1,
5750 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5751 mips_optimize
= hold_mips_optimize
;
5753 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5754 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5755 used_at
&& mips_opts
.noat
),
5756 offset_expr
.X_add_symbol
, (offsetT
) 0,
5759 /* We just generated two relocs. When tc_gen_reloc
5760 handles this case, it will skip the first reloc and
5761 handle the second. The second reloc already has an
5762 extra addend of 4, which we added above. We must
5763 subtract it out, and then subtract another 4 to make
5764 the first reloc come out right. The second reloc
5765 will come out right because we are going to add 4 to
5766 offset_expr when we build its instruction below.
5768 If we have a symbol, then we don't want to include
5769 the offset, because it will wind up being included
5770 when we generate the reloc. */
5772 if (offset_expr
.X_op
== O_constant
)
5773 offset_expr
.X_add_number
-= 8;
5776 offset_expr
.X_add_number
= -4;
5777 offset_expr
.X_op
= O_constant
;
5780 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5785 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5786 ((bfd_arch_bits_per_address (stdoutput
) == 32
5787 || mips_opts
.isa
< 3)
5788 ? "addu" : "daddu"),
5789 "d,v,t", AT
, breg
, AT
);
5793 /* Itbl support may require additional care here. */
5794 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5795 coproc
? treg
+ 1 : treg
,
5796 (int) BFD_RELOC_LO16
, AT
);
5799 /* FIXME: How do we handle overflow here? */
5800 offset_expr
.X_add_number
+= 4;
5801 /* Itbl support may require additional care here. */
5802 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5803 coproc
? treg
: treg
+ 1,
5804 (int) BFD_RELOC_LO16
, AT
);
5806 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5810 /* If this is a reference to an external symbol, we want
5811 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5816 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5818 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5819 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5820 If there is a base register we add it to $at before the
5821 lwc1 instructions. If there is a constant we include it
5822 in the lwc1 instructions. */
5824 expr1
.X_add_number
= offset_expr
.X_add_number
;
5825 offset_expr
.X_add_number
= 0;
5826 if (expr1
.X_add_number
< -0x8000
5827 || expr1
.X_add_number
>= 0x8000 - 4)
5828 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5833 frag_grow (24 + off
);
5834 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5835 ((bfd_arch_bits_per_address (stdoutput
) == 32
5836 || mips_opts
.isa
< 3)
5838 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5842 ((bfd_arch_bits_per_address (stdoutput
) == 32
5843 || mips_opts
.isa
< 3)
5844 ? "addu" : "daddu"),
5845 "d,v,t", AT
, breg
, AT
);
5846 /* Itbl support may require additional care here. */
5847 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5848 coproc
? treg
+ 1 : treg
,
5849 (int) BFD_RELOC_LO16
, AT
);
5850 expr1
.X_add_number
+= 4;
5852 /* Set mips_optimize to 2 to avoid inserting an undesired
5854 hold_mips_optimize
= mips_optimize
;
5856 /* Itbl support may require additional care here. */
5857 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5858 coproc
? treg
: treg
+ 1,
5859 (int) BFD_RELOC_LO16
, AT
);
5860 mips_optimize
= hold_mips_optimize
;
5862 (void) frag_var (rs_machine_dependent
, 0, 0,
5863 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5864 offset_expr
.X_add_symbol
, (offsetT
) 0,
5867 else if (mips_pic
== SVR4_PIC
)
5871 /* If this is a reference to an external symbol, we want
5872 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5874 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5879 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5881 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5882 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5883 If there is a base register we add it to $at before the
5884 lwc1 instructions. If there is a constant we include it
5885 in the lwc1 instructions. */
5887 expr1
.X_add_number
= offset_expr
.X_add_number
;
5888 offset_expr
.X_add_number
= 0;
5889 if (expr1
.X_add_number
< -0x8000
5890 || expr1
.X_add_number
>= 0x8000 - 4)
5891 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5892 if (reg_needs_delay (GP
))
5901 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5902 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5903 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5904 ((bfd_arch_bits_per_address (stdoutput
) == 32
5905 || mips_opts
.isa
< 3)
5906 ? "addu" : "daddu"),
5907 "d,v,t", AT
, AT
, GP
);
5908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5909 ((bfd_arch_bits_per_address (stdoutput
) == 32
5910 || mips_opts
.isa
< 3)
5912 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5913 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5916 ((bfd_arch_bits_per_address (stdoutput
) == 32
5917 || mips_opts
.isa
< 3)
5918 ? "addu" : "daddu"),
5919 "d,v,t", AT
, breg
, AT
);
5920 /* Itbl support may require additional care here. */
5921 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5922 coproc
? treg
+ 1 : treg
,
5923 (int) BFD_RELOC_LO16
, AT
);
5924 expr1
.X_add_number
+= 4;
5926 /* Set mips_optimize to 2 to avoid inserting an undesired
5928 hold_mips_optimize
= mips_optimize
;
5930 /* Itbl support may require additional care here. */
5931 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5932 coproc
? treg
: treg
+ 1,
5933 (int) BFD_RELOC_LO16
, AT
);
5934 mips_optimize
= hold_mips_optimize
;
5935 expr1
.X_add_number
-= 4;
5937 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5938 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5939 8 + gpdel
+ off
, 1, 0),
5940 offset_expr
.X_add_symbol
, (offsetT
) 0,
5944 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5947 macro_build (p
, &icnt
, &offset_expr
,
5948 ((bfd_arch_bits_per_address (stdoutput
) == 32
5949 || mips_opts
.isa
< 3)
5951 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5953 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5957 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5958 ((bfd_arch_bits_per_address (stdoutput
) == 32
5959 || mips_opts
.isa
< 3)
5960 ? "addu" : "daddu"),
5961 "d,v,t", AT
, breg
, AT
);
5964 /* Itbl support may require additional care here. */
5965 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5966 coproc
? treg
+ 1 : treg
,
5967 (int) BFD_RELOC_LO16
, AT
);
5969 expr1
.X_add_number
+= 4;
5971 /* Set mips_optimize to 2 to avoid inserting an undesired
5973 hold_mips_optimize
= mips_optimize
;
5975 /* Itbl support may require additional care here. */
5976 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5977 coproc
? treg
: treg
+ 1,
5978 (int) BFD_RELOC_LO16
, AT
);
5979 mips_optimize
= hold_mips_optimize
;
5981 else if (mips_pic
== EMBEDDED_PIC
)
5983 /* If there is no base register, we use
5984 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5985 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5986 If we have a base register, we use
5988 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5989 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5999 ((bfd_arch_bits_per_address (stdoutput
) == 32
6000 || mips_opts
.isa
< 3)
6001 ? "addu" : "daddu"),
6002 "d,v,t", AT
, breg
, GP
);
6007 /* Itbl support may require additional care here. */
6008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6009 coproc
? treg
+ 1 : treg
,
6010 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6011 offset_expr
.X_add_number
+= 4;
6012 /* Itbl support may require additional care here. */
6013 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6014 coproc
? treg
: treg
+ 1,
6015 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6031 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
6032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6033 (int) BFD_RELOC_LO16
, breg
);
6034 offset_expr
.X_add_number
+= 4;
6035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6036 (int) BFD_RELOC_LO16
, breg
);
6039 /* New code added to support COPZ instructions.
6040 This code builds table entries out of the macros in mip_opcodes.
6041 R4000 uses interlocks to handle coproc delays.
6042 Other chips (like the R3000) require nops to be inserted for delays.
6044 FIXME: Currently, we require that the user handle delays.
6045 In order to fill delay slots for non-interlocked chips,
6046 we must have a way to specify delays based on the coprocessor.
6047 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6048 What are the side-effects of the cop instruction?
6049 What cache support might we have and what are its effects?
6050 Both coprocessor & memory require delays. how long???
6051 What registers are read/set/modified?
6053 If an itbl is provided to interpret cop instructions,
6054 this knowledge can be encoded in the itbl spec. */
6068 /* For now we just do C (same as Cz). The parameter will be
6069 stored in insn_opcode by mips_ip. */
6070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6074 #ifdef LOSING_COMPILER
6076 /* Try and see if this is a new itbl instruction.
6077 This code builds table entries out of the macros in mip_opcodes.
6078 FIXME: For now we just assemble the expression and pass it's
6079 value along as a 32-bit immediate.
6080 We may want to have the assembler assemble this value,
6081 so that we gain the assembler's knowledge of delay slots,
6083 Would it be more efficient to use mask (id) here? */
6084 if (itbl_have_entries
6085 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6087 s
= ip
->insn_mo
->name
;
6089 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6090 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6097 as_warn (_("Macro used $at after \".set noat\""));
6102 struct mips_cl_insn
*ip
;
6104 register int treg
, sreg
, dreg
, breg
;
6120 bfd_reloc_code_real_type r
;
6123 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6124 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6125 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6126 mask
= ip
->insn_mo
->mask
;
6128 expr1
.X_op
= O_constant
;
6129 expr1
.X_op_symbol
= NULL
;
6130 expr1
.X_add_symbol
= NULL
;
6131 expr1
.X_add_number
= 1;
6135 #endif /* LOSING_COMPILER */
6140 macro_build ((char *) NULL
, &icnt
, NULL
,
6141 dbl
? "dmultu" : "multu",
6143 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6149 /* The MIPS assembler some times generates shifts and adds. I'm
6150 not trying to be that fancy. GCC should do this for us
6152 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6153 macro_build ((char *) NULL
, &icnt
, NULL
,
6154 dbl
? "dmult" : "mult",
6156 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6169 mips_emit_delays (true);
6170 ++mips_opts
.noreorder
;
6171 mips_any_noreorder
= 1;
6173 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6174 macro_build ((char *) NULL
, &icnt
, NULL
,
6175 dbl
? "dmult" : "mult",
6176 "s,t", sreg
, imm
? AT
: treg
);
6177 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6178 macro_build ((char *) NULL
, &icnt
, NULL
,
6179 dbl
? "dsra32" : "sra",
6180 "d,w,<", dreg
, dreg
, 31);
6181 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6183 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6186 expr1
.X_add_number
= 8;
6187 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6188 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6189 /* start-sanitize-r5900 */
6191 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6193 /* end-sanitize-r5900 */
6194 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6196 --mips_opts
.noreorder
;
6197 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6210 mips_emit_delays (true);
6211 ++mips_opts
.noreorder
;
6212 mips_any_noreorder
= 1;
6214 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6215 macro_build ((char *) NULL
, &icnt
, NULL
,
6216 dbl
? "dmultu" : "multu",
6217 "s,t", sreg
, imm
? AT
: treg
);
6218 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6219 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6221 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6224 expr1
.X_add_number
= 8;
6225 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6226 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6227 /* start-sanitize-r5900 */
6229 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6231 /* end-sanitize-r5900 */
6232 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6234 --mips_opts
.noreorder
;
6238 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6239 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6240 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6242 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6246 if (imm_expr
.X_op
!= O_constant
)
6247 as_bad (_("rotate count too large"));
6248 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6249 (int) (imm_expr
.X_add_number
& 0x1f));
6250 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6251 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6252 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6256 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6257 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6258 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6260 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6264 if (imm_expr
.X_op
!= O_constant
)
6265 as_bad (_("rotate count too large"));
6266 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6267 (int) (imm_expr
.X_add_number
& 0x1f));
6268 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6269 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6270 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6276 as_bad (_("opcode not supported on this processor"));
6279 assert (mips_opts
.isa
< 2);
6280 /* Even on a big endian machine $fn comes before $fn+1. We have
6281 to adjust when storing to memory. */
6282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6283 target_big_endian
? treg
+ 1 : treg
,
6284 (int) BFD_RELOC_LO16
, breg
);
6285 offset_expr
.X_add_number
+= 4;
6286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6287 target_big_endian
? treg
: treg
+ 1,
6288 (int) BFD_RELOC_LO16
, breg
);
6293 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6294 treg
, (int) BFD_RELOC_LO16
);
6296 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6297 sreg
, (int) BFD_RELOC_LO16
);
6300 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6302 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6303 dreg
, (int) BFD_RELOC_LO16
);
6308 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6310 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6311 sreg
, (int) BFD_RELOC_LO16
);
6316 as_warn (_("Instruction %s: result is always false"),
6318 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6321 if (imm_expr
.X_op
== O_constant
6322 && imm_expr
.X_add_number
>= 0
6323 && imm_expr
.X_add_number
< 0x10000)
6325 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6326 sreg
, (int) BFD_RELOC_LO16
);
6329 else if (imm_expr
.X_op
== O_constant
6330 && imm_expr
.X_add_number
> -0x8000
6331 && imm_expr
.X_add_number
< 0)
6333 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6334 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6335 ((bfd_arch_bits_per_address (stdoutput
) == 32
6336 || mips_opts
.isa
< 3)
6337 ? "addiu" : "daddiu"),
6338 "t,r,j", dreg
, sreg
,
6339 (int) BFD_RELOC_LO16
);
6344 load_register (&icnt
, AT
, &imm_expr
, 0);
6345 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6349 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6350 (int) BFD_RELOC_LO16
);
6355 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6361 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6362 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6363 (int) BFD_RELOC_LO16
);
6366 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6368 if (imm_expr
.X_op
== O_constant
6369 && imm_expr
.X_add_number
>= -0x8000
6370 && imm_expr
.X_add_number
< 0x8000)
6372 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6373 mask
== M_SGE_I
? "slti" : "sltiu",
6374 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6379 load_register (&icnt
, AT
, &imm_expr
, 0);
6380 macro_build ((char *) NULL
, &icnt
, NULL
,
6381 mask
== M_SGE_I
? "slt" : "sltu",
6382 "d,v,t", dreg
, sreg
, AT
);
6385 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6386 (int) BFD_RELOC_LO16
);
6391 case M_SGT
: /* sreg > treg <==> treg < sreg */
6397 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6400 case M_SGT_I
: /* sreg > I <==> I < sreg */
6406 load_register (&icnt
, AT
, &imm_expr
, 0);
6407 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6410 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6416 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6417 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6418 (int) BFD_RELOC_LO16
);
6421 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6427 load_register (&icnt
, AT
, &imm_expr
, 0);
6428 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6429 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6430 (int) BFD_RELOC_LO16
);
6434 if (imm_expr
.X_op
== O_constant
6435 && imm_expr
.X_add_number
>= -0x8000
6436 && imm_expr
.X_add_number
< 0x8000)
6438 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6439 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6442 load_register (&icnt
, AT
, &imm_expr
, 0);
6443 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6447 if (imm_expr
.X_op
== O_constant
6448 && imm_expr
.X_add_number
>= -0x8000
6449 && imm_expr
.X_add_number
< 0x8000)
6451 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6452 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6455 load_register (&icnt
, AT
, &imm_expr
, 0);
6456 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6462 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6465 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6469 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6471 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6477 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6479 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6485 as_warn (_("Instruction %s: result is always true"),
6487 macro_build ((char *) NULL
, &icnt
, &expr1
,
6488 ((bfd_arch_bits_per_address (stdoutput
) == 32
6489 || mips_opts
.isa
< 3)
6490 ? "addiu" : "daddiu"),
6491 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6494 if (imm_expr
.X_op
== O_constant
6495 && imm_expr
.X_add_number
>= 0
6496 && imm_expr
.X_add_number
< 0x10000)
6498 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6499 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6502 else if (imm_expr
.X_op
== O_constant
6503 && imm_expr
.X_add_number
> -0x8000
6504 && imm_expr
.X_add_number
< 0)
6506 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6507 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6508 ((bfd_arch_bits_per_address (stdoutput
) == 32
6509 || mips_opts
.isa
< 3)
6510 ? "addiu" : "daddiu"),
6511 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6516 load_register (&icnt
, AT
, &imm_expr
, 0);
6517 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6521 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6529 if (imm_expr
.X_op
== O_constant
6530 && imm_expr
.X_add_number
> -0x8000
6531 && imm_expr
.X_add_number
<= 0x8000)
6533 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6534 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6535 dbl
? "daddi" : "addi",
6536 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6539 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6540 macro_build ((char *) NULL
, &icnt
, NULL
,
6541 dbl
? "dsub" : "sub",
6542 "d,v,t", dreg
, sreg
, AT
);
6548 if (imm_expr
.X_op
== O_constant
6549 && imm_expr
.X_add_number
> -0x8000
6550 && imm_expr
.X_add_number
<= 0x8000)
6552 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6553 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6554 dbl
? "daddiu" : "addiu",
6555 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6558 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6559 macro_build ((char *) NULL
, &icnt
, NULL
,
6560 dbl
? "dsubu" : "subu",
6561 "d,v,t", dreg
, sreg
, AT
);
6582 load_register (&icnt
, AT
, &imm_expr
, 0);
6583 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6588 assert (mips_opts
.isa
< 2);
6589 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6590 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6593 * Is the double cfc1 instruction a bug in the mips assembler;
6594 * or is there a reason for it?
6596 mips_emit_delays (true);
6597 ++mips_opts
.noreorder
;
6598 mips_any_noreorder
= 1;
6599 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6600 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6601 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6602 expr1
.X_add_number
= 3;
6603 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6604 (int) BFD_RELOC_LO16
);
6605 expr1
.X_add_number
= 2;
6606 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6607 (int) BFD_RELOC_LO16
);
6608 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6609 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6610 macro_build ((char *) NULL
, &icnt
, NULL
,
6611 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6612 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6613 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6614 --mips_opts
.noreorder
;
6623 if (offset_expr
.X_add_number
>= 0x7fff)
6624 as_bad (_("operand overflow"));
6625 /* avoid load delay */
6626 if (! target_big_endian
)
6627 offset_expr
.X_add_number
+= 1;
6628 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6629 (int) BFD_RELOC_LO16
, breg
);
6630 if (! target_big_endian
)
6631 offset_expr
.X_add_number
-= 1;
6633 offset_expr
.X_add_number
+= 1;
6634 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6635 (int) BFD_RELOC_LO16
, breg
);
6636 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6637 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6650 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6651 as_bad (_("operand overflow"));
6652 if (! target_big_endian
)
6653 offset_expr
.X_add_number
+= off
;
6654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6655 (int) BFD_RELOC_LO16
, breg
);
6656 if (! target_big_endian
)
6657 offset_expr
.X_add_number
-= off
;
6659 offset_expr
.X_add_number
+= off
;
6660 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6661 (int) BFD_RELOC_LO16
, breg
);
6674 load_address (&icnt
, AT
, &offset_expr
);
6676 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6677 ((bfd_arch_bits_per_address (stdoutput
) == 32
6678 || mips_opts
.isa
< 3)
6679 ? "addu" : "daddu"),
6680 "d,v,t", AT
, AT
, breg
);
6681 if (! target_big_endian
)
6682 expr1
.X_add_number
= off
;
6684 expr1
.X_add_number
= 0;
6685 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6686 (int) BFD_RELOC_LO16
, AT
);
6687 if (! target_big_endian
)
6688 expr1
.X_add_number
= 0;
6690 expr1
.X_add_number
= off
;
6691 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6692 (int) BFD_RELOC_LO16
, AT
);
6697 load_address (&icnt
, AT
, &offset_expr
);
6699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6700 ((bfd_arch_bits_per_address (stdoutput
) == 32
6701 || mips_opts
.isa
< 3)
6702 ? "addu" : "daddu"),
6703 "d,v,t", AT
, AT
, breg
);
6704 if (target_big_endian
)
6705 expr1
.X_add_number
= 0;
6706 macro_build ((char *) NULL
, &icnt
, &expr1
,
6707 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6708 (int) BFD_RELOC_LO16
, AT
);
6709 if (target_big_endian
)
6710 expr1
.X_add_number
= 1;
6712 expr1
.X_add_number
= 0;
6713 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6714 (int) BFD_RELOC_LO16
, AT
);
6715 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6717 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6722 if (offset_expr
.X_add_number
>= 0x7fff)
6723 as_bad (_("operand overflow"));
6724 if (target_big_endian
)
6725 offset_expr
.X_add_number
+= 1;
6726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6727 (int) BFD_RELOC_LO16
, breg
);
6728 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6729 if (target_big_endian
)
6730 offset_expr
.X_add_number
-= 1;
6732 offset_expr
.X_add_number
+= 1;
6733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6734 (int) BFD_RELOC_LO16
, breg
);
6747 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6748 as_bad (_("operand overflow"));
6749 if (! target_big_endian
)
6750 offset_expr
.X_add_number
+= off
;
6751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6752 (int) BFD_RELOC_LO16
, breg
);
6753 if (! target_big_endian
)
6754 offset_expr
.X_add_number
-= off
;
6756 offset_expr
.X_add_number
+= off
;
6757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6758 (int) BFD_RELOC_LO16
, breg
);
6771 load_address (&icnt
, AT
, &offset_expr
);
6773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6774 ((bfd_arch_bits_per_address (stdoutput
) == 32
6775 || mips_opts
.isa
< 3)
6776 ? "addu" : "daddu"),
6777 "d,v,t", AT
, AT
, breg
);
6778 if (! target_big_endian
)
6779 expr1
.X_add_number
= off
;
6781 expr1
.X_add_number
= 0;
6782 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6783 (int) BFD_RELOC_LO16
, AT
);
6784 if (! target_big_endian
)
6785 expr1
.X_add_number
= 0;
6787 expr1
.X_add_number
= off
;
6788 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6789 (int) BFD_RELOC_LO16
, AT
);
6793 load_address (&icnt
, AT
, &offset_expr
);
6795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6796 ((bfd_arch_bits_per_address (stdoutput
) == 32
6797 || mips_opts
.isa
< 3)
6798 ? "addu" : "daddu"),
6799 "d,v,t", AT
, AT
, breg
);
6800 if (! target_big_endian
)
6801 expr1
.X_add_number
= 0;
6802 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6803 (int) BFD_RELOC_LO16
, AT
);
6804 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6806 if (! target_big_endian
)
6807 expr1
.X_add_number
= 1;
6809 expr1
.X_add_number
= 0;
6810 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6811 (int) BFD_RELOC_LO16
, AT
);
6812 if (! target_big_endian
)
6813 expr1
.X_add_number
= 0;
6815 expr1
.X_add_number
= 1;
6816 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6817 (int) BFD_RELOC_LO16
, AT
);
6818 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6820 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6825 /* FIXME: Check if this is one of the itbl macros, since they
6826 are added dynamically. */
6827 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6831 as_warn (_("Macro used $at after \".set noat\""));
6834 /* Implement macros in mips16 mode. */
6838 struct mips_cl_insn
*ip
;
6841 int xreg
, yreg
, zreg
, tmp
;
6845 const char *s
, *s2
, *s3
;
6847 mask
= ip
->insn_mo
->mask
;
6849 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6850 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6851 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6855 expr1
.X_op
= O_constant
;
6856 expr1
.X_op_symbol
= NULL
;
6857 expr1
.X_add_symbol
= NULL
;
6858 expr1
.X_add_number
= 1;
6877 mips_emit_delays (true);
6878 ++mips_opts
.noreorder
;
6879 mips_any_noreorder
= 1;
6880 macro_build ((char *) NULL
, &icnt
, NULL
,
6881 dbl
? "ddiv" : "div",
6882 "0,x,y", xreg
, yreg
);
6883 expr1
.X_add_number
= 2;
6884 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6885 /* start-sanitize-r5900 */
6887 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6889 /* end-sanitize-r5900 */
6890 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6892 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6893 since that causes an overflow. We should do that as well,
6894 but I don't see how to do the comparisons without a temporary
6896 --mips_opts
.noreorder
;
6897 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6916 mips_emit_delays (true);
6917 ++mips_opts
.noreorder
;
6918 mips_any_noreorder
= 1;
6919 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6920 expr1
.X_add_number
= 2;
6921 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6922 /* start-sanitize-r5900 */
6924 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6926 /* end-sanitize-r5900 */
6927 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6928 --mips_opts
.noreorder
;
6929 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6935 macro_build ((char *) NULL
, &icnt
, NULL
,
6936 dbl
? "dmultu" : "multu",
6938 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6946 if (imm_expr
.X_op
!= O_constant
)
6947 as_bad (_("Unsupported large constant"));
6948 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6949 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6950 dbl
? "daddiu" : "addiu",
6951 "y,x,4", yreg
, xreg
);
6955 if (imm_expr
.X_op
!= O_constant
)
6956 as_bad (_("Unsupported large constant"));
6957 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6958 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6963 if (imm_expr
.X_op
!= O_constant
)
6964 as_bad (_("Unsupported large constant"));
6965 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6966 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6989 goto do_reverse_branch
;
6993 goto do_reverse_branch
;
7005 goto do_reverse_branch
;
7016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7045 goto do_addone_branch_i
;
7050 goto do_addone_branch_i
;
7065 goto do_addone_branch_i
;
7072 if (imm_expr
.X_op
!= O_constant
)
7073 as_bad (_("Unsupported large constant"));
7074 ++imm_expr
.X_add_number
;
7077 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7082 expr1
.X_add_number
= 0;
7083 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7085 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7086 "move", "y,X", xreg
, yreg
);
7087 expr1
.X_add_number
= 2;
7088 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7089 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7090 "neg", "x,w", xreg
, xreg
);
7094 /* For consistency checking, verify that all bits are specified either
7095 by the match/mask part of the instruction definition, or by the
7098 validate_mips_insn (opc
)
7099 const struct mips_opcode
*opc
;
7101 const char *p
= opc
->args
;
7103 unsigned long used_bits
= opc
->mask
;
7105 if ((used_bits
& opc
->match
) != opc
->match
)
7107 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7108 opc
->name
, opc
->args
);
7111 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7118 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7119 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7121 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
7122 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7123 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7124 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7126 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7129 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7130 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7131 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7132 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7133 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7134 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7135 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7136 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7137 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7138 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7139 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7141 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7142 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7143 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7144 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7146 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7147 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7148 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7149 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7150 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7151 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7152 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7153 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7154 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7157 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7158 /* start-sanitize-r5900 */
7159 case '0': USE_BITS (OP_MASK_VADDI
, OP_SH_VADDI
); break;
7160 case '1': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7161 case '2': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7162 case '3': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7163 case '4': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7164 case '5': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7165 case '6': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7167 USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
);
7168 USE_BITS (OP_MASK_VUFTF
, OP_SH_VUFTF
);
7171 USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
);
7172 USE_BITS (OP_MASK_VUFSF
, OP_SH_VUFSF
);
7180 case 'O': USE_BITS (OP_MASK_VUCALLMS
, OP_SH_VUCALLMS
);break;
7181 case '&': USE_BITS (OP_MASK_VUDEST
, OP_SH_VUDEST
); break;
7188 /* end-sanitize-r5900 */
7189 /* start-sanitize-cygnus */
7190 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7191 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7194 /* end-sanitize-cygnus */
7196 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7197 c
, opc
->name
, opc
->args
);
7201 if (used_bits
!= 0xffffffff)
7203 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7204 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7210 /* This routine assembles an instruction into its binary format. As a
7211 side effect, it sets one of the global variables imm_reloc or
7212 offset_reloc to the type of relocation to do if one of the operands
7213 is an address expression. */
7218 struct mips_cl_insn
*ip
;
7223 struct mips_opcode
*insn
;
7226 unsigned int lastregno
= 0;
7229 int full_opcode_match
= 1;
7233 /* If the instruction contains a '.', we first try to match an instruction
7234 including the '.'. Then we try again without the '.'. */
7236 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
7239 /* If we stopped on whitespace, then replace the whitespace with null for
7240 the call to hash_find. Save the character we replaced just in case we
7241 have to re-parse the instruction. */
7248 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7250 /* If we didn't find the instruction in the opcode table, try again, but
7251 this time with just the instruction up to, but not including the
7255 /* Restore the character we overwrite above (if any). */
7259 /* Scan up to the first '.' or whitespace. */
7260 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
7263 /* If we did not find a '.', then we can quit now. */
7266 insn_error
= "unrecognized opcode";
7270 /* Lookup the instruction in the hash table. */
7272 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7274 insn_error
= "unrecognized opcode";
7278 full_opcode_match
= 0;
7287 assert (strcmp (insn
->name
, str
) == 0);
7289 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7291 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7293 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7295 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7300 if (insn_isa
<= mips_opts
.isa
)
7302 else if (insn
->pinfo
== INSN_MACRO
)
7304 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7305 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7306 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7307 /* start-sanitize-vr4xxx */
7308 || (mips_4121
&& (insn
->membership
& INSN_4121
) != 0)
7309 /* end-sanitize-vr4xxx */
7310 /* start-sanitize-vr4320 */
7311 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7312 /* end-sanitize-vr4320 */
7313 /* start-sanitize-tx49 */
7314 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7315 /* end-sanitize-tx49 */
7316 /* start-sanitize-r5900 */
7317 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7318 /* end-sanitize-r5900 */
7319 /* start-sanitize-cygnus */
7320 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7321 /* end-sanitize-cygnus */
7322 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7327 if (insn
->pinfo
!= INSN_MACRO
)
7329 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7331 /* start-sanitize-r5900 */
7332 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7334 /* end-sanitize-r5900 */
7339 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7340 && strcmp (insn
->name
, insn
[1].name
) == 0)
7346 || insn_isa
<= mips_opts
.isa
)
7347 insn_error
= _("opcode not supported on this processor");
7350 static char buf
[100];
7352 sprintf (buf
, _("opcode requires -mips%d or greater"), insn_isa
);
7359 ip
->insn_opcode
= insn
->match
;
7360 for (args
= insn
->args
;; ++args
)
7366 case '\0': /* end of args */
7379 ip
->insn_opcode
|= lastregno
<< 21;
7384 ip
->insn_opcode
|= lastregno
<< 16;
7388 ip
->insn_opcode
|= lastregno
<< 11;
7394 /* Handle optional base register.
7395 Either the base register is omitted or
7396 we must have a left paren. */
7397 /* This is dependent on the next operand specifier
7398 is a base register specification. */
7399 assert (args
[1] == 'b' || args
[1] == '5'
7400 || args
[1] == '-' || args
[1] == '4');
7404 case ')': /* these must match exactly */
7405 /* start-sanitize-cygnus */
7408 /* end-sanitize-cygnus */
7409 /* start-sanitize-r5900 */
7412 /* end-sanitize-r5900 */
7417 case '<': /* must be at least one digit */
7419 * According to the manual, if the shift amount is greater
7420 * than 31 or less than 0 the the shift amount should be
7421 * mod 32. In reality the mips assembler issues an error.
7422 * We issue a warning and mask out all but the low 5 bits.
7424 my_getExpression (&imm_expr
, s
);
7425 check_absolute_expr (ip
, &imm_expr
);
7426 if ((unsigned long) imm_expr
.X_add_number
> 31)
7428 as_warn (_("Improper shift amount (%ld)"),
7429 (long) imm_expr
.X_add_number
);
7430 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7432 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7433 imm_expr
.X_op
= O_absent
;
7437 case '>': /* shift amount minus 32 */
7438 my_getExpression (&imm_expr
, s
);
7439 check_absolute_expr (ip
, &imm_expr
);
7440 if ((unsigned long) imm_expr
.X_add_number
< 32
7441 || (unsigned long) imm_expr
.X_add_number
> 63)
7443 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7444 imm_expr
.X_op
= O_absent
;
7448 /* start-sanitize-r5900 */
7449 case '0': /* 5 bit signed immediate at 6 */
7450 my_getExpression (&imm_expr
, s
);
7451 check_absolute_expr (ip
, &imm_expr
);
7452 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7453 || ((imm_expr
.X_add_number
< -16
7454 || imm_expr
.X_add_number
>= 16)
7455 && imm_expr
.X_op
== O_constant
))
7457 if (imm_expr
.X_op
!= O_constant
7458 && imm_expr
.X_op
!= O_big
)
7459 insn_error
= "absolute expression required";
7461 as_bad (_("5 bit expression not in range -16..15"));
7463 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7464 imm_expr
.X_op
= O_absent
;
7468 case '9': /* vi27 for vcallmsr */
7469 if (strncmp (s
, "$vi27", 5) == 0)
7471 else if (strncmp (s
, "vi27", 4) == 0)
7474 as_bad (_("expected vi27"));
7477 case '#': /* escape character */
7478 /* '#' specifies that we've got an optional suffix to this
7479 operand that must match exactly (if it exists). */
7480 if (*s
!= '\0' && *s
!= ','
7481 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7483 if (*s
== *(args
+ 1))
7494 case 'K': /* DEST operand completer (optional), must
7495 match previous dest if specified. */
7496 case '&': /* DEST instruction completer */
7497 case ';': /* DEST instruction completer, must be xyz */
7504 /* Parse the completer. */
7506 while ((!full_opcode_match
|| *args
== 'K')
7507 && *s
!= '\0' && *s
!= ' ' && *s
!= ',')
7519 insn_error
= "Invalid dest specification";
7528 /* Each completer can only appear once. */
7529 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7531 insn_error
= "Invalid dest specification";
7535 /* If this is the opcode completer, then we must insert
7536 the appropriate value into the insn. */
7539 /* Not strictly in the specs, but requested by users. */
7540 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7543 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7544 | (y
<< 23) | (z
<< 22));
7545 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7547 else if (*args
== ';')
7549 /* This implicitly has the .xyz completer. */
7550 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7553 if (w
!= 0 || x
!= 1 || y
!= 1 || z
!= 1)
7555 insn_error
= "Invalid dest specification";
7559 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7565 /* This is the operand completer, make sure it matches
7566 the previous opcode completer. */
7567 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7568 if (temp
&& temp
!= last_h
)
7570 insn_error
= "DEST field in operand does not match DEST field in instruction";
7579 case 'J': /* vu0 I register */
7583 insn_error
= "operand `I' expected";
7586 case 'Q': /* vu0 Q register */
7590 insn_error
= "operand `Q' expected";
7593 case 'X': /* vu0 R register */
7597 insn_error
= "operand `R' expected";
7600 case 'U': /* vu0 ACC register */
7601 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7604 insn_error
= "operand `ACC' expected";
7608 my_getSmallExpression (&imm_expr
, s
);
7609 imm_reloc
= BFD_RELOC_MIPS15_S3
;
7612 /* end-sanitize-r5900 */
7614 case 'k': /* cache code */
7615 case 'h': /* prefx code */
7616 my_getExpression (&imm_expr
, s
);
7617 check_absolute_expr (ip
, &imm_expr
);
7618 if ((unsigned long) imm_expr
.X_add_number
> 31)
7620 as_warn (_("Invalid value for `%s' (%lu)"),
7622 (unsigned long) imm_expr
.X_add_number
);
7623 imm_expr
.X_add_number
&= 0x1f;
7626 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7628 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7629 imm_expr
.X_op
= O_absent
;
7633 case 'c': /* break code */
7634 my_getExpression (&imm_expr
, s
);
7635 check_absolute_expr (ip
, &imm_expr
);
7636 if ((unsigned) imm_expr
.X_add_number
> 1023)
7638 as_warn (_("Illegal break code (%ld)"),
7639 (long) imm_expr
.X_add_number
);
7640 imm_expr
.X_add_number
&= 0x3ff;
7642 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7643 imm_expr
.X_op
= O_absent
;
7647 case 'q': /* lower break code */
7648 my_getExpression (&imm_expr
, s
);
7649 check_absolute_expr (ip
, &imm_expr
);
7650 if ((unsigned) imm_expr
.X_add_number
> 1023)
7652 as_warn (_("Illegal lower break code (%ld)"),
7653 (long) imm_expr
.X_add_number
);
7654 imm_expr
.X_add_number
&= 0x3ff;
7656 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7657 imm_expr
.X_op
= O_absent
;
7661 case 'B': /* syscall code */
7662 my_getExpression (&imm_expr
, s
);
7663 check_absolute_expr (ip
, &imm_expr
);
7664 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7665 as_warn (_("Illegal syscall code (%ld)"),
7666 (long) imm_expr
.X_add_number
);
7667 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7668 imm_expr
.X_op
= O_absent
;
7672 case 'C': /* Coprocessor code */
7673 my_getExpression (&imm_expr
, s
);
7674 check_absolute_expr (ip
, &imm_expr
);
7675 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7677 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7678 (long) imm_expr
.X_add_number
);
7679 imm_expr
.X_add_number
&= ((1<<25) - 1);
7681 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7682 imm_expr
.X_op
= O_absent
;
7686 case 'P': /* Performance register */
7687 my_getExpression (&imm_expr
, s
);
7688 check_absolute_expr (ip
, &imm_expr
);
7689 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7691 as_warn (_("Invalidate performance regster (%ld)"),
7692 (long) imm_expr
.X_add_number
);
7693 imm_expr
.X_add_number
&= 1;
7695 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7696 imm_expr
.X_op
= O_absent
;
7700 case 'b': /* base register */
7701 case 'd': /* destination register */
7702 case 's': /* source register */
7703 case 't': /* target register */
7704 case 'r': /* both target and source */
7705 case 'v': /* both dest and source */
7706 case 'w': /* both dest and target */
7707 case 'E': /* coprocessor target register */
7708 case 'G': /* coprocessor destination register */
7709 case 'x': /* ignore register name */
7710 case 'z': /* must be zero register */
7714 /* start-sanitize-r5900 */
7715 /* Allow "$viNN" as coprocessor register name */
7723 /* end-sanitize-r5900 */
7735 while (isdigit (*s
));
7737 as_bad (_("Invalid register number (%d)"), regno
);
7739 else if (*args
== 'E' || *args
== 'G')
7743 if (s
[1] == 'f' && s
[2] == 'p')
7748 else if (s
[1] == 's' && s
[2] == 'p')
7753 else if (s
[1] == 'g' && s
[2] == 'p')
7758 else if (s
[1] == 'a' && s
[2] == 't')
7763 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7768 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7773 else if (itbl_have_entries
)
7778 p
= s
+1; /* advance past '$' */
7779 n
= itbl_get_field (&p
); /* n is name */
7781 /* See if this is a register defined in an
7783 r
= itbl_get_reg_val (n
);
7786 /* Get_field advances to the start of
7787 the next field, so we need to back
7788 rack to the end of the last field. */
7792 s
= strchr (s
,'\0');
7805 as_warn (_("Used $at without \".set noat\""));
7811 if (c
== 'r' || c
== 'v' || c
== 'w')
7818 /* 'z' only matches $0. */
7819 if (c
== 'z' && regno
!= 0)
7822 /* Now that we have assembled one operand, we use the args string
7823 * to figure out where it goes in the instruction. */
7830 ip
->insn_opcode
|= regno
<< 21;
7834 ip
->insn_opcode
|= regno
<< 11;
7839 ip
->insn_opcode
|= regno
<< 16;
7842 /* This case exists because on the r3000 trunc
7843 expands into a macro which requires a gp
7844 register. On the r6000 or r4000 it is
7845 assembled into a single instruction which
7846 ignores the register. Thus the insn version
7847 is MIPS_ISA2 and uses 'x', and the macro
7848 version is MIPS_ISA1 and uses 't'. */
7851 /* This case is for the div instruction, which
7852 acts differently if the destination argument
7853 is $0. This only matches $0, and is checked
7854 outside the switch. */
7857 /* Itbl operand; not yet implemented. FIXME ?? */
7859 /* What about all other operands like 'i', which
7860 can be specified in the opcode table? */
7870 ip
->insn_opcode
|= lastregno
<< 21;
7873 ip
->insn_opcode
|= lastregno
<< 16;
7878 case 'D': /* floating point destination register */
7879 case 'S': /* floating point source register */
7880 case 'T': /* floating point target register */
7881 case 'R': /* floating point source register */
7884 /* start-sanitize-r5900 */
7885 case '1': /* vu0 fp reg position 1 */
7886 case '2': /* vu0 fp reg position 2 */
7887 case '3': /* vu0 fp reg position 3 */
7888 case '4': /* vu0 int reg position 1 */
7889 case '5': /* vu0 int reg position 2 */
7890 case '6': /* vu0 int reg position 3 */
7891 case '7': /* vu0 fp reg with ftf modifier */
7892 case '8': /* vu0 fp reg with fsf modifier */
7893 /* end-sanitize-r5900 */
7895 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7905 while (isdigit (*s
));
7908 as_bad (_("Invalid float register number (%d)"), regno
);
7910 if ((regno
& 1) != 0
7911 && mips_opts
.isa
< 3
7912 && ! (strcmp (str
, "mtc1") == 0
7913 || strcmp (str
, "mfc1") == 0
7914 || strcmp (str
, "lwc1") == 0
7915 || strcmp (str
, "swc1") == 0
7916 || strcmp (str
, "l.s") == 0
7917 || strcmp (str
, "s.s") == 0))
7918 as_warn (_("Float register should be even, was %d"),
7926 if (c
== 'V' || c
== 'W')
7936 ip
->insn_opcode
|= regno
<< 6;
7940 ip
->insn_opcode
|= regno
<< 11;
7944 ip
->insn_opcode
|= regno
<< 16;
7947 ip
->insn_opcode
|= regno
<< 21;
7954 /* start-sanitize-r5900 */
7955 /* Handle vf and vi regsiters for vu0. Handle optional
7959 && (s
[1] == 'f' || s
[1] == 'i')
7964 && (s
[2] == 'f' || s
[2] == 'i')
7977 while (isdigit (*s
));
7980 as_bad (_("Invalid vu0 register number (%d)"), regno
);
7984 if (c
== '7' || c
== '8')
7993 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7998 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
8003 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
8008 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
8011 as_bad (_("Invalid FSF/FTF specification"));
8019 if (c
== 'V' || c
== 'W')
8031 ip
->insn_opcode
|= regno
<< 16;
8036 ip
->insn_opcode
|= regno
<< 11;
8040 ip
->insn_opcode
|= regno
<< 6;
8046 /* end-sanitize-r5900 */
8051 ip
->insn_opcode
|= lastregno
<< 11;
8054 ip
->insn_opcode
|= lastregno
<< 16;
8060 my_getExpression (&imm_expr
, s
);
8061 if (imm_expr
.X_op
!= O_big
8062 && imm_expr
.X_op
!= O_constant
)
8063 insn_error
= _("absolute expression required");
8068 my_getExpression (&offset_expr
, s
);
8069 imm_reloc
= BFD_RELOC_32
;
8081 unsigned char temp
[8];
8083 unsigned int length
;
8088 /* These only appear as the last operand in an
8089 instruction, and every instruction that accepts
8090 them in any variant accepts them in all variants.
8091 This means we don't have to worry about backing out
8092 any changes if the instruction does not match.
8094 The difference between them is the size of the
8095 floating point constant and where it goes. For 'F'
8096 and 'L' the constant is 64 bits; for 'f' and 'l' it
8097 is 32 bits. Where the constant is placed is based
8098 on how the MIPS assembler does things:
8101 f -- immediate value
8104 The .lit4 and .lit8 sections are only used if
8105 permitted by the -G argument.
8107 When generating embedded PIC code, we use the
8108 .lit8 section but not the .lit4 section (we can do
8109 .lit4 inline easily; we need to put .lit8
8110 somewhere in the data segment, and using .lit8
8111 permits the linker to eventually combine identical
8114 f64
= *args
== 'F' || *args
== 'L';
8116 save_in
= input_line_pointer
;
8117 input_line_pointer
= s
;
8118 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8120 s
= input_line_pointer
;
8121 input_line_pointer
= save_in
;
8122 if (err
!= NULL
&& *err
!= '\0')
8124 as_bad (_("Bad floating point constant: %s"), err
);
8125 memset (temp
, '\0', sizeof temp
);
8126 length
= f64
? 8 : 4;
8129 assert (length
== (f64
? 8 : 4));
8133 && (! USE_GLOBAL_POINTER_OPT
8134 || mips_pic
== EMBEDDED_PIC
8135 || g_switch_value
< 4
8136 || (temp
[0] == 0 && temp
[1] == 0)
8137 || (temp
[2] == 0 && temp
[3] == 0))))
8139 imm_expr
.X_op
= O_constant
;
8140 if (! target_big_endian
)
8141 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8143 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8146 && ((temp
[0] == 0 && temp
[1] == 0)
8147 || (temp
[2] == 0 && temp
[3] == 0))
8148 && ((temp
[4] == 0 && temp
[5] == 0)
8149 || (temp
[6] == 0 && temp
[7] == 0)))
8151 /* The value is simple enough to load with a
8152 couple of instructions. In mips1 mode, set
8153 imm_expr to the high order 32 bits and
8154 offset_expr to the low order 32 bits.
8155 Otherwise, set imm_expr to the entire 64 bit
8157 if (mips_opts
.isa
< 3)
8159 imm_expr
.X_op
= O_constant
;
8160 offset_expr
.X_op
= O_constant
;
8161 if (! target_big_endian
)
8163 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8164 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8168 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8169 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8171 if (offset_expr
.X_add_number
== 0)
8172 offset_expr
.X_op
= O_absent
;
8174 else if (sizeof (imm_expr
.X_add_number
) > 4)
8176 imm_expr
.X_op
= O_constant
;
8177 if (! target_big_endian
)
8178 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8180 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8184 imm_expr
.X_op
= O_big
;
8185 imm_expr
.X_add_number
= 4;
8186 if (! target_big_endian
)
8188 generic_bignum
[0] = bfd_getl16 (temp
);
8189 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8190 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8191 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8195 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8196 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8197 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8198 generic_bignum
[3] = bfd_getb16 (temp
);
8204 const char *newname
;
8207 /* Switch to the right section. */
8209 subseg
= now_subseg
;
8212 default: /* unused default case avoids warnings. */
8214 newname
= RDATA_SECTION_NAME
;
8215 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8219 newname
= RDATA_SECTION_NAME
;
8222 assert (!USE_GLOBAL_POINTER_OPT
8223 || g_switch_value
>= 4);
8227 new_seg
= subseg_new (newname
, (subsegT
) 0);
8228 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8229 bfd_set_section_flags (stdoutput
, new_seg
,
8234 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8235 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8236 && strcmp (TARGET_OS
, "elf") != 0)
8237 record_alignment (new_seg
, 4);
8239 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8241 as_bad (_("Can't use floating point insn in this section"));
8243 /* Set the argument to the current address in the
8245 offset_expr
.X_op
= O_symbol
;
8246 offset_expr
.X_add_symbol
=
8247 symbol_new ("L0\001", now_seg
,
8248 (valueT
) frag_now_fix (), frag_now
);
8249 offset_expr
.X_add_number
= 0;
8251 /* Put the floating point number into the section. */
8252 p
= frag_more ((int) length
);
8253 memcpy (p
, temp
, length
);
8255 /* Switch back to the original section. */
8256 subseg_set (seg
, subseg
);
8261 case 'i': /* 16 bit unsigned immediate */
8262 case 'j': /* 16 bit signed immediate */
8263 imm_reloc
= BFD_RELOC_LO16
;
8264 c
= my_getSmallExpression (&imm_expr
, s
);
8269 if (imm_expr
.X_op
== O_constant
)
8270 imm_expr
.X_add_number
=
8271 (imm_expr
.X_add_number
>> 16) & 0xffff;
8274 imm_reloc
= BFD_RELOC_HI16_S
;
8275 imm_unmatched_hi
= true;
8278 imm_reloc
= BFD_RELOC_HI16
;
8280 else if (imm_expr
.X_op
== O_constant
)
8281 imm_expr
.X_add_number
&= 0xffff;
8285 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8286 || ((imm_expr
.X_add_number
< 0
8287 || imm_expr
.X_add_number
>= 0x10000)
8288 && imm_expr
.X_op
== O_constant
))
8290 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8291 !strcmp (insn
->name
, insn
[1].name
))
8293 if (imm_expr
.X_op
!= O_constant
8294 && imm_expr
.X_op
!= O_big
)
8295 insn_error
= _("absolute expression required");
8297 as_bad (_("16 bit expression not in range 0..65535"));
8305 /* The upper bound should be 0x8000, but
8306 unfortunately the MIPS assembler accepts numbers
8307 from 0x8000 to 0xffff and sign extends them, and
8308 we want to be compatible. We only permit this
8309 extended range for an instruction which does not
8310 provide any further alternates, since those
8311 alternates may handle other cases. People should
8312 use the numbers they mean, rather than relying on
8313 a mysterious sign extension. */
8314 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8315 strcmp (insn
->name
, insn
[1].name
) == 0);
8320 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8321 || ((imm_expr
.X_add_number
< -0x8000
8322 || imm_expr
.X_add_number
>= max
)
8323 && imm_expr
.X_op
== O_constant
)
8325 && imm_expr
.X_add_number
< 0
8326 && mips_opts
.isa
>= 3
8327 && imm_expr
.X_unsigned
8328 && sizeof (imm_expr
.X_add_number
) <= 4))
8332 if (imm_expr
.X_op
!= O_constant
8333 && imm_expr
.X_op
!= O_big
)
8334 insn_error
= _("absolute expression required");
8336 as_bad (_("16 bit expression not in range -32768..32767"));
8342 case 'o': /* 16 bit offset */
8343 c
= my_getSmallExpression (&offset_expr
, s
);
8345 /* If this value won't fit into a 16 bit offset, then go
8346 find a macro that will generate the 32 bit offset
8347 code pattern. As a special hack, we accept the
8348 difference of two local symbols as a constant. This
8349 is required to suppose embedded PIC switches, which
8350 use an instruction which looks like
8351 lw $4,$L12-$LS12($4)
8352 The problem with handling this in a more general
8353 fashion is that the macro function doesn't expect to
8354 see anything which can be handled in a single
8355 constant instruction. */
8357 && (offset_expr
.X_op
!= O_constant
8358 || offset_expr
.X_add_number
>= 0x8000
8359 || offset_expr
.X_add_number
< -0x8000)
8360 && (mips_pic
!= EMBEDDED_PIC
8361 || offset_expr
.X_op
!= O_subtract
8362 || now_seg
!= text_section
8363 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8367 offset_reloc
= BFD_RELOC_LO16
;
8368 if (c
== 'h' || c
== 'H')
8370 assert (offset_expr
.X_op
== O_constant
);
8371 offset_expr
.X_add_number
=
8372 (offset_expr
.X_add_number
>> 16) & 0xffff;
8377 case 'p': /* pc relative offset */
8378 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8379 my_getExpression (&offset_expr
, s
);
8383 case 'u': /* upper 16 bits */
8384 c
= my_getSmallExpression (&imm_expr
, s
);
8385 imm_reloc
= BFD_RELOC_LO16
;
8390 if (imm_expr
.X_op
== O_constant
)
8391 imm_expr
.X_add_number
=
8392 (imm_expr
.X_add_number
>> 16) & 0xffff;
8395 imm_reloc
= BFD_RELOC_HI16_S
;
8396 imm_unmatched_hi
= true;
8399 imm_reloc
= BFD_RELOC_HI16
;
8401 else if (imm_expr
.X_op
== O_constant
)
8402 imm_expr
.X_add_number
&= 0xffff;
8404 if (imm_expr
.X_op
== O_constant
8405 && (imm_expr
.X_add_number
< 0
8406 || imm_expr
.X_add_number
>= 0x10000))
8407 as_bad (_("lui expression not in range 0..65535"));
8411 case 'a': /* 26 bit address */
8412 my_getExpression (&offset_expr
, s
);
8414 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8417 case 'N': /* 3 bit branch condition code */
8418 case 'M': /* 3 bit compare condition code */
8419 if (strncmp (s
, "$fcc", 4) != 0)
8429 while (isdigit (*s
));
8431 as_bad (_("invalid condition code register $fcc%d"), regno
);
8433 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8435 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8438 /* start-sanitize-cygnus */
8439 case 'e': /* must be at least one digit */
8440 my_getExpression (&imm_expr
, s
);
8441 check_absolute_expr (ip
, &imm_expr
);
8442 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8444 as_bad (_("bad byte vector index (%ld)"),
8445 (long) imm_expr
.X_add_number
);
8446 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8448 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8449 imm_expr
.X_op
= O_absent
;
8454 my_getExpression (&imm_expr
, s
);
8455 check_absolute_expr (ip
, &imm_expr
);
8456 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8458 as_bad (_("bad byte vector index (%ld)"),
8459 (long) imm_expr
.X_add_number
);
8460 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8462 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8463 imm_expr
.X_op
= O_absent
;
8467 /* end-sanitize-cygnus */
8469 as_bad (_("bad char = '%c'\n"), *args
);
8474 /* Args don't match. */
8475 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8476 !strcmp (insn
->name
, insn
[1].name
))
8482 insn_error
= _("illegal operands");
8487 /* This routine assembles an instruction into its binary format when
8488 assembling for the mips16. As a side effect, it sets one of the
8489 global variables imm_reloc or offset_reloc to the type of
8490 relocation to do if one of the operands is an address expression.
8491 It also sets mips16_small and mips16_ext if the user explicitly
8492 requested a small or extended instruction. */
8497 struct mips_cl_insn
*ip
;
8501 struct mips_opcode
*insn
;
8504 unsigned int lastregno
= 0;
8509 mips16_small
= false;
8512 for (s
= str
; islower (*s
); ++s
)
8524 if (s
[1] == 't' && s
[2] == ' ')
8527 mips16_small
= true;
8531 else if (s
[1] == 'e' && s
[2] == ' ')
8540 insn_error
= _("unknown opcode");
8544 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8545 mips16_small
= true;
8547 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8549 insn_error
= _("unrecognized opcode");
8556 assert (strcmp (insn
->name
, str
) == 0);
8559 ip
->insn_opcode
= insn
->match
;
8560 ip
->use_extend
= false;
8561 imm_expr
.X_op
= O_absent
;
8562 imm_reloc
= BFD_RELOC_UNUSED
;
8563 offset_expr
.X_op
= O_absent
;
8564 offset_reloc
= BFD_RELOC_UNUSED
;
8565 for (args
= insn
->args
; 1; ++args
)
8572 /* In this switch statement we call break if we did not find
8573 a match, continue if we did find a match, or return if we
8582 /* Stuff the immediate value in now, if we can. */
8583 if (imm_expr
.X_op
== O_constant
8584 && imm_reloc
> BFD_RELOC_UNUSED
8585 && insn
->pinfo
!= INSN_MACRO
)
8587 mips16_immed ((char *) NULL
, 0,
8588 imm_reloc
- BFD_RELOC_UNUSED
,
8589 imm_expr
.X_add_number
, true, mips16_small
,
8590 mips16_ext
, &ip
->insn_opcode
,
8591 &ip
->use_extend
, &ip
->extend
);
8592 imm_expr
.X_op
= O_absent
;
8593 imm_reloc
= BFD_RELOC_UNUSED
;
8607 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8610 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8626 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8628 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8655 while (isdigit (*s
));
8658 as_bad (_("invalid register number (%d)"), regno
);
8664 if (s
[1] == 'f' && s
[2] == 'p')
8669 else if (s
[1] == 's' && s
[2] == 'p')
8674 else if (s
[1] == 'g' && s
[2] == 'p')
8679 else if (s
[1] == 'a' && s
[2] == 't')
8684 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8689 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8702 if (c
== 'v' || c
== 'w')
8704 regno
= mips16_to_32_reg_map
[lastregno
];
8718 regno
= mips32_to_16_reg_map
[regno
];
8723 regno
= ILLEGAL_REG
;
8728 regno
= ILLEGAL_REG
;
8733 regno
= ILLEGAL_REG
;
8738 if (regno
== AT
&& ! mips_opts
.noat
)
8739 as_warn (_("used $at without \".set noat\""));
8746 if (regno
== ILLEGAL_REG
)
8753 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8757 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8760 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8763 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8769 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8772 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8773 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8783 if (strncmp (s
, "$pc", 3) == 0)
8807 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8809 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8810 and generate the appropriate reloc. If the text
8811 inside %gprel is not a symbol name with an
8812 optional offset, then we generate a normal reloc
8813 and will probably fail later. */
8814 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8815 if (imm_expr
.X_op
== O_symbol
)
8818 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8820 ip
->use_extend
= true;
8827 /* Just pick up a normal expression. */
8828 my_getExpression (&imm_expr
, s
);
8831 if (imm_expr
.X_op
== O_register
)
8833 /* What we thought was an expression turned out to
8836 if (s
[0] == '(' && args
[1] == '(')
8838 /* It looks like the expression was omitted
8839 before a register indirection, which means
8840 that the expression is implicitly zero. We
8841 still set up imm_expr, so that we handle
8842 explicit extensions correctly. */
8843 imm_expr
.X_op
= O_constant
;
8844 imm_expr
.X_add_number
= 0;
8845 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8852 /* We need to relax this instruction. */
8853 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8862 /* We use offset_reloc rather than imm_reloc for the PC
8863 relative operands. This lets macros with both
8864 immediate and address operands work correctly. */
8865 my_getExpression (&offset_expr
, s
);
8867 if (offset_expr
.X_op
== O_register
)
8870 /* We need to relax this instruction. */
8871 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8875 case '6': /* break code */
8876 my_getExpression (&imm_expr
, s
);
8877 check_absolute_expr (ip
, &imm_expr
);
8878 if ((unsigned long) imm_expr
.X_add_number
> 63)
8880 as_warn (_("Invalid value for `%s' (%lu)"),
8882 (unsigned long) imm_expr
.X_add_number
);
8883 imm_expr
.X_add_number
&= 0x3f;
8885 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8886 imm_expr
.X_op
= O_absent
;
8890 case 'a': /* 26 bit address */
8891 my_getExpression (&offset_expr
, s
);
8893 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8894 ip
->insn_opcode
<<= 16;
8897 case 'l': /* register list for entry macro */
8898 case 'L': /* register list for exit macro */
8908 int freg
, reg1
, reg2
;
8910 while (*s
== ' ' || *s
== ',')
8914 as_bad (_("can't parse register list"));
8926 while (isdigit (*s
))
8948 as_bad (_("invalid register list"));
8953 while (isdigit (*s
))
8960 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8965 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8970 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8971 mask
|= (reg2
- 3) << 3;
8972 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8973 mask
|= (reg2
- 15) << 1;
8974 else if (reg1
== 31 && reg2
== 31)
8978 as_bad (_("invalid register list"));
8982 /* The mask is filled in in the opcode table for the
8983 benefit of the disassembler. We remove it before
8984 applying the actual mask. */
8985 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8986 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8990 case 'e': /* extend code */
8991 my_getExpression (&imm_expr
, s
);
8992 check_absolute_expr (ip
, &imm_expr
);
8993 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8995 as_warn (_("Invalid value for `%s' (%lu)"),
8997 (unsigned long) imm_expr
.X_add_number
);
8998 imm_expr
.X_add_number
&= 0x7ff;
9000 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9001 imm_expr
.X_op
= O_absent
;
9011 /* Args don't match. */
9012 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9013 strcmp (insn
->name
, insn
[1].name
) == 0)
9020 insn_error
= _("illegal operands");
9026 /* This structure holds information we know about a mips16 immediate
9029 struct mips16_immed_operand
9031 /* The type code used in the argument string in the opcode table. */
9033 /* The number of bits in the short form of the opcode. */
9035 /* The number of bits in the extended form of the opcode. */
9037 /* The amount by which the short form is shifted when it is used;
9038 for example, the sw instruction has a shift count of 2. */
9040 /* The amount by which the short form is shifted when it is stored
9041 into the instruction code. */
9043 /* Non-zero if the short form is unsigned. */
9045 /* Non-zero if the extended form is unsigned. */
9047 /* Non-zero if the value is PC relative. */
9051 /* The mips16 immediate operand types. */
9053 static const struct mips16_immed_operand mips16_immed_operands
[] =
9055 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9056 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9057 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9058 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9059 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9060 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9061 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9062 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9063 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9064 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9065 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9066 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9067 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9068 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9069 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9070 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9071 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9072 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9073 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9074 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9075 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9078 #define MIPS16_NUM_IMMED \
9079 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9081 /* Handle a mips16 instruction with an immediate value. This or's the
9082 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9083 whether an extended value is needed; if one is needed, it sets
9084 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9085 If SMALL is true, an unextended opcode was explicitly requested.
9086 If EXT is true, an extended opcode was explicitly requested. If
9087 WARN is true, warn if EXT does not match reality. */
9090 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9099 unsigned long *insn
;
9100 boolean
*use_extend
;
9101 unsigned short *extend
;
9103 register const struct mips16_immed_operand
*op
;
9104 int mintiny
, maxtiny
;
9107 op
= mips16_immed_operands
;
9108 while (op
->type
!= type
)
9111 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9116 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9119 maxtiny
= 1 << op
->nbits
;
9124 maxtiny
= (1 << op
->nbits
) - 1;
9129 mintiny
= - (1 << (op
->nbits
- 1));
9130 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9133 /* Branch offsets have an implicit 0 in the lowest bit. */
9134 if (type
== 'p' || type
== 'q')
9137 if ((val
& ((1 << op
->shift
) - 1)) != 0
9138 || val
< (mintiny
<< op
->shift
)
9139 || val
> (maxtiny
<< op
->shift
))
9144 if (warn
&& ext
&& ! needext
)
9145 as_warn_where (file
, line
, _("extended operand requested but not required"));
9146 if (small
&& needext
)
9147 as_bad_where (file
, line
, _("invalid unextended operand value"));
9149 if (small
|| (! ext
&& ! needext
))
9153 *use_extend
= false;
9154 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9155 insnval
<<= op
->op_shift
;
9160 long minext
, maxext
;
9166 maxext
= (1 << op
->extbits
) - 1;
9170 minext
= - (1 << (op
->extbits
- 1));
9171 maxext
= (1 << (op
->extbits
- 1)) - 1;
9173 if (val
< minext
|| val
> maxext
)
9174 as_bad_where (file
, line
,
9175 _("operand value out of range for instruction"));
9178 if (op
->extbits
== 16)
9180 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9183 else if (op
->extbits
== 15)
9185 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9190 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9194 *extend
= (unsigned short) extval
;
9203 my_getSmallExpression (ep
, str
)
9214 ((str
[1] == 'h' && str
[2] == 'i')
9215 || (str
[1] == 'H' && str
[2] == 'I')
9216 || (str
[1] == 'l' && str
[2] == 'o'))
9228 * A small expression may be followed by a base register.
9229 * Scan to the end of this operand, and then back over a possible
9230 * base register. Then scan the small expression up to that
9231 * point. (Based on code in sparc.c...)
9233 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
9235 if (sp
- 4 >= str
&& sp
[-1] == RP
)
9237 if (isdigit (sp
[-2]))
9239 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
9241 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
9247 else if (sp
- 5 >= str
9250 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
9251 || (sp
[-3] == 's' && sp
[-2] == 'p')
9252 || (sp
[-3] == 'g' && sp
[-2] == 'p')
9253 || (sp
[-3] == 'a' && sp
[-2] == 't')))
9259 /* no expression means zero offset */
9262 /* %xx(reg) is an error */
9263 ep
->X_op
= O_absent
;
9268 ep
->X_op
= O_constant
;
9271 ep
->X_add_symbol
= NULL
;
9272 ep
->X_op_symbol
= NULL
;
9273 ep
->X_add_number
= 0;
9278 my_getExpression (ep
, str
);
9285 my_getExpression (ep
, str
);
9286 return c
; /* => %hi or %lo encountered */
9290 my_getExpression (ep
, str
)
9296 save_in
= input_line_pointer
;
9297 input_line_pointer
= str
;
9299 expr_end
= input_line_pointer
;
9300 input_line_pointer
= save_in
;
9302 /* If we are in mips16 mode, and this is an expression based on `.',
9303 then we bump the value of the symbol by 1 since that is how other
9304 text symbols are handled. We don't bother to handle complex
9305 expressions, just `.' plus or minus a constant. */
9306 if (mips_opts
.mips16
9307 && ep
->X_op
== O_symbol
9308 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9309 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9310 && ep
->X_add_symbol
->sy_frag
== frag_now
9311 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
9312 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
9313 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
9316 /* Turn a string in input_line_pointer into a floating point constant
9317 of type type, and store the appropriate bytes in *litP. The number
9318 of LITTLENUMS emitted is stored in *sizeP . An error message is
9319 returned, or NULL on OK. */
9322 md_atof (type
, litP
, sizeP
)
9328 LITTLENUM_TYPE words
[4];
9344 return _("bad call to md_atof");
9347 t
= atof_ieee (input_line_pointer
, type
, words
);
9349 input_line_pointer
= t
;
9353 if (! target_big_endian
)
9355 for (i
= prec
- 1; i
>= 0; i
--)
9357 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9363 for (i
= 0; i
< prec
; i
++)
9365 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9374 md_number_to_chars (buf
, val
, n
)
9379 if (target_big_endian
)
9380 number_to_chars_bigendian (buf
, val
, n
);
9382 number_to_chars_littleendian (buf
, val
, n
);
9385 CONST
char *md_shortopts
= "O::g::G:";
9387 struct option md_longopts
[] = {
9388 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9389 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9390 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9391 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9392 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9393 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9394 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9395 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9396 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9397 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9398 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9399 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9400 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9401 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9402 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9403 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9404 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9405 {"break", no_argument
, NULL
, OPTION_BREAK
},
9406 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9407 #define OPTION_EB (OPTION_MD_BASE + 11)
9408 {"EB", no_argument
, NULL
, OPTION_EB
},
9409 #define OPTION_EL (OPTION_MD_BASE + 12)
9410 {"EL", no_argument
, NULL
, OPTION_EL
},
9411 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9412 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9413 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9414 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9415 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9416 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9417 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9418 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9419 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9420 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9421 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9422 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9423 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9424 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9425 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9426 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9427 /* start-sanitize-r5900 */
9428 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9429 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9430 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9431 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9432 /* end-sanitize-r5900 */
9433 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9434 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9435 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9436 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9438 /* start-sanitize-tx19 */
9439 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9440 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9441 /* end-sanitize-tx19 */
9443 /* start-sanitize-cygnus */
9444 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9445 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9446 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9447 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9449 /* end-sanitize-cygnus */
9450 /* start-sanitize-tx49 */
9451 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9452 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9453 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9454 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9456 /* end-sanitize-tx49 */
9457 /* start-sanitize-vr4320 */
9458 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9459 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9460 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9461 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9463 /* end-sanitize-vr4320 */
9464 /* start-sanitize-branchbug4011 */
9465 #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34)
9466 {"fix-4011-branch-bug", no_argument
, NULL
, OPTION_FIX_4011_BRANCH_BUG
},
9467 #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35)
9468 {"no-fix-4011-branch-bug", no_argument
, NULL
, OPTION_NO_FIX_4011_BRANCH_BUG
},
9470 /* end-sanitize-branchbug4011 */
9471 /* start-sanitize-vr4xxx */
9472 #define OPTION_M4121 (OPTION_MD_BASE + 36)
9473 {"m4121", no_argument
, NULL
, OPTION_M4121
},
9474 #define OPTION_NO_M4121 (OPTION_MD_BASE + 37)
9475 {"no-m4121", no_argument
, NULL
, OPTION_NO_M4121
},
9477 /* end-sanitize-vr4xxx */
9478 #define OPTION_MABI (OPTION_MD_BASE + 38)
9479 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9481 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9482 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9483 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9484 #define OPTION_32 (OPTION_MD_BASE + 20)
9485 #define OPTION_64 (OPTION_MD_BASE + 21)
9487 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9488 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9489 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9490 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9491 {"32", no_argument
, NULL
, OPTION_32
},
9492 {"64", no_argument
, NULL
, OPTION_64
},
9495 {NULL
, no_argument
, NULL
, 0}
9497 size_t md_longopts_size
= sizeof(md_longopts
);
9500 md_parse_option (c
, arg
)
9515 target_big_endian
= 1;
9519 target_big_endian
= 0;
9523 if (arg
&& arg
[1] == '0')
9533 mips_debug
= atoi (arg
);
9534 /* When the MIPS assembler sees -g or -g2, it does not do
9535 optimizations which limit full symbolic debugging. We take
9536 that to be equivalent to -O0. */
9537 if (mips_debug
== 2)
9561 /* Identify the processor type */
9563 if (strcmp (p
, "default") == 0
9564 || strcmp (p
, "DEFAULT") == 0)
9570 /* We need to cope with the various "vr" prefixes for the 4300
9572 if (*p
== 'v' || *p
== 'V')
9578 if (*p
== 'r' || *p
== 'R')
9585 if (strcmp (p
, "10000") == 0
9586 || strcmp (p
, "10k") == 0
9587 || strcmp (p
, "10K") == 0)
9589 /* start-sanitize-tx19 */
9590 else if (strcmp (p
, "1900") == 0)
9592 /* end-sanitize-tx19 */
9596 if (strcmp (p
, "2000") == 0
9597 || strcmp (p
, "2k") == 0
9598 || strcmp (p
, "2K") == 0)
9603 if (strcmp (p
, "3000") == 0
9604 || strcmp (p
, "3k") == 0
9605 || strcmp (p
, "3K") == 0)
9607 else if (strcmp (p
, "3900") == 0)
9612 if (strcmp (p
, "4000") == 0
9613 || strcmp (p
, "4k") == 0
9614 || strcmp (p
, "4K") == 0)
9616 else if (strcmp (p
, "4100") == 0)
9618 /* start-sanitize-vr4xxx */
9619 else if (strcmp (p
, "4111") == 0)
9621 else if (strcmp (p
, "4121") == 0)
9623 /* end-sanitize-vr4xxx */
9624 else if (strcmp (p
, "4300") == 0)
9626 /* start-sanitize-vr4320 */
9627 else if (strcmp (p
, "4320") == 0)
9629 /* end-sanitize-vr4320 */
9630 else if (strcmp (p
, "4400") == 0)
9632 else if (strcmp (p
, "4600") == 0)
9634 else if (strcmp (p
, "4650") == 0)
9636 /* start-sanitize-tx49 */
9637 else if (strcmp (p
, "4900") == 0)
9639 /* end-sanitize-tx49 */
9640 else if (strcmp (p
, "4010") == 0)
9645 if (strcmp (p
, "5000") == 0
9646 || strcmp (p
, "5k") == 0
9647 || strcmp (p
, "5K") == 0)
9649 /* start-sanitize-cygnus */
9650 else if (strcmp (p
, "5400") == 0)
9652 /* end-sanitize-cygnus */
9653 /* start-sanitize-r5900 */
9654 else if (strcmp (p
, "5900") == 0)
9656 /* end-sanitize-r5900 */
9660 if (strcmp (p
, "6000") == 0
9661 || strcmp (p
, "6k") == 0
9662 || strcmp (p
, "6K") == 0)
9667 if (strcmp (p
, "8000") == 0
9668 || strcmp (p
, "8k") == 0
9669 || strcmp (p
, "8K") == 0)
9674 if (strcmp (p
, "orion") == 0)
9680 && (mips_cpu
!= 4300
9682 /* start-sanitize-vr4xxx */
9685 /* end-sanitize-vr4xxx */
9686 /* start-sanitize-vr4320 */
9688 /* end-sanitize-vr4320 */
9689 /* start-sanitize-cygnus */
9691 /* end-sanitize-cygnus */
9692 && mips_cpu
!= 5000))
9694 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9700 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9711 case OPTION_NO_M4650
:
9719 case OPTION_NO_M4010
:
9727 case OPTION_NO_M4100
:
9731 /* start-sanitize-vr4xxx */
9736 case OPTION_NO_M4121
:
9740 /* end-sanitize-vr4xxx */
9741 /* start-sanitize-r5900 */
9746 case OPTION_NO_M5900
:
9749 /* end-sanitize-r5900 */
9751 /* start-sanitize-vr4320 */
9756 case OPTION_NO_M4320
:
9760 /* end-sanitize-vr4320 */
9761 /* start-sanitize-cygnus */
9766 case OPTION_NO_M5400
:
9770 /* end-sanitize-cygnus */
9775 case OPTION_NO_M3900
:
9779 /* start-sanitize-tx49 */
9784 case OPTION_NO_M4900
:
9788 /* end-sanitize-tx49 */
9790 mips_opts
.mips16
= 1;
9791 mips_no_prev_insn (false);
9794 case OPTION_NO_MIPS16
:
9795 mips_opts
.mips16
= 0;
9796 mips_no_prev_insn (false);
9799 case OPTION_MEMBEDDED_PIC
:
9800 mips_pic
= EMBEDDED_PIC
;
9801 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9803 as_bad (_("-G may not be used with embedded PIC code"));
9806 g_switch_value
= 0x7fffffff;
9809 /* When generating ELF code, we permit -KPIC and -call_shared to
9810 select SVR4_PIC, and -non_shared to select no PIC. This is
9811 intended to be compatible with Irix 5. */
9812 case OPTION_CALL_SHARED
:
9813 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9815 as_bad (_("-call_shared is supported only for ELF format"));
9818 mips_pic
= SVR4_PIC
;
9819 if (g_switch_seen
&& g_switch_value
!= 0)
9821 as_bad (_("-G may not be used with SVR4 PIC code"));
9827 case OPTION_NON_SHARED
:
9828 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9830 as_bad (_("-non_shared is supported only for ELF format"));
9836 /* The -xgot option tells the assembler to use 32 offsets when
9837 accessing the got in SVR4_PIC mode. It is for Irix
9844 if (! USE_GLOBAL_POINTER_OPT
)
9846 as_bad (_("-G is not supported for this configuration"));
9849 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9851 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9855 g_switch_value
= atoi (arg
);
9859 /* The -32 and -64 options tell the assembler to output the 32
9860 bit or the 64 bit MIPS ELF format. */
9867 const char **list
, **l
;
9869 list
= bfd_target_list ();
9870 for (l
= list
; *l
!= NULL
; l
++)
9871 if (strcmp (*l
, "elf64-bigmips") == 0
9872 || strcmp (*l
, "elf64-littlemips") == 0)
9875 as_fatal (_("No compiled in support for 64 bit object file format"));
9881 /* start-sanitize-branchbug4011 */
9882 case OPTION_FIX_4011_BRANCH_BUG
:
9883 mips_fix_4011_branch_bug
= 1;
9886 case OPTION_NO_FIX_4011_BRANCH_BUG
:
9887 mips_fix_4011_branch_bug
= 0;
9890 /* end-sanitize-branchbug4011 */
9893 if (strcmp (arg
,"32") == 0
9894 || strcmp (arg
,"n32") == 0
9895 || strcmp (arg
,"64") == 0
9896 || strcmp (arg
,"o64") == 0
9897 || strcmp (arg
,"eabi") == 0)
9898 mips_abi_string
= arg
;
9909 md_show_usage (stream
)
9912 fprintf(stream
, _("\
9914 -membedded-pic generate embedded position independent code\n\
9915 -EB generate big endian output\n\
9916 -EL generate little endian output\n\
9917 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9918 -G NUM allow referencing objects up to NUM bytes\n\
9919 implicitly with the gp register [default 8]\n"));
9920 fprintf(stream
, _("\
9921 -mips1 generate MIPS ISA I instructions\n\
9922 -mips2 generate MIPS ISA II instructions\n\
9923 -mips3 generate MIPS ISA III instructions\n\
9924 -mips4 generate MIPS ISA IV instructions\n\
9925 -mcpu=vr4300 generate code for vr4300\n\
9926 -mcpu=vr4100 generate code for vr4100\n\
9927 -m4650 permit R4650 instructions\n\
9928 -no-m4650 do not permit R4650 instructions\n\
9929 -m4010 permit R4010 instructions\n\
9930 -no-m4010 do not permit R4010 instructions\n\
9931 -m4100 permit VR4100 instructions\n\
9932 -no-m4100 do not permit VR4100 instructions\n"));
9933 /* start-sanitize-vr4xxx */
9934 fprintf(stream
, _("\
9935 -mcpu=vr4111 generate code for vr4111\n"));
9936 fprintf(stream
, _("\
9937 -mcpu=vr4121 generate code for vr4121\n\
9938 -m4121 permit VR4121 instructions\n\
9939 -no-m4121 do not permit VR4121 instructions\n"));
9940 /* end-sanitize-vr4xxx */
9941 fprintf(stream
, _("\
9942 -mips16 generate mips16 instructions\n\
9943 -no-mips16 do not generate mips16 instructions\n"));
9944 fprintf(stream
, _("\
9945 -O0 remove unneeded NOPs, do not swap branches\n\
9946 -O remove unneeded NOPs and swap branches\n\
9947 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9948 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9950 fprintf(stream
, _("\
9951 -KPIC, -call_shared generate SVR4 position independent code\n\
9952 -non_shared do not generate position independent code\n\
9953 -xgot assume a 32 bit GOT\n\
9954 -32 create 32 bit object file (default)\n\
9955 -64 create 64 bit object file\n"));
9960 mips_init_after_args ()
9962 /* initialize opcodes */
9963 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9964 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9968 md_pcrel_from (fixP
)
9971 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9972 && fixP
->fx_addsy
!= (symbolS
*) NULL
9973 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9975 /* This makes a branch to an undefined symbol be a branch to the
9976 current location. */
9980 /* return the address of the delay slot */
9981 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9984 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9985 reloc for a cons. We could use the definition there, except that
9986 we want to handle 64 bit relocs specially. */
9989 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9992 unsigned int nbytes
;
9996 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9998 if (nbytes
== 8 && ! mips_64
)
10000 if (target_big_endian
)
10006 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
10007 as_bad (_("Unsupported reloc size %d"), nbytes
);
10009 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
10012 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
10015 /* This is called before the symbol table is processed. In order to
10016 work with gcc when using mips-tfile, we must keep all local labels.
10017 However, in other cases, we want to discard them. If we were
10018 called with -g, but we didn't see any debugging information, it may
10019 mean that gcc is smuggling debugging information through to
10020 mips-tfile, in which case we must generate all local labels. */
10023 mips_frob_file_before_adjust ()
10025 #ifndef NO_ECOFF_DEBUGGING
10026 if (ECOFF_DEBUGGING
10028 && ! ecoff_debugging_seen
)
10029 flag_keep_locals
= 1;
10033 /* Sort any unmatched HI16_S relocs so that they immediately precede
10034 the corresponding LO reloc. This is called before md_apply_fix and
10035 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10036 explicit use of the %hi modifier. */
10041 struct mips_hi_fixup
*l
;
10043 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10045 segment_info_type
*seginfo
;
10048 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10050 /* Check quickly whether the next fixup happens to be a matching
10052 if (l
->fixp
->fx_next
!= NULL
10053 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10054 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10055 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10058 /* Look through the fixups for this segment for a matching %lo.
10059 When we find one, move the %hi just in front of it. We do
10060 this in two passes. In the first pass, we try to find a
10061 unique %lo. In the second pass, we permit multiple %hi
10062 relocs for a single %lo (this is a GNU extension). */
10063 seginfo
= seg_info (l
->seg
);
10064 for (pass
= 0; pass
< 2; pass
++)
10069 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10071 /* Check whether this is a %lo fixup which matches l->fixp. */
10072 if (f
->fx_r_type
== BFD_RELOC_LO16
10073 && f
->fx_addsy
== l
->fixp
->fx_addsy
10074 && f
->fx_offset
== l
->fixp
->fx_offset
10077 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10078 || prev
->fx_addsy
!= f
->fx_addsy
10079 || prev
->fx_offset
!= f
->fx_offset
))
10083 /* Move l->fixp before f. */
10084 for (pf
= &seginfo
->fix_root
;
10086 pf
= &(*pf
)->fx_next
)
10087 assert (*pf
!= NULL
);
10089 *pf
= l
->fixp
->fx_next
;
10091 l
->fixp
->fx_next
= f
;
10093 seginfo
->fix_root
= l
->fixp
;
10095 prev
->fx_next
= l
->fixp
;
10107 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10108 _("Unmatched %%hi reloc"));
10113 /* When generating embedded PIC code we need to use a special
10114 relocation to represent the difference of two symbols in the .text
10115 section (switch tables use a difference of this sort). See
10116 include/coff/mips.h for details. This macro checks whether this
10117 fixup requires the special reloc. */
10118 #define SWITCH_TABLE(fixp) \
10119 ((fixp)->fx_r_type == BFD_RELOC_32 \
10120 && (fixp)->fx_addsy != NULL \
10121 && (fixp)->fx_subsy != NULL \
10122 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10123 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10125 /* When generating embedded PIC code we must keep all PC relative
10126 relocations, in case the linker has to relax a call. We also need
10127 to keep relocations for switch table entries. */
10131 mips_force_relocation (fixp
)
10134 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10135 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10138 return (mips_pic
== EMBEDDED_PIC
10140 || SWITCH_TABLE (fixp
)
10141 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10142 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10145 /* Apply a fixup to the object file. */
10148 md_apply_fix (fixP
, valueP
)
10152 unsigned char *buf
;
10155 assert (fixP
->fx_size
== 4
10156 || fixP
->fx_r_type
== BFD_RELOC_16
10157 || fixP
->fx_r_type
== BFD_RELOC_64
10158 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10159 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10163 /* If we aren't adjusting this fixup to be against the section
10164 symbol, we need to adjust the value. */
10166 if (fixP
->fx_addsy
!= NULL
10167 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
10168 && (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10169 || S_IS_WEAK (fixP
->fx_addsy
)))
10171 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10172 if (value
!= 0 && ! fixP
->fx_pcrel
)
10174 /* In this case, the bfd_install_relocation routine will
10175 incorrectly add the symbol value back in. We just want
10176 the addend to appear in the object file. */
10177 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10182 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10184 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10187 switch (fixP
->fx_r_type
)
10189 case BFD_RELOC_MIPS_JMP
:
10190 case BFD_RELOC_HI16
:
10191 case BFD_RELOC_HI16_S
:
10192 case BFD_RELOC_MIPS_GPREL
:
10193 case BFD_RELOC_MIPS_LITERAL
:
10194 case BFD_RELOC_MIPS_CALL16
:
10195 case BFD_RELOC_MIPS_GOT16
:
10196 case BFD_RELOC_MIPS_GPREL32
:
10197 case BFD_RELOC_MIPS_GOT_HI16
:
10198 case BFD_RELOC_MIPS_GOT_LO16
:
10199 case BFD_RELOC_MIPS_CALL_HI16
:
10200 case BFD_RELOC_MIPS_CALL_LO16
:
10201 case BFD_RELOC_MIPS16_GPREL
:
10202 /* start-sanitize-r5900 */
10203 case BFD_RELOC_MIPS15_S3
:
10204 /* end-sanitize-r5900 */
10205 if (fixP
->fx_pcrel
)
10206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10207 _("Invalid PC relative reloc"));
10208 /* Nothing needed to do. The value comes from the reloc entry */
10211 case BFD_RELOC_MIPS16_JMP
:
10212 /* We currently always generate a reloc against a symbol, which
10213 means that we don't want an addend even if the symbol is
10215 fixP
->fx_addnumber
= 0;
10218 case BFD_RELOC_PCREL_HI16_S
:
10219 /* The addend for this is tricky if it is internal, so we just
10220 do everything here rather than in bfd_install_relocation. */
10221 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10223 /* For an external symbol adjust by the address to make it
10224 pcrel_offset. We use the address of the RELLO reloc
10225 which follows this one. */
10226 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10227 + fixP
->fx_next
->fx_where
);
10229 if (value
& 0x8000)
10232 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10233 if (target_big_endian
)
10235 md_number_to_chars (buf
, value
, 2);
10238 case BFD_RELOC_PCREL_LO16
:
10239 /* The addend for this is tricky if it is internal, so we just
10240 do everything here rather than in bfd_install_relocation. */
10241 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10242 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10243 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10244 if (target_big_endian
)
10246 md_number_to_chars (buf
, value
, 2);
10250 /* This is handled like BFD_RELOC_32, but we output a sign
10251 extended value if we are only 32 bits. */
10253 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10255 if (8 <= sizeof (valueT
))
10256 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10263 w1
= w2
= fixP
->fx_where
;
10264 if (target_big_endian
)
10268 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10269 if ((value
& 0x80000000) != 0)
10273 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10279 /* If we are deleting this reloc entry, we must fill in the
10280 value now. This can happen if we have a .word which is not
10281 resolved when it appears but is later defined. We also need
10282 to fill in the value if this is an embedded PIC switch table
10285 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10286 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10291 /* If we are deleting this reloc entry, we must fill in the
10293 assert (fixP
->fx_size
== 2);
10295 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10299 case BFD_RELOC_LO16
:
10300 /* When handling an embedded PIC switch statement, we can wind
10301 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10304 if (value
< -0x8000 || value
> 0x7fff)
10305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10306 _("relocation overflow"));
10307 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10308 if (target_big_endian
)
10310 md_number_to_chars (buf
, value
, 2);
10314 case BFD_RELOC_16_PCREL_S2
:
10316 * We need to save the bits in the instruction since fixup_segment()
10317 * might be deleting the relocation entry (i.e., a branch within
10318 * the current segment).
10320 if ((value
& 0x3) != 0)
10321 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10322 _("Branch to odd address (%lx)"), value
);
10325 /* update old instruction data */
10326 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10327 if (target_big_endian
)
10328 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10330 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10332 if (value
>= -0x8000 && value
< 0x8000)
10333 insn
|= value
& 0xffff;
10336 /* The branch offset is too large. If this is an
10337 unconditional branch, and we are not generating PIC code,
10338 we can convert it to an absolute jump instruction. */
10339 if (mips_pic
== NO_PIC
10341 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10342 && (fixP
->fx_frag
->fr_address
10343 < text_section
->vma
+ text_section
->_raw_size
)
10344 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10345 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10346 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10348 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10349 insn
= 0x0c000000; /* jal */
10351 insn
= 0x08000000; /* j */
10352 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10354 fixP
->fx_addsy
= section_symbol (text_section
);
10355 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10359 /* FIXME. It would be possible in principle to handle
10360 conditional branches which overflow. They could be
10361 transformed into a branch around a jump. This would
10362 require setting up variant frags for each different
10363 branch type. The native MIPS assembler attempts to
10364 handle these cases, but it appears to do it
10366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10367 _("Branch out of range"));
10371 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10374 case BFD_RELOC_VTABLE_INHERIT
:
10377 && !S_IS_DEFINED (fixP
->fx_addsy
)
10378 && !S_IS_WEAK (fixP
->fx_addsy
))
10379 S_SET_WEAK (fixP
->fx_addsy
);
10382 case BFD_RELOC_VTABLE_ENTRY
:
10398 const struct mips_opcode
*p
;
10399 int treg
, sreg
, dreg
, shamt
;
10404 for (i
= 0; i
< NUMOPCODES
; ++i
)
10406 p
= &mips_opcodes
[i
];
10407 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10409 printf ("%08lx %s\t", oc
, p
->name
);
10410 treg
= (oc
>> 16) & 0x1f;
10411 sreg
= (oc
>> 21) & 0x1f;
10412 dreg
= (oc
>> 11) & 0x1f;
10413 shamt
= (oc
>> 6) & 0x1f;
10415 for (args
= p
->args
;; ++args
)
10426 printf ("%c", *args
);
10430 assert (treg
== sreg
);
10431 printf ("$%d,$%d", treg
, sreg
);
10436 printf ("$%d", dreg
);
10441 printf ("$%d", treg
);
10445 printf ("0x%x", treg
);
10450 printf ("$%d", sreg
);
10454 printf ("0x%08lx", oc
& 0x1ffffff);
10461 printf ("%d", imm
);
10466 printf ("$%d", shamt
);
10477 printf (_("%08lx UNDEFINED\n"), oc
);
10488 name
= input_line_pointer
;
10489 c
= get_symbol_end ();
10490 p
= (symbolS
*) symbol_find_or_make (name
);
10491 *input_line_pointer
= c
;
10495 /* Align the current frag to a given power of two. The MIPS assembler
10496 also automatically adjusts any preceding label. */
10499 mips_align (to
, fill
, label
)
10504 mips_emit_delays (false);
10505 frag_align (to
, fill
, 0);
10506 record_alignment (now_seg
, to
);
10509 assert (S_GET_SEGMENT (label
) == now_seg
);
10510 label
->sy_frag
= frag_now
;
10511 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10515 /* Align to a given power of two. .align 0 turns off the automatic
10516 alignment used by the data creating pseudo-ops. */
10523 register long temp_fill
;
10524 long max_alignment
= 15;
10528 o Note that the assembler pulls down any immediately preceeding label
10529 to the aligned address.
10530 o It's not documented but auto alignment is reinstated by
10531 a .align pseudo instruction.
10532 o Note also that after auto alignment is turned off the mips assembler
10533 issues an error on attempt to assemble an improperly aligned data item.
10538 temp
= get_absolute_expression ();
10539 if (temp
> max_alignment
)
10540 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10543 as_warn (_("Alignment negative: 0 assumed."));
10546 if (*input_line_pointer
== ',')
10548 input_line_pointer
++;
10549 temp_fill
= get_absolute_expression ();
10556 mips_align (temp
, (int) temp_fill
,
10557 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10564 demand_empty_rest_of_line ();
10568 mips_flush_pending_output ()
10570 mips_emit_delays (false);
10571 mips_clear_insn_labels ();
10580 /* When generating embedded PIC code, we only use the .text, .lit8,
10581 .sdata and .sbss sections. We change the .data and .rdata
10582 pseudo-ops to use .sdata. */
10583 if (mips_pic
== EMBEDDED_PIC
10584 && (sec
== 'd' || sec
== 'r'))
10588 /* The ELF backend needs to know that we are changing sections, so
10589 that .previous works correctly. We could do something like check
10590 for a obj_section_change_hook macro, but that might be confusing
10591 as it would not be appropriate to use it in the section changing
10592 functions in read.c, since obj-elf.c intercepts those. FIXME:
10593 This should be cleaner, somehow. */
10594 obj_elf_section_change_hook ();
10597 mips_emit_delays (false);
10607 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10608 demand_empty_rest_of_line ();
10612 if (USE_GLOBAL_POINTER_OPT
)
10614 seg
= subseg_new (RDATA_SECTION_NAME
,
10615 (subsegT
) get_absolute_expression ());
10616 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10618 bfd_set_section_flags (stdoutput
, seg
,
10624 if (strcmp (TARGET_OS
, "elf") != 0)
10625 bfd_set_section_alignment (stdoutput
, seg
, 4);
10627 demand_empty_rest_of_line ();
10631 as_bad (_("No read only data section in this object file format"));
10632 demand_empty_rest_of_line ();
10638 if (USE_GLOBAL_POINTER_OPT
)
10640 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10641 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10643 bfd_set_section_flags (stdoutput
, seg
,
10644 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10646 if (strcmp (TARGET_OS
, "elf") != 0)
10647 bfd_set_section_alignment (stdoutput
, seg
, 4);
10649 demand_empty_rest_of_line ();
10654 as_bad (_("Global pointers not supported; recompile -G 0"));
10655 demand_empty_rest_of_line ();
10664 mips_enable_auto_align ()
10675 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10676 mips_emit_delays (false);
10677 if (log_size
> 0 && auto_align
)
10678 mips_align (log_size
, 0, label
);
10679 mips_clear_insn_labels ();
10680 cons (1 << log_size
);
10684 s_float_cons (type
)
10689 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10691 mips_emit_delays (false);
10695 mips_align (3, 0, label
);
10697 mips_align (2, 0, label
);
10699 mips_clear_insn_labels ();
10704 /* Handle .globl. We need to override it because on Irix 5 you are
10707 where foo is an undefined symbol, to mean that foo should be
10708 considered to be the address of a function. */
10719 name
= input_line_pointer
;
10720 c
= get_symbol_end ();
10721 symbolP
= symbol_find_or_make (name
);
10722 *input_line_pointer
= c
;
10723 SKIP_WHITESPACE ();
10725 /* On Irix 5, every global symbol that is not explicitly labelled as
10726 being a function is apparently labelled as being an object. */
10729 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10734 secname
= input_line_pointer
;
10735 c
= get_symbol_end ();
10736 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10738 as_bad (_("%s: no such section"), secname
);
10739 *input_line_pointer
= c
;
10741 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10742 flag
= BSF_FUNCTION
;
10745 symbolP
->bsym
->flags
|= flag
;
10747 S_SET_EXTERNAL (symbolP
);
10748 demand_empty_rest_of_line ();
10758 opt
= input_line_pointer
;
10759 c
= get_symbol_end ();
10763 /* FIXME: What does this mean? */
10765 else if (strncmp (opt
, "pic", 3) == 0)
10769 i
= atoi (opt
+ 3);
10773 mips_pic
= SVR4_PIC
;
10775 as_bad (_(".option pic%d not supported"), i
);
10777 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10779 if (g_switch_seen
&& g_switch_value
!= 0)
10780 as_warn (_("-G may not be used with SVR4 PIC code"));
10781 g_switch_value
= 0;
10782 bfd_set_gp_size (stdoutput
, 0);
10786 as_warn (_("Unrecognized option \"%s\""), opt
);
10788 *input_line_pointer
= c
;
10789 demand_empty_rest_of_line ();
10792 /* This structure is used to hold a stack of .set values. */
10794 struct mips_option_stack
10796 struct mips_option_stack
*next
;
10797 struct mips_set_options options
;
10800 static struct mips_option_stack
*mips_opts_stack
;
10802 /* Handle the .set pseudo-op. */
10808 char *name
= input_line_pointer
, ch
;
10810 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10811 input_line_pointer
++;
10812 ch
= *input_line_pointer
;
10813 *input_line_pointer
= '\0';
10815 if (strcmp (name
, "reorder") == 0)
10817 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10819 /* If we still have pending nops, we can discard them. The
10820 usual nop handling will insert any that are still
10822 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10823 * (mips_opts
.mips16
? 2 : 4));
10824 prev_nop_frag
= NULL
;
10826 mips_opts
.noreorder
= 0;
10828 else if (strcmp (name
, "noreorder") == 0)
10830 mips_emit_delays (true);
10831 mips_opts
.noreorder
= 1;
10832 mips_any_noreorder
= 1;
10834 else if (strcmp (name
, "at") == 0)
10836 mips_opts
.noat
= 0;
10838 else if (strcmp (name
, "noat") == 0)
10840 mips_opts
.noat
= 1;
10842 else if (strcmp (name
, "macro") == 0)
10844 mips_opts
.warn_about_macros
= 0;
10846 else if (strcmp (name
, "nomacro") == 0)
10848 if (mips_opts
.noreorder
== 0)
10849 as_bad (_("`noreorder' must be set before `nomacro'"));
10850 mips_opts
.warn_about_macros
= 1;
10852 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10854 mips_opts
.nomove
= 0;
10856 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10858 mips_opts
.nomove
= 1;
10860 else if (strcmp (name
, "bopt") == 0)
10862 mips_opts
.nobopt
= 0;
10864 else if (strcmp (name
, "nobopt") == 0)
10866 mips_opts
.nobopt
= 1;
10868 else if (strcmp (name
, "mips16") == 0
10869 || strcmp (name
, "MIPS-16") == 0)
10870 mips_opts
.mips16
= 1;
10871 else if (strcmp (name
, "nomips16") == 0
10872 || strcmp (name
, "noMIPS-16") == 0)
10873 mips_opts
.mips16
= 0;
10874 else if (strncmp (name
, "mips", 4) == 0)
10878 /* Permit the user to change the ISA on the fly. Needless to
10879 say, misuse can cause serious problems. */
10880 isa
= atoi (name
+ 4);
10882 mips_opts
.isa
= file_mips_isa
;
10883 else if (isa
< 1 || isa
> 4)
10884 as_bad (_("unknown ISA level"));
10886 mips_opts
.isa
= isa
;
10888 else if (strcmp (name
, "autoextend") == 0)
10889 mips_opts
.noautoextend
= 0;
10890 else if (strcmp (name
, "noautoextend") == 0)
10891 mips_opts
.noautoextend
= 1;
10892 else if (strcmp (name
, "push") == 0)
10894 struct mips_option_stack
*s
;
10896 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10897 s
->next
= mips_opts_stack
;
10898 s
->options
= mips_opts
;
10899 mips_opts_stack
= s
;
10901 else if (strcmp (name
, "pop") == 0)
10903 struct mips_option_stack
*s
;
10905 s
= mips_opts_stack
;
10907 as_bad (_(".set pop with no .set push"));
10910 /* If we're changing the reorder mode we need to handle
10911 delay slots correctly. */
10912 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10913 mips_emit_delays (true);
10914 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10916 if (prev_nop_frag
!= NULL
)
10918 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10919 * (mips_opts
.mips16
? 2 : 4));
10920 prev_nop_frag
= NULL
;
10924 mips_opts
= s
->options
;
10925 mips_opts_stack
= s
->next
;
10931 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10933 *input_line_pointer
= ch
;
10934 demand_empty_rest_of_line ();
10937 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10938 .option pic2. It means to generate SVR4 PIC calls. */
10941 s_abicalls (ignore
)
10944 mips_pic
= SVR4_PIC
;
10945 if (USE_GLOBAL_POINTER_OPT
)
10947 if (g_switch_seen
&& g_switch_value
!= 0)
10948 as_warn (_("-G may not be used with SVR4 PIC code"));
10949 g_switch_value
= 0;
10951 bfd_set_gp_size (stdoutput
, 0);
10952 demand_empty_rest_of_line ();
10955 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10956 PIC code. It sets the $gp register for the function based on the
10957 function address, which is in the register named in the argument.
10958 This uses a relocation against _gp_disp, which is handled specially
10959 by the linker. The result is:
10960 lui $gp,%hi(_gp_disp)
10961 addiu $gp,$gp,%lo(_gp_disp)
10962 addu $gp,$gp,.cpload argument
10963 The .cpload argument is normally $25 == $t9. */
10972 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10973 if (mips_pic
!= SVR4_PIC
)
10979 /* .cpload should be a in .set noreorder section. */
10980 if (mips_opts
.noreorder
== 0)
10981 as_warn (_(".cpload not in noreorder section"));
10983 ex
.X_op
= O_symbol
;
10984 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10985 ex
.X_op_symbol
= NULL
;
10986 ex
.X_add_number
= 0;
10988 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10989 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10991 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10992 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10993 (int) BFD_RELOC_LO16
);
10995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10996 GP
, GP
, tc_get_register (0));
10998 demand_empty_rest_of_line ();
11001 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11002 offset from $sp. The offset is remembered, and after making a PIC
11003 call $gp is restored from that location. */
11006 s_cprestore (ignore
)
11012 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
11013 if (mips_pic
!= SVR4_PIC
)
11019 mips_cprestore_offset
= get_absolute_expression ();
11021 ex
.X_op
= O_constant
;
11022 ex
.X_add_symbol
= NULL
;
11023 ex
.X_op_symbol
= NULL
;
11024 ex
.X_add_number
= mips_cprestore_offset
;
11026 macro_build ((char *) NULL
, &icnt
, &ex
,
11027 ((bfd_arch_bits_per_address (stdoutput
) == 32
11028 || mips_opts
.isa
< 3)
11030 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11032 demand_empty_rest_of_line ();
11035 /* Handle the .gpword pseudo-op. This is used when generating PIC
11036 code. It generates a 32 bit GP relative reloc. */
11046 /* When not generating PIC code, this is treated as .word. */
11047 if (mips_pic
!= SVR4_PIC
)
11053 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11054 mips_emit_delays (true);
11056 mips_align (2, 0, label
);
11057 mips_clear_insn_labels ();
11061 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11063 as_bad (_("Unsupported use of .gpword"));
11064 ignore_rest_of_line ();
11068 md_number_to_chars (p
, (valueT
) 0, 4);
11069 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11070 BFD_RELOC_MIPS_GPREL32
);
11072 demand_empty_rest_of_line ();
11075 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11076 tables in SVR4 PIC code. */
11085 /* This is ignored when not generating SVR4 PIC code. */
11086 if (mips_pic
!= SVR4_PIC
)
11092 /* Add $gp to the register named as an argument. */
11093 reg
= tc_get_register (0);
11094 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11095 ((bfd_arch_bits_per_address (stdoutput
) == 32
11096 || mips_opts
.isa
< 3)
11097 ? "addu" : "daddu"),
11098 "d,v,t", reg
, reg
, GP
);
11100 demand_empty_rest_of_line ();
11103 /* Handle the .insn pseudo-op. This marks instruction labels in
11104 mips16 mode. This permits the linker to handle them specially,
11105 such as generating jalx instructions when needed. We also make
11106 them odd for the duration of the assembly, in order to generate the
11107 right sort of code. We will make them even in the adjust_symtab
11108 routine, while leaving them marked. This is convenient for the
11109 debugger and the disassembler. The linker knows to make them odd
11116 if (mips_opts
.mips16
)
11117 mips16_mark_labels ();
11119 demand_empty_rest_of_line ();
11122 /* Handle a .stabn directive. We need these in order to mark a label
11123 as being a mips16 text label correctly. Sometimes the compiler
11124 will emit a label, followed by a .stabn, and then switch sections.
11125 If the label and .stabn are in mips16 mode, then the label is
11126 really a mips16 text label. */
11132 if (type
== 'n' && mips_opts
.mips16
)
11133 mips16_mark_labels ();
11138 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11142 s_mips_weakext (ignore
)
11150 name
= input_line_pointer
;
11151 c
= get_symbol_end ();
11152 symbolP
= symbol_find_or_make (name
);
11153 S_SET_WEAK (symbolP
);
11154 *input_line_pointer
= c
;
11156 SKIP_WHITESPACE ();
11158 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11160 if (S_IS_DEFINED (symbolP
))
11162 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11163 S_GET_NAME (symbolP
));
11164 ignore_rest_of_line ();
11168 if (*input_line_pointer
== ',')
11170 ++input_line_pointer
;
11171 SKIP_WHITESPACE ();
11175 if (exp
.X_op
!= O_symbol
)
11177 as_bad ("bad .weakext directive");
11178 ignore_rest_of_line();
11181 symbolP
->sy_value
= exp
;
11184 demand_empty_rest_of_line ();
11187 /* Parse a register string into a number. Called from the ECOFF code
11188 to parse .frame. The argument is non-zero if this is the frame
11189 register, so that we can record it in mips_frame_reg. */
11192 tc_get_register (frame
)
11197 SKIP_WHITESPACE ();
11198 if (*input_line_pointer
++ != '$')
11200 as_warn (_("expected `$'"));
11203 else if (isdigit ((unsigned char) *input_line_pointer
))
11205 reg
= get_absolute_expression ();
11206 if (reg
< 0 || reg
>= 32)
11208 as_warn (_("Bad register number"));
11214 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11216 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11218 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11220 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11224 as_warn (_("Unrecognized register name"));
11227 input_line_pointer
+= 2;
11230 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11235 md_section_align (seg
, addr
)
11239 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11242 /* We don't need to align ELF sections to the full alignment.
11243 However, Irix 5 may prefer that we align them at least to a 16
11244 byte boundary. We don't bother to align the sections if we are
11245 targeted for an embedded system. */
11246 if (strcmp (TARGET_OS
, "elf") == 0)
11252 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11255 /* Utility routine, called from above as well. If called while the
11256 input file is still being read, it's only an approximation. (For
11257 example, a symbol may later become defined which appeared to be
11258 undefined earlier.) */
11261 nopic_need_relax (sym
, before_relaxing
)
11263 int before_relaxing
;
11268 if (USE_GLOBAL_POINTER_OPT
)
11270 const char *symname
;
11273 /* Find out whether this symbol can be referenced off the GP
11274 register. It can be if it is smaller than the -G size or if
11275 it is in the .sdata or .sbss section. Certain symbols can
11276 not be referenced off the GP, although it appears as though
11278 symname
= S_GET_NAME (sym
);
11279 if (symname
!= (const char *) NULL
11280 && (strcmp (symname
, "eprol") == 0
11281 || strcmp (symname
, "etext") == 0
11282 || strcmp (symname
, "_gp") == 0
11283 || strcmp (symname
, "edata") == 0
11284 || strcmp (symname
, "_fbss") == 0
11285 || strcmp (symname
, "_fdata") == 0
11286 || strcmp (symname
, "_ftext") == 0
11287 || strcmp (symname
, "end") == 0
11288 || strcmp (symname
, "_gp_disp") == 0))
11290 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11292 #ifndef NO_ECOFF_DEBUGGING
11293 || (sym
->ecoff_extern_size
!= 0
11294 && sym
->ecoff_extern_size
<= g_switch_value
)
11296 /* We must defer this decision until after the whole
11297 file has been read, since there might be a .extern
11298 after the first use of this symbol. */
11299 || (before_relaxing
11300 #ifndef NO_ECOFF_DEBUGGING
11301 && sym
->ecoff_extern_size
== 0
11303 && S_GET_VALUE (sym
) == 0)
11304 || (S_GET_VALUE (sym
) != 0
11305 && S_GET_VALUE (sym
) <= g_switch_value
)))
11309 const char *segname
;
11311 segname
= segment_name (S_GET_SEGMENT (sym
));
11312 assert (strcmp (segname
, ".lit8") != 0
11313 && strcmp (segname
, ".lit4") != 0);
11314 change
= (strcmp (segname
, ".sdata") != 0
11315 && strcmp (segname
, ".sbss") != 0);
11320 /* We are not optimizing for the GP register. */
11324 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11325 extended opcode. SEC is the section the frag is in. */
11328 mips16_extended_frag (fragp
, sec
, stretch
)
11334 register const struct mips16_immed_operand
*op
;
11336 int mintiny
, maxtiny
;
11339 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11341 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11344 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11345 op
= mips16_immed_operands
;
11346 while (op
->type
!= type
)
11349 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11354 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11357 maxtiny
= 1 << op
->nbits
;
11362 maxtiny
= (1 << op
->nbits
) - 1;
11367 mintiny
= - (1 << (op
->nbits
- 1));
11368 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11371 /* We can't call S_GET_VALUE here, because we don't want to lock in
11372 a particular frag address. */
11373 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
11375 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
11376 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11377 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11379 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
11380 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
11383 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
11384 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
11385 + fragp
->fr_symbol
->sy_value
.X_add_number
11386 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11387 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
11396 /* We won't have the section when we are called from
11397 mips_relax_frag. However, we will always have been called
11398 from md_estimate_size_before_relax first. If this is a
11399 branch to a different section, we mark it as such. If SEC is
11400 NULL, and the frag is not marked, then it must be a branch to
11401 the same section. */
11404 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11411 fragp
->fr_subtype
=
11412 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11414 /* FIXME: We should support this, and let the linker
11415 catch branches and loads that are out of range. */
11416 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11417 _("unsupported PC relative reference to different section"));
11423 /* In this case, we know for sure that the symbol fragment is in
11424 the same section. If the fr_address of the symbol fragment
11425 is greater then the address of this fragment we want to add
11426 in STRETCH in order to get a better estimate of the address.
11427 This particularly matters because of the shift bits. */
11429 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
11433 /* Adjust stretch for any alignment frag. Note that if have
11434 been expanding the earlier code, the symbol may be
11435 defined in what appears to be an earlier frag. FIXME:
11436 This doesn't handle the fr_subtype field, which specifies
11437 a maximum number of bytes to skip when doing an
11440 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
11443 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11446 stretch
= - ((- stretch
)
11447 & ~ ((1 << (int) f
->fr_offset
) - 1));
11449 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11458 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11460 /* The base address rules are complicated. The base address of
11461 a branch is the following instruction. The base address of a
11462 PC relative load or add is the instruction itself, but if it
11463 is in a delay slot (in which case it can not be extended) use
11464 the address of the instruction whose delay slot it is in. */
11465 if (type
== 'p' || type
== 'q')
11469 /* If we are currently assuming that this frag should be
11470 extended, then, the current address is two bytes
11472 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11475 /* Ignore the low bit in the target, since it will be set
11476 for a text label. */
11477 if ((val
& 1) != 0)
11480 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11482 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11485 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11487 /* Branch offsets have an implicit 0 in the lowest bit. */
11488 if (type
== 'p' || type
== 'q')
11491 /* If any of the shifted bits are set, we must use an extended
11492 opcode. If the address depends on the size of this
11493 instruction, this can lead to a loop, so we arrange to always
11494 use an extended opcode. We only check this when we are in
11495 the main relaxation loop, when SEC is NULL. */
11496 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11498 fragp
->fr_subtype
=
11499 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11503 /* If we are about to mark a frag as extended because the value
11504 is precisely maxtiny + 1, then there is a chance of an
11505 infinite loop as in the following code:
11510 In this case when the la is extended, foo is 0x3fc bytes
11511 away, so the la can be shrunk, but then foo is 0x400 away, so
11512 the la must be extended. To avoid this loop, we mark the
11513 frag as extended if it was small, and is about to become
11514 extended with a value of maxtiny + 1. */
11515 if (val
== ((maxtiny
+ 1) << op
->shift
)
11516 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11519 fragp
->fr_subtype
=
11520 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11524 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11525 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11527 if ((val
& ((1 << op
->shift
) - 1)) != 0
11528 || val
< (mintiny
<< op
->shift
)
11529 || val
> (maxtiny
<< op
->shift
))
11535 /* Estimate the size of a frag before relaxing. Unless this is the
11536 mips16, we are not really relaxing here, and the final size is
11537 encoded in the subtype information. For the mips16, we have to
11538 decide whether we are using an extended opcode or not. */
11542 md_estimate_size_before_relax (fragp
, segtype
)
11548 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11550 if (mips16_extended_frag (fragp
, segtype
, 0))
11552 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11557 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11562 if (mips_pic
== NO_PIC
)
11564 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11566 else if (mips_pic
== SVR4_PIC
)
11571 sym
= fragp
->fr_symbol
;
11573 /* Handle the case of a symbol equated to another symbol. */
11574 while (sym
->sy_value
.X_op
== O_symbol
11575 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11579 /* It's possible to get a loop here in a badly written
11581 n
= sym
->sy_value
.X_add_symbol
;
11587 symsec
= S_GET_SEGMENT (sym
);
11589 /* This must duplicate the test in adjust_reloc_syms. */
11590 change
= (symsec
!= &bfd_und_section
11591 && symsec
!= &bfd_abs_section
11592 && ! bfd_is_com_section (symsec
));
11599 /* Record the offset to the first reloc in the fr_opcode field.
11600 This lets md_convert_frag and tc_gen_reloc know that the code
11601 must be expanded. */
11602 fragp
->fr_opcode
= (fragp
->fr_literal
11604 - RELAX_OLD (fragp
->fr_subtype
)
11605 + RELAX_RELOC1 (fragp
->fr_subtype
));
11606 /* FIXME: This really needs as_warn_where. */
11607 if (RELAX_WARN (fragp
->fr_subtype
))
11608 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11614 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11617 /* This is called to see whether a reloc against a defined symbol
11618 should be converted into a reloc against a section. Don't adjust
11619 MIPS16 jump relocations, so we don't have to worry about the format
11620 of the offset in the .o file. Don't adjust relocations against
11621 mips16 symbols, so that the linker can find them if it needs to set
11625 mips_fix_adjustable (fixp
)
11628 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11630 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11631 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11633 if (fixp
->fx_addsy
== NULL
)
11636 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11637 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11638 && fixp
->fx_subsy
== NULL
)
11644 /* Translate internal representation of relocation info to BFD target
11648 tc_gen_reloc (section
, fixp
)
11652 static arelent
*retval
[4];
11654 bfd_reloc_code_real_type code
;
11656 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11659 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11660 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11662 if (mips_pic
== EMBEDDED_PIC
11663 && SWITCH_TABLE (fixp
))
11665 /* For a switch table entry we use a special reloc. The addend
11666 is actually the difference between the reloc address and the
11668 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11669 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11670 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11671 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11673 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11675 /* We use a special addend for an internal RELLO reloc. */
11676 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11677 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11679 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11681 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11683 assert (fixp
->fx_next
!= NULL
11684 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11685 /* We use a special addend for an internal RELHI reloc. The
11686 reloc is relative to the RELLO; adjust the addend
11688 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11689 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11690 + fixp
->fx_next
->fx_where
11691 - S_GET_VALUE (fixp
->fx_subsy
));
11693 reloc
->addend
= (fixp
->fx_addnumber
11694 + fixp
->fx_next
->fx_frag
->fr_address
11695 + fixp
->fx_next
->fx_where
);
11697 else if (fixp
->fx_pcrel
== 0)
11698 reloc
->addend
= fixp
->fx_addnumber
;
11701 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11702 /* A gruesome hack which is a result of the gruesome gas reloc
11704 reloc
->addend
= reloc
->address
;
11706 reloc
->addend
= -reloc
->address
;
11709 /* If this is a variant frag, we may need to adjust the existing
11710 reloc and generate a new one. */
11711 if (fixp
->fx_frag
->fr_opcode
!= NULL
11712 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11713 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11714 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11715 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11716 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11717 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11718 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11722 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11724 /* If this is not the last reloc in this frag, then we have two
11725 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11726 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11727 the second one handle all of them. */
11728 if (fixp
->fx_next
!= NULL
11729 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11731 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11732 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11733 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11734 && (fixp
->fx_next
->fx_r_type
11735 == BFD_RELOC_MIPS_GOT_LO16
))
11736 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11737 && (fixp
->fx_next
->fx_r_type
11738 == BFD_RELOC_MIPS_CALL_LO16
)));
11743 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11744 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11745 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11747 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11748 reloc2
->address
= (reloc
->address
11749 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11750 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11751 reloc2
->addend
= fixp
->fx_addnumber
;
11752 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11753 assert (reloc2
->howto
!= NULL
);
11755 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11759 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11762 reloc3
->address
+= 4;
11765 if (mips_pic
== NO_PIC
)
11767 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11768 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11770 else if (mips_pic
== SVR4_PIC
)
11772 switch (fixp
->fx_r_type
)
11776 case BFD_RELOC_MIPS_GOT16
:
11778 case BFD_RELOC_MIPS_CALL16
:
11779 case BFD_RELOC_MIPS_GOT_LO16
:
11780 case BFD_RELOC_MIPS_CALL_LO16
:
11781 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11789 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11790 to be used in the relocation's section offset. */
11791 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11793 reloc
->address
= reloc
->addend
;
11797 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11798 fixup_segment converted a non-PC relative reloc into a PC
11799 relative reloc. In such a case, we need to convert the reloc
11801 code
= fixp
->fx_r_type
;
11802 if (fixp
->fx_pcrel
)
11807 code
= BFD_RELOC_8_PCREL
;
11810 code
= BFD_RELOC_16_PCREL
;
11813 code
= BFD_RELOC_32_PCREL
;
11816 code
= BFD_RELOC_64_PCREL
;
11818 case BFD_RELOC_8_PCREL
:
11819 case BFD_RELOC_16_PCREL
:
11820 case BFD_RELOC_32_PCREL
:
11821 case BFD_RELOC_64_PCREL
:
11822 case BFD_RELOC_16_PCREL_S2
:
11823 case BFD_RELOC_PCREL_HI16_S
:
11824 case BFD_RELOC_PCREL_LO16
:
11827 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11828 _("Cannot make %s relocation PC relative"),
11829 bfd_get_reloc_code_name (code
));
11833 /* To support a PC relative reloc when generating embedded PIC code
11834 for ECOFF, we use a Cygnus extension. We check for that here to
11835 make sure that we don't let such a reloc escape normally. */
11836 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11837 && code
== BFD_RELOC_16_PCREL_S2
11838 && mips_pic
!= EMBEDDED_PIC
)
11839 reloc
->howto
= NULL
;
11841 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11843 if (reloc
->howto
== NULL
)
11845 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11846 _("Can not represent %s relocation in this object file format"),
11847 bfd_get_reloc_code_name (code
));
11854 /* Relax a machine dependent frag. This returns the amount by which
11855 the current size of the frag should change. */
11858 mips_relax_frag (fragp
, stretch
)
11862 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11865 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11867 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11869 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11874 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11876 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11883 /* Convert a machine dependent frag. */
11886 md_convert_frag (abfd
, asec
, fragp
)
11894 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11897 register const struct mips16_immed_operand
*op
;
11898 boolean small
, ext
;
11901 unsigned long insn
;
11902 boolean use_extend
;
11903 unsigned short extend
;
11905 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11906 op
= mips16_immed_operands
;
11907 while (op
->type
!= type
)
11910 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11921 resolve_symbol_value (fragp
->fr_symbol
, 1);
11922 val
= S_GET_VALUE (fragp
->fr_symbol
);
11927 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11929 /* The rules for the base address of a PC relative reloc are
11930 complicated; see mips16_extended_frag. */
11931 if (type
== 'p' || type
== 'q')
11936 /* Ignore the low bit in the target, since it will be
11937 set for a text label. */
11938 if ((val
& 1) != 0)
11941 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11943 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11946 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11949 /* Make sure the section winds up with the alignment we have
11952 record_alignment (asec
, op
->shift
);
11956 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11957 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11958 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11959 _("extended instruction in delay slot"));
11961 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11963 if (target_big_endian
)
11964 insn
= bfd_getb16 (buf
);
11966 insn
= bfd_getl16 (buf
);
11968 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11969 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11970 small
, ext
, &insn
, &use_extend
, &extend
);
11974 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11975 fragp
->fr_fix
+= 2;
11979 md_number_to_chars (buf
, insn
, 2);
11980 fragp
->fr_fix
+= 2;
11985 if (fragp
->fr_opcode
== NULL
)
11988 old
= RELAX_OLD (fragp
->fr_subtype
);
11989 new = RELAX_NEW (fragp
->fr_subtype
);
11990 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11993 memcpy (fixptr
- old
, fixptr
, new);
11995 fragp
->fr_fix
+= new - old
;
12001 /* This function is called after the relocs have been generated.
12002 We've been storing mips16 text labels as odd. Here we convert them
12003 back to even for the convenience of the debugger. */
12006 mips_frob_file_after_relocs ()
12009 unsigned int count
, i
;
12011 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12014 syms
= bfd_get_outsymbols (stdoutput
);
12015 count
= bfd_get_symcount (stdoutput
);
12016 for (i
= 0; i
< count
; i
++, syms
++)
12018 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12019 && ((*syms
)->value
& 1) != 0)
12021 (*syms
)->value
&= ~1;
12022 /* If the symbol has an odd size, it was probably computed
12023 incorrectly, so adjust that as well. */
12024 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12025 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12032 /* This function is called whenever a label is defined. It is used
12033 when handling branch delays; if a branch has a label, we assume we
12034 can not move it. */
12037 mips_define_label (sym
)
12040 struct insn_label_list
*l
;
12042 if (free_insn_labels
== NULL
)
12043 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12046 l
= free_insn_labels
;
12047 free_insn_labels
= l
->next
;
12051 l
->next
= insn_labels
;
12055 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12057 /* Some special processing for a MIPS ELF file. */
12060 mips_elf_final_processing ()
12062 /* Write out the register information. */
12067 s
.ri_gprmask
= mips_gprmask
;
12068 s
.ri_cprmask
[0] = mips_cprmask
[0];
12069 s
.ri_cprmask
[1] = mips_cprmask
[1];
12070 s
.ri_cprmask
[2] = mips_cprmask
[2];
12071 s
.ri_cprmask
[3] = mips_cprmask
[3];
12072 /* The gp_value field is set by the MIPS ELF backend. */
12074 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12075 ((Elf32_External_RegInfo
*)
12076 mips_regmask_frag
));
12080 Elf64_Internal_RegInfo s
;
12082 s
.ri_gprmask
= mips_gprmask
;
12084 s
.ri_cprmask
[0] = mips_cprmask
[0];
12085 s
.ri_cprmask
[1] = mips_cprmask
[1];
12086 s
.ri_cprmask
[2] = mips_cprmask
[2];
12087 s
.ri_cprmask
[3] = mips_cprmask
[3];
12088 /* The gp_value field is set by the MIPS ELF backend. */
12090 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12091 ((Elf64_External_RegInfo
*)
12092 mips_regmask_frag
));
12095 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12096 sort of BFD interface for this. */
12097 if (mips_any_noreorder
)
12098 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12099 if (mips_pic
!= NO_PIC
)
12100 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12102 /* Set the MIPS ELF ABI flags. */
12103 if (mips_abi_string
== 0)
12105 else if (strcmp (mips_abi_string
,"32") == 0)
12106 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12107 else if (strcmp (mips_abi_string
,"o64") == 0)
12108 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12109 else if (strcmp (mips_abi_string
,"eabi") == 0)
12112 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12114 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12118 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12120 typedef struct proc
12122 struct symbol
*isym
;
12123 unsigned long reg_mask
;
12124 unsigned long reg_offset
;
12125 unsigned long fpreg_mask
;
12126 unsigned long fpreg_offset
;
12127 unsigned long frame_offset
;
12128 unsigned long frame_reg
;
12129 unsigned long pc_reg
;
12133 static procS cur_proc
;
12134 static procS
*cur_proc_ptr
;
12135 static int numprocs
;
12145 /* check for premature end, nesting errors, etc */
12147 as_warn (_("missing `.end' at end of assembly"));
12156 if (*input_line_pointer
== '-')
12158 ++input_line_pointer
;
12161 if (!isdigit (*input_line_pointer
))
12162 as_bad (_("Expected simple number."));
12163 if (input_line_pointer
[0] == '0')
12165 if (input_line_pointer
[1] == 'x')
12167 input_line_pointer
+= 2;
12168 while (isxdigit (*input_line_pointer
))
12171 val
|= hex_value (*input_line_pointer
++);
12173 return negative
? -val
: val
;
12177 ++input_line_pointer
;
12178 while (isdigit (*input_line_pointer
))
12181 val
|= *input_line_pointer
++ - '0';
12183 return negative
? -val
: val
;
12186 if (!isdigit (*input_line_pointer
))
12188 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12189 *input_line_pointer
, *input_line_pointer
);
12190 as_warn (_("Invalid number"));
12193 while (isdigit (*input_line_pointer
))
12196 val
+= *input_line_pointer
++ - '0';
12198 return negative
? -val
: val
;
12201 /* The .file directive; just like the usual .file directive, but there
12202 is an initial number which is the ECOFF file index. */
12210 line
= get_number ();
12215 /* The .end directive. */
12224 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12227 demand_empty_rest_of_line ();
12232 #ifdef BFD_ASSEMBLER
12233 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12238 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12245 as_warn (_(".end not in text section"));
12249 as_warn (_(".end directive without a preceding .ent directive."));
12250 demand_empty_rest_of_line ();
12256 assert (S_GET_NAME (p
));
12257 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12258 as_warn (_(".end symbol does not match .ent symbol."));
12261 as_warn (_(".end directive missing or unknown symbol"));
12263 #ifdef MIPS_STABS_ELF
12265 segT saved_seg
= now_seg
;
12266 subsegT saved_subseg
= now_subseg
;
12267 fragS
*saved_frag
= frag_now
;
12273 dot
= frag_now_fix ();
12275 #ifdef md_flush_pending_output
12276 md_flush_pending_output ();
12280 subseg_set (pdr_seg
, 0);
12282 /* Write the symbol */
12283 exp
.X_op
= O_symbol
;
12284 exp
.X_add_symbol
= p
;
12285 exp
.X_add_number
= 0;
12286 emit_expr (&exp
, 4);
12288 fragp
= frag_more (7*4);
12290 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12291 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12292 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12293 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12294 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12295 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12296 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12298 subseg_set (saved_seg
, saved_subseg
);
12302 cur_proc_ptr
= NULL
;
12305 /* The .aent and .ent directives. */
12315 symbolP
= get_symbol ();
12316 if (*input_line_pointer
== ',')
12317 input_line_pointer
++;
12318 SKIP_WHITESPACE ();
12319 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
12320 number
= get_number ();
12322 #ifdef BFD_ASSEMBLER
12323 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12328 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12335 as_warn (_(".ent or .aent not in text section."));
12337 if (!aent
&& cur_proc_ptr
)
12338 as_warn (_("missing `.end'"));
12342 cur_proc_ptr
= &cur_proc
;
12343 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12345 cur_proc_ptr
->isym
= symbolP
;
12347 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
12352 demand_empty_rest_of_line ();
12355 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12356 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12357 s_mips_frame is used so that we can set the PDR information correctly.
12358 We can't use the ecoff routines because they make reference to the ecoff
12359 symbol table (in the mdebug section). */
12362 s_mips_frame (ignore
)
12365 #ifdef MIPS_STABS_ELF
12369 if (cur_proc_ptr
== (procS
*) NULL
)
12371 as_warn (_(".frame outside of .ent"));
12372 demand_empty_rest_of_line ();
12376 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12378 SKIP_WHITESPACE ();
12379 if (*input_line_pointer
++ != ','
12380 || get_absolute_expression_and_terminator (&val
) != ',')
12382 as_warn (_("Bad .frame directive"));
12383 --input_line_pointer
;
12384 demand_empty_rest_of_line ();
12388 cur_proc_ptr
->frame_offset
= val
;
12389 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12391 demand_empty_rest_of_line ();
12394 #endif /* MIPS_STABS_ELF */
12397 /* The .fmask and .mask directives. If the mdebug section is present
12398 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12399 embedded targets, s_mips_mask is used so that we can set the PDR
12400 information correctly. We can't use the ecoff routines because they
12401 make reference to the ecoff symbol table (in the mdebug section). */
12404 s_mips_mask (reg_type
)
12407 #ifdef MIPS_STABS_ELF
12410 if (cur_proc_ptr
== (procS
*) NULL
)
12412 as_warn (_(".mask/.fmask outside of .ent"));
12413 demand_empty_rest_of_line ();
12417 if (get_absolute_expression_and_terminator (&mask
) != ',')
12419 as_warn (_("Bad .mask/.fmask directive"));
12420 --input_line_pointer
;
12421 demand_empty_rest_of_line ();
12425 off
= get_absolute_expression ();
12427 if (reg_type
== 'F')
12429 cur_proc_ptr
->fpreg_mask
= mask
;
12430 cur_proc_ptr
->fpreg_offset
= off
;
12434 cur_proc_ptr
->reg_mask
= mask
;
12435 cur_proc_ptr
->reg_offset
= off
;
12438 demand_empty_rest_of_line ();
12440 s_ignore (reg_type
);
12441 #endif /* MIPS_STABS_ELF */
12444 /* The .loc directive. */
12455 assert (now_seg
== text_section
);
12457 lineno
= get_number ();
12458 addroff
= frag_now_fix ();
12460 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12461 S_SET_TYPE (symbolP
, N_SLINE
);
12462 S_SET_OTHER (symbolP
, 0);
12463 S_SET_DESC (symbolP
, lineno
);
12464 symbolP
->sy_segment
= now_seg
;