1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error
;
635 static int auto_align
= 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset
= -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset
= -1;
647 static int mips_cpreturn_register
= -1;
648 static int mips_gp_register
= GP
;
649 static int mips_gprel_offset
= 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid
= 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg
= SP
;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid
= 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize
= 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug
= 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history
[1 + MAX_NOPS
];
692 /* Arrays of operands for each instruction. */
693 #define MAX_OPERANDS 5
694 struct mips_operand_array
{
695 const struct mips_operand
*operand
[MAX_OPERANDS
];
697 static struct mips_operand_array
*mips_operands
;
698 static struct mips_operand_array
*mips16_operands
;
699 static struct mips_operand_array
*micromips_operands
;
701 /* Nop instructions used by emit_nop. */
702 static struct mips_cl_insn nop_insn
;
703 static struct mips_cl_insn mips16_nop_insn
;
704 static struct mips_cl_insn micromips_nop16_insn
;
705 static struct mips_cl_insn micromips_nop32_insn
;
707 /* The appropriate nop for the current mode. */
708 #define NOP_INSN (mips_opts.mips16 \
710 : (mips_opts.micromips \
711 ? (mips_opts.insn32 \
712 ? µmips_nop32_insn \
713 : µmips_nop16_insn) \
716 /* The size of NOP_INSN in bytes. */
717 #define NOP_INSN_SIZE ((mips_opts.mips16 \
718 || (mips_opts.micromips && !mips_opts.insn32)) \
721 /* If this is set, it points to a frag holding nop instructions which
722 were inserted before the start of a noreorder section. If those
723 nops turn out to be unnecessary, the size of the frag can be
725 static fragS
*prev_nop_frag
;
727 /* The number of nop instructions we created in prev_nop_frag. */
728 static int prev_nop_frag_holds
;
730 /* The number of nop instructions that we know we need in
732 static int prev_nop_frag_required
;
734 /* The number of instructions we've seen since prev_nop_frag. */
735 static int prev_nop_frag_since
;
737 /* Relocations against symbols are sometimes done in two parts, with a HI
738 relocation and a LO relocation. Each relocation has only 16 bits of
739 space to store an addend. This means that in order for the linker to
740 handle carries correctly, it must be able to locate both the HI and
741 the LO relocation. This means that the relocations must appear in
742 order in the relocation table.
744 In order to implement this, we keep track of each unmatched HI
745 relocation. We then sort them so that they immediately precede the
746 corresponding LO relocation. */
751 struct mips_hi_fixup
*next
;
754 /* The section this fixup is in. */
758 /* The list of unmatched HI relocs. */
760 static struct mips_hi_fixup
*mips_hi_fixup_list
;
762 /* The frag containing the last explicit relocation operator.
763 Null if explicit relocations have not been used. */
765 static fragS
*prev_reloc_op_frag
;
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map
[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map microMIPS register numbers to normal MIPS register numbers. */
776 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
778 /* The microMIPS registers with type h. */
779 static const unsigned int micromips_to_32_reg_h_map1
[] =
781 5, 5, 6, 4, 4, 4, 4, 4
783 static const unsigned int micromips_to_32_reg_h_map2
[] =
785 6, 7, 7, 21, 22, 5, 6, 7
788 /* The microMIPS registers with type m. */
789 static const unsigned int micromips_to_32_reg_m_map
[] =
791 0, 17, 2, 3, 16, 18, 19, 20
794 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
796 /* Classifies the kind of instructions we're interested in when
797 implementing -mfix-vr4120. */
798 enum fix_vr4120_class
806 NUM_FIX_VR4120_CLASSES
809 /* ...likewise -mfix-loongson2f-jump. */
810 static bfd_boolean mips_fix_loongson2f_jump
;
812 /* ...likewise -mfix-loongson2f-nop. */
813 static bfd_boolean mips_fix_loongson2f_nop
;
815 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
816 static bfd_boolean mips_fix_loongson2f
;
818 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
819 there must be at least one other instruction between an instruction
820 of type X and an instruction of type Y. */
821 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
823 /* True if -mfix-vr4120 is in force. */
824 static int mips_fix_vr4120
;
826 /* ...likewise -mfix-vr4130. */
827 static int mips_fix_vr4130
;
829 /* ...likewise -mfix-24k. */
830 static int mips_fix_24k
;
832 /* ...likewise -mfix-cn63xxp1 */
833 static bfd_boolean mips_fix_cn63xxp1
;
835 /* We don't relax branches by default, since this causes us to expand
836 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
837 fail to compute the offset before expanding the macro to the most
838 efficient expansion. */
840 static int mips_relax_branch
;
842 /* The expansion of many macros depends on the type of symbol that
843 they refer to. For example, when generating position-dependent code,
844 a macro that refers to a symbol may have two different expansions,
845 one which uses GP-relative addresses and one which uses absolute
846 addresses. When generating SVR4-style PIC, a macro may have
847 different expansions for local and global symbols.
849 We handle these situations by generating both sequences and putting
850 them in variant frags. In position-dependent code, the first sequence
851 will be the GP-relative one and the second sequence will be the
852 absolute one. In SVR4 PIC, the first sequence will be for global
853 symbols and the second will be for local symbols.
855 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
856 SECOND are the lengths of the two sequences in bytes. These fields
857 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
858 the subtype has the following flags:
861 Set if it has been decided that we should use the second
862 sequence instead of the first.
865 Set in the first variant frag if the macro's second implementation
866 is longer than its first. This refers to the macro as a whole,
867 not an individual relaxation.
870 Set in the first variant frag if the macro appeared in a .set nomacro
871 block and if one alternative requires a warning but the other does not.
874 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
877 RELAX_DELAY_SLOT_16BIT
878 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
881 RELAX_DELAY_SLOT_SIZE_FIRST
882 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
883 the macro is of the wrong size for the branch delay slot.
885 RELAX_DELAY_SLOT_SIZE_SECOND
886 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
887 the macro is of the wrong size for the branch delay slot.
889 The frag's "opcode" points to the first fixup for relaxable code.
891 Relaxable macros are generated using a sequence such as:
893 relax_start (SYMBOL);
894 ... generate first expansion ...
896 ... generate second expansion ...
899 The code and fixups for the unwanted alternative are discarded
900 by md_convert_frag. */
901 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
903 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
904 #define RELAX_SECOND(X) ((X) & 0xff)
905 #define RELAX_USE_SECOND 0x10000
906 #define RELAX_SECOND_LONGER 0x20000
907 #define RELAX_NOMACRO 0x40000
908 #define RELAX_DELAY_SLOT 0x80000
909 #define RELAX_DELAY_SLOT_16BIT 0x100000
910 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
911 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
913 /* Branch without likely bit. If label is out of range, we turn:
915 beq reg1, reg2, label
925 with the following opcode replacements:
932 bltzal <-> bgezal (with jal label instead of j label)
934 Even though keeping the delay slot instruction in the delay slot of
935 the branch would be more efficient, it would be very tricky to do
936 correctly, because we'd have to introduce a variable frag *after*
937 the delay slot instruction, and expand that instead. Let's do it
938 the easy way for now, even if the branch-not-taken case now costs
939 one additional instruction. Out-of-range branches are not supposed
940 to be common, anyway.
942 Branch likely. If label is out of range, we turn:
944 beql reg1, reg2, label
945 delay slot (annulled if branch not taken)
954 delay slot (executed only if branch taken)
957 It would be possible to generate a shorter sequence by losing the
958 likely bit, generating something like:
963 delay slot (executed only if branch taken)
975 bltzall -> bgezal (with jal label instead of j label)
976 bgezall -> bltzal (ditto)
979 but it's not clear that it would actually improve performance. */
980 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
984 | ((toofar) ? 0x20 : 0) \
985 | ((link) ? 0x40 : 0) \
986 | ((likely) ? 0x80 : 0) \
987 | ((uncond) ? 0x100 : 0)))
988 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
989 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
990 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
991 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
992 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
993 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
995 /* For mips16 code, we use an entirely different form of relaxation.
996 mips16 supports two versions of most instructions which take
997 immediate values: a small one which takes some small value, and a
998 larger one which takes a 16 bit value. Since branches also follow
999 this pattern, relaxing these values is required.
1001 We can assemble both mips16 and normal MIPS code in a single
1002 object. Therefore, we need to support this type of relaxation at
1003 the same time that we support the relaxation described above. We
1004 use the high bit of the subtype field to distinguish these cases.
1006 The information we store for this type of relaxation is the
1007 argument code found in the opcode file for this relocation, whether
1008 the user explicitly requested a small or extended form, and whether
1009 the relocation is in a jump or jal delay slot. That tells us the
1010 size of the value, and how it should be stored. We also store
1011 whether the fragment is considered to be extended or not. We also
1012 store whether this is known to be a branch to a different section,
1013 whether we have tried to relax this frag yet, and whether we have
1014 ever extended a PC relative fragment because of a shift count. */
1015 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1018 | ((small) ? 0x100 : 0) \
1019 | ((ext) ? 0x200 : 0) \
1020 | ((dslot) ? 0x400 : 0) \
1021 | ((jal_dslot) ? 0x800 : 0))
1022 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1023 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1024 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1025 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1026 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1027 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1028 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1029 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1030 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1031 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1032 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1033 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1035 /* For microMIPS code, we use relaxation similar to one we use for
1036 MIPS16 code. Some instructions that take immediate values support
1037 two encodings: a small one which takes some small value, and a
1038 larger one which takes a 16 bit value. As some branches also follow
1039 this pattern, relaxing these values is required.
1041 We can assemble both microMIPS and normal MIPS code in a single
1042 object. Therefore, we need to support this type of relaxation at
1043 the same time that we support the relaxation described above. We
1044 use one of the high bits of the subtype field to distinguish these
1047 The information we store for this type of relaxation is the argument
1048 code found in the opcode file for this relocation, the register
1049 selected as the assembler temporary, whether the branch is
1050 unconditional, whether it is compact, whether it stores the link
1051 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1052 branches to a sequence of instructions is enabled, and whether the
1053 displacement of a branch is too large to fit as an immediate argument
1054 of a 16-bit and a 32-bit branch, respectively. */
1055 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1056 relax32, toofar16, toofar32) \
1059 | (((at) & 0x1f) << 8) \
1060 | ((uncond) ? 0x2000 : 0) \
1061 | ((compact) ? 0x4000 : 0) \
1062 | ((link) ? 0x8000 : 0) \
1063 | ((relax32) ? 0x10000 : 0) \
1064 | ((toofar16) ? 0x20000 : 0) \
1065 | ((toofar32) ? 0x40000 : 0))
1066 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1067 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1068 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1069 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1070 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1071 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1072 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1074 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1075 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1076 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1077 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1078 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1079 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1081 /* Sign-extend 16-bit value X. */
1082 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1084 /* Is the given value a sign-extended 32-bit value? */
1085 #define IS_SEXT_32BIT_NUM(x) \
1086 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1087 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1089 /* Is the given value a sign-extended 16-bit value? */
1090 #define IS_SEXT_16BIT_NUM(x) \
1091 (((x) &~ (offsetT) 0x7fff) == 0 \
1092 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1094 /* Is the given value a sign-extended 12-bit value? */
1095 #define IS_SEXT_12BIT_NUM(x) \
1096 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1098 /* Is the given value a sign-extended 9-bit value? */
1099 #define IS_SEXT_9BIT_NUM(x) \
1100 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1102 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1103 #define IS_ZEXT_32BIT_NUM(x) \
1104 (((x) &~ (offsetT) 0xffffffff) == 0 \
1105 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1107 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1109 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1110 (((STRUCT) >> (SHIFT)) & (MASK))
1112 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1113 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1115 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1116 : EXTRACT_BITS ((INSN).insn_opcode, \
1117 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1118 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1119 EXTRACT_BITS ((INSN).insn_opcode, \
1120 MIPS16OP_MASK_##FIELD, \
1121 MIPS16OP_SH_##FIELD)
1123 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1124 #define MIPS16_EXTEND (0xf000U << 16)
1126 /* Whether or not we are emitting a branch-likely macro. */
1127 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1129 /* Global variables used when generating relaxable macros. See the
1130 comment above RELAX_ENCODE for more details about how relaxation
1133 /* 0 if we're not emitting a relaxable macro.
1134 1 if we're emitting the first of the two relaxation alternatives.
1135 2 if we're emitting the second alternative. */
1138 /* The first relaxable fixup in the current frag. (In other words,
1139 the first fixup that refers to relaxable code.) */
1142 /* sizes[0] says how many bytes of the first alternative are stored in
1143 the current frag. Likewise sizes[1] for the second alternative. */
1144 unsigned int sizes
[2];
1146 /* The symbol on which the choice of sequence depends. */
1150 /* Global variables used to decide whether a macro needs a warning. */
1152 /* True if the macro is in a branch delay slot. */
1153 bfd_boolean delay_slot_p
;
1155 /* Set to the length in bytes required if the macro is in a delay slot
1156 that requires a specific length of instruction, otherwise zero. */
1157 unsigned int delay_slot_length
;
1159 /* For relaxable macros, sizes[0] is the length of the first alternative
1160 in bytes and sizes[1] is the length of the second alternative.
1161 For non-relaxable macros, both elements give the length of the
1163 unsigned int sizes
[2];
1165 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1166 instruction of the first alternative in bytes and first_insn_sizes[1]
1167 is the length of the first instruction of the second alternative.
1168 For non-relaxable macros, both elements give the length of the first
1169 instruction in bytes.
1171 Set to zero if we haven't yet seen the first instruction. */
1172 unsigned int first_insn_sizes
[2];
1174 /* For relaxable macros, insns[0] is the number of instructions for the
1175 first alternative and insns[1] is the number of instructions for the
1178 For non-relaxable macros, both elements give the number of
1179 instructions for the macro. */
1180 unsigned int insns
[2];
1182 /* The first variant frag for this macro. */
1184 } mips_macro_warning
;
1186 /* Prototypes for static functions. */
1188 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1190 static void append_insn
1191 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1192 bfd_boolean expansionp
);
1193 static void mips_no_prev_insn (void);
1194 static void macro_build (expressionS
*, const char *, const char *, ...);
1195 static void mips16_macro_build
1196 (expressionS
*, const char *, const char *, va_list *);
1197 static void load_register (int, expressionS
*, int);
1198 static void macro_start (void);
1199 static void macro_end (void);
1200 static void macro (struct mips_cl_insn
*ip
, char *str
);
1201 static void mips16_macro (struct mips_cl_insn
* ip
);
1202 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1203 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1204 static void mips16_immed
1205 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1206 unsigned int, unsigned long *);
1207 static size_t my_getSmallExpression
1208 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1209 static void my_getExpression (expressionS
*, char *);
1210 static void s_align (int);
1211 static void s_change_sec (int);
1212 static void s_change_section (int);
1213 static void s_cons (int);
1214 static void s_float_cons (int);
1215 static void s_mips_globl (int);
1216 static void s_option (int);
1217 static void s_mipsset (int);
1218 static void s_abicalls (int);
1219 static void s_cpload (int);
1220 static void s_cpsetup (int);
1221 static void s_cplocal (int);
1222 static void s_cprestore (int);
1223 static void s_cpreturn (int);
1224 static void s_dtprelword (int);
1225 static void s_dtpreldword (int);
1226 static void s_tprelword (int);
1227 static void s_tpreldword (int);
1228 static void s_gpvalue (int);
1229 static void s_gpword (int);
1230 static void s_gpdword (int);
1231 static void s_ehword (int);
1232 static void s_cpadd (int);
1233 static void s_insn (int);
1234 static void s_nan (int);
1235 static void md_obj_begin (void);
1236 static void md_obj_end (void);
1237 static void s_mips_ent (int);
1238 static void s_mips_end (int);
1239 static void s_mips_frame (int);
1240 static void s_mips_mask (int reg_type
);
1241 static void s_mips_stab (int);
1242 static void s_mips_weakext (int);
1243 static void s_mips_file (int);
1244 static void s_mips_loc (int);
1245 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1246 static int relaxed_branch_length (fragS
*, asection
*, int);
1247 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1248 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1250 /* Table and functions used to map between CPU/ISA names, and
1251 ISA levels, and CPU numbers. */
1253 struct mips_cpu_info
1255 const char *name
; /* CPU or ISA name. */
1256 int flags
; /* MIPS_CPU_* flags. */
1257 int ase
; /* Set of ASEs implemented by the CPU. */
1258 int isa
; /* ISA level. */
1259 int cpu
; /* CPU number (default CPU if ISA). */
1262 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1264 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1265 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1266 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1268 /* Command-line options. */
1269 const char *md_shortopts
= "O::g::G:";
1273 OPTION_MARCH
= OPTION_MD_BASE
,
1297 OPTION_NO_SMARTMIPS
,
1303 OPTION_NO_MICROMIPS
,
1306 OPTION_COMPAT_ARCH_BASE
,
1315 OPTION_M7000_HILO_FIX
,
1316 OPTION_MNO_7000_HILO_FIX
,
1319 OPTION_FIX_LOONGSON2F_JUMP
,
1320 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1321 OPTION_FIX_LOONGSON2F_NOP
,
1322 OPTION_NO_FIX_LOONGSON2F_NOP
,
1324 OPTION_NO_FIX_VR4120
,
1326 OPTION_NO_FIX_VR4130
,
1327 OPTION_FIX_CN63XXP1
,
1328 OPTION_NO_FIX_CN63XXP1
,
1335 OPTION_CONSTRUCT_FLOATS
,
1336 OPTION_NO_CONSTRUCT_FLOATS
,
1339 OPTION_RELAX_BRANCH
,
1340 OPTION_NO_RELAX_BRANCH
,
1349 OPTION_SINGLE_FLOAT
,
1350 OPTION_DOUBLE_FLOAT
,
1363 OPTION_MVXWORKS_PIC
,
1368 struct option md_longopts
[] =
1370 /* Options which specify architecture. */
1371 {"march", required_argument
, NULL
, OPTION_MARCH
},
1372 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1373 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1374 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1375 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1376 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1377 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1378 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1379 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1380 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1381 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1382 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1384 /* Options which specify Application Specific Extensions (ASEs). */
1385 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1386 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1387 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1388 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1389 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1390 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1391 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1392 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1393 {"mmt", no_argument
, NULL
, OPTION_MT
},
1394 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1395 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1396 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1397 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1398 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1399 {"meva", no_argument
, NULL
, OPTION_EVA
},
1400 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1401 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1402 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1403 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1404 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1405 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1406 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1408 /* Old-style architecture options. Don't add more of these. */
1409 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1410 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1411 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1412 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1413 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1414 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1415 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1416 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1418 /* Options which enable bug fixes. */
1419 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1420 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1421 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1422 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1423 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1424 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1425 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1426 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1427 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1428 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1429 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1430 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1431 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1432 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1433 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1435 /* Miscellaneous options. */
1436 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1437 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1438 {"break", no_argument
, NULL
, OPTION_BREAK
},
1439 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1440 {"EB", no_argument
, NULL
, OPTION_EB
},
1441 {"EL", no_argument
, NULL
, OPTION_EL
},
1442 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1443 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1444 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1445 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1446 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1447 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1448 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1449 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1450 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1451 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1452 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1453 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1454 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1455 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1456 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1457 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1458 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1459 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1461 /* Strictly speaking this next option is ELF specific,
1462 but we allow it for other ports as well in order to
1463 make testing easier. */
1464 {"32", no_argument
, NULL
, OPTION_32
},
1466 /* ELF-specific options. */
1467 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1468 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1469 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1470 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1471 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1472 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1473 {"n32", no_argument
, NULL
, OPTION_N32
},
1474 {"64", no_argument
, NULL
, OPTION_64
},
1475 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1476 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1477 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1478 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1479 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1480 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1482 {NULL
, no_argument
, NULL
, 0}
1484 size_t md_longopts_size
= sizeof (md_longopts
);
1486 /* Information about either an Application Specific Extension or an
1487 optional architecture feature that, for simplicity, we treat in the
1488 same way as an ASE. */
1491 /* The name of the ASE, used in both the command-line and .set options. */
1494 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1495 and 64-bit architectures, the flags here refer to the subset that
1496 is available on both. */
1499 /* The ASE_* flag used for instructions that are available on 64-bit
1500 architectures but that are not included in FLAGS. */
1501 unsigned int flags64
;
1503 /* The command-line options that turn the ASE on and off. */
1507 /* The minimum required architecture revisions for MIPS32, MIPS64,
1508 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1511 int micromips32_rev
;
1512 int micromips64_rev
;
1515 /* A table of all supported ASEs. */
1516 static const struct mips_ase mips_ases
[] = {
1517 { "dsp", ASE_DSP
, ASE_DSP64
,
1518 OPTION_DSP
, OPTION_NO_DSP
,
1521 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1522 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1525 { "eva", ASE_EVA
, 0,
1526 OPTION_EVA
, OPTION_NO_EVA
,
1529 { "mcu", ASE_MCU
, 0,
1530 OPTION_MCU
, OPTION_NO_MCU
,
1533 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1534 { "mdmx", ASE_MDMX
, 0,
1535 OPTION_MDMX
, OPTION_NO_MDMX
,
1538 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1539 { "mips3d", ASE_MIPS3D
, 0,
1540 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1544 OPTION_MT
, OPTION_NO_MT
,
1547 { "smartmips", ASE_SMARTMIPS
, 0,
1548 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1551 { "virt", ASE_VIRT
, ASE_VIRT64
,
1552 OPTION_VIRT
, OPTION_NO_VIRT
,
1556 /* The set of ASEs that require -mfp64. */
1557 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1559 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1560 static const unsigned int mips_ase_groups
[] = {
1566 The following pseudo-ops from the Kane and Heinrich MIPS book
1567 should be defined here, but are currently unsupported: .alias,
1568 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1570 The following pseudo-ops from the Kane and Heinrich MIPS book are
1571 specific to the type of debugging information being generated, and
1572 should be defined by the object format: .aent, .begin, .bend,
1573 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1576 The following pseudo-ops from the Kane and Heinrich MIPS book are
1577 not MIPS CPU specific, but are also not specific to the object file
1578 format. This file is probably the best place to define them, but
1579 they are not currently supported: .asm0, .endr, .lab, .struct. */
1581 static const pseudo_typeS mips_pseudo_table
[] =
1583 /* MIPS specific pseudo-ops. */
1584 {"option", s_option
, 0},
1585 {"set", s_mipsset
, 0},
1586 {"rdata", s_change_sec
, 'r'},
1587 {"sdata", s_change_sec
, 's'},
1588 {"livereg", s_ignore
, 0},
1589 {"abicalls", s_abicalls
, 0},
1590 {"cpload", s_cpload
, 0},
1591 {"cpsetup", s_cpsetup
, 0},
1592 {"cplocal", s_cplocal
, 0},
1593 {"cprestore", s_cprestore
, 0},
1594 {"cpreturn", s_cpreturn
, 0},
1595 {"dtprelword", s_dtprelword
, 0},
1596 {"dtpreldword", s_dtpreldword
, 0},
1597 {"tprelword", s_tprelword
, 0},
1598 {"tpreldword", s_tpreldword
, 0},
1599 {"gpvalue", s_gpvalue
, 0},
1600 {"gpword", s_gpword
, 0},
1601 {"gpdword", s_gpdword
, 0},
1602 {"ehword", s_ehword
, 0},
1603 {"cpadd", s_cpadd
, 0},
1604 {"insn", s_insn
, 0},
1607 /* Relatively generic pseudo-ops that happen to be used on MIPS
1609 {"asciiz", stringer
, 8 + 1},
1610 {"bss", s_change_sec
, 'b'},
1612 {"half", s_cons
, 1},
1613 {"dword", s_cons
, 3},
1614 {"weakext", s_mips_weakext
, 0},
1615 {"origin", s_org
, 0},
1616 {"repeat", s_rept
, 0},
1618 /* For MIPS this is non-standard, but we define it for consistency. */
1619 {"sbss", s_change_sec
, 'B'},
1621 /* These pseudo-ops are defined in read.c, but must be overridden
1622 here for one reason or another. */
1623 {"align", s_align
, 0},
1624 {"byte", s_cons
, 0},
1625 {"data", s_change_sec
, 'd'},
1626 {"double", s_float_cons
, 'd'},
1627 {"float", s_float_cons
, 'f'},
1628 {"globl", s_mips_globl
, 0},
1629 {"global", s_mips_globl
, 0},
1630 {"hword", s_cons
, 1},
1632 {"long", s_cons
, 2},
1633 {"octa", s_cons
, 4},
1634 {"quad", s_cons
, 3},
1635 {"section", s_change_section
, 0},
1636 {"short", s_cons
, 1},
1637 {"single", s_float_cons
, 'f'},
1638 {"stabd", s_mips_stab
, 'd'},
1639 {"stabn", s_mips_stab
, 'n'},
1640 {"stabs", s_mips_stab
, 's'},
1641 {"text", s_change_sec
, 't'},
1642 {"word", s_cons
, 2},
1644 { "extern", ecoff_directive_extern
, 0},
1649 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1651 /* These pseudo-ops should be defined by the object file format.
1652 However, a.out doesn't support them, so we have versions here. */
1653 {"aent", s_mips_ent
, 1},
1654 {"bgnb", s_ignore
, 0},
1655 {"end", s_mips_end
, 0},
1656 {"endb", s_ignore
, 0},
1657 {"ent", s_mips_ent
, 0},
1658 {"file", s_mips_file
, 0},
1659 {"fmask", s_mips_mask
, 'F'},
1660 {"frame", s_mips_frame
, 0},
1661 {"loc", s_mips_loc
, 0},
1662 {"mask", s_mips_mask
, 'R'},
1663 {"verstamp", s_ignore
, 0},
1667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1668 purpose of the `.dc.a' internal pseudo-op. */
1671 mips_address_bytes (void)
1673 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1676 extern void pop_insert (const pseudo_typeS
*);
1679 mips_pop_insert (void)
1681 pop_insert (mips_pseudo_table
);
1682 if (! ECOFF_DEBUGGING
)
1683 pop_insert (mips_nonecoff_pseudo_table
);
1686 /* Symbols labelling the current insn. */
1688 struct insn_label_list
1690 struct insn_label_list
*next
;
1694 static struct insn_label_list
*free_insn_labels
;
1695 #define label_list tc_segment_info_data.labels
1697 static void mips_clear_insn_labels (void);
1698 static void mips_mark_labels (void);
1699 static void mips_compressed_mark_labels (void);
1702 mips_clear_insn_labels (void)
1704 register struct insn_label_list
**pl
;
1705 segment_info_type
*si
;
1709 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1712 si
= seg_info (now_seg
);
1713 *pl
= si
->label_list
;
1714 si
->label_list
= NULL
;
1718 /* Mark instruction labels in MIPS16/microMIPS mode. */
1721 mips_mark_labels (void)
1723 if (HAVE_CODE_COMPRESSION
)
1724 mips_compressed_mark_labels ();
1727 static char *expr_end
;
1729 /* Expressions which appear in macro instructions. These are set by
1730 mips_ip and read by macro. */
1732 static expressionS imm_expr
;
1733 static expressionS imm2_expr
;
1735 /* The relocatable field in an instruction and the relocs associated
1736 with it. These variables are used for instructions like LUI and
1737 JAL as well as true offsets. They are also used for address
1738 operands in macros. */
1740 static expressionS offset_expr
;
1741 static bfd_reloc_code_real_type offset_reloc
[3]
1742 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1744 /* This is set to the resulting size of the instruction to be produced
1745 by mips16_ip if an explicit extension is used or by mips_ip if an
1746 explicit size is supplied. */
1748 static unsigned int forced_insn_length
;
1750 /* True if we are assembling an instruction. All dot symbols defined during
1751 this time should be treated as code labels. */
1753 static bfd_boolean mips_assembling_insn
;
1755 /* The pdr segment for per procedure frame/regmask info. Not used for
1758 static segT pdr_seg
;
1760 /* The default target format to use. */
1762 #if defined (TE_FreeBSD)
1763 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1764 #elif defined (TE_TMIPS)
1765 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1771 mips_target_format (void)
1773 switch (OUTPUT_FLAVOR
)
1775 case bfd_target_elf_flavour
:
1777 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1778 return (target_big_endian
1779 ? "elf32-bigmips-vxworks"
1780 : "elf32-littlemips-vxworks");
1782 return (target_big_endian
1783 ? (HAVE_64BIT_OBJECTS
1784 ? ELF_TARGET ("elf64-", "big")
1786 ? ELF_TARGET ("elf32-n", "big")
1787 : ELF_TARGET ("elf32-", "big")))
1788 : (HAVE_64BIT_OBJECTS
1789 ? ELF_TARGET ("elf64-", "little")
1791 ? ELF_TARGET ("elf32-n", "little")
1792 : ELF_TARGET ("elf32-", "little"))));
1799 /* Return the ISA revision that is currently in use, or 0 if we are
1800 generating code for MIPS V or below. */
1805 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1808 /* microMIPS implies revision 2 or above. */
1809 if (mips_opts
.micromips
)
1812 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1818 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1821 mips_ase_mask (unsigned int flags
)
1825 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1826 if (flags
& mips_ase_groups
[i
])
1827 flags
|= mips_ase_groups
[i
];
1831 /* Check whether the current ISA supports ASE. Issue a warning if
1835 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1839 static unsigned int warned_isa
;
1840 static unsigned int warned_fp32
;
1842 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1843 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1845 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1846 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1847 && (warned_isa
& ase
->flags
) != ase
->flags
)
1849 warned_isa
|= ase
->flags
;
1850 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1851 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1853 as_warn (_("The %d-bit %s architecture does not support the"
1854 " `%s' extension"), size
, base
, ase
->name
);
1856 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1857 ase
->name
, base
, size
, min_rev
);
1859 if ((ase
->flags
& FP64_ASES
)
1861 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1863 warned_fp32
|= ase
->flags
;
1864 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1868 /* Check all enabled ASEs to see whether they are supported by the
1869 chosen architecture. */
1872 mips_check_isa_supports_ases (void)
1874 unsigned int i
, mask
;
1876 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1878 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1879 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1880 mips_check_isa_supports_ase (&mips_ases
[i
]);
1884 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1885 that were affected. */
1888 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1892 mask
= mips_ase_mask (ase
->flags
);
1893 mips_opts
.ase
&= ~mask
;
1895 mips_opts
.ase
|= ase
->flags
;
1899 /* Return the ASE called NAME, or null if none. */
1901 static const struct mips_ase
*
1902 mips_lookup_ase (const char *name
)
1906 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1907 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1908 return &mips_ases
[i
];
1912 /* Return the length of a microMIPS instruction in bytes. If bits of
1913 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1914 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1915 major opcode) will require further modifications to the opcode
1918 static inline unsigned int
1919 micromips_insn_length (const struct mips_opcode
*mo
)
1921 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1924 /* Return the length of MIPS16 instruction OPCODE. */
1926 static inline unsigned int
1927 mips16_opcode_length (unsigned long opcode
)
1929 return (opcode
>> 16) == 0 ? 2 : 4;
1932 /* Return the length of instruction INSN. */
1934 static inline unsigned int
1935 insn_length (const struct mips_cl_insn
*insn
)
1937 if (mips_opts
.micromips
)
1938 return micromips_insn_length (insn
->insn_mo
);
1939 else if (mips_opts
.mips16
)
1940 return mips16_opcode_length (insn
->insn_opcode
);
1945 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1948 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1953 insn
->insn_opcode
= mo
->match
;
1956 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1957 insn
->fixp
[i
] = NULL
;
1958 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1959 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1960 insn
->mips16_absolute_jump_p
= 0;
1961 insn
->complete_p
= 0;
1962 insn
->cleared_p
= 0;
1965 /* Get a list of all the operands in INSN. */
1967 static const struct mips_operand_array
*
1968 insn_operands (const struct mips_cl_insn
*insn
)
1970 if (insn
->insn_mo
>= &mips_opcodes
[0]
1971 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
1972 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
1974 if (insn
->insn_mo
>= &mips16_opcodes
[0]
1975 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
1976 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
1978 if (insn
->insn_mo
>= µmips_opcodes
[0]
1979 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
1980 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
1985 /* Get a description of operand OPNO of INSN. */
1987 static const struct mips_operand
*
1988 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
1990 const struct mips_operand_array
*operands
;
1992 operands
= insn_operands (insn
);
1993 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
1995 return operands
->operand
[opno
];
1998 /* Install UVAL as the value of OPERAND in INSN. */
2001 insn_insert_operand (struct mips_cl_insn
*insn
,
2002 const struct mips_operand
*operand
, unsigned int uval
)
2004 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2007 /* Extract the value of OPERAND from INSN. */
2009 static inline unsigned
2010 insn_extract_operand (const struct mips_cl_insn
*insn
,
2011 const struct mips_operand
*operand
)
2013 return mips_extract_operand (operand
, insn
->insn_opcode
);
2016 /* Record the current MIPS16/microMIPS mode in now_seg. */
2019 mips_record_compressed_mode (void)
2021 segment_info_type
*si
;
2023 si
= seg_info (now_seg
);
2024 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2025 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2026 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2027 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2030 /* Read a standard MIPS instruction from BUF. */
2032 static unsigned long
2033 read_insn (char *buf
)
2035 if (target_big_endian
)
2036 return bfd_getb32 ((bfd_byte
*) buf
);
2038 return bfd_getl32 ((bfd_byte
*) buf
);
2041 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2045 write_insn (char *buf
, unsigned int insn
)
2047 md_number_to_chars (buf
, insn
, 4);
2051 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2052 has length LENGTH. */
2054 static unsigned long
2055 read_compressed_insn (char *buf
, unsigned int length
)
2061 for (i
= 0; i
< length
; i
+= 2)
2064 if (target_big_endian
)
2065 insn
|= bfd_getb16 ((char *) buf
);
2067 insn
|= bfd_getl16 ((char *) buf
);
2073 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2074 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2077 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2081 for (i
= 0; i
< length
; i
+= 2)
2082 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2083 return buf
+ length
;
2086 /* Install INSN at the location specified by its "frag" and "where" fields. */
2089 install_insn (const struct mips_cl_insn
*insn
)
2091 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2092 if (HAVE_CODE_COMPRESSION
)
2093 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2095 write_insn (f
, insn
->insn_opcode
);
2096 mips_record_compressed_mode ();
2099 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2100 and install the opcode in the new location. */
2103 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2108 insn
->where
= where
;
2109 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2110 if (insn
->fixp
[i
] != NULL
)
2112 insn
->fixp
[i
]->fx_frag
= frag
;
2113 insn
->fixp
[i
]->fx_where
= where
;
2115 install_insn (insn
);
2118 /* Add INSN to the end of the output. */
2121 add_fixed_insn (struct mips_cl_insn
*insn
)
2123 char *f
= frag_more (insn_length (insn
));
2124 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2127 /* Start a variant frag and move INSN to the start of the variant part,
2128 marking it as fixed. The other arguments are as for frag_var. */
2131 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2132 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2134 frag_grow (max_chars
);
2135 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2137 frag_var (rs_machine_dependent
, max_chars
, var
,
2138 subtype
, symbol
, offset
, NULL
);
2141 /* Insert N copies of INSN into the history buffer, starting at
2142 position FIRST. Neither FIRST nor N need to be clipped. */
2145 insert_into_history (unsigned int first
, unsigned int n
,
2146 const struct mips_cl_insn
*insn
)
2148 if (mips_relax
.sequence
!= 2)
2152 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2154 history
[i
] = history
[i
- n
];
2160 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2161 the idea is to make it obvious at a glance that each errata is
2165 init_vr4120_conflicts (void)
2167 #define CONFLICT(FIRST, SECOND) \
2168 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2170 /* Errata 21 - [D]DIV[U] after [D]MACC */
2171 CONFLICT (MACC
, DIV
);
2172 CONFLICT (DMACC
, DIV
);
2174 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2175 CONFLICT (DMULT
, DMULT
);
2176 CONFLICT (DMULT
, DMACC
);
2177 CONFLICT (DMACC
, DMULT
);
2178 CONFLICT (DMACC
, DMACC
);
2180 /* Errata 24 - MT{LO,HI} after [D]MACC */
2181 CONFLICT (MACC
, MTHILO
);
2182 CONFLICT (DMACC
, MTHILO
);
2184 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2185 instruction is executed immediately after a MACC or DMACC
2186 instruction, the result of [either instruction] is incorrect." */
2187 CONFLICT (MACC
, MULT
);
2188 CONFLICT (MACC
, DMULT
);
2189 CONFLICT (DMACC
, MULT
);
2190 CONFLICT (DMACC
, DMULT
);
2192 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2193 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2194 DDIV or DDIVU instruction, the result of the MACC or
2195 DMACC instruction is incorrect.". */
2196 CONFLICT (DMULT
, MACC
);
2197 CONFLICT (DMULT
, DMACC
);
2198 CONFLICT (DIV
, MACC
);
2199 CONFLICT (DIV
, DMACC
);
2209 #define RTYPE_MASK 0x1ff00
2210 #define RTYPE_NUM 0x00100
2211 #define RTYPE_FPU 0x00200
2212 #define RTYPE_FCC 0x00400
2213 #define RTYPE_VEC 0x00800
2214 #define RTYPE_GP 0x01000
2215 #define RTYPE_CP0 0x02000
2216 #define RTYPE_PC 0x04000
2217 #define RTYPE_ACC 0x08000
2218 #define RTYPE_CCC 0x10000
2219 #define RNUM_MASK 0x000ff
2220 #define RWARN 0x80000
2222 #define GENERIC_REGISTER_NUMBERS \
2223 {"$0", RTYPE_NUM | 0}, \
2224 {"$1", RTYPE_NUM | 1}, \
2225 {"$2", RTYPE_NUM | 2}, \
2226 {"$3", RTYPE_NUM | 3}, \
2227 {"$4", RTYPE_NUM | 4}, \
2228 {"$5", RTYPE_NUM | 5}, \
2229 {"$6", RTYPE_NUM | 6}, \
2230 {"$7", RTYPE_NUM | 7}, \
2231 {"$8", RTYPE_NUM | 8}, \
2232 {"$9", RTYPE_NUM | 9}, \
2233 {"$10", RTYPE_NUM | 10}, \
2234 {"$11", RTYPE_NUM | 11}, \
2235 {"$12", RTYPE_NUM | 12}, \
2236 {"$13", RTYPE_NUM | 13}, \
2237 {"$14", RTYPE_NUM | 14}, \
2238 {"$15", RTYPE_NUM | 15}, \
2239 {"$16", RTYPE_NUM | 16}, \
2240 {"$17", RTYPE_NUM | 17}, \
2241 {"$18", RTYPE_NUM | 18}, \
2242 {"$19", RTYPE_NUM | 19}, \
2243 {"$20", RTYPE_NUM | 20}, \
2244 {"$21", RTYPE_NUM | 21}, \
2245 {"$22", RTYPE_NUM | 22}, \
2246 {"$23", RTYPE_NUM | 23}, \
2247 {"$24", RTYPE_NUM | 24}, \
2248 {"$25", RTYPE_NUM | 25}, \
2249 {"$26", RTYPE_NUM | 26}, \
2250 {"$27", RTYPE_NUM | 27}, \
2251 {"$28", RTYPE_NUM | 28}, \
2252 {"$29", RTYPE_NUM | 29}, \
2253 {"$30", RTYPE_NUM | 30}, \
2254 {"$31", RTYPE_NUM | 31}
2256 #define FPU_REGISTER_NAMES \
2257 {"$f0", RTYPE_FPU | 0}, \
2258 {"$f1", RTYPE_FPU | 1}, \
2259 {"$f2", RTYPE_FPU | 2}, \
2260 {"$f3", RTYPE_FPU | 3}, \
2261 {"$f4", RTYPE_FPU | 4}, \
2262 {"$f5", RTYPE_FPU | 5}, \
2263 {"$f6", RTYPE_FPU | 6}, \
2264 {"$f7", RTYPE_FPU | 7}, \
2265 {"$f8", RTYPE_FPU | 8}, \
2266 {"$f9", RTYPE_FPU | 9}, \
2267 {"$f10", RTYPE_FPU | 10}, \
2268 {"$f11", RTYPE_FPU | 11}, \
2269 {"$f12", RTYPE_FPU | 12}, \
2270 {"$f13", RTYPE_FPU | 13}, \
2271 {"$f14", RTYPE_FPU | 14}, \
2272 {"$f15", RTYPE_FPU | 15}, \
2273 {"$f16", RTYPE_FPU | 16}, \
2274 {"$f17", RTYPE_FPU | 17}, \
2275 {"$f18", RTYPE_FPU | 18}, \
2276 {"$f19", RTYPE_FPU | 19}, \
2277 {"$f20", RTYPE_FPU | 20}, \
2278 {"$f21", RTYPE_FPU | 21}, \
2279 {"$f22", RTYPE_FPU | 22}, \
2280 {"$f23", RTYPE_FPU | 23}, \
2281 {"$f24", RTYPE_FPU | 24}, \
2282 {"$f25", RTYPE_FPU | 25}, \
2283 {"$f26", RTYPE_FPU | 26}, \
2284 {"$f27", RTYPE_FPU | 27}, \
2285 {"$f28", RTYPE_FPU | 28}, \
2286 {"$f29", RTYPE_FPU | 29}, \
2287 {"$f30", RTYPE_FPU | 30}, \
2288 {"$f31", RTYPE_FPU | 31}
2290 #define FPU_CONDITION_CODE_NAMES \
2291 {"$fcc0", RTYPE_FCC | 0}, \
2292 {"$fcc1", RTYPE_FCC | 1}, \
2293 {"$fcc2", RTYPE_FCC | 2}, \
2294 {"$fcc3", RTYPE_FCC | 3}, \
2295 {"$fcc4", RTYPE_FCC | 4}, \
2296 {"$fcc5", RTYPE_FCC | 5}, \
2297 {"$fcc6", RTYPE_FCC | 6}, \
2298 {"$fcc7", RTYPE_FCC | 7}
2300 #define COPROC_CONDITION_CODE_NAMES \
2301 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2302 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2303 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2304 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2305 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2306 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2307 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2308 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2310 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2311 {"$a4", RTYPE_GP | 8}, \
2312 {"$a5", RTYPE_GP | 9}, \
2313 {"$a6", RTYPE_GP | 10}, \
2314 {"$a7", RTYPE_GP | 11}, \
2315 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2316 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2317 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2318 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2319 {"$t0", RTYPE_GP | 12}, \
2320 {"$t1", RTYPE_GP | 13}, \
2321 {"$t2", RTYPE_GP | 14}, \
2322 {"$t3", RTYPE_GP | 15}
2324 #define O32_SYMBOLIC_REGISTER_NAMES \
2325 {"$t0", RTYPE_GP | 8}, \
2326 {"$t1", RTYPE_GP | 9}, \
2327 {"$t2", RTYPE_GP | 10}, \
2328 {"$t3", RTYPE_GP | 11}, \
2329 {"$t4", RTYPE_GP | 12}, \
2330 {"$t5", RTYPE_GP | 13}, \
2331 {"$t6", RTYPE_GP | 14}, \
2332 {"$t7", RTYPE_GP | 15}, \
2333 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2334 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2335 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2336 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2338 /* Remaining symbolic register names */
2339 #define SYMBOLIC_REGISTER_NAMES \
2340 {"$zero", RTYPE_GP | 0}, \
2341 {"$at", RTYPE_GP | 1}, \
2342 {"$AT", RTYPE_GP | 1}, \
2343 {"$v0", RTYPE_GP | 2}, \
2344 {"$v1", RTYPE_GP | 3}, \
2345 {"$a0", RTYPE_GP | 4}, \
2346 {"$a1", RTYPE_GP | 5}, \
2347 {"$a2", RTYPE_GP | 6}, \
2348 {"$a3", RTYPE_GP | 7}, \
2349 {"$s0", RTYPE_GP | 16}, \
2350 {"$s1", RTYPE_GP | 17}, \
2351 {"$s2", RTYPE_GP | 18}, \
2352 {"$s3", RTYPE_GP | 19}, \
2353 {"$s4", RTYPE_GP | 20}, \
2354 {"$s5", RTYPE_GP | 21}, \
2355 {"$s6", RTYPE_GP | 22}, \
2356 {"$s7", RTYPE_GP | 23}, \
2357 {"$t8", RTYPE_GP | 24}, \
2358 {"$t9", RTYPE_GP | 25}, \
2359 {"$k0", RTYPE_GP | 26}, \
2360 {"$kt0", RTYPE_GP | 26}, \
2361 {"$k1", RTYPE_GP | 27}, \
2362 {"$kt1", RTYPE_GP | 27}, \
2363 {"$gp", RTYPE_GP | 28}, \
2364 {"$sp", RTYPE_GP | 29}, \
2365 {"$s8", RTYPE_GP | 30}, \
2366 {"$fp", RTYPE_GP | 30}, \
2367 {"$ra", RTYPE_GP | 31}
2369 #define MIPS16_SPECIAL_REGISTER_NAMES \
2370 {"$pc", RTYPE_PC | 0}
2372 #define MDMX_VECTOR_REGISTER_NAMES \
2373 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2374 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2375 {"$v2", RTYPE_VEC | 2}, \
2376 {"$v3", RTYPE_VEC | 3}, \
2377 {"$v4", RTYPE_VEC | 4}, \
2378 {"$v5", RTYPE_VEC | 5}, \
2379 {"$v6", RTYPE_VEC | 6}, \
2380 {"$v7", RTYPE_VEC | 7}, \
2381 {"$v8", RTYPE_VEC | 8}, \
2382 {"$v9", RTYPE_VEC | 9}, \
2383 {"$v10", RTYPE_VEC | 10}, \
2384 {"$v11", RTYPE_VEC | 11}, \
2385 {"$v12", RTYPE_VEC | 12}, \
2386 {"$v13", RTYPE_VEC | 13}, \
2387 {"$v14", RTYPE_VEC | 14}, \
2388 {"$v15", RTYPE_VEC | 15}, \
2389 {"$v16", RTYPE_VEC | 16}, \
2390 {"$v17", RTYPE_VEC | 17}, \
2391 {"$v18", RTYPE_VEC | 18}, \
2392 {"$v19", RTYPE_VEC | 19}, \
2393 {"$v20", RTYPE_VEC | 20}, \
2394 {"$v21", RTYPE_VEC | 21}, \
2395 {"$v22", RTYPE_VEC | 22}, \
2396 {"$v23", RTYPE_VEC | 23}, \
2397 {"$v24", RTYPE_VEC | 24}, \
2398 {"$v25", RTYPE_VEC | 25}, \
2399 {"$v26", RTYPE_VEC | 26}, \
2400 {"$v27", RTYPE_VEC | 27}, \
2401 {"$v28", RTYPE_VEC | 28}, \
2402 {"$v29", RTYPE_VEC | 29}, \
2403 {"$v30", RTYPE_VEC | 30}, \
2404 {"$v31", RTYPE_VEC | 31}
2406 #define MIPS_DSP_ACCUMULATOR_NAMES \
2407 {"$ac0", RTYPE_ACC | 0}, \
2408 {"$ac1", RTYPE_ACC | 1}, \
2409 {"$ac2", RTYPE_ACC | 2}, \
2410 {"$ac3", RTYPE_ACC | 3}
2412 static const struct regname reg_names
[] = {
2413 GENERIC_REGISTER_NUMBERS
,
2415 FPU_CONDITION_CODE_NAMES
,
2416 COPROC_CONDITION_CODE_NAMES
,
2418 /* The $txx registers depends on the abi,
2419 these will be added later into the symbol table from
2420 one of the tables below once mips_abi is set after
2421 parsing of arguments from the command line. */
2422 SYMBOLIC_REGISTER_NAMES
,
2424 MIPS16_SPECIAL_REGISTER_NAMES
,
2425 MDMX_VECTOR_REGISTER_NAMES
,
2426 MIPS_DSP_ACCUMULATOR_NAMES
,
2430 static const struct regname reg_names_o32
[] = {
2431 O32_SYMBOLIC_REGISTER_NAMES
,
2435 static const struct regname reg_names_n32n64
[] = {
2436 N32N64_SYMBOLIC_REGISTER_NAMES
,
2440 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2441 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2442 of these register symbols, return the associated vector register,
2443 otherwise return SYMVAL itself. */
2446 mips_prefer_vec_regno (unsigned int symval
)
2448 if ((symval
& -2) == (RTYPE_GP
| 2))
2449 return RTYPE_VEC
| (symval
& 1);
2453 /* Return true if the string at *SPTR is a valid register name. If so,
2454 move *SPTR past the register and store the register's symbol value
2455 in *SYMVAL. This symbol value includes the register number
2456 (RNUM_MASK) and register type (RTYPE_MASK). */
2459 mips_parse_register (char **sptr
, unsigned int *symval
)
2465 /* Find end of name. */
2467 if (is_name_beginner (*e
))
2469 while (is_part_of_name (*e
))
2472 /* Terminate name. */
2476 /* Look up the name. */
2477 symbol
= symbol_find (s
);
2480 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2484 *symval
= S_GET_VALUE (symbol
);
2488 /* Check if SPTR points at a valid register specifier according to TYPES.
2489 If so, then return 1, advance S to consume the specifier and store
2490 the register's number in REGNOP, otherwise return 0. */
2493 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2497 if (mips_parse_register (s
, ®no
))
2499 if (types
& RTYPE_VEC
)
2500 regno
= mips_prefer_vec_regno (regno
);
2509 as_warn (_("Unrecognized register name `%s'"), *s
);
2514 return regno
<= RNUM_MASK
;
2517 /* Token types for parsed operand lists. */
2518 enum mips_operand_token_type
{
2519 /* A plain register, e.g. $f2. */
2522 /* An element of a vector, e.g. $v0[1]. */
2525 /* A continuous range of registers, e.g. $s0-$s4. */
2528 /* A (possibly relocated) expression. */
2531 /* A floating-point value. */
2534 /* A single character. This can be '(', ')' or ',', but '(' only appears
2538 /* The end of the operand list. */
2542 /* A parsed operand token. */
2543 struct mips_operand_token
2545 /* The type of token. */
2546 enum mips_operand_token_type type
;
2549 /* The register symbol value for an OT_REG. */
2552 /* The register symbol value and index for an OT_REG_ELEMENT. */
2558 /* The two register symbol values involved in an OT_REG_RANGE. */
2560 unsigned int regno1
;
2561 unsigned int regno2
;
2564 /* The value of an OT_INTEGER. The value is represented as an
2565 expression and the relocation operators that were applied to
2566 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2567 relocation operators were used. */
2570 bfd_reloc_code_real_type relocs
[3];
2573 /* The binary data for an OT_FLOAT constant, and the number of bytes
2576 unsigned char data
[8];
2580 /* The character represented by an OT_CHAR. */
2585 /* An obstack used to construct lists of mips_operand_tokens. */
2586 static struct obstack mips_operand_tokens
;
2588 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2591 mips_add_token (struct mips_operand_token
*token
,
2592 enum mips_operand_token_type type
)
2595 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2598 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2599 and OT_REG tokens for them if so, and return a pointer to the first
2600 unconsumed character. Return null otherwise. */
2603 mips_parse_base_start (char *s
)
2605 struct mips_operand_token token
;
2612 SKIP_SPACE_TABS (s
);
2613 if (!mips_parse_register (&s
, ®no
))
2617 mips_add_token (&token
, OT_CHAR
);
2619 token
.u
.regno
= regno
;
2620 mips_add_token (&token
, OT_REG
);
2625 /* Parse one or more tokens from S. Return a pointer to the first
2626 unconsumed character on success. Return null if an error was found
2627 and store the error text in insn_error. FLOAT_FORMAT is as for
2628 mips_parse_arguments. */
2631 mips_parse_argument_token (char *s
, char float_format
)
2633 char *end
, *save_in
, *err
;
2634 unsigned int regno1
, regno2
;
2635 struct mips_operand_token token
;
2637 /* First look for "($reg", since we want to treat that as an
2638 OT_CHAR and OT_REG rather than an expression. */
2639 end
= mips_parse_base_start (s
);
2643 /* Handle other characters that end up as OT_CHARs. */
2644 if (*s
== ')' || *s
== ',')
2647 mips_add_token (&token
, OT_CHAR
);
2652 /* Handle tokens that start with a register. */
2653 if (mips_parse_register (&s
, ®no1
))
2655 SKIP_SPACE_TABS (s
);
2658 /* A register range. */
2660 SKIP_SPACE_TABS (s
);
2661 if (!mips_parse_register (&s
, ®no2
))
2663 insn_error
= _("Invalid register range");
2667 token
.u
.reg_range
.regno1
= regno1
;
2668 token
.u
.reg_range
.regno2
= regno2
;
2669 mips_add_token (&token
, OT_REG_RANGE
);
2674 /* A vector element. */
2675 expressionS element
;
2678 SKIP_SPACE_TABS (s
);
2679 my_getExpression (&element
, s
);
2680 if (element
.X_op
!= O_constant
)
2682 insn_error
= _("Vector element must be constant");
2686 SKIP_SPACE_TABS (s
);
2689 insn_error
= _("Missing `]'");
2694 token
.u
.reg_element
.regno
= regno1
;
2695 token
.u
.reg_element
.index
= element
.X_add_number
;
2696 mips_add_token (&token
, OT_REG_ELEMENT
);
2700 /* Looks like just a plain register. */
2701 token
.u
.regno
= regno1
;
2702 mips_add_token (&token
, OT_REG
);
2708 /* First try to treat expressions as floats. */
2709 save_in
= input_line_pointer
;
2710 input_line_pointer
= s
;
2711 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2712 &token
.u
.flt
.length
);
2713 end
= input_line_pointer
;
2714 input_line_pointer
= save_in
;
2722 mips_add_token (&token
, OT_FLOAT
);
2727 /* Treat everything else as an integer expression. */
2728 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
2729 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
2730 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
2731 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
2733 mips_add_token (&token
, OT_INTEGER
);
2737 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2738 if expressions should be treated as 32-bit floating-point constants,
2739 'd' if they should be treated as 64-bit floating-point constants,
2740 or 0 if they should be treated as integer expressions (the usual case).
2742 Return a list of tokens on success, otherwise return 0. The caller
2743 must obstack_free the list after use. */
2745 static struct mips_operand_token
*
2746 mips_parse_arguments (char *s
, char float_format
)
2748 struct mips_operand_token token
;
2750 SKIP_SPACE_TABS (s
);
2753 s
= mips_parse_argument_token (s
, float_format
);
2756 obstack_free (&mips_operand_tokens
,
2757 obstack_finish (&mips_operand_tokens
));
2760 SKIP_SPACE_TABS (s
);
2762 mips_add_token (&token
, OT_END
);
2763 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
2766 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2767 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2770 is_opcode_valid (const struct mips_opcode
*mo
)
2772 int isa
= mips_opts
.isa
;
2773 int ase
= mips_opts
.ase
;
2777 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2778 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2779 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2780 ase
|= mips_ases
[i
].flags64
;
2782 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2785 /* Check whether the instruction or macro requires single-precision or
2786 double-precision floating-point support. Note that this information is
2787 stored differently in the opcode table for insns and macros. */
2788 if (mo
->pinfo
== INSN_MACRO
)
2790 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2791 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2795 fp_s
= mo
->pinfo
& FP_S
;
2796 fp_d
= mo
->pinfo
& FP_D
;
2799 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2802 if (fp_s
&& mips_opts
.soft_float
)
2808 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2809 selected ISA and architecture. */
2812 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2814 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2817 /* Return TRUE if the size of the microMIPS opcode MO matches one
2818 explicitly requested. Always TRUE in the standard MIPS mode. */
2821 is_size_valid (const struct mips_opcode
*mo
)
2823 if (!mips_opts
.micromips
)
2826 if (mips_opts
.insn32
)
2828 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2830 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2833 if (!forced_insn_length
)
2835 if (mo
->pinfo
== INSN_MACRO
)
2837 return forced_insn_length
== micromips_insn_length (mo
);
2840 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2841 of the preceding instruction. Always TRUE in the standard MIPS mode.
2843 We don't accept macros in 16-bit delay slots to avoid a case where
2844 a macro expansion fails because it relies on a preceding 32-bit real
2845 instruction to have matched and does not handle the operands correctly.
2846 The only macros that may expand to 16-bit instructions are JAL that
2847 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2848 and BGT (that likewise cannot be placed in a delay slot) that decay to
2849 a NOP. In all these cases the macros precede any corresponding real
2850 instruction definitions in the opcode table, so they will match in the
2851 second pass where the size of the delay slot is ignored and therefore
2852 produce correct code. */
2855 is_delay_slot_valid (const struct mips_opcode
*mo
)
2857 if (!mips_opts
.micromips
)
2860 if (mo
->pinfo
== INSN_MACRO
)
2861 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2862 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2863 && micromips_insn_length (mo
) != 4)
2865 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2866 && micromips_insn_length (mo
) != 2)
2872 /* For consistency checking, verify that all bits of OPCODE are specified
2873 either by the match/mask part of the instruction definition, or by the
2874 operand list. Also build up a list of operands in OPERANDS.
2876 INSN_BITS says which bits of the instruction are significant.
2877 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
2878 provides the mips_operand description of each operand. DECODE_OPERAND
2879 is null for MIPS16 instructions. */
2882 validate_mips_insn (const struct mips_opcode
*opcode
,
2883 unsigned long insn_bits
,
2884 const struct mips_operand
*(*decode_operand
) (const char *),
2885 struct mips_operand_array
*operands
)
2888 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
2889 const struct mips_operand
*operand
;
2891 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
2892 if ((mask
& opcode
->match
) != opcode
->match
)
2894 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2895 opcode
->name
, opcode
->args
);
2900 for (s
= opcode
->args
; *s
; ++s
)
2909 if (!decode_operand
)
2910 operand
= decode_mips16_operand (*s
, FALSE
);
2912 operand
= decode_operand (s
);
2913 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
2915 as_bad (_("internal: unknown operand type: %s %s"),
2916 opcode
->name
, opcode
->args
);
2919 gas_assert (opno
< MAX_OPERANDS
);
2920 operands
->operand
[opno
] = operand
;
2923 used_bits
|= ((1 << operand
->size
) - 1) << operand
->lsb
;
2924 if (operand
->type
== OP_MDMX_IMM_REG
)
2925 /* Bit 5 is the format selector (OB vs QH). The opcode table
2926 has separate entries for each format. */
2927 used_bits
&= ~(1 << (operand
->lsb
+ 5));
2928 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
2929 used_bits
&= ~(mask
& 0x700);
2931 /* Skip prefix characters. */
2932 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
2937 doubled
= used_bits
& mask
& insn_bits
;
2940 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2941 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
2945 undefined
= ~used_bits
& insn_bits
;
2946 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
2948 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2949 undefined
, opcode
->name
, opcode
->args
);
2952 used_bits
&= ~insn_bits
;
2955 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2956 used_bits
, opcode
->name
, opcode
->args
);
2962 /* The MIPS16 version of validate_mips_insn. */
2965 validate_mips16_insn (const struct mips_opcode
*opcode
,
2966 struct mips_operand_array
*operands
)
2968 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
2970 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
2971 instruction. Use TMP to describe the full instruction. */
2972 struct mips_opcode tmp
;
2977 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
2979 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
2982 /* The microMIPS version of validate_mips_insn. */
2985 validate_micromips_insn (const struct mips_opcode
*opc
,
2986 struct mips_operand_array
*operands
)
2988 unsigned long insn_bits
;
2989 unsigned long major
;
2990 unsigned int length
;
2992 if (opc
->pinfo
== INSN_MACRO
)
2993 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
2996 length
= micromips_insn_length (opc
);
2997 if (length
!= 2 && length
!= 4)
2999 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3000 "%s %s"), length
, opc
->name
, opc
->args
);
3003 major
= opc
->match
>> (10 + 8 * (length
- 2));
3004 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3005 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3007 as_bad (_("Internal error: bad microMIPS opcode "
3008 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3012 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3013 insn_bits
= 1 << 4 * length
;
3014 insn_bits
<<= 4 * length
;
3016 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3020 /* This function is called once, at assembler startup time. It should set up
3021 all the tables, etc. that the MD part of the assembler will need. */
3026 const char *retval
= NULL
;
3030 if (mips_pic
!= NO_PIC
)
3032 if (g_switch_seen
&& g_switch_value
!= 0)
3033 as_bad (_("-G may not be used in position-independent code"));
3037 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3038 as_warn (_("Could not set architecture and machine"));
3040 op_hash
= hash_new ();
3042 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3043 for (i
= 0; i
< NUMOPCODES
;)
3045 const char *name
= mips_opcodes
[i
].name
;
3047 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3050 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3051 mips_opcodes
[i
].name
, retval
);
3052 /* Probably a memory allocation problem? Give up now. */
3053 as_fatal (_("Broken assembler. No assembly attempted."));
3057 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3058 decode_mips_operand
, &mips_operands
[i
]))
3060 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3062 create_insn (&nop_insn
, mips_opcodes
+ i
);
3063 if (mips_fix_loongson2f_nop
)
3064 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3065 nop_insn
.fixed_p
= 1;
3069 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3072 mips16_op_hash
= hash_new ();
3073 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3074 bfd_mips16_num_opcodes
);
3077 while (i
< bfd_mips16_num_opcodes
)
3079 const char *name
= mips16_opcodes
[i
].name
;
3081 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3083 as_fatal (_("internal: can't hash `%s': %s"),
3084 mips16_opcodes
[i
].name
, retval
);
3087 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3089 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3091 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3092 mips16_nop_insn
.fixed_p
= 1;
3096 while (i
< bfd_mips16_num_opcodes
3097 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3100 micromips_op_hash
= hash_new ();
3101 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3102 bfd_micromips_num_opcodes
);
3105 while (i
< bfd_micromips_num_opcodes
)
3107 const char *name
= micromips_opcodes
[i
].name
;
3109 retval
= hash_insert (micromips_op_hash
, name
,
3110 (void *) µmips_opcodes
[i
]);
3112 as_fatal (_("internal: can't hash `%s': %s"),
3113 micromips_opcodes
[i
].name
, retval
);
3116 struct mips_cl_insn
*micromips_nop_insn
;
3118 if (!validate_micromips_insn (µmips_opcodes
[i
],
3119 µmips_operands
[i
]))
3122 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3124 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3125 micromips_nop_insn
= µmips_nop16_insn
;
3126 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3127 micromips_nop_insn
= µmips_nop32_insn
;
3131 if (micromips_nop_insn
->insn_mo
== NULL
3132 && strcmp (name
, "nop") == 0)
3134 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3135 micromips_nop_insn
->fixed_p
= 1;
3139 while (++i
< bfd_micromips_num_opcodes
3140 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3144 as_fatal (_("Broken assembler. No assembly attempted."));
3146 /* We add all the general register names to the symbol table. This
3147 helps us detect invalid uses of them. */
3148 for (i
= 0; reg_names
[i
].name
; i
++)
3149 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3150 reg_names
[i
].num
, /* & RNUM_MASK, */
3151 &zero_address_frag
));
3153 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3154 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3155 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3156 &zero_address_frag
));
3158 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3159 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3160 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3161 &zero_address_frag
));
3163 obstack_init (&mips_operand_tokens
);
3165 mips_no_prev_insn ();
3168 mips_cprmask
[0] = 0;
3169 mips_cprmask
[1] = 0;
3170 mips_cprmask
[2] = 0;
3171 mips_cprmask
[3] = 0;
3173 /* set the default alignment for the text section (2**2) */
3174 record_alignment (text_section
, 2);
3176 bfd_set_gp_size (stdoutput
, g_switch_value
);
3178 /* On a native system other than VxWorks, sections must be aligned
3179 to 16 byte boundaries. When configured for an embedded ELF
3180 target, we don't bother. */
3181 if (strncmp (TARGET_OS
, "elf", 3) != 0
3182 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3184 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3185 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3186 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3189 /* Create a .reginfo section for register masks and a .mdebug
3190 section for debugging information. */
3198 subseg
= now_subseg
;
3200 /* The ABI says this section should be loaded so that the
3201 running program can access it. However, we don't load it
3202 if we are configured for an embedded target */
3203 flags
= SEC_READONLY
| SEC_DATA
;
3204 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3205 flags
|= SEC_ALLOC
| SEC_LOAD
;
3207 if (mips_abi
!= N64_ABI
)
3209 sec
= subseg_new (".reginfo", (subsegT
) 0);
3211 bfd_set_section_flags (stdoutput
, sec
, flags
);
3212 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3214 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3218 /* The 64-bit ABI uses a .MIPS.options section rather than
3219 .reginfo section. */
3220 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3221 bfd_set_section_flags (stdoutput
, sec
, flags
);
3222 bfd_set_section_alignment (stdoutput
, sec
, 3);
3224 /* Set up the option header. */
3226 Elf_Internal_Options opthdr
;
3229 opthdr
.kind
= ODK_REGINFO
;
3230 opthdr
.size
= (sizeof (Elf_External_Options
)
3231 + sizeof (Elf64_External_RegInfo
));
3234 f
= frag_more (sizeof (Elf_External_Options
));
3235 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3236 (Elf_External_Options
*) f
);
3238 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3242 if (ECOFF_DEBUGGING
)
3244 sec
= subseg_new (".mdebug", (subsegT
) 0);
3245 (void) bfd_set_section_flags (stdoutput
, sec
,
3246 SEC_HAS_CONTENTS
| SEC_READONLY
);
3247 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3249 else if (mips_flag_pdr
)
3251 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3252 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3253 SEC_READONLY
| SEC_RELOC
3255 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3258 subseg_set (seg
, subseg
);
3261 if (! ECOFF_DEBUGGING
)
3264 if (mips_fix_vr4120
)
3265 init_vr4120_conflicts ();
3271 mips_emit_delays ();
3272 if (! ECOFF_DEBUGGING
)
3277 md_assemble (char *str
)
3279 struct mips_cl_insn insn
;
3280 bfd_reloc_code_real_type unused_reloc
[3]
3281 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3283 imm_expr
.X_op
= O_absent
;
3284 imm2_expr
.X_op
= O_absent
;
3285 offset_expr
.X_op
= O_absent
;
3286 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3287 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3288 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3290 mips_mark_labels ();
3291 mips_assembling_insn
= TRUE
;
3293 if (mips_opts
.mips16
)
3294 mips16_ip (str
, &insn
);
3297 mips_ip (str
, &insn
);
3298 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3299 str
, insn
.insn_opcode
));
3303 as_bad ("%s `%s'", insn_error
, str
);
3304 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3307 if (mips_opts
.mips16
)
3308 mips16_macro (&insn
);
3315 if (offset_expr
.X_op
!= O_absent
)
3316 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3318 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3321 mips_assembling_insn
= FALSE
;
3324 /* Convenience functions for abstracting away the differences between
3325 MIPS16 and non-MIPS16 relocations. */
3327 static inline bfd_boolean
3328 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3332 case BFD_RELOC_MIPS16_JMP
:
3333 case BFD_RELOC_MIPS16_GPREL
:
3334 case BFD_RELOC_MIPS16_GOT16
:
3335 case BFD_RELOC_MIPS16_CALL16
:
3336 case BFD_RELOC_MIPS16_HI16_S
:
3337 case BFD_RELOC_MIPS16_HI16
:
3338 case BFD_RELOC_MIPS16_LO16
:
3346 static inline bfd_boolean
3347 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3351 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3352 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3353 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3354 case BFD_RELOC_MICROMIPS_GPREL16
:
3355 case BFD_RELOC_MICROMIPS_JMP
:
3356 case BFD_RELOC_MICROMIPS_HI16
:
3357 case BFD_RELOC_MICROMIPS_HI16_S
:
3358 case BFD_RELOC_MICROMIPS_LO16
:
3359 case BFD_RELOC_MICROMIPS_LITERAL
:
3360 case BFD_RELOC_MICROMIPS_GOT16
:
3361 case BFD_RELOC_MICROMIPS_CALL16
:
3362 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3363 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3364 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3365 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3366 case BFD_RELOC_MICROMIPS_SUB
:
3367 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3368 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3369 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3370 case BFD_RELOC_MICROMIPS_HIGHEST
:
3371 case BFD_RELOC_MICROMIPS_HIGHER
:
3372 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3373 case BFD_RELOC_MICROMIPS_JALR
:
3381 static inline bfd_boolean
3382 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3384 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3387 static inline bfd_boolean
3388 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3390 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3391 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3394 static inline bfd_boolean
3395 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3397 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3398 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3401 static inline bfd_boolean
3402 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3404 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3405 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3408 static inline bfd_boolean
3409 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3411 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3414 static inline bfd_boolean
3415 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3417 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3418 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3421 /* Return true if RELOC is a PC-relative relocation that does not have
3422 full address range. */
3424 static inline bfd_boolean
3425 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3429 case BFD_RELOC_16_PCREL_S2
:
3430 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3431 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3432 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3435 case BFD_RELOC_32_PCREL
:
3436 return HAVE_64BIT_ADDRESSES
;
3443 /* Return true if the given relocation might need a matching %lo().
3444 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3445 need a matching %lo() when applied to local symbols. */
3447 static inline bfd_boolean
3448 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3450 return (HAVE_IN_PLACE_ADDENDS
3451 && (hi16_reloc_p (reloc
)
3452 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3453 all GOT16 relocations evaluate to "G". */
3454 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3457 /* Return the type of %lo() reloc needed by RELOC, given that
3458 reloc_needs_lo_p. */
3460 static inline bfd_reloc_code_real_type
3461 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3463 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3464 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3468 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3471 static inline bfd_boolean
3472 fixup_has_matching_lo_p (fixS
*fixp
)
3474 return (fixp
->fx_next
!= NULL
3475 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3476 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3477 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3480 /* Move all labels in LABELS to the current insertion point. TEXT_P
3481 says whether the labels refer to text or data. */
3484 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3486 struct insn_label_list
*l
;
3489 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3491 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3492 symbol_set_frag (l
->label
, frag_now
);
3493 val
= (valueT
) frag_now_fix ();
3494 /* MIPS16/microMIPS text labels are stored as odd. */
3495 if (text_p
&& HAVE_CODE_COMPRESSION
)
3497 S_SET_VALUE (l
->label
, val
);
3501 /* Move all labels in insn_labels to the current insertion point
3502 and treat them as text labels. */
3505 mips_move_text_labels (void)
3507 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3511 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3513 bfd_boolean linkonce
= FALSE
;
3514 segT symseg
= S_GET_SEGMENT (sym
);
3516 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3518 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3520 /* The GNU toolchain uses an extension for ELF: a section
3521 beginning with the magic string .gnu.linkonce is a
3522 linkonce section. */
3523 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3524 sizeof ".gnu.linkonce" - 1) == 0)
3530 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3531 linker to handle them specially, such as generating jalx instructions
3532 when needed. We also make them odd for the duration of the assembly,
3533 in order to generate the right sort of code. We will make them even
3534 in the adjust_symtab routine, while leaving them marked. This is
3535 convenient for the debugger and the disassembler. The linker knows
3536 to make them odd again. */
3539 mips_compressed_mark_label (symbolS
*label
)
3541 gas_assert (HAVE_CODE_COMPRESSION
);
3543 if (mips_opts
.mips16
)
3544 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3546 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3547 if ((S_GET_VALUE (label
) & 1) == 0
3548 /* Don't adjust the address if the label is global or weak, or
3549 in a link-once section, since we'll be emitting symbol reloc
3550 references to it which will be patched up by the linker, and
3551 the final value of the symbol may or may not be MIPS16/microMIPS. */
3552 && !S_IS_WEAK (label
)
3553 && !S_IS_EXTERNAL (label
)
3554 && !s_is_linkonce (label
, now_seg
))
3555 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3558 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3561 mips_compressed_mark_labels (void)
3563 struct insn_label_list
*l
;
3565 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3566 mips_compressed_mark_label (l
->label
);
3569 /* End the current frag. Make it a variant frag and record the
3573 relax_close_frag (void)
3575 mips_macro_warning
.first_frag
= frag_now
;
3576 frag_var (rs_machine_dependent
, 0, 0,
3577 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3578 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3580 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3581 mips_relax
.first_fixup
= 0;
3584 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3585 See the comment above RELAX_ENCODE for more details. */
3588 relax_start (symbolS
*symbol
)
3590 gas_assert (mips_relax
.sequence
== 0);
3591 mips_relax
.sequence
= 1;
3592 mips_relax
.symbol
= symbol
;
3595 /* Start generating the second version of a relaxable sequence.
3596 See the comment above RELAX_ENCODE for more details. */
3601 gas_assert (mips_relax
.sequence
== 1);
3602 mips_relax
.sequence
= 2;
3605 /* End the current relaxable sequence. */
3610 gas_assert (mips_relax
.sequence
== 2);
3611 relax_close_frag ();
3612 mips_relax
.sequence
= 0;
3615 /* Return true if IP is a delayed branch or jump. */
3617 static inline bfd_boolean
3618 delayed_branch_p (const struct mips_cl_insn
*ip
)
3620 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3621 | INSN_COND_BRANCH_DELAY
3622 | INSN_COND_BRANCH_LIKELY
)) != 0;
3625 /* Return true if IP is a compact branch or jump. */
3627 static inline bfd_boolean
3628 compact_branch_p (const struct mips_cl_insn
*ip
)
3630 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3631 | INSN2_COND_BRANCH
)) != 0;
3634 /* Return true if IP is an unconditional branch or jump. */
3636 static inline bfd_boolean
3637 uncond_branch_p (const struct mips_cl_insn
*ip
)
3639 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3640 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3643 /* Return true if IP is a branch-likely instruction. */
3645 static inline bfd_boolean
3646 branch_likely_p (const struct mips_cl_insn
*ip
)
3648 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3651 /* Return the type of nop that should be used to fill the delay slot
3652 of delayed branch IP. */
3654 static struct mips_cl_insn
*
3655 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3657 if (mips_opts
.micromips
3658 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3659 return µmips_nop32_insn
;
3663 /* Return a mask that has bit N set if OPCODE reads the register(s)
3667 insn_read_mask (const struct mips_opcode
*opcode
)
3669 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3672 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3676 insn_write_mask (const struct mips_opcode
*opcode
)
3678 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3681 /* Return a mask of the registers specified by operand OPERAND of INSN.
3682 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3686 operand_reg_mask (const struct mips_cl_insn
*insn
,
3687 const struct mips_operand
*operand
,
3688 unsigned int type_mask
)
3690 unsigned int uval
, vsel
;
3692 switch (operand
->type
)
3699 case OP_ADDIUSP_INT
:
3700 case OP_ENTRY_EXIT_LIST
:
3701 case OP_REPEAT_DEST_REG
:
3702 case OP_REPEAT_PREV_REG
:
3708 const struct mips_reg_operand
*reg_op
;
3710 reg_op
= (const struct mips_reg_operand
*) operand
;
3711 if (!(type_mask
& (1 << reg_op
->reg_type
)))
3713 uval
= insn_extract_operand (insn
, operand
);
3714 return 1 << mips_decode_reg_operand (reg_op
, uval
);
3719 const struct mips_reg_pair_operand
*pair_op
;
3721 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
3722 if (!(type_mask
& (1 << pair_op
->reg_type
)))
3724 uval
= insn_extract_operand (insn
, operand
);
3725 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
3728 case OP_CLO_CLZ_DEST
:
3729 if (!(type_mask
& (1 << OP_REG_GP
)))
3731 uval
= insn_extract_operand (insn
, operand
);
3732 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
3734 case OP_LWM_SWM_LIST
:
3737 case OP_SAVE_RESTORE_LIST
:
3740 case OP_MDMX_IMM_REG
:
3741 if (!(type_mask
& (1 << OP_REG_VEC
)))
3743 uval
= insn_extract_operand (insn
, operand
);
3745 if ((vsel
& 0x18) == 0x18)
3747 return 1 << (uval
& 31);
3752 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
3753 where bit N of OPNO_MASK is set if operand N should be included.
3754 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3758 insn_reg_mask (const struct mips_cl_insn
*insn
,
3759 unsigned int type_mask
, unsigned int opno_mask
)
3761 unsigned int opno
, reg_mask
;
3765 while (opno_mask
!= 0)
3768 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
3775 /* Return the mask of core registers that IP reads. */
3778 gpr_read_mask (const struct mips_cl_insn
*ip
)
3780 unsigned long pinfo
, pinfo2
;
3783 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
3784 pinfo
= ip
->insn_mo
->pinfo
;
3785 pinfo2
= ip
->insn_mo
->pinfo2
;
3786 if (pinfo
& INSN_UDI
)
3788 /* UDI instructions have traditionally been assumed to read RS
3790 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3791 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3793 if (pinfo
& INSN_READ_GPR_24
)
3795 if (pinfo2
& INSN2_READ_GPR_16
)
3797 if (pinfo2
& INSN2_READ_SP
)
3799 if (pinfo2
& INSN2_READ_GPR_31
)
3801 /* Don't include register 0. */
3805 /* Return the mask of core registers that IP writes. */
3808 gpr_write_mask (const struct mips_cl_insn
*ip
)
3810 unsigned long pinfo
, pinfo2
;
3813 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
3814 pinfo
= ip
->insn_mo
->pinfo
;
3815 pinfo2
= ip
->insn_mo
->pinfo2
;
3816 if (pinfo
& INSN_WRITE_GPR_24
)
3818 if (pinfo
& INSN_WRITE_GPR_31
)
3820 if (pinfo
& INSN_UDI
)
3821 /* UDI instructions have traditionally been assumed to write to RD. */
3822 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3823 if (pinfo2
& INSN2_WRITE_SP
)
3825 /* Don't include register 0. */
3829 /* Return the mask of floating-point registers that IP reads. */
3832 fpr_read_mask (const struct mips_cl_insn
*ip
)
3834 unsigned long pinfo
;
3837 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
3838 insn_read_mask (ip
->insn_mo
));
3839 pinfo
= ip
->insn_mo
->pinfo
;
3840 /* Conservatively treat all operands to an FP_D instruction are doubles.
3841 (This is overly pessimistic for things like cvt.d.s.) */
3842 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3847 /* Return the mask of floating-point registers that IP writes. */
3850 fpr_write_mask (const struct mips_cl_insn
*ip
)
3852 unsigned long pinfo
;
3855 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
3856 insn_write_mask (ip
->insn_mo
));
3857 pinfo
= ip
->insn_mo
->pinfo
;
3858 /* Conservatively treat all operands to an FP_D instruction are doubles.
3859 (This is overly pessimistic for things like cvt.s.d.) */
3860 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3865 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3866 Check whether that is allowed. */
3869 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
3871 const char *s
= insn
->name
;
3873 if (insn
->pinfo
== INSN_MACRO
)
3874 /* Let a macro pass, we'll catch it later when it is expanded. */
3877 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
3879 /* Allow odd registers for single-precision ops. */
3880 switch (insn
->pinfo
& (FP_S
| FP_D
))
3891 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3892 s
= strchr (insn
->name
, '.');
3893 if (s
!= NULL
&& opnum
== 2)
3894 s
= strchr (s
+ 1, '.');
3895 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
3898 /* Single-precision coprocessor loads and moves are OK too. */
3899 if ((insn
->pinfo
& FP_S
)
3900 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
3901 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
3907 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3908 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3909 this operand is normally printed in hex or decimal. */
3912 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
3913 offsetT val
, int min_val
, int max_val
,
3914 bfd_boolean print_hex
)
3916 if (print_hex
&& val
>= 0)
3917 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3919 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3921 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3923 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3925 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3927 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
3930 /* Report an invalid combination of position and size operands for a bitfield
3931 operation. POS and SIZE are the values that were given. */
3934 report_bad_field (offsetT pos
, offsetT size
)
3936 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3937 (unsigned long) pos
, (unsigned long) size
);
3940 /* Information about an instruction argument that we're trying to match. */
3941 struct mips_arg_info
3943 /* The instruction so far. */
3944 struct mips_cl_insn
*insn
;
3946 /* The first unconsumed operand token. */
3947 struct mips_operand_token
*token
;
3949 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3952 /* The 1-based argument number, for error reporting. This does not
3953 count elided optional registers, etc.. */
3956 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3957 unsigned int last_regno
;
3959 /* If the first operand was an OP_REG, this is the register that it
3960 specified, otherwise it is ILLEGAL_REG. */
3961 unsigned int dest_regno
;
3963 /* The value of the last OP_INT operand. Only used for OP_MSB,
3964 where it gives the lsb position. */
3965 unsigned int last_op_int
;
3967 /* If true, match routines should silently reject invalid arguments.
3968 If false, match routines can accept invalid arguments as long as
3969 they report an appropriate error. They still have the option of
3970 silently rejecting arguments, in which case a generic "Invalid operands"
3971 style of error will be used instead. */
3972 bfd_boolean soft_match
;
3974 /* If true, the OP_INT match routine should treat plain symbolic operands
3975 as if a relocation operator like %lo(...) had been used. This is only
3976 ever true if the operand can be relocated. */
3977 bfd_boolean allow_nonconst
;
3979 /* When true, the OP_INT match routine should allow unsigned N-bit
3980 arguments to be used where a signed N-bit operand is expected. */
3981 bfd_boolean lax_max
;
3983 /* True if a reference to the current AT register was seen. */
3984 bfd_boolean seen_at
;
3987 /* Try to match an OT_CHAR token for character CH. Consume the token
3988 and return true on success, otherwise return false. */
3991 match_char (struct mips_arg_info
*arg
, char ch
)
3993 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4003 /* Try to get an expression from the next tokens in ARG. Consume the
4004 tokens and return true on success, storing the expression value in
4005 VALUE and relocation types in R. */
4008 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4009 bfd_reloc_code_real_type
*r
)
4011 if (arg
->token
->type
== OT_INTEGER
)
4013 *value
= arg
->token
->u
.integer
.value
;
4014 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4019 /* Error-reporting is more consistent if we treat registers as O_register
4020 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4021 then handled in the same way. */
4022 if (arg
->token
->type
== OT_REG
)
4024 value
->X_add_number
= arg
->token
->u
.regno
;
4027 else if (arg
->token
[0].type
== OT_CHAR
4028 && arg
->token
[0].u
.ch
== '('
4029 && arg
->token
[1].type
== OT_REG
4030 && arg
->token
[2].type
== OT_CHAR
4031 && arg
->token
[2].u
.ch
== ')')
4033 value
->X_add_number
= arg
->token
[1].u
.regno
;
4039 value
->X_op
= O_register
;
4040 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4044 /* Try to get a constant expression from the next tokens in ARG. Consume
4045 the tokens and return return true on success, storing the constant value
4046 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4050 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
, offsetT fallback
)
4053 bfd_reloc_code_real_type r
[3];
4055 if (!match_expression (arg
, &ex
, r
))
4058 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4059 *value
= ex
.X_add_number
;
4062 if (arg
->soft_match
)
4064 as_bad (_("Operand %d of `%s' must be constant"),
4065 arg
->argnum
, arg
->insn
->insn_mo
->name
);
4071 /* Return the RTYPE_* flags for a register operand of type TYPE that
4072 appears in instruction OPCODE. */
4075 convert_reg_type (const struct mips_opcode
*opcode
,
4076 enum mips_reg_operand_type type
)
4081 return RTYPE_NUM
| RTYPE_GP
;
4084 /* Allow vector register names for MDMX if the instruction is a 64-bit
4085 FPR load, store or move (including moves to and from GPRs). */
4086 if ((mips_opts
.ase
& ASE_MDMX
)
4087 && (opcode
->pinfo
& FP_D
)
4088 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4089 | INSN_COPROC_MEMORY_DELAY
4090 | INSN_LOAD_COPROC_DELAY
4091 | INSN_LOAD_MEMORY_DELAY
4092 | INSN_STORE_MEMORY
)))
4093 return RTYPE_FPU
| RTYPE_VEC
;
4097 if (opcode
->pinfo
& (FP_D
| FP_S
))
4098 return RTYPE_CCC
| RTYPE_FCC
;
4102 if (opcode
->membership
& INSN_5400
)
4104 return RTYPE_FPU
| RTYPE_VEC
;
4110 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4111 return RTYPE_NUM
| RTYPE_CP0
;
4120 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4123 check_regno (struct mips_arg_info
*arg
,
4124 enum mips_reg_operand_type type
, unsigned int regno
)
4126 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4127 arg
->seen_at
= TRUE
;
4129 if (type
== OP_REG_FP
4132 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4133 as_warn (_("Float register should be even, was %d"), regno
);
4135 if (type
== OP_REG_CCC
)
4140 name
= arg
->insn
->insn_mo
->name
;
4141 length
= strlen (name
);
4142 if ((regno
& 1) != 0
4143 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4144 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4145 as_warn (_("Condition code register should be even for %s, was %d"),
4148 if ((regno
& 3) != 0
4149 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4150 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4155 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4156 a register of type TYPE. Return true on success, storing the register
4157 number in *REGNO and warning about any dubious uses. */
4160 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4161 unsigned int symval
, unsigned int *regno
)
4163 if (type
== OP_REG_VEC
)
4164 symval
= mips_prefer_vec_regno (symval
);
4165 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4168 *regno
= symval
& RNUM_MASK
;
4169 check_regno (arg
, type
, *regno
);
4173 /* Try to interpret the next token in ARG as a register of type TYPE.
4174 Consume the token and return true on success, storing the register
4175 number in *REGNO. Return false on failure. */
4178 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4179 unsigned int *regno
)
4181 if (arg
->token
->type
== OT_REG
4182 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4190 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4191 Consume the token and return true on success, storing the register numbers
4192 in *REGNO1 and *REGNO2. Return false on failure. */
4195 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4196 unsigned int *regno1
, unsigned int *regno2
)
4198 if (match_reg (arg
, type
, regno1
))
4203 if (arg
->token
->type
== OT_REG_RANGE
4204 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4205 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4206 && *regno1
<= *regno2
)
4214 /* OP_INT matcher. */
4217 match_int_operand (struct mips_arg_info
*arg
,
4218 const struct mips_operand
*operand_base
)
4220 const struct mips_int_operand
*operand
;
4221 unsigned int uval
, mask
;
4222 int min_val
, max_val
, factor
;
4224 bfd_boolean print_hex
;
4226 operand
= (const struct mips_int_operand
*) operand_base
;
4227 factor
= 1 << operand
->shift
;
4228 mask
= (1 << operand_base
->size
) - 1;
4229 max_val
= (operand
->max_val
+ operand
->bias
) << operand
->shift
;
4230 min_val
= max_val
- (mask
<< operand
->shift
);
4232 max_val
= mask
<< operand
->shift
;
4234 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4235 /* Assume we have an elided offset. The later match will fail
4236 if this turns out to be wrong. */
4238 else if (operand_base
->lsb
== 0
4239 && operand_base
->size
== 16
4240 && operand
->shift
== 0
4241 && operand
->bias
== 0
4242 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4244 /* The operand can be relocated. */
4245 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4248 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4249 /* Relocation operators were used. Accept the arguent and
4250 leave the relocation value in offset_expr and offset_relocs
4251 for the caller to process. */
4254 if (offset_expr
.X_op
!= O_constant
)
4256 /* If non-constant operands are allowed then leave them for
4257 the caller to process, otherwise fail the match. */
4258 if (!arg
->allow_nonconst
)
4260 offset_reloc
[0] = BFD_RELOC_LO16
;
4264 /* Clear the global state; we're going to install the operand
4266 sval
= offset_expr
.X_add_number
;
4267 offset_expr
.X_op
= O_absent
;
4271 if (!match_const_int (arg
, &sval
, min_val
))
4275 arg
->last_op_int
= sval
;
4277 /* Check the range. If there's a problem, record the lowest acceptable
4278 value in arg->last_op_int in order to prevent an unhelpful error
4281 Bit counts have traditionally been printed in hex by the disassembler
4282 but printed as decimal in error messages. Only resort to hex if
4283 the operand is bigger than 6 bits. */
4284 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
4285 if (sval
< min_val
|| sval
> max_val
)
4287 if (arg
->soft_match
)
4289 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
4291 arg
->last_op_int
= min_val
;
4293 else if (sval
% factor
)
4295 if (arg
->soft_match
)
4297 as_bad (print_hex
&& sval
>= 0
4298 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4299 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4300 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
4301 (unsigned long) sval
);
4302 arg
->last_op_int
= min_val
;
4305 uval
= (unsigned int) sval
>> operand
->shift
;
4306 uval
-= operand
->bias
;
4308 /* Handle -mfix-cn63xxp1. */
4310 && mips_fix_cn63xxp1
4311 && !mips_opts
.micromips
4312 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4327 /* The rest must be changed to 28. */
4332 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4336 /* OP_MAPPED_INT matcher. */
4339 match_mapped_int_operand (struct mips_arg_info
*arg
,
4340 const struct mips_operand
*operand_base
)
4342 const struct mips_mapped_int_operand
*operand
;
4343 unsigned int uval
, num_vals
;
4346 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4347 if (!match_const_int (arg
, &sval
, operand
->int_map
[0]))
4350 num_vals
= 1 << operand_base
->size
;
4351 for (uval
= 0; uval
< num_vals
; uval
++)
4352 if (operand
->int_map
[uval
] == sval
)
4354 if (uval
== num_vals
)
4357 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4361 /* OP_MSB matcher. */
4364 match_msb_operand (struct mips_arg_info
*arg
,
4365 const struct mips_operand
*operand_base
)
4367 const struct mips_msb_operand
*operand
;
4368 int min_val
, max_val
, max_high
;
4369 offsetT size
, sval
, high
;
4371 operand
= (const struct mips_msb_operand
*) operand_base
;
4372 min_val
= operand
->bias
;
4373 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4374 max_high
= operand
->opsize
;
4376 if (!match_const_int (arg
, &size
, 1))
4379 high
= size
+ arg
->last_op_int
;
4380 sval
= operand
->add_lsb
? high
: size
;
4382 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4384 if (arg
->soft_match
)
4386 report_bad_field (arg
->last_op_int
, size
);
4389 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4393 /* OP_REG matcher. */
4396 match_reg_operand (struct mips_arg_info
*arg
,
4397 const struct mips_operand
*operand_base
)
4399 const struct mips_reg_operand
*operand
;
4400 unsigned int regno
, uval
, num_vals
;
4402 operand
= (const struct mips_reg_operand
*) operand_base
;
4403 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4406 if (operand
->reg_map
)
4408 num_vals
= 1 << operand
->root
.size
;
4409 for (uval
= 0; uval
< num_vals
; uval
++)
4410 if (operand
->reg_map
[uval
] == regno
)
4412 if (num_vals
== uval
)
4418 arg
->last_regno
= regno
;
4419 if (arg
->opnum
== 1)
4420 arg
->dest_regno
= regno
;
4421 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4425 /* OP_REG_PAIR matcher. */
4428 match_reg_pair_operand (struct mips_arg_info
*arg
,
4429 const struct mips_operand
*operand_base
)
4431 const struct mips_reg_pair_operand
*operand
;
4432 unsigned int regno1
, regno2
, uval
, num_vals
;
4434 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4435 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4436 || !match_char (arg
, ',')
4437 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4440 num_vals
= 1 << operand_base
->size
;
4441 for (uval
= 0; uval
< num_vals
; uval
++)
4442 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4444 if (uval
== num_vals
)
4447 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4451 /* OP_PCREL matcher. The caller chooses the relocation type. */
4454 match_pcrel_operand (struct mips_arg_info
*arg
)
4456 bfd_reloc_code_real_type r
[3];
4458 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4461 /* OP_PERF_REG matcher. */
4464 match_perf_reg_operand (struct mips_arg_info
*arg
,
4465 const struct mips_operand
*operand
)
4469 if (!match_const_int (arg
, &sval
, 0))
4474 || (mips_opts
.arch
== CPU_R5900
4475 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4476 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4478 if (arg
->soft_match
)
4480 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4483 insn_insert_operand (arg
->insn
, operand
, sval
);
4487 /* OP_ADDIUSP matcher. */
4490 match_addiusp_operand (struct mips_arg_info
*arg
,
4491 const struct mips_operand
*operand
)
4496 if (!match_const_int (arg
, &sval
, -256))
4503 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4506 uval
= (unsigned int) sval
;
4507 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4508 insn_insert_operand (arg
->insn
, operand
, uval
);
4512 /* OP_CLO_CLZ_DEST matcher. */
4515 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4516 const struct mips_operand
*operand
)
4520 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4523 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4527 /* OP_LWM_SWM_LIST matcher. */
4530 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4531 const struct mips_operand
*operand
)
4533 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4534 struct mips_arg_info reset
;
4537 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4541 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4546 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4549 while (match_char (arg
, ',')
4550 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4553 if (operand
->size
== 2)
4555 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4561 and any permutations of these. */
4562 if ((reglist
& 0xfff1ffff) != 0x80010000)
4565 sregs
= (reglist
>> 17) & 7;
4570 /* The list must include at least one of ra and s0-sN,
4571 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4572 which are $23 and $30 respectively.) E.g.:
4580 and any permutations of these. */
4581 if ((reglist
& 0x3f00ffff) != 0)
4584 ra
= (reglist
>> 27) & 0x10;
4585 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4588 if ((sregs
& -sregs
) != sregs
)
4591 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4595 /* OP_ENTRY_EXIT_LIST matcher. */
4598 match_entry_exit_operand (struct mips_arg_info
*arg
,
4599 const struct mips_operand
*operand
)
4602 bfd_boolean is_exit
;
4604 /* The format is the same for both ENTRY and EXIT, but the constraints
4606 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4607 mask
= (is_exit
? 7 << 3 : 0);
4610 unsigned int regno1
, regno2
;
4611 bfd_boolean is_freg
;
4613 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4615 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4620 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4623 mask
|= (5 + regno2
) << 3;
4625 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4626 mask
|= (regno2
- 3) << 3;
4627 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4628 mask
|= (regno2
- 15) << 1;
4629 else if (regno1
== RA
&& regno2
== RA
)
4634 while (match_char (arg
, ','));
4636 insn_insert_operand (arg
->insn
, operand
, mask
);
4640 /* OP_SAVE_RESTORE_LIST matcher. */
4643 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4645 unsigned int opcode
, args
, statics
, sregs
;
4646 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4651 opcode
= arg
->insn
->insn_opcode
;
4653 num_frame_sizes
= 0;
4659 unsigned int regno1
, regno2
;
4661 if (arg
->token
->type
== OT_INTEGER
)
4663 /* Handle the frame size. */
4664 if (!match_const_int (arg
, &frame_size
, 0))
4666 num_frame_sizes
+= 1;
4670 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4673 while (regno1
<= regno2
)
4675 if (regno1
>= 4 && regno1
<= 7)
4677 if (num_frame_sizes
== 0)
4679 args
|= 1 << (regno1
- 4);
4681 /* statics $a0-$a3 */
4682 statics
|= 1 << (regno1
- 4);
4684 else if (regno1
>= 16 && regno1
<= 23)
4686 sregs
|= 1 << (regno1
- 16);
4687 else if (regno1
== 30)
4690 else if (regno1
== 31)
4691 /* Add $ra to insn. */
4701 while (match_char (arg
, ','));
4703 /* Encode args/statics combination. */
4706 else if (args
== 0xf)
4707 /* All $a0-$a3 are args. */
4708 opcode
|= MIPS16_ALL_ARGS
<< 16;
4709 else if (statics
== 0xf)
4710 /* All $a0-$a3 are statics. */
4711 opcode
|= MIPS16_ALL_STATICS
<< 16;
4714 /* Count arg registers. */
4724 /* Count static registers. */
4726 while (statics
& 0x8)
4728 statics
= (statics
<< 1) & 0xf;
4734 /* Encode args/statics. */
4735 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
4738 /* Encode $s0/$s1. */
4739 if (sregs
& (1 << 0)) /* $s0 */
4741 if (sregs
& (1 << 1)) /* $s1 */
4745 /* Encode $s2-$s8. */
4754 opcode
|= num_sregs
<< 24;
4756 /* Encode frame size. */
4757 if (num_frame_sizes
== 0)
4758 error
= _("Missing frame size");
4759 else if (num_frame_sizes
> 1)
4760 error
= _("Frame size specified twice");
4761 else if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
4762 error
= _("Invalid frame size");
4763 else if (frame_size
!= 128 || (opcode
>> 16) != 0)
4766 opcode
|= (((frame_size
& 0xf0) << 16)
4767 | (frame_size
& 0x0f));
4772 if (arg
->soft_match
)
4774 as_bad ("%s", error
);
4777 /* Finally build the instruction. */
4778 if ((opcode
>> 16) != 0 || frame_size
== 0)
4779 opcode
|= MIPS16_EXTEND
;
4780 arg
->insn
->insn_opcode
= opcode
;
4784 /* OP_MDMX_IMM_REG matcher. */
4787 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
4788 const struct mips_operand
*operand
)
4790 unsigned int regno
, uval
;
4792 const struct mips_opcode
*opcode
;
4794 /* The mips_opcode records whether this is an octobyte or quadhalf
4795 instruction. Start out with that bit in place. */
4796 opcode
= arg
->insn
->insn_mo
;
4797 uval
= mips_extract_operand (operand
, opcode
->match
);
4798 is_qh
= (uval
!= 0);
4800 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
4802 if ((opcode
->membership
& INSN_5400
)
4803 && strcmp (opcode
->name
, "rzu.ob") == 0)
4805 if (arg
->soft_match
)
4807 as_bad (_("Operand %d of `%s' must be an immediate"),
4808 arg
->argnum
, opcode
->name
);
4811 /* Check whether this is a vector register or a broadcast of
4812 a single element. */
4813 if (arg
->token
->type
== OT_REG_ELEMENT
)
4815 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
4818 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
4820 if (arg
->soft_match
)
4822 as_bad (_("Invalid element selector"));
4825 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
4829 /* A full vector. */
4830 if ((opcode
->membership
& INSN_5400
)
4831 && (strcmp (opcode
->name
, "sll.ob") == 0
4832 || strcmp (opcode
->name
, "srl.ob") == 0))
4834 if (arg
->soft_match
)
4836 as_bad (_("Operand %d of `%s' must be scalar"),
4837 arg
->argnum
, opcode
->name
);
4840 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
4843 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
4845 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
4854 if (!match_const_int (arg
, &sval
, 0))
4856 if (sval
< 0 || sval
> 31)
4858 if (arg
->soft_match
)
4860 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
4862 uval
|= (sval
& 31);
4864 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
4866 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
4868 insn_insert_operand (arg
->insn
, operand
, uval
);
4872 /* OP_PC matcher. */
4875 match_pc_operand (struct mips_arg_info
*arg
)
4877 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
4885 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4886 register that we need to match. */
4889 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
4893 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
4896 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4897 the length of the value in bytes (4 for float, 8 for double) and
4898 USING_GPRS says whether the destination is a GPR rather than an FPR.
4900 Return the constant in IMM and OFFSET as follows:
4902 - If the constant should be loaded via memory, set IMM to O_absent and
4903 OFFSET to the memory address.
4905 - Otherwise, if the constant should be loaded into two 32-bit registers,
4906 set IMM to the O_constant to load into the high register and OFFSET
4907 to the corresponding value for the low register.
4909 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4911 These constants only appear as the last operand in an instruction,
4912 and every instruction that accepts them in any variant accepts them
4913 in all variants. This means we don't have to worry about backing out
4914 any changes if the instruction does not match. We just match
4915 unconditionally and report an error if the constant is invalid. */
4918 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
4919 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
4924 const char *newname
;
4925 unsigned char *data
;
4927 /* Where the constant is placed is based on how the MIPS assembler
4930 length == 4 && using_gprs -- immediate value only
4931 length == 8 && using_gprs -- .rdata or immediate value
4932 length == 4 && !using_gprs -- .lit4 or immediate value
4933 length == 8 && !using_gprs -- .lit8 or immediate value
4935 The .lit4 and .lit8 sections are only used if permitted by the
4937 if (arg
->token
->type
!= OT_FLOAT
)
4940 gas_assert (arg
->token
->u
.flt
.length
== length
);
4941 data
= arg
->token
->u
.flt
.data
;
4944 /* Handle 32-bit constants for which an immediate value is best. */
4947 || g_switch_value
< 4
4948 || (data
[0] == 0 && data
[1] == 0)
4949 || (data
[2] == 0 && data
[3] == 0)))
4951 imm
->X_op
= O_constant
;
4952 if (!target_big_endian
)
4953 imm
->X_add_number
= bfd_getl32 (data
);
4955 imm
->X_add_number
= bfd_getb32 (data
);
4956 offset
->X_op
= O_absent
;
4960 /* Handle 64-bit constants for which an immediate value is best. */
4962 && !mips_disable_float_construction
4963 /* Constants can only be constructed in GPRs and copied
4964 to FPRs if the GPRs are at least as wide as the FPRs.
4965 Force the constant into memory if we are using 64-bit FPRs
4966 but the GPRs are only 32 bits wide. */
4967 /* ??? No longer true with the addition of MTHC1, but this
4968 is legacy code... */
4969 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
4970 && ((data
[0] == 0 && data
[1] == 0)
4971 || (data
[2] == 0 && data
[3] == 0))
4972 && ((data
[4] == 0 && data
[5] == 0)
4973 || (data
[6] == 0 && data
[7] == 0)))
4975 /* The value is simple enough to load with a couple of instructions.
4976 If using 32-bit registers, set IMM to the high order 32 bits and
4977 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4979 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
4981 imm
->X_op
= O_constant
;
4982 offset
->X_op
= O_constant
;
4983 if (!target_big_endian
)
4985 imm
->X_add_number
= bfd_getl32 (data
+ 4);
4986 offset
->X_add_number
= bfd_getl32 (data
);
4990 imm
->X_add_number
= bfd_getb32 (data
);
4991 offset
->X_add_number
= bfd_getb32 (data
+ 4);
4993 if (offset
->X_add_number
== 0)
4994 offset
->X_op
= O_absent
;
4998 imm
->X_op
= O_constant
;
4999 if (!target_big_endian
)
5000 imm
->X_add_number
= bfd_getl64 (data
);
5002 imm
->X_add_number
= bfd_getb64 (data
);
5003 offset
->X_op
= O_absent
;
5008 /* Switch to the right section. */
5010 subseg
= now_subseg
;
5013 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5018 if (using_gprs
|| g_switch_value
< 8)
5019 newname
= RDATA_SECTION_NAME
;
5024 new_seg
= subseg_new (newname
, (subsegT
) 0);
5025 bfd_set_section_flags (stdoutput
, new_seg
,
5026 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5027 frag_align (length
== 4 ? 2 : 3, 0, 0);
5028 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5029 record_alignment (new_seg
, 4);
5031 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5033 as_bad (_("Can't use floating point insn in this section"));
5035 /* Set the argument to the current address in the section. */
5036 imm
->X_op
= O_absent
;
5037 offset
->X_op
= O_symbol
;
5038 offset
->X_add_symbol
= symbol_temp_new_now ();
5039 offset
->X_add_number
= 0;
5041 /* Put the floating point number into the section. */
5042 p
= frag_more (length
);
5043 memcpy (p
, data
, length
);
5045 /* Switch back to the original section. */
5046 subseg_set (seg
, subseg
);
5050 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5051 of the argument text if the match is successful, otherwise return null. */
5054 match_operand (struct mips_arg_info
*arg
,
5055 const struct mips_operand
*operand
)
5057 switch (operand
->type
)
5060 return match_int_operand (arg
, operand
);
5063 return match_mapped_int_operand (arg
, operand
);
5066 return match_msb_operand (arg
, operand
);
5069 return match_reg_operand (arg
, operand
);
5072 return match_reg_pair_operand (arg
, operand
);
5075 return match_pcrel_operand (arg
);
5078 return match_perf_reg_operand (arg
, operand
);
5080 case OP_ADDIUSP_INT
:
5081 return match_addiusp_operand (arg
, operand
);
5083 case OP_CLO_CLZ_DEST
:
5084 return match_clo_clz_dest_operand (arg
, operand
);
5086 case OP_LWM_SWM_LIST
:
5087 return match_lwm_swm_list_operand (arg
, operand
);
5089 case OP_ENTRY_EXIT_LIST
:
5090 return match_entry_exit_operand (arg
, operand
);
5092 case OP_SAVE_RESTORE_LIST
:
5093 return match_save_restore_list_operand (arg
);
5095 case OP_MDMX_IMM_REG
:
5096 return match_mdmx_imm_reg_operand (arg
, operand
);
5098 case OP_REPEAT_DEST_REG
:
5099 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5101 case OP_REPEAT_PREV_REG
:
5102 return match_tied_reg_operand (arg
, arg
->last_regno
);
5105 return match_pc_operand (arg
);
5110 /* ARG is the state after successfully matching an instruction.
5111 Issue any queued-up warnings. */
5114 check_completed_insn (struct mips_arg_info
*arg
)
5119 as_warn (_("Used $at without \".set noat\""));
5121 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5125 /* Return true if modifying general-purpose register REG needs a delay. */
5128 reg_needs_delay (unsigned int reg
)
5130 unsigned long prev_pinfo
;
5132 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5133 if (!mips_opts
.noreorder
5134 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5135 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5136 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5142 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5143 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5144 by VR4120 errata. */
5147 classify_vr4120_insn (const char *name
)
5149 if (strncmp (name
, "macc", 4) == 0)
5150 return FIX_VR4120_MACC
;
5151 if (strncmp (name
, "dmacc", 5) == 0)
5152 return FIX_VR4120_DMACC
;
5153 if (strncmp (name
, "mult", 4) == 0)
5154 return FIX_VR4120_MULT
;
5155 if (strncmp (name
, "dmult", 5) == 0)
5156 return FIX_VR4120_DMULT
;
5157 if (strstr (name
, "div"))
5158 return FIX_VR4120_DIV
;
5159 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5160 return FIX_VR4120_MTHILO
;
5161 return NUM_FIX_VR4120_CLASSES
;
5164 #define INSN_ERET 0x42000018
5165 #define INSN_DERET 0x4200001f
5167 /* Return the number of instructions that must separate INSN1 and INSN2,
5168 where INSN1 is the earlier instruction. Return the worst-case value
5169 for any INSN2 if INSN2 is null. */
5172 insns_between (const struct mips_cl_insn
*insn1
,
5173 const struct mips_cl_insn
*insn2
)
5175 unsigned long pinfo1
, pinfo2
;
5178 /* If INFO2 is null, pessimistically assume that all flags are set for
5179 the second instruction. */
5180 pinfo1
= insn1
->insn_mo
->pinfo
;
5181 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5183 /* For most targets, write-after-read dependencies on the HI and LO
5184 registers must be separated by at least two instructions. */
5185 if (!hilo_interlocks
)
5187 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5189 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5193 /* If we're working around r7000 errata, there must be two instructions
5194 between an mfhi or mflo and any instruction that uses the result. */
5195 if (mips_7000_hilo_fix
5196 && !mips_opts
.micromips
5197 && MF_HILO_INSN (pinfo1
)
5198 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5201 /* If we're working around 24K errata, one instruction is required
5202 if an ERET or DERET is followed by a branch instruction. */
5203 if (mips_fix_24k
&& !mips_opts
.micromips
)
5205 if (insn1
->insn_opcode
== INSN_ERET
5206 || insn1
->insn_opcode
== INSN_DERET
)
5209 || insn2
->insn_opcode
== INSN_ERET
5210 || insn2
->insn_opcode
== INSN_DERET
5211 || delayed_branch_p (insn2
))
5216 /* If working around VR4120 errata, check for combinations that need
5217 a single intervening instruction. */
5218 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5220 unsigned int class1
, class2
;
5222 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5223 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5227 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5228 if (vr4120_conflicts
[class1
] & (1 << class2
))
5233 if (!HAVE_CODE_COMPRESSION
)
5235 /* Check for GPR or coprocessor load delays. All such delays
5236 are on the RT register. */
5237 /* Itbl support may require additional care here. */
5238 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5239 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5241 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5245 /* Check for generic coprocessor hazards.
5247 This case is not handled very well. There is no special
5248 knowledge of CP0 handling, and the coprocessors other than
5249 the floating point unit are not distinguished at all. */
5250 /* Itbl support may require additional care here. FIXME!
5251 Need to modify this to include knowledge about
5252 user specified delays! */
5253 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5254 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5256 /* Handle cases where INSN1 writes to a known general coprocessor
5257 register. There must be a one instruction delay before INSN2
5258 if INSN2 reads that register, otherwise no delay is needed. */
5259 mask
= fpr_write_mask (insn1
);
5262 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5267 /* Read-after-write dependencies on the control registers
5268 require a two-instruction gap. */
5269 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5270 && (pinfo2
& INSN_READ_COND_CODE
))
5273 /* We don't know exactly what INSN1 does. If INSN2 is
5274 also a coprocessor instruction, assume there must be
5275 a one instruction gap. */
5276 if (pinfo2
& INSN_COP
)
5281 /* Check for read-after-write dependencies on the coprocessor
5282 control registers in cases where INSN1 does not need a general
5283 coprocessor delay. This means that INSN1 is a floating point
5284 comparison instruction. */
5285 /* Itbl support may require additional care here. */
5286 else if (!cop_interlocks
5287 && (pinfo1
& INSN_WRITE_COND_CODE
)
5288 && (pinfo2
& INSN_READ_COND_CODE
))
5295 /* Return the number of nops that would be needed to work around the
5296 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5297 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5298 that are contained within the first IGNORE instructions of HIST. */
5301 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5302 const struct mips_cl_insn
*insn
)
5307 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5308 are not affected by the errata. */
5310 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5311 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5312 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5315 /* Search for the first MFLO or MFHI. */
5316 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5317 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5319 /* Extract the destination register. */
5320 mask
= gpr_write_mask (&hist
[i
]);
5322 /* No nops are needed if INSN reads that register. */
5323 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5326 /* ...or if any of the intervening instructions do. */
5327 for (j
= 0; j
< i
; j
++)
5328 if (gpr_read_mask (&hist
[j
]) & mask
)
5332 return MAX_VR4130_NOPS
- i
;
5337 #define BASE_REG_EQ(INSN1, INSN2) \
5338 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5339 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5341 /* Return the minimum alignment for this store instruction. */
5344 fix_24k_align_to (const struct mips_opcode
*mo
)
5346 if (strcmp (mo
->name
, "sh") == 0)
5349 if (strcmp (mo
->name
, "swc1") == 0
5350 || strcmp (mo
->name
, "swc2") == 0
5351 || strcmp (mo
->name
, "sw") == 0
5352 || strcmp (mo
->name
, "sc") == 0
5353 || strcmp (mo
->name
, "s.s") == 0)
5356 if (strcmp (mo
->name
, "sdc1") == 0
5357 || strcmp (mo
->name
, "sdc2") == 0
5358 || strcmp (mo
->name
, "s.d") == 0)
5365 struct fix_24k_store_info
5367 /* Immediate offset, if any, for this store instruction. */
5369 /* Alignment required by this store instruction. */
5371 /* True for register offsets. */
5372 int register_offset
;
5375 /* Comparison function used by qsort. */
5378 fix_24k_sort (const void *a
, const void *b
)
5380 const struct fix_24k_store_info
*pos1
= a
;
5381 const struct fix_24k_store_info
*pos2
= b
;
5383 return (pos1
->off
- pos2
->off
);
5386 /* INSN is a store instruction. Try to record the store information
5387 in STINFO. Return false if the information isn't known. */
5390 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5391 const struct mips_cl_insn
*insn
)
5393 /* The instruction must have a known offset. */
5394 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5397 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5398 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5402 /* Return the number of nops that would be needed to work around the 24k
5403 "lost data on stores during refill" errata if instruction INSN
5404 immediately followed the 2 instructions described by HIST.
5405 Ignore hazards that are contained within the first IGNORE
5406 instructions of HIST.
5408 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5409 for the data cache refills and store data. The following describes
5410 the scenario where the store data could be lost.
5412 * A data cache miss, due to either a load or a store, causing fill
5413 data to be supplied by the memory subsystem
5414 * The first three doublewords of fill data are returned and written
5416 * A sequence of four stores occurs in consecutive cycles around the
5417 final doubleword of the fill:
5421 * Zero, One or more instructions
5424 The four stores A-D must be to different doublewords of the line that
5425 is being filled. The fourth instruction in the sequence above permits
5426 the fill of the final doubleword to be transferred from the FSB into
5427 the cache. In the sequence above, the stores may be either integer
5428 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5429 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5430 different doublewords on the line. If the floating point unit is
5431 running in 1:2 mode, it is not possible to create the sequence above
5432 using only floating point store instructions.
5434 In this case, the cache line being filled is incorrectly marked
5435 invalid, thereby losing the data from any store to the line that
5436 occurs between the original miss and the completion of the five
5437 cycle sequence shown above.
5439 The workarounds are:
5441 * Run the data cache in write-through mode.
5442 * Insert a non-store instruction between
5443 Store A and Store B or Store B and Store C. */
5446 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5447 const struct mips_cl_insn
*insn
)
5449 struct fix_24k_store_info pos
[3];
5450 int align
, i
, base_offset
;
5455 /* If the previous instruction wasn't a store, there's nothing to
5457 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5460 /* If the instructions after the previous one are unknown, we have
5461 to assume the worst. */
5465 /* Check whether we are dealing with three consecutive stores. */
5466 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5467 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5470 /* If we don't know the relationship between the store addresses,
5471 assume the worst. */
5472 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5473 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5476 if (!fix_24k_record_store_info (&pos
[0], insn
)
5477 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5478 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5481 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5483 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5484 X bytes and such that the base register + X is known to be aligned
5487 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5491 align
= pos
[0].align_to
;
5492 base_offset
= pos
[0].off
;
5493 for (i
= 1; i
< 3; i
++)
5494 if (align
< pos
[i
].align_to
)
5496 align
= pos
[i
].align_to
;
5497 base_offset
= pos
[i
].off
;
5499 for (i
= 0; i
< 3; i
++)
5500 pos
[i
].off
-= base_offset
;
5503 pos
[0].off
&= ~align
+ 1;
5504 pos
[1].off
&= ~align
+ 1;
5505 pos
[2].off
&= ~align
+ 1;
5507 /* If any two stores write to the same chunk, they also write to the
5508 same doubleword. The offsets are still sorted at this point. */
5509 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5512 /* A range of at least 9 bytes is needed for the stores to be in
5513 non-overlapping doublewords. */
5514 if (pos
[2].off
- pos
[0].off
<= 8)
5517 if (pos
[2].off
- pos
[1].off
>= 24
5518 || pos
[1].off
- pos
[0].off
>= 24
5519 || pos
[2].off
- pos
[0].off
>= 32)
5525 /* Return the number of nops that would be needed if instruction INSN
5526 immediately followed the MAX_NOPS instructions given by HIST,
5527 where HIST[0] is the most recent instruction. Ignore hazards
5528 between INSN and the first IGNORE instructions in HIST.
5530 If INSN is null, return the worse-case number of nops for any
5534 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5535 const struct mips_cl_insn
*insn
)
5537 int i
, nops
, tmp_nops
;
5540 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5542 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5543 if (tmp_nops
> nops
)
5547 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5549 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5550 if (tmp_nops
> nops
)
5554 if (mips_fix_24k
&& !mips_opts
.micromips
)
5556 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5557 if (tmp_nops
> nops
)
5564 /* The variable arguments provide NUM_INSNS extra instructions that
5565 might be added to HIST. Return the largest number of nops that
5566 would be needed after the extended sequence, ignoring hazards
5567 in the first IGNORE instructions. */
5570 nops_for_sequence (int num_insns
, int ignore
,
5571 const struct mips_cl_insn
*hist
, ...)
5574 struct mips_cl_insn buffer
[MAX_NOPS
];
5575 struct mips_cl_insn
*cursor
;
5578 va_start (args
, hist
);
5579 cursor
= buffer
+ num_insns
;
5580 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5581 while (cursor
> buffer
)
5582 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5584 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5589 /* Like nops_for_insn, but if INSN is a branch, take into account the
5590 worst-case delay for the branch target. */
5593 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5594 const struct mips_cl_insn
*insn
)
5598 nops
= nops_for_insn (ignore
, hist
, insn
);
5599 if (delayed_branch_p (insn
))
5601 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5602 hist
, insn
, get_delay_slot_nop (insn
));
5603 if (tmp_nops
> nops
)
5606 else if (compact_branch_p (insn
))
5608 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5609 if (tmp_nops
> nops
)
5615 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5618 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5620 gas_assert (!HAVE_CODE_COMPRESSION
);
5621 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5622 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5625 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5626 jr target pc &= 'hffff_ffff_cfff_ffff. */
5629 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5631 gas_assert (!HAVE_CODE_COMPRESSION
);
5632 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5633 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5634 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5642 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5643 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5646 ep
.X_op
= O_constant
;
5647 ep
.X_add_number
= 0xcfff0000;
5648 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5649 ep
.X_add_number
= 0xffff;
5650 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5651 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5656 fix_loongson2f (struct mips_cl_insn
* ip
)
5658 if (mips_fix_loongson2f_nop
)
5659 fix_loongson2f_nop (ip
);
5661 if (mips_fix_loongson2f_jump
)
5662 fix_loongson2f_jump (ip
);
5665 /* IP is a branch that has a delay slot, and we need to fill it
5666 automatically. Return true if we can do that by swapping IP
5667 with the previous instruction.
5668 ADDRESS_EXPR is an operand of the instruction to be used with
5672 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5673 bfd_reloc_code_real_type
*reloc_type
)
5675 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5676 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
5678 /* -O2 and above is required for this optimization. */
5679 if (mips_optimize
< 2)
5682 /* If we have seen .set volatile or .set nomove, don't optimize. */
5683 if (mips_opts
.nomove
)
5686 /* We can't swap if the previous instruction's position is fixed. */
5687 if (history
[0].fixed_p
)
5690 /* If the previous previous insn was in a .set noreorder, we can't
5691 swap. Actually, the MIPS assembler will swap in this situation.
5692 However, gcc configured -with-gnu-as will generate code like
5700 in which we can not swap the bne and INSN. If gcc is not configured
5701 -with-gnu-as, it does not output the .set pseudo-ops. */
5702 if (history
[1].noreorder_p
)
5705 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5706 This means that the previous instruction was a 4-byte one anyhow. */
5707 if (mips_opts
.mips16
&& history
[0].fixp
[0])
5710 /* If the branch is itself the target of a branch, we can not swap.
5711 We cheat on this; all we check for is whether there is a label on
5712 this instruction. If there are any branches to anything other than
5713 a label, users must use .set noreorder. */
5714 if (seg_info (now_seg
)->label_list
)
5717 /* If the previous instruction is in a variant frag other than this
5718 branch's one, we cannot do the swap. This does not apply to
5719 MIPS16 code, which uses variant frags for different purposes. */
5720 if (!mips_opts
.mips16
5722 && history
[0].frag
->fr_type
== rs_machine_dependent
)
5725 /* We do not swap with instructions that cannot architecturally
5726 be placed in a branch delay slot, such as SYNC or ERET. We
5727 also refrain from swapping with a trap instruction, since it
5728 complicates trap handlers to have the trap instruction be in
5730 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5731 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
5734 /* Check for conflicts between the branch and the instructions
5735 before the candidate delay slot. */
5736 if (nops_for_insn (0, history
+ 1, ip
) > 0)
5739 /* Check for conflicts between the swapped sequence and the
5740 target of the branch. */
5741 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
5744 /* If the branch reads a register that the previous
5745 instruction sets, we can not swap. */
5746 gpr_read
= gpr_read_mask (ip
);
5747 prev_gpr_write
= gpr_write_mask (&history
[0]);
5748 if (gpr_read
& prev_gpr_write
)
5751 /* If the branch writes a register that the previous
5752 instruction sets, we can not swap. */
5753 gpr_write
= gpr_write_mask (ip
);
5754 if (gpr_write
& prev_gpr_write
)
5757 /* If the branch writes a register that the previous
5758 instruction reads, we can not swap. */
5759 prev_gpr_read
= gpr_read_mask (&history
[0]);
5760 if (gpr_write
& prev_gpr_read
)
5763 /* If one instruction sets a condition code and the
5764 other one uses a condition code, we can not swap. */
5765 pinfo
= ip
->insn_mo
->pinfo
;
5766 if ((pinfo
& INSN_READ_COND_CODE
)
5767 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
5769 if ((pinfo
& INSN_WRITE_COND_CODE
)
5770 && (prev_pinfo
& INSN_READ_COND_CODE
))
5773 /* If the previous instruction uses the PC, we can not swap. */
5774 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5775 if (prev_pinfo2
& INSN2_READ_PC
)
5778 /* If the previous instruction has an incorrect size for a fixed
5779 branch delay slot in microMIPS mode, we cannot swap. */
5780 pinfo2
= ip
->insn_mo
->pinfo2
;
5781 if (mips_opts
.micromips
5782 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
5783 && insn_length (history
) != 2)
5785 if (mips_opts
.micromips
5786 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
5787 && insn_length (history
) != 4)
5790 /* On R5900 short loops need to be fixed by inserting a nop in
5791 the branch delay slots.
5792 A short loop can be terminated too early. */
5793 if (mips_opts
.arch
== CPU_R5900
5794 /* Check if instruction has a parameter, ignore "j $31". */
5795 && (address_expr
!= NULL
)
5796 /* Parameter must be 16 bit. */
5797 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
5798 /* Branch to same segment. */
5799 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
5800 /* Branch to same code fragment. */
5801 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
5802 /* Can only calculate branch offset if value is known. */
5803 && symbol_constant_p(address_expr
->X_add_symbol
)
5804 /* Check if branch is really conditional. */
5805 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5806 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
5807 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5810 /* Check if loop is shorter than 6 instructions including
5811 branch and delay slot. */
5812 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
5819 /* When the loop includes branches or jumps,
5820 it is not a short loop. */
5821 for (i
= 0; i
< (distance
/ 4); i
++)
5823 if ((history
[i
].cleared_p
)
5824 || delayed_branch_p(&history
[i
]))
5832 /* Insert nop after branch to fix short loop. */
5841 /* Decide how we should add IP to the instruction stream.
5842 ADDRESS_EXPR is an operand of the instruction to be used with
5845 static enum append_method
5846 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5847 bfd_reloc_code_real_type
*reloc_type
)
5849 /* The relaxed version of a macro sequence must be inherently
5851 if (mips_relax
.sequence
== 2)
5854 /* We must not dabble with instructions in a ".set norerorder" block. */
5855 if (mips_opts
.noreorder
)
5858 /* Otherwise, it's our responsibility to fill branch delay slots. */
5859 if (delayed_branch_p (ip
))
5861 if (!branch_likely_p (ip
)
5862 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
5865 if (mips_opts
.mips16
5866 && ISA_SUPPORTS_MIPS16E
5867 && gpr_read_mask (ip
) != 0)
5868 return APPEND_ADD_COMPACT
;
5870 return APPEND_ADD_WITH_NOP
;
5876 /* IP is a MIPS16 instruction whose opcode we have just changed.
5877 Point IP->insn_mo to the new opcode's definition. */
5880 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
5882 const struct mips_opcode
*mo
, *end
;
5884 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
5885 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
5886 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
5894 /* For microMIPS macros, we need to generate a local number label
5895 as the target of branches. */
5896 #define MICROMIPS_LABEL_CHAR '\037'
5897 static unsigned long micromips_target_label
;
5898 static char micromips_target_name
[32];
5901 micromips_label_name (void)
5903 char *p
= micromips_target_name
;
5904 char symbol_name_temporary
[24];
5912 l
= micromips_target_label
;
5913 #ifdef LOCAL_LABEL_PREFIX
5914 *p
++ = LOCAL_LABEL_PREFIX
;
5917 *p
++ = MICROMIPS_LABEL_CHAR
;
5920 symbol_name_temporary
[i
++] = l
% 10 + '0';
5925 *p
++ = symbol_name_temporary
[--i
];
5928 return micromips_target_name
;
5932 micromips_label_expr (expressionS
*label_expr
)
5934 label_expr
->X_op
= O_symbol
;
5935 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
5936 label_expr
->X_add_number
= 0;
5940 micromips_label_inc (void)
5942 micromips_target_label
++;
5943 *micromips_target_name
= '\0';
5947 micromips_add_label (void)
5951 s
= colon (micromips_label_name ());
5952 micromips_label_inc ();
5953 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
5956 /* If assembling microMIPS code, then return the microMIPS reloc
5957 corresponding to the requested one if any. Otherwise return
5958 the reloc unchanged. */
5960 static bfd_reloc_code_real_type
5961 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
5963 static const bfd_reloc_code_real_type relocs
[][2] =
5965 /* Keep sorted incrementally by the left-hand key. */
5966 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
5967 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
5968 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
5969 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
5970 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
5971 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
5972 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
5973 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
5974 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
5975 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
5976 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
5977 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
5978 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
5979 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
5980 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
5981 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
5982 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
5983 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
5984 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
5985 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
5986 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
5987 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
5988 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
5989 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
5990 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
5991 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
5992 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
5994 bfd_reloc_code_real_type r
;
5997 if (!mips_opts
.micromips
)
5999 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6005 return relocs
[i
][1];
6010 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6011 Return true on success, storing the resolved value in RESULT. */
6014 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6019 case BFD_RELOC_MIPS_HIGHEST
:
6020 case BFD_RELOC_MICROMIPS_HIGHEST
:
6021 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6024 case BFD_RELOC_MIPS_HIGHER
:
6025 case BFD_RELOC_MICROMIPS_HIGHER
:
6026 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6029 case BFD_RELOC_HI16_S
:
6030 case BFD_RELOC_MICROMIPS_HI16_S
:
6031 case BFD_RELOC_MIPS16_HI16_S
:
6032 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6035 case BFD_RELOC_HI16
:
6036 case BFD_RELOC_MICROMIPS_HI16
:
6037 case BFD_RELOC_MIPS16_HI16
:
6038 *result
= (operand
>> 16) & 0xffff;
6041 case BFD_RELOC_LO16
:
6042 case BFD_RELOC_MICROMIPS_LO16
:
6043 case BFD_RELOC_MIPS16_LO16
:
6044 *result
= operand
& 0xffff;
6047 case BFD_RELOC_UNUSED
:
6056 /* Output an instruction. IP is the instruction information.
6057 ADDRESS_EXPR is an operand of the instruction to be used with
6058 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6059 a macro expansion. */
6062 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6063 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6065 unsigned long prev_pinfo2
, pinfo
;
6066 bfd_boolean relaxed_branch
= FALSE
;
6067 enum append_method method
;
6068 bfd_boolean relax32
;
6071 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6072 fix_loongson2f (ip
);
6074 file_ase_mips16
|= mips_opts
.mips16
;
6075 file_ase_micromips
|= mips_opts
.micromips
;
6077 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6078 pinfo
= ip
->insn_mo
->pinfo
;
6080 if (mips_opts
.micromips
6082 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6083 && micromips_insn_length (ip
->insn_mo
) != 2)
6084 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6085 && micromips_insn_length (ip
->insn_mo
) != 4)))
6086 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6087 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6089 if (address_expr
== NULL
)
6091 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6092 && reloc_type
[1] == BFD_RELOC_UNUSED
6093 && reloc_type
[2] == BFD_RELOC_UNUSED
6094 && address_expr
->X_op
== O_constant
)
6096 switch (*reloc_type
)
6098 case BFD_RELOC_MIPS_JMP
:
6102 shift
= mips_opts
.micromips
? 1 : 2;
6103 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6104 as_bad (_("jump to misaligned address (0x%lx)"),
6105 (unsigned long) address_expr
->X_add_number
);
6106 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6112 case BFD_RELOC_MIPS16_JMP
:
6113 if ((address_expr
->X_add_number
& 3) != 0)
6114 as_bad (_("jump to misaligned address (0x%lx)"),
6115 (unsigned long) address_expr
->X_add_number
);
6117 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6118 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6119 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6123 case BFD_RELOC_16_PCREL_S2
:
6127 shift
= mips_opts
.micromips
? 1 : 2;
6128 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6129 as_bad (_("branch to misaligned address (0x%lx)"),
6130 (unsigned long) address_expr
->X_add_number
);
6131 if (!mips_relax_branch
)
6133 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6134 & ~((1 << (shift
+ 16)) - 1))
6135 as_bad (_("branch address range overflow (0x%lx)"),
6136 (unsigned long) address_expr
->X_add_number
);
6137 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6147 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6150 ip
->insn_opcode
|= value
& 0xffff;
6158 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6160 /* There are a lot of optimizations we could do that we don't.
6161 In particular, we do not, in general, reorder instructions.
6162 If you use gcc with optimization, it will reorder
6163 instructions and generally do much more optimization then we
6164 do here; repeating all that work in the assembler would only
6165 benefit hand written assembly code, and does not seem worth
6167 int nops
= (mips_optimize
== 0
6168 ? nops_for_insn (0, history
, NULL
)
6169 : nops_for_insn_or_target (0, history
, ip
));
6173 unsigned long old_frag_offset
;
6176 old_frag
= frag_now
;
6177 old_frag_offset
= frag_now_fix ();
6179 for (i
= 0; i
< nops
; i
++)
6180 add_fixed_insn (NOP_INSN
);
6181 insert_into_history (0, nops
, NOP_INSN
);
6185 listing_prev_line ();
6186 /* We may be at the start of a variant frag. In case we
6187 are, make sure there is enough space for the frag
6188 after the frags created by listing_prev_line. The
6189 argument to frag_grow here must be at least as large
6190 as the argument to all other calls to frag_grow in
6191 this file. We don't have to worry about being in the
6192 middle of a variant frag, because the variants insert
6193 all needed nop instructions themselves. */
6197 mips_move_text_labels ();
6199 #ifndef NO_ECOFF_DEBUGGING
6200 if (ECOFF_DEBUGGING
)
6201 ecoff_fix_loc (old_frag
, old_frag_offset
);
6205 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6209 /* Work out how many nops in prev_nop_frag are needed by IP,
6210 ignoring hazards generated by the first prev_nop_frag_since
6212 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6213 gas_assert (nops
<= prev_nop_frag_holds
);
6215 /* Enforce NOPS as a minimum. */
6216 if (nops
> prev_nop_frag_required
)
6217 prev_nop_frag_required
= nops
;
6219 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6221 /* Settle for the current number of nops. Update the history
6222 accordingly (for the benefit of any future .set reorder code). */
6223 prev_nop_frag
= NULL
;
6224 insert_into_history (prev_nop_frag_since
,
6225 prev_nop_frag_holds
, NOP_INSN
);
6229 /* Allow this instruction to replace one of the nops that was
6230 tentatively added to prev_nop_frag. */
6231 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6232 prev_nop_frag_holds
--;
6233 prev_nop_frag_since
++;
6237 method
= get_append_method (ip
, address_expr
, reloc_type
);
6238 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6240 dwarf2_emit_insn (0);
6241 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6242 so "move" the instruction address accordingly.
6244 Also, it doesn't seem appropriate for the assembler to reorder .loc
6245 entries. If this instruction is a branch that we are going to swap
6246 with the previous instruction, the two instructions should be
6247 treated as a unit, and the debug information for both instructions
6248 should refer to the start of the branch sequence. Using the
6249 current position is certainly wrong when swapping a 32-bit branch
6250 and a 16-bit delay slot, since the current position would then be
6251 in the middle of a branch. */
6252 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6254 relax32
= (mips_relax_branch
6255 /* Don't try branch relaxation within .set nomacro, or within
6256 .set noat if we use $at for PIC computations. If it turns
6257 out that the branch was out-of-range, we'll get an error. */
6258 && !mips_opts
.warn_about_macros
6259 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6260 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6261 as they have no complementing branches. */
6262 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6264 if (!HAVE_CODE_COMPRESSION
6267 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6268 && delayed_branch_p (ip
))
6270 relaxed_branch
= TRUE
;
6271 add_relaxed_insn (ip
, (relaxed_branch_length
6273 uncond_branch_p (ip
) ? -1
6274 : branch_likely_p (ip
) ? 1
6278 uncond_branch_p (ip
),
6279 branch_likely_p (ip
),
6280 pinfo
& INSN_WRITE_GPR_31
,
6282 address_expr
->X_add_symbol
,
6283 address_expr
->X_add_number
);
6284 *reloc_type
= BFD_RELOC_UNUSED
;
6286 else if (mips_opts
.micromips
6288 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6289 || *reloc_type
> BFD_RELOC_UNUSED
)
6290 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6291 /* Don't try branch relaxation when users specify
6292 16-bit/32-bit instructions. */
6293 && !forced_insn_length
)
6295 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6296 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6297 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6298 int compact
= compact_branch_p (ip
);
6299 int al
= pinfo
& INSN_WRITE_GPR_31
;
6302 gas_assert (address_expr
!= NULL
);
6303 gas_assert (!mips_relax
.sequence
);
6305 relaxed_branch
= TRUE
;
6306 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6307 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6308 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6310 address_expr
->X_add_symbol
,
6311 address_expr
->X_add_number
);
6312 *reloc_type
= BFD_RELOC_UNUSED
;
6314 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6316 /* We need to set up a variant frag. */
6317 gas_assert (address_expr
!= NULL
);
6318 add_relaxed_insn (ip
, 4, 0,
6320 (*reloc_type
- BFD_RELOC_UNUSED
,
6321 forced_insn_length
== 2, forced_insn_length
== 4,
6322 delayed_branch_p (&history
[0]),
6323 history
[0].mips16_absolute_jump_p
),
6324 make_expr_symbol (address_expr
), 0);
6326 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6328 if (!delayed_branch_p (ip
))
6329 /* Make sure there is enough room to swap this instruction with
6330 a following jump instruction. */
6332 add_fixed_insn (ip
);
6336 if (mips_opts
.mips16
6337 && mips_opts
.noreorder
6338 && delayed_branch_p (&history
[0]))
6339 as_warn (_("extended instruction in delay slot"));
6341 if (mips_relax
.sequence
)
6343 /* If we've reached the end of this frag, turn it into a variant
6344 frag and record the information for the instructions we've
6346 if (frag_room () < 4)
6347 relax_close_frag ();
6348 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6351 if (mips_relax
.sequence
!= 2)
6353 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6354 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6355 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6356 mips_macro_warning
.insns
[0]++;
6358 if (mips_relax
.sequence
!= 1)
6360 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6361 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6362 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6363 mips_macro_warning
.insns
[1]++;
6366 if (mips_opts
.mips16
)
6369 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6371 add_fixed_insn (ip
);
6374 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6376 bfd_reloc_code_real_type final_type
[3];
6377 reloc_howto_type
*howto0
;
6378 reloc_howto_type
*howto
;
6381 /* Perform any necessary conversion to microMIPS relocations
6382 and find out how many relocations there actually are. */
6383 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6384 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6386 /* In a compound relocation, it is the final (outermost)
6387 operator that determines the relocated field. */
6388 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6393 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6394 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6395 bfd_get_reloc_size (howto
),
6397 howto0
&& howto0
->pc_relative
,
6400 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6401 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6402 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6404 /* These relocations can have an addend that won't fit in
6405 4 octets for 64bit assembly. */
6407 && ! howto
->partial_inplace
6408 && (reloc_type
[0] == BFD_RELOC_16
6409 || reloc_type
[0] == BFD_RELOC_32
6410 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6411 || reloc_type
[0] == BFD_RELOC_GPREL16
6412 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6413 || reloc_type
[0] == BFD_RELOC_GPREL32
6414 || reloc_type
[0] == BFD_RELOC_64
6415 || reloc_type
[0] == BFD_RELOC_CTOR
6416 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6417 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6418 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6419 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6420 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6421 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6422 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6423 || hi16_reloc_p (reloc_type
[0])
6424 || lo16_reloc_p (reloc_type
[0])))
6425 ip
->fixp
[0]->fx_no_overflow
= 1;
6427 /* These relocations can have an addend that won't fit in 2 octets. */
6428 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6429 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6430 ip
->fixp
[0]->fx_no_overflow
= 1;
6432 if (mips_relax
.sequence
)
6434 if (mips_relax
.first_fixup
== 0)
6435 mips_relax
.first_fixup
= ip
->fixp
[0];
6437 else if (reloc_needs_lo_p (*reloc_type
))
6439 struct mips_hi_fixup
*hi_fixup
;
6441 /* Reuse the last entry if it already has a matching %lo. */
6442 hi_fixup
= mips_hi_fixup_list
;
6444 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6446 hi_fixup
= ((struct mips_hi_fixup
*)
6447 xmalloc (sizeof (struct mips_hi_fixup
)));
6448 hi_fixup
->next
= mips_hi_fixup_list
;
6449 mips_hi_fixup_list
= hi_fixup
;
6451 hi_fixup
->fixp
= ip
->fixp
[0];
6452 hi_fixup
->seg
= now_seg
;
6455 /* Add fixups for the second and third relocations, if given.
6456 Note that the ABI allows the second relocation to be
6457 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6458 moment we only use RSS_UNDEF, but we could add support
6459 for the others if it ever becomes necessary. */
6460 for (i
= 1; i
< 3; i
++)
6461 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6463 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6464 ip
->fixp
[0]->fx_size
, NULL
, 0,
6465 FALSE
, final_type
[i
]);
6467 /* Use fx_tcbit to mark compound relocs. */
6468 ip
->fixp
[0]->fx_tcbit
= 1;
6469 ip
->fixp
[i
]->fx_tcbit
= 1;
6474 /* Update the register mask information. */
6475 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6476 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6481 insert_into_history (0, 1, ip
);
6484 case APPEND_ADD_WITH_NOP
:
6486 struct mips_cl_insn
*nop
;
6488 insert_into_history (0, 1, ip
);
6489 nop
= get_delay_slot_nop (ip
);
6490 add_fixed_insn (nop
);
6491 insert_into_history (0, 1, nop
);
6492 if (mips_relax
.sequence
)
6493 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6497 case APPEND_ADD_COMPACT
:
6498 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6499 gas_assert (mips_opts
.mips16
);
6500 ip
->insn_opcode
|= 0x0080;
6501 find_altered_mips16_opcode (ip
);
6503 insert_into_history (0, 1, ip
);
6508 struct mips_cl_insn delay
= history
[0];
6509 if (mips_opts
.mips16
)
6511 know (delay
.frag
== ip
->frag
);
6512 move_insn (ip
, delay
.frag
, delay
.where
);
6513 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6515 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6517 /* Add the delay slot instruction to the end of the
6518 current frag and shrink the fixed part of the
6519 original frag. If the branch occupies the tail of
6520 the latter, move it backwards to cover the gap. */
6521 delay
.frag
->fr_fix
-= branch_disp
;
6522 if (delay
.frag
== ip
->frag
)
6523 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6524 add_fixed_insn (&delay
);
6528 move_insn (&delay
, ip
->frag
,
6529 ip
->where
- branch_disp
+ insn_length (ip
));
6530 move_insn (ip
, history
[0].frag
, history
[0].where
);
6534 insert_into_history (0, 1, &delay
);
6539 /* If we have just completed an unconditional branch, clear the history. */
6540 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6541 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6545 mips_no_prev_insn ();
6547 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6548 history
[i
].cleared_p
= 1;
6551 /* We need to emit a label at the end of branch-likely macros. */
6552 if (emit_branch_likely_macro
)
6554 emit_branch_likely_macro
= FALSE
;
6555 micromips_add_label ();
6558 /* We just output an insn, so the next one doesn't have a label. */
6559 mips_clear_insn_labels ();
6562 /* Forget that there was any previous instruction or label.
6563 When BRANCH is true, the branch history is also flushed. */
6566 mips_no_prev_insn (void)
6568 prev_nop_frag
= NULL
;
6569 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6570 mips_clear_insn_labels ();
6573 /* This function must be called before we emit something other than
6574 instructions. It is like mips_no_prev_insn except that it inserts
6575 any NOPS that might be needed by previous instructions. */
6578 mips_emit_delays (void)
6580 if (! mips_opts
.noreorder
)
6582 int nops
= nops_for_insn (0, history
, NULL
);
6586 add_fixed_insn (NOP_INSN
);
6587 mips_move_text_labels ();
6590 mips_no_prev_insn ();
6593 /* Start a (possibly nested) noreorder block. */
6596 start_noreorder (void)
6598 if (mips_opts
.noreorder
== 0)
6603 /* None of the instructions before the .set noreorder can be moved. */
6604 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6605 history
[i
].fixed_p
= 1;
6607 /* Insert any nops that might be needed between the .set noreorder
6608 block and the previous instructions. We will later remove any
6609 nops that turn out not to be needed. */
6610 nops
= nops_for_insn (0, history
, NULL
);
6613 if (mips_optimize
!= 0)
6615 /* Record the frag which holds the nop instructions, so
6616 that we can remove them if we don't need them. */
6617 frag_grow (nops
* NOP_INSN_SIZE
);
6618 prev_nop_frag
= frag_now
;
6619 prev_nop_frag_holds
= nops
;
6620 prev_nop_frag_required
= 0;
6621 prev_nop_frag_since
= 0;
6624 for (; nops
> 0; --nops
)
6625 add_fixed_insn (NOP_INSN
);
6627 /* Move on to a new frag, so that it is safe to simply
6628 decrease the size of prev_nop_frag. */
6629 frag_wane (frag_now
);
6631 mips_move_text_labels ();
6633 mips_mark_labels ();
6634 mips_clear_insn_labels ();
6636 mips_opts
.noreorder
++;
6637 mips_any_noreorder
= 1;
6640 /* End a nested noreorder block. */
6643 end_noreorder (void)
6645 mips_opts
.noreorder
--;
6646 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6648 /* Commit to inserting prev_nop_frag_required nops and go back to
6649 handling nop insertion the .set reorder way. */
6650 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6652 insert_into_history (prev_nop_frag_since
,
6653 prev_nop_frag_required
, NOP_INSN
);
6654 prev_nop_frag
= NULL
;
6658 /* Set up global variables for the start of a new macro. */
6663 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
6664 memset (&mips_macro_warning
.first_insn_sizes
, 0,
6665 sizeof (mips_macro_warning
.first_insn_sizes
));
6666 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
6667 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
6668 && delayed_branch_p (&history
[0]));
6669 switch (history
[0].insn_mo
->pinfo2
6670 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
6672 case INSN2_BRANCH_DELAY_32BIT
:
6673 mips_macro_warning
.delay_slot_length
= 4;
6675 case INSN2_BRANCH_DELAY_16BIT
:
6676 mips_macro_warning
.delay_slot_length
= 2;
6679 mips_macro_warning
.delay_slot_length
= 0;
6682 mips_macro_warning
.first_frag
= NULL
;
6685 /* Given that a macro is longer than one instruction or of the wrong size,
6686 return the appropriate warning for it. Return null if no warning is
6687 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6688 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6689 and RELAX_NOMACRO. */
6692 macro_warning (relax_substateT subtype
)
6694 if (subtype
& RELAX_DELAY_SLOT
)
6695 return _("Macro instruction expanded into multiple instructions"
6696 " in a branch delay slot");
6697 else if (subtype
& RELAX_NOMACRO
)
6698 return _("Macro instruction expanded into multiple instructions");
6699 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
6700 | RELAX_DELAY_SLOT_SIZE_SECOND
))
6701 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
6702 ? _("Macro instruction expanded into a wrong size instruction"
6703 " in a 16-bit branch delay slot")
6704 : _("Macro instruction expanded into a wrong size instruction"
6705 " in a 32-bit branch delay slot"));
6710 /* Finish up a macro. Emit warnings as appropriate. */
6715 /* Relaxation warning flags. */
6716 relax_substateT subtype
= 0;
6718 /* Check delay slot size requirements. */
6719 if (mips_macro_warning
.delay_slot_length
== 2)
6720 subtype
|= RELAX_DELAY_SLOT_16BIT
;
6721 if (mips_macro_warning
.delay_slot_length
!= 0)
6723 if (mips_macro_warning
.delay_slot_length
6724 != mips_macro_warning
.first_insn_sizes
[0])
6725 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
6726 if (mips_macro_warning
.delay_slot_length
6727 != mips_macro_warning
.first_insn_sizes
[1])
6728 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
6731 /* Check instruction count requirements. */
6732 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
6734 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
6735 subtype
|= RELAX_SECOND_LONGER
;
6736 if (mips_opts
.warn_about_macros
)
6737 subtype
|= RELAX_NOMACRO
;
6738 if (mips_macro_warning
.delay_slot_p
)
6739 subtype
|= RELAX_DELAY_SLOT
;
6742 /* If both alternatives fail to fill a delay slot correctly,
6743 emit the warning now. */
6744 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
6745 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
6750 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
6751 | RELAX_DELAY_SLOT_SIZE_FIRST
6752 | RELAX_DELAY_SLOT_SIZE_SECOND
);
6753 msg
= macro_warning (s
);
6755 as_warn ("%s", msg
);
6759 /* If both implementations are longer than 1 instruction, then emit the
6761 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
6766 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
6767 msg
= macro_warning (s
);
6769 as_warn ("%s", msg
);
6773 /* If any flags still set, then one implementation might need a warning
6774 and the other either will need one of a different kind or none at all.
6775 Pass any remaining flags over to relaxation. */
6776 if (mips_macro_warning
.first_frag
!= NULL
)
6777 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
6780 /* Instruction operand formats used in macros that vary between
6781 standard MIPS and microMIPS code. */
6783 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
6784 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
6785 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
6786 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
6787 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
6788 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
6789 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
6790 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
6792 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6793 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6794 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6795 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6796 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6797 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6798 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6799 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6801 /* Read a macro's relocation codes from *ARGS and store them in *R.
6802 The first argument in *ARGS will be either the code for a single
6803 relocation or -1 followed by the three codes that make up a
6804 composite relocation. */
6807 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
6811 next
= va_arg (*args
, int);
6813 r
[0] = (bfd_reloc_code_real_type
) next
;
6816 for (i
= 0; i
< 3; i
++)
6817 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
6818 /* This function is only used for 16-bit relocation fields.
6819 To make the macro code simpler, treat an unrelocated value
6820 in the same way as BFD_RELOC_LO16. */
6821 if (r
[0] == BFD_RELOC_UNUSED
)
6822 r
[0] = BFD_RELOC_LO16
;
6826 /* Build an instruction created by a macro expansion. This is passed
6827 a pointer to the count of instructions created so far, an
6828 expression, the name of the instruction to build, an operand format
6829 string, and corresponding arguments. */
6832 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
6834 const struct mips_opcode
*mo
= NULL
;
6835 bfd_reloc_code_real_type r
[3];
6836 const struct mips_opcode
*amo
;
6837 const struct mips_operand
*operand
;
6838 struct hash_control
*hash
;
6839 struct mips_cl_insn insn
;
6843 va_start (args
, fmt
);
6845 if (mips_opts
.mips16
)
6847 mips16_macro_build (ep
, name
, fmt
, &args
);
6852 r
[0] = BFD_RELOC_UNUSED
;
6853 r
[1] = BFD_RELOC_UNUSED
;
6854 r
[2] = BFD_RELOC_UNUSED
;
6855 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
6856 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
6858 gas_assert (strcmp (name
, amo
->name
) == 0);
6862 /* Search until we get a match for NAME. It is assumed here that
6863 macros will never generate MDMX, MIPS-3D, or MT instructions.
6864 We try to match an instruction that fulfils the branch delay
6865 slot instruction length requirement (if any) of the previous
6866 instruction. While doing this we record the first instruction
6867 seen that matches all the other conditions and use it anyway
6868 if the requirement cannot be met; we will issue an appropriate
6869 warning later on. */
6870 if (strcmp (fmt
, amo
->args
) == 0
6871 && amo
->pinfo
!= INSN_MACRO
6872 && is_opcode_valid (amo
)
6873 && is_size_valid (amo
))
6875 if (is_delay_slot_valid (amo
))
6885 gas_assert (amo
->name
);
6887 while (strcmp (name
, amo
->name
) == 0);
6890 create_insn (&insn
, mo
);
6903 macro_read_relocs (&args
, r
);
6904 gas_assert (*r
== BFD_RELOC_GPREL16
6905 || *r
== BFD_RELOC_MIPS_HIGHER
6906 || *r
== BFD_RELOC_HI16_S
6907 || *r
== BFD_RELOC_LO16
6908 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
6912 macro_read_relocs (&args
, r
);
6916 macro_read_relocs (&args
, r
);
6917 gas_assert (ep
!= NULL
6918 && (ep
->X_op
== O_constant
6919 || (ep
->X_op
== O_symbol
6920 && (*r
== BFD_RELOC_MIPS_HIGHEST
6921 || *r
== BFD_RELOC_HI16_S
6922 || *r
== BFD_RELOC_HI16
6923 || *r
== BFD_RELOC_GPREL16
6924 || *r
== BFD_RELOC_MIPS_GOT_HI16
6925 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
6929 gas_assert (ep
!= NULL
);
6932 * This allows macro() to pass an immediate expression for
6933 * creating short branches without creating a symbol.
6935 * We don't allow branch relaxation for these branches, as
6936 * they should only appear in ".set nomacro" anyway.
6938 if (ep
->X_op
== O_constant
)
6940 /* For microMIPS we always use relocations for branches.
6941 So we should not resolve immediate values. */
6942 gas_assert (!mips_opts
.micromips
);
6944 if ((ep
->X_add_number
& 3) != 0)
6945 as_bad (_("branch to misaligned address (0x%lx)"),
6946 (unsigned long) ep
->X_add_number
);
6947 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
6948 as_bad (_("branch address range overflow (0x%lx)"),
6949 (unsigned long) ep
->X_add_number
);
6950 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
6954 *r
= BFD_RELOC_16_PCREL_S2
;
6958 gas_assert (ep
!= NULL
);
6959 *r
= BFD_RELOC_MIPS_JMP
;
6963 operand
= (mips_opts
.micromips
6964 ? decode_micromips_operand (fmt
)
6965 : decode_mips_operand (fmt
));
6969 uval
= va_arg (args
, int);
6970 if (operand
->type
== OP_CLO_CLZ_DEST
)
6971 uval
|= (uval
<< 5);
6972 insn_insert_operand (&insn
, operand
, uval
);
6974 if (*fmt
== '+' || *fmt
== 'm')
6980 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
6982 append_insn (&insn
, ep
, r
, TRUE
);
6986 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
6989 struct mips_opcode
*mo
;
6990 struct mips_cl_insn insn
;
6991 const struct mips_operand
*operand
;
6992 bfd_reloc_code_real_type r
[3]
6993 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
6995 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
6997 gas_assert (strcmp (name
, mo
->name
) == 0);
6999 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7002 gas_assert (mo
->name
);
7003 gas_assert (strcmp (name
, mo
->name
) == 0);
7006 create_insn (&insn
, mo
);
7044 gas_assert (ep
!= NULL
);
7046 if (ep
->X_op
!= O_constant
)
7047 *r
= (int) BFD_RELOC_UNUSED
+ c
;
7048 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
7050 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
7052 *r
= BFD_RELOC_UNUSED
;
7058 operand
= decode_mips16_operand (c
, FALSE
);
7062 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
7067 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7069 append_insn (&insn
, ep
, r
, TRUE
);
7073 * Sign-extend 32-bit mode constants that have bit 31 set and all
7074 * higher bits unset.
7077 normalize_constant_expr (expressionS
*ex
)
7079 if (ex
->X_op
== O_constant
7080 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7081 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7086 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7087 * all higher bits unset.
7090 normalize_address_expr (expressionS
*ex
)
7092 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7093 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7094 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7095 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7100 * Generate a "jalr" instruction with a relocation hint to the called
7101 * function. This occurs in NewABI PIC code.
7104 macro_build_jalr (expressionS
*ep
, int cprestore
)
7106 static const bfd_reloc_code_real_type jalr_relocs
[2]
7107 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
7108 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
7112 if (MIPS_JALR_HINT_P (ep
))
7117 if (mips_opts
.micromips
)
7119 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
7120 ? "jalr" : "jalrs");
7121 if (MIPS_JALR_HINT_P (ep
)
7123 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7124 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
7126 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
7129 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
7130 if (MIPS_JALR_HINT_P (ep
))
7131 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
7135 * Generate a "lui" instruction.
7138 macro_build_lui (expressionS
*ep
, int regnum
)
7140 gas_assert (! mips_opts
.mips16
);
7142 if (ep
->X_op
!= O_constant
)
7144 gas_assert (ep
->X_op
== O_symbol
);
7145 /* _gp_disp is a special case, used from s_cpload.
7146 __gnu_local_gp is used if mips_no_shared. */
7147 gas_assert (mips_pic
== NO_PIC
7149 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
7150 || (! mips_in_shared
7151 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
7152 "__gnu_local_gp") == 0));
7155 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
7158 /* Generate a sequence of instructions to do a load or store from a constant
7159 offset off of a base register (breg) into/from a target register (treg),
7160 using AT if necessary. */
7162 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
7163 int treg
, int breg
, int dbl
)
7165 gas_assert (ep
->X_op
== O_constant
);
7167 /* Sign-extending 32-bit constants makes their handling easier. */
7169 normalize_constant_expr (ep
);
7171 /* Right now, this routine can only handle signed 32-bit constants. */
7172 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
7173 as_warn (_("operand overflow"));
7175 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
7177 /* Signed 16-bit offset will fit in the op. Easy! */
7178 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7182 /* 32-bit offset, need multiple instructions and AT, like:
7183 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7184 addu $tempreg,$tempreg,$breg
7185 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7186 to handle the complete offset. */
7187 macro_build_lui (ep
, AT
);
7188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7189 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7192 as_bad (_("Macro used $at after \".set noat\""));
7197 * Generates code to set the $at register to true (one)
7198 * if reg is less than the immediate expression.
7201 set_at (int reg
, int unsignedp
)
7203 if (imm_expr
.X_op
== O_constant
7204 && imm_expr
.X_add_number
>= -0x8000
7205 && imm_expr
.X_add_number
< 0x8000)
7206 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
7207 AT
, reg
, BFD_RELOC_LO16
);
7210 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7211 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
7215 /* Count the leading zeroes by performing a binary chop. This is a
7216 bulky bit of source, but performance is a LOT better for the
7217 majority of values than a simple loop to count the bits:
7218 for (lcnt = 0; (lcnt < 32); lcnt++)
7219 if ((v) & (1 << (31 - lcnt)))
7221 However it is not code size friendly, and the gain will drop a bit
7222 on certain cached systems.
7224 #define COUNT_TOP_ZEROES(v) \
7225 (((v) & ~0xffff) == 0 \
7226 ? ((v) & ~0xff) == 0 \
7227 ? ((v) & ~0xf) == 0 \
7228 ? ((v) & ~0x3) == 0 \
7229 ? ((v) & ~0x1) == 0 \
7234 : ((v) & ~0x7) == 0 \
7237 : ((v) & ~0x3f) == 0 \
7238 ? ((v) & ~0x1f) == 0 \
7241 : ((v) & ~0x7f) == 0 \
7244 : ((v) & ~0xfff) == 0 \
7245 ? ((v) & ~0x3ff) == 0 \
7246 ? ((v) & ~0x1ff) == 0 \
7249 : ((v) & ~0x7ff) == 0 \
7252 : ((v) & ~0x3fff) == 0 \
7253 ? ((v) & ~0x1fff) == 0 \
7256 : ((v) & ~0x7fff) == 0 \
7259 : ((v) & ~0xffffff) == 0 \
7260 ? ((v) & ~0xfffff) == 0 \
7261 ? ((v) & ~0x3ffff) == 0 \
7262 ? ((v) & ~0x1ffff) == 0 \
7265 : ((v) & ~0x7ffff) == 0 \
7268 : ((v) & ~0x3fffff) == 0 \
7269 ? ((v) & ~0x1fffff) == 0 \
7272 : ((v) & ~0x7fffff) == 0 \
7275 : ((v) & ~0xfffffff) == 0 \
7276 ? ((v) & ~0x3ffffff) == 0 \
7277 ? ((v) & ~0x1ffffff) == 0 \
7280 : ((v) & ~0x7ffffff) == 0 \
7283 : ((v) & ~0x3fffffff) == 0 \
7284 ? ((v) & ~0x1fffffff) == 0 \
7287 : ((v) & ~0x7fffffff) == 0 \
7292 * This routine generates the least number of instructions necessary to load
7293 * an absolute expression value into a register.
7296 load_register (int reg
, expressionS
*ep
, int dbl
)
7299 expressionS hi32
, lo32
;
7301 if (ep
->X_op
!= O_big
)
7303 gas_assert (ep
->X_op
== O_constant
);
7305 /* Sign-extending 32-bit constants makes their handling easier. */
7307 normalize_constant_expr (ep
);
7309 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
7311 /* We can handle 16 bit signed values with an addiu to
7312 $zero. No need to ever use daddiu here, since $zero and
7313 the result are always correct in 32 bit mode. */
7314 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7317 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
7319 /* We can handle 16 bit unsigned values with an ori to
7321 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7324 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
7326 /* 32 bit values require an lui. */
7327 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7328 if ((ep
->X_add_number
& 0xffff) != 0)
7329 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7334 /* The value is larger than 32 bits. */
7336 if (!dbl
|| HAVE_32BIT_GPRS
)
7340 sprintf_vma (value
, ep
->X_add_number
);
7341 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7342 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7346 if (ep
->X_op
!= O_big
)
7349 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7350 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7351 hi32
.X_add_number
&= 0xffffffff;
7353 lo32
.X_add_number
&= 0xffffffff;
7357 gas_assert (ep
->X_add_number
> 2);
7358 if (ep
->X_add_number
== 3)
7359 generic_bignum
[3] = 0;
7360 else if (ep
->X_add_number
> 4)
7361 as_bad (_("Number larger than 64 bits"));
7362 lo32
.X_op
= O_constant
;
7363 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
7364 hi32
.X_op
= O_constant
;
7365 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
7368 if (hi32
.X_add_number
== 0)
7373 unsigned long hi
, lo
;
7375 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
7377 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
7379 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7382 if (lo32
.X_add_number
& 0x80000000)
7384 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7385 if (lo32
.X_add_number
& 0xffff)
7386 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7391 /* Check for 16bit shifted constant. We know that hi32 is
7392 non-zero, so start the mask on the first bit of the hi32
7397 unsigned long himask
, lomask
;
7401 himask
= 0xffff >> (32 - shift
);
7402 lomask
= (0xffff << shift
) & 0xffffffff;
7406 himask
= 0xffff << (shift
- 32);
7409 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
7410 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
7414 tmp
.X_op
= O_constant
;
7416 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
7417 | (lo32
.X_add_number
>> shift
));
7419 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
7420 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7421 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7422 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7427 while (shift
<= (64 - 16));
7429 /* Find the bit number of the lowest one bit, and store the
7430 shifted value in hi/lo. */
7431 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
7432 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
7436 while ((lo
& 1) == 0)
7441 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
7447 while ((hi
& 1) == 0)
7456 /* Optimize if the shifted value is a (power of 2) - 1. */
7457 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
7458 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
7460 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
7465 /* This instruction will set the register to be all
7467 tmp
.X_op
= O_constant
;
7468 tmp
.X_add_number
= (offsetT
) -1;
7469 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7473 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7474 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
7476 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
7477 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7482 /* Sign extend hi32 before calling load_register, because we can
7483 generally get better code when we load a sign extended value. */
7484 if ((hi32
.X_add_number
& 0x80000000) != 0)
7485 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
7486 load_register (reg
, &hi32
, 0);
7489 if ((lo32
.X_add_number
& 0xffff0000) == 0)
7493 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
7501 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
7503 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7504 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
7510 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
7514 mid16
.X_add_number
>>= 16;
7515 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7516 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7519 if ((lo32
.X_add_number
& 0xffff) != 0)
7520 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7524 load_delay_nop (void)
7526 if (!gpr_interlocks
)
7527 macro_build (NULL
, "nop", "");
7530 /* Load an address into a register. */
7533 load_address (int reg
, expressionS
*ep
, int *used_at
)
7535 if (ep
->X_op
!= O_constant
7536 && ep
->X_op
!= O_symbol
)
7538 as_bad (_("expression too complex"));
7539 ep
->X_op
= O_constant
;
7542 if (ep
->X_op
== O_constant
)
7544 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
7548 if (mips_pic
== NO_PIC
)
7550 /* If this is a reference to a GP relative symbol, we want
7551 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7553 lui $reg,<sym> (BFD_RELOC_HI16_S)
7554 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7555 If we have an addend, we always use the latter form.
7557 With 64bit address space and a usable $at we want
7558 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7559 lui $at,<sym> (BFD_RELOC_HI16_S)
7560 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7561 daddiu $at,<sym> (BFD_RELOC_LO16)
7565 If $at is already in use, we use a path which is suboptimal
7566 on superscalar processors.
7567 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7568 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7570 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7572 daddiu $reg,<sym> (BFD_RELOC_LO16)
7574 For GP relative symbols in 64bit address space we can use
7575 the same sequence as in 32bit address space. */
7576 if (HAVE_64BIT_SYMBOLS
)
7578 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7579 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7581 relax_start (ep
->X_add_symbol
);
7582 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7583 mips_gp_register
, BFD_RELOC_GPREL16
);
7587 if (*used_at
== 0 && mips_opts
.at
)
7589 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7590 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
7591 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7592 BFD_RELOC_MIPS_HIGHER
);
7593 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
7594 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
7595 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
7600 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7601 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7602 BFD_RELOC_MIPS_HIGHER
);
7603 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7604 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
7605 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7606 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
7609 if (mips_relax
.sequence
)
7614 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7615 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7617 relax_start (ep
->X_add_symbol
);
7618 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7619 mips_gp_register
, BFD_RELOC_GPREL16
);
7622 macro_build_lui (ep
, reg
);
7623 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
7624 reg
, reg
, BFD_RELOC_LO16
);
7625 if (mips_relax
.sequence
)
7629 else if (!mips_big_got
)
7633 /* If this is a reference to an external symbol, we want
7634 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7636 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7638 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7639 If there is a constant, it must be added in after.
7641 If we have NewABI, we want
7642 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7643 unless we're referencing a global symbol with a non-zero
7644 offset, in which case cst must be added separately. */
7647 if (ep
->X_add_number
)
7649 ex
.X_add_number
= ep
->X_add_number
;
7650 ep
->X_add_number
= 0;
7651 relax_start (ep
->X_add_symbol
);
7652 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7653 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7654 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7655 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7656 ex
.X_op
= O_constant
;
7657 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7658 reg
, reg
, BFD_RELOC_LO16
);
7659 ep
->X_add_number
= ex
.X_add_number
;
7662 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7663 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7664 if (mips_relax
.sequence
)
7669 ex
.X_add_number
= ep
->X_add_number
;
7670 ep
->X_add_number
= 0;
7671 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7672 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7674 relax_start (ep
->X_add_symbol
);
7676 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7680 if (ex
.X_add_number
!= 0)
7682 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7683 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7684 ex
.X_op
= O_constant
;
7685 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7686 reg
, reg
, BFD_RELOC_LO16
);
7690 else if (mips_big_got
)
7694 /* This is the large GOT case. If this is a reference to an
7695 external symbol, we want
7696 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7698 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7700 Otherwise, for a reference to a local symbol in old ABI, we want
7701 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7703 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7704 If there is a constant, it must be added in after.
7706 In the NewABI, for local symbols, with or without offsets, we want:
7707 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7708 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7712 ex
.X_add_number
= ep
->X_add_number
;
7713 ep
->X_add_number
= 0;
7714 relax_start (ep
->X_add_symbol
);
7715 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7716 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7717 reg
, reg
, mips_gp_register
);
7718 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7719 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7720 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7721 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7722 else if (ex
.X_add_number
)
7724 ex
.X_op
= O_constant
;
7725 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7729 ep
->X_add_number
= ex
.X_add_number
;
7731 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7732 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7733 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7734 BFD_RELOC_MIPS_GOT_OFST
);
7739 ex
.X_add_number
= ep
->X_add_number
;
7740 ep
->X_add_number
= 0;
7741 relax_start (ep
->X_add_symbol
);
7742 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7743 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7744 reg
, reg
, mips_gp_register
);
7745 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7746 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7748 if (reg_needs_delay (mips_gp_register
))
7750 /* We need a nop before loading from $gp. This special
7751 check is required because the lui which starts the main
7752 instruction stream does not refer to $gp, and so will not
7753 insert the nop which may be required. */
7754 macro_build (NULL
, "nop", "");
7756 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7757 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7759 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7763 if (ex
.X_add_number
!= 0)
7765 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7766 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7767 ex
.X_op
= O_constant
;
7768 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7776 if (!mips_opts
.at
&& *used_at
== 1)
7777 as_bad (_("Macro used $at after \".set noat\""));
7780 /* Move the contents of register SOURCE into register DEST. */
7783 move_register (int dest
, int source
)
7785 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7786 instruction specifically requires a 32-bit one. */
7787 if (mips_opts
.micromips
7788 && !mips_opts
.insn32
7789 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7790 macro_build (NULL
, "move", "mp,mj", dest
, source
);
7792 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
7796 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7797 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7798 The two alternatives are:
7800 Global symbol Local sybmol
7801 ------------- ------------
7802 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7804 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7806 load_got_offset emits the first instruction and add_got_offset
7807 emits the second for a 16-bit offset or add_got_offset_hilo emits
7808 a sequence to add a 32-bit offset using a scratch register. */
7811 load_got_offset (int dest
, expressionS
*local
)
7816 global
.X_add_number
= 0;
7818 relax_start (local
->X_add_symbol
);
7819 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7820 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7822 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
7823 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7828 add_got_offset (int dest
, expressionS
*local
)
7832 global
.X_op
= O_constant
;
7833 global
.X_op_symbol
= NULL
;
7834 global
.X_add_symbol
= NULL
;
7835 global
.X_add_number
= local
->X_add_number
;
7837 relax_start (local
->X_add_symbol
);
7838 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
7839 dest
, dest
, BFD_RELOC_LO16
);
7841 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
7846 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
7849 int hold_mips_optimize
;
7851 global
.X_op
= O_constant
;
7852 global
.X_op_symbol
= NULL
;
7853 global
.X_add_symbol
= NULL
;
7854 global
.X_add_number
= local
->X_add_number
;
7856 relax_start (local
->X_add_symbol
);
7857 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
7859 /* Set mips_optimize around the lui instruction to avoid
7860 inserting an unnecessary nop after the lw. */
7861 hold_mips_optimize
= mips_optimize
;
7863 macro_build_lui (&global
, tmp
);
7864 mips_optimize
= hold_mips_optimize
;
7865 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
7868 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
7871 /* Emit a sequence of instructions to emulate a branch likely operation.
7872 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7873 is its complementing branch with the original condition negated.
7874 CALL is set if the original branch specified the link operation.
7875 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7877 Code like this is produced in the noreorder mode:
7882 delay slot (executed only if branch taken)
7890 delay slot (executed only if branch taken)
7893 In the reorder mode the delay slot would be filled with a nop anyway,
7894 so code produced is simply:
7899 This function is used when producing code for the microMIPS ASE that
7900 does not implement branch likely instructions in hardware. */
7903 macro_build_branch_likely (const char *br
, const char *brneg
,
7904 int call
, expressionS
*ep
, const char *fmt
,
7905 unsigned int sreg
, unsigned int treg
)
7907 int noreorder
= mips_opts
.noreorder
;
7910 gas_assert (mips_opts
.micromips
);
7914 micromips_label_expr (&expr1
);
7915 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
7916 macro_build (NULL
, "nop", "");
7917 macro_build (ep
, call
? "bal" : "b", "p");
7919 /* Set to true so that append_insn adds a label. */
7920 emit_branch_likely_macro
= TRUE
;
7924 macro_build (ep
, br
, fmt
, sreg
, treg
);
7925 macro_build (NULL
, "nop", "");
7930 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7931 the condition code tested. EP specifies the branch target. */
7934 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
7961 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
7964 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7965 the register tested. EP specifies the branch target. */
7968 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
7970 const char *brneg
= NULL
;
7980 br
= mips_opts
.micromips
? "bgez" : "bgezl";
7984 gas_assert (mips_opts
.micromips
);
7985 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
7993 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8000 br
= mips_opts
.micromips
? "blez" : "blezl";
8007 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8011 gas_assert (mips_opts
.micromips
);
8012 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8019 if (mips_opts
.micromips
&& brneg
)
8020 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8022 macro_build (ep
, br
, "s,p", sreg
);
8025 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8026 TREG as the registers tested. EP specifies the branch target. */
8029 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8030 unsigned int sreg
, unsigned int treg
)
8032 const char *brneg
= NULL
;
8044 br
= mips_opts
.micromips
? "beq" : "beql";
8053 br
= mips_opts
.micromips
? "bne" : "bnel";
8059 if (mips_opts
.micromips
&& brneg
)
8060 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8062 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8065 /* Return the high part that should be loaded in order to make the low
8066 part of VALUE accessible using an offset of OFFBITS bits. */
8069 offset_high_part (offsetT value
, unsigned int offbits
)
8076 bias
= 1 << (offbits
- 1);
8077 low_mask
= bias
* 2 - 1;
8078 return (value
+ bias
) & ~low_mask
;
8081 /* Return true if the value stored in offset_expr and offset_reloc
8082 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8083 amount that the caller wants to add without inducing overflow
8084 and ALIGN is the known alignment of the value in bytes. */
8087 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
8091 /* Accept any relocation operator if overflow isn't a concern. */
8092 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8095 /* These relocations are guaranteed not to overflow in correct links. */
8096 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
8097 || gprel16_reloc_p (*offset_reloc
))
8100 if (offset_expr
.X_op
== O_constant
8101 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
8102 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
8109 * This routine implements the seemingly endless macro or synthesized
8110 * instructions and addressing modes in the mips assembly language. Many
8111 * of these macros are simple and are similar to each other. These could
8112 * probably be handled by some kind of table or grammar approach instead of
8113 * this verbose method. Others are not simple macros but are more like
8114 * optimizing code generation.
8115 * One interesting optimization is when several store macros appear
8116 * consecutively that would load AT with the upper half of the same address.
8117 * The ensuing load upper instructions are ommited. This implies some kind
8118 * of global optimization. We currently only optimize within a single macro.
8119 * For many of the load and store macros if the address is specified as a
8120 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8121 * first load register 'at' with zero and use it as the base register. The
8122 * mips assembler simply uses register $zero. Just one tiny optimization
8126 macro (struct mips_cl_insn
*ip
, char *str
)
8128 unsigned int treg
, sreg
, dreg
, breg
;
8129 unsigned int tempreg
;
8132 expressionS label_expr
;
8147 bfd_boolean large_offset
;
8149 int hold_mips_optimize
;
8152 gas_assert (! mips_opts
.mips16
);
8154 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
8155 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
8156 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
8157 mask
= ip
->insn_mo
->mask
;
8159 label_expr
.X_op
= O_constant
;
8160 label_expr
.X_op_symbol
= NULL
;
8161 label_expr
.X_add_symbol
= NULL
;
8162 label_expr
.X_add_number
= 0;
8164 expr1
.X_op
= O_constant
;
8165 expr1
.X_op_symbol
= NULL
;
8166 expr1
.X_add_symbol
= NULL
;
8167 expr1
.X_add_number
= 1;
8183 if (mips_opts
.micromips
)
8184 micromips_label_expr (&label_expr
);
8186 label_expr
.X_add_number
= 8;
8187 macro_build (&label_expr
, "bgez", "s,p", sreg
);
8189 macro_build (NULL
, "nop", "");
8191 move_register (dreg
, sreg
);
8192 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
8193 if (mips_opts
.micromips
)
8194 micromips_add_label ();
8211 if (!mips_opts
.micromips
)
8213 if (imm_expr
.X_op
== O_constant
8214 && imm_expr
.X_add_number
>= -0x200
8215 && imm_expr
.X_add_number
< 0x200)
8217 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
8226 if (imm_expr
.X_op
== O_constant
8227 && imm_expr
.X_add_number
>= -0x8000
8228 && imm_expr
.X_add_number
< 0x8000)
8230 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
8235 load_register (AT
, &imm_expr
, dbl
);
8236 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
8255 if (imm_expr
.X_op
== O_constant
8256 && imm_expr
.X_add_number
>= 0
8257 && imm_expr
.X_add_number
< 0x10000)
8259 if (mask
!= M_NOR_I
)
8260 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
8263 macro_build (&imm_expr
, "ori", "t,r,i",
8264 treg
, sreg
, BFD_RELOC_LO16
);
8265 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
8271 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8272 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
8276 switch (imm_expr
.X_add_number
)
8279 macro_build (NULL
, "nop", "");
8282 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
8286 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
8287 (int) imm_expr
.X_add_number
);
8290 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8291 (unsigned long) imm_expr
.X_add_number
);
8300 gas_assert (mips_opts
.micromips
);
8301 macro_build_branch_ccl (mask
, &offset_expr
,
8302 EXTRACT_OPERAND (1, BCC
, *ip
));
8309 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8315 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
8320 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
8327 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
8329 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
8333 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
8334 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8335 &offset_expr
, AT
, ZERO
);
8345 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
8351 /* Check for > max integer. */
8352 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8355 /* Result is always false. */
8357 macro_build (NULL
, "nop", "");
8359 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
8362 if (imm_expr
.X_op
!= O_constant
)
8363 as_bad (_("Unsupported large constant"));
8364 ++imm_expr
.X_add_number
;
8368 if (mask
== M_BGEL_I
)
8370 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8372 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
8373 &offset_expr
, sreg
);
8376 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8378 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
8379 &offset_expr
, sreg
);
8382 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
8385 /* result is always true */
8386 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
8387 macro_build (&offset_expr
, "b", "p");
8392 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8393 &offset_expr
, AT
, ZERO
);
8402 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8403 &offset_expr
, ZERO
, treg
);
8407 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
8408 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8409 &offset_expr
, AT
, ZERO
);
8418 && imm_expr
.X_op
== O_constant
8419 && imm_expr
.X_add_number
== -1))
8421 if (imm_expr
.X_op
!= O_constant
)
8422 as_bad (_("Unsupported large constant"));
8423 ++imm_expr
.X_add_number
;
8427 if (mask
== M_BGEUL_I
)
8429 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8431 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8432 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8433 &offset_expr
, sreg
, ZERO
);
8438 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8439 &offset_expr
, AT
, ZERO
);
8447 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
8449 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
8453 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
8454 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8455 &offset_expr
, AT
, ZERO
);
8463 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8464 &offset_expr
, sreg
, ZERO
);
8470 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
8471 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8472 &offset_expr
, AT
, ZERO
);
8480 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
8482 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
8486 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
8487 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8488 &offset_expr
, AT
, ZERO
);
8495 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8497 if (imm_expr
.X_op
!= O_constant
)
8498 as_bad (_("Unsupported large constant"));
8499 ++imm_expr
.X_add_number
;
8503 if (mask
== M_BLTL_I
)
8505 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8506 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8507 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8508 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
8513 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8514 &offset_expr
, AT
, ZERO
);
8522 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8523 &offset_expr
, sreg
, ZERO
);
8529 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
8530 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8531 &offset_expr
, AT
, ZERO
);
8540 && imm_expr
.X_op
== O_constant
8541 && imm_expr
.X_add_number
== -1))
8543 if (imm_expr
.X_op
!= O_constant
)
8544 as_bad (_("Unsupported large constant"));
8545 ++imm_expr
.X_add_number
;
8549 if (mask
== M_BLTUL_I
)
8551 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8553 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8554 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8555 &offset_expr
, sreg
, ZERO
);
8560 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8561 &offset_expr
, AT
, ZERO
);
8569 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
8571 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
8575 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
8576 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8577 &offset_expr
, AT
, ZERO
);
8587 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8588 &offset_expr
, ZERO
, treg
);
8592 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
8593 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8594 &offset_expr
, AT
, ZERO
);
8600 /* Use unsigned arithmetic. */
8604 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8606 as_bad (_("Unsupported large constant"));
8611 pos
= imm_expr
.X_add_number
;
8612 size
= imm2_expr
.X_add_number
;
8617 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8620 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8622 report_bad_field (pos
, size
);
8626 if (size
<= 32 && pos
< 32)
8631 else if (size
<= 32)
8641 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8648 /* Use unsigned arithmetic. */
8652 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8654 as_bad (_("Unsupported large constant"));
8659 pos
= imm_expr
.X_add_number
;
8660 size
= imm2_expr
.X_add_number
;
8665 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8668 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8670 report_bad_field (pos
, size
);
8674 if (pos
< 32 && (pos
+ size
- 1) < 32)
8689 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
8690 (int) (pos
+ size
- 1));
8706 as_warn (_("Divide by zero."));
8708 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8710 macro_build (NULL
, "break", BRK_FMT
, 7);
8717 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8718 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8722 if (mips_opts
.micromips
)
8723 micromips_label_expr (&label_expr
);
8725 label_expr
.X_add_number
= 8;
8726 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8727 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
8728 macro_build (NULL
, "break", BRK_FMT
, 7);
8729 if (mips_opts
.micromips
)
8730 micromips_add_label ();
8732 expr1
.X_add_number
= -1;
8734 load_register (AT
, &expr1
, dbl
);
8735 if (mips_opts
.micromips
)
8736 micromips_label_expr (&label_expr
);
8738 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
8739 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
8742 expr1
.X_add_number
= 1;
8743 load_register (AT
, &expr1
, dbl
);
8744 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
8748 expr1
.X_add_number
= 0x80000000;
8749 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
8753 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
8754 /* We want to close the noreorder block as soon as possible, so
8755 that later insns are available for delay slot filling. */
8760 if (mips_opts
.micromips
)
8761 micromips_label_expr (&label_expr
);
8763 label_expr
.X_add_number
= 8;
8764 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
8765 macro_build (NULL
, "nop", "");
8767 /* We want to close the noreorder block as soon as possible, so
8768 that later insns are available for delay slot filling. */
8771 macro_build (NULL
, "break", BRK_FMT
, 6);
8773 if (mips_opts
.micromips
)
8774 micromips_add_label ();
8775 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
8814 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8816 as_warn (_("Divide by zero."));
8818 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8820 macro_build (NULL
, "break", BRK_FMT
, 7);
8823 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8825 if (strcmp (s2
, "mflo") == 0)
8826 move_register (dreg
, sreg
);
8828 move_register (dreg
, ZERO
);
8831 if (imm_expr
.X_op
== O_constant
8832 && imm_expr
.X_add_number
== -1
8833 && s
[strlen (s
) - 1] != 'u')
8835 if (strcmp (s2
, "mflo") == 0)
8837 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
8840 move_register (dreg
, ZERO
);
8845 load_register (AT
, &imm_expr
, dbl
);
8846 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
8847 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8869 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
8870 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8871 /* We want to close the noreorder block as soon as possible, so
8872 that later insns are available for delay slot filling. */
8877 if (mips_opts
.micromips
)
8878 micromips_label_expr (&label_expr
);
8880 label_expr
.X_add_number
= 8;
8881 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
8882 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
8884 /* We want to close the noreorder block as soon as possible, so
8885 that later insns are available for delay slot filling. */
8887 macro_build (NULL
, "break", BRK_FMT
, 7);
8888 if (mips_opts
.micromips
)
8889 micromips_add_label ();
8891 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
8903 /* Load the address of a symbol into a register. If breg is not
8904 zero, we then add a base register to it. */
8906 if (dbl
&& HAVE_32BIT_GPRS
)
8907 as_warn (_("dla used to load 32-bit register"));
8909 if (!dbl
&& HAVE_64BIT_OBJECTS
)
8910 as_warn (_("la used to load 64-bit address"));
8912 if (small_offset_p (0, align
, 16))
8914 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", treg
, breg
,
8915 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8919 if (mips_opts
.at
&& (treg
== breg
))
8929 if (offset_expr
.X_op
!= O_symbol
8930 && offset_expr
.X_op
!= O_constant
)
8932 as_bad (_("Expression too complex"));
8933 offset_expr
.X_op
= O_constant
;
8936 if (offset_expr
.X_op
== O_constant
)
8937 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
8938 else if (mips_pic
== NO_PIC
)
8940 /* If this is a reference to a GP relative symbol, we want
8941 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8943 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8944 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8945 If we have a constant, we need two instructions anyhow,
8946 so we may as well always use the latter form.
8948 With 64bit address space and a usable $at we want
8949 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8950 lui $at,<sym> (BFD_RELOC_HI16_S)
8951 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8952 daddiu $at,<sym> (BFD_RELOC_LO16)
8954 daddu $tempreg,$tempreg,$at
8956 If $at is already in use, we use a path which is suboptimal
8957 on superscalar processors.
8958 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8959 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8961 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8963 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8965 For GP relative symbols in 64bit address space we can use
8966 the same sequence as in 32bit address space. */
8967 if (HAVE_64BIT_SYMBOLS
)
8969 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8970 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8972 relax_start (offset_expr
.X_add_symbol
);
8973 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8974 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
8978 if (used_at
== 0 && mips_opts
.at
)
8980 macro_build (&offset_expr
, "lui", LUI_FMT
,
8981 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8982 macro_build (&offset_expr
, "lui", LUI_FMT
,
8983 AT
, BFD_RELOC_HI16_S
);
8984 macro_build (&offset_expr
, "daddiu", "t,r,j",
8985 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8986 macro_build (&offset_expr
, "daddiu", "t,r,j",
8987 AT
, AT
, BFD_RELOC_LO16
);
8988 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8989 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8994 macro_build (&offset_expr
, "lui", LUI_FMT
,
8995 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
8996 macro_build (&offset_expr
, "daddiu", "t,r,j",
8997 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
8998 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8999 macro_build (&offset_expr
, "daddiu", "t,r,j",
9000 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9001 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9002 macro_build (&offset_expr
, "daddiu", "t,r,j",
9003 tempreg
, tempreg
, BFD_RELOC_LO16
);
9006 if (mips_relax
.sequence
)
9011 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9012 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9014 relax_start (offset_expr
.X_add_symbol
);
9015 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9016 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9019 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9020 as_bad (_("Offset too large"));
9021 macro_build_lui (&offset_expr
, tempreg
);
9022 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9023 tempreg
, tempreg
, BFD_RELOC_LO16
);
9024 if (mips_relax
.sequence
)
9028 else if (!mips_big_got
&& !HAVE_NEWABI
)
9030 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9032 /* If this is a reference to an external symbol, and there
9033 is no constant, we want
9034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9035 or for lca or if tempreg is PIC_CALL_REG
9036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9037 For a local symbol, we want
9038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9040 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9042 If we have a small constant, and this is a reference to
9043 an external symbol, we want
9044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9046 addiu $tempreg,$tempreg,<constant>
9047 For a local symbol, we want the same instruction
9048 sequence, but we output a BFD_RELOC_LO16 reloc on the
9051 If we have a large constant, and this is a reference to
9052 an external symbol, we want
9053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9054 lui $at,<hiconstant>
9055 addiu $at,$at,<loconstant>
9056 addu $tempreg,$tempreg,$at
9057 For a local symbol, we want the same instruction
9058 sequence, but we output a BFD_RELOC_LO16 reloc on the
9062 if (offset_expr
.X_add_number
== 0)
9064 if (mips_pic
== SVR4_PIC
9066 && (call
|| tempreg
== PIC_CALL_REG
))
9067 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9069 relax_start (offset_expr
.X_add_symbol
);
9070 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9071 lw_reloc_type
, mips_gp_register
);
9074 /* We're going to put in an addu instruction using
9075 tempreg, so we may as well insert the nop right
9080 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9081 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9083 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9084 tempreg
, tempreg
, BFD_RELOC_LO16
);
9086 /* FIXME: If breg == 0, and the next instruction uses
9087 $tempreg, then if this variant case is used an extra
9088 nop will be generated. */
9090 else if (offset_expr
.X_add_number
>= -0x8000
9091 && offset_expr
.X_add_number
< 0x8000)
9093 load_got_offset (tempreg
, &offset_expr
);
9095 add_got_offset (tempreg
, &offset_expr
);
9099 expr1
.X_add_number
= offset_expr
.X_add_number
;
9100 offset_expr
.X_add_number
=
9101 SEXT_16BIT (offset_expr
.X_add_number
);
9102 load_got_offset (tempreg
, &offset_expr
);
9103 offset_expr
.X_add_number
= expr1
.X_add_number
;
9104 /* If we are going to add in a base register, and the
9105 target register and the base register are the same,
9106 then we are using AT as a temporary register. Since
9107 we want to load the constant into AT, we add our
9108 current AT (from the global offset table) and the
9109 register into the register now, and pretend we were
9110 not using a base register. */
9114 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9119 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9123 else if (!mips_big_got
&& HAVE_NEWABI
)
9125 int add_breg_early
= 0;
9127 /* If this is a reference to an external, and there is no
9128 constant, or local symbol (*), with or without a
9130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9131 or for lca or if tempreg is PIC_CALL_REG
9132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9134 If we have a small constant, and this is a reference to
9135 an external symbol, we want
9136 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9137 addiu $tempreg,$tempreg,<constant>
9139 If we have a large constant, and this is a reference to
9140 an external symbol, we want
9141 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9142 lui $at,<hiconstant>
9143 addiu $at,$at,<loconstant>
9144 addu $tempreg,$tempreg,$at
9146 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9147 local symbols, even though it introduces an additional
9150 if (offset_expr
.X_add_number
)
9152 expr1
.X_add_number
= offset_expr
.X_add_number
;
9153 offset_expr
.X_add_number
= 0;
9155 relax_start (offset_expr
.X_add_symbol
);
9156 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9157 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9159 if (expr1
.X_add_number
>= -0x8000
9160 && expr1
.X_add_number
< 0x8000)
9162 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9163 tempreg
, tempreg
, BFD_RELOC_LO16
);
9165 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9167 /* If we are going to add in a base register, and the
9168 target register and the base register are the same,
9169 then we are using AT as a temporary register. Since
9170 we want to load the constant into AT, we add our
9171 current AT (from the global offset table) and the
9172 register into the register now, and pretend we were
9173 not using a base register. */
9178 gas_assert (tempreg
== AT
);
9179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9185 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9186 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9192 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9195 offset_expr
.X_add_number
= expr1
.X_add_number
;
9197 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9198 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9201 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9202 treg
, tempreg
, breg
);
9208 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
9210 relax_start (offset_expr
.X_add_symbol
);
9211 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9212 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
9214 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9215 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9220 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9221 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9224 else if (mips_big_got
&& !HAVE_NEWABI
)
9227 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9228 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9229 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9231 /* This is the large GOT case. If this is a reference to an
9232 external symbol, and there is no constant, we want
9233 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9234 addu $tempreg,$tempreg,$gp
9235 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9236 or for lca or if tempreg is PIC_CALL_REG
9237 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9238 addu $tempreg,$tempreg,$gp
9239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9240 For a local symbol, we want
9241 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9243 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9245 If we have a small constant, and this is a reference to
9246 an external symbol, we want
9247 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9248 addu $tempreg,$tempreg,$gp
9249 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9251 addiu $tempreg,$tempreg,<constant>
9252 For a local symbol, we want
9253 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9255 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9257 If we have a large constant, and this is a reference to
9258 an external symbol, we want
9259 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9260 addu $tempreg,$tempreg,$gp
9261 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9262 lui $at,<hiconstant>
9263 addiu $at,$at,<loconstant>
9264 addu $tempreg,$tempreg,$at
9265 For a local symbol, we want
9266 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9267 lui $at,<hiconstant>
9268 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9269 addu $tempreg,$tempreg,$at
9272 expr1
.X_add_number
= offset_expr
.X_add_number
;
9273 offset_expr
.X_add_number
= 0;
9274 relax_start (offset_expr
.X_add_symbol
);
9275 gpdelay
= reg_needs_delay (mips_gp_register
);
9276 if (expr1
.X_add_number
== 0 && breg
== 0
9277 && (call
|| tempreg
== PIC_CALL_REG
))
9279 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9280 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9282 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9283 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9284 tempreg
, tempreg
, mips_gp_register
);
9285 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9286 tempreg
, lw_reloc_type
, tempreg
);
9287 if (expr1
.X_add_number
== 0)
9291 /* We're going to put in an addu instruction using
9292 tempreg, so we may as well insert the nop right
9297 else if (expr1
.X_add_number
>= -0x8000
9298 && expr1
.X_add_number
< 0x8000)
9301 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9302 tempreg
, tempreg
, BFD_RELOC_LO16
);
9306 /* If we are going to add in a base register, and the
9307 target register and the base register are the same,
9308 then we are using AT as a temporary register. Since
9309 we want to load the constant into AT, we add our
9310 current AT (from the global offset table) and the
9311 register into the register now, and pretend we were
9312 not using a base register. */
9317 gas_assert (tempreg
== AT
);
9319 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9324 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9325 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9329 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
9334 /* This is needed because this instruction uses $gp, but
9335 the first instruction on the main stream does not. */
9336 macro_build (NULL
, "nop", "");
9339 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9340 local_reloc_type
, mips_gp_register
);
9341 if (expr1
.X_add_number
>= -0x8000
9342 && expr1
.X_add_number
< 0x8000)
9345 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9346 tempreg
, tempreg
, BFD_RELOC_LO16
);
9347 /* FIXME: If add_number is 0, and there was no base
9348 register, the external symbol case ended with a load,
9349 so if the symbol turns out to not be external, and
9350 the next instruction uses tempreg, an unnecessary nop
9351 will be inserted. */
9357 /* We must add in the base register now, as in the
9358 external symbol case. */
9359 gas_assert (tempreg
== AT
);
9361 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9364 /* We set breg to 0 because we have arranged to add
9365 it in in both cases. */
9369 macro_build_lui (&expr1
, AT
);
9370 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9371 AT
, AT
, BFD_RELOC_LO16
);
9372 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9373 tempreg
, tempreg
, AT
);
9378 else if (mips_big_got
&& HAVE_NEWABI
)
9380 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9381 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9382 int add_breg_early
= 0;
9384 /* This is the large GOT case. If this is a reference to an
9385 external symbol, and there is no constant, we want
9386 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9387 add $tempreg,$tempreg,$gp
9388 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9389 or for lca or if tempreg is PIC_CALL_REG
9390 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9391 add $tempreg,$tempreg,$gp
9392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9394 If we have a small constant, and this is a reference to
9395 an external symbol, we want
9396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9397 add $tempreg,$tempreg,$gp
9398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9399 addi $tempreg,$tempreg,<constant>
9401 If we have a large constant, and this is a reference to
9402 an external symbol, we want
9403 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9404 addu $tempreg,$tempreg,$gp
9405 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9406 lui $at,<hiconstant>
9407 addi $at,$at,<loconstant>
9408 add $tempreg,$tempreg,$at
9410 If we have NewABI, and we know it's a local symbol, we want
9411 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9412 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9413 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9415 relax_start (offset_expr
.X_add_symbol
);
9417 expr1
.X_add_number
= offset_expr
.X_add_number
;
9418 offset_expr
.X_add_number
= 0;
9420 if (expr1
.X_add_number
== 0 && breg
== 0
9421 && (call
|| tempreg
== PIC_CALL_REG
))
9423 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9424 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9426 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9427 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9428 tempreg
, tempreg
, mips_gp_register
);
9429 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9430 tempreg
, lw_reloc_type
, tempreg
);
9432 if (expr1
.X_add_number
== 0)
9434 else if (expr1
.X_add_number
>= -0x8000
9435 && expr1
.X_add_number
< 0x8000)
9437 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9438 tempreg
, tempreg
, BFD_RELOC_LO16
);
9440 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9442 /* If we are going to add in a base register, and the
9443 target register and the base register are the same,
9444 then we are using AT as a temporary register. Since
9445 we want to load the constant into AT, we add our
9446 current AT (from the global offset table) and the
9447 register into the register now, and pretend we were
9448 not using a base register. */
9453 gas_assert (tempreg
== AT
);
9454 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9460 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9466 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9469 offset_expr
.X_add_number
= expr1
.X_add_number
;
9470 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9471 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9472 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9473 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
9476 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9477 treg
, tempreg
, breg
);
9487 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
9491 gas_assert (!mips_opts
.micromips
);
9492 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x01);
9496 gas_assert (!mips_opts
.micromips
);
9497 macro_build (NULL
, "c2", "C", 0x02);
9501 gas_assert (!mips_opts
.micromips
);
9502 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x02);
9506 gas_assert (!mips_opts
.micromips
);
9507 macro_build (NULL
, "c2", "C", 3);
9511 gas_assert (!mips_opts
.micromips
);
9512 macro_build (NULL
, "c2", "C", (treg
<< 16) | 0x03);
9516 /* The j instruction may not be used in PIC code, since it
9517 requires an absolute address. We convert it to a b
9519 if (mips_pic
== NO_PIC
)
9520 macro_build (&offset_expr
, "j", "a");
9522 macro_build (&offset_expr
, "b", "p");
9525 /* The jal instructions must be handled as macros because when
9526 generating PIC code they expand to multi-instruction
9527 sequences. Normally they are simple instructions. */
9532 gas_assert (mips_opts
.micromips
);
9533 if (mips_opts
.insn32
)
9535 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9545 if (mips_pic
== NO_PIC
)
9547 s
= jals
? "jalrs" : "jalr";
9548 if (mips_opts
.micromips
9549 && !mips_opts
.insn32
9551 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9552 macro_build (NULL
, s
, "mj", sreg
);
9554 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9558 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
9559 && mips_cprestore_offset
>= 0);
9561 if (sreg
!= PIC_CALL_REG
)
9562 as_warn (_("MIPS PIC call to register other than $25"));
9564 s
= ((mips_opts
.micromips
9565 && !mips_opts
.insn32
9566 && (!mips_opts
.noreorder
|| cprestore
))
9567 ? "jalrs" : "jalr");
9568 if (mips_opts
.micromips
9569 && !mips_opts
.insn32
9571 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9572 macro_build (NULL
, s
, "mj", sreg
);
9574 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
9575 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
9577 if (mips_cprestore_offset
< 0)
9578 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9581 if (!mips_frame_reg_valid
)
9583 as_warn (_("No .frame pseudo-op used in PIC code"));
9584 /* Quiet this warning. */
9585 mips_frame_reg_valid
= 1;
9587 if (!mips_cprestore_valid
)
9589 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9590 /* Quiet this warning. */
9591 mips_cprestore_valid
= 1;
9593 if (mips_opts
.noreorder
)
9594 macro_build (NULL
, "nop", "");
9595 expr1
.X_add_number
= mips_cprestore_offset
;
9596 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9599 HAVE_64BIT_ADDRESSES
);
9607 gas_assert (mips_opts
.micromips
);
9608 if (mips_opts
.insn32
)
9610 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9616 if (mips_pic
== NO_PIC
)
9617 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
9618 else if (mips_pic
== SVR4_PIC
)
9620 /* If this is a reference to an external symbol, and we are
9621 using a small GOT, we want
9622 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9626 lw $gp,cprestore($sp)
9627 The cprestore value is set using the .cprestore
9628 pseudo-op. If we are using a big GOT, we want
9629 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9631 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9635 lw $gp,cprestore($sp)
9636 If the symbol is not external, we want
9637 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9639 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9642 lw $gp,cprestore($sp)
9644 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9645 sequences above, minus nops, unless the symbol is local,
9646 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9652 relax_start (offset_expr
.X_add_symbol
);
9653 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9654 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9657 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9658 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
9664 relax_start (offset_expr
.X_add_symbol
);
9665 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9666 BFD_RELOC_MIPS_CALL_HI16
);
9667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9668 PIC_CALL_REG
, mips_gp_register
);
9669 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9670 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9673 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9674 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
9676 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9677 PIC_CALL_REG
, PIC_CALL_REG
,
9678 BFD_RELOC_MIPS_GOT_OFST
);
9682 macro_build_jalr (&offset_expr
, 0);
9686 relax_start (offset_expr
.X_add_symbol
);
9689 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9690 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9699 gpdelay
= reg_needs_delay (mips_gp_register
);
9700 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9701 BFD_RELOC_MIPS_CALL_HI16
);
9702 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9703 PIC_CALL_REG
, mips_gp_register
);
9704 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9705 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9710 macro_build (NULL
, "nop", "");
9712 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9713 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
9716 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9717 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
9719 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
9721 if (mips_cprestore_offset
< 0)
9722 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9725 if (!mips_frame_reg_valid
)
9727 as_warn (_("No .frame pseudo-op used in PIC code"));
9728 /* Quiet this warning. */
9729 mips_frame_reg_valid
= 1;
9731 if (!mips_cprestore_valid
)
9733 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9734 /* Quiet this warning. */
9735 mips_cprestore_valid
= 1;
9737 if (mips_opts
.noreorder
)
9738 macro_build (NULL
, "nop", "");
9739 expr1
.X_add_number
= mips_cprestore_offset
;
9740 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9743 HAVE_64BIT_ADDRESSES
);
9747 else if (mips_pic
== VXWORKS_PIC
)
9748 as_bad (_("Non-PIC jump used in PIC library"));
9826 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9832 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
9857 gas_assert (!mips_opts
.micromips
);
9860 /* Itbl support may require additional care here. */
9866 /* Itbl support may require additional care here. */
9872 offbits
= (mips_opts
.micromips
? 12 : 16);
9873 /* Itbl support may require additional care here. */
9877 gas_assert (!mips_opts
.micromips
);
9880 /* Itbl support may require additional care here. */
9886 offbits
= (mips_opts
.micromips
? 12 : 16);
9891 offbits
= (mips_opts
.micromips
? 12 : 16);
9896 /* Itbl support may require additional care here. */
9902 offbits
= (mips_opts
.micromips
? 12 : 16);
9903 /* Itbl support may require additional care here. */
9909 /* Itbl support may require additional care here. */
9915 /* Itbl support may require additional care here. */
9921 offbits
= (mips_opts
.micromips
? 12 : 16);
9926 offbits
= (mips_opts
.micromips
? 12 : 16);
9931 offbits
= (mips_opts
.micromips
? 12 : 16);
9936 offbits
= (mips_opts
.micromips
? 12 : 16);
9941 offbits
= (mips_opts
.micromips
? 12 : 16);
9944 gas_assert (mips_opts
.micromips
);
9951 gas_assert (mips_opts
.micromips
);
9958 gas_assert (mips_opts
.micromips
);
9964 gas_assert (mips_opts
.micromips
);
9971 /* We don't want to use $0 as tempreg. */
9972 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
9975 tempreg
= treg
+ lp
;
9991 gas_assert (!mips_opts
.micromips
);
9994 /* Itbl support may require additional care here. */
10000 /* Itbl support may require additional care here. */
10006 offbits
= (mips_opts
.micromips
? 12 : 16);
10007 /* Itbl support may require additional care here. */
10011 gas_assert (!mips_opts
.micromips
);
10014 /* Itbl support may require additional care here. */
10020 offbits
= (mips_opts
.micromips
? 12 : 16);
10025 offbits
= (mips_opts
.micromips
? 12 : 16);
10030 offbits
= (mips_opts
.micromips
? 12 : 16);
10035 offbits
= (mips_opts
.micromips
? 12 : 16);
10039 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10040 offbits
= (mips_opts
.micromips
? 12 : 16);
10049 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10050 offbits
= (mips_opts
.micromips
? 12 : 16);
10061 /* Itbl support may require additional care here. */
10066 offbits
= (mips_opts
.micromips
? 12 : 16);
10067 /* Itbl support may require additional care here. */
10073 /* Itbl support may require additional care here. */
10077 gas_assert (!mips_opts
.micromips
);
10080 /* Itbl support may require additional care here. */
10086 offbits
= (mips_opts
.micromips
? 12 : 16);
10091 offbits
= (mips_opts
.micromips
? 12 : 16);
10094 gas_assert (mips_opts
.micromips
);
10100 gas_assert (mips_opts
.micromips
);
10106 gas_assert (mips_opts
.micromips
);
10112 gas_assert (mips_opts
.micromips
);
10120 if (small_offset_p (0, align
, 16))
10122 /* The first case exists for M_LD_AB and M_SD_AB, which are
10123 macros for o32 but which should act like normal instructions
10126 macro_build (&offset_expr
, s
, fmt
, treg
, -1, offset_reloc
[0],
10127 offset_reloc
[1], offset_reloc
[2], breg
);
10128 else if (small_offset_p (0, align
, offbits
))
10131 macro_build (NULL
, s
, fmt
, treg
, breg
);
10133 macro_build (NULL
, s
, fmt
, treg
,
10134 (int) offset_expr
.X_add_number
, breg
);
10140 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10141 tempreg
, breg
, -1, offset_reloc
[0],
10142 offset_reloc
[1], offset_reloc
[2]);
10144 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
10146 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
10154 if (offset_expr
.X_op
!= O_constant
10155 && offset_expr
.X_op
!= O_symbol
)
10157 as_bad (_("Expression too complex"));
10158 offset_expr
.X_op
= O_constant
;
10161 if (HAVE_32BIT_ADDRESSES
10162 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10166 sprintf_vma (value
, offset_expr
.X_add_number
);
10167 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10170 /* A constant expression in PIC code can be handled just as it
10171 is in non PIC code. */
10172 if (offset_expr
.X_op
== O_constant
)
10174 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
10175 offbits
== 0 ? 16 : offbits
);
10176 offset_expr
.X_add_number
-= expr1
.X_add_number
;
10178 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
10180 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10181 tempreg
, tempreg
, breg
);
10184 if (offset_expr
.X_add_number
!= 0)
10185 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
10186 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
10187 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
10189 else if (offbits
== 16)
10190 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10192 macro_build (NULL
, s
, fmt
, treg
,
10193 (int) offset_expr
.X_add_number
, tempreg
);
10195 else if (offbits
!= 16)
10197 /* The offset field is too narrow to be used for a low-part
10198 relocation, so load the whole address into the auxillary
10200 load_address (tempreg
, &offset_expr
, &used_at
);
10202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10203 tempreg
, tempreg
, breg
);
10205 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
10207 macro_build (NULL
, s
, fmt
, treg
, 0, tempreg
);
10209 else if (mips_pic
== NO_PIC
)
10211 /* If this is a reference to a GP relative symbol, and there
10212 is no base register, we want
10213 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10214 Otherwise, if there is no base register, we want
10215 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10216 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10217 If we have a constant, we need two instructions anyhow,
10218 so we always use the latter form.
10220 If we have a base register, and this is a reference to a
10221 GP relative symbol, we want
10222 addu $tempreg,$breg,$gp
10223 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
10225 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10226 addu $tempreg,$tempreg,$breg
10227 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10228 With a constant we always use the latter case.
10230 With 64bit address space and no base register and $at usable,
10232 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10233 lui $at,<sym> (BFD_RELOC_HI16_S)
10234 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10237 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10238 If we have a base register, we want
10239 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10240 lui $at,<sym> (BFD_RELOC_HI16_S)
10241 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10245 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10247 Without $at we can't generate the optimal path for superscalar
10248 processors here since this would require two temporary registers.
10249 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10250 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10252 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10254 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10255 If we have a base register, we want
10256 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10257 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10259 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10261 daddu $tempreg,$tempreg,$breg
10262 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10264 For GP relative symbols in 64bit address space we can use
10265 the same sequence as in 32bit address space. */
10266 if (HAVE_64BIT_SYMBOLS
)
10268 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10269 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10271 relax_start (offset_expr
.X_add_symbol
);
10274 macro_build (&offset_expr
, s
, fmt
, treg
,
10275 BFD_RELOC_GPREL16
, mips_gp_register
);
10279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10280 tempreg
, breg
, mips_gp_register
);
10281 macro_build (&offset_expr
, s
, fmt
, treg
,
10282 BFD_RELOC_GPREL16
, tempreg
);
10287 if (used_at
== 0 && mips_opts
.at
)
10289 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10290 BFD_RELOC_MIPS_HIGHEST
);
10291 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
10293 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10294 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10296 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
10297 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10298 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10299 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
10305 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10306 BFD_RELOC_MIPS_HIGHEST
);
10307 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10308 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10309 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10310 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10311 tempreg
, BFD_RELOC_HI16_S
);
10312 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10314 macro_build (NULL
, "daddu", "d,v,t",
10315 tempreg
, tempreg
, breg
);
10316 macro_build (&offset_expr
, s
, fmt
, treg
,
10317 BFD_RELOC_LO16
, tempreg
);
10320 if (mips_relax
.sequence
)
10327 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10328 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10330 relax_start (offset_expr
.X_add_symbol
);
10331 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
10335 macro_build_lui (&offset_expr
, tempreg
);
10336 macro_build (&offset_expr
, s
, fmt
, treg
,
10337 BFD_RELOC_LO16
, tempreg
);
10338 if (mips_relax
.sequence
)
10343 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10344 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10346 relax_start (offset_expr
.X_add_symbol
);
10347 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10348 tempreg
, breg
, mips_gp_register
);
10349 macro_build (&offset_expr
, s
, fmt
, treg
,
10350 BFD_RELOC_GPREL16
, tempreg
);
10353 macro_build_lui (&offset_expr
, tempreg
);
10354 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10355 tempreg
, tempreg
, breg
);
10356 macro_build (&offset_expr
, s
, fmt
, treg
,
10357 BFD_RELOC_LO16
, tempreg
);
10358 if (mips_relax
.sequence
)
10362 else if (!mips_big_got
)
10364 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10366 /* If this is a reference to an external symbol, we want
10367 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10369 <op> $treg,0($tempreg)
10371 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10373 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10374 <op> $treg,0($tempreg)
10376 For NewABI, we want
10377 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10378 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10380 If there is a base register, we add it to $tempreg before
10381 the <op>. If there is a constant, we stick it in the
10382 <op> instruction. We don't handle constants larger than
10383 16 bits, because we have no way to load the upper 16 bits
10384 (actually, we could handle them for the subset of cases
10385 in which we are not using $at). */
10386 gas_assert (offset_expr
.X_op
== O_symbol
);
10389 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10390 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10392 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10393 tempreg
, tempreg
, breg
);
10394 macro_build (&offset_expr
, s
, fmt
, treg
,
10395 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10398 expr1
.X_add_number
= offset_expr
.X_add_number
;
10399 offset_expr
.X_add_number
= 0;
10400 if (expr1
.X_add_number
< -0x8000
10401 || expr1
.X_add_number
>= 0x8000)
10402 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10403 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10404 lw_reloc_type
, mips_gp_register
);
10406 relax_start (offset_expr
.X_add_symbol
);
10408 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10409 tempreg
, BFD_RELOC_LO16
);
10412 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10413 tempreg
, tempreg
, breg
);
10414 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10416 else if (mips_big_got
&& !HAVE_NEWABI
)
10420 /* If this is a reference to an external symbol, we want
10421 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10422 addu $tempreg,$tempreg,$gp
10423 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10424 <op> $treg,0($tempreg)
10426 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10428 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10429 <op> $treg,0($tempreg)
10430 If there is a base register, we add it to $tempreg before
10431 the <op>. If there is a constant, we stick it in the
10432 <op> instruction. We don't handle constants larger than
10433 16 bits, because we have no way to load the upper 16 bits
10434 (actually, we could handle them for the subset of cases
10435 in which we are not using $at). */
10436 gas_assert (offset_expr
.X_op
== O_symbol
);
10437 expr1
.X_add_number
= offset_expr
.X_add_number
;
10438 offset_expr
.X_add_number
= 0;
10439 if (expr1
.X_add_number
< -0x8000
10440 || expr1
.X_add_number
>= 0x8000)
10441 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10442 gpdelay
= reg_needs_delay (mips_gp_register
);
10443 relax_start (offset_expr
.X_add_symbol
);
10444 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10445 BFD_RELOC_MIPS_GOT_HI16
);
10446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10448 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10449 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10452 macro_build (NULL
, "nop", "");
10453 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10454 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10456 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10457 tempreg
, BFD_RELOC_LO16
);
10461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10462 tempreg
, tempreg
, breg
);
10463 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10465 else if (mips_big_got
&& HAVE_NEWABI
)
10467 /* If this is a reference to an external symbol, we want
10468 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10469 add $tempreg,$tempreg,$gp
10470 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10471 <op> $treg,<ofst>($tempreg)
10472 Otherwise, for local symbols, we want:
10473 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10474 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10475 gas_assert (offset_expr
.X_op
== O_symbol
);
10476 expr1
.X_add_number
= offset_expr
.X_add_number
;
10477 offset_expr
.X_add_number
= 0;
10478 if (expr1
.X_add_number
< -0x8000
10479 || expr1
.X_add_number
>= 0x8000)
10480 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10481 relax_start (offset_expr
.X_add_symbol
);
10482 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10483 BFD_RELOC_MIPS_GOT_HI16
);
10484 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10486 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10487 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10489 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10490 tempreg
, tempreg
, breg
);
10491 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
10494 offset_expr
.X_add_number
= expr1
.X_add_number
;
10495 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10496 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10498 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10499 tempreg
, tempreg
, breg
);
10500 macro_build (&offset_expr
, s
, fmt
, treg
,
10501 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10510 gas_assert (mips_opts
.micromips
);
10511 gas_assert (mips_opts
.insn32
);
10512 start_noreorder ();
10513 macro_build (NULL
, "jr", "s", RA
);
10514 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
10515 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
10520 gas_assert (mips_opts
.micromips
);
10521 gas_assert (mips_opts
.insn32
);
10522 macro_build (NULL
, "jr", "s", sreg
);
10523 if (mips_opts
.noreorder
)
10524 macro_build (NULL
, "nop", "");
10529 load_register (treg
, &imm_expr
, 0);
10533 load_register (treg
, &imm_expr
, 1);
10537 if (imm_expr
.X_op
== O_constant
)
10540 load_register (AT
, &imm_expr
, 0);
10541 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10546 gas_assert (offset_expr
.X_op
== O_symbol
10547 && strcmp (segment_name (S_GET_SEGMENT
10548 (offset_expr
.X_add_symbol
)),
10550 && offset_expr
.X_add_number
== 0);
10551 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
10552 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
10557 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10558 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10559 order 32 bits of the value and the low order 32 bits are either
10560 zero or in OFFSET_EXPR. */
10561 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10563 if (HAVE_64BIT_GPRS
)
10564 load_register (treg
, &imm_expr
, 1);
10569 if (target_big_endian
)
10581 load_register (hreg
, &imm_expr
, 0);
10584 if (offset_expr
.X_op
== O_absent
)
10585 move_register (lreg
, 0);
10588 gas_assert (offset_expr
.X_op
== O_constant
);
10589 load_register (lreg
, &offset_expr
, 0);
10596 /* We know that sym is in the .rdata section. First we get the
10597 upper 16 bits of the address. */
10598 if (mips_pic
== NO_PIC
)
10600 macro_build_lui (&offset_expr
, AT
);
10605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10606 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10610 /* Now we load the register(s). */
10611 if (HAVE_64BIT_GPRS
)
10614 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10619 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
10622 /* FIXME: How in the world do we deal with the possible
10624 offset_expr
.X_add_number
+= 4;
10625 macro_build (&offset_expr
, "lw", "t,o(b)",
10626 treg
+ 1, BFD_RELOC_LO16
, AT
);
10632 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10633 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10634 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10635 the value and the low order 32 bits are either zero or in
10637 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10640 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
10641 if (HAVE_64BIT_FPRS
)
10643 gas_assert (HAVE_64BIT_GPRS
);
10644 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
10648 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
10649 if (offset_expr
.X_op
== O_absent
)
10650 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
10653 gas_assert (offset_expr
.X_op
== O_constant
);
10654 load_register (AT
, &offset_expr
, 0);
10655 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
10661 gas_assert (offset_expr
.X_op
== O_symbol
10662 && offset_expr
.X_add_number
== 0);
10663 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
10664 if (strcmp (s
, ".lit8") == 0)
10666 breg
= mips_gp_register
;
10667 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
10668 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10669 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10673 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
10675 if (mips_pic
!= NO_PIC
)
10676 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10677 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10680 /* FIXME: This won't work for a 64 bit address. */
10681 macro_build_lui (&offset_expr
, AT
);
10685 offset_reloc
[0] = BFD_RELOC_LO16
;
10686 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10687 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10694 * The MIPS assembler seems to check for X_add_number not
10695 * being double aligned and generating:
10696 * lui at,%hi(foo+1)
10698 * addiu at,at,%lo(foo+1)
10701 * But, the resulting address is the same after relocation so why
10702 * generate the extra instruction?
10704 /* Itbl support may require additional care here. */
10707 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10716 gas_assert (!mips_opts
.micromips
);
10717 /* Itbl support may require additional care here. */
10720 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10740 if (HAVE_64BIT_GPRS
)
10750 if (HAVE_64BIT_GPRS
)
10758 /* Even on a big endian machine $fn comes before $fn+1. We have
10759 to adjust when loading from memory. We set coproc if we must
10760 load $fn+1 first. */
10761 /* Itbl support may require additional care here. */
10762 if (!target_big_endian
)
10765 if (small_offset_p (0, align
, 16))
10768 if (!small_offset_p (4, align
, 16))
10770 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
10771 -1, offset_reloc
[0], offset_reloc
[1],
10773 expr1
.X_add_number
= 0;
10777 offset_reloc
[0] = BFD_RELOC_LO16
;
10778 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10779 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10781 if (strcmp (s
, "lw") == 0 && treg
== breg
)
10783 ep
->X_add_number
+= 4;
10784 macro_build (ep
, s
, fmt
, treg
+ 1, -1, offset_reloc
[0],
10785 offset_reloc
[1], offset_reloc
[2], breg
);
10786 ep
->X_add_number
-= 4;
10787 macro_build (ep
, s
, fmt
, treg
, -1, offset_reloc
[0],
10788 offset_reloc
[1], offset_reloc
[2], breg
);
10792 macro_build (ep
, s
, fmt
, coproc
? treg
+ 1 : treg
, -1,
10793 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10795 ep
->X_add_number
+= 4;
10796 macro_build (ep
, s
, fmt
, coproc
? treg
: treg
+ 1, -1,
10797 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
10803 if (offset_expr
.X_op
!= O_symbol
10804 && offset_expr
.X_op
!= O_constant
)
10806 as_bad (_("Expression too complex"));
10807 offset_expr
.X_op
= O_constant
;
10810 if (HAVE_32BIT_ADDRESSES
10811 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10815 sprintf_vma (value
, offset_expr
.X_add_number
);
10816 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10819 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
10821 /* If this is a reference to a GP relative symbol, we want
10822 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10823 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10824 If we have a base register, we use this
10826 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10827 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10828 If this is not a GP relative symbol, we want
10829 lui $at,<sym> (BFD_RELOC_HI16_S)
10830 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10831 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10832 If there is a base register, we add it to $at after the
10833 lui instruction. If there is a constant, we always use
10835 if (offset_expr
.X_op
== O_symbol
10836 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10837 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10839 relax_start (offset_expr
.X_add_symbol
);
10842 tempreg
= mips_gp_register
;
10846 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10847 AT
, breg
, mips_gp_register
);
10852 /* Itbl support may require additional care here. */
10853 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10854 BFD_RELOC_GPREL16
, tempreg
);
10855 offset_expr
.X_add_number
+= 4;
10857 /* Set mips_optimize to 2 to avoid inserting an
10859 hold_mips_optimize
= mips_optimize
;
10861 /* Itbl support may require additional care here. */
10862 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10863 BFD_RELOC_GPREL16
, tempreg
);
10864 mips_optimize
= hold_mips_optimize
;
10868 offset_expr
.X_add_number
-= 4;
10871 if (offset_high_part (offset_expr
.X_add_number
, 16)
10872 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
10874 load_address (AT
, &offset_expr
, &used_at
);
10875 offset_expr
.X_op
= O_constant
;
10876 offset_expr
.X_add_number
= 0;
10879 macro_build_lui (&offset_expr
, AT
);
10881 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10882 /* Itbl support may require additional care here. */
10883 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10884 BFD_RELOC_LO16
, AT
);
10885 /* FIXME: How do we handle overflow here? */
10886 offset_expr
.X_add_number
+= 4;
10887 /* Itbl support may require additional care here. */
10888 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10889 BFD_RELOC_LO16
, AT
);
10890 if (mips_relax
.sequence
)
10893 else if (!mips_big_got
)
10895 /* If this is a reference to an external symbol, we want
10896 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10899 <op> $treg+1,4($at)
10901 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10903 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10904 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10905 If there is a base register we add it to $at before the
10906 lwc1 instructions. If there is a constant we include it
10907 in the lwc1 instructions. */
10909 expr1
.X_add_number
= offset_expr
.X_add_number
;
10910 if (expr1
.X_add_number
< -0x8000
10911 || expr1
.X_add_number
>= 0x8000 - 4)
10912 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10913 load_got_offset (AT
, &offset_expr
);
10916 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10918 /* Set mips_optimize to 2 to avoid inserting an undesired
10920 hold_mips_optimize
= mips_optimize
;
10923 /* Itbl support may require additional care here. */
10924 relax_start (offset_expr
.X_add_symbol
);
10925 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10926 BFD_RELOC_LO16
, AT
);
10927 expr1
.X_add_number
+= 4;
10928 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10929 BFD_RELOC_LO16
, AT
);
10931 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10932 BFD_RELOC_LO16
, AT
);
10933 offset_expr
.X_add_number
+= 4;
10934 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
10935 BFD_RELOC_LO16
, AT
);
10938 mips_optimize
= hold_mips_optimize
;
10940 else if (mips_big_got
)
10944 /* If this is a reference to an external symbol, we want
10945 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10947 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10950 <op> $treg+1,4($at)
10952 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10954 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10955 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10956 If there is a base register we add it to $at before the
10957 lwc1 instructions. If there is a constant we include it
10958 in the lwc1 instructions. */
10960 expr1
.X_add_number
= offset_expr
.X_add_number
;
10961 offset_expr
.X_add_number
= 0;
10962 if (expr1
.X_add_number
< -0x8000
10963 || expr1
.X_add_number
>= 0x8000 - 4)
10964 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10965 gpdelay
= reg_needs_delay (mips_gp_register
);
10966 relax_start (offset_expr
.X_add_symbol
);
10967 macro_build (&offset_expr
, "lui", LUI_FMT
,
10968 AT
, BFD_RELOC_MIPS_GOT_HI16
);
10969 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10970 AT
, AT
, mips_gp_register
);
10971 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10972 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
10975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
10976 /* Itbl support may require additional care here. */
10977 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
10978 BFD_RELOC_LO16
, AT
);
10979 expr1
.X_add_number
+= 4;
10981 /* Set mips_optimize to 2 to avoid inserting an undesired
10983 hold_mips_optimize
= mips_optimize
;
10985 /* Itbl support may require additional care here. */
10986 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
10987 BFD_RELOC_LO16
, AT
);
10988 mips_optimize
= hold_mips_optimize
;
10989 expr1
.X_add_number
-= 4;
10992 offset_expr
.X_add_number
= expr1
.X_add_number
;
10994 macro_build (NULL
, "nop", "");
10995 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10996 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10999 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11000 /* Itbl support may require additional care here. */
11001 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
11002 BFD_RELOC_LO16
, AT
);
11003 offset_expr
.X_add_number
+= 4;
11005 /* Set mips_optimize to 2 to avoid inserting an undesired
11007 hold_mips_optimize
= mips_optimize
;
11009 /* Itbl support may require additional care here. */
11010 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
11011 BFD_RELOC_LO16
, AT
);
11012 mips_optimize
= hold_mips_optimize
;
11031 /* New code added to support COPZ instructions.
11032 This code builds table entries out of the macros in mip_opcodes.
11033 R4000 uses interlocks to handle coproc delays.
11034 Other chips (like the R3000) require nops to be inserted for delays.
11036 FIXME: Currently, we require that the user handle delays.
11037 In order to fill delay slots for non-interlocked chips,
11038 we must have a way to specify delays based on the coprocessor.
11039 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11040 What are the side-effects of the cop instruction?
11041 What cache support might we have and what are its effects?
11042 Both coprocessor & memory require delays. how long???
11043 What registers are read/set/modified?
11045 If an itbl is provided to interpret cop instructions,
11046 this knowledge can be encoded in the itbl spec. */
11060 gas_assert (!mips_opts
.micromips
);
11061 /* For now we just do C (same as Cz). The parameter will be
11062 stored in insn_opcode by mips_ip. */
11063 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11067 move_register (dreg
, sreg
);
11071 gas_assert (mips_opts
.micromips
);
11072 gas_assert (mips_opts
.insn32
);
11073 dreg
= micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
11074 breg
= micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
11075 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
11076 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
11077 move_register (dreg
, sreg
);
11078 move_register (breg
, treg
);
11084 if (mips_opts
.arch
== CPU_R5900
)
11086 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
11090 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
11091 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11098 /* The MIPS assembler some times generates shifts and adds. I'm
11099 not trying to be that fancy. GCC should do this for us
11102 load_register (AT
, &imm_expr
, dbl
);
11103 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
11104 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11117 start_noreorder ();
11120 load_register (AT
, &imm_expr
, dbl
);
11121 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
11122 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11123 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
11124 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11126 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
11129 if (mips_opts
.micromips
)
11130 micromips_label_expr (&label_expr
);
11132 label_expr
.X_add_number
= 8;
11133 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
11134 macro_build (NULL
, "nop", "");
11135 macro_build (NULL
, "break", BRK_FMT
, 6);
11136 if (mips_opts
.micromips
)
11137 micromips_add_label ();
11140 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11153 start_noreorder ();
11156 load_register (AT
, &imm_expr
, dbl
);
11157 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
11158 sreg
, imm
? AT
: treg
);
11159 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11160 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
11162 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
11165 if (mips_opts
.micromips
)
11166 micromips_label_expr (&label_expr
);
11168 label_expr
.X_add_number
= 8;
11169 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
11170 macro_build (NULL
, "nop", "");
11171 macro_build (NULL
, "break", BRK_FMT
, 6);
11172 if (mips_opts
.micromips
)
11173 micromips_add_label ();
11179 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11190 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
11191 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
11195 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
11196 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
11197 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
11198 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11202 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11213 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
11214 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
11218 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
11219 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
11220 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
11221 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11230 if (imm_expr
.X_op
!= O_constant
)
11231 as_bad (_("Improper rotate count"));
11232 rot
= imm_expr
.X_add_number
& 0x3f;
11233 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11235 rot
= (64 - rot
) & 0x3f;
11237 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
11239 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
11244 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
11247 l
= (rot
< 0x20) ? "dsll" : "dsll32";
11248 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
11251 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
11252 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11253 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11261 if (imm_expr
.X_op
!= O_constant
)
11262 as_bad (_("Improper rotate count"));
11263 rot
= imm_expr
.X_add_number
& 0x1f;
11264 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11266 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
11271 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
11275 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
11276 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11277 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11282 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11284 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
11288 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
11289 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
11290 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
11291 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11295 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11297 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
11301 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
11302 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
11303 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
11304 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11313 if (imm_expr
.X_op
!= O_constant
)
11314 as_bad (_("Improper rotate count"));
11315 rot
= imm_expr
.X_add_number
& 0x3f;
11316 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11319 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
11321 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
11326 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
11329 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
11330 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
11333 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
11334 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11335 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11343 if (imm_expr
.X_op
!= O_constant
)
11344 as_bad (_("Improper rotate count"));
11345 rot
= imm_expr
.X_add_number
& 0x1f;
11346 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11348 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
11353 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
11357 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
11358 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
11359 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
11365 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
11366 else if (treg
== 0)
11367 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11370 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
11371 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
11376 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11378 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11383 as_warn (_("Instruction %s: result is always false"),
11384 ip
->insn_mo
->name
);
11385 move_register (dreg
, 0);
11388 if (CPU_HAS_SEQ (mips_opts
.arch
)
11389 && -512 <= imm_expr
.X_add_number
11390 && imm_expr
.X_add_number
< 512)
11392 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
11393 (int) imm_expr
.X_add_number
);
11396 if (imm_expr
.X_op
== O_constant
11397 && imm_expr
.X_add_number
>= 0
11398 && imm_expr
.X_add_number
< 0x10000)
11400 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
11402 else if (imm_expr
.X_op
== O_constant
11403 && imm_expr
.X_add_number
> -0x8000
11404 && imm_expr
.X_add_number
< 0)
11406 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11407 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11408 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11410 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11413 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11414 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
11419 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11420 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
11423 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
11426 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
11432 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
11433 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11436 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
11438 if (imm_expr
.X_op
== O_constant
11439 && imm_expr
.X_add_number
>= -0x8000
11440 && imm_expr
.X_add_number
< 0x8000)
11442 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
11443 dreg
, sreg
, BFD_RELOC_LO16
);
11447 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11448 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
11452 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11455 case M_SGT
: /* sreg > treg <==> treg < sreg */
11461 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
11464 case M_SGT_I
: /* sreg > I <==> I < sreg */
11471 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11472 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
11475 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
11481 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
11482 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11485 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
11492 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11493 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
11494 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
11498 if (imm_expr
.X_op
== O_constant
11499 && imm_expr
.X_add_number
>= -0x8000
11500 && imm_expr
.X_add_number
< 0x8000)
11502 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11506 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11507 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
11511 if (imm_expr
.X_op
== O_constant
11512 && imm_expr
.X_add_number
>= -0x8000
11513 && imm_expr
.X_add_number
< 0x8000)
11515 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
11520 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11521 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
11526 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
11527 else if (treg
== 0)
11528 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
11531 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
11532 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11537 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11539 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
11544 as_warn (_("Instruction %s: result is always true"),
11545 ip
->insn_mo
->name
);
11546 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
11547 dreg
, 0, BFD_RELOC_LO16
);
11550 if (CPU_HAS_SEQ (mips_opts
.arch
)
11551 && -512 <= imm_expr
.X_add_number
11552 && imm_expr
.X_add_number
< 512)
11554 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
11555 (int) imm_expr
.X_add_number
);
11558 if (imm_expr
.X_op
== O_constant
11559 && imm_expr
.X_add_number
>= 0
11560 && imm_expr
.X_add_number
< 0x10000)
11562 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
11564 else if (imm_expr
.X_op
== O_constant
11565 && imm_expr
.X_add_number
> -0x8000
11566 && imm_expr
.X_add_number
< 0)
11568 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11569 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11570 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11572 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11575 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11576 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
11581 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11582 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
11585 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
11600 if (!mips_opts
.micromips
)
11602 if (imm_expr
.X_op
== O_constant
11603 && imm_expr
.X_add_number
> -0x200
11604 && imm_expr
.X_add_number
<= 0x200)
11606 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
11615 if (imm_expr
.X_op
== O_constant
11616 && imm_expr
.X_add_number
> -0x8000
11617 && imm_expr
.X_add_number
<= 0x8000)
11619 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11620 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
11625 load_register (AT
, &imm_expr
, dbl
);
11626 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
11648 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11649 macro_build (NULL
, s
, "s,t", sreg
, AT
);
11654 gas_assert (!mips_opts
.micromips
);
11655 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
11657 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
11658 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
11661 * Is the double cfc1 instruction a bug in the mips assembler;
11662 * or is there a reason for it?
11664 start_noreorder ();
11665 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11666 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
11667 macro_build (NULL
, "nop", "");
11668 expr1
.X_add_number
= 3;
11669 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
11670 expr1
.X_add_number
= 2;
11671 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
11672 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
11673 macro_build (NULL
, "nop", "");
11674 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
11676 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
11677 macro_build (NULL
, "nop", "");
11694 offbits
= (mips_opts
.micromips
? 12 : 16);
11700 offbits
= (mips_opts
.micromips
? 12 : 16);
11712 offbits
= (mips_opts
.micromips
? 12 : 16);
11719 offbits
= (mips_opts
.micromips
? 12 : 16);
11724 large_offset
= !small_offset_p (off
, align
, offbits
);
11726 expr1
.X_add_number
= 0;
11731 if (small_offset_p (0, align
, 16))
11732 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
11733 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11736 load_address (tempreg
, ep
, &used_at
);
11738 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11739 tempreg
, tempreg
, breg
);
11741 offset_reloc
[0] = BFD_RELOC_LO16
;
11742 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11743 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11748 else if (!ust
&& treg
== breg
)
11759 if (!target_big_endian
)
11760 ep
->X_add_number
+= off
;
11762 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
11764 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11765 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11767 if (!target_big_endian
)
11768 ep
->X_add_number
-= off
;
11770 ep
->X_add_number
+= off
;
11772 macro_build (NULL
, s2
, "t,~(b)",
11773 tempreg
, (int) ep
->X_add_number
, breg
);
11775 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11776 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11778 /* If necessary, move the result in tempreg to the final destination. */
11779 if (!ust
&& treg
!= tempreg
)
11781 /* Protect second load's delay slot. */
11783 move_register (treg
, tempreg
);
11789 if (target_big_endian
== ust
)
11790 ep
->X_add_number
+= off
;
11791 tempreg
= ust
|| large_offset
? treg
: AT
;
11792 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11793 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11795 /* For halfword transfers we need a temporary register to shuffle
11796 bytes. Unfortunately for M_USH_A we have none available before
11797 the next store as AT holds the base address. We deal with this
11798 case by clobbering TREG and then restoring it as with ULH. */
11799 tempreg
= ust
== large_offset
? treg
: AT
;
11801 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
11803 if (target_big_endian
== ust
)
11804 ep
->X_add_number
-= off
;
11806 ep
->X_add_number
+= off
;
11807 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
11808 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11810 /* For M_USH_A re-retrieve the LSB. */
11811 if (ust
&& large_offset
)
11813 if (target_big_endian
)
11814 ep
->X_add_number
+= off
;
11816 ep
->X_add_number
-= off
;
11817 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
11818 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
11820 /* For ULH and M_USH_A OR the LSB in. */
11821 if (!ust
|| large_offset
)
11823 tempreg
= !large_offset
? AT
: treg
;
11824 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
11825 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
11830 /* FIXME: Check if this is one of the itbl macros, since they
11831 are added dynamically. */
11832 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
11835 if (!mips_opts
.at
&& used_at
)
11836 as_bad (_("Macro used $at after \".set noat\""));
11839 /* Implement macros in mips16 mode. */
11842 mips16_macro (struct mips_cl_insn
*ip
)
11845 int xreg
, yreg
, zreg
, tmp
;
11848 const char *s
, *s2
, *s3
;
11850 mask
= ip
->insn_mo
->mask
;
11852 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
11853 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
11854 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
11856 expr1
.X_op
= O_constant
;
11857 expr1
.X_op_symbol
= NULL
;
11858 expr1
.X_add_symbol
= NULL
;
11859 expr1
.X_add_number
= 1;
11878 start_noreorder ();
11879 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
11880 expr1
.X_add_number
= 2;
11881 macro_build (&expr1
, "bnez", "x,p", yreg
);
11882 macro_build (NULL
, "break", "6", 7);
11884 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11885 since that causes an overflow. We should do that as well,
11886 but I don't see how to do the comparisons without a temporary
11889 macro_build (NULL
, s
, "x", zreg
);
11908 start_noreorder ();
11909 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
11910 expr1
.X_add_number
= 2;
11911 macro_build (&expr1
, "bnez", "x,p", yreg
);
11912 macro_build (NULL
, "break", "6", 7);
11914 macro_build (NULL
, s2
, "x", zreg
);
11920 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
11921 macro_build (NULL
, "mflo", "x", zreg
);
11929 if (imm_expr
.X_op
!= O_constant
)
11930 as_bad (_("Unsupported large constant"));
11931 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11932 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
11936 if (imm_expr
.X_op
!= O_constant
)
11937 as_bad (_("Unsupported large constant"));
11938 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11939 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
11943 if (imm_expr
.X_op
!= O_constant
)
11944 as_bad (_("Unsupported large constant"));
11945 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11946 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
11968 goto do_reverse_branch
;
11972 goto do_reverse_branch
;
11984 goto do_reverse_branch
;
11995 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
11996 macro_build (&offset_expr
, s2
, "p");
12023 goto do_addone_branch_i
;
12028 goto do_addone_branch_i
;
12043 goto do_addone_branch_i
;
12049 do_addone_branch_i
:
12050 if (imm_expr
.X_op
!= O_constant
)
12051 as_bad (_("Unsupported large constant"));
12052 ++imm_expr
.X_add_number
;
12055 macro_build (&imm_expr
, s
, s3
, xreg
);
12056 macro_build (&offset_expr
, s2
, "p");
12060 expr1
.X_add_number
= 0;
12061 macro_build (&expr1
, "slti", "x,8", yreg
);
12063 move_register (xreg
, yreg
);
12064 expr1
.X_add_number
= 2;
12065 macro_build (&expr1
, "bteqz", "p");
12066 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
12070 /* Assemble an instruction into its binary format. If the instruction
12071 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12072 associated with "I", "+I" and "A" operands respectively. Otherwise
12073 store the value of the relocatable field (if any) in offset_expr.
12074 In both cases set offset_reloc to the relocation operators applied
12078 mips_ip (char *str
, struct mips_cl_insn
*ip
)
12080 bfd_boolean wrong_delay_slot_insns
= FALSE
;
12081 bfd_boolean need_delay_slot_ok
= TRUE
;
12082 struct mips_opcode
*firstinsn
= NULL
;
12083 const struct mips_opcode
*past
;
12084 struct hash_control
*hash
;
12087 struct mips_opcode
*insn
;
12093 const struct mips_operand
*operand
;
12094 struct mips_arg_info arg
;
12095 struct mips_operand_token
*tokens
;
12096 bfd_boolean optional_reg
;
12100 if (mips_opts
.micromips
)
12102 hash
= micromips_op_hash
;
12103 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
12108 past
= &mips_opcodes
[NUMOPCODES
];
12110 forced_insn_length
= 0;
12113 /* We first try to match an instruction up to a space or to the end. */
12114 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
12117 /* Make a copy of the instruction so that we can fiddle with it. */
12118 name
= alloca (end
+ 1);
12119 memcpy (name
, str
, end
);
12124 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12126 if (insn
!= NULL
|| !mips_opts
.micromips
)
12128 if (forced_insn_length
)
12131 /* See if there's an instruction size override suffix,
12132 either `16' or `32', at the end of the mnemonic proper,
12133 that defines the operation, i.e. before the first `.'
12134 character if any. Strip it and retry. */
12135 dot
= strchr (name
, '.');
12136 opend
= dot
!= NULL
? dot
- name
: end
;
12139 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12140 forced_insn_length
= 2;
12141 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
12142 forced_insn_length
= 4;
12145 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
12149 insn_error
= _("Unrecognized opcode");
12153 if (strcmp (name
, "li.s") == 0)
12155 else if (strcmp (name
, "li.d") == 0)
12159 tokens
= mips_parse_arguments (str
+ end
, format
);
12163 /* For microMIPS instructions placed in a fixed-length branch delay slot
12164 we make up to two passes over the relevant fragment of the opcode
12165 table. First we try instructions that meet the delay slot's length
12166 requirement. If none matched, then we retry with the remaining ones
12167 and if one matches, then we use it and then issue an appropriate
12168 warning later on. */
12171 bfd_boolean delay_slot_ok
;
12172 bfd_boolean size_ok
;
12174 bfd_boolean more_alts
;
12176 gas_assert (strcmp (insn
->name
, name
) == 0);
12178 ok
= is_opcode_valid (insn
);
12179 size_ok
= is_size_valid (insn
);
12180 delay_slot_ok
= is_delay_slot_valid (insn
);
12181 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
12184 wrong_delay_slot_insns
= TRUE
;
12186 more_alts
= (insn
+ 1 < past
12187 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12188 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
12190 static char buf
[256];
12197 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12199 gas_assert (firstinsn
);
12200 need_delay_slot_ok
= FALSE
;
12206 obstack_free (&mips_operand_tokens
, tokens
);
12211 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
12212 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12213 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12214 else if (mips_opts
.insn32
)
12215 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
12217 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
12218 8 * forced_insn_length
);
12224 imm_expr
.X_op
= O_absent
;
12225 imm2_expr
.X_op
= O_absent
;
12226 offset_expr
.X_op
= O_absent
;
12227 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12228 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12229 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12231 create_insn (ip
, insn
);
12233 memset (&arg
, 0, sizeof (arg
));
12235 arg
.token
= tokens
;
12237 arg
.last_regno
= ILLEGAL_REG
;
12238 arg
.dest_regno
= ILLEGAL_REG
;
12239 arg
.soft_match
= (more_alts
12240 || (wrong_delay_slot_insns
&& need_delay_slot_ok
));
12241 for (args
= insn
->args
;; ++args
)
12243 if (arg
.token
->type
== OT_END
)
12245 /* Handle unary instructions in which only one operand is given.
12246 The source is then the same as the destination. */
12247 if (arg
.opnum
== 1 && *args
== ',')
12255 arg
.token
= tokens
;
12260 /* Treat elided base registers as $0. */
12261 if (strcmp (args
, "(b)") == 0)
12264 /* Fail the match if there were too few operands. */
12268 /* Successful match. */
12269 if (arg
.dest_regno
== arg
.last_regno
12270 && strncmp (ip
->insn_mo
->name
, "jalr", 4) == 0)
12272 if (arg
.opnum
== 2)
12273 as_bad (_("Source and destination must be different"));
12274 else if (arg
.last_regno
== 31)
12275 as_bad (_("A destination register must be supplied"));
12277 check_completed_insn (&arg
);
12278 obstack_free (&mips_operand_tokens
, tokens
);
12282 /* Fail the match if the line has too many operands. */
12286 /* Handle characters that need to match exactly. */
12287 if (*args
== '(' || *args
== ')' || *args
== ',')
12289 if (match_char (&arg
, *args
))
12294 /* Handle special macro operands. Work out the properties of
12297 arg
.lax_max
= FALSE
;
12298 optional_reg
= FALSE
;
12317 /* If these integer forms come last, there is no other
12318 form of the instruction that could match. Prefer to
12319 give detailed error messages where possible. */
12321 arg
.soft_match
= FALSE
;
12325 /* "+I" is like "I", except that imm2_expr is used. */
12326 if (match_const_int (&arg
, &imm2_expr
.X_add_number
, 0))
12327 imm2_expr
.X_op
= O_constant
;
12329 insn_error
= _("absolute expression required");
12330 if (HAVE_32BIT_GPRS
)
12331 normalize_constant_expr (&imm2_expr
);
12336 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12366 /* If these integer forms come last, there is no other
12367 form of the instruction that could match. Prefer to
12368 give detailed error messages where possible. */
12370 arg
.soft_match
= FALSE
;
12378 /* We have already matched a comma by this point, so the register
12379 is only optional if there is another operand to come. */
12380 gas_assert (arg
.opnum
== 2);
12381 optional_reg
= (args
[1] == ',');
12385 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
12386 imm_expr
.X_op
= O_constant
;
12388 insn_error
= _("absolute expression required");
12389 if (HAVE_32BIT_GPRS
)
12390 normalize_constant_expr (&imm_expr
);
12394 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
12396 /* Assume that the offset has been elided and that what
12397 we saw was a base register. The match will fail later
12398 if that assumption turns out to be wrong. */
12399 offset_expr
.X_op
= O_constant
;
12400 offset_expr
.X_add_number
= 0;
12402 else if (match_expression (&arg
, &offset_expr
, offset_reloc
))
12403 normalize_address_expr (&offset_expr
);
12405 insn_error
= _("absolute expression required");
12409 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12411 insn_error
= _("floating-point expression required");
12415 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12417 insn_error
= _("floating-point expression required");
12421 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12423 insn_error
= _("floating-point expression required");
12427 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12429 insn_error
= _("floating-point expression required");
12432 /* ??? This is the traditional behavior, but is flaky if
12433 there are alternative versions of the same instruction
12434 for different subarchitectures. The next alternative
12435 might not be suitable. */
12437 /* For compatibility with older assemblers, we accept
12438 0x8000-0xffff as signed 16-bit numbers when only
12439 signed numbers are allowed. */
12440 arg
.lax_max
= !more_alts
;
12442 /* Only accept non-constant operands if this is the
12443 final alternative. Later alternatives might include
12444 a macro implementation. */
12445 arg
.allow_nonconst
= !more_alts
;
12449 /* There are no macro implementations for out-of-range values. */
12450 arg
.allow_nonconst
= TRUE
;
12454 /* There should always be a macro implementation. */
12455 arg
.allow_nonconst
= FALSE
;
12459 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12463 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12467 gas_assert (mips_opts
.micromips
);
12474 /* We have already matched a comma by this point,
12475 so the register is only optional if there is another
12476 operand to come. */
12477 gas_assert (arg
.opnum
== 2);
12478 optional_reg
= (args
[2] == ',');
12483 if (!forced_insn_length
)
12484 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12486 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12488 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12494 operand
= (mips_opts
.micromips
12495 ? decode_micromips_operand (args
)
12496 : decode_mips_operand (args
));
12501 && (arg
.token
[0].type
!= OT_REG
12502 || arg
.token
[1].type
== OT_END
))
12504 /* Assume that the register has been elided and is the
12505 same as the first operand. */
12506 arg
.token
= tokens
;
12510 if (!match_operand (&arg
, operand
))
12513 /* Skip prefixes. */
12514 if (*args
== '+' || *args
== 'm')
12519 /* Args don't match. */
12520 insn_error
= _("Illegal operands");
12526 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12528 gas_assert (firstinsn
);
12529 need_delay_slot_ok
= FALSE
;
12534 obstack_free (&mips_operand_tokens
, tokens
);
12539 /* As for mips_ip, but used when assembling MIPS16 code.
12540 Also set forced_insn_length to the resulting instruction size in
12541 bytes if the user explicitly requested a small or extended instruction. */
12544 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
12548 struct mips_opcode
*insn
;
12549 const struct mips_operand
*operand
;
12550 const struct mips_operand
*ext_operand
;
12551 struct mips_arg_info arg
;
12552 struct mips_operand_token
*tokens
;
12553 bfd_boolean optional_reg
;
12557 forced_insn_length
= 0;
12559 for (s
= str
; ISLOWER (*s
); ++s
)
12571 if (s
[1] == 't' && s
[2] == ' ')
12574 forced_insn_length
= 2;
12578 else if (s
[1] == 'e' && s
[2] == ' ')
12581 forced_insn_length
= 4;
12585 /* Fall through. */
12587 insn_error
= _("unknown opcode");
12591 if (mips_opts
.noautoextend
&& !forced_insn_length
)
12592 forced_insn_length
= 2;
12594 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
12596 insn_error
= _("unrecognized opcode");
12600 tokens
= mips_parse_arguments (s
, 0);
12607 bfd_boolean more_alts
;
12610 gas_assert (strcmp (insn
->name
, str
) == 0);
12612 ok
= is_opcode_valid_16 (insn
);
12613 more_alts
= (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
12614 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12626 static char buf
[100];
12628 _("Opcode not supported on this processor: %s (%s)"),
12629 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12630 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12633 obstack_free (&mips_operand_tokens
, tokens
);
12638 create_insn (ip
, insn
);
12639 imm_expr
.X_op
= O_absent
;
12640 imm2_expr
.X_op
= O_absent
;
12641 offset_expr
.X_op
= O_absent
;
12642 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12643 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12644 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12647 memset (&arg
, 0, sizeof (arg
));
12649 arg
.token
= tokens
;
12651 arg
.last_regno
= ILLEGAL_REG
;
12652 arg
.dest_regno
= ILLEGAL_REG
;
12653 arg
.soft_match
= more_alts
;
12655 for (args
= insn
->args
; 1; ++args
)
12659 if (arg
.token
->type
== OT_END
)
12663 /* Handle unary instructions in which only one operand is given.
12664 The source is then the same as the destination. */
12665 if (arg
.opnum
== 1 && *args
== ',')
12670 arg
.token
= tokens
;
12675 /* Fail the match if there were too few operands. */
12679 /* Successful match. Stuff the immediate value in now, if
12681 if (insn
->pinfo
== INSN_MACRO
)
12683 gas_assert (relax_char
== 0);
12684 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
12686 else if (relax_char
12687 && offset_expr
.X_op
== O_constant
12688 && calculate_reloc (*offset_reloc
,
12689 offset_expr
.X_add_number
,
12692 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
12693 forced_insn_length
, &ip
->insn_opcode
);
12694 offset_expr
.X_op
= O_absent
;
12695 *offset_reloc
= BFD_RELOC_UNUSED
;
12697 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
12699 if (forced_insn_length
== 2)
12700 as_bad (_("invalid unextended operand value"));
12701 forced_insn_length
= 4;
12702 ip
->insn_opcode
|= MIPS16_EXTEND
;
12704 else if (relax_char
)
12705 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
12707 check_completed_insn (&arg
);
12708 obstack_free (&mips_operand_tokens
, tokens
);
12712 /* Fail the match if the line has too many operands. */
12716 /* Handle characters that need to match exactly. */
12717 if (*args
== '(' || *args
== ')' || *args
== ',')
12719 if (match_char (&arg
, *args
))
12725 optional_reg
= FALSE
;
12731 optional_reg
= (args
[1] == ',');
12743 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
12744 imm_expr
.X_op
= O_constant
;
12746 insn_error
= _("absolute expression required");
12747 if (HAVE_32BIT_GPRS
)
12748 normalize_constant_expr (&imm_expr
);
12753 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
12754 ip
->insn_opcode
<<= 16;
12758 operand
= decode_mips16_operand (c
, FALSE
);
12762 /* '6' is a special case. It is used for BREAK and SDBBP,
12763 whose operands are only meaningful to the software that decodes
12764 them. This means that there is no architectural reason why
12765 they cannot be prefixed by EXTEND, but in practice,
12766 exception handlers will only look at the instruction
12767 itself. We therefore allow '6' to be extended when
12768 disassembling but not when assembling. */
12769 if (operand
->type
!= OP_PCREL
&& c
!= '6')
12771 ext_operand
= decode_mips16_operand (c
, TRUE
);
12772 if (operand
!= ext_operand
)
12774 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
12776 offset_expr
.X_op
= O_constant
;
12777 offset_expr
.X_add_number
= 0;
12782 /* We need the OT_INTEGER check because some MIPS16
12783 immediate variants are listed before the register ones. */
12784 if (arg
.token
->type
!= OT_INTEGER
12785 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
12788 /* '8' is used for SLTI(U) and has traditionally not
12789 been allowed to take relocation operators. */
12790 if (offset_reloc
[0] != BFD_RELOC_UNUSED
12791 && (ext_operand
->size
!= 16 || c
== '8'))
12800 && (arg
.token
[0].type
!= OT_REG
12801 || arg
.token
[1].type
== OT_END
))
12803 /* Assume that the register has been elided and is the
12804 same as the first operand. */
12805 arg
.token
= tokens
;
12809 if (!match_operand (&arg
, operand
))
12814 /* Args don't match. */
12821 insn_error
= _("illegal operands");
12823 obstack_free (&mips_operand_tokens
, tokens
);
12828 /* This structure holds information we know about a mips16 immediate
12831 struct mips16_immed_operand
12833 /* The type code used in the argument string in the opcode table. */
12835 /* The number of bits in the short form of the opcode. */
12837 /* The number of bits in the extended form of the opcode. */
12839 /* The amount by which the short form is shifted when it is used;
12840 for example, the sw instruction has a shift count of 2. */
12842 /* The amount by which the short form is shifted when it is stored
12843 into the instruction code. */
12845 /* Non-zero if the short form is unsigned. */
12847 /* Non-zero if the extended form is unsigned. */
12849 /* Non-zero if the value is PC relative. */
12853 /* The mips16 immediate operand types. */
12855 static const struct mips16_immed_operand mips16_immed_operands
[] =
12857 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
12858 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
12859 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
12860 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
12861 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
12862 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12863 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12864 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12865 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
12866 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
12867 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12868 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12869 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
12870 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
12871 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
12872 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
12873 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
12874 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
12875 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
12876 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
12877 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
12880 #define MIPS16_NUM_IMMED \
12881 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
12883 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12884 NBITS is the number of significant bits in VAL. */
12886 static unsigned long
12887 mips16_immed_extend (offsetT val
, unsigned int nbits
)
12892 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
12895 else if (nbits
== 15)
12897 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
12902 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
12905 return (extval
<< 16) | val
;
12908 /* Install immediate value VAL into MIPS16 instruction *INSN,
12909 extending it if necessary. The instruction in *INSN may
12910 already be extended.
12912 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12913 if none. In the former case, VAL is a 16-bit number with no
12914 defined signedness.
12916 TYPE is the type of the immediate field. USER_INSN_LENGTH
12917 is the length that the user requested, or 0 if none. */
12920 mips16_immed (char *file
, unsigned int line
, int type
,
12921 bfd_reloc_code_real_type reloc
, offsetT val
,
12922 unsigned int user_insn_length
, unsigned long *insn
)
12924 const struct mips16_immed_operand
*op
;
12925 int mintiny
, maxtiny
;
12927 op
= mips16_immed_operands
;
12928 while (op
->type
!= type
)
12931 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12936 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12939 maxtiny
= 1 << op
->nbits
;
12944 maxtiny
= (1 << op
->nbits
) - 1;
12946 if (reloc
!= BFD_RELOC_UNUSED
)
12951 mintiny
= - (1 << (op
->nbits
- 1));
12952 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12953 if (reloc
!= BFD_RELOC_UNUSED
)
12954 val
= SEXT_16BIT (val
);
12957 /* Branch offsets have an implicit 0 in the lowest bit. */
12958 if (type
== 'p' || type
== 'q')
12961 if ((val
& ((1 << op
->shift
) - 1)) != 0
12962 || val
< (mintiny
<< op
->shift
)
12963 || val
> (maxtiny
<< op
->shift
))
12965 /* We need an extended instruction. */
12966 if (user_insn_length
== 2)
12967 as_bad_where (file
, line
, _("invalid unextended operand value"));
12969 *insn
|= MIPS16_EXTEND
;
12971 else if (user_insn_length
== 4)
12973 /* The operand doesn't force an unextended instruction to be extended.
12974 Warn if the user wanted an extended instruction anyway. */
12975 *insn
|= MIPS16_EXTEND
;
12976 as_warn_where (file
, line
,
12977 _("extended operand requested but not required"));
12980 if (mips16_opcode_length (*insn
) == 2)
12984 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
12985 insnval
<<= op
->op_shift
;
12990 long minext
, maxext
;
12992 if (reloc
== BFD_RELOC_UNUSED
)
12997 maxext
= (1 << op
->extbits
) - 1;
13001 minext
= - (1 << (op
->extbits
- 1));
13002 maxext
= (1 << (op
->extbits
- 1)) - 1;
13004 if (val
< minext
|| val
> maxext
)
13005 as_bad_where (file
, line
,
13006 _("operand value out of range for instruction"));
13009 *insn
|= mips16_immed_extend (val
, op
->extbits
);
13013 struct percent_op_match
13016 bfd_reloc_code_real_type reloc
;
13019 static const struct percent_op_match mips_percent_op
[] =
13021 {"%lo", BFD_RELOC_LO16
},
13022 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13023 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13024 {"%call16", BFD_RELOC_MIPS_CALL16
},
13025 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13026 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13027 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13028 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13029 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13030 {"%got", BFD_RELOC_MIPS_GOT16
},
13031 {"%gp_rel", BFD_RELOC_GPREL16
},
13032 {"%half", BFD_RELOC_16
},
13033 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13034 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13035 {"%neg", BFD_RELOC_MIPS_SUB
},
13036 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13037 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13038 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13039 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13040 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13041 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13042 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13043 {"%hi", BFD_RELOC_HI16_S
}
13046 static const struct percent_op_match mips16_percent_op
[] =
13048 {"%lo", BFD_RELOC_MIPS16_LO16
},
13049 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13050 {"%got", BFD_RELOC_MIPS16_GOT16
},
13051 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13052 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13053 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13054 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13055 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13056 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13057 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13058 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13059 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13063 /* Return true if *STR points to a relocation operator. When returning true,
13064 move *STR over the operator and store its relocation code in *RELOC.
13065 Leave both *STR and *RELOC alone when returning false. */
13068 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13070 const struct percent_op_match
*percent_op
;
13073 if (mips_opts
.mips16
)
13075 percent_op
= mips16_percent_op
;
13076 limit
= ARRAY_SIZE (mips16_percent_op
);
13080 percent_op
= mips_percent_op
;
13081 limit
= ARRAY_SIZE (mips_percent_op
);
13084 for (i
= 0; i
< limit
; i
++)
13085 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13087 int len
= strlen (percent_op
[i
].str
);
13089 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13092 *str
+= strlen (percent_op
[i
].str
);
13093 *reloc
= percent_op
[i
].reloc
;
13095 /* Check whether the output BFD supports this relocation.
13096 If not, issue an error and fall back on something safe. */
13097 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13099 as_bad (_("relocation %s isn't supported by the current ABI"),
13100 percent_op
[i
].str
);
13101 *reloc
= BFD_RELOC_UNUSED
;
13109 /* Parse string STR as a 16-bit relocatable operand. Store the
13110 expression in *EP and the relocations in the array starting
13111 at RELOC. Return the number of relocation operators used.
13113 On exit, EXPR_END points to the first character after the expression. */
13116 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13119 bfd_reloc_code_real_type reversed_reloc
[3];
13120 size_t reloc_index
, i
;
13121 int crux_depth
, str_depth
;
13124 /* Search for the start of the main expression, recoding relocations
13125 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13126 of the main expression and with CRUX_DEPTH containing the number
13127 of open brackets at that point. */
13134 crux_depth
= str_depth
;
13136 /* Skip over whitespace and brackets, keeping count of the number
13138 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13143 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13144 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13146 my_getExpression (ep
, crux
);
13149 /* Match every open bracket. */
13150 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13154 if (crux_depth
> 0)
13155 as_bad (_("unclosed '('"));
13159 if (reloc_index
!= 0)
13161 prev_reloc_op_frag
= frag_now
;
13162 for (i
= 0; i
< reloc_index
; i
++)
13163 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13166 return reloc_index
;
13170 my_getExpression (expressionS
*ep
, char *str
)
13174 save_in
= input_line_pointer
;
13175 input_line_pointer
= str
;
13177 expr_end
= input_line_pointer
;
13178 input_line_pointer
= save_in
;
13182 md_atof (int type
, char *litP
, int *sizeP
)
13184 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13188 md_number_to_chars (char *buf
, valueT val
, int n
)
13190 if (target_big_endian
)
13191 number_to_chars_bigendian (buf
, val
, n
);
13193 number_to_chars_littleendian (buf
, val
, n
);
13196 static int support_64bit_objects(void)
13198 const char **list
, **l
;
13201 list
= bfd_target_list ();
13202 for (l
= list
; *l
!= NULL
; l
++)
13203 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13204 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13206 yes
= (*l
!= NULL
);
13211 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13212 NEW_VALUE. Warn if another value was already specified. Note:
13213 we have to defer parsing the -march and -mtune arguments in order
13214 to handle 'from-abi' correctly, since the ABI might be specified
13215 in a later argument. */
13218 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13220 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13221 as_warn (_("A different %s was already specified, is now %s"),
13222 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13225 *string_ptr
= new_value
;
13229 md_parse_option (int c
, char *arg
)
13233 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13234 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13236 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13237 c
== mips_ases
[i
].option_on
);
13243 case OPTION_CONSTRUCT_FLOATS
:
13244 mips_disable_float_construction
= 0;
13247 case OPTION_NO_CONSTRUCT_FLOATS
:
13248 mips_disable_float_construction
= 1;
13260 target_big_endian
= 1;
13264 target_big_endian
= 0;
13270 else if (arg
[0] == '0')
13272 else if (arg
[0] == '1')
13282 mips_debug
= atoi (arg
);
13286 file_mips_isa
= ISA_MIPS1
;
13290 file_mips_isa
= ISA_MIPS2
;
13294 file_mips_isa
= ISA_MIPS3
;
13298 file_mips_isa
= ISA_MIPS4
;
13302 file_mips_isa
= ISA_MIPS5
;
13305 case OPTION_MIPS32
:
13306 file_mips_isa
= ISA_MIPS32
;
13309 case OPTION_MIPS32R2
:
13310 file_mips_isa
= ISA_MIPS32R2
;
13313 case OPTION_MIPS64R2
:
13314 file_mips_isa
= ISA_MIPS64R2
;
13317 case OPTION_MIPS64
:
13318 file_mips_isa
= ISA_MIPS64
;
13322 mips_set_option_string (&mips_tune_string
, arg
);
13326 mips_set_option_string (&mips_arch_string
, arg
);
13330 mips_set_option_string (&mips_arch_string
, "4650");
13331 mips_set_option_string (&mips_tune_string
, "4650");
13334 case OPTION_NO_M4650
:
13338 mips_set_option_string (&mips_arch_string
, "4010");
13339 mips_set_option_string (&mips_tune_string
, "4010");
13342 case OPTION_NO_M4010
:
13346 mips_set_option_string (&mips_arch_string
, "4100");
13347 mips_set_option_string (&mips_tune_string
, "4100");
13350 case OPTION_NO_M4100
:
13354 mips_set_option_string (&mips_arch_string
, "3900");
13355 mips_set_option_string (&mips_tune_string
, "3900");
13358 case OPTION_NO_M3900
:
13361 case OPTION_MICROMIPS
:
13362 if (mips_opts
.mips16
== 1)
13364 as_bad (_("-mmicromips cannot be used with -mips16"));
13367 mips_opts
.micromips
= 1;
13368 mips_no_prev_insn ();
13371 case OPTION_NO_MICROMIPS
:
13372 mips_opts
.micromips
= 0;
13373 mips_no_prev_insn ();
13376 case OPTION_MIPS16
:
13377 if (mips_opts
.micromips
== 1)
13379 as_bad (_("-mips16 cannot be used with -micromips"));
13382 mips_opts
.mips16
= 1;
13383 mips_no_prev_insn ();
13386 case OPTION_NO_MIPS16
:
13387 mips_opts
.mips16
= 0;
13388 mips_no_prev_insn ();
13391 case OPTION_FIX_24K
:
13395 case OPTION_NO_FIX_24K
:
13399 case OPTION_FIX_LOONGSON2F_JUMP
:
13400 mips_fix_loongson2f_jump
= TRUE
;
13403 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13404 mips_fix_loongson2f_jump
= FALSE
;
13407 case OPTION_FIX_LOONGSON2F_NOP
:
13408 mips_fix_loongson2f_nop
= TRUE
;
13411 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13412 mips_fix_loongson2f_nop
= FALSE
;
13415 case OPTION_FIX_VR4120
:
13416 mips_fix_vr4120
= 1;
13419 case OPTION_NO_FIX_VR4120
:
13420 mips_fix_vr4120
= 0;
13423 case OPTION_FIX_VR4130
:
13424 mips_fix_vr4130
= 1;
13427 case OPTION_NO_FIX_VR4130
:
13428 mips_fix_vr4130
= 0;
13431 case OPTION_FIX_CN63XXP1
:
13432 mips_fix_cn63xxp1
= TRUE
;
13435 case OPTION_NO_FIX_CN63XXP1
:
13436 mips_fix_cn63xxp1
= FALSE
;
13439 case OPTION_RELAX_BRANCH
:
13440 mips_relax_branch
= 1;
13443 case OPTION_NO_RELAX_BRANCH
:
13444 mips_relax_branch
= 0;
13447 case OPTION_INSN32
:
13448 mips_opts
.insn32
= TRUE
;
13451 case OPTION_NO_INSN32
:
13452 mips_opts
.insn32
= FALSE
;
13455 case OPTION_MSHARED
:
13456 mips_in_shared
= TRUE
;
13459 case OPTION_MNO_SHARED
:
13460 mips_in_shared
= FALSE
;
13463 case OPTION_MSYM32
:
13464 mips_opts
.sym32
= TRUE
;
13467 case OPTION_MNO_SYM32
:
13468 mips_opts
.sym32
= FALSE
;
13471 /* When generating ELF code, we permit -KPIC and -call_shared to
13472 select SVR4_PIC, and -non_shared to select no PIC. This is
13473 intended to be compatible with Irix 5. */
13474 case OPTION_CALL_SHARED
:
13475 mips_pic
= SVR4_PIC
;
13476 mips_abicalls
= TRUE
;
13479 case OPTION_CALL_NONPIC
:
13481 mips_abicalls
= TRUE
;
13484 case OPTION_NON_SHARED
:
13486 mips_abicalls
= FALSE
;
13489 /* The -xgot option tells the assembler to use 32 bit offsets
13490 when accessing the got in SVR4_PIC mode. It is for Irix
13497 g_switch_value
= atoi (arg
);
13501 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13504 mips_abi
= O32_ABI
;
13508 mips_abi
= N32_ABI
;
13512 mips_abi
= N64_ABI
;
13513 if (!support_64bit_objects())
13514 as_fatal (_("No compiled in support for 64 bit object file format"));
13518 file_mips_gp32
= 1;
13522 file_mips_gp32
= 0;
13526 file_mips_fp32
= 1;
13530 file_mips_fp32
= 0;
13533 case OPTION_SINGLE_FLOAT
:
13534 file_mips_single_float
= 1;
13537 case OPTION_DOUBLE_FLOAT
:
13538 file_mips_single_float
= 0;
13541 case OPTION_SOFT_FLOAT
:
13542 file_mips_soft_float
= 1;
13545 case OPTION_HARD_FLOAT
:
13546 file_mips_soft_float
= 0;
13550 if (strcmp (arg
, "32") == 0)
13551 mips_abi
= O32_ABI
;
13552 else if (strcmp (arg
, "o64") == 0)
13553 mips_abi
= O64_ABI
;
13554 else if (strcmp (arg
, "n32") == 0)
13555 mips_abi
= N32_ABI
;
13556 else if (strcmp (arg
, "64") == 0)
13558 mips_abi
= N64_ABI
;
13559 if (! support_64bit_objects())
13560 as_fatal (_("No compiled in support for 64 bit object file "
13563 else if (strcmp (arg
, "eabi") == 0)
13564 mips_abi
= EABI_ABI
;
13567 as_fatal (_("invalid abi -mabi=%s"), arg
);
13572 case OPTION_M7000_HILO_FIX
:
13573 mips_7000_hilo_fix
= TRUE
;
13576 case OPTION_MNO_7000_HILO_FIX
:
13577 mips_7000_hilo_fix
= FALSE
;
13580 case OPTION_MDEBUG
:
13581 mips_flag_mdebug
= TRUE
;
13584 case OPTION_NO_MDEBUG
:
13585 mips_flag_mdebug
= FALSE
;
13589 mips_flag_pdr
= TRUE
;
13592 case OPTION_NO_PDR
:
13593 mips_flag_pdr
= FALSE
;
13596 case OPTION_MVXWORKS_PIC
:
13597 mips_pic
= VXWORKS_PIC
;
13601 if (strcmp (arg
, "2008") == 0)
13602 mips_flag_nan2008
= TRUE
;
13603 else if (strcmp (arg
, "legacy") == 0)
13604 mips_flag_nan2008
= FALSE
;
13607 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13616 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13621 /* Set up globals to generate code for the ISA or processor
13622 described by INFO. */
13625 mips_set_architecture (const struct mips_cpu_info
*info
)
13629 file_mips_arch
= info
->cpu
;
13630 mips_opts
.arch
= info
->cpu
;
13631 mips_opts
.isa
= info
->isa
;
13636 /* Likewise for tuning. */
13639 mips_set_tune (const struct mips_cpu_info
*info
)
13642 mips_tune
= info
->cpu
;
13647 mips_after_parse_args (void)
13649 const struct mips_cpu_info
*arch_info
= 0;
13650 const struct mips_cpu_info
*tune_info
= 0;
13652 /* GP relative stuff not working for PE */
13653 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13655 if (g_switch_seen
&& g_switch_value
!= 0)
13656 as_bad (_("-G not supported in this configuration."));
13657 g_switch_value
= 0;
13660 if (mips_abi
== NO_ABI
)
13661 mips_abi
= MIPS_DEFAULT_ABI
;
13663 /* The following code determines the architecture and register size.
13664 Similar code was added to GCC 3.3 (see override_options() in
13665 config/mips/mips.c). The GAS and GCC code should be kept in sync
13666 as much as possible. */
13668 if (mips_arch_string
!= 0)
13669 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13671 if (file_mips_isa
!= ISA_UNKNOWN
)
13673 /* Handle -mipsN. At this point, file_mips_isa contains the
13674 ISA level specified by -mipsN, while arch_info->isa contains
13675 the -march selection (if any). */
13676 if (arch_info
!= 0)
13678 /* -march takes precedence over -mipsN, since it is more descriptive.
13679 There's no harm in specifying both as long as the ISA levels
13681 if (file_mips_isa
!= arch_info
->isa
)
13682 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13683 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13684 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13687 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13690 if (arch_info
== 0)
13692 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13693 gas_assert (arch_info
);
13696 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13697 as_bad (_("-march=%s is not compatible with the selected ABI"),
13700 mips_set_architecture (arch_info
);
13702 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13703 if (mips_tune_string
!= 0)
13704 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13706 if (tune_info
== 0)
13707 mips_set_tune (arch_info
);
13709 mips_set_tune (tune_info
);
13711 if (file_mips_gp32
>= 0)
13713 /* The user specified the size of the integer registers. Make sure
13714 it agrees with the ABI and ISA. */
13715 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13716 as_bad (_("-mgp64 used with a 32-bit processor"));
13717 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13718 as_bad (_("-mgp32 used with a 64-bit ABI"));
13719 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13720 as_bad (_("-mgp64 used with a 32-bit ABI"));
13724 /* Infer the integer register size from the ABI and processor.
13725 Restrict ourselves to 32-bit registers if that's all the
13726 processor has, or if the ABI cannot handle 64-bit registers. */
13727 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13728 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13731 switch (file_mips_fp32
)
13735 /* No user specified float register size.
13736 ??? GAS treats single-float processors as though they had 64-bit
13737 float registers (although it complains when double-precision
13738 instructions are used). As things stand, saying they have 32-bit
13739 registers would lead to spurious "register must be even" messages.
13740 So here we assume float registers are never smaller than the
13742 if (file_mips_gp32
== 0)
13743 /* 64-bit integer registers implies 64-bit float registers. */
13744 file_mips_fp32
= 0;
13745 else if ((mips_opts
.ase
& FP64_ASES
)
13746 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13747 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13748 file_mips_fp32
= 0;
13750 /* 32-bit float registers. */
13751 file_mips_fp32
= 1;
13754 /* The user specified the size of the float registers. Check if it
13755 agrees with the ABI and ISA. */
13757 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13758 as_bad (_("-mfp64 used with a 32-bit fpu"));
13759 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13760 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13761 as_warn (_("-mfp64 used with a 32-bit ABI"));
13764 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13765 as_warn (_("-mfp32 used with a 64-bit ABI"));
13769 /* End of GCC-shared inference code. */
13771 /* This flag is set when we have a 64-bit capable CPU but use only
13772 32-bit wide registers. Note that EABI does not use it. */
13773 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
13774 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
13775 || mips_abi
== O32_ABI
))
13776 mips_32bitmode
= 1;
13778 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
13779 as_bad (_("trap exception not supported at ISA 1"));
13781 /* If the selected architecture includes support for ASEs, enable
13782 generation of code for them. */
13783 if (mips_opts
.mips16
== -1)
13784 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
13785 if (mips_opts
.micromips
== -1)
13786 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
13788 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13789 ASEs from being selected implicitly. */
13790 if (file_mips_fp32
== 1)
13791 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
13793 /* If the user didn't explicitly select or deselect a particular ASE,
13794 use the default setting for the CPU. */
13795 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
13797 file_mips_isa
= mips_opts
.isa
;
13798 file_ase
= mips_opts
.ase
;
13799 mips_opts
.gp32
= file_mips_gp32
;
13800 mips_opts
.fp32
= file_mips_fp32
;
13801 mips_opts
.soft_float
= file_mips_soft_float
;
13802 mips_opts
.single_float
= file_mips_single_float
;
13804 mips_check_isa_supports_ases ();
13806 if (mips_flag_mdebug
< 0)
13807 mips_flag_mdebug
= 0;
13811 mips_init_after_args (void)
13813 /* initialize opcodes */
13814 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
13815 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
13819 md_pcrel_from (fixS
*fixP
)
13821 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13822 switch (fixP
->fx_r_type
)
13824 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
13825 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
13826 /* Return the address of the delay slot. */
13829 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
13830 case BFD_RELOC_MICROMIPS_JMP
:
13831 case BFD_RELOC_16_PCREL_S2
:
13832 case BFD_RELOC_MIPS_JMP
:
13833 /* Return the address of the delay slot. */
13836 case BFD_RELOC_32_PCREL
:
13840 /* We have no relocation type for PC relative MIPS16 instructions. */
13841 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
13842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13843 _("PC relative MIPS16 instruction references a different section"));
13848 /* This is called before the symbol table is processed. In order to
13849 work with gcc when using mips-tfile, we must keep all local labels.
13850 However, in other cases, we want to discard them. If we were
13851 called with -g, but we didn't see any debugging information, it may
13852 mean that gcc is smuggling debugging information through to
13853 mips-tfile, in which case we must generate all local labels. */
13856 mips_frob_file_before_adjust (void)
13858 #ifndef NO_ECOFF_DEBUGGING
13859 if (ECOFF_DEBUGGING
13861 && ! ecoff_debugging_seen
)
13862 flag_keep_locals
= 1;
13866 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13867 the corresponding LO16 reloc. This is called before md_apply_fix and
13868 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13869 relocation operators.
13871 For our purposes, a %lo() expression matches a %got() or %hi()
13874 (a) it refers to the same symbol; and
13875 (b) the offset applied in the %lo() expression is no lower than
13876 the offset applied in the %got() or %hi().
13878 (b) allows us to cope with code like:
13881 lh $4,%lo(foo+2)($4)
13883 ...which is legal on RELA targets, and has a well-defined behaviour
13884 if the user knows that adding 2 to "foo" will not induce a carry to
13887 When several %lo()s match a particular %got() or %hi(), we use the
13888 following rules to distinguish them:
13890 (1) %lo()s with smaller offsets are a better match than %lo()s with
13893 (2) %lo()s with no matching %got() or %hi() are better than those
13894 that already have a matching %got() or %hi().
13896 (3) later %lo()s are better than earlier %lo()s.
13898 These rules are applied in order.
13900 (1) means, among other things, that %lo()s with identical offsets are
13901 chosen if they exist.
13903 (2) means that we won't associate several high-part relocations with
13904 the same low-part relocation unless there's no alternative. Having
13905 several high parts for the same low part is a GNU extension; this rule
13906 allows careful users to avoid it.
13908 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13909 with the last high-part relocation being at the front of the list.
13910 It therefore makes sense to choose the last matching low-part
13911 relocation, all other things being equal. It's also easier
13912 to code that way. */
13915 mips_frob_file (void)
13917 struct mips_hi_fixup
*l
;
13918 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
13920 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
13922 segment_info_type
*seginfo
;
13923 bfd_boolean matched_lo_p
;
13924 fixS
**hi_pos
, **lo_pos
, **pos
;
13926 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
13928 /* If a GOT16 relocation turns out to be against a global symbol,
13929 there isn't supposed to be a matching LO. Ignore %gots against
13930 constants; we'll report an error for those later. */
13931 if (got16_reloc_p (l
->fixp
->fx_r_type
)
13932 && !(l
->fixp
->fx_addsy
13933 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
13936 /* Check quickly whether the next fixup happens to be a matching %lo. */
13937 if (fixup_has_matching_lo_p (l
->fixp
))
13940 seginfo
= seg_info (l
->seg
);
13942 /* Set HI_POS to the position of this relocation in the chain.
13943 Set LO_POS to the position of the chosen low-part relocation.
13944 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13945 relocation that matches an immediately-preceding high-part
13949 matched_lo_p
= FALSE
;
13950 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
13952 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
13954 if (*pos
== l
->fixp
)
13957 if ((*pos
)->fx_r_type
== looking_for_rtype
13958 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
13959 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
13961 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
13963 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
13966 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
13967 && fixup_has_matching_lo_p (*pos
));
13970 /* If we found a match, remove the high-part relocation from its
13971 current position and insert it before the low-part relocation.
13972 Make the offsets match so that fixup_has_matching_lo_p()
13975 We don't warn about unmatched high-part relocations since some
13976 versions of gcc have been known to emit dead "lui ...%hi(...)"
13978 if (lo_pos
!= NULL
)
13980 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
13981 if (l
->fixp
->fx_next
!= *lo_pos
)
13983 *hi_pos
= l
->fixp
->fx_next
;
13984 l
->fixp
->fx_next
= *lo_pos
;
13992 mips_force_relocation (fixS
*fixp
)
13994 if (generic_force_reloc (fixp
))
13997 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13998 so that the linker relaxation can update targets. */
13999 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14000 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14001 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14007 /* Read the instruction associated with RELOC from BUF. */
14009 static unsigned int
14010 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14012 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14013 return read_compressed_insn (buf
, 4);
14015 return read_insn (buf
);
14018 /* Write instruction INSN to BUF, given that it has been relocated
14022 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14023 unsigned long insn
)
14025 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14026 write_compressed_insn (buf
, insn
, 4);
14028 write_insn (buf
, insn
);
14031 /* Apply a fixup to the object file. */
14034 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14037 unsigned long insn
;
14038 reloc_howto_type
*howto
;
14040 /* We ignore generic BFD relocations we don't know about. */
14041 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14045 gas_assert (fixP
->fx_size
== 2
14046 || fixP
->fx_size
== 4
14047 || fixP
->fx_r_type
== BFD_RELOC_16
14048 || fixP
->fx_r_type
== BFD_RELOC_64
14049 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14050 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14051 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14052 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14053 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14054 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14056 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14058 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14059 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14060 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14061 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14062 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14064 /* Don't treat parts of a composite relocation as done. There are two
14067 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14068 should nevertheless be emitted if the first part is.
14070 (2) In normal usage, composite relocations are never assembly-time
14071 constants. The easiest way of dealing with the pathological
14072 exceptions is to generate a relocation against STN_UNDEF and
14073 leave everything up to the linker. */
14074 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14077 switch (fixP
->fx_r_type
)
14079 case BFD_RELOC_MIPS_TLS_GD
:
14080 case BFD_RELOC_MIPS_TLS_LDM
:
14081 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14082 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14083 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14084 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14085 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14086 case BFD_RELOC_MIPS_TLS_TPREL32
:
14087 case BFD_RELOC_MIPS_TLS_TPREL64
:
14088 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14089 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14090 case BFD_RELOC_MICROMIPS_TLS_GD
:
14091 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14092 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14093 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14094 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14095 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14096 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14097 case BFD_RELOC_MIPS16_TLS_GD
:
14098 case BFD_RELOC_MIPS16_TLS_LDM
:
14099 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14100 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14101 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14102 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14103 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14104 if (!fixP
->fx_addsy
)
14106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14107 _("TLS relocation against a constant"));
14110 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14113 case BFD_RELOC_MIPS_JMP
:
14114 case BFD_RELOC_MIPS_SHIFT5
:
14115 case BFD_RELOC_MIPS_SHIFT6
:
14116 case BFD_RELOC_MIPS_GOT_DISP
:
14117 case BFD_RELOC_MIPS_GOT_PAGE
:
14118 case BFD_RELOC_MIPS_GOT_OFST
:
14119 case BFD_RELOC_MIPS_SUB
:
14120 case BFD_RELOC_MIPS_INSERT_A
:
14121 case BFD_RELOC_MIPS_INSERT_B
:
14122 case BFD_RELOC_MIPS_DELETE
:
14123 case BFD_RELOC_MIPS_HIGHEST
:
14124 case BFD_RELOC_MIPS_HIGHER
:
14125 case BFD_RELOC_MIPS_SCN_DISP
:
14126 case BFD_RELOC_MIPS_REL16
:
14127 case BFD_RELOC_MIPS_RELGOT
:
14128 case BFD_RELOC_MIPS_JALR
:
14129 case BFD_RELOC_HI16
:
14130 case BFD_RELOC_HI16_S
:
14131 case BFD_RELOC_LO16
:
14132 case BFD_RELOC_GPREL16
:
14133 case BFD_RELOC_MIPS_LITERAL
:
14134 case BFD_RELOC_MIPS_CALL16
:
14135 case BFD_RELOC_MIPS_GOT16
:
14136 case BFD_RELOC_GPREL32
:
14137 case BFD_RELOC_MIPS_GOT_HI16
:
14138 case BFD_RELOC_MIPS_GOT_LO16
:
14139 case BFD_RELOC_MIPS_CALL_HI16
:
14140 case BFD_RELOC_MIPS_CALL_LO16
:
14141 case BFD_RELOC_MIPS16_GPREL
:
14142 case BFD_RELOC_MIPS16_GOT16
:
14143 case BFD_RELOC_MIPS16_CALL16
:
14144 case BFD_RELOC_MIPS16_HI16
:
14145 case BFD_RELOC_MIPS16_HI16_S
:
14146 case BFD_RELOC_MIPS16_LO16
:
14147 case BFD_RELOC_MIPS16_JMP
:
14148 case BFD_RELOC_MICROMIPS_JMP
:
14149 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14150 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14151 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14152 case BFD_RELOC_MICROMIPS_SUB
:
14153 case BFD_RELOC_MICROMIPS_HIGHEST
:
14154 case BFD_RELOC_MICROMIPS_HIGHER
:
14155 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14156 case BFD_RELOC_MICROMIPS_JALR
:
14157 case BFD_RELOC_MICROMIPS_HI16
:
14158 case BFD_RELOC_MICROMIPS_HI16_S
:
14159 case BFD_RELOC_MICROMIPS_LO16
:
14160 case BFD_RELOC_MICROMIPS_GPREL16
:
14161 case BFD_RELOC_MICROMIPS_LITERAL
:
14162 case BFD_RELOC_MICROMIPS_CALL16
:
14163 case BFD_RELOC_MICROMIPS_GOT16
:
14164 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14165 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14166 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14167 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14168 case BFD_RELOC_MIPS_EH
:
14173 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14175 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14176 if (mips16_reloc_p (fixP
->fx_r_type
))
14177 insn
|= mips16_immed_extend (value
, 16);
14179 insn
|= (value
& 0xffff);
14180 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14184 _("Unsupported constant in relocation"));
14189 /* This is handled like BFD_RELOC_32, but we output a sign
14190 extended value if we are only 32 bits. */
14193 if (8 <= sizeof (valueT
))
14194 md_number_to_chars (buf
, *valP
, 8);
14199 if ((*valP
& 0x80000000) != 0)
14203 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14204 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14209 case BFD_RELOC_RVA
:
14211 case BFD_RELOC_32_PCREL
:
14213 /* If we are deleting this reloc entry, we must fill in the
14214 value now. This can happen if we have a .word which is not
14215 resolved when it appears but is later defined. */
14217 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14220 case BFD_RELOC_16_PCREL_S2
:
14221 if ((*valP
& 0x3) != 0)
14222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14223 _("Branch to misaligned address (%lx)"), (long) *valP
);
14225 /* We need to save the bits in the instruction since fixup_segment()
14226 might be deleting the relocation entry (i.e., a branch within
14227 the current segment). */
14228 if (! fixP
->fx_done
)
14231 /* Update old instruction data. */
14232 insn
= read_insn (buf
);
14234 if (*valP
+ 0x20000 <= 0x3ffff)
14236 insn
|= (*valP
>> 2) & 0xffff;
14237 write_insn (buf
, insn
);
14239 else if (mips_pic
== NO_PIC
14241 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14242 && (fixP
->fx_frag
->fr_address
14243 < text_section
->vma
+ bfd_get_section_size (text_section
))
14244 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14245 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14246 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14248 /* The branch offset is too large. If this is an
14249 unconditional branch, and we are not generating PIC code,
14250 we can convert it to an absolute jump instruction. */
14251 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14252 insn
= 0x0c000000; /* jal */
14254 insn
= 0x08000000; /* j */
14255 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14257 fixP
->fx_addsy
= section_symbol (text_section
);
14258 *valP
+= md_pcrel_from (fixP
);
14259 write_insn (buf
, insn
);
14263 /* If we got here, we have branch-relaxation disabled,
14264 and there's nothing we can do to fix this instruction
14265 without turning it into a longer sequence. */
14266 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14267 _("Branch out of range"));
14271 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14272 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14273 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14274 /* We adjust the offset back to even. */
14275 if ((*valP
& 0x1) != 0)
14278 if (! fixP
->fx_done
)
14281 /* Should never visit here, because we keep the relocation. */
14285 case BFD_RELOC_VTABLE_INHERIT
:
14288 && !S_IS_DEFINED (fixP
->fx_addsy
)
14289 && !S_IS_WEAK (fixP
->fx_addsy
))
14290 S_SET_WEAK (fixP
->fx_addsy
);
14293 case BFD_RELOC_VTABLE_ENTRY
:
14301 /* Remember value for tc_gen_reloc. */
14302 fixP
->fx_addnumber
= *valP
;
14312 name
= input_line_pointer
;
14313 c
= get_symbol_end ();
14314 p
= (symbolS
*) symbol_find_or_make (name
);
14315 *input_line_pointer
= c
;
14319 /* Align the current frag to a given power of two. If a particular
14320 fill byte should be used, FILL points to an integer that contains
14321 that byte, otherwise FILL is null.
14323 This function used to have the comment:
14325 The MIPS assembler also automatically adjusts any preceding label.
14327 The implementation therefore applied the adjustment to a maximum of
14328 one label. However, other label adjustments are applied to batches
14329 of labels, and adjusting just one caused problems when new labels
14330 were added for the sake of debugging or unwind information.
14331 We therefore adjust all preceding labels (given as LABELS) instead. */
14334 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14336 mips_emit_delays ();
14337 mips_record_compressed_mode ();
14338 if (fill
== NULL
&& subseg_text_p (now_seg
))
14339 frag_align_code (to
, 0);
14341 frag_align (to
, fill
? *fill
: 0, 0);
14342 record_alignment (now_seg
, to
);
14343 mips_move_labels (labels
, FALSE
);
14346 /* Align to a given power of two. .align 0 turns off the automatic
14347 alignment used by the data creating pseudo-ops. */
14350 s_align (int x ATTRIBUTE_UNUSED
)
14352 int temp
, fill_value
, *fill_ptr
;
14353 long max_alignment
= 28;
14355 /* o Note that the assembler pulls down any immediately preceding label
14356 to the aligned address.
14357 o It's not documented but auto alignment is reinstated by
14358 a .align pseudo instruction.
14359 o Note also that after auto alignment is turned off the mips assembler
14360 issues an error on attempt to assemble an improperly aligned data item.
14363 temp
= get_absolute_expression ();
14364 if (temp
> max_alignment
)
14365 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14368 as_warn (_("Alignment negative: 0 assumed."));
14371 if (*input_line_pointer
== ',')
14373 ++input_line_pointer
;
14374 fill_value
= get_absolute_expression ();
14375 fill_ptr
= &fill_value
;
14381 segment_info_type
*si
= seg_info (now_seg
);
14382 struct insn_label_list
*l
= si
->label_list
;
14383 /* Auto alignment should be switched on by next section change. */
14385 mips_align (temp
, fill_ptr
, l
);
14392 demand_empty_rest_of_line ();
14396 s_change_sec (int sec
)
14400 /* The ELF backend needs to know that we are changing sections, so
14401 that .previous works correctly. We could do something like check
14402 for an obj_section_change_hook macro, but that might be confusing
14403 as it would not be appropriate to use it in the section changing
14404 functions in read.c, since obj-elf.c intercepts those. FIXME:
14405 This should be cleaner, somehow. */
14406 obj_elf_section_change_hook ();
14408 mips_emit_delays ();
14419 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14420 demand_empty_rest_of_line ();
14424 seg
= subseg_new (RDATA_SECTION_NAME
,
14425 (subsegT
) get_absolute_expression ());
14426 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14427 | SEC_READONLY
| SEC_RELOC
14429 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14430 record_alignment (seg
, 4);
14431 demand_empty_rest_of_line ();
14435 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14436 bfd_set_section_flags (stdoutput
, seg
,
14437 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14438 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14439 record_alignment (seg
, 4);
14440 demand_empty_rest_of_line ();
14444 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14445 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14446 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14447 record_alignment (seg
, 4);
14448 demand_empty_rest_of_line ();
14456 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14458 char *section_name
;
14463 int section_entry_size
;
14464 int section_alignment
;
14466 section_name
= input_line_pointer
;
14467 c
= get_symbol_end ();
14469 next_c
= *(input_line_pointer
+ 1);
14471 /* Do we have .section Name<,"flags">? */
14472 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14474 /* just after name is now '\0'. */
14475 *input_line_pointer
= c
;
14476 input_line_pointer
= section_name
;
14477 obj_elf_section (ignore
);
14480 input_line_pointer
++;
14482 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14484 section_type
= get_absolute_expression ();
14487 if (*input_line_pointer
++ == ',')
14488 section_flag
= get_absolute_expression ();
14491 if (*input_line_pointer
++ == ',')
14492 section_entry_size
= get_absolute_expression ();
14494 section_entry_size
= 0;
14495 if (*input_line_pointer
++ == ',')
14496 section_alignment
= get_absolute_expression ();
14498 section_alignment
= 0;
14499 /* FIXME: really ignore? */
14500 (void) section_alignment
;
14502 section_name
= xstrdup (section_name
);
14504 /* When using the generic form of .section (as implemented by obj-elf.c),
14505 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14506 traditionally had to fall back on the more common @progbits instead.
14508 There's nothing really harmful in this, since bfd will correct
14509 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14510 means that, for backwards compatibility, the special_section entries
14511 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14513 Even so, we shouldn't force users of the MIPS .section syntax to
14514 incorrectly label the sections as SHT_PROGBITS. The best compromise
14515 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14516 generic type-checking code. */
14517 if (section_type
== SHT_MIPS_DWARF
)
14518 section_type
= SHT_PROGBITS
;
14520 obj_elf_change_section (section_name
, section_type
, section_flag
,
14521 section_entry_size
, 0, 0, 0);
14523 if (now_seg
->name
!= section_name
)
14524 free (section_name
);
14528 mips_enable_auto_align (void)
14534 s_cons (int log_size
)
14536 segment_info_type
*si
= seg_info (now_seg
);
14537 struct insn_label_list
*l
= si
->label_list
;
14539 mips_emit_delays ();
14540 if (log_size
> 0 && auto_align
)
14541 mips_align (log_size
, 0, l
);
14542 cons (1 << log_size
);
14543 mips_clear_insn_labels ();
14547 s_float_cons (int type
)
14549 segment_info_type
*si
= seg_info (now_seg
);
14550 struct insn_label_list
*l
= si
->label_list
;
14552 mips_emit_delays ();
14557 mips_align (3, 0, l
);
14559 mips_align (2, 0, l
);
14563 mips_clear_insn_labels ();
14566 /* Handle .globl. We need to override it because on Irix 5 you are
14569 where foo is an undefined symbol, to mean that foo should be
14570 considered to be the address of a function. */
14573 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14582 name
= input_line_pointer
;
14583 c
= get_symbol_end ();
14584 symbolP
= symbol_find_or_make (name
);
14585 S_SET_EXTERNAL (symbolP
);
14587 *input_line_pointer
= c
;
14588 SKIP_WHITESPACE ();
14590 /* On Irix 5, every global symbol that is not explicitly labelled as
14591 being a function is apparently labelled as being an object. */
14594 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14595 && (*input_line_pointer
!= ','))
14600 secname
= input_line_pointer
;
14601 c
= get_symbol_end ();
14602 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14604 as_bad (_("%s: no such section"), secname
);
14605 *input_line_pointer
= c
;
14607 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14608 flag
= BSF_FUNCTION
;
14611 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14613 c
= *input_line_pointer
;
14616 input_line_pointer
++;
14617 SKIP_WHITESPACE ();
14618 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14624 demand_empty_rest_of_line ();
14628 s_option (int x ATTRIBUTE_UNUSED
)
14633 opt
= input_line_pointer
;
14634 c
= get_symbol_end ();
14638 /* FIXME: What does this mean? */
14640 else if (strncmp (opt
, "pic", 3) == 0)
14644 i
= atoi (opt
+ 3);
14649 mips_pic
= SVR4_PIC
;
14650 mips_abicalls
= TRUE
;
14653 as_bad (_(".option pic%d not supported"), i
);
14655 if (mips_pic
== SVR4_PIC
)
14657 if (g_switch_seen
&& g_switch_value
!= 0)
14658 as_warn (_("-G may not be used with SVR4 PIC code"));
14659 g_switch_value
= 0;
14660 bfd_set_gp_size (stdoutput
, 0);
14664 as_warn (_("Unrecognized option \"%s\""), opt
);
14666 *input_line_pointer
= c
;
14667 demand_empty_rest_of_line ();
14670 /* This structure is used to hold a stack of .set values. */
14672 struct mips_option_stack
14674 struct mips_option_stack
*next
;
14675 struct mips_set_options options
;
14678 static struct mips_option_stack
*mips_opts_stack
;
14680 /* Handle the .set pseudo-op. */
14683 s_mipsset (int x ATTRIBUTE_UNUSED
)
14685 char *name
= input_line_pointer
, ch
;
14686 const struct mips_ase
*ase
;
14688 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14689 ++input_line_pointer
;
14690 ch
= *input_line_pointer
;
14691 *input_line_pointer
= '\0';
14693 if (strcmp (name
, "reorder") == 0)
14695 if (mips_opts
.noreorder
)
14698 else if (strcmp (name
, "noreorder") == 0)
14700 if (!mips_opts
.noreorder
)
14701 start_noreorder ();
14703 else if (strncmp (name
, "at=", 3) == 0)
14705 char *s
= name
+ 3;
14707 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14708 as_bad (_("Unrecognized register name `%s'"), s
);
14710 else if (strcmp (name
, "at") == 0)
14712 mips_opts
.at
= ATREG
;
14714 else if (strcmp (name
, "noat") == 0)
14716 mips_opts
.at
= ZERO
;
14718 else if (strcmp (name
, "macro") == 0)
14720 mips_opts
.warn_about_macros
= 0;
14722 else if (strcmp (name
, "nomacro") == 0)
14724 if (mips_opts
.noreorder
== 0)
14725 as_bad (_("`noreorder' must be set before `nomacro'"));
14726 mips_opts
.warn_about_macros
= 1;
14728 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14730 mips_opts
.nomove
= 0;
14732 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14734 mips_opts
.nomove
= 1;
14736 else if (strcmp (name
, "bopt") == 0)
14738 mips_opts
.nobopt
= 0;
14740 else if (strcmp (name
, "nobopt") == 0)
14742 mips_opts
.nobopt
= 1;
14744 else if (strcmp (name
, "gp=default") == 0)
14745 mips_opts
.gp32
= file_mips_gp32
;
14746 else if (strcmp (name
, "gp=32") == 0)
14747 mips_opts
.gp32
= 1;
14748 else if (strcmp (name
, "gp=64") == 0)
14750 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14751 as_warn (_("%s isa does not support 64-bit registers"),
14752 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14753 mips_opts
.gp32
= 0;
14755 else if (strcmp (name
, "fp=default") == 0)
14756 mips_opts
.fp32
= file_mips_fp32
;
14757 else if (strcmp (name
, "fp=32") == 0)
14758 mips_opts
.fp32
= 1;
14759 else if (strcmp (name
, "fp=64") == 0)
14761 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14762 as_warn (_("%s isa does not support 64-bit floating point registers"),
14763 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14764 mips_opts
.fp32
= 0;
14766 else if (strcmp (name
, "softfloat") == 0)
14767 mips_opts
.soft_float
= 1;
14768 else if (strcmp (name
, "hardfloat") == 0)
14769 mips_opts
.soft_float
= 0;
14770 else if (strcmp (name
, "singlefloat") == 0)
14771 mips_opts
.single_float
= 1;
14772 else if (strcmp (name
, "doublefloat") == 0)
14773 mips_opts
.single_float
= 0;
14774 else if (strcmp (name
, "mips16") == 0
14775 || strcmp (name
, "MIPS-16") == 0)
14777 if (mips_opts
.micromips
== 1)
14778 as_fatal (_("`mips16' cannot be used with `micromips'"));
14779 mips_opts
.mips16
= 1;
14781 else if (strcmp (name
, "nomips16") == 0
14782 || strcmp (name
, "noMIPS-16") == 0)
14783 mips_opts
.mips16
= 0;
14784 else if (strcmp (name
, "micromips") == 0)
14786 if (mips_opts
.mips16
== 1)
14787 as_fatal (_("`micromips' cannot be used with `mips16'"));
14788 mips_opts
.micromips
= 1;
14790 else if (strcmp (name
, "nomicromips") == 0)
14791 mips_opts
.micromips
= 0;
14792 else if (name
[0] == 'n'
14794 && (ase
= mips_lookup_ase (name
+ 2)))
14795 mips_set_ase (ase
, FALSE
);
14796 else if ((ase
= mips_lookup_ase (name
)))
14797 mips_set_ase (ase
, TRUE
);
14798 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
14802 /* Permit the user to change the ISA and architecture on the fly.
14803 Needless to say, misuse can cause serious problems. */
14804 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
14807 mips_opts
.isa
= file_mips_isa
;
14808 mips_opts
.arch
= file_mips_arch
;
14810 else if (strncmp (name
, "arch=", 5) == 0)
14812 const struct mips_cpu_info
*p
;
14814 p
= mips_parse_cpu("internal use", name
+ 5);
14816 as_bad (_("unknown architecture %s"), name
+ 5);
14819 mips_opts
.arch
= p
->cpu
;
14820 mips_opts
.isa
= p
->isa
;
14823 else if (strncmp (name
, "mips", 4) == 0)
14825 const struct mips_cpu_info
*p
;
14827 p
= mips_parse_cpu("internal use", name
);
14829 as_bad (_("unknown ISA level %s"), name
+ 4);
14832 mips_opts
.arch
= p
->cpu
;
14833 mips_opts
.isa
= p
->isa
;
14837 as_bad (_("unknown ISA or architecture %s"), name
);
14839 switch (mips_opts
.isa
)
14847 mips_opts
.gp32
= 1;
14848 mips_opts
.fp32
= 1;
14855 mips_opts
.gp32
= 0;
14856 if (mips_opts
.arch
== CPU_R5900
)
14858 mips_opts
.fp32
= 1;
14862 mips_opts
.fp32
= 0;
14866 as_bad (_("unknown ISA level %s"), name
+ 4);
14871 mips_opts
.gp32
= file_mips_gp32
;
14872 mips_opts
.fp32
= file_mips_fp32
;
14875 else if (strcmp (name
, "autoextend") == 0)
14876 mips_opts
.noautoextend
= 0;
14877 else if (strcmp (name
, "noautoextend") == 0)
14878 mips_opts
.noautoextend
= 1;
14879 else if (strcmp (name
, "insn32") == 0)
14880 mips_opts
.insn32
= TRUE
;
14881 else if (strcmp (name
, "noinsn32") == 0)
14882 mips_opts
.insn32
= FALSE
;
14883 else if (strcmp (name
, "push") == 0)
14885 struct mips_option_stack
*s
;
14887 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
14888 s
->next
= mips_opts_stack
;
14889 s
->options
= mips_opts
;
14890 mips_opts_stack
= s
;
14892 else if (strcmp (name
, "pop") == 0)
14894 struct mips_option_stack
*s
;
14896 s
= mips_opts_stack
;
14898 as_bad (_(".set pop with no .set push"));
14901 /* If we're changing the reorder mode we need to handle
14902 delay slots correctly. */
14903 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
14904 start_noreorder ();
14905 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
14908 mips_opts
= s
->options
;
14909 mips_opts_stack
= s
->next
;
14913 else if (strcmp (name
, "sym32") == 0)
14914 mips_opts
.sym32
= TRUE
;
14915 else if (strcmp (name
, "nosym32") == 0)
14916 mips_opts
.sym32
= FALSE
;
14917 else if (strchr (name
, ','))
14919 /* Generic ".set" directive; use the generic handler. */
14920 *input_line_pointer
= ch
;
14921 input_line_pointer
= name
;
14927 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
14929 mips_check_isa_supports_ases ();
14930 *input_line_pointer
= ch
;
14931 demand_empty_rest_of_line ();
14934 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14935 .option pic2. It means to generate SVR4 PIC calls. */
14938 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
14940 mips_pic
= SVR4_PIC
;
14941 mips_abicalls
= TRUE
;
14943 if (g_switch_seen
&& g_switch_value
!= 0)
14944 as_warn (_("-G may not be used with SVR4 PIC code"));
14945 g_switch_value
= 0;
14947 bfd_set_gp_size (stdoutput
, 0);
14948 demand_empty_rest_of_line ();
14951 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14952 PIC code. It sets the $gp register for the function based on the
14953 function address, which is in the register named in the argument.
14954 This uses a relocation against _gp_disp, which is handled specially
14955 by the linker. The result is:
14956 lui $gp,%hi(_gp_disp)
14957 addiu $gp,$gp,%lo(_gp_disp)
14958 addu $gp,$gp,.cpload argument
14959 The .cpload argument is normally $25 == $t9.
14961 The -mno-shared option changes this to:
14962 lui $gp,%hi(__gnu_local_gp)
14963 addiu $gp,$gp,%lo(__gnu_local_gp)
14964 and the argument is ignored. This saves an instruction, but the
14965 resulting code is not position independent; it uses an absolute
14966 address for __gnu_local_gp. Thus code assembled with -mno-shared
14967 can go into an ordinary executable, but not into a shared library. */
14970 s_cpload (int ignore ATTRIBUTE_UNUSED
)
14976 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14977 .cpload is ignored. */
14978 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
14984 if (mips_opts
.mips16
)
14986 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14987 ignore_rest_of_line ();
14991 /* .cpload should be in a .set noreorder section. */
14992 if (mips_opts
.noreorder
== 0)
14993 as_warn (_(".cpload not in noreorder section"));
14995 reg
= tc_get_register (0);
14997 /* If we need to produce a 64-bit address, we are better off using
14998 the default instruction sequence. */
14999 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15001 ex
.X_op
= O_symbol
;
15002 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15004 ex
.X_op_symbol
= NULL
;
15005 ex
.X_add_number
= 0;
15007 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15008 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15010 mips_mark_labels ();
15011 mips_assembling_insn
= TRUE
;
15014 macro_build_lui (&ex
, mips_gp_register
);
15015 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15016 mips_gp_register
, BFD_RELOC_LO16
);
15018 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15019 mips_gp_register
, reg
);
15022 mips_assembling_insn
= FALSE
;
15023 demand_empty_rest_of_line ();
15026 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15027 .cpsetup $reg1, offset|$reg2, label
15029 If offset is given, this results in:
15030 sd $gp, offset($sp)
15031 lui $gp, %hi(%neg(%gp_rel(label)))
15032 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15033 daddu $gp, $gp, $reg1
15035 If $reg2 is given, this results in:
15036 daddu $reg2, $gp, $0
15037 lui $gp, %hi(%neg(%gp_rel(label)))
15038 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15039 daddu $gp, $gp, $reg1
15040 $reg1 is normally $25 == $t9.
15042 The -mno-shared option replaces the last three instructions with
15044 addiu $gp,$gp,%lo(_gp) */
15047 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15049 expressionS ex_off
;
15050 expressionS ex_sym
;
15053 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15054 We also need NewABI support. */
15055 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15061 if (mips_opts
.mips16
)
15063 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15064 ignore_rest_of_line ();
15068 reg1
= tc_get_register (0);
15069 SKIP_WHITESPACE ();
15070 if (*input_line_pointer
!= ',')
15072 as_bad (_("missing argument separator ',' for .cpsetup"));
15076 ++input_line_pointer
;
15077 SKIP_WHITESPACE ();
15078 if (*input_line_pointer
== '$')
15080 mips_cpreturn_register
= tc_get_register (0);
15081 mips_cpreturn_offset
= -1;
15085 mips_cpreturn_offset
= get_absolute_expression ();
15086 mips_cpreturn_register
= -1;
15088 SKIP_WHITESPACE ();
15089 if (*input_line_pointer
!= ',')
15091 as_bad (_("missing argument separator ',' for .cpsetup"));
15095 ++input_line_pointer
;
15096 SKIP_WHITESPACE ();
15097 expression (&ex_sym
);
15099 mips_mark_labels ();
15100 mips_assembling_insn
= TRUE
;
15103 if (mips_cpreturn_register
== -1)
15105 ex_off
.X_op
= O_constant
;
15106 ex_off
.X_add_symbol
= NULL
;
15107 ex_off
.X_op_symbol
= NULL
;
15108 ex_off
.X_add_number
= mips_cpreturn_offset
;
15110 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15111 BFD_RELOC_LO16
, SP
);
15114 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15115 mips_gp_register
, 0);
15117 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15119 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15120 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15123 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15124 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15125 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15127 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15128 mips_gp_register
, reg1
);
15134 ex
.X_op
= O_symbol
;
15135 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15136 ex
.X_op_symbol
= NULL
;
15137 ex
.X_add_number
= 0;
15139 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15140 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15142 macro_build_lui (&ex
, mips_gp_register
);
15143 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15144 mips_gp_register
, BFD_RELOC_LO16
);
15149 mips_assembling_insn
= FALSE
;
15150 demand_empty_rest_of_line ();
15154 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15156 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15157 .cplocal is ignored. */
15158 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15164 if (mips_opts
.mips16
)
15166 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15167 ignore_rest_of_line ();
15171 mips_gp_register
= tc_get_register (0);
15172 demand_empty_rest_of_line ();
15175 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15176 offset from $sp. The offset is remembered, and after making a PIC
15177 call $gp is restored from that location. */
15180 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15184 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15185 .cprestore is ignored. */
15186 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15192 if (mips_opts
.mips16
)
15194 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15195 ignore_rest_of_line ();
15199 mips_cprestore_offset
= get_absolute_expression ();
15200 mips_cprestore_valid
= 1;
15202 ex
.X_op
= O_constant
;
15203 ex
.X_add_symbol
= NULL
;
15204 ex
.X_op_symbol
= NULL
;
15205 ex
.X_add_number
= mips_cprestore_offset
;
15207 mips_mark_labels ();
15208 mips_assembling_insn
= TRUE
;
15211 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15212 SP
, HAVE_64BIT_ADDRESSES
);
15215 mips_assembling_insn
= FALSE
;
15216 demand_empty_rest_of_line ();
15219 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15220 was given in the preceding .cpsetup, it results in:
15221 ld $gp, offset($sp)
15223 If a register $reg2 was given there, it results in:
15224 daddu $gp, $reg2, $0 */
15227 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15231 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15232 We also need NewABI support. */
15233 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15239 if (mips_opts
.mips16
)
15241 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15242 ignore_rest_of_line ();
15246 mips_mark_labels ();
15247 mips_assembling_insn
= TRUE
;
15250 if (mips_cpreturn_register
== -1)
15252 ex
.X_op
= O_constant
;
15253 ex
.X_add_symbol
= NULL
;
15254 ex
.X_op_symbol
= NULL
;
15255 ex
.X_add_number
= mips_cpreturn_offset
;
15257 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15260 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15261 mips_cpreturn_register
, 0);
15264 mips_assembling_insn
= FALSE
;
15265 demand_empty_rest_of_line ();
15268 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15269 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15270 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15271 debug information or MIPS16 TLS. */
15274 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15275 bfd_reloc_code_real_type rtype
)
15282 if (ex
.X_op
!= O_symbol
)
15284 as_bad (_("Unsupported use of %s"), dirstr
);
15285 ignore_rest_of_line ();
15288 p
= frag_more (bytes
);
15289 md_number_to_chars (p
, 0, bytes
);
15290 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15291 demand_empty_rest_of_line ();
15292 mips_clear_insn_labels ();
15295 /* Handle .dtprelword. */
15298 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15300 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15303 /* Handle .dtpreldword. */
15306 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15308 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15311 /* Handle .tprelword. */
15314 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15316 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15319 /* Handle .tpreldword. */
15322 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15324 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15327 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15328 code. It sets the offset to use in gp_rel relocations. */
15331 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15333 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15334 We also need NewABI support. */
15335 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15341 mips_gprel_offset
= get_absolute_expression ();
15343 demand_empty_rest_of_line ();
15346 /* Handle the .gpword pseudo-op. This is used when generating PIC
15347 code. It generates a 32 bit GP relative reloc. */
15350 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15352 segment_info_type
*si
;
15353 struct insn_label_list
*l
;
15357 /* When not generating PIC code, this is treated as .word. */
15358 if (mips_pic
!= SVR4_PIC
)
15364 si
= seg_info (now_seg
);
15365 l
= si
->label_list
;
15366 mips_emit_delays ();
15368 mips_align (2, 0, l
);
15371 mips_clear_insn_labels ();
15373 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15375 as_bad (_("Unsupported use of .gpword"));
15376 ignore_rest_of_line ();
15380 md_number_to_chars (p
, 0, 4);
15381 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15382 BFD_RELOC_GPREL32
);
15384 demand_empty_rest_of_line ();
15388 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15390 segment_info_type
*si
;
15391 struct insn_label_list
*l
;
15395 /* When not generating PIC code, this is treated as .dword. */
15396 if (mips_pic
!= SVR4_PIC
)
15402 si
= seg_info (now_seg
);
15403 l
= si
->label_list
;
15404 mips_emit_delays ();
15406 mips_align (3, 0, l
);
15409 mips_clear_insn_labels ();
15411 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15413 as_bad (_("Unsupported use of .gpdword"));
15414 ignore_rest_of_line ();
15418 md_number_to_chars (p
, 0, 8);
15419 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15420 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15422 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15423 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15424 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15426 demand_empty_rest_of_line ();
15429 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15430 tables. It generates a R_MIPS_EH reloc. */
15433 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15438 mips_emit_delays ();
15441 mips_clear_insn_labels ();
15443 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15445 as_bad (_("Unsupported use of .ehword"));
15446 ignore_rest_of_line ();
15450 md_number_to_chars (p
, 0, 4);
15451 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15452 BFD_RELOC_MIPS_EH
);
15454 demand_empty_rest_of_line ();
15457 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15458 tables in SVR4 PIC code. */
15461 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15465 /* This is ignored when not generating SVR4 PIC code. */
15466 if (mips_pic
!= SVR4_PIC
)
15472 mips_mark_labels ();
15473 mips_assembling_insn
= TRUE
;
15475 /* Add $gp to the register named as an argument. */
15477 reg
= tc_get_register (0);
15478 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15481 mips_assembling_insn
= FALSE
;
15482 demand_empty_rest_of_line ();
15485 /* Handle the .insn pseudo-op. This marks instruction labels in
15486 mips16/micromips mode. This permits the linker to handle them specially,
15487 such as generating jalx instructions when needed. We also make
15488 them odd for the duration of the assembly, in order to generate the
15489 right sort of code. We will make them even in the adjust_symtab
15490 routine, while leaving them marked. This is convenient for the
15491 debugger and the disassembler. The linker knows to make them odd
15495 s_insn (int ignore ATTRIBUTE_UNUSED
)
15497 mips_mark_labels ();
15499 demand_empty_rest_of_line ();
15502 /* Handle the .nan pseudo-op. */
15505 s_nan (int ignore ATTRIBUTE_UNUSED
)
15507 static const char str_legacy
[] = "legacy";
15508 static const char str_2008
[] = "2008";
15511 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15513 if (i
== sizeof (str_2008
) - 1
15514 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15515 mips_flag_nan2008
= TRUE
;
15516 else if (i
== sizeof (str_legacy
) - 1
15517 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15518 mips_flag_nan2008
= FALSE
;
15520 as_bad (_("Bad .nan directive"));
15522 input_line_pointer
+= i
;
15523 demand_empty_rest_of_line ();
15526 /* Handle a .stab[snd] directive. Ideally these directives would be
15527 implemented in a transparent way, so that removing them would not
15528 have any effect on the generated instructions. However, s_stab
15529 internally changes the section, so in practice we need to decide
15530 now whether the preceding label marks compressed code. We do not
15531 support changing the compression mode of a label after a .stab*
15532 directive, such as in:
15538 so the current mode wins. */
15541 s_mips_stab (int type
)
15543 mips_mark_labels ();
15547 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15550 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15557 name
= input_line_pointer
;
15558 c
= get_symbol_end ();
15559 symbolP
= symbol_find_or_make (name
);
15560 S_SET_WEAK (symbolP
);
15561 *input_line_pointer
= c
;
15563 SKIP_WHITESPACE ();
15565 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15567 if (S_IS_DEFINED (symbolP
))
15569 as_bad (_("ignoring attempt to redefine symbol %s"),
15570 S_GET_NAME (symbolP
));
15571 ignore_rest_of_line ();
15575 if (*input_line_pointer
== ',')
15577 ++input_line_pointer
;
15578 SKIP_WHITESPACE ();
15582 if (exp
.X_op
!= O_symbol
)
15584 as_bad (_("bad .weakext directive"));
15585 ignore_rest_of_line ();
15588 symbol_set_value_expression (symbolP
, &exp
);
15591 demand_empty_rest_of_line ();
15594 /* Parse a register string into a number. Called from the ECOFF code
15595 to parse .frame. The argument is non-zero if this is the frame
15596 register, so that we can record it in mips_frame_reg. */
15599 tc_get_register (int frame
)
15603 SKIP_WHITESPACE ();
15604 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15608 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15609 mips_frame_reg_valid
= 1;
15610 mips_cprestore_valid
= 0;
15616 md_section_align (asection
*seg
, valueT addr
)
15618 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15620 /* We don't need to align ELF sections to the full alignment.
15621 However, Irix 5 may prefer that we align them at least to a 16
15622 byte boundary. We don't bother to align the sections if we
15623 are targeted for an embedded system. */
15624 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15629 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15632 /* Utility routine, called from above as well. If called while the
15633 input file is still being read, it's only an approximation. (For
15634 example, a symbol may later become defined which appeared to be
15635 undefined earlier.) */
15638 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15643 if (g_switch_value
> 0)
15645 const char *symname
;
15648 /* Find out whether this symbol can be referenced off the $gp
15649 register. It can be if it is smaller than the -G size or if
15650 it is in the .sdata or .sbss section. Certain symbols can
15651 not be referenced off the $gp, although it appears as though
15653 symname
= S_GET_NAME (sym
);
15654 if (symname
!= (const char *) NULL
15655 && (strcmp (symname
, "eprol") == 0
15656 || strcmp (symname
, "etext") == 0
15657 || strcmp (symname
, "_gp") == 0
15658 || strcmp (symname
, "edata") == 0
15659 || strcmp (symname
, "_fbss") == 0
15660 || strcmp (symname
, "_fdata") == 0
15661 || strcmp (symname
, "_ftext") == 0
15662 || strcmp (symname
, "end") == 0
15663 || strcmp (symname
, "_gp_disp") == 0))
15665 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15667 #ifndef NO_ECOFF_DEBUGGING
15668 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15669 && (symbol_get_obj (sym
)->ecoff_extern_size
15670 <= g_switch_value
))
15672 /* We must defer this decision until after the whole
15673 file has been read, since there might be a .extern
15674 after the first use of this symbol. */
15675 || (before_relaxing
15676 #ifndef NO_ECOFF_DEBUGGING
15677 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15679 && S_GET_VALUE (sym
) == 0)
15680 || (S_GET_VALUE (sym
) != 0
15681 && S_GET_VALUE (sym
) <= g_switch_value
)))
15685 const char *segname
;
15687 segname
= segment_name (S_GET_SEGMENT (sym
));
15688 gas_assert (strcmp (segname
, ".lit8") != 0
15689 && strcmp (segname
, ".lit4") != 0);
15690 change
= (strcmp (segname
, ".sdata") != 0
15691 && strcmp (segname
, ".sbss") != 0
15692 && strncmp (segname
, ".sdata.", 7) != 0
15693 && strncmp (segname
, ".sbss.", 6) != 0
15694 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15695 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15700 /* We are not optimizing for the $gp register. */
15705 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15708 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15712 /* Handle the case of a symbol equated to another symbol. */
15713 while (symbol_equated_reloc_p (sym
))
15717 /* It's possible to get a loop here in a badly written program. */
15718 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15724 if (symbol_section_p (sym
))
15727 symsec
= S_GET_SEGMENT (sym
);
15729 /* This must duplicate the test in adjust_reloc_syms. */
15730 return (!bfd_is_und_section (symsec
)
15731 && !bfd_is_abs_section (symsec
)
15732 && !bfd_is_com_section (symsec
)
15733 && !s_is_linkonce (sym
, segtype
)
15734 /* A global or weak symbol is treated as external. */
15735 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15739 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15740 extended opcode. SEC is the section the frag is in. */
15743 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15746 const struct mips16_immed_operand
*op
;
15748 int mintiny
, maxtiny
;
15752 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15754 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15757 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15758 op
= mips16_immed_operands
;
15759 while (op
->type
!= type
)
15762 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
15767 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
15770 maxtiny
= 1 << op
->nbits
;
15775 maxtiny
= (1 << op
->nbits
) - 1;
15780 mintiny
= - (1 << (op
->nbits
- 1));
15781 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
15784 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15785 val
= S_GET_VALUE (fragp
->fr_symbol
);
15786 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15792 /* We won't have the section when we are called from
15793 mips_relax_frag. However, we will always have been called
15794 from md_estimate_size_before_relax first. If this is a
15795 branch to a different section, we mark it as such. If SEC is
15796 NULL, and the frag is not marked, then it must be a branch to
15797 the same section. */
15800 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
15805 /* Must have been called from md_estimate_size_before_relax. */
15808 fragp
->fr_subtype
=
15809 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15811 /* FIXME: We should support this, and let the linker
15812 catch branches and loads that are out of range. */
15813 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
15814 _("unsupported PC relative reference to different section"));
15818 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
15819 /* Assume non-extended on the first relaxation pass.
15820 The address we have calculated will be bogus if this is
15821 a forward branch to another frag, as the forward frag
15822 will have fr_address == 0. */
15826 /* In this case, we know for sure that the symbol fragment is in
15827 the same section. If the relax_marker of the symbol fragment
15828 differs from the relax_marker of this fragment, we have not
15829 yet adjusted the symbol fragment fr_address. We want to add
15830 in STRETCH in order to get a better estimate of the address.
15831 This particularly matters because of the shift bits. */
15833 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
15837 /* Adjust stretch for any alignment frag. Note that if have
15838 been expanding the earlier code, the symbol may be
15839 defined in what appears to be an earlier frag. FIXME:
15840 This doesn't handle the fr_subtype field, which specifies
15841 a maximum number of bytes to skip when doing an
15843 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
15845 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
15848 stretch
= - ((- stretch
)
15849 & ~ ((1 << (int) f
->fr_offset
) - 1));
15851 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
15860 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
15862 /* The base address rules are complicated. The base address of
15863 a branch is the following instruction. The base address of a
15864 PC relative load or add is the instruction itself, but if it
15865 is in a delay slot (in which case it can not be extended) use
15866 the address of the instruction whose delay slot it is in. */
15867 if (type
== 'p' || type
== 'q')
15871 /* If we are currently assuming that this frag should be
15872 extended, then, the current address is two bytes
15874 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
15877 /* Ignore the low bit in the target, since it will be set
15878 for a text label. */
15879 if ((val
& 1) != 0)
15882 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
15884 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
15887 val
-= addr
& ~ ((1 << op
->shift
) - 1);
15889 /* Branch offsets have an implicit 0 in the lowest bit. */
15890 if (type
== 'p' || type
== 'q')
15893 /* If any of the shifted bits are set, we must use an extended
15894 opcode. If the address depends on the size of this
15895 instruction, this can lead to a loop, so we arrange to always
15896 use an extended opcode. We only check this when we are in
15897 the main relaxation loop, when SEC is NULL. */
15898 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
15900 fragp
->fr_subtype
=
15901 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15905 /* If we are about to mark a frag as extended because the value
15906 is precisely maxtiny + 1, then there is a chance of an
15907 infinite loop as in the following code:
15912 In this case when the la is extended, foo is 0x3fc bytes
15913 away, so the la can be shrunk, but then foo is 0x400 away, so
15914 the la must be extended. To avoid this loop, we mark the
15915 frag as extended if it was small, and is about to become
15916 extended with a value of maxtiny + 1. */
15917 if (val
== ((maxtiny
+ 1) << op
->shift
)
15918 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
15921 fragp
->fr_subtype
=
15922 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15926 else if (symsec
!= absolute_section
&& sec
!= NULL
)
15927 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
15929 if ((val
& ((1 << op
->shift
) - 1)) != 0
15930 || val
< (mintiny
<< op
->shift
)
15931 || val
> (maxtiny
<< op
->shift
))
15937 /* Compute the length of a branch sequence, and adjust the
15938 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15939 worst-case length is computed, with UPDATE being used to indicate
15940 whether an unconditional (-1), branch-likely (+1) or regular (0)
15941 branch is to be computed. */
15943 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
15945 bfd_boolean toofar
;
15949 && S_IS_DEFINED (fragp
->fr_symbol
)
15950 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
15955 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
15957 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
15961 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
15964 /* If the symbol is not defined or it's in a different segment,
15965 assume the user knows what's going on and emit a short
15971 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
15973 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
15974 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
15975 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
15976 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
15982 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
15985 if (mips_pic
!= NO_PIC
)
15987 /* Additional space for PIC loading of target address. */
15989 if (mips_opts
.isa
== ISA_MIPS1
)
15990 /* Additional space for $at-stabilizing nop. */
15994 /* If branch is conditional. */
15995 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16002 /* Compute the length of a branch sequence, and adjust the
16003 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16004 worst-case length is computed, with UPDATE being used to indicate
16005 whether an unconditional (-1), or regular (0) branch is to be
16009 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16011 bfd_boolean toofar
;
16015 && S_IS_DEFINED (fragp
->fr_symbol
)
16016 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16021 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16022 /* Ignore the low bit in the target, since it will be set
16023 for a text label. */
16024 if ((val
& 1) != 0)
16027 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16031 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16034 /* If the symbol is not defined or it's in a different segment,
16035 assume the user knows what's going on and emit a short
16041 if (fragp
&& update
16042 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16043 fragp
->fr_subtype
= (toofar
16044 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16045 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16050 bfd_boolean compact_known
= fragp
!= NULL
;
16051 bfd_boolean compact
= FALSE
;
16052 bfd_boolean uncond
;
16055 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16057 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16059 uncond
= update
< 0;
16061 /* If label is out of range, we turn branch <br>:
16063 <br> label # 4 bytes
16069 nop # 2 bytes if compact && !PIC
16072 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16075 /* If assembling PIC code, we further turn:
16081 lw/ld at, %got(label)(gp) # 4 bytes
16082 d/addiu at, %lo(label) # 4 bytes
16085 if (mips_pic
!= NO_PIC
)
16088 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16090 <brneg> 0f # 4 bytes
16091 nop # 2 bytes if !compact
16094 length
+= (compact_known
&& compact
) ? 4 : 6;
16100 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16101 bit accordingly. */
16104 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16106 bfd_boolean toofar
;
16109 && S_IS_DEFINED (fragp
->fr_symbol
)
16110 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16116 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16117 /* Ignore the low bit in the target, since it will be set
16118 for a text label. */
16119 if ((val
& 1) != 0)
16122 /* Assume this is a 2-byte branch. */
16123 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16125 /* We try to avoid the infinite loop by not adding 2 more bytes for
16130 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16132 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16133 else if (type
== 'E')
16134 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16139 /* If the symbol is not defined or it's in a different segment,
16140 we emit a normal 32-bit branch. */
16143 if (fragp
&& update
16144 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16146 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16147 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16155 /* Estimate the size of a frag before relaxing. Unless this is the
16156 mips16, we are not really relaxing here, and the final size is
16157 encoded in the subtype information. For the mips16, we have to
16158 decide whether we are using an extended opcode or not. */
16161 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16165 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16168 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16170 return fragp
->fr_var
;
16173 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16174 /* We don't want to modify the EXTENDED bit here; it might get us
16175 into infinite loops. We change it only in mips_relax_frag(). */
16176 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16178 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16182 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16183 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16184 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16185 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16186 fragp
->fr_var
= length
;
16191 if (mips_pic
== NO_PIC
)
16192 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16193 else if (mips_pic
== SVR4_PIC
)
16194 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16195 else if (mips_pic
== VXWORKS_PIC
)
16196 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16203 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16204 return -RELAX_FIRST (fragp
->fr_subtype
);
16207 return -RELAX_SECOND (fragp
->fr_subtype
);
16210 /* This is called to see whether a reloc against a defined symbol
16211 should be converted into a reloc against a section. */
16214 mips_fix_adjustable (fixS
*fixp
)
16216 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16217 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16220 if (fixp
->fx_addsy
== NULL
)
16223 /* If symbol SYM is in a mergeable section, relocations of the form
16224 SYM + 0 can usually be made section-relative. The mergeable data
16225 is then identified by the section offset rather than by the symbol.
16227 However, if we're generating REL LO16 relocations, the offset is split
16228 between the LO16 and parterning high part relocation. The linker will
16229 need to recalculate the complete offset in order to correctly identify
16232 The linker has traditionally not looked for the parterning high part
16233 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16234 placed anywhere. Rather than break backwards compatibility by changing
16235 this, it seems better not to force the issue, and instead keep the
16236 original symbol. This will work with either linker behavior. */
16237 if ((lo16_reloc_p (fixp
->fx_r_type
)
16238 || reloc_needs_lo_p (fixp
->fx_r_type
))
16239 && HAVE_IN_PLACE_ADDENDS
16240 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16243 /* There is no place to store an in-place offset for JALR relocations.
16244 Likewise an in-range offset of limited PC-relative relocations may
16245 overflow the in-place relocatable field if recalculated against the
16246 start address of the symbol's containing section. */
16247 if (HAVE_IN_PLACE_ADDENDS
16248 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16249 || jalr_reloc_p (fixp
->fx_r_type
)))
16252 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16253 to a floating-point stub. The same is true for non-R_MIPS16_26
16254 relocations against MIPS16 functions; in this case, the stub becomes
16255 the function's canonical address.
16257 Floating-point stubs are stored in unique .mips16.call.* or
16258 .mips16.fn.* sections. If a stub T for function F is in section S,
16259 the first relocation in section S must be against F; this is how the
16260 linker determines the target function. All relocations that might
16261 resolve to T must also be against F. We therefore have the following
16262 restrictions, which are given in an intentionally-redundant way:
16264 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16267 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16268 if that stub might be used.
16270 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16273 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16274 that stub might be used.
16276 There is a further restriction:
16278 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16279 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16280 targets with in-place addends; the relocation field cannot
16281 encode the low bit.
16283 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16284 against a MIPS16 symbol. We deal with (5) by by not reducing any
16285 such relocations on REL targets.
16287 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16288 relocation against some symbol R, no relocation against R may be
16289 reduced. (Note that this deals with (2) as well as (1) because
16290 relocations against global symbols will never be reduced on ELF
16291 targets.) This approach is a little simpler than trying to detect
16292 stub sections, and gives the "all or nothing" per-symbol consistency
16293 that we have for MIPS16 symbols. */
16294 if (fixp
->fx_subsy
== NULL
16295 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16296 || *symbol_get_tc (fixp
->fx_addsy
)
16297 || (HAVE_IN_PLACE_ADDENDS
16298 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16299 && jmp_reloc_p (fixp
->fx_r_type
))))
16305 /* Translate internal representation of relocation info to BFD target
16309 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16311 static arelent
*retval
[4];
16313 bfd_reloc_code_real_type code
;
16315 memset (retval
, 0, sizeof(retval
));
16316 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16317 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16318 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16319 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16321 if (fixp
->fx_pcrel
)
16323 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16324 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16325 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16326 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16327 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16329 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16330 Relocations want only the symbol offset. */
16331 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16334 reloc
->addend
= fixp
->fx_addnumber
;
16336 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16337 entry to be used in the relocation's section offset. */
16338 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16340 reloc
->address
= reloc
->addend
;
16344 code
= fixp
->fx_r_type
;
16346 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16347 if (reloc
->howto
== NULL
)
16349 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16350 _("Can not represent %s relocation in this object file format"),
16351 bfd_get_reloc_code_name (code
));
16358 /* Relax a machine dependent frag. This returns the amount by which
16359 the current size of the frag should change. */
16362 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16364 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16366 offsetT old_var
= fragp
->fr_var
;
16368 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16370 return fragp
->fr_var
- old_var
;
16373 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16375 offsetT old_var
= fragp
->fr_var
;
16376 offsetT new_var
= 4;
16378 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16379 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16380 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16381 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16382 fragp
->fr_var
= new_var
;
16384 return new_var
- old_var
;
16387 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16390 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16392 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16394 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16399 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16401 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16408 /* Convert a machine dependent frag. */
16411 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16413 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16416 unsigned long insn
;
16420 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16421 insn
= read_insn (buf
);
16423 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16425 /* We generate a fixup instead of applying it right now
16426 because, if there are linker relaxations, we're going to
16427 need the relocations. */
16428 exp
.X_op
= O_symbol
;
16429 exp
.X_add_symbol
= fragp
->fr_symbol
;
16430 exp
.X_add_number
= fragp
->fr_offset
;
16432 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16433 BFD_RELOC_16_PCREL_S2
);
16434 fixp
->fx_file
= fragp
->fr_file
;
16435 fixp
->fx_line
= fragp
->fr_line
;
16437 buf
= write_insn (buf
, insn
);
16443 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16444 _("Relaxed out-of-range branch into a jump"));
16446 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16449 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16451 /* Reverse the branch. */
16452 switch ((insn
>> 28) & 0xf)
16455 /* bc[0-3][tf]l? instructions can have the condition
16456 reversed by tweaking a single TF bit, and their
16457 opcodes all have 0x4???????. */
16458 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16459 insn
^= 0x00010000;
16463 /* bltz 0x04000000 bgez 0x04010000
16464 bltzal 0x04100000 bgezal 0x04110000 */
16465 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16466 insn
^= 0x00010000;
16470 /* beq 0x10000000 bne 0x14000000
16471 blez 0x18000000 bgtz 0x1c000000 */
16472 insn
^= 0x04000000;
16480 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16482 /* Clear the and-link bit. */
16483 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16485 /* bltzal 0x04100000 bgezal 0x04110000
16486 bltzall 0x04120000 bgezall 0x04130000 */
16487 insn
&= ~0x00100000;
16490 /* Branch over the branch (if the branch was likely) or the
16491 full jump (not likely case). Compute the offset from the
16492 current instruction to branch to. */
16493 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16497 /* How many bytes in instructions we've already emitted? */
16498 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16499 /* How many bytes in instructions from here to the end? */
16500 i
= fragp
->fr_var
- i
;
16502 /* Convert to instruction count. */
16504 /* Branch counts from the next instruction. */
16507 /* Branch over the jump. */
16508 buf
= write_insn (buf
, insn
);
16511 buf
= write_insn (buf
, 0);
16513 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16515 /* beql $0, $0, 2f */
16517 /* Compute the PC offset from the current instruction to
16518 the end of the variable frag. */
16519 /* How many bytes in instructions we've already emitted? */
16520 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16521 /* How many bytes in instructions from here to the end? */
16522 i
= fragp
->fr_var
- i
;
16523 /* Convert to instruction count. */
16525 /* Don't decrement i, because we want to branch over the
16529 buf
= write_insn (buf
, insn
);
16530 buf
= write_insn (buf
, 0);
16534 if (mips_pic
== NO_PIC
)
16537 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16538 ? 0x0c000000 : 0x08000000);
16539 exp
.X_op
= O_symbol
;
16540 exp
.X_add_symbol
= fragp
->fr_symbol
;
16541 exp
.X_add_number
= fragp
->fr_offset
;
16543 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16544 FALSE
, BFD_RELOC_MIPS_JMP
);
16545 fixp
->fx_file
= fragp
->fr_file
;
16546 fixp
->fx_line
= fragp
->fr_line
;
16548 buf
= write_insn (buf
, insn
);
16552 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16554 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16555 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16556 insn
|= at
<< OP_SH_RT
;
16557 exp
.X_op
= O_symbol
;
16558 exp
.X_add_symbol
= fragp
->fr_symbol
;
16559 exp
.X_add_number
= fragp
->fr_offset
;
16561 if (fragp
->fr_offset
)
16563 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16564 exp
.X_add_number
= 0;
16567 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16568 FALSE
, BFD_RELOC_MIPS_GOT16
);
16569 fixp
->fx_file
= fragp
->fr_file
;
16570 fixp
->fx_line
= fragp
->fr_line
;
16572 buf
= write_insn (buf
, insn
);
16574 if (mips_opts
.isa
== ISA_MIPS1
)
16576 buf
= write_insn (buf
, 0);
16578 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16579 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16580 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16582 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16583 FALSE
, BFD_RELOC_LO16
);
16584 fixp
->fx_file
= fragp
->fr_file
;
16585 fixp
->fx_line
= fragp
->fr_line
;
16587 buf
= write_insn (buf
, insn
);
16590 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16594 insn
|= at
<< OP_SH_RS
;
16596 buf
= write_insn (buf
, insn
);
16600 fragp
->fr_fix
+= fragp
->fr_var
;
16601 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16605 /* Relax microMIPS branches. */
16606 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16608 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16609 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16610 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16611 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16612 bfd_boolean short_ds
;
16613 unsigned long insn
;
16617 exp
.X_op
= O_symbol
;
16618 exp
.X_add_symbol
= fragp
->fr_symbol
;
16619 exp
.X_add_number
= fragp
->fr_offset
;
16621 fragp
->fr_fix
+= fragp
->fr_var
;
16623 /* Handle 16-bit branches that fit or are forced to fit. */
16624 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16626 /* We generate a fixup instead of applying it right now,
16627 because if there is linker relaxation, we're going to
16628 need the relocations. */
16630 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16631 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16632 else if (type
== 'E')
16633 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16634 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16638 fixp
->fx_file
= fragp
->fr_file
;
16639 fixp
->fx_line
= fragp
->fr_line
;
16641 /* These relocations can have an addend that won't fit in
16643 fixp
->fx_no_overflow
= 1;
16648 /* Handle 32-bit branches that fit or are forced to fit. */
16649 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16650 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16652 /* We generate a fixup instead of applying it right now,
16653 because if there is linker relaxation, we're going to
16654 need the relocations. */
16655 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16656 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16657 fixp
->fx_file
= fragp
->fr_file
;
16658 fixp
->fx_line
= fragp
->fr_line
;
16664 /* Relax 16-bit branches to 32-bit branches. */
16667 insn
= read_compressed_insn (buf
, 2);
16669 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16670 insn
= 0x94000000; /* beq */
16671 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16673 unsigned long regno
;
16675 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16676 regno
= micromips_to_32_reg_d_map
[regno
];
16677 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16678 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16683 /* Nothing else to do, just write it out. */
16684 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16685 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16687 buf
= write_compressed_insn (buf
, insn
, 4);
16688 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16693 insn
= read_compressed_insn (buf
, 4);
16695 /* Relax 32-bit branches to a sequence of instructions. */
16696 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16697 _("Relaxed out-of-range branch into a jump"));
16699 /* Set the short-delay-slot bit. */
16700 short_ds
= al
&& (insn
& 0x02000000) != 0;
16702 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16706 /* Reverse the branch. */
16707 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16708 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16709 insn
^= 0x20000000;
16710 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16711 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16712 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16713 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16714 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16715 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16716 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16717 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16718 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16719 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16720 insn
^= 0x00400000;
16721 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16722 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16723 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16724 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16725 insn
^= 0x00200000;
16731 /* Clear the and-link and short-delay-slot bits. */
16732 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16734 /* bltzal 0x40200000 bgezal 0x40600000 */
16735 /* bltzals 0x42200000 bgezals 0x42600000 */
16736 insn
&= ~0x02200000;
16739 /* Make a label at the end for use with the branch. */
16740 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16741 micromips_label_inc ();
16742 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16745 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16746 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16747 fixp
->fx_file
= fragp
->fr_file
;
16748 fixp
->fx_line
= fragp
->fr_line
;
16750 /* Branch over the jump. */
16751 buf
= write_compressed_insn (buf
, insn
, 4);
16754 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16757 if (mips_pic
== NO_PIC
)
16759 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16761 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16762 insn
= al
? jal
: 0xd4000000;
16764 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16765 BFD_RELOC_MICROMIPS_JMP
);
16766 fixp
->fx_file
= fragp
->fr_file
;
16767 fixp
->fx_line
= fragp
->fr_line
;
16769 buf
= write_compressed_insn (buf
, insn
, 4);
16772 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16776 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16777 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16778 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16780 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16781 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16782 insn
|= at
<< MICROMIPSOP_SH_RT
;
16784 if (exp
.X_add_number
)
16786 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16787 exp
.X_add_number
= 0;
16790 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16791 BFD_RELOC_MICROMIPS_GOT16
);
16792 fixp
->fx_file
= fragp
->fr_file
;
16793 fixp
->fx_line
= fragp
->fr_line
;
16795 buf
= write_compressed_insn (buf
, insn
, 4);
16797 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16798 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16799 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16801 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16802 BFD_RELOC_MICROMIPS_LO16
);
16803 fixp
->fx_file
= fragp
->fr_file
;
16804 fixp
->fx_line
= fragp
->fr_line
;
16806 buf
= write_compressed_insn (buf
, insn
, 4);
16808 /* jr/jrc/jalr/jalrs $at */
16809 insn
= al
? jalr
: jr
;
16810 insn
|= at
<< MICROMIPSOP_SH_MJ
;
16812 buf
= write_compressed_insn (buf
, insn
, 2);
16815 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16819 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16822 const struct mips16_immed_operand
*op
;
16825 unsigned int user_length
, length
;
16826 unsigned long insn
;
16829 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16830 op
= mips16_immed_operands
;
16831 while (op
->type
!= type
)
16834 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
16835 val
= resolve_symbol_value (fragp
->fr_symbol
);
16840 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16842 /* The rules for the base address of a PC relative reloc are
16843 complicated; see mips16_extended_frag. */
16844 if (type
== 'p' || type
== 'q')
16849 /* Ignore the low bit in the target, since it will be
16850 set for a text label. */
16851 if ((val
& 1) != 0)
16854 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16856 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16859 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
16862 /* Make sure the section winds up with the alignment we have
16865 record_alignment (asec
, op
->shift
);
16869 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
16870 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
16871 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16872 _("extended instruction in delay slot"));
16874 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16876 insn
= read_compressed_insn (buf
, 2);
16878 insn
|= MIPS16_EXTEND
;
16880 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16882 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16887 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
16888 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
16890 length
= (ext
? 4 : 2);
16891 gas_assert (mips16_opcode_length (insn
) == length
);
16892 write_compressed_insn (buf
, insn
, length
);
16893 fragp
->fr_fix
+= length
;
16897 relax_substateT subtype
= fragp
->fr_subtype
;
16898 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
16899 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
16903 first
= RELAX_FIRST (subtype
);
16904 second
= RELAX_SECOND (subtype
);
16905 fixp
= (fixS
*) fragp
->fr_opcode
;
16907 /* If the delay slot chosen does not match the size of the instruction,
16908 then emit a warning. */
16909 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
16910 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
16915 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
16916 | RELAX_DELAY_SLOT_SIZE_FIRST
16917 | RELAX_DELAY_SLOT_SIZE_SECOND
);
16918 msg
= macro_warning (s
);
16920 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
16924 /* Possibly emit a warning if we've chosen the longer option. */
16925 if (use_second
== second_longer
)
16931 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
16932 msg
= macro_warning (s
);
16934 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
16938 /* Go through all the fixups for the first sequence. Disable them
16939 (by marking them as done) if we're going to use the second
16940 sequence instead. */
16942 && fixp
->fx_frag
== fragp
16943 && fixp
->fx_where
< fragp
->fr_fix
- second
)
16945 if (subtype
& RELAX_USE_SECOND
)
16947 fixp
= fixp
->fx_next
;
16950 /* Go through the fixups for the second sequence. Disable them if
16951 we're going to use the first sequence, otherwise adjust their
16952 addresses to account for the relaxation. */
16953 while (fixp
&& fixp
->fx_frag
== fragp
)
16955 if (subtype
& RELAX_USE_SECOND
)
16956 fixp
->fx_where
-= first
;
16959 fixp
= fixp
->fx_next
;
16962 /* Now modify the frag contents. */
16963 if (subtype
& RELAX_USE_SECOND
)
16967 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
16968 memmove (start
, start
+ first
, second
);
16969 fragp
->fr_fix
-= first
;
16972 fragp
->fr_fix
-= second
;
16976 /* This function is called after the relocs have been generated.
16977 We've been storing mips16 text labels as odd. Here we convert them
16978 back to even for the convenience of the debugger. */
16981 mips_frob_file_after_relocs (void)
16984 unsigned int count
, i
;
16986 syms
= bfd_get_outsymbols (stdoutput
);
16987 count
= bfd_get_symcount (stdoutput
);
16988 for (i
= 0; i
< count
; i
++, syms
++)
16989 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
16990 && ((*syms
)->value
& 1) != 0)
16992 (*syms
)->value
&= ~1;
16993 /* If the symbol has an odd size, it was probably computed
16994 incorrectly, so adjust that as well. */
16995 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
16996 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17000 /* This function is called whenever a label is defined, including fake
17001 labels instantiated off the dot special symbol. It is used when
17002 handling branch delays; if a branch has a label, we assume we cannot
17003 move it. This also bumps the value of the symbol by 1 in compressed
17007 mips_record_label (symbolS
*sym
)
17009 segment_info_type
*si
= seg_info (now_seg
);
17010 struct insn_label_list
*l
;
17012 if (free_insn_labels
== NULL
)
17013 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17016 l
= free_insn_labels
;
17017 free_insn_labels
= l
->next
;
17021 l
->next
= si
->label_list
;
17022 si
->label_list
= l
;
17025 /* This function is called as tc_frob_label() whenever a label is defined
17026 and adds a DWARF-2 record we only want for true labels. */
17029 mips_define_label (symbolS
*sym
)
17031 mips_record_label (sym
);
17032 dwarf2_emit_label (sym
);
17035 /* This function is called by tc_new_dot_label whenever a new dot symbol
17039 mips_add_dot_label (symbolS
*sym
)
17041 mips_record_label (sym
);
17042 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17043 mips_compressed_mark_label (sym
);
17046 /* Some special processing for a MIPS ELF file. */
17049 mips_elf_final_processing (void)
17051 /* Write out the register information. */
17052 if (mips_abi
!= N64_ABI
)
17056 s
.ri_gprmask
= mips_gprmask
;
17057 s
.ri_cprmask
[0] = mips_cprmask
[0];
17058 s
.ri_cprmask
[1] = mips_cprmask
[1];
17059 s
.ri_cprmask
[2] = mips_cprmask
[2];
17060 s
.ri_cprmask
[3] = mips_cprmask
[3];
17061 /* The gp_value field is set by the MIPS ELF backend. */
17063 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17064 ((Elf32_External_RegInfo
*)
17065 mips_regmask_frag
));
17069 Elf64_Internal_RegInfo s
;
17071 s
.ri_gprmask
= mips_gprmask
;
17073 s
.ri_cprmask
[0] = mips_cprmask
[0];
17074 s
.ri_cprmask
[1] = mips_cprmask
[1];
17075 s
.ri_cprmask
[2] = mips_cprmask
[2];
17076 s
.ri_cprmask
[3] = mips_cprmask
[3];
17077 /* The gp_value field is set by the MIPS ELF backend. */
17079 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17080 ((Elf64_External_RegInfo
*)
17081 mips_regmask_frag
));
17084 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17085 sort of BFD interface for this. */
17086 if (mips_any_noreorder
)
17087 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17088 if (mips_pic
!= NO_PIC
)
17090 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17091 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17094 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17096 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17097 defined at present; this might need to change in future. */
17098 if (file_ase_mips16
)
17099 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17100 if (file_ase_micromips
)
17101 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17102 if (file_ase
& ASE_MDMX
)
17103 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17105 /* Set the MIPS ELF ABI flags. */
17106 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17107 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17108 else if (mips_abi
== O64_ABI
)
17109 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17110 else if (mips_abi
== EABI_ABI
)
17112 if (!file_mips_gp32
)
17113 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17115 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17117 else if (mips_abi
== N32_ABI
)
17118 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17120 /* Nothing to do for N64_ABI. */
17122 if (mips_32bitmode
)
17123 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17125 if (mips_flag_nan2008
)
17126 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17128 #if 0 /* XXX FIXME */
17129 /* 32 bit code with 64 bit FP registers. */
17130 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17131 elf_elfheader (stdoutput
)->e_flags
|= ???;
17135 typedef struct proc
{
17137 symbolS
*func_end_sym
;
17138 unsigned long reg_mask
;
17139 unsigned long reg_offset
;
17140 unsigned long fpreg_mask
;
17141 unsigned long fpreg_offset
;
17142 unsigned long frame_offset
;
17143 unsigned long frame_reg
;
17144 unsigned long pc_reg
;
17147 static procS cur_proc
;
17148 static procS
*cur_proc_ptr
;
17149 static int numprocs
;
17151 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17152 as "2", and a normal nop as "0". */
17154 #define NOP_OPCODE_MIPS 0
17155 #define NOP_OPCODE_MIPS16 1
17156 #define NOP_OPCODE_MICROMIPS 2
17159 mips_nop_opcode (void)
17161 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17162 return NOP_OPCODE_MICROMIPS
;
17163 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17164 return NOP_OPCODE_MIPS16
;
17166 return NOP_OPCODE_MIPS
;
17169 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17170 32-bit microMIPS NOPs here (if applicable). */
17173 mips_handle_align (fragS
*fragp
)
17177 int bytes
, size
, excess
;
17180 if (fragp
->fr_type
!= rs_align_code
)
17183 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17185 switch (nop_opcode
)
17187 case NOP_OPCODE_MICROMIPS
:
17188 opcode
= micromips_nop32_insn
.insn_opcode
;
17191 case NOP_OPCODE_MIPS16
:
17192 opcode
= mips16_nop_insn
.insn_opcode
;
17195 case NOP_OPCODE_MIPS
:
17197 opcode
= nop_insn
.insn_opcode
;
17202 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17203 excess
= bytes
% size
;
17205 /* Handle the leading part if we're not inserting a whole number of
17206 instructions, and make it the end of the fixed part of the frag.
17207 Try to fit in a short microMIPS NOP if applicable and possible,
17208 and use zeroes otherwise. */
17209 gas_assert (excess
< 4);
17210 fragp
->fr_fix
+= excess
;
17215 /* Fall through. */
17217 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17219 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17223 /* Fall through. */
17226 /* Fall through. */
17231 md_number_to_chars (p
, opcode
, size
);
17232 fragp
->fr_var
= size
;
17236 md_obj_begin (void)
17243 /* Check for premature end, nesting errors, etc. */
17245 as_warn (_("missing .end at end of assembly"));
17254 if (*input_line_pointer
== '-')
17256 ++input_line_pointer
;
17259 if (!ISDIGIT (*input_line_pointer
))
17260 as_bad (_("expected simple number"));
17261 if (input_line_pointer
[0] == '0')
17263 if (input_line_pointer
[1] == 'x')
17265 input_line_pointer
+= 2;
17266 while (ISXDIGIT (*input_line_pointer
))
17269 val
|= hex_value (*input_line_pointer
++);
17271 return negative
? -val
: val
;
17275 ++input_line_pointer
;
17276 while (ISDIGIT (*input_line_pointer
))
17279 val
|= *input_line_pointer
++ - '0';
17281 return negative
? -val
: val
;
17284 if (!ISDIGIT (*input_line_pointer
))
17286 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17287 *input_line_pointer
, *input_line_pointer
);
17288 as_warn (_("invalid number"));
17291 while (ISDIGIT (*input_line_pointer
))
17294 val
+= *input_line_pointer
++ - '0';
17296 return negative
? -val
: val
;
17299 /* The .file directive; just like the usual .file directive, but there
17300 is an initial number which is the ECOFF file index. In the non-ECOFF
17301 case .file implies DWARF-2. */
17304 s_mips_file (int x ATTRIBUTE_UNUSED
)
17306 static int first_file_directive
= 0;
17308 if (ECOFF_DEBUGGING
)
17317 filename
= dwarf2_directive_file (0);
17319 /* Versions of GCC up to 3.1 start files with a ".file"
17320 directive even for stabs output. Make sure that this
17321 ".file" is handled. Note that you need a version of GCC
17322 after 3.1 in order to support DWARF-2 on MIPS. */
17323 if (filename
!= NULL
&& ! first_file_directive
)
17325 (void) new_logical_line (filename
, -1);
17326 s_app_file_string (filename
, 0);
17328 first_file_directive
= 1;
17332 /* The .loc directive, implying DWARF-2. */
17335 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17337 if (!ECOFF_DEBUGGING
)
17338 dwarf2_directive_loc (0);
17341 /* The .end directive. */
17344 s_mips_end (int x ATTRIBUTE_UNUSED
)
17348 /* Following functions need their own .frame and .cprestore directives. */
17349 mips_frame_reg_valid
= 0;
17350 mips_cprestore_valid
= 0;
17352 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17355 demand_empty_rest_of_line ();
17360 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17361 as_warn (_(".end not in text section"));
17365 as_warn (_(".end directive without a preceding .ent directive."));
17366 demand_empty_rest_of_line ();
17372 gas_assert (S_GET_NAME (p
));
17373 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17374 as_warn (_(".end symbol does not match .ent symbol."));
17376 if (debug_type
== DEBUG_STABS
)
17377 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17381 as_warn (_(".end directive missing or unknown symbol"));
17383 /* Create an expression to calculate the size of the function. */
17384 if (p
&& cur_proc_ptr
)
17386 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17387 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17390 exp
->X_op
= O_subtract
;
17391 exp
->X_add_symbol
= symbol_temp_new_now ();
17392 exp
->X_op_symbol
= p
;
17393 exp
->X_add_number
= 0;
17395 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17398 /* Generate a .pdr section. */
17399 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17401 segT saved_seg
= now_seg
;
17402 subsegT saved_subseg
= now_subseg
;
17406 #ifdef md_flush_pending_output
17407 md_flush_pending_output ();
17410 gas_assert (pdr_seg
);
17411 subseg_set (pdr_seg
, 0);
17413 /* Write the symbol. */
17414 exp
.X_op
= O_symbol
;
17415 exp
.X_add_symbol
= p
;
17416 exp
.X_add_number
= 0;
17417 emit_expr (&exp
, 4);
17419 fragp
= frag_more (7 * 4);
17421 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17422 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17423 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17424 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17425 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17426 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17427 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17429 subseg_set (saved_seg
, saved_subseg
);
17432 cur_proc_ptr
= NULL
;
17435 /* The .aent and .ent directives. */
17438 s_mips_ent (int aent
)
17442 symbolP
= get_symbol ();
17443 if (*input_line_pointer
== ',')
17444 ++input_line_pointer
;
17445 SKIP_WHITESPACE ();
17446 if (ISDIGIT (*input_line_pointer
)
17447 || *input_line_pointer
== '-')
17450 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17451 as_warn (_(".ent or .aent not in text section."));
17453 if (!aent
&& cur_proc_ptr
)
17454 as_warn (_("missing .end"));
17458 /* This function needs its own .frame and .cprestore directives. */
17459 mips_frame_reg_valid
= 0;
17460 mips_cprestore_valid
= 0;
17462 cur_proc_ptr
= &cur_proc
;
17463 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17465 cur_proc_ptr
->func_sym
= symbolP
;
17469 if (debug_type
== DEBUG_STABS
)
17470 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17471 S_GET_NAME (symbolP
));
17474 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17476 demand_empty_rest_of_line ();
17479 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17480 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17481 s_mips_frame is used so that we can set the PDR information correctly.
17482 We can't use the ecoff routines because they make reference to the ecoff
17483 symbol table (in the mdebug section). */
17486 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17488 if (ECOFF_DEBUGGING
)
17494 if (cur_proc_ptr
== (procS
*) NULL
)
17496 as_warn (_(".frame outside of .ent"));
17497 demand_empty_rest_of_line ();
17501 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17503 SKIP_WHITESPACE ();
17504 if (*input_line_pointer
++ != ','
17505 || get_absolute_expression_and_terminator (&val
) != ',')
17507 as_warn (_("Bad .frame directive"));
17508 --input_line_pointer
;
17509 demand_empty_rest_of_line ();
17513 cur_proc_ptr
->frame_offset
= val
;
17514 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17516 demand_empty_rest_of_line ();
17520 /* The .fmask and .mask directives. If the mdebug section is present
17521 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17522 embedded targets, s_mips_mask is used so that we can set the PDR
17523 information correctly. We can't use the ecoff routines because they
17524 make reference to the ecoff symbol table (in the mdebug section). */
17527 s_mips_mask (int reg_type
)
17529 if (ECOFF_DEBUGGING
)
17530 s_ignore (reg_type
);
17535 if (cur_proc_ptr
== (procS
*) NULL
)
17537 as_warn (_(".mask/.fmask outside of .ent"));
17538 demand_empty_rest_of_line ();
17542 if (get_absolute_expression_and_terminator (&mask
) != ',')
17544 as_warn (_("Bad .mask/.fmask directive"));
17545 --input_line_pointer
;
17546 demand_empty_rest_of_line ();
17550 off
= get_absolute_expression ();
17552 if (reg_type
== 'F')
17554 cur_proc_ptr
->fpreg_mask
= mask
;
17555 cur_proc_ptr
->fpreg_offset
= off
;
17559 cur_proc_ptr
->reg_mask
= mask
;
17560 cur_proc_ptr
->reg_offset
= off
;
17563 demand_empty_rest_of_line ();
17567 /* A table describing all the processors gas knows about. Names are
17568 matched in the order listed.
17570 To ease comparison, please keep this table in the same order as
17571 gcc's mips_cpu_info_table[]. */
17572 static const struct mips_cpu_info mips_cpu_info_table
[] =
17574 /* Entries for generic ISAs */
17575 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17576 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17577 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17578 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17579 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17580 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17581 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17582 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17583 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17586 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17587 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17588 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17591 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17594 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17595 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17596 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17597 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17598 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17599 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17600 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17601 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17602 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17603 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17604 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17605 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17606 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17607 /* ST Microelectronics Loongson 2E and 2F cores */
17608 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17609 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17612 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17613 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17614 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17615 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17616 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17617 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17618 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17619 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17620 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17621 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17622 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17623 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17624 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17625 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17626 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17629 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17630 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17631 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17632 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17634 /* MIPS 32 Release 2 */
17635 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17636 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17637 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17638 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17639 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17640 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17641 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17642 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17643 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17644 ISA_MIPS32R2
, CPU_MIPS32R2
},
17645 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17646 ISA_MIPS32R2
, CPU_MIPS32R2
},
17647 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17648 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17649 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17650 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17651 /* Deprecated forms of the above. */
17652 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17653 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17654 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17655 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17656 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17657 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17658 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17659 /* Deprecated forms of the above. */
17660 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17661 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17662 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17663 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17664 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17665 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17666 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17667 /* Deprecated forms of the above. */
17668 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17669 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17670 /* 34Kn is a 34kc without DSP. */
17671 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17672 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17673 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17674 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17675 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17676 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17677 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17678 /* Deprecated forms of the above. */
17679 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17680 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17681 /* 1004K cores are multiprocessor versions of the 34K. */
17682 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17683 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17684 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17685 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17688 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17689 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17690 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17691 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17693 /* Broadcom SB-1 CPU core */
17694 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17695 /* Broadcom SB-1A CPU core */
17696 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17698 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17700 /* MIPS 64 Release 2 */
17702 /* Cavium Networks Octeon CPU core */
17703 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17704 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17705 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17708 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17711 XLP is mostly like XLR, with the prominent exception that it is
17712 MIPS64R2 rather than MIPS64. */
17713 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17716 { NULL
, 0, 0, 0, 0 }
17720 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17721 with a final "000" replaced by "k". Ignore case.
17723 Note: this function is shared between GCC and GAS. */
17726 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17728 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17729 given
++, canonical
++;
17731 return ((*given
== 0 && *canonical
== 0)
17732 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17736 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17737 CPU name. We've traditionally allowed a lot of variation here.
17739 Note: this function is shared between GCC and GAS. */
17742 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17744 /* First see if the name matches exactly, or with a final "000"
17745 turned into "k". */
17746 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17749 /* If not, try comparing based on numerical designation alone.
17750 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17751 if (TOLOWER (*given
) == 'r')
17753 if (!ISDIGIT (*given
))
17756 /* Skip over some well-known prefixes in the canonical name,
17757 hoping to find a number there too. */
17758 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17760 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17762 else if (TOLOWER (canonical
[0]) == 'r')
17765 return mips_strict_matching_cpu_name_p (canonical
, given
);
17769 /* Parse an option that takes the name of a processor as its argument.
17770 OPTION is the name of the option and CPU_STRING is the argument.
17771 Return the corresponding processor enumeration if the CPU_STRING is
17772 recognized, otherwise report an error and return null.
17774 A similar function exists in GCC. */
17776 static const struct mips_cpu_info
*
17777 mips_parse_cpu (const char *option
, const char *cpu_string
)
17779 const struct mips_cpu_info
*p
;
17781 /* 'from-abi' selects the most compatible architecture for the given
17782 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17783 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17784 version. Look first at the -mgp options, if given, otherwise base
17785 the choice on MIPS_DEFAULT_64BIT.
17787 Treat NO_ABI like the EABIs. One reason to do this is that the
17788 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17789 architecture. This code picks MIPS I for 'mips' and MIPS III for
17790 'mips64', just as we did in the days before 'from-abi'. */
17791 if (strcasecmp (cpu_string
, "from-abi") == 0)
17793 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17794 return mips_cpu_info_from_isa (ISA_MIPS1
);
17796 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17797 return mips_cpu_info_from_isa (ISA_MIPS3
);
17799 if (file_mips_gp32
>= 0)
17800 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17802 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17807 /* 'default' has traditionally been a no-op. Probably not very useful. */
17808 if (strcasecmp (cpu_string
, "default") == 0)
17811 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
17812 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
17815 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
17819 /* Return the canonical processor information for ISA (a member of the
17820 ISA_MIPS* enumeration). */
17822 static const struct mips_cpu_info
*
17823 mips_cpu_info_from_isa (int isa
)
17827 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17828 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
17829 && isa
== mips_cpu_info_table
[i
].isa
)
17830 return (&mips_cpu_info_table
[i
]);
17835 static const struct mips_cpu_info
*
17836 mips_cpu_info_from_arch (int arch
)
17840 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17841 if (arch
== mips_cpu_info_table
[i
].cpu
)
17842 return (&mips_cpu_info_table
[i
]);
17848 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
17852 fprintf (stream
, "%24s", "");
17857 fprintf (stream
, ", ");
17861 if (*col_p
+ strlen (string
) > 72)
17863 fprintf (stream
, "\n%24s", "");
17867 fprintf (stream
, "%s", string
);
17868 *col_p
+= strlen (string
);
17874 md_show_usage (FILE *stream
)
17879 fprintf (stream
, _("\
17881 -EB generate big endian output\n\
17882 -EL generate little endian output\n\
17883 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17884 -G NUM allow referencing objects up to NUM bytes\n\
17885 implicitly with the gp register [default 8]\n"));
17886 fprintf (stream
, _("\
17887 -mips1 generate MIPS ISA I instructions\n\
17888 -mips2 generate MIPS ISA II instructions\n\
17889 -mips3 generate MIPS ISA III instructions\n\
17890 -mips4 generate MIPS ISA IV instructions\n\
17891 -mips5 generate MIPS ISA V instructions\n\
17892 -mips32 generate MIPS32 ISA instructions\n\
17893 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17894 -mips64 generate MIPS64 ISA instructions\n\
17895 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17896 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17900 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17901 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
17902 show (stream
, "from-abi", &column
, &first
);
17903 fputc ('\n', stream
);
17905 fprintf (stream
, _("\
17906 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17907 -no-mCPU don't generate code specific to CPU.\n\
17908 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17912 show (stream
, "3900", &column
, &first
);
17913 show (stream
, "4010", &column
, &first
);
17914 show (stream
, "4100", &column
, &first
);
17915 show (stream
, "4650", &column
, &first
);
17916 fputc ('\n', stream
);
17918 fprintf (stream
, _("\
17919 -mips16 generate mips16 instructions\n\
17920 -no-mips16 do not generate mips16 instructions\n"));
17921 fprintf (stream
, _("\
17922 -mmicromips generate microMIPS instructions\n\
17923 -mno-micromips do not generate microMIPS instructions\n"));
17924 fprintf (stream
, _("\
17925 -msmartmips generate smartmips instructions\n\
17926 -mno-smartmips do not generate smartmips instructions\n"));
17927 fprintf (stream
, _("\
17928 -mdsp generate DSP instructions\n\
17929 -mno-dsp do not generate DSP instructions\n"));
17930 fprintf (stream
, _("\
17931 -mdspr2 generate DSP R2 instructions\n\
17932 -mno-dspr2 do not generate DSP R2 instructions\n"));
17933 fprintf (stream
, _("\
17934 -mmt generate MT instructions\n\
17935 -mno-mt do not generate MT instructions\n"));
17936 fprintf (stream
, _("\
17937 -mmcu generate MCU instructions\n\
17938 -mno-mcu do not generate MCU instructions\n"));
17939 fprintf (stream
, _("\
17940 -mvirt generate Virtualization instructions\n\
17941 -mno-virt do not generate Virtualization instructions\n"));
17942 fprintf (stream
, _("\
17943 -minsn32 only generate 32-bit microMIPS instructions\n\
17944 -mno-insn32 generate all microMIPS instructions\n"));
17945 fprintf (stream
, _("\
17946 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17947 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17948 -mfix-vr4120 work around certain VR4120 errata\n\
17949 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17950 -mfix-24k insert a nop after ERET and DERET instructions\n\
17951 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17952 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17953 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17954 -msym32 assume all symbols have 32-bit values\n\
17955 -O0 remove unneeded NOPs, do not swap branches\n\
17956 -O remove unneeded NOPs and swap branches\n\
17957 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17958 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17959 fprintf (stream
, _("\
17960 -mhard-float allow floating-point instructions\n\
17961 -msoft-float do not allow floating-point instructions\n\
17962 -msingle-float only allow 32-bit floating-point operations\n\
17963 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17964 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17965 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17966 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17970 show (stream
, "legacy", &column
, &first
);
17971 show (stream
, "2008", &column
, &first
);
17973 fputc ('\n', stream
);
17975 fprintf (stream
, _("\
17976 -KPIC, -call_shared generate SVR4 position independent code\n\
17977 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17978 -mvxworks-pic generate VxWorks position independent code\n\
17979 -non_shared do not generate code that can operate with DSOs\n\
17980 -xgot assume a 32 bit GOT\n\
17981 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17982 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17983 position dependent (non shared) code\n\
17984 -mabi=ABI create ABI conformant object file for:\n"));
17988 show (stream
, "32", &column
, &first
);
17989 show (stream
, "o64", &column
, &first
);
17990 show (stream
, "n32", &column
, &first
);
17991 show (stream
, "64", &column
, &first
);
17992 show (stream
, "eabi", &column
, &first
);
17994 fputc ('\n', stream
);
17996 fprintf (stream
, _("\
17997 -32 create o32 ABI object file (default)\n\
17998 -n32 create n32 ABI object file\n\
17999 -64 create 64 ABI object file\n"));
18004 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18006 if (HAVE_64BIT_SYMBOLS
)
18007 return dwarf2_format_64bit_irix
;
18009 return dwarf2_format_32bit
;
18014 mips_dwarf2_addr_size (void)
18016 if (HAVE_64BIT_OBJECTS
)
18022 /* Standard calling conventions leave the CFA at SP on entry. */
18024 mips_cfi_frame_initial_instructions (void)
18026 cfi_add_CFA_def_cfa_register (SP
);
18030 tc_mips_regname_to_dw2regnum (char *regname
)
18032 unsigned int regnum
= -1;
18035 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))