1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
273 /* Specifies whether module level options have been checked yet. */
274 static bfd_boolean file_mips_opts_checked
= FALSE
;
276 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
277 value has not been initialized. Changed by `.nan legacy' and
278 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
279 options, and the default CPU. */
280 static int mips_nan2008
= -1;
282 /* This is the struct we use to hold the module level set of options.
283 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
284 fp fields to -1 to indicate that they have not been initialized. */
286 static struct mips_set_options file_mips_opts
=
288 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
289 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
290 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
291 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
292 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
295 /* This is similar to file_mips_opts, but for the current set of options. */
297 static struct mips_set_options mips_opts
=
299 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
300 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
301 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
302 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
303 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
306 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
307 static unsigned int file_ase_explicit
;
309 /* These variables are filled in with the masks of registers used.
310 The object format code reads them and puts them in the appropriate
312 unsigned long mips_gprmask
;
313 unsigned long mips_cprmask
[4];
315 /* True if any MIPS16 code was produced. */
316 static int file_ase_mips16
;
318 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
319 || mips_opts.isa == ISA_MIPS32R2 \
320 || mips_opts.isa == ISA_MIPS32R3 \
321 || mips_opts.isa == ISA_MIPS32R5 \
322 || mips_opts.isa == ISA_MIPS64 \
323 || mips_opts.isa == ISA_MIPS64R2 \
324 || mips_opts.isa == ISA_MIPS64R3 \
325 || mips_opts.isa == ISA_MIPS64R5)
327 /* True if any microMIPS code was produced. */
328 static int file_ase_micromips
;
330 /* True if we want to create R_MIPS_JALR for jalr $25. */
332 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
334 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
335 because there's no place for any addend, the only acceptable
336 expression is a bare symbol. */
337 #define MIPS_JALR_HINT_P(EXPR) \
338 (!HAVE_IN_PLACE_ADDENDS \
339 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
342 /* The argument of the -march= flag. The architecture we are assembling. */
343 static const char *mips_arch_string
;
345 /* The argument of the -mtune= flag. The architecture for which we
347 static int mips_tune
= CPU_UNKNOWN
;
348 static const char *mips_tune_string
;
350 /* True when generating 32-bit code for a 64-bit processor. */
351 static int mips_32bitmode
= 0;
353 /* True if the given ABI requires 32-bit registers. */
354 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
356 /* Likewise 64-bit registers. */
357 #define ABI_NEEDS_64BIT_REGS(ABI) \
359 || (ABI) == N64_ABI \
362 #define ISA_IS_R6(ISA) \
363 ((ISA) == ISA_MIPS32R6 \
364 || (ISA) == ISA_MIPS64R6)
366 /* Return true if ISA supports 64 bit wide gp registers. */
367 #define ISA_HAS_64BIT_REGS(ISA) \
368 ((ISA) == ISA_MIPS3 \
369 || (ISA) == ISA_MIPS4 \
370 || (ISA) == ISA_MIPS5 \
371 || (ISA) == ISA_MIPS64 \
372 || (ISA) == ISA_MIPS64R2 \
373 || (ISA) == ISA_MIPS64R3 \
374 || (ISA) == ISA_MIPS64R5 \
375 || (ISA) == ISA_MIPS64R6)
377 /* Return true if ISA supports 64 bit wide float registers. */
378 #define ISA_HAS_64BIT_FPRS(ISA) \
379 ((ISA) == ISA_MIPS3 \
380 || (ISA) == ISA_MIPS4 \
381 || (ISA) == ISA_MIPS5 \
382 || (ISA) == ISA_MIPS32R2 \
383 || (ISA) == ISA_MIPS32R3 \
384 || (ISA) == ISA_MIPS32R5 \
385 || (ISA) == ISA_MIPS32R6 \
386 || (ISA) == ISA_MIPS64 \
387 || (ISA) == ISA_MIPS64R2 \
388 || (ISA) == ISA_MIPS64R3 \
389 || (ISA) == ISA_MIPS64R5 \
390 || (ISA) == ISA_MIPS64R6)
392 /* Return true if ISA supports 64-bit right rotate (dror et al.)
394 #define ISA_HAS_DROR(ISA) \
395 ((ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6 \
399 || (mips_opts.micromips \
400 && ISA_HAS_64BIT_REGS (ISA)) \
403 /* Return true if ISA supports 32-bit right rotate (ror et al.)
405 #define ISA_HAS_ROR(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS32R3 \
408 || (ISA) == ISA_MIPS32R5 \
409 || (ISA) == ISA_MIPS32R6 \
410 || (ISA) == ISA_MIPS64R2 \
411 || (ISA) == ISA_MIPS64R3 \
412 || (ISA) == ISA_MIPS64R5 \
413 || (ISA) == ISA_MIPS64R6 \
414 || (mips_opts.ase & ASE_SMARTMIPS) \
415 || mips_opts.micromips \
418 /* Return true if ISA supports single-precision floats in odd registers. */
419 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
420 (((ISA) == ISA_MIPS32 \
421 || (ISA) == ISA_MIPS32R2 \
422 || (ISA) == ISA_MIPS32R3 \
423 || (ISA) == ISA_MIPS32R5 \
424 || (ISA) == ISA_MIPS32R6 \
425 || (ISA) == ISA_MIPS64 \
426 || (ISA) == ISA_MIPS64R2 \
427 || (ISA) == ISA_MIPS64R3 \
428 || (ISA) == ISA_MIPS64R5 \
429 || (ISA) == ISA_MIPS64R6 \
430 || (CPU) == CPU_R5900) \
431 && ((CPU) != CPU_GS464 \
432 || (CPU) != CPU_GS464E \
433 || (CPU) != CPU_GS264E))
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS32R3 \
440 || (ISA) == ISA_MIPS32R5 \
441 || (ISA) == ISA_MIPS32R6 \
442 || (ISA) == ISA_MIPS64R2 \
443 || (ISA) == ISA_MIPS64R3 \
444 || (ISA) == ISA_MIPS64R5 \
445 || (ISA) == ISA_MIPS64R6)
447 /* Return true if ISA supports legacy NAN. */
448 #define ISA_HAS_LEGACY_NAN(ISA) \
449 ((ISA) == ISA_MIPS1 \
450 || (ISA) == ISA_MIPS2 \
451 || (ISA) == ISA_MIPS3 \
452 || (ISA) == ISA_MIPS4 \
453 || (ISA) == ISA_MIPS5 \
454 || (ISA) == ISA_MIPS32 \
455 || (ISA) == ISA_MIPS32R2 \
456 || (ISA) == ISA_MIPS32R3 \
457 || (ISA) == ISA_MIPS32R5 \
458 || (ISA) == ISA_MIPS64 \
459 || (ISA) == ISA_MIPS64R2 \
460 || (ISA) == ISA_MIPS64R3 \
461 || (ISA) == ISA_MIPS64R5)
464 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
469 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
473 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
475 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
477 /* True if relocations are stored in-place. */
478 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
480 /* The ABI-derived address size. */
481 #define HAVE_64BIT_ADDRESSES \
482 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
483 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
485 /* The size of symbolic constants (i.e., expressions of the form
486 "SYMBOL" or "SYMBOL + OFFSET"). */
487 #define HAVE_32BIT_SYMBOLS \
488 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
489 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
491 /* Addresses are loaded in different ways, depending on the address size
492 in use. The n32 ABI Documentation also mandates the use of additions
493 with overflow checking, but existing implementations don't follow it. */
494 #define ADDRESS_ADD_INSN \
495 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
497 #define ADDRESS_ADDI_INSN \
498 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
500 #define ADDRESS_LOAD_INSN \
501 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
503 #define ADDRESS_STORE_INSN \
504 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
506 /* Return true if the given CPU supports the MIPS16 ASE. */
507 #define CPU_HAS_MIPS16(cpu) \
508 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
509 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
511 /* Return true if the given CPU supports the microMIPS ASE. */
512 #define CPU_HAS_MICROMIPS(cpu) 0
514 /* True if CPU has a dror instruction. */
515 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
517 /* True if CPU has a ror instruction. */
518 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
520 /* True if CPU is in the Octeon family. */
521 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
522 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
524 /* True if CPU has seq/sne and seqi/snei instructions. */
525 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
527 /* True, if CPU has support for ldc1 and sdc1. */
528 #define CPU_HAS_LDC1_SDC1(CPU) \
529 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
531 /* True if mflo and mfhi can be immediately followed by instructions
532 which write to the HI and LO registers.
534 According to MIPS specifications, MIPS ISAs I, II, and III need
535 (at least) two instructions between the reads of HI/LO and
536 instructions which write them, and later ISAs do not. Contradicting
537 the MIPS specifications, some MIPS IV processor user manuals (e.g.
538 the UM for the NEC Vr5000) document needing the instructions between
539 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
540 MIPS64 and later ISAs to have the interlocks, plus any specific
541 earlier-ISA CPUs for which CPU documentation declares that the
542 instructions are really interlocked. */
543 #define hilo_interlocks \
544 (mips_opts.isa == ISA_MIPS32 \
545 || mips_opts.isa == ISA_MIPS32R2 \
546 || mips_opts.isa == ISA_MIPS32R3 \
547 || mips_opts.isa == ISA_MIPS32R5 \
548 || mips_opts.isa == ISA_MIPS32R6 \
549 || mips_opts.isa == ISA_MIPS64 \
550 || mips_opts.isa == ISA_MIPS64R2 \
551 || mips_opts.isa == ISA_MIPS64R3 \
552 || mips_opts.isa == ISA_MIPS64R5 \
553 || mips_opts.isa == ISA_MIPS64R6 \
554 || mips_opts.arch == CPU_R4010 \
555 || mips_opts.arch == CPU_R5900 \
556 || mips_opts.arch == CPU_R10000 \
557 || mips_opts.arch == CPU_R12000 \
558 || mips_opts.arch == CPU_R14000 \
559 || mips_opts.arch == CPU_R16000 \
560 || mips_opts.arch == CPU_RM7000 \
561 || mips_opts.arch == CPU_VR5500 \
562 || mips_opts.micromips \
565 /* Whether the processor uses hardware interlocks to protect reads
566 from the GPRs after they are loaded from memory, and thus does not
567 require nops to be inserted. This applies to instructions marked
568 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
569 level I and microMIPS mode instructions are always interlocked. */
570 #define gpr_interlocks \
571 (mips_opts.isa != ISA_MIPS1 \
572 || mips_opts.arch == CPU_R3900 \
573 || mips_opts.arch == CPU_R5900 \
574 || mips_opts.micromips \
577 /* Whether the processor uses hardware interlocks to avoid delays
578 required by coprocessor instructions, and thus does not require
579 nops to be inserted. This applies to instructions marked
580 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
581 instructions marked INSN_WRITE_COND_CODE and ones marked
582 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
583 levels I, II, and III and microMIPS mode instructions are always
585 /* Itbl support may require additional care here. */
586 #define cop_interlocks \
587 ((mips_opts.isa != ISA_MIPS1 \
588 && mips_opts.isa != ISA_MIPS2 \
589 && mips_opts.isa != ISA_MIPS3) \
590 || mips_opts.arch == CPU_R4300 \
591 || mips_opts.micromips \
594 /* Whether the processor uses hardware interlocks to protect reads
595 from coprocessor registers after they are loaded from memory, and
596 thus does not require nops to be inserted. This applies to
597 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
598 requires at MIPS ISA level I and microMIPS mode instructions are
599 always interlocked. */
600 #define cop_mem_interlocks \
601 (mips_opts.isa != ISA_MIPS1 \
602 || mips_opts.micromips \
605 /* Is this a mfhi or mflo instruction? */
606 #define MF_HILO_INSN(PINFO) \
607 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
609 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
610 has been selected. This implies, in particular, that addresses of text
611 labels have their LSB set. */
612 #define HAVE_CODE_COMPRESSION \
613 ((mips_opts.mips16 | mips_opts.micromips) != 0)
615 /* The minimum and maximum signed values that can be stored in a GPR. */
616 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
617 #define GPR_SMIN (-GPR_SMAX - 1)
619 /* MIPS PIC level. */
621 enum mips_pic_level mips_pic
;
623 /* 1 if we should generate 32 bit offsets from the $gp register in
624 SVR4_PIC mode. Currently has no meaning in other modes. */
625 static int mips_big_got
= 0;
627 /* 1 if trap instructions should used for overflow rather than break
629 static int mips_trap
= 0;
631 /* 1 if double width floating point constants should not be constructed
632 by assembling two single width halves into two single width floating
633 point registers which just happen to alias the double width destination
634 register. On some architectures this aliasing can be disabled by a bit
635 in the status register, and the setting of this bit cannot be determined
636 automatically at assemble time. */
637 static int mips_disable_float_construction
;
639 /* Non-zero if any .set noreorder directives were used. */
641 static int mips_any_noreorder
;
643 /* Non-zero if nops should be inserted when the register referenced in
644 an mfhi/mflo instruction is read in the next two instructions. */
645 static int mips_7000_hilo_fix
;
647 /* The size of objects in the small data section. */
648 static unsigned int g_switch_value
= 8;
649 /* Whether the -G option was used. */
650 static int g_switch_seen
= 0;
655 /* If we can determine in advance that GP optimization won't be
656 possible, we can skip the relaxation stuff that tries to produce
657 GP-relative references. This makes delay slot optimization work
660 This function can only provide a guess, but it seems to work for
661 gcc output. It needs to guess right for gcc, otherwise gcc
662 will put what it thinks is a GP-relative instruction in a branch
665 I don't know if a fix is needed for the SVR4_PIC mode. I've only
666 fixed it for the non-PIC mode. KR 95/04/07 */
667 static int nopic_need_relax (symbolS
*, int);
669 /* Handle of the OPCODE hash table. */
670 static struct hash_control
*op_hash
= NULL
;
672 /* The opcode hash table we use for the mips16. */
673 static struct hash_control
*mips16_op_hash
= NULL
;
675 /* The opcode hash table we use for the microMIPS ASE. */
676 static struct hash_control
*micromips_op_hash
= NULL
;
678 /* This array holds the chars that always start a comment. If the
679 pre-processor is disabled, these aren't very useful. */
680 const char comment_chars
[] = "#";
682 /* This array holds the chars that only start a comment at the beginning of
683 a line. If the line seems to have the form '# 123 filename'
684 .line and .file directives will appear in the pre-processed output. */
685 /* Note that input_file.c hand checks for '#' at the beginning of the
686 first line of the input file. This is because the compiler outputs
687 #NO_APP at the beginning of its output. */
688 /* Also note that C style comments are always supported. */
689 const char line_comment_chars
[] = "#";
691 /* This array holds machine specific line separator characters. */
692 const char line_separator_chars
[] = ";";
694 /* Chars that can be used to separate mant from exp in floating point nums. */
695 const char EXP_CHARS
[] = "eE";
697 /* Chars that mean this number is a floating point constant.
700 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
702 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
703 changed in read.c . Ideally it shouldn't have to know about it at all,
704 but nothing is ideal around here. */
706 /* Types of printf format used for instruction-related error messages.
707 "I" means int ("%d") and "S" means string ("%s"). */
708 enum mips_insn_error_format
715 /* Information about an error that was found while assembling the current
717 struct mips_insn_error
719 /* We sometimes need to match an instruction against more than one
720 opcode table entry. Errors found during this matching are reported
721 against a particular syntactic argument rather than against the
722 instruction as a whole. We grade these messages so that errors
723 against argument N have a greater priority than an error against
724 any argument < N, since the former implies that arguments up to N
725 were acceptable and that the opcode entry was therefore a closer match.
726 If several matches report an error against the same argument,
727 we only use that error if it is the same in all cases.
729 min_argnum is the minimum argument number for which an error message
730 should be accepted. It is 0 if MSG is against the instruction as
734 /* The printf()-style message, including its format and arguments. */
735 enum mips_insn_error_format format
;
744 /* The error that should be reported for the current instruction. */
745 static struct mips_insn_error insn_error
;
747 static int auto_align
= 1;
749 /* When outputting SVR4 PIC code, the assembler needs to know the
750 offset in the stack frame from which to restore the $gp register.
751 This is set by the .cprestore pseudo-op, and saved in this
753 static offsetT mips_cprestore_offset
= -1;
755 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
756 more optimizations, it can use a register value instead of a memory-saved
757 offset and even an other register than $gp as global pointer. */
758 static offsetT mips_cpreturn_offset
= -1;
759 static int mips_cpreturn_register
= -1;
760 static int mips_gp_register
= GP
;
761 static int mips_gprel_offset
= 0;
763 /* Whether mips_cprestore_offset has been set in the current function
764 (or whether it has already been warned about, if not). */
765 static int mips_cprestore_valid
= 0;
767 /* This is the register which holds the stack frame, as set by the
768 .frame pseudo-op. This is needed to implement .cprestore. */
769 static int mips_frame_reg
= SP
;
771 /* Whether mips_frame_reg has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_frame_reg_valid
= 0;
775 /* To output NOP instructions correctly, we need to keep information
776 about the previous two instructions. */
778 /* Whether we are optimizing. The default value of 2 means to remove
779 unneeded NOPs and swap branch instructions when possible. A value
780 of 1 means to not swap branches. A value of 0 means to always
782 static int mips_optimize
= 2;
784 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
785 equivalent to seeing no -g option at all. */
786 static int mips_debug
= 0;
788 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
789 #define MAX_VR4130_NOPS 4
791 /* The maximum number of NOPs needed to fill delay slots. */
792 #define MAX_DELAY_NOPS 2
794 /* The maximum number of NOPs needed for any purpose. */
797 /* The maximum range of context length of ll/sc. */
798 #define MAX_LLSC_RANGE 20
800 /* A list of previous instructions, with index 0 being the most recent.
801 We need to look back MAX_NOPS instructions when filling delay slots
802 or working around processor errata. We need to look back one
803 instruction further if we're thinking about using history[0] to
804 fill a branch delay slot. */
805 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
807 /* Arrays of operands for each instruction. */
808 #define MAX_OPERANDS 6
809 struct mips_operand_array
811 const struct mips_operand
*operand
[MAX_OPERANDS
];
813 static struct mips_operand_array
*mips_operands
;
814 static struct mips_operand_array
*mips16_operands
;
815 static struct mips_operand_array
*micromips_operands
;
817 /* Nop instructions used by emit_nop. */
818 static struct mips_cl_insn nop_insn
;
819 static struct mips_cl_insn mips16_nop_insn
;
820 static struct mips_cl_insn micromips_nop16_insn
;
821 static struct mips_cl_insn micromips_nop32_insn
;
823 /* Sync instructions used by insert sync. */
824 static struct mips_cl_insn sync_insn
;
826 /* The appropriate nop for the current mode. */
827 #define NOP_INSN (mips_opts.mips16 \
829 : (mips_opts.micromips \
830 ? (mips_opts.insn32 \
831 ? µmips_nop32_insn \
832 : µmips_nop16_insn) \
835 /* The size of NOP_INSN in bytes. */
836 #define NOP_INSN_SIZE ((mips_opts.mips16 \
837 || (mips_opts.micromips && !mips_opts.insn32)) \
840 /* If this is set, it points to a frag holding nop instructions which
841 were inserted before the start of a noreorder section. If those
842 nops turn out to be unnecessary, the size of the frag can be
844 static fragS
*prev_nop_frag
;
846 /* The number of nop instructions we created in prev_nop_frag. */
847 static int prev_nop_frag_holds
;
849 /* The number of nop instructions that we know we need in
851 static int prev_nop_frag_required
;
853 /* The number of instructions we've seen since prev_nop_frag. */
854 static int prev_nop_frag_since
;
856 /* Relocations against symbols are sometimes done in two parts, with a HI
857 relocation and a LO relocation. Each relocation has only 16 bits of
858 space to store an addend. This means that in order for the linker to
859 handle carries correctly, it must be able to locate both the HI and
860 the LO relocation. This means that the relocations must appear in
861 order in the relocation table.
863 In order to implement this, we keep track of each unmatched HI
864 relocation. We then sort them so that they immediately precede the
865 corresponding LO relocation. */
870 struct mips_hi_fixup
*next
;
873 /* The section this fixup is in. */
877 /* The list of unmatched HI relocs. */
879 static struct mips_hi_fixup
*mips_hi_fixup_list
;
881 /* The frag containing the last explicit relocation operator.
882 Null if explicit relocations have not been used. */
884 static fragS
*prev_reloc_op_frag
;
886 /* Map mips16 register numbers to normal MIPS register numbers. */
888 static const unsigned int mips16_to_32_reg_map
[] =
890 16, 17, 2, 3, 4, 5, 6, 7
893 /* Map microMIPS register numbers to normal MIPS register numbers. */
895 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
897 /* The microMIPS registers with type h. */
898 static const unsigned int micromips_to_32_reg_h_map1
[] =
900 5, 5, 6, 4, 4, 4, 4, 4
902 static const unsigned int micromips_to_32_reg_h_map2
[] =
904 6, 7, 7, 21, 22, 5, 6, 7
907 /* The microMIPS registers with type m. */
908 static const unsigned int micromips_to_32_reg_m_map
[] =
910 0, 17, 2, 3, 16, 18, 19, 20
913 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
915 /* Classifies the kind of instructions we're interested in when
916 implementing -mfix-vr4120. */
917 enum fix_vr4120_class
925 NUM_FIX_VR4120_CLASSES
928 /* ...likewise -mfix-loongson2f-jump. */
929 static bfd_boolean mips_fix_loongson2f_jump
;
931 /* ...likewise -mfix-loongson2f-nop. */
932 static bfd_boolean mips_fix_loongson2f_nop
;
934 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
935 static bfd_boolean mips_fix_loongson2f
;
937 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
938 there must be at least one other instruction between an instruction
939 of type X and an instruction of type Y. */
940 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
942 /* True if -mfix-vr4120 is in force. */
943 static int mips_fix_vr4120
;
945 /* ...likewise -mfix-vr4130. */
946 static int mips_fix_vr4130
;
948 /* ...likewise -mfix-24k. */
949 static int mips_fix_24k
;
951 /* ...likewise -mfix-rm7000 */
952 static int mips_fix_rm7000
;
954 /* ...likewise -mfix-cn63xxp1 */
955 static bfd_boolean mips_fix_cn63xxp1
;
957 /* ...likewise -mfix-r5900 */
958 static bfd_boolean mips_fix_r5900
;
959 static bfd_boolean mips_fix_r5900_explicit
;
961 /* ...likewise -mfix-loongson3-llsc. */
962 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
964 /* We don't relax branches by default, since this causes us to expand
965 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
966 fail to compute the offset before expanding the macro to the most
967 efficient expansion. */
969 static int mips_relax_branch
;
971 /* TRUE if checks are suppressed for invalid branches between ISA modes.
972 Needed for broken assembly produced by some GCC versions and some
973 sloppy code out there, where branches to data labels are present. */
974 static bfd_boolean mips_ignore_branch_isa
;
976 /* The expansion of many macros depends on the type of symbol that
977 they refer to. For example, when generating position-dependent code,
978 a macro that refers to a symbol may have two different expansions,
979 one which uses GP-relative addresses and one which uses absolute
980 addresses. When generating SVR4-style PIC, a macro may have
981 different expansions for local and global symbols.
983 We handle these situations by generating both sequences and putting
984 them in variant frags. In position-dependent code, the first sequence
985 will be the GP-relative one and the second sequence will be the
986 absolute one. In SVR4 PIC, the first sequence will be for global
987 symbols and the second will be for local symbols.
989 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
990 SECOND are the lengths of the two sequences in bytes. These fields
991 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
992 the subtype has the following flags:
995 Set if generating PIC code.
998 Set if it has been decided that we should use the second
999 sequence instead of the first.
1002 Set in the first variant frag if the macro's second implementation
1003 is longer than its first. This refers to the macro as a whole,
1004 not an individual relaxation.
1007 Set in the first variant frag if the macro appeared in a .set nomacro
1008 block and if one alternative requires a warning but the other does not.
1011 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1014 RELAX_DELAY_SLOT_16BIT
1015 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1018 RELAX_DELAY_SLOT_SIZE_FIRST
1019 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1020 the macro is of the wrong size for the branch delay slot.
1022 RELAX_DELAY_SLOT_SIZE_SECOND
1023 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1024 the macro is of the wrong size for the branch delay slot.
1026 The frag's "opcode" points to the first fixup for relaxable code.
1028 Relaxable macros are generated using a sequence such as:
1030 relax_start (SYMBOL);
1031 ... generate first expansion ...
1033 ... generate second expansion ...
1036 The code and fixups for the unwanted alternative are discarded
1037 by md_convert_frag. */
1038 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1039 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1041 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1042 #define RELAX_SECOND(X) ((X) & 0xff)
1043 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1044 #define RELAX_USE_SECOND 0x20000
1045 #define RELAX_SECOND_LONGER 0x40000
1046 #define RELAX_NOMACRO 0x80000
1047 #define RELAX_DELAY_SLOT 0x100000
1048 #define RELAX_DELAY_SLOT_16BIT 0x200000
1049 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1050 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1052 /* Branch without likely bit. If label is out of range, we turn:
1054 beq reg1, reg2, label
1064 with the following opcode replacements:
1071 bltzal <-> bgezal (with jal label instead of j label)
1073 Even though keeping the delay slot instruction in the delay slot of
1074 the branch would be more efficient, it would be very tricky to do
1075 correctly, because we'd have to introduce a variable frag *after*
1076 the delay slot instruction, and expand that instead. Let's do it
1077 the easy way for now, even if the branch-not-taken case now costs
1078 one additional instruction. Out-of-range branches are not supposed
1079 to be common, anyway.
1081 Branch likely. If label is out of range, we turn:
1083 beql reg1, reg2, label
1084 delay slot (annulled if branch not taken)
1093 delay slot (executed only if branch taken)
1096 It would be possible to generate a shorter sequence by losing the
1097 likely bit, generating something like:
1102 delay slot (executed only if branch taken)
1114 bltzall -> bgezal (with jal label instead of j label)
1115 bgezall -> bltzal (ditto)
1118 but it's not clear that it would actually improve performance. */
1119 #define RELAX_BRANCH_ENCODE(at, pic, \
1120 uncond, likely, link, toofar) \
1121 ((relax_substateT) \
1124 | ((pic) ? 0x20 : 0) \
1125 | ((toofar) ? 0x40 : 0) \
1126 | ((link) ? 0x80 : 0) \
1127 | ((likely) ? 0x100 : 0) \
1128 | ((uncond) ? 0x200 : 0)))
1129 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1130 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1131 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1132 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1133 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1134 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1135 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1137 /* For mips16 code, we use an entirely different form of relaxation.
1138 mips16 supports two versions of most instructions which take
1139 immediate values: a small one which takes some small value, and a
1140 larger one which takes a 16 bit value. Since branches also follow
1141 this pattern, relaxing these values is required.
1143 We can assemble both mips16 and normal MIPS code in a single
1144 object. Therefore, we need to support this type of relaxation at
1145 the same time that we support the relaxation described above. We
1146 use the high bit of the subtype field to distinguish these cases.
1148 The information we store for this type of relaxation is the
1149 argument code found in the opcode file for this relocation, whether
1150 the user explicitly requested a small or extended form, and whether
1151 the relocation is in a jump or jal delay slot. That tells us the
1152 size of the value, and how it should be stored. We also store
1153 whether the fragment is considered to be extended or not. We also
1154 store whether this is known to be a branch to a different section,
1155 whether we have tried to relax this frag yet, and whether we have
1156 ever extended a PC relative fragment because of a shift count. */
1157 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1162 | ((e2) ? 0x100 : 0) \
1163 | ((pic) ? 0x200 : 0) \
1164 | ((sym32) ? 0x400 : 0) \
1165 | ((nomacro) ? 0x800 : 0) \
1166 | ((small) ? 0x1000 : 0) \
1167 | ((ext) ? 0x2000 : 0) \
1168 | ((dslot) ? 0x4000 : 0) \
1169 | ((jal_dslot) ? 0x8000 : 0))
1171 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1172 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1174 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1175 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1176 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1177 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1178 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1179 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1180 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1182 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1183 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1184 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1185 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1186 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1187 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1188 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1189 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1190 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1192 /* For microMIPS code, we use relaxation similar to one we use for
1193 MIPS16 code. Some instructions that take immediate values support
1194 two encodings: a small one which takes some small value, and a
1195 larger one which takes a 16 bit value. As some branches also follow
1196 this pattern, relaxing these values is required.
1198 We can assemble both microMIPS and normal MIPS code in a single
1199 object. Therefore, we need to support this type of relaxation at
1200 the same time that we support the relaxation described above. We
1201 use one of the high bits of the subtype field to distinguish these
1204 The information we store for this type of relaxation is the argument
1205 code found in the opcode file for this relocation, the register
1206 selected as the assembler temporary, whether in the 32-bit
1207 instruction mode, whether the branch is unconditional, whether it is
1208 compact, whether there is no delay-slot instruction available to fill
1209 in, whether it stores the link address implicitly in $ra, whether
1210 relaxation of out-of-range 32-bit branches to a sequence of
1211 instructions is enabled, and whether the displacement of a branch is
1212 too large to fit as an immediate argument of a 16-bit and a 32-bit
1213 branch, respectively. */
1214 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1215 uncond, compact, link, nods, \
1216 relax32, toofar16, toofar32) \
1219 | (((at) & 0x1f) << 8) \
1220 | ((insn32) ? 0x2000 : 0) \
1221 | ((pic) ? 0x4000 : 0) \
1222 | ((uncond) ? 0x8000 : 0) \
1223 | ((compact) ? 0x10000 : 0) \
1224 | ((link) ? 0x20000 : 0) \
1225 | ((nods) ? 0x40000 : 0) \
1226 | ((relax32) ? 0x80000 : 0) \
1227 | ((toofar16) ? 0x100000 : 0) \
1228 | ((toofar32) ? 0x200000 : 0))
1229 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1230 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1231 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1232 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1233 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1234 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1235 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1236 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1237 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1238 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1240 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1241 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1242 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1243 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1244 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1245 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1247 /* Sign-extend 16-bit value X. */
1248 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1250 /* Is the given value a sign-extended 32-bit value? */
1251 #define IS_SEXT_32BIT_NUM(x) \
1252 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1253 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1255 /* Is the given value a sign-extended 16-bit value? */
1256 #define IS_SEXT_16BIT_NUM(x) \
1257 (((x) &~ (offsetT) 0x7fff) == 0 \
1258 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1260 /* Is the given value a sign-extended 12-bit value? */
1261 #define IS_SEXT_12BIT_NUM(x) \
1262 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1264 /* Is the given value a sign-extended 9-bit value? */
1265 #define IS_SEXT_9BIT_NUM(x) \
1266 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1268 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1269 #define IS_ZEXT_32BIT_NUM(x) \
1270 (((x) &~ (offsetT) 0xffffffff) == 0 \
1271 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1273 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1275 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1276 (((STRUCT) >> (SHIFT)) & (MASK))
1278 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1279 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1281 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1282 : EXTRACT_BITS ((INSN).insn_opcode, \
1283 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1284 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1285 EXTRACT_BITS ((INSN).insn_opcode, \
1286 MIPS16OP_MASK_##FIELD, \
1287 MIPS16OP_SH_##FIELD)
1289 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1290 #define MIPS16_EXTEND (0xf000U << 16)
1292 /* Whether or not we are emitting a branch-likely macro. */
1293 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1295 /* Global variables used when generating relaxable macros. See the
1296 comment above RELAX_ENCODE for more details about how relaxation
1299 /* 0 if we're not emitting a relaxable macro.
1300 1 if we're emitting the first of the two relaxation alternatives.
1301 2 if we're emitting the second alternative. */
1304 /* The first relaxable fixup in the current frag. (In other words,
1305 the first fixup that refers to relaxable code.) */
1308 /* sizes[0] says how many bytes of the first alternative are stored in
1309 the current frag. Likewise sizes[1] for the second alternative. */
1310 unsigned int sizes
[2];
1312 /* The symbol on which the choice of sequence depends. */
1316 /* Global variables used to decide whether a macro needs a warning. */
1318 /* True if the macro is in a branch delay slot. */
1319 bfd_boolean delay_slot_p
;
1321 /* Set to the length in bytes required if the macro is in a delay slot
1322 that requires a specific length of instruction, otherwise zero. */
1323 unsigned int delay_slot_length
;
1325 /* For relaxable macros, sizes[0] is the length of the first alternative
1326 in bytes and sizes[1] is the length of the second alternative.
1327 For non-relaxable macros, both elements give the length of the
1329 unsigned int sizes
[2];
1331 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1332 instruction of the first alternative in bytes and first_insn_sizes[1]
1333 is the length of the first instruction of the second alternative.
1334 For non-relaxable macros, both elements give the length of the first
1335 instruction in bytes.
1337 Set to zero if we haven't yet seen the first instruction. */
1338 unsigned int first_insn_sizes
[2];
1340 /* For relaxable macros, insns[0] is the number of instructions for the
1341 first alternative and insns[1] is the number of instructions for the
1344 For non-relaxable macros, both elements give the number of
1345 instructions for the macro. */
1346 unsigned int insns
[2];
1348 /* The first variant frag for this macro. */
1350 } mips_macro_warning
;
1352 /* Prototypes for static functions. */
1354 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1356 static void append_insn
1357 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1358 bfd_boolean expansionp
);
1359 static void mips_no_prev_insn (void);
1360 static void macro_build (expressionS
*, const char *, const char *, ...);
1361 static void mips16_macro_build
1362 (expressionS
*, const char *, const char *, va_list *);
1363 static void load_register (int, expressionS
*, int);
1364 static void macro_start (void);
1365 static void macro_end (void);
1366 static void macro (struct mips_cl_insn
*ip
, char *str
);
1367 static void mips16_macro (struct mips_cl_insn
* ip
);
1368 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1369 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1370 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1371 static void mips16_immed
1372 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1373 unsigned int, unsigned long *);
1374 static size_t my_getSmallExpression
1375 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1376 static void my_getExpression (expressionS
*, char *);
1377 static void s_align (int);
1378 static void s_change_sec (int);
1379 static void s_change_section (int);
1380 static void s_cons (int);
1381 static void s_float_cons (int);
1382 static void s_mips_globl (int);
1383 static void s_option (int);
1384 static void s_mipsset (int);
1385 static void s_abicalls (int);
1386 static void s_cpload (int);
1387 static void s_cpsetup (int);
1388 static void s_cplocal (int);
1389 static void s_cprestore (int);
1390 static void s_cpreturn (int);
1391 static void s_dtprelword (int);
1392 static void s_dtpreldword (int);
1393 static void s_tprelword (int);
1394 static void s_tpreldword (int);
1395 static void s_gpvalue (int);
1396 static void s_gpword (int);
1397 static void s_gpdword (int);
1398 static void s_ehword (int);
1399 static void s_cpadd (int);
1400 static void s_insn (int);
1401 static void s_nan (int);
1402 static void s_module (int);
1403 static void s_mips_ent (int);
1404 static void s_mips_end (int);
1405 static void s_mips_frame (int);
1406 static void s_mips_mask (int reg_type
);
1407 static void s_mips_stab (int);
1408 static void s_mips_weakext (int);
1409 static void s_mips_file (int);
1410 static void s_mips_loc (int);
1411 static bfd_boolean
pic_need_relax (symbolS
*);
1412 static int relaxed_branch_length (fragS
*, asection
*, int);
1413 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1414 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1415 static void file_mips_check_options (void);
1417 /* Table and functions used to map between CPU/ISA names, and
1418 ISA levels, and CPU numbers. */
1420 struct mips_cpu_info
1422 const char *name
; /* CPU or ISA name. */
1423 int flags
; /* MIPS_CPU_* flags. */
1424 int ase
; /* Set of ASEs implemented by the CPU. */
1425 int isa
; /* ISA level. */
1426 int cpu
; /* CPU number (default CPU if ISA). */
1429 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1431 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1432 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1433 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1435 /* Command-line options. */
1436 const char *md_shortopts
= "O::g::G:";
1440 OPTION_MARCH
= OPTION_MD_BASE
,
1472 OPTION_NO_SMARTMIPS
,
1482 OPTION_NO_MICROMIPS
,
1497 OPTION_M7000_HILO_FIX
,
1498 OPTION_MNO_7000_HILO_FIX
,
1502 OPTION_NO_FIX_RM7000
,
1503 OPTION_FIX_LOONGSON3_LLSC
,
1504 OPTION_NO_FIX_LOONGSON3_LLSC
,
1505 OPTION_FIX_LOONGSON2F_JUMP
,
1506 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1507 OPTION_FIX_LOONGSON2F_NOP
,
1508 OPTION_NO_FIX_LOONGSON2F_NOP
,
1510 OPTION_NO_FIX_VR4120
,
1512 OPTION_NO_FIX_VR4130
,
1513 OPTION_FIX_CN63XXP1
,
1514 OPTION_NO_FIX_CN63XXP1
,
1516 OPTION_NO_FIX_R5900
,
1523 OPTION_CONSTRUCT_FLOATS
,
1524 OPTION_NO_CONSTRUCT_FLOATS
,
1528 OPTION_RELAX_BRANCH
,
1529 OPTION_NO_RELAX_BRANCH
,
1530 OPTION_IGNORE_BRANCH_ISA
,
1531 OPTION_NO_IGNORE_BRANCH_ISA
,
1540 OPTION_SINGLE_FLOAT
,
1541 OPTION_DOUBLE_FLOAT
,
1554 OPTION_MVXWORKS_PIC
,
1557 OPTION_NO_ODD_SPREG
,
1560 OPTION_LOONGSON_MMI
,
1561 OPTION_NO_LOONGSON_MMI
,
1562 OPTION_LOONGSON_CAM
,
1563 OPTION_NO_LOONGSON_CAM
,
1564 OPTION_LOONGSON_EXT
,
1565 OPTION_NO_LOONGSON_EXT
,
1566 OPTION_LOONGSON_EXT2
,
1567 OPTION_NO_LOONGSON_EXT2
,
1571 struct option md_longopts
[] =
1573 /* Options which specify architecture. */
1574 {"march", required_argument
, NULL
, OPTION_MARCH
},
1575 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1576 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1577 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1578 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1579 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1580 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1581 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1582 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1583 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1584 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1585 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1586 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1587 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1588 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1589 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1590 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1591 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1593 /* Options which specify Application Specific Extensions (ASEs). */
1594 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1595 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1596 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1597 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1598 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1599 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1600 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1601 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1602 {"mmt", no_argument
, NULL
, OPTION_MT
},
1603 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1604 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1605 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1606 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1607 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1608 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1609 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1610 {"meva", no_argument
, NULL
, OPTION_EVA
},
1611 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1612 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1613 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1614 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1615 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1616 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1617 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1618 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1619 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1620 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1621 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1622 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1623 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1624 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1625 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1626 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1627 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1628 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1629 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1630 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1631 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1632 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1633 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1634 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1635 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1637 /* Old-style architecture options. Don't add more of these. */
1638 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1639 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1640 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1641 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1642 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1643 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1644 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1645 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1647 /* Options which enable bug fixes. */
1648 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1649 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1650 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1651 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1652 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1653 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1654 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1655 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1656 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1657 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1658 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1659 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1660 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1661 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1662 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1663 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1664 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1665 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1666 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1667 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1668 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1670 /* Miscellaneous options. */
1671 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1672 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1673 {"break", no_argument
, NULL
, OPTION_BREAK
},
1674 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1675 {"EB", no_argument
, NULL
, OPTION_EB
},
1676 {"EL", no_argument
, NULL
, OPTION_EL
},
1677 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1678 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1679 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1680 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1681 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1682 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1683 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1684 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1685 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1686 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1687 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1688 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1689 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1690 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1691 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1692 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1693 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1694 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1695 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1696 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1697 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1698 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1699 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1701 /* Strictly speaking this next option is ELF specific,
1702 but we allow it for other ports as well in order to
1703 make testing easier. */
1704 {"32", no_argument
, NULL
, OPTION_32
},
1706 /* ELF-specific options. */
1707 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1708 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1709 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1710 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1711 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1712 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1713 {"n32", no_argument
, NULL
, OPTION_N32
},
1714 {"64", no_argument
, NULL
, OPTION_64
},
1715 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1716 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1717 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1718 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1719 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1720 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1722 {NULL
, no_argument
, NULL
, 0}
1724 size_t md_longopts_size
= sizeof (md_longopts
);
1726 /* Information about either an Application Specific Extension or an
1727 optional architecture feature that, for simplicity, we treat in the
1728 same way as an ASE. */
1731 /* The name of the ASE, used in both the command-line and .set options. */
1734 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1735 and 64-bit architectures, the flags here refer to the subset that
1736 is available on both. */
1739 /* The ASE_* flag used for instructions that are available on 64-bit
1740 architectures but that are not included in FLAGS. */
1741 unsigned int flags64
;
1743 /* The command-line options that turn the ASE on and off. */
1747 /* The minimum required architecture revisions for MIPS32, MIPS64,
1748 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1751 int micromips32_rev
;
1752 int micromips64_rev
;
1754 /* The architecture where the ASE was removed or -1 if the extension has not
1759 /* A table of all supported ASEs. */
1760 static const struct mips_ase mips_ases
[] = {
1761 { "dsp", ASE_DSP
, ASE_DSP64
,
1762 OPTION_DSP
, OPTION_NO_DSP
,
1766 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1767 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1771 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1772 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1776 { "eva", ASE_EVA
, 0,
1777 OPTION_EVA
, OPTION_NO_EVA
,
1781 { "mcu", ASE_MCU
, 0,
1782 OPTION_MCU
, OPTION_NO_MCU
,
1786 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1787 { "mdmx", ASE_MDMX
, 0,
1788 OPTION_MDMX
, OPTION_NO_MDMX
,
1792 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1793 { "mips3d", ASE_MIPS3D
, 0,
1794 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1799 OPTION_MT
, OPTION_NO_MT
,
1803 { "smartmips", ASE_SMARTMIPS
, 0,
1804 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1808 { "virt", ASE_VIRT
, ASE_VIRT64
,
1809 OPTION_VIRT
, OPTION_NO_VIRT
,
1813 { "msa", ASE_MSA
, ASE_MSA64
,
1814 OPTION_MSA
, OPTION_NO_MSA
,
1818 { "xpa", ASE_XPA
, 0,
1819 OPTION_XPA
, OPTION_NO_XPA
,
1823 { "mips16e2", ASE_MIPS16E2
, 0,
1824 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1828 { "crc", ASE_CRC
, ASE_CRC64
,
1829 OPTION_CRC
, OPTION_NO_CRC
,
1833 { "ginv", ASE_GINV
, 0,
1834 OPTION_GINV
, OPTION_NO_GINV
,
1838 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1839 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1843 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1844 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1848 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1849 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1853 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1854 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1859 /* The set of ASEs that require -mfp64. */
1860 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1862 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1863 static const unsigned int mips_ase_groups
[] = {
1864 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1865 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1870 The following pseudo-ops from the Kane and Heinrich MIPS book
1871 should be defined here, but are currently unsupported: .alias,
1872 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1874 The following pseudo-ops from the Kane and Heinrich MIPS book are
1875 specific to the type of debugging information being generated, and
1876 should be defined by the object format: .aent, .begin, .bend,
1877 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1880 The following pseudo-ops from the Kane and Heinrich MIPS book are
1881 not MIPS CPU specific, but are also not specific to the object file
1882 format. This file is probably the best place to define them, but
1883 they are not currently supported: .asm0, .endr, .lab, .struct. */
1885 static const pseudo_typeS mips_pseudo_table
[] =
1887 /* MIPS specific pseudo-ops. */
1888 {"option", s_option
, 0},
1889 {"set", s_mipsset
, 0},
1890 {"rdata", s_change_sec
, 'r'},
1891 {"sdata", s_change_sec
, 's'},
1892 {"livereg", s_ignore
, 0},
1893 {"abicalls", s_abicalls
, 0},
1894 {"cpload", s_cpload
, 0},
1895 {"cpsetup", s_cpsetup
, 0},
1896 {"cplocal", s_cplocal
, 0},
1897 {"cprestore", s_cprestore
, 0},
1898 {"cpreturn", s_cpreturn
, 0},
1899 {"dtprelword", s_dtprelword
, 0},
1900 {"dtpreldword", s_dtpreldword
, 0},
1901 {"tprelword", s_tprelword
, 0},
1902 {"tpreldword", s_tpreldword
, 0},
1903 {"gpvalue", s_gpvalue
, 0},
1904 {"gpword", s_gpword
, 0},
1905 {"gpdword", s_gpdword
, 0},
1906 {"ehword", s_ehword
, 0},
1907 {"cpadd", s_cpadd
, 0},
1908 {"insn", s_insn
, 0},
1910 {"module", s_module
, 0},
1912 /* Relatively generic pseudo-ops that happen to be used on MIPS
1914 {"asciiz", stringer
, 8 + 1},
1915 {"bss", s_change_sec
, 'b'},
1917 {"half", s_cons
, 1},
1918 {"dword", s_cons
, 3},
1919 {"weakext", s_mips_weakext
, 0},
1920 {"origin", s_org
, 0},
1921 {"repeat", s_rept
, 0},
1923 /* For MIPS this is non-standard, but we define it for consistency. */
1924 {"sbss", s_change_sec
, 'B'},
1926 /* These pseudo-ops are defined in read.c, but must be overridden
1927 here for one reason or another. */
1928 {"align", s_align
, 0},
1929 {"byte", s_cons
, 0},
1930 {"data", s_change_sec
, 'd'},
1931 {"double", s_float_cons
, 'd'},
1932 {"float", s_float_cons
, 'f'},
1933 {"globl", s_mips_globl
, 0},
1934 {"global", s_mips_globl
, 0},
1935 {"hword", s_cons
, 1},
1937 {"long", s_cons
, 2},
1938 {"octa", s_cons
, 4},
1939 {"quad", s_cons
, 3},
1940 {"section", s_change_section
, 0},
1941 {"short", s_cons
, 1},
1942 {"single", s_float_cons
, 'f'},
1943 {"stabd", s_mips_stab
, 'd'},
1944 {"stabn", s_mips_stab
, 'n'},
1945 {"stabs", s_mips_stab
, 's'},
1946 {"text", s_change_sec
, 't'},
1947 {"word", s_cons
, 2},
1949 { "extern", ecoff_directive_extern
, 0},
1954 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1956 /* These pseudo-ops should be defined by the object file format.
1957 However, a.out doesn't support them, so we have versions here. */
1958 {"aent", s_mips_ent
, 1},
1959 {"bgnb", s_ignore
, 0},
1960 {"end", s_mips_end
, 0},
1961 {"endb", s_ignore
, 0},
1962 {"ent", s_mips_ent
, 0},
1963 {"file", s_mips_file
, 0},
1964 {"fmask", s_mips_mask
, 'F'},
1965 {"frame", s_mips_frame
, 0},
1966 {"loc", s_mips_loc
, 0},
1967 {"mask", s_mips_mask
, 'R'},
1968 {"verstamp", s_ignore
, 0},
1972 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1973 purpose of the `.dc.a' internal pseudo-op. */
1976 mips_address_bytes (void)
1978 file_mips_check_options ();
1979 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1982 extern void pop_insert (const pseudo_typeS
*);
1985 mips_pop_insert (void)
1987 pop_insert (mips_pseudo_table
);
1988 if (! ECOFF_DEBUGGING
)
1989 pop_insert (mips_nonecoff_pseudo_table
);
1992 /* Symbols labelling the current insn. */
1994 struct insn_label_list
1996 struct insn_label_list
*next
;
2000 static struct insn_label_list
*free_insn_labels
;
2001 #define label_list tc_segment_info_data.labels
2003 static void mips_clear_insn_labels (void);
2004 static void mips_mark_labels (void);
2005 static void mips_compressed_mark_labels (void);
2008 mips_clear_insn_labels (void)
2010 struct insn_label_list
**pl
;
2011 segment_info_type
*si
;
2015 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2018 si
= seg_info (now_seg
);
2019 *pl
= si
->label_list
;
2020 si
->label_list
= NULL
;
2024 /* Mark instruction labels in MIPS16/microMIPS mode. */
2027 mips_mark_labels (void)
2029 if (HAVE_CODE_COMPRESSION
)
2030 mips_compressed_mark_labels ();
2033 static char *expr_end
;
2035 /* An expression in a macro instruction. This is set by mips_ip and
2036 mips16_ip and when populated is always an O_constant. */
2038 static expressionS imm_expr
;
2040 /* The relocatable field in an instruction and the relocs associated
2041 with it. These variables are used for instructions like LUI and
2042 JAL as well as true offsets. They are also used for address
2043 operands in macros. */
2045 static expressionS offset_expr
;
2046 static bfd_reloc_code_real_type offset_reloc
[3]
2047 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2049 /* This is set to the resulting size of the instruction to be produced
2050 by mips16_ip if an explicit extension is used or by mips_ip if an
2051 explicit size is supplied. */
2053 static unsigned int forced_insn_length
;
2055 /* True if we are assembling an instruction. All dot symbols defined during
2056 this time should be treated as code labels. */
2058 static bfd_boolean mips_assembling_insn
;
2060 /* The pdr segment for per procedure frame/regmask info. Not used for
2063 static segT pdr_seg
;
2065 /* The default target format to use. */
2067 #if defined (TE_FreeBSD)
2068 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2069 #elif defined (TE_TMIPS)
2070 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2072 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2076 mips_target_format (void)
2078 switch (OUTPUT_FLAVOR
)
2080 case bfd_target_elf_flavour
:
2082 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2083 return (target_big_endian
2084 ? "elf32-bigmips-vxworks"
2085 : "elf32-littlemips-vxworks");
2087 return (target_big_endian
2088 ? (HAVE_64BIT_OBJECTS
2089 ? ELF_TARGET ("elf64-", "big")
2091 ? ELF_TARGET ("elf32-n", "big")
2092 : ELF_TARGET ("elf32-", "big")))
2093 : (HAVE_64BIT_OBJECTS
2094 ? ELF_TARGET ("elf64-", "little")
2096 ? ELF_TARGET ("elf32-n", "little")
2097 : ELF_TARGET ("elf32-", "little"))));
2104 /* Return the ISA revision that is currently in use, or 0 if we are
2105 generating code for MIPS V or below. */
2110 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2113 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2116 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2119 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2122 /* microMIPS implies revision 2 or above. */
2123 if (mips_opts
.micromips
)
2126 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2132 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2135 mips_ase_mask (unsigned int flags
)
2139 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2140 if (flags
& mips_ase_groups
[i
])
2141 flags
|= mips_ase_groups
[i
];
2145 /* Check whether the current ISA supports ASE. Issue a warning if
2149 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2153 static unsigned int warned_isa
;
2154 static unsigned int warned_fp32
;
2156 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2157 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2159 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2160 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2161 && (warned_isa
& ase
->flags
) != ase
->flags
)
2163 warned_isa
|= ase
->flags
;
2164 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2165 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2167 as_warn (_("the %d-bit %s architecture does not support the"
2168 " `%s' extension"), size
, base
, ase
->name
);
2170 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2171 ase
->name
, base
, size
, min_rev
);
2173 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2174 && (warned_isa
& ase
->flags
) != ase
->flags
)
2176 warned_isa
|= ase
->flags
;
2177 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2178 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2179 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2180 ase
->name
, base
, size
, ase
->rem_rev
);
2183 if ((ase
->flags
& FP64_ASES
)
2184 && mips_opts
.fp
!= 64
2185 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2187 warned_fp32
|= ase
->flags
;
2188 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2192 /* Check all enabled ASEs to see whether they are supported by the
2193 chosen architecture. */
2196 mips_check_isa_supports_ases (void)
2198 unsigned int i
, mask
;
2200 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2202 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2203 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2204 mips_check_isa_supports_ase (&mips_ases
[i
]);
2208 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2209 that were affected. */
2212 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2213 bfd_boolean enabled_p
)
2217 mask
= mips_ase_mask (ase
->flags
);
2220 /* Clear combination ASE flags, which need to be recalculated based on
2221 updated regular ASE settings. */
2222 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2225 opts
->ase
|= ase
->flags
;
2227 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2228 instructions which are only valid when both ASEs are enabled.
2229 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2230 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2232 opts
->ase
|= ASE_XPA_VIRT
;
2233 mask
|= ASE_XPA_VIRT
;
2235 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2237 opts
->ase
|= ASE_MIPS16E2_MT
;
2238 mask
|= ASE_MIPS16E2_MT
;
2244 /* Return the ASE called NAME, or null if none. */
2246 static const struct mips_ase
*
2247 mips_lookup_ase (const char *name
)
2251 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2252 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2253 return &mips_ases
[i
];
2257 /* Return the length of a microMIPS instruction in bytes. If bits of
2258 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2259 otherwise it is a 32-bit instruction. */
2261 static inline unsigned int
2262 micromips_insn_length (const struct mips_opcode
*mo
)
2264 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2267 /* Return the length of MIPS16 instruction OPCODE. */
2269 static inline unsigned int
2270 mips16_opcode_length (unsigned long opcode
)
2272 return (opcode
>> 16) == 0 ? 2 : 4;
2275 /* Return the length of instruction INSN. */
2277 static inline unsigned int
2278 insn_length (const struct mips_cl_insn
*insn
)
2280 if (mips_opts
.micromips
)
2281 return micromips_insn_length (insn
->insn_mo
);
2282 else if (mips_opts
.mips16
)
2283 return mips16_opcode_length (insn
->insn_opcode
);
2288 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2291 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2296 insn
->insn_opcode
= mo
->match
;
2299 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2300 insn
->fixp
[i
] = NULL
;
2301 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2302 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2303 insn
->mips16_absolute_jump_p
= 0;
2304 insn
->complete_p
= 0;
2305 insn
->cleared_p
= 0;
2308 /* Get a list of all the operands in INSN. */
2310 static const struct mips_operand_array
*
2311 insn_operands (const struct mips_cl_insn
*insn
)
2313 if (insn
->insn_mo
>= &mips_opcodes
[0]
2314 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2315 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2317 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2318 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2319 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2321 if (insn
->insn_mo
>= µmips_opcodes
[0]
2322 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2323 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2328 /* Get a description of operand OPNO of INSN. */
2330 static const struct mips_operand
*
2331 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2333 const struct mips_operand_array
*operands
;
2335 operands
= insn_operands (insn
);
2336 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2338 return operands
->operand
[opno
];
2341 /* Install UVAL as the value of OPERAND in INSN. */
2344 insn_insert_operand (struct mips_cl_insn
*insn
,
2345 const struct mips_operand
*operand
, unsigned int uval
)
2347 if (mips_opts
.mips16
2348 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2349 && mips_opcode_32bit_p (insn
->insn_mo
))
2350 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2352 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2355 /* Extract the value of OPERAND from INSN. */
2357 static inline unsigned
2358 insn_extract_operand (const struct mips_cl_insn
*insn
,
2359 const struct mips_operand
*operand
)
2361 return mips_extract_operand (operand
, insn
->insn_opcode
);
2364 /* Record the current MIPS16/microMIPS mode in now_seg. */
2367 mips_record_compressed_mode (void)
2369 segment_info_type
*si
;
2371 si
= seg_info (now_seg
);
2372 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2373 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2374 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2375 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2378 /* Read a standard MIPS instruction from BUF. */
2380 static unsigned long
2381 read_insn (char *buf
)
2383 if (target_big_endian
)
2384 return bfd_getb32 ((bfd_byte
*) buf
);
2386 return bfd_getl32 ((bfd_byte
*) buf
);
2389 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2393 write_insn (char *buf
, unsigned int insn
)
2395 md_number_to_chars (buf
, insn
, 4);
2399 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2400 has length LENGTH. */
2402 static unsigned long
2403 read_compressed_insn (char *buf
, unsigned int length
)
2409 for (i
= 0; i
< length
; i
+= 2)
2412 if (target_big_endian
)
2413 insn
|= bfd_getb16 ((char *) buf
);
2415 insn
|= bfd_getl16 ((char *) buf
);
2421 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2422 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2425 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2429 for (i
= 0; i
< length
; i
+= 2)
2430 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2431 return buf
+ length
;
2434 /* Install INSN at the location specified by its "frag" and "where" fields. */
2437 install_insn (const struct mips_cl_insn
*insn
)
2439 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2440 if (HAVE_CODE_COMPRESSION
)
2441 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2443 write_insn (f
, insn
->insn_opcode
);
2444 mips_record_compressed_mode ();
2447 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2448 and install the opcode in the new location. */
2451 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2456 insn
->where
= where
;
2457 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2458 if (insn
->fixp
[i
] != NULL
)
2460 insn
->fixp
[i
]->fx_frag
= frag
;
2461 insn
->fixp
[i
]->fx_where
= where
;
2463 install_insn (insn
);
2466 /* Add INSN to the end of the output. */
2469 add_fixed_insn (struct mips_cl_insn
*insn
)
2471 char *f
= frag_more (insn_length (insn
));
2472 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2475 /* Start a variant frag and move INSN to the start of the variant part,
2476 marking it as fixed. The other arguments are as for frag_var. */
2479 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2480 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2482 frag_grow (max_chars
);
2483 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2485 frag_var (rs_machine_dependent
, max_chars
, var
,
2486 subtype
, symbol
, offset
, NULL
);
2489 /* Insert N copies of INSN into the history buffer, starting at
2490 position FIRST. Neither FIRST nor N need to be clipped. */
2493 insert_into_history (unsigned int first
, unsigned int n
,
2494 const struct mips_cl_insn
*insn
)
2496 if (mips_relax
.sequence
!= 2)
2500 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2502 history
[i
] = history
[i
- n
];
2508 /* Clear the error in insn_error. */
2511 clear_insn_error (void)
2513 memset (&insn_error
, 0, sizeof (insn_error
));
2516 /* Possibly record error message MSG for the current instruction.
2517 If the error is about a particular argument, ARGNUM is the 1-based
2518 number of that argument, otherwise it is 0. FORMAT is the format
2519 of MSG. Return true if MSG was used, false if the current message
2523 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2528 /* Give priority to errors against specific arguments, and to
2529 the first whole-instruction message. */
2535 /* Keep insn_error if it is against a later argument. */
2536 if (argnum
< insn_error
.min_argnum
)
2539 /* If both errors are against the same argument but are different,
2540 give up on reporting a specific error for this argument.
2541 See the comment about mips_insn_error for details. */
2542 if (argnum
== insn_error
.min_argnum
2544 && strcmp (insn_error
.msg
, msg
) != 0)
2547 insn_error
.min_argnum
+= 1;
2551 insn_error
.min_argnum
= argnum
;
2552 insn_error
.format
= format
;
2553 insn_error
.msg
= msg
;
2557 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2558 as for set_insn_error_format. */
2561 set_insn_error (int argnum
, const char *msg
)
2563 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2566 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2567 as for set_insn_error_format. */
2570 set_insn_error_i (int argnum
, const char *msg
, int i
)
2572 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2576 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2577 are as for set_insn_error_format. */
2580 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2582 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2584 insn_error
.u
.ss
[0] = s1
;
2585 insn_error
.u
.ss
[1] = s2
;
2589 /* Report the error in insn_error, which is against assembly code STR. */
2592 report_insn_error (const char *str
)
2594 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2596 switch (insn_error
.format
)
2603 as_bad (msg
, insn_error
.u
.i
, str
);
2607 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2611 free ((char *) msg
);
2614 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2615 the idea is to make it obvious at a glance that each errata is
2619 init_vr4120_conflicts (void)
2621 #define CONFLICT(FIRST, SECOND) \
2622 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2624 /* Errata 21 - [D]DIV[U] after [D]MACC */
2625 CONFLICT (MACC
, DIV
);
2626 CONFLICT (DMACC
, DIV
);
2628 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2629 CONFLICT (DMULT
, DMULT
);
2630 CONFLICT (DMULT
, DMACC
);
2631 CONFLICT (DMACC
, DMULT
);
2632 CONFLICT (DMACC
, DMACC
);
2634 /* Errata 24 - MT{LO,HI} after [D]MACC */
2635 CONFLICT (MACC
, MTHILO
);
2636 CONFLICT (DMACC
, MTHILO
);
2638 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2639 instruction is executed immediately after a MACC or DMACC
2640 instruction, the result of [either instruction] is incorrect." */
2641 CONFLICT (MACC
, MULT
);
2642 CONFLICT (MACC
, DMULT
);
2643 CONFLICT (DMACC
, MULT
);
2644 CONFLICT (DMACC
, DMULT
);
2646 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2647 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2648 DDIV or DDIVU instruction, the result of the MACC or
2649 DMACC instruction is incorrect.". */
2650 CONFLICT (DMULT
, MACC
);
2651 CONFLICT (DMULT
, DMACC
);
2652 CONFLICT (DIV
, MACC
);
2653 CONFLICT (DIV
, DMACC
);
2663 #define RNUM_MASK 0x00000ff
2664 #define RTYPE_MASK 0x0ffff00
2665 #define RTYPE_NUM 0x0000100
2666 #define RTYPE_FPU 0x0000200
2667 #define RTYPE_FCC 0x0000400
2668 #define RTYPE_VEC 0x0000800
2669 #define RTYPE_GP 0x0001000
2670 #define RTYPE_CP0 0x0002000
2671 #define RTYPE_PC 0x0004000
2672 #define RTYPE_ACC 0x0008000
2673 #define RTYPE_CCC 0x0010000
2674 #define RTYPE_VI 0x0020000
2675 #define RTYPE_VF 0x0040000
2676 #define RTYPE_R5900_I 0x0080000
2677 #define RTYPE_R5900_Q 0x0100000
2678 #define RTYPE_R5900_R 0x0200000
2679 #define RTYPE_R5900_ACC 0x0400000
2680 #define RTYPE_MSA 0x0800000
2681 #define RWARN 0x8000000
2683 #define GENERIC_REGISTER_NUMBERS \
2684 {"$0", RTYPE_NUM | 0}, \
2685 {"$1", RTYPE_NUM | 1}, \
2686 {"$2", RTYPE_NUM | 2}, \
2687 {"$3", RTYPE_NUM | 3}, \
2688 {"$4", RTYPE_NUM | 4}, \
2689 {"$5", RTYPE_NUM | 5}, \
2690 {"$6", RTYPE_NUM | 6}, \
2691 {"$7", RTYPE_NUM | 7}, \
2692 {"$8", RTYPE_NUM | 8}, \
2693 {"$9", RTYPE_NUM | 9}, \
2694 {"$10", RTYPE_NUM | 10}, \
2695 {"$11", RTYPE_NUM | 11}, \
2696 {"$12", RTYPE_NUM | 12}, \
2697 {"$13", RTYPE_NUM | 13}, \
2698 {"$14", RTYPE_NUM | 14}, \
2699 {"$15", RTYPE_NUM | 15}, \
2700 {"$16", RTYPE_NUM | 16}, \
2701 {"$17", RTYPE_NUM | 17}, \
2702 {"$18", RTYPE_NUM | 18}, \
2703 {"$19", RTYPE_NUM | 19}, \
2704 {"$20", RTYPE_NUM | 20}, \
2705 {"$21", RTYPE_NUM | 21}, \
2706 {"$22", RTYPE_NUM | 22}, \
2707 {"$23", RTYPE_NUM | 23}, \
2708 {"$24", RTYPE_NUM | 24}, \
2709 {"$25", RTYPE_NUM | 25}, \
2710 {"$26", RTYPE_NUM | 26}, \
2711 {"$27", RTYPE_NUM | 27}, \
2712 {"$28", RTYPE_NUM | 28}, \
2713 {"$29", RTYPE_NUM | 29}, \
2714 {"$30", RTYPE_NUM | 30}, \
2715 {"$31", RTYPE_NUM | 31}
2717 #define FPU_REGISTER_NAMES \
2718 {"$f0", RTYPE_FPU | 0}, \
2719 {"$f1", RTYPE_FPU | 1}, \
2720 {"$f2", RTYPE_FPU | 2}, \
2721 {"$f3", RTYPE_FPU | 3}, \
2722 {"$f4", RTYPE_FPU | 4}, \
2723 {"$f5", RTYPE_FPU | 5}, \
2724 {"$f6", RTYPE_FPU | 6}, \
2725 {"$f7", RTYPE_FPU | 7}, \
2726 {"$f8", RTYPE_FPU | 8}, \
2727 {"$f9", RTYPE_FPU | 9}, \
2728 {"$f10", RTYPE_FPU | 10}, \
2729 {"$f11", RTYPE_FPU | 11}, \
2730 {"$f12", RTYPE_FPU | 12}, \
2731 {"$f13", RTYPE_FPU | 13}, \
2732 {"$f14", RTYPE_FPU | 14}, \
2733 {"$f15", RTYPE_FPU | 15}, \
2734 {"$f16", RTYPE_FPU | 16}, \
2735 {"$f17", RTYPE_FPU | 17}, \
2736 {"$f18", RTYPE_FPU | 18}, \
2737 {"$f19", RTYPE_FPU | 19}, \
2738 {"$f20", RTYPE_FPU | 20}, \
2739 {"$f21", RTYPE_FPU | 21}, \
2740 {"$f22", RTYPE_FPU | 22}, \
2741 {"$f23", RTYPE_FPU | 23}, \
2742 {"$f24", RTYPE_FPU | 24}, \
2743 {"$f25", RTYPE_FPU | 25}, \
2744 {"$f26", RTYPE_FPU | 26}, \
2745 {"$f27", RTYPE_FPU | 27}, \
2746 {"$f28", RTYPE_FPU | 28}, \
2747 {"$f29", RTYPE_FPU | 29}, \
2748 {"$f30", RTYPE_FPU | 30}, \
2749 {"$f31", RTYPE_FPU | 31}
2751 #define FPU_CONDITION_CODE_NAMES \
2752 {"$fcc0", RTYPE_FCC | 0}, \
2753 {"$fcc1", RTYPE_FCC | 1}, \
2754 {"$fcc2", RTYPE_FCC | 2}, \
2755 {"$fcc3", RTYPE_FCC | 3}, \
2756 {"$fcc4", RTYPE_FCC | 4}, \
2757 {"$fcc5", RTYPE_FCC | 5}, \
2758 {"$fcc6", RTYPE_FCC | 6}, \
2759 {"$fcc7", RTYPE_FCC | 7}
2761 #define COPROC_CONDITION_CODE_NAMES \
2762 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2763 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2764 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2765 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2766 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2767 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2768 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2769 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2771 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2772 {"$a4", RTYPE_GP | 8}, \
2773 {"$a5", RTYPE_GP | 9}, \
2774 {"$a6", RTYPE_GP | 10}, \
2775 {"$a7", RTYPE_GP | 11}, \
2776 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2777 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2778 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2779 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2780 {"$t0", RTYPE_GP | 12}, \
2781 {"$t1", RTYPE_GP | 13}, \
2782 {"$t2", RTYPE_GP | 14}, \
2783 {"$t3", RTYPE_GP | 15}
2785 #define O32_SYMBOLIC_REGISTER_NAMES \
2786 {"$t0", RTYPE_GP | 8}, \
2787 {"$t1", RTYPE_GP | 9}, \
2788 {"$t2", RTYPE_GP | 10}, \
2789 {"$t3", RTYPE_GP | 11}, \
2790 {"$t4", RTYPE_GP | 12}, \
2791 {"$t5", RTYPE_GP | 13}, \
2792 {"$t6", RTYPE_GP | 14}, \
2793 {"$t7", RTYPE_GP | 15}, \
2794 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2795 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2796 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2797 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2799 /* Remaining symbolic register names. */
2800 #define SYMBOLIC_REGISTER_NAMES \
2801 {"$zero", RTYPE_GP | 0}, \
2802 {"$at", RTYPE_GP | 1}, \
2803 {"$AT", RTYPE_GP | 1}, \
2804 {"$v0", RTYPE_GP | 2}, \
2805 {"$v1", RTYPE_GP | 3}, \
2806 {"$a0", RTYPE_GP | 4}, \
2807 {"$a1", RTYPE_GP | 5}, \
2808 {"$a2", RTYPE_GP | 6}, \
2809 {"$a3", RTYPE_GP | 7}, \
2810 {"$s0", RTYPE_GP | 16}, \
2811 {"$s1", RTYPE_GP | 17}, \
2812 {"$s2", RTYPE_GP | 18}, \
2813 {"$s3", RTYPE_GP | 19}, \
2814 {"$s4", RTYPE_GP | 20}, \
2815 {"$s5", RTYPE_GP | 21}, \
2816 {"$s6", RTYPE_GP | 22}, \
2817 {"$s7", RTYPE_GP | 23}, \
2818 {"$t8", RTYPE_GP | 24}, \
2819 {"$t9", RTYPE_GP | 25}, \
2820 {"$k0", RTYPE_GP | 26}, \
2821 {"$kt0", RTYPE_GP | 26}, \
2822 {"$k1", RTYPE_GP | 27}, \
2823 {"$kt1", RTYPE_GP | 27}, \
2824 {"$gp", RTYPE_GP | 28}, \
2825 {"$sp", RTYPE_GP | 29}, \
2826 {"$s8", RTYPE_GP | 30}, \
2827 {"$fp", RTYPE_GP | 30}, \
2828 {"$ra", RTYPE_GP | 31}
2830 #define MIPS16_SPECIAL_REGISTER_NAMES \
2831 {"$pc", RTYPE_PC | 0}
2833 #define MDMX_VECTOR_REGISTER_NAMES \
2834 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2835 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2836 {"$v2", RTYPE_VEC | 2}, \
2837 {"$v3", RTYPE_VEC | 3}, \
2838 {"$v4", RTYPE_VEC | 4}, \
2839 {"$v5", RTYPE_VEC | 5}, \
2840 {"$v6", RTYPE_VEC | 6}, \
2841 {"$v7", RTYPE_VEC | 7}, \
2842 {"$v8", RTYPE_VEC | 8}, \
2843 {"$v9", RTYPE_VEC | 9}, \
2844 {"$v10", RTYPE_VEC | 10}, \
2845 {"$v11", RTYPE_VEC | 11}, \
2846 {"$v12", RTYPE_VEC | 12}, \
2847 {"$v13", RTYPE_VEC | 13}, \
2848 {"$v14", RTYPE_VEC | 14}, \
2849 {"$v15", RTYPE_VEC | 15}, \
2850 {"$v16", RTYPE_VEC | 16}, \
2851 {"$v17", RTYPE_VEC | 17}, \
2852 {"$v18", RTYPE_VEC | 18}, \
2853 {"$v19", RTYPE_VEC | 19}, \
2854 {"$v20", RTYPE_VEC | 20}, \
2855 {"$v21", RTYPE_VEC | 21}, \
2856 {"$v22", RTYPE_VEC | 22}, \
2857 {"$v23", RTYPE_VEC | 23}, \
2858 {"$v24", RTYPE_VEC | 24}, \
2859 {"$v25", RTYPE_VEC | 25}, \
2860 {"$v26", RTYPE_VEC | 26}, \
2861 {"$v27", RTYPE_VEC | 27}, \
2862 {"$v28", RTYPE_VEC | 28}, \
2863 {"$v29", RTYPE_VEC | 29}, \
2864 {"$v30", RTYPE_VEC | 30}, \
2865 {"$v31", RTYPE_VEC | 31}
2867 #define R5900_I_NAMES \
2868 {"$I", RTYPE_R5900_I | 0}
2870 #define R5900_Q_NAMES \
2871 {"$Q", RTYPE_R5900_Q | 0}
2873 #define R5900_R_NAMES \
2874 {"$R", RTYPE_R5900_R | 0}
2876 #define R5900_ACC_NAMES \
2877 {"$ACC", RTYPE_R5900_ACC | 0 }
2879 #define MIPS_DSP_ACCUMULATOR_NAMES \
2880 {"$ac0", RTYPE_ACC | 0}, \
2881 {"$ac1", RTYPE_ACC | 1}, \
2882 {"$ac2", RTYPE_ACC | 2}, \
2883 {"$ac3", RTYPE_ACC | 3}
2885 static const struct regname reg_names
[] = {
2886 GENERIC_REGISTER_NUMBERS
,
2888 FPU_CONDITION_CODE_NAMES
,
2889 COPROC_CONDITION_CODE_NAMES
,
2891 /* The $txx registers depends on the abi,
2892 these will be added later into the symbol table from
2893 one of the tables below once mips_abi is set after
2894 parsing of arguments from the command line. */
2895 SYMBOLIC_REGISTER_NAMES
,
2897 MIPS16_SPECIAL_REGISTER_NAMES
,
2898 MDMX_VECTOR_REGISTER_NAMES
,
2903 MIPS_DSP_ACCUMULATOR_NAMES
,
2907 static const struct regname reg_names_o32
[] = {
2908 O32_SYMBOLIC_REGISTER_NAMES
,
2912 static const struct regname reg_names_n32n64
[] = {
2913 N32N64_SYMBOLIC_REGISTER_NAMES
,
2917 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2918 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2919 of these register symbols, return the associated vector register,
2920 otherwise return SYMVAL itself. */
2923 mips_prefer_vec_regno (unsigned int symval
)
2925 if ((symval
& -2) == (RTYPE_GP
| 2))
2926 return RTYPE_VEC
| (symval
& 1);
2930 /* Return true if string [S, E) is a valid register name, storing its
2931 symbol value in *SYMVAL_PTR if so. */
2934 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2939 /* Terminate name. */
2943 /* Look up the name. */
2944 symbol
= symbol_find (s
);
2947 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2950 *symval_ptr
= S_GET_VALUE (symbol
);
2954 /* Return true if the string at *SPTR is a valid register name. Allow it
2955 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2958 When returning true, move *SPTR past the register, store the
2959 register's symbol value in *SYMVAL_PTR and the channel mask in
2960 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2961 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2962 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2965 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2966 unsigned int *channels_ptr
)
2970 unsigned int channels
, symval
, bit
;
2972 /* Find end of name. */
2974 if (is_name_beginner (*e
))
2976 while (is_part_of_name (*e
))
2980 if (!mips_parse_register_1 (s
, e
, &symval
))
2985 /* Eat characters from the end of the string that are valid
2986 channel suffixes. The preceding register must be $ACC or
2987 end with a digit, so there is no ambiguity. */
2990 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2991 if (m
> s
&& m
[-1] == *q
)
2998 || !mips_parse_register_1 (s
, m
, &symval
)
2999 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3004 *symval_ptr
= symval
;
3006 *channels_ptr
= channels
;
3010 /* Check if SPTR points at a valid register specifier according to TYPES.
3011 If so, then return 1, advance S to consume the specifier and store
3012 the register's number in REGNOP, otherwise return 0. */
3015 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3019 if (mips_parse_register (s
, ®no
, NULL
))
3021 if (types
& RTYPE_VEC
)
3022 regno
= mips_prefer_vec_regno (regno
);
3031 as_warn (_("unrecognized register name `%s'"), *s
);
3036 return regno
<= RNUM_MASK
;
3039 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3040 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3043 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3048 for (i
= 0; i
< 4; i
++)
3049 if (*s
== "xyzw"[i
])
3051 *channels
|= 1 << (3 - i
);
3057 /* Token types for parsed operand lists. */
3058 enum mips_operand_token_type
{
3059 /* A plain register, e.g. $f2. */
3062 /* A 4-bit XYZW channel mask. */
3065 /* A constant vector index, e.g. [1]. */
3068 /* A register vector index, e.g. [$2]. */
3071 /* A continuous range of registers, e.g. $s0-$s4. */
3074 /* A (possibly relocated) expression. */
3077 /* A floating-point value. */
3080 /* A single character. This can be '(', ')' or ',', but '(' only appears
3084 /* A doubled character, either "--" or "++". */
3087 /* The end of the operand list. */
3091 /* A parsed operand token. */
3092 struct mips_operand_token
3094 /* The type of token. */
3095 enum mips_operand_token_type type
;
3098 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3101 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3102 unsigned int channels
;
3104 /* The integer value of an OT_INTEGER_INDEX. */
3107 /* The two register symbol values involved in an OT_REG_RANGE. */
3109 unsigned int regno1
;
3110 unsigned int regno2
;
3113 /* The value of an OT_INTEGER. The value is represented as an
3114 expression and the relocation operators that were applied to
3115 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3116 relocation operators were used. */
3119 bfd_reloc_code_real_type relocs
[3];
3122 /* The binary data for an OT_FLOAT constant, and the number of bytes
3125 unsigned char data
[8];
3129 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3134 /* An obstack used to construct lists of mips_operand_tokens. */
3135 static struct obstack mips_operand_tokens
;
3137 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3140 mips_add_token (struct mips_operand_token
*token
,
3141 enum mips_operand_token_type type
)
3144 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3147 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3148 and OT_REG tokens for them if so, and return a pointer to the first
3149 unconsumed character. Return null otherwise. */
3152 mips_parse_base_start (char *s
)
3154 struct mips_operand_token token
;
3155 unsigned int regno
, channels
;
3156 bfd_boolean decrement_p
;
3162 SKIP_SPACE_TABS (s
);
3164 /* Only match "--" as part of a base expression. In other contexts "--X"
3165 is a double negative. */
3166 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3170 SKIP_SPACE_TABS (s
);
3173 /* Allow a channel specifier because that leads to better error messages
3174 than treating something like "$vf0x++" as an expression. */
3175 if (!mips_parse_register (&s
, ®no
, &channels
))
3179 mips_add_token (&token
, OT_CHAR
);
3184 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3187 token
.u
.regno
= regno
;
3188 mips_add_token (&token
, OT_REG
);
3192 token
.u
.channels
= channels
;
3193 mips_add_token (&token
, OT_CHANNELS
);
3196 /* For consistency, only match "++" as part of base expressions too. */
3197 SKIP_SPACE_TABS (s
);
3198 if (s
[0] == '+' && s
[1] == '+')
3202 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3208 /* Parse one or more tokens from S. Return a pointer to the first
3209 unconsumed character on success. Return null if an error was found
3210 and store the error text in insn_error. FLOAT_FORMAT is as for
3211 mips_parse_arguments. */
3214 mips_parse_argument_token (char *s
, char float_format
)
3216 char *end
, *save_in
;
3218 unsigned int regno1
, regno2
, channels
;
3219 struct mips_operand_token token
;
3221 /* First look for "($reg", since we want to treat that as an
3222 OT_CHAR and OT_REG rather than an expression. */
3223 end
= mips_parse_base_start (s
);
3227 /* Handle other characters that end up as OT_CHARs. */
3228 if (*s
== ')' || *s
== ',')
3231 mips_add_token (&token
, OT_CHAR
);
3236 /* Handle tokens that start with a register. */
3237 if (mips_parse_register (&s
, ®no1
, &channels
))
3241 /* A register and a VU0 channel suffix. */
3242 token
.u
.regno
= regno1
;
3243 mips_add_token (&token
, OT_REG
);
3245 token
.u
.channels
= channels
;
3246 mips_add_token (&token
, OT_CHANNELS
);
3250 SKIP_SPACE_TABS (s
);
3253 /* A register range. */
3255 SKIP_SPACE_TABS (s
);
3256 if (!mips_parse_register (&s
, ®no2
, NULL
))
3258 set_insn_error (0, _("invalid register range"));
3262 token
.u
.reg_range
.regno1
= regno1
;
3263 token
.u
.reg_range
.regno2
= regno2
;
3264 mips_add_token (&token
, OT_REG_RANGE
);
3268 /* Add the register itself. */
3269 token
.u
.regno
= regno1
;
3270 mips_add_token (&token
, OT_REG
);
3272 /* Check for a vector index. */
3276 SKIP_SPACE_TABS (s
);
3277 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3278 mips_add_token (&token
, OT_REG_INDEX
);
3281 expressionS element
;
3283 my_getExpression (&element
, s
);
3284 if (element
.X_op
!= O_constant
)
3286 set_insn_error (0, _("vector element must be constant"));
3290 token
.u
.index
= element
.X_add_number
;
3291 mips_add_token (&token
, OT_INTEGER_INDEX
);
3293 SKIP_SPACE_TABS (s
);
3296 set_insn_error (0, _("missing `]'"));
3306 /* First try to treat expressions as floats. */
3307 save_in
= input_line_pointer
;
3308 input_line_pointer
= s
;
3309 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3310 &token
.u
.flt
.length
);
3311 end
= input_line_pointer
;
3312 input_line_pointer
= save_in
;
3315 set_insn_error (0, err
);
3320 mips_add_token (&token
, OT_FLOAT
);
3325 /* Treat everything else as an integer expression. */
3326 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3327 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3328 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3329 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3331 mips_add_token (&token
, OT_INTEGER
);
3335 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3336 if expressions should be treated as 32-bit floating-point constants,
3337 'd' if they should be treated as 64-bit floating-point constants,
3338 or 0 if they should be treated as integer expressions (the usual case).
3340 Return a list of tokens on success, otherwise return 0. The caller
3341 must obstack_free the list after use. */
3343 static struct mips_operand_token
*
3344 mips_parse_arguments (char *s
, char float_format
)
3346 struct mips_operand_token token
;
3348 SKIP_SPACE_TABS (s
);
3351 s
= mips_parse_argument_token (s
, float_format
);
3354 obstack_free (&mips_operand_tokens
,
3355 obstack_finish (&mips_operand_tokens
));
3358 SKIP_SPACE_TABS (s
);
3360 mips_add_token (&token
, OT_END
);
3361 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3364 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3365 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3368 is_opcode_valid (const struct mips_opcode
*mo
)
3370 int isa
= mips_opts
.isa
;
3371 int ase
= mips_opts
.ase
;
3375 if (ISA_HAS_64BIT_REGS (isa
))
3376 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3377 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3378 ase
|= mips_ases
[i
].flags64
;
3380 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3383 /* Check whether the instruction or macro requires single-precision or
3384 double-precision floating-point support. Note that this information is
3385 stored differently in the opcode table for insns and macros. */
3386 if (mo
->pinfo
== INSN_MACRO
)
3388 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3389 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3393 fp_s
= mo
->pinfo
& FP_S
;
3394 fp_d
= mo
->pinfo
& FP_D
;
3397 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3400 if (fp_s
&& mips_opts
.soft_float
)
3406 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3407 selected ISA and architecture. */
3410 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3412 int isa
= mips_opts
.isa
;
3413 int ase
= mips_opts
.ase
;
3416 if (ISA_HAS_64BIT_REGS (isa
))
3417 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3418 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3419 ase
|= mips_ases
[i
].flags64
;
3421 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3424 /* Return TRUE if the size of the microMIPS opcode MO matches one
3425 explicitly requested. Always TRUE in the standard MIPS mode.
3426 Use is_size_valid_16 for MIPS16 opcodes. */
3429 is_size_valid (const struct mips_opcode
*mo
)
3431 if (!mips_opts
.micromips
)
3434 if (mips_opts
.insn32
)
3436 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3438 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3441 if (!forced_insn_length
)
3443 if (mo
->pinfo
== INSN_MACRO
)
3445 return forced_insn_length
== micromips_insn_length (mo
);
3448 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3449 explicitly requested. */
3452 is_size_valid_16 (const struct mips_opcode
*mo
)
3454 if (!forced_insn_length
)
3456 if (mo
->pinfo
== INSN_MACRO
)
3458 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3460 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3465 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3466 of the preceding instruction. Always TRUE in the standard MIPS mode.
3468 We don't accept macros in 16-bit delay slots to avoid a case where
3469 a macro expansion fails because it relies on a preceding 32-bit real
3470 instruction to have matched and does not handle the operands correctly.
3471 The only macros that may expand to 16-bit instructions are JAL that
3472 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3473 and BGT (that likewise cannot be placed in a delay slot) that decay to
3474 a NOP. In all these cases the macros precede any corresponding real
3475 instruction definitions in the opcode table, so they will match in the
3476 second pass where the size of the delay slot is ignored and therefore
3477 produce correct code. */
3480 is_delay_slot_valid (const struct mips_opcode
*mo
)
3482 if (!mips_opts
.micromips
)
3485 if (mo
->pinfo
== INSN_MACRO
)
3486 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3487 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3488 && micromips_insn_length (mo
) != 4)
3490 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3491 && micromips_insn_length (mo
) != 2)
3497 /* For consistency checking, verify that all bits of OPCODE are specified
3498 either by the match/mask part of the instruction definition, or by the
3499 operand list. Also build up a list of operands in OPERANDS.
3501 INSN_BITS says which bits of the instruction are significant.
3502 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3503 provides the mips_operand description of each operand. DECODE_OPERAND
3504 is null for MIPS16 instructions. */
3507 validate_mips_insn (const struct mips_opcode
*opcode
,
3508 unsigned long insn_bits
,
3509 const struct mips_operand
*(*decode_operand
) (const char *),
3510 struct mips_operand_array
*operands
)
3513 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3514 const struct mips_operand
*operand
;
3516 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3517 if ((mask
& opcode
->match
) != opcode
->match
)
3519 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3520 opcode
->name
, opcode
->args
);
3525 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3526 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3527 for (s
= opcode
->args
; *s
; ++s
)
3540 if (!decode_operand
)
3541 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3543 operand
= decode_operand (s
);
3544 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3546 as_bad (_("internal: unknown operand type: %s %s"),
3547 opcode
->name
, opcode
->args
);
3550 gas_assert (opno
< MAX_OPERANDS
);
3551 operands
->operand
[opno
] = operand
;
3552 if (!decode_operand
&& operand
3553 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3554 && mips_opcode_32bit_p (opcode
))
3555 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3556 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3558 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3559 if (operand
->type
== OP_MDMX_IMM_REG
)
3560 /* Bit 5 is the format selector (OB vs QH). The opcode table
3561 has separate entries for each format. */
3562 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3563 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3564 used_bits
&= ~(mask
& 0x700);
3565 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3566 operand field that cannot be fully described with LSB/SIZE. */
3567 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3568 used_bits
&= ~0x6000;
3570 /* Skip prefix characters. */
3571 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3576 doubled
= used_bits
& mask
& insn_bits
;
3579 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3580 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3584 undefined
= ~used_bits
& insn_bits
;
3585 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3587 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3588 undefined
, opcode
->name
, opcode
->args
);
3591 used_bits
&= ~insn_bits
;
3594 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3595 used_bits
, opcode
->name
, opcode
->args
);
3601 /* The MIPS16 version of validate_mips_insn. */
3604 validate_mips16_insn (const struct mips_opcode
*opcode
,
3605 struct mips_operand_array
*operands
)
3607 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3609 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3612 /* The microMIPS version of validate_mips_insn. */
3615 validate_micromips_insn (const struct mips_opcode
*opc
,
3616 struct mips_operand_array
*operands
)
3618 unsigned long insn_bits
;
3619 unsigned long major
;
3620 unsigned int length
;
3622 if (opc
->pinfo
== INSN_MACRO
)
3623 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3626 length
= micromips_insn_length (opc
);
3627 if (length
!= 2 && length
!= 4)
3629 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3630 "%s %s"), length
, opc
->name
, opc
->args
);
3633 major
= opc
->match
>> (10 + 8 * (length
- 2));
3634 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3635 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3637 as_bad (_("internal error: bad microMIPS opcode "
3638 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3642 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3643 insn_bits
= 1 << 4 * length
;
3644 insn_bits
<<= 4 * length
;
3646 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3650 /* This function is called once, at assembler startup time. It should set up
3651 all the tables, etc. that the MD part of the assembler will need. */
3656 const char *retval
= NULL
;
3660 if (mips_pic
!= NO_PIC
)
3662 if (g_switch_seen
&& g_switch_value
!= 0)
3663 as_bad (_("-G may not be used in position-independent code"));
3666 else if (mips_abicalls
)
3668 if (g_switch_seen
&& g_switch_value
!= 0)
3669 as_bad (_("-G may not be used with abicalls"));
3673 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3674 as_warn (_("could not set architecture and machine"));
3676 op_hash
= hash_new ();
3678 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3679 for (i
= 0; i
< NUMOPCODES
;)
3681 const char *name
= mips_opcodes
[i
].name
;
3683 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3686 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3687 mips_opcodes
[i
].name
, retval
);
3688 /* Probably a memory allocation problem? Give up now. */
3689 as_fatal (_("broken assembler, no assembly attempted"));
3693 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3694 decode_mips_operand
, &mips_operands
[i
]))
3697 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3699 create_insn (&nop_insn
, mips_opcodes
+ i
);
3700 if (mips_fix_loongson2f_nop
)
3701 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3702 nop_insn
.fixed_p
= 1;
3705 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3706 create_insn (&sync_insn
, mips_opcodes
+ i
);
3710 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3713 mips16_op_hash
= hash_new ();
3714 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3715 bfd_mips16_num_opcodes
);
3718 while (i
< bfd_mips16_num_opcodes
)
3720 const char *name
= mips16_opcodes
[i
].name
;
3722 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3724 as_fatal (_("internal: can't hash `%s': %s"),
3725 mips16_opcodes
[i
].name
, retval
);
3728 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3730 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3732 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3733 mips16_nop_insn
.fixed_p
= 1;
3737 while (i
< bfd_mips16_num_opcodes
3738 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3741 micromips_op_hash
= hash_new ();
3742 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3743 bfd_micromips_num_opcodes
);
3746 while (i
< bfd_micromips_num_opcodes
)
3748 const char *name
= micromips_opcodes
[i
].name
;
3750 retval
= hash_insert (micromips_op_hash
, name
,
3751 (void *) µmips_opcodes
[i
]);
3753 as_fatal (_("internal: can't hash `%s': %s"),
3754 micromips_opcodes
[i
].name
, retval
);
3757 struct mips_cl_insn
*micromips_nop_insn
;
3759 if (!validate_micromips_insn (µmips_opcodes
[i
],
3760 µmips_operands
[i
]))
3763 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3765 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3766 micromips_nop_insn
= µmips_nop16_insn
;
3767 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3768 micromips_nop_insn
= µmips_nop32_insn
;
3772 if (micromips_nop_insn
->insn_mo
== NULL
3773 && strcmp (name
, "nop") == 0)
3775 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3776 micromips_nop_insn
->fixed_p
= 1;
3780 while (++i
< bfd_micromips_num_opcodes
3781 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3785 as_fatal (_("broken assembler, no assembly attempted"));
3787 /* We add all the general register names to the symbol table. This
3788 helps us detect invalid uses of them. */
3789 for (i
= 0; reg_names
[i
].name
; i
++)
3790 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3791 reg_names
[i
].num
, /* & RNUM_MASK, */
3792 &zero_address_frag
));
3794 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3795 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3796 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3797 &zero_address_frag
));
3799 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3800 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3801 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3802 &zero_address_frag
));
3804 for (i
= 0; i
< 32; i
++)
3808 /* R5900 VU0 floating-point register. */
3809 sprintf (regname
, "$vf%d", i
);
3810 symbol_table_insert (symbol_new (regname
, reg_section
,
3811 RTYPE_VF
| i
, &zero_address_frag
));
3813 /* R5900 VU0 integer register. */
3814 sprintf (regname
, "$vi%d", i
);
3815 symbol_table_insert (symbol_new (regname
, reg_section
,
3816 RTYPE_VI
| i
, &zero_address_frag
));
3819 sprintf (regname
, "$w%d", i
);
3820 symbol_table_insert (symbol_new (regname
, reg_section
,
3821 RTYPE_MSA
| i
, &zero_address_frag
));
3824 obstack_init (&mips_operand_tokens
);
3826 mips_no_prev_insn ();
3829 mips_cprmask
[0] = 0;
3830 mips_cprmask
[1] = 0;
3831 mips_cprmask
[2] = 0;
3832 mips_cprmask
[3] = 0;
3834 /* set the default alignment for the text section (2**2) */
3835 record_alignment (text_section
, 2);
3837 bfd_set_gp_size (stdoutput
, g_switch_value
);
3839 /* On a native system other than VxWorks, sections must be aligned
3840 to 16 byte boundaries. When configured for an embedded ELF
3841 target, we don't bother. */
3842 if (strncmp (TARGET_OS
, "elf", 3) != 0
3843 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3845 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3846 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3847 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3850 /* Create a .reginfo section for register masks and a .mdebug
3851 section for debugging information. */
3859 subseg
= now_subseg
;
3861 /* The ABI says this section should be loaded so that the
3862 running program can access it. However, we don't load it
3863 if we are configured for an embedded target. */
3864 flags
= SEC_READONLY
| SEC_DATA
;
3865 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3866 flags
|= SEC_ALLOC
| SEC_LOAD
;
3868 if (mips_abi
!= N64_ABI
)
3870 sec
= subseg_new (".reginfo", (subsegT
) 0);
3872 bfd_set_section_flags (stdoutput
, sec
, flags
);
3873 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3875 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3879 /* The 64-bit ABI uses a .MIPS.options section rather than
3880 .reginfo section. */
3881 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3882 bfd_set_section_flags (stdoutput
, sec
, flags
);
3883 bfd_set_section_alignment (stdoutput
, sec
, 3);
3885 /* Set up the option header. */
3887 Elf_Internal_Options opthdr
;
3890 opthdr
.kind
= ODK_REGINFO
;
3891 opthdr
.size
= (sizeof (Elf_External_Options
)
3892 + sizeof (Elf64_External_RegInfo
));
3895 f
= frag_more (sizeof (Elf_External_Options
));
3896 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3897 (Elf_External_Options
*) f
);
3899 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3903 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3904 bfd_set_section_flags (stdoutput
, sec
,
3905 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3906 bfd_set_section_alignment (stdoutput
, sec
, 3);
3907 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3909 if (ECOFF_DEBUGGING
)
3911 sec
= subseg_new (".mdebug", (subsegT
) 0);
3912 (void) bfd_set_section_flags (stdoutput
, sec
,
3913 SEC_HAS_CONTENTS
| SEC_READONLY
);
3914 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3916 else if (mips_flag_pdr
)
3918 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3919 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3920 SEC_READONLY
| SEC_RELOC
3922 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3925 subseg_set (seg
, subseg
);
3928 if (mips_fix_vr4120
)
3929 init_vr4120_conflicts ();
3933 fpabi_incompatible_with (int fpabi
, const char *what
)
3935 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3936 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3940 fpabi_requires (int fpabi
, const char *what
)
3942 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3943 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3946 /* Check -mabi and register sizes against the specified FP ABI. */
3948 check_fpabi (int fpabi
)
3952 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3953 if (file_mips_opts
.soft_float
)
3954 fpabi_incompatible_with (fpabi
, "softfloat");
3955 else if (file_mips_opts
.single_float
)
3956 fpabi_incompatible_with (fpabi
, "singlefloat");
3957 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3958 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3959 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3960 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3963 case Val_GNU_MIPS_ABI_FP_XX
:
3964 if (mips_abi
!= O32_ABI
)
3965 fpabi_requires (fpabi
, "-mabi=32");
3966 else if (file_mips_opts
.soft_float
)
3967 fpabi_incompatible_with (fpabi
, "softfloat");
3968 else if (file_mips_opts
.single_float
)
3969 fpabi_incompatible_with (fpabi
, "singlefloat");
3970 else if (file_mips_opts
.fp
!= 0)
3971 fpabi_requires (fpabi
, "fp=xx");
3974 case Val_GNU_MIPS_ABI_FP_64A
:
3975 case Val_GNU_MIPS_ABI_FP_64
:
3976 if (mips_abi
!= O32_ABI
)
3977 fpabi_requires (fpabi
, "-mabi=32");
3978 else if (file_mips_opts
.soft_float
)
3979 fpabi_incompatible_with (fpabi
, "softfloat");
3980 else if (file_mips_opts
.single_float
)
3981 fpabi_incompatible_with (fpabi
, "singlefloat");
3982 else if (file_mips_opts
.fp
!= 64)
3983 fpabi_requires (fpabi
, "fp=64");
3984 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3985 fpabi_incompatible_with (fpabi
, "nooddspreg");
3986 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3987 fpabi_requires (fpabi
, "nooddspreg");
3990 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3991 if (file_mips_opts
.soft_float
)
3992 fpabi_incompatible_with (fpabi
, "softfloat");
3993 else if (!file_mips_opts
.single_float
)
3994 fpabi_requires (fpabi
, "singlefloat");
3997 case Val_GNU_MIPS_ABI_FP_SOFT
:
3998 if (!file_mips_opts
.soft_float
)
3999 fpabi_requires (fpabi
, "softfloat");
4002 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4003 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4004 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4007 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4008 /* Silently ignore compatibility value. */
4012 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4013 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4018 /* Perform consistency checks on the current options. */
4021 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4023 /* Check the size of integer registers agrees with the ABI and ISA. */
4024 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4025 as_bad (_("`gp=64' used with a 32-bit processor"));
4027 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4028 as_bad (_("`gp=32' used with a 64-bit ABI"));
4030 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4031 as_bad (_("`gp=64' used with a 32-bit ABI"));
4033 /* Check the size of the float registers agrees with the ABI and ISA. */
4037 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4038 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4039 else if (opts
->single_float
== 1)
4040 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4043 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4044 as_bad (_("`fp=64' used with a 32-bit fpu"));
4046 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4047 && !ISA_HAS_MXHC1 (opts
->isa
))
4048 as_warn (_("`fp=64' used with a 32-bit ABI"));
4052 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4053 as_warn (_("`fp=32' used with a 64-bit ABI"));
4054 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4055 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4058 as_bad (_("Unknown size of floating point registers"));
4062 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4063 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4065 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4066 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4067 else if (ISA_IS_R6 (opts
->isa
)
4068 && (opts
->micromips
== 1
4069 || opts
->mips16
== 1))
4070 as_fatal (_("`%s' cannot be used with `%s'"),
4071 opts
->micromips
? "micromips" : "mips16",
4072 mips_cpu_info_from_isa (opts
->isa
)->name
);
4074 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4075 as_fatal (_("branch relaxation is not supported in `%s'"),
4076 mips_cpu_info_from_isa (opts
->isa
)->name
);
4079 /* Perform consistency checks on the module level options exactly once.
4080 This is a deferred check that happens:
4081 at the first .set directive
4082 or, at the first pseudo op that generates code (inc .dc.a)
4083 or, at the first instruction
4087 file_mips_check_options (void)
4089 const struct mips_cpu_info
*arch_info
= 0;
4091 if (file_mips_opts_checked
)
4094 /* The following code determines the register size.
4095 Similar code was added to GCC 3.3 (see override_options() in
4096 config/mips/mips.c). The GAS and GCC code should be kept in sync
4097 as much as possible. */
4099 if (file_mips_opts
.gp
< 0)
4101 /* Infer the integer register size from the ABI and processor.
4102 Restrict ourselves to 32-bit registers if that's all the
4103 processor has, or if the ABI cannot handle 64-bit registers. */
4104 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4105 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4109 if (file_mips_opts
.fp
< 0)
4111 /* No user specified float register size.
4112 ??? GAS treats single-float processors as though they had 64-bit
4113 float registers (although it complains when double-precision
4114 instructions are used). As things stand, saying they have 32-bit
4115 registers would lead to spurious "register must be even" messages.
4116 So here we assume float registers are never smaller than the
4118 if (file_mips_opts
.gp
== 64)
4119 /* 64-bit integer registers implies 64-bit float registers. */
4120 file_mips_opts
.fp
= 64;
4121 else if ((file_mips_opts
.ase
& FP64_ASES
)
4122 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4123 /* Handle ASEs that require 64-bit float registers, if possible. */
4124 file_mips_opts
.fp
= 64;
4125 else if (ISA_IS_R6 (mips_opts
.isa
))
4126 /* R6 implies 64-bit float registers. */
4127 file_mips_opts
.fp
= 64;
4129 /* 32-bit float registers. */
4130 file_mips_opts
.fp
= 32;
4133 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4135 /* Disable operations on odd-numbered floating-point registers by default
4136 when using the FPXX ABI. */
4137 if (file_mips_opts
.oddspreg
< 0)
4139 if (file_mips_opts
.fp
== 0)
4140 file_mips_opts
.oddspreg
= 0;
4142 file_mips_opts
.oddspreg
= 1;
4145 /* End of GCC-shared inference code. */
4147 /* This flag is set when we have a 64-bit capable CPU but use only
4148 32-bit wide registers. Note that EABI does not use it. */
4149 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4150 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4151 || mips_abi
== O32_ABI
))
4154 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4155 as_bad (_("trap exception not supported at ISA 1"));
4157 /* If the selected architecture includes support for ASEs, enable
4158 generation of code for them. */
4159 if (file_mips_opts
.mips16
== -1)
4160 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4161 if (file_mips_opts
.micromips
== -1)
4162 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4165 if (mips_nan2008
== -1)
4166 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4167 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4168 as_fatal (_("`%s' does not support legacy NaN"),
4169 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4171 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4172 being selected implicitly. */
4173 if (file_mips_opts
.fp
!= 64)
4174 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4176 /* If the user didn't explicitly select or deselect a particular ASE,
4177 use the default setting for the CPU. */
4178 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4180 /* Set up the current options. These may change throughout assembly. */
4181 mips_opts
= file_mips_opts
;
4183 mips_check_isa_supports_ases ();
4184 mips_check_options (&file_mips_opts
, TRUE
);
4185 file_mips_opts_checked
= TRUE
;
4187 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4188 as_warn (_("could not set architecture and machine"));
4192 md_assemble (char *str
)
4194 struct mips_cl_insn insn
;
4195 bfd_reloc_code_real_type unused_reloc
[3]
4196 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4198 file_mips_check_options ();
4200 imm_expr
.X_op
= O_absent
;
4201 offset_expr
.X_op
= O_absent
;
4202 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4203 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4204 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4206 mips_mark_labels ();
4207 mips_assembling_insn
= TRUE
;
4208 clear_insn_error ();
4210 if (mips_opts
.mips16
)
4211 mips16_ip (str
, &insn
);
4214 mips_ip (str
, &insn
);
4215 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4216 str
, insn
.insn_opcode
));
4220 report_insn_error (str
);
4221 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4224 if (mips_opts
.mips16
)
4225 mips16_macro (&insn
);
4232 if (offset_expr
.X_op
!= O_absent
)
4233 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4235 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4238 mips_assembling_insn
= FALSE
;
4241 /* Convenience functions for abstracting away the differences between
4242 MIPS16 and non-MIPS16 relocations. */
4244 static inline bfd_boolean
4245 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4249 case BFD_RELOC_MIPS16_JMP
:
4250 case BFD_RELOC_MIPS16_GPREL
:
4251 case BFD_RELOC_MIPS16_GOT16
:
4252 case BFD_RELOC_MIPS16_CALL16
:
4253 case BFD_RELOC_MIPS16_HI16_S
:
4254 case BFD_RELOC_MIPS16_HI16
:
4255 case BFD_RELOC_MIPS16_LO16
:
4256 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4264 static inline bfd_boolean
4265 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4269 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4270 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4271 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4272 case BFD_RELOC_MICROMIPS_GPREL16
:
4273 case BFD_RELOC_MICROMIPS_JMP
:
4274 case BFD_RELOC_MICROMIPS_HI16
:
4275 case BFD_RELOC_MICROMIPS_HI16_S
:
4276 case BFD_RELOC_MICROMIPS_LO16
:
4277 case BFD_RELOC_MICROMIPS_LITERAL
:
4278 case BFD_RELOC_MICROMIPS_GOT16
:
4279 case BFD_RELOC_MICROMIPS_CALL16
:
4280 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4281 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4282 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4283 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4284 case BFD_RELOC_MICROMIPS_SUB
:
4285 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4286 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4287 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4288 case BFD_RELOC_MICROMIPS_HIGHEST
:
4289 case BFD_RELOC_MICROMIPS_HIGHER
:
4290 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4291 case BFD_RELOC_MICROMIPS_JALR
:
4299 static inline bfd_boolean
4300 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4302 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4305 static inline bfd_boolean
4306 b_reloc_p (bfd_reloc_code_real_type reloc
)
4308 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4309 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4310 || reloc
== BFD_RELOC_16_PCREL_S2
4311 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4312 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4313 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4314 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4317 static inline bfd_boolean
4318 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4320 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4321 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4324 static inline bfd_boolean
4325 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4327 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4328 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4331 static inline bfd_boolean
4332 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4334 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4335 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4338 static inline bfd_boolean
4339 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4341 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4344 static inline bfd_boolean
4345 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4347 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4348 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4351 /* Return true if RELOC is a PC-relative relocation that does not have
4352 full address range. */
4354 static inline bfd_boolean
4355 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4359 case BFD_RELOC_16_PCREL_S2
:
4360 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4361 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4362 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4363 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4364 case BFD_RELOC_MIPS_21_PCREL_S2
:
4365 case BFD_RELOC_MIPS_26_PCREL_S2
:
4366 case BFD_RELOC_MIPS_18_PCREL_S3
:
4367 case BFD_RELOC_MIPS_19_PCREL_S2
:
4370 case BFD_RELOC_32_PCREL
:
4371 case BFD_RELOC_HI16_S_PCREL
:
4372 case BFD_RELOC_LO16_PCREL
:
4373 return HAVE_64BIT_ADDRESSES
;
4380 /* Return true if the given relocation might need a matching %lo().
4381 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4382 need a matching %lo() when applied to local symbols. */
4384 static inline bfd_boolean
4385 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4387 return (HAVE_IN_PLACE_ADDENDS
4388 && (hi16_reloc_p (reloc
)
4389 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4390 all GOT16 relocations evaluate to "G". */
4391 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4394 /* Return the type of %lo() reloc needed by RELOC, given that
4395 reloc_needs_lo_p. */
4397 static inline bfd_reloc_code_real_type
4398 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4400 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4401 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4405 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4408 static inline bfd_boolean
4409 fixup_has_matching_lo_p (fixS
*fixp
)
4411 return (fixp
->fx_next
!= NULL
4412 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4413 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4414 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4417 /* Move all labels in LABELS to the current insertion point. TEXT_P
4418 says whether the labels refer to text or data. */
4421 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4423 struct insn_label_list
*l
;
4426 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4428 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4429 symbol_set_frag (l
->label
, frag_now
);
4430 val
= (valueT
) frag_now_fix ();
4431 /* MIPS16/microMIPS text labels are stored as odd. */
4432 if (text_p
&& HAVE_CODE_COMPRESSION
)
4434 S_SET_VALUE (l
->label
, val
);
4438 /* Move all labels in insn_labels to the current insertion point
4439 and treat them as text labels. */
4442 mips_move_text_labels (void)
4444 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4447 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4450 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4452 bfd_boolean linkonce
= FALSE
;
4453 segT symseg
= S_GET_SEGMENT (sym
);
4455 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4457 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4459 /* The GNU toolchain uses an extension for ELF: a section
4460 beginning with the magic string .gnu.linkonce is a
4461 linkonce section. */
4462 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4463 sizeof ".gnu.linkonce" - 1) == 0)
4469 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4470 linker to handle them specially, such as generating jalx instructions
4471 when needed. We also make them odd for the duration of the assembly,
4472 in order to generate the right sort of code. We will make them even
4473 in the adjust_symtab routine, while leaving them marked. This is
4474 convenient for the debugger and the disassembler. The linker knows
4475 to make them odd again. */
4478 mips_compressed_mark_label (symbolS
*label
)
4480 gas_assert (HAVE_CODE_COMPRESSION
);
4482 if (mips_opts
.mips16
)
4483 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4485 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4486 if ((S_GET_VALUE (label
) & 1) == 0
4487 /* Don't adjust the address if the label is global or weak, or
4488 in a link-once section, since we'll be emitting symbol reloc
4489 references to it which will be patched up by the linker, and
4490 the final value of the symbol may or may not be MIPS16/microMIPS. */
4491 && !S_IS_WEAK (label
)
4492 && !S_IS_EXTERNAL (label
)
4493 && !s_is_linkonce (label
, now_seg
))
4494 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4497 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4500 mips_compressed_mark_labels (void)
4502 struct insn_label_list
*l
;
4504 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4505 mips_compressed_mark_label (l
->label
);
4508 /* End the current frag. Make it a variant frag and record the
4512 relax_close_frag (void)
4514 mips_macro_warning
.first_frag
= frag_now
;
4515 frag_var (rs_machine_dependent
, 0, 0,
4516 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4517 mips_pic
!= NO_PIC
),
4518 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4520 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4521 mips_relax
.first_fixup
= 0;
4524 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4525 See the comment above RELAX_ENCODE for more details. */
4528 relax_start (symbolS
*symbol
)
4530 gas_assert (mips_relax
.sequence
== 0);
4531 mips_relax
.sequence
= 1;
4532 mips_relax
.symbol
= symbol
;
4535 /* Start generating the second version of a relaxable sequence.
4536 See the comment above RELAX_ENCODE for more details. */
4541 gas_assert (mips_relax
.sequence
== 1);
4542 mips_relax
.sequence
= 2;
4545 /* End the current relaxable sequence. */
4550 gas_assert (mips_relax
.sequence
== 2);
4551 relax_close_frag ();
4552 mips_relax
.sequence
= 0;
4555 /* Return true if IP is a delayed branch or jump. */
4557 static inline bfd_boolean
4558 delayed_branch_p (const struct mips_cl_insn
*ip
)
4560 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4561 | INSN_COND_BRANCH_DELAY
4562 | INSN_COND_BRANCH_LIKELY
)) != 0;
4565 /* Return true if IP is a compact branch or jump. */
4567 static inline bfd_boolean
4568 compact_branch_p (const struct mips_cl_insn
*ip
)
4570 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4571 | INSN2_COND_BRANCH
)) != 0;
4574 /* Return true if IP is an unconditional branch or jump. */
4576 static inline bfd_boolean
4577 uncond_branch_p (const struct mips_cl_insn
*ip
)
4579 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4580 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4583 /* Return true if IP is a branch-likely instruction. */
4585 static inline bfd_boolean
4586 branch_likely_p (const struct mips_cl_insn
*ip
)
4588 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4591 /* Return the type of nop that should be used to fill the delay slot
4592 of delayed branch IP. */
4594 static struct mips_cl_insn
*
4595 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4597 if (mips_opts
.micromips
4598 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4599 return µmips_nop32_insn
;
4603 /* Return a mask that has bit N set if OPCODE reads the register(s)
4607 insn_read_mask (const struct mips_opcode
*opcode
)
4609 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4612 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4616 insn_write_mask (const struct mips_opcode
*opcode
)
4618 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4621 /* Return a mask of the registers specified by operand OPERAND of INSN.
4622 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4626 operand_reg_mask (const struct mips_cl_insn
*insn
,
4627 const struct mips_operand
*operand
,
4628 unsigned int type_mask
)
4630 unsigned int uval
, vsel
;
4632 switch (operand
->type
)
4639 case OP_ADDIUSP_INT
:
4640 case OP_ENTRY_EXIT_LIST
:
4641 case OP_REPEAT_DEST_REG
:
4642 case OP_REPEAT_PREV_REG
:
4645 case OP_VU0_MATCH_SUFFIX
:
4653 case OP_OPTIONAL_REG
:
4655 const struct mips_reg_operand
*reg_op
;
4657 reg_op
= (const struct mips_reg_operand
*) operand
;
4658 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4660 uval
= insn_extract_operand (insn
, operand
);
4661 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4666 const struct mips_reg_pair_operand
*pair_op
;
4668 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4669 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4671 uval
= insn_extract_operand (insn
, operand
);
4672 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4675 case OP_CLO_CLZ_DEST
:
4676 if (!(type_mask
& (1 << OP_REG_GP
)))
4678 uval
= insn_extract_operand (insn
, operand
);
4679 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4682 if (!(type_mask
& (1 << OP_REG_GP
)))
4684 uval
= insn_extract_operand (insn
, operand
);
4685 gas_assert ((uval
& 31) == (uval
>> 5));
4686 return 1 << (uval
& 31);
4689 case OP_NON_ZERO_REG
:
4690 if (!(type_mask
& (1 << OP_REG_GP
)))
4692 uval
= insn_extract_operand (insn
, operand
);
4693 return 1 << (uval
& 31);
4695 case OP_LWM_SWM_LIST
:
4698 case OP_SAVE_RESTORE_LIST
:
4701 case OP_MDMX_IMM_REG
:
4702 if (!(type_mask
& (1 << OP_REG_VEC
)))
4704 uval
= insn_extract_operand (insn
, operand
);
4706 if ((vsel
& 0x18) == 0x18)
4708 return 1 << (uval
& 31);
4711 if (!(type_mask
& (1 << OP_REG_GP
)))
4713 return 1 << insn_extract_operand (insn
, operand
);
4718 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4719 where bit N of OPNO_MASK is set if operand N should be included.
4720 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4724 insn_reg_mask (const struct mips_cl_insn
*insn
,
4725 unsigned int type_mask
, unsigned int opno_mask
)
4727 unsigned int opno
, reg_mask
;
4731 while (opno_mask
!= 0)
4734 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4741 /* Return the mask of core registers that IP reads. */
4744 gpr_read_mask (const struct mips_cl_insn
*ip
)
4746 unsigned long pinfo
, pinfo2
;
4749 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4750 pinfo
= ip
->insn_mo
->pinfo
;
4751 pinfo2
= ip
->insn_mo
->pinfo2
;
4752 if (pinfo
& INSN_UDI
)
4754 /* UDI instructions have traditionally been assumed to read RS
4756 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4757 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4759 if (pinfo
& INSN_READ_GPR_24
)
4761 if (pinfo2
& INSN2_READ_GPR_16
)
4763 if (pinfo2
& INSN2_READ_SP
)
4765 if (pinfo2
& INSN2_READ_GPR_31
)
4767 /* Don't include register 0. */
4771 /* Return the mask of core registers that IP writes. */
4774 gpr_write_mask (const struct mips_cl_insn
*ip
)
4776 unsigned long pinfo
, pinfo2
;
4779 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4780 pinfo
= ip
->insn_mo
->pinfo
;
4781 pinfo2
= ip
->insn_mo
->pinfo2
;
4782 if (pinfo
& INSN_WRITE_GPR_24
)
4784 if (pinfo
& INSN_WRITE_GPR_31
)
4786 if (pinfo
& INSN_UDI
)
4787 /* UDI instructions have traditionally been assumed to write to RD. */
4788 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4789 if (pinfo2
& INSN2_WRITE_SP
)
4791 /* Don't include register 0. */
4795 /* Return the mask of floating-point registers that IP reads. */
4798 fpr_read_mask (const struct mips_cl_insn
*ip
)
4800 unsigned long pinfo
;
4803 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4804 | (1 << OP_REG_MSA
)),
4805 insn_read_mask (ip
->insn_mo
));
4806 pinfo
= ip
->insn_mo
->pinfo
;
4807 /* Conservatively treat all operands to an FP_D instruction are doubles.
4808 (This is overly pessimistic for things like cvt.d.s.) */
4809 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4814 /* Return the mask of floating-point registers that IP writes. */
4817 fpr_write_mask (const struct mips_cl_insn
*ip
)
4819 unsigned long pinfo
;
4822 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4823 | (1 << OP_REG_MSA
)),
4824 insn_write_mask (ip
->insn_mo
));
4825 pinfo
= ip
->insn_mo
->pinfo
;
4826 /* Conservatively treat all operands to an FP_D instruction are doubles.
4827 (This is overly pessimistic for things like cvt.s.d.) */
4828 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4833 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4834 Check whether that is allowed. */
4837 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4839 const char *s
= insn
->name
;
4840 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4842 && mips_opts
.oddspreg
;
4844 if (insn
->pinfo
== INSN_MACRO
)
4845 /* Let a macro pass, we'll catch it later when it is expanded. */
4848 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4849 otherwise it depends on oddspreg. */
4850 if ((insn
->pinfo
& FP_S
)
4851 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4852 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4853 return FPR_SIZE
== 32 || oddspreg
;
4855 /* Allow odd registers for single-precision ops and double-precision if the
4856 floating-point registers are 64-bit wide. */
4857 switch (insn
->pinfo
& (FP_S
| FP_D
))
4863 return FPR_SIZE
== 64;
4868 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4869 s
= strchr (insn
->name
, '.');
4870 if (s
!= NULL
&& opnum
== 2)
4871 s
= strchr (s
+ 1, '.');
4872 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4875 return FPR_SIZE
== 64;
4878 /* Information about an instruction argument that we're trying to match. */
4879 struct mips_arg_info
4881 /* The instruction so far. */
4882 struct mips_cl_insn
*insn
;
4884 /* The first unconsumed operand token. */
4885 struct mips_operand_token
*token
;
4887 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4890 /* The 1-based argument number, for error reporting. This does not
4891 count elided optional registers, etc.. */
4894 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4895 unsigned int last_regno
;
4897 /* If the first operand was an OP_REG, this is the register that it
4898 specified, otherwise it is ILLEGAL_REG. */
4899 unsigned int dest_regno
;
4901 /* The value of the last OP_INT operand. Only used for OP_MSB,
4902 where it gives the lsb position. */
4903 unsigned int last_op_int
;
4905 /* If true, match routines should assume that no later instruction
4906 alternative matches and should therefore be as accommodating as
4907 possible. Match routines should not report errors if something
4908 is only invalid for !LAX_MATCH. */
4909 bfd_boolean lax_match
;
4911 /* True if a reference to the current AT register was seen. */
4912 bfd_boolean seen_at
;
4915 /* Record that the argument is out of range. */
4918 match_out_of_range (struct mips_arg_info
*arg
)
4920 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4923 /* Record that the argument isn't constant but needs to be. */
4926 match_not_constant (struct mips_arg_info
*arg
)
4928 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4932 /* Try to match an OT_CHAR token for character CH. Consume the token
4933 and return true on success, otherwise return false. */
4936 match_char (struct mips_arg_info
*arg
, char ch
)
4938 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4948 /* Try to get an expression from the next tokens in ARG. Consume the
4949 tokens and return true on success, storing the expression value in
4950 VALUE and relocation types in R. */
4953 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4954 bfd_reloc_code_real_type
*r
)
4956 /* If the next token is a '(' that was parsed as being part of a base
4957 expression, assume we have an elided offset. The later match will fail
4958 if this turns out to be wrong. */
4959 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4961 value
->X_op
= O_constant
;
4962 value
->X_add_number
= 0;
4963 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4967 /* Reject register-based expressions such as "0+$2" and "(($2))".
4968 For plain registers the default error seems more appropriate. */
4969 if (arg
->token
->type
== OT_INTEGER
4970 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4972 set_insn_error (arg
->argnum
, _("register value used as expression"));
4976 if (arg
->token
->type
== OT_INTEGER
)
4978 *value
= arg
->token
->u
.integer
.value
;
4979 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4985 (arg
->argnum
, _("operand %d must be an immediate expression"),
4990 /* Try to get a constant expression from the next tokens in ARG. Consume
4991 the tokens and return true on success, storing the constant value
4995 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4998 bfd_reloc_code_real_type r
[3];
5000 if (!match_expression (arg
, &ex
, r
))
5003 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5004 *value
= ex
.X_add_number
;
5007 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5008 match_out_of_range (arg
);
5010 match_not_constant (arg
);
5016 /* Return the RTYPE_* flags for a register operand of type TYPE that
5017 appears in instruction OPCODE. */
5020 convert_reg_type (const struct mips_opcode
*opcode
,
5021 enum mips_reg_operand_type type
)
5026 return RTYPE_NUM
| RTYPE_GP
;
5029 /* Allow vector register names for MDMX if the instruction is a 64-bit
5030 FPR load, store or move (including moves to and from GPRs). */
5031 if ((mips_opts
.ase
& ASE_MDMX
)
5032 && (opcode
->pinfo
& FP_D
)
5033 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5034 | INSN_COPROC_MEMORY_DELAY
5037 | INSN_STORE_MEMORY
)))
5038 return RTYPE_FPU
| RTYPE_VEC
;
5042 if (opcode
->pinfo
& (FP_D
| FP_S
))
5043 return RTYPE_CCC
| RTYPE_FCC
;
5047 if (opcode
->membership
& INSN_5400
)
5049 return RTYPE_FPU
| RTYPE_VEC
;
5055 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5056 return RTYPE_NUM
| RTYPE_CP0
;
5063 return RTYPE_NUM
| RTYPE_VI
;
5066 return RTYPE_NUM
| RTYPE_VF
;
5068 case OP_REG_R5900_I
:
5069 return RTYPE_R5900_I
;
5071 case OP_REG_R5900_Q
:
5072 return RTYPE_R5900_Q
;
5074 case OP_REG_R5900_R
:
5075 return RTYPE_R5900_R
;
5077 case OP_REG_R5900_ACC
:
5078 return RTYPE_R5900_ACC
;
5083 case OP_REG_MSA_CTRL
:
5089 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5092 check_regno (struct mips_arg_info
*arg
,
5093 enum mips_reg_operand_type type
, unsigned int regno
)
5095 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5096 arg
->seen_at
= TRUE
;
5098 if (type
== OP_REG_FP
5100 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5102 /* This was a warning prior to introducing O32 FPXX and FP64 support
5103 so maintain a warning for FP32 but raise an error for the new
5106 as_warn (_("float register should be even, was %d"), regno
);
5108 as_bad (_("float register should be even, was %d"), regno
);
5111 if (type
== OP_REG_CCC
)
5116 name
= arg
->insn
->insn_mo
->name
;
5117 length
= strlen (name
);
5118 if ((regno
& 1) != 0
5119 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5120 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5121 as_warn (_("condition code register should be even for %s, was %d"),
5124 if ((regno
& 3) != 0
5125 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5126 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5131 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5132 a register of type TYPE. Return true on success, storing the register
5133 number in *REGNO and warning about any dubious uses. */
5136 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5137 unsigned int symval
, unsigned int *regno
)
5139 if (type
== OP_REG_VEC
)
5140 symval
= mips_prefer_vec_regno (symval
);
5141 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5144 *regno
= symval
& RNUM_MASK
;
5145 check_regno (arg
, type
, *regno
);
5149 /* Try to interpret the next token in ARG as a register of type TYPE.
5150 Consume the token and return true on success, storing the register
5151 number in *REGNO. Return false on failure. */
5154 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5155 unsigned int *regno
)
5157 if (arg
->token
->type
== OT_REG
5158 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5166 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5167 Consume the token and return true on success, storing the register numbers
5168 in *REGNO1 and *REGNO2. Return false on failure. */
5171 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5172 unsigned int *regno1
, unsigned int *regno2
)
5174 if (match_reg (arg
, type
, regno1
))
5179 if (arg
->token
->type
== OT_REG_RANGE
5180 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5181 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5182 && *regno1
<= *regno2
)
5190 /* OP_INT matcher. */
5193 match_int_operand (struct mips_arg_info
*arg
,
5194 const struct mips_operand
*operand_base
)
5196 const struct mips_int_operand
*operand
;
5198 int min_val
, max_val
, factor
;
5201 operand
= (const struct mips_int_operand
*) operand_base
;
5202 factor
= 1 << operand
->shift
;
5203 min_val
= mips_int_operand_min (operand
);
5204 max_val
= mips_int_operand_max (operand
);
5206 if (operand_base
->lsb
== 0
5207 && operand_base
->size
== 16
5208 && operand
->shift
== 0
5209 && operand
->bias
== 0
5210 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5212 /* The operand can be relocated. */
5213 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5216 if (offset_expr
.X_op
== O_big
)
5218 match_out_of_range (arg
);
5222 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5223 /* Relocation operators were used. Accept the argument and
5224 leave the relocation value in offset_expr and offset_relocs
5225 for the caller to process. */
5228 if (offset_expr
.X_op
!= O_constant
)
5230 /* Accept non-constant operands if no later alternative matches,
5231 leaving it for the caller to process. */
5232 if (!arg
->lax_match
)
5234 match_not_constant (arg
);
5237 offset_reloc
[0] = BFD_RELOC_LO16
;
5241 /* Clear the global state; we're going to install the operand
5243 sval
= offset_expr
.X_add_number
;
5244 offset_expr
.X_op
= O_absent
;
5246 /* For compatibility with older assemblers, we accept
5247 0x8000-0xffff as signed 16-bit numbers when only
5248 signed numbers are allowed. */
5251 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5252 if (!arg
->lax_match
&& sval
<= max_val
)
5254 match_out_of_range (arg
);
5261 if (!match_const_int (arg
, &sval
))
5265 arg
->last_op_int
= sval
;
5267 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5269 match_out_of_range (arg
);
5273 uval
= (unsigned int) sval
>> operand
->shift
;
5274 uval
-= operand
->bias
;
5276 /* Handle -mfix-cn63xxp1. */
5278 && mips_fix_cn63xxp1
5279 && !mips_opts
.micromips
5280 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5295 /* The rest must be changed to 28. */
5300 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5304 /* OP_MAPPED_INT matcher. */
5307 match_mapped_int_operand (struct mips_arg_info
*arg
,
5308 const struct mips_operand
*operand_base
)
5310 const struct mips_mapped_int_operand
*operand
;
5311 unsigned int uval
, num_vals
;
5314 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5315 if (!match_const_int (arg
, &sval
))
5318 num_vals
= 1 << operand_base
->size
;
5319 for (uval
= 0; uval
< num_vals
; uval
++)
5320 if (operand
->int_map
[uval
] == sval
)
5322 if (uval
== num_vals
)
5324 match_out_of_range (arg
);
5328 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5332 /* OP_MSB matcher. */
5335 match_msb_operand (struct mips_arg_info
*arg
,
5336 const struct mips_operand
*operand_base
)
5338 const struct mips_msb_operand
*operand
;
5339 int min_val
, max_val
, max_high
;
5340 offsetT size
, sval
, high
;
5342 operand
= (const struct mips_msb_operand
*) operand_base
;
5343 min_val
= operand
->bias
;
5344 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5345 max_high
= operand
->opsize
;
5347 if (!match_const_int (arg
, &size
))
5350 high
= size
+ arg
->last_op_int
;
5351 sval
= operand
->add_lsb
? high
: size
;
5353 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5355 match_out_of_range (arg
);
5358 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5362 /* OP_REG matcher. */
5365 match_reg_operand (struct mips_arg_info
*arg
,
5366 const struct mips_operand
*operand_base
)
5368 const struct mips_reg_operand
*operand
;
5369 unsigned int regno
, uval
, num_vals
;
5371 operand
= (const struct mips_reg_operand
*) operand_base
;
5372 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5375 if (operand
->reg_map
)
5377 num_vals
= 1 << operand
->root
.size
;
5378 for (uval
= 0; uval
< num_vals
; uval
++)
5379 if (operand
->reg_map
[uval
] == regno
)
5381 if (num_vals
== uval
)
5387 arg
->last_regno
= regno
;
5388 if (arg
->opnum
== 1)
5389 arg
->dest_regno
= regno
;
5390 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5394 /* OP_REG_PAIR matcher. */
5397 match_reg_pair_operand (struct mips_arg_info
*arg
,
5398 const struct mips_operand
*operand_base
)
5400 const struct mips_reg_pair_operand
*operand
;
5401 unsigned int regno1
, regno2
, uval
, num_vals
;
5403 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5404 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5405 || !match_char (arg
, ',')
5406 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5409 num_vals
= 1 << operand_base
->size
;
5410 for (uval
= 0; uval
< num_vals
; uval
++)
5411 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5413 if (uval
== num_vals
)
5416 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5420 /* OP_PCREL matcher. The caller chooses the relocation type. */
5423 match_pcrel_operand (struct mips_arg_info
*arg
)
5425 bfd_reloc_code_real_type r
[3];
5427 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5430 /* OP_PERF_REG matcher. */
5433 match_perf_reg_operand (struct mips_arg_info
*arg
,
5434 const struct mips_operand
*operand
)
5438 if (!match_const_int (arg
, &sval
))
5443 || (mips_opts
.arch
== CPU_R5900
5444 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5445 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5447 set_insn_error (arg
->argnum
, _("invalid performance register"));
5451 insn_insert_operand (arg
->insn
, operand
, sval
);
5455 /* OP_ADDIUSP matcher. */
5458 match_addiusp_operand (struct mips_arg_info
*arg
,
5459 const struct mips_operand
*operand
)
5464 if (!match_const_int (arg
, &sval
))
5469 match_out_of_range (arg
);
5474 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5476 match_out_of_range (arg
);
5480 uval
= (unsigned int) sval
;
5481 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5482 insn_insert_operand (arg
->insn
, operand
, uval
);
5486 /* OP_CLO_CLZ_DEST matcher. */
5489 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5490 const struct mips_operand
*operand
)
5494 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5497 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5501 /* OP_CHECK_PREV matcher. */
5504 match_check_prev_operand (struct mips_arg_info
*arg
,
5505 const struct mips_operand
*operand_base
)
5507 const struct mips_check_prev_operand
*operand
;
5510 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5512 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5515 if (!operand
->zero_ok
&& regno
== 0)
5518 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5519 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5520 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5522 arg
->last_regno
= regno
;
5523 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5530 /* OP_SAME_RS_RT matcher. */
5533 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5534 const struct mips_operand
*operand
)
5538 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5543 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5547 arg
->last_regno
= regno
;
5549 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5553 /* OP_LWM_SWM_LIST matcher. */
5556 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5557 const struct mips_operand
*operand
)
5559 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5560 struct mips_arg_info reset
;
5563 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5567 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5572 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5575 while (match_char (arg
, ',')
5576 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5579 if (operand
->size
== 2)
5581 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5587 and any permutations of these. */
5588 if ((reglist
& 0xfff1ffff) != 0x80010000)
5591 sregs
= (reglist
>> 17) & 7;
5596 /* The list must include at least one of ra and s0-sN,
5597 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5598 which are $23 and $30 respectively.) E.g.:
5606 and any permutations of these. */
5607 if ((reglist
& 0x3f00ffff) != 0)
5610 ra
= (reglist
>> 27) & 0x10;
5611 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5614 if ((sregs
& -sregs
) != sregs
)
5617 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5621 /* OP_ENTRY_EXIT_LIST matcher. */
5624 match_entry_exit_operand (struct mips_arg_info
*arg
,
5625 const struct mips_operand
*operand
)
5628 bfd_boolean is_exit
;
5630 /* The format is the same for both ENTRY and EXIT, but the constraints
5632 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5633 mask
= (is_exit
? 7 << 3 : 0);
5636 unsigned int regno1
, regno2
;
5637 bfd_boolean is_freg
;
5639 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5641 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5646 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5649 mask
|= (5 + regno2
) << 3;
5651 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5652 mask
|= (regno2
- 3) << 3;
5653 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5654 mask
|= (regno2
- 15) << 1;
5655 else if (regno1
== RA
&& regno2
== RA
)
5660 while (match_char (arg
, ','));
5662 insn_insert_operand (arg
->insn
, operand
, mask
);
5666 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5667 the argument register mask AMASK, the number of static registers
5668 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5669 respectively, and the frame size FRAME_SIZE. */
5672 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5673 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5674 unsigned int frame_size
)
5676 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5677 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5680 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5681 argument register mask AMASK, the number of static registers saved
5682 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5683 respectively, and the frame size FRAME_SIZE. */
5686 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5687 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5688 unsigned int frame_size
)
5692 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5693 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5694 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5695 | ((frame_size
& 0xf0) << 16));
5699 /* OP_SAVE_RESTORE_LIST matcher. */
5702 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5704 unsigned int opcode
, args
, statics
, sregs
;
5705 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5706 unsigned int arg_mask
, ra
, s0
, s1
;
5709 opcode
= arg
->insn
->insn_opcode
;
5711 num_frame_sizes
= 0;
5720 unsigned int regno1
, regno2
;
5722 if (arg
->token
->type
== OT_INTEGER
)
5724 /* Handle the frame size. */
5725 if (!match_const_int (arg
, &frame_size
))
5727 num_frame_sizes
+= 1;
5731 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5734 while (regno1
<= regno2
)
5736 if (regno1
>= 4 && regno1
<= 7)
5738 if (num_frame_sizes
== 0)
5740 args
|= 1 << (regno1
- 4);
5742 /* statics $a0-$a3 */
5743 statics
|= 1 << (regno1
- 4);
5745 else if (regno1
>= 16 && regno1
<= 23)
5747 sregs
|= 1 << (regno1
- 16);
5748 else if (regno1
== 30)
5751 else if (regno1
== 31)
5752 /* Add $ra to insn. */
5762 while (match_char (arg
, ','));
5764 /* Encode args/statics combination. */
5767 else if (args
== 0xf)
5768 /* All $a0-$a3 are args. */
5769 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5770 else if (statics
== 0xf)
5771 /* All $a0-$a3 are statics. */
5772 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5775 /* Count arg registers. */
5785 /* Count static registers. */
5787 while (statics
& 0x8)
5789 statics
= (statics
<< 1) & 0xf;
5795 /* Encode args/statics. */
5796 arg_mask
= (num_args
<< 2) | num_statics
;
5799 /* Encode $s0/$s1. */
5800 if (sregs
& (1 << 0)) /* $s0 */
5802 if (sregs
& (1 << 1)) /* $s1 */
5806 /* Encode $s2-$s8. */
5816 /* Encode frame size. */
5817 if (num_frame_sizes
== 0)
5819 set_insn_error (arg
->argnum
, _("missing frame size"));
5822 if (num_frame_sizes
> 1)
5824 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5827 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5829 set_insn_error (arg
->argnum
, _("invalid frame size"));
5834 /* Finally build the instruction. */
5835 if (mips_opts
.mips16
)
5836 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5838 else if (!mips_opts
.micromips
)
5839 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5844 arg
->insn
->insn_opcode
= opcode
;
5848 /* OP_MDMX_IMM_REG matcher. */
5851 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5852 const struct mips_operand
*operand
)
5854 unsigned int regno
, uval
;
5856 const struct mips_opcode
*opcode
;
5858 /* The mips_opcode records whether this is an octobyte or quadhalf
5859 instruction. Start out with that bit in place. */
5860 opcode
= arg
->insn
->insn_mo
;
5861 uval
= mips_extract_operand (operand
, opcode
->match
);
5862 is_qh
= (uval
!= 0);
5864 if (arg
->token
->type
== OT_REG
)
5866 if ((opcode
->membership
& INSN_5400
)
5867 && strcmp (opcode
->name
, "rzu.ob") == 0)
5869 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5874 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5878 /* Check whether this is a vector register or a broadcast of
5879 a single element. */
5880 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5882 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5884 set_insn_error (arg
->argnum
, _("invalid element selector"));
5887 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5892 /* A full vector. */
5893 if ((opcode
->membership
& INSN_5400
)
5894 && (strcmp (opcode
->name
, "sll.ob") == 0
5895 || strcmp (opcode
->name
, "srl.ob") == 0))
5897 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5903 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5905 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5913 if (!match_const_int (arg
, &sval
))
5915 if (sval
< 0 || sval
> 31)
5917 match_out_of_range (arg
);
5920 uval
|= (sval
& 31);
5922 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5924 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5926 insn_insert_operand (arg
->insn
, operand
, uval
);
5930 /* OP_IMM_INDEX matcher. */
5933 match_imm_index_operand (struct mips_arg_info
*arg
,
5934 const struct mips_operand
*operand
)
5936 unsigned int max_val
;
5938 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5941 max_val
= (1 << operand
->size
) - 1;
5942 if (arg
->token
->u
.index
> max_val
)
5944 match_out_of_range (arg
);
5947 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5952 /* OP_REG_INDEX matcher. */
5955 match_reg_index_operand (struct mips_arg_info
*arg
,
5956 const struct mips_operand
*operand
)
5960 if (arg
->token
->type
!= OT_REG_INDEX
)
5963 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5966 insn_insert_operand (arg
->insn
, operand
, regno
);
5971 /* OP_PC matcher. */
5974 match_pc_operand (struct mips_arg_info
*arg
)
5976 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5984 /* OP_REG28 matcher. */
5987 match_reg28_operand (struct mips_arg_info
*arg
)
5991 if (arg
->token
->type
== OT_REG
5992 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6001 /* OP_NON_ZERO_REG matcher. */
6004 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6005 const struct mips_operand
*operand
)
6009 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6015 arg
->last_regno
= regno
;
6016 insn_insert_operand (arg
->insn
, operand
, regno
);
6020 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6021 register that we need to match. */
6024 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6028 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6031 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6032 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6033 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6035 Return the constant in IMM and OFFSET as follows:
6037 - If the constant should be loaded via memory, set IMM to O_absent and
6038 OFFSET to the memory address.
6040 - Otherwise, if the constant should be loaded into two 32-bit registers,
6041 set IMM to the O_constant to load into the high register and OFFSET
6042 to the corresponding value for the low register.
6044 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6046 These constants only appear as the last operand in an instruction,
6047 and every instruction that accepts them in any variant accepts them
6048 in all variants. This means we don't have to worry about backing out
6049 any changes if the instruction does not match. We just match
6050 unconditionally and report an error if the constant is invalid. */
6053 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6054 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6059 const char *newname
;
6060 unsigned char *data
;
6062 /* Where the constant is placed is based on how the MIPS assembler
6065 length == 4 && using_gprs -- immediate value only
6066 length == 8 && using_gprs -- .rdata or immediate value
6067 length == 4 && !using_gprs -- .lit4 or immediate value
6068 length == 8 && !using_gprs -- .lit8 or immediate value
6070 The .lit4 and .lit8 sections are only used if permitted by the
6072 if (arg
->token
->type
!= OT_FLOAT
)
6074 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6078 gas_assert (arg
->token
->u
.flt
.length
== length
);
6079 data
= arg
->token
->u
.flt
.data
;
6082 /* Handle 32-bit constants for which an immediate value is best. */
6085 || g_switch_value
< 4
6086 || (data
[0] == 0 && data
[1] == 0)
6087 || (data
[2] == 0 && data
[3] == 0)))
6089 imm
->X_op
= O_constant
;
6090 if (!target_big_endian
)
6091 imm
->X_add_number
= bfd_getl32 (data
);
6093 imm
->X_add_number
= bfd_getb32 (data
);
6094 offset
->X_op
= O_absent
;
6098 /* Handle 64-bit constants for which an immediate value is best. */
6100 && !mips_disable_float_construction
6101 /* Constants can only be constructed in GPRs and copied to FPRs if the
6102 GPRs are at least as wide as the FPRs or MTHC1 is available.
6103 Unlike most tests for 32-bit floating-point registers this check
6104 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6105 permit 64-bit moves without MXHC1.
6106 Force the constant into memory otherwise. */
6109 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6111 && ((data
[0] == 0 && data
[1] == 0)
6112 || (data
[2] == 0 && data
[3] == 0))
6113 && ((data
[4] == 0 && data
[5] == 0)
6114 || (data
[6] == 0 && data
[7] == 0)))
6116 /* The value is simple enough to load with a couple of instructions.
6117 If using 32-bit registers, set IMM to the high order 32 bits and
6118 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6120 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6122 imm
->X_op
= O_constant
;
6123 offset
->X_op
= O_constant
;
6124 if (!target_big_endian
)
6126 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6127 offset
->X_add_number
= bfd_getl32 (data
);
6131 imm
->X_add_number
= bfd_getb32 (data
);
6132 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6134 if (offset
->X_add_number
== 0)
6135 offset
->X_op
= O_absent
;
6139 imm
->X_op
= O_constant
;
6140 if (!target_big_endian
)
6141 imm
->X_add_number
= bfd_getl64 (data
);
6143 imm
->X_add_number
= bfd_getb64 (data
);
6144 offset
->X_op
= O_absent
;
6149 /* Switch to the right section. */
6151 subseg
= now_subseg
;
6154 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6159 if (using_gprs
|| g_switch_value
< 8)
6160 newname
= RDATA_SECTION_NAME
;
6165 new_seg
= subseg_new (newname
, (subsegT
) 0);
6166 bfd_set_section_flags (stdoutput
, new_seg
,
6167 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6168 frag_align (length
== 4 ? 2 : 3, 0, 0);
6169 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6170 record_alignment (new_seg
, 4);
6172 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6174 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6176 /* Set the argument to the current address in the section. */
6177 imm
->X_op
= O_absent
;
6178 offset
->X_op
= O_symbol
;
6179 offset
->X_add_symbol
= symbol_temp_new_now ();
6180 offset
->X_add_number
= 0;
6182 /* Put the floating point number into the section. */
6183 p
= frag_more (length
);
6184 memcpy (p
, data
, length
);
6186 /* Switch back to the original section. */
6187 subseg_set (seg
, subseg
);
6191 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6195 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6196 const struct mips_operand
*operand
,
6197 bfd_boolean match_p
)
6201 /* The operand can be an XYZW mask or a single 2-bit channel index
6202 (with X being 0). */
6203 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6205 /* The suffix can be omitted when it is already part of the opcode. */
6206 if (arg
->token
->type
!= OT_CHANNELS
)
6209 uval
= arg
->token
->u
.channels
;
6210 if (operand
->size
== 2)
6212 /* Check that a single bit is set and convert it into a 2-bit index. */
6213 if ((uval
& -uval
) != uval
)
6215 uval
= 4 - ffs (uval
);
6218 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6223 insn_insert_operand (arg
->insn
, operand
, uval
);
6227 /* Try to match a token from ARG against OPERAND. Consume the token
6228 and return true on success, otherwise return false. */
6231 match_operand (struct mips_arg_info
*arg
,
6232 const struct mips_operand
*operand
)
6234 switch (operand
->type
)
6237 return match_int_operand (arg
, operand
);
6240 return match_mapped_int_operand (arg
, operand
);
6243 return match_msb_operand (arg
, operand
);
6246 case OP_OPTIONAL_REG
:
6247 return match_reg_operand (arg
, operand
);
6250 return match_reg_pair_operand (arg
, operand
);
6253 return match_pcrel_operand (arg
);
6256 return match_perf_reg_operand (arg
, operand
);
6258 case OP_ADDIUSP_INT
:
6259 return match_addiusp_operand (arg
, operand
);
6261 case OP_CLO_CLZ_DEST
:
6262 return match_clo_clz_dest_operand (arg
, operand
);
6264 case OP_LWM_SWM_LIST
:
6265 return match_lwm_swm_list_operand (arg
, operand
);
6267 case OP_ENTRY_EXIT_LIST
:
6268 return match_entry_exit_operand (arg
, operand
);
6270 case OP_SAVE_RESTORE_LIST
:
6271 return match_save_restore_list_operand (arg
);
6273 case OP_MDMX_IMM_REG
:
6274 return match_mdmx_imm_reg_operand (arg
, operand
);
6276 case OP_REPEAT_DEST_REG
:
6277 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6279 case OP_REPEAT_PREV_REG
:
6280 return match_tied_reg_operand (arg
, arg
->last_regno
);
6283 return match_pc_operand (arg
);
6286 return match_reg28_operand (arg
);
6289 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6291 case OP_VU0_MATCH_SUFFIX
:
6292 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6295 return match_imm_index_operand (arg
, operand
);
6298 return match_reg_index_operand (arg
, operand
);
6301 return match_same_rs_rt_operand (arg
, operand
);
6304 return match_check_prev_operand (arg
, operand
);
6306 case OP_NON_ZERO_REG
:
6307 return match_non_zero_reg_operand (arg
, operand
);
6312 /* ARG is the state after successfully matching an instruction.
6313 Issue any queued-up warnings. */
6316 check_completed_insn (struct mips_arg_info
*arg
)
6321 as_warn (_("used $at without \".set noat\""));
6323 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6327 /* Return true if modifying general-purpose register REG needs a delay. */
6330 reg_needs_delay (unsigned int reg
)
6332 unsigned long prev_pinfo
;
6334 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6335 if (!mips_opts
.noreorder
6336 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6337 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6338 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6344 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6345 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6346 by VR4120 errata. */
6349 classify_vr4120_insn (const char *name
)
6351 if (strncmp (name
, "macc", 4) == 0)
6352 return FIX_VR4120_MACC
;
6353 if (strncmp (name
, "dmacc", 5) == 0)
6354 return FIX_VR4120_DMACC
;
6355 if (strncmp (name
, "mult", 4) == 0)
6356 return FIX_VR4120_MULT
;
6357 if (strncmp (name
, "dmult", 5) == 0)
6358 return FIX_VR4120_DMULT
;
6359 if (strstr (name
, "div"))
6360 return FIX_VR4120_DIV
;
6361 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6362 return FIX_VR4120_MTHILO
;
6363 return NUM_FIX_VR4120_CLASSES
;
6366 #define INSN_ERET 0x42000018
6367 #define INSN_DERET 0x4200001f
6368 #define INSN_DMULT 0x1c
6369 #define INSN_DMULTU 0x1d
6371 /* Return the number of instructions that must separate INSN1 and INSN2,
6372 where INSN1 is the earlier instruction. Return the worst-case value
6373 for any INSN2 if INSN2 is null. */
6376 insns_between (const struct mips_cl_insn
*insn1
,
6377 const struct mips_cl_insn
*insn2
)
6379 unsigned long pinfo1
, pinfo2
;
6382 /* If INFO2 is null, pessimistically assume that all flags are set for
6383 the second instruction. */
6384 pinfo1
= insn1
->insn_mo
->pinfo
;
6385 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6387 /* For most targets, write-after-read dependencies on the HI and LO
6388 registers must be separated by at least two instructions. */
6389 if (!hilo_interlocks
)
6391 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6393 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6397 /* If we're working around r7000 errata, there must be two instructions
6398 between an mfhi or mflo and any instruction that uses the result. */
6399 if (mips_7000_hilo_fix
6400 && !mips_opts
.micromips
6401 && MF_HILO_INSN (pinfo1
)
6402 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6405 /* If we're working around 24K errata, one instruction is required
6406 if an ERET or DERET is followed by a branch instruction. */
6407 if (mips_fix_24k
&& !mips_opts
.micromips
)
6409 if (insn1
->insn_opcode
== INSN_ERET
6410 || insn1
->insn_opcode
== INSN_DERET
)
6413 || insn2
->insn_opcode
== INSN_ERET
6414 || insn2
->insn_opcode
== INSN_DERET
6415 || delayed_branch_p (insn2
))
6420 /* If we're working around PMC RM7000 errata, there must be three
6421 nops between a dmult and a load instruction. */
6422 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6424 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6425 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6427 if (pinfo2
& INSN_LOAD_MEMORY
)
6432 /* If working around VR4120 errata, check for combinations that need
6433 a single intervening instruction. */
6434 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6436 unsigned int class1
, class2
;
6438 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6439 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6443 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6444 if (vr4120_conflicts
[class1
] & (1 << class2
))
6449 if (!HAVE_CODE_COMPRESSION
)
6451 /* Check for GPR or coprocessor load delays. All such delays
6452 are on the RT register. */
6453 /* Itbl support may require additional care here. */
6454 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6455 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6457 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6461 /* Check for generic coprocessor hazards.
6463 This case is not handled very well. There is no special
6464 knowledge of CP0 handling, and the coprocessors other than
6465 the floating point unit are not distinguished at all. */
6466 /* Itbl support may require additional care here. FIXME!
6467 Need to modify this to include knowledge about
6468 user specified delays! */
6469 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6470 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6472 /* Handle cases where INSN1 writes to a known general coprocessor
6473 register. There must be a one instruction delay before INSN2
6474 if INSN2 reads that register, otherwise no delay is needed. */
6475 mask
= fpr_write_mask (insn1
);
6478 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6483 /* Read-after-write dependencies on the control registers
6484 require a two-instruction gap. */
6485 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6486 && (pinfo2
& INSN_READ_COND_CODE
))
6489 /* We don't know exactly what INSN1 does. If INSN2 is
6490 also a coprocessor instruction, assume there must be
6491 a one instruction gap. */
6492 if (pinfo2
& INSN_COP
)
6497 /* Check for read-after-write dependencies on the coprocessor
6498 control registers in cases where INSN1 does not need a general
6499 coprocessor delay. This means that INSN1 is a floating point
6500 comparison instruction. */
6501 /* Itbl support may require additional care here. */
6502 else if (!cop_interlocks
6503 && (pinfo1
& INSN_WRITE_COND_CODE
)
6504 && (pinfo2
& INSN_READ_COND_CODE
))
6508 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6509 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6511 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6512 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6513 || (insn2
&& delayed_branch_p (insn2
))))
6519 /* Return the number of nops that would be needed to work around the
6520 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6521 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6522 that are contained within the first IGNORE instructions of HIST. */
6525 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6526 const struct mips_cl_insn
*insn
)
6531 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6532 are not affected by the errata. */
6534 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6535 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6536 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6539 /* Search for the first MFLO or MFHI. */
6540 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6541 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6543 /* Extract the destination register. */
6544 mask
= gpr_write_mask (&hist
[i
]);
6546 /* No nops are needed if INSN reads that register. */
6547 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6550 /* ...or if any of the intervening instructions do. */
6551 for (j
= 0; j
< i
; j
++)
6552 if (gpr_read_mask (&hist
[j
]) & mask
)
6556 return MAX_VR4130_NOPS
- i
;
6561 #define BASE_REG_EQ(INSN1, INSN2) \
6562 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6563 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6565 /* Return the minimum alignment for this store instruction. */
6568 fix_24k_align_to (const struct mips_opcode
*mo
)
6570 if (strcmp (mo
->name
, "sh") == 0)
6573 if (strcmp (mo
->name
, "swc1") == 0
6574 || strcmp (mo
->name
, "swc2") == 0
6575 || strcmp (mo
->name
, "sw") == 0
6576 || strcmp (mo
->name
, "sc") == 0
6577 || strcmp (mo
->name
, "s.s") == 0)
6580 if (strcmp (mo
->name
, "sdc1") == 0
6581 || strcmp (mo
->name
, "sdc2") == 0
6582 || strcmp (mo
->name
, "s.d") == 0)
6589 struct fix_24k_store_info
6591 /* Immediate offset, if any, for this store instruction. */
6593 /* Alignment required by this store instruction. */
6595 /* True for register offsets. */
6596 int register_offset
;
6599 /* Comparison function used by qsort. */
6602 fix_24k_sort (const void *a
, const void *b
)
6604 const struct fix_24k_store_info
*pos1
= a
;
6605 const struct fix_24k_store_info
*pos2
= b
;
6607 return (pos1
->off
- pos2
->off
);
6610 /* INSN is a store instruction. Try to record the store information
6611 in STINFO. Return false if the information isn't known. */
6614 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6615 const struct mips_cl_insn
*insn
)
6617 /* The instruction must have a known offset. */
6618 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6621 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6622 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6626 /* Return the number of nops that would be needed to work around the 24k
6627 "lost data on stores during refill" errata if instruction INSN
6628 immediately followed the 2 instructions described by HIST.
6629 Ignore hazards that are contained within the first IGNORE
6630 instructions of HIST.
6632 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6633 for the data cache refills and store data. The following describes
6634 the scenario where the store data could be lost.
6636 * A data cache miss, due to either a load or a store, causing fill
6637 data to be supplied by the memory subsystem
6638 * The first three doublewords of fill data are returned and written
6640 * A sequence of four stores occurs in consecutive cycles around the
6641 final doubleword of the fill:
6645 * Zero, One or more instructions
6648 The four stores A-D must be to different doublewords of the line that
6649 is being filled. The fourth instruction in the sequence above permits
6650 the fill of the final doubleword to be transferred from the FSB into
6651 the cache. In the sequence above, the stores may be either integer
6652 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6653 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6654 different doublewords on the line. If the floating point unit is
6655 running in 1:2 mode, it is not possible to create the sequence above
6656 using only floating point store instructions.
6658 In this case, the cache line being filled is incorrectly marked
6659 invalid, thereby losing the data from any store to the line that
6660 occurs between the original miss and the completion of the five
6661 cycle sequence shown above.
6663 The workarounds are:
6665 * Run the data cache in write-through mode.
6666 * Insert a non-store instruction between
6667 Store A and Store B or Store B and Store C. */
6670 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6671 const struct mips_cl_insn
*insn
)
6673 struct fix_24k_store_info pos
[3];
6674 int align
, i
, base_offset
;
6679 /* If the previous instruction wasn't a store, there's nothing to
6681 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6684 /* If the instructions after the previous one are unknown, we have
6685 to assume the worst. */
6689 /* Check whether we are dealing with three consecutive stores. */
6690 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6691 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6694 /* If we don't know the relationship between the store addresses,
6695 assume the worst. */
6696 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6697 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6700 if (!fix_24k_record_store_info (&pos
[0], insn
)
6701 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6702 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6705 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6707 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6708 X bytes and such that the base register + X is known to be aligned
6711 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6715 align
= pos
[0].align_to
;
6716 base_offset
= pos
[0].off
;
6717 for (i
= 1; i
< 3; i
++)
6718 if (align
< pos
[i
].align_to
)
6720 align
= pos
[i
].align_to
;
6721 base_offset
= pos
[i
].off
;
6723 for (i
= 0; i
< 3; i
++)
6724 pos
[i
].off
-= base_offset
;
6727 pos
[0].off
&= ~align
+ 1;
6728 pos
[1].off
&= ~align
+ 1;
6729 pos
[2].off
&= ~align
+ 1;
6731 /* If any two stores write to the same chunk, they also write to the
6732 same doubleword. The offsets are still sorted at this point. */
6733 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6736 /* A range of at least 9 bytes is needed for the stores to be in
6737 non-overlapping doublewords. */
6738 if (pos
[2].off
- pos
[0].off
<= 8)
6741 if (pos
[2].off
- pos
[1].off
>= 24
6742 || pos
[1].off
- pos
[0].off
>= 24
6743 || pos
[2].off
- pos
[0].off
>= 32)
6749 /* Return the number of nops that would be needed if instruction INSN
6750 immediately followed the MAX_NOPS instructions given by HIST,
6751 where HIST[0] is the most recent instruction. Ignore hazards
6752 between INSN and the first IGNORE instructions in HIST.
6754 If INSN is null, return the worse-case number of nops for any
6758 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6759 const struct mips_cl_insn
*insn
)
6761 int i
, nops
, tmp_nops
;
6764 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6766 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6767 if (tmp_nops
> nops
)
6771 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6773 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6774 if (tmp_nops
> nops
)
6778 if (mips_fix_24k
&& !mips_opts
.micromips
)
6780 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6781 if (tmp_nops
> nops
)
6788 /* The variable arguments provide NUM_INSNS extra instructions that
6789 might be added to HIST. Return the largest number of nops that
6790 would be needed after the extended sequence, ignoring hazards
6791 in the first IGNORE instructions. */
6794 nops_for_sequence (int num_insns
, int ignore
,
6795 const struct mips_cl_insn
*hist
, ...)
6798 struct mips_cl_insn buffer
[MAX_NOPS
];
6799 struct mips_cl_insn
*cursor
;
6802 va_start (args
, hist
);
6803 cursor
= buffer
+ num_insns
;
6804 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6805 while (cursor
> buffer
)
6806 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6808 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6813 /* Like nops_for_insn, but if INSN is a branch, take into account the
6814 worst-case delay for the branch target. */
6817 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6818 const struct mips_cl_insn
*insn
)
6822 nops
= nops_for_insn (ignore
, hist
, insn
);
6823 if (delayed_branch_p (insn
))
6825 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6826 hist
, insn
, get_delay_slot_nop (insn
));
6827 if (tmp_nops
> nops
)
6830 else if (compact_branch_p (insn
))
6832 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6833 if (tmp_nops
> nops
)
6839 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6842 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6844 gas_assert (!HAVE_CODE_COMPRESSION
);
6845 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6846 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6849 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6850 jr target pc &= 'hffff_ffff_cfff_ffff. */
6853 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6855 gas_assert (!HAVE_CODE_COMPRESSION
);
6856 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6857 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6858 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6866 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6867 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6870 ep
.X_op
= O_constant
;
6871 ep
.X_add_number
= 0xcfff0000;
6872 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6873 ep
.X_add_number
= 0xffff;
6874 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6875 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6880 fix_loongson2f (struct mips_cl_insn
* ip
)
6882 if (mips_fix_loongson2f_nop
)
6883 fix_loongson2f_nop (ip
);
6885 if (mips_fix_loongson2f_jump
)
6886 fix_loongson2f_jump (ip
);
6889 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6892 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6894 gas_assert (!HAVE_CODE_COMPRESSION
);
6896 /* If is an local label and the insn is not sync,
6897 look forward that whether an branch between ll/sc jump to here
6898 if so, insert a sync. */
6899 if (seg_info (now_seg
)->label_list
6900 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6901 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6903 const char *label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6904 unsigned long lookback
= ARRAY_SIZE (history
);
6907 for (i
= 0; i
< lookback
; i
++)
6909 if (streq (history
[i
].insn_mo
->name
, "ll")
6910 || streq (history
[i
].insn_mo
->name
, "lld"))
6913 if (streq (history
[i
].insn_mo
->name
, "sc")
6914 || streq (history
[i
].insn_mo
->name
, "scd"))
6918 for (j
= i
+ 1; j
< lookback
; j
++)
6920 if (streq (history
[i
].insn_mo
->name
, "ll")
6921 || streq (history
[i
].insn_mo
->name
, "lld"))
6924 if (delayed_branch_p (&history
[j
]))
6926 if (streq (history
[j
].target
, label_name
))
6928 add_fixed_insn (&sync_insn
);
6929 insert_into_history (0, 1, &sync_insn
);
6938 /* If we find a sc, we look forward to look for an branch insn,
6939 and see whether it jump back and out of ll/sc. */
6940 else if (streq(ip
->insn_mo
->name
, "sc") || streq(ip
->insn_mo
->name
, "scd"))
6942 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6945 for (i
= 0; i
< lookback
; i
++)
6947 if (streq (history
[i
].insn_mo
->name
, "ll")
6948 || streq (history
[i
].insn_mo
->name
, "lld"))
6951 if (delayed_branch_p (&history
[i
]))
6955 for (j
= i
+ 1; j
< lookback
; j
++)
6957 if (streq (history
[j
].insn_mo
->name
, "ll")
6958 || streq (history
[i
].insn_mo
->name
, "lld"))
6962 for (; j
< lookback
; j
++)
6964 if (history
[j
].label
[0] != '\0'
6965 && streq (history
[j
].label
, history
[i
].target
)
6966 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
6968 add_fixed_insn (&sync_insn
);
6969 insert_into_history (++j
, 1, &sync_insn
);
6976 /* Skip if there is a sync before ll/lld. */
6977 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
6978 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
6979 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
6981 add_fixed_insn (&sync_insn
);
6982 insert_into_history (0, 1, &sync_insn
);
6986 /* IP is a branch that has a delay slot, and we need to fill it
6987 automatically. Return true if we can do that by swapping IP
6988 with the previous instruction.
6989 ADDRESS_EXPR is an operand of the instruction to be used with
6993 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6994 bfd_reloc_code_real_type
*reloc_type
)
6996 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6997 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6998 unsigned int fpr_read
, prev_fpr_write
;
7000 /* -O2 and above is required for this optimization. */
7001 if (mips_optimize
< 2)
7004 /* If we have seen .set volatile or .set nomove, don't optimize. */
7005 if (mips_opts
.nomove
)
7008 /* We can't swap if the previous instruction's position is fixed. */
7009 if (history
[0].fixed_p
)
7012 /* If the previous previous insn was in a .set noreorder, we can't
7013 swap. Actually, the MIPS assembler will swap in this situation.
7014 However, gcc configured -with-gnu-as will generate code like
7022 in which we can not swap the bne and INSN. If gcc is not configured
7023 -with-gnu-as, it does not output the .set pseudo-ops. */
7024 if (history
[1].noreorder_p
)
7027 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7028 This means that the previous instruction was a 4-byte one anyhow. */
7029 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7032 /* If the branch is itself the target of a branch, we can not swap.
7033 We cheat on this; all we check for is whether there is a label on
7034 this instruction. If there are any branches to anything other than
7035 a label, users must use .set noreorder. */
7036 if (seg_info (now_seg
)->label_list
)
7039 /* If the previous instruction is in a variant frag other than this
7040 branch's one, we cannot do the swap. This does not apply to
7041 MIPS16 code, which uses variant frags for different purposes. */
7042 if (!mips_opts
.mips16
7044 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7047 /* We do not swap with instructions that cannot architecturally
7048 be placed in a branch delay slot, such as SYNC or ERET. We
7049 also refrain from swapping with a trap instruction, since it
7050 complicates trap handlers to have the trap instruction be in
7052 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7053 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7056 /* Check for conflicts between the branch and the instructions
7057 before the candidate delay slot. */
7058 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7061 /* Check for conflicts between the swapped sequence and the
7062 target of the branch. */
7063 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7066 /* If the branch reads a register that the previous
7067 instruction sets, we can not swap. */
7068 gpr_read
= gpr_read_mask (ip
);
7069 prev_gpr_write
= gpr_write_mask (&history
[0]);
7070 if (gpr_read
& prev_gpr_write
)
7073 fpr_read
= fpr_read_mask (ip
);
7074 prev_fpr_write
= fpr_write_mask (&history
[0]);
7075 if (fpr_read
& prev_fpr_write
)
7078 /* If the branch writes a register that the previous
7079 instruction sets, we can not swap. */
7080 gpr_write
= gpr_write_mask (ip
);
7081 if (gpr_write
& prev_gpr_write
)
7084 /* If the branch writes a register that the previous
7085 instruction reads, we can not swap. */
7086 prev_gpr_read
= gpr_read_mask (&history
[0]);
7087 if (gpr_write
& prev_gpr_read
)
7090 /* If one instruction sets a condition code and the
7091 other one uses a condition code, we can not swap. */
7092 pinfo
= ip
->insn_mo
->pinfo
;
7093 if ((pinfo
& INSN_READ_COND_CODE
)
7094 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7096 if ((pinfo
& INSN_WRITE_COND_CODE
)
7097 && (prev_pinfo
& INSN_READ_COND_CODE
))
7100 /* If the previous instruction uses the PC, we can not swap. */
7101 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7102 if (prev_pinfo2
& INSN2_READ_PC
)
7105 /* If the previous instruction has an incorrect size for a fixed
7106 branch delay slot in microMIPS mode, we cannot swap. */
7107 pinfo2
= ip
->insn_mo
->pinfo2
;
7108 if (mips_opts
.micromips
7109 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7110 && insn_length (history
) != 2)
7112 if (mips_opts
.micromips
7113 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7114 && insn_length (history
) != 4)
7117 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7120 The short loop bug under certain conditions causes loops to execute
7121 only once or twice. We must ensure that the assembler never
7122 generates loops that satisfy all of the following conditions:
7124 - a loop consists of less than or equal to six instructions
7125 (including the branch delay slot);
7126 - a loop contains only one conditional branch instruction at the end
7128 - a loop does not contain any other branch or jump instructions;
7129 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7131 We need to do this because of a hardware bug in the R5900 chip. */
7133 /* Check if instruction has a parameter, ignore "j $31". */
7134 && (address_expr
!= NULL
)
7135 /* Parameter must be 16 bit. */
7136 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7137 /* Branch to same segment. */
7138 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7139 /* Branch to same code fragment. */
7140 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7141 /* Can only calculate branch offset if value is known. */
7142 && symbol_constant_p (address_expr
->X_add_symbol
)
7143 /* Check if branch is really conditional. */
7144 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7145 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7146 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7149 /* Check if loop is shorter than or equal to 6 instructions
7150 including branch and delay slot. */
7151 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7158 /* When the loop includes branches or jumps,
7159 it is not a short loop. */
7160 for (i
= 0; i
< (distance
/ 4); i
++)
7162 if ((history
[i
].cleared_p
)
7163 || delayed_branch_p (&history
[i
]))
7171 /* Insert nop after branch to fix short loop. */
7180 /* Decide how we should add IP to the instruction stream.
7181 ADDRESS_EXPR is an operand of the instruction to be used with
7184 static enum append_method
7185 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7186 bfd_reloc_code_real_type
*reloc_type
)
7188 /* The relaxed version of a macro sequence must be inherently
7190 if (mips_relax
.sequence
== 2)
7193 /* We must not dabble with instructions in a ".set noreorder" block. */
7194 if (mips_opts
.noreorder
)
7197 /* Otherwise, it's our responsibility to fill branch delay slots. */
7198 if (delayed_branch_p (ip
))
7200 if (!branch_likely_p (ip
)
7201 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7204 if (mips_opts
.mips16
7205 && ISA_SUPPORTS_MIPS16E
7206 && gpr_read_mask (ip
) != 0)
7207 return APPEND_ADD_COMPACT
;
7209 if (mips_opts
.micromips
7210 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7211 || (!forced_insn_length
7212 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7213 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7214 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7215 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7216 return APPEND_ADD_COMPACT
;
7218 return APPEND_ADD_WITH_NOP
;
7224 /* IP is an instruction whose opcode we have just changed, END points
7225 to the end of the opcode table processed. Point IP->insn_mo to the
7226 new opcode's definition. */
7229 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7231 const struct mips_opcode
*mo
;
7233 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7234 if (mo
->pinfo
!= INSN_MACRO
7235 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7243 /* IP is a MIPS16 instruction whose opcode we have just changed.
7244 Point IP->insn_mo to the new opcode's definition. */
7247 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7249 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7252 /* IP is a microMIPS instruction whose opcode we have just changed.
7253 Point IP->insn_mo to the new opcode's definition. */
7256 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7258 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7261 /* For microMIPS macros, we need to generate a local number label
7262 as the target of branches. */
7263 #define MICROMIPS_LABEL_CHAR '\037'
7264 static unsigned long micromips_target_label
;
7265 static char micromips_target_name
[32];
7268 micromips_label_name (void)
7270 char *p
= micromips_target_name
;
7271 char symbol_name_temporary
[24];
7279 l
= micromips_target_label
;
7280 #ifdef LOCAL_LABEL_PREFIX
7281 *p
++ = LOCAL_LABEL_PREFIX
;
7284 *p
++ = MICROMIPS_LABEL_CHAR
;
7287 symbol_name_temporary
[i
++] = l
% 10 + '0';
7292 *p
++ = symbol_name_temporary
[--i
];
7295 return micromips_target_name
;
7299 micromips_label_expr (expressionS
*label_expr
)
7301 label_expr
->X_op
= O_symbol
;
7302 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7303 label_expr
->X_add_number
= 0;
7307 micromips_label_inc (void)
7309 micromips_target_label
++;
7310 *micromips_target_name
= '\0';
7314 micromips_add_label (void)
7318 s
= colon (micromips_label_name ());
7319 micromips_label_inc ();
7320 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7323 /* If assembling microMIPS code, then return the microMIPS reloc
7324 corresponding to the requested one if any. Otherwise return
7325 the reloc unchanged. */
7327 static bfd_reloc_code_real_type
7328 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7330 static const bfd_reloc_code_real_type relocs
[][2] =
7332 /* Keep sorted incrementally by the left-hand key. */
7333 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7334 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7335 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7336 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7337 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7338 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7339 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7340 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7341 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7342 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7343 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7344 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7345 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7346 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7347 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7348 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7349 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7350 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7351 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7352 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7353 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7354 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7355 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7356 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7357 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7358 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7359 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7361 bfd_reloc_code_real_type r
;
7364 if (!mips_opts
.micromips
)
7366 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7372 return relocs
[i
][1];
7377 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7378 Return true on success, storing the resolved value in RESULT. */
7381 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7386 case BFD_RELOC_MIPS_HIGHEST
:
7387 case BFD_RELOC_MICROMIPS_HIGHEST
:
7388 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7391 case BFD_RELOC_MIPS_HIGHER
:
7392 case BFD_RELOC_MICROMIPS_HIGHER
:
7393 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7396 case BFD_RELOC_HI16_S
:
7397 case BFD_RELOC_HI16_S_PCREL
:
7398 case BFD_RELOC_MICROMIPS_HI16_S
:
7399 case BFD_RELOC_MIPS16_HI16_S
:
7400 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7403 case BFD_RELOC_HI16
:
7404 case BFD_RELOC_MICROMIPS_HI16
:
7405 case BFD_RELOC_MIPS16_HI16
:
7406 *result
= (operand
>> 16) & 0xffff;
7409 case BFD_RELOC_LO16
:
7410 case BFD_RELOC_LO16_PCREL
:
7411 case BFD_RELOC_MICROMIPS_LO16
:
7412 case BFD_RELOC_MIPS16_LO16
:
7413 *result
= operand
& 0xffff;
7416 case BFD_RELOC_UNUSED
:
7425 /* Output an instruction. IP is the instruction information.
7426 ADDRESS_EXPR is an operand of the instruction to be used with
7427 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7428 a macro expansion. */
7431 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7432 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7434 unsigned long prev_pinfo2
, pinfo
;
7435 bfd_boolean relaxed_branch
= FALSE
;
7436 enum append_method method
;
7437 bfd_boolean relax32
;
7440 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7441 fix_loongson2f (ip
);
7443 ip
->target
[0] = '\0';
7444 if (offset_expr
.X_op
== O_symbol
)
7445 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7446 ip
->label
[0] = '\0';
7447 if (seg_info (now_seg
)->label_list
)
7448 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7449 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7450 fix_loongson3_llsc (ip
);
7452 file_ase_mips16
|= mips_opts
.mips16
;
7453 file_ase_micromips
|= mips_opts
.micromips
;
7455 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7456 pinfo
= ip
->insn_mo
->pinfo
;
7458 /* Don't raise alarm about `nods' frags as they'll fill in the right
7459 kind of nop in relaxation if required. */
7460 if (mips_opts
.micromips
7462 && !(history
[0].frag
7463 && history
[0].frag
->fr_type
== rs_machine_dependent
7464 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7465 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7466 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7467 && micromips_insn_length (ip
->insn_mo
) != 2)
7468 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7469 && micromips_insn_length (ip
->insn_mo
) != 4)))
7470 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7471 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7473 if (address_expr
== NULL
)
7475 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7476 && reloc_type
[1] == BFD_RELOC_UNUSED
7477 && reloc_type
[2] == BFD_RELOC_UNUSED
7478 && address_expr
->X_op
== O_constant
)
7480 switch (*reloc_type
)
7482 case BFD_RELOC_MIPS_JMP
:
7486 /* Shift is 2, unusually, for microMIPS JALX. */
7487 shift
= (mips_opts
.micromips
7488 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7489 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7490 as_bad (_("jump to misaligned address (0x%lx)"),
7491 (unsigned long) address_expr
->X_add_number
);
7492 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7498 case BFD_RELOC_MIPS16_JMP
:
7499 if ((address_expr
->X_add_number
& 3) != 0)
7500 as_bad (_("jump to misaligned address (0x%lx)"),
7501 (unsigned long) address_expr
->X_add_number
);
7503 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7504 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7505 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7509 case BFD_RELOC_16_PCREL_S2
:
7513 shift
= mips_opts
.micromips
? 1 : 2;
7514 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7515 as_bad (_("branch to misaligned address (0x%lx)"),
7516 (unsigned long) address_expr
->X_add_number
);
7517 if (!mips_relax_branch
)
7519 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7520 & ~((1 << (shift
+ 16)) - 1))
7521 as_bad (_("branch address range overflow (0x%lx)"),
7522 (unsigned long) address_expr
->X_add_number
);
7523 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7529 case BFD_RELOC_MIPS_21_PCREL_S2
:
7534 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7535 as_bad (_("branch to misaligned address (0x%lx)"),
7536 (unsigned long) address_expr
->X_add_number
);
7537 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7538 & ~((1 << (shift
+ 21)) - 1))
7539 as_bad (_("branch address range overflow (0x%lx)"),
7540 (unsigned long) address_expr
->X_add_number
);
7541 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7546 case BFD_RELOC_MIPS_26_PCREL_S2
:
7551 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7552 as_bad (_("branch to misaligned address (0x%lx)"),
7553 (unsigned long) address_expr
->X_add_number
);
7554 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7555 & ~((1 << (shift
+ 26)) - 1))
7556 as_bad (_("branch address range overflow (0x%lx)"),
7557 (unsigned long) address_expr
->X_add_number
);
7558 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7567 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7570 ip
->insn_opcode
|= value
& 0xffff;
7578 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7580 /* There are a lot of optimizations we could do that we don't.
7581 In particular, we do not, in general, reorder instructions.
7582 If you use gcc with optimization, it will reorder
7583 instructions and generally do much more optimization then we
7584 do here; repeating all that work in the assembler would only
7585 benefit hand written assembly code, and does not seem worth
7587 int nops
= (mips_optimize
== 0
7588 ? nops_for_insn (0, history
, NULL
)
7589 : nops_for_insn_or_target (0, history
, ip
));
7593 unsigned long old_frag_offset
;
7596 old_frag
= frag_now
;
7597 old_frag_offset
= frag_now_fix ();
7599 for (i
= 0; i
< nops
; i
++)
7600 add_fixed_insn (NOP_INSN
);
7601 insert_into_history (0, nops
, NOP_INSN
);
7605 listing_prev_line ();
7606 /* We may be at the start of a variant frag. In case we
7607 are, make sure there is enough space for the frag
7608 after the frags created by listing_prev_line. The
7609 argument to frag_grow here must be at least as large
7610 as the argument to all other calls to frag_grow in
7611 this file. We don't have to worry about being in the
7612 middle of a variant frag, because the variants insert
7613 all needed nop instructions themselves. */
7617 mips_move_text_labels ();
7619 #ifndef NO_ECOFF_DEBUGGING
7620 if (ECOFF_DEBUGGING
)
7621 ecoff_fix_loc (old_frag
, old_frag_offset
);
7625 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7629 /* Work out how many nops in prev_nop_frag are needed by IP,
7630 ignoring hazards generated by the first prev_nop_frag_since
7632 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7633 gas_assert (nops
<= prev_nop_frag_holds
);
7635 /* Enforce NOPS as a minimum. */
7636 if (nops
> prev_nop_frag_required
)
7637 prev_nop_frag_required
= nops
;
7639 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7641 /* Settle for the current number of nops. Update the history
7642 accordingly (for the benefit of any future .set reorder code). */
7643 prev_nop_frag
= NULL
;
7644 insert_into_history (prev_nop_frag_since
,
7645 prev_nop_frag_holds
, NOP_INSN
);
7649 /* Allow this instruction to replace one of the nops that was
7650 tentatively added to prev_nop_frag. */
7651 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7652 prev_nop_frag_holds
--;
7653 prev_nop_frag_since
++;
7657 method
= get_append_method (ip
, address_expr
, reloc_type
);
7658 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7660 dwarf2_emit_insn (0);
7661 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7662 so "move" the instruction address accordingly.
7664 Also, it doesn't seem appropriate for the assembler to reorder .loc
7665 entries. If this instruction is a branch that we are going to swap
7666 with the previous instruction, the two instructions should be
7667 treated as a unit, and the debug information for both instructions
7668 should refer to the start of the branch sequence. Using the
7669 current position is certainly wrong when swapping a 32-bit branch
7670 and a 16-bit delay slot, since the current position would then be
7671 in the middle of a branch. */
7672 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7674 relax32
= (mips_relax_branch
7675 /* Don't try branch relaxation within .set nomacro, or within
7676 .set noat if we use $at for PIC computations. If it turns
7677 out that the branch was out-of-range, we'll get an error. */
7678 && !mips_opts
.warn_about_macros
7679 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7680 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7681 as they have no complementing branches. */
7682 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7684 if (!HAVE_CODE_COMPRESSION
7687 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7688 && delayed_branch_p (ip
))
7690 relaxed_branch
= TRUE
;
7691 add_relaxed_insn (ip
, (relaxed_branch_length
7693 uncond_branch_p (ip
) ? -1
7694 : branch_likely_p (ip
) ? 1
7697 (AT
, mips_pic
!= NO_PIC
,
7698 uncond_branch_p (ip
),
7699 branch_likely_p (ip
),
7700 pinfo
& INSN_WRITE_GPR_31
,
7702 address_expr
->X_add_symbol
,
7703 address_expr
->X_add_number
);
7704 *reloc_type
= BFD_RELOC_UNUSED
;
7706 else if (mips_opts
.micromips
7708 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7709 || *reloc_type
> BFD_RELOC_UNUSED
)
7710 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7711 /* Don't try branch relaxation when users specify
7712 16-bit/32-bit instructions. */
7713 && !forced_insn_length
)
7715 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7716 && *reloc_type
> BFD_RELOC_UNUSED
);
7717 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7718 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7719 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7720 int nods
= method
== APPEND_ADD_WITH_NOP
;
7721 int al
= pinfo
& INSN_WRITE_GPR_31
;
7722 int length32
= nods
? 8 : 4;
7724 gas_assert (address_expr
!= NULL
);
7725 gas_assert (!mips_relax
.sequence
);
7727 relaxed_branch
= TRUE
;
7729 method
= APPEND_ADD
;
7731 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7732 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7733 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7735 uncond
, compact
, al
, nods
,
7737 address_expr
->X_add_symbol
,
7738 address_expr
->X_add_number
);
7739 *reloc_type
= BFD_RELOC_UNUSED
;
7741 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7743 bfd_boolean require_unextended
;
7744 bfd_boolean require_extended
;
7748 if (forced_insn_length
!= 0)
7750 require_unextended
= forced_insn_length
== 2;
7751 require_extended
= forced_insn_length
== 4;
7755 require_unextended
= (mips_opts
.noautoextend
7756 && !mips_opcode_32bit_p (ip
->insn_mo
));
7757 require_extended
= 0;
7760 /* We need to set up a variant frag. */
7761 gas_assert (address_expr
!= NULL
);
7762 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7763 symbol created by `make_expr_symbol' may not get a necessary
7764 external relocation produced. */
7765 if (address_expr
->X_op
== O_symbol
)
7767 symbol
= address_expr
->X_add_symbol
;
7768 offset
= address_expr
->X_add_number
;
7772 symbol
= make_expr_symbol (address_expr
);
7773 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7776 add_relaxed_insn (ip
, 12, 0,
7778 (*reloc_type
- BFD_RELOC_UNUSED
,
7779 mips_opts
.ase
& ASE_MIPS16E2
,
7782 mips_opts
.warn_about_macros
,
7783 require_unextended
, require_extended
,
7784 delayed_branch_p (&history
[0]),
7785 history
[0].mips16_absolute_jump_p
),
7788 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7790 if (!delayed_branch_p (ip
))
7791 /* Make sure there is enough room to swap this instruction with
7792 a following jump instruction. */
7794 add_fixed_insn (ip
);
7798 if (mips_opts
.mips16
7799 && mips_opts
.noreorder
7800 && delayed_branch_p (&history
[0]))
7801 as_warn (_("extended instruction in delay slot"));
7803 if (mips_relax
.sequence
)
7805 /* If we've reached the end of this frag, turn it into a variant
7806 frag and record the information for the instructions we've
7808 if (frag_room () < 4)
7809 relax_close_frag ();
7810 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7813 if (mips_relax
.sequence
!= 2)
7815 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7816 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7817 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7818 mips_macro_warning
.insns
[0]++;
7820 if (mips_relax
.sequence
!= 1)
7822 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7823 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7824 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7825 mips_macro_warning
.insns
[1]++;
7828 if (mips_opts
.mips16
)
7831 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7833 add_fixed_insn (ip
);
7836 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7838 bfd_reloc_code_real_type final_type
[3];
7839 reloc_howto_type
*howto0
;
7840 reloc_howto_type
*howto
;
7843 /* Perform any necessary conversion to microMIPS relocations
7844 and find out how many relocations there actually are. */
7845 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7846 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7848 /* In a compound relocation, it is the final (outermost)
7849 operator that determines the relocated field. */
7850 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7855 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7856 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7857 bfd_get_reloc_size (howto
),
7859 howto0
&& howto0
->pc_relative
,
7861 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7862 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7864 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7865 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7866 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7868 /* These relocations can have an addend that won't fit in
7869 4 octets for 64bit assembly. */
7871 && ! howto
->partial_inplace
7872 && (reloc_type
[0] == BFD_RELOC_16
7873 || reloc_type
[0] == BFD_RELOC_32
7874 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7875 || reloc_type
[0] == BFD_RELOC_GPREL16
7876 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7877 || reloc_type
[0] == BFD_RELOC_GPREL32
7878 || reloc_type
[0] == BFD_RELOC_64
7879 || reloc_type
[0] == BFD_RELOC_CTOR
7880 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7881 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7882 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7883 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7884 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7885 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7886 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7887 || hi16_reloc_p (reloc_type
[0])
7888 || lo16_reloc_p (reloc_type
[0])))
7889 ip
->fixp
[0]->fx_no_overflow
= 1;
7891 /* These relocations can have an addend that won't fit in 2 octets. */
7892 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7893 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7894 ip
->fixp
[0]->fx_no_overflow
= 1;
7896 if (mips_relax
.sequence
)
7898 if (mips_relax
.first_fixup
== 0)
7899 mips_relax
.first_fixup
= ip
->fixp
[0];
7901 else if (reloc_needs_lo_p (*reloc_type
))
7903 struct mips_hi_fixup
*hi_fixup
;
7905 /* Reuse the last entry if it already has a matching %lo. */
7906 hi_fixup
= mips_hi_fixup_list
;
7908 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7910 hi_fixup
= XNEW (struct mips_hi_fixup
);
7911 hi_fixup
->next
= mips_hi_fixup_list
;
7912 mips_hi_fixup_list
= hi_fixup
;
7914 hi_fixup
->fixp
= ip
->fixp
[0];
7915 hi_fixup
->seg
= now_seg
;
7918 /* Add fixups for the second and third relocations, if given.
7919 Note that the ABI allows the second relocation to be
7920 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7921 moment we only use RSS_UNDEF, but we could add support
7922 for the others if it ever becomes necessary. */
7923 for (i
= 1; i
< 3; i
++)
7924 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7926 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7927 ip
->fixp
[0]->fx_size
, NULL
, 0,
7928 FALSE
, final_type
[i
]);
7930 /* Use fx_tcbit to mark compound relocs. */
7931 ip
->fixp
[0]->fx_tcbit
= 1;
7932 ip
->fixp
[i
]->fx_tcbit
= 1;
7936 /* Update the register mask information. */
7937 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7938 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7943 insert_into_history (0, 1, ip
);
7946 case APPEND_ADD_WITH_NOP
:
7948 struct mips_cl_insn
*nop
;
7950 insert_into_history (0, 1, ip
);
7951 nop
= get_delay_slot_nop (ip
);
7952 add_fixed_insn (nop
);
7953 insert_into_history (0, 1, nop
);
7954 if (mips_relax
.sequence
)
7955 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7959 case APPEND_ADD_COMPACT
:
7960 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7961 if (mips_opts
.mips16
)
7963 ip
->insn_opcode
|= 0x0080;
7964 find_altered_mips16_opcode (ip
);
7966 /* Convert microMIPS instructions. */
7967 else if (mips_opts
.micromips
)
7970 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7971 ip
->insn_opcode
|= 0x0020;
7973 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7974 ip
->insn_opcode
= 0x40e00000;
7975 /* beqz16->beqzc, bnez16->bnezc */
7976 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7978 unsigned long regno
;
7980 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7981 regno
&= MICROMIPSOP_MASK_MD
;
7982 regno
= micromips_to_32_reg_d_map
[regno
];
7983 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7984 | (regno
<< MICROMIPSOP_SH_RS
)
7985 | 0x40a00000) ^ 0x00400000;
7987 /* beqz->beqzc, bnez->bnezc */
7988 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7989 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7990 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7991 | 0x40a00000) ^ 0x00400000;
7992 /* beq $0->beqzc, bne $0->bnezc */
7993 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7994 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7995 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7996 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7997 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7998 | 0x40a00000) ^ 0x00400000;
8001 find_altered_micromips_opcode (ip
);
8006 insert_into_history (0, 1, ip
);
8011 struct mips_cl_insn delay
= history
[0];
8013 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8015 /* Add the delay slot instruction to the end of the
8016 current frag and shrink the fixed part of the
8017 original frag. If the branch occupies the tail of
8018 the latter, move it backwards to cover the gap. */
8019 delay
.frag
->fr_fix
-= branch_disp
;
8020 if (delay
.frag
== ip
->frag
)
8021 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8022 add_fixed_insn (&delay
);
8026 /* If this is not a relaxed branch and we are in the
8027 same frag, then just swap the instructions. */
8028 move_insn (ip
, delay
.frag
, delay
.where
);
8029 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8033 insert_into_history (0, 1, &delay
);
8038 /* If we have just completed an unconditional branch, clear the history. */
8039 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8040 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8044 mips_no_prev_insn ();
8046 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8047 history
[i
].cleared_p
= 1;
8050 /* We need to emit a label at the end of branch-likely macros. */
8051 if (emit_branch_likely_macro
)
8053 emit_branch_likely_macro
= FALSE
;
8054 micromips_add_label ();
8057 /* We just output an insn, so the next one doesn't have a label. */
8058 mips_clear_insn_labels ();
8061 /* Forget that there was any previous instruction or label.
8062 When BRANCH is true, the branch history is also flushed. */
8065 mips_no_prev_insn (void)
8067 prev_nop_frag
= NULL
;
8068 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8069 mips_clear_insn_labels ();
8072 /* This function must be called before we emit something other than
8073 instructions. It is like mips_no_prev_insn except that it inserts
8074 any NOPS that might be needed by previous instructions. */
8077 mips_emit_delays (void)
8079 if (! mips_opts
.noreorder
)
8081 int nops
= nops_for_insn (0, history
, NULL
);
8085 add_fixed_insn (NOP_INSN
);
8086 mips_move_text_labels ();
8089 mips_no_prev_insn ();
8092 /* Start a (possibly nested) noreorder block. */
8095 start_noreorder (void)
8097 if (mips_opts
.noreorder
== 0)
8102 /* None of the instructions before the .set noreorder can be moved. */
8103 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8104 history
[i
].fixed_p
= 1;
8106 /* Insert any nops that might be needed between the .set noreorder
8107 block and the previous instructions. We will later remove any
8108 nops that turn out not to be needed. */
8109 nops
= nops_for_insn (0, history
, NULL
);
8112 if (mips_optimize
!= 0)
8114 /* Record the frag which holds the nop instructions, so
8115 that we can remove them if we don't need them. */
8116 frag_grow (nops
* NOP_INSN_SIZE
);
8117 prev_nop_frag
= frag_now
;
8118 prev_nop_frag_holds
= nops
;
8119 prev_nop_frag_required
= 0;
8120 prev_nop_frag_since
= 0;
8123 for (; nops
> 0; --nops
)
8124 add_fixed_insn (NOP_INSN
);
8126 /* Move on to a new frag, so that it is safe to simply
8127 decrease the size of prev_nop_frag. */
8128 frag_wane (frag_now
);
8130 mips_move_text_labels ();
8132 mips_mark_labels ();
8133 mips_clear_insn_labels ();
8135 mips_opts
.noreorder
++;
8136 mips_any_noreorder
= 1;
8139 /* End a nested noreorder block. */
8142 end_noreorder (void)
8144 mips_opts
.noreorder
--;
8145 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8147 /* Commit to inserting prev_nop_frag_required nops and go back to
8148 handling nop insertion the .set reorder way. */
8149 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8151 insert_into_history (prev_nop_frag_since
,
8152 prev_nop_frag_required
, NOP_INSN
);
8153 prev_nop_frag
= NULL
;
8157 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8158 higher bits unset. */
8161 normalize_constant_expr (expressionS
*ex
)
8163 if (ex
->X_op
== O_constant
8164 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8165 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8169 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8170 all higher bits unset. */
8173 normalize_address_expr (expressionS
*ex
)
8175 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8176 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8177 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8178 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8182 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8183 Return true if the match was successful.
8185 OPCODE_EXTRA is a value that should be ORed into the opcode
8186 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8187 there are more alternatives after OPCODE and SOFT_MATCH is
8188 as for mips_arg_info. */
8191 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8192 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8193 bfd_boolean lax_match
, bfd_boolean complete_p
)
8196 struct mips_arg_info arg
;
8197 const struct mips_operand
*operand
;
8200 imm_expr
.X_op
= O_absent
;
8201 offset_expr
.X_op
= O_absent
;
8202 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8203 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8204 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8206 create_insn (insn
, opcode
);
8207 /* When no opcode suffix is specified, assume ".xyzw". */
8208 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8209 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8211 insn
->insn_opcode
|= opcode_extra
;
8212 memset (&arg
, 0, sizeof (arg
));
8216 arg
.last_regno
= ILLEGAL_REG
;
8217 arg
.dest_regno
= ILLEGAL_REG
;
8218 arg
.lax_match
= lax_match
;
8219 for (args
= opcode
->args
;; ++args
)
8221 if (arg
.token
->type
== OT_END
)
8223 /* Handle unary instructions in which only one operand is given.
8224 The source is then the same as the destination. */
8225 if (arg
.opnum
== 1 && *args
== ',')
8227 operand
= (mips_opts
.micromips
8228 ? decode_micromips_operand (args
+ 1)
8229 : decode_mips_operand (args
+ 1));
8230 if (operand
&& mips_optional_operand_p (operand
))
8238 /* Treat elided base registers as $0. */
8239 if (strcmp (args
, "(b)") == 0)
8247 /* The register suffix is optional. */
8252 /* Fail the match if there were too few operands. */
8256 /* Successful match. */
8259 clear_insn_error ();
8260 if (arg
.dest_regno
== arg
.last_regno
8261 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8265 (0, _("source and destination must be different"));
8266 else if (arg
.last_regno
== 31)
8268 (0, _("a destination register must be supplied"));
8270 else if (arg
.last_regno
== 31
8271 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8272 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8273 set_insn_error (0, _("the source register must not be $31"));
8274 check_completed_insn (&arg
);
8278 /* Fail the match if the line has too many operands. */
8282 /* Handle characters that need to match exactly. */
8283 if (*args
== '(' || *args
== ')' || *args
== ',')
8285 if (match_char (&arg
, *args
))
8292 if (arg
.token
->type
== OT_DOUBLE_CHAR
8293 && arg
.token
->u
.ch
== *args
)
8301 /* Handle special macro operands. Work out the properties of
8310 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8314 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8323 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8327 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8331 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8337 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8339 imm_expr
.X_op
= O_constant
;
8341 normalize_constant_expr (&imm_expr
);
8345 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8347 /* Assume that the offset has been elided and that what
8348 we saw was a base register. The match will fail later
8349 if that assumption turns out to be wrong. */
8350 offset_expr
.X_op
= O_constant
;
8351 offset_expr
.X_add_number
= 0;
8355 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8357 normalize_address_expr (&offset_expr
);
8362 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8368 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8374 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8380 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8386 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8390 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8394 gas_assert (mips_opts
.micromips
);
8400 if (!forced_insn_length
)
8401 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8403 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8405 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8411 operand
= (mips_opts
.micromips
8412 ? decode_micromips_operand (args
)
8413 : decode_mips_operand (args
));
8417 /* Skip prefixes. */
8418 if (*args
== '+' || *args
== 'm' || *args
== '-')
8421 if (mips_optional_operand_p (operand
)
8423 && (arg
.token
[0].type
!= OT_REG
8424 || arg
.token
[1].type
== OT_END
))
8426 /* Assume that the register has been elided and is the
8427 same as the first operand. */
8432 if (!match_operand (&arg
, operand
))
8437 /* Like match_insn, but for MIPS16. */
8440 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8441 struct mips_operand_token
*tokens
)
8444 const struct mips_operand
*operand
;
8445 const struct mips_operand
*ext_operand
;
8446 bfd_boolean pcrel
= FALSE
;
8447 int required_insn_length
;
8448 struct mips_arg_info arg
;
8451 if (forced_insn_length
)
8452 required_insn_length
= forced_insn_length
;
8453 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8454 required_insn_length
= 2;
8456 required_insn_length
= 0;
8458 create_insn (insn
, opcode
);
8459 imm_expr
.X_op
= O_absent
;
8460 offset_expr
.X_op
= O_absent
;
8461 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8462 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8463 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8466 memset (&arg
, 0, sizeof (arg
));
8470 arg
.last_regno
= ILLEGAL_REG
;
8471 arg
.dest_regno
= ILLEGAL_REG
;
8473 for (args
= opcode
->args
;; ++args
)
8477 if (arg
.token
->type
== OT_END
)
8481 /* Handle unary instructions in which only one operand is given.
8482 The source is then the same as the destination. */
8483 if (arg
.opnum
== 1 && *args
== ',')
8485 operand
= decode_mips16_operand (args
[1], FALSE
);
8486 if (operand
&& mips_optional_operand_p (operand
))
8494 /* Fail the match if there were too few operands. */
8498 /* Successful match. Stuff the immediate value in now, if
8500 clear_insn_error ();
8501 if (opcode
->pinfo
== INSN_MACRO
)
8503 gas_assert (relax_char
== 0 || relax_char
== 'p');
8504 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8507 && offset_expr
.X_op
== O_constant
8509 && calculate_reloc (*offset_reloc
,
8510 offset_expr
.X_add_number
,
8513 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8514 required_insn_length
, &insn
->insn_opcode
);
8515 offset_expr
.X_op
= O_absent
;
8516 *offset_reloc
= BFD_RELOC_UNUSED
;
8518 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8520 if (required_insn_length
== 2)
8521 set_insn_error (0, _("invalid unextended operand value"));
8522 else if (!mips_opcode_32bit_p (opcode
))
8524 forced_insn_length
= 4;
8525 insn
->insn_opcode
|= MIPS16_EXTEND
;
8528 else if (relax_char
)
8529 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8531 check_completed_insn (&arg
);
8535 /* Fail the match if the line has too many operands. */
8539 /* Handle characters that need to match exactly. */
8540 if (*args
== '(' || *args
== ')' || *args
== ',')
8542 if (match_char (&arg
, *args
))
8562 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8564 imm_expr
.X_op
= O_constant
;
8566 normalize_constant_expr (&imm_expr
);
8571 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8575 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8579 if (operand
->type
== OP_PCREL
)
8583 ext_operand
= decode_mips16_operand (c
, TRUE
);
8584 if (operand
!= ext_operand
)
8586 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8588 offset_expr
.X_op
= O_constant
;
8589 offset_expr
.X_add_number
= 0;
8594 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8597 /* '8' is used for SLTI(U) and has traditionally not
8598 been allowed to take relocation operators. */
8599 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8600 && (ext_operand
->size
!= 16 || c
== '8'))
8602 match_not_constant (&arg
);
8606 if (offset_expr
.X_op
== O_big
)
8608 match_out_of_range (&arg
);
8617 if (mips_optional_operand_p (operand
)
8619 && (arg
.token
[0].type
!= OT_REG
8620 || arg
.token
[1].type
== OT_END
))
8622 /* Assume that the register has been elided and is the
8623 same as the first operand. */
8628 if (!match_operand (&arg
, operand
))
8633 /* Record that the current instruction is invalid for the current ISA. */
8636 match_invalid_for_isa (void)
8639 (0, _("opcode not supported on this processor: %s (%s)"),
8640 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8641 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8644 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8645 Return true if a definite match or failure was found, storing any match
8646 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8647 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8648 tried and failed to match under normal conditions and now want to try a
8649 more relaxed match. */
8652 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8653 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8654 int opcode_extra
, bfd_boolean lax_match
)
8656 const struct mips_opcode
*opcode
;
8657 const struct mips_opcode
*invalid_delay_slot
;
8658 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8660 /* Search for a match, ignoring alternatives that don't satisfy the
8661 current ISA or forced_length. */
8662 invalid_delay_slot
= 0;
8663 seen_valid_for_isa
= FALSE
;
8664 seen_valid_for_size
= FALSE
;
8668 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8669 if (is_opcode_valid (opcode
))
8671 seen_valid_for_isa
= TRUE
;
8672 if (is_size_valid (opcode
))
8674 bfd_boolean delay_slot_ok
;
8676 seen_valid_for_size
= TRUE
;
8677 delay_slot_ok
= is_delay_slot_valid (opcode
);
8678 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8679 lax_match
, delay_slot_ok
))
8683 if (!invalid_delay_slot
)
8684 invalid_delay_slot
= opcode
;
8693 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8695 /* If the only matches we found had the wrong length for the delay slot,
8696 pick the first such match. We'll issue an appropriate warning later. */
8697 if (invalid_delay_slot
)
8699 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8705 /* Handle the case where we didn't try to match an instruction because
8706 all the alternatives were incompatible with the current ISA. */
8707 if (!seen_valid_for_isa
)
8709 match_invalid_for_isa ();
8713 /* Handle the case where we didn't try to match an instruction because
8714 all the alternatives were of the wrong size. */
8715 if (!seen_valid_for_size
)
8717 if (mips_opts
.insn32
)
8718 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8721 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8722 8 * forced_insn_length
);
8729 /* Like match_insns, but for MIPS16. */
8732 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8733 struct mips_operand_token
*tokens
)
8735 const struct mips_opcode
*opcode
;
8736 bfd_boolean seen_valid_for_isa
;
8737 bfd_boolean seen_valid_for_size
;
8739 /* Search for a match, ignoring alternatives that don't satisfy the
8740 current ISA. There are no separate entries for extended forms so
8741 we deal with forced_length later. */
8742 seen_valid_for_isa
= FALSE
;
8743 seen_valid_for_size
= FALSE
;
8747 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8748 if (is_opcode_valid_16 (opcode
))
8750 seen_valid_for_isa
= TRUE
;
8751 if (is_size_valid_16 (opcode
))
8753 seen_valid_for_size
= TRUE
;
8754 if (match_mips16_insn (insn
, opcode
, tokens
))
8760 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8761 && strcmp (opcode
->name
, first
->name
) == 0);
8763 /* Handle the case where we didn't try to match an instruction because
8764 all the alternatives were incompatible with the current ISA. */
8765 if (!seen_valid_for_isa
)
8767 match_invalid_for_isa ();
8771 /* Handle the case where we didn't try to match an instruction because
8772 all the alternatives were of the wrong size. */
8773 if (!seen_valid_for_size
)
8775 if (forced_insn_length
== 2)
8777 (0, _("unrecognized unextended version of MIPS16 opcode"));
8780 (0, _("unrecognized extended version of MIPS16 opcode"));
8787 /* Set up global variables for the start of a new macro. */
8792 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8793 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8794 sizeof (mips_macro_warning
.first_insn_sizes
));
8795 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8796 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8797 && delayed_branch_p (&history
[0]));
8799 && history
[0].frag
->fr_type
== rs_machine_dependent
8800 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8801 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8802 mips_macro_warning
.delay_slot_length
= 0;
8804 switch (history
[0].insn_mo
->pinfo2
8805 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8807 case INSN2_BRANCH_DELAY_32BIT
:
8808 mips_macro_warning
.delay_slot_length
= 4;
8810 case INSN2_BRANCH_DELAY_16BIT
:
8811 mips_macro_warning
.delay_slot_length
= 2;
8814 mips_macro_warning
.delay_slot_length
= 0;
8817 mips_macro_warning
.first_frag
= NULL
;
8820 /* Given that a macro is longer than one instruction or of the wrong size,
8821 return the appropriate warning for it. Return null if no warning is
8822 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8823 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8824 and RELAX_NOMACRO. */
8827 macro_warning (relax_substateT subtype
)
8829 if (subtype
& RELAX_DELAY_SLOT
)
8830 return _("macro instruction expanded into multiple instructions"
8831 " in a branch delay slot");
8832 else if (subtype
& RELAX_NOMACRO
)
8833 return _("macro instruction expanded into multiple instructions");
8834 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8835 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8836 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8837 ? _("macro instruction expanded into a wrong size instruction"
8838 " in a 16-bit branch delay slot")
8839 : _("macro instruction expanded into a wrong size instruction"
8840 " in a 32-bit branch delay slot"));
8845 /* Finish up a macro. Emit warnings as appropriate. */
8850 /* Relaxation warning flags. */
8851 relax_substateT subtype
= 0;
8853 /* Check delay slot size requirements. */
8854 if (mips_macro_warning
.delay_slot_length
== 2)
8855 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8856 if (mips_macro_warning
.delay_slot_length
!= 0)
8858 if (mips_macro_warning
.delay_slot_length
8859 != mips_macro_warning
.first_insn_sizes
[0])
8860 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8861 if (mips_macro_warning
.delay_slot_length
8862 != mips_macro_warning
.first_insn_sizes
[1])
8863 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8866 /* Check instruction count requirements. */
8867 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8869 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8870 subtype
|= RELAX_SECOND_LONGER
;
8871 if (mips_opts
.warn_about_macros
)
8872 subtype
|= RELAX_NOMACRO
;
8873 if (mips_macro_warning
.delay_slot_p
)
8874 subtype
|= RELAX_DELAY_SLOT
;
8877 /* If both alternatives fail to fill a delay slot correctly,
8878 emit the warning now. */
8879 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8880 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8885 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8886 | RELAX_DELAY_SLOT_SIZE_FIRST
8887 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8888 msg
= macro_warning (s
);
8890 as_warn ("%s", msg
);
8894 /* If both implementations are longer than 1 instruction, then emit the
8896 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8901 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8902 msg
= macro_warning (s
);
8904 as_warn ("%s", msg
);
8908 /* If any flags still set, then one implementation might need a warning
8909 and the other either will need one of a different kind or none at all.
8910 Pass any remaining flags over to relaxation. */
8911 if (mips_macro_warning
.first_frag
!= NULL
)
8912 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8915 /* Instruction operand formats used in macros that vary between
8916 standard MIPS and microMIPS code. */
8918 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8919 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8920 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8921 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8922 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8923 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8924 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8925 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8927 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8928 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8929 : cop12_fmt[mips_opts.micromips])
8930 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8931 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8932 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8933 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8934 : mem12_fmt[mips_opts.micromips])
8935 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8936 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8937 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8939 /* Read a macro's relocation codes from *ARGS and store them in *R.
8940 The first argument in *ARGS will be either the code for a single
8941 relocation or -1 followed by the three codes that make up a
8942 composite relocation. */
8945 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8949 next
= va_arg (*args
, int);
8951 r
[0] = (bfd_reloc_code_real_type
) next
;
8954 for (i
= 0; i
< 3; i
++)
8955 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8956 /* This function is only used for 16-bit relocation fields.
8957 To make the macro code simpler, treat an unrelocated value
8958 in the same way as BFD_RELOC_LO16. */
8959 if (r
[0] == BFD_RELOC_UNUSED
)
8960 r
[0] = BFD_RELOC_LO16
;
8964 /* Build an instruction created by a macro expansion. This is passed
8965 a pointer to the count of instructions created so far, an
8966 expression, the name of the instruction to build, an operand format
8967 string, and corresponding arguments. */
8970 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8972 const struct mips_opcode
*mo
= NULL
;
8973 bfd_reloc_code_real_type r
[3];
8974 const struct mips_opcode
*amo
;
8975 const struct mips_operand
*operand
;
8976 struct hash_control
*hash
;
8977 struct mips_cl_insn insn
;
8981 va_start (args
, fmt
);
8983 if (mips_opts
.mips16
)
8985 mips16_macro_build (ep
, name
, fmt
, &args
);
8990 r
[0] = BFD_RELOC_UNUSED
;
8991 r
[1] = BFD_RELOC_UNUSED
;
8992 r
[2] = BFD_RELOC_UNUSED
;
8993 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8994 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8996 gas_assert (strcmp (name
, amo
->name
) == 0);
9000 /* Search until we get a match for NAME. It is assumed here that
9001 macros will never generate MDMX, MIPS-3D, or MT instructions.
9002 We try to match an instruction that fulfills the branch delay
9003 slot instruction length requirement (if any) of the previous
9004 instruction. While doing this we record the first instruction
9005 seen that matches all the other conditions and use it anyway
9006 if the requirement cannot be met; we will issue an appropriate
9007 warning later on. */
9008 if (strcmp (fmt
, amo
->args
) == 0
9009 && amo
->pinfo
!= INSN_MACRO
9010 && is_opcode_valid (amo
)
9011 && is_size_valid (amo
))
9013 if (is_delay_slot_valid (amo
))
9023 gas_assert (amo
->name
);
9025 while (strcmp (name
, amo
->name
) == 0);
9028 create_insn (&insn
, mo
);
9041 macro_read_relocs (&args
, r
);
9042 gas_assert (*r
== BFD_RELOC_GPREL16
9043 || *r
== BFD_RELOC_MIPS_HIGHER
9044 || *r
== BFD_RELOC_HI16_S
9045 || *r
== BFD_RELOC_LO16
9046 || *r
== BFD_RELOC_MIPS_GOT_OFST
9047 || (mips_opts
.micromips
9048 && (*r
== BFD_RELOC_16
9049 || *r
== BFD_RELOC_MIPS_GOT16
9050 || *r
== BFD_RELOC_MIPS_CALL16
9051 || *r
== BFD_RELOC_MIPS_GOT_HI16
9052 || *r
== BFD_RELOC_MIPS_GOT_LO16
9053 || *r
== BFD_RELOC_MIPS_CALL_HI16
9054 || *r
== BFD_RELOC_MIPS_CALL_LO16
9055 || *r
== BFD_RELOC_MIPS_SUB
9056 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9057 || *r
== BFD_RELOC_MIPS_HIGHEST
9058 || *r
== BFD_RELOC_MIPS_GOT_DISP
9059 || *r
== BFD_RELOC_MIPS_TLS_GD
9060 || *r
== BFD_RELOC_MIPS_TLS_LDM
9061 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9062 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9063 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9064 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9065 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9069 macro_read_relocs (&args
, r
);
9073 macro_read_relocs (&args
, r
);
9074 gas_assert (ep
!= NULL
9075 && (ep
->X_op
== O_constant
9076 || (ep
->X_op
== O_symbol
9077 && (*r
== BFD_RELOC_MIPS_HIGHEST
9078 || *r
== BFD_RELOC_HI16_S
9079 || *r
== BFD_RELOC_HI16
9080 || *r
== BFD_RELOC_GPREL16
9081 || *r
== BFD_RELOC_MIPS_GOT_HI16
9082 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9086 gas_assert (ep
!= NULL
);
9089 * This allows macro() to pass an immediate expression for
9090 * creating short branches without creating a symbol.
9092 * We don't allow branch relaxation for these branches, as
9093 * they should only appear in ".set nomacro" anyway.
9095 if (ep
->X_op
== O_constant
)
9097 /* For microMIPS we always use relocations for branches.
9098 So we should not resolve immediate values. */
9099 gas_assert (!mips_opts
.micromips
);
9101 if ((ep
->X_add_number
& 3) != 0)
9102 as_bad (_("branch to misaligned address (0x%lx)"),
9103 (unsigned long) ep
->X_add_number
);
9104 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9105 as_bad (_("branch address range overflow (0x%lx)"),
9106 (unsigned long) ep
->X_add_number
);
9107 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9111 *r
= BFD_RELOC_16_PCREL_S2
;
9115 gas_assert (ep
!= NULL
);
9116 *r
= BFD_RELOC_MIPS_JMP
;
9120 operand
= (mips_opts
.micromips
9121 ? decode_micromips_operand (fmt
)
9122 : decode_mips_operand (fmt
));
9126 uval
= va_arg (args
, int);
9127 if (operand
->type
== OP_CLO_CLZ_DEST
)
9128 uval
|= (uval
<< 5);
9129 insn_insert_operand (&insn
, operand
, uval
);
9131 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9137 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9139 append_insn (&insn
, ep
, r
, TRUE
);
9143 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9146 struct mips_opcode
*mo
;
9147 struct mips_cl_insn insn
;
9148 const struct mips_operand
*operand
;
9149 bfd_reloc_code_real_type r
[3]
9150 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9152 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9154 gas_assert (strcmp (name
, mo
->name
) == 0);
9156 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9159 gas_assert (mo
->name
);
9160 gas_assert (strcmp (name
, mo
->name
) == 0);
9163 create_insn (&insn
, mo
);
9200 gas_assert (ep
!= NULL
);
9202 if (ep
->X_op
!= O_constant
)
9203 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9204 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9206 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9208 *r
= BFD_RELOC_UNUSED
;
9214 operand
= decode_mips16_operand (c
, FALSE
);
9218 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9223 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9225 append_insn (&insn
, ep
, r
, TRUE
);
9229 * Generate a "jalr" instruction with a relocation hint to the called
9230 * function. This occurs in NewABI PIC code.
9233 macro_build_jalr (expressionS
*ep
, int cprestore
)
9235 static const bfd_reloc_code_real_type jalr_relocs
[2]
9236 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9237 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9241 if (MIPS_JALR_HINT_P (ep
))
9246 if (mips_opts
.micromips
)
9248 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9249 ? "jalr" : "jalrs");
9250 if (MIPS_JALR_HINT_P (ep
)
9252 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9253 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9255 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9258 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9259 if (MIPS_JALR_HINT_P (ep
))
9260 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9264 * Generate a "lui" instruction.
9267 macro_build_lui (expressionS
*ep
, int regnum
)
9269 gas_assert (! mips_opts
.mips16
);
9271 if (ep
->X_op
!= O_constant
)
9273 gas_assert (ep
->X_op
== O_symbol
);
9274 /* _gp_disp is a special case, used from s_cpload.
9275 __gnu_local_gp is used if mips_no_shared. */
9276 gas_assert (mips_pic
== NO_PIC
9278 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9279 || (! mips_in_shared
9280 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9281 "__gnu_local_gp") == 0));
9284 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9287 /* Generate a sequence of instructions to do a load or store from a constant
9288 offset off of a base register (breg) into/from a target register (treg),
9289 using AT if necessary. */
9291 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9292 int treg
, int breg
, int dbl
)
9294 gas_assert (ep
->X_op
== O_constant
);
9296 /* Sign-extending 32-bit constants makes their handling easier. */
9298 normalize_constant_expr (ep
);
9300 /* Right now, this routine can only handle signed 32-bit constants. */
9301 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9302 as_warn (_("operand overflow"));
9304 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9306 /* Signed 16-bit offset will fit in the op. Easy! */
9307 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9311 /* 32-bit offset, need multiple instructions and AT, like:
9312 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9313 addu $tempreg,$tempreg,$breg
9314 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9315 to handle the complete offset. */
9316 macro_build_lui (ep
, AT
);
9317 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9318 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9321 as_bad (_("macro used $at after \".set noat\""));
9326 * Generates code to set the $at register to true (one)
9327 * if reg is less than the immediate expression.
9330 set_at (int reg
, int unsignedp
)
9332 if (imm_expr
.X_add_number
>= -0x8000
9333 && imm_expr
.X_add_number
< 0x8000)
9334 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9335 AT
, reg
, BFD_RELOC_LO16
);
9338 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9339 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9343 /* Count the leading zeroes by performing a binary chop. This is a
9344 bulky bit of source, but performance is a LOT better for the
9345 majority of values than a simple loop to count the bits:
9346 for (lcnt = 0; (lcnt < 32); lcnt++)
9347 if ((v) & (1 << (31 - lcnt)))
9349 However it is not code size friendly, and the gain will drop a bit
9350 on certain cached systems.
9352 #define COUNT_TOP_ZEROES(v) \
9353 (((v) & ~0xffff) == 0 \
9354 ? ((v) & ~0xff) == 0 \
9355 ? ((v) & ~0xf) == 0 \
9356 ? ((v) & ~0x3) == 0 \
9357 ? ((v) & ~0x1) == 0 \
9362 : ((v) & ~0x7) == 0 \
9365 : ((v) & ~0x3f) == 0 \
9366 ? ((v) & ~0x1f) == 0 \
9369 : ((v) & ~0x7f) == 0 \
9372 : ((v) & ~0xfff) == 0 \
9373 ? ((v) & ~0x3ff) == 0 \
9374 ? ((v) & ~0x1ff) == 0 \
9377 : ((v) & ~0x7ff) == 0 \
9380 : ((v) & ~0x3fff) == 0 \
9381 ? ((v) & ~0x1fff) == 0 \
9384 : ((v) & ~0x7fff) == 0 \
9387 : ((v) & ~0xffffff) == 0 \
9388 ? ((v) & ~0xfffff) == 0 \
9389 ? ((v) & ~0x3ffff) == 0 \
9390 ? ((v) & ~0x1ffff) == 0 \
9393 : ((v) & ~0x7ffff) == 0 \
9396 : ((v) & ~0x3fffff) == 0 \
9397 ? ((v) & ~0x1fffff) == 0 \
9400 : ((v) & ~0x7fffff) == 0 \
9403 : ((v) & ~0xfffffff) == 0 \
9404 ? ((v) & ~0x3ffffff) == 0 \
9405 ? ((v) & ~0x1ffffff) == 0 \
9408 : ((v) & ~0x7ffffff) == 0 \
9411 : ((v) & ~0x3fffffff) == 0 \
9412 ? ((v) & ~0x1fffffff) == 0 \
9415 : ((v) & ~0x7fffffff) == 0 \
9420 * This routine generates the least number of instructions necessary to load
9421 * an absolute expression value into a register.
9424 load_register (int reg
, expressionS
*ep
, int dbl
)
9427 expressionS hi32
, lo32
;
9429 if (ep
->X_op
!= O_big
)
9431 gas_assert (ep
->X_op
== O_constant
);
9433 /* Sign-extending 32-bit constants makes their handling easier. */
9435 normalize_constant_expr (ep
);
9437 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9439 /* We can handle 16 bit signed values with an addiu to
9440 $zero. No need to ever use daddiu here, since $zero and
9441 the result are always correct in 32 bit mode. */
9442 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9445 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9447 /* We can handle 16 bit unsigned values with an ori to
9449 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9452 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9454 /* 32 bit values require an lui. */
9455 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9456 if ((ep
->X_add_number
& 0xffff) != 0)
9457 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9462 /* The value is larger than 32 bits. */
9464 if (!dbl
|| GPR_SIZE
== 32)
9468 sprintf_vma (value
, ep
->X_add_number
);
9469 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9470 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9474 if (ep
->X_op
!= O_big
)
9477 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9478 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9479 hi32
.X_add_number
&= 0xffffffff;
9481 lo32
.X_add_number
&= 0xffffffff;
9485 gas_assert (ep
->X_add_number
> 2);
9486 if (ep
->X_add_number
== 3)
9487 generic_bignum
[3] = 0;
9488 else if (ep
->X_add_number
> 4)
9489 as_bad (_("number larger than 64 bits"));
9490 lo32
.X_op
= O_constant
;
9491 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9492 hi32
.X_op
= O_constant
;
9493 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9496 if (hi32
.X_add_number
== 0)
9501 unsigned long hi
, lo
;
9503 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9505 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9507 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9510 if (lo32
.X_add_number
& 0x80000000)
9512 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9513 if (lo32
.X_add_number
& 0xffff)
9514 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9519 /* Check for 16bit shifted constant. We know that hi32 is
9520 non-zero, so start the mask on the first bit of the hi32
9525 unsigned long himask
, lomask
;
9529 himask
= 0xffff >> (32 - shift
);
9530 lomask
= (0xffff << shift
) & 0xffffffff;
9534 himask
= 0xffff << (shift
- 32);
9537 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9538 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9542 tmp
.X_op
= O_constant
;
9544 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9545 | (lo32
.X_add_number
>> shift
));
9547 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9548 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9549 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9550 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9555 while (shift
<= (64 - 16));
9557 /* Find the bit number of the lowest one bit, and store the
9558 shifted value in hi/lo. */
9559 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9560 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9564 while ((lo
& 1) == 0)
9569 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9575 while ((hi
& 1) == 0)
9584 /* Optimize if the shifted value is a (power of 2) - 1. */
9585 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9586 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9588 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9593 /* This instruction will set the register to be all
9595 tmp
.X_op
= O_constant
;
9596 tmp
.X_add_number
= (offsetT
) -1;
9597 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9601 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9602 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9604 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9605 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9610 /* Sign extend hi32 before calling load_register, because we can
9611 generally get better code when we load a sign extended value. */
9612 if ((hi32
.X_add_number
& 0x80000000) != 0)
9613 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9614 load_register (reg
, &hi32
, 0);
9617 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9621 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9629 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9631 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9632 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9638 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9642 mid16
.X_add_number
>>= 16;
9643 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9644 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9647 if ((lo32
.X_add_number
& 0xffff) != 0)
9648 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9652 load_delay_nop (void)
9654 if (!gpr_interlocks
)
9655 macro_build (NULL
, "nop", "");
9658 /* Load an address into a register. */
9661 load_address (int reg
, expressionS
*ep
, int *used_at
)
9663 if (ep
->X_op
!= O_constant
9664 && ep
->X_op
!= O_symbol
)
9666 as_bad (_("expression too complex"));
9667 ep
->X_op
= O_constant
;
9670 if (ep
->X_op
== O_constant
)
9672 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9676 if (mips_pic
== NO_PIC
)
9678 /* If this is a reference to a GP relative symbol, we want
9679 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9681 lui $reg,<sym> (BFD_RELOC_HI16_S)
9682 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9683 If we have an addend, we always use the latter form.
9685 With 64bit address space and a usable $at we want
9686 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9687 lui $at,<sym> (BFD_RELOC_HI16_S)
9688 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9689 daddiu $at,<sym> (BFD_RELOC_LO16)
9693 If $at is already in use, we use a path which is suboptimal
9694 on superscalar processors.
9695 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9696 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9698 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9700 daddiu $reg,<sym> (BFD_RELOC_LO16)
9702 For GP relative symbols in 64bit address space we can use
9703 the same sequence as in 32bit address space. */
9704 if (HAVE_64BIT_SYMBOLS
)
9706 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9707 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9709 relax_start (ep
->X_add_symbol
);
9710 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9711 mips_gp_register
, BFD_RELOC_GPREL16
);
9715 if (*used_at
== 0 && mips_opts
.at
)
9717 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9718 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9719 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9720 BFD_RELOC_MIPS_HIGHER
);
9721 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9722 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9723 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9728 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9729 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9730 BFD_RELOC_MIPS_HIGHER
);
9731 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9732 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9733 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9734 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9737 if (mips_relax
.sequence
)
9742 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9743 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9745 relax_start (ep
->X_add_symbol
);
9746 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9747 mips_gp_register
, BFD_RELOC_GPREL16
);
9750 macro_build_lui (ep
, reg
);
9751 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9752 reg
, reg
, BFD_RELOC_LO16
);
9753 if (mips_relax
.sequence
)
9757 else if (!mips_big_got
)
9761 /* If this is a reference to an external symbol, we want
9762 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9764 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9766 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9767 If there is a constant, it must be added in after.
9769 If we have NewABI, we want
9770 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9771 unless we're referencing a global symbol with a non-zero
9772 offset, in which case cst must be added separately. */
9775 if (ep
->X_add_number
)
9777 ex
.X_add_number
= ep
->X_add_number
;
9778 ep
->X_add_number
= 0;
9779 relax_start (ep
->X_add_symbol
);
9780 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9781 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9782 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9783 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9784 ex
.X_op
= O_constant
;
9785 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9786 reg
, reg
, BFD_RELOC_LO16
);
9787 ep
->X_add_number
= ex
.X_add_number
;
9790 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9791 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9792 if (mips_relax
.sequence
)
9797 ex
.X_add_number
= ep
->X_add_number
;
9798 ep
->X_add_number
= 0;
9799 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9800 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9802 relax_start (ep
->X_add_symbol
);
9804 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9808 if (ex
.X_add_number
!= 0)
9810 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9811 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9812 ex
.X_op
= O_constant
;
9813 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9814 reg
, reg
, BFD_RELOC_LO16
);
9818 else if (mips_big_got
)
9822 /* This is the large GOT case. If this is a reference to an
9823 external symbol, we want
9824 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9826 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9828 Otherwise, for a reference to a local symbol in old ABI, we want
9829 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9831 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9832 If there is a constant, it must be added in after.
9834 In the NewABI, for local symbols, with or without offsets, we want:
9835 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9836 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9840 ex
.X_add_number
= ep
->X_add_number
;
9841 ep
->X_add_number
= 0;
9842 relax_start (ep
->X_add_symbol
);
9843 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9844 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9845 reg
, reg
, mips_gp_register
);
9846 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9847 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9848 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9849 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9850 else if (ex
.X_add_number
)
9852 ex
.X_op
= O_constant
;
9853 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9857 ep
->X_add_number
= ex
.X_add_number
;
9859 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9860 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9861 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9862 BFD_RELOC_MIPS_GOT_OFST
);
9867 ex
.X_add_number
= ep
->X_add_number
;
9868 ep
->X_add_number
= 0;
9869 relax_start (ep
->X_add_symbol
);
9870 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9871 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9872 reg
, reg
, mips_gp_register
);
9873 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9874 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9876 if (reg_needs_delay (mips_gp_register
))
9878 /* We need a nop before loading from $gp. This special
9879 check is required because the lui which starts the main
9880 instruction stream does not refer to $gp, and so will not
9881 insert the nop which may be required. */
9882 macro_build (NULL
, "nop", "");
9884 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9885 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9887 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9891 if (ex
.X_add_number
!= 0)
9893 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9894 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9895 ex
.X_op
= O_constant
;
9896 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9904 if (!mips_opts
.at
&& *used_at
== 1)
9905 as_bad (_("macro used $at after \".set noat\""));
9908 /* Move the contents of register SOURCE into register DEST. */
9911 move_register (int dest
, int source
)
9913 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9914 instruction specifically requires a 32-bit one. */
9915 if (mips_opts
.micromips
9916 && !mips_opts
.insn32
9917 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9918 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9920 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9923 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9924 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9925 The two alternatives are:
9927 Global symbol Local symbol
9928 ------------- ------------
9929 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9931 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9933 load_got_offset emits the first instruction and add_got_offset
9934 emits the second for a 16-bit offset or add_got_offset_hilo emits
9935 a sequence to add a 32-bit offset using a scratch register. */
9938 load_got_offset (int dest
, expressionS
*local
)
9943 global
.X_add_number
= 0;
9945 relax_start (local
->X_add_symbol
);
9946 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9947 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9949 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9950 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9955 add_got_offset (int dest
, expressionS
*local
)
9959 global
.X_op
= O_constant
;
9960 global
.X_op_symbol
= NULL
;
9961 global
.X_add_symbol
= NULL
;
9962 global
.X_add_number
= local
->X_add_number
;
9964 relax_start (local
->X_add_symbol
);
9965 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9966 dest
, dest
, BFD_RELOC_LO16
);
9968 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9973 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9976 int hold_mips_optimize
;
9978 global
.X_op
= O_constant
;
9979 global
.X_op_symbol
= NULL
;
9980 global
.X_add_symbol
= NULL
;
9981 global
.X_add_number
= local
->X_add_number
;
9983 relax_start (local
->X_add_symbol
);
9984 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9986 /* Set mips_optimize around the lui instruction to avoid
9987 inserting an unnecessary nop after the lw. */
9988 hold_mips_optimize
= mips_optimize
;
9990 macro_build_lui (&global
, tmp
);
9991 mips_optimize
= hold_mips_optimize
;
9992 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9995 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9998 /* Emit a sequence of instructions to emulate a branch likely operation.
9999 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10000 is its complementing branch with the original condition negated.
10001 CALL is set if the original branch specified the link operation.
10002 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10004 Code like this is produced in the noreorder mode:
10009 delay slot (executed only if branch taken)
10012 or, if CALL is set:
10017 delay slot (executed only if branch taken)
10020 In the reorder mode the delay slot would be filled with a nop anyway,
10021 so code produced is simply:
10026 This function is used when producing code for the microMIPS ASE that
10027 does not implement branch likely instructions in hardware. */
10030 macro_build_branch_likely (const char *br
, const char *brneg
,
10031 int call
, expressionS
*ep
, const char *fmt
,
10032 unsigned int sreg
, unsigned int treg
)
10034 int noreorder
= mips_opts
.noreorder
;
10037 gas_assert (mips_opts
.micromips
);
10038 start_noreorder ();
10041 micromips_label_expr (&expr1
);
10042 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10043 macro_build (NULL
, "nop", "");
10044 macro_build (ep
, call
? "bal" : "b", "p");
10046 /* Set to true so that append_insn adds a label. */
10047 emit_branch_likely_macro
= TRUE
;
10051 macro_build (ep
, br
, fmt
, sreg
, treg
);
10052 macro_build (NULL
, "nop", "");
10057 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10058 the condition code tested. EP specifies the branch target. */
10061 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10063 const int call
= 0;
10088 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10091 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10092 the register tested. EP specifies the branch target. */
10095 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10097 const char *brneg
= NULL
;
10107 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10111 gas_assert (mips_opts
.micromips
);
10112 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10120 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10127 br
= mips_opts
.micromips
? "blez" : "blezl";
10134 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10138 gas_assert (mips_opts
.micromips
);
10139 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10146 if (mips_opts
.micromips
&& brneg
)
10147 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10149 macro_build (ep
, br
, "s,p", sreg
);
10152 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10153 TREG as the registers tested. EP specifies the branch target. */
10156 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10157 unsigned int sreg
, unsigned int treg
)
10159 const char *brneg
= NULL
;
10160 const int call
= 0;
10171 br
= mips_opts
.micromips
? "beq" : "beql";
10180 br
= mips_opts
.micromips
? "bne" : "bnel";
10186 if (mips_opts
.micromips
&& brneg
)
10187 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10189 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10192 /* Return the high part that should be loaded in order to make the low
10193 part of VALUE accessible using an offset of OFFBITS bits. */
10196 offset_high_part (offsetT value
, unsigned int offbits
)
10203 bias
= 1 << (offbits
- 1);
10204 low_mask
= bias
* 2 - 1;
10205 return (value
+ bias
) & ~low_mask
;
10208 /* Return true if the value stored in offset_expr and offset_reloc
10209 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10210 amount that the caller wants to add without inducing overflow
10211 and ALIGN is the known alignment of the value in bytes. */
10214 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10218 /* Accept any relocation operator if overflow isn't a concern. */
10219 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10222 /* These relocations are guaranteed not to overflow in correct links. */
10223 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10224 || gprel16_reloc_p (*offset_reloc
))
10227 if (offset_expr
.X_op
== O_constant
10228 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10229 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10236 * This routine implements the seemingly endless macro or synthesized
10237 * instructions and addressing modes in the mips assembly language. Many
10238 * of these macros are simple and are similar to each other. These could
10239 * probably be handled by some kind of table or grammar approach instead of
10240 * this verbose method. Others are not simple macros but are more like
10241 * optimizing code generation.
10242 * One interesting optimization is when several store macros appear
10243 * consecutively that would load AT with the upper half of the same address.
10244 * The ensuing load upper instructions are omitted. This implies some kind
10245 * of global optimization. We currently only optimize within a single macro.
10246 * For many of the load and store macros if the address is specified as a
10247 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10248 * first load register 'at' with zero and use it as the base register. The
10249 * mips assembler simply uses register $zero. Just one tiny optimization
10253 macro (struct mips_cl_insn
*ip
, char *str
)
10255 const struct mips_operand_array
*operands
;
10256 unsigned int breg
, i
;
10257 unsigned int tempreg
;
10260 expressionS label_expr
;
10275 bfd_boolean large_offset
;
10277 int hold_mips_optimize
;
10278 unsigned int align
;
10279 unsigned int op
[MAX_OPERANDS
];
10281 gas_assert (! mips_opts
.mips16
);
10283 operands
= insn_operands (ip
);
10284 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10285 if (operands
->operand
[i
])
10286 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10290 mask
= ip
->insn_mo
->mask
;
10292 label_expr
.X_op
= O_constant
;
10293 label_expr
.X_op_symbol
= NULL
;
10294 label_expr
.X_add_symbol
= NULL
;
10295 label_expr
.X_add_number
= 0;
10297 expr1
.X_op
= O_constant
;
10298 expr1
.X_op_symbol
= NULL
;
10299 expr1
.X_add_symbol
= NULL
;
10300 expr1
.X_add_number
= 1;
10307 /* Fall through. */
10315 start_noreorder ();
10317 if (mips_opts
.micromips
)
10318 micromips_label_expr (&label_expr
);
10320 label_expr
.X_add_number
= 8;
10321 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10322 if (op
[0] == op
[1])
10323 macro_build (NULL
, "nop", "");
10325 move_register (op
[0], op
[1]);
10326 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10327 if (mips_opts
.micromips
)
10328 micromips_add_label ();
10345 if (!mips_opts
.micromips
)
10347 if (imm_expr
.X_add_number
>= -0x200
10348 && imm_expr
.X_add_number
< 0x200)
10350 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10351 (int) imm_expr
.X_add_number
);
10360 if (imm_expr
.X_add_number
>= -0x8000
10361 && imm_expr
.X_add_number
< 0x8000)
10363 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10368 load_register (AT
, &imm_expr
, dbl
);
10369 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10388 if (imm_expr
.X_add_number
>= 0
10389 && imm_expr
.X_add_number
< 0x10000)
10391 if (mask
!= M_NOR_I
)
10392 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10395 macro_build (&imm_expr
, "ori", "t,r,i",
10396 op
[0], op
[1], BFD_RELOC_LO16
);
10397 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10403 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10404 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10408 switch (imm_expr
.X_add_number
)
10411 macro_build (NULL
, "nop", "");
10414 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10418 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10419 (int) imm_expr
.X_add_number
);
10422 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10423 (unsigned long) imm_expr
.X_add_number
);
10432 gas_assert (mips_opts
.micromips
);
10433 macro_build_branch_ccl (mask
, &offset_expr
,
10434 EXTRACT_OPERAND (1, BCC
, *ip
));
10441 if (imm_expr
.X_add_number
== 0)
10447 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10449 /* Fall through. */
10452 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10457 /* Fall through. */
10460 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10461 else if (op
[0] == 0)
10462 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10466 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10467 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10468 &offset_expr
, AT
, ZERO
);
10478 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10483 /* Fall through. */
10485 /* Check for > max integer. */
10486 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10489 /* Result is always false. */
10491 macro_build (NULL
, "nop", "");
10493 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10496 ++imm_expr
.X_add_number
;
10497 /* Fall through. */
10500 if (mask
== M_BGEL_I
)
10502 if (imm_expr
.X_add_number
== 0)
10504 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10505 &offset_expr
, op
[0]);
10508 if (imm_expr
.X_add_number
== 1)
10510 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10511 &offset_expr
, op
[0]);
10514 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10517 /* Result is always true. */
10518 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10519 macro_build (&offset_expr
, "b", "p");
10524 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10525 &offset_expr
, AT
, ZERO
);
10530 /* Fall through. */
10534 else if (op
[0] == 0)
10535 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10536 &offset_expr
, ZERO
, op
[1]);
10540 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10541 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10542 &offset_expr
, AT
, ZERO
);
10548 /* Fall through. */
10552 && imm_expr
.X_add_number
== -1))
10554 ++imm_expr
.X_add_number
;
10555 /* Fall through. */
10558 if (mask
== M_BGEUL_I
)
10560 if (imm_expr
.X_add_number
== 0)
10562 else if (imm_expr
.X_add_number
== 1)
10563 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10564 &offset_expr
, op
[0], ZERO
);
10569 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10570 &offset_expr
, AT
, ZERO
);
10576 /* Fall through. */
10579 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10580 else if (op
[0] == 0)
10581 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10585 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10586 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10587 &offset_expr
, AT
, ZERO
);
10593 /* Fall through. */
10596 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10597 &offset_expr
, op
[0], ZERO
);
10598 else if (op
[0] == 0)
10603 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10604 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10605 &offset_expr
, AT
, ZERO
);
10611 /* Fall through. */
10614 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10615 else if (op
[0] == 0)
10616 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10620 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10621 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10622 &offset_expr
, AT
, ZERO
);
10628 /* Fall through. */
10630 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10632 ++imm_expr
.X_add_number
;
10633 /* Fall through. */
10636 if (mask
== M_BLTL_I
)
10638 if (imm_expr
.X_add_number
== 0)
10639 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10640 else if (imm_expr
.X_add_number
== 1)
10641 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10646 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10647 &offset_expr
, AT
, ZERO
);
10653 /* Fall through. */
10656 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10657 &offset_expr
, op
[0], ZERO
);
10658 else if (op
[0] == 0)
10663 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10664 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10665 &offset_expr
, AT
, ZERO
);
10671 /* Fall through. */
10675 && imm_expr
.X_add_number
== -1))
10677 ++imm_expr
.X_add_number
;
10678 /* Fall through. */
10681 if (mask
== M_BLTUL_I
)
10683 if (imm_expr
.X_add_number
== 0)
10685 else if (imm_expr
.X_add_number
== 1)
10686 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10687 &offset_expr
, op
[0], ZERO
);
10692 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10693 &offset_expr
, AT
, ZERO
);
10699 /* Fall through. */
10702 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10703 else if (op
[0] == 0)
10704 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10708 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10709 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10710 &offset_expr
, AT
, ZERO
);
10716 /* Fall through. */
10720 else if (op
[0] == 0)
10721 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10722 &offset_expr
, ZERO
, op
[1]);
10726 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10727 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10728 &offset_expr
, AT
, ZERO
);
10734 /* Fall through. */
10740 /* Fall through. */
10746 as_warn (_("divide by zero"));
10748 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10750 macro_build (NULL
, "break", BRK_FMT
, 7);
10754 start_noreorder ();
10757 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10758 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10762 if (mips_opts
.micromips
)
10763 micromips_label_expr (&label_expr
);
10765 label_expr
.X_add_number
= 8;
10766 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10767 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10768 macro_build (NULL
, "break", BRK_FMT
, 7);
10769 if (mips_opts
.micromips
)
10770 micromips_add_label ();
10772 expr1
.X_add_number
= -1;
10774 load_register (AT
, &expr1
, dbl
);
10775 if (mips_opts
.micromips
)
10776 micromips_label_expr (&label_expr
);
10778 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10779 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10782 expr1
.X_add_number
= 1;
10783 load_register (AT
, &expr1
, dbl
);
10784 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10788 expr1
.X_add_number
= 0x80000000;
10789 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10793 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10794 /* We want to close the noreorder block as soon as possible, so
10795 that later insns are available for delay slot filling. */
10800 if (mips_opts
.micromips
)
10801 micromips_label_expr (&label_expr
);
10803 label_expr
.X_add_number
= 8;
10804 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10805 macro_build (NULL
, "nop", "");
10807 /* We want to close the noreorder block as soon as possible, so
10808 that later insns are available for delay slot filling. */
10811 macro_build (NULL
, "break", BRK_FMT
, 6);
10813 if (mips_opts
.micromips
)
10814 micromips_add_label ();
10815 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10854 if (imm_expr
.X_add_number
== 0)
10856 as_warn (_("divide by zero"));
10858 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10860 macro_build (NULL
, "break", BRK_FMT
, 7);
10863 if (imm_expr
.X_add_number
== 1)
10865 if (strcmp (s2
, "mflo") == 0)
10866 move_register (op
[0], op
[1]);
10868 move_register (op
[0], ZERO
);
10871 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10873 if (strcmp (s2
, "mflo") == 0)
10874 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10876 move_register (op
[0], ZERO
);
10881 load_register (AT
, &imm_expr
, dbl
);
10882 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10883 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10902 start_noreorder ();
10905 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10906 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10907 /* We want to close the noreorder block as soon as possible, so
10908 that later insns are available for delay slot filling. */
10913 if (mips_opts
.micromips
)
10914 micromips_label_expr (&label_expr
);
10916 label_expr
.X_add_number
= 8;
10917 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10918 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10920 /* We want to close the noreorder block as soon as possible, so
10921 that later insns are available for delay slot filling. */
10923 macro_build (NULL
, "break", BRK_FMT
, 7);
10924 if (mips_opts
.micromips
)
10925 micromips_add_label ();
10927 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10932 /* Fall through. */
10938 /* Fall through. */
10941 /* Load the address of a symbol into a register. If breg is not
10942 zero, we then add a base register to it. */
10945 if (dbl
&& GPR_SIZE
== 32)
10946 as_warn (_("dla used to load 32-bit register; recommend using la "
10949 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10950 as_warn (_("la used to load 64-bit address; recommend using dla "
10953 if (small_offset_p (0, align
, 16))
10955 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10956 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10960 if (mips_opts
.at
&& (op
[0] == breg
))
10968 if (offset_expr
.X_op
!= O_symbol
10969 && offset_expr
.X_op
!= O_constant
)
10971 as_bad (_("expression too complex"));
10972 offset_expr
.X_op
= O_constant
;
10975 if (offset_expr
.X_op
== O_constant
)
10976 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10977 else if (mips_pic
== NO_PIC
)
10979 /* If this is a reference to a GP relative symbol, we want
10980 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10982 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10983 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10984 If we have a constant, we need two instructions anyhow,
10985 so we may as well always use the latter form.
10987 With 64bit address space and a usable $at we want
10988 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10989 lui $at,<sym> (BFD_RELOC_HI16_S)
10990 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10991 daddiu $at,<sym> (BFD_RELOC_LO16)
10993 daddu $tempreg,$tempreg,$at
10995 If $at is already in use, we use a path which is suboptimal
10996 on superscalar processors.
10997 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10998 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11000 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11002 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11004 For GP relative symbols in 64bit address space we can use
11005 the same sequence as in 32bit address space. */
11006 if (HAVE_64BIT_SYMBOLS
)
11008 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11009 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11011 relax_start (offset_expr
.X_add_symbol
);
11012 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11013 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11017 if (used_at
== 0 && mips_opts
.at
)
11019 macro_build (&offset_expr
, "lui", LUI_FMT
,
11020 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11021 macro_build (&offset_expr
, "lui", LUI_FMT
,
11022 AT
, BFD_RELOC_HI16_S
);
11023 macro_build (&offset_expr
, "daddiu", "t,r,j",
11024 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11025 macro_build (&offset_expr
, "daddiu", "t,r,j",
11026 AT
, AT
, BFD_RELOC_LO16
);
11027 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11028 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11033 macro_build (&offset_expr
, "lui", LUI_FMT
,
11034 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11035 macro_build (&offset_expr
, "daddiu", "t,r,j",
11036 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11037 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11038 macro_build (&offset_expr
, "daddiu", "t,r,j",
11039 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11040 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11041 macro_build (&offset_expr
, "daddiu", "t,r,j",
11042 tempreg
, tempreg
, BFD_RELOC_LO16
);
11045 if (mips_relax
.sequence
)
11050 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11051 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11053 relax_start (offset_expr
.X_add_symbol
);
11054 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11055 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11058 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11059 as_bad (_("offset too large"));
11060 macro_build_lui (&offset_expr
, tempreg
);
11061 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11062 tempreg
, tempreg
, BFD_RELOC_LO16
);
11063 if (mips_relax
.sequence
)
11067 else if (!mips_big_got
&& !HAVE_NEWABI
)
11069 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11071 /* If this is a reference to an external symbol, and there
11072 is no constant, we want
11073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11074 or for lca or if tempreg is PIC_CALL_REG
11075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11076 For a local symbol, we want
11077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11079 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11081 If we have a small constant, and this is a reference to
11082 an external symbol, we want
11083 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11085 addiu $tempreg,$tempreg,<constant>
11086 For a local symbol, we want the same instruction
11087 sequence, but we output a BFD_RELOC_LO16 reloc on the
11090 If we have a large constant, and this is a reference to
11091 an external symbol, we want
11092 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11093 lui $at,<hiconstant>
11094 addiu $at,$at,<loconstant>
11095 addu $tempreg,$tempreg,$at
11096 For a local symbol, we want the same instruction
11097 sequence, but we output a BFD_RELOC_LO16 reloc on the
11101 if (offset_expr
.X_add_number
== 0)
11103 if (mips_pic
== SVR4_PIC
11105 && (call
|| tempreg
== PIC_CALL_REG
))
11106 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11108 relax_start (offset_expr
.X_add_symbol
);
11109 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11110 lw_reloc_type
, mips_gp_register
);
11113 /* We're going to put in an addu instruction using
11114 tempreg, so we may as well insert the nop right
11119 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11120 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11122 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11123 tempreg
, tempreg
, BFD_RELOC_LO16
);
11125 /* FIXME: If breg == 0, and the next instruction uses
11126 $tempreg, then if this variant case is used an extra
11127 nop will be generated. */
11129 else if (offset_expr
.X_add_number
>= -0x8000
11130 && offset_expr
.X_add_number
< 0x8000)
11132 load_got_offset (tempreg
, &offset_expr
);
11134 add_got_offset (tempreg
, &offset_expr
);
11138 expr1
.X_add_number
= offset_expr
.X_add_number
;
11139 offset_expr
.X_add_number
=
11140 SEXT_16BIT (offset_expr
.X_add_number
);
11141 load_got_offset (tempreg
, &offset_expr
);
11142 offset_expr
.X_add_number
= expr1
.X_add_number
;
11143 /* If we are going to add in a base register, and the
11144 target register and the base register are the same,
11145 then we are using AT as a temporary register. Since
11146 we want to load the constant into AT, we add our
11147 current AT (from the global offset table) and the
11148 register into the register now, and pretend we were
11149 not using a base register. */
11153 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11158 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11162 else if (!mips_big_got
&& HAVE_NEWABI
)
11164 int add_breg_early
= 0;
11166 /* If this is a reference to an external, and there is no
11167 constant, or local symbol (*), with or without a
11169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11170 or for lca or if tempreg is PIC_CALL_REG
11171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11173 If we have a small constant, and this is a reference to
11174 an external symbol, we want
11175 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11176 addiu $tempreg,$tempreg,<constant>
11178 If we have a large constant, and this is a reference to
11179 an external symbol, we want
11180 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11181 lui $at,<hiconstant>
11182 addiu $at,$at,<loconstant>
11183 addu $tempreg,$tempreg,$at
11185 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11186 local symbols, even though it introduces an additional
11189 if (offset_expr
.X_add_number
)
11191 expr1
.X_add_number
= offset_expr
.X_add_number
;
11192 offset_expr
.X_add_number
= 0;
11194 relax_start (offset_expr
.X_add_symbol
);
11195 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11196 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11198 if (expr1
.X_add_number
>= -0x8000
11199 && expr1
.X_add_number
< 0x8000)
11201 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11202 tempreg
, tempreg
, BFD_RELOC_LO16
);
11204 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11208 /* If we are going to add in a base register, and the
11209 target register and the base register are the same,
11210 then we are using AT as a temporary register. Since
11211 we want to load the constant into AT, we add our
11212 current AT (from the global offset table) and the
11213 register into the register now, and pretend we were
11214 not using a base register. */
11219 gas_assert (tempreg
== AT
);
11220 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11223 add_breg_early
= 1;
11226 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11233 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11236 offset_expr
.X_add_number
= expr1
.X_add_number
;
11238 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11239 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11240 if (add_breg_early
)
11242 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11243 op
[0], tempreg
, breg
);
11249 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11251 relax_start (offset_expr
.X_add_symbol
);
11252 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11253 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11255 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11256 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11261 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11262 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11265 else if (mips_big_got
&& !HAVE_NEWABI
)
11268 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11269 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11270 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11272 /* This is the large GOT case. If this is a reference to an
11273 external symbol, and there is no constant, we want
11274 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11275 addu $tempreg,$tempreg,$gp
11276 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11277 or for lca or if tempreg is PIC_CALL_REG
11278 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11279 addu $tempreg,$tempreg,$gp
11280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11281 For a local symbol, we want
11282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11284 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11286 If we have a small constant, and this is a reference to
11287 an external symbol, we want
11288 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11289 addu $tempreg,$tempreg,$gp
11290 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11292 addiu $tempreg,$tempreg,<constant>
11293 For a local symbol, we want
11294 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11296 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11298 If we have a large constant, and this is a reference to
11299 an external symbol, we want
11300 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11301 addu $tempreg,$tempreg,$gp
11302 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11303 lui $at,<hiconstant>
11304 addiu $at,$at,<loconstant>
11305 addu $tempreg,$tempreg,$at
11306 For a local symbol, we want
11307 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11308 lui $at,<hiconstant>
11309 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11310 addu $tempreg,$tempreg,$at
11313 expr1
.X_add_number
= offset_expr
.X_add_number
;
11314 offset_expr
.X_add_number
= 0;
11315 relax_start (offset_expr
.X_add_symbol
);
11316 gpdelay
= reg_needs_delay (mips_gp_register
);
11317 if (expr1
.X_add_number
== 0 && breg
== 0
11318 && (call
|| tempreg
== PIC_CALL_REG
))
11320 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11321 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11323 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11324 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11325 tempreg
, tempreg
, mips_gp_register
);
11326 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11327 tempreg
, lw_reloc_type
, tempreg
);
11328 if (expr1
.X_add_number
== 0)
11332 /* We're going to put in an addu instruction using
11333 tempreg, so we may as well insert the nop right
11338 else if (expr1
.X_add_number
>= -0x8000
11339 && expr1
.X_add_number
< 0x8000)
11342 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11343 tempreg
, tempreg
, BFD_RELOC_LO16
);
11349 /* If we are going to add in a base register, and the
11350 target register and the base register are the same,
11351 then we are using AT as a temporary register. Since
11352 we want to load the constant into AT, we add our
11353 current AT (from the global offset table) and the
11354 register into the register now, and pretend we were
11355 not using a base register. */
11360 gas_assert (tempreg
== AT
);
11362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11367 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11372 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11377 /* This is needed because this instruction uses $gp, but
11378 the first instruction on the main stream does not. */
11379 macro_build (NULL
, "nop", "");
11382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11383 local_reloc_type
, mips_gp_register
);
11384 if (expr1
.X_add_number
>= -0x8000
11385 && expr1
.X_add_number
< 0x8000)
11388 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11389 tempreg
, tempreg
, BFD_RELOC_LO16
);
11390 /* FIXME: If add_number is 0, and there was no base
11391 register, the external symbol case ended with a load,
11392 so if the symbol turns out to not be external, and
11393 the next instruction uses tempreg, an unnecessary nop
11394 will be inserted. */
11400 /* We must add in the base register now, as in the
11401 external symbol case. */
11402 gas_assert (tempreg
== AT
);
11404 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11407 /* We set breg to 0 because we have arranged to add
11408 it in in both cases. */
11412 macro_build_lui (&expr1
, AT
);
11413 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11414 AT
, AT
, BFD_RELOC_LO16
);
11415 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11416 tempreg
, tempreg
, AT
);
11421 else if (mips_big_got
&& HAVE_NEWABI
)
11423 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11424 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11425 int add_breg_early
= 0;
11427 /* This is the large GOT case. If this is a reference to an
11428 external symbol, and there is no constant, we want
11429 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11430 add $tempreg,$tempreg,$gp
11431 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11432 or for lca or if tempreg is PIC_CALL_REG
11433 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11434 add $tempreg,$tempreg,$gp
11435 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11437 If we have a small constant, and this is a reference to
11438 an external symbol, we want
11439 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11440 add $tempreg,$tempreg,$gp
11441 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11442 addi $tempreg,$tempreg,<constant>
11444 If we have a large constant, and this is a reference to
11445 an external symbol, we want
11446 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11447 addu $tempreg,$tempreg,$gp
11448 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11449 lui $at,<hiconstant>
11450 addi $at,$at,<loconstant>
11451 add $tempreg,$tempreg,$at
11453 If we have NewABI, and we know it's a local symbol, we want
11454 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11455 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11456 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11458 relax_start (offset_expr
.X_add_symbol
);
11460 expr1
.X_add_number
= offset_expr
.X_add_number
;
11461 offset_expr
.X_add_number
= 0;
11463 if (expr1
.X_add_number
== 0 && breg
== 0
11464 && (call
|| tempreg
== PIC_CALL_REG
))
11466 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11467 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11469 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11470 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11471 tempreg
, tempreg
, mips_gp_register
);
11472 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11473 tempreg
, lw_reloc_type
, tempreg
);
11475 if (expr1
.X_add_number
== 0)
11477 else if (expr1
.X_add_number
>= -0x8000
11478 && expr1
.X_add_number
< 0x8000)
11480 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11481 tempreg
, tempreg
, BFD_RELOC_LO16
);
11483 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11487 /* If we are going to add in a base register, and the
11488 target register and the base register are the same,
11489 then we are using AT as a temporary register. Since
11490 we want to load the constant into AT, we add our
11491 current AT (from the global offset table) and the
11492 register into the register now, and pretend we were
11493 not using a base register. */
11498 gas_assert (tempreg
== AT
);
11499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11502 add_breg_early
= 1;
11505 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11506 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11511 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11514 offset_expr
.X_add_number
= expr1
.X_add_number
;
11515 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11516 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11517 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11518 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11519 if (add_breg_early
)
11521 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11522 op
[0], tempreg
, breg
);
11532 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11536 gas_assert (!mips_opts
.micromips
);
11537 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11541 gas_assert (!mips_opts
.micromips
);
11542 macro_build (NULL
, "c2", "C", 0x02);
11546 gas_assert (!mips_opts
.micromips
);
11547 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11551 gas_assert (!mips_opts
.micromips
);
11552 macro_build (NULL
, "c2", "C", 3);
11556 gas_assert (!mips_opts
.micromips
);
11557 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11561 /* The j instruction may not be used in PIC code, since it
11562 requires an absolute address. We convert it to a b
11564 if (mips_pic
== NO_PIC
)
11565 macro_build (&offset_expr
, "j", "a");
11567 macro_build (&offset_expr
, "b", "p");
11570 /* The jal instructions must be handled as macros because when
11571 generating PIC code they expand to multi-instruction
11572 sequences. Normally they are simple instructions. */
11576 /* Fall through. */
11578 gas_assert (mips_opts
.micromips
);
11579 if (mips_opts
.insn32
)
11581 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11589 /* Fall through. */
11592 if (mips_pic
== NO_PIC
)
11594 s
= jals
? "jalrs" : "jalr";
11595 if (mips_opts
.micromips
11596 && !mips_opts
.insn32
11598 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11599 macro_build (NULL
, s
, "mj", op
[1]);
11601 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11605 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11606 && mips_cprestore_offset
>= 0);
11608 if (op
[1] != PIC_CALL_REG
)
11609 as_warn (_("MIPS PIC call to register other than $25"));
11611 s
= ((mips_opts
.micromips
11612 && !mips_opts
.insn32
11613 && (!mips_opts
.noreorder
|| cprestore
))
11614 ? "jalrs" : "jalr");
11615 if (mips_opts
.micromips
11616 && !mips_opts
.insn32
11618 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11619 macro_build (NULL
, s
, "mj", op
[1]);
11621 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11622 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11624 if (mips_cprestore_offset
< 0)
11625 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11628 if (!mips_frame_reg_valid
)
11630 as_warn (_("no .frame pseudo-op used in PIC code"));
11631 /* Quiet this warning. */
11632 mips_frame_reg_valid
= 1;
11634 if (!mips_cprestore_valid
)
11636 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11637 /* Quiet this warning. */
11638 mips_cprestore_valid
= 1;
11640 if (mips_opts
.noreorder
)
11641 macro_build (NULL
, "nop", "");
11642 expr1
.X_add_number
= mips_cprestore_offset
;
11643 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11646 HAVE_64BIT_ADDRESSES
);
11654 gas_assert (mips_opts
.micromips
);
11655 if (mips_opts
.insn32
)
11657 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11661 /* Fall through. */
11663 if (mips_pic
== NO_PIC
)
11664 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11665 else if (mips_pic
== SVR4_PIC
)
11667 /* If this is a reference to an external symbol, and we are
11668 using a small GOT, we want
11669 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11673 lw $gp,cprestore($sp)
11674 The cprestore value is set using the .cprestore
11675 pseudo-op. If we are using a big GOT, we want
11676 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11678 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11682 lw $gp,cprestore($sp)
11683 If the symbol is not external, we want
11684 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11686 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11689 lw $gp,cprestore($sp)
11691 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11692 sequences above, minus nops, unless the symbol is local,
11693 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11699 relax_start (offset_expr
.X_add_symbol
);
11700 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11701 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11704 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11705 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11711 relax_start (offset_expr
.X_add_symbol
);
11712 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11713 BFD_RELOC_MIPS_CALL_HI16
);
11714 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11715 PIC_CALL_REG
, mips_gp_register
);
11716 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11717 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11720 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11721 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11723 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11724 PIC_CALL_REG
, PIC_CALL_REG
,
11725 BFD_RELOC_MIPS_GOT_OFST
);
11729 macro_build_jalr (&offset_expr
, 0);
11733 relax_start (offset_expr
.X_add_symbol
);
11736 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11737 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11746 gpdelay
= reg_needs_delay (mips_gp_register
);
11747 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11748 BFD_RELOC_MIPS_CALL_HI16
);
11749 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11750 PIC_CALL_REG
, mips_gp_register
);
11751 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11752 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11757 macro_build (NULL
, "nop", "");
11759 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11760 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11763 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11764 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11766 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11768 if (mips_cprestore_offset
< 0)
11769 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11772 if (!mips_frame_reg_valid
)
11774 as_warn (_("no .frame pseudo-op used in PIC code"));
11775 /* Quiet this warning. */
11776 mips_frame_reg_valid
= 1;
11778 if (!mips_cprestore_valid
)
11780 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11781 /* Quiet this warning. */
11782 mips_cprestore_valid
= 1;
11784 if (mips_opts
.noreorder
)
11785 macro_build (NULL
, "nop", "");
11786 expr1
.X_add_number
= mips_cprestore_offset
;
11787 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11790 HAVE_64BIT_ADDRESSES
);
11794 else if (mips_pic
== VXWORKS_PIC
)
11795 as_bad (_("non-PIC jump used in PIC library"));
11902 gas_assert (!mips_opts
.micromips
);
11905 /* Itbl support may require additional care here. */
11911 /* Itbl support may require additional care here. */
11917 offbits
= (mips_opts
.micromips
? 12
11918 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11920 /* Itbl support may require additional care here. */
11924 gas_assert (!mips_opts
.micromips
);
11927 /* Itbl support may require additional care here. */
11933 offbits
= (mips_opts
.micromips
? 12 : 16);
11938 offbits
= (mips_opts
.micromips
? 12 : 16);
11943 /* Itbl support may require additional care here. */
11949 offbits
= (mips_opts
.micromips
? 12
11950 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11952 /* Itbl support may require additional care here. */
11958 /* Itbl support may require additional care here. */
11964 /* Itbl support may require additional care here. */
11970 offbits
= (mips_opts
.micromips
? 12 : 16);
11975 offbits
= (mips_opts
.micromips
? 12 : 16);
11980 offbits
= (mips_opts
.micromips
? 12
11981 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11987 offbits
= (mips_opts
.micromips
? 12
11988 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11994 offbits
= (mips_opts
.micromips
? 12 : 16);
11997 gas_assert (mips_opts
.micromips
);
12004 gas_assert (mips_opts
.micromips
);
12011 gas_assert (mips_opts
.micromips
);
12017 gas_assert (mips_opts
.micromips
);
12024 /* We don't want to use $0 as tempreg. */
12025 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12028 tempreg
= op
[0] + lp
;
12044 gas_assert (!mips_opts
.micromips
);
12047 /* Itbl support may require additional care here. */
12053 /* Itbl support may require additional care here. */
12059 offbits
= (mips_opts
.micromips
? 12
12060 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12062 /* Itbl support may require additional care here. */
12066 gas_assert (!mips_opts
.micromips
);
12069 /* Itbl support may require additional care here. */
12075 offbits
= (mips_opts
.micromips
? 12 : 16);
12080 offbits
= (mips_opts
.micromips
? 12 : 16);
12085 offbits
= (mips_opts
.micromips
? 12
12086 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12092 offbits
= (mips_opts
.micromips
? 12
12093 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12098 fmt
= (mips_opts
.micromips
? "k,~(b)"
12099 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12101 offbits
= (mips_opts
.micromips
? 12
12102 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12112 fmt
= (mips_opts
.micromips
? "k,~(b)"
12113 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12115 offbits
= (mips_opts
.micromips
? 12
12116 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12128 /* Itbl support may require additional care here. */
12133 offbits
= (mips_opts
.micromips
? 12
12134 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12136 /* Itbl support may require additional care here. */
12142 /* Itbl support may require additional care here. */
12146 gas_assert (!mips_opts
.micromips
);
12149 /* Itbl support may require additional care here. */
12155 offbits
= (mips_opts
.micromips
? 12 : 16);
12160 offbits
= (mips_opts
.micromips
? 12 : 16);
12163 gas_assert (mips_opts
.micromips
);
12169 gas_assert (mips_opts
.micromips
);
12175 gas_assert (mips_opts
.micromips
);
12181 gas_assert (mips_opts
.micromips
);
12190 if (small_offset_p (0, align
, 16))
12192 /* The first case exists for M_LD_AB and M_SD_AB, which are
12193 macros for o32 but which should act like normal instructions
12196 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12197 offset_reloc
[1], offset_reloc
[2], breg
);
12198 else if (small_offset_p (0, align
, offbits
))
12201 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12203 macro_build (NULL
, s
, fmt
, op
[0],
12204 (int) offset_expr
.X_add_number
, breg
);
12210 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12211 tempreg
, breg
, -1, offset_reloc
[0],
12212 offset_reloc
[1], offset_reloc
[2]);
12214 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12216 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12224 if (offset_expr
.X_op
!= O_constant
12225 && offset_expr
.X_op
!= O_symbol
)
12227 as_bad (_("expression too complex"));
12228 offset_expr
.X_op
= O_constant
;
12231 if (HAVE_32BIT_ADDRESSES
12232 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12236 sprintf_vma (value
, offset_expr
.X_add_number
);
12237 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12240 /* A constant expression in PIC code can be handled just as it
12241 is in non PIC code. */
12242 if (offset_expr
.X_op
== O_constant
)
12244 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12245 offbits
== 0 ? 16 : offbits
);
12246 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12248 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12250 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12251 tempreg
, tempreg
, breg
);
12254 if (offset_expr
.X_add_number
!= 0)
12255 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12256 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12257 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12259 else if (offbits
== 16)
12260 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12262 macro_build (NULL
, s
, fmt
, op
[0],
12263 (int) offset_expr
.X_add_number
, tempreg
);
12265 else if (offbits
!= 16)
12267 /* The offset field is too narrow to be used for a low-part
12268 relocation, so load the whole address into the auxiliary
12270 load_address (tempreg
, &offset_expr
, &used_at
);
12272 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12273 tempreg
, tempreg
, breg
);
12275 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12277 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12279 else if (mips_pic
== NO_PIC
)
12281 /* If this is a reference to a GP relative symbol, and there
12282 is no base register, we want
12283 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12284 Otherwise, if there is no base register, we want
12285 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12286 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12287 If we have a constant, we need two instructions anyhow,
12288 so we always use the latter form.
12290 If we have a base register, and this is a reference to a
12291 GP relative symbol, we want
12292 addu $tempreg,$breg,$gp
12293 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12295 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12296 addu $tempreg,$tempreg,$breg
12297 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12298 With a constant we always use the latter case.
12300 With 64bit address space and no base register and $at usable,
12302 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12303 lui $at,<sym> (BFD_RELOC_HI16_S)
12304 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12307 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12308 If we have a base register, we want
12309 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12310 lui $at,<sym> (BFD_RELOC_HI16_S)
12311 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12315 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12317 Without $at we can't generate the optimal path for superscalar
12318 processors here since this would require two temporary registers.
12319 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12320 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12322 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12324 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12325 If we have a base register, we want
12326 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12327 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12329 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12331 daddu $tempreg,$tempreg,$breg
12332 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12334 For GP relative symbols in 64bit address space we can use
12335 the same sequence as in 32bit address space. */
12336 if (HAVE_64BIT_SYMBOLS
)
12338 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12339 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12341 relax_start (offset_expr
.X_add_symbol
);
12344 macro_build (&offset_expr
, s
, fmt
, op
[0],
12345 BFD_RELOC_GPREL16
, mips_gp_register
);
12349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12350 tempreg
, breg
, mips_gp_register
);
12351 macro_build (&offset_expr
, s
, fmt
, op
[0],
12352 BFD_RELOC_GPREL16
, tempreg
);
12357 if (used_at
== 0 && mips_opts
.at
)
12359 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12360 BFD_RELOC_MIPS_HIGHEST
);
12361 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12363 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12364 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12366 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12367 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12368 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12369 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12375 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12376 BFD_RELOC_MIPS_HIGHEST
);
12377 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12378 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12379 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12380 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12381 tempreg
, BFD_RELOC_HI16_S
);
12382 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12384 macro_build (NULL
, "daddu", "d,v,t",
12385 tempreg
, tempreg
, breg
);
12386 macro_build (&offset_expr
, s
, fmt
, op
[0],
12387 BFD_RELOC_LO16
, tempreg
);
12390 if (mips_relax
.sequence
)
12397 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12398 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12400 relax_start (offset_expr
.X_add_symbol
);
12401 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12405 macro_build_lui (&offset_expr
, tempreg
);
12406 macro_build (&offset_expr
, s
, fmt
, op
[0],
12407 BFD_RELOC_LO16
, tempreg
);
12408 if (mips_relax
.sequence
)
12413 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12414 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12416 relax_start (offset_expr
.X_add_symbol
);
12417 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12418 tempreg
, breg
, mips_gp_register
);
12419 macro_build (&offset_expr
, s
, fmt
, op
[0],
12420 BFD_RELOC_GPREL16
, tempreg
);
12423 macro_build_lui (&offset_expr
, tempreg
);
12424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12425 tempreg
, tempreg
, breg
);
12426 macro_build (&offset_expr
, s
, fmt
, op
[0],
12427 BFD_RELOC_LO16
, tempreg
);
12428 if (mips_relax
.sequence
)
12432 else if (!mips_big_got
)
12434 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12436 /* If this is a reference to an external symbol, we want
12437 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12439 <op> op[0],0($tempreg)
12441 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12443 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12444 <op> op[0],0($tempreg)
12446 For NewABI, we want
12447 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12448 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12450 If there is a base register, we add it to $tempreg before
12451 the <op>. If there is a constant, we stick it in the
12452 <op> instruction. We don't handle constants larger than
12453 16 bits, because we have no way to load the upper 16 bits
12454 (actually, we could handle them for the subset of cases
12455 in which we are not using $at). */
12456 gas_assert (offset_expr
.X_op
== O_symbol
);
12459 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12460 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12462 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12463 tempreg
, tempreg
, breg
);
12464 macro_build (&offset_expr
, s
, fmt
, op
[0],
12465 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12468 expr1
.X_add_number
= offset_expr
.X_add_number
;
12469 offset_expr
.X_add_number
= 0;
12470 if (expr1
.X_add_number
< -0x8000
12471 || expr1
.X_add_number
>= 0x8000)
12472 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12473 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12474 lw_reloc_type
, mips_gp_register
);
12476 relax_start (offset_expr
.X_add_symbol
);
12478 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12479 tempreg
, BFD_RELOC_LO16
);
12482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12483 tempreg
, tempreg
, breg
);
12484 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12486 else if (mips_big_got
&& !HAVE_NEWABI
)
12490 /* If this is a reference to an external symbol, we want
12491 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12492 addu $tempreg,$tempreg,$gp
12493 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12494 <op> op[0],0($tempreg)
12496 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12498 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12499 <op> op[0],0($tempreg)
12500 If there is a base register, we add it to $tempreg before
12501 the <op>. If there is a constant, we stick it in the
12502 <op> instruction. We don't handle constants larger than
12503 16 bits, because we have no way to load the upper 16 bits
12504 (actually, we could handle them for the subset of cases
12505 in which we are not using $at). */
12506 gas_assert (offset_expr
.X_op
== O_symbol
);
12507 expr1
.X_add_number
= offset_expr
.X_add_number
;
12508 offset_expr
.X_add_number
= 0;
12509 if (expr1
.X_add_number
< -0x8000
12510 || expr1
.X_add_number
>= 0x8000)
12511 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12512 gpdelay
= reg_needs_delay (mips_gp_register
);
12513 relax_start (offset_expr
.X_add_symbol
);
12514 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12515 BFD_RELOC_MIPS_GOT_HI16
);
12516 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12518 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12519 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12522 macro_build (NULL
, "nop", "");
12523 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12524 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12526 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12527 tempreg
, BFD_RELOC_LO16
);
12531 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12532 tempreg
, tempreg
, breg
);
12533 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12535 else if (mips_big_got
&& HAVE_NEWABI
)
12537 /* If this is a reference to an external symbol, we want
12538 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12539 add $tempreg,$tempreg,$gp
12540 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12541 <op> op[0],<ofst>($tempreg)
12542 Otherwise, for local symbols, we want:
12543 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12544 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12545 gas_assert (offset_expr
.X_op
== O_symbol
);
12546 expr1
.X_add_number
= offset_expr
.X_add_number
;
12547 offset_expr
.X_add_number
= 0;
12548 if (expr1
.X_add_number
< -0x8000
12549 || expr1
.X_add_number
>= 0x8000)
12550 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12551 relax_start (offset_expr
.X_add_symbol
);
12552 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12553 BFD_RELOC_MIPS_GOT_HI16
);
12554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12556 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12557 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12559 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12560 tempreg
, tempreg
, breg
);
12561 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12564 offset_expr
.X_add_number
= expr1
.X_add_number
;
12565 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12566 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12568 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12569 tempreg
, tempreg
, breg
);
12570 macro_build (&offset_expr
, s
, fmt
, op
[0],
12571 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12580 gas_assert (mips_opts
.micromips
);
12581 gas_assert (mips_opts
.insn32
);
12582 start_noreorder ();
12583 macro_build (NULL
, "jr", "s", RA
);
12584 expr1
.X_add_number
= op
[0] << 2;
12585 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12590 gas_assert (mips_opts
.micromips
);
12591 gas_assert (mips_opts
.insn32
);
12592 macro_build (NULL
, "jr", "s", op
[0]);
12593 if (mips_opts
.noreorder
)
12594 macro_build (NULL
, "nop", "");
12599 load_register (op
[0], &imm_expr
, 0);
12603 load_register (op
[0], &imm_expr
, 1);
12607 if (imm_expr
.X_op
== O_constant
)
12610 load_register (AT
, &imm_expr
, 0);
12611 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12616 gas_assert (imm_expr
.X_op
== O_absent
12617 && offset_expr
.X_op
== O_symbol
12618 && strcmp (segment_name (S_GET_SEGMENT
12619 (offset_expr
.X_add_symbol
)),
12621 && offset_expr
.X_add_number
== 0);
12622 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12623 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12628 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12629 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12630 order 32 bits of the value and the low order 32 bits are either
12631 zero or in OFFSET_EXPR. */
12632 if (imm_expr
.X_op
== O_constant
)
12634 if (GPR_SIZE
== 64)
12635 load_register (op
[0], &imm_expr
, 1);
12640 if (target_big_endian
)
12652 load_register (hreg
, &imm_expr
, 0);
12655 if (offset_expr
.X_op
== O_absent
)
12656 move_register (lreg
, 0);
12659 gas_assert (offset_expr
.X_op
== O_constant
);
12660 load_register (lreg
, &offset_expr
, 0);
12666 gas_assert (imm_expr
.X_op
== O_absent
);
12668 /* We know that sym is in the .rdata section. First we get the
12669 upper 16 bits of the address. */
12670 if (mips_pic
== NO_PIC
)
12672 macro_build_lui (&offset_expr
, AT
);
12677 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12678 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12682 /* Now we load the register(s). */
12683 if (GPR_SIZE
== 64)
12686 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12687 BFD_RELOC_LO16
, AT
);
12692 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12693 BFD_RELOC_LO16
, AT
);
12696 /* FIXME: How in the world do we deal with the possible
12698 offset_expr
.X_add_number
+= 4;
12699 macro_build (&offset_expr
, "lw", "t,o(b)",
12700 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12706 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12707 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12708 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12709 the value and the low order 32 bits are either zero or in
12711 if (imm_expr
.X_op
== O_constant
)
12714 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12715 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12716 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12719 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12720 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12721 else if (FPR_SIZE
!= 32)
12722 as_bad (_("Unable to generate `%s' compliant code "
12724 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12726 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12727 if (offset_expr
.X_op
== O_absent
)
12728 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12731 gas_assert (offset_expr
.X_op
== O_constant
);
12732 load_register (AT
, &offset_expr
, 0);
12733 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12739 gas_assert (imm_expr
.X_op
== O_absent
12740 && offset_expr
.X_op
== O_symbol
12741 && offset_expr
.X_add_number
== 0);
12742 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12743 if (strcmp (s
, ".lit8") == 0)
12745 op
[2] = mips_gp_register
;
12746 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12747 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12748 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12752 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12754 if (mips_pic
!= NO_PIC
)
12755 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12756 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12759 /* FIXME: This won't work for a 64 bit address. */
12760 macro_build_lui (&offset_expr
, AT
);
12764 offset_reloc
[0] = BFD_RELOC_LO16
;
12765 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12766 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12769 /* Fall through. */
12772 /* The MIPS assembler seems to check for X_add_number not
12773 being double aligned and generating:
12776 addiu at,at,%lo(foo+1)
12779 But, the resulting address is the same after relocation so why
12780 generate the extra instruction? */
12781 /* Itbl support may require additional care here. */
12784 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12793 gas_assert (!mips_opts
.micromips
);
12794 /* Itbl support may require additional care here. */
12797 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12817 if (GPR_SIZE
== 64)
12827 if (GPR_SIZE
== 64)
12835 /* Even on a big endian machine $fn comes before $fn+1. We have
12836 to adjust when loading from memory. We set coproc if we must
12837 load $fn+1 first. */
12838 /* Itbl support may require additional care here. */
12839 if (!target_big_endian
)
12843 if (small_offset_p (0, align
, 16))
12846 if (!small_offset_p (4, align
, 16))
12848 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12849 -1, offset_reloc
[0], offset_reloc
[1],
12851 expr1
.X_add_number
= 0;
12855 offset_reloc
[0] = BFD_RELOC_LO16
;
12856 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12857 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12859 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12861 ep
->X_add_number
+= 4;
12862 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12863 offset_reloc
[1], offset_reloc
[2], breg
);
12864 ep
->X_add_number
-= 4;
12865 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12866 offset_reloc
[1], offset_reloc
[2], breg
);
12870 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12871 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12873 ep
->X_add_number
+= 4;
12874 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12875 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12881 if (offset_expr
.X_op
!= O_symbol
12882 && offset_expr
.X_op
!= O_constant
)
12884 as_bad (_("expression too complex"));
12885 offset_expr
.X_op
= O_constant
;
12888 if (HAVE_32BIT_ADDRESSES
12889 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12893 sprintf_vma (value
, offset_expr
.X_add_number
);
12894 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12897 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12899 /* If this is a reference to a GP relative symbol, we want
12900 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12901 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12902 If we have a base register, we use this
12904 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12905 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12906 If this is not a GP relative symbol, we want
12907 lui $at,<sym> (BFD_RELOC_HI16_S)
12908 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12909 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12910 If there is a base register, we add it to $at after the
12911 lui instruction. If there is a constant, we always use
12913 if (offset_expr
.X_op
== O_symbol
12914 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12915 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12917 relax_start (offset_expr
.X_add_symbol
);
12920 tempreg
= mips_gp_register
;
12924 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12925 AT
, breg
, mips_gp_register
);
12930 /* Itbl support may require additional care here. */
12931 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12932 BFD_RELOC_GPREL16
, tempreg
);
12933 offset_expr
.X_add_number
+= 4;
12935 /* Set mips_optimize to 2 to avoid inserting an
12937 hold_mips_optimize
= mips_optimize
;
12939 /* Itbl support may require additional care here. */
12940 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12941 BFD_RELOC_GPREL16
, tempreg
);
12942 mips_optimize
= hold_mips_optimize
;
12946 offset_expr
.X_add_number
-= 4;
12949 if (offset_high_part (offset_expr
.X_add_number
, 16)
12950 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12952 load_address (AT
, &offset_expr
, &used_at
);
12953 offset_expr
.X_op
= O_constant
;
12954 offset_expr
.X_add_number
= 0;
12957 macro_build_lui (&offset_expr
, AT
);
12959 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12960 /* Itbl support may require additional care here. */
12961 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12962 BFD_RELOC_LO16
, AT
);
12963 /* FIXME: How do we handle overflow here? */
12964 offset_expr
.X_add_number
+= 4;
12965 /* Itbl support may require additional care here. */
12966 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12967 BFD_RELOC_LO16
, AT
);
12968 if (mips_relax
.sequence
)
12971 else if (!mips_big_got
)
12973 /* If this is a reference to an external symbol, we want
12974 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12977 <op> op[0]+1,4($at)
12979 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12981 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12982 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12983 If there is a base register we add it to $at before the
12984 lwc1 instructions. If there is a constant we include it
12985 in the lwc1 instructions. */
12987 expr1
.X_add_number
= offset_expr
.X_add_number
;
12988 if (expr1
.X_add_number
< -0x8000
12989 || expr1
.X_add_number
>= 0x8000 - 4)
12990 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12991 load_got_offset (AT
, &offset_expr
);
12994 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12996 /* Set mips_optimize to 2 to avoid inserting an undesired
12998 hold_mips_optimize
= mips_optimize
;
13001 /* Itbl support may require additional care here. */
13002 relax_start (offset_expr
.X_add_symbol
);
13003 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13004 BFD_RELOC_LO16
, AT
);
13005 expr1
.X_add_number
+= 4;
13006 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13007 BFD_RELOC_LO16
, AT
);
13009 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13010 BFD_RELOC_LO16
, AT
);
13011 offset_expr
.X_add_number
+= 4;
13012 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13013 BFD_RELOC_LO16
, AT
);
13016 mips_optimize
= hold_mips_optimize
;
13018 else if (mips_big_got
)
13022 /* If this is a reference to an external symbol, we want
13023 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13025 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13028 <op> op[0]+1,4($at)
13030 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13032 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13033 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13034 If there is a base register we add it to $at before the
13035 lwc1 instructions. If there is a constant we include it
13036 in the lwc1 instructions. */
13038 expr1
.X_add_number
= offset_expr
.X_add_number
;
13039 offset_expr
.X_add_number
= 0;
13040 if (expr1
.X_add_number
< -0x8000
13041 || expr1
.X_add_number
>= 0x8000 - 4)
13042 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13043 gpdelay
= reg_needs_delay (mips_gp_register
);
13044 relax_start (offset_expr
.X_add_symbol
);
13045 macro_build (&offset_expr
, "lui", LUI_FMT
,
13046 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13047 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13048 AT
, AT
, mips_gp_register
);
13049 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13050 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13053 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13054 /* Itbl support may require additional care here. */
13055 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13056 BFD_RELOC_LO16
, AT
);
13057 expr1
.X_add_number
+= 4;
13059 /* Set mips_optimize to 2 to avoid inserting an undesired
13061 hold_mips_optimize
= mips_optimize
;
13063 /* Itbl support may require additional care here. */
13064 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13065 BFD_RELOC_LO16
, AT
);
13066 mips_optimize
= hold_mips_optimize
;
13067 expr1
.X_add_number
-= 4;
13070 offset_expr
.X_add_number
= expr1
.X_add_number
;
13072 macro_build (NULL
, "nop", "");
13073 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13074 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13077 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13078 /* Itbl support may require additional care here. */
13079 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13080 BFD_RELOC_LO16
, AT
);
13081 offset_expr
.X_add_number
+= 4;
13083 /* Set mips_optimize to 2 to avoid inserting an undesired
13085 hold_mips_optimize
= mips_optimize
;
13087 /* Itbl support may require additional care here. */
13088 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13089 BFD_RELOC_LO16
, AT
);
13090 mips_optimize
= hold_mips_optimize
;
13104 gas_assert (!mips_opts
.micromips
);
13109 /* New code added to support COPZ instructions.
13110 This code builds table entries out of the macros in mip_opcodes.
13111 R4000 uses interlocks to handle coproc delays.
13112 Other chips (like the R3000) require nops to be inserted for delays.
13114 FIXME: Currently, we require that the user handle delays.
13115 In order to fill delay slots for non-interlocked chips,
13116 we must have a way to specify delays based on the coprocessor.
13117 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13118 What are the side-effects of the cop instruction?
13119 What cache support might we have and what are its effects?
13120 Both coprocessor & memory require delays. how long???
13121 What registers are read/set/modified?
13123 If an itbl is provided to interpret cop instructions,
13124 this knowledge can be encoded in the itbl spec. */
13138 gas_assert (!mips_opts
.micromips
);
13139 /* For now we just do C (same as Cz). The parameter will be
13140 stored in insn_opcode by mips_ip. */
13141 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13145 move_register (op
[0], op
[1]);
13149 gas_assert (mips_opts
.micromips
);
13150 gas_assert (mips_opts
.insn32
);
13151 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13152 micromips_to_32_reg_m_map
[op
[1]]);
13153 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13154 micromips_to_32_reg_n_map
[op
[2]]);
13159 /* Fall through. */
13161 if (mips_opts
.arch
== CPU_R5900
)
13162 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13166 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13167 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13173 /* Fall through. */
13175 /* The MIPS assembler some times generates shifts and adds. I'm
13176 not trying to be that fancy. GCC should do this for us
13179 load_register (AT
, &imm_expr
, dbl
);
13180 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13181 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13186 /* Fall through. */
13193 /* Fall through. */
13196 start_noreorder ();
13199 load_register (AT
, &imm_expr
, dbl
);
13200 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13201 op
[1], imm
? AT
: op
[2]);
13202 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13203 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13204 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13206 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13209 if (mips_opts
.micromips
)
13210 micromips_label_expr (&label_expr
);
13212 label_expr
.X_add_number
= 8;
13213 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13214 macro_build (NULL
, "nop", "");
13215 macro_build (NULL
, "break", BRK_FMT
, 6);
13216 if (mips_opts
.micromips
)
13217 micromips_add_label ();
13220 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13225 /* Fall through. */
13232 /* Fall through. */
13235 start_noreorder ();
13238 load_register (AT
, &imm_expr
, dbl
);
13239 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13240 op
[1], imm
? AT
: op
[2]);
13241 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13242 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13244 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13247 if (mips_opts
.micromips
)
13248 micromips_label_expr (&label_expr
);
13250 label_expr
.X_add_number
= 8;
13251 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13252 macro_build (NULL
, "nop", "");
13253 macro_build (NULL
, "break", BRK_FMT
, 6);
13254 if (mips_opts
.micromips
)
13255 micromips_add_label ();
13261 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13263 if (op
[0] == op
[1])
13270 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13271 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13275 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13276 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13277 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13278 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13282 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13284 if (op
[0] == op
[1])
13291 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13292 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13296 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13297 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13298 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13299 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13308 rot
= imm_expr
.X_add_number
& 0x3f;
13309 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13311 rot
= (64 - rot
) & 0x3f;
13313 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13315 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13320 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13323 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13324 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13327 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13328 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13329 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13337 rot
= imm_expr
.X_add_number
& 0x1f;
13338 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13340 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13341 (32 - rot
) & 0x1f);
13346 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13350 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13351 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13352 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13357 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13359 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13363 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13364 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13365 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13366 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13370 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13372 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13376 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13377 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13378 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13379 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13388 rot
= imm_expr
.X_add_number
& 0x3f;
13389 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13392 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13394 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13399 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13402 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13403 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13406 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13407 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13408 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13416 rot
= imm_expr
.X_add_number
& 0x1f;
13417 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13419 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13424 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13428 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13429 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13430 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13436 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13437 else if (op
[2] == 0)
13438 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13441 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13442 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13447 if (imm_expr
.X_add_number
== 0)
13449 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13454 as_warn (_("instruction %s: result is always false"),
13455 ip
->insn_mo
->name
);
13456 move_register (op
[0], 0);
13459 if (CPU_HAS_SEQ (mips_opts
.arch
)
13460 && -512 <= imm_expr
.X_add_number
13461 && imm_expr
.X_add_number
< 512)
13463 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13464 (int) imm_expr
.X_add_number
);
13467 if (imm_expr
.X_add_number
>= 0
13468 && imm_expr
.X_add_number
< 0x10000)
13469 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13470 else if (imm_expr
.X_add_number
> -0x8000
13471 && imm_expr
.X_add_number
< 0)
13473 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13474 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13475 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13477 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13480 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13481 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13486 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13487 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13490 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13493 case M_SGE
: /* X >= Y <==> not (X < Y) */
13499 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13500 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13503 case M_SGE_I
: /* X >= I <==> not (X < I). */
13505 if (imm_expr
.X_add_number
>= -0x8000
13506 && imm_expr
.X_add_number
< 0x8000)
13507 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13508 op
[0], op
[1], BFD_RELOC_LO16
);
13511 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13512 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13516 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13519 case M_SGT
: /* X > Y <==> Y < X. */
13525 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13528 case M_SGT_I
: /* X > I <==> I < X. */
13535 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13536 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13539 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13545 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13546 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13549 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13556 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13557 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13558 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13562 if (imm_expr
.X_add_number
>= -0x8000
13563 && imm_expr
.X_add_number
< 0x8000)
13565 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13570 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13571 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13575 if (imm_expr
.X_add_number
>= -0x8000
13576 && imm_expr
.X_add_number
< 0x8000)
13578 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13583 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13584 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13589 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13590 else if (op
[2] == 0)
13591 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13594 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13595 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13600 if (imm_expr
.X_add_number
== 0)
13602 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13607 as_warn (_("instruction %s: result is always true"),
13608 ip
->insn_mo
->name
);
13609 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13610 op
[0], 0, BFD_RELOC_LO16
);
13613 if (CPU_HAS_SEQ (mips_opts
.arch
)
13614 && -512 <= imm_expr
.X_add_number
13615 && imm_expr
.X_add_number
< 512)
13617 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13618 (int) imm_expr
.X_add_number
);
13621 if (imm_expr
.X_add_number
>= 0
13622 && imm_expr
.X_add_number
< 0x10000)
13624 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13627 else if (imm_expr
.X_add_number
> -0x8000
13628 && imm_expr
.X_add_number
< 0)
13630 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13631 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13632 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13634 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13637 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13638 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13643 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13644 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13647 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13662 if (!mips_opts
.micromips
)
13664 if (imm_expr
.X_add_number
> -0x200
13665 && imm_expr
.X_add_number
<= 0x200)
13667 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13668 (int) -imm_expr
.X_add_number
);
13677 if (imm_expr
.X_add_number
> -0x8000
13678 && imm_expr
.X_add_number
<= 0x8000)
13680 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13681 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13686 load_register (AT
, &imm_expr
, dbl
);
13687 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13709 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13710 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13715 gas_assert (!mips_opts
.micromips
);
13716 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13720 * Is the double cfc1 instruction a bug in the mips assembler;
13721 * or is there a reason for it?
13723 start_noreorder ();
13724 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13725 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13726 macro_build (NULL
, "nop", "");
13727 expr1
.X_add_number
= 3;
13728 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13729 expr1
.X_add_number
= 2;
13730 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13731 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13732 macro_build (NULL
, "nop", "");
13733 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13735 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13736 macro_build (NULL
, "nop", "");
13753 offbits
= (mips_opts
.micromips
? 12 : 16);
13759 offbits
= (mips_opts
.micromips
? 12 : 16);
13771 offbits
= (mips_opts
.micromips
? 12 : 16);
13778 offbits
= (mips_opts
.micromips
? 12 : 16);
13784 large_offset
= !small_offset_p (off
, align
, offbits
);
13786 expr1
.X_add_number
= 0;
13791 if (small_offset_p (0, align
, 16))
13792 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13793 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13796 load_address (tempreg
, ep
, &used_at
);
13798 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13799 tempreg
, tempreg
, breg
);
13801 offset_reloc
[0] = BFD_RELOC_LO16
;
13802 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13803 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13808 else if (!ust
&& op
[0] == breg
)
13819 if (!target_big_endian
)
13820 ep
->X_add_number
+= off
;
13822 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13824 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13825 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13827 if (!target_big_endian
)
13828 ep
->X_add_number
-= off
;
13830 ep
->X_add_number
+= off
;
13832 macro_build (NULL
, s2
, "t,~(b)",
13833 tempreg
, (int) ep
->X_add_number
, breg
);
13835 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13836 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13838 /* If necessary, move the result in tempreg to the final destination. */
13839 if (!ust
&& op
[0] != tempreg
)
13841 /* Protect second load's delay slot. */
13843 move_register (op
[0], tempreg
);
13849 if (target_big_endian
== ust
)
13850 ep
->X_add_number
+= off
;
13851 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13852 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13853 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13855 /* For halfword transfers we need a temporary register to shuffle
13856 bytes. Unfortunately for M_USH_A we have none available before
13857 the next store as AT holds the base address. We deal with this
13858 case by clobbering TREG and then restoring it as with ULH. */
13859 tempreg
= ust
== large_offset
? op
[0] : AT
;
13861 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13863 if (target_big_endian
== ust
)
13864 ep
->X_add_number
-= off
;
13866 ep
->X_add_number
+= off
;
13867 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13868 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13870 /* For M_USH_A re-retrieve the LSB. */
13871 if (ust
&& large_offset
)
13873 if (target_big_endian
)
13874 ep
->X_add_number
+= off
;
13876 ep
->X_add_number
-= off
;
13877 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13878 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13880 /* For ULH and M_USH_A OR the LSB in. */
13881 if (!ust
|| large_offset
)
13883 tempreg
= !large_offset
? AT
: op
[0];
13884 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13885 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13890 /* FIXME: Check if this is one of the itbl macros, since they
13891 are added dynamically. */
13892 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13895 if (!mips_opts
.at
&& used_at
)
13896 as_bad (_("macro used $at after \".set noat\""));
13899 /* Implement macros in mips16 mode. */
13902 mips16_macro (struct mips_cl_insn
*ip
)
13904 const struct mips_operand_array
*operands
;
13909 const char *s
, *s2
, *s3
;
13910 unsigned int op
[MAX_OPERANDS
];
13913 mask
= ip
->insn_mo
->mask
;
13915 operands
= insn_operands (ip
);
13916 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13917 if (operands
->operand
[i
])
13918 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13922 expr1
.X_op
= O_constant
;
13923 expr1
.X_op_symbol
= NULL
;
13924 expr1
.X_add_symbol
= NULL
;
13925 expr1
.X_add_number
= 1;
13936 /* Fall through. */
13942 /* Fall through. */
13946 start_noreorder ();
13947 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13948 expr1
.X_add_number
= 2;
13949 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13950 macro_build (NULL
, "break", "6", 7);
13952 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13953 since that causes an overflow. We should do that as well,
13954 but I don't see how to do the comparisons without a temporary
13957 macro_build (NULL
, s
, "x", op
[0]);
13976 start_noreorder ();
13977 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13978 expr1
.X_add_number
= 2;
13979 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13980 macro_build (NULL
, "break", "6", 7);
13982 macro_build (NULL
, s2
, "x", op
[0]);
13987 /* Fall through. */
13989 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13990 macro_build (NULL
, "mflo", "x", op
[0]);
13998 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13999 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14003 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14004 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14008 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14009 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14031 goto do_reverse_branch
;
14035 goto do_reverse_branch
;
14047 goto do_reverse_branch
;
14058 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14059 macro_build (&offset_expr
, s2
, "p");
14086 goto do_addone_branch_i
;
14091 goto do_addone_branch_i
;
14106 goto do_addone_branch_i
;
14112 do_addone_branch_i
:
14113 ++imm_expr
.X_add_number
;
14116 macro_build (&imm_expr
, s
, s3
, op
[0]);
14117 macro_build (&offset_expr
, s2
, "p");
14121 expr1
.X_add_number
= 0;
14122 macro_build (&expr1
, "slti", "x,8", op
[1]);
14123 if (op
[0] != op
[1])
14124 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14125 expr1
.X_add_number
= 2;
14126 macro_build (&expr1
, "bteqz", "p");
14127 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14132 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14133 opcode bits in *OPCODE_EXTRA. */
14135 static struct mips_opcode
*
14136 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14137 ssize_t length
, unsigned int *opcode_extra
)
14139 char *name
, *dot
, *p
;
14140 unsigned int mask
, suffix
;
14142 struct mips_opcode
*insn
;
14144 /* Make a copy of the instruction so that we can fiddle with it. */
14145 name
= xstrndup (start
, length
);
14147 /* Look up the instruction as-is. */
14148 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14152 dot
= strchr (name
, '.');
14155 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14156 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14157 if (*p
== 0 && mask
!= 0)
14160 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14162 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14164 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14170 if (mips_opts
.micromips
)
14172 /* See if there's an instruction size override suffix,
14173 either `16' or `32', at the end of the mnemonic proper,
14174 that defines the operation, i.e. before the first `.'
14175 character if any. Strip it and retry. */
14176 opend
= dot
!= NULL
? dot
- name
: length
;
14177 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14179 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14185 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14186 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14189 forced_insn_length
= suffix
;
14201 /* Assemble an instruction into its binary format. If the instruction
14202 is a macro, set imm_expr and offset_expr to the values associated
14203 with "I" and "A" operands respectively. Otherwise store the value
14204 of the relocatable field (if any) in offset_expr. In both cases
14205 set offset_reloc to the relocation operators applied to offset_expr. */
14208 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14210 const struct mips_opcode
*first
, *past
;
14211 struct hash_control
*hash
;
14214 struct mips_operand_token
*tokens
;
14215 unsigned int opcode_extra
;
14217 if (mips_opts
.micromips
)
14219 hash
= micromips_op_hash
;
14220 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14225 past
= &mips_opcodes
[NUMOPCODES
];
14227 forced_insn_length
= 0;
14230 /* We first try to match an instruction up to a space or to the end. */
14231 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14234 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14237 set_insn_error (0, _("unrecognized opcode"));
14241 if (strcmp (first
->name
, "li.s") == 0)
14243 else if (strcmp (first
->name
, "li.d") == 0)
14247 tokens
= mips_parse_arguments (str
+ end
, format
);
14251 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14252 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14253 set_insn_error (0, _("invalid operands"));
14255 obstack_free (&mips_operand_tokens
, tokens
);
14258 /* As for mips_ip, but used when assembling MIPS16 code.
14259 Also set forced_insn_length to the resulting instruction size in
14260 bytes if the user explicitly requested a small or extended instruction. */
14263 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14266 struct mips_opcode
*first
;
14267 struct mips_operand_token
*tokens
;
14270 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14292 else if (*s
== 'e')
14299 else if (*s
++ == ' ')
14301 set_insn_error (0, _("unrecognized opcode"));
14304 forced_insn_length
= l
;
14307 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14312 set_insn_error (0, _("unrecognized opcode"));
14316 tokens
= mips_parse_arguments (s
, 0);
14320 if (!match_mips16_insns (insn
, first
, tokens
))
14321 set_insn_error (0, _("invalid operands"));
14323 obstack_free (&mips_operand_tokens
, tokens
);
14326 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14327 NBITS is the number of significant bits in VAL. */
14329 static unsigned long
14330 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14335 val
&= (1U << nbits
) - 1;
14336 if (nbits
== 16 || nbits
== 9)
14338 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14341 else if (nbits
== 15)
14343 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14346 else if (nbits
== 6)
14348 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14351 return (extval
<< 16) | val
;
14354 /* Like decode_mips16_operand, but require the operand to be defined and
14355 require it to be an integer. */
14357 static const struct mips_int_operand
*
14358 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14360 const struct mips_operand
*operand
;
14362 operand
= decode_mips16_operand (type
, extended_p
);
14363 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14365 return (const struct mips_int_operand
*) operand
;
14368 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14371 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14372 bfd_reloc_code_real_type reloc
, offsetT sval
)
14374 int min_val
, max_val
;
14376 min_val
= mips_int_operand_min (operand
);
14377 max_val
= mips_int_operand_max (operand
);
14378 if (reloc
!= BFD_RELOC_UNUSED
)
14381 sval
= SEXT_16BIT (sval
);
14386 return (sval
>= min_val
14388 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14391 /* Install immediate value VAL into MIPS16 instruction *INSN,
14392 extending it if necessary. The instruction in *INSN may
14393 already be extended.
14395 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14396 if none. In the former case, VAL is a 16-bit number with no
14397 defined signedness.
14399 TYPE is the type of the immediate field. USER_INSN_LENGTH
14400 is the length that the user requested, or 0 if none. */
14403 mips16_immed (const char *file
, unsigned int line
, int type
,
14404 bfd_reloc_code_real_type reloc
, offsetT val
,
14405 unsigned int user_insn_length
, unsigned long *insn
)
14407 const struct mips_int_operand
*operand
;
14408 unsigned int uval
, length
;
14410 operand
= mips16_immed_operand (type
, FALSE
);
14411 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14413 /* We need an extended instruction. */
14414 if (user_insn_length
== 2)
14415 as_bad_where (file
, line
, _("invalid unextended operand value"));
14417 *insn
|= MIPS16_EXTEND
;
14419 else if (user_insn_length
== 4)
14421 /* The operand doesn't force an unextended instruction to be extended.
14422 Warn if the user wanted an extended instruction anyway. */
14423 *insn
|= MIPS16_EXTEND
;
14424 as_warn_where (file
, line
,
14425 _("extended operand requested but not required"));
14428 length
= mips16_opcode_length (*insn
);
14431 operand
= mips16_immed_operand (type
, TRUE
);
14432 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14433 as_bad_where (file
, line
,
14434 _("operand value out of range for instruction"));
14436 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14437 if (length
== 2 || operand
->root
.lsb
!= 0)
14438 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14440 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14443 struct percent_op_match
14446 bfd_reloc_code_real_type reloc
;
14449 static const struct percent_op_match mips_percent_op
[] =
14451 {"%lo", BFD_RELOC_LO16
},
14452 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14453 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14454 {"%call16", BFD_RELOC_MIPS_CALL16
},
14455 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14456 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14457 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14458 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14459 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14460 {"%got", BFD_RELOC_MIPS_GOT16
},
14461 {"%gp_rel", BFD_RELOC_GPREL16
},
14462 {"%gprel", BFD_RELOC_GPREL16
},
14463 {"%half", BFD_RELOC_16
},
14464 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14465 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14466 {"%neg", BFD_RELOC_MIPS_SUB
},
14467 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14468 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14469 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14470 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14471 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14472 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14473 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14474 {"%hi", BFD_RELOC_HI16_S
},
14475 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14476 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14479 static const struct percent_op_match mips16_percent_op
[] =
14481 {"%lo", BFD_RELOC_MIPS16_LO16
},
14482 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14483 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14484 {"%got", BFD_RELOC_MIPS16_GOT16
},
14485 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14486 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14487 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14488 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14489 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14490 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14491 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14492 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14493 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14497 /* Return true if *STR points to a relocation operator. When returning true,
14498 move *STR over the operator and store its relocation code in *RELOC.
14499 Leave both *STR and *RELOC alone when returning false. */
14502 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14504 const struct percent_op_match
*percent_op
;
14507 if (mips_opts
.mips16
)
14509 percent_op
= mips16_percent_op
;
14510 limit
= ARRAY_SIZE (mips16_percent_op
);
14514 percent_op
= mips_percent_op
;
14515 limit
= ARRAY_SIZE (mips_percent_op
);
14518 for (i
= 0; i
< limit
; i
++)
14519 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14521 int len
= strlen (percent_op
[i
].str
);
14523 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14526 *str
+= strlen (percent_op
[i
].str
);
14527 *reloc
= percent_op
[i
].reloc
;
14529 /* Check whether the output BFD supports this relocation.
14530 If not, issue an error and fall back on something safe. */
14531 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14533 as_bad (_("relocation %s isn't supported by the current ABI"),
14534 percent_op
[i
].str
);
14535 *reloc
= BFD_RELOC_UNUSED
;
14543 /* Parse string STR as a 16-bit relocatable operand. Store the
14544 expression in *EP and the relocations in the array starting
14545 at RELOC. Return the number of relocation operators used.
14547 On exit, EXPR_END points to the first character after the expression. */
14550 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14553 bfd_reloc_code_real_type reversed_reloc
[3];
14554 size_t reloc_index
, i
;
14555 int crux_depth
, str_depth
;
14558 /* Search for the start of the main expression, recoding relocations
14559 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14560 of the main expression and with CRUX_DEPTH containing the number
14561 of open brackets at that point. */
14568 crux_depth
= str_depth
;
14570 /* Skip over whitespace and brackets, keeping count of the number
14572 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14577 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14578 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14580 my_getExpression (ep
, crux
);
14583 /* Match every open bracket. */
14584 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14588 if (crux_depth
> 0)
14589 as_bad (_("unclosed '('"));
14593 if (reloc_index
!= 0)
14595 prev_reloc_op_frag
= frag_now
;
14596 for (i
= 0; i
< reloc_index
; i
++)
14597 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14600 return reloc_index
;
14604 my_getExpression (expressionS
*ep
, char *str
)
14608 save_in
= input_line_pointer
;
14609 input_line_pointer
= str
;
14611 expr_end
= input_line_pointer
;
14612 input_line_pointer
= save_in
;
14616 md_atof (int type
, char *litP
, int *sizeP
)
14618 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14622 md_number_to_chars (char *buf
, valueT val
, int n
)
14624 if (target_big_endian
)
14625 number_to_chars_bigendian (buf
, val
, n
);
14627 number_to_chars_littleendian (buf
, val
, n
);
14630 static int support_64bit_objects(void)
14632 const char **list
, **l
;
14635 list
= bfd_target_list ();
14636 for (l
= list
; *l
!= NULL
; l
++)
14637 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14638 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14640 yes
= (*l
!= NULL
);
14645 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14646 NEW_VALUE. Warn if another value was already specified. Note:
14647 we have to defer parsing the -march and -mtune arguments in order
14648 to handle 'from-abi' correctly, since the ABI might be specified
14649 in a later argument. */
14652 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14654 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14655 as_warn (_("a different %s was already specified, is now %s"),
14656 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14659 *string_ptr
= new_value
;
14663 md_parse_option (int c
, const char *arg
)
14667 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14668 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14670 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14671 c
== mips_ases
[i
].option_on
);
14677 case OPTION_CONSTRUCT_FLOATS
:
14678 mips_disable_float_construction
= 0;
14681 case OPTION_NO_CONSTRUCT_FLOATS
:
14682 mips_disable_float_construction
= 1;
14694 target_big_endian
= 1;
14698 target_big_endian
= 0;
14704 else if (arg
[0] == '0')
14706 else if (arg
[0] == '1')
14716 mips_debug
= atoi (arg
);
14720 file_mips_opts
.isa
= ISA_MIPS1
;
14724 file_mips_opts
.isa
= ISA_MIPS2
;
14728 file_mips_opts
.isa
= ISA_MIPS3
;
14732 file_mips_opts
.isa
= ISA_MIPS4
;
14736 file_mips_opts
.isa
= ISA_MIPS5
;
14739 case OPTION_MIPS32
:
14740 file_mips_opts
.isa
= ISA_MIPS32
;
14743 case OPTION_MIPS32R2
:
14744 file_mips_opts
.isa
= ISA_MIPS32R2
;
14747 case OPTION_MIPS32R3
:
14748 file_mips_opts
.isa
= ISA_MIPS32R3
;
14751 case OPTION_MIPS32R5
:
14752 file_mips_opts
.isa
= ISA_MIPS32R5
;
14755 case OPTION_MIPS32R6
:
14756 file_mips_opts
.isa
= ISA_MIPS32R6
;
14759 case OPTION_MIPS64R2
:
14760 file_mips_opts
.isa
= ISA_MIPS64R2
;
14763 case OPTION_MIPS64R3
:
14764 file_mips_opts
.isa
= ISA_MIPS64R3
;
14767 case OPTION_MIPS64R5
:
14768 file_mips_opts
.isa
= ISA_MIPS64R5
;
14771 case OPTION_MIPS64R6
:
14772 file_mips_opts
.isa
= ISA_MIPS64R6
;
14775 case OPTION_MIPS64
:
14776 file_mips_opts
.isa
= ISA_MIPS64
;
14780 mips_set_option_string (&mips_tune_string
, arg
);
14784 mips_set_option_string (&mips_arch_string
, arg
);
14788 mips_set_option_string (&mips_arch_string
, "4650");
14789 mips_set_option_string (&mips_tune_string
, "4650");
14792 case OPTION_NO_M4650
:
14796 mips_set_option_string (&mips_arch_string
, "4010");
14797 mips_set_option_string (&mips_tune_string
, "4010");
14800 case OPTION_NO_M4010
:
14804 mips_set_option_string (&mips_arch_string
, "4100");
14805 mips_set_option_string (&mips_tune_string
, "4100");
14808 case OPTION_NO_M4100
:
14812 mips_set_option_string (&mips_arch_string
, "3900");
14813 mips_set_option_string (&mips_tune_string
, "3900");
14816 case OPTION_NO_M3900
:
14819 case OPTION_MICROMIPS
:
14820 if (file_mips_opts
.mips16
== 1)
14822 as_bad (_("-mmicromips cannot be used with -mips16"));
14825 file_mips_opts
.micromips
= 1;
14826 mips_no_prev_insn ();
14829 case OPTION_NO_MICROMIPS
:
14830 file_mips_opts
.micromips
= 0;
14831 mips_no_prev_insn ();
14834 case OPTION_MIPS16
:
14835 if (file_mips_opts
.micromips
== 1)
14837 as_bad (_("-mips16 cannot be used with -micromips"));
14840 file_mips_opts
.mips16
= 1;
14841 mips_no_prev_insn ();
14844 case OPTION_NO_MIPS16
:
14845 file_mips_opts
.mips16
= 0;
14846 mips_no_prev_insn ();
14849 case OPTION_FIX_24K
:
14853 case OPTION_NO_FIX_24K
:
14857 case OPTION_FIX_RM7000
:
14858 mips_fix_rm7000
= 1;
14861 case OPTION_NO_FIX_RM7000
:
14862 mips_fix_rm7000
= 0;
14865 case OPTION_FIX_LOONGSON3_LLSC
:
14866 mips_fix_loongson3_llsc
= TRUE
;
14869 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14870 mips_fix_loongson3_llsc
= FALSE
;
14873 case OPTION_FIX_LOONGSON2F_JUMP
:
14874 mips_fix_loongson2f_jump
= TRUE
;
14877 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14878 mips_fix_loongson2f_jump
= FALSE
;
14881 case OPTION_FIX_LOONGSON2F_NOP
:
14882 mips_fix_loongson2f_nop
= TRUE
;
14885 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14886 mips_fix_loongson2f_nop
= FALSE
;
14889 case OPTION_FIX_VR4120
:
14890 mips_fix_vr4120
= 1;
14893 case OPTION_NO_FIX_VR4120
:
14894 mips_fix_vr4120
= 0;
14897 case OPTION_FIX_VR4130
:
14898 mips_fix_vr4130
= 1;
14901 case OPTION_NO_FIX_VR4130
:
14902 mips_fix_vr4130
= 0;
14905 case OPTION_FIX_CN63XXP1
:
14906 mips_fix_cn63xxp1
= TRUE
;
14909 case OPTION_NO_FIX_CN63XXP1
:
14910 mips_fix_cn63xxp1
= FALSE
;
14913 case OPTION_FIX_R5900
:
14914 mips_fix_r5900
= TRUE
;
14915 mips_fix_r5900_explicit
= TRUE
;
14918 case OPTION_NO_FIX_R5900
:
14919 mips_fix_r5900
= FALSE
;
14920 mips_fix_r5900_explicit
= TRUE
;
14923 case OPTION_RELAX_BRANCH
:
14924 mips_relax_branch
= 1;
14927 case OPTION_NO_RELAX_BRANCH
:
14928 mips_relax_branch
= 0;
14931 case OPTION_IGNORE_BRANCH_ISA
:
14932 mips_ignore_branch_isa
= TRUE
;
14935 case OPTION_NO_IGNORE_BRANCH_ISA
:
14936 mips_ignore_branch_isa
= FALSE
;
14939 case OPTION_INSN32
:
14940 file_mips_opts
.insn32
= TRUE
;
14943 case OPTION_NO_INSN32
:
14944 file_mips_opts
.insn32
= FALSE
;
14947 case OPTION_MSHARED
:
14948 mips_in_shared
= TRUE
;
14951 case OPTION_MNO_SHARED
:
14952 mips_in_shared
= FALSE
;
14955 case OPTION_MSYM32
:
14956 file_mips_opts
.sym32
= TRUE
;
14959 case OPTION_MNO_SYM32
:
14960 file_mips_opts
.sym32
= FALSE
;
14963 /* When generating ELF code, we permit -KPIC and -call_shared to
14964 select SVR4_PIC, and -non_shared to select no PIC. This is
14965 intended to be compatible with Irix 5. */
14966 case OPTION_CALL_SHARED
:
14967 mips_pic
= SVR4_PIC
;
14968 mips_abicalls
= TRUE
;
14971 case OPTION_CALL_NONPIC
:
14973 mips_abicalls
= TRUE
;
14976 case OPTION_NON_SHARED
:
14978 mips_abicalls
= FALSE
;
14981 /* The -xgot option tells the assembler to use 32 bit offsets
14982 when accessing the got in SVR4_PIC mode. It is for Irix
14989 g_switch_value
= atoi (arg
);
14993 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14996 mips_abi
= O32_ABI
;
15000 mips_abi
= N32_ABI
;
15004 mips_abi
= N64_ABI
;
15005 if (!support_64bit_objects())
15006 as_fatal (_("no compiled in support for 64 bit object file format"));
15010 file_mips_opts
.gp
= 32;
15014 file_mips_opts
.gp
= 64;
15018 file_mips_opts
.fp
= 32;
15022 file_mips_opts
.fp
= 0;
15026 file_mips_opts
.fp
= 64;
15029 case OPTION_ODD_SPREG
:
15030 file_mips_opts
.oddspreg
= 1;
15033 case OPTION_NO_ODD_SPREG
:
15034 file_mips_opts
.oddspreg
= 0;
15037 case OPTION_SINGLE_FLOAT
:
15038 file_mips_opts
.single_float
= 1;
15041 case OPTION_DOUBLE_FLOAT
:
15042 file_mips_opts
.single_float
= 0;
15045 case OPTION_SOFT_FLOAT
:
15046 file_mips_opts
.soft_float
= 1;
15049 case OPTION_HARD_FLOAT
:
15050 file_mips_opts
.soft_float
= 0;
15054 if (strcmp (arg
, "32") == 0)
15055 mips_abi
= O32_ABI
;
15056 else if (strcmp (arg
, "o64") == 0)
15057 mips_abi
= O64_ABI
;
15058 else if (strcmp (arg
, "n32") == 0)
15059 mips_abi
= N32_ABI
;
15060 else if (strcmp (arg
, "64") == 0)
15062 mips_abi
= N64_ABI
;
15063 if (! support_64bit_objects())
15064 as_fatal (_("no compiled in support for 64 bit object file "
15067 else if (strcmp (arg
, "eabi") == 0)
15068 mips_abi
= EABI_ABI
;
15071 as_fatal (_("invalid abi -mabi=%s"), arg
);
15076 case OPTION_M7000_HILO_FIX
:
15077 mips_7000_hilo_fix
= TRUE
;
15080 case OPTION_MNO_7000_HILO_FIX
:
15081 mips_7000_hilo_fix
= FALSE
;
15084 case OPTION_MDEBUG
:
15085 mips_flag_mdebug
= TRUE
;
15088 case OPTION_NO_MDEBUG
:
15089 mips_flag_mdebug
= FALSE
;
15093 mips_flag_pdr
= TRUE
;
15096 case OPTION_NO_PDR
:
15097 mips_flag_pdr
= FALSE
;
15100 case OPTION_MVXWORKS_PIC
:
15101 mips_pic
= VXWORKS_PIC
;
15105 if (strcmp (arg
, "2008") == 0)
15107 else if (strcmp (arg
, "legacy") == 0)
15111 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15120 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15125 /* Set up globals to tune for the ISA or processor described by INFO. */
15128 mips_set_tune (const struct mips_cpu_info
*info
)
15131 mips_tune
= info
->cpu
;
15136 mips_after_parse_args (void)
15138 const struct mips_cpu_info
*arch_info
= 0;
15139 const struct mips_cpu_info
*tune_info
= 0;
15141 /* GP relative stuff not working for PE. */
15142 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15144 if (g_switch_seen
&& g_switch_value
!= 0)
15145 as_bad (_("-G not supported in this configuration"));
15146 g_switch_value
= 0;
15149 if (mips_abi
== NO_ABI
)
15150 mips_abi
= MIPS_DEFAULT_ABI
;
15152 /* The following code determines the architecture.
15153 Similar code was added to GCC 3.3 (see override_options() in
15154 config/mips/mips.c). The GAS and GCC code should be kept in sync
15155 as much as possible. */
15157 if (mips_arch_string
!= 0)
15158 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15160 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15162 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15163 ISA level specified by -mipsN, while arch_info->isa contains
15164 the -march selection (if any). */
15165 if (arch_info
!= 0)
15167 /* -march takes precedence over -mipsN, since it is more descriptive.
15168 There's no harm in specifying both as long as the ISA levels
15170 if (file_mips_opts
.isa
!= arch_info
->isa
)
15171 as_bad (_("-%s conflicts with the other architecture options,"
15172 " which imply -%s"),
15173 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15174 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15177 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15180 if (arch_info
== 0)
15182 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15183 gas_assert (arch_info
);
15186 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15187 as_bad (_("-march=%s is not compatible with the selected ABI"),
15190 file_mips_opts
.arch
= arch_info
->cpu
;
15191 file_mips_opts
.isa
= arch_info
->isa
;
15193 /* Set up initial mips_opts state. */
15194 mips_opts
= file_mips_opts
;
15196 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15197 if (!mips_fix_r5900_explicit
)
15198 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15200 /* The register size inference code is now placed in
15201 file_mips_check_options. */
15203 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15205 if (mips_tune_string
!= 0)
15206 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15208 if (tune_info
== 0)
15209 mips_set_tune (arch_info
);
15211 mips_set_tune (tune_info
);
15213 if (mips_flag_mdebug
< 0)
15214 mips_flag_mdebug
= 0;
15218 mips_init_after_args (void)
15220 /* Initialize opcodes. */
15221 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15222 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15226 md_pcrel_from (fixS
*fixP
)
15228 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15230 switch (fixP
->fx_r_type
)
15232 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15233 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15234 /* Return the address of the delay slot. */
15237 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15238 case BFD_RELOC_MICROMIPS_JMP
:
15239 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15240 case BFD_RELOC_16_PCREL_S2
:
15241 case BFD_RELOC_MIPS_21_PCREL_S2
:
15242 case BFD_RELOC_MIPS_26_PCREL_S2
:
15243 case BFD_RELOC_MIPS_JMP
:
15244 /* Return the address of the delay slot. */
15247 case BFD_RELOC_MIPS_18_PCREL_S3
:
15248 /* Return the aligned address of the doubleword containing
15249 the instruction. */
15257 /* This is called before the symbol table is processed. In order to
15258 work with gcc when using mips-tfile, we must keep all local labels.
15259 However, in other cases, we want to discard them. If we were
15260 called with -g, but we didn't see any debugging information, it may
15261 mean that gcc is smuggling debugging information through to
15262 mips-tfile, in which case we must generate all local labels. */
15265 mips_frob_file_before_adjust (void)
15267 #ifndef NO_ECOFF_DEBUGGING
15268 if (ECOFF_DEBUGGING
15270 && ! ecoff_debugging_seen
)
15271 flag_keep_locals
= 1;
15275 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15276 the corresponding LO16 reloc. This is called before md_apply_fix and
15277 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15278 relocation operators.
15280 For our purposes, a %lo() expression matches a %got() or %hi()
15283 (a) it refers to the same symbol; and
15284 (b) the offset applied in the %lo() expression is no lower than
15285 the offset applied in the %got() or %hi().
15287 (b) allows us to cope with code like:
15290 lh $4,%lo(foo+2)($4)
15292 ...which is legal on RELA targets, and has a well-defined behaviour
15293 if the user knows that adding 2 to "foo" will not induce a carry to
15296 When several %lo()s match a particular %got() or %hi(), we use the
15297 following rules to distinguish them:
15299 (1) %lo()s with smaller offsets are a better match than %lo()s with
15302 (2) %lo()s with no matching %got() or %hi() are better than those
15303 that already have a matching %got() or %hi().
15305 (3) later %lo()s are better than earlier %lo()s.
15307 These rules are applied in order.
15309 (1) means, among other things, that %lo()s with identical offsets are
15310 chosen if they exist.
15312 (2) means that we won't associate several high-part relocations with
15313 the same low-part relocation unless there's no alternative. Having
15314 several high parts for the same low part is a GNU extension; this rule
15315 allows careful users to avoid it.
15317 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15318 with the last high-part relocation being at the front of the list.
15319 It therefore makes sense to choose the last matching low-part
15320 relocation, all other things being equal. It's also easier
15321 to code that way. */
15324 mips_frob_file (void)
15326 struct mips_hi_fixup
*l
;
15327 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15329 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15331 segment_info_type
*seginfo
;
15332 bfd_boolean matched_lo_p
;
15333 fixS
**hi_pos
, **lo_pos
, **pos
;
15335 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15337 /* If a GOT16 relocation turns out to be against a global symbol,
15338 there isn't supposed to be a matching LO. Ignore %gots against
15339 constants; we'll report an error for those later. */
15340 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15341 && !(l
->fixp
->fx_addsy
15342 && pic_need_relax (l
->fixp
->fx_addsy
)))
15345 /* Check quickly whether the next fixup happens to be a matching %lo. */
15346 if (fixup_has_matching_lo_p (l
->fixp
))
15349 seginfo
= seg_info (l
->seg
);
15351 /* Set HI_POS to the position of this relocation in the chain.
15352 Set LO_POS to the position of the chosen low-part relocation.
15353 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15354 relocation that matches an immediately-preceding high-part
15358 matched_lo_p
= FALSE
;
15359 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15361 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15363 if (*pos
== l
->fixp
)
15366 if ((*pos
)->fx_r_type
== looking_for_rtype
15367 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15368 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15370 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15372 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15375 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15376 && fixup_has_matching_lo_p (*pos
));
15379 /* If we found a match, remove the high-part relocation from its
15380 current position and insert it before the low-part relocation.
15381 Make the offsets match so that fixup_has_matching_lo_p()
15384 We don't warn about unmatched high-part relocations since some
15385 versions of gcc have been known to emit dead "lui ...%hi(...)"
15387 if (lo_pos
!= NULL
)
15389 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15390 if (l
->fixp
->fx_next
!= *lo_pos
)
15392 *hi_pos
= l
->fixp
->fx_next
;
15393 l
->fixp
->fx_next
= *lo_pos
;
15401 mips_force_relocation (fixS
*fixp
)
15403 if (generic_force_reloc (fixp
))
15406 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15407 so that the linker relaxation can update targets. */
15408 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15409 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15410 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15413 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15414 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15415 microMIPS symbols so that we can do cross-mode branch diagnostics
15416 and BAL to JALX conversion by the linker. */
15417 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15418 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15419 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15421 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15424 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15425 if (ISA_IS_R6 (file_mips_opts
.isa
)
15426 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15427 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15428 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15429 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15430 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15431 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15432 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15438 /* Implement TC_FORCE_RELOCATION_ABS. */
15441 mips_force_relocation_abs (fixS
*fixp
)
15443 if (generic_force_reloc (fixp
))
15446 /* These relocations do not have enough bits in the in-place addend
15447 to hold an arbitrary absolute section's offset. */
15448 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15454 /* Read the instruction associated with RELOC from BUF. */
15456 static unsigned int
15457 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15459 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15460 return read_compressed_insn (buf
, 4);
15462 return read_insn (buf
);
15465 /* Write instruction INSN to BUF, given that it has been relocated
15469 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15470 unsigned long insn
)
15472 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15473 write_compressed_insn (buf
, insn
, 4);
15475 write_insn (buf
, insn
);
15478 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15479 to a symbol in another ISA mode, which cannot be converted to JALX. */
15482 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15484 unsigned long opcode
;
15488 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15491 other
= S_GET_OTHER (fixP
->fx_addsy
);
15492 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15493 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15494 switch (fixP
->fx_r_type
)
15496 case BFD_RELOC_MIPS_JMP
:
15497 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15498 case BFD_RELOC_MICROMIPS_JMP
:
15499 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15505 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15506 jump to a symbol in the same ISA mode. */
15509 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15511 unsigned long opcode
;
15515 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15518 other
= S_GET_OTHER (fixP
->fx_addsy
);
15519 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15520 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15521 switch (fixP
->fx_r_type
)
15523 case BFD_RELOC_MIPS_JMP
:
15524 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15525 case BFD_RELOC_MIPS16_JMP
:
15526 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15527 case BFD_RELOC_MICROMIPS_JMP
:
15528 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15534 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15535 to a symbol whose value plus addend is not aligned according to the
15536 ultimate (after linker relaxation) jump instruction's immediate field
15537 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15538 regular MIPS code, to (1 << 2). */
15541 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15543 bfd_boolean micro_to_mips_p
;
15547 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15550 other
= S_GET_OTHER (fixP
->fx_addsy
);
15551 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15552 val
+= fixP
->fx_offset
;
15553 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15554 && !ELF_ST_IS_MICROMIPS (other
));
15555 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15556 != ELF_ST_IS_COMPRESSED (other
));
15559 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15560 to a symbol whose annotation indicates another ISA mode. For absolute
15561 symbols check the ISA bit instead.
15563 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15564 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15565 MIPS symbols and associated with BAL instructions as these instructions
15566 may be converted to JALX by the linker. */
15569 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15571 bfd_boolean absolute_p
;
15572 unsigned long opcode
;
15578 if (mips_ignore_branch_isa
)
15581 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15584 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15585 absolute_p
= bfd_is_abs_section (symsec
);
15587 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15588 other
= S_GET_OTHER (fixP
->fx_addsy
);
15590 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15591 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15592 switch (fixP
->fx_r_type
)
15594 case BFD_RELOC_16_PCREL_S2
:
15595 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15596 && opcode
!= 0x0411);
15597 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15598 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15599 && opcode
!= 0x4060);
15600 case BFD_RELOC_MIPS_21_PCREL_S2
:
15601 case BFD_RELOC_MIPS_26_PCREL_S2
:
15602 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15603 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15604 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15605 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15606 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15607 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15613 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15614 branch instruction pointed to by FIXP is not aligned according to the
15615 branch instruction's immediate field requirement. We need the addend
15616 to preserve the ISA bit and also the sum must not have bit 2 set. We
15617 must explicitly OR in the ISA bit from symbol annotation as the bit
15618 won't be set in the symbol's value then. */
15621 fix_bad_misaligned_branch_p (fixS
*fixP
)
15623 bfd_boolean absolute_p
;
15630 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15633 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15634 absolute_p
= bfd_is_abs_section (symsec
);
15636 val
= S_GET_VALUE (fixP
->fx_addsy
);
15637 other
= S_GET_OTHER (fixP
->fx_addsy
);
15638 off
= fixP
->fx_offset
;
15640 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15641 val
|= ELF_ST_IS_COMPRESSED (other
);
15643 return (val
& 0x3) != isa_bit
;
15646 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15647 and its calculated value VAL. */
15650 fix_validate_branch (fixS
*fixP
, valueT val
)
15652 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15654 _("branch to misaligned address (0x%lx)"),
15655 (long) (val
+ md_pcrel_from (fixP
)));
15656 else if (fix_bad_cross_mode_branch_p (fixP
))
15657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15658 _("branch to a symbol in another ISA mode"));
15659 else if (fix_bad_misaligned_branch_p (fixP
))
15660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15661 _("branch to misaligned address (0x%lx)"),
15662 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15663 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15665 _("cannot encode misaligned addend "
15666 "in the relocatable field (0x%lx)"),
15667 (long) fixP
->fx_offset
);
15670 /* Apply a fixup to the object file. */
15673 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15676 unsigned long insn
;
15677 reloc_howto_type
*howto
;
15679 if (fixP
->fx_pcrel
)
15680 switch (fixP
->fx_r_type
)
15682 case BFD_RELOC_16_PCREL_S2
:
15683 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15684 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15685 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15686 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15687 case BFD_RELOC_32_PCREL
:
15688 case BFD_RELOC_MIPS_21_PCREL_S2
:
15689 case BFD_RELOC_MIPS_26_PCREL_S2
:
15690 case BFD_RELOC_MIPS_18_PCREL_S3
:
15691 case BFD_RELOC_MIPS_19_PCREL_S2
:
15692 case BFD_RELOC_HI16_S_PCREL
:
15693 case BFD_RELOC_LO16_PCREL
:
15697 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15702 _("PC-relative reference to a different section"));
15706 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15707 that have no MIPS ELF equivalent. */
15708 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15710 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15715 gas_assert (fixP
->fx_size
== 2
15716 || fixP
->fx_size
== 4
15717 || fixP
->fx_r_type
== BFD_RELOC_8
15718 || fixP
->fx_r_type
== BFD_RELOC_16
15719 || fixP
->fx_r_type
== BFD_RELOC_64
15720 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15721 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15722 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15723 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15724 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15725 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15726 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15728 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15730 /* Don't treat parts of a composite relocation as done. There are two
15733 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15734 should nevertheless be emitted if the first part is.
15736 (2) In normal usage, composite relocations are never assembly-time
15737 constants. The easiest way of dealing with the pathological
15738 exceptions is to generate a relocation against STN_UNDEF and
15739 leave everything up to the linker. */
15740 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15743 switch (fixP
->fx_r_type
)
15745 case BFD_RELOC_MIPS_TLS_GD
:
15746 case BFD_RELOC_MIPS_TLS_LDM
:
15747 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15748 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15749 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15750 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15751 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15752 case BFD_RELOC_MIPS_TLS_TPREL32
:
15753 case BFD_RELOC_MIPS_TLS_TPREL64
:
15754 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15755 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15756 case BFD_RELOC_MICROMIPS_TLS_GD
:
15757 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15758 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15759 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15760 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15761 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15762 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15763 case BFD_RELOC_MIPS16_TLS_GD
:
15764 case BFD_RELOC_MIPS16_TLS_LDM
:
15765 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15766 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15767 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15768 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15769 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15770 if (fixP
->fx_addsy
)
15771 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15774 _("TLS relocation against a constant"));
15777 case BFD_RELOC_MIPS_JMP
:
15778 case BFD_RELOC_MIPS16_JMP
:
15779 case BFD_RELOC_MICROMIPS_JMP
:
15783 gas_assert (!fixP
->fx_done
);
15785 /* Shift is 2, unusually, for microMIPS JALX. */
15786 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15787 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15792 if (fix_bad_cross_mode_jump_p (fixP
))
15793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15794 _("jump to a symbol in another ISA mode"));
15795 else if (fix_bad_same_mode_jalx_p (fixP
))
15796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15797 _("JALX to a symbol in the same ISA mode"));
15798 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15800 _("jump to misaligned address (0x%lx)"),
15801 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15802 + fixP
->fx_offset
));
15803 else if (HAVE_IN_PLACE_ADDENDS
15804 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15806 _("cannot encode misaligned addend "
15807 "in the relocatable field (0x%lx)"),
15808 (long) fixP
->fx_offset
);
15810 /* Fall through. */
15812 case BFD_RELOC_MIPS_SHIFT5
:
15813 case BFD_RELOC_MIPS_SHIFT6
:
15814 case BFD_RELOC_MIPS_GOT_DISP
:
15815 case BFD_RELOC_MIPS_GOT_PAGE
:
15816 case BFD_RELOC_MIPS_GOT_OFST
:
15817 case BFD_RELOC_MIPS_SUB
:
15818 case BFD_RELOC_MIPS_INSERT_A
:
15819 case BFD_RELOC_MIPS_INSERT_B
:
15820 case BFD_RELOC_MIPS_DELETE
:
15821 case BFD_RELOC_MIPS_HIGHEST
:
15822 case BFD_RELOC_MIPS_HIGHER
:
15823 case BFD_RELOC_MIPS_SCN_DISP
:
15824 case BFD_RELOC_MIPS_REL16
:
15825 case BFD_RELOC_MIPS_RELGOT
:
15826 case BFD_RELOC_MIPS_JALR
:
15827 case BFD_RELOC_HI16
:
15828 case BFD_RELOC_HI16_S
:
15829 case BFD_RELOC_LO16
:
15830 case BFD_RELOC_GPREL16
:
15831 case BFD_RELOC_MIPS_LITERAL
:
15832 case BFD_RELOC_MIPS_CALL16
:
15833 case BFD_RELOC_MIPS_GOT16
:
15834 case BFD_RELOC_GPREL32
:
15835 case BFD_RELOC_MIPS_GOT_HI16
:
15836 case BFD_RELOC_MIPS_GOT_LO16
:
15837 case BFD_RELOC_MIPS_CALL_HI16
:
15838 case BFD_RELOC_MIPS_CALL_LO16
:
15839 case BFD_RELOC_HI16_S_PCREL
:
15840 case BFD_RELOC_LO16_PCREL
:
15841 case BFD_RELOC_MIPS16_GPREL
:
15842 case BFD_RELOC_MIPS16_GOT16
:
15843 case BFD_RELOC_MIPS16_CALL16
:
15844 case BFD_RELOC_MIPS16_HI16
:
15845 case BFD_RELOC_MIPS16_HI16_S
:
15846 case BFD_RELOC_MIPS16_LO16
:
15847 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15848 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15849 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15850 case BFD_RELOC_MICROMIPS_SUB
:
15851 case BFD_RELOC_MICROMIPS_HIGHEST
:
15852 case BFD_RELOC_MICROMIPS_HIGHER
:
15853 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15854 case BFD_RELOC_MICROMIPS_JALR
:
15855 case BFD_RELOC_MICROMIPS_HI16
:
15856 case BFD_RELOC_MICROMIPS_HI16_S
:
15857 case BFD_RELOC_MICROMIPS_LO16
:
15858 case BFD_RELOC_MICROMIPS_GPREL16
:
15859 case BFD_RELOC_MICROMIPS_LITERAL
:
15860 case BFD_RELOC_MICROMIPS_CALL16
:
15861 case BFD_RELOC_MICROMIPS_GOT16
:
15862 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15863 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15864 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15865 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15866 case BFD_RELOC_MIPS_EH
:
15871 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15873 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15874 if (mips16_reloc_p (fixP
->fx_r_type
))
15875 insn
|= mips16_immed_extend (value
, 16);
15877 insn
|= (value
& 0xffff);
15878 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15882 _("unsupported constant in relocation"));
15887 /* This is handled like BFD_RELOC_32, but we output a sign
15888 extended value if we are only 32 bits. */
15891 if (8 <= sizeof (valueT
))
15892 md_number_to_chars (buf
, *valP
, 8);
15897 if ((*valP
& 0x80000000) != 0)
15901 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15902 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15907 case BFD_RELOC_RVA
:
15909 case BFD_RELOC_32_PCREL
:
15912 /* If we are deleting this reloc entry, we must fill in the
15913 value now. This can happen if we have a .word which is not
15914 resolved when it appears but is later defined. */
15916 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15919 case BFD_RELOC_MIPS_21_PCREL_S2
:
15920 fix_validate_branch (fixP
, *valP
);
15921 if (!fixP
->fx_done
)
15924 if (*valP
+ 0x400000 <= 0x7fffff)
15926 insn
= read_insn (buf
);
15927 insn
|= (*valP
>> 2) & 0x1fffff;
15928 write_insn (buf
, insn
);
15931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15932 _("branch out of range"));
15935 case BFD_RELOC_MIPS_26_PCREL_S2
:
15936 fix_validate_branch (fixP
, *valP
);
15937 if (!fixP
->fx_done
)
15940 if (*valP
+ 0x8000000 <= 0xfffffff)
15942 insn
= read_insn (buf
);
15943 insn
|= (*valP
>> 2) & 0x3ffffff;
15944 write_insn (buf
, insn
);
15947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15948 _("branch out of range"));
15951 case BFD_RELOC_MIPS_18_PCREL_S3
:
15952 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15954 _("PC-relative access using misaligned symbol (%lx)"),
15955 (long) S_GET_VALUE (fixP
->fx_addsy
));
15956 if ((fixP
->fx_offset
& 0x7) != 0)
15957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15958 _("PC-relative access using misaligned offset (%lx)"),
15959 (long) fixP
->fx_offset
);
15960 if (!fixP
->fx_done
)
15963 if (*valP
+ 0x100000 <= 0x1fffff)
15965 insn
= read_insn (buf
);
15966 insn
|= (*valP
>> 3) & 0x3ffff;
15967 write_insn (buf
, insn
);
15970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15971 _("PC-relative access out of range"));
15974 case BFD_RELOC_MIPS_19_PCREL_S2
:
15975 if ((*valP
& 0x3) != 0)
15976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15977 _("PC-relative access to misaligned address (%lx)"),
15979 if (!fixP
->fx_done
)
15982 if (*valP
+ 0x100000 <= 0x1fffff)
15984 insn
= read_insn (buf
);
15985 insn
|= (*valP
>> 2) & 0x7ffff;
15986 write_insn (buf
, insn
);
15989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15990 _("PC-relative access out of range"));
15993 case BFD_RELOC_16_PCREL_S2
:
15994 fix_validate_branch (fixP
, *valP
);
15996 /* We need to save the bits in the instruction since fixup_segment()
15997 might be deleting the relocation entry (i.e., a branch within
15998 the current segment). */
15999 if (! fixP
->fx_done
)
16002 /* Update old instruction data. */
16003 insn
= read_insn (buf
);
16005 if (*valP
+ 0x20000 <= 0x3ffff)
16007 insn
|= (*valP
>> 2) & 0xffff;
16008 write_insn (buf
, insn
);
16010 else if (fixP
->fx_tcbit2
16012 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16013 && (fixP
->fx_frag
->fr_address
16014 < text_section
->vma
+ bfd_get_section_size (text_section
))
16015 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16016 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16017 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16019 /* The branch offset is too large. If this is an
16020 unconditional branch, and we are not generating PIC code,
16021 we can convert it to an absolute jump instruction. */
16022 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16023 insn
= 0x0c000000; /* jal */
16025 insn
= 0x08000000; /* j */
16026 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16028 fixP
->fx_addsy
= section_symbol (text_section
);
16029 *valP
+= md_pcrel_from (fixP
);
16030 write_insn (buf
, insn
);
16034 /* If we got here, we have branch-relaxation disabled,
16035 and there's nothing we can do to fix this instruction
16036 without turning it into a longer sequence. */
16037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16038 _("branch out of range"));
16042 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16043 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16044 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16045 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16046 gas_assert (!fixP
->fx_done
);
16047 if (fix_bad_cross_mode_branch_p (fixP
))
16048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16049 _("branch to a symbol in another ISA mode"));
16050 else if (fixP
->fx_addsy
16051 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16052 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16053 && (fixP
->fx_offset
& 0x1) != 0)
16054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16055 _("branch to misaligned address (0x%lx)"),
16056 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
16057 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16059 _("cannot encode misaligned addend "
16060 "in the relocatable field (0x%lx)"),
16061 (long) fixP
->fx_offset
);
16064 case BFD_RELOC_VTABLE_INHERIT
:
16067 && !S_IS_DEFINED (fixP
->fx_addsy
)
16068 && !S_IS_WEAK (fixP
->fx_addsy
))
16069 S_SET_WEAK (fixP
->fx_addsy
);
16072 case BFD_RELOC_NONE
:
16073 case BFD_RELOC_VTABLE_ENTRY
:
16081 /* Remember value for tc_gen_reloc. */
16082 fixP
->fx_addnumber
= *valP
;
16092 c
= get_symbol_name (&name
);
16093 p
= (symbolS
*) symbol_find_or_make (name
);
16094 (void) restore_line_pointer (c
);
16098 /* Align the current frag to a given power of two. If a particular
16099 fill byte should be used, FILL points to an integer that contains
16100 that byte, otherwise FILL is null.
16102 This function used to have the comment:
16104 The MIPS assembler also automatically adjusts any preceding label.
16106 The implementation therefore applied the adjustment to a maximum of
16107 one label. However, other label adjustments are applied to batches
16108 of labels, and adjusting just one caused problems when new labels
16109 were added for the sake of debugging or unwind information.
16110 We therefore adjust all preceding labels (given as LABELS) instead. */
16113 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16115 mips_emit_delays ();
16116 mips_record_compressed_mode ();
16117 if (fill
== NULL
&& subseg_text_p (now_seg
))
16118 frag_align_code (to
, 0);
16120 frag_align (to
, fill
? *fill
: 0, 0);
16121 record_alignment (now_seg
, to
);
16122 mips_move_labels (labels
, FALSE
);
16125 /* Align to a given power of two. .align 0 turns off the automatic
16126 alignment used by the data creating pseudo-ops. */
16129 s_align (int x ATTRIBUTE_UNUSED
)
16131 int temp
, fill_value
, *fill_ptr
;
16132 long max_alignment
= 28;
16134 /* o Note that the assembler pulls down any immediately preceding label
16135 to the aligned address.
16136 o It's not documented but auto alignment is reinstated by
16137 a .align pseudo instruction.
16138 o Note also that after auto alignment is turned off the mips assembler
16139 issues an error on attempt to assemble an improperly aligned data item.
16142 temp
= get_absolute_expression ();
16143 if (temp
> max_alignment
)
16144 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16147 as_warn (_("alignment negative, 0 assumed"));
16150 if (*input_line_pointer
== ',')
16152 ++input_line_pointer
;
16153 fill_value
= get_absolute_expression ();
16154 fill_ptr
= &fill_value
;
16160 segment_info_type
*si
= seg_info (now_seg
);
16161 struct insn_label_list
*l
= si
->label_list
;
16162 /* Auto alignment should be switched on by next section change. */
16164 mips_align (temp
, fill_ptr
, l
);
16171 demand_empty_rest_of_line ();
16175 s_change_sec (int sec
)
16179 /* The ELF backend needs to know that we are changing sections, so
16180 that .previous works correctly. We could do something like check
16181 for an obj_section_change_hook macro, but that might be confusing
16182 as it would not be appropriate to use it in the section changing
16183 functions in read.c, since obj-elf.c intercepts those. FIXME:
16184 This should be cleaner, somehow. */
16185 obj_elf_section_change_hook ();
16187 mips_emit_delays ();
16198 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16199 demand_empty_rest_of_line ();
16203 seg
= subseg_new (RDATA_SECTION_NAME
,
16204 (subsegT
) get_absolute_expression ());
16205 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16206 | SEC_READONLY
| SEC_RELOC
16208 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16209 record_alignment (seg
, 4);
16210 demand_empty_rest_of_line ();
16214 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16215 bfd_set_section_flags (stdoutput
, seg
,
16216 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16217 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16218 record_alignment (seg
, 4);
16219 demand_empty_rest_of_line ();
16223 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16224 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16225 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16226 record_alignment (seg
, 4);
16227 demand_empty_rest_of_line ();
16235 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16238 char *section_name
;
16243 int section_entry_size
;
16244 int section_alignment
;
16246 saved_ilp
= input_line_pointer
;
16247 endc
= get_symbol_name (§ion_name
);
16248 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16250 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16252 /* Do we have .section Name<,"flags">? */
16253 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16255 /* Just after name is now '\0'. */
16256 (void) restore_line_pointer (endc
);
16257 input_line_pointer
= saved_ilp
;
16258 obj_elf_section (ignore
);
16262 section_name
= xstrdup (section_name
);
16263 c
= restore_line_pointer (endc
);
16265 input_line_pointer
++;
16267 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16269 section_type
= get_absolute_expression ();
16273 if (*input_line_pointer
++ == ',')
16274 section_flag
= get_absolute_expression ();
16278 if (*input_line_pointer
++ == ',')
16279 section_entry_size
= get_absolute_expression ();
16281 section_entry_size
= 0;
16283 if (*input_line_pointer
++ == ',')
16284 section_alignment
= get_absolute_expression ();
16286 section_alignment
= 0;
16288 /* FIXME: really ignore? */
16289 (void) section_alignment
;
16291 /* When using the generic form of .section (as implemented by obj-elf.c),
16292 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16293 traditionally had to fall back on the more common @progbits instead.
16295 There's nothing really harmful in this, since bfd will correct
16296 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16297 means that, for backwards compatibility, the special_section entries
16298 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16300 Even so, we shouldn't force users of the MIPS .section syntax to
16301 incorrectly label the sections as SHT_PROGBITS. The best compromise
16302 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16303 generic type-checking code. */
16304 if (section_type
== SHT_MIPS_DWARF
)
16305 section_type
= SHT_PROGBITS
;
16307 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16308 section_entry_size
, 0, 0, 0);
16310 if (now_seg
->name
!= section_name
)
16311 free (section_name
);
16315 mips_enable_auto_align (void)
16321 s_cons (int log_size
)
16323 segment_info_type
*si
= seg_info (now_seg
);
16324 struct insn_label_list
*l
= si
->label_list
;
16326 mips_emit_delays ();
16327 if (log_size
> 0 && auto_align
)
16328 mips_align (log_size
, 0, l
);
16329 cons (1 << log_size
);
16330 mips_clear_insn_labels ();
16334 s_float_cons (int type
)
16336 segment_info_type
*si
= seg_info (now_seg
);
16337 struct insn_label_list
*l
= si
->label_list
;
16339 mips_emit_delays ();
16344 mips_align (3, 0, l
);
16346 mips_align (2, 0, l
);
16350 mips_clear_insn_labels ();
16353 /* Handle .globl. We need to override it because on Irix 5 you are
16356 where foo is an undefined symbol, to mean that foo should be
16357 considered to be the address of a function. */
16360 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16369 c
= get_symbol_name (&name
);
16370 symbolP
= symbol_find_or_make (name
);
16371 S_SET_EXTERNAL (symbolP
);
16373 *input_line_pointer
= c
;
16374 SKIP_WHITESPACE_AFTER_NAME ();
16376 /* On Irix 5, every global symbol that is not explicitly labelled as
16377 being a function is apparently labelled as being an object. */
16380 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16381 && (*input_line_pointer
!= ','))
16386 c
= get_symbol_name (&secname
);
16387 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16389 as_bad (_("%s: no such section"), secname
);
16390 (void) restore_line_pointer (c
);
16392 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16393 flag
= BSF_FUNCTION
;
16396 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16398 c
= *input_line_pointer
;
16401 input_line_pointer
++;
16402 SKIP_WHITESPACE ();
16403 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16409 demand_empty_rest_of_line ();
16413 s_option (int x ATTRIBUTE_UNUSED
)
16418 c
= get_symbol_name (&opt
);
16422 /* FIXME: What does this mean? */
16424 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16428 i
= atoi (opt
+ 3);
16429 if (i
!= 0 && i
!= 2)
16430 as_bad (_(".option pic%d not supported"), i
);
16431 else if (mips_pic
== VXWORKS_PIC
)
16432 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16437 mips_pic
= SVR4_PIC
;
16438 mips_abicalls
= TRUE
;
16441 if (mips_pic
== SVR4_PIC
)
16443 if (g_switch_seen
&& g_switch_value
!= 0)
16444 as_warn (_("-G may not be used with SVR4 PIC code"));
16445 g_switch_value
= 0;
16446 bfd_set_gp_size (stdoutput
, 0);
16450 as_warn (_("unrecognized option \"%s\""), opt
);
16452 (void) restore_line_pointer (c
);
16453 demand_empty_rest_of_line ();
16456 /* This structure is used to hold a stack of .set values. */
16458 struct mips_option_stack
16460 struct mips_option_stack
*next
;
16461 struct mips_set_options options
;
16464 static struct mips_option_stack
*mips_opts_stack
;
16466 /* Return status for .set/.module option handling. */
16468 enum code_option_type
16470 /* Unrecognized option. */
16471 OPTION_TYPE_BAD
= -1,
16473 /* Ordinary option. */
16474 OPTION_TYPE_NORMAL
,
16476 /* ISA changing option. */
16480 /* Handle common .set/.module options. Return status indicating option
16483 static enum code_option_type
16484 parse_code_option (char * name
)
16486 bfd_boolean isa_set
= FALSE
;
16487 const struct mips_ase
*ase
;
16489 if (strncmp (name
, "at=", 3) == 0)
16491 char *s
= name
+ 3;
16493 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16494 as_bad (_("unrecognized register name `%s'"), s
);
16496 else if (strcmp (name
, "at") == 0)
16497 mips_opts
.at
= ATREG
;
16498 else if (strcmp (name
, "noat") == 0)
16499 mips_opts
.at
= ZERO
;
16500 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16501 mips_opts
.nomove
= 0;
16502 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16503 mips_opts
.nomove
= 1;
16504 else if (strcmp (name
, "bopt") == 0)
16505 mips_opts
.nobopt
= 0;
16506 else if (strcmp (name
, "nobopt") == 0)
16507 mips_opts
.nobopt
= 1;
16508 else if (strcmp (name
, "gp=32") == 0)
16510 else if (strcmp (name
, "gp=64") == 0)
16512 else if (strcmp (name
, "fp=32") == 0)
16514 else if (strcmp (name
, "fp=xx") == 0)
16516 else if (strcmp (name
, "fp=64") == 0)
16518 else if (strcmp (name
, "softfloat") == 0)
16519 mips_opts
.soft_float
= 1;
16520 else if (strcmp (name
, "hardfloat") == 0)
16521 mips_opts
.soft_float
= 0;
16522 else if (strcmp (name
, "singlefloat") == 0)
16523 mips_opts
.single_float
= 1;
16524 else if (strcmp (name
, "doublefloat") == 0)
16525 mips_opts
.single_float
= 0;
16526 else if (strcmp (name
, "nooddspreg") == 0)
16527 mips_opts
.oddspreg
= 0;
16528 else if (strcmp (name
, "oddspreg") == 0)
16529 mips_opts
.oddspreg
= 1;
16530 else if (strcmp (name
, "mips16") == 0
16531 || strcmp (name
, "MIPS-16") == 0)
16532 mips_opts
.mips16
= 1;
16533 else if (strcmp (name
, "nomips16") == 0
16534 || strcmp (name
, "noMIPS-16") == 0)
16535 mips_opts
.mips16
= 0;
16536 else if (strcmp (name
, "micromips") == 0)
16537 mips_opts
.micromips
= 1;
16538 else if (strcmp (name
, "nomicromips") == 0)
16539 mips_opts
.micromips
= 0;
16540 else if (name
[0] == 'n'
16542 && (ase
= mips_lookup_ase (name
+ 2)))
16543 mips_set_ase (ase
, &mips_opts
, FALSE
);
16544 else if ((ase
= mips_lookup_ase (name
)))
16545 mips_set_ase (ase
, &mips_opts
, TRUE
);
16546 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16548 /* Permit the user to change the ISA and architecture on the fly.
16549 Needless to say, misuse can cause serious problems. */
16550 if (strncmp (name
, "arch=", 5) == 0)
16552 const struct mips_cpu_info
*p
;
16554 p
= mips_parse_cpu ("internal use", name
+ 5);
16556 as_bad (_("unknown architecture %s"), name
+ 5);
16559 mips_opts
.arch
= p
->cpu
;
16560 mips_opts
.isa
= p
->isa
;
16564 else if (strncmp (name
, "mips", 4) == 0)
16566 const struct mips_cpu_info
*p
;
16568 p
= mips_parse_cpu ("internal use", name
);
16570 as_bad (_("unknown ISA level %s"), name
+ 4);
16573 mips_opts
.arch
= p
->cpu
;
16574 mips_opts
.isa
= p
->isa
;
16579 as_bad (_("unknown ISA or architecture %s"), name
);
16581 else if (strcmp (name
, "autoextend") == 0)
16582 mips_opts
.noautoextend
= 0;
16583 else if (strcmp (name
, "noautoextend") == 0)
16584 mips_opts
.noautoextend
= 1;
16585 else if (strcmp (name
, "insn32") == 0)
16586 mips_opts
.insn32
= TRUE
;
16587 else if (strcmp (name
, "noinsn32") == 0)
16588 mips_opts
.insn32
= FALSE
;
16589 else if (strcmp (name
, "sym32") == 0)
16590 mips_opts
.sym32
= TRUE
;
16591 else if (strcmp (name
, "nosym32") == 0)
16592 mips_opts
.sym32
= FALSE
;
16594 return OPTION_TYPE_BAD
;
16596 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16599 /* Handle the .set pseudo-op. */
16602 s_mipsset (int x ATTRIBUTE_UNUSED
)
16604 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16605 char *name
= input_line_pointer
, ch
;
16607 file_mips_check_options ();
16609 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16610 ++input_line_pointer
;
16611 ch
= *input_line_pointer
;
16612 *input_line_pointer
= '\0';
16614 if (strchr (name
, ','))
16616 /* Generic ".set" directive; use the generic handler. */
16617 *input_line_pointer
= ch
;
16618 input_line_pointer
= name
;
16623 if (strcmp (name
, "reorder") == 0)
16625 if (mips_opts
.noreorder
)
16628 else if (strcmp (name
, "noreorder") == 0)
16630 if (!mips_opts
.noreorder
)
16631 start_noreorder ();
16633 else if (strcmp (name
, "macro") == 0)
16634 mips_opts
.warn_about_macros
= 0;
16635 else if (strcmp (name
, "nomacro") == 0)
16637 if (mips_opts
.noreorder
== 0)
16638 as_bad (_("`noreorder' must be set before `nomacro'"));
16639 mips_opts
.warn_about_macros
= 1;
16641 else if (strcmp (name
, "gp=default") == 0)
16642 mips_opts
.gp
= file_mips_opts
.gp
;
16643 else if (strcmp (name
, "fp=default") == 0)
16644 mips_opts
.fp
= file_mips_opts
.fp
;
16645 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16647 mips_opts
.isa
= file_mips_opts
.isa
;
16648 mips_opts
.arch
= file_mips_opts
.arch
;
16649 mips_opts
.gp
= file_mips_opts
.gp
;
16650 mips_opts
.fp
= file_mips_opts
.fp
;
16652 else if (strcmp (name
, "push") == 0)
16654 struct mips_option_stack
*s
;
16656 s
= XNEW (struct mips_option_stack
);
16657 s
->next
= mips_opts_stack
;
16658 s
->options
= mips_opts
;
16659 mips_opts_stack
= s
;
16661 else if (strcmp (name
, "pop") == 0)
16663 struct mips_option_stack
*s
;
16665 s
= mips_opts_stack
;
16667 as_bad (_(".set pop with no .set push"));
16670 /* If we're changing the reorder mode we need to handle
16671 delay slots correctly. */
16672 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16673 start_noreorder ();
16674 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16677 mips_opts
= s
->options
;
16678 mips_opts_stack
= s
->next
;
16684 type
= parse_code_option (name
);
16685 if (type
== OPTION_TYPE_BAD
)
16686 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16689 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16690 registers based on what is supported by the arch/cpu. */
16691 if (type
== OPTION_TYPE_ISA
)
16693 switch (mips_opts
.isa
)
16698 /* MIPS I cannot support FPXX. */
16700 /* fall-through. */
16707 if (mips_opts
.fp
!= 0)
16723 if (mips_opts
.fp
!= 0)
16725 if (mips_opts
.arch
== CPU_R5900
)
16732 as_bad (_("unknown ISA level %s"), name
+ 4);
16737 mips_check_options (&mips_opts
, FALSE
);
16739 mips_check_isa_supports_ases ();
16740 *input_line_pointer
= ch
;
16741 demand_empty_rest_of_line ();
16744 /* Handle the .module pseudo-op. */
16747 s_module (int ignore ATTRIBUTE_UNUSED
)
16749 char *name
= input_line_pointer
, ch
;
16751 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16752 ++input_line_pointer
;
16753 ch
= *input_line_pointer
;
16754 *input_line_pointer
= '\0';
16756 if (!file_mips_opts_checked
)
16758 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16759 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16761 /* Update module level settings from mips_opts. */
16762 file_mips_opts
= mips_opts
;
16765 as_bad (_(".module is not permitted after generating code"));
16767 *input_line_pointer
= ch
;
16768 demand_empty_rest_of_line ();
16771 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16772 .option pic2. It means to generate SVR4 PIC calls. */
16775 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16777 mips_pic
= SVR4_PIC
;
16778 mips_abicalls
= TRUE
;
16780 if (g_switch_seen
&& g_switch_value
!= 0)
16781 as_warn (_("-G may not be used with SVR4 PIC code"));
16782 g_switch_value
= 0;
16784 bfd_set_gp_size (stdoutput
, 0);
16785 demand_empty_rest_of_line ();
16788 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16789 PIC code. It sets the $gp register for the function based on the
16790 function address, which is in the register named in the argument.
16791 This uses a relocation against _gp_disp, which is handled specially
16792 by the linker. The result is:
16793 lui $gp,%hi(_gp_disp)
16794 addiu $gp,$gp,%lo(_gp_disp)
16795 addu $gp,$gp,.cpload argument
16796 The .cpload argument is normally $25 == $t9.
16798 The -mno-shared option changes this to:
16799 lui $gp,%hi(__gnu_local_gp)
16800 addiu $gp,$gp,%lo(__gnu_local_gp)
16801 and the argument is ignored. This saves an instruction, but the
16802 resulting code is not position independent; it uses an absolute
16803 address for __gnu_local_gp. Thus code assembled with -mno-shared
16804 can go into an ordinary executable, but not into a shared library. */
16807 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16813 file_mips_check_options ();
16815 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16816 .cpload is ignored. */
16817 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16823 if (mips_opts
.mips16
)
16825 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16826 ignore_rest_of_line ();
16830 /* .cpload should be in a .set noreorder section. */
16831 if (mips_opts
.noreorder
== 0)
16832 as_warn (_(".cpload not in noreorder section"));
16834 reg
= tc_get_register (0);
16836 /* If we need to produce a 64-bit address, we are better off using
16837 the default instruction sequence. */
16838 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16840 ex
.X_op
= O_symbol
;
16841 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16843 ex
.X_op_symbol
= NULL
;
16844 ex
.X_add_number
= 0;
16846 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16847 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16849 mips_mark_labels ();
16850 mips_assembling_insn
= TRUE
;
16853 macro_build_lui (&ex
, mips_gp_register
);
16854 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16855 mips_gp_register
, BFD_RELOC_LO16
);
16857 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16858 mips_gp_register
, reg
);
16861 mips_assembling_insn
= FALSE
;
16862 demand_empty_rest_of_line ();
16865 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16866 .cpsetup $reg1, offset|$reg2, label
16868 If offset is given, this results in:
16869 sd $gp, offset($sp)
16870 lui $gp, %hi(%neg(%gp_rel(label)))
16871 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16872 daddu $gp, $gp, $reg1
16874 If $reg2 is given, this results in:
16876 lui $gp, %hi(%neg(%gp_rel(label)))
16877 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16878 daddu $gp, $gp, $reg1
16879 $reg1 is normally $25 == $t9.
16881 The -mno-shared option replaces the last three instructions with
16883 addiu $gp,$gp,%lo(_gp) */
16886 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16888 expressionS ex_off
;
16889 expressionS ex_sym
;
16892 file_mips_check_options ();
16894 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16895 We also need NewABI support. */
16896 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16902 if (mips_opts
.mips16
)
16904 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16905 ignore_rest_of_line ();
16909 reg1
= tc_get_register (0);
16910 SKIP_WHITESPACE ();
16911 if (*input_line_pointer
!= ',')
16913 as_bad (_("missing argument separator ',' for .cpsetup"));
16917 ++input_line_pointer
;
16918 SKIP_WHITESPACE ();
16919 if (*input_line_pointer
== '$')
16921 mips_cpreturn_register
= tc_get_register (0);
16922 mips_cpreturn_offset
= -1;
16926 mips_cpreturn_offset
= get_absolute_expression ();
16927 mips_cpreturn_register
= -1;
16929 SKIP_WHITESPACE ();
16930 if (*input_line_pointer
!= ',')
16932 as_bad (_("missing argument separator ',' for .cpsetup"));
16936 ++input_line_pointer
;
16937 SKIP_WHITESPACE ();
16938 expression (&ex_sym
);
16940 mips_mark_labels ();
16941 mips_assembling_insn
= TRUE
;
16944 if (mips_cpreturn_register
== -1)
16946 ex_off
.X_op
= O_constant
;
16947 ex_off
.X_add_symbol
= NULL
;
16948 ex_off
.X_op_symbol
= NULL
;
16949 ex_off
.X_add_number
= mips_cpreturn_offset
;
16951 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16952 BFD_RELOC_LO16
, SP
);
16955 move_register (mips_cpreturn_register
, mips_gp_register
);
16957 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16959 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16960 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16963 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16964 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16965 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16967 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16968 mips_gp_register
, reg1
);
16974 ex
.X_op
= O_symbol
;
16975 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16976 ex
.X_op_symbol
= NULL
;
16977 ex
.X_add_number
= 0;
16979 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16980 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16982 macro_build_lui (&ex
, mips_gp_register
);
16983 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16984 mips_gp_register
, BFD_RELOC_LO16
);
16989 mips_assembling_insn
= FALSE
;
16990 demand_empty_rest_of_line ();
16994 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16996 file_mips_check_options ();
16998 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16999 .cplocal is ignored. */
17000 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17006 if (mips_opts
.mips16
)
17008 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17009 ignore_rest_of_line ();
17013 mips_gp_register
= tc_get_register (0);
17014 demand_empty_rest_of_line ();
17017 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17018 offset from $sp. The offset is remembered, and after making a PIC
17019 call $gp is restored from that location. */
17022 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17026 file_mips_check_options ();
17028 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17029 .cprestore is ignored. */
17030 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17036 if (mips_opts
.mips16
)
17038 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17039 ignore_rest_of_line ();
17043 mips_cprestore_offset
= get_absolute_expression ();
17044 mips_cprestore_valid
= 1;
17046 ex
.X_op
= O_constant
;
17047 ex
.X_add_symbol
= NULL
;
17048 ex
.X_op_symbol
= NULL
;
17049 ex
.X_add_number
= mips_cprestore_offset
;
17051 mips_mark_labels ();
17052 mips_assembling_insn
= TRUE
;
17055 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17056 SP
, HAVE_64BIT_ADDRESSES
);
17059 mips_assembling_insn
= FALSE
;
17060 demand_empty_rest_of_line ();
17063 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17064 was given in the preceding .cpsetup, it results in:
17065 ld $gp, offset($sp)
17067 If a register $reg2 was given there, it results in:
17068 or $gp, $reg2, $0 */
17071 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17075 file_mips_check_options ();
17077 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17078 We also need NewABI support. */
17079 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17085 if (mips_opts
.mips16
)
17087 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17088 ignore_rest_of_line ();
17092 mips_mark_labels ();
17093 mips_assembling_insn
= TRUE
;
17096 if (mips_cpreturn_register
== -1)
17098 ex
.X_op
= O_constant
;
17099 ex
.X_add_symbol
= NULL
;
17100 ex
.X_op_symbol
= NULL
;
17101 ex
.X_add_number
= mips_cpreturn_offset
;
17103 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17106 move_register (mips_gp_register
, mips_cpreturn_register
);
17110 mips_assembling_insn
= FALSE
;
17111 demand_empty_rest_of_line ();
17114 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17115 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17116 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17117 debug information or MIPS16 TLS. */
17120 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17121 bfd_reloc_code_real_type rtype
)
17128 if (ex
.X_op
!= O_symbol
)
17130 as_bad (_("unsupported use of %s"), dirstr
);
17131 ignore_rest_of_line ();
17134 p
= frag_more (bytes
);
17135 md_number_to_chars (p
, 0, bytes
);
17136 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17137 demand_empty_rest_of_line ();
17138 mips_clear_insn_labels ();
17141 /* Handle .dtprelword. */
17144 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17146 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17149 /* Handle .dtpreldword. */
17152 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17154 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17157 /* Handle .tprelword. */
17160 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17162 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17165 /* Handle .tpreldword. */
17168 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17170 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17173 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17174 code. It sets the offset to use in gp_rel relocations. */
17177 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17179 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17180 We also need NewABI support. */
17181 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17187 mips_gprel_offset
= get_absolute_expression ();
17189 demand_empty_rest_of_line ();
17192 /* Handle the .gpword pseudo-op. This is used when generating PIC
17193 code. It generates a 32 bit GP relative reloc. */
17196 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17198 segment_info_type
*si
;
17199 struct insn_label_list
*l
;
17203 /* When not generating PIC code, this is treated as .word. */
17204 if (mips_pic
!= SVR4_PIC
)
17210 si
= seg_info (now_seg
);
17211 l
= si
->label_list
;
17212 mips_emit_delays ();
17214 mips_align (2, 0, l
);
17217 mips_clear_insn_labels ();
17219 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17221 as_bad (_("unsupported use of .gpword"));
17222 ignore_rest_of_line ();
17226 md_number_to_chars (p
, 0, 4);
17227 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17228 BFD_RELOC_GPREL32
);
17230 demand_empty_rest_of_line ();
17234 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17236 segment_info_type
*si
;
17237 struct insn_label_list
*l
;
17241 /* When not generating PIC code, this is treated as .dword. */
17242 if (mips_pic
!= SVR4_PIC
)
17248 si
= seg_info (now_seg
);
17249 l
= si
->label_list
;
17250 mips_emit_delays ();
17252 mips_align (3, 0, l
);
17255 mips_clear_insn_labels ();
17257 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17259 as_bad (_("unsupported use of .gpdword"));
17260 ignore_rest_of_line ();
17264 md_number_to_chars (p
, 0, 8);
17265 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17266 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17268 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17269 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17270 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17272 demand_empty_rest_of_line ();
17275 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17276 tables. It generates a R_MIPS_EH reloc. */
17279 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17284 mips_emit_delays ();
17287 mips_clear_insn_labels ();
17289 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17291 as_bad (_("unsupported use of .ehword"));
17292 ignore_rest_of_line ();
17296 md_number_to_chars (p
, 0, 4);
17297 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17298 BFD_RELOC_32_PCREL
);
17300 demand_empty_rest_of_line ();
17303 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17304 tables in SVR4 PIC code. */
17307 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17311 file_mips_check_options ();
17313 /* This is ignored when not generating SVR4 PIC code. */
17314 if (mips_pic
!= SVR4_PIC
)
17320 mips_mark_labels ();
17321 mips_assembling_insn
= TRUE
;
17323 /* Add $gp to the register named as an argument. */
17325 reg
= tc_get_register (0);
17326 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17329 mips_assembling_insn
= FALSE
;
17330 demand_empty_rest_of_line ();
17333 /* Handle the .insn pseudo-op. This marks instruction labels in
17334 mips16/micromips mode. This permits the linker to handle them specially,
17335 such as generating jalx instructions when needed. We also make
17336 them odd for the duration of the assembly, in order to generate the
17337 right sort of code. We will make them even in the adjust_symtab
17338 routine, while leaving them marked. This is convenient for the
17339 debugger and the disassembler. The linker knows to make them odd
17343 s_insn (int ignore ATTRIBUTE_UNUSED
)
17345 file_mips_check_options ();
17346 file_ase_mips16
|= mips_opts
.mips16
;
17347 file_ase_micromips
|= mips_opts
.micromips
;
17349 mips_mark_labels ();
17351 demand_empty_rest_of_line ();
17354 /* Handle the .nan pseudo-op. */
17357 s_nan (int ignore ATTRIBUTE_UNUSED
)
17359 static const char str_legacy
[] = "legacy";
17360 static const char str_2008
[] = "2008";
17363 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17365 if (i
== sizeof (str_2008
) - 1
17366 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17368 else if (i
== sizeof (str_legacy
) - 1
17369 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17371 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17374 as_bad (_("`%s' does not support legacy NaN"),
17375 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17378 as_bad (_("bad .nan directive"));
17380 input_line_pointer
+= i
;
17381 demand_empty_rest_of_line ();
17384 /* Handle a .stab[snd] directive. Ideally these directives would be
17385 implemented in a transparent way, so that removing them would not
17386 have any effect on the generated instructions. However, s_stab
17387 internally changes the section, so in practice we need to decide
17388 now whether the preceding label marks compressed code. We do not
17389 support changing the compression mode of a label after a .stab*
17390 directive, such as in:
17396 so the current mode wins. */
17399 s_mips_stab (int type
)
17401 file_mips_check_options ();
17402 mips_mark_labels ();
17406 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17409 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17416 c
= get_symbol_name (&name
);
17417 symbolP
= symbol_find_or_make (name
);
17418 S_SET_WEAK (symbolP
);
17419 *input_line_pointer
= c
;
17421 SKIP_WHITESPACE_AFTER_NAME ();
17423 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17425 if (S_IS_DEFINED (symbolP
))
17427 as_bad (_("ignoring attempt to redefine symbol %s"),
17428 S_GET_NAME (symbolP
));
17429 ignore_rest_of_line ();
17433 if (*input_line_pointer
== ',')
17435 ++input_line_pointer
;
17436 SKIP_WHITESPACE ();
17440 if (exp
.X_op
!= O_symbol
)
17442 as_bad (_("bad .weakext directive"));
17443 ignore_rest_of_line ();
17446 symbol_set_value_expression (symbolP
, &exp
);
17449 demand_empty_rest_of_line ();
17452 /* Parse a register string into a number. Called from the ECOFF code
17453 to parse .frame. The argument is non-zero if this is the frame
17454 register, so that we can record it in mips_frame_reg. */
17457 tc_get_register (int frame
)
17461 SKIP_WHITESPACE ();
17462 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17466 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17467 mips_frame_reg_valid
= 1;
17468 mips_cprestore_valid
= 0;
17474 md_section_align (asection
*seg
, valueT addr
)
17476 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17478 /* We don't need to align ELF sections to the full alignment.
17479 However, Irix 5 may prefer that we align them at least to a 16
17480 byte boundary. We don't bother to align the sections if we
17481 are targeted for an embedded system. */
17482 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17487 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17490 /* Utility routine, called from above as well. If called while the
17491 input file is still being read, it's only an approximation. (For
17492 example, a symbol may later become defined which appeared to be
17493 undefined earlier.) */
17496 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17501 if (g_switch_value
> 0)
17503 const char *symname
;
17506 /* Find out whether this symbol can be referenced off the $gp
17507 register. It can be if it is smaller than the -G size or if
17508 it is in the .sdata or .sbss section. Certain symbols can
17509 not be referenced off the $gp, although it appears as though
17511 symname
= S_GET_NAME (sym
);
17512 if (symname
!= (const char *) NULL
17513 && (strcmp (symname
, "eprol") == 0
17514 || strcmp (symname
, "etext") == 0
17515 || strcmp (symname
, "_gp") == 0
17516 || strcmp (symname
, "edata") == 0
17517 || strcmp (symname
, "_fbss") == 0
17518 || strcmp (symname
, "_fdata") == 0
17519 || strcmp (symname
, "_ftext") == 0
17520 || strcmp (symname
, "end") == 0
17521 || strcmp (symname
, "_gp_disp") == 0))
17523 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17525 #ifndef NO_ECOFF_DEBUGGING
17526 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17527 && (symbol_get_obj (sym
)->ecoff_extern_size
17528 <= g_switch_value
))
17530 /* We must defer this decision until after the whole
17531 file has been read, since there might be a .extern
17532 after the first use of this symbol. */
17533 || (before_relaxing
17534 #ifndef NO_ECOFF_DEBUGGING
17535 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17537 && S_GET_VALUE (sym
) == 0)
17538 || (S_GET_VALUE (sym
) != 0
17539 && S_GET_VALUE (sym
) <= g_switch_value
)))
17543 const char *segname
;
17545 segname
= segment_name (S_GET_SEGMENT (sym
));
17546 gas_assert (strcmp (segname
, ".lit8") != 0
17547 && strcmp (segname
, ".lit4") != 0);
17548 change
= (strcmp (segname
, ".sdata") != 0
17549 && strcmp (segname
, ".sbss") != 0
17550 && strncmp (segname
, ".sdata.", 7) != 0
17551 && strncmp (segname
, ".sbss.", 6) != 0
17552 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17553 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17558 /* We are not optimizing for the $gp register. */
17563 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17566 pic_need_relax (symbolS
*sym
)
17570 /* Handle the case of a symbol equated to another symbol. */
17571 while (symbol_equated_reloc_p (sym
))
17575 /* It's possible to get a loop here in a badly written program. */
17576 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17582 if (symbol_section_p (sym
))
17585 symsec
= S_GET_SEGMENT (sym
);
17587 /* This must duplicate the test in adjust_reloc_syms. */
17588 return (!bfd_is_und_section (symsec
)
17589 && !bfd_is_abs_section (symsec
)
17590 && !bfd_is_com_section (symsec
)
17591 /* A global or weak symbol is treated as external. */
17592 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17595 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17596 convert a section-relative value VAL to the equivalent PC-relative
17600 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17601 offsetT val
, long stretch
)
17606 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17608 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17610 /* If the relax_marker of the symbol fragment differs from the
17611 relax_marker of this fragment, we have not yet adjusted the
17612 symbol fragment fr_address. We want to add in STRETCH in
17613 order to get a better estimate of the address. This
17614 particularly matters because of the shift bits. */
17615 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17619 /* Adjust stretch for any alignment frag. Note that if have
17620 been expanding the earlier code, the symbol may be
17621 defined in what appears to be an earlier frag. FIXME:
17622 This doesn't handle the fr_subtype field, which specifies
17623 a maximum number of bytes to skip when doing an
17625 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17627 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17630 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17632 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17641 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17643 /* The base address rules are complicated. The base address of
17644 a branch is the following instruction. The base address of a
17645 PC relative load or add is the instruction itself, but if it
17646 is in a delay slot (in which case it can not be extended) use
17647 the address of the instruction whose delay slot it is in. */
17648 if (pcrel_op
->include_isa_bit
)
17652 /* If we are currently assuming that this frag should be
17653 extended, then the current address is two bytes higher. */
17654 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17657 /* Ignore the low bit in the target, since it will be set
17658 for a text label. */
17661 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17663 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17666 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17671 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17672 extended opcode. SEC is the section the frag is in. */
17675 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17677 const struct mips_int_operand
*operand
;
17682 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17684 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17687 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17688 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17689 operand
= mips16_immed_operand (type
, FALSE
);
17690 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17691 || (operand
->root
.type
== OP_PCREL
17693 : !bfd_is_abs_section (symsec
)))
17696 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17698 if (operand
->root
.type
== OP_PCREL
)
17700 const struct mips_pcrel_operand
*pcrel_op
;
17703 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17706 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17707 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17709 /* If any of the shifted bits are set, we must use an extended
17710 opcode. If the address depends on the size of this
17711 instruction, this can lead to a loop, so we arrange to always
17712 use an extended opcode. */
17713 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17715 fragp
->fr_subtype
=
17716 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17720 /* If we are about to mark a frag as extended because the value
17721 is precisely the next value above maxtiny, then there is a
17722 chance of an infinite loop as in the following code:
17727 In this case when the la is extended, foo is 0x3fc bytes
17728 away, so the la can be shrunk, but then foo is 0x400 away, so
17729 the la must be extended. To avoid this loop, we mark the
17730 frag as extended if it was small, and is about to become
17731 extended with the next value above maxtiny. */
17732 maxtiny
= mips_int_operand_max (operand
);
17733 if (val
== maxtiny
+ (1 << operand
->shift
)
17734 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17736 fragp
->fr_subtype
=
17737 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17742 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17745 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17746 macro expansion. SEC is the section the frag is in. We only
17747 support PC-relative instructions (LA, DLA, LW, LD) here, in
17748 non-PIC code using 32-bit addressing. */
17751 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17753 const struct mips_pcrel_operand
*pcrel_op
;
17754 const struct mips_int_operand
*operand
;
17759 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17761 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17763 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17766 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17772 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17773 if (bfd_is_abs_section (symsec
))
17775 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17777 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17780 operand
= mips16_immed_operand (type
, TRUE
);
17781 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17782 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17783 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17785 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17792 /* Compute the length of a branch sequence, and adjust the
17793 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17794 worst-case length is computed, with UPDATE being used to indicate
17795 whether an unconditional (-1), branch-likely (+1) or regular (0)
17796 branch is to be computed. */
17798 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17800 bfd_boolean toofar
;
17804 && S_IS_DEFINED (fragp
->fr_symbol
)
17805 && !S_IS_WEAK (fragp
->fr_symbol
)
17806 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17811 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17813 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17817 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17820 /* If the symbol is not defined or it's in a different segment,
17821 we emit the long sequence. */
17824 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17826 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17827 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17828 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17829 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17830 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17836 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17839 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17841 /* Additional space for PIC loading of target address. */
17843 if (mips_opts
.isa
== ISA_MIPS1
)
17844 /* Additional space for $at-stabilizing nop. */
17848 /* If branch is conditional. */
17849 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17856 /* Get a FRAG's branch instruction delay slot size, either from the
17857 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17858 or SHORT_INSN_SIZE otherwise. */
17861 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17863 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17866 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17868 return short_insn_size
;
17871 /* Compute the length of a branch sequence, and adjust the
17872 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17873 worst-case length is computed, with UPDATE being used to indicate
17874 whether an unconditional (-1), or regular (0) branch is to be
17878 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17880 bfd_boolean insn32
= TRUE
;
17881 bfd_boolean nods
= TRUE
;
17882 bfd_boolean pic
= TRUE
;
17883 bfd_boolean al
= TRUE
;
17884 int short_insn_size
;
17885 bfd_boolean toofar
;
17890 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17891 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17892 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17893 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17895 short_insn_size
= insn32
? 4 : 2;
17898 && S_IS_DEFINED (fragp
->fr_symbol
)
17899 && !S_IS_WEAK (fragp
->fr_symbol
)
17900 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17905 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17906 /* Ignore the low bit in the target, since it will be set
17907 for a text label. */
17908 if ((val
& 1) != 0)
17911 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17915 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17918 /* If the symbol is not defined or it's in a different segment,
17919 we emit the long sequence. */
17922 if (fragp
&& update
17923 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17924 fragp
->fr_subtype
= (toofar
17925 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17926 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17931 bfd_boolean compact_known
= fragp
!= NULL
;
17932 bfd_boolean compact
= FALSE
;
17933 bfd_boolean uncond
;
17937 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17938 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17941 uncond
= update
< 0;
17943 /* If label is out of range, we turn branch <br>:
17945 <br> label # 4 bytes
17952 # compact && (!PIC || insn32)
17955 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17956 length
+= short_insn_size
;
17958 /* If assembling PIC code, we further turn:
17964 lw/ld at, %got(label)(gp) # 4 bytes
17965 d/addiu at, %lo(label) # 4 bytes
17966 jr/c at # 2/4 bytes
17969 length
+= 4 + short_insn_size
;
17971 /* Add an extra nop if the jump has no compact form and we need
17972 to fill the delay slot. */
17973 if ((!pic
|| al
) && nods
)
17975 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17976 : short_insn_size
);
17978 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17980 <brneg> 0f # 4 bytes
17981 nop # 2/4 bytes if !compact
17984 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17988 /* Add an extra nop to fill the delay slot. */
17989 gas_assert (fragp
);
17990 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17996 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17997 bit accordingly. */
18000 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18002 bfd_boolean toofar
;
18005 && S_IS_DEFINED (fragp
->fr_symbol
)
18006 && !S_IS_WEAK (fragp
->fr_symbol
)
18007 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18013 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18014 /* Ignore the low bit in the target, since it will be set
18015 for a text label. */
18016 if ((val
& 1) != 0)
18019 /* Assume this is a 2-byte branch. */
18020 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18022 /* We try to avoid the infinite loop by not adding 2 more bytes for
18027 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18029 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18030 else if (type
== 'E')
18031 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18036 /* If the symbol is not defined or it's in a different segment,
18037 we emit a normal 32-bit branch. */
18040 if (fragp
&& update
18041 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18043 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18044 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18052 /* Estimate the size of a frag before relaxing. Unless this is the
18053 mips16, we are not really relaxing here, and the final size is
18054 encoded in the subtype information. For the mips16, we have to
18055 decide whether we are using an extended opcode or not. */
18058 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18062 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18065 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18067 return fragp
->fr_var
;
18070 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18072 /* We don't want to modify the EXTENDED bit here; it might get us
18073 into infinite loops. We change it only in mips_relax_frag(). */
18074 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18075 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18077 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18080 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18084 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18085 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18086 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18087 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18088 fragp
->fr_var
= length
;
18093 if (mips_pic
== VXWORKS_PIC
)
18094 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18096 else if (RELAX_PIC (fragp
->fr_subtype
))
18097 change
= pic_need_relax (fragp
->fr_symbol
);
18099 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18103 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18104 return -RELAX_FIRST (fragp
->fr_subtype
);
18107 return -RELAX_SECOND (fragp
->fr_subtype
);
18110 /* This is called to see whether a reloc against a defined symbol
18111 should be converted into a reloc against a section. */
18114 mips_fix_adjustable (fixS
*fixp
)
18116 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18117 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18120 if (fixp
->fx_addsy
== NULL
)
18123 /* Allow relocs used for EH tables. */
18124 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18127 /* If symbol SYM is in a mergeable section, relocations of the form
18128 SYM + 0 can usually be made section-relative. The mergeable data
18129 is then identified by the section offset rather than by the symbol.
18131 However, if we're generating REL LO16 relocations, the offset is split
18132 between the LO16 and partnering high part relocation. The linker will
18133 need to recalculate the complete offset in order to correctly identify
18136 The linker has traditionally not looked for the partnering high part
18137 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18138 placed anywhere. Rather than break backwards compatibility by changing
18139 this, it seems better not to force the issue, and instead keep the
18140 original symbol. This will work with either linker behavior. */
18141 if ((lo16_reloc_p (fixp
->fx_r_type
)
18142 || reloc_needs_lo_p (fixp
->fx_r_type
))
18143 && HAVE_IN_PLACE_ADDENDS
18144 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18147 /* There is no place to store an in-place offset for JALR relocations. */
18148 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18151 /* Likewise an in-range offset of limited PC-relative relocations may
18152 overflow the in-place relocatable field if recalculated against the
18153 start address of the symbol's containing section.
18155 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18156 section relative to allow linker relaxations to be performed later on. */
18157 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18158 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18161 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18162 to a floating-point stub. The same is true for non-R_MIPS16_26
18163 relocations against MIPS16 functions; in this case, the stub becomes
18164 the function's canonical address.
18166 Floating-point stubs are stored in unique .mips16.call.* or
18167 .mips16.fn.* sections. If a stub T for function F is in section S,
18168 the first relocation in section S must be against F; this is how the
18169 linker determines the target function. All relocations that might
18170 resolve to T must also be against F. We therefore have the following
18171 restrictions, which are given in an intentionally-redundant way:
18173 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18176 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18177 if that stub might be used.
18179 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18182 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18183 that stub might be used.
18185 There is a further restriction:
18187 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18188 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18189 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18190 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18191 against MIPS16 or microMIPS symbols because we need to keep the
18192 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18193 detection and JAL or BAL to JALX instruction conversion in the
18196 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18197 against a MIPS16 symbol. We deal with (5) by additionally leaving
18198 alone any jump and branch relocations against a microMIPS symbol.
18200 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18201 relocation against some symbol R, no relocation against R may be
18202 reduced. (Note that this deals with (2) as well as (1) because
18203 relocations against global symbols will never be reduced on ELF
18204 targets.) This approach is a little simpler than trying to detect
18205 stub sections, and gives the "all or nothing" per-symbol consistency
18206 that we have for MIPS16 symbols. */
18207 if (fixp
->fx_subsy
== NULL
18208 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18209 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18210 && (jmp_reloc_p (fixp
->fx_r_type
)
18211 || b_reloc_p (fixp
->fx_r_type
)))
18212 || *symbol_get_tc (fixp
->fx_addsy
)))
18218 /* Translate internal representation of relocation info to BFD target
18222 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18224 static arelent
*retval
[4];
18226 bfd_reloc_code_real_type code
;
18228 memset (retval
, 0, sizeof(retval
));
18229 reloc
= retval
[0] = XCNEW (arelent
);
18230 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18231 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18232 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18234 if (fixp
->fx_pcrel
)
18236 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18237 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18238 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18239 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18240 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18241 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18242 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18243 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18244 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18245 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18246 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18247 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18249 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18250 Relocations want only the symbol offset. */
18251 switch (fixp
->fx_r_type
)
18253 case BFD_RELOC_MIPS_18_PCREL_S3
:
18254 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18257 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18261 else if (HAVE_IN_PLACE_ADDENDS
18262 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18263 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18264 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18266 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18267 addend accordingly. */
18268 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18271 reloc
->addend
= fixp
->fx_addnumber
;
18273 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18274 entry to be used in the relocation's section offset. */
18275 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18277 reloc
->address
= reloc
->addend
;
18281 code
= fixp
->fx_r_type
;
18283 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18284 if (reloc
->howto
== NULL
)
18286 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18287 _("cannot represent %s relocation in this object file"
18289 bfd_get_reloc_code_name (code
));
18296 /* Relax a machine dependent frag. This returns the amount by which
18297 the current size of the frag should change. */
18300 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18302 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18304 offsetT old_var
= fragp
->fr_var
;
18306 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18308 return fragp
->fr_var
- old_var
;
18311 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18313 offsetT old_var
= fragp
->fr_var
;
18314 offsetT new_var
= 4;
18316 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18317 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18318 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18319 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18320 fragp
->fr_var
= new_var
;
18322 return new_var
- old_var
;
18325 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18328 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18330 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18332 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18333 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18335 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18337 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18343 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18345 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18347 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18348 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18349 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18351 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18353 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18361 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18363 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18365 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18366 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18367 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18371 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18372 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18379 /* Convert a machine dependent frag. */
18382 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18384 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18387 unsigned long insn
;
18390 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18391 insn
= read_insn (buf
);
18393 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18395 /* We generate a fixup instead of applying it right now
18396 because, if there are linker relaxations, we're going to
18397 need the relocations. */
18398 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18399 fragp
->fr_symbol
, fragp
->fr_offset
,
18400 TRUE
, BFD_RELOC_16_PCREL_S2
);
18401 fixp
->fx_file
= fragp
->fr_file
;
18402 fixp
->fx_line
= fragp
->fr_line
;
18404 buf
= write_insn (buf
, insn
);
18410 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18411 _("relaxed out-of-range branch into a jump"));
18413 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18416 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18418 /* Reverse the branch. */
18419 switch ((insn
>> 28) & 0xf)
18422 if ((insn
& 0xff000000) == 0x47000000
18423 || (insn
& 0xff600000) == 0x45600000)
18425 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18426 reversed by tweaking bit 23. */
18427 insn
^= 0x00800000;
18431 /* bc[0-3][tf]l? instructions can have the condition
18432 reversed by tweaking a single TF bit, and their
18433 opcodes all have 0x4???????. */
18434 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18435 insn
^= 0x00010000;
18440 /* bltz 0x04000000 bgez 0x04010000
18441 bltzal 0x04100000 bgezal 0x04110000 */
18442 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18443 insn
^= 0x00010000;
18447 /* beq 0x10000000 bne 0x14000000
18448 blez 0x18000000 bgtz 0x1c000000 */
18449 insn
^= 0x04000000;
18457 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18459 /* Clear the and-link bit. */
18460 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18462 /* bltzal 0x04100000 bgezal 0x04110000
18463 bltzall 0x04120000 bgezall 0x04130000 */
18464 insn
&= ~0x00100000;
18467 /* Branch over the branch (if the branch was likely) or the
18468 full jump (not likely case). Compute the offset from the
18469 current instruction to branch to. */
18470 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18474 /* How many bytes in instructions we've already emitted? */
18475 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18476 /* How many bytes in instructions from here to the end? */
18477 i
= fragp
->fr_var
- i
;
18479 /* Convert to instruction count. */
18481 /* Branch counts from the next instruction. */
18484 /* Branch over the jump. */
18485 buf
= write_insn (buf
, insn
);
18488 buf
= write_insn (buf
, 0);
18490 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18492 /* beql $0, $0, 2f */
18494 /* Compute the PC offset from the current instruction to
18495 the end of the variable frag. */
18496 /* How many bytes in instructions we've already emitted? */
18497 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18498 /* How many bytes in instructions from here to the end? */
18499 i
= fragp
->fr_var
- i
;
18500 /* Convert to instruction count. */
18502 /* Don't decrement i, because we want to branch over the
18506 buf
= write_insn (buf
, insn
);
18507 buf
= write_insn (buf
, 0);
18511 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18514 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18515 ? 0x0c000000 : 0x08000000);
18517 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18518 fragp
->fr_symbol
, fragp
->fr_offset
,
18519 FALSE
, BFD_RELOC_MIPS_JMP
);
18520 fixp
->fx_file
= fragp
->fr_file
;
18521 fixp
->fx_line
= fragp
->fr_line
;
18523 buf
= write_insn (buf
, insn
);
18527 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18529 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18530 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18531 insn
|= at
<< OP_SH_RT
;
18533 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18534 fragp
->fr_symbol
, fragp
->fr_offset
,
18535 FALSE
, BFD_RELOC_MIPS_GOT16
);
18536 fixp
->fx_file
= fragp
->fr_file
;
18537 fixp
->fx_line
= fragp
->fr_line
;
18539 buf
= write_insn (buf
, insn
);
18541 if (mips_opts
.isa
== ISA_MIPS1
)
18543 buf
= write_insn (buf
, 0);
18545 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18546 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18547 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18549 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18550 fragp
->fr_symbol
, fragp
->fr_offset
,
18551 FALSE
, BFD_RELOC_LO16
);
18552 fixp
->fx_file
= fragp
->fr_file
;
18553 fixp
->fx_line
= fragp
->fr_line
;
18555 buf
= write_insn (buf
, insn
);
18558 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18562 insn
|= at
<< OP_SH_RS
;
18564 buf
= write_insn (buf
, insn
);
18568 fragp
->fr_fix
+= fragp
->fr_var
;
18569 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18573 /* Relax microMIPS branches. */
18574 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18576 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18577 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18578 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18579 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18580 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18581 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18582 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18583 bfd_boolean short_ds
;
18584 unsigned long insn
;
18587 fragp
->fr_fix
+= fragp
->fr_var
;
18589 /* Handle 16-bit branches that fit or are forced to fit. */
18590 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18592 /* We generate a fixup instead of applying it right now,
18593 because if there is linker relaxation, we're going to
18594 need the relocations. */
18598 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18599 fragp
->fr_symbol
, fragp
->fr_offset
,
18600 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18603 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18604 fragp
->fr_symbol
, fragp
->fr_offset
,
18605 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18611 fixp
->fx_file
= fragp
->fr_file
;
18612 fixp
->fx_line
= fragp
->fr_line
;
18614 /* These relocations can have an addend that won't fit in
18616 fixp
->fx_no_overflow
= 1;
18621 /* Handle 32-bit branches that fit or are forced to fit. */
18622 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18623 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18625 /* We generate a fixup instead of applying it right now,
18626 because if there is linker relaxation, we're going to
18627 need the relocations. */
18628 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18629 fragp
->fr_symbol
, fragp
->fr_offset
,
18630 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18631 fixp
->fx_file
= fragp
->fr_file
;
18632 fixp
->fx_line
= fragp
->fr_line
;
18636 insn
= read_compressed_insn (buf
, 4);
18641 /* Check the short-delay-slot bit. */
18642 if (!al
|| (insn
& 0x02000000) != 0)
18643 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18645 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18648 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18653 /* Relax 16-bit branches to 32-bit branches. */
18656 insn
= read_compressed_insn (buf
, 2);
18658 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18659 insn
= 0x94000000; /* beq */
18660 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18662 unsigned long regno
;
18664 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18665 regno
= micromips_to_32_reg_d_map
[regno
];
18666 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18667 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18672 /* Nothing else to do, just write it out. */
18673 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18674 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18676 buf
= write_compressed_insn (buf
, insn
, 4);
18678 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18679 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18684 insn
= read_compressed_insn (buf
, 4);
18686 /* Relax 32-bit branches to a sequence of instructions. */
18687 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18688 _("relaxed out-of-range branch into a jump"));
18690 /* Set the short-delay-slot bit. */
18691 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18693 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18697 /* Reverse the branch. */
18698 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18699 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18700 insn
^= 0x20000000;
18701 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18702 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18703 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18704 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18705 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18706 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18707 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18708 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18709 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18710 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18711 insn
^= 0x00400000;
18712 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18713 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18714 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18715 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18716 insn
^= 0x00200000;
18717 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18719 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18721 insn
^= 0x00800000;
18727 /* Clear the and-link and short-delay-slot bits. */
18728 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18730 /* bltzal 0x40200000 bgezal 0x40600000 */
18731 /* bltzals 0x42200000 bgezals 0x42600000 */
18732 insn
&= ~0x02200000;
18735 /* Make a label at the end for use with the branch. */
18736 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18737 micromips_label_inc ();
18738 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18741 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18742 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18743 fixp
->fx_file
= fragp
->fr_file
;
18744 fixp
->fx_line
= fragp
->fr_line
;
18746 /* Branch over the jump. */
18747 buf
= write_compressed_insn (buf
, insn
, 4);
18753 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18755 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18761 unsigned long jal
= (short_ds
|| nods
18762 ? 0x74000000 : 0xf4000000); /* jal/s */
18764 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18765 insn
= al
? jal
: 0xd4000000;
18767 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18768 fragp
->fr_symbol
, fragp
->fr_offset
,
18769 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18770 fixp
->fx_file
= fragp
->fr_file
;
18771 fixp
->fx_line
= fragp
->fr_line
;
18773 buf
= write_compressed_insn (buf
, insn
, 4);
18775 if (compact
|| nods
)
18779 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18781 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18786 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18788 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18789 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18790 insn
|= at
<< MICROMIPSOP_SH_RT
;
18792 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18793 fragp
->fr_symbol
, fragp
->fr_offset
,
18794 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18795 fixp
->fx_file
= fragp
->fr_file
;
18796 fixp
->fx_line
= fragp
->fr_line
;
18798 buf
= write_compressed_insn (buf
, insn
, 4);
18800 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18801 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18802 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18804 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18805 fragp
->fr_symbol
, fragp
->fr_offset
,
18806 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18807 fixp
->fx_file
= fragp
->fr_file
;
18808 fixp
->fx_line
= fragp
->fr_line
;
18810 buf
= write_compressed_insn (buf
, insn
, 4);
18815 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18816 insn
|= at
<< MICROMIPSOP_SH_RS
;
18818 buf
= write_compressed_insn (buf
, insn
, 4);
18820 if (compact
|| nods
)
18822 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18826 /* jr/jrc/jalr/jalrs $at */
18827 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18828 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18830 insn
= al
? jalr
: jr
;
18831 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18833 buf
= write_compressed_insn (buf
, insn
, 2);
18838 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18840 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18845 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18849 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18852 const struct mips_int_operand
*operand
;
18855 unsigned int user_length
;
18856 bfd_boolean need_reloc
;
18857 unsigned long insn
;
18862 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18863 operand
= mips16_immed_operand (type
, FALSE
);
18865 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18866 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18867 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18869 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18870 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18871 || (operand
->root
.type
== OP_PCREL
&& !mac
18873 : !bfd_is_abs_section (symsec
)));
18875 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18877 const struct mips_pcrel_operand
*pcrel_op
;
18879 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18881 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18883 if (!mips_ignore_branch_isa
18884 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18885 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18886 _("branch to a symbol in another ISA mode"));
18887 else if ((fragp
->fr_offset
& 0x1) != 0)
18888 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18889 _("branch to misaligned address (0x%lx)"),
18893 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18895 /* Make sure the section winds up with the alignment we have
18897 if (operand
->shift
> 0)
18898 record_alignment (asec
, operand
->shift
);
18901 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18902 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18905 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18906 _("macro instruction expanded into multiple "
18907 "instructions in a branch delay slot"));
18909 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18910 _("extended instruction in a branch delay slot"));
18912 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18913 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18914 _("macro instruction expanded into multiple "
18917 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18919 insn
= read_compressed_insn (buf
, 2);
18921 insn
|= MIPS16_EXTEND
;
18923 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18925 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18937 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18938 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18940 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18946 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18948 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18949 fragp
->fr_symbol
, fragp
->fr_offset
,
18950 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18951 fixp
->fx_file
= fragp
->fr_file
;
18952 fixp
->fx_line
= fragp
->fr_line
;
18954 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18955 fragp
->fr_symbol
, fragp
->fr_offset
,
18956 FALSE
, BFD_RELOC_MIPS16_LO16
);
18957 fixp
->fx_file
= fragp
->fr_file
;
18958 fixp
->fx_line
= fragp
->fr_line
;
18963 switch (insn
& 0xf800)
18965 case 0x0800: /* ADDIU */
18966 reg
= (insn
>> 8) & 0x7;
18967 op
= 0xf0004800 | (reg
<< 8);
18969 case 0xb000: /* LW */
18970 reg
= (insn
>> 8) & 0x7;
18971 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18973 case 0xf800: /* I64 */
18974 reg
= (insn
>> 5) & 0x7;
18975 switch (insn
& 0x0700)
18977 case 0x0400: /* LD */
18978 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18980 case 0x0600: /* DADDIU */
18981 op
= 0xf000fd00 | (reg
<< 5);
18991 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18992 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18993 buf
= write_compressed_insn (buf
, new, 4);
18996 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18997 buf
= write_compressed_insn (buf
, new, 4);
18999 op
|= mips16_immed_extend (val
, 16);
19000 buf
= write_compressed_insn (buf
, op
, 4);
19002 fragp
->fr_fix
+= e2
? 8 : 12;
19006 unsigned int length
= ext
? 4 : 2;
19010 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19017 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19022 if (mac
|| reloc
== BFD_RELOC_NONE
)
19023 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19024 _("unsupported relocation"));
19027 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19028 fragp
->fr_symbol
, fragp
->fr_offset
,
19030 fixp
->fx_file
= fragp
->fr_file
;
19031 fixp
->fx_line
= fragp
->fr_line
;
19034 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19035 _("invalid unextended operand value"));
19038 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19039 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19041 gas_assert (mips16_opcode_length (insn
) == length
);
19042 write_compressed_insn (buf
, insn
, length
);
19043 fragp
->fr_fix
+= length
;
19048 relax_substateT subtype
= fragp
->fr_subtype
;
19049 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19050 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19054 first
= RELAX_FIRST (subtype
);
19055 second
= RELAX_SECOND (subtype
);
19056 fixp
= (fixS
*) fragp
->fr_opcode
;
19058 /* If the delay slot chosen does not match the size of the instruction,
19059 then emit a warning. */
19060 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19061 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19066 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19067 | RELAX_DELAY_SLOT_SIZE_FIRST
19068 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19069 msg
= macro_warning (s
);
19071 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19075 /* Possibly emit a warning if we've chosen the longer option. */
19076 if (use_second
== second_longer
)
19082 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19083 msg
= macro_warning (s
);
19085 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19089 /* Go through all the fixups for the first sequence. Disable them
19090 (by marking them as done) if we're going to use the second
19091 sequence instead. */
19093 && fixp
->fx_frag
== fragp
19094 && fixp
->fx_where
< fragp
->fr_fix
- second
)
19096 if (subtype
& RELAX_USE_SECOND
)
19098 fixp
= fixp
->fx_next
;
19101 /* Go through the fixups for the second sequence. Disable them if
19102 we're going to use the first sequence, otherwise adjust their
19103 addresses to account for the relaxation. */
19104 while (fixp
&& fixp
->fx_frag
== fragp
)
19106 if (subtype
& RELAX_USE_SECOND
)
19107 fixp
->fx_where
-= first
;
19110 fixp
= fixp
->fx_next
;
19113 /* Now modify the frag contents. */
19114 if (subtype
& RELAX_USE_SECOND
)
19118 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19119 memmove (start
, start
+ first
, second
);
19120 fragp
->fr_fix
-= first
;
19123 fragp
->fr_fix
-= second
;
19127 /* This function is called after the relocs have been generated.
19128 We've been storing mips16 text labels as odd. Here we convert them
19129 back to even for the convenience of the debugger. */
19132 mips_frob_file_after_relocs (void)
19135 unsigned int count
, i
;
19137 syms
= bfd_get_outsymbols (stdoutput
);
19138 count
= bfd_get_symcount (stdoutput
);
19139 for (i
= 0; i
< count
; i
++, syms
++)
19140 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19141 && ((*syms
)->value
& 1) != 0)
19143 (*syms
)->value
&= ~1;
19144 /* If the symbol has an odd size, it was probably computed
19145 incorrectly, so adjust that as well. */
19146 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19147 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19151 /* This function is called whenever a label is defined, including fake
19152 labels instantiated off the dot special symbol. It is used when
19153 handling branch delays; if a branch has a label, we assume we cannot
19154 move it. This also bumps the value of the symbol by 1 in compressed
19158 mips_record_label (symbolS
*sym
)
19160 segment_info_type
*si
= seg_info (now_seg
);
19161 struct insn_label_list
*l
;
19163 if (free_insn_labels
== NULL
)
19164 l
= XNEW (struct insn_label_list
);
19167 l
= free_insn_labels
;
19168 free_insn_labels
= l
->next
;
19172 l
->next
= si
->label_list
;
19173 si
->label_list
= l
;
19176 /* This function is called as tc_frob_label() whenever a label is defined
19177 and adds a DWARF-2 record we only want for true labels. */
19180 mips_define_label (symbolS
*sym
)
19182 mips_record_label (sym
);
19183 dwarf2_emit_label (sym
);
19186 /* This function is called by tc_new_dot_label whenever a new dot symbol
19190 mips_add_dot_label (symbolS
*sym
)
19192 mips_record_label (sym
);
19193 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19194 mips_compressed_mark_label (sym
);
19197 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19198 static unsigned int
19199 mips_convert_ase_flags (int ase
)
19201 unsigned int ext_ases
= 0;
19204 ext_ases
|= AFL_ASE_DSP
;
19205 if (ase
& ASE_DSPR2
)
19206 ext_ases
|= AFL_ASE_DSPR2
;
19207 if (ase
& ASE_DSPR3
)
19208 ext_ases
|= AFL_ASE_DSPR3
;
19210 ext_ases
|= AFL_ASE_EVA
;
19212 ext_ases
|= AFL_ASE_MCU
;
19213 if (ase
& ASE_MDMX
)
19214 ext_ases
|= AFL_ASE_MDMX
;
19215 if (ase
& ASE_MIPS3D
)
19216 ext_ases
|= AFL_ASE_MIPS3D
;
19218 ext_ases
|= AFL_ASE_MT
;
19219 if (ase
& ASE_SMARTMIPS
)
19220 ext_ases
|= AFL_ASE_SMARTMIPS
;
19221 if (ase
& ASE_VIRT
)
19222 ext_ases
|= AFL_ASE_VIRT
;
19224 ext_ases
|= AFL_ASE_MSA
;
19226 ext_ases
|= AFL_ASE_XPA
;
19227 if (ase
& ASE_MIPS16E2
)
19228 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19230 ext_ases
|= AFL_ASE_CRC
;
19231 if (ase
& ASE_GINV
)
19232 ext_ases
|= AFL_ASE_GINV
;
19233 if (ase
& ASE_LOONGSON_MMI
)
19234 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19235 if (ase
& ASE_LOONGSON_CAM
)
19236 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19237 if (ase
& ASE_LOONGSON_EXT
)
19238 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19239 if (ase
& ASE_LOONGSON_EXT2
)
19240 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19244 /* Some special processing for a MIPS ELF file. */
19247 mips_elf_final_processing (void)
19250 Elf_Internal_ABIFlags_v0 flags
;
19254 switch (file_mips_opts
.isa
)
19257 flags
.isa_level
= 1;
19260 flags
.isa_level
= 2;
19263 flags
.isa_level
= 3;
19266 flags
.isa_level
= 4;
19269 flags
.isa_level
= 5;
19272 flags
.isa_level
= 32;
19276 flags
.isa_level
= 32;
19280 flags
.isa_level
= 32;
19284 flags
.isa_level
= 32;
19288 flags
.isa_level
= 32;
19292 flags
.isa_level
= 64;
19296 flags
.isa_level
= 64;
19300 flags
.isa_level
= 64;
19304 flags
.isa_level
= 64;
19308 flags
.isa_level
= 64;
19313 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19314 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19315 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19316 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19318 flags
.cpr2_size
= AFL_REG_NONE
;
19319 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19320 Tag_GNU_MIPS_ABI_FP
);
19321 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19322 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19323 if (file_ase_mips16
)
19324 flags
.ases
|= AFL_ASE_MIPS16
;
19325 if (file_ase_micromips
)
19326 flags
.ases
|= AFL_ASE_MICROMIPS
;
19328 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19329 || file_mips_opts
.fp
== 64)
19330 && file_mips_opts
.oddspreg
)
19331 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19334 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19335 ((Elf_External_ABIFlags_v0
*)
19338 /* Write out the register information. */
19339 if (mips_abi
!= N64_ABI
)
19343 s
.ri_gprmask
= mips_gprmask
;
19344 s
.ri_cprmask
[0] = mips_cprmask
[0];
19345 s
.ri_cprmask
[1] = mips_cprmask
[1];
19346 s
.ri_cprmask
[2] = mips_cprmask
[2];
19347 s
.ri_cprmask
[3] = mips_cprmask
[3];
19348 /* The gp_value field is set by the MIPS ELF backend. */
19350 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19351 ((Elf32_External_RegInfo
*)
19352 mips_regmask_frag
));
19356 Elf64_Internal_RegInfo s
;
19358 s
.ri_gprmask
= mips_gprmask
;
19360 s
.ri_cprmask
[0] = mips_cprmask
[0];
19361 s
.ri_cprmask
[1] = mips_cprmask
[1];
19362 s
.ri_cprmask
[2] = mips_cprmask
[2];
19363 s
.ri_cprmask
[3] = mips_cprmask
[3];
19364 /* The gp_value field is set by the MIPS ELF backend. */
19366 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19367 ((Elf64_External_RegInfo
*)
19368 mips_regmask_frag
));
19371 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19372 sort of BFD interface for this. */
19373 if (mips_any_noreorder
)
19374 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19375 if (mips_pic
!= NO_PIC
)
19377 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19378 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19381 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19383 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19384 defined at present; this might need to change in future. */
19385 if (file_ase_mips16
)
19386 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19387 if (file_ase_micromips
)
19388 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19389 if (file_mips_opts
.ase
& ASE_MDMX
)
19390 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19392 /* Set the MIPS ELF ABI flags. */
19393 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19394 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19395 else if (mips_abi
== O64_ABI
)
19396 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19397 else if (mips_abi
== EABI_ABI
)
19399 if (file_mips_opts
.gp
== 64)
19400 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19402 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19405 /* Nothing to do for N32_ABI or N64_ABI. */
19407 if (mips_32bitmode
)
19408 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19410 if (mips_nan2008
== 1)
19411 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19413 /* 32 bit code with 64 bit FP registers. */
19414 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19415 Tag_GNU_MIPS_ABI_FP
);
19416 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19417 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19420 typedef struct proc
{
19422 symbolS
*func_end_sym
;
19423 unsigned long reg_mask
;
19424 unsigned long reg_offset
;
19425 unsigned long fpreg_mask
;
19426 unsigned long fpreg_offset
;
19427 unsigned long frame_offset
;
19428 unsigned long frame_reg
;
19429 unsigned long pc_reg
;
19432 static procS cur_proc
;
19433 static procS
*cur_proc_ptr
;
19434 static int numprocs
;
19436 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19437 as "2", and a normal nop as "0". */
19439 #define NOP_OPCODE_MIPS 0
19440 #define NOP_OPCODE_MIPS16 1
19441 #define NOP_OPCODE_MICROMIPS 2
19444 mips_nop_opcode (void)
19446 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19447 return NOP_OPCODE_MICROMIPS
;
19448 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19449 return NOP_OPCODE_MIPS16
;
19451 return NOP_OPCODE_MIPS
;
19454 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19455 32-bit microMIPS NOPs here (if applicable). */
19458 mips_handle_align (fragS
*fragp
)
19462 int bytes
, size
, excess
;
19465 if (fragp
->fr_type
!= rs_align_code
)
19468 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19470 switch (nop_opcode
)
19472 case NOP_OPCODE_MICROMIPS
:
19473 opcode
= micromips_nop32_insn
.insn_opcode
;
19476 case NOP_OPCODE_MIPS16
:
19477 opcode
= mips16_nop_insn
.insn_opcode
;
19480 case NOP_OPCODE_MIPS
:
19482 opcode
= nop_insn
.insn_opcode
;
19487 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19488 excess
= bytes
% size
;
19490 /* Handle the leading part if we're not inserting a whole number of
19491 instructions, and make it the end of the fixed part of the frag.
19492 Try to fit in a short microMIPS NOP if applicable and possible,
19493 and use zeroes otherwise. */
19494 gas_assert (excess
< 4);
19495 fragp
->fr_fix
+= excess
;
19500 /* Fall through. */
19502 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19504 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19508 /* Fall through. */
19511 /* Fall through. */
19516 md_number_to_chars (p
, opcode
, size
);
19517 fragp
->fr_var
= size
;
19526 if (*input_line_pointer
== '-')
19528 ++input_line_pointer
;
19531 if (!ISDIGIT (*input_line_pointer
))
19532 as_bad (_("expected simple number"));
19533 if (input_line_pointer
[0] == '0')
19535 if (input_line_pointer
[1] == 'x')
19537 input_line_pointer
+= 2;
19538 while (ISXDIGIT (*input_line_pointer
))
19541 val
|= hex_value (*input_line_pointer
++);
19543 return negative
? -val
: val
;
19547 ++input_line_pointer
;
19548 while (ISDIGIT (*input_line_pointer
))
19551 val
|= *input_line_pointer
++ - '0';
19553 return negative
? -val
: val
;
19556 if (!ISDIGIT (*input_line_pointer
))
19558 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19559 *input_line_pointer
, *input_line_pointer
);
19560 as_warn (_("invalid number"));
19563 while (ISDIGIT (*input_line_pointer
))
19566 val
+= *input_line_pointer
++ - '0';
19568 return negative
? -val
: val
;
19571 /* The .file directive; just like the usual .file directive, but there
19572 is an initial number which is the ECOFF file index. In the non-ECOFF
19573 case .file implies DWARF-2. */
19576 s_mips_file (int x ATTRIBUTE_UNUSED
)
19578 static int first_file_directive
= 0;
19580 if (ECOFF_DEBUGGING
)
19589 filename
= dwarf2_directive_filename ();
19591 /* Versions of GCC up to 3.1 start files with a ".file"
19592 directive even for stabs output. Make sure that this
19593 ".file" is handled. Note that you need a version of GCC
19594 after 3.1 in order to support DWARF-2 on MIPS. */
19595 if (filename
!= NULL
&& ! first_file_directive
)
19597 (void) new_logical_line (filename
, -1);
19598 s_app_file_string (filename
, 0);
19600 first_file_directive
= 1;
19604 /* The .loc directive, implying DWARF-2. */
19607 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19609 if (!ECOFF_DEBUGGING
)
19610 dwarf2_directive_loc (0);
19613 /* The .end directive. */
19616 s_mips_end (int x ATTRIBUTE_UNUSED
)
19620 /* Following functions need their own .frame and .cprestore directives. */
19621 mips_frame_reg_valid
= 0;
19622 mips_cprestore_valid
= 0;
19624 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19627 demand_empty_rest_of_line ();
19632 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19633 as_warn (_(".end not in text section"));
19637 as_warn (_(".end directive without a preceding .ent directive"));
19638 demand_empty_rest_of_line ();
19644 gas_assert (S_GET_NAME (p
));
19645 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19646 as_warn (_(".end symbol does not match .ent symbol"));
19648 if (debug_type
== DEBUG_STABS
)
19649 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19653 as_warn (_(".end directive missing or unknown symbol"));
19655 /* Create an expression to calculate the size of the function. */
19656 if (p
&& cur_proc_ptr
)
19658 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19659 expressionS
*exp
= XNEW (expressionS
);
19662 exp
->X_op
= O_subtract
;
19663 exp
->X_add_symbol
= symbol_temp_new_now ();
19664 exp
->X_op_symbol
= p
;
19665 exp
->X_add_number
= 0;
19667 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19670 #ifdef md_flush_pending_output
19671 md_flush_pending_output ();
19674 /* Generate a .pdr section. */
19675 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19677 segT saved_seg
= now_seg
;
19678 subsegT saved_subseg
= now_subseg
;
19682 gas_assert (pdr_seg
);
19683 subseg_set (pdr_seg
, 0);
19685 /* Write the symbol. */
19686 exp
.X_op
= O_symbol
;
19687 exp
.X_add_symbol
= p
;
19688 exp
.X_add_number
= 0;
19689 emit_expr (&exp
, 4);
19691 fragp
= frag_more (7 * 4);
19693 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19694 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19695 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19696 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19697 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19698 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19699 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19701 subseg_set (saved_seg
, saved_subseg
);
19704 cur_proc_ptr
= NULL
;
19707 /* The .aent and .ent directives. */
19710 s_mips_ent (int aent
)
19714 symbolP
= get_symbol ();
19715 if (*input_line_pointer
== ',')
19716 ++input_line_pointer
;
19717 SKIP_WHITESPACE ();
19718 if (ISDIGIT (*input_line_pointer
)
19719 || *input_line_pointer
== '-')
19722 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19723 as_warn (_(".ent or .aent not in text section"));
19725 if (!aent
&& cur_proc_ptr
)
19726 as_warn (_("missing .end"));
19730 /* This function needs its own .frame and .cprestore directives. */
19731 mips_frame_reg_valid
= 0;
19732 mips_cprestore_valid
= 0;
19734 cur_proc_ptr
= &cur_proc
;
19735 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19737 cur_proc_ptr
->func_sym
= symbolP
;
19741 if (debug_type
== DEBUG_STABS
)
19742 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19743 S_GET_NAME (symbolP
));
19746 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19748 demand_empty_rest_of_line ();
19751 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19752 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19753 s_mips_frame is used so that we can set the PDR information correctly.
19754 We can't use the ecoff routines because they make reference to the ecoff
19755 symbol table (in the mdebug section). */
19758 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19760 if (ECOFF_DEBUGGING
)
19766 if (cur_proc_ptr
== (procS
*) NULL
)
19768 as_warn (_(".frame outside of .ent"));
19769 demand_empty_rest_of_line ();
19773 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19775 SKIP_WHITESPACE ();
19776 if (*input_line_pointer
++ != ','
19777 || get_absolute_expression_and_terminator (&val
) != ',')
19779 as_warn (_("bad .frame directive"));
19780 --input_line_pointer
;
19781 demand_empty_rest_of_line ();
19785 cur_proc_ptr
->frame_offset
= val
;
19786 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19788 demand_empty_rest_of_line ();
19792 /* The .fmask and .mask directives. If the mdebug section is present
19793 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19794 embedded targets, s_mips_mask is used so that we can set the PDR
19795 information correctly. We can't use the ecoff routines because they
19796 make reference to the ecoff symbol table (in the mdebug section). */
19799 s_mips_mask (int reg_type
)
19801 if (ECOFF_DEBUGGING
)
19802 s_ignore (reg_type
);
19807 if (cur_proc_ptr
== (procS
*) NULL
)
19809 as_warn (_(".mask/.fmask outside of .ent"));
19810 demand_empty_rest_of_line ();
19814 if (get_absolute_expression_and_terminator (&mask
) != ',')
19816 as_warn (_("bad .mask/.fmask directive"));
19817 --input_line_pointer
;
19818 demand_empty_rest_of_line ();
19822 off
= get_absolute_expression ();
19824 if (reg_type
== 'F')
19826 cur_proc_ptr
->fpreg_mask
= mask
;
19827 cur_proc_ptr
->fpreg_offset
= off
;
19831 cur_proc_ptr
->reg_mask
= mask
;
19832 cur_proc_ptr
->reg_offset
= off
;
19835 demand_empty_rest_of_line ();
19839 /* A table describing all the processors gas knows about. Names are
19840 matched in the order listed.
19842 To ease comparison, please keep this table in the same order as
19843 gcc's mips_cpu_info_table[]. */
19844 static const struct mips_cpu_info mips_cpu_info_table
[] =
19846 /* Entries for generic ISAs. */
19847 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19848 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19849 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19850 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19851 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19852 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19853 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19854 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19855 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19856 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19857 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19858 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19859 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19860 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19861 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19864 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19865 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19866 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19869 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19872 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19873 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19874 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19875 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19876 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19877 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19878 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19879 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19880 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19881 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19882 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19883 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19884 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19885 /* ST Microelectronics Loongson 2E and 2F cores. */
19886 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19887 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19890 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19891 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19892 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19893 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19894 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19895 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19896 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19897 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19898 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19899 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19900 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19901 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19902 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19903 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19904 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19907 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19908 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19909 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19910 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19912 /* MIPS 32 Release 2 */
19913 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19914 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19915 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19916 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19917 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19918 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19919 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19920 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19921 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19922 ISA_MIPS32R2
, CPU_MIPS32R2
},
19923 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19924 ISA_MIPS32R2
, CPU_MIPS32R2
},
19925 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19926 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19927 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19928 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19929 /* Deprecated forms of the above. */
19930 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19931 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19932 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19933 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19934 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19935 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19936 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19937 /* Deprecated forms of the above. */
19938 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19939 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19940 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19941 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19942 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19943 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19944 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19945 /* Deprecated forms of the above. */
19946 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19947 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19948 /* 34Kn is a 34kc without DSP. */
19949 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19950 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19951 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19952 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19953 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19954 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19955 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19956 /* Deprecated forms of the above. */
19957 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19958 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19959 /* 1004K cores are multiprocessor versions of the 34K. */
19960 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19961 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19962 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19963 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19964 /* interaptiv is the new name for 1004kf. */
19965 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19966 { "interaptiv-mr2", 0,
19967 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19968 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19969 /* M5100 family. */
19970 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19971 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19972 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19973 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19976 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19977 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19978 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19979 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19981 /* Broadcom SB-1 CPU core. */
19982 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19983 /* Broadcom SB-1A CPU core. */
19984 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19986 /* MIPS 64 Release 2. */
19987 /* Loongson CPU core. */
19988 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
19989 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19990 ISA_MIPS64R2
, CPU_GS464
},
19991 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19992 ISA_MIPS64R2
, CPU_GS464
},
19993 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
19994 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
19995 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
19996 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
19998 /* Cavium Networks Octeon CPU core. */
19999 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20000 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20001 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20002 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20005 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20008 XLP is mostly like XLR, with the prominent exception that it is
20009 MIPS64R2 rather than MIPS64. */
20010 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20012 /* MIPS 64 Release 6. */
20013 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20014 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20017 { NULL
, 0, 0, 0, 0 }
20021 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20022 with a final "000" replaced by "k". Ignore case.
20024 Note: this function is shared between GCC and GAS. */
20027 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20029 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20030 given
++, canonical
++;
20032 return ((*given
== 0 && *canonical
== 0)
20033 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20037 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20038 CPU name. We've traditionally allowed a lot of variation here.
20040 Note: this function is shared between GCC and GAS. */
20043 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20045 /* First see if the name matches exactly, or with a final "000"
20046 turned into "k". */
20047 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20050 /* If not, try comparing based on numerical designation alone.
20051 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20052 if (TOLOWER (*given
) == 'r')
20054 if (!ISDIGIT (*given
))
20057 /* Skip over some well-known prefixes in the canonical name,
20058 hoping to find a number there too. */
20059 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20061 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20063 else if (TOLOWER (canonical
[0]) == 'r')
20066 return mips_strict_matching_cpu_name_p (canonical
, given
);
20070 /* Parse an option that takes the name of a processor as its argument.
20071 OPTION is the name of the option and CPU_STRING is the argument.
20072 Return the corresponding processor enumeration if the CPU_STRING is
20073 recognized, otherwise report an error and return null.
20075 A similar function exists in GCC. */
20077 static const struct mips_cpu_info
*
20078 mips_parse_cpu (const char *option
, const char *cpu_string
)
20080 const struct mips_cpu_info
*p
;
20082 /* 'from-abi' selects the most compatible architecture for the given
20083 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20084 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20085 version. Look first at the -mgp options, if given, otherwise base
20086 the choice on MIPS_DEFAULT_64BIT.
20088 Treat NO_ABI like the EABIs. One reason to do this is that the
20089 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20090 architecture. This code picks MIPS I for 'mips' and MIPS III for
20091 'mips64', just as we did in the days before 'from-abi'. */
20092 if (strcasecmp (cpu_string
, "from-abi") == 0)
20094 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20095 return mips_cpu_info_from_isa (ISA_MIPS1
);
20097 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20098 return mips_cpu_info_from_isa (ISA_MIPS3
);
20100 if (file_mips_opts
.gp
>= 0)
20101 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20102 ? ISA_MIPS1
: ISA_MIPS3
);
20104 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20109 /* 'default' has traditionally been a no-op. Probably not very useful. */
20110 if (strcasecmp (cpu_string
, "default") == 0)
20113 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20114 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20117 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20121 /* Return the canonical processor information for ISA (a member of the
20122 ISA_MIPS* enumeration). */
20124 static const struct mips_cpu_info
*
20125 mips_cpu_info_from_isa (int isa
)
20129 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20130 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20131 && isa
== mips_cpu_info_table
[i
].isa
)
20132 return (&mips_cpu_info_table
[i
]);
20137 static const struct mips_cpu_info
*
20138 mips_cpu_info_from_arch (int arch
)
20142 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20143 if (arch
== mips_cpu_info_table
[i
].cpu
)
20144 return (&mips_cpu_info_table
[i
]);
20150 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20154 fprintf (stream
, "%24s", "");
20159 fprintf (stream
, ", ");
20163 if (*col_p
+ strlen (string
) > 72)
20165 fprintf (stream
, "\n%24s", "");
20169 fprintf (stream
, "%s", string
);
20170 *col_p
+= strlen (string
);
20176 md_show_usage (FILE *stream
)
20181 fprintf (stream
, _("\
20183 -EB generate big endian output\n\
20184 -EL generate little endian output\n\
20185 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20186 -G NUM allow referencing objects up to NUM bytes\n\
20187 implicitly with the gp register [default 8]\n"));
20188 fprintf (stream
, _("\
20189 -mips1 generate MIPS ISA I instructions\n\
20190 -mips2 generate MIPS ISA II instructions\n\
20191 -mips3 generate MIPS ISA III instructions\n\
20192 -mips4 generate MIPS ISA IV instructions\n\
20193 -mips5 generate MIPS ISA V instructions\n\
20194 -mips32 generate MIPS32 ISA instructions\n\
20195 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20196 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20197 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20198 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20199 -mips64 generate MIPS64 ISA instructions\n\
20200 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20201 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20202 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20203 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20204 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20208 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20209 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20210 show (stream
, "from-abi", &column
, &first
);
20211 fputc ('\n', stream
);
20213 fprintf (stream
, _("\
20214 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20215 -no-mCPU don't generate code specific to CPU.\n\
20216 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20220 show (stream
, "3900", &column
, &first
);
20221 show (stream
, "4010", &column
, &first
);
20222 show (stream
, "4100", &column
, &first
);
20223 show (stream
, "4650", &column
, &first
);
20224 fputc ('\n', stream
);
20226 fprintf (stream
, _("\
20227 -mips16 generate mips16 instructions\n\
20228 -no-mips16 do not generate mips16 instructions\n"));
20229 fprintf (stream
, _("\
20230 -mmips16e2 generate MIPS16e2 instructions\n\
20231 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20232 fprintf (stream
, _("\
20233 -mmicromips generate microMIPS instructions\n\
20234 -mno-micromips do not generate microMIPS instructions\n"));
20235 fprintf (stream
, _("\
20236 -msmartmips generate smartmips instructions\n\
20237 -mno-smartmips do not generate smartmips instructions\n"));
20238 fprintf (stream
, _("\
20239 -mdsp generate DSP instructions\n\
20240 -mno-dsp do not generate DSP instructions\n"));
20241 fprintf (stream
, _("\
20242 -mdspr2 generate DSP R2 instructions\n\
20243 -mno-dspr2 do not generate DSP R2 instructions\n"));
20244 fprintf (stream
, _("\
20245 -mdspr3 generate DSP R3 instructions\n\
20246 -mno-dspr3 do not generate DSP R3 instructions\n"));
20247 fprintf (stream
, _("\
20248 -mmt generate MT instructions\n\
20249 -mno-mt do not generate MT instructions\n"));
20250 fprintf (stream
, _("\
20251 -mmcu generate MCU instructions\n\
20252 -mno-mcu do not generate MCU instructions\n"));
20253 fprintf (stream
, _("\
20254 -mmsa generate MSA instructions\n\
20255 -mno-msa do not generate MSA instructions\n"));
20256 fprintf (stream
, _("\
20257 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20258 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20259 fprintf (stream
, _("\
20260 -mvirt generate Virtualization instructions\n\
20261 -mno-virt do not generate Virtualization instructions\n"));
20262 fprintf (stream
, _("\
20263 -mcrc generate CRC instructions\n\
20264 -mno-crc do not generate CRC instructions\n"));
20265 fprintf (stream
, _("\
20266 -mginv generate Global INValidate (GINV) instructions\n\
20267 -mno-ginv do not generate Global INValidate instructions\n"));
20268 fprintf (stream
, _("\
20269 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20270 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20271 fprintf (stream
, _("\
20272 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20273 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20274 fprintf (stream
, _("\
20275 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20276 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20277 fprintf (stream
, _("\
20278 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20279 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20280 fprintf (stream
, _("\
20281 -minsn32 only generate 32-bit microMIPS instructions\n\
20282 -mno-insn32 generate all microMIPS instructions\n"));
20283 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20284 fprintf (stream
, _("\
20285 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20286 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20288 fprintf (stream
, _("\
20289 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20290 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20292 fprintf (stream
, _("\
20293 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20294 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20295 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20296 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20297 -mfix-vr4120 work around certain VR4120 errata\n\
20298 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20299 -mfix-24k insert a nop after ERET and DERET instructions\n\
20300 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20301 -mfix-r5900 work around R5900 short loop errata\n\
20302 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20303 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20304 -msym32 assume all symbols have 32-bit values\n\
20305 -O0 do not remove unneeded NOPs, do not swap branches\n\
20306 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20307 -O2 remove unneeded NOPs and swap branches\n\
20308 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20309 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20310 fprintf (stream
, _("\
20311 -mhard-float allow floating-point instructions\n\
20312 -msoft-float do not allow floating-point instructions\n\
20313 -msingle-float only allow 32-bit floating-point operations\n\
20314 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20315 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20316 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20317 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20318 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20319 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20323 show (stream
, "legacy", &column
, &first
);
20324 show (stream
, "2008", &column
, &first
);
20326 fputc ('\n', stream
);
20328 fprintf (stream
, _("\
20329 -KPIC, -call_shared generate SVR4 position independent code\n\
20330 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20331 -mvxworks-pic generate VxWorks position independent code\n\
20332 -non_shared do not generate code that can operate with DSOs\n\
20333 -xgot assume a 32 bit GOT\n\
20334 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20335 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20336 position dependent (non shared) code\n\
20337 -mabi=ABI create ABI conformant object file for:\n"));
20341 show (stream
, "32", &column
, &first
);
20342 show (stream
, "o64", &column
, &first
);
20343 show (stream
, "n32", &column
, &first
);
20344 show (stream
, "64", &column
, &first
);
20345 show (stream
, "eabi", &column
, &first
);
20347 fputc ('\n', stream
);
20349 fprintf (stream
, _("\
20350 -32 create o32 ABI object file%s\n"),
20351 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20352 fprintf (stream
, _("\
20353 -n32 create n32 ABI object file%s\n"),
20354 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20355 fprintf (stream
, _("\
20356 -64 create 64 ABI object file%s\n"),
20357 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20362 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20364 if (HAVE_64BIT_SYMBOLS
)
20365 return dwarf2_format_64bit_irix
;
20367 return dwarf2_format_32bit
;
20372 mips_dwarf2_addr_size (void)
20374 if (HAVE_64BIT_OBJECTS
)
20380 /* Standard calling conventions leave the CFA at SP on entry. */
20382 mips_cfi_frame_initial_instructions (void)
20384 cfi_add_CFA_def_cfa_register (SP
);
20388 tc_mips_regname_to_dw2regnum (char *regname
)
20390 unsigned int regnum
= -1;
20393 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20399 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20400 Given a symbolic attribute NAME, return the proper integer value.
20401 Returns -1 if the attribute is not known. */
20404 mips_convert_symbolic_attribute (const char *name
)
20406 static const struct
20411 attribute_table
[] =
20413 #define T(tag) {#tag, tag}
20414 T (Tag_GNU_MIPS_ABI_FP
),
20415 T (Tag_GNU_MIPS_ABI_MSA
),
20423 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20424 if (streq (name
, attribute_table
[i
].name
))
20425 return attribute_table
[i
].tag
;
20433 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20435 mips_emit_delays ();
20437 as_warn (_("missing .end at end of assembly"));
20439 /* Just in case no code was emitted, do the consistency check. */
20440 file_mips_check_options ();
20442 /* Set a floating-point ABI if the user did not. */
20443 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20445 /* Perform consistency checks on the floating-point ABI. */
20446 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20447 Tag_GNU_MIPS_ABI_FP
);
20448 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20449 check_fpabi (fpabi
);
20453 /* Soft-float gets precedence over single-float, the two options should
20454 not be used together so this should not matter. */
20455 if (file_mips_opts
.soft_float
== 1)
20456 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20457 /* Single-float gets precedence over all double_float cases. */
20458 else if (file_mips_opts
.single_float
== 1)
20459 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20462 switch (file_mips_opts
.fp
)
20465 if (file_mips_opts
.gp
== 32)
20466 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20469 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20472 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20473 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20474 else if (file_mips_opts
.gp
== 32)
20475 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20477 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20482 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20483 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20487 /* Returns the relocation type required for a particular CFI encoding. */
20489 bfd_reloc_code_real_type
20490 mips_cfi_reloc_for_encoding (int encoding
)
20492 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20493 return BFD_RELOC_32_PCREL
;
20494 else return BFD_RELOC_NONE
;